From f579666f6bb75fe9cabb1765462e2a41d3393bfb Mon Sep 17 00:00:00 2001 From: CYFS <2805686936@qq.com> Date: Tue, 14 Jul 2026 14:53:50 +0800 Subject: [PATCH 1/2] bsp: fix RA8P1 Titan Keil startup --- .../ra8p1-titan-board/board/bsp_linker_info.h | 76 +++++++++++++++++++ bsp/renesas/ra8p1-titan-board/project.uvprojx | 2 +- bsp/renesas/ra8p1-titan-board/ra/SConscript | 6 +- bsp/renesas/ra8p1-titan-board/rtconfig.py | 4 +- .../ra8p1-titan-board/template.uvprojx | 2 +- 5 files changed, 85 insertions(+), 5 deletions(-) diff --git a/bsp/renesas/ra8p1-titan-board/board/bsp_linker_info.h b/bsp/renesas/ra8p1-titan-board/board/bsp_linker_info.h index e49a74df0b2..356e4ba4572 100644 --- a/bsp/renesas/ra8p1-titan-board/board/bsp_linker_info.h +++ b/bsp/renesas/ra8p1-titan-board/board/bsp_linker_info.h @@ -136,6 +136,82 @@ extern bsp_init_info_t const g_init_info; **********************************************************************************************************************/ /* DDSC symbol definitions */ #if defined(__ARMCC_VERSION) +#define __sdram_zero_nocache$$Base Image$$__sdram_zero_nocache$$ZI$$Base +#define __sdram_zero_nocache$$Limit Image$$__sdram_zero_nocache$$ZI$$Limit +#define __sdram_zero$$Base Image$$__sdram_zero$$ZI$$Base +#define __sdram_zero$$Limit Image$$__sdram_zero$$ZI$$Limit +#define __ospi0_cs0_zero_nocache$$Base Image$$__ospi0_cs0_zero_nocache$$ZI$$Base +#define __ospi0_cs0_zero_nocache$$Limit Image$$__ospi0_cs0_zero_nocache$$ZI$$Limit +#define __ospi0_cs0_zero$$Base Image$$__ospi0_cs0_zero$$ZI$$Base +#define __ospi0_cs0_zero$$Limit Image$$__ospi0_cs0_zero$$ZI$$Limit +#define __ospi1_cs0_zero_nocache$$Base Image$$__ospi1_cs0_zero_nocache$$ZI$$Base +#define __ospi1_cs0_zero_nocache$$Limit Image$$__ospi1_cs0_zero_nocache$$ZI$$Limit +#define __ospi1_cs0_zero$$Base Image$$__ospi1_cs0_zero$$ZI$$Base +#define __ospi1_cs0_zero$$Limit Image$$__ospi1_cs0_zero$$ZI$$Limit +#define __itcm_zero$$Base Image$$__itcm_zero$$ZI$$Base +#define __itcm_zero$$Limit Image$$__itcm_zero$$ZI$$Limit +#define __dtcm_zero$$Base Image$$__dtcm_zero$$ZI$$Base +#define __dtcm_zero$$Limit Image$$__dtcm_zero$$ZI$$Limit +#define __ram_zero_nocache$$Base Image$$__ram_zero_nocache$$ZI$$Base +#define __ram_zero_nocache$$Limit Image$$__ram_zero_nocache$$ZI$$Limit +#define __ram_zero$$Base Image$$__ram_zero$$ZI$$Base +#define __ram_zero$$Limit Image$$__ram_zero$$ZI$$Limit +#define __sdram_from_ospi0_cs1$$Base Image$$__sdram_from_ospi0_cs1$$Base +#define __sdram_from_ospi0_cs1$$Limit Image$$__sdram_from_ospi0_cs1$$Limit +#define __sdram_from_ospi1_cs1$$Base Image$$__sdram_from_ospi1_cs1$$Base +#define __sdram_from_ospi1_cs1$$Limit Image$$__sdram_from_ospi1_cs1$$Limit +#define __sdram_from_data_flash$$Base Image$$__sdram_from_data_flash$$Base +#define __sdram_from_data_flash$$Limit Image$$__sdram_from_data_flash$$Limit +#define __sdram_from_flash$$Base Image$$__sdram_from_flash$$Base +#define __sdram_from_flash$$Limit Image$$__sdram_from_flash$$Limit +#define __ospi0_cs0_from_ospi0_cs1$$Base Image$$__ospi0_cs0_from_ospi0_cs1$$Base +#define __ospi0_cs0_from_ospi0_cs1$$Limit Image$$__ospi0_cs0_from_ospi0_cs1$$Limit +#define __ospi0_cs0_from_ospi1_cs1$$Base Image$$__ospi0_cs0_from_ospi1_cs1$$Base +#define __ospi0_cs0_from_ospi1_cs1$$Limit Image$$__ospi0_cs0_from_ospi1_cs1$$Limit +#define __ospi0_cs0_from_data_flash$$Base Image$$__ospi0_cs0_from_data_flash$$Base +#define __ospi0_cs0_from_data_flash$$Limit Image$$__ospi0_cs0_from_data_flash$$Limit +#define __ospi0_cs0_from_flash$$Base Image$$__ospi0_cs0_from_flash$$Base +#define __ospi0_cs0_from_flash$$Limit Image$$__ospi0_cs0_from_flash$$Limit +#define __ospi1_cs0_from_ospi0_cs1$$Base Image$$__ospi1_cs0_from_ospi0_cs1$$Base +#define __ospi1_cs0_from_ospi0_cs1$$Limit Image$$__ospi1_cs0_from_ospi0_cs1$$Limit +#define __ospi1_cs0_from_ospi1_cs1$$Base Image$$__ospi1_cs0_from_ospi1_cs1$$Base +#define __ospi1_cs0_from_ospi1_cs1$$Limit Image$$__ospi1_cs0_from_ospi1_cs1$$Limit +#define __ospi1_cs0_from_data_flash$$Base Image$$__ospi1_cs0_from_data_flash$$Base +#define __ospi1_cs0_from_data_flash$$Limit Image$$__ospi1_cs0_from_data_flash$$Limit +#define __ospi1_cs0_from_flash$$Base Image$$__ospi1_cs0_from_flash$$Base +#define __ospi1_cs0_from_flash$$Limit Image$$__ospi1_cs0_from_flash$$Limit +#define __itcm_from_ospi0_cs1$$Base Image$$__itcm_from_ospi0_cs1$$Base +#define __itcm_from_ospi0_cs1$$Limit Image$$__itcm_from_ospi0_cs1$$Limit +#define __itcm_from_ospi1_cs1$$Base Image$$__itcm_from_ospi1_cs1$$Base +#define __itcm_from_ospi1_cs1$$Limit Image$$__itcm_from_ospi1_cs1$$Limit +#define __itcm_from_data_flash$$Base Image$$__itcm_from_data_flash$$Base +#define __itcm_from_data_flash$$Limit Image$$__itcm_from_data_flash$$Limit +#define __itcm_from_flash$$Base Image$$__itcm_from_flash$$Base +#define __itcm_from_flash$$Limit Image$$__itcm_from_flash$$Limit +#define __dtcm_from_ospi0_cs1$$Base Image$$__dtcm_from_ospi0_cs1$$Base +#define __dtcm_from_ospi0_cs1$$Limit Image$$__dtcm_from_ospi0_cs1$$Limit +#define __dtcm_from_ospi1_cs1$$Base Image$$__dtcm_from_ospi1_cs1$$Base +#define __dtcm_from_ospi1_cs1$$Limit Image$$__dtcm_from_ospi1_cs1$$Limit +#define __dtcm_from_data_flash$$Base Image$$__dtcm_from_data_flash$$Base +#define __dtcm_from_data_flash$$Limit Image$$__dtcm_from_data_flash$$Limit +#define __dtcm_from_flash$$Base Image$$__dtcm_from_flash$$Base +#define __dtcm_from_flash$$Limit Image$$__dtcm_from_flash$$Limit +#define __ram_from_ospi0_cs1$$Base Image$$__ram_from_ospi0_cs1$$Base +#define __ram_from_ospi0_cs1$$Limit Image$$__ram_from_ospi0_cs1$$Limit +#define __ram_from_ospi1_cs1$$Base Image$$__ram_from_ospi1_cs1$$Base +#define __ram_from_ospi1_cs1$$Limit Image$$__ram_from_ospi1_cs1$$Limit +#define __ram_from_data_flash$$Base Image$$__ram_from_data_flash$$Base +#define __ram_from_data_flash$$Limit Image$$__ram_from_data_flash$$Limit +#define __ram_from_flash$$Base Image$$__ram_from_flash$$Base +#define __ram_from_flash$$Limit Image$$__ram_from_flash$$Limit +#define __sdram_noinit_nocache$$Base Image$$__sdram_noinit_nocache$$ZI$$Base +#define __sdram_noinit_nocache$$Limit Image$$__sdram_noinit_nocache$$ZI$$Limit +#define __ospi0_cs0_noinit_nocache$$Base Image$$__ospi0_cs0_noinit_nocache$$ZI$$Base +#define __ospi0_cs0_noinit_nocache$$Limit Image$$__ospi0_cs0_noinit_nocache$$ZI$$Limit +#define __ospi1_cs0_noinit_nocache$$Base Image$$__ospi1_cs0_noinit_nocache$$ZI$$Base +#define __ospi1_cs0_noinit_nocache$$Limit Image$$__ospi1_cs0_noinit_nocache$$ZI$$Limit +#define __ram_noinit_nocache$$Base Image$$__ram_noinit_nocache$$ZI$$Base +#define __ram_noinit_nocache$$Limit Image$$__ram_noinit_nocache$$ZI$$Limit #define __sdram_from_ospi0_cs1$$Load Load$$__sdram_from_ospi0_cs1$$Base #define __sdram_from_ospi1_cs1$$Load Load$$__sdram_from_ospi1_cs1$$Base #define __sdram_from_data_flash$$Load Load$$__sdram_from_data_flash$$Base diff --git a/bsp/renesas/ra8p1-titan-board/project.uvprojx b/bsp/renesas/ra8p1-titan-board/project.uvprojx index cdd2eca8b8c..dcf071cfdaf 100644 --- a/bsp/renesas/ra8p1-titan-board/project.uvprojx +++ b/bsp/renesas/ra8p1-titan-board/project.uvprojx @@ -374,7 +374,7 @@ .\script\fsp.scat - + --entry=Reset_Handler --no_startup 6319,6314 diff --git a/bsp/renesas/ra8p1-titan-board/ra/SConscript b/bsp/renesas/ra8p1-titan-board/ra/SConscript index fcb234ff98d..d0f1ad38298 100644 --- a/bsp/renesas/ra8p1-titan-board/ra/SConscript +++ b/bsp/renesas/ra8p1-titan-board/ra/SConscript @@ -7,6 +7,10 @@ cwd = GetCurrentDir() src = [] group = [] CPPPATH = [] +LINKFLAGS = '' + +if rtconfig.PLATFORM == 'armclang': + LINKFLAGS = ' --entry=Reset_Handler --no_startup' if rtconfig.PLATFORM in ['iccarm'] + GetGCCLikePLATFORM(): src += Glob('./fsp/src/bsp/mcu/all/*.c') @@ -54,5 +58,5 @@ if rtconfig.PLATFORM in ['iccarm'] + GetGCCLikePLATFORM(): cwd + '/fsp/src/r_vin' ] -group = DefineGroup('RA', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('RA', src, depend = [''], CPPPATH = CPPPATH, LINKFLAGS = LINKFLAGS) Return('group') diff --git a/bsp/renesas/ra8p1-titan-board/rtconfig.py b/bsp/renesas/ra8p1-titan-board/rtconfig.py index 8861aa879e8..00c18ed879f 100644 --- a/bsp/renesas/ra8p1-titan-board/rtconfig.py +++ b/bsp/renesas/ra8p1-titan-board/rtconfig.py @@ -76,9 +76,9 @@ CFLAGS += ' -fno-rtti -funsigned-char -ffunction-sections' CFLAGS += ' -Wno-license-management -Wuninitialized -Wall -Wmissing-declarations -Wpointer-arith -Waggregate-return -Wfloat-equal' - AFLAGS = DEVICE + ' --fpu=FPv5_D16 --apcs=interwork ' + AFLAGS = ' -mcpu=Cortex-M85 --target=arm-arm-none-eabi -mfpu=fpv5-d16 -mfloat-abi=hard -c -x assembler-with-cpp' - LFLAGS = DEVICE + ' --scatter ' + 'script/fsp.scat' + LFLAGS = DEVICE + ' --scatter script/fsp.scat' LFLAGS +=' --info sizes --info totals --info unused --info veneers ' LFLAGS += ' --list rt-thread.map --strict' LFLAGS += ' --diag_suppress 6319,6314 --summary_stderr --info summarysizes' diff --git a/bsp/renesas/ra8p1-titan-board/template.uvprojx b/bsp/renesas/ra8p1-titan-board/template.uvprojx index 84bb782d048..199ed07a779 100644 --- a/bsp/renesas/ra8p1-titan-board/template.uvprojx +++ b/bsp/renesas/ra8p1-titan-board/template.uvprojx @@ -374,7 +374,7 @@ .\script\fsp.scat - + --entry=Reset_Handler --no_startup 6319,6314 From c857c14373f8be3bc2e5928a43cee980a3053a40 Mon Sep 17 00:00:00 2001 From: CYFS <2805686936@qq.com> Date: Wed, 15 Jul 2026 15:07:14 +0800 Subject: [PATCH 2/2] bsp: support RA8P1 Titan dual-core projects --- bsp/renesas/libraries/Kconfig | 14 +- bsp/renesas/ra8p1-titan-board/.gitignore | 26 +- bsp/renesas/ra8p1-titan-board/README.md | 61 +- bsp/renesas/ra8p1-titan-board/README_zh.md | 59 +- .../ra8p1-titan-board/build_solution_sbd.bat | 37 + .../ra8p1-titan-board/build_solution_sbd.ps1 | 174 + bsp/renesas/ra8p1-titan-board/m33/.config | 399 + bsp/renesas/ra8p1-titan-board/m33/.gitignore | 32 + bsp/renesas/ra8p1-titan-board/m33/Kconfig | 20 + bsp/renesas/ra8p1-titan-board/m33/SConscript | 28 + bsp/renesas/ra8p1-titan-board/m33/SConstruct | 51 + .../ra8p1-titan-board/m33/board/Kconfig | 31 + .../{ => m33}/board/SConscript | 2 +- .../ra8p1-titan-board/m33/board/board.h | 40 + .../m33/board/bsp_linker_info.h | 412 + .../ra8p1-titan-board/m33/board/ra8_it.c | 3 + .../ra8p1-titan-board/m33/buildinfo.json | 33 + .../ra8p1-titan-board/m33/configuration.xml | 801 + .../ra8p1-titan-board/m33/project.uvoptx | 366 + .../ra8p1-titan-board/m33/project.uvprojx | 1683 + .../ra8p1-titan-board/m33/ra/SConscript | 29 + .../Core/Include/a-profile/cmsis_armclang_a.h | 0 .../Core/Include/a-profile/cmsis_clang_a.h | 0 .../CMSIS/Core/Include/a-profile/cmsis_cp15.h | 0 .../Core/Include/a-profile/cmsis_gcc_a.h | 0 .../Core/Include/a-profile/cmsis_iccarm_a.h | 0 .../CMSIS/Core/Include/a-profile/irq_ctrl.h | 0 .../CMSIS/Core/Include/cmsis_armclang.h | 0 .../CMSIS_6/CMSIS/Core/Include/cmsis_clang.h | 0 .../CMSIS/Core/Include/cmsis_compiler.h | 0 .../CMSIS_6/CMSIS/Core/Include/cmsis_gcc.h | 0 .../CMSIS/Core/Include/cmsis_version.h | 0 .../arm/CMSIS_6/CMSIS/Core/Include/core_ca.h | 0 .../arm/CMSIS_6/CMSIS/Core/Include/core_cm0.h | 0 .../CMSIS_6/CMSIS/Core/Include/core_cm0plus.h | 0 .../arm/CMSIS_6/CMSIS/Core/Include/core_cm1.h | 0 .../CMSIS_6/CMSIS/Core/Include/core_cm23.h | 0 .../arm/CMSIS_6/CMSIS/Core/Include/core_cm3.h | 0 .../CMSIS_6/CMSIS/Core/Include/core_cm33.h | 0 .../CMSIS_6/CMSIS/Core/Include/core_cm35p.h | 0 .../arm/CMSIS_6/CMSIS/Core/Include/core_cm4.h | 0 .../CMSIS_6/CMSIS/Core/Include/core_cm52.h | 0 .../CMSIS_6/CMSIS/Core/Include/core_cm55.h | 0 .../arm/CMSIS_6/CMSIS/Core/Include/core_cm7.h | 0 .../CMSIS_6/CMSIS/Core/Include/core_cm85.h | 0 .../CMSIS_6/CMSIS/Core/Include/core_sc000.h | 0 .../CMSIS_6/CMSIS/Core/Include/core_sc300.h | 0 .../CMSIS_6/CMSIS/Core/Include/core_starmc1.h | 0 .../Core/Include/m-profile/armv7m_cachel1.h | 0 .../CMSIS/Core/Include/m-profile/armv7m_mpu.h | 0 .../Core/Include/m-profile/armv81m_pac.h | 0 .../CMSIS/Core/Include/m-profile/armv8m_mpu.h | 0 .../CMSIS/Core/Include/m-profile/armv8m_pmu.h | 0 .../Core/Include/m-profile/cmsis_armclang_m.h | 0 .../Core/Include/m-profile/cmsis_clang_m.h | 0 .../Core/Include/m-profile/cmsis_gcc_m.h | 0 .../Core/Include/m-profile/cmsis_iccarm_m.h | 0 .../Include/m-profile/cmsis_tiarmclang_m.h | 0 .../Core/Include/r-profile/cmsis_armclang_r.h | 0 .../Core/Include/r-profile/cmsis_clang_r.h | 0 .../Core/Include/r-profile/cmsis_gcc_r.h | 0 .../CMSIS_6/CMSIS/Core/Include/tz_context.h | 0 .../{ => m33}/ra/arm/CMSIS_6/LICENSE | 0 .../{ => m33}/ra/fsp/inc/api/bsp_api.h | 0 .../{ => m33}/ra/fsp/inc/api/fsp_common_api.h | 0 .../{ => m33}/ra/fsp/inc/api/r_ioport_api.h | 0 .../{ => m33}/ra/fsp/inc/api/r_transfer_api.h | 0 .../{ => m33}/ra/fsp/inc/api/r_uart_api.h | 0 .../{ => m33}/ra/fsp/inc/fsp_features.h | 0 .../{ => m33}/ra/fsp/inc/fsp_version.h | 0 .../{ => m33}/ra/fsp/inc/instances/r_ioport.h | 0 .../ra/fsp/inc/instances/r_sci_b_uart.h | 0 .../Device/RENESAS/Include/R7KA8P1KF_core0.h | 0 .../Device/RENESAS/Include/R7KA8P1KF_core1.h | 0 .../cmsis/Device/RENESAS/Include/renesas.h | 0 .../bsp/cmsis/Device/RENESAS/Include/system.h | 0 .../bsp/cmsis/Device/RENESAS/Source/startup.c | 0 .../bsp/cmsis/Device/RENESAS/Source/system.c | 0 .../ra/fsp/src/bsp/mcu/all/bsp_clocks.c | 0 .../ra/fsp/src/bsp/mcu/all/bsp_clocks.h | 0 .../ra/fsp/src/bsp/mcu/all/bsp_common.c | 0 .../ra/fsp/src/bsp/mcu/all/bsp_common.h | 0 .../src/bsp/mcu/all/bsp_compiler_support.h | 0 .../ra/fsp/src/bsp/mcu/all/bsp_delay.c | 0 .../ra/fsp/src/bsp/mcu/all/bsp_delay.h | 0 .../ra/fsp/src/bsp/mcu/all/bsp_exceptions.h | 0 .../ra/fsp/src/bsp/mcu/all/bsp_group_irq.c | 0 .../ra/fsp/src/bsp/mcu/all/bsp_group_irq.h | 0 .../ra/fsp/src/bsp/mcu/all/bsp_guard.c | 0 .../ra/fsp/src/bsp/mcu/all/bsp_guard.h | 0 .../{ => m33}/ra/fsp/src/bsp/mcu/all/bsp_io.c | 0 .../{ => m33}/ra/fsp/src/bsp/mcu/all/bsp_io.h | 0 .../ra/fsp/src/bsp/mcu/all/bsp_ipc.c | 0 .../ra/fsp/src/bsp/mcu/all/bsp_ipc.h | 0 .../ra/fsp/src/bsp/mcu/all/bsp_irq.c | 0 .../ra/fsp/src/bsp/mcu/all/bsp_irq.h | 0 .../ra/fsp/src/bsp/mcu/all/bsp_macl.c | 0 .../ra/fsp/src/bsp/mcu/all/bsp_macl.h | 0 .../ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h | 0 .../ra/fsp/src/bsp/mcu/all/bsp_mmf.h | 0 .../ra/fsp/src/bsp/mcu/all/bsp_module_stop.h | 0 .../ra/fsp/src/bsp/mcu/all/bsp_ospi_b.c | 0 .../ra/fsp/src/bsp/mcu/all/bsp_ospi_b.h | 0 .../src/bsp/mcu/all/bsp_register_protection.c | 0 .../src/bsp/mcu/all/bsp_register_protection.h | 0 .../ra/fsp/src/bsp/mcu/all/bsp_sbrk.c | 0 .../ra/fsp/src/bsp/mcu/all/bsp_sdram.c | 0 .../ra/fsp/src/bsp/mcu/all/bsp_sdram.h | 0 .../ra/fsp/src/bsp/mcu/all/bsp_security.c | 0 .../ra/fsp/src/bsp/mcu/all/bsp_security.h | 0 .../ra/fsp/src/bsp/mcu/all/bsp_tfu.h | 0 .../ra/fsp/src/bsp/mcu/ra8p1/bsp_elc.h | 0 .../ra/fsp/src/bsp/mcu/ra8p1/bsp_feature.h | 0 .../ra/fsp/src/bsp/mcu/ra8p1/bsp_linker.c | 0 .../ra/fsp/src/bsp/mcu/ra8p1/bsp_mcu_info.h | 0 .../ra/fsp/src/bsp/mcu/ra8p1/bsp_override.h | 0 .../ra/fsp/src/bsp/mcu/ra8p1/bsp_peripheral.h | 0 .../src/bsp/mcu/ra8p1/r_adc_device_types.h | 0 .../src/bsp/mcu/ra8p1/r_lpm_device_types.h | 0 .../{ => m33}/ra/fsp/src/r_ioport/r_ioport.c | 0 .../ra/fsp/src/r_sci_b_uart/r_sci_b_uart.c | 0 .../{ => m33}/ra_cfg/SConscript | 0 .../m33/ra_cfg/fsp_cfg/bsp/board_cfg.h | 13 + .../m33/ra_cfg/fsp_cfg/bsp/bsp_cfg.h | 63 + .../ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h | 0 .../fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 12 + .../ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 503 + .../ra_cfg/fsp_cfg/bsp/bsp_mcu_ofs_cfg.h | 0 .../m33/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h | 212 + .../m33/ra_cfg/fsp_cfg/r_ioport_cfg.h | 13 + .../m33/ra_cfg/fsp_cfg/r_sci_b_uart_cfg.h | 16 + .../{ => m33}/ra_gen/SConscript | 0 .../m33/ra_gen/bsp_clock_cfg.h | 75 + .../m33/ra_gen/common_data.c | 8 + .../m33/ra_gen/common_data.h | 20 + .../ra8p1-titan-board/m33/ra_gen/hal_data.c | 76 + .../ra8p1-titan-board/m33/ra_gen/hal_data.h | 24 + .../ra8p1-titan-board/m33/ra_gen/main.c | 7 + .../ra8p1-titan-board/m33/ra_gen/pin_data.c | 53 + .../m33/ra_gen/vector_data.c | 21 + .../m33/ra_gen/vector_data.h | 32 + .../ra8p1-titan-board/m33/rasc_launcher.bat | 43 + .../ra8p1-titan-board/m33/rasc_version.bat | 36 + bsp/renesas/ra8p1-titan-board/m33/rtconfig.h | 225 + bsp/renesas/ra8p1-titan-board/m33/rtconfig.py | 104 + .../ra8p1-titan-board/m33/script/fsp.icf | 969 + .../ra8p1-titan-board/m33/script/fsp.ld | 1104 + .../ra8p1-titan-board/m33/script/fsp.scat | 1166 + .../ra8p1-titan-board/m33/src/hal_entry.c | 33 + .../ra8p1-titan-board/m33/template.uvoptx | 366 + .../ra8p1-titan-board/m33/template.uvprojx | 782 + .../.ci/attachconfig/attachconfig.yml | 0 .../ra8p1-titan-board/{ => m85}/.config | 32 +- .../ra8p1-titan-board/{ => m85}/.cproject | 0 bsp/renesas/ra8p1-titan-board/m85/.gitignore | 32 + .../ra8p1-titan-board/{ => m85}/.project | 0 .../{ => m85}/.settings/.rtmenus | Bin ...gnumcueclipse.managedbuild.cross.arm.prefs | 0 .../{ => m85}/.settings/language.settings.xml | 0 .../org.eclipse.core.resources.prefs | 0 .../.settings/org.eclipse.core.runtime.prefs | 0 .../{ => m85}/.settings/projcfg.ini | 0 .../{ => m85}/.settings/standalone.prefs | 0 .../titan_bsp.DAPLink.Debug.rttlaunch | 0 .../ra8p1-titan-board/{ => m85}/Kconfig | 4 +- .../ra8p1-titan-board/{ => m85}/SConscript | 0 .../ra8p1-titan-board/{ => m85}/SConstruct | 7 +- .../ra8p1-titan-board/{ => m85}/board/Kconfig | 2 +- .../ra8p1-titan-board/m85/board/SConscript | 18 + .../ra8p1-titan-board/{ => m85}/board/board.h | 0 .../{ => m85}/board/bsp_linker_info.h | 2 +- .../{ => m85}/board/ports/SConscript | 0 .../{ => m85}/board/ports/drv_filesystem.c | 0 .../{ => m85}/board/ports/drv_rtl8211.c | 0 .../{ => m85}/board/ports/fal_cfg.h | 0 .../{ => m85}/board/ports/gpio_cfg.h | 0 .../board/ports/gt9147_touch/SConscript | 0 .../board/ports/gt9147_touch/inc/gt9147.h | 0 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=> m85}/ra/fsp/src/r_rmac_phy/targets/KSZ8041/r_rmac_phy_target_ksz8041.c (100%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra/fsp/src/r_rmac_phy/targets/KSZ8091RNB/r_rmac_phy_target_ksz8091rnb.c (100%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra/fsp/src/r_rtc/r_rtc.c (100%) create mode 100644 bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_sci_b_uart/r_sci_b_uart.c rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra/fsp/src/r_sdhi/r_sdhi.c (100%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra/fsp/src/r_sdhi/r_sdhi_private.h (100%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra/fsp/src/r_spi_b/r_spi_b.c (100%) create mode 100644 bsp/renesas/ra8p1-titan-board/m85/ra_cfg/SConscript rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra_cfg/fsp_cfg/bsp/board_cfg.h (100%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra_cfg/fsp_cfg/bsp/bsp_cfg.h (100%) create mode 100644 bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h (100%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h (100%) create mode 100644 bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/bsp/bsp_mcu_ofs_cfg.h rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h (100%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra_cfg/fsp_cfg/r_adc_b_cfg.h (100%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra_cfg/fsp_cfg/r_canfd_cfg.h (100%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra_cfg/fsp_cfg/r_dmac_cfg.h (100%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra_cfg/fsp_cfg/r_gpt_cfg.h (100%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra_cfg/fsp_cfg/r_iic_master_cfg.h (100%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra_cfg/fsp_cfg/r_ioport_cfg.h (100%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra_cfg/fsp_cfg/r_layer3_switch_cfg.h (100%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra_cfg/fsp_cfg/r_ospi_b_cfg.h (100%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra_cfg/fsp_cfg/r_rmac_cfg.h (100%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra_cfg/fsp_cfg/r_rmac_phy_cfg.h (100%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra_cfg/fsp_cfg/r_rtc_cfg.h (100%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra_cfg/fsp_cfg/r_sci_b_uart_cfg.h (100%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra_cfg/fsp_cfg/r_sdhi_cfg.h (100%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra_cfg/fsp_cfg/r_spi_b_cfg.h (100%) create mode 100644 bsp/renesas/ra8p1-titan-board/m85/ra_gen/SConscript rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra_gen/bsp_clock_cfg.h (100%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra_gen/common_data.c (100%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra_gen/common_data.h (100%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra_gen/hal_data.c (100%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra_gen/hal_data.h (100%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra_gen/main.c (100%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra_gen/pin_data.c (100%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra_gen/vector_data.c (100%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/ra_gen/vector_data.h (100%) create mode 100644 bsp/renesas/ra8p1-titan-board/m85/rasc_launcher.bat create mode 100644 bsp/renesas/ra8p1-titan-board/m85/rasc_version.bat rename bsp/renesas/ra8p1-titan-board/{ => m85}/rtconfig.h (97%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/rtconfig.py (100%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/script/fsp.icf (99%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/script/fsp.ld (99%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/script/fsp.scat (99%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/src/hal_entry.c (100%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/template.uvoptx (90%) rename bsp/renesas/ra8p1-titan-board/{ => m85}/template.uvprojx (95%) delete mode 100644 bsp/renesas/ra8p1-titan-board/project.uvprojx create mode 100644 bsp/renesas/ra8p1-titan-board/solution.xml diff --git a/bsp/renesas/libraries/Kconfig b/bsp/renesas/libraries/Kconfig index 40b97913f0e..fd73d38a05e 100644 --- a/bsp/renesas/libraries/Kconfig +++ b/bsp/renesas/libraries/Kconfig @@ -63,10 +63,22 @@ config SOC_SERIES_R7FA8M85 config SOC_SERIES_R7KA8P1 bool - select ARCH_ARM_CORTEX_M85 select SOC_FAMILY_RENESAS_RA default n +config SOC_SERIES_R7KA8P1_CORE0 + bool + select SOC_SERIES_R7KA8P1 + select ARCH_ARM_CORTEX_M85 + default n + +config SOC_SERIES_R7KA8P1_CORE1 + bool + select SOC_SERIES_R7KA8P1 + select ARCH_ARM_CORTEX_M33 + select ARCH_ARM_CORTEX_SECURE + default n + config SOC_SERIES_R9A07G0 bool select ARCH_ARM_CORTEX_R52 diff --git a/bsp/renesas/ra8p1-titan-board/.gitignore b/bsp/renesas/ra8p1-titan-board/.gitignore index 38515c8a9c8..4d2b8c172f1 100644 --- a/bsp/renesas/ra8p1-titan-board/.gitignore +++ b/bsp/renesas/ra8p1-titan-board/.gitignore @@ -1,26 +1,4 @@ -/RTE -/Listings -/Objects -/Debug -/build -/makefile.targets -/rtconfig.pyc -/libraries -/rt-thread -/project.custom_argvars -/.vscode -/__pycache -/settings -/rtconfig_preinc.h -/bsp_linker_info.h -/fsp_gen.ld -/memory_regions.ld -/cmake -/.api_xml -/.clangd +/build/ +/.secure_xml /.secure_azone /.secure_rzone -/.secure_xml -/ra_cfg.txt -/packages/pkgs.json -/packages/pkgs_error.json \ No newline at end of file diff --git a/bsp/renesas/ra8p1-titan-board/README.md b/bsp/renesas/ra8p1-titan-board/README.md index 57c3f4cc72c..9e9d383e825 100644 --- a/bsp/renesas/ra8p1-titan-board/README.md +++ b/bsp/renesas/ra8p1-titan-board/README.md @@ -6,6 +6,13 @@ This document provides the BSP (Board Support Package) description for the RT-Thread **Titan Board** development board. By following the Quick Start Guide, developers can quickly get started with this BSP and run RT-Thread on the development board. +This BSP contains two independent projects: + +- `m85`: Cortex-M85 (CPU0), using UART8 and responsible for starting CPU1. +- `m33`: Cortex-M33 (CPU1), using UART5 and started by CPU0. + +Run SCons from the corresponding core directory. Each project has its own `configuration.xml`, `ra`, `ra_cfg`, `ra_gen`, and linker scripts. + The main contents include: - Introduction to the development board @@ -19,11 +26,11 @@ Titan Board integrates the **RA8P1** chip featuring a **1GHz Arm® Cortex®-M85* The front view of the development board is shown below: -![big](figures/big.png) +![big](m85/figures/big.png) Common **on-board resources** are as follows: -![titan_board_hw_resource](figures/titan_board_hw_resource.png) +![titan_board_hw_resource](m85/figures/titan_board_hw_resource.png) ## Peripheral Support @@ -77,31 +84,31 @@ This BSP can be directly imported into **RT-Thread Studio v2.3.0**. The followin 1. Install the compiler toolchain: -![image-20251127164450247](figures/image-20251127164450247.png) +![image-20251127164450247](m85/figures/image-20251127164450247.png) 2. Install debugging tools: Download **J-Link v8.48** and **PyOCD 0.2.9**. -![image-20251127164534568](figures/image-20251127164534568.png) +![image-20251127164534568](m85/figures/image-20251127164534568.png) ### **Create a Project** 1. Click **File → Import**. -![image-20251127164859503](figures/image-20251127164859503.png) +![image-20251127164859503](m85/figures/image-20251127164859503.png) 2. Select **Import RT-Thread BSP**, then click **Next**. -![image-20251127164952040](figures/image-20251127164952040.png) +![image-20251127164952040](m85/figures/image-20251127164952040.png) 3. Select the BSP root directory and fill in project information, then click **Finish**. -![image-20251127165319591](figures/image-20251127165319591.png) +![image-20251127165319591](m85/figures/image-20251127165319591.png) 4. The project based on the BSP is created. -![image-20251127165406340](figures/image-20251127165406340.png) +![image-20251127165406340](m85/figures/image-20251127165406340.png) ### **Configure Debug/Download Settings** @@ -109,13 +116,13 @@ Download **J-Link v8.48** and **PyOCD 0.2.9**. Modify the debugger configuration in the **Debugger** tab. -![image-20251127165957537](figures/image-20251127165957537.png) +![image-20251127165957537](m85/figures/image-20251127165957537.png) In the **Download** tab, change the download method to **Flash Hex File**, then click **OK**. -![image-20251127170436152](figures/image-20251127170436152.png) +![image-20251127170436152](m85/figures/image-20251127170436152.png) -![image-20251127171037225](figures/image-20251127171037225.png) +![image-20251127171037225](m85/figures/image-20251127171037225.png) **Hardware Connection** @@ -123,7 +130,29 @@ Use a USB cable to connect the development board to the PC, and use the DAP-Link **Build and Download** -![image-20251127165554294](figures/image-20251127165554294.png) +![image-20251127165554294](m85/figures/image-20251127165554294.png) + +When either the `m85` or `m33` Keil project is built, FSP Smart Configurator 6.2.0 runs after linking and generates `Objects/template.sbd`. The SBD stores the core's security and memory-region metadata for RA8P1 dual-core FSP solution partitioning and composition; it is not a directly flashable image. Only the SBD after-build step is enabled, so the build does not regenerate or overwrite the FSP-generated sources and linker scripts. + +After building `m85/project.uvprojx` and `m33/project.uvprojx` with Keil, run `build_solution_sbd.bat` from this BSP root. The script validates the core, device, and FSP version of both core SBDs, then uses `solution.xml` to generate `build/ra8p1_titan_dualcore.sbd`. This solution SBD is used for FSP dual-core partition and configuration exchange; it is not a directly flashable firmware image. + +The RA8P1 code MRAM is shared by both cores, but the J-Link Flash Algorithm must access it through CPU0/AP0, while M33 debugging must attach to CPU1/AP2. A Keil target has only one Device selection shared by its download and debug settings, so one target cannot select CPU0 for programming and CPU1 for debugging. The two M33 targets therefore share the same `Objects/template.axf`; they do not produce two M33 images. + +| Target | Device | Purpose | +| --- | --- | --- | +| `M33_Debug_CPU1` | `R7KA8P1KF:CPU1` | Build the Cortex-M33 image and attach to CPU1. Its Flash Download utility is disabled. | +| `M33_Download_CPU0` | `R7KA8P1KF:CPU0` | Program the existing M33 AXF at `0x020C0000` through CPU0 using Keil's native J-Link Flash driver. | + +Run `scons --target=mdk5` from the `m33` directory to regenerate `project.uvprojx`. Both targets are defined in `template.uvprojx` and are preserved in the generated project. + +1. Build and download the CPU0 firmware from the `m85` Keil project. +2. Select and build `M33_Debug_CPU1` in the `m33` project. +3. Switch to `M33_Download_CPU0` and click Download without building this target. The J-Link log must report `R7KA8P1KF_CPU0`. +4. Switch back to `M33_Debug_CPU1` and attach to CPU1 after programming. + +CPU0 starts CPU1 once from the common RA board initialization in `bsp/renesas/libraries/HAL_Drivers/drv_common.c` when `BSP_START_SECONDARY_CORE` is enabled. `hal_entry()` must not start CPU1 again. + +Do not use the M33 Reset command. Restart both cores with the board reset button, wait for M85 to start CPU1, and then attach again. **View Running Results** @@ -209,17 +238,17 @@ Users can locate the `configuration.xml` file in the project and import it into Select **File → Open** at the top-left corner to open the configuration file. -![image-20251030163423452](figures/image-20251030163423452.png) +![image-20251030163423452](m85/figures/image-20251030163423452.png) * **Generate FSP Code:** -![image-20251030163707813](figures/image-20251030163707813.png) +![image-20251030163707813](m85/figures/image-20251030163707813.png) **RT-Thread Settings** In **RT-Thread Settings**, you can configure the RT-Thread kernel, components, software packages, and Titan Board device drivers. -![image-20250819173700386](figures/image-20250819173700386.png) +![image-20250819173700386](m85/figures/image-20250819173700386.png) ## Contact Information @@ -227,4 +256,4 @@ If you have any thoughts or suggestions during usage, please feel free to contac ## Contribute Code -If you're interested in Titan Board and have some exciting projects you'd like to share, we welcome code contributions. Please refer to [How to Contribute to RT-Thread Code](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github). \ No newline at end of file +If you're interested in Titan Board and have some exciting projects you'd like to share, we welcome code contributions. Please refer to [How to Contribute to RT-Thread Code](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github). diff --git a/bsp/renesas/ra8p1-titan-board/README_zh.md b/bsp/renesas/ra8p1-titan-board/README_zh.md index 6d718343bb7..dcaa4edc56e 100644 --- a/bsp/renesas/ra8p1-titan-board/README_zh.md +++ b/bsp/renesas/ra8p1-titan-board/README_zh.md @@ -6,6 +6,13 @@ 本文档为 RT-Thread Titan Board 开发板提供 BSP (板级支持包) 说明。通过阅读快速上手章节，开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。 +本 BSP 包含两个相互独立的工程： + +- `m85`：Cortex-M85（CPU0），使用 UART8，并负责启动 CPU1。 +- `m33`：Cortex-M33（CPU1），使用 UART5，由 CPU0 启动。 + +请进入对应核心目录运行 SCons。两个工程分别维护自己的 `configuration.xml`、`ra`、`ra_cfg`、`ra_gen` 和链接脚本。 + 主要内容如下： - 开发板介绍 @@ -19,11 +26,11 @@ Titan Board 搭载频率 1GHz Arm® Cortex®-M85 与 250MHz Arm® Cortex®-M33 开发板正面外观如下图： -![big](figures/big.png) +![big](m85/figures/big.png) 该开发板常用 **板载资源** 如下： -![titan_board_hw_resource](figures/titan_board_hw_resource.png) +![titan_board_hw_resource](m85/figures/titan_board_hw_resource.png) ## 外设支持 @@ -75,31 +82,31 @@ Titan Board 搭载频率 1GHz Arm® Cortex®-M85 与 250MHz Arm® Cortex®-M33 1. 安装编译工具链 -![image-20251127164450247](figures/image-20251127164450247.png) +![image-20251127164450247](m85/figures/image-20251127164450247.png) 2. 调试工具 ​ 下载 J-Link v8.48 和 PyOCD 0.2.9。 -![image-20251127164534568](figures/image-20251127164534568.png) +![image-20251127164534568](m85/figures/image-20251127164534568.png) **创建工程** 1. 点击左上角 文件-->导入。 -![image-20251127164859503](figures/image-20251127164859503.png) +![image-20251127164859503](m85/figures/image-20251127164859503.png) 2. 选择导入 RT-Thread Bsp 到工作空间，点击“下一步”。 -![image-20251127164952040](figures/image-20251127164952040.png) +![image-20251127164952040](m85/figures/image-20251127164952040.png) 3. 选择 BSP 根目录并填写好工程信息，点击“完成”。 -![image-20251127165319591](figures/image-20251127165319591.png) +![image-20251127165319591](m85/figures/image-20251127165319591.png) 4. 基于 BSP 创建工程就完成了。 -![image-20251127165406340](figures/image-20251127165406340.png) +![image-20251127165406340](m85/figures/image-20251127165406340.png) **配置工程的调试下载设置** @@ -107,13 +114,13 @@ Titan Board 搭载频率 1GHz Arm® Cortex®-M85 与 250MHz Arm® Cortex®-M33 在”调试器“选项卡中修改调试器的配置。 -![image-20251127165957537](figures/image-20251127165957537.png) +![image-20251127165957537](m85/figures/image-20251127165957537.png) 在“下载”选项卡中将烧录方式改为“烧录Hex文件”，之后点击“确定“完成配置。 -![image-20251127170436152](figures/image-20251127170436152.png) +![image-20251127170436152](m85/figures/image-20251127170436152.png) -![image-20251127171037225](figures/image-20251127171037225.png) +![image-20251127171037225](m85/figures/image-20251127171037225.png) **硬件连接** @@ -121,7 +128,29 @@ Titan Board 搭载频率 1GHz Arm® Cortex®-M85 与 250MHz Arm® Cortex®-M33 **编译下载** -![image-20251127165554294](figures/image-20251127165554294.png) +![image-20251127165554294](m85/figures/image-20251127165554294.png) + +使用 Keil 编译 `m85` 或 `m33` 工程时，链接完成后会调用 FSP Smart Configurator 6.2.0 生成对应的 `Objects/template.sbd`。SBD 保存该核的安全区和内存区域描述，供 RA8P1 双核 FSP solution 进行分区与组合；它不是可直接烧录的固件。工程只启用 SBD 的 after-build 生成，不会在编译前覆盖 FSP 已生成的源码和链接脚本。 + +依次使用 Keil 编译 `m85/project.uvprojx` 和 `m33/project.uvprojx` 后，在本 BSP 根目录执行 `build_solution_sbd.bat`。脚本会检查两个核级 SBD 的核心、器件和 FSP 版本，并根据 `solution.xml` 生成 `build/ra8p1_titan_dualcore.sbd`。该板级 SBD 用于 FSP 双核 solution 的分区与配置交换，不是可直接烧录的固件。 + +RA8P1 的 Code MRAM 由两个核心共享，但 J-Link Flash Algorithm 需要通过 CPU0/AP0 访问，M33 调试则需要连接 CPU1/AP2。Keil 的一个 Target 只有一个 Device 选择，下载和调试共用该设置，因此无法在同一个 Target 中同时选择 CPU0 烧录和 CPU1 调试。两个 M33 Target 复用同一个 `Objects/template.axf`，并不是生成两份 M33 镜像。 + +| Target | Device | 用途 | +| --- | --- | --- | +| `M33_Debug_CPU1` | `R7KA8P1KF:CPU1` | 编译 Cortex-M33 镜像并连接 CPU1；该 Target 的 Flash Download 功能已禁用。 | +| `M33_Download_CPU0` | `R7KA8P1KF:CPU0` | 通过 Keil 原生 J-Link Flash 驱动和 CPU0，将已有 M33 AXF 烧写到 `0x020C0000`。 | + +在 `m33` 目录执行 `scons --target=mdk5` 可重新生成 `project.uvprojx`。两个 Target 都定义在 `template.uvprojx` 中，生成工程后仍会保留。 + +1. 使用 `m85` Keil 工程编译并下载 CPU0 固件。 +2. 在 `m33` 工程中选择并编译 `M33_Debug_CPU1`。 +3. 切换到 `M33_Download_CPU0`，不要编译该 Target，直接点击 Download；J-Link 日志必须显示 `R7KA8P1KF_CPU0`。 +4. 烧录完成后切回 `M33_Debug_CPU1`，连接 CPU1 调试。 + +启用 `BSP_START_SECONDARY_CORE` 后，CPU0 会在 `bsp/renesas/libraries/HAL_Drivers/drv_common.c` 的 RA 公共板级初始化中启动一次 CPU1，`hal_entry()` 不应再次启动 CPU1。 + +不要在 M33 工程中执行 Reset。需要重启时按开发板复位键同时复位两个核，等待 M85 再次启动 CPU1 后重新 attach。 **查看运行结果** @@ -207,17 +236,17 @@ void hal_entry(void) 选择左上角 file->open 打开配置文件 -![image-20251030163423452](figures/image-20251030163423452.png) +![image-20251030163423452](m85/figures/image-20251030163423452.png) * **生成 FSP 代码：** -![image-20251030163707813](figures/image-20251030163707813.png) +![image-20251030163707813](m85/figures/image-20251030163707813.png) **RT-Thread Settings** 在 RT-Thread Settings 中可以对 RT-Thread 的内核、组件、软件包以及 Titan Board 的设备驱动进行配置。 -![image-20250819173700386](figures/image-20250819173700386.png) +![image-20250819173700386](m85/figures/image-20250819173700386.png) ## 联系人信息 diff --git a/bsp/renesas/ra8p1-titan-board/build_solution_sbd.bat b/bsp/renesas/ra8p1-titan-board/build_solution_sbd.bat new file mode 100644 index 00000000000..caa8fb8f130 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/build_solution_sbd.bat @@ -0,0 +1,37 @@ +@echo off +setlocal ENABLEEXTENSIONS ENABLEDELAYEDEXPANSION + +set "BspRoot=%~dp0" +set "Cpu0Bundle=%BspRoot%m85\Objects\template.sbd" +set "Cpu1Bundle=%BspRoot%m33\Objects\template.sbd" +set "RascVersionFile=%BspRoot%m85\rasc_version.txt" + +if not exist "%Cpu0Bundle%" ( + echo [ERROR] CPU0 Smart Bundle "%Cpu0Bundle%" does not exist. + echo [ERROR] Build the m85 Keil project first. + exit /b 1 +) + +if not exist "%Cpu1Bundle%" ( + echo [ERROR] CPU1 Smart Bundle "%Cpu1Bundle%" does not exist. + echo [ERROR] Build the m33 Keil project first. + exit /b 1 +) + +call "%BspRoot%m85\rasc_version.bat" "%RascVersionFile%" +if errorlevel 1 exit /b 1 + +set /a idx=0 +for /f "usebackq tokens=*" %%a in ("%RascVersionFile%") do ( + if !idx! EQU 2 set "RascExe=%%a" + set /a idx+=1 +) + +if not defined RascExe ( + echo [ERROR] RASC executable is not configured. + exit /b 1 +) + +set "RascExe=%RascExe:rasc.exe=rascc.exe%" +powershell -NoProfile -ExecutionPolicy Bypass -File "%BspRoot%build_solution_sbd.ps1" -RascExe "%RascExe%" +exit /b %errorlevel% diff --git a/bsp/renesas/ra8p1-titan-board/build_solution_sbd.ps1 b/bsp/renesas/ra8p1-titan-board/build_solution_sbd.ps1 new file mode 100644 index 00000000000..496515041c8 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/build_solution_sbd.ps1 @@ -0,0 +1,174 @@ +param( + [Parameter(Mandatory = $true)] + [string] $RascExe +) + +$ErrorActionPreference = "Stop" +$bspRoot = $PSScriptRoot +$solutionPath = Join-Path $bspRoot "solution.xml" +$cpu0Bundle = Join-Path $bspRoot "m85\Objects\template.sbd" +$cpu1Bundle = Join-Path $bspRoot "m33\Objects\template.sbd" +$secureXmlPath = Join-Path $bspRoot ".secure_xml" +$secureAzonePath = Join-Path $bspRoot ".secure_azone" +$secureRzonePath = Join-Path $bspRoot ".secure_rzone" +$outputPath = Join-Path $bspRoot "build\ra8p1_titan_dualcore.sbd" + +Add-Type -AssemblyName System.IO.Compression.FileSystem + +function Save-XmlDocument +{ + param( + [System.Xml.XmlDocument] $Document, + [string] $Path + ) + + $settings = New-Object System.Xml.XmlWriterSettings + $settings.Encoding = New-Object System.Text.UTF8Encoding($false) + $settings.Indent = $true + $settings.NewLineChars = "`r`n" + $writer = [System.Xml.XmlWriter]::Create($Path, $settings) + try + { + $Document.Save($writer) + } + finally + { + $writer.Dispose() + } +} + +function Assert-SmartBundle +{ + param( + [string] $Path, + [string] $ExpectedCore, + [string] $ExpectedTarget, + [string] $ExpectedFspVersion + ) + + $archive = [System.IO.Compression.ZipFile]::OpenRead($Path) + try + { + $entry = $archive.GetEntry("cfg/secure.xml") + if ($null -eq $entry) + { + throw "Smart Bundle '$Path' does not contain cfg/secure.xml." + } + $stream = $entry.Open() + $reader = New-Object System.IO.StreamReader($stream) + try + { + [xml] $configuration = $reader.ReadToEnd() + } + finally + { + $reader.Dispose() + $stream.Dispose() + } + + $settings = $configuration.raConfiguration.generalSettings.option + $core = ($settings | Where-Object key -eq "Core").value + $target = ($settings | Where-Object key -eq "#TargetName#").value + $fspVersion = ($settings | Where-Object key -eq "#FSPVersion#").value + if ($core -ne $ExpectedCore -or $target -ne $ExpectedTarget -or $fspVersion -ne $ExpectedFspVersion) + { + throw "Smart Bundle '$Path' is $core/$target/FSP $fspVersion; expected $ExpectedCore/$ExpectedTarget/FSP $ExpectedFspVersion." + } + } + finally + { + $archive.Dispose() + } +} + +if (-not (Test-Path -LiteralPath $cpu0Bundle)) +{ + throw "CPU0 Smart Bundle '$cpu0Bundle' does not exist. Build the m85 Keil project first." +} + +if (-not (Test-Path -LiteralPath $cpu1Bundle)) +{ + throw "CPU1 Smart Bundle '$cpu1Bundle' does not exist. Build the m33 Keil project first." +} + +[xml] $solution = Get-Content -Raw -LiteralPath $solutionPath +$targetName = ($solution.raSolution.generalSettings.option | Where-Object key -eq "#TargetName#").value +$fspVersion = ($solution.raSolution.generalSettings.option | Where-Object key -eq "#FSPVersion#").value +Assert-SmartBundle -Path $cpu0Bundle -ExpectedCore "CPU0" -ExpectedTarget $targetName -ExpectedFspVersion $fspVersion +Assert-SmartBundle -Path $cpu1Bundle -ExpectedCore "CPU1" -ExpectedTarget $targetName -ExpectedFspVersion $fspVersion + +$secureXml = New-Object System.Xml.XmlDocument +$null = $secureXml.AppendChild($secureXml.CreateXmlDeclaration("1.0", "UTF-8", "no")) +$secureSolution = $secureXml.CreateElement("raSolution") +$secureSolution.SetAttribute("version", "12") +$null = $secureXml.AppendChild($secureSolution) +$null = $secureSolution.AppendChild($secureXml.ImportNode($solution.raSolution.generalSettings, $true)) + +$secureAzone = New-Object System.Xml.XmlDocument +$null = $secureAzone.AppendChild($secureAzone.CreateXmlDeclaration("1.0", "UTF-8", "yes")) +$azone = $secureAzone.CreateElement("azone") +$null = $secureAzone.AppendChild($azone) +$rzone = $secureAzone.CreateElement("rzone") +$rzone.SetAttribute("name", "$targetName.rzone") +$null = $azone.AppendChild($rzone) +$partition = $secureAzone.CreateElement("partition") +$null = $azone.AppendChild($partition) + +foreach ($sourceMemory in $solution.raSolution.raPartitions.memory) +{ + $memory = $secureAzone.CreateElement("memory") + foreach ($attributeName in @("parent", "name", "size", "offset", "security", "Pname")) + { + $memory.SetAttribute($attributeName, $sourceMemory.$attributeName) + } + if ($sourceMemory.userDefined -eq "true") + { + $memory.SetAttribute("info", "@user") + } + $null = $partition.AppendChild($memory) +} + +$archive = [System.IO.Compression.ZipFile]::OpenRead($cpu0Bundle) +try +{ + $entry = $archive.GetEntry("cfg/$targetName.rzone") + if ($null -eq $entry) + { + throw "Device resource '$targetName.rzone' is missing from '$cpu0Bundle'." + } + $inputStream = $entry.Open() + $outputStream = [System.IO.File]::Create($secureRzonePath) + try + { + $inputStream.CopyTo($outputStream) + } + finally + { + $outputStream.Dispose() + $inputStream.Dispose() + } +} +finally +{ + $archive.Dispose() +} + +try +{ + Save-XmlDocument -Document $secureXml -Path $secureXmlPath + Save-XmlDocument -Document $secureAzone -Path $secureAzonePath + & $RascExe -nosplash --launcher.suppressErrors --gensolutionbundle --compiler ARMv6 --devicefamily ra --projectname ra8p1_titan_dualcore $solutionPath + if ($LASTEXITCODE -ne 0) + { + throw "FSP Smart Configurator failed with exit code $LASTEXITCODE." + } + if (-not (Test-Path -LiteralPath $outputPath)) + { + throw "Solution Smart Bundle '$outputPath' was not generated." + } + Write-Output "Generated '$outputPath'." +} +finally +{ + Remove-Item -LiteralPath $secureXmlPath, $secureAzonePath, $secureRzonePath -Force -ErrorAction SilentlyContinue +} diff --git a/bsp/renesas/ra8p1-titan-board/m33/.config b/bsp/renesas/ra8p1-titan-board/m33/.config new file mode 100644 index 00000000000..7c86fb993f1 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/.config @@ -0,0 +1,399 @@ +CONFIG_SOC_R7KA8P1KF=y + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options +# end of klibc options + +CONFIG_RT_NAME_MAX=12 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice options +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice options + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_SMALL_MEM is not set +# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_USING_MEMHEAP=y +CONFIG_RT_MEMHEAP_FAST_MODE=y +# CONFIG_RT_MEMHEAP_BEST_MODE is not set +# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set +CONFIG_RT_USING_MEMHEAP_AS_HEAP=y +CONFIG_RT_USING_MEMHEAP_AUTO_BINDING=y +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart5" +CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y +CONFIG_RT_VER_NUM=0x50300 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_RT_USING_HW_ATOMIC=y +CONFIG_ARCH_USING_HW_ATOMIC_8=y +CONFIG_ARCH_USING_HW_ATOMIC_16=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_SECURE=y +CONFIG_ARCH_ARM_CORTEX_M33=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set +# CONFIG_FINSH_USING_FUNC_EXT is not set +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_SERIAL_V1 is not set +CONFIG_RT_USING_SERIAL_V2=y +# CONFIG_RT_SERIAL_BUF_STRATEGY_DROP is not set +CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y +CONFIG_RT_SERIAL_USING_DMA=y +# CONFIG_RT_USING_SERIAL_BYPASS is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_CLOCK_TIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_RPMSG is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_REGULATOR is not set +# CONFIG_RT_USING_POWER_SUPPLY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +CONFIG_SOC_FAMILY_RENESAS_RA=y +CONFIG_SOC_SERIES_R7KA8P1=y +CONFIG_SOC_SERIES_R7KA8P1_CORE1=y + +# +# Hardware Drivers Config +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_USING_ONCHIP_FLASH is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_ONCHIP_RTC is not set +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART5=y +CONFIG_BSP_UART5_RX_BUFSIZE=256 +CONFIG_BSP_UART5_TX_BUFSIZE=0 +# end of On-chip Peripheral Drivers +# end of Hardware Drivers Config diff --git a/bsp/renesas/ra8p1-titan-board/m33/.gitignore b/bsp/renesas/ra8p1-titan-board/m33/.gitignore new file mode 100644 index 00000000000..2f503652558 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/.gitignore @@ -0,0 +1,32 @@ +/RTE +/Listings +/Objects +/Debug +/build +/makefile.targets +/rtconfig.pyc +/libraries +/rt-thread +/project.custom_argvars +/.vscode +/__pycache +/settings +/rtconfig_preinc.h +/bsp_linker_info.h +/fsp_gen.ld +/memory_regions.ld +/cmake +/.api_xml +/.clangd +/.secure_azone +/.secure_rzone +/.secure_xml +/ra_cfg.txt +/packages/pkgs.json +/packages/pkgs_error.json +/output.rasc +/rasc_version.txt +/EventRecorderStub.scvd +/JLinkLog.txt +/JLinkSettings.ini +/*.uvguix.* diff --git a/bsp/renesas/ra8p1-titan-board/m33/Kconfig b/bsp/renesas/ra8p1-titan-board/m33/Kconfig new file mode 100644 index 00000000000..6370a55a552 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/Kconfig @@ -0,0 +1,20 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . +RTT_DIR := ../../../.. +PKGS_DIR := packages + +config SOC_R7KA8P1KF + bool + select SOC_SERIES_R7KA8P1_CORE1 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +source "$(RTT_DIR)/Kconfig" +osource "$(PKGS_DIR)/Kconfig" +rsource "../../libraries/Kconfig" + +if !RT_USING_NANO +rsource "$(BSP_DIR)/board/Kconfig" +endif diff --git a/bsp/renesas/ra8p1-titan-board/m33/SConscript b/bsp/renesas/ra8p1-titan-board/m33/SConscript new file mode 100644 index 00000000000..ecc73c48ae0 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/SConscript @@ -0,0 +1,28 @@ +# for module compiling +import os +Import('RTT_ROOT') +Import('rtconfig') +from building import * +from gcc import * + +cwd = GetCurrentDir() +src = [] +CPPPATH = [] +group = [] +list = os.listdir(cwd) + +if rtconfig.PLATFORM in ['iccarm']: + print("\nThe current project does not support IAR build\n") + Return('group') +elif rtconfig.PLATFORM in GetGCCLikePLATFORM(): + CPPPATH = [cwd] + src = Glob('./src/*.c') + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + group = group + SConscript(os.path.join(d, 'SConscript')) + +Return('group') diff --git a/bsp/renesas/ra8p1-titan-board/m33/SConstruct b/bsp/renesas/ra8p1-titan-board/m33/SConstruct new file mode 100644 index 00000000000..0040f826e82 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/SConstruct @@ -0,0 +1,51 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./..') +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +rtconfig.BSP_LIBRARY_TYPE = None + +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'), + variant_dir='build/libraries/HAL_Drivers', duplicate=0)) +DoBuilding(TARGET, objs) diff --git a/bsp/renesas/ra8p1-titan-board/m33/board/Kconfig b/bsp/renesas/ra8p1-titan-board/m33/board/Kconfig new file mode 100644 index 00000000000..e024016f835 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/board/Kconfig @@ -0,0 +1,31 @@ +menu "Hardware Drivers Config" + + menu "On-chip Peripheral Drivers" + + rsource "../../../libraries/HAL_Drivers/drivers/Kconfig" + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + select RT_USING_SERIAL_V2 + if BSP_USING_UART + menuconfig BSP_USING_UART5 + bool "Enable UART5" + default y + if BSP_USING_UART5 + config BSP_UART5_RX_BUFSIZE + int "Set UART5 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART5_TX_BUFSIZE + int "Set UART5 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + endmenu +endmenu diff --git a/bsp/renesas/ra8p1-titan-board/board/SConscript b/bsp/renesas/ra8p1-titan-board/m33/board/SConscript similarity index 85% rename from bsp/renesas/ra8p1-titan-board/board/SConscript rename to bsp/renesas/ra8p1-titan-board/m33/board/SConscript index 5d9eaf6e1a6..41bc3e76543 100644 --- a/bsp/renesas/ra8p1-titan-board/board/SConscript +++ b/bsp/renesas/ra8p1-titan-board/m33/board/SConscript @@ -7,7 +7,7 @@ list = os.listdir(cwd) CPPPATH = [cwd] src = Glob('*.c') -CPPDEFINES = ['_RA_CORE=0'] +CPPDEFINES = ['_RENESAS_RA_', '_RA_CORE=CPU1', '_RA_ORDINAL=2'] objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) diff --git a/bsp/renesas/ra8p1-titan-board/m33/board/board.h b/bsp/renesas/ra8p1-titan-board/m33/board/board.h new file mode 100644 index 00000000000..362a1f42d08 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/board/board.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-10 Sherman first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include "hal_data.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define RA_SRAM_SIZE 256 /* The SRAM size of the chip needs to be modified */ +#define RA_SRAM_END (0x22194000 + RA_SRAM_SIZE * 1024) + +#ifdef __ARMCC_VERSION +extern int Image$$RAM_END$$ZI$$Base; +#define HEAP_BEGIN ((void *)&Image$$RAM_END$$ZI$$Base) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +extern int __RAM_segment_used_end__; +#define HEAP_BEGIN (&__RAM_segment_used_end__) +#endif + +#define HEAP_END RA_SRAM_END + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m33/board/bsp_linker_info.h b/bsp/renesas/ra8p1-titan-board/m33/board/bsp_linker_info.h new file mode 100644 index 00000000000..0679a0df674 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/board/bsp_linker_info.h @@ -0,0 +1,412 @@ +/* UNCRUSTIFY-OFF */ +#ifndef BSP_LINKER_H +#define BSP_LINKER_H + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/******* Solution Definitions *************/ +#define BSP_PARTITION_RAM_CPU0_S_START (0x22000000) +#define BSP_PARTITION_RAM_CPU0_S_SIZE (0x174000) +#define BSP_PARTITION_SHARED_MEM_START (0x22174000) +#define BSP_PARTITION_SHARED_MEM_SIZE (0x20000) +#define BSP_PARTITION_RAM_CPU0_C_START (0x22174000) +#define BSP_PARTITION_RAM_CPU0_C_SIZE (0x0) +#define BSP_PARTITION_RAM_CPU1_S_START (0x22194000) +#define BSP_PARTITION_RAM_CPU1_S_SIZE (0x40000) +#define BSP_PARTITION_RAM_CPU1_C_START (0x221D4000) +#define BSP_PARTITION_RAM_CPU1_C_SIZE (0x0) +#define BSP_PARTITION_FLASH_CPU0_S_START (0x02000000) +#define BSP_PARTITION_FLASH_CPU0_S_SIZE (0xC0000) +#define BSP_PARTITION_FLASH_CPU0_C_START (0x020C0000) +#define BSP_PARTITION_FLASH_CPU0_C_SIZE (0x0) +#define BSP_PARTITION_FLASH_CPU1_S_START (0x020C0000) +#define BSP_PARTITION_FLASH_CPU1_S_SIZE (0x40000) +#define BSP_PARTITION_FLASH_CPU1_C_START (0x02100000) +#define BSP_PARTITION_FLASH_CPU1_C_SIZE (0x0) +#define BSP_PARTITION_DATA_FLASH_CPU0_S_START (0x27000000) +#define BSP_PARTITION_DATA_FLASH_CPU0_S_SIZE (0x0) +#define BSP_PARTITION_DATA_FLASH_CPU1_S_START (0x27000000) +#define BSP_PARTITION_DATA_FLASH_CPU1_S_SIZE (0x0) +#define BSP_PARTITION_SDRAM_CPU0_S_START (0x68000000) +#define BSP_PARTITION_SDRAM_CPU0_S_SIZE (0x4000000) +#define BSP_PARTITION_SDRAM_CPU1_S_START (0x6C000000) +#define BSP_PARTITION_SDRAM_CPU1_S_SIZE (0x4000000) +#define BSP_PARTITION_OSPI0_CS0_CPU0_S_START (0x80000000) +#define BSP_PARTITION_OSPI0_CS0_CPU0_S_SIZE (0x8000000) +#define BSP_PARTITION_OSPI0_CS0_CPU1_S_START (0x88000000) +#define BSP_PARTITION_OSPI0_CS0_CPU1_S_SIZE (0x8000000) +#define BSP_PARTITION_OSPI0_CS1_CPU0_S_START (0x90000000) +#define BSP_PARTITION_OSPI0_CS1_CPU0_S_SIZE (0x8000000) +#define BSP_PARTITION_OSPI0_CS1_CPU1_S_START (0x98000000) +#define BSP_PARTITION_OSPI0_CS1_CPU1_S_SIZE (0x8000000) +#define BSP_PARTITION_OSPI1_CS0_CPU0_S_START (0x70000000) +#define BSP_PARTITION_OSPI1_CS0_CPU0_S_SIZE (0x4000000) +#define BSP_PARTITION_OSPI1_CS0_CPU1_S_START (0x74000000) +#define BSP_PARTITION_OSPI1_CS0_CPU1_S_SIZE (0x4000000) +#define BSP_PARTITION_OSPI1_CS1_CPU0_S_START (0x78000000) +#define BSP_PARTITION_OSPI1_CS1_CPU0_S_SIZE (0x4000000) +#define BSP_PARTITION_OSPI1_CS1_CPU1_S_START (0x7C000000) +#define BSP_PARTITION_OSPI1_CS1_CPU1_S_SIZE (0x4000000) +#define BSP_PARTITION_ITCM_CPU0_S_START (0x00000000) +#define BSP_PARTITION_ITCM_CPU0_S_SIZE (0x20000) +#define BSP_PARTITION_DTCM_CPU0_S_START (0x20000000) +#define BSP_PARTITION_DTCM_CPU0_S_SIZE (0x20000) +#define BSP_PARTITION_CTCM_CPU1_S_START (0x00000000) +#define BSP_PARTITION_CTCM_CPU1_S_SIZE (0x10000) +#define BSP_PARTITION_STCM_CPU1_S_START (0x20000000) +#define BSP_PARTITION_STCM_CPU1_S_SIZE (0x10000) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +/* linker generated initialization table data structures types */ +typedef enum e_bsp_init_mem +{ + INIT_MEM_ZERO, + INIT_MEM_FLASH, + INIT_MEM_DATA_FLASH, + INIT_MEM_RAM, + INIT_MEM_DTCM, + INIT_MEM_ITCM, + INIT_MEM_CTCM, + INIT_MEM_STCM, + INIT_MEM_OSPI0_CS0, + INIT_MEM_OSPI0_CS1, + INIT_MEM_OSPI1_CS0, + INIT_MEM_OSPI1_CS1, + INIT_MEM_QSPI_FLASH, + INIT_MEM_SDRAM, + INIT_MEM_SIP_FLASH, +} bsp_init_mem_t; + +typedef struct st_bsp_init_type +{ + uint32_t copy_64 :8; /* if 1, must use 64 bit copy operation (to keep ecc happy) */ + uint32_t external :8; /* =1 if either source or destination is external, else 0 */ + uint32_t source_type :8; + uint32_t destination_type :8; +} bsp_init_type_t; + +typedef struct st_bsp_init_zero_info +{ + uint32_t *const p_base; + uint32_t *const p_limit; + bsp_init_type_t type; +} bsp_init_zero_info_t; + +typedef struct st_bsp_init_copy_info +{ + uint32_t *const p_base; + uint32_t *const p_limit; + uint32_t *const p_load; + bsp_init_type_t type; +} bsp_init_copy_info_t; +typedef struct st_bsp_init_nocache_info +{ + uint32_t *const p_base; + uint32_t *const p_limit; +} bsp_mpu_nocache_info_t; + +typedef struct st_bsp_init_info +{ + uint32_t zero_count; + bsp_init_zero_info_t const *const p_zero_list; + uint32_t copy_count; + bsp_init_copy_info_t const *const p_copy_list; + uint32_t nocache_count; + bsp_mpu_nocache_info_t const *const p_nocache_list; +} bsp_init_info_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +extern bsp_init_info_t const g_init_info; +/* These symbols are used for sau/idau configuration in a secure project */ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +#endif // BSP_LINKER_H +#ifdef BSP_LINKER_C +/*********************************************************************************************************************** + * Objects allocated by bsp_linker.c + **********************************************************************************************************************/ +/* DDSC symbol definitions */ +#if defined(__ARMCC_VERSION) +#define __sdram_zero_nocache$$Base Image$$__sdram_zero_nocache$$ZI$$Base +#define __sdram_zero_nocache$$Limit Image$$__sdram_zero_nocache$$ZI$$Limit +#define __sdram_zero$$Base Image$$__sdram_zero$$ZI$$Base +#define __sdram_zero$$Limit Image$$__sdram_zero$$ZI$$Limit +#define __ospi0_cs0_zero_nocache$$Base Image$$__ospi0_cs0_zero_nocache$$ZI$$Base +#define __ospi0_cs0_zero_nocache$$Limit Image$$__ospi0_cs0_zero_nocache$$ZI$$Limit +#define __ospi0_cs0_zero$$Base Image$$__ospi0_cs0_zero$$ZI$$Base +#define __ospi0_cs0_zero$$Limit Image$$__ospi0_cs0_zero$$ZI$$Limit +#define __ospi1_cs0_zero_nocache$$Base Image$$__ospi1_cs0_zero_nocache$$ZI$$Base +#define __ospi1_cs0_zero_nocache$$Limit Image$$__ospi1_cs0_zero_nocache$$ZI$$Limit +#define __ospi1_cs0_zero$$Base Image$$__ospi1_cs0_zero$$ZI$$Base +#define __ospi1_cs0_zero$$Limit Image$$__ospi1_cs0_zero$$ZI$$Limit +#define __ctcm_zero$$Base Image$$__ctcm_zero$$ZI$$Base +#define __ctcm_zero$$Limit Image$$__ctcm_zero$$ZI$$Limit +#define __stcm_zero$$Base Image$$__stcm_zero$$ZI$$Base +#define __stcm_zero$$Limit Image$$__stcm_zero$$ZI$$Limit +#define __ram_zero_nocache$$Base Image$$__ram_zero_nocache$$ZI$$Base +#define __ram_zero_nocache$$Limit Image$$__ram_zero_nocache$$ZI$$Limit +#define __ram_zero$$Base Image$$__ram_zero$$ZI$$Base +#define __ram_zero$$Limit Image$$__ram_zero$$ZI$$Limit +#define __sdram_from_ospi0_cs1$$Base Image$$__sdram_from_ospi0_cs1$$Base +#define __sdram_from_ospi0_cs1$$Limit Image$$__sdram_from_ospi0_cs1$$Limit +#define __sdram_from_ospi1_cs1$$Base Image$$__sdram_from_ospi1_cs1$$Base +#define __sdram_from_ospi1_cs1$$Limit Image$$__sdram_from_ospi1_cs1$$Limit +#define __sdram_from_data_flash$$Base Image$$__sdram_from_data_flash$$Base +#define __sdram_from_data_flash$$Limit Image$$__sdram_from_data_flash$$Limit +#define __sdram_from_flash$$Base Image$$__sdram_from_flash$$Base +#define __sdram_from_flash$$Limit Image$$__sdram_from_flash$$Limit +#define __ospi0_cs0_from_ospi0_cs1$$Base Image$$__ospi0_cs0_from_ospi0_cs1$$Base +#define __ospi0_cs0_from_ospi0_cs1$$Limit Image$$__ospi0_cs0_from_ospi0_cs1$$Limit +#define __ospi0_cs0_from_ospi1_cs1$$Base Image$$__ospi0_cs0_from_ospi1_cs1$$Base +#define __ospi0_cs0_from_ospi1_cs1$$Limit Image$$__ospi0_cs0_from_ospi1_cs1$$Limit +#define __ospi0_cs0_from_data_flash$$Base Image$$__ospi0_cs0_from_data_flash$$Base +#define __ospi0_cs0_from_data_flash$$Limit Image$$__ospi0_cs0_from_data_flash$$Limit +#define __ospi0_cs0_from_flash$$Base Image$$__ospi0_cs0_from_flash$$Base +#define __ospi0_cs0_from_flash$$Limit Image$$__ospi0_cs0_from_flash$$Limit +#define __ospi1_cs0_from_ospi0_cs1$$Base Image$$__ospi1_cs0_from_ospi0_cs1$$Base +#define __ospi1_cs0_from_ospi0_cs1$$Limit Image$$__ospi1_cs0_from_ospi0_cs1$$Limit +#define __ospi1_cs0_from_ospi1_cs1$$Base Image$$__ospi1_cs0_from_ospi1_cs1$$Base +#define __ospi1_cs0_from_ospi1_cs1$$Limit Image$$__ospi1_cs0_from_ospi1_cs1$$Limit +#define __ospi1_cs0_from_data_flash$$Base Image$$__ospi1_cs0_from_data_flash$$Base +#define __ospi1_cs0_from_data_flash$$Limit Image$$__ospi1_cs0_from_data_flash$$Limit +#define __ospi1_cs0_from_flash$$Base Image$$__ospi1_cs0_from_flash$$Base +#define __ospi1_cs0_from_flash$$Limit Image$$__ospi1_cs0_from_flash$$Limit +#define __ctcm_from_ospi0_cs1$$Base Image$$__ctcm_from_ospi0_cs1$$Base +#define __ctcm_from_ospi0_cs1$$Limit Image$$__ctcm_from_ospi0_cs1$$Limit +#define __ctcm_from_ospi1_cs1$$Base Image$$__ctcm_from_ospi1_cs1$$Base +#define __ctcm_from_ospi1_cs1$$Limit Image$$__ctcm_from_ospi1_cs1$$Limit +#define __ctcm_from_data_flash$$Base Image$$__ctcm_from_data_flash$$Base +#define __ctcm_from_data_flash$$Limit Image$$__ctcm_from_data_flash$$Limit +#define __ctcm_from_flash$$Base Image$$__ctcm_from_flash$$Base +#define __ctcm_from_flash$$Limit Image$$__ctcm_from_flash$$Limit +#define __stcm_from_ospi0_cs1$$Base Image$$__stcm_from_ospi0_cs1$$Base +#define __stcm_from_ospi0_cs1$$Limit Image$$__stcm_from_ospi0_cs1$$Limit +#define __stcm_from_ospi1_cs1$$Base Image$$__stcm_from_ospi1_cs1$$Base +#define __stcm_from_ospi1_cs1$$Limit Image$$__stcm_from_ospi1_cs1$$Limit +#define __stcm_from_data_flash$$Base Image$$__stcm_from_data_flash$$Base +#define __stcm_from_data_flash$$Limit Image$$__stcm_from_data_flash$$Limit +#define __stcm_from_flash$$Base Image$$__stcm_from_flash$$Base +#define __stcm_from_flash$$Limit Image$$__stcm_from_flash$$Limit +#define __ram_from_ospi0_cs1$$Base Image$$__ram_from_ospi0_cs1$$Base +#define __ram_from_ospi0_cs1$$Limit Image$$__ram_from_ospi0_cs1$$Limit +#define __ram_from_ospi1_cs1$$Base Image$$__ram_from_ospi1_cs1$$Base +#define __ram_from_ospi1_cs1$$Limit Image$$__ram_from_ospi1_cs1$$Limit +#define __ram_from_data_flash$$Base Image$$__ram_from_data_flash$$Base +#define __ram_from_data_flash$$Limit Image$$__ram_from_data_flash$$Limit +#define __ram_from_flash$$Base Image$$__ram_from_flash$$Base +#define __ram_from_flash$$Limit Image$$__ram_from_flash$$Limit +#define __sdram_noinit_nocache$$Base Image$$__sdram_noinit_nocache$$ZI$$Base +#define __sdram_noinit_nocache$$Limit Image$$__sdram_noinit_nocache$$ZI$$Limit +#define __ospi0_cs0_noinit_nocache$$Base Image$$__ospi0_cs0_noinit_nocache$$ZI$$Base +#define __ospi0_cs0_noinit_nocache$$Limit Image$$__ospi0_cs0_noinit_nocache$$ZI$$Limit +#define __ospi1_cs0_noinit_nocache$$Base Image$$__ospi1_cs0_noinit_nocache$$ZI$$Base +#define __ospi1_cs0_noinit_nocache$$Limit Image$$__ospi1_cs0_noinit_nocache$$ZI$$Limit +#define __ram_noinit_nocache$$Base Image$$__ram_noinit_nocache$$ZI$$Base +#define __ram_noinit_nocache$$Limit Image$$__ram_noinit_nocache$$ZI$$Limit +#define __sdram_from_ospi0_cs1$$Load Load$$__sdram_from_ospi0_cs1$$Base +#define __sdram_from_ospi1_cs1$$Load Load$$__sdram_from_ospi1_cs1$$Base +#define __sdram_from_data_flash$$Load Load$$__sdram_from_data_flash$$Base +#define __sdram_from_flash$$Load Load$$__sdram_from_flash$$Base +#define __ospi0_cs0_from_ospi0_cs1$$Load Load$$__ospi0_cs0_from_ospi0_cs1$$Base +#define __ospi0_cs0_from_ospi1_cs1$$Load Load$$__ospi0_cs0_from_ospi1_cs1$$Base +#define __ospi0_cs0_from_data_flash$$Load Load$$__ospi0_cs0_from_data_flash$$Base +#define __ospi0_cs0_from_flash$$Load Load$$__ospi0_cs0_from_flash$$Base +#define __ospi1_cs0_from_ospi0_cs1$$Load Load$$__ospi1_cs0_from_ospi0_cs1$$Base +#define __ospi1_cs0_from_ospi1_cs1$$Load Load$$__ospi1_cs0_from_ospi1_cs1$$Base +#define __ospi1_cs0_from_data_flash$$Load Load$$__ospi1_cs0_from_data_flash$$Base +#define __ospi1_cs0_from_flash$$Load Load$$__ospi1_cs0_from_flash$$Base +#define __ctcm_from_ospi0_cs1$$Load Load$$__ctcm_from_ospi0_cs1$$Base +#define __ctcm_from_ospi1_cs1$$Load Load$$__ctcm_from_ospi1_cs1$$Base +#define __ctcm_from_data_flash$$Load Load$$__ctcm_from_data_flash$$Base +#define __ctcm_from_flash$$Load Load$$__ctcm_from_flash$$Base +#define __stcm_from_ospi0_cs1$$Load Load$$__stcm_from_ospi0_cs1$$Base +#define __stcm_from_ospi1_cs1$$Load Load$$__stcm_from_ospi1_cs1$$Base +#define __stcm_from_data_flash$$Load Load$$__stcm_from_data_flash$$Base +#define __stcm_from_flash$$Load Load$$__stcm_from_flash$$Base +#define __ram_from_ospi0_cs1$$Load Load$$__ram_from_ospi0_cs1$$Base +#define __ram_from_ospi1_cs1$$Load Load$$__ram_from_ospi1_cs1$$Base +#define __ram_from_data_flash$$Load Load$$__ram_from_data_flash$$Base +#define __ram_from_flash$$Load Load$$__ram_from_flash$$Base +#endif +/* Zero initialization tables */ +extern uint32_t __sdram_zero_nocache$$Base; +extern uint32_t __sdram_zero_nocache$$Limit; +extern uint32_t __sdram_zero$$Base; +extern uint32_t __sdram_zero$$Limit; +extern uint32_t __ospi0_cs0_zero_nocache$$Base; +extern uint32_t __ospi0_cs0_zero_nocache$$Limit; +extern uint32_t __ospi0_cs0_zero$$Base; +extern uint32_t __ospi0_cs0_zero$$Limit; +extern uint32_t __ospi1_cs0_zero_nocache$$Base; +extern uint32_t __ospi1_cs0_zero_nocache$$Limit; +extern uint32_t __ospi1_cs0_zero$$Base; +extern uint32_t __ospi1_cs0_zero$$Limit; +extern uint32_t __ctcm_zero$$Base; +extern uint32_t __ctcm_zero$$Limit; +extern uint32_t __stcm_zero$$Base; +extern uint32_t __stcm_zero$$Limit; +extern uint32_t __ram_zero_nocache$$Base; +extern uint32_t __ram_zero_nocache$$Limit; +extern uint32_t __ram_zero$$Base; +extern uint32_t __ram_zero$$Limit; +static const bsp_init_zero_info_t zero_list[] = +{ + {.p_base = &__sdram_zero_nocache$$Base, .p_limit = &__sdram_zero_nocache$$Limit,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_SDRAM}}, + {.p_base = &__sdram_zero$$Base, .p_limit = &__sdram_zero$$Limit,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_SDRAM}}, + {.p_base = &__ospi0_cs0_zero_nocache$$Base, .p_limit = &__ospi0_cs0_zero_nocache$$Limit,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_OSPI0_CS0}}, + {.p_base = &__ospi0_cs0_zero$$Base, .p_limit = &__ospi0_cs0_zero$$Limit,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_OSPI0_CS0}}, + {.p_base = &__ospi1_cs0_zero_nocache$$Base, .p_limit = &__ospi1_cs0_zero_nocache$$Limit,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_OSPI1_CS0}}, + {.p_base = &__ospi1_cs0_zero$$Base, .p_limit = &__ospi1_cs0_zero$$Limit,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_OSPI1_CS0}}, + {.p_base = &__ctcm_zero$$Base, .p_limit = &__ctcm_zero$$Limit,.type={.copy_64 = 0, .external = 0, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_CTCM}}, + {.p_base = &__stcm_zero$$Base, .p_limit = &__stcm_zero$$Limit,.type={.copy_64 = 0, .external = 0, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_STCM}}, + {.p_base = &__ram_zero_nocache$$Base, .p_limit = &__ram_zero_nocache$$Limit,.type={.copy_64 = 0, .external = 0, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_RAM}}, + {.p_base = &__ram_zero$$Base, .p_limit = &__ram_zero$$Limit,.type={.copy_64 = 0, .external = 0, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_RAM}} +}; +/* Load initialization tables */ +extern uint32_t __sdram_from_ospi0_cs1$$Base; +extern uint32_t __sdram_from_ospi0_cs1$$Limit; +extern uint32_t __sdram_from_ospi0_cs1$$Load; +extern uint32_t __sdram_from_ospi1_cs1$$Base; +extern uint32_t __sdram_from_ospi1_cs1$$Limit; +extern uint32_t __sdram_from_ospi1_cs1$$Load; +extern uint32_t __sdram_from_data_flash$$Base; +extern uint32_t __sdram_from_data_flash$$Limit; +extern uint32_t __sdram_from_data_flash$$Load; +extern uint32_t __sdram_from_flash$$Base; +extern uint32_t __sdram_from_flash$$Limit; +extern uint32_t __sdram_from_flash$$Load; +extern uint32_t __ospi0_cs0_from_ospi0_cs1$$Base; +extern uint32_t __ospi0_cs0_from_ospi0_cs1$$Limit; +extern uint32_t __ospi0_cs0_from_ospi0_cs1$$Load; +extern uint32_t __ospi0_cs0_from_ospi1_cs1$$Base; +extern uint32_t __ospi0_cs0_from_ospi1_cs1$$Limit; +extern uint32_t __ospi0_cs0_from_ospi1_cs1$$Load; +extern uint32_t __ospi0_cs0_from_data_flash$$Base; +extern uint32_t __ospi0_cs0_from_data_flash$$Limit; +extern uint32_t __ospi0_cs0_from_data_flash$$Load; +extern uint32_t __ospi0_cs0_from_flash$$Base; +extern uint32_t __ospi0_cs0_from_flash$$Limit; +extern uint32_t __ospi0_cs0_from_flash$$Load; +extern uint32_t __ospi1_cs0_from_ospi0_cs1$$Base; +extern uint32_t __ospi1_cs0_from_ospi0_cs1$$Limit; +extern uint32_t __ospi1_cs0_from_ospi0_cs1$$Load; +extern uint32_t __ospi1_cs0_from_ospi1_cs1$$Base; +extern uint32_t __ospi1_cs0_from_ospi1_cs1$$Limit; +extern uint32_t __ospi1_cs0_from_ospi1_cs1$$Load; +extern uint32_t __ospi1_cs0_from_data_flash$$Base; +extern uint32_t __ospi1_cs0_from_data_flash$$Limit; +extern uint32_t __ospi1_cs0_from_data_flash$$Load; +extern uint32_t __ospi1_cs0_from_flash$$Base; +extern uint32_t __ospi1_cs0_from_flash$$Limit; +extern uint32_t __ospi1_cs0_from_flash$$Load; +extern uint32_t __ctcm_from_ospi0_cs1$$Base; +extern uint32_t __ctcm_from_ospi0_cs1$$Limit; +extern uint32_t __ctcm_from_ospi0_cs1$$Load; +extern uint32_t __ctcm_from_ospi1_cs1$$Base; +extern uint32_t __ctcm_from_ospi1_cs1$$Limit; +extern uint32_t __ctcm_from_ospi1_cs1$$Load; +extern uint32_t __ctcm_from_data_flash$$Base; +extern uint32_t __ctcm_from_data_flash$$Limit; +extern uint32_t __ctcm_from_data_flash$$Load; +extern uint32_t __ctcm_from_flash$$Base; +extern uint32_t __ctcm_from_flash$$Limit; +extern uint32_t __ctcm_from_flash$$Load; +extern uint32_t __stcm_from_ospi0_cs1$$Base; +extern uint32_t __stcm_from_ospi0_cs1$$Limit; +extern uint32_t __stcm_from_ospi0_cs1$$Load; +extern uint32_t __stcm_from_ospi1_cs1$$Base; +extern uint32_t __stcm_from_ospi1_cs1$$Limit; +extern uint32_t __stcm_from_ospi1_cs1$$Load; +extern uint32_t __stcm_from_data_flash$$Base; +extern uint32_t __stcm_from_data_flash$$Limit; +extern uint32_t __stcm_from_data_flash$$Load; +extern uint32_t __stcm_from_flash$$Base; +extern uint32_t __stcm_from_flash$$Limit; +extern uint32_t __stcm_from_flash$$Load; +extern uint32_t __ram_from_ospi0_cs1$$Base; +extern uint32_t __ram_from_ospi0_cs1$$Limit; +extern uint32_t __ram_from_ospi0_cs1$$Load; +extern uint32_t __ram_from_ospi1_cs1$$Base; +extern uint32_t __ram_from_ospi1_cs1$$Limit; +extern uint32_t __ram_from_ospi1_cs1$$Load; +extern uint32_t __ram_from_data_flash$$Base; +extern uint32_t __ram_from_data_flash$$Limit; +extern uint32_t __ram_from_data_flash$$Load; +extern uint32_t __ram_from_flash$$Base; +extern uint32_t __ram_from_flash$$Limit; +extern uint32_t __ram_from_flash$$Load; +static const bsp_init_copy_info_t copy_list[] = +{ + {.p_base = &__sdram_from_ospi0_cs1$$Base, .p_limit = &__sdram_from_ospi0_cs1$$Limit, .p_load = &__sdram_from_ospi0_cs1$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_OSPI0_CS1, .destination_type = INIT_MEM_SDRAM}}, + {.p_base = &__sdram_from_ospi1_cs1$$Base, .p_limit = &__sdram_from_ospi1_cs1$$Limit, .p_load = &__sdram_from_ospi1_cs1$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_OSPI1_CS1, .destination_type = INIT_MEM_SDRAM}}, + {.p_base = &__sdram_from_data_flash$$Base, .p_limit = &__sdram_from_data_flash$$Limit, .p_load = &__sdram_from_data_flash$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_DATA_FLASH, .destination_type = INIT_MEM_SDRAM}}, + {.p_base = &__sdram_from_flash$$Base, .p_limit = &__sdram_from_flash$$Limit, .p_load = &__sdram_from_flash$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_FLASH, .destination_type = INIT_MEM_SDRAM}}, + {.p_base = &__ospi0_cs0_from_ospi0_cs1$$Base, .p_limit = &__ospi0_cs0_from_ospi0_cs1$$Limit, .p_load = &__ospi0_cs0_from_ospi0_cs1$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_OSPI0_CS1, .destination_type = INIT_MEM_OSPI0_CS0}}, + {.p_base = &__ospi0_cs0_from_ospi1_cs1$$Base, .p_limit = &__ospi0_cs0_from_ospi1_cs1$$Limit, .p_load = &__ospi0_cs0_from_ospi1_cs1$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_OSPI1_CS1, .destination_type = INIT_MEM_OSPI0_CS0}}, + {.p_base = &__ospi0_cs0_from_data_flash$$Base, .p_limit = &__ospi0_cs0_from_data_flash$$Limit, .p_load = &__ospi0_cs0_from_data_flash$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_DATA_FLASH, .destination_type = INIT_MEM_OSPI0_CS0}}, + {.p_base = &__ospi0_cs0_from_flash$$Base, .p_limit = &__ospi0_cs0_from_flash$$Limit, .p_load = &__ospi0_cs0_from_flash$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_FLASH, .destination_type = INIT_MEM_OSPI0_CS0}}, + {.p_base = &__ospi1_cs0_from_ospi0_cs1$$Base, .p_limit = &__ospi1_cs0_from_ospi0_cs1$$Limit, .p_load = &__ospi1_cs0_from_ospi0_cs1$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_OSPI0_CS1, .destination_type = INIT_MEM_OSPI1_CS0}}, + {.p_base = &__ospi1_cs0_from_ospi1_cs1$$Base, .p_limit = &__ospi1_cs0_from_ospi1_cs1$$Limit, .p_load = &__ospi1_cs0_from_ospi1_cs1$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_OSPI1_CS1, .destination_type = INIT_MEM_OSPI1_CS0}}, + {.p_base = &__ospi1_cs0_from_data_flash$$Base, .p_limit = &__ospi1_cs0_from_data_flash$$Limit, .p_load = &__ospi1_cs0_from_data_flash$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_DATA_FLASH, .destination_type = INIT_MEM_OSPI1_CS0}}, + {.p_base = &__ospi1_cs0_from_flash$$Base, .p_limit = &__ospi1_cs0_from_flash$$Limit, .p_load = &__ospi1_cs0_from_flash$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_FLASH, .destination_type = INIT_MEM_OSPI1_CS0}}, + {.p_base = &__ctcm_from_ospi0_cs1$$Base, .p_limit = &__ctcm_from_ospi0_cs1$$Limit, .p_load = &__ctcm_from_ospi0_cs1$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_OSPI0_CS1, .destination_type = INIT_MEM_CTCM}}, + {.p_base = &__ctcm_from_ospi1_cs1$$Base, .p_limit = &__ctcm_from_ospi1_cs1$$Limit, .p_load = &__ctcm_from_ospi1_cs1$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_OSPI1_CS1, .destination_type = INIT_MEM_CTCM}}, + {.p_base = &__ctcm_from_data_flash$$Base, .p_limit = &__ctcm_from_data_flash$$Limit, .p_load = &__ctcm_from_data_flash$$Load,.type={.copy_64 = 0, .external = 0, .source_type = INIT_MEM_DATA_FLASH, .destination_type = INIT_MEM_CTCM}}, + {.p_base = &__ctcm_from_flash$$Base, .p_limit = &__ctcm_from_flash$$Limit, .p_load = &__ctcm_from_flash$$Load,.type={.copy_64 = 0, .external = 0, .source_type = INIT_MEM_FLASH, .destination_type = INIT_MEM_CTCM}}, + {.p_base = &__stcm_from_ospi0_cs1$$Base, .p_limit = &__stcm_from_ospi0_cs1$$Limit, .p_load = &__stcm_from_ospi0_cs1$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_OSPI0_CS1, .destination_type = INIT_MEM_STCM}}, + {.p_base = &__stcm_from_ospi1_cs1$$Base, .p_limit = &__stcm_from_ospi1_cs1$$Limit, .p_load = &__stcm_from_ospi1_cs1$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_OSPI1_CS1, .destination_type = INIT_MEM_STCM}}, + {.p_base = &__stcm_from_data_flash$$Base, .p_limit = &__stcm_from_data_flash$$Limit, .p_load = &__stcm_from_data_flash$$Load,.type={.copy_64 = 0, .external = 0, .source_type = INIT_MEM_DATA_FLASH, .destination_type = INIT_MEM_STCM}}, + {.p_base = &__stcm_from_flash$$Base, .p_limit = &__stcm_from_flash$$Limit, .p_load = &__stcm_from_flash$$Load,.type={.copy_64 = 0, .external = 0, .source_type = INIT_MEM_FLASH, .destination_type = INIT_MEM_STCM}}, + {.p_base = &__ram_from_ospi0_cs1$$Base, .p_limit = &__ram_from_ospi0_cs1$$Limit, .p_load = &__ram_from_ospi0_cs1$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_OSPI0_CS1, .destination_type = INIT_MEM_RAM}}, + {.p_base = &__ram_from_ospi1_cs1$$Base, .p_limit = &__ram_from_ospi1_cs1$$Limit, .p_load = &__ram_from_ospi1_cs1$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_OSPI1_CS1, .destination_type = INIT_MEM_RAM}}, + {.p_base = &__ram_from_data_flash$$Base, .p_limit = &__ram_from_data_flash$$Limit, .p_load = &__ram_from_data_flash$$Load,.type={.copy_64 = 0, .external = 0, .source_type = INIT_MEM_DATA_FLASH, .destination_type = INIT_MEM_RAM}}, + {.p_base = &__ram_from_flash$$Base, .p_limit = &__ram_from_flash$$Limit, .p_load = &__ram_from_flash$$Load,.type={.copy_64 = 0, .external = 0, .source_type = INIT_MEM_FLASH, .destination_type = INIT_MEM_RAM}} +}; +/* nocache regions */ +extern uint32_t __sdram_noinit_nocache$$Base; +extern uint32_t __sdram_noinit_nocache$$Limit; +extern uint32_t __sdram_zero_nocache$$Base; +extern uint32_t __sdram_zero_nocache$$Limit; +extern uint32_t __ospi0_cs0_noinit_nocache$$Base; +extern uint32_t __ospi0_cs0_noinit_nocache$$Limit; +extern uint32_t __ospi0_cs0_zero_nocache$$Base; +extern uint32_t __ospi0_cs0_zero_nocache$$Limit; +extern uint32_t __ospi1_cs0_noinit_nocache$$Base; +extern uint32_t __ospi1_cs0_noinit_nocache$$Limit; +extern uint32_t __ospi1_cs0_zero_nocache$$Base; +extern uint32_t __ospi1_cs0_zero_nocache$$Limit; +extern uint32_t __ram_noinit_nocache$$Base; +extern uint32_t __ram_noinit_nocache$$Limit; +extern uint32_t __ram_zero_nocache$$Base; +extern uint32_t __ram_zero_nocache$$Limit; +static const bsp_mpu_nocache_info_t nocache_list[] = +{ + {.p_base = &__sdram_noinit_nocache$$Base, .p_limit = &__sdram_zero_nocache$$Limit}, + {.p_base = &__ospi0_cs0_noinit_nocache$$Base, .p_limit = &__ospi0_cs0_zero_nocache$$Limit}, + {.p_base = &__ospi1_cs0_noinit_nocache$$Base, .p_limit = &__ospi1_cs0_zero_nocache$$Limit}, + {.p_base = &__ram_noinit_nocache$$Base, .p_limit = &__ram_zero_nocache$$Limit}, +}; + +/* initialization data structure */ +const bsp_init_info_t g_init_info = +{ + .zero_count = sizeof(zero_list) / sizeof(zero_list[0]), + .p_zero_list = zero_list, + .copy_count = sizeof(copy_list) / sizeof(copy_list[0]), + .p_copy_list = copy_list, + .nocache_count = sizeof(nocache_list) / sizeof(nocache_list[0]), + .p_nocache_list = nocache_list +}; + +#endif // BSP_LINKER_C + +/* UNCRUSTIFY-ON */ diff --git a/bsp/renesas/ra8p1-titan-board/m33/board/ra8_it.c b/bsp/renesas/ra8p1-titan-board/m33/board/ra8_it.c new file mode 100644 index 00000000000..e574ed7c3bd --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/board/ra8_it.c @@ -0,0 +1,3 @@ +#include +#include "hal_data.h" + diff --git a/bsp/renesas/ra8p1-titan-board/m33/buildinfo.json b/bsp/renesas/ra8p1-titan-board/m33/buildinfo.json new file mode 100644 index 00000000000..6c7ca19260a --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/buildinfo.json @@ -0,0 +1,33 @@ +{ + "definedMacros": [ + "_RA_CORE=CPU1", + "_RA_ORDINAL=2", + "_RENESAS_RA_" + ], + "sourcePaths": [ + "ra", + "ra_gen", + "src" + ], + "excludedFilePaths": [], + "includePaths": [ + "ra/arm/CMSIS_6/CMSIS/Core/Include", + "ra/fsp/inc", + "ra/fsp/inc/api", + "ra/fsp/inc/instances", + "ra_cfg/fsp_cfg", + "ra_cfg/fsp_cfg/bsp", + "ra_gen", + "src" + ], + "libraryPaths": [], + "libraryNames": [], + "objectFiles": [], + "linkerScript": "script/fsp.ld", + "targetDeviceName": "R7KA8P1KFLCAC", + "entrySymbol": "Reset_Handler", + "isPreBuildContentGenEnabled": true, + "isPostBuildContentGenEnabled": true, + "isTargetDeviceSupportsTrustZone": true, + "buildOptionsMap": {} +} diff --git a/bsp/renesas/ra8p1-titan-board/m33/configuration.xml b/bsp/renesas/ra8p1-titan-board/m33/configuration.xml new file mode 100644 index 00000000000..30e9b5d62db --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/configuration.xml @@ -0,0 +1,801 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Board support package for R7KA8P1KFLCAC + Renesas.RA_mcu_ra8p1.6.2.0.pack + + + Board support package for RA8P1 + Renesas.RA_mcu_ra8p1.6.2.0.pack + + + Board support package for RA8P1 - FSP Data + Renesas.RA_mcu_ra8p1.6.2.0.pack + + + Board support package for RA8P1 - Events + Renesas.RA_mcu_ra8p1.6.2.0.pack + + + Board support package for RA8P1 - Linker + Renesas.RA_mcu_ra8p1.6.2.0.pack + + + Arm CMSIS Version 6 - Core (M) + Arm.CMSIS6.6.1.0+fsp.6.2.0.pack + + + Board Support Package Common Files + Renesas.RA.6.2.0.pack + + + I/O Port + Renesas.RA.6.2.0.pack + + + SCI UART + Renesas.RA.6.2.0.pack + + + Custom Board Support Files + Renesas.RA_board_custom.6.2.0.pack + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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### uVision Project, (C) Keil Software
+ + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp; *.cc; *.cxx + 0 + + + 0 + 0 + + + M33_Debug_CPU1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 1 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) + + + 0 + JL2CM3 + -O111 -N00("ARM CoreSight SW-DP") -S2 -ZTIFSpeedSel5000 -A0 -C-1 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD22000000 -FC7800 -FN3 -FF0RA8P1_1M.FLM -FS02000000 -FL0100000 -FP0($$Device:R7KA8P1KF$Flash\RA8P1_1M.FLM) -FF1RA8P1_CONF.FLM -FS102C9F040 -FL17C0 -FP1($$Device:R7KA8P1KF$Flash\RA8P1_CONF.FLM) -FF2RA8P1_OTP.FLM -FS202E07600 -FL210334 -FP2($$Device:R7KA8P1KF$Flash\RA8P1_OTP.FLM) + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 ) -FN3 -FC7800 -FD22000000 -FF0RA8P1_1M -FF1RA8P1_CONF -FF2RA8P1_OTP -FL0100000 -FL17C0 -FL210334 -FS02000000 -FS102C9F040 -FS202E07600 -FP0($$Device:R7KA8P1KF$Flash\RA8P1_1M.FLM) -FP1($$Device:R7KA8P1KF$Flash\RA8P1_CONF.FLM) -FP2($$Device:R7KA8P1KF$Flash\RA8P1_OTP.FLM) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + :Renesas RA Smart Configurator:Common Sources + 1 + 0 + 0 + 0 + + 2 + 1 + 1 + 0 + 0 + 0 + .\src\hal_entry.c + hal_entry.c + 0 + 0 + + + + ::Flex Software + 0 + 0 + 0 + 1 + + + M33_Download_CPU0 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 1 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 0 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) + + + 0 + JL2CM3 + -O111 -N00("ARM CoreSight SW-DP") -S2 -ZTIFSpeedSel5000 -A0 -C-1 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD22000000 -FC7800 -FN3 -FF0RA8P1_1M.FLM -FS02000000 -FL0100000 -FP0($$Device:R7KA8P1KF$Flash\RA8P1_1M.FLM) -FF1RA8P1_CONF.FLM -FS102C9F040 -FL17C0 -FP1($$Device:R7KA8P1KF$Flash\RA8P1_CONF.FLM) -FF2RA8P1_OTP.FLM -FS202E07600 -FL210334 -FP2($$Device:R7KA8P1KF$Flash\RA8P1_OTP.FLM) + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 ) -FN3 -FC7800 -FD22000000 -FF0RA8P1_1M -FF1RA8P1_CONF -FF2RA8P1_OTP -FL0100000 -FL17C0 -FL210334 -FS02000000 -FS102C9F040 -FS202E07600 -FP0($$Device:R7KA8P1KF$Flash\RA8P1_1M.FLM) -FP1($$Device:R7KA8P1KF$Flash\RA8P1_CONF.FLM) -FP2($$Device:R7KA8P1KF$Flash\RA8P1_OTP.FLM) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + diff --git a/bsp/renesas/ra8p1-titan-board/m33/project.uvprojx b/bsp/renesas/ra8p1-titan-board/m33/project.uvprojx new file mode 100644 index 00000000000..3d7f86fb79e --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/project.uvprojx @@ -0,0 +1,1683 @@ + + + 2.1 +
### uVision Project, (C) Keil Software
+ + + M33_Debug_CPU1 + 0x4 + ARM-ADS + 6190000::V6.19::ARMCLANG + 1 + + + R7KA8P1KF:CPU1 + Renesas + Renesas.RA_DFP.6.1.0 + https://www2.renesas.eu/Keil_MDK_Packs/ + CPUTYPE("Cortex-M33") DSP TZ FPU3(SFPU) CLOCK(12000000) ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD22000000 -FC7800 -FN3 -FF0RA8P1_1M -FS02000000 -FL0100000 -FF1RA8P1_CONF -FS102C9F040 -FL17C0 -FF2RA8P1_OTP -FS202E07600 -FL210334 -FP0($$Device:R7KA8P1KF$Flash\RA8P1_1M.FLM) -FP1($$Device:R7KA8P1KF$Flash\RA8P1_CONF.FLM) -FP2($$Device:R7KA8P1KF$Flash\RA8P1_OTP.FLM)) + 0 + + + + + + + + + + + $$Device:R7KA8P1KF$SVD\R7KA8P1AD.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 2 + 0 + + + 1 + 0 + cmd /c ""$Prasc_launcher.bat" "$Prasc_version.txt" -nosplash --launcher.suppressErrors --gensmartbundle --compiler ARMv6 --devicefamily ra "$Pconfiguration.xml" "$L%L" 2> "$PObjects\rasc_stderr.out"" + + 0 + 0 + 2 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMV8M.DLL + -MPU + DCM.DLL + -pCM4 + SARMV8M.DLL + -MPU + TCM.DLL + -pCM33 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 0 + 1 + 0 + 0 + 1 + -1 + + 1 + BIN\UL2V8M.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M33" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 3 + 6 + 0 + 0 + 0 + 0 + 0 + + + __CLK_TCK=RT_TICK_PER_SECOND, _RA_CORE=CPU1, __STDC_LIMIT_MACROS, _RA_ORDINAL=2, RT_USING_ARMLIBC, __RTTHREAD__, _RENESAS_RA_, RT_USING_LIBC + + ra_cfg\fsp_cfg;..\..\..\..\components\drivers\smp_call;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\posix\ipc;..\..\..\..\components\drivers\phy;..\..\..\..\components\drivers\include;..\..\..\..\libcpu\arm\common;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\..\components\libc\posix\io\epoll;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;ra\fsp\inc\api;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\compilers\common\extension;..\..\..\..\components\finsh;ra_cfg\fsp_cfg\bsp;..\..\..\..\components\net\utest;ra\fsp\inc;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\posix\io\poll;..\..\..\..\include;..\..\libraries\HAL_Drivers\drivers;..\..\..\..\components\libc\posix\io\eventfd;..\..\libraries\HAL_Drivers\drivers\config;..\..\..\..\components\libc\compilers\common\include;.;board;ra_gen;..\..\libraries\HAL_Drivers;ra\arm\CMSIS_6\CMSIS\Core\Include;..\..\..\..\libcpu\arm\cortex-m33;ra\fsp\inc\instances + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + . + + + + 0 + 0 + 0 + 0 + 0 + 0 + + + + .\script\fsp.scat + + + --entry=Reset_Handler --no_startup + + 6319,6314 + + + + + + Applications + + + hal_entry.c + 1 + src\hal_entry.c + + + + + CPU + + + atomic_arm.c + 1 + ..\..\..\..\libcpu\arm\common\atomic_arm.c + + + + + div0.c + 1 + ..\..\..\..\libcpu\arm\common\div0.c + + + + + showmem.c + 1 + ..\..\..\..\libcpu\arm\common\showmem.c + + + + + context_rvds.S + 2 + ..\..\..\..\libcpu\arm\cortex-m33\context_rvds.S + + + + + cpuport.c + 1 + ..\..\..\..\libcpu\arm\cortex-m33\cpuport.c + + + + + syscall_rvds.S + 2 + ..\..\..\..\libcpu\arm\cortex-m33\syscall_rvds.S + + + + + trustzone.c + 1 + ..\..\..\..\libcpu\arm\cortex-m33\trustzone.c + + + + + DeviceDrivers + + + device.c + 1 + ..\..\..\..\components\drivers\core\device.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + completion_comm.c + 1 + ..\..\..\..\components\drivers\ipc\completion_comm.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + completion_up.c + 1 + ..\..\..\..\components\drivers\ipc\completion_up.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + dataqueue.c + 1 + ..\..\..\..\components\drivers\ipc\dataqueue.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + pipe.c + 1 + ..\..\..\..\components\drivers\ipc\pipe.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + ringblk_buf.c + 1 + ..\..\..\..\components\drivers\ipc\ringblk_buf.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + ringbuffer.c + 1 + ..\..\..\..\components\drivers\ipc\ringbuffer.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + waitqueue.c + 1 + ..\..\..\..\components\drivers\ipc\waitqueue.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + workqueue.c + 1 + ..\..\..\..\components\drivers\ipc\workqueue.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + dev_pin.c + 1 + ..\..\..\..\components\drivers\pin\dev_pin.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + dev_serial_v2.c + 1 + ..\..\..\..\components\drivers\serial\dev_serial_v2.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + Drivers + + + drv_gpio.c + 1 + ..\..\libraries\HAL_Drivers\drivers\drv_gpio.c + + + + + drv_usart_v2.c + 1 + ..\..\libraries\HAL_Drivers\drivers\drv_usart_v2.c + + + + + drv_common.c + 1 + ..\..\libraries\HAL_Drivers\drv_common.c + + + + + ra8_it.c + 1 + board\ra8_it.c + + + + + Finsh + + + shell.c + 1 + ..\..\..\..\components\finsh\shell.c + + + + + msh.c + 1 + ..\..\..\..\components\finsh\msh.c + + + + + msh_parse.c + 1 + ..\..\..\..\components\finsh\msh_parse.c + + + + + cmd.c + 1 + ..\..\..\..\components\finsh\cmd.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\..\src\clock.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + components.c + 1 + ..\..\..\..\src\components.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + cpu_up.c + 1 + ..\..\..\..\src\cpu_up.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + defunct.c + 1 + ..\..\..\..\src\defunct.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + idle.c + 1 + ..\..\..\..\src\idle.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + ipc.c + 1 + ..\..\..\..\src\ipc.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + irq.c + 1 + ..\..\..\..\src\irq.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + kservice.c + 1 + ..\..\..\..\src\kservice.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + memheap.c + 1 + ..\..\..\..\src\memheap.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + mempool.c + 1 + ..\..\..\..\src\mempool.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + object.c + 1 + ..\..\..\..\src\object.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + scheduler_comm.c + 1 + ..\..\..\..\src\scheduler_comm.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + scheduler_up.c + 1 + ..\..\..\..\src\scheduler_up.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + thread.c + 1 + ..\..\..\..\src\thread.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + timer.c + 1 + ..\..\..\..\src\timer.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + Libc + + + syscall_mem.c + 1 + ..\..\..\..\components\libc\compilers\armlibc\syscall_mem.c + + + + + syscalls.c + 1 + ..\..\..\..\components\libc\compilers\armlibc\syscalls.c + + + + + cctype.c + 1 + ..\..\..\..\components\libc\compilers\common\cctype.c + + + + + cstdlib.c + 1 + ..\..\..\..\components\libc\compilers\common\cstdlib.c + + + + + cstring.c + 1 + ..\..\..\..\components\libc\compilers\common\cstring.c + + + + + ctime.c + 1 + ..\..\..\..\components\libc\compilers\common\ctime.c + + + + + cunistd.c + 1 + ..\..\..\..\components\libc\compilers\common\cunistd.c + + + + + cwchar.c + 1 + ..\..\..\..\components\libc\compilers\common\cwchar.c + + + + + kerrno.c + 1 + ..\..\..\..\src\klibc\kerrno.c + + + + + kstdio.c + 1 + ..\..\..\..\src\klibc\kstdio.c + + + + + kstring.c + 1 + ..\..\..\..\src\klibc\kstring.c + + + + + rt_vsnprintf_tiny.c + 1 + ..\..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + + + rt_vsscanf.c + 1 + ..\..\..\..\src\klibc\rt_vsscanf.c + + + + + RA + + + bsp_clocks.c + 1 + ra\fsp\src\bsp\mcu\all\bsp_clocks.c + + + + + bsp_common.c + 1 + ra\fsp\src\bsp\mcu\all\bsp_common.c + + + + + bsp_delay.c + 1 + ra\fsp\src\bsp\mcu\all\bsp_delay.c + + + + + bsp_group_irq.c + 1 + ra\fsp\src\bsp\mcu\all\bsp_group_irq.c + + + + + bsp_guard.c + 1 + ra\fsp\src\bsp\mcu\all\bsp_guard.c + + + + + bsp_io.c + 1 + ra\fsp\src\bsp\mcu\all\bsp_io.c + + + + + bsp_ipc.c + 1 + ra\fsp\src\bsp\mcu\all\bsp_ipc.c + + + + + bsp_irq.c + 1 + ra\fsp\src\bsp\mcu\all\bsp_irq.c + + + + + bsp_macl.c + 1 + ra\fsp\src\bsp\mcu\all\bsp_macl.c + + + + + bsp_ospi_b.c + 1 + ra\fsp\src\bsp\mcu\all\bsp_ospi_b.c + + + + + bsp_register_protection.c + 1 + ra\fsp\src\bsp\mcu\all\bsp_register_protection.c + + + + + bsp_sbrk.c + 1 + ra\fsp\src\bsp\mcu\all\bsp_sbrk.c + + + + + bsp_sdram.c + 1 + ra\fsp\src\bsp\mcu\all\bsp_sdram.c + + + + + bsp_security.c + 1 + ra\fsp\src\bsp\mcu\all\bsp_security.c + + + + + bsp_linker.c + 1 + ra\fsp\src\bsp\mcu\ra8p1\bsp_linker.c + + + + + system.c + 1 + ra\fsp\src\bsp\cmsis\Device\RENESAS\Source\system.c + + + + + startup.c + 1 + ra\fsp\src\bsp\cmsis\Device\RENESAS\Source\startup.c + + + + + r_ioport.c + 1 + ra\fsp\src\r_ioport\r_ioport.c + + + + + r_sci_b_uart.c + 1 + ra\fsp\src\r_sci_b_uart\r_sci_b_uart.c + + + + + RA_gen + + + common_data.c + 1 + ra_gen\common_data.c + + + + + hal_data.c + 1 + ra_gen\hal_data.c + + + + + main.c + 1 + ra_gen\main.c + + + + + pin_data.c + 1 + ra_gen\pin_data.c + + + + + vector_data.c + 1 + ra_gen\vector_data.c + + + + + + + M33_Download_CPU0 + 0x4 + ARM-ADS + 6190000::V6.19::ARMCLANG + 1 + + + R7KA8P1KF:CPU0 + Renesas + Renesas.RA_DFP.6.1.0 + https://www2.renesas.eu/Keil_MDK_Packs/ + CPUTYPE("Cortex-M85") DSP TZ MVE(FP) FPU3(DFPU) PACBTI CLOCK(12000000) ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD22000000 -FC7800 -FN3 -FF0RA8P1_1M -FS02000000 -FL0100000 -FF1RA8P1_CONF -FS102C9F040 -FL17C0 -FF2RA8P1_OTP -FS202E07600 -FL210334 -FP0($$Device:R7KA8P1KF$Flash\RA8P1_1M.FLM) -FP1($$Device:R7KA8P1KF$Flash\RA8P1_CONF.FLM) -FP2($$Device:R7KA8P1KF$Flash\RA8P1_OTP.FLM)) + 0 + + + + + + + + + + + $$Device:R7KA8P1KF$SVD\R7KA8P1AD.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 2 + 0 + + + 1 + 0 + cmd /c ""$Prasc_launcher.bat" "$Prasc_version.txt" -nosplash --launcher.suppressErrors --gensmartbundle --compiler ARMv6 --devicefamily ra "$Pconfiguration.xml" "$L%L" 2> "$PObjects\rasc_stderr.out"" + + 0 + 0 + 2 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMV8M.DLL + -MPU + DCM.DLL + -pCM4 + SARMV8M.DLL + -MPU -MVE -PACBTI + TCM.DLL + -pCM85 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 0 + 1 + 4102 + + 1 + BIN\UL2V8M.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M85" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 3 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 3 + 6 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + + + + + + + + + 0 + 0 + 0 + 0 + 0 + 0 + + + + .\script\fsp.scat + + + --entry=Reset_Handler --no_startup + + 6319,6314 + + + + + + + + + + + + + + + + + + + diff --git a/bsp/renesas/ra8p1-titan-board/m33/ra/SConscript b/bsp/renesas/ra8p1-titan-board/m33/ra/SConscript new file mode 100644 index 00000000000..240631c9cbb --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/ra/SConscript @@ -0,0 +1,29 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * +from gcc import * + +cwd = GetCurrentDir() +src = [] +group = [] +CPPPATH = [] +LINKFLAGS = '' + +if rtconfig.PLATFORM == 'armclang': + LINKFLAGS = ' --entry=Reset_Handler --no_startup' + +if rtconfig.PLATFORM in ['iccarm'] + GetGCCLikePLATFORM(): + src += Glob('./fsp/src/bsp/mcu/all/*.c') + src += Glob('./fsp/src/bsp/mcu/ra8p1/*.c') + src += Glob('./fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c') + src += Glob('./fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c') + src += Glob('./fsp/src/r_ioport/*.c') + src += Glob('./fsp/src/r_sci_b_uart/*.c') + CPPPATH = [ cwd + '/arm/CMSIS_6/CMSIS/Core/Include', + cwd + '/fsp/inc', + cwd + '/fsp/inc/api', + cwd + '/fsp/inc/instances', + ] + +group = DefineGroup('RA', src, depend = [''], CPPPATH = CPPPATH, LINKFLAGS = LINKFLAGS) +Return('group') diff --git a/bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_armclang_a.h b/bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_armclang_a.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_armclang_a.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_armclang_a.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_clang_a.h b/bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_clang_a.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_clang_a.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_clang_a.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_cp15.h b/bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_cp15.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_cp15.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_cp15.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_gcc_a.h b/bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_gcc_a.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_gcc_a.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_gcc_a.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_iccarm_a.h b/bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_iccarm_a.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_iccarm_a.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_iccarm_a.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/irq_ctrl.h b/bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/irq_ctrl.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/irq_ctrl.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/irq_ctrl.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_armclang.h b/bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_armclang.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_armclang.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_armclang.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_clang.h b/bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_clang.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_clang.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_clang.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_compiler.h b/bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_compiler.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_compiler.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_compiler.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_gcc.h b/bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_gcc.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_gcc.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_gcc.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_version.h b/bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_version.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_version.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_version.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/core_ca.h b/bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/core_ca.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/core_ca.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/core_ca.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0.h b/bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0plus.h b/bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0plus.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0plus.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0plus.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm1.h b/bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm1.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm1.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm1.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm23.h b/bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm23.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm23.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm23.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm3.h b/bsp/renesas/ra8p1-titan-board/m33/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm3.h similarity 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a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_clocks.c b/bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_clocks.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_clocks.c rename to bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_clocks.c diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_clocks.h b/bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_clocks.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_clocks.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_clocks.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_common.c b/bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_common.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_common.c rename to bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_common.c diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_common.h b/bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_common.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_common.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_common.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h b/bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_delay.c b/bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_delay.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_delay.c rename to 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from bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_guard.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_guard.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_io.c b/bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_io.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_io.c rename to bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_io.c diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_io.h b/bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_io.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_io.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_io.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_ipc.c b/bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_ipc.c similarity index 100% rename from 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from bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_ospi_b.c rename to bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_ospi_b.c diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_ospi_b.h b/bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_ospi_b.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_ospi_b.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_ospi_b.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c b/bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c rename to bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h b/bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c b/bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c rename to bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_sdram.c b/bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_sdram.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_sdram.c rename to bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_sdram.c diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_sdram.h b/bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_sdram.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_sdram.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_sdram.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_security.c b/bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_security.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_security.c rename to bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_security.c diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_security.h b/bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_security.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_security.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_security.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_tfu.h b/bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_tfu.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/all/bsp_tfu.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/all/bsp_tfu.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/ra8p1/bsp_elc.h b/bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/ra8p1/bsp_elc.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/ra8p1/bsp_elc.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/ra8p1/bsp_elc.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/ra8p1/bsp_feature.h b/bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/ra8p1/bsp_feature.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/ra8p1/bsp_feature.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/ra8p1/bsp_feature.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/ra8p1/bsp_linker.c b/bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/ra8p1/bsp_linker.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/ra8p1/bsp_linker.c rename to bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/ra8p1/bsp_linker.c diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/ra8p1/bsp_mcu_info.h b/bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/ra8p1/bsp_mcu_info.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/ra8p1/bsp_mcu_info.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/ra8p1/bsp_mcu_info.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/ra8p1/bsp_override.h b/bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/ra8p1/bsp_override.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/ra8p1/bsp_override.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/ra8p1/bsp_override.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/ra8p1/bsp_peripheral.h b/bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/ra8p1/bsp_peripheral.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/ra8p1/bsp_peripheral.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/ra8p1/bsp_peripheral.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/ra8p1/r_adc_device_types.h b/bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/ra8p1/r_adc_device_types.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/ra8p1/r_adc_device_types.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/ra8p1/r_adc_device_types.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/ra8p1/r_lpm_device_types.h b/bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/ra8p1/r_lpm_device_types.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/bsp/mcu/ra8p1/r_lpm_device_types.h rename to bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/bsp/mcu/ra8p1/r_lpm_device_types.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_ioport/r_ioport.c b/bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/r_ioport/r_ioport.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_ioport/r_ioport.c rename to bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/r_ioport/r_ioport.c diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_sci_b_uart/r_sci_b_uart.c b/bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/r_sci_b_uart/r_sci_b_uart.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_sci_b_uart/r_sci_b_uart.c rename to bsp/renesas/ra8p1-titan-board/m33/ra/fsp/src/r_sci_b_uart/r_sci_b_uart.c diff --git a/bsp/renesas/ra8p1-titan-board/ra_cfg/SConscript b/bsp/renesas/ra8p1-titan-board/m33/ra_cfg/SConscript similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_cfg/SConscript rename to bsp/renesas/ra8p1-titan-board/m33/ra_cfg/SConscript diff --git a/bsp/renesas/ra8p1-titan-board/m33/ra_cfg/fsp_cfg/bsp/board_cfg.h b/bsp/renesas/ra8p1-titan-board/m33/ra_cfg/fsp_cfg/bsp/board_cfg.h new file mode 100644 index 00000000000..2e11f5aca21 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/ra_cfg/fsp_cfg/bsp/board_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef BOARD_CFG_H_ +#define BOARD_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + +void bsp_init(void *p_args); + +#ifdef __cplusplus + } + #endif +#endif /* BOARD_CFG_H_ */ diff --git a/bsp/renesas/ra8p1-titan-board/m33/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/bsp/renesas/ra8p1-titan-board/m33/ra_cfg/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 00000000000..5c17eb43690 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,63 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + +#include "bsp_clock_cfg.h" +#include "bsp_mcu_family_cfg.h" +#include "bsp_mcu_ofs_cfg.h" +#include "board_cfg.h" +#include "vector_data.h" +#define RA_NOT_DEFINED 0 +#ifndef BSP_CFG_RTOS +#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (2) + #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (1) + #else +#define BSP_CFG_RTOS (0) +#endif +#endif +#ifndef BSP_CFG_RTC_USED +#define BSP_CFG_RTC_USED (RA_NOT_DEFINED) +#endif +#undef RA_NOT_DEFINED +#if defined(_RA_BOOT_IMAGE) + #define BSP_CFG_BOOT_IMAGE (1) + #endif +#define BSP_CFG_MCU_VCC_MV (3300) +#define BSP_CFG_STACK_MAIN_BYTES (0x20000) +#define BSP_CFG_HEAP_BYTES (0x4000) +#define BSP_CFG_PARAM_CHECKING_ENABLE (1) +#define BSP_CFG_ASSERT (0) + +#define BSP_CFG_PFS_PROTECT ((1)) + +#define BSP_CFG_C_RUNTIME_INIT ((1)) +#define BSP_CFG_EARLY_INIT ((0)) + +#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED +#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) +#endif + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE +#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE +#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED +#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS +#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 +#endif + +#ifdef __cplusplus + } + #endif +#endif /* BSP_CFG_H_ */ diff --git a/bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/bsp/renesas/ra8p1-titan-board/m33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h rename to bsp/renesas/ra8p1-titan-board/m33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h diff --git a/bsp/renesas/ra8p1-titan-board/m33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/bsp/renesas/ra8p1-titan-board/m33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 00000000000..885b35c74a7 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,12 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7KA8P1KFLCAC +#define BSP_MCU_FEATURE_SET ('K') +#define BSP_ROM_SIZE_BYTES (1048576) +#define BSP_RAM_SIZE_BYTES (1916928) +#define BSP_DATA_FLASH_SIZE_BYTES (0) +#define BSP_NUMBER_OF_CORES (2) +#define BSP_PACKAGE_LFBGA +#define BSP_PACKAGE_PINS (289) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/bsp/renesas/ra8p1-titan-board/m33/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/bsp/renesas/ra8p1-titan-board/m33/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 00000000000..599de661a19 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,503 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ +#include "bsp_mcu_device_pn_cfg.h" +#include "bsp_mcu_device_cfg.h" +#include "../../../ra/fsp/src/bsp/mcu/ra8p1/bsp_override.h" +#include "../../../ra/fsp/src/bsp/mcu/ra8p1/bsp_mcu_info.h" +#include "../../../ra/fsp/src/bsp/mcu/ra8p1/r_adc_device_types.h" +#include "bsp_clock_cfg.h" +#define BSP_MCU_GROUP_RA8P1 (1) +#define BSP_MCU_GROUP_RA8_GEN2 (1) + +#define CPU0 (0) +#define CPU1 (1) + +#if (_RA_CORE == CPU1) + #define BSP_CFG_CPU_CORE (1) + #define BSP_CFG_SKIP_INIT (1) + #define BSP_SECONDARY_CORE_BUILD (1) + #else +#define BSP_CFG_CPU_CORE (0) +#endif + +#define BSP_LOCO_HZ (32768) +#define BSP_MOCO_HZ (8000000) +#define BSP_SUB_CLOCK_HZ (0) +#if BSP_CFG_HOCO_FREQUENCY == 0 +#define BSP_HOCO_HZ (16000000) +#elif BSP_CFG_HOCO_FREQUENCY == 1 + #define BSP_HOCO_HZ (18000000) + #elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (20000000) + #elif BSP_CFG_HOCO_FREQUENCY == 4 + #define BSP_HOCO_HZ (32000000) + #elif BSP_CFG_HOCO_FREQUENCY == 7 + #define BSP_HOCO_HZ (48000000) + #else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" + #endif + +#define BSP_CFG_FLL_ENABLE (0) + +#define BSP_CFG_CLOCK_SETTLING_DELAY_ENABLE (1) +#define BSP_CFG_SLEEP_MODE_DELAY_ENABLE (1) +#define BSP_CFG_MSTP_CHANGE_DELAY_ENABLE (1) +#define BSP_CFG_RTOS_SLEEP_MODE_DELAY_ENABLE (1) +#define BSP_CFG_CLOCK_SETTLING_DELAY_US (30) + +#if defined(BSP_PACKAGE_HLQFP) + #define BSP_MAX_CLOCK_CHANGE_THRESHOLD (300000000U) + #else +#define BSP_MAX_CLOCK_CHANGE_THRESHOLD (500000000U) +#endif + +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) +#define BSP_CFG_INLINE_IRQ_FUNCTIONS (1) + +#if defined(_RA_TZ_SECURE) + #define BSP_TZ_SECURE_BUILD (1) + #define BSP_TZ_NONSECURE_BUILD (0) + #elif defined(_RA_TZ_NONSECURE) + #define BSP_TZ_SECURE_BUILD (0) + #define BSP_TZ_NONSECURE_BUILD (1) + #else +#define BSP_TZ_SECURE_BUILD (0) +#define BSP_TZ_NONSECURE_BUILD (0) +#endif + +/* TrustZone Settings */ +#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) +#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) +#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) + +/* CMSIS TrustZone Settings */ +#define SCB_CSR_AIRCR_INIT (1) +#define SCB_AIRCR_BFHFNMINS_VAL (0) +#define SCB_AIRCR_SYSRESETREQS_VAL (1) +#define SCB_AIRCR_PRIS_VAL (0) +#define TZ_FPU_NS_USAGE (1) +#ifndef SCB_NSACR_CP10_11_VAL +#define SCB_NSACR_CP10_11_VAL (3U) +#endif + +#ifndef FPU_FPCCR_TS_VAL +#define FPU_FPCCR_TS_VAL (1U) +#endif +#define FPU_FPCCR_CLRONRETS_VAL (1) + +#ifndef FPU_FPCCR_CLRONRET_VAL +#define FPU_FPCCR_CLRONRET_VAL (1) +#endif + +/* Type 1 Peripheral Security Attribution */ + +/* Peripheral Security Attribution Register (PSAR) Settings */ +#ifndef BSP_TZ_CFG_PSARB +#define BSP_TZ_CFG_PSARB (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4) /* I3C */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7) /* IIC2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* USBHS */ | \ + (1 << 16) /* OSPI0 */ | \ + (1 << 17) /* OSPI1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \ + (((1 > 0) ? 0U : 1U) << 26) /* SCI5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */) +#endif +#ifndef BSP_TZ_CFG_PSARC +#define BSP_TZ_CFG_PSARC (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7) /* SSIE1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* SDHI1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* GLCDC/MIPI-DSI/DRW */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* MIPI_CSI */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* CEU */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* PDM */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* CANFD1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* CANFD0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* ETHPHYCLK */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* ESWM */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* RSIP-E50D */) +#endif +#ifndef BSP_TZ_CFG_PSARD +#define BSP_TZ_CFG_PSARD (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4) /* AGT1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5) /* AGT0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6) /* PDG */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* PGI3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* PGI2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* PGI1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* PGI0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* DAC121 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC120 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 21) /* ADC_B */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* ACMPHS3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* ACMPHS2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* ACMPHS1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* ACMPHS0 */) +#endif +#ifndef BSP_TZ_CFG_PSARE +#define BSP_TZ_CFG_PSARE (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* WDT0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* IWDT */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* RTC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* ULPT1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* ULPT0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* GPT COMMON */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* GPT13 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* GPT12 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* GPT11 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 21) /* GPT10 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */) +#endif +#ifndef BSP_TZ_CFG_MSSAR +#define BSP_TZ_CFG_MSSAR (\ + (1U << 0) /* SRAM0 */ | \ + (1U << 1) /* SRAM1 */ | \ + (1U << 2) /* SRAM2 */ | \ + (1U << 3) /* SRAM3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* NPU */ | \ + (1U << 22) /* DTC0_DMAC0 */ | \ + (1U << 23) /* DTC1_DMAC1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* ELC */) +#endif + +/* Type 2 Peripheral Security Attribution */ + +/* Security attribution for RSTSRn registers. */ +#ifndef BSP_TZ_CFG_RSTSAR +#define BSP_TZ_CFG_RSTSAR (0x0000000FU) +#endif + +/* Security attribution for registers of LVD channels. */ +#ifndef BSP_TZ_CFG_LVDSAR +/* The LVD driver needs to access both channels. This means that the security attribution for both channels must be the same. */ +#if (RA_NOT_DEFINED > 0) || (RA_NOT_DEFINED > 0) +#define BSP_TZ_CFG_LVDSAR (0U) +#else +#define BSP_TZ_CFG_LVDSAR (3U) +#endif +#endif + +/* Security attribution for LPM registers. + * - OPCCR based on clock security. + * - Set remaining registers based on LPM security. + */ +#ifndef BSP_TZ_CFG_LPMSAR +#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? BSP_CFG_CLOCKS_SECURE == 0 : (\ + 0x002E0116U | \ + (BSP_CFG_CLOCKS_SECURE == 0))) +#endif +/* Deep Standby Interrupt Factor Security Attribution Register. */ +#ifndef BSP_TZ_CFG_DPFSAR +#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0U : 0xEF1FFFFFU) +#endif +/* Deep Standby Interrupt Factor Security Attribution Register 1. */ +#ifndef BSP_TZ_CFG_DPFSAR1 +#define BSP_TZ_CFG_DPFSAR1 ((RA_NOT_DEFINED > 0) ? 0U : 0x0000FFFFU) +#endif +/* RAM Standby Control Security Attribution Register. */ +#ifndef BSP_TZ_CFG_RSCSAR +#define BSP_TZ_CFG_RSCSAR ((RA_NOT_DEFINED > 0) ? 0U : 0x00037FFFU) +#endif +/* Power Gating Control Security Attribution Register */ +#ifndef BSP_TZ_CFG_PGCSAR +#define BSP_TZ_CFG_PGCSAR 0 +#endif + +/* Security attribution for CGC registers. */ +#ifndef BSP_TZ_CFG_CGFSAR +#if BSP_CFG_CLOCKS_SECURE +/* Protect all CGC registers from Non-secure write access. */ +#define BSP_TZ_CFG_CGFSAR (0U) +#else +/* Allow Secure and Non-secure write access. */ +#define BSP_TZ_CFG_CGFSAR (0x1F7F7FFDU) +#endif +#endif + +/* Security attribution for Battery Backup registers. */ +#ifndef BSP_TZ_CFG_BBFSAR +#if 0 +#define BSP_TZ_CFG_BBFSAR (0U) +#else +#define BSP_TZ_CFG_BBFSAR (0x7FU) +#endif +#endif + +/* Security attribution for Battery Backup registers (VBTBKRn). */ +#ifndef BSP_TZ_CFG_VBRSABAR +#if 0 +#define BSP_TZ_CFG_VBRSABAR (0xFFE0) +#else +#define BSP_TZ_CFG_VBRSABAR (0xED00) +#endif +#endif + +/* Security attribution for registers for IRQ channels. */ +#ifndef BSP_TZ_CFG_ICUSARA +#define BSP_TZ_CFG_ICUSARA (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16U) /* External IRQ16 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 17U) /* External IRQ17 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18U) /* External IRQ18 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19U) /* External IRQ19 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20U) /* External IRQ20 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 21U) /* External IRQ21 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22U) /* External IRQ22 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23U) /* External IRQ23 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24U) /* External IRQ24 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25U) /* External IRQ25 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26U) /* External IRQ26 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27U) /* External IRQ27 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28U) /* External IRQ28 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29U) /* External IRQ29 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30U) /* External IRQ30 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31U) /* External IRQ31 */) +#endif + +/* Security attribution for NMI registers. */ +#ifndef BSP_TZ_CFG_ICUSARB +#define BSP_TZ_CFG_ICUSARB (0 ? 7U : 0U) /* Should follow the secure attribution set in AIRCR.BFHFNMINS. */ +#endif + +/* Security attribution for registers for DMAC channels */ +#ifndef BSP_TZ_CFG_DMACCHSAR +#if (0 == BSP_CFG_CPU_CORE) +#define BSP_TZ_CFG_DMACCHSAR (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */) +#else +#define BSP_TZ_CFG_DMACCHSAR (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16U) /* DMAC1 Channel 0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 17U) /* DMAC1 Channel 1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18U) /* DMAC1 Channel 2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19U) /* DMAC1 Channel 3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20U) /* DMAC1 Channel 4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 21U) /* DMAC1 Channel 5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22U) /* DMAC1 Channel 6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23U) /* DMAC1 Channel 7 */) +#endif +#endif + +/* Security attribution registers for WUPEN0. */ +#ifndef BSP_TZ_CFG_ICUSARE +#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0U : 0xFF1D0000U) +#endif + +/* Security attribution registers for WUPEN1. */ +#ifndef BSP_TZ_CFG_ICUSARF +#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0U : 0x0000FF88U) +#endif + +/* Trusted Event Route Control Register for IELSR, DMAC.DELSR and ELC.ELSR. Note that currently Trusted Event Route Control is not supported. */ +#ifndef BSP_TZ_CFG_TEVTRCR +#define BSP_TZ_CFG_TEVTRCR (0) +#endif + +/* Security attribution register for ELCR, ELSEGR0, ELSEGR1, ELSEGR2, ELSEGR3 Security Attribution. */ +#ifndef BSP_TZ_CFG_ELCSARA +#define BSP_TZ_CFG_ELCSARA (0x0000001FU) +#endif + +/* Set DTCSTSAR if the Secure program uses the DTC. */ +#if RA_NOT_DEFINED == RA_NOT_DEFINED +#define BSP_TZ_CFG_DTC_USED (0U) +#else + #define BSP_TZ_CFG_DTC_USED (1U) +#endif + +/* Security attribution for IPC */ +#ifndef BSP_TZ_CFG_IPCSAR +#define BSP_TZ_CFG_IPCSAR (\ + ((0) << 0U) | /* SAIPCSEM0 */\ + ((0) << 1U) | /* SAIPCSEM1 */\ + ((0) << 8U) | /* SAIPCNMI0 */\ + ((0) << 9U) | /* SAIPCNMI1 */\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16U) /* IPC 00 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 17U) /* IPC 01 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18U) /* IPC 10 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19U) /* IPC 11 */) +#endif + +/* Security attribution of MRAM registers. */ +#ifndef BSP_TZ_CFG_MSAR +#define BSP_TZ_CFG_MSAR (\ + ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1) : 0U) | /* MREFREQ */\ + ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 3) : 0U) | /* MRCFREQ */\ + ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 4) : 0U) /* MRCPFB */) +#endif + +/* Security attribution for SRAM registers. */ +#ifndef BSP_TZ_CFG_SRAMSAR +/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access + * SRAM0WTEN and therefore there is no reason to access PRCR2. */ +#define BSP_TZ_CFG_SRAMSAR (\ + ((1U) << 0U) | /* SRAMSA0 */\ + ((1U) << 1U) | /* SRAMSA1 */\ + ((1U) << 2U) | /* SRAMSA2 */\ + ((1U) << 3U) | /* SRAMSA3 */\ + ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 8U) : 0U) /* SRAMWTSA */) +#endif + +/* SRAM ECC Region Security Attribution Register. */ +#ifndef BSP_TZ_CFG_SRAMESAR +#define BSP_TZ_CFG_SRAMESAR (0x1U) +#endif + +/* Security attribution for the DMAC Bus Master MPU settings. */ +#ifndef BSP_TZ_CFG_MMPUSARA +/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ +#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_DMACCHSAR) +#endif + +/* Security Attribution Register A for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARA +#define BSP_TZ_CFG_BUSSARA (1U) +#endif +/* Security Attribution Register B for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARB +#define BSP_TZ_CFG_BUSSARB (1U) +#endif +/* Security Attribution Register C for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARC +#define BSP_TZ_CFG_BUSSARC (1U) +#endif + +/* Enable Uninitialized Non-Secure Application Fallback. */ +#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK +#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) +#endif + +/* Security attribution for Cache registers. */ +#ifndef BSP_TZ_CFG_CACHESAR +#define BSP_TZ_CFG_CACHESAR (0x00000000U) +#endif + +/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ +#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT +#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif + +#ifndef BSP_CFG_DCACHE_ENABLED +#if (0U == BSP_CFG_CPU_CORE) +#define BSP_CFG_DCACHE_ENABLED (0) +#else + #define BSP_CFG_DCACHE_ENABLED (0) + #endif +#endif + +#ifndef BSP_CFG_DCACHE_FORCE_WRITETHROUGH +#if (0U == BSP_CFG_CPU_CORE) +#define BSP_CFG_DCACHE_FORCE_WRITETHROUGH (0) +#else + #define BSP_CFG_DCACHE_FORCE_WRITETHROUGH (0) + #endif +#endif + +#ifndef BSP_CFG_SDRAM_ENABLED +#define BSP_CFG_SDRAM_ENABLED (0) +#endif + +#ifndef BSP_CFG_SDRAM_TRAS +#define BSP_CFG_SDRAM_TRAS (6) +#endif + +#ifndef BSP_CFG_SDRAM_TRCD +#define BSP_CFG_SDRAM_TRCD (3) +#endif + +#ifndef BSP_CFG_SDRAM_TRP +#define BSP_CFG_SDRAM_TRP (3) +#endif + +#ifndef BSP_CFG_SDRAM_TWR +#define BSP_CFG_SDRAM_TWR (2) +#endif + +#ifndef BSP_CFG_SDRAM_TCL +#define BSP_CFG_SDRAM_TCL (3) +#endif + +#ifndef BSP_CFG_SDRAM_TRFC +#define BSP_CFG_SDRAM_TRFC (937) +#endif + +#ifndef BSP_CFG_SDRAM_TREFW +#define BSP_CFG_SDRAM_TREFW (8) +#endif + +#ifndef BSP_CFG_SDRAM_INIT_ARFI +#define BSP_CFG_SDRAM_INIT_ARFI (10) +#endif + +#ifndef BSP_CFG_SDRAM_INIT_ARFC +#define BSP_CFG_SDRAM_INIT_ARFC (8) +#endif + +#ifndef BSP_CFG_SDRAM_INIT_PRC +#define BSP_CFG_SDRAM_INIT_PRC (3) +#endif + +#ifndef BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT +#define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT (1) +#endif + +#ifndef BSP_CFG_SDRAM_ENDIAN_MODE +#define BSP_CFG_SDRAM_ENDIAN_MODE (0) +#endif + +#ifndef BSP_CFG_SDRAM_ACCESS_MODE +#define BSP_CFG_SDRAM_ACCESS_MODE (1) +#endif + +#ifndef BSP_CFG_SDRAM_BUS_WIDTH +#define BSP_CFG_SDRAM_BUS_WIDTH (1) +#endif +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/bsp/bsp_mcu_ofs_cfg.h b/bsp/renesas/ra8p1-titan-board/m33/ra_cfg/fsp_cfg/bsp/bsp_mcu_ofs_cfg.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/bsp/bsp_mcu_ofs_cfg.h rename to bsp/renesas/ra8p1-titan-board/m33/ra_cfg/fsp_cfg/bsp/bsp_mcu_ofs_cfg.h diff --git a/bsp/renesas/ra8p1-titan-board/m33/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/bsp/renesas/ra8p1-titan-board/m33/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h new file mode 100644 index 00000000000..c7915c64935 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h @@ -0,0 +1,212 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "r_ioport.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#define USER_SW_CFG_INT (BSP_IO_PORT_00_PIN_00) +#define ARDUINO_AN0 (BSP_IO_PORT_00_PIN_01) /* Enable when connected */ +#define GROVE2_AN0 (BSP_IO_PORT_00_PIN_02) /* Reference E42 / E40 */ +#define ARDUINO_AN2 (BSP_IO_PORT_00_PIN_03) /* Enable when connected */ +#define ARDUINO_AN3 (BSP_IO_PORT_00_PIN_04) /* Enable when connected */ +#define GROVE2_AN1 (BSP_IO_PORT_00_PIN_05) /* Reference E41 / E39 */ +#define PMOD1_IRQ (BSP_IO_PORT_00_PIN_06) +#define ARDUINO_AN1 (BSP_IO_PORT_00_PIN_07) /* Enable when connected */ +#define USER_SW2 (BSP_IO_PORT_00_PIN_08) +#define USER_SW1 (BSP_IO_PORT_00_PIN_09) +#define CAMERA_IRQ (BSP_IO_PORT_00_PIN_10) /* Enable when connected */ +#define ARDUINO_D2_INT0 (BSP_IO_PORT_00_PIN_11) /* Enable when connected */ +#define PMOD2_INT (BSP_IO_PORT_00_PIN_12) +#define I3C_SCL_PU (BSP_IO_PORT_00_PIN_13) /* Enable I3C_SEL_L to use */ +#define ARDUINO_AN4 (BSP_IO_PORT_00_PIN_14) /* Enable when connected */ +#define ARDUINO_AN5 (BSP_IO_PORT_00_PIN_15) /* Enable when connected */ +#define OSPI_SIO0_ARDUINO_MISO (BSP_IO_PORT_01_PIN_00) /* See SW4 in manual */ +#define OSPI_SIO3_ARDUINO_MOSI (BSP_IO_PORT_01_PIN_01) /* See SW4 in manual */ +#define OSPI_SIO4_ARDUINO_D13_SCK (BSP_IO_PORT_01_PIN_02) /* See SW4 in manual */ +#define OSPI_SIO2_ARDUINO_D10_SS (BSP_IO_PORT_01_PIN_03) /* See SW4 in manual */ +#define OSPI_CS_ARDUINO_D5 (BSP_IO_PORT_01_PIN_04) /* See SW4 in manual */ +#define OSPI_ECS_ARDUINO_D6 (BSP_IO_PORT_01_PIN_05) /* See SW4 in manual */ +#define OSPI_RESET (BSP_IO_PORT_01_PIN_06) /* See SW4 in manual */ +#define ETHERNET_MDINT (BSP_IO_PORT_01_PIN_07) +#define J2_30 (BSP_IO_PORT_01_PIN_08) /* Enable when connected */ +#define I3C_SDA_PU (BSP_IO_PORT_01_PIN_09) /* Enable I3C_SEL_L to use */ +#define ARDUINO_D9 (BSP_IO_PORT_01_PIN_10) /* Enable when connected */ +#define MIPI_INT (BSP_IO_PORT_01_PIN_11) /* See SW4 in manual */ +#define SDRAM_DQ3 (BSP_IO_PORT_01_PIN_12) +#define SDRAM_DQ4 (BSP_IO_PORT_01_PIN_13) +#define SDRAM_DQ5 (BSP_IO_PORT_01_PIN_14) +#define SDRAM_DQ6 (BSP_IO_PORT_01_PIN_15) +#define NMI (BSP_IO_PORT_02_PIN_00) +#define BOOT_MODE (BSP_IO_PORT_02_PIN_01) /* See Manual */ +#define ETHERNET_RXCTL (BSP_IO_PORT_02_PIN_06) /* Reference E38 in manual */ +#define PARLCD_D9G1 (BSP_IO_PORT_02_PIN_07) +#define JTAG_SWD_TDI (BSP_IO_PORT_02_PIN_08) +#define JTAG_SWD_TDO (BSP_IO_PORT_02_PIN_09) +#define JTAG_SWD_TMS (BSP_IO_PORT_02_PIN_10) +#define JTAG_SWD_TCK (BSP_IO_PORT_02_PIN_11) +#define EXTAL (BSP_IO_PORT_02_PIN_12) /* Main clock */ +#define XTAL (BSP_IO_PORT_02_PIN_13) /* Main clock */ +#define XCOUT (BSP_IO_PORT_02_PIN_14) /* Subclock */ +#define XCIN (BSP_IO_PORT_02_PIN_15) /* Subclock */ +#define SDRAM_DQ2 (BSP_IO_PORT_03_PIN_00) +#define SDRAM_DQ1 (BSP_IO_PORT_03_PIN_01) +#define SDRAM_DQ0 (BSP_IO_PORT_03_PIN_02) +#define USER_LED_GREEN (BSP_IO_PORT_03_PIN_03) +#define ETHERNET_TXD3_TDATA3 (BSP_IO_PORT_03_PIN_04) /* Reference SW4 / E44 / E18 in manual */ +#define ETHERNET_TXD2_TDATA2 (BSP_IO_PORT_03_PIN_05) /* Reference SW4 / E45 / E19 in manual */ +#define ETHERNET_TXD1_TDATA1 (BSP_IO_PORT_03_PIN_06) /* Reference SW4 / E46 / E20 in manual */ +#define ETHERNET_TXD0_TDATA0 (BSP_IO_PORT_03_PIN_07) /* Reference SW4 / E47 / E21 in manual */ +#define TCLK (BSP_IO_PORT_03_PIN_08) /* Reference SW4 / E48 in manual */ +#define ETHERNET_TCLK (BSP_IO_PORT_03_PIN_09) /* Reference SW4 / E23 in manual */ +#define ETHERNET_TCTL (BSP_IO_PORT_03_PIN_10) /* Reference SW4 / E22 in manual */ +#define ARDUINO_D7 (BSP_IO_PORT_03_PIN_12) /* Enable when connected */ +#define I3C_SCL (BSP_IO_PORT_04_PIN_00) +#define I3C_SDA (BSP_IO_PORT_04_PIN_01) +#define PMOD1_RST (BSP_IO_PORT_04_PIN_02) /* Enable when connected */ +#define AUDIO_BCLK (BSP_IO_PORT_04_PIN_03) +#define AUDIO_WCLK (BSP_IO_PORT_04_PIN_04) +#define AUDIO_SSITX (BSP_IO_PORT_04_PIN_05) /* See J41 in manual */ +#define AUDIO_SSIRX_DCAM_D2 (BSP_IO_PORT_04_PIN_06) /* See J41 in manual */ +#define USB_FS_VBUS (BSP_IO_PORT_04_PIN_07) +#define USB_HS_VBUS (BSP_IO_PORT_04_PIN_08) +#define PMOD2_GPIO1 (BSP_IO_PORT_04_PIN_09) /* Enable when connected */ +#define PMOD2_RST (BSP_IO_PORT_04_PIN_10) /* Enable when connected */ +#define MIPI_TE (BSP_IO_PORT_04_PIN_11) +#define PMOD1_GPIO1 (BSP_IO_PORT_04_PIN_12) /* Enable when connected */ +#define PMOD1_GPIO2 (BSP_IO_PORT_04_PIN_13) /* Enable when connected */ +#define ETHERNET_MDIO (BSP_IO_PORT_04_PIN_14) +#define ETHERNET_MDC (BSP_IO_PORT_04_PIN_15) +#define USB_FS_VBUSEN (BSP_IO_PORT_05_PIN_00) +#define CAM_XCLK (BSP_IO_PORT_05_PIN_01) /* Required for communication / operation */ +#define MIC_DAT (BSP_IO_PORT_05_PIN_02) +#define SDRAM_A4_32BIT (BSP_IO_PORT_05_PIN_03) +#define SDRAM_A5_32BIT (BSP_IO_PORT_05_PIN_04) +#define SDRAM_A6_32BIT (BSP_IO_PORT_05_PIN_05) +#define SDRAM_A7_32BIT (BSP_IO_PORT_05_PIN_06) +#define SDRAM_A8_32BIT (BSP_IO_PORT_05_PIN_07) +#define SDRAM_A9_32BIT (BSP_IO_PORT_05_PIN_08) +#define SDRAM_A10_32BIT (BSP_IO_PORT_05_PIN_09) +#define SDRAM_A11_32BIT (BSP_IO_PORT_05_PIN_10) +#define SYS_I2C_SDA (BSP_IO_PORT_05_PIN_11) +#define SYS_I2C_SCL (BSP_IO_PORT_05_PIN_12) +#define DISP_TCON3 (BSP_IO_PORT_05_PIN_13) +#define DISP_BLEN (BSP_IO_PORT_05_PIN_14) +#define DISP_CLK (BSP_IO_PORT_05_PIN_15) /* Enable when connected */ +#define USER_LED_BLUE (BSP_IO_PORT_06_PIN_00) +#define PMOD2_RTS_SSL (BSP_IO_PORT_06_PIN_01) /* See E16 / E14 in manual */ +#define PMOD2_RX (BSP_IO_PORT_06_PIN_02) +#define PMOD2_TX (BSP_IO_PORT_06_PIN_03) +#define PMOD2_CTS (BSP_IO_PORT_06_PIN_04) /* See E14 / E15 in manual */ +#define PMOD2_SSL (BSP_IO_PORT_06_PIN_05) /* See E10 in manual */ +#define DISP_RESET (BSP_IO_PORT_06_PIN_06) +#define SDRAM_DQ31 (BSP_IO_PORT_06_PIN_07) +#define SDRAM_A12_32BIT (BSP_IO_PORT_06_PIN_08) +#define SDRAM_DQ7 (BSP_IO_PORT_06_PIN_09) +#define SDRAM_DQ12 (BSP_IO_PORT_06_PIN_10) +#define SDRAM_DQ13 (BSP_IO_PORT_06_PIN_11) +#define SDRAM_DQ14 (BSP_IO_PORT_06_PIN_12) +#define SDRAM_DQ15 (BSP_IO_PORT_06_PIN_13) +#define SDRAM_DQM0 (BSP_IO_PORT_06_PIN_14) +#define SDRAM_DQM2 (BSP_IO_PORT_06_PIN_15) +#define DCAM_D4 (BSP_IO_PORT_07_PIN_00) /* See SW4 in manual */ +#define DCAM_D5 (BSP_IO_PORT_07_PIN_01) /* See SW4 in manual */ +#define DCAM_D6 (BSP_IO_PORT_07_PIN_02) /* See SW4 in manual */ +#define DCAM_D7 (BSP_IO_PORT_07_PIN_03) /* See SW4 in manual */ +#define PMOD2_GPIO2 (BSP_IO_PORT_07_PIN_04) /* Enable when connected */ +#define PARLCD_D18R2 (BSP_IO_PORT_07_PIN_07) +#define ETHERNET_RST (BSP_IO_PORT_07_PIN_08) +#define CAMERA_RESET (BSP_IO_PORT_07_PIN_09) +#define PARLCD_EXTCLK (BSP_IO_PORT_07_PIN_10) +#define PARLCD_D19R3 (BSP_IO_PORT_07_PIN_11) +#define PARLCD_D20R4 (BSP_IO_PORT_07_PIN_12) +#define PARLCD_D21R5 (BSP_IO_PORT_07_PIN_13) +#define PARLCD_D22R6 (BSP_IO_PORT_07_PIN_14) +#define PARLCD_D23R7 (BSP_IO_PORT_07_PIN_15) +#define OSPI_SIO5_PMOD1_CTS_IRQ (BSP_IO_PORT_08_PIN_00) /* See SW4 in manual */ +#define OSPI_DQS_PMOD1_TXD_MOSI (BSP_IO_PORT_08_PIN_01) /* See SW4 in manual */ +#define OSPI_SIO6_PMOD1_RXD_MISO (BSP_IO_PORT_08_PIN_02) /* See SW4 in manual */ +#define OSPI_SIO1_PMOD1_SCK (BSP_IO_PORT_08_PIN_03) /* See SW4 in manual */ +#define OSPI_SIO7_PMOD1_CTSRTS_SS (BSP_IO_PORT_08_PIN_04) /* See SW4 in manual */ +#define PARLCD_HSYNC (BSP_IO_PORT_08_PIN_05) /* See SW4 in manual */ +#define PARLCD_VSYNC (BSP_IO_PORT_08_PIN_06) /* See SW4 in manual */ +#define PARLCD_DE (BSP_IO_PORT_08_PIN_07) /* See SW4 in manual */ +#define OSPI_CLK_ARDUINO_MISO (BSP_IO_PORT_08_PIN_08) /* See SW4 in manual */ +#define ARDUINO_D1TX_MIKROBUS_TX (BSP_IO_PORT_08_PIN_09) /* Enable when connected */ +#define ARDUINO_D4_MIKROBUS_PWM (BSP_IO_PORT_08_PIN_10) /* Enable when connected */ +#define ARDUINO_D3 (BSP_IO_PORT_08_PIN_11) /* Enable when connected */ +#define MIC_CLK (BSP_IO_PORT_08_PIN_12) +#define SDRAM_CS (BSP_IO_PORT_08_PIN_13) /* See E50 in manual */ +#define USB_FS_DP (BSP_IO_PORT_08_PIN_14) +#define USB_FS_DM (BSP_IO_PORT_08_PIN_15) +#define PARLCD_D3B3_PARCAM_D1 (BSP_IO_PORT_09_PIN_02) /* See SW4 in manual */ +#define PARLCD_D2B2 (BSP_IO_PORT_09_PIN_03) +#define PARLCD_D8G0 (BSP_IO_PORT_09_PIN_04) +#define ETHERNET_RXC (BSP_IO_PORT_09_PIN_05) /* See E37 in manual */ +#define ETHERNET_RXD0 (BSP_IO_PORT_09_PIN_06) /* See E36 in manual */ +#define ETHERNET_RXD1 (BSP_IO_PORT_09_PIN_07) /* See E34 in manual */ +#define ETHERNET_RXD2 (BSP_IO_PORT_09_PIN_08) /* See E33 in manual */ +#define ETHERNET_RXD3 (BSP_IO_PORT_09_PIN_09) /* See E24 in manual */ +#define PARLCD_D4B4 (BSP_IO_PORT_09_PIN_10) /* See SW4 in manual */ +#define PARLCD_D5B5 (BSP_IO_PORT_09_PIN_11) /* See SW4 in manual */ +#define PARLCD_D6B6 (BSP_IO_PORT_09_PIN_12) /* See SW4 in manual */ +#define PARLCD_D7B7 (BSP_IO_PORT_09_PIN_13) /* See SW4 in manual */ +#define PARLCD_D0B0 (BSP_IO_PORT_09_PIN_14) /* See SW4 in manual */ +#define PARLCD_D1B1 (BSP_IO_PORT_09_PIN_15) /* See SW4 in manual */ +#define SDRAM_A3_32BIT (BSP_IO_PORT_10_PIN_00) +#define SDRAM_A2_32BIT (BSP_IO_PORT_10_PIN_01) +#define SDRAM_A1_32BIT (BSP_IO_PORT_10_PIN_02) +#define SDRAM_A0_32BIT (BSP_IO_PORT_10_PIN_03) +#define SDRAM_DQM3 (BSP_IO_PORT_10_PIN_04) +#define SDRAM_DQM1 (BSP_IO_PORT_10_PIN_05) +#define SDRAM_CKE (BSP_IO_PORT_10_PIN_06) +#define USER_LED_RED (BSP_IO_PORT_10_PIN_07) +#define SDRAM_WE (BSP_IO_PORT_10_PIN_08) +#define SDRAM_CAS (BSP_IO_PORT_10_PIN_09) +#define SDRAM_RAS (BSP_IO_PORT_10_PIN_10) +#define SDRAM_DQ8 (BSP_IO_PORT_10_PIN_11) +#define SDRAM_DQ9 (BSP_IO_PORT_10_PIN_12) +#define SDRAM_DQ10 (BSP_IO_PORT_10_PIN_13) +#define SDRAM_DQ11 (BSP_IO_PORT_10_PIN_14) +#define SDRAM_CLK (BSP_IO_PORT_10_PIN_15) +#define PARLCD_D17R1 (BSP_IO_PORT_11_PIN_00) +#define PARLCD_D13G5 (BSP_IO_PORT_11_PIN_01) +#define PARLCD_D16R0_PARCAM_VSYNC (BSP_IO_PORT_11_PIN_02) /* See SW4 in manual */ +#define PARLCD_D15G7_PARCAM_HSYNC (BSP_IO_PORT_11_PIN_03) /* See SW4 in manual */ +#define PARLCD_D14G6_PARCAM_PCLK (BSP_IO_PORT_11_PIN_04) /* See SW4 in manual */ +#define PARLCD_D12G4 (BSP_IO_PORT_11_PIN_05) +#define PARLCD_D11G3 (BSP_IO_PORT_11_PIN_06) +#define PARLCD_D10G2 (BSP_IO_PORT_11_PIN_07) +#define SDRAM_DQ30 (BSP_IO_PORT_12_PIN_00) +#define SDRAM_DQ29 (BSP_IO_PORT_12_PIN_01) +#define SDRAM_DQ28 (BSP_IO_PORT_12_PIN_02) +#define SDRAM_DQ27 (BSP_IO_PORT_12_PIN_03) +#define SDRAM_DQ26 (BSP_IO_PORT_12_PIN_04) +#define SDRAM_DQ25 (BSP_IO_PORT_12_PIN_05) +#define SDRAM_DQ24 (BSP_IO_PORT_12_PIN_06) +#define SDRAM_DQ23 (BSP_IO_PORT_12_PIN_07) +#define SDRAM_DQ22 (BSP_IO_PORT_12_PIN_08) +#define SDRAM_DQ21 (BSP_IO_PORT_12_PIN_09) +#define SDRAM_DQ20 (BSP_IO_PORT_12_PIN_10) +#define SDRAM_DQ19 (BSP_IO_PORT_12_PIN_11) +#define SDRAM_DQ18 (BSP_IO_PORT_12_PIN_12) +#define SDRAM_DQ17 (BSP_IO_PORT_12_PIN_13) +#define SDRAM_DQ16 (BSP_IO_PORT_12_PIN_14) +#define SDRAM_BA1 (BSP_IO_PORT_12_PIN_15) +#define SDRAM_BA0 (BSP_IO_PORT_13_PIN_00) +#define ARDUINO_D8_MIKROBUS_INT (BSP_IO_PORT_13_PIN_01) /* Enable when connected */ +#define VCOMM_TXD_TO_EXT (BSP_IO_PORT_13_PIN_02) +#define VCOMM_RXD_FROM_EXT (BSP_IO_PORT_13_PIN_03) +#define VCOMM_RTS_FROM_EXT (BSP_IO_PORT_13_PIN_04) /* See E17 in manual */ +#define VCOMM_CTS_TO_EXT (BSP_IO_PORT_13_PIN_05) /* See E9 in manual */ +#define AUDIO_MCLK (BSP_IO_PORT_13_PIN_06) /* Enable when connected */ +#define USB_HS_VBUSEN (BSP_IO_PORT_13_PIN_07) + +extern const ioport_cfg_t g_bsp_pin_cfg; /* Titan_Board */ + +void BSP_PinConfigSecurityInit(); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif /* BSP_PIN_CFG_H_ */ diff --git a/bsp/renesas/ra8p1-titan-board/m33/ra_cfg/fsp_cfg/r_ioport_cfg.h b/bsp/renesas/ra8p1-titan-board/m33/ra_cfg/fsp_cfg/r_ioport_cfg.h new file mode 100644 index 00000000000..d2688bf5ba3 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/ra_cfg/fsp_cfg/r_ioport_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IOPORT_CFG_H_ +#define R_IOPORT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_IOPORT_CFG_H_ */ diff --git a/bsp/renesas/ra8p1-titan-board/m33/ra_cfg/fsp_cfg/r_sci_b_uart_cfg.h b/bsp/renesas/ra8p1-titan-board/m33/ra_cfg/fsp_cfg/r_sci_b_uart_cfg.h new file mode 100644 index 00000000000..aa4b4341990 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/ra_cfg/fsp_cfg/r_sci_b_uart_cfg.h @@ -0,0 +1,16 @@ +/* generated configuration header file - do not edit */ +#ifndef R_SCI_B_UART_CFG_H_ +#define R_SCI_B_UART_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + +#define SCI_B_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SCI_B_UART_CFG_FIFO_SUPPORT (1) +#define SCI_B_UART_CFG_DTC_SUPPORTED (0) +#define SCI_B_UART_CFG_FLOW_CONTROL_SUPPORT (0) + +#ifdef __cplusplus + } + #endif +#endif /* R_SCI_B_UART_CFG_H_ */ diff --git a/bsp/renesas/ra8p1-titan-board/ra_gen/SConscript b/bsp/renesas/ra8p1-titan-board/m33/ra_gen/SConscript similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_gen/SConscript rename to bsp/renesas/ra8p1-titan-board/m33/ra_gen/SConscript diff --git a/bsp/renesas/ra8p1-titan-board/m33/ra_gen/bsp_clock_cfg.h b/bsp/renesas/ra8p1-titan-board/m33/ra_gen/bsp_clock_cfg.h new file mode 100644 index 00000000000..f4f5d17474b --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/ra_gen/bsp_clock_cfg.h @@ -0,0 +1,75 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ +#define BSP_CFG_HOCO_FREQUENCY (7) /* HOCO 48MHz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(250,0) /* PLL Mul x240-259|Mul x250|PLL Mul x250.00 */ +#define BSP_CFG_PLL_FREQUENCY_HZ (2000000000) /* PLL 2000000000Hz */ +#define BSP_CFG_PLODIVP (BSP_CLOCKS_PLL_DIV_2) /* PLL1P Div /2 */ +#define BSP_CFG_PLL1P_FREQUENCY_HZ (1000000000) /* PLL1P 1000000000Hz */ +#define BSP_CFG_PLODIVQ (BSP_CLOCKS_PLL_DIV_6) /* PLL1Q Div /6 */ +#define BSP_CFG_PLL1Q_FREQUENCY_HZ (333333333) /* PLL1Q 333333333Hz */ +#define BSP_CFG_PLODIVR (BSP_CLOCKS_PLL_DIV_5) /* PLL1R Div /5 */ +#define BSP_CFG_PLL1R_FREQUENCY_HZ (400000000) /* PLL1R 400000000Hz */ +#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */ +#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL2 Div /3 */ +#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(300,0) /* PLL2 Mul x280-300|Mul x300|PLL2 Mul x300.00 */ +#define BSP_CFG_PLL2_FREQUENCY_HZ (2400000000) /* PLL2 2400000000Hz */ +#define BSP_CFG_PL2ODIVP (BSP_CLOCKS_PLL_DIV_4) /* PLL2P Div /4 */ +#define BSP_CFG_PLL2P_FREQUENCY_HZ (600000000) /* PLL2P 600000000Hz */ +#define BSP_CFG_PL2ODIVQ (BSP_CLOCKS_PLL_DIV_3) /* PLL2Q Div /3 */ +#define BSP_CFG_PLL2Q_FREQUENCY_HZ (800000000) /* PLL2Q 800000000Hz */ +#define BSP_CFG_PL2ODIVR (BSP_CLOCKS_PLL_DIV_5) /* PLL2R Div /5 */ +#define BSP_CFG_PLL2R_FREQUENCY_HZ (480000000) /* PLL2R 480000000Hz */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL1P) /* Clock Src: PLL1P */ +#define BSP_CFG_CPUCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CPUCLK Div /1 */ +#define BSP_CFG_CPUCLK1_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* CPUCLK1 Div /4 */ +#define BSP_CFG_NPUCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* NPUCLK Div /2 */ +#define BSP_CFG_MRICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* MRICLK Div /4 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_8) /* MRPCLK Div /8 */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* ICLK Div /4 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_8) /* PCLKA Div /8 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_16) /* PCLKB Div /16 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_8) /* PCLKC Div /8 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKD Div /4 */ +#define BSP_CFG_PCLKE_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKE Div /4 */ +#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_8) /* BCLK Div /8 */ +#define BSP_CFG_BCLKA_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2Q) /* BCLKA Src: PLL2Q */ +#define BSP_CFG_BCLKA_DIV (BSP_CLOCKS_BCLKA_CLOCK_DIV_6) /* BCLKA Div /6 */ +#define BSP_CFG_SDCLK_OUTPUT (1) /* SDCLK Enabled */ +#define BSP_CFG_EBCLKA_SEL (0) /* EBCLK Src: BCLK (Synchronous) */ +#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* CLKOUT Src: HOCO */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#define BSP_CFG_SCICLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2R) /* SCICLK Src: PLL2R */ +#define BSP_CFG_SCICLK_DIV (BSP_CLOCKS_SCI_CLOCK_DIV_4) /* SCICLK Div /4 */ +#define BSP_CFG_SPICLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL1Q) /* SPICLK Src: PLL1Q */ +#define BSP_CFG_SPICLK_DIV (BSP_CLOCKS_SPI_CLOCK_DIV_1) /* SPICLK Div /1 */ +#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2R) /* CANFDCLK Src: PLL2R */ +#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_6) /* CANFDCLK Div /6 */ +#define BSP_CFG_GPTCLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2P) /* GPTCLK Src: PLL2P */ +#define BSP_CFG_GPTCLK_DIV (BSP_CLOCKS_GPT_CLOCK_DIV_2) /* GPTCLK Div /2 */ +#define BSP_CFG_GPT_COUNT_CLOCK_SOURCE (0) /* GPT Src: GPTCLK */ +#define BSP_CFG_LCDCLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2R) /* LCDCLK Src: PLL2R */ +#define BSP_CFG_LCDCLK_DIV (BSP_CLOCKS_LCD_CLOCK_DIV_2) /* LCDCLK Div /2 */ +#define BSP_CFG_I3CCLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2Q) /* I3CCLK Src: PLL2Q */ +#define BSP_CFG_I3CCLK_DIV (BSP_CLOCKS_I3C_CLOCK_DIV_4) /* I3CCLK Div /4 */ +#define BSP_CFG_UCLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2R) /* USBCLK Src: PLL2R */ +#define BSP_CFG_UCLK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_10) /* USBCLK Div /10 */ +#define BSP_CFG_USB60CLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2R) /* USB60CLK Src: PLL2R */ +#define BSP_CFG_USB60CLK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_8) /* USB60CLK Div /8 */ +#define BSP_CFG_OCTACLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL1Q) /* OCTACLK Src: PLL1Q */ +#define BSP_CFG_OCTACLK_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTACLK Div /1 */ +#define BSP_CFG_ADCCLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2R) /* ADCCLK Src: PLL2R */ +#define BSP_CFG_ADCCLK_DIV (BSP_CLOCKS_ADC_CLOCK_DIV_4) /* ADCCLK Div /4 */ +#define BSP_CFG_ESWCLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL1P) /* ESWCLK Src: PLL1P */ +#define BSP_CFG_ESWCLK_DIV (BSP_CLOCKS_ESW_CLOCK_DIV_4) /* ESWCLK Div /4 */ +#define BSP_CFG_ESWPHYCLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL1P) /* ESWPHYCLK Src: PLL1P */ +#define BSP_CFG_ESWPHYCLK_DIV (BSP_CLOCKS_ESWPHY_CLOCK_DIV_2) /* ESWPHYCLK Div /2 */ +#define BSP_CFG_ETHPHYCLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2Q) /* ETHPHYCLK Src: PLL2Q */ +#define BSP_CFG_ETHPHYCLK_DIV (BSP_CLOCKS_ETHPHY_CLOCK_DIV_32) /* ETHPHYCLK Div /32 */ +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/bsp/renesas/ra8p1-titan-board/m33/ra_gen/common_data.c b/bsp/renesas/ra8p1-titan-board/m33/ra_gen/common_data.c new file mode 100644 index 00000000000..5a5bbae8b59 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/ra_gen/common_data.c @@ -0,0 +1,8 @@ +/* generated common source file - do not edit */ +#include "common_data.h" +ioport_instance_ctrl_t g_ioport_ctrl; +const ioport_instance_t g_ioport = +{ .p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg, }; +void g_common_init(void) +{ +} diff --git a/bsp/renesas/ra8p1-titan-board/m33/ra_gen/common_data.h b/bsp/renesas/ra8p1-titan-board/m33/ra_gen/common_data.h new file mode 100644 index 00000000000..6a08cbee095 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/ra_gen/common_data.h @@ -0,0 +1,20 @@ +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include +#include "bsp_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +#define IOPORT_CFG_NAME g_bsp_pin_cfg +#define IOPORT_CFG_OPEN R_IOPORT_Open +#define IOPORT_CFG_CTRL g_ioport_ctrl + +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/bsp/renesas/ra8p1-titan-board/m33/ra_gen/hal_data.c b/bsp/renesas/ra8p1-titan-board/m33/ra_gen/hal_data.c new file mode 100644 index 00000000000..2cab034048e --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/ra_gen/hal_data.c @@ -0,0 +1,76 @@ +/* generated HAL source file - do not edit */ +#include "hal_data.h" +sci_b_uart_instance_ctrl_t g_uart5_ctrl; + +sci_b_baud_setting_t g_uart5_baud_setting = + { + /* Baud rate calculated with 0.160% error. */.baudrate_bits_b.abcse = 0, + .baudrate_bits_b.abcs = 0, .baudrate_bits_b.bgdm = 1, .baudrate_bits_b.cks = 0, .baudrate_bits_b.brr = 64, .baudrate_bits_b.mddr = + (uint8_t) 256, + .baudrate_bits_b.brme = false }; + +/** UART extended configuration for UARTonSCI HAL driver */ +const sci_b_uart_extended_cfg_t g_uart5_cfg_extend = +{ .clock = SCI_B_UART_CLOCK_INT, .rx_edge_start = SCI_B_UART_START_BIT_FALLING_EDGE, .noise_cancel = + SCI_B_UART_NOISE_CANCELLATION_DISABLE, + .rx_fifo_trigger = SCI_B_UART_RX_FIFO_TRIGGER_MAX, .p_baud_setting = &g_uart5_baud_setting, .flow_control = + SCI_B_UART_FLOW_CONTROL_RTS, +#if 0xFF != 0xFF + .flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF, + #else + .flow_control_pin = (bsp_io_port_pin_t) UINT16_MAX, +#endif + .rs485_setting = + { .enable = SCI_B_UART_RS485_DISABLE, + .polarity = SCI_B_UART_RS485_DE_POLARITY_HIGH, + .assertion_time = 1, + .negation_time = 1, } }; + +/** UART interface configuration */ +const uart_cfg_t g_uart5_cfg = +{ .channel = 5, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = + user_uart5_callback, + .p_context = NULL, .p_extend = &g_uart5_cfg_extend, +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, +#else + .p_transfer_tx = &RA_NOT_DEFINED, +#endif +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, +#else + .p_transfer_rx = &RA_NOT_DEFINED, +#endif +#undef RA_NOT_DEFINED + .rxi_ipl = (12), + .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), +#if defined(VECTOR_NUMBER_SCI5_RXI) + .rxi_irq = VECTOR_NUMBER_SCI5_RXI, +#else + .rxi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI5_TXI) + .txi_irq = VECTOR_NUMBER_SCI5_TXI, +#else + .txi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI5_TEI) + .tei_irq = VECTOR_NUMBER_SCI5_TEI, +#else + .tei_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI5_ERI) + .eri_irq = VECTOR_NUMBER_SCI5_ERI, +#else + .eri_irq = FSP_INVALID_VECTOR, +#endif + }; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart5 = +{ .p_ctrl = &g_uart5_ctrl, .p_cfg = &g_uart5_cfg, .p_api = &g_uart_on_sci_b }; +void g_hal_init(void) +{ + g_common_init (); +} diff --git a/bsp/renesas/ra8p1-titan-board/m33/ra_gen/hal_data.h b/bsp/renesas/ra8p1-titan-board/m33/ra_gen/hal_data.h new file mode 100644 index 00000000000..d221c4c1bb6 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/ra_gen/hal_data.h @@ -0,0 +1,24 @@ +/* generated HAL header file - do not edit */ +#ifndef HAL_DATA_H_ +#define HAL_DATA_H_ +#include +#include "bsp_api.h" +#include "common_data.h" +#include "r_sci_b_uart.h" +#include "r_uart_api.h" +FSP_HEADER +/** UART on SCI Instance. */ +extern const uart_instance_t g_uart5; + +/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ +extern sci_b_uart_instance_ctrl_t g_uart5_ctrl; +extern const uart_cfg_t g_uart5_cfg; +extern const sci_b_uart_extended_cfg_t g_uart5_cfg_extend; + +#ifndef user_uart5_callback +void user_uart5_callback(uart_callback_args_t *p_args); +#endif +void hal_entry(void); +void g_hal_init(void); +FSP_FOOTER +#endif /* HAL_DATA_H_ */ diff --git a/bsp/renesas/ra8p1-titan-board/m33/ra_gen/main.c b/bsp/renesas/ra8p1-titan-board/m33/ra_gen/main.c new file mode 100644 index 00000000000..6f1f9608fa0 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/ra_gen/main.c @@ -0,0 +1,7 @@ +/* generated main source file - do not edit */ +#include "hal_data.h" +int main(void) +{ + hal_entry (); + return 0; +} diff --git a/bsp/renesas/ra8p1-titan-board/m33/ra_gen/pin_data.c b/bsp/renesas/ra8p1-titan-board/m33/ra_gen/pin_data.c new file mode 100644 index 00000000000..a3bd423b592 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/ra_gen/pin_data.c @@ -0,0 +1,53 @@ +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_ioport.h" + +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = +{ +{ .pin = BSP_IO_PORT_04_PIN_02, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SSI) }, + { .pin = BSP_IO_PORT_10_PIN_08, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9) }, + { .pin = BSP_IO_PORT_10_PIN_09, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9) }, }; + +const ioport_cfg_t g_bsp_pin_cfg = +{ .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t), .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], }; + +#if BSP_TZ_SECURE_BUILD + +void R_BSP_PinCfgSecurityInit(void); + +/* Initialize SAR registers for secure pins. */ +void R_BSP_PinCfgSecurityInit(void) +{ + #if (2U == BSP_FEATURE_IOPORT_VERSION) + uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #else + uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #endif + memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0])); + + + for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++) + { + uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin; + uint32_t port = port_pin >> 8U; + uint32_t pin = port_pin & 0xFFU; + pmsar[port] &= (uint16_t) ~(1U << pin); + } + + for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++) + { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + #if BSP_SECONDARY_CORE_BUILD + R_PMISC->PMSAR[i].PMSAR &= (uint16_t) pmsar[i]; + #else + R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i]; + #endif + #else + R_PMISC->PMSAR[i].PMSAR = pmsar[i]; + #endif + } + +} +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m33/ra_gen/vector_data.c b/bsp/renesas/ra8p1-titan-board/m33/ra_gen/vector_data.c new file mode 100644 index 00000000000..eee2ef12f54 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/ra_gen/vector_data.c @@ -0,0 +1,21 @@ +/* generated vector source file - do not edit */ +#include "bsp_api.h" +/* Do not build these data structures if no interrupts are currently allocated because IAR will have build errors. */ +#if VECTOR_DATA_IRQ_COUNT > 0 + BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_NUM_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = + { + [0] = sci_b_uart_rxi_isr, /* SCI5 RXI (Receive data full) */ + [1] = sci_b_uart_txi_isr, /* SCI5 TXI (Transmit data empty) */ + [2] = sci_b_uart_tei_isr, /* SCI5 TEI (Transmit end) */ + [3] = sci_b_uart_eri_isr, /* SCI5 ERI (Receive error) */ + }; + #if BSP_FEATURE_ICU_HAS_IELSR + const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_NUM_ENTRIES] = + { + [0] = BSP_PRV_VECT_ENUM(EVENT_SCI5_RXI,GROUP0), /* SCI5 RXI (Receive data full) */ + [1] = BSP_PRV_VECT_ENUM(EVENT_SCI5_TXI,GROUP1), /* SCI5 TXI (Transmit data empty) */ + [2] = BSP_PRV_VECT_ENUM(EVENT_SCI5_TEI,GROUP2), /* SCI5 TEI (Transmit end) */ + [3] = BSP_PRV_VECT_ENUM(EVENT_SCI5_ERI,GROUP3), /* SCI5 ERI (Receive error) */ + }; + #endif + #endif diff --git a/bsp/renesas/ra8p1-titan-board/m33/ra_gen/vector_data.h b/bsp/renesas/ra8p1-titan-board/m33/ra_gen/vector_data.h new file mode 100644 index 00000000000..04ea75483a3 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/ra_gen/vector_data.h @@ -0,0 +1,32 @@ +/* generated vector header file - do not edit */ +#ifndef VECTOR_DATA_H +#define VECTOR_DATA_H +#ifdef __cplusplus + extern "C" { + #endif +/* Number of interrupts allocated */ +#ifndef VECTOR_DATA_IRQ_COUNT +#define VECTOR_DATA_IRQ_COUNT (4) +#endif +/* ISR prototypes */ +void sci_b_uart_rxi_isr(void); +void sci_b_uart_txi_isr(void); +void sci_b_uart_tei_isr(void); +void sci_b_uart_eri_isr(void); + +/* Vector table allocations */ +#define VECTOR_NUMBER_SCI5_RXI ((IRQn_Type) 0) /* SCI5 RXI (Receive data full) */ +#define SCI5_RXI_IRQn ((IRQn_Type) 0) /* SCI5 RXI (Receive data full) */ +#define VECTOR_NUMBER_SCI5_TXI ((IRQn_Type) 1) /* SCI5 TXI (Transmit data empty) */ +#define SCI5_TXI_IRQn ((IRQn_Type) 1) /* SCI5 TXI (Transmit data empty) */ +#define VECTOR_NUMBER_SCI5_TEI ((IRQn_Type) 2) /* SCI5 TEI (Transmit end) */ +#define SCI5_TEI_IRQn ((IRQn_Type) 2) /* SCI5 TEI (Transmit end) */ +#define VECTOR_NUMBER_SCI5_ERI ((IRQn_Type) 3) /* SCI5 ERI (Receive error) */ +#define SCI5_ERI_IRQn ((IRQn_Type) 3) /* SCI5 ERI (Receive error) */ +/* The number of entries required for the ICU vector table. */ +#define BSP_ICU_VECTOR_NUM_ENTRIES (4) + +#ifdef __cplusplus + } + #endif +#endif /* VECTOR_DATA_H */ diff --git a/bsp/renesas/ra8p1-titan-board/m33/rasc_launcher.bat b/bsp/renesas/ra8p1-titan-board/m33/rasc_launcher.bat new file mode 100644 index 00000000000..db4a2e1c500 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/rasc_launcher.bat @@ -0,0 +1,43 @@ +@echo off +setlocal ENABLEEXTENSIONS ENABLEDELAYEDEXPANSION + +set "RascVersionFile=%~1" +shift + +set "InputFile=%~dp0configuration.xml" +set "OutputFile=%~dp0output.rasc" + +if /i "%~3"=="--gensmartbundle" ( + set "InputFile=%~9" + set "OutputFile=%~dpn9.sbd" +) + +if not exist "%InputFile%" ( + echo [ERROR] Input file "%InputFile%" does not exist. + exit /b 1 +) + +call "%~dp0rasc_version.bat" "%RascVersionFile%" +if errorlevel 1 exit /b 1 + +set /a idx=0 +for /f "usebackq tokens=*" %%a in ("%RascVersionFile%") do ( + if !idx! EQU 2 set "RascExe=%%a" + set /a idx+=1 +) + +if not defined RascExe ( + echo [ERROR] RASC executable is not configured. + exit /b 1 +) + +set "RascExe=%RascExe:rasc.exe=rascc.exe%" +set "Parameters=" +for %%a in (%*) do ( + if defined FirstParamSkipped set Parameters=!Parameters! %%a + set FirstParamSkipped=true +) + +echo [INFO] Generating Smart Bundle "%OutputFile%"... +"%RascExe%" %Parameters% +exit /b %errorlevel% diff --git a/bsp/renesas/ra8p1-titan-board/m33/rasc_version.bat b/bsp/renesas/ra8p1-titan-board/m33/rasc_version.bat new file mode 100644 index 00000000000..7ae172b6242 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/rasc_version.bat @@ -0,0 +1,36 @@ +@echo off +setlocal ENABLEEXTENSIONS ENABLEDELAYEDEXPANSION + +set "RascVersionFile=%~1" +set "RascVersion=" +set "RascExe=" + +if exist "%RascVersionFile%" ( + set /a idx=0 + for /f "usebackq tokens=*" %%a in ("%RascVersionFile%") do ( + if !idx! EQU 1 set "RascVersion=%%a" + if !idx! EQU 2 set "RascExe=%%a" + set /a idx+=1 + ) +) + +if defined RascExe if exist "%RascExe%" exit /b 0 + +set "RascExe=" +for %%r in ("C:\Tools\Renesas\FSP" "C:\Renesas\RA" "C:\Renesas") do ( + if not defined RascExe if exist "%%~r" ( + for /d %%d in ("%%~r\*fsp_v6.2.0*") do ( + if not defined RascExe if exist "%%~d\eclipse\rascc.exe" set "RascExe=%%~d\eclipse\rascc.exe" + ) + ) +) + +if not defined RascExe ( + echo [ERROR] Renesas FSP 6.2.0 Smart Configurator was not found. + exit /b 1 +) + +>"%RascVersionFile%" echo # RASC version and installation file +>>"%RascVersionFile%" echo 6.2.0 +>>"%RascVersionFile%" echo %RascExe% +exit /b 0 diff --git a/bsp/renesas/ra8p1-titan-board/m33/rtconfig.h b/bsp/renesas/ra8p1-titan-board/m33/rtconfig.h new file mode 100644 index 00000000000..90eb9908d88 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/rtconfig.h @@ -0,0 +1,225 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +#define SOC_R7KA8P1KF + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 12 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice options */ + +/* end of kservice options */ +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP +#define RT_MEMHEAP_FAST_MODE +#define RT_USING_MEMHEAP_AS_HEAP +#define RT_USING_MEMHEAP_AUTO_BINDING +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart5" +#define RT_USING_CONSOLE_OUTPUT_CTL +#define RT_VER_NUM 0x50300 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define RT_USING_HW_ATOMIC +#define ARCH_USING_HW_ATOMIC_8 +#define ARCH_USING_HW_ATOMIC_16 +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_SECURE +#define ARCH_ARM_CORTEX_M33 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V2 +#define RT_SERIAL_BUF_STRATEGY_OVERWRITE +#define RT_SERIAL_USING_DMA +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ +#define SOC_FAMILY_RENESAS_RA +#define SOC_SERIES_R7KA8P1 +#define SOC_SERIES_R7KA8P1_CORE1 + +/* Hardware Drivers Config */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART5 +#define BSP_UART5_RX_BUFSIZE 256 +#define BSP_UART5_TX_BUFSIZE 0 +/* end of On-chip Peripheral Drivers */ +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m33/rtconfig.py b/bsp/renesas/ra8p1-titan-board/m33/rtconfig.py new file mode 100644 index 00000000000..9fdc622b58e --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/rtconfig.py @@ -0,0 +1,104 @@ +import os +import sys + +# toolchains options +ARCH='arm' +CPU='cortex-m33' +CROSS_TOOL='gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armclang' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +# BUILD = 'release' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + NM = PREFIX + 'nm' + + DEVICE = ' -mcpu=cortex-m33 -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T script/fsp.ld -L script/' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g -Wall' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -Os' + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n' + # POST_ACTION += OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + CXX = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M33' + + CFLAGS = ' -mcpu=Cortex-M33 -xc -std=c99 --target=arm-arm-none-eabi -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c' + CFLAGS += ' -fno-rtti -funsigned-char -ffunction-sections' + CFLAGS += ' -Wno-license-management -Wuninitialized -Wall -Wmissing-declarations -Wpointer-arith -Waggregate-return -Wfloat-equal' + + AFLAGS = DEVICE + ' --fpu FPv5-SP --apcs=interwork' + + LFLAGS = DEVICE + ' --scatter ' + 'script/fsp.scat' + LFLAGS +=' --info sizes --info totals --info unused --info veneers ' + LFLAGS += ' --list rt-thread.map --strict' + LFLAGS += ' --diag_suppress 6319,6314 --summary_stderr --info summarysizes' + LFLAGS += ' --map --load_addr_map_info --xref --callgraph --symbols' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' + + EXEC_PATH += '/ARM/ARMCLANG/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -Os' + CXXFLAGS = CFLAGS + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET \n' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/renesas/ra8p1-titan-board/m33/script/fsp.icf b/bsp/renesas/ra8p1-titan-board/m33/script/fsp.icf new file mode 100644 index 00000000000..cb6daddc4c3 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/script/fsp.icf @@ -0,0 +1,969 @@ + /* generated memory regions file - do not edit */ + define symbol RAM_START = 0x22194000; + define symbol RAM_LENGTH = 0x40000; + define symbol FLASH_START = 0x020C0000; + define symbol FLASH_LENGTH = 0x00040000; + define symbol DATA_FLASH_START = 0x27000000; + define symbol DATA_FLASH_LENGTH = 0x00000000; + define symbol SDRAM_START = 0x68000000; + define symbol SDRAM_LENGTH = 0x08000000; + define symbol OSPI0_CS0_START = 0x80000000; + define symbol OSPI0_CS0_LENGTH = 0x10000000; + define symbol OSPI0_CS1_START = 0x90000000; + define symbol OSPI0_CS1_LENGTH = 0x10000000; + define symbol OSPI1_CS0_START = 0x70000000; + define symbol OSPI1_CS0_LENGTH = 0x08000000; + define symbol OSPI1_CS1_START = 0x78000000; + define symbol OSPI1_CS1_LENGTH = 0x08000000; + define symbol OPTION_SETTING_OFS0_START = 0x02c9f040; + define symbol OPTION_SETTING_OFS0_LENGTH = 0x00000004; + define symbol OPTION_SETTING_OFS2_START = 0x02c9f044; + define symbol OPTION_SETTING_OFS2_LENGTH = 0x00000004; + define symbol OPTION_SETTING_SAS_START = 0x02c9f074; + define symbol OPTION_SETTING_SAS_LENGTH = 0x00000004; + define symbol OPTION_SETTING_OFS1_START = 0x12c9f4c0; + define symbol OPTION_SETTING_OFS1_LENGTH = 0x00000004; + define symbol OPTION_SETTING_OFS1_SEC_START = 0x02c9f0c0; + define symbol OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; + define symbol OPTION_SETTING_OFS1_SEL_START = 0x02c9f120; + define symbol OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; + define symbol OPTION_SETTING_OFS3_START = 0x12c9f4c4; + define symbol OPTION_SETTING_OFS3_LENGTH = 0x00000004; + define symbol OPTION_SETTING_OFS3_SEC_START = 0x02c9f0c4; + define symbol OPTION_SETTING_OFS3_SEC_LENGTH = 0x00000004; + define symbol OPTION_SETTING_OFS3_SEL_START = 0x02c9f124; + define symbol OPTION_SETTING_OFS3_SEL_LENGTH = 0x00000004; + define symbol OPTION_SETTING_BPS_START = 0x12c9f600; + define symbol OPTION_SETTING_BPS_LENGTH = 0x00000080; + define symbol OPTION_SETTING_BPS_SEC_START = 0x02c9f200; + define symbol OPTION_SETTING_BPS_SEC_LENGTH = 0x00000080; + define symbol OPTION_SETTING_OTP_PBPS_SEC_START = 0x02e07700; + define symbol OPTION_SETTING_OTP_PBPS_SEC_LENGTH = 0x00000080; + define symbol OPTION_SETTING_OTP_PBPS_START = 0x12e07780; + define symbol OPTION_SETTING_OTP_PBPS_LENGTH = 0x00000080; + define symbol CTCM_START = 0x00000000; + define symbol CTCM_LENGTH = 0x00010000; + define symbol STCM_START = 0x20000000; + define symbol STCM_LENGTH = 0x00010000; + + define region RAM = mem:[from RAM_START size RAM_LENGTH]; + define region FLASH = mem:[from FLASH_START size FLASH_LENGTH]; + define region DATA_FLASH = mem:[from DATA_FLASH_START size DATA_FLASH_LENGTH]; + define region SDRAM = mem:[from SDRAM_START size SDRAM_LENGTH]; + define region OSPI0_CS0 = mem:[from OSPI0_CS0_START size OSPI0_CS0_LENGTH]; + define region OSPI0_CS1 = mem:[from OSPI0_CS1_START size OSPI0_CS1_LENGTH]; + define region OSPI1_CS0 = mem:[from OSPI1_CS0_START size OSPI1_CS0_LENGTH]; + define region OSPI1_CS1 = mem:[from OSPI1_CS1_START size OSPI1_CS1_LENGTH]; + define region OPTION_SETTING_OFS0 = mem:[from OPTION_SETTING_OFS0_START size OPTION_SETTING_OFS0_LENGTH]; + define region OPTION_SETTING_OFS2 = mem:[from OPTION_SETTING_OFS2_START size OPTION_SETTING_OFS2_LENGTH]; + define region OPTION_SETTING_SAS = mem:[from OPTION_SETTING_SAS_START size OPTION_SETTING_SAS_LENGTH]; + define region OPTION_SETTING_OFS1 = mem:[from OPTION_SETTING_OFS1_START size OPTION_SETTING_OFS1_LENGTH]; + define region OPTION_SETTING_OFS1_SEC = mem:[from OPTION_SETTING_OFS1_SEC_START size OPTION_SETTING_OFS1_SEC_LENGTH]; + define region OPTION_SETTING_OFS1_SEL = mem:[from OPTION_SETTING_OFS1_SEL_START size OPTION_SETTING_OFS1_SEL_LENGTH]; + define region OPTION_SETTING_OFS3 = mem:[from OPTION_SETTING_OFS3_START size OPTION_SETTING_OFS3_LENGTH]; + define region OPTION_SETTING_OFS3_SEC = mem:[from OPTION_SETTING_OFS3_SEC_START size OPTION_SETTING_OFS3_SEC_LENGTH]; + define region OPTION_SETTING_OFS3_SEL = mem:[from OPTION_SETTING_OFS3_SEL_START size OPTION_SETTING_OFS3_SEL_LENGTH]; + define region OPTION_SETTING_BPS = mem:[from OPTION_SETTING_BPS_START size OPTION_SETTING_BPS_LENGTH]; + define region OPTION_SETTING_BPS_SEC = mem:[from OPTION_SETTING_BPS_SEC_START size OPTION_SETTING_BPS_SEC_LENGTH]; + define region OPTION_SETTING_OTP_PBPS_SEC = mem:[from OPTION_SETTING_OTP_PBPS_SEC_START size OPTION_SETTING_OTP_PBPS_SEC_LENGTH]; + define region OPTION_SETTING_OTP_PBPS = mem:[from OPTION_SETTING_OTP_PBPS_START size OPTION_SETTING_OTP_PBPS_LENGTH]; + define region CTCM = mem:[from CTCM_START size CTCM_LENGTH]; + define region STCM = mem:[from STCM_START size STCM_LENGTH]; +/***** OSPI0_CS1 memory section allocations ******/ +define section __ddsc_OSPI0_CS1_START {public __ddsc_OSPI0_CS1_START:}; +keep {section __ddsc_OSPI0_CS1_START}; +define section __ddsc_OSPI0_CS1_END {public __ddsc_OSPI0_CS1_END:}; +keep {section __ddsc_OSPI0_CS1_END}; +define block ospi0_cs1_BLOCK with fixed order { + block .ospi0_cs1.startof with fixed order { + block __ddsc_OSPI0_CS1_START {section __ddsc_OSPI0_CS1_START},}, + /* sdram initialized from ospi0_cs1 */ + block __ospi0_cs1_init_sdram_from_ospi0_cs1 with fixed order { + /* section.sdram.from_ospi0_cs1 */ + section .sdram_from_ospi0_cs1_init, + /* section.sdram.code_from_ospi0_cs1 */ + section .sdram_code_from_ospi0_cs1_init}, + /* ospi0_cs0 initialized from ospi0_cs1 */ + block __ospi0_cs1_init_ospi0_cs0_from_ospi0_cs1 with fixed order { + /* section.ospi0_cs0.from_ospi0_cs1 */ + section .ospi0_cs0_from_ospi0_cs1_init, + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + section .ospi0_cs0_code_from_ospi0_cs1_init}, + /* ospi1_cs0 initialized from ospi0_cs1 */ + block __ospi0_cs1_init_ospi1_cs0_from_ospi0_cs1 with fixed order { + /* section.ospi1_cs0.from_ospi0_cs1 */ + section .ospi1_cs0_from_ospi0_cs1_init, + /* section.ospi1_cs0.code_from_ospi0_cs1 */ + section .ospi1_cs0_code_from_ospi0_cs1_init}, + /* ctcm initialized from ospi0_cs1 */ + block __ospi0_cs1_init_ctcm_from_ospi0_cs1 with fixed order { + /* section.ctcm.from_ospi0_cs1 */ + section .ctcm_from_ospi0_cs1_init, + /* section.ctcm.code_from_ospi0_cs1 */ + section .ctcm_code_from_ospi0_cs1_init}, + /* stcm initialized from ospi0_cs1 */ + block __ospi0_cs1_init_stcm_from_ospi0_cs1 with fixed order { + /* section.stcm.from_ospi0_cs1 */ + section .stcm_from_ospi0_cs1_init, + /* section.stcm.code_from_ospi0_cs1 */ + section .stcm_code_from_ospi0_cs1_init}, + /* ram initialized from ospi0_cs1 */ + block __ospi0_cs1_init_ram_from_ospi0_cs1 with fixed order { + /* section.ram.from_ospi0_cs1 */ + section .ram_from_ospi0_cs1_init, + /* section.ram.code_from_ospi0_cs1 */ + section .ram_code_from_ospi0_cs1_init}, + block __ospi0_cs1_readonly with fixed order { + /* section.ospi0_cs1.readonly */ + section .ospi0_cs1, + /* section.ospi0_cs1.code */ + section .ospi0_cs1_code}, + block __ospi0_cs1_noinit with fixed order { + /* section.ospi0_cs1.noinit */ + section .ospi0_cs1_noinit}, + block .ospi0_cs1.endof with alignment = 512, fixed order { + block __ddsc_OSPI0_CS1_END {section __ddsc_OSPI0_CS1_END},}, +}; + +place in OSPI0_CS1 { block ospi0_cs1_BLOCK }; +/***** OSPI1_CS1 memory section allocations ******/ +define section __ddsc_OSPI1_CS1_START {public __ddsc_OSPI1_CS1_START:}; +keep {section __ddsc_OSPI1_CS1_START}; +define section __ddsc_OSPI1_CS1_END {public __ddsc_OSPI1_CS1_END:}; +keep {section __ddsc_OSPI1_CS1_END}; +define block ospi1_cs1_BLOCK with fixed order { + block .ospi1_cs1.startof with fixed order { + block __ddsc_OSPI1_CS1_START {section __ddsc_OSPI1_CS1_START},}, + /* sdram initialized from ospi1_cs1 */ + block __ospi1_cs1_init_sdram_from_ospi1_cs1 with fixed order { + /* section.sdram.from_ospi1_cs1 */ + section .sdram_from_ospi1_cs1_init, + /* section.sdram.code_from_ospi1_cs1 */ + section .sdram_code_from_ospi1_cs1_init}, + /* ospi0_cs0 initialized from ospi1_cs1 */ + block __ospi1_cs1_init_ospi0_cs0_from_ospi1_cs1 with fixed order { + /* section.ospi0_cs0.from_ospi1_cs1 */ + section .ospi0_cs0_from_ospi1_cs1_init, + /* section.ospi0_cs0.code_from_ospi1_cs1 */ + section .ospi0_cs0_code_from_ospi1_cs1_init}, + /* ospi1_cs0 initialized from ospi1_cs1 */ + block __ospi1_cs1_init_ospi1_cs0_from_ospi1_cs1 with fixed order { + /* section.ospi1_cs0.from_ospi1_cs1 */ + section .ospi1_cs0_from_ospi1_cs1_init, + /* section.ospi1_cs0.code_from_ospi1_cs1 */ + section .ospi1_cs0_code_from_ospi1_cs1_init}, + /* ctcm initialized from ospi1_cs1 */ + block __ospi1_cs1_init_ctcm_from_ospi1_cs1 with fixed order { + /* section.ctcm.from_ospi1_cs1 */ + section .ctcm_from_ospi1_cs1_init, + /* section.ctcm.code_from_ospi1_cs1 */ + section .ctcm_code_from_ospi1_cs1_init}, + /* stcm initialized from ospi1_cs1 */ + block __ospi1_cs1_init_stcm_from_ospi1_cs1 with fixed order { + /* section.stcm.from_ospi1_cs1 */ + section .stcm_from_ospi1_cs1_init, + /* section.stcm.code_from_ospi1_cs1 */ + section .stcm_code_from_ospi1_cs1_init}, + /* ram initialized from ospi1_cs1 */ + block __ospi1_cs1_init_ram_from_ospi1_cs1 with fixed order { + /* section.ram.from_ospi1_cs1 */ + section .ram_from_ospi1_cs1_init, + /* section.ram.code_from_ospi1_cs1 */ + section .ram_code_from_ospi1_cs1_init}, + block __ospi1_cs1_readonly with fixed order { + /* section.ospi1_cs1.readonly */ + section .ospi1_cs1, + /* section.ospi1_cs1.code */ + section .ospi1_cs1_code}, + block __ospi1_cs1_noinit with fixed order { + /* section.ospi1_cs1.noinit */ + section .ospi1_cs1_noinit}, + block .ospi1_cs1.endof with alignment = 512, fixed order { + block __ddsc_OSPI1_CS1_END {section __ddsc_OSPI1_CS1_END},}, +}; + +place in OSPI1_CS1 { block ospi1_cs1_BLOCK }; +/***** SDRAM memory section allocations ******/ +define section __ddsc_SDRAM_START {public __ddsc_SDRAM_START:}; +keep {section __ddsc_SDRAM_START}; +define section __ddsc_SDRAM_END {public __ddsc_SDRAM_END:}; +keep {section __ddsc_SDRAM_END}; +define block sdram_BLOCK with fixed order { + block .sdram.startof with fixed order { + block __ddsc_SDRAM_START {section __ddsc_SDRAM_START},}, + /* sdram initialized from ospi0_cs1 */ + block __sdram_from_ospi0_cs1 with fixed order { + /* section.sdram.from_ospi0_cs1 */ + section .sdram_from_ospi0_cs1, + /* section.sdram.code_from_ospi0_cs1 */ + section .sdram_code_from_ospi0_cs1}, + /* sdram initialized from ospi1_cs1 */ + block __sdram_from_ospi1_cs1 with fixed order { + /* section.sdram.from_ospi1_cs1 */ + section .sdram_from_ospi1_cs1, + /* section.sdram.code_from_ospi1_cs1 */ + section .sdram_code_from_ospi1_cs1}, + /* sdram initialized from data_flash */ + block __sdram_from_data_flash with fixed order { + /* section.sdram.from_data_flash */ + section .sdram_from_data_flash, + /* section.sdram.code_from_data_flash */ + section .sdram_code_from_data_flash}, + /* sdram initialized from flash */ + block __sdram_from_flash with fixed order { + /* section.sdram.from_flash */ + section .sdram_from_flash, + /* section.sdram.code_from_flash */ + section .sdram_code_from_flash}, + /* Non-initialized, non-cached sdram */ + block __sdram_noinit_nocache with alignment = 32, fixed order { + /* section.sdram.noinit_nocache */ + section .sdram_noinit_nocache}, + /* Zeroed, non-cached sdram */ + block __sdram_zero_nocache with end alignment = 32, fixed order { + /* section.sdram.zero_nocache */ + section .sdram_nocache}, + /* Non-initialized sdram */ + block __sdram_noinit with fixed order { + /* section.sdram.noinit */ + section .sdram_noinit}, + /* Zeroed sdram */ + block __sdram_zero with fixed order { + /* section.sdram.zero */ + section .sdram}, + block .sdram.endof with alignment = 512, fixed order { + block __ddsc_SDRAM_END {section __ddsc_SDRAM_END},}, +}; + +place in SDRAM { block sdram_BLOCK }; +/***** OSPI0_CS0 memory section allocations ******/ +define section __ddsc_OSPI0_CS0_START {public __ddsc_OSPI0_CS0_START:}; +keep {section __ddsc_OSPI0_CS0_START}; +define section __ddsc_OSPI0_CS0_END {public __ddsc_OSPI0_CS0_END:}; +keep {section __ddsc_OSPI0_CS0_END}; +define block ospi0_cs0_BLOCK with fixed order { + block .ospi0_cs0.startof with fixed order { + block __ddsc_OSPI0_CS0_START {section __ddsc_OSPI0_CS0_START},}, + /* ospi0_cs0 initialized from ospi0_cs1 */ + block __ospi0_cs0_from_ospi0_cs1 with fixed order { + /* section.ospi0_cs0.from_ospi0_cs1 */ + section .ospi0_cs0_from_ospi0_cs1, + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + section .ospi0_cs0_code_from_ospi0_cs1}, + /* ospi0_cs0 initialized from ospi1_cs1 */ + block __ospi0_cs0_from_ospi1_cs1 with fixed order { + /* section.ospi0_cs0.from_ospi1_cs1 */ + section .ospi0_cs0_from_ospi1_cs1, + /* section.ospi0_cs0.code_from_ospi1_cs1 */ + section .ospi0_cs0_code_from_ospi1_cs1}, + /* ospi0_cs0 initialized from data_flash */ + block __ospi0_cs0_from_data_flash with fixed order { + /* section.ospi0_cs0.from_data_flash */ + section .ospi0_cs0_from_data_flash, + /* section.ospi0_cs0.code_from_data_flash */ + section .ospi0_cs0_code_from_data_flash}, + /* ospi0_cs0 initialized from flash */ + block __ospi0_cs0_from_flash with fixed order { + /* section.ospi0_cs0.from_flash */ + section .ospi0_cs0_from_flash, + /* section.ospi0_cs0.code_from_flash */ + section .ospi0_cs0_code_from_flash}, + /* Non-initialized, non-cached ospi0_cs0 */ + block __ospi0_cs0_noinit_nocache with alignment = 32, fixed order { + /* section.ospi0_cs0.noinit_nocache */ + section .ospi0_cs0_noinit_nocache}, + /* Zeroed, non-cached ospi0_cs0 */ + block __ospi0_cs0_zero_nocache with end alignment = 32, fixed order { + /* section.ospi0_cs0.zero_nocache */ + section .ospi0_cs0_nocache}, + /* Non-initialized ospi0_cs0 */ + block __ospi0_cs0_noinit with fixed order { + /* section.ospi0_cs0.noinit */ + section .ospi0_cs0_noinit}, + /* Zeroed ospi0_cs0 */ + block __ospi0_cs0_zero with fixed order { + /* section.ospi0_cs0.zero */ + section .ospi0_cs0}, + block .ospi0_cs0.endof with alignment = 512, fixed order { + block __ddsc_OSPI0_CS0_END {section __ddsc_OSPI0_CS0_END},}, +}; + +place in OSPI0_CS0 { block ospi0_cs0_BLOCK }; +/***** OSPI1_CS0 memory section allocations ******/ +define section __ddsc_OSPI1_CS0_START {public __ddsc_OSPI1_CS0_START:}; +keep {section __ddsc_OSPI1_CS0_START}; +define section __ddsc_OSPI1_CS0_END {public __ddsc_OSPI1_CS0_END:}; +keep {section __ddsc_OSPI1_CS0_END}; +define block ospi1_cs0_BLOCK with fixed order { + block .ospi1_cs0.startof with fixed order { + block __ddsc_OSPI1_CS0_START {section __ddsc_OSPI1_CS0_START},}, + /* ospi1_cs0 initialized from ospi0_cs1 */ + block __ospi1_cs0_from_ospi0_cs1 with fixed order { + /* section.ospi1_cs0.from_ospi0_cs1 */ + section .ospi1_cs0_from_ospi0_cs1, + /* section.ospi1_cs0.code_from_ospi0_cs1 */ + section .ospi1_cs0_code_from_ospi0_cs1}, + /* ospi1_cs0 initialized from ospi1_cs1 */ + block __ospi1_cs0_from_ospi1_cs1 with fixed order { + /* section.ospi1_cs0.from_ospi1_cs1 */ + section .ospi1_cs0_from_ospi1_cs1, + /* section.ospi1_cs0.code_from_ospi1_cs1 */ + section .ospi1_cs0_code_from_ospi1_cs1}, + /* ospi1_cs0 initialized from data_flash */ + block __ospi1_cs0_from_data_flash with fixed order { + /* section.ospi1_cs0.from_data_flash */ + section .ospi1_cs0_from_data_flash, + /* section.ospi1_cs0.code_from_data_flash */ + section .ospi1_cs0_code_from_data_flash}, + /* ospi1_cs0 initialized from flash */ + block __ospi1_cs0_from_flash with fixed order { + /* section.ospi1_cs0.from_flash */ + section .ospi1_cs0_from_flash, + /* section.ospi1_cs0.code_from_flash */ + section .ospi1_cs0_code_from_flash}, + /* Non-initialized, non-cached ospi1_cs0 */ + block __ospi1_cs0_noinit_nocache with alignment = 32, fixed order { + /* section.ospi1_cs0.noinit_nocache */ + section .ospi1_cs0_noinit_nocache}, + /* Zeroed, non-cached ospi1_cs0 */ + block __ospi1_cs0_zero_nocache with end alignment = 32, fixed order { + /* section.ospi1_cs0.zero_nocache */ + section .ospi1_cs0_nocache}, + /* Non-initialized ospi1_cs0 */ + block __ospi1_cs0_noinit with fixed order { + /* section.ospi1_cs0.noinit */ + section .ospi1_cs0_noinit}, + /* Zeroed ospi1_cs0 */ + block __ospi1_cs0_zero with fixed order { + /* section.ospi1_cs0.zero */ + section .ospi1_cs0}, + block .ospi1_cs0.endof with alignment = 512, fixed order { + block __ddsc_OSPI1_CS0_END {section __ddsc_OSPI1_CS0_END},}, +}; + +place in OSPI1_CS0 { block ospi1_cs0_BLOCK }; +/***** DATA_FLASH memory section allocations ******/ +define section __ddsc_DATA_FLASH_START {public __ddsc_DATA_FLASH_START:}; +keep {section __ddsc_DATA_FLASH_START}; +define section __ddsc_DATA_FLASH_END {public __ddsc_DATA_FLASH_END:}; +keep {section __ddsc_DATA_FLASH_END}; +define block data_flash_BLOCK with fixed order { + block .data_flash.startof with fixed order { + block __ddsc_DATA_FLASH_START {section __ddsc_DATA_FLASH_START},}, + /* sdram initialized from data_flash */ + block __data_flash_init_sdram_from_data_flash with fixed order { + /* section.sdram.from_data_flash */ + section .sdram_from_data_flash_init, + /* section.sdram.code_from_data_flash */ + section .sdram_code_from_data_flash_init}, + /* ospi0_cs0 initialized from data_flash */ + block __data_flash_init_ospi0_cs0_from_data_flash with fixed order { + /* section.ospi0_cs0.from_data_flash */ + section .ospi0_cs0_from_data_flash_init, + /* section.ospi0_cs0.code_from_data_flash */ + section .ospi0_cs0_code_from_data_flash_init}, + /* ospi1_cs0 initialized from data_flash */ + block __data_flash_init_ospi1_cs0_from_data_flash with fixed order { + /* section.ospi1_cs0.from_data_flash */ + section .ospi1_cs0_from_data_flash_init, + /* section.ospi1_cs0.code_from_data_flash */ + section .ospi1_cs0_code_from_data_flash_init}, + /* ctcm initialized from data_flash */ + block __data_flash_init_ctcm_from_data_flash with fixed order { + /* section.ctcm.from_data_flash */ + section .ctcm_from_data_flash_init, + /* section.ctcm.code_from_data_flash */ + section .ctcm_code_from_data_flash_init}, + /* stcm initialized from data_flash */ + block __data_flash_init_stcm_from_data_flash with fixed order { + /* section.stcm.from_data_flash */ + section .stcm_from_data_flash_init, + /* section.stcm.code_from_data_flash */ + section .stcm_code_from_data_flash_init}, + /* ram initialized from data_flash */ + block __data_flash_init_ram_from_data_flash with fixed order { + /* section.ram.from_data_flash */ + section .ram_from_data_flash_init, + /* section.ram.code_from_data_flash */ + section .ram_code_from_data_flash_init}, + block __data_flash_readonly with fixed order { + /* section.data_flash.readonly */ + section .data_flash, + /* section.data_flash.code */ + section .data_flash_code}, + block __data_flash_noinit with fixed order { + /* section.data_flash.noinit */ + section .data_flash_noinit}, + block .data_flash.endof with alignment = 1024, fixed order { + block __ddsc_DATA_FLASH_END {section __ddsc_DATA_FLASH_END},}, +}; + +place in DATA_FLASH { block data_flash_BLOCK }; +/***** CTCM memory section allocations ******/ +define section __ddsc_CTCM_START {public __ddsc_CTCM_START:}; +keep {section __ddsc_CTCM_START}; +define section __ddsc_CTCM_END {public __ddsc_CTCM_END:}; +keep {section __ddsc_CTCM_END}; +define block ctcm_BLOCK with fixed order { + block .ctcm.startof with fixed order { + block __ddsc_CTCM_START {section __ddsc_CTCM_START},}, + /* ctcm initialized from ospi0_cs1 */ + block __ctcm_from_ospi0_cs1 with fixed order { + /* section.ctcm.from_ospi0_cs1 */ + section .ctcm_from_ospi0_cs1, + /* section.ctcm.code_from_ospi0_cs1 */ + section .ctcm_code_from_ospi0_cs1}, + /* ctcm initialized from ospi1_cs1 */ + block __ctcm_from_ospi1_cs1 with fixed order { + /* section.ctcm.from_ospi1_cs1 */ + section .ctcm_from_ospi1_cs1, + /* section.ctcm.code_from_ospi1_cs1 */ + section .ctcm_code_from_ospi1_cs1}, + /* ctcm initialized from data_flash */ + block __ctcm_from_data_flash with fixed order { + /* section.ctcm.from_data_flash */ + section .ctcm_from_data_flash, + /* section.ctcm.code_from_data_flash */ + section .ctcm_code_from_data_flash}, + /* ctcm initialized from flash */ + block __ctcm_from_flash with fixed order { + /* section.ctcm.from_flash */ + section .ctcm_from_flash, + /* section.ctcm.code_from_flash */ + section .ctcm_code_from_flash}, + /* Non-initialized ctcm */ + block __ctcm_noinit with fixed order { + /* section.ctcm.noinit */ + section .ctcm_noinit}, + /* Zeroed ctcm */ + block __ctcm_zero with fixed order { + /* section.ctcm.zero */ + section .ctcm}, + block .ctcm.endof with alignment = 8192, fixed order { + block __ddsc_CTCM_END {section __ddsc_CTCM_END},}, +}; + +place in CTCM { block ctcm_BLOCK }; +/***** STCM memory section allocations ******/ +define section __ddsc_STCM_START {public __ddsc_STCM_START:}; +keep {section __ddsc_STCM_START}; +define section __ddsc_STCM_END {public __ddsc_STCM_END:}; +keep {section __ddsc_STCM_END}; +define block stcm_BLOCK with fixed order { + block .stcm.startof with fixed order { + block __ddsc_STCM_START {section __ddsc_STCM_START},}, + /* stcm initialized from ospi0_cs1 */ + block __stcm_from_ospi0_cs1 with fixed order { + /* section.stcm.from_ospi0_cs1 */ + section .stcm_from_ospi0_cs1, + /* section.stcm.code_from_ospi0_cs1 */ + section .stcm_code_from_ospi0_cs1}, + /* stcm initialized from ospi1_cs1 */ + block __stcm_from_ospi1_cs1 with fixed order { + /* section.stcm.from_ospi1_cs1 */ + section .stcm_from_ospi1_cs1, + /* section.stcm.code_from_ospi1_cs1 */ + section .stcm_code_from_ospi1_cs1}, + /* stcm initialized from data_flash */ + block __stcm_from_data_flash with fixed order { + /* section.stcm.from_data_flash */ + section .stcm_from_data_flash, + /* section.stcm.code_from_data_flash */ + section .stcm_code_from_data_flash}, + /* stcm initialized from flash */ + block __stcm_from_flash with fixed order { + /* section.stcm.from_flash */ + section .stcm_from_flash, + /* section.stcm.code_from_flash */ + section .stcm_code_from_flash}, + /* Non-initialized stcm */ + block __stcm_noinit with fixed order { + /* section.stcm.noinit */ + section .stcm_noinit}, + /* Zeroed stcm */ + block __stcm_zero with fixed order { + /* section.stcm.zero */ + section .stcm}, + block .stcm.endof with alignment = 8192, fixed order { + block __ddsc_STCM_END {section __ddsc_STCM_END},}, +}; + +place in STCM { block stcm_BLOCK }; +/***** FLASH memory section allocations ******/ +define section __ddsc_FLASH_START {public __ddsc_FLASH_START:}; +keep {section __ddsc_FLASH_START}; +define section _VECTORS {public _VECTORS:}; +keep {section _VECTORS}; +define section __ddsc_FLASH_END {public __ddsc_FLASH_END:}; +keep {section __ddsc_FLASH_END}; +define section __sau_ddsc_FLASH_NSC {public __sau_ddsc_FLASH_NSC:}; +keep {section __sau_ddsc_FLASH_NSC}; +define block flash_BLOCK with fixed order { + block .flash.startof with fixed order { + block __ddsc_FLASH_START {section __ddsc_FLASH_START},}, + /* MCU vector table */ + block __flash_vectors with fixed order { + block _VECTORS {section _VECTORS}, + section .fixed_vectors, + section .application_vectors}, + block __flash_noinit with fixed order { + /* section.flash.noinit */ + section .flash_noinit}, + /* sdram initialized from flash */ + block __flash_init_sdram_from_flash with fixed order { + /* section.sdram.from_flash */ + section .sdram_from_flash_init, + /* section.sdram.code_from_flash */ + section .sdram_code_from_flash_init}, + /* ospi0_cs0 initialized from flash */ + block __flash_init_ospi0_cs0_from_flash with fixed order { + /* section.ospi0_cs0.from_flash */ + section .ospi0_cs0_from_flash_init, + /* section.ospi0_cs0.code_from_flash */ + section .ospi0_cs0_code_from_flash_init}, + /* ospi1_cs0 initialized from flash */ + block __flash_init_ospi1_cs0_from_flash with fixed order { + /* section.ospi1_cs0.from_flash */ + section .ospi1_cs0_from_flash_init, + /* section.ospi1_cs0.code_from_flash */ + section .ospi1_cs0_code_from_flash_init}, + /* ctcm initialized from flash */ + block __flash_init_ctcm_from_flash with fixed order { + /* section.ctcm.from_flash */ + section .ctcm_from_flash_init, + /* section.ctcm.code_from_flash */ + section .ctcm_code_from_flash_init}, + /* stcm initialized from flash */ + block __flash_init_stcm_from_flash with fixed order { + /* section.stcm.from_flash */ + section .stcm_from_flash_init, + /* section.stcm.code_from_flash */ + section .stcm_code_from_flash_init}, + /* ram initialized from flash */ + block __flash_init_ram_from_flash with fixed order { + /* section.ram.from_flash */ + section .ram_from_flash_init, + /* section.ram.code_from_flash */ + section .ram_code_from_flash_init, + section .data*_init, + section vtable_init}, + block __flash_readonly with fixed order { + /* section.flash.readonly */ + section .flash, + /* section.flash.code */ + section .flash_code, + ro code , + ro data , + section .mcuboot_sce9_key, + section .version}, + + block .flash.endof with alignment = 32768, fixed order { + block __ddsc_FLASH_END {section __ddsc_FLASH_END},}, + block .flash.flat_nsc with alignment = 32768, fixed order { + block __sau_ddsc_FLASH_NSC {section __sau_ddsc_FLASH_NSC},}, +}; + +place at start of FLASH { block flash_BLOCK }; +/***** RAM memory section allocations ******/ +define section __ddsc_RAM_START {public __ddsc_RAM_START:}; +keep {section __ddsc_RAM_START}; +define section __ddsc_RAM_END {public __ddsc_RAM_END:}; +keep {section __ddsc_RAM_END}; +define section __sau_ddsc_RAM_NSC {public __sau_ddsc_RAM_NSC:}; +keep {section __sau_ddsc_RAM_NSC}; +define block ram_BLOCK with fixed order { + block .ram.startof with fixed order { + block __ddsc_RAM_START {section __ddsc_RAM_START},}, + block __ram_dtc_vector with fixed order { + section .fsp_dtc_vector_table}, + /* ram initialized from ospi0_cs1 */ + block __ram_from_ospi0_cs1 with fixed order { + /* section.ram.from_ospi0_cs1 */ + section .ram_from_ospi0_cs1, + /* section.ram.code_from_ospi0_cs1 */ + section .ram_code_from_ospi0_cs1}, + /* ram initialized from ospi1_cs1 */ + block __ram_from_ospi1_cs1 with fixed order { + /* section.ram.from_ospi1_cs1 */ + section .ram_from_ospi1_cs1, + /* section.ram.code_from_ospi1_cs1 */ + section .ram_code_from_ospi1_cs1}, + /* ram initialized from data_flash */ + block __ram_from_data_flash with fixed order { + /* section.ram.from_data_flash */ + section .ram_from_data_flash, + /* section.ram.code_from_data_flash */ + section .ram_code_from_data_flash}, + /* ram initialized from flash */ + block __ram_from_flash with fixed order { + /* section.ram.from_flash */ + section .ram_from_flash, + /* section.ram.code_from_flash */ + section .ram_code_from_flash, + section .data*, + section vtable}, + /* Non-initialized, non-cached ram */ + block __ram_noinit_nocache with alignment = 32, fixed order { + /* section.ram.noinit_nocache */ + section .ram_noinit_nocache}, + /* Zeroed, non-cached ram */ + block __ram_zero_nocache with end alignment = 32, fixed order { + /* section.ram.zero_nocache */ + section .ram_nocache}, + /* Non-initialized ram */ + block __ram_noinit with fixed order { + /* section.ram.noinit */ + block HEAP { section .bss object * symbol g_heap}, + section .bss object * symbol g_main_stack, + section .ram_noinit, + section .noinit}, + /* Zeroed ram */ + block __ram_zero with fixed order { + /* section.ram.zero */ + section .ram, + zi }, + /* Thread Stacks */ + block __ram_thread_stack with alignment = 8, fixed order { + section .stack?*}, + + block .ram.endof with alignment = 8192, fixed order { + block __ddsc_RAM_END {section __ddsc_RAM_END},}, + block .ram.flat_nsc with alignment = 8192, fixed order { + block __sau_ddsc_RAM_NSC {section __sau_ddsc_RAM_NSC},}, +}; + +place at start of RAM { block ram_BLOCK }; +/***** OPTION_SETTING_OFS0 memory section allocations ******/ +define section __ddsc_OPTION_SETTING_OFS0_START {public __ddsc_OPTION_SETTING_OFS0_START:}; +keep {section __ddsc_OPTION_SETTING_OFS0_START}; +define section __ddsc_OPTION_SETTING_OFS0_END {public __ddsc_OPTION_SETTING_OFS0_END:}; +keep {section __ddsc_OPTION_SETTING_OFS0_END}; +define block option_setting_ofs0_BLOCK with fixed order { + block .option_setting_ofs0.startof with fixed order { + block __ddsc_OPTION_SETTING_OFS0_START {section __ddsc_OPTION_SETTING_OFS0_START},}, + /* Option Function Select Register 0 */ + block __option_setting_ofs0_reg with fixed order { + section .option_setting_ofs0}, + block .option_setting_ofs0.endof with fixed order { + block __ddsc_OPTION_SETTING_OFS0_END {section __ddsc_OPTION_SETTING_OFS0_END},}, +}; + +place in OPTION_SETTING_OFS0 { block option_setting_ofs0_BLOCK }; +/***** OPTION_SETTING_OFS2 memory section allocations ******/ +define section __ddsc_OPTION_SETTING_OFS2_START {public __ddsc_OPTION_SETTING_OFS2_START:}; +keep {section __ddsc_OPTION_SETTING_OFS2_START}; +define section __ddsc_OPTION_SETTING_OFS2_END {public __ddsc_OPTION_SETTING_OFS2_END:}; +keep {section __ddsc_OPTION_SETTING_OFS2_END}; +define block option_setting_ofs2_BLOCK with fixed order { + block .option_setting_ofs2.startof with fixed order { + block __ddsc_OPTION_SETTING_OFS2_START {section __ddsc_OPTION_SETTING_OFS2_START},}, + /* Option Function Select Register 2 */ + block __option_setting_ofs2_reg with fixed order { + section .option_setting_ofs2}, + block .option_setting_ofs2.endof with fixed order { + block __ddsc_OPTION_SETTING_OFS2_END {section __ddsc_OPTION_SETTING_OFS2_END},}, +}; + +place in OPTION_SETTING_OFS2 { block option_setting_ofs2_BLOCK }; +/***** OPTION_SETTING_SAS memory section allocations ******/ +define section __ddsc_OPTION_SETTING_SAS_START {public __ddsc_OPTION_SETTING_SAS_START:}; +keep {section __ddsc_OPTION_SETTING_SAS_START}; +define section __ddsc_OPTION_SETTING_SAS_END {public __ddsc_OPTION_SETTING_SAS_END:}; +keep {section __ddsc_OPTION_SETTING_SAS_END}; +define block option_setting_sas_BLOCK with fixed order { + block .option_setting_sas.startof with fixed order { + block __ddsc_OPTION_SETTING_SAS_START {section __ddsc_OPTION_SETTING_SAS_START},}, + /* Startup Area Setting Register */ + block __option_setting_sas_reg with fixed order { + section .option_setting_sas}, + block .option_setting_sas.endof with fixed order { + block __ddsc_OPTION_SETTING_SAS_END {section __ddsc_OPTION_SETTING_SAS_END},}, +}; + +place in OPTION_SETTING_SAS { block option_setting_sas_BLOCK }; +/***** OPTION_SETTING_OFS1 memory section allocations ******/ +define section __ddsc_OPTION_SETTING_OFS1_START {public __ddsc_OPTION_SETTING_OFS1_START:}; +keep {section __ddsc_OPTION_SETTING_OFS1_START}; +define section __ddsc_OPTION_SETTING_OFS1_END {public __ddsc_OPTION_SETTING_OFS1_END:}; +keep {section __ddsc_OPTION_SETTING_OFS1_END}; +define block option_setting_ofs1_BLOCK with fixed order { + block .option_setting_ofs1.startof with fixed order { + block __ddsc_OPTION_SETTING_OFS1_START {section __ddsc_OPTION_SETTING_OFS1_START},}, + /* Option Function Select Register 1 */ + block __option_setting_ofs1_reg with fixed order { + section .option_setting_ofs1}, + block .option_setting_ofs1.endof with fixed order { + block __ddsc_OPTION_SETTING_OFS1_END {section __ddsc_OPTION_SETTING_OFS1_END},}, +}; + +place in OPTION_SETTING_OFS1 { block option_setting_ofs1_BLOCK }; +/***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ +define section __ddsc_OPTION_SETTING_OFS1_SEC_START {public __ddsc_OPTION_SETTING_OFS1_SEC_START:}; +keep {section __ddsc_OPTION_SETTING_OFS1_SEC_START}; +define section __ddsc_OPTION_SETTING_OFS1_SEC_END {public __ddsc_OPTION_SETTING_OFS1_SEC_END:}; +keep {section __ddsc_OPTION_SETTING_OFS1_SEC_END}; +define block option_setting_ofs1_sec_BLOCK with fixed order { + block .option_setting_ofs1_sec.startof with fixed order { + block __ddsc_OPTION_SETTING_OFS1_SEC_START {section __ddsc_OPTION_SETTING_OFS1_SEC_START},}, + /* Option Function Select Register 1 Secure */ + block __option_setting_ofs1_sec_reg with fixed order { + section .option_setting_ofs1_sec}, + block .option_setting_ofs1_sec.endof with fixed order { + block __ddsc_OPTION_SETTING_OFS1_SEC_END {section __ddsc_OPTION_SETTING_OFS1_SEC_END},}, +}; + +place in OPTION_SETTING_OFS1_SEC { block option_setting_ofs1_sec_BLOCK }; +/***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ +define section __ddsc_OPTION_SETTING_OFS1_SEL_START {public __ddsc_OPTION_SETTING_OFS1_SEL_START:}; +keep {section __ddsc_OPTION_SETTING_OFS1_SEL_START}; +define section __ddsc_OPTION_SETTING_OFS1_SEL_END {public __ddsc_OPTION_SETTING_OFS1_SEL_END:}; +keep {section __ddsc_OPTION_SETTING_OFS1_SEL_END}; +define block option_setting_ofs1_sel_BLOCK with fixed order { + block .option_setting_ofs1_sel.startof with fixed order { + block __ddsc_OPTION_SETTING_OFS1_SEL_START {section __ddsc_OPTION_SETTING_OFS1_SEL_START},}, + /* OFS1 Register Select */ + block __option_setting_ofs1_sel_reg with fixed order { + section .option_setting_ofs1_sel}, + block .option_setting_ofs1_sel.endof with fixed order { + block __ddsc_OPTION_SETTING_OFS1_SEL_END {section __ddsc_OPTION_SETTING_OFS1_SEL_END},}, +}; + +place in OPTION_SETTING_OFS1_SEL { block option_setting_ofs1_sel_BLOCK }; +/***** OPTION_SETTING_OFS3 memory section allocations ******/ +define section __ddsc_OPTION_SETTING_OFS3_START {public __ddsc_OPTION_SETTING_OFS3_START:}; +keep {section __ddsc_OPTION_SETTING_OFS3_START}; +define section __ddsc_OPTION_SETTING_OFS3_END {public __ddsc_OPTION_SETTING_OFS3_END:}; +keep {section __ddsc_OPTION_SETTING_OFS3_END}; +define block option_setting_ofs3_BLOCK with fixed order { + block .option_setting_ofs3.startof with fixed order { + block __ddsc_OPTION_SETTING_OFS3_START {section __ddsc_OPTION_SETTING_OFS3_START},}, + /* Option Function Select Register 3 */ + block __option_setting_ofs3_reg with fixed order { + section .option_setting_ofs3}, + block .option_setting_ofs3.endof with fixed order { + block __ddsc_OPTION_SETTING_OFS3_END {section __ddsc_OPTION_SETTING_OFS3_END},}, +}; + +place in OPTION_SETTING_OFS3 { block option_setting_ofs3_BLOCK }; +/***** OPTION_SETTING_OFS3_SEC memory section allocations ******/ +define section __ddsc_OPTION_SETTING_OFS3_SEC_START {public __ddsc_OPTION_SETTING_OFS3_SEC_START:}; +keep {section __ddsc_OPTION_SETTING_OFS3_SEC_START}; +define section __ddsc_OPTION_SETTING_OFS3_SEC_END {public __ddsc_OPTION_SETTING_OFS3_SEC_END:}; +keep {section __ddsc_OPTION_SETTING_OFS3_SEC_END}; +define block option_setting_ofs3_sec_BLOCK with fixed order { + block .option_setting_ofs3_sec.startof with fixed order { + block __ddsc_OPTION_SETTING_OFS3_SEC_START {section __ddsc_OPTION_SETTING_OFS3_SEC_START},}, + /* Option Function Select Register 3 Secure */ + block __option_setting_ofs3_sec_reg with fixed order { + section .option_setting_ofs3_sec}, + block .option_setting_ofs3_sec.endof with fixed order { + block __ddsc_OPTION_SETTING_OFS3_SEC_END {section __ddsc_OPTION_SETTING_OFS3_SEC_END},}, +}; + +place in OPTION_SETTING_OFS3_SEC { block option_setting_ofs3_sec_BLOCK }; +/***** OPTION_SETTING_OFS3_SEL memory section allocations ******/ +define section __ddsc_OPTION_SETTING_OFS3_SEL_START {public __ddsc_OPTION_SETTING_OFS3_SEL_START:}; +keep {section __ddsc_OPTION_SETTING_OFS3_SEL_START}; +define section __ddsc_OPTION_SETTING_OFS3_SEL_END {public __ddsc_OPTION_SETTING_OFS3_SEL_END:}; +keep {section __ddsc_OPTION_SETTING_OFS3_SEL_END}; +define block option_setting_ofs3_sel_BLOCK with fixed order { + block .option_setting_ofs3_sel.startof with fixed order { + block __ddsc_OPTION_SETTING_OFS3_SEL_START {section __ddsc_OPTION_SETTING_OFS3_SEL_START},}, + /* OFS3 Register Select */ + block __option_setting_ofs3_sel_reg with fixed order { + section .option_setting_ofs3_sel}, + block .option_setting_ofs3_sel.endof with fixed order { + block __ddsc_OPTION_SETTING_OFS3_SEL_END {section __ddsc_OPTION_SETTING_OFS3_SEL_END},}, +}; + +place in OPTION_SETTING_OFS3_SEL { block option_setting_ofs3_sel_BLOCK }; +/***** OPTION_SETTING_BPS memory section allocations ******/ +define section __ddsc_OPTION_SETTING_BPS_START {public __ddsc_OPTION_SETTING_BPS_START:}; +keep {section __ddsc_OPTION_SETTING_BPS_START}; +define section __ddsc_OPTION_SETTING_BPS_END {public __ddsc_OPTION_SETTING_BPS_END:}; +keep {section __ddsc_OPTION_SETTING_BPS_END}; +define block option_setting_bps_BLOCK with fixed order { + block .option_setting_bps.startof with fixed order { + block __ddsc_OPTION_SETTING_BPS_START {section __ddsc_OPTION_SETTING_BPS_START},}, + /* Block Protect Setting Register */ + block __option_setting_bps_reg with fixed order { + section .option_setting_bps}, + block .option_setting_bps.endof with fixed order { + block __ddsc_OPTION_SETTING_BPS_END {section __ddsc_OPTION_SETTING_BPS_END},}, +}; + +place in OPTION_SETTING_BPS { block option_setting_bps_BLOCK }; +/***** OPTION_SETTING_BPS_SEC memory section allocations ******/ +define section __ddsc_OPTION_SETTING_BPS_SEC_START {public __ddsc_OPTION_SETTING_BPS_SEC_START:}; +keep {section __ddsc_OPTION_SETTING_BPS_SEC_START}; +define section __ddsc_OPTION_SETTING_BPS_SEC_END {public __ddsc_OPTION_SETTING_BPS_SEC_END:}; +keep {section __ddsc_OPTION_SETTING_BPS_SEC_END}; +define block option_setting_bps_sec_BLOCK with fixed order { + block .option_setting_bps_sec.startof with fixed order { + block __ddsc_OPTION_SETTING_BPS_SEC_START {section __ddsc_OPTION_SETTING_BPS_SEC_START},}, + /* Block Protect Setting Register Secure */ + block __option_setting_bps_sec_reg with fixed order { + section .option_setting_bps_sec}, + block .option_setting_bps_sec.endof with fixed order { + block __ddsc_OPTION_SETTING_BPS_SEC_END {section __ddsc_OPTION_SETTING_BPS_SEC_END},}, +}; + +place in OPTION_SETTING_BPS_SEC { block option_setting_bps_sec_BLOCK }; +/***** OPTION_SETTING_OTP_PBPS_SEC memory section allocations ******/ +define section __ddsc_OPTION_SETTING_OTP_PBPS_SEC_START {public __ddsc_OPTION_SETTING_OTP_PBPS_SEC_START:}; +keep {section __ddsc_OPTION_SETTING_OTP_PBPS_SEC_START}; +define section __ddsc_OPTION_SETTING_OTP_PBPS_SEC_END {public __ddsc_OPTION_SETTING_OTP_PBPS_SEC_END:}; +keep {section __ddsc_OPTION_SETTING_OTP_PBPS_SEC_END}; +define block option_setting_otp_pbps_sec_BLOCK with fixed order { + block .option_setting_otp_pbps_sec.startof with fixed order { + block __ddsc_OPTION_SETTING_OTP_PBPS_SEC_START {section __ddsc_OPTION_SETTING_OTP_PBPS_SEC_START},}, + /* Permanent Block Protect Setting Register Secure */ + block __option_setting_otp_pbps_sec_reg with fixed order { + section .option_setting_otp_pbps_sec}, + block .option_setting_otp_pbps_sec.endof with fixed order { + block __ddsc_OPTION_SETTING_OTP_PBPS_SEC_END {section __ddsc_OPTION_SETTING_OTP_PBPS_SEC_END},}, +}; + +place in OPTION_SETTING_OTP_PBPS_SEC { block option_setting_otp_pbps_sec_BLOCK }; +/***** OPTION_SETTING_OTP_PBPS memory section allocations ******/ +define section __ddsc_OPTION_SETTING_OTP_PBPS_START {public __ddsc_OPTION_SETTING_OTP_PBPS_START:}; +keep {section __ddsc_OPTION_SETTING_OTP_PBPS_START}; +define section __ddsc_OPTION_SETTING_OTP_PBPS_END {public __ddsc_OPTION_SETTING_OTP_PBPS_END:}; +keep {section __ddsc_OPTION_SETTING_OTP_PBPS_END}; +define block option_setting_otp_pbps_BLOCK with fixed order { + block .option_setting_otp_pbps.startof with fixed order { + block __ddsc_OPTION_SETTING_OTP_PBPS_START {section __ddsc_OPTION_SETTING_OTP_PBPS_START},}, + /* Permanent Block Protect Setting Register */ + block __option_setting_otp_pbps_reg with fixed order { + section .option_setting_otp_pbps}, + block .option_setting_otp_pbps.endof with fixed order { + block __ddsc_OPTION_SETTING_OTP_PBPS_END {section __ddsc_OPTION_SETTING_OTP_PBPS_END},}, +}; + +place in OPTION_SETTING_OTP_PBPS { block option_setting_otp_pbps_BLOCK }; + + +/***** Selectors that must be kept ******/ +keep{ + section .fixed_vectors, + section .application_vectors, + section .mcuboot_sce9_key, + section .version, + section .stack?*, + section .option_setting_ofs0, + section .option_setting_ofs2, + section .option_setting_sas, + section .option_setting_ofs1, + section .option_setting_ofs1_sec, + section .option_setting_ofs1_sel, + section .option_setting_ofs3, + section .option_setting_ofs3_sec, + section .option_setting_ofs3_sel, + section .option_setting_bps, + section .option_setting_bps_sec, + section .option_setting_otp_pbps_sec, + section .option_setting_otp_pbps}; + +/***** FSP handles all initialization ******/ +initialize manually with alignment preservation{ + /* section.sdram.from_ospi0_cs1 */ + section .sdram_from_ospi0_cs1, + /* section.sdram.code_from_ospi0_cs1 */ + section .sdram_code_from_ospi0_cs1, + /* section.sdram.from_ospi1_cs1 */ + section .sdram_from_ospi1_cs1, + /* section.sdram.code_from_ospi1_cs1 */ + section .sdram_code_from_ospi1_cs1, + /* section.sdram.from_data_flash */ + section .sdram_from_data_flash, + /* section.sdram.code_from_data_flash */ + section .sdram_code_from_data_flash, + /* section.sdram.from_flash */ + section .sdram_from_flash, + /* section.sdram.code_from_flash */ + section .sdram_code_from_flash, + /* section.ospi0_cs0.from_ospi0_cs1 */ + section .ospi0_cs0_from_ospi0_cs1, + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + section .ospi0_cs0_code_from_ospi0_cs1, + /* section.ospi0_cs0.from_ospi1_cs1 */ + section .ospi0_cs0_from_ospi1_cs1, + /* section.ospi0_cs0.code_from_ospi1_cs1 */ + section .ospi0_cs0_code_from_ospi1_cs1, + /* section.ospi0_cs0.from_data_flash */ + section .ospi0_cs0_from_data_flash, + /* section.ospi0_cs0.code_from_data_flash */ + section .ospi0_cs0_code_from_data_flash, + /* section.ospi0_cs0.from_flash */ + section .ospi0_cs0_from_flash, + /* section.ospi0_cs0.code_from_flash */ + section .ospi0_cs0_code_from_flash, + /* section.ospi1_cs0.from_ospi0_cs1 */ + section .ospi1_cs0_from_ospi0_cs1, + /* section.ospi1_cs0.code_from_ospi0_cs1 */ + section .ospi1_cs0_code_from_ospi0_cs1, + /* section.ospi1_cs0.from_ospi1_cs1 */ + section .ospi1_cs0_from_ospi1_cs1, + /* section.ospi1_cs0.code_from_ospi1_cs1 */ + section .ospi1_cs0_code_from_ospi1_cs1, + /* section.ospi1_cs0.from_data_flash */ + section .ospi1_cs0_from_data_flash, + /* section.ospi1_cs0.code_from_data_flash */ + section .ospi1_cs0_code_from_data_flash, + /* section.ospi1_cs0.from_flash */ + section .ospi1_cs0_from_flash, + /* section.ospi1_cs0.code_from_flash */ + section .ospi1_cs0_code_from_flash, + /* section.ctcm.from_ospi0_cs1 */ + section .ctcm_from_ospi0_cs1, + /* section.ctcm.code_from_ospi0_cs1 */ + section .ctcm_code_from_ospi0_cs1, + /* section.ctcm.from_ospi1_cs1 */ + section .ctcm_from_ospi1_cs1, + /* section.ctcm.code_from_ospi1_cs1 */ + section .ctcm_code_from_ospi1_cs1, + /* section.ctcm.from_data_flash */ + section .ctcm_from_data_flash, + /* section.ctcm.code_from_data_flash */ + section .ctcm_code_from_data_flash, + /* section.ctcm.from_flash */ + section .ctcm_from_flash, + /* section.ctcm.code_from_flash */ + section .ctcm_code_from_flash, + /* section.stcm.from_ospi0_cs1 */ + section .stcm_from_ospi0_cs1, + /* section.stcm.code_from_ospi0_cs1 */ + section .stcm_code_from_ospi0_cs1, + /* section.stcm.from_ospi1_cs1 */ + section .stcm_from_ospi1_cs1, + /* section.stcm.code_from_ospi1_cs1 */ + section .stcm_code_from_ospi1_cs1, + /* section.stcm.from_data_flash */ + section .stcm_from_data_flash, + /* section.stcm.code_from_data_flash */ + section .stcm_code_from_data_flash, + /* section.stcm.from_flash */ + section .stcm_from_flash, + /* section.stcm.code_from_flash */ + section .stcm_code_from_flash, + /* section.ram.from_ospi0_cs1 */ + section .ram_from_ospi0_cs1, + /* section.ram.code_from_ospi0_cs1 */ + section .ram_code_from_ospi0_cs1, + /* section.ram.from_ospi1_cs1 */ + section .ram_from_ospi1_cs1, + /* section.ram.code_from_ospi1_cs1 */ + section .ram_code_from_ospi1_cs1, + /* section.ram.from_data_flash */ + section .ram_from_data_flash, + /* section.ram.code_from_data_flash */ + section .ram_code_from_data_flash, + /* section.ram.from_flash */ + section .ram_from_flash, + /* section.ram.code_from_flash */ + section .ram_code_from_flash, + section .data*, + section vtable}; +do not initialize{zi}; +initialize manually with alignment preservation{rw}; + diff --git a/bsp/renesas/ra8p1-titan-board/m33/script/fsp.ld b/bsp/renesas/ra8p1-titan-board/m33/script/fsp.ld new file mode 100644 index 00000000000..30ae501a60d --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/script/fsp.ld @@ -0,0 +1,1104 @@ +/* + Linker File for Renesas FSP +*/ + + +/* generated memory regions file - do not edit */ +RAM_START = 0x22194000; +RAM_LENGTH = 0x40000; +FLASH_START = 0x020C0000; +FLASH_LENGTH = 0x00040000; +DATA_FLASH_START = 0x27000000; +DATA_FLASH_LENGTH = 0x00000000; +SDRAM_START = 0x68000000; +SDRAM_LENGTH = 0x08000000; +OSPI0_CS0_START = 0x80000000; +OSPI0_CS0_LENGTH = 0x10000000; +OSPI0_CS1_START = 0x90000000; +OSPI0_CS1_LENGTH = 0x10000000; +OSPI1_CS0_START = 0x70000000; +OSPI1_CS0_LENGTH = 0x08000000; +OSPI1_CS1_START = 0x78000000; +OSPI1_CS1_LENGTH = 0x08000000; +OPTION_SETTING_OFS0_START = 0x02c9f040; +OPTION_SETTING_OFS0_LENGTH = 0x00000004; +OPTION_SETTING_OFS2_START = 0x02c9f044; +OPTION_SETTING_OFS2_LENGTH = 0x00000004; +OPTION_SETTING_SAS_START = 0x02c9f074; +OPTION_SETTING_SAS_LENGTH = 0x00000004; +OPTION_SETTING_OFS1_START = 0x12c9f4c0; +OPTION_SETTING_OFS1_LENGTH = 0x00000004; +OPTION_SETTING_OFS1_SEC_START = 0x02c9f0c0; +OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; +OPTION_SETTING_OFS1_SEL_START = 0x02c9f120; +OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; +OPTION_SETTING_OFS3_START = 0x12c9f4c4; +OPTION_SETTING_OFS3_LENGTH = 0x00000004; +OPTION_SETTING_OFS3_SEC_START = 0x02c9f0c4; +OPTION_SETTING_OFS3_SEC_LENGTH = 0x00000004; +OPTION_SETTING_OFS3_SEL_START = 0x02c9f124; +OPTION_SETTING_OFS3_SEL_LENGTH = 0x00000004; +OPTION_SETTING_BPS_START = 0x12c9f600; +OPTION_SETTING_BPS_LENGTH = 0x00000080; +OPTION_SETTING_BPS_SEC_START = 0x02c9f200; +OPTION_SETTING_BPS_SEC_LENGTH = 0x00000080; +OPTION_SETTING_OTP_PBPS_SEC_START = 0x02e07700; +OPTION_SETTING_OTP_PBPS_SEC_LENGTH = 0x00000080; +OPTION_SETTING_OTP_PBPS_START = 0x12e07780; +OPTION_SETTING_OTP_PBPS_LENGTH = 0x00000080; +CTCM_START = 0x00000000; +CTCM_LENGTH = 0x00010000; +STCM_START = 0x20000000; +STCM_LENGTH = 0x00010000; + + +MEMORY +{ + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OSPI1_CS0 (rwx) : ORIGIN = OSPI1_CS0_START, LENGTH = OSPI1_CS0_LENGTH + OSPI1_CS1 (rx) : ORIGIN = OSPI1_CS1_START, LENGTH = OSPI1_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_OFS2 (r) : ORIGIN = OPTION_SETTING_OFS2_START, LENGTH = OPTION_SETTING_OFS2_LENGTH + OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_SAS_START, LENGTH = OPTION_SETTING_SAS_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_OFS3 (r) : ORIGIN = OPTION_SETTING_OFS3_START, LENGTH = OPTION_SETTING_OFS3_LENGTH + OPTION_SETTING_OFS3_SEC (r) : ORIGIN = OPTION_SETTING_OFS3_SEC_START, LENGTH = OPTION_SETTING_OFS3_SEC_LENGTH + OPTION_SETTING_OFS3_SEL (r) : ORIGIN = OPTION_SETTING_OFS3_SEL_START, LENGTH = OPTION_SETTING_OFS3_SEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_OTP_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_OTP_PBPS_SEC_START, LENGTH = OPTION_SETTING_OTP_PBPS_SEC_LENGTH + OPTION_SETTING_OTP_PBPS (r) : ORIGIN = OPTION_SETTING_OTP_PBPS_START, LENGTH = OPTION_SETTING_OTP_PBPS_LENGTH + CTCM (rwx) : ORIGIN = CTCM_START, LENGTH = CTCM_LENGTH + STCM (rwx) : ORIGIN = STCM_START, LENGTH = STCM_LENGTH +} + +/* code entry point...need to define to keep crt0 _start out */ +ENTRY( Reset_Handler) +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a) + +SECTIONS +{ + + + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = .; + + }> OSPI0_CS1 + /***** SDRAM memory section allocations ******/ + .sdram.startof : + { + __ddsc_SDRAM_START = .; + + }> SDRAM + /* sdram initialized from ospi0_cs1 */ + __sdram_from_ospi0_cs1$$ : ALIGN(4) + { + __sdram_from_ospi0_cs1$$Base = .;__sdram_from_ospi0_cs1$$Load = LOADADDR(__sdram_from_ospi0_cs1$$); + /* section.sdram.from_ospi0_cs1 */ + *(.sdram_from_ospi0_cs1) + /* section.sdram.code_from_ospi0_cs1 */ + *(.sdram_code_from_ospi0_cs1) + __sdram_from_ospi0_cs1$$Limit = .; + }> SDRAM AT > OSPI0_CS1 + + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = .; + + }> OSPI0_CS0 + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : ALIGN(4) + { + __ospi0_cs0_from_ospi0_cs1$$Base = .;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$); + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = .; + }> OSPI0_CS0 AT > OSPI0_CS1 + + /***** OSPI1_CS0 memory section allocations ******/ + .ospi1_cs0.startof : + { + __ddsc_OSPI1_CS0_START = .; + + }> OSPI1_CS0 + /* ospi1_cs0 initialized from ospi0_cs1 */ + __ospi1_cs0_from_ospi0_cs1$$ : ALIGN(4) + { + __ospi1_cs0_from_ospi0_cs1$$Base = .;__ospi1_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi1_cs0_from_ospi0_cs1$$); + /* section.ospi1_cs0.from_ospi0_cs1 */ + *(.ospi1_cs0_from_ospi0_cs1) + /* section.ospi1_cs0.code_from_ospi0_cs1 */ + *(.ospi1_cs0_code_from_ospi0_cs1) + __ospi1_cs0_from_ospi0_cs1$$Limit = .; + }> OSPI1_CS0 AT > OSPI0_CS1 + + /***** CTCM memory section allocations ******/ + .ctcm.startof : + { + __ddsc_CTCM_START = .; + + }> CTCM + /* ctcm initialized from ospi0_cs1 */ + __ctcm_from_ospi0_cs1$$ : ALIGN(8) + { + __ctcm_from_ospi0_cs1$$Base = .;__ctcm_from_ospi0_cs1$$Load = LOADADDR(__ctcm_from_ospi0_cs1$$); + /* section.ctcm.from_ospi0_cs1 */ + *(.ctcm_from_ospi0_cs1) + /* section.ctcm.code_from_ospi0_cs1 */ + *(.ctcm_code_from_ospi0_cs1) + . = ALIGN(8); + __ctcm_from_ospi0_cs1$$Limit = .; + }> CTCM AT > OSPI0_CS1 + + /***** STCM memory section allocations ******/ + .stcm.startof : + { + __ddsc_STCM_START = .; + + }> STCM + /* stcm initialized from ospi0_cs1 */ + __stcm_from_ospi0_cs1$$ : ALIGN(8) + { + __stcm_from_ospi0_cs1$$Base = .;__stcm_from_ospi0_cs1$$Load = LOADADDR(__stcm_from_ospi0_cs1$$); + /* section.stcm.from_ospi0_cs1 */ + *(.stcm_from_ospi0_cs1) + /* section.stcm.code_from_ospi0_cs1 */ + *(.stcm_code_from_ospi0_cs1) + . = ALIGN(8); + __stcm_from_ospi0_cs1$$Limit = .; + }> STCM AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = .; + + }> RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = .; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = .; + }> RAM + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : ALIGN(4) + { + __ram_from_ospi0_cs1$$Base = .;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$); + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = .; + }> RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = .; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = .; + }> OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = .; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = .; + }> OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = .; + + }> OSPI0_CS1 + + /***** OSPI1_CS1 memory section allocations ******/ + .ospi1_cs1.startof (READONLY) : + { + __ddsc_OSPI1_CS1_START = .; + + }> OSPI1_CS1 + /***** SDRAM memory section allocations ******/ + /* sdram initialized from ospi1_cs1 */ + __sdram_from_ospi1_cs1$$ : ALIGN(4) + { + __sdram_from_ospi1_cs1$$Base = .;__sdram_from_ospi1_cs1$$Load = LOADADDR(__sdram_from_ospi1_cs1$$); + /* section.sdram.from_ospi1_cs1 */ + *(.sdram_from_ospi1_cs1) + /* section.sdram.code_from_ospi1_cs1 */ + *(.sdram_code_from_ospi1_cs1) + __sdram_from_ospi1_cs1$$Limit = .; + }> SDRAM AT > OSPI1_CS1 + + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from ospi1_cs1 */ + __ospi0_cs0_from_ospi1_cs1$$ : ALIGN(4) + { + __ospi0_cs0_from_ospi1_cs1$$Base = .;__ospi0_cs0_from_ospi1_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi1_cs1$$); + /* section.ospi0_cs0.from_ospi1_cs1 */ + *(.ospi0_cs0_from_ospi1_cs1) + /* section.ospi0_cs0.code_from_ospi1_cs1 */ + *(.ospi0_cs0_code_from_ospi1_cs1) + __ospi0_cs0_from_ospi1_cs1$$Limit = .; + }> OSPI0_CS0 AT > OSPI1_CS1 + + /***** OSPI1_CS0 memory section allocations ******/ + /* ospi1_cs0 initialized from ospi1_cs1 */ + __ospi1_cs0_from_ospi1_cs1$$ : ALIGN(4) + { + __ospi1_cs0_from_ospi1_cs1$$Base = .;__ospi1_cs0_from_ospi1_cs1$$Load = LOADADDR(__ospi1_cs0_from_ospi1_cs1$$); + /* section.ospi1_cs0.from_ospi1_cs1 */ + *(.ospi1_cs0_from_ospi1_cs1) + /* section.ospi1_cs0.code_from_ospi1_cs1 */ + *(.ospi1_cs0_code_from_ospi1_cs1) + __ospi1_cs0_from_ospi1_cs1$$Limit = .; + }> OSPI1_CS0 AT > OSPI1_CS1 + + /***** CTCM memory section allocations ******/ + /* ctcm initialized from ospi1_cs1 */ + __ctcm_from_ospi1_cs1$$ : ALIGN(8) + { + __ctcm_from_ospi1_cs1$$Base = .;__ctcm_from_ospi1_cs1$$Load = LOADADDR(__ctcm_from_ospi1_cs1$$); + /* section.ctcm.from_ospi1_cs1 */ + *(.ctcm_from_ospi1_cs1) + /* section.ctcm.code_from_ospi1_cs1 */ + *(.ctcm_code_from_ospi1_cs1) + . = ALIGN(8); + __ctcm_from_ospi1_cs1$$Limit = .; + }> CTCM AT > OSPI1_CS1 + + /***** STCM memory section allocations ******/ + /* stcm initialized from ospi1_cs1 */ + __stcm_from_ospi1_cs1$$ : ALIGN(8) + { + __stcm_from_ospi1_cs1$$Base = .;__stcm_from_ospi1_cs1$$Load = LOADADDR(__stcm_from_ospi1_cs1$$); + /* section.stcm.from_ospi1_cs1 */ + *(.stcm_from_ospi1_cs1) + /* section.stcm.code_from_ospi1_cs1 */ + *(.stcm_code_from_ospi1_cs1) + . = ALIGN(8); + __stcm_from_ospi1_cs1$$Limit = .; + }> STCM AT > OSPI1_CS1 + + /***** RAM memory section allocations ******/ + /* ram initialized from ospi1_cs1 */ + __ram_from_ospi1_cs1$$ : ALIGN(4) + { + __ram_from_ospi1_cs1$$Base = .;__ram_from_ospi1_cs1$$Load = LOADADDR(__ram_from_ospi1_cs1$$); + /* section.ram.from_ospi1_cs1 */ + *(.ram_from_ospi1_cs1) + /* section.ram.code_from_ospi1_cs1 */ + *(.ram_code_from_ospi1_cs1) + __ram_from_ospi1_cs1$$Limit = .; + }> RAM AT > OSPI1_CS1 + + __ospi1_cs1_readonly$$ (READONLY) : + { + __ospi1_cs1_readonly$$Base = .; + /* section.ospi1_cs1.readonly */ + *(.ospi1_cs1) + /* section.ospi1_cs1.code */ + *(.ospi1_cs1_code) + __ospi1_cs1_readonly$$Limit = .; + }> OSPI1_CS1 + __ospi1_cs1_noinit$$ (NOLOAD) : + { + __ospi1_cs1_noinit$$Base = .; + /* section.ospi1_cs1.noinit */ + *(.ospi1_cs1_noinit) + __ospi1_cs1_noinit$$Limit = .; + }> OSPI1_CS1 + .ospi1_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI1_CS1_END = .; + + }> OSPI1_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = .; + + }> DATA_FLASH + /***** SDRAM memory section allocations ******/ + /* sdram initialized from data_flash */ + __sdram_from_data_flash$$ : ALIGN(4) + { + __sdram_from_data_flash$$Base = .;__sdram_from_data_flash$$Load = LOADADDR(__sdram_from_data_flash$$); + /* section.sdram.from_data_flash */ + *(.sdram_from_data_flash) + /* section.sdram.code_from_data_flash */ + *(.sdram_code_from_data_flash) + __sdram_from_data_flash$$Limit = .; + }> SDRAM AT > DATA_FLASH + + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : ALIGN(4) + { + __ospi0_cs0_from_data_flash$$Base = .;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$); + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = .; + }> OSPI0_CS0 AT > DATA_FLASH + + /***** OSPI1_CS0 memory section allocations ******/ + /* ospi1_cs0 initialized from data_flash */ + __ospi1_cs0_from_data_flash$$ : ALIGN(4) + { + __ospi1_cs0_from_data_flash$$Base = .;__ospi1_cs0_from_data_flash$$Load = LOADADDR(__ospi1_cs0_from_data_flash$$); + /* section.ospi1_cs0.from_data_flash */ + *(.ospi1_cs0_from_data_flash) + /* section.ospi1_cs0.code_from_data_flash */ + *(.ospi1_cs0_code_from_data_flash) + __ospi1_cs0_from_data_flash$$Limit = .; + }> OSPI1_CS0 AT > DATA_FLASH + + /***** CTCM memory section allocations ******/ + /* ctcm initialized from data_flash */ + __ctcm_from_data_flash$$ : ALIGN(8) + { + __ctcm_from_data_flash$$Base = .;__ctcm_from_data_flash$$Load = LOADADDR(__ctcm_from_data_flash$$); + /* section.ctcm.from_data_flash */ + *(.ctcm_from_data_flash) + /* section.ctcm.code_from_data_flash */ + *(.ctcm_code_from_data_flash) + . = ALIGN(8); + __ctcm_from_data_flash$$Limit = .; + }> CTCM AT > DATA_FLASH + + /***** STCM memory section allocations ******/ + /* stcm initialized from data_flash */ + __stcm_from_data_flash$$ : ALIGN(8) + { + __stcm_from_data_flash$$Base = .;__stcm_from_data_flash$$Load = LOADADDR(__stcm_from_data_flash$$); + /* section.stcm.from_data_flash */ + *(.stcm_from_data_flash) + /* section.stcm.code_from_data_flash */ + *(.stcm_code_from_data_flash) + . = ALIGN(8); + __stcm_from_data_flash$$Limit = .; + }> STCM AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : ALIGN(4) + { + __ram_from_data_flash$$Base = .;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$); + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = .; + }> RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = .; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = .; + }> DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = .; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = .; + }> DATA_FLASH + .data_flash.endof ALIGN(.,1024) (READONLY) : + { + __ddsc_DATA_FLASH_END = .; + + }> DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = .; + + }> FLASH + /* MCU vector table */ + __flash_vectors$$ (READONLY) : + { + __flash_vectors$$Base = .; _VECTORS = .; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = .; + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for utest */ + . = ALIGN(4); + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + KEEP(*(FalPartTable)) + }> FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = .; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = .; + }> FLASH + /***** SDRAM memory section allocations ******/ + /* sdram initialized from flash */ + __sdram_from_flash$$ : ALIGN(4) + { + __sdram_from_flash$$Base = .;__sdram_from_flash$$Load = LOADADDR(__sdram_from_flash$$); + /* section.sdram.from_flash */ + *(.sdram_from_flash) + /* section.sdram.code_from_flash */ + *(.sdram_code_from_flash) + __sdram_from_flash$$Limit = .; + }> SDRAM AT > FLASH + /* Non-initialized, non-cached sdram */ + __sdram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __sdram_noinit_nocache$$Base = .; + /* section.sdram.noinit_nocache */ + *(.sdram_noinit_nocache) + __sdram_noinit_nocache$$Limit = .; + }> SDRAM + /* Zeroed, non-cached sdram */ + __sdram_zero_nocache$$ (NOLOAD) : + { + __sdram_zero_nocache$$Base = .; + /* section.sdram.zero_nocache */ + *(.sdram_nocache) + . = ALIGN(32); + __sdram_zero_nocache$$Limit = .; + }> SDRAM + /* Non-initialized sdram */ + __sdram_noinit$$ (NOLOAD) : ALIGN(4) + { + __sdram_noinit$$Base = .; + /* section.sdram.noinit */ + *(.sdram_noinit) + __sdram_noinit$$Limit = .; + }> SDRAM + /* Zeroed sdram */ + __sdram_zero$$ (NOLOAD) : ALIGN(4) + { + __sdram_zero$$Base = .; + /* section.sdram.zero */ + *(.sdram) + __sdram_zero$$Limit = .; + }> SDRAM + .sdram.endof ALIGN(.,512) : + { + __ddsc_SDRAM_END = .; + + }> SDRAM + + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : ALIGN(4) + { + __ospi0_cs0_from_flash$$Base = .;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$); + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = .; + }> OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = .; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = .; + }> OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = .; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = .; + }> OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : ALIGN(4) + { + __ospi0_cs0_noinit$$Base = .; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = .; + }> OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : ALIGN(4) + { + __ospi0_cs0_zero$$Base = .; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = .; + }> OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = .; + + }> OSPI0_CS0 + + /***** OSPI1_CS0 memory section allocations ******/ + /* ospi1_cs0 initialized from flash */ + __ospi1_cs0_from_flash$$ : ALIGN(4) + { + __ospi1_cs0_from_flash$$Base = .;__ospi1_cs0_from_flash$$Load = LOADADDR(__ospi1_cs0_from_flash$$); + /* section.ospi1_cs0.from_flash */ + *(.ospi1_cs0_from_flash) + /* section.ospi1_cs0.code_from_flash */ + *(.ospi1_cs0_code_from_flash) + __ospi1_cs0_from_flash$$Limit = .; + }> OSPI1_CS0 AT > FLASH + /* Non-initialized, non-cached ospi1_cs0 */ + __ospi1_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi1_cs0_noinit_nocache$$Base = .; + /* section.ospi1_cs0.noinit_nocache */ + *(.ospi1_cs0_noinit_nocache) + __ospi1_cs0_noinit_nocache$$Limit = .; + }> OSPI1_CS0 + /* Zeroed, non-cached ospi1_cs0 */ + __ospi1_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi1_cs0_zero_nocache$$Base = .; + /* section.ospi1_cs0.zero_nocache */ + *(.ospi1_cs0_nocache) + . = ALIGN(32); + __ospi1_cs0_zero_nocache$$Limit = .; + }> OSPI1_CS0 + /* Non-initialized ospi1_cs0 */ + __ospi1_cs0_noinit$$ (NOLOAD) : ALIGN(4) + { + __ospi1_cs0_noinit$$Base = .; + /* section.ospi1_cs0.noinit */ + *(.ospi1_cs0_noinit) + __ospi1_cs0_noinit$$Limit = .; + }> OSPI1_CS0 + /* Zeroed ospi1_cs0 */ + __ospi1_cs0_zero$$ (NOLOAD) : ALIGN(4) + { + __ospi1_cs0_zero$$Base = .; + /* section.ospi1_cs0.zero */ + *(.ospi1_cs0) + __ospi1_cs0_zero$$Limit = .; + }> OSPI1_CS0 + .ospi1_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI1_CS0_END = .; + + }> OSPI1_CS0 + + /***** CTCM memory section allocations ******/ + /* ctcm initialized from flash */ + __ctcm_from_flash$$ : ALIGN(8) + { + __ctcm_from_flash$$Base = .;__ctcm_from_flash$$Load = LOADADDR(__ctcm_from_flash$$); + /* section.ctcm.from_flash */ + *(.ctcm_from_flash) + /* section.ctcm.code_from_flash */ + *(.ctcm_code_from_flash) + . = ALIGN(8); + __ctcm_from_flash$$Limit = .; + }> CTCM AT > FLASH + /* Non-initialized ctcm */ + __ctcm_noinit$$ (NOLOAD) : ALIGN(8) + { + __ctcm_noinit$$Base = .; + /* section.ctcm.noinit */ + *(.ctcm_noinit) + . = ALIGN(8); + __ctcm_noinit$$Limit = .; + }> CTCM + /* Zeroed ctcm */ + __ctcm_zero$$ (NOLOAD) : ALIGN(8) + { + __ctcm_zero$$Base = .; + /* section.ctcm.zero */ + *(.ctcm) + . = ALIGN(8); + __ctcm_zero$$Limit = .; + }> CTCM + .ctcm.endof ALIGN(.,8192) : + { + __ddsc_CTCM_END = .; + + }> CTCM + + /***** STCM memory section allocations ******/ + /* stcm initialized from flash */ + __stcm_from_flash$$ : ALIGN(8) + { + __stcm_from_flash$$Base = .;__stcm_from_flash$$Load = LOADADDR(__stcm_from_flash$$); + /* section.stcm.from_flash */ + *(.stcm_from_flash) + /* section.stcm.code_from_flash */ + *(.stcm_code_from_flash) + . = ALIGN(8); + __stcm_from_flash$$Limit = .; + }> STCM AT > FLASH + /* Non-initialized stcm */ + __stcm_noinit$$ (NOLOAD) : ALIGN(8) + { + __stcm_noinit$$Base = .; + /* section.stcm.noinit */ + *(.stcm_noinit) + . = ALIGN(8); + __stcm_noinit$$Limit = .; + }> STCM + /* Zeroed stcm */ + __stcm_zero$$ (NOLOAD) : ALIGN(8) + { + __stcm_zero$$Base = .; + /* section.stcm.zero */ + *(.stcm) + . = ALIGN(8); + __stcm_zero$$Limit = .; + }> STCM + .stcm.endof ALIGN(.,8192) : + { + __ddsc_STCM_END = .; + + }> STCM + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + __ram_from_flash$$ : ALIGN(4) + { + __ram_from_flash$$Base = .;__ram_from_flash$$Load = LOADADDR(__ram_from_flash$$); + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + *(vtable) + __ram_from_flash$$Limit = .; + }> RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = .; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = .; + }> RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = .; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = .; + }> RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : ALIGN(4) + { + __ram_noinit$$Base = .; + /* section.ram.noinit */ + *(.bss.g_heap) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = .; + }> RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : ALIGN(4) + { + __ram_zero$$Base = .; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = .; + }> RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = .; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = .; + }> RAM + .ram.endof ALIGN(.,8192) : + { + __ddsc_RAM_END = .; + + }> RAM + .ram.flat_nsc : + { + __sau_ddsc_RAM_NSC = .; + + }> RAM + + /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used + at run time for things such as ThreadX memory pool allocations. */ + __RAM_segment_used_end__ = ALIGN(__sau_ddsc_RAM_NSC , 4); + + __flash_readonly$$ (READONLY) : + { + __flash_readonly$$Base = .; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = .; + }> FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + }> FLASH + __flash_preinit_array$$ (READONLY) : ALIGN(4) + { + __preinit_array_start = .; + KEEP(*(.preinit_array)) + __preinit_array_end = .; + }> FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + }> FLASH + __flash_init_array$$ (READONLY) : ALIGN(4) + { + __init_array_start = .; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = .; + }> FLASH + __flash_fini_array$$ (READONLY) : ALIGN(4) + { + __fini_array_start = .; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = .; + }> FLASH + /* Discard exception tables */ + /DISCARD/ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + + }> FLASH + /* Dummy section to hold required exidx labels */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = .; + __exidx_end = .; + }> FLASH + .flash.endof ALIGN(.,32768) (READONLY) : + { + __ddsc_FLASH_END = .; + + }> FLASH + .flash.flat_nsc (READONLY) : + { + __sau_ddsc_FLASH_NSC = .; + + }> FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = .; + + }> OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = .; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = .; + }> OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = .; + + }> OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_OFS2 memory section allocations ******/ + .option_setting_ofs2.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS2_START = .; + + }> OPTION_SETTING_OFS2 + /* Option Function Select Register 2 */ + __option_setting_ofs2_reg$$ (READONLY) : + { + __option_setting_ofs2_reg$$Base = .; + KEEP(*(.option_setting_ofs2)) + __option_setting_ofs2_reg$$Limit = .; + }> OPTION_SETTING_OFS2 + .option_setting_ofs2.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS2_END = .; + + }> OPTION_SETTING_OFS2 + + /***** OPTION_SETTING_SAS memory section allocations ******/ + .option_setting_sas.startof (READONLY) : + { + __ddsc_OPTION_SETTING_SAS_START = .; + + }> OPTION_SETTING_SAS + /* Startup Area Setting Register */ + __option_setting_sas_reg$$ (READONLY) : + { + __option_setting_sas_reg$$Base = .; + KEEP(*(.option_setting_sas)) + __option_setting_sas_reg$$Limit = .; + }> OPTION_SETTING_SAS + .option_setting_sas.endof (READONLY) : + { + __ddsc_OPTION_SETTING_SAS_END = .; + + }> OPTION_SETTING_SAS + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = .; + + }> OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = .; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = .; + }> OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = .; + + }> OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = .; + + }> OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = .; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = .; + }> OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = .; + + }> OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = .; + + }> OPTION_SETTING_OFS1_SEL + /* OFS1 Register Select */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = .; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = .; + }> OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = .; + + }> OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_OFS3 memory section allocations ******/ + .option_setting_ofs3.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS3_START = .; + + }> OPTION_SETTING_OFS3 + /* Option Function Select Register 3 */ + __option_setting_ofs3_reg$$ (READONLY) : + { + __option_setting_ofs3_reg$$Base = .; + KEEP(*(.option_setting_ofs3)) + __option_setting_ofs3_reg$$Limit = .; + }> OPTION_SETTING_OFS3 + .option_setting_ofs3.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS3_END = .; + + }> OPTION_SETTING_OFS3 + + /***** OPTION_SETTING_OFS3_SEC memory section allocations ******/ + .option_setting_ofs3_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS3_SEC_START = .; + + }> OPTION_SETTING_OFS3_SEC + /* Option Function Select Register 3 Secure */ + __option_setting_ofs3_sec_reg$$ (READONLY) : + { + __option_setting_ofs3_sec_reg$$Base = .; + KEEP(*(.option_setting_ofs3_sec)) + __option_setting_ofs3_sec_reg$$Limit = .; + }> OPTION_SETTING_OFS3_SEC + .option_setting_ofs3_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS3_SEC_END = .; + + }> OPTION_SETTING_OFS3_SEC + + /***** OPTION_SETTING_OFS3_SEL memory section allocations ******/ + .option_setting_ofs3_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS3_SEL_START = .; + + }> OPTION_SETTING_OFS3_SEL + /* OFS3 Register Select */ + __option_setting_ofs3_sel_reg$$ (READONLY) : + { + __option_setting_ofs3_sel_reg$$Base = .; + KEEP(*(.option_setting_ofs3_sel)) + __option_setting_ofs3_sel_reg$$Limit = .; + }> OPTION_SETTING_OFS3_SEL + .option_setting_ofs3_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS3_SEL_END = .; + + }> OPTION_SETTING_OFS3_SEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = .; + + }> OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = .; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = .; + }> OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = .; + + }> OPTION_SETTING_BPS + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = .; + + }> OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = .; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = .; + }> OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = .; + + }> OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_OTP_PBPS_SEC memory section allocations ******/ + .option_setting_otp_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OTP_PBPS_SEC_START = .; + + }> OPTION_SETTING_OTP_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_otp_pbps_sec_reg$$ (READONLY) : + { + __option_setting_otp_pbps_sec_reg$$Base = .; + KEEP(*(.option_setting_otp_pbps_sec)) + __option_setting_otp_pbps_sec_reg$$Limit = .; + }> OPTION_SETTING_OTP_PBPS_SEC + .option_setting_otp_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OTP_PBPS_SEC_END = .; + + }> OPTION_SETTING_OTP_PBPS_SEC + + /***** OPTION_SETTING_OTP_PBPS memory section allocations ******/ + .option_setting_otp_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OTP_PBPS_START = .; + + }> OPTION_SETTING_OTP_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_otp_pbps_reg$$ (READONLY) : + { + __option_setting_otp_pbps_reg$$Base = .; + KEEP(*(.option_setting_otp_pbps)) + __option_setting_otp_pbps_reg$$Limit = .; + }> OPTION_SETTING_OTP_PBPS + .option_setting_otp_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OTP_PBPS_END = .; + + }> OPTION_SETTING_OTP_PBPS + +} + diff --git a/bsp/renesas/ra8p1-titan-board/m33/script/fsp.scat b/bsp/renesas/ra8p1-titan-board/m33/script/fsp.scat new file mode 100644 index 00000000000..33c4b9d904c --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/script/fsp.scat @@ -0,0 +1,1166 @@ +#! armclang -mcpu=cortex-m33 --target=arm-arm-none-eabi -E -x c -I. + /* generated memory regions file - do not edit */ + #define RAM_START 0x22194000 + #define RAM_LENGTH 0x00040000 + #define FLASH_START 0x020C0000 + #define FLASH_LENGTH 0x00040000 + #define DATA_FLASH_START 0x27000000 + #define DATA_FLASH_LENGTH 0x00000000 + #define SDRAM_START 0x68000000 + #define SDRAM_LENGTH 0x08000000 + #define OSPI0_CS0_START 0x80000000 + #define OSPI0_CS0_LENGTH 0x10000000 + #define OSPI0_CS1_START 0x90000000 + #define OSPI0_CS1_LENGTH 0x10000000 + #define OSPI1_CS0_START 0x70000000 + #define OSPI1_CS0_LENGTH 0x08000000 + #define OSPI1_CS1_START 0x78000000 + #define OSPI1_CS1_LENGTH 0x08000000 + #define OPTION_SETTING_OFS0_START 0x02c9f040 + #define OPTION_SETTING_OFS0_LENGTH 0x00000004 + #define OPTION_SETTING_OFS2_START 0x02c9f044 + #define OPTION_SETTING_OFS2_LENGTH 0x00000004 + #define OPTION_SETTING_SAS_START 0x02c9f074 + #define OPTION_SETTING_SAS_LENGTH 0x00000004 + #define OPTION_SETTING_OFS1_START 0x12c9f4c0 + #define OPTION_SETTING_OFS1_LENGTH 0x00000004 + #define OPTION_SETTING_OFS1_SEC_START 0x02c9f0c0 + #define OPTION_SETTING_OFS1_SEC_LENGTH 0x00000004 + #define OPTION_SETTING_OFS1_SEL_START 0x02c9f120 + #define OPTION_SETTING_OFS1_SEL_LENGTH 0x00000004 + #define OPTION_SETTING_OFS3_START 0x12c9f4c4 + #define OPTION_SETTING_OFS3_LENGTH 0x00000004 + #define OPTION_SETTING_OFS3_SEC_START 0x02c9f0c4 + #define OPTION_SETTING_OFS3_SEC_LENGTH 0x00000004 + #define OPTION_SETTING_OFS3_SEL_START 0x02c9f124 + #define OPTION_SETTING_OFS3_SEL_LENGTH 0x00000004 + #define OPTION_SETTING_BPS_START 0x12c9f600 + #define OPTION_SETTING_BPS_LENGTH 0x00000080 + #define OPTION_SETTING_BPS_SEC_START 0x02c9f200 + #define OPTION_SETTING_BPS_SEC_LENGTH 0x00000080 + #define OPTION_SETTING_OTP_PBPS_SEC_START 0x02e07700 + #define OPTION_SETTING_OTP_PBPS_SEC_LENGTH 0x00000080 + #define OPTION_SETTING_OTP_PBPS_START 0x12e07780 + #define OPTION_SETTING_OTP_PBPS_LENGTH 0x00000080 + #define CTCM_START 0x00000000 + #define CTCM_LENGTH 0x00010000 + #define STCM_START 0x20000000 + #define STCM_LENGTH 0x00010000 + +LOAD_REGION_OSPI0_CS1 OSPI0_CS1_START NOCOMPRESS OSPI0_CS1_LENGTH +{ + __OSPI0_CS1_start +0 EMPTY 0 {} + __OSPI0_CS1_init +0 EMPTY 0 {} + + + __ddsc_OSPI0_CS1_START +0 EMPTY 0 {} + .ospi0_cs1.startof +0 EMPTY 0 + { + } + __SDRAM_start SDRAM_START +0 EMPTY 0 {} + + __ddsc_SDRAM_START +0 EMPTY 0 {} + .sdram.startof +0 EMPTY 0 + { + } + + ; sdram initialized from ospi0_cs1 + __sdram_from_ospi0_cs1 +0 + { + ; section.sdram.from_ospi0_cs1 + *(.sdram_from_ospi0_cs1) + ; section.sdram.code_from_ospi0_cs1 + *(.sdram_code_from_ospi0_cs1) + } + __OSPI0_CS0_start OSPI0_CS0_START +0 EMPTY 0 {} + + __ddsc_OSPI0_CS0_START +0 EMPTY 0 {} + .ospi0_cs0.startof +0 EMPTY 0 + { + } + + ; ospi0_cs0 initialized from ospi0_cs1 + __ospi0_cs0_from_ospi0_cs1 +0 + { + ; section.ospi0_cs0.from_ospi0_cs1 + *(.ospi0_cs0_from_ospi0_cs1) + ; section.ospi0_cs0.code_from_ospi0_cs1 + *(.ospi0_cs0_code_from_ospi0_cs1) + } + __OSPI1_CS0_start OSPI1_CS0_START +0 EMPTY 0 {} + + __ddsc_OSPI1_CS0_START +0 EMPTY 0 {} + .ospi1_cs0.startof +0 EMPTY 0 + { + } + + ; ospi1_cs0 initialized from ospi0_cs1 + __ospi1_cs0_from_ospi0_cs1 +0 + { + ; section.ospi1_cs0.from_ospi0_cs1 + *(.ospi1_cs0_from_ospi0_cs1) + ; section.ospi1_cs0.code_from_ospi0_cs1 + *(.ospi1_cs0_code_from_ospi0_cs1) + } + __CTCM_start CTCM_START +0 EMPTY 0 {} + + __ddsc_CTCM_START +0 EMPTY 0 {} + .ctcm.startof +0 EMPTY 0 + { + } + + ; ctcm initialized from ospi0_cs1 + __ctcm_from_ospi0_cs1 +0 + { + ; section.ctcm.from_ospi0_cs1 + *(.ctcm_from_ospi0_cs1) + ; section.ctcm.code_from_ospi0_cs1 + *(.ctcm_code_from_ospi0_cs1) + } + __STCM_start STCM_START +0 EMPTY 0 {} + + __ddsc_STCM_START +0 EMPTY 0 {} + .stcm.startof +0 EMPTY 0 + { + } + + ; stcm initialized from ospi0_cs1 + __stcm_from_ospi0_cs1 +0 + { + ; section.stcm.from_ospi0_cs1 + *(.stcm_from_ospi0_cs1) + ; section.stcm.code_from_ospi0_cs1 + *(.stcm_code_from_ospi0_cs1) + } + __RAM_start RAM_START +0 EMPTY 0 {} + + __ddsc_RAM_START +0 EMPTY 0 {} + .ram.startof +0 EMPTY 0 + { + } + + + __ram_dtc_vector +0 UNINIT + { + *(.fsp_dtc_vector_table) + *(.bss.fsp_dtc_vector_table) + } + + ; ram initialized from ospi0_cs1 + __ram_from_ospi0_cs1 +0 + { + ; section.ram.from_ospi0_cs1 + *(.ram_from_ospi0_cs1) + ; section.ram.code_from_ospi0_cs1 + *(.ram_code_from_ospi0_cs1) + } + } ; create a root region after the RAM init ERs for remainder of ROM ERs + LOAD_REGION_OSPI0_CS1_JUMP +0 NOCOMPRESS + { + + __ospi0_cs1_readonly +0 FIXED + { + ; section.ospi0_cs1.readonly + *(.ospi0_cs1) + ; section.ospi0_cs1.code + *(.ospi0_cs1_code) + } + + + + __ospi0_cs1_noinit +0 FIXED UNINIT + { + ; section.ospi0_cs1.noinit + *(.ospi0_cs1_noinit) + *(.bss.ospi0_cs1_noinit) + } + + + + __ddsc_OSPI0_CS1_END AlignExpr(+0, 512) EMPTY 0 {} + .ospi0_cs1.endof AlignExpr(+0, 512) EMPTY 0 + { + } + + + __OSPI0_CS1_end +0 EMPTY 0 {} + SCatterAssert( (LoadBase(__OSPI0_CS1_end) - LoadBase(__OSPI0_CS1_start)) <= OSPI0_CS1_LENGTH ) +} +LOAD_REGION_OSPI1_CS1 OSPI1_CS1_START NOCOMPRESS OSPI1_CS1_LENGTH +{ + __OSPI1_CS1_start +0 EMPTY 0 {} + __OSPI1_CS1_init +0 EMPTY 0 {} + + + __ddsc_OSPI1_CS1_START +0 EMPTY 0 {} + .ospi1_cs1.startof +0 EMPTY 0 + { + } + __sdram_from_ospi0_cs1_jump ImageLimit(__sdram_from_ospi0_cs1) EMPTY 0 {} + ; sdram initialized from ospi1_cs1 + __sdram_from_ospi1_cs1 +0 + { + ; section.sdram.from_ospi1_cs1 + *(.sdram_from_ospi1_cs1) + ; section.sdram.code_from_ospi1_cs1 + *(.sdram_code_from_ospi1_cs1) + } + __ospi0_cs0_from_ospi0_cs1_jump ImageLimit(__ospi0_cs0_from_ospi0_cs1) EMPTY 0 {} + ; ospi0_cs0 initialized from ospi1_cs1 + __ospi0_cs0_from_ospi1_cs1 +0 + { + ; section.ospi0_cs0.from_ospi1_cs1 + *(.ospi0_cs0_from_ospi1_cs1) + ; section.ospi0_cs0.code_from_ospi1_cs1 + *(.ospi0_cs0_code_from_ospi1_cs1) + } + __ospi1_cs0_from_ospi0_cs1_jump ImageLimit(__ospi1_cs0_from_ospi0_cs1) EMPTY 0 {} + ; ospi1_cs0 initialized from ospi1_cs1 + __ospi1_cs0_from_ospi1_cs1 +0 + { + ; section.ospi1_cs0.from_ospi1_cs1 + *(.ospi1_cs0_from_ospi1_cs1) + ; section.ospi1_cs0.code_from_ospi1_cs1 + *(.ospi1_cs0_code_from_ospi1_cs1) + } + __ctcm_from_ospi0_cs1_jump ImageLimit(__ctcm_from_ospi0_cs1) EMPTY 0 {} + ; ctcm initialized from ospi1_cs1 + __ctcm_from_ospi1_cs1 +0 + { + ; section.ctcm.from_ospi1_cs1 + *(.ctcm_from_ospi1_cs1) + ; section.ctcm.code_from_ospi1_cs1 + *(.ctcm_code_from_ospi1_cs1) + } + __stcm_from_ospi0_cs1_jump ImageLimit(__stcm_from_ospi0_cs1) EMPTY 0 {} + ; stcm initialized from ospi1_cs1 + __stcm_from_ospi1_cs1 +0 + { + ; section.stcm.from_ospi1_cs1 + *(.stcm_from_ospi1_cs1) + ; section.stcm.code_from_ospi1_cs1 + *(.stcm_code_from_ospi1_cs1) + } + __ram_from_ospi0_cs1_jump ImageLimit(__ram_from_ospi0_cs1) EMPTY 0 {} + ; ram initialized from ospi1_cs1 + __ram_from_ospi1_cs1 +0 + { + ; section.ram.from_ospi1_cs1 + *(.ram_from_ospi1_cs1) + ; section.ram.code_from_ospi1_cs1 + *(.ram_code_from_ospi1_cs1) + } + } ; create a root region after the RAM init ERs for remainder of ROM ERs + LOAD_REGION_OSPI1_CS1_JUMP +0 NOCOMPRESS + { + + __ospi1_cs1_readonly +0 FIXED + { + ; section.ospi1_cs1.readonly + *(.ospi1_cs1) + ; section.ospi1_cs1.code + *(.ospi1_cs1_code) + } + + + + __ospi1_cs1_noinit +0 FIXED UNINIT + { + ; section.ospi1_cs1.noinit + *(.ospi1_cs1_noinit) + *(.bss.ospi1_cs1_noinit) + } + + + + __ddsc_OSPI1_CS1_END AlignExpr(+0, 512) EMPTY 0 {} + .ospi1_cs1.endof AlignExpr(+0, 512) EMPTY 0 + { + } + + + __OSPI1_CS1_end +0 EMPTY 0 {} + SCatterAssert( (LoadBase(__OSPI1_CS1_end) - LoadBase(__OSPI1_CS1_start)) <= OSPI1_CS1_LENGTH ) +} +LOAD_REGION_DATA_FLASH DATA_FLASH_START NOCOMPRESS DATA_FLASH_LENGTH +{ + __DATA_FLASH_start +0 EMPTY 0 {} + __DATA_FLASH_init +0 EMPTY 0 {} + + + __ddsc_DATA_FLASH_START +0 EMPTY 0 {} + .data_flash.startof +0 EMPTY 0 + { + } + __sdram_from_ospi1_cs1_jump ImageLimit(__sdram_from_ospi1_cs1) EMPTY 0 {} + ; sdram initialized from data_flash + __sdram_from_data_flash +0 + { + ; section.sdram.from_data_flash + *(.sdram_from_data_flash) + ; section.sdram.code_from_data_flash + *(.sdram_code_from_data_flash) + } + __ospi0_cs0_from_ospi1_cs1_jump ImageLimit(__ospi0_cs0_from_ospi1_cs1) EMPTY 0 {} + ; ospi0_cs0 initialized from data_flash + __ospi0_cs0_from_data_flash +0 + { + ; section.ospi0_cs0.from_data_flash + *(.ospi0_cs0_from_data_flash) + ; section.ospi0_cs0.code_from_data_flash + *(.ospi0_cs0_code_from_data_flash) + } + __ospi1_cs0_from_ospi1_cs1_jump ImageLimit(__ospi1_cs0_from_ospi1_cs1) EMPTY 0 {} + ; ospi1_cs0 initialized from data_flash + __ospi1_cs0_from_data_flash +0 + { + ; section.ospi1_cs0.from_data_flash + *(.ospi1_cs0_from_data_flash) + ; section.ospi1_cs0.code_from_data_flash + *(.ospi1_cs0_code_from_data_flash) + } + __ctcm_from_ospi1_cs1_jump ImageLimit(__ctcm_from_ospi1_cs1) EMPTY 0 {} + ; ctcm initialized from data_flash + __ctcm_from_data_flash +0 + { + ; section.ctcm.from_data_flash + *(.ctcm_from_data_flash) + ; section.ctcm.code_from_data_flash + *(.ctcm_code_from_data_flash) + } + __stcm_from_ospi1_cs1_jump ImageLimit(__stcm_from_ospi1_cs1) EMPTY 0 {} + ; stcm initialized from data_flash + __stcm_from_data_flash +0 + { + ; section.stcm.from_data_flash + *(.stcm_from_data_flash) + ; section.stcm.code_from_data_flash + *(.stcm_code_from_data_flash) + } + __ram_from_ospi1_cs1_jump ImageLimit(__ram_from_ospi1_cs1) EMPTY 0 {} + ; ram initialized from data_flash + __ram_from_data_flash +0 + { + ; section.ram.from_data_flash + *(.ram_from_data_flash) + ; section.ram.code_from_data_flash + *(.ram_code_from_data_flash) + } + } ; create a root region after the RAM init ERs for remainder of ROM ERs + LOAD_REGION_DATA_FLASH_JUMP +0 NOCOMPRESS + { + + __data_flash_readonly +0 FIXED + { + ; section.data_flash.readonly + *(.data_flash) + ; section.data_flash.code + *(.data_flash_code) + } + + + + __data_flash_noinit +0 FIXED UNINIT + { + ; section.data_flash.noinit + *(.data_flash_noinit) + *(.bss.data_flash_noinit) + } + + + + __ddsc_DATA_FLASH_END AlignExpr(+0, 1024) EMPTY 0 {} + .data_flash.endof AlignExpr(+0, 1024) EMPTY 0 + { + } + + + __DATA_FLASH_end +0 EMPTY 0 {} + SCatterAssert( (LoadBase(__DATA_FLASH_end) - LoadBase(__DATA_FLASH_start)) <= DATA_FLASH_LENGTH ) +} +LOAD_REGION_FLASH FLASH_START NOCOMPRESS FLASH_LENGTH +{ + __FLASH_start +0 EMPTY 0 {} + __FLASH_init +0 EMPTY 0 {} + + + __ddsc_FLASH_START +0 EMPTY 0 {} + .flash.startof +0 EMPTY 0 + { + } + + + ; MCU vector table + _VECTORS +0 EMPTY 0 {} + __flash_vectors +0 FIXED + { + *(.fixed_vectors, +FIRST) + *(.application_vectors) + } + + FSymTab +0 FIXED + { + *(FSymTab) + } + + VSymTab +0 FIXED + { + *(VSymTab) + } + + UtestTcTab +0 FIXED + { + *(UtestTcTab) + } + + RTInitTab +0 FIXED + { + *(.rti_fn*) + } + + FalPartTable +0 FIXED + { + *(FalPartTable) + } + + + + __flash_noinit +0 FIXED UNINIT + { + ; section.flash.noinit + *(.flash_noinit) + *(.bss.flash_noinit) + } + __sdram_from_data_flash_jump ImageLimit(__sdram_from_data_flash) EMPTY 0 {} + ; sdram initialized from flash + __sdram_from_flash +0 + { + ; section.sdram.from_flash + *(.sdram_from_flash) + ; section.sdram.code_from_flash + *(.sdram_code_from_flash) + } + + ; Non-initialized, non-cached sdram + __sdram_noinit_nocache AlignExpr(+0, 32) UNINIT + { + ; section.sdram.noinit_nocache + *(.sdram_noinit_nocache) + *(.bss.sdram_noinit_nocache) + } + + ; Zeroed, non-cached sdram + __sdram_zero_nocache +0 + { + ; section.sdram.zero_nocache + *(.sdram_nocache) + *(.bss.sdram_nocache) + } + ; Execution region required to end align __sdram_zero_nocache on ac6 + __sdram_zero_nocache_pad (ImageLimit(__sdram_zero_nocache)) EMPTY (AlignExpr(ImageLimit(__sdram_zero_nocache),32) - ImageLimit(__sdram_zero_nocache)) {} + + ; Non-initialized sdram + __sdram_noinit +0 UNINIT + { + ; section.sdram.noinit + *(.sdram_noinit) + *(.bss.sdram_noinit) + } + + ; Zeroed sdram + __sdram_zero +0 + { + ; section.sdram.zero + *(.sdram) + *(.bss.sdram) + } + + + __ddsc_SDRAM_END AlignExpr(+0, 512) EMPTY 0 {} + .sdram.endof AlignExpr(+0, 512) EMPTY 0 + { + } + + __SDRAM_end +0 EMPTY 0 {} + SCatterAssert( (LoadBase(__SDRAM_end) - LoadBase(__SDRAM_start)) <= SDRAM_LENGTH ) + __ospi0_cs0_from_data_flash_jump ImageLimit(__ospi0_cs0_from_data_flash) EMPTY 0 {} + ; ospi0_cs0 initialized from flash + __ospi0_cs0_from_flash +0 + { + ; section.ospi0_cs0.from_flash + *(.ospi0_cs0_from_flash) + ; section.ospi0_cs0.code_from_flash + *(.ospi0_cs0_code_from_flash) + } + + ; Non-initialized, non-cached ospi0_cs0 + __ospi0_cs0_noinit_nocache AlignExpr(+0, 32) UNINIT + { + ; section.ospi0_cs0.noinit_nocache + *(.ospi0_cs0_noinit_nocache) + *(.bss.ospi0_cs0_noinit_nocache) + } + + ; Zeroed, non-cached ospi0_cs0 + __ospi0_cs0_zero_nocache +0 + { + ; section.ospi0_cs0.zero_nocache + *(.ospi0_cs0_nocache) + *(.bss.ospi0_cs0_nocache) + } + ; Execution region required to end align __ospi0_cs0_zero_nocache on ac6 + __ospi0_cs0_zero_nocache_pad (ImageLimit(__ospi0_cs0_zero_nocache)) EMPTY (AlignExpr(ImageLimit(__ospi0_cs0_zero_nocache),32) - ImageLimit(__ospi0_cs0_zero_nocache)) {} + + ; Non-initialized ospi0_cs0 + __ospi0_cs0_noinit +0 UNINIT + { + ; section.ospi0_cs0.noinit + *(.ospi0_cs0_noinit) + *(.bss.ospi0_cs0_noinit) + } + + ; Zeroed ospi0_cs0 + __ospi0_cs0_zero +0 + { + ; section.ospi0_cs0.zero + *(.ospi0_cs0) + *(.bss.ospi0_cs0) + } + + + __ddsc_OSPI0_CS0_END AlignExpr(+0, 512) EMPTY 0 {} + .ospi0_cs0.endof AlignExpr(+0, 512) EMPTY 0 + { + } + + __OSPI0_CS0_end +0 EMPTY 0 {} + SCatterAssert( (LoadBase(__OSPI0_CS0_end) - LoadBase(__OSPI0_CS0_start)) <= OSPI0_CS0_LENGTH ) + __ospi1_cs0_from_data_flash_jump ImageLimit(__ospi1_cs0_from_data_flash) EMPTY 0 {} + ; ospi1_cs0 initialized from flash + __ospi1_cs0_from_flash +0 + { + ; section.ospi1_cs0.from_flash + *(.ospi1_cs0_from_flash) + ; section.ospi1_cs0.code_from_flash + *(.ospi1_cs0_code_from_flash) + } + + ; Non-initialized, non-cached ospi1_cs0 + __ospi1_cs0_noinit_nocache AlignExpr(+0, 32) UNINIT + { + ; section.ospi1_cs0.noinit_nocache + *(.ospi1_cs0_noinit_nocache) + *(.bss.ospi1_cs0_noinit_nocache) + } + + ; Zeroed, non-cached ospi1_cs0 + __ospi1_cs0_zero_nocache +0 + { + ; section.ospi1_cs0.zero_nocache + *(.ospi1_cs0_nocache) + *(.bss.ospi1_cs0_nocache) + } + ; Execution region required to end align __ospi1_cs0_zero_nocache on ac6 + __ospi1_cs0_zero_nocache_pad (ImageLimit(__ospi1_cs0_zero_nocache)) EMPTY (AlignExpr(ImageLimit(__ospi1_cs0_zero_nocache),32) - ImageLimit(__ospi1_cs0_zero_nocache)) {} + + ; Non-initialized ospi1_cs0 + __ospi1_cs0_noinit +0 UNINIT + { + ; section.ospi1_cs0.noinit + *(.ospi1_cs0_noinit) + *(.bss.ospi1_cs0_noinit) + } + + ; Zeroed ospi1_cs0 + __ospi1_cs0_zero +0 + { + ; section.ospi1_cs0.zero + *(.ospi1_cs0) + *(.bss.ospi1_cs0) + } + + + __ddsc_OSPI1_CS0_END AlignExpr(+0, 512) EMPTY 0 {} + .ospi1_cs0.endof AlignExpr(+0, 512) EMPTY 0 + { + } + + __OSPI1_CS0_end +0 EMPTY 0 {} + SCatterAssert( (LoadBase(__OSPI1_CS0_end) - LoadBase(__OSPI1_CS0_start)) <= OSPI1_CS0_LENGTH ) + __ctcm_from_data_flash_jump ImageLimit(__ctcm_from_data_flash) EMPTY 0 {} + ; ctcm initialized from flash + __ctcm_from_flash +0 + { + ; section.ctcm.from_flash + *(.ctcm_from_flash) + ; section.ctcm.code_from_flash + *(.ctcm_code_from_flash) + } + + ; Non-initialized ctcm + __ctcm_noinit +0 UNINIT + { + ; section.ctcm.noinit + *(.ctcm_noinit) + *(.bss.ctcm_noinit) + } + + ; Zeroed ctcm + __ctcm_zero +0 + { + ; section.ctcm.zero + *(.ctcm) + *(.bss.ctcm) + } + + + __ddsc_CTCM_END AlignExpr(+0, 8192) EMPTY 0 {} + .ctcm.endof AlignExpr(+0, 8192) EMPTY 0 + { + } + + __CTCM_end +0 EMPTY 0 {} + SCatterAssert( (LoadBase(__CTCM_end) - LoadBase(__CTCM_start)) <= CTCM_LENGTH ) + __stcm_from_data_flash_jump ImageLimit(__stcm_from_data_flash) EMPTY 0 {} + ; stcm initialized from flash + __stcm_from_flash +0 + { + ; section.stcm.from_flash + *(.stcm_from_flash) + ; section.stcm.code_from_flash + *(.stcm_code_from_flash) + } + + ; Non-initialized stcm + __stcm_noinit +0 UNINIT + { + ; section.stcm.noinit + *(.stcm_noinit) + *(.bss.stcm_noinit) + } + + ; Zeroed stcm + __stcm_zero +0 + { + ; section.stcm.zero + *(.stcm) + *(.bss.stcm) + } + + + __ddsc_STCM_END AlignExpr(+0, 8192) EMPTY 0 {} + .stcm.endof AlignExpr(+0, 8192) EMPTY 0 + { + } + + __STCM_end +0 EMPTY 0 {} + SCatterAssert( (LoadBase(__STCM_end) - LoadBase(__STCM_start)) <= STCM_LENGTH ) + __ram_from_data_flash_jump ImageLimit(__ram_from_data_flash) EMPTY 0 {} + ; ram initialized from flash + __ram_from_flash +0 + { + ; section.ram.from_flash + *(.ram_from_flash) + ; section.ram.code_from_flash + *(.ram_code_from_flash) + .ANY(+RW ) + *(vtable) + } + + ; Non-initialized, non-cached ram + __ram_noinit_nocache AlignExpr(+0, 32) UNINIT + { + ; section.ram.noinit_nocache + *(.ram_noinit_nocache) + *(.bss.ram_noinit_nocache) + } + + ; Zeroed, non-cached ram + __ram_zero_nocache +0 + { + ; section.ram.zero_nocache + *(.ram_nocache) + *(.bss.ram_nocache) + } + ; Execution region required to end align __ram_zero_nocache on ac6 + __ram_zero_nocache_pad (ImageLimit(__ram_zero_nocache)) EMPTY (AlignExpr(ImageLimit(__ram_zero_nocache),32) - ImageLimit(__ram_zero_nocache)) {} + + ; Non-initialized ram + __ram_noinit +0 UNINIT + { + ; section.ram.noinit + ; *(.bss.g_heap) + ; In case this execution region becomes empty due to heap placement place dummy selector + $$.$$(.$$) + } + ARM_LIB_STACK +0 UNINIT EMPTY 0 + { + } + ARM_LIB_HEAP +0 UNINIT + { + *(.bss.g_heap) + } + __post_heap +0 UNINIT + { + ; *(.bss.g_main_stack) + *(.bss.g_main_stack) + *(.ram_noinit) + *(.bss.ram_noinit) + *(.noinit) + *(.bss.noinit) + } + + ; Zeroed ram + __ram_zero +0 + { + ; section.ram.zero + *(.ram) + *(.bss.ram) + .ANY(+ZI ) + } + + ; Thread Stacks + __ram_thread_stack AlignExpr(+0, 8) UNINIT + { + *(.stack?*) + *(.bss.stack?*) + } + + + + __ddsc_RAM_END AlignExpr(+0, 8192) EMPTY 0 {} + .ram.endof AlignExpr(+0, 8192) EMPTY 0 + { + } + + __sau_ddsc_RAM_NSC AlignExpr(+0, 8192) EMPTY 0 {} + .ram.flat_nsc AlignExpr(+0, 8192) EMPTY 0 + { + } + + RAM_END +0 UNINIT EMPTY 0 {} + __RAM_end +0 EMPTY 0 {} + SCatterAssert( (LoadBase(__RAM_end) - LoadBase(__RAM_start)) <= RAM_LENGTH ) + } ; create a root region after the RAM init ERs for remainder of ROM ERs + LOAD_REGION_FLASH_JUMP +0 NOCOMPRESS + { + + __flash_readonly +0 FIXED + { + ; section.flash.readonly + *(.flash) + ; section.flash.code + *(.flash_code) + .ANY(+RO-CODE ) + .ANY(+RO-DATA ) + *(.mcuboot_sce9_key) + *(.version) + } + + + + __init_array_start +0 EMPTY 0 {} + __flash_init_array +0 FIXED + { + *(.init_array.*) + *(.init_array) + } + __init_array_end +0 EMPTY 0 {} + + + + + + __ddsc_FLASH_END AlignExpr(+0, 32768) EMPTY 0 {} + .flash.endof AlignExpr(+0, 32768) EMPTY 0 + { + } + + + __sau_ddsc_FLASH_NSC AlignExpr(+0, 32768) EMPTY 0 {} + .flash.flat_nsc AlignExpr(+0, 32768) EMPTY 0 + { + } + + + __FLASH_end +0 EMPTY 0 {} + SCatterAssert( (LoadBase(__FLASH_end) - LoadBase(__FLASH_start)) <= FLASH_LENGTH ) +} +LOAD_REGION_OPTION_SETTING_OFS0 OPTION_SETTING_OFS0_START NOCOMPRESS OPTION_SETTING_OFS0_LENGTH +{ + __OPTION_SETTING_OFS0_start +0 EMPTY 0 {} + __OPTION_SETTING_OFS0_init +0 EMPTY 0 {} + + + __ddsc_OPTION_SETTING_OFS0_START +0 EMPTY 0 {} + .option_setting_ofs0.startof +0 EMPTY 0 + { + } + + + ; Option Function Select Register 0 + __option_setting_ofs0_reg +0 FIXED + { + *(.option_setting_ofs0) + } + + + + __ddsc_OPTION_SETTING_OFS0_END +0 EMPTY 0 {} + .option_setting_ofs0.endof +0 EMPTY 0 + { + } + + + __OPTION_SETTING_OFS0_end +0 EMPTY 0 {} + SCatterAssert( (LoadBase(__OPTION_SETTING_OFS0_end) - LoadBase(__OPTION_SETTING_OFS0_start)) <= OPTION_SETTING_OFS0_LENGTH ) +} +LOAD_REGION_OPTION_SETTING_OFS2 OPTION_SETTING_OFS2_START NOCOMPRESS OPTION_SETTING_OFS2_LENGTH +{ + __OPTION_SETTING_OFS2_start +0 EMPTY 0 {} + __OPTION_SETTING_OFS2_init +0 EMPTY 0 {} + + + __ddsc_OPTION_SETTING_OFS2_START +0 EMPTY 0 {} + .option_setting_ofs2.startof +0 EMPTY 0 + { + } + + + ; Option Function Select Register 2 + __option_setting_ofs2_reg +0 FIXED + { + *(.option_setting_ofs2) + } + + + + __ddsc_OPTION_SETTING_OFS2_END +0 EMPTY 0 {} + .option_setting_ofs2.endof +0 EMPTY 0 + { + } + + + __OPTION_SETTING_OFS2_end +0 EMPTY 0 {} + SCatterAssert( (LoadBase(__OPTION_SETTING_OFS2_end) - LoadBase(__OPTION_SETTING_OFS2_start)) <= OPTION_SETTING_OFS2_LENGTH ) +} +LOAD_REGION_OPTION_SETTING_SAS OPTION_SETTING_SAS_START NOCOMPRESS OPTION_SETTING_SAS_LENGTH +{ + __OPTION_SETTING_SAS_start +0 EMPTY 0 {} + __OPTION_SETTING_SAS_init +0 EMPTY 0 {} + + + __ddsc_OPTION_SETTING_SAS_START +0 EMPTY 0 {} + .option_setting_sas.startof +0 EMPTY 0 + { + } + + + ; Startup Area Setting Register + __option_setting_sas_reg +0 FIXED + { + *(.option_setting_sas) + } + + + + __ddsc_OPTION_SETTING_SAS_END +0 EMPTY 0 {} + .option_setting_sas.endof +0 EMPTY 0 + { + } + + + __OPTION_SETTING_SAS_end +0 EMPTY 0 {} + SCatterAssert( (LoadBase(__OPTION_SETTING_SAS_end) - LoadBase(__OPTION_SETTING_SAS_start)) <= OPTION_SETTING_SAS_LENGTH ) +} +LOAD_REGION_OPTION_SETTING_OFS1 OPTION_SETTING_OFS1_START NOCOMPRESS OPTION_SETTING_OFS1_LENGTH +{ + __OPTION_SETTING_OFS1_start +0 EMPTY 0 {} + __OPTION_SETTING_OFS1_init +0 EMPTY 0 {} + + + __ddsc_OPTION_SETTING_OFS1_START +0 EMPTY 0 {} + .option_setting_ofs1.startof +0 EMPTY 0 + { + } + + + ; Option Function Select Register 1 + __option_setting_ofs1_reg +0 FIXED + { + *(.option_setting_ofs1) + } + + + + __ddsc_OPTION_SETTING_OFS1_END +0 EMPTY 0 {} + .option_setting_ofs1.endof +0 EMPTY 0 + { + } + + + __OPTION_SETTING_OFS1_end +0 EMPTY 0 {} + SCatterAssert( (LoadBase(__OPTION_SETTING_OFS1_end) - LoadBase(__OPTION_SETTING_OFS1_start)) <= OPTION_SETTING_OFS1_LENGTH ) +} +LOAD_REGION_OPTION_SETTING_OFS1_SEC OPTION_SETTING_OFS1_SEC_START NOCOMPRESS OPTION_SETTING_OFS1_SEC_LENGTH +{ + __OPTION_SETTING_OFS1_SEC_start +0 EMPTY 0 {} + __OPTION_SETTING_OFS1_SEC_init +0 EMPTY 0 {} + + + __ddsc_OPTION_SETTING_OFS1_SEC_START +0 EMPTY 0 {} + .option_setting_ofs1_sec.startof +0 EMPTY 0 + { + } + + + ; Option Function Select Register 1 Secure + __option_setting_ofs1_sec_reg +0 FIXED + { + *(.option_setting_ofs1_sec) + } + + + + __ddsc_OPTION_SETTING_OFS1_SEC_END +0 EMPTY 0 {} + .option_setting_ofs1_sec.endof +0 EMPTY 0 + { + } + + + __OPTION_SETTING_OFS1_SEC_end +0 EMPTY 0 {} + SCatterAssert( (LoadBase(__OPTION_SETTING_OFS1_SEC_end) - LoadBase(__OPTION_SETTING_OFS1_SEC_start)) <= OPTION_SETTING_OFS1_SEC_LENGTH ) +} +LOAD_REGION_OPTION_SETTING_OFS1_SEL OPTION_SETTING_OFS1_SEL_START NOCOMPRESS OPTION_SETTING_OFS1_SEL_LENGTH +{ + __OPTION_SETTING_OFS1_SEL_start +0 EMPTY 0 {} + __OPTION_SETTING_OFS1_SEL_init +0 EMPTY 0 {} + + + __ddsc_OPTION_SETTING_OFS1_SEL_START +0 EMPTY 0 {} + .option_setting_ofs1_sel.startof +0 EMPTY 0 + { + } + + + ; OFS1 Register Select + __option_setting_ofs1_sel_reg +0 FIXED + { + *(.option_setting_ofs1_sel) + } + + + + __ddsc_OPTION_SETTING_OFS1_SEL_END +0 EMPTY 0 {} + .option_setting_ofs1_sel.endof +0 EMPTY 0 + { + } + + + __OPTION_SETTING_OFS1_SEL_end +0 EMPTY 0 {} + SCatterAssert( (LoadBase(__OPTION_SETTING_OFS1_SEL_end) - LoadBase(__OPTION_SETTING_OFS1_SEL_start)) <= OPTION_SETTING_OFS1_SEL_LENGTH ) +} +LOAD_REGION_OPTION_SETTING_OFS3 OPTION_SETTING_OFS3_START NOCOMPRESS OPTION_SETTING_OFS3_LENGTH +{ + __OPTION_SETTING_OFS3_start +0 EMPTY 0 {} + __OPTION_SETTING_OFS3_init +0 EMPTY 0 {} + + + __ddsc_OPTION_SETTING_OFS3_START +0 EMPTY 0 {} + .option_setting_ofs3.startof +0 EMPTY 0 + { + } + + + ; Option Function Select Register 3 + __option_setting_ofs3_reg +0 FIXED + { + *(.option_setting_ofs3) + } + + + + __ddsc_OPTION_SETTING_OFS3_END +0 EMPTY 0 {} + .option_setting_ofs3.endof +0 EMPTY 0 + { + } + + + __OPTION_SETTING_OFS3_end +0 EMPTY 0 {} + SCatterAssert( (LoadBase(__OPTION_SETTING_OFS3_end) - LoadBase(__OPTION_SETTING_OFS3_start)) <= OPTION_SETTING_OFS3_LENGTH ) +} +LOAD_REGION_OPTION_SETTING_OFS3_SEC OPTION_SETTING_OFS3_SEC_START NOCOMPRESS OPTION_SETTING_OFS3_SEC_LENGTH +{ + __OPTION_SETTING_OFS3_SEC_start +0 EMPTY 0 {} + __OPTION_SETTING_OFS3_SEC_init +0 EMPTY 0 {} + + + __ddsc_OPTION_SETTING_OFS3_SEC_START +0 EMPTY 0 {} + .option_setting_ofs3_sec.startof +0 EMPTY 0 + { + } + + + ; Option Function Select Register 3 Secure + __option_setting_ofs3_sec_reg +0 FIXED + { + *(.option_setting_ofs3_sec) + } + + + + __ddsc_OPTION_SETTING_OFS3_SEC_END +0 EMPTY 0 {} + .option_setting_ofs3_sec.endof +0 EMPTY 0 + { + } + + + __OPTION_SETTING_OFS3_SEC_end +0 EMPTY 0 {} + SCatterAssert( (LoadBase(__OPTION_SETTING_OFS3_SEC_end) - LoadBase(__OPTION_SETTING_OFS3_SEC_start)) <= OPTION_SETTING_OFS3_SEC_LENGTH ) +} +LOAD_REGION_OPTION_SETTING_OFS3_SEL OPTION_SETTING_OFS3_SEL_START NOCOMPRESS OPTION_SETTING_OFS3_SEL_LENGTH +{ + __OPTION_SETTING_OFS3_SEL_start +0 EMPTY 0 {} + __OPTION_SETTING_OFS3_SEL_init +0 EMPTY 0 {} + + + __ddsc_OPTION_SETTING_OFS3_SEL_START +0 EMPTY 0 {} + .option_setting_ofs3_sel.startof +0 EMPTY 0 + { + } + + + ; OFS3 Register Select + __option_setting_ofs3_sel_reg +0 FIXED + { + *(.option_setting_ofs3_sel) + } + + + + __ddsc_OPTION_SETTING_OFS3_SEL_END +0 EMPTY 0 {} + .option_setting_ofs3_sel.endof +0 EMPTY 0 + { + } + + + __OPTION_SETTING_OFS3_SEL_end +0 EMPTY 0 {} + SCatterAssert( (LoadBase(__OPTION_SETTING_OFS3_SEL_end) - LoadBase(__OPTION_SETTING_OFS3_SEL_start)) <= OPTION_SETTING_OFS3_SEL_LENGTH ) +} +LOAD_REGION_OPTION_SETTING_BPS OPTION_SETTING_BPS_START NOCOMPRESS OPTION_SETTING_BPS_LENGTH +{ + __OPTION_SETTING_BPS_start +0 EMPTY 0 {} + __OPTION_SETTING_BPS_init +0 EMPTY 0 {} + + + __ddsc_OPTION_SETTING_BPS_START +0 EMPTY 0 {} + .option_setting_bps.startof +0 EMPTY 0 + { + } + + + ; Block Protect Setting Register + __option_setting_bps_reg +0 FIXED + { + *(.option_setting_bps) + } + + + + __ddsc_OPTION_SETTING_BPS_END +0 EMPTY 0 {} + .option_setting_bps.endof +0 EMPTY 0 + { + } + + + __OPTION_SETTING_BPS_end +0 EMPTY 0 {} + SCatterAssert( (LoadBase(__OPTION_SETTING_BPS_end) - LoadBase(__OPTION_SETTING_BPS_start)) <= OPTION_SETTING_BPS_LENGTH ) +} +LOAD_REGION_OPTION_SETTING_BPS_SEC OPTION_SETTING_BPS_SEC_START NOCOMPRESS OPTION_SETTING_BPS_SEC_LENGTH +{ + __OPTION_SETTING_BPS_SEC_start +0 EMPTY 0 {} + __OPTION_SETTING_BPS_SEC_init +0 EMPTY 0 {} + + + __ddsc_OPTION_SETTING_BPS_SEC_START +0 EMPTY 0 {} + .option_setting_bps_sec.startof +0 EMPTY 0 + { + } + + + ; Block Protect Setting Register Secure + __option_setting_bps_sec_reg +0 FIXED + { + *(.option_setting_bps_sec) + } + + + + __ddsc_OPTION_SETTING_BPS_SEC_END +0 EMPTY 0 {} + .option_setting_bps_sec.endof +0 EMPTY 0 + { + } + + + __OPTION_SETTING_BPS_SEC_end +0 EMPTY 0 {} + SCatterAssert( (LoadBase(__OPTION_SETTING_BPS_SEC_end) - LoadBase(__OPTION_SETTING_BPS_SEC_start)) <= OPTION_SETTING_BPS_SEC_LENGTH ) +} +LOAD_REGION_OPTION_SETTING_OTP_PBPS_SEC OPTION_SETTING_OTP_PBPS_SEC_START NOCOMPRESS OPTION_SETTING_OTP_PBPS_SEC_LENGTH +{ + __OPTION_SETTING_OTP_PBPS_SEC_start +0 EMPTY 0 {} + __OPTION_SETTING_OTP_PBPS_SEC_init +0 EMPTY 0 {} + + + __ddsc_OPTION_SETTING_OTP_PBPS_SEC_START +0 EMPTY 0 {} + .option_setting_otp_pbps_sec.startof +0 EMPTY 0 + { + } + + + ; Permanent Block Protect Setting Register Secure + __option_setting_otp_pbps_sec_reg +0 FIXED + { + *(.option_setting_otp_pbps_sec) + } + + + + __ddsc_OPTION_SETTING_OTP_PBPS_SEC_END +0 EMPTY 0 {} + .option_setting_otp_pbps_sec.endof +0 EMPTY 0 + { + } + + + __OPTION_SETTING_OTP_PBPS_SEC_end +0 EMPTY 0 {} + SCatterAssert( (LoadBase(__OPTION_SETTING_OTP_PBPS_SEC_end) - LoadBase(__OPTION_SETTING_OTP_PBPS_SEC_start)) <= OPTION_SETTING_OTP_PBPS_SEC_LENGTH ) +} +LOAD_REGION_OPTION_SETTING_OTP_PBPS OPTION_SETTING_OTP_PBPS_START NOCOMPRESS OPTION_SETTING_OTP_PBPS_LENGTH +{ + __OPTION_SETTING_OTP_PBPS_start +0 EMPTY 0 {} + __OPTION_SETTING_OTP_PBPS_init +0 EMPTY 0 {} + + + __ddsc_OPTION_SETTING_OTP_PBPS_START +0 EMPTY 0 {} + .option_setting_otp_pbps.startof +0 EMPTY 0 + { + } + + + ; Permanent Block Protect Setting Register + __option_setting_otp_pbps_reg +0 FIXED + { + *(.option_setting_otp_pbps) + } + + + + __ddsc_OPTION_SETTING_OTP_PBPS_END +0 EMPTY 0 {} + .option_setting_otp_pbps.endof +0 EMPTY 0 + { + } + + + __OPTION_SETTING_OTP_PBPS_end +0 EMPTY 0 {} + SCatterAssert( (LoadBase(__OPTION_SETTING_OTP_PBPS_end) - LoadBase(__OPTION_SETTING_OTP_PBPS_start)) <= OPTION_SETTING_OTP_PBPS_LENGTH ) +} + diff --git a/bsp/renesas/ra8p1-titan-board/m33/src/hal_entry.c b/bsp/renesas/ra8p1-titan-board/m33/src/hal_entry.c new file mode 100644 index 00000000000..985a25f9a89 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/src/hal_entry.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-03-11 kurisaW first version + */ + +#include +#include "hal_data.h" +#include +#include + +#define LED_PIN_0 BSP_IO_PORT_00_PIN_13 /* Onboard LED pins */ + +void hal_entry(void) +{ + rt_kprintf("\n==================================================\n"); + rt_kprintf("This is core1!\n"); + rt_kprintf("Hello, Titan Board!\n"); + rt_kprintf("==================================================\n"); + + rt_kprintf("\nThe dual-core project should collaborate with the SDK project for development: << Titan_dual_core0 >>\n"); + while (1) + { + rt_pin_write(LED_PIN_0, PIN_HIGH); + rt_thread_mdelay(1000); + rt_pin_write(LED_PIN_0, PIN_LOW); + rt_thread_mdelay(1000); + } +} diff --git a/bsp/renesas/ra8p1-titan-board/m33/template.uvoptx b/bsp/renesas/ra8p1-titan-board/m33/template.uvoptx new file mode 100644 index 00000000000..e7a15c50046 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/template.uvoptx @@ -0,0 +1,366 @@ + + + 1.0 +
### uVision Project, (C) Keil Software
+ + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp; *.cc; *.cxx + 0 + + + 0 + 0 + + + M33_Debug_CPU1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 1 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) + + + 0 + JL2CM3 + -O111 -N00("ARM CoreSight SW-DP") -S2 -ZTIFSpeedSel5000 -A0 -C-1 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD22000000 -FC7800 -FN3 -FF0RA8P1_1M.FLM -FS02000000 -FL0100000 -FP0($$Device:R7KA8P1KF$Flash\RA8P1_1M.FLM) -FF1RA8P1_CONF.FLM -FS102C9F040 -FL17C0 -FP1($$Device:R7KA8P1KF$Flash\RA8P1_CONF.FLM) -FF2RA8P1_OTP.FLM -FS202E07600 -FL210334 -FP2($$Device:R7KA8P1KF$Flash\RA8P1_OTP.FLM) + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 ) -FN3 -FC7800 -FD22000000 -FF0RA8P1_1M -FF1RA8P1_CONF -FF2RA8P1_OTP -FL0100000 -FL17C0 -FL210334 -FS02000000 -FS102C9F040 -FS202E07600 -FP0($$Device:R7KA8P1KF$Flash\RA8P1_1M.FLM) -FP1($$Device:R7KA8P1KF$Flash\RA8P1_CONF.FLM) -FP2($$Device:R7KA8P1KF$Flash\RA8P1_OTP.FLM) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + :Renesas RA Smart Configurator:Common Sources + 1 + 0 + 0 + 0 + + 2 + 1 + 1 + 0 + 0 + 0 + .\src\hal_entry.c + hal_entry.c + 0 + 0 + + + + ::Flex Software + 0 + 0 + 0 + 1 + + + M33_Download_CPU0 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 1 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 0 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) + + + 0 + JL2CM3 + -O111 -N00("ARM CoreSight SW-DP") -S2 -ZTIFSpeedSel5000 -A0 -C-1 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD22000000 -FC7800 -FN3 -FF0RA8P1_1M.FLM -FS02000000 -FL0100000 -FP0($$Device:R7KA8P1KF$Flash\RA8P1_1M.FLM) -FF1RA8P1_CONF.FLM -FS102C9F040 -FL17C0 -FP1($$Device:R7KA8P1KF$Flash\RA8P1_CONF.FLM) -FF2RA8P1_OTP.FLM -FS202E07600 -FL210334 -FP2($$Device:R7KA8P1KF$Flash\RA8P1_OTP.FLM) + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 ) -FN3 -FC7800 -FD22000000 -FF0RA8P1_1M -FF1RA8P1_CONF -FF2RA8P1_OTP -FL0100000 -FL17C0 -FL210334 -FS02000000 -FS102C9F040 -FS202E07600 -FP0($$Device:R7KA8P1KF$Flash\RA8P1_1M.FLM) -FP1($$Device:R7KA8P1KF$Flash\RA8P1_CONF.FLM) -FP2($$Device:R7KA8P1KF$Flash\RA8P1_OTP.FLM) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + diff --git a/bsp/renesas/ra8p1-titan-board/m33/template.uvprojx b/bsp/renesas/ra8p1-titan-board/m33/template.uvprojx new file mode 100644 index 00000000000..59f1913674b --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m33/template.uvprojx @@ -0,0 +1,782 @@ + + + 2.1 +
### uVision Project, (C) Keil Software
+ + + M33_Debug_CPU1 + 0x4 + ARM-ADS + 6190000::V6.19::ARMCLANG + 1 + + + R7KA8P1KF:CPU1 + Renesas + Renesas.RA_DFP.6.1.0 + https://www2.renesas.eu/Keil_MDK_Packs/ + CPUTYPE("Cortex-M33") DSP TZ FPU3(SFPU) CLOCK(12000000) ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD22000000 -FC7800 -FN3 -FF0RA8P1_1M -FS02000000 -FL0100000 -FF1RA8P1_CONF -FS102C9F040 -FL17C0 -FF2RA8P1_OTP -FS202E07600 -FL210334 -FP0($$Device:R7KA8P1KF$Flash\RA8P1_1M.FLM) -FP1($$Device:R7KA8P1KF$Flash\RA8P1_CONF.FLM) -FP2($$Device:R7KA8P1KF$Flash\RA8P1_OTP.FLM)) + 0 + + + + + + + + + + + $$Device:R7KA8P1KF$SVD\R7KA8P1AD.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 2 + 0 + + + 1 + 0 + cmd /c ""$Prasc_launcher.bat" "$Prasc_version.txt" -nosplash --launcher.suppressErrors --gensmartbundle --compiler ARMv6 --devicefamily ra "$Pconfiguration.xml" "$L%L" 2> "$PObjects\rasc_stderr.out"" + + 0 + 0 + 2 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMV8M.DLL + -MPU + DCM.DLL + -pCM4 + SARMV8M.DLL + -MPU + TCM.DLL + -pCM33 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 0 + 1 + 0 + 0 + 1 + -1 + + 1 + BIN\UL2V8M.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M33" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 3 + 6 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + . + + + + 0 + 0 + 0 + 0 + 0 + 0 + + + + .\script\fsp.scat + + + --entry=Reset_Handler --no_startup + + 6319,6314 + + + + + + Source Group 1 + + + :Renesas RA Smart Configurator:Common Sources + + + + ::Flex Software + + + + + M33_Download_CPU0 + 0x4 + ARM-ADS + 6190000::V6.19::ARMCLANG + 1 + + + R7KA8P1KF:CPU0 + Renesas + Renesas.RA_DFP.6.1.0 + https://www2.renesas.eu/Keil_MDK_Packs/ + CPUTYPE("Cortex-M85") DSP TZ MVE(FP) FPU3(DFPU) PACBTI CLOCK(12000000) ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD22000000 -FC7800 -FN3 -FF0RA8P1_1M -FS02000000 -FL0100000 -FF1RA8P1_CONF -FS102C9F040 -FL17C0 -FF2RA8P1_OTP -FS202E07600 -FL210334 -FP0($$Device:R7KA8P1KF$Flash\RA8P1_1M.FLM) -FP1($$Device:R7KA8P1KF$Flash\RA8P1_CONF.FLM) -FP2($$Device:R7KA8P1KF$Flash\RA8P1_OTP.FLM)) + 0 + + + + + + + + + + + $$Device:R7KA8P1KF$SVD\R7KA8P1AD.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 2 + 0 + + + 1 + 0 + cmd /c ""$Prasc_launcher.bat" "$Prasc_version.txt" -nosplash --launcher.suppressErrors --gensmartbundle --compiler ARMv6 --devicefamily ra "$Pconfiguration.xml" "$L%L" 2> "$PObjects\rasc_stderr.out"" + + 0 + 0 + 2 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMV8M.DLL + -MPU + DCM.DLL + -pCM4 + SARMV8M.DLL + -MPU -MVE -PACBTI + TCM.DLL + -pCM85 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 0 + 1 + 4102 + + 1 + BIN\UL2V8M.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M85" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 3 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 3 + 6 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + + + + + + + + + 0 + 0 + 0 + 0 + 0 + 0 + + + + .\script\fsp.scat + + + --entry=Reset_Handler --no_startup + + 6319,6314 + + + + + + + + + + + + + + + + + + + diff --git a/bsp/renesas/ra8p1-titan-board/.ci/attachconfig/attachconfig.yml b/bsp/renesas/ra8p1-titan-board/m85/.ci/attachconfig/attachconfig.yml similarity index 100% rename from bsp/renesas/ra8p1-titan-board/.ci/attachconfig/attachconfig.yml rename to bsp/renesas/ra8p1-titan-board/m85/.ci/attachconfig/attachconfig.yml diff --git a/bsp/renesas/ra8p1-titan-board/.config b/bsp/renesas/ra8p1-titan-board/m85/.config similarity index 98% rename from bsp/renesas/ra8p1-titan-board/.config rename to bsp/renesas/ra8p1-titan-board/m85/.config index 8b5566c065a..23c5a099c6e 100644 --- a/bsp/renesas/ra8p1-titan-board/.config +++ b/bsp/renesas/ra8p1-titan-board/m85/.config @@ -252,11 +252,11 @@ CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_CLOCK_TIME is not set # CONFIG_RT_USING_I2C is not set # CONFIG_RT_USING_PHY is not set # CONFIG_RT_USING_PHY_V2 is not set -# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_NULL is not set # CONFIG_RT_USING_ZERO is not set @@ -277,10 +277,10 @@ CONFIG_RT_USING_MTD_NOR=y # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_RPMSG is not set # CONFIG_RT_USING_BLK is not set # CONFIG_RT_USING_REGULATOR is not set # CONFIG_RT_USING_POWER_SUPPLY is not set -# CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers @@ -473,6 +473,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ABUP_FOTA is not set # CONFIG_PKG_USING_LIBCURL2RTT is not set # CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_ERPC is not set # CONFIG_PKG_USING_AGILE_TELNET is not set # CONFIG_PKG_USING_NMEALIB is not set # CONFIG_PKG_USING_PDULIB is not set @@ -827,7 +828,21 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set -# CONFIG_PKG_USING_MM32 is not set + +# +# MM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_MM32F103XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F3270X_CMSIS is not set +# CONFIG_PKG_USING_MM32F5260X_CMSIS is not set +# CONFIG_PKG_USING_MM32L0XX_CMSIS is not set +# CONFIG_PKG_USING_MM32L3XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F103XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F3270X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F5260X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L0XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L3XX_HAL_DRIVER is not set +# end of MM32 HAL & SDK Drivers # # WCH HAL & SDK Drivers @@ -915,6 +930,12 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set # CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set # end of FT32 HAL & SDK Drivers + +# +# NOVOSNS Drivers +# +# CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER is not set +# end of NOVOSNS Drivers # end of HAL & SDK Drivers # @@ -1098,6 +1119,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_IRUART is not set # CONFIG_PKG_USING_ST7305 is not set # CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_TCA9548A is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1199,6 +1221,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QPARAM is not set # CONFIG_PKG_USING_CorevMCU_CLI is not set # CONFIG_PKG_USING_DRMP is not set +# CONFIG_PKG_USING_AUTOGEN_PARAMETER_MANAGER is not set # end of miscellaneous packages # @@ -1440,6 +1463,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 CONFIG_SOC_FAMILY_RENESAS_RA=y CONFIG_SOC_SERIES_R7KA8P1=y +CONFIG_SOC_SERIES_R7KA8P1_CORE0=y # # Hardware Drivers Config @@ -1448,7 +1472,7 @@ CONFIG_SOC_SERIES_R7KA8P1=y # # Onboard Peripheral Drivers # -# CONFIG_BSP_START_SECONDARY_CORE is not set +CONFIG_BSP_START_SECONDARY_CORE=y # CONFIG_BSP_USING_RPMSG is not set # CONFIG_BSP_USING_FILESYSTEM is not set # CONFIG_BSP_USING_IST8310 is not set diff --git a/bsp/renesas/ra8p1-titan-board/.cproject b/bsp/renesas/ra8p1-titan-board/m85/.cproject similarity index 100% rename from bsp/renesas/ra8p1-titan-board/.cproject rename to bsp/renesas/ra8p1-titan-board/m85/.cproject diff --git a/bsp/renesas/ra8p1-titan-board/m85/.gitignore b/bsp/renesas/ra8p1-titan-board/m85/.gitignore new file mode 100644 index 00000000000..2f503652558 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/.gitignore @@ -0,0 +1,32 @@ +/RTE +/Listings +/Objects +/Debug +/build +/makefile.targets +/rtconfig.pyc +/libraries +/rt-thread +/project.custom_argvars +/.vscode +/__pycache +/settings +/rtconfig_preinc.h +/bsp_linker_info.h +/fsp_gen.ld +/memory_regions.ld +/cmake +/.api_xml +/.clangd +/.secure_azone +/.secure_rzone +/.secure_xml +/ra_cfg.txt +/packages/pkgs.json +/packages/pkgs_error.json +/output.rasc +/rasc_version.txt +/EventRecorderStub.scvd +/JLinkLog.txt +/JLinkSettings.ini +/*.uvguix.* diff --git a/bsp/renesas/ra8p1-titan-board/.project b/bsp/renesas/ra8p1-titan-board/m85/.project similarity index 100% rename from bsp/renesas/ra8p1-titan-board/.project rename to bsp/renesas/ra8p1-titan-board/m85/.project diff --git a/bsp/renesas/ra8p1-titan-board/.settings/.rtmenus b/bsp/renesas/ra8p1-titan-board/m85/.settings/.rtmenus similarity index 100% rename from bsp/renesas/ra8p1-titan-board/.settings/.rtmenus rename to bsp/renesas/ra8p1-titan-board/m85/.settings/.rtmenus diff --git a/bsp/renesas/ra8p1-titan-board/.settings/ilg.gnumcueclipse.managedbuild.cross.arm.prefs b/bsp/renesas/ra8p1-titan-board/m85/.settings/ilg.gnumcueclipse.managedbuild.cross.arm.prefs similarity index 100% rename from bsp/renesas/ra8p1-titan-board/.settings/ilg.gnumcueclipse.managedbuild.cross.arm.prefs rename to bsp/renesas/ra8p1-titan-board/m85/.settings/ilg.gnumcueclipse.managedbuild.cross.arm.prefs diff --git a/bsp/renesas/ra8p1-titan-board/.settings/language.settings.xml b/bsp/renesas/ra8p1-titan-board/m85/.settings/language.settings.xml similarity index 100% rename from bsp/renesas/ra8p1-titan-board/.settings/language.settings.xml rename to bsp/renesas/ra8p1-titan-board/m85/.settings/language.settings.xml diff --git a/bsp/renesas/ra8p1-titan-board/.settings/org.eclipse.core.resources.prefs b/bsp/renesas/ra8p1-titan-board/m85/.settings/org.eclipse.core.resources.prefs similarity index 100% rename from bsp/renesas/ra8p1-titan-board/.settings/org.eclipse.core.resources.prefs rename to bsp/renesas/ra8p1-titan-board/m85/.settings/org.eclipse.core.resources.prefs diff --git a/bsp/renesas/ra8p1-titan-board/.settings/org.eclipse.core.runtime.prefs b/bsp/renesas/ra8p1-titan-board/m85/.settings/org.eclipse.core.runtime.prefs similarity index 100% rename from bsp/renesas/ra8p1-titan-board/.settings/org.eclipse.core.runtime.prefs rename to bsp/renesas/ra8p1-titan-board/m85/.settings/org.eclipse.core.runtime.prefs diff --git a/bsp/renesas/ra8p1-titan-board/.settings/projcfg.ini b/bsp/renesas/ra8p1-titan-board/m85/.settings/projcfg.ini similarity index 100% rename from bsp/renesas/ra8p1-titan-board/.settings/projcfg.ini rename to bsp/renesas/ra8p1-titan-board/m85/.settings/projcfg.ini diff --git a/bsp/renesas/ra8p1-titan-board/.settings/standalone.prefs b/bsp/renesas/ra8p1-titan-board/m85/.settings/standalone.prefs similarity index 100% rename from bsp/renesas/ra8p1-titan-board/.settings/standalone.prefs rename to bsp/renesas/ra8p1-titan-board/m85/.settings/standalone.prefs diff --git a/bsp/renesas/ra8p1-titan-board/.settings/titan_bsp.DAPLink.Debug.rttlaunch b/bsp/renesas/ra8p1-titan-board/m85/.settings/titan_bsp.DAPLink.Debug.rttlaunch similarity index 100% rename from bsp/renesas/ra8p1-titan-board/.settings/titan_bsp.DAPLink.Debug.rttlaunch rename to bsp/renesas/ra8p1-titan-board/m85/.settings/titan_bsp.DAPLink.Debug.rttlaunch diff --git a/bsp/renesas/ra8p1-titan-board/Kconfig b/bsp/renesas/ra8p1-titan-board/m85/Kconfig similarity index 89% rename from bsp/renesas/ra8p1-titan-board/Kconfig rename to bsp/renesas/ra8p1-titan-board/m85/Kconfig index 1d2285c372d..85230cecf13 100644 --- a/bsp/renesas/ra8p1-titan-board/Kconfig +++ b/bsp/renesas/ra8p1-titan-board/m85/Kconfig @@ -2,7 +2,7 @@ mainmenu "RT-Thread Configuration" BSP_DIR := . -RTT_DIR := ../../.. +RTT_DIR := ../../../.. # you can change the RTT_ROOT default "../.." to your rtthread_root, # example : default "F:/git_repositories/rt-thread" @@ -21,7 +21,7 @@ config SOC_R7KA8P1KF source "$(RTT_DIR)/Kconfig" osource "$PKGS_DIR/Kconfig" -rsource "../libraries/Kconfig" +rsource "../../libraries/Kconfig" if !RT_USING_NANO rsource "$(BSP_DIR)/board/Kconfig" diff --git a/bsp/renesas/ra8p1-titan-board/SConscript b/bsp/renesas/ra8p1-titan-board/m85/SConscript similarity index 100% rename from bsp/renesas/ra8p1-titan-board/SConscript rename to bsp/renesas/ra8p1-titan-board/m85/SConscript diff --git a/bsp/renesas/ra8p1-titan-board/SConstruct b/bsp/renesas/ra8p1-titan-board/m85/SConstruct similarity index 87% rename from bsp/renesas/ra8p1-titan-board/SConstruct rename to bsp/renesas/ra8p1-titan-board/m85/SConstruct index 67511e3048a..ec8c43740cf 100644 --- a/bsp/renesas/ra8p1-titan-board/SConstruct +++ b/bsp/renesas/ra8p1-titan-board/m85/SConstruct @@ -5,7 +5,7 @@ import rtconfig if os.getenv('RTT_ROOT'): RTT_ROOT = os.getenv('RTT_ROOT') else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..') sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] try: @@ -34,7 +34,7 @@ if rtconfig.PLATFORM in ['iccarm']: Export('RTT_ROOT') Export('rtconfig') -SDK_ROOT = os.path.abspath('./') +SDK_ROOT = os.path.abspath('./..') if os.path.exists(SDK_ROOT + '/libraries'): libraries_path_prefix = SDK_ROOT + '/libraries' else: @@ -49,7 +49,8 @@ rtconfig.BSP_LIBRARY_TYPE = None objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) # include drivers -objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'))) +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'), + variant_dir='build/libraries/HAL_Drivers', duplicate=0)) # make a building DoBuilding(TARGET, objs) diff --git a/bsp/renesas/ra8p1-titan-board/board/Kconfig b/bsp/renesas/ra8p1-titan-board/m85/board/Kconfig similarity index 99% rename from bsp/renesas/ra8p1-titan-board/board/Kconfig rename to bsp/renesas/ra8p1-titan-board/m85/board/Kconfig index 7d1e754f491..b18466f6032 100644 --- a/bsp/renesas/ra8p1-titan-board/board/Kconfig +++ b/bsp/renesas/ra8p1-titan-board/m85/board/Kconfig @@ -111,7 +111,7 @@ menu "Hardware Drivers Config" menu "On-chip Peripheral Drivers" - rsource "../../libraries/HAL_Drivers/drivers/Kconfig" + rsource "../../../libraries/HAL_Drivers/drivers/Kconfig" menuconfig BSP_USING_UART bool "Enable UART" diff --git a/bsp/renesas/ra8p1-titan-board/m85/board/SConscript b/bsp/renesas/ra8p1-titan-board/m85/board/SConscript new file mode 100644 index 00000000000..35eedcfe573 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/board/SConscript @@ -0,0 +1,18 @@ +import os +from building import * + +objs = [] +cwd = GetCurrentDir() +list = os.listdir(cwd) +CPPPATH = [cwd] +src = Glob('*.c') + +CPPDEFINES = ['_RENESAS_RA_', '_RA_CORE=CPU0', '_RA_ORDINAL=1'] + +objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + objs = objs + SConscript(os.path.join(item, 'SConscript')) + +Return('objs') diff --git a/bsp/renesas/ra8p1-titan-board/board/board.h b/bsp/renesas/ra8p1-titan-board/m85/board/board.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/board/board.h rename to bsp/renesas/ra8p1-titan-board/m85/board/board.h diff --git a/bsp/renesas/ra8p1-titan-board/board/bsp_linker_info.h b/bsp/renesas/ra8p1-titan-board/m85/board/bsp_linker_info.h similarity index 99% rename from bsp/renesas/ra8p1-titan-board/board/bsp_linker_info.h rename to bsp/renesas/ra8p1-titan-board/m85/board/bsp_linker_info.h index 356e4ba4572..3ce6fca10a8 100644 --- a/bsp/renesas/ra8p1-titan-board/board/bsp_linker_info.h +++ b/bsp/renesas/ra8p1-titan-board/m85/board/bsp_linker_info.h @@ -18,7 +18,7 @@ #define BSP_PARTITION_RAM_CPU1_C_START (0x221D4000) #define BSP_PARTITION_RAM_CPU1_C_SIZE (0x0) #define BSP_PARTITION_FLASH_CPU0_S_START (0x02000000) -#define BSP_PARTITION_FLASH_CPU0_S_SIZE (OxCO000) +#define BSP_PARTITION_FLASH_CPU0_S_SIZE (0xC0000) #define BSP_PARTITION_FLASH_CPU0_C_START (0x020C0000) #define BSP_PARTITION_FLASH_CPU0_C_SIZE (0x0) #define BSP_PARTITION_FLASH_CPU1_S_START (0x020C0000) diff --git a/bsp/renesas/ra8p1-titan-board/board/ports/SConscript b/bsp/renesas/ra8p1-titan-board/m85/board/ports/SConscript similarity index 100% rename from bsp/renesas/ra8p1-titan-board/board/ports/SConscript rename to bsp/renesas/ra8p1-titan-board/m85/board/ports/SConscript diff --git a/bsp/renesas/ra8p1-titan-board/board/ports/drv_filesystem.c b/bsp/renesas/ra8p1-titan-board/m85/board/ports/drv_filesystem.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/board/ports/drv_filesystem.c rename to bsp/renesas/ra8p1-titan-board/m85/board/ports/drv_filesystem.c diff --git a/bsp/renesas/ra8p1-titan-board/board/ports/drv_rtl8211.c b/bsp/renesas/ra8p1-titan-board/m85/board/ports/drv_rtl8211.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/board/ports/drv_rtl8211.c rename to bsp/renesas/ra8p1-titan-board/m85/board/ports/drv_rtl8211.c diff --git a/bsp/renesas/ra8p1-titan-board/board/ports/fal_cfg.h b/bsp/renesas/ra8p1-titan-board/m85/board/ports/fal_cfg.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/board/ports/fal_cfg.h rename to bsp/renesas/ra8p1-titan-board/m85/board/ports/fal_cfg.h diff --git a/bsp/renesas/ra8p1-titan-board/board/ports/gpio_cfg.h b/bsp/renesas/ra8p1-titan-board/m85/board/ports/gpio_cfg.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/board/ports/gpio_cfg.h rename to bsp/renesas/ra8p1-titan-board/m85/board/ports/gpio_cfg.h diff --git a/bsp/renesas/ra8p1-titan-board/board/ports/gt9147_touch/SConscript b/bsp/renesas/ra8p1-titan-board/m85/board/ports/gt9147_touch/SConscript similarity index 100% rename from bsp/renesas/ra8p1-titan-board/board/ports/gt9147_touch/SConscript rename to bsp/renesas/ra8p1-titan-board/m85/board/ports/gt9147_touch/SConscript diff --git a/bsp/renesas/ra8p1-titan-board/board/ports/gt9147_touch/inc/gt9147.h b/bsp/renesas/ra8p1-titan-board/m85/board/ports/gt9147_touch/inc/gt9147.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/board/ports/gt9147_touch/inc/gt9147.h rename to bsp/renesas/ra8p1-titan-board/m85/board/ports/gt9147_touch/inc/gt9147.h diff --git a/bsp/renesas/ra8p1-titan-board/board/ports/gt9147_touch/samples/gt9147_sample.c b/bsp/renesas/ra8p1-titan-board/m85/board/ports/gt9147_touch/samples/gt9147_sample.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/board/ports/gt9147_touch/samples/gt9147_sample.c rename to bsp/renesas/ra8p1-titan-board/m85/board/ports/gt9147_touch/samples/gt9147_sample.c diff --git a/bsp/renesas/ra8p1-titan-board/board/ports/gt9147_touch/src/gt9147.c b/bsp/renesas/ra8p1-titan-board/m85/board/ports/gt9147_touch/src/gt9147.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/board/ports/gt9147_touch/src/gt9147.c rename to bsp/renesas/ra8p1-titan-board/m85/board/ports/gt9147_touch/src/gt9147.c diff --git a/bsp/renesas/ra8p1-titan-board/board/ports/hyperflash/SConscript b/bsp/renesas/ra8p1-titan-board/m85/board/ports/hyperflash/SConscript similarity index 100% rename from bsp/renesas/ra8p1-titan-board/board/ports/hyperflash/SConscript rename to bsp/renesas/ra8p1-titan-board/m85/board/ports/hyperflash/SConscript diff --git a/bsp/renesas/ra8p1-titan-board/board/ports/hyperflash/drv_ospi_flash.c b/bsp/renesas/ra8p1-titan-board/m85/board/ports/hyperflash/drv_ospi_flash.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/board/ports/hyperflash/drv_ospi_flash.c rename to bsp/renesas/ra8p1-titan-board/m85/board/ports/hyperflash/drv_ospi_flash.c diff --git a/bsp/renesas/ra8p1-titan-board/board/ports/hyperflash/ospi_b_commands.c b/bsp/renesas/ra8p1-titan-board/m85/board/ports/hyperflash/ospi_b_commands.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/board/ports/hyperflash/ospi_b_commands.c rename to bsp/renesas/ra8p1-titan-board/m85/board/ports/hyperflash/ospi_b_commands.c diff --git a/bsp/renesas/ra8p1-titan-board/board/ports/hyperflash/ospi_b_commands.h b/bsp/renesas/ra8p1-titan-board/m85/board/ports/hyperflash/ospi_b_commands.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/board/ports/hyperflash/ospi_b_commands.h rename to bsp/renesas/ra8p1-titan-board/m85/board/ports/hyperflash/ospi_b_commands.h diff --git a/bsp/renesas/ra8p1-titan-board/board/ports/hyperflash/ospi_b_ep.c b/bsp/renesas/ra8p1-titan-board/m85/board/ports/hyperflash/ospi_b_ep.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/board/ports/hyperflash/ospi_b_ep.c rename to bsp/renesas/ra8p1-titan-board/m85/board/ports/hyperflash/ospi_b_ep.c diff --git a/bsp/renesas/ra8p1-titan-board/board/ports/hyperflash/ospi_b_ep.h b/bsp/renesas/ra8p1-titan-board/m85/board/ports/hyperflash/ospi_b_ep.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/board/ports/hyperflash/ospi_b_ep.h rename to bsp/renesas/ra8p1-titan-board/m85/board/ports/hyperflash/ospi_b_ep.h diff --git a/bsp/renesas/ra8p1-titan-board/board/ports/hyperram/SConscript b/bsp/renesas/ra8p1-titan-board/m85/board/ports/hyperram/SConscript similarity index 100% rename from bsp/renesas/ra8p1-titan-board/board/ports/hyperram/SConscript rename to bsp/renesas/ra8p1-titan-board/m85/board/ports/hyperram/SConscript diff --git a/bsp/renesas/ra8p1-titan-board/board/ports/hyperram/hyper_ram_test.c b/bsp/renesas/ra8p1-titan-board/m85/board/ports/hyperram/hyper_ram_test.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/board/ports/hyperram/hyper_ram_test.c rename to bsp/renesas/ra8p1-titan-board/m85/board/ports/hyperram/hyper_ram_test.c diff --git a/bsp/renesas/ra8p1-titan-board/board/ports/hyperram/hyper_ram_test.h b/bsp/renesas/ra8p1-titan-board/m85/board/ports/hyperram/hyper_ram_test.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/board/ports/hyperram/hyper_ram_test.h rename to bsp/renesas/ra8p1-titan-board/m85/board/ports/hyperram/hyper_ram_test.h diff --git a/bsp/renesas/ra8p1-titan-board/board/ports/lcd_port.h b/bsp/renesas/ra8p1-titan-board/m85/board/ports/lcd_port.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/board/ports/lcd_port.h rename to bsp/renesas/ra8p1-titan-board/m85/board/ports/lcd_port.h diff --git a/bsp/renesas/ra8p1-titan-board/board/ports/mipi_lcd/SConscript b/bsp/renesas/ra8p1-titan-board/m85/board/ports/mipi_lcd/SConscript similarity index 100% rename from bsp/renesas/ra8p1-titan-board/board/ports/mipi_lcd/SConscript rename to bsp/renesas/ra8p1-titan-board/m85/board/ports/mipi_lcd/SConscript diff --git a/bsp/renesas/ra8p1-titan-board/board/ports/mipi_lcd/mipi_config.c b/bsp/renesas/ra8p1-titan-board/m85/board/ports/mipi_lcd/mipi_config.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/board/ports/mipi_lcd/mipi_config.c rename to bsp/renesas/ra8p1-titan-board/m85/board/ports/mipi_lcd/mipi_config.c diff --git a/bsp/renesas/ra8p1-titan-board/board/ra8_it.c b/bsp/renesas/ra8p1-titan-board/m85/board/ra8_it.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/board/ra8_it.c rename to bsp/renesas/ra8p1-titan-board/m85/board/ra8_it.c diff --git a/bsp/renesas/ra8p1-titan-board/buildinfo.json b/bsp/renesas/ra8p1-titan-board/m85/buildinfo.json similarity index 100% rename from bsp/renesas/ra8p1-titan-board/buildinfo.json rename to bsp/renesas/ra8p1-titan-board/m85/buildinfo.json diff --git a/bsp/renesas/ra8p1-titan-board/configuration.xml b/bsp/renesas/ra8p1-titan-board/m85/configuration.xml similarity index 100% rename from bsp/renesas/ra8p1-titan-board/configuration.xml rename to bsp/renesas/ra8p1-titan-board/m85/configuration.xml diff --git a/bsp/renesas/ra8p1-titan-board/figures/big.png b/bsp/renesas/ra8p1-titan-board/m85/figures/big.png similarity index 100% rename from bsp/renesas/ra8p1-titan-board/figures/big.png rename to bsp/renesas/ra8p1-titan-board/m85/figures/big.png diff --git a/bsp/renesas/ra8p1-titan-board/figures/image-20250819171348952.png b/bsp/renesas/ra8p1-titan-board/m85/figures/image-20250819171348952.png similarity index 100% rename from bsp/renesas/ra8p1-titan-board/figures/image-20250819171348952.png rename to bsp/renesas/ra8p1-titan-board/m85/figures/image-20250819171348952.png diff --git a/bsp/renesas/ra8p1-titan-board/figures/image-20250819173700386.png b/bsp/renesas/ra8p1-titan-board/m85/figures/image-20250819173700386.png similarity index 100% rename from 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bsp/renesas/ra8p1-titan-board/figures/image-20251127171037225.png rename to bsp/renesas/ra8p1-titan-board/m85/figures/image-20251127171037225.png diff --git a/bsp/renesas/ra8p1-titan-board/figures/titan_board_hw_resource.png b/bsp/renesas/ra8p1-titan-board/m85/figures/titan_board_hw_resource.png similarity index 100% rename from bsp/renesas/ra8p1-titan-board/figures/titan_board_hw_resource.png rename to bsp/renesas/ra8p1-titan-board/m85/figures/titan_board_hw_resource.png diff --git a/bsp/renesas/ra8p1-titan-board/project.uvoptx b/bsp/renesas/ra8p1-titan-board/m85/project.uvoptx similarity index 90% rename from bsp/renesas/ra8p1-titan-board/project.uvoptx rename to bsp/renesas/ra8p1-titan-board/m85/project.uvoptx index 19bf068336b..b4908b6fb24 100644 --- a/bsp/renesas/ra8p1-titan-board/project.uvoptx +++ b/bsp/renesas/ra8p1-titan-board/m85/project.uvoptx @@ -125,12 +125,12 @@ 0 JL2CM3 - -O111 -N00("ARM CoreSight SW-DP") -S2 -ZTIFSpeedSel5000 -A0 -C-1 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD0 -FC800 -FN0 + -O111 -N00("ARM CoreSight SW-DP") -S2 -ZTIFSpeedSel5000 -A0 -C-1 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD22000000 -FC7800 -FN3 -FF0RA8P1_1M.FLM -FS02000000 -FL0100000 -FP0($$Device:R7KA8P1KF$Flash\RA8P1_1M.FLM) -FF1RA8P1_CONF.FLM -FS102C9F040 -FL17C0 -FP1($$Device:R7KA8P1KF$Flash\RA8P1_CONF.FLM) -FF2RA8P1_OTP.FLM -FS202E07600 -FL210334 -FP2($$Device:R7KA8P1KF$Flash\RA8P1_OTP.FLM) 0 UL2V8M - UL2V8M(-S0 -C0 -P0 ) + UL2V8M(-S0 -C0 -P0 ) -FN3 -FC7800 -FD22000000 -FF0RA8P1_1M -FF1RA8P1_CONF -FF2RA8P1_OTP -FL0100000 -FL17C0 -FL210334 -FS02000000 -FS102C9F040 -FS202E07600 -FP0($$Device:R7KA8P1KF$Flash\RA8P1_1M.FLM) -FP1($$Device:R7KA8P1KF$Flash\RA8P1_CONF.FLM) -FP2($$Device:R7KA8P1KF$Flash\RA8P1_OTP.FLM) diff --git a/bsp/renesas/ra8p1-titan-board/m85/project.uvprojx b/bsp/renesas/ra8p1-titan-board/m85/project.uvprojx new file mode 100644 index 00000000000..d245f229f3e --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/project.uvprojx @@ -0,0 +1,1396 @@ + + + 2.1 +
### uVision Project, (C) Keil Software
+ + + Target_1 + 0x4 + ARM-ADS + 6190000::V6.19::ARMCLANG + 1 + + + R7KA8P1KF:CPU0 + Renesas + Renesas.RA_DFP.6.1.0 + https://www2.renesas.eu/Keil_MDK_Packs/ + CPUTYPE("Cortex-M85") DSP TZ MVE(FP) FPU3(DFPU) PACBTI CLOCK(12000000) ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD22000000 -FC7800 -FN3 -FF0RA8P1_1M -FS02000000 -FL0100000 -FF1RA8P1_CONF -FS102C9F040 -FL17C0 -FF2RA8P1_OTP -FS202E07600 -FL210334 -FP0($$Device:R7KA8P1KF$Flash\RA8P1_1M.FLM) -FP1($$Device:R7KA8P1KF$Flash\RA8P1_CONF.FLM) -FP2($$Device:R7KA8P1KF$Flash\RA8P1_OTP.FLM)) + 0 + + + + + + + + + + + $$Device:R7KA8P1KF$SVD\R7KA8P1AD.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 2 + 0 + + + 1 + 0 + cmd /c ""$Prasc_launcher.bat" "$Prasc_version.txt" -nosplash --launcher.suppressErrors --gensmartbundle --compiler ARMv6 --devicefamily ra "$Pconfiguration.xml" "$L%L" 2> "$PObjects\rasc_stderr.out"" + + 0 + 0 + 2 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMV8M.DLL + -MPU + DCM.DLL + -pCM4 + SARMV8M.DLL + -MPU -MVE -PACBTI + TCM.DLL + -pCM85 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 0 + 1 + 4102 + + 1 + BIN\UL2V8M.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M85" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 3 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 3 + 6 + 0 + 0 + 0 + 0 + 0 + + + __CLK_TCK=RT_TICK_PER_SECOND, RT_USING_ARMLIBC, _RA_CORE=CPU0, __RTTHREAD__, _RENESAS_RA_, __STDC_LIMIT_MACROS, RT_USING_LIBC, _RA_ORDINAL=1 + + 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+ 1 + ..\..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + + + rt_vsscanf.c + 1 + ..\..\..\..\src\klibc\rt_vsscanf.c + + + + + RA + + + bsp_clocks.c + 1 + ra\fsp\src\bsp\mcu\all\bsp_clocks.c + + + + + bsp_common.c + 1 + ra\fsp\src\bsp\mcu\all\bsp_common.c + + + + + bsp_delay.c + 1 + ra\fsp\src\bsp\mcu\all\bsp_delay.c + + + + + bsp_group_irq.c + 1 + ra\fsp\src\bsp\mcu\all\bsp_group_irq.c + + + + + bsp_guard.c + 1 + ra\fsp\src\bsp\mcu\all\bsp_guard.c + + + + + bsp_io.c + 1 + ra\fsp\src\bsp\mcu\all\bsp_io.c + + + + + bsp_ipc.c + 1 + ra\fsp\src\bsp\mcu\all\bsp_ipc.c + + + + + bsp_irq.c + 1 + ra\fsp\src\bsp\mcu\all\bsp_irq.c + + + + + bsp_macl.c + 1 + ra\fsp\src\bsp\mcu\all\bsp_macl.c + + + + + bsp_ospi_b.c + 1 + ra\fsp\src\bsp\mcu\all\bsp_ospi_b.c + + + + + bsp_register_protection.c + 1 + ra\fsp\src\bsp\mcu\all\bsp_register_protection.c + + + + + bsp_sbrk.c + 1 + ra\fsp\src\bsp\mcu\all\bsp_sbrk.c + + + + + bsp_sdram.c + 1 + ra\fsp\src\bsp\mcu\all\bsp_sdram.c + + + + + bsp_security.c + 1 + ra\fsp\src\bsp\mcu\all\bsp_security.c + + + + + bsp_linker.c + 1 + ra\fsp\src\bsp\mcu\ra8p1\bsp_linker.c + + + + + system.c + 1 + ra\fsp\src\bsp\cmsis\Device\RENESAS\Source\system.c + + + + + startup.c + 1 + ra\fsp\src\bsp\cmsis\Device\RENESAS\Source\startup.c + + + + + r_adc_b.c + 1 + ra\fsp\src\r_adc_b\r_adc_b.c + + + + + r_canfd.c + 1 + ra\fsp\src\r_canfd\r_canfd.c + + + + + r_dmac.c + 1 + ra\fsp\src\r_dmac\r_dmac.c + + + + + r_gpt.c + 1 + ra\fsp\src\r_gpt\r_gpt.c + + + + + r_iic_master.c + 1 + ra\fsp\src\r_iic_master\r_iic_master.c + + + + + r_ioport.c + 1 + ra\fsp\src\r_ioport\r_ioport.c + + + + + r_layer3_switch.c + 1 + ra\fsp\src\r_layer3_switch\r_layer3_switch.c + + + + + r_ospi_b.c + 1 + ra\fsp\src\r_ospi_b\r_ospi_b.c + + + + + r_rmac.c + 1 + ra\fsp\src\r_rmac\r_rmac.c + + + + + r_rmac_phy.c + 1 + ra\fsp\src\r_rmac_phy\r_rmac_phy.c + + + + + r_rtc.c + 1 + ra\fsp\src\r_rtc\r_rtc.c + + + + + r_sci_b_uart.c + 1 + ra\fsp\src\r_sci_b_uart\r_sci_b_uart.c + + + + + r_sdhi.c + 1 + ra\fsp\src\r_sdhi\r_sdhi.c + + + + + r_spi_b.c + 1 + ra\fsp\src\r_spi_b\r_spi_b.c + + + + + RA_gen + + + common_data.c + 1 + ra_gen\common_data.c + + + + + hal_data.c + 1 + ra_gen\hal_data.c + + + + + main.c + 1 + ra_gen\main.c + + + + + pin_data.c + 1 + ra_gen\pin_data.c + + + + + vector_data.c + 1 + ra_gen\vector_data.c + + + + + + + + + + + + + + + + + + + diff --git a/bsp/renesas/ra8p1-titan-board/ra/SConscript b/bsp/renesas/ra8p1-titan-board/m85/ra/SConscript similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/SConscript rename to bsp/renesas/ra8p1-titan-board/m85/ra/SConscript diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_armclang_a.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_armclang_a.h new file mode 100644 index 00000000000..760c6305729 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_armclang_a.h @@ -0,0 +1,392 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(A) Compiler ARMClang (Arm Compiler 6) Header File + */ + +#ifndef __CMSIS_ARMCLANG_A_H +#define __CMSIS_ARMCLANG_A_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __CMSIS_ARMCLANG_H + #error "This file must not be included directly" +#endif + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0, #0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0, #0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0, #0" : "=Q" (*ptr) : "r" (value) ); +} + + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) + { + __ASM volatile("sxtb16 %0, %1, ROR %2" : "=r"(result) : "r"(op1), "i"(rotate)); + } + else + { + result = __SXTB16(__ROR(op1, rotate)); + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) + { + __ASM volatile("sxtab16 %0, %1, %2, ROR %3" : "=r"(result) : "r"(op1), "r"(op2), "i"(rotate)); + } + else + { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return (result); +} + +#endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */ + /** @} end of group CMSIS_SIMD_intrinsics */ + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** \brief Get CPSR Register + \return CPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set + */ +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) +{ + __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory"); +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP(void) +{ + uint32_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP_usr(void) +{ + uint32_t cpsr; + uint32_t result; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV %1, sp \n" + "MSR cpsr_c, %0 \n" // no effect in USR mode + "ISB" : "=r"(cpsr), "=r"(result) : : "memory" + ); + return result; +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV sp, %1 \n" + "MSR cpsr_c, %0 \n" // no effect in USR mode + "ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory" + ); +} + +/** \brief Get FPEXC + \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); +#else + return(0); +#endif +} + +/** \brief Set FPEXC + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#endif +} + +/** @} end of CMSIS_Core_RegAccFunctions */ + + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +#include "cmsis_cp15.h" + +/** \brief Enable Floating Point Unit + + Critical section, called from undef handler, so systick is disabled + */ +__STATIC_INLINE void __FPU_Enable(void) +{ + __ASM volatile( + // Permit access to VFP/NEON, registers by modifying CPACR + " MRC p15,0,R1,c1,c0,2 \n" + " ORR R1,R1,#0x00F00000 \n" + " MCR p15,0,R1,c1,c0,2 \n" + + // Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + " ISB \n" + + // Enable VFP/NEON + " VMRS R1,FPEXC \n" + " ORR R1,R1,#0x40000000 \n" + " VMSR FPEXC,R1 \n" + + // Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + + // Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" + +#if (defined(__ARM_NEON) && (__ARM_NEON == 1)) + // Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" +#endif + + // Initialise FPSCR to a known state + " VMRS R1,FPSCR \n" + " LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + " AND R1,R1,R2 \n" + " VMSR FPSCR,R1 " + : : : "cc", "r1", "r2" + ); +} + +#endif /* __CMSIS_ARMCLANG_A_H */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_clang_a.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_clang_a.h new file mode 100644 index 00000000000..91ca6a2a590 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_clang_a.h @@ -0,0 +1,386 @@ +/* + * Copyright (c) 2023-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(A) Compiler LLVM/Clang Header File + */ + +#ifndef __CMSIS_CLANG_A_H +#define __CMSIS_CLANG_A_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __CMSIS_CLANG_H + #error "This file must not be included directly" +#endif +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0, #0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0, #0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0, #0" : "=Q" (*ptr) : "r" (value) ); +} + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) + { + __ASM volatile("sxtb16 %0, %1, ROR %2" : "=r"(result) : "r"(op1), "i"(rotate)); + } + else + { + result = __SXTB16(__ROR(op1, rotate)); + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) + { + __ASM volatile("sxtab16 %0, %1, %2, ROR %3" : "=r"(result) : "r"(op1), "r"(op2), "i"(rotate)); + } + else + { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return (result); +} + +#endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */ + /** @} end of group CMSIS_SIMD_intrinsics */ + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** \brief Get CPSR Register + \return CPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set + */ +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) +{ + __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory"); +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP(void) +{ + uint32_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP_usr(void) +{ + uint32_t cpsr; + uint32_t result; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV %1, sp \n" + "MSR cpsr_c, %0 \n" // no effect in USR mode + "ISB" : "=r"(cpsr), "=r"(result) : : "memory" + ); + return result; +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV sp, %1 \n" + "MSR cpsr_c, %0 \n" // no effect in USR mode + "ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory" + ); +} + +/** \brief Get FPEXC + \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); +#else + return(0); +#endif +} + +/** \brief Set FPEXC + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#endif +} + +/** @} end of CMSIS_Core_RegAccFunctions */ + + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +#include "cmsis_cp15.h" + +/** \brief Enable Floating Point Unit + + Critical section, called from undef handler, so systick is disabled + */ +__STATIC_INLINE void __FPU_Enable(void) +{ + // Permit access to VFP/NEON, registers by modifying CPACR + const uint32_t cpacr = __get_CPACR(); + __set_CPACR(cpacr | 0x00F00000ul); + __ISB(); + + // Enable VFP/NEON + const uint32_t fpexc = __get_FPEXC(); + __set_FPEXC(fpexc | 0x40000000ul); + + __ASM volatile( + // Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + + // Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" + +#if (defined(__ARM_NEON) && (__ARM_NEON == 1)) + // Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" +#endif + : : : "cc", "r2" + ); + + // Initialise FPSCR to a known state + const uint32_t fpscr = __get_FPSCR(); + __set_FPSCR(fpscr & 0x00086060ul); +} + +/*@} end of group CMSIS_Core_intrinsics */ + +#pragma clang diagnostic pop + +#endif /* __CMSIS_CLANG_A_H */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_cp15.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_cp15.h new file mode 100644 index 00000000000..582b1bc54fe --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_cp15.h @@ -0,0 +1,564 @@ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(A) Compiler Specific Macros, Functions, Instructions + */ + +#ifndef __CMSIS_CP15_H +#define __CMSIS_CP15_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +/** \brief Get ACTLR + \return Auxiliary Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_ACTLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 1); + return(result); +} + +/** \brief Set ACTLR + \param [in] actlr Auxiliary Control value to set + */ +__STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr) +{ + __set_CP(15, 0, actlr, 1, 0, 1); +} + +/** \brief Get CPACR + \return Coprocessor Access Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPACR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 2); + return result; +} + +/** \brief Set CPACR + \param [in] cpacr Coprocessor Access Control value to set + */ +__STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr) +{ + __set_CP(15, 0, cpacr, 1, 0, 2); +} + +/** \brief Get DFSR + \return Data Fault Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_DFSR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 5, 0, 0); + return result; +} + +/** \brief Set DFSR + \param [in] dfsr Data Fault Status value to set + */ +__STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr) +{ + __set_CP(15, 0, dfsr, 5, 0, 0); +} + +/** \brief Get IFSR + \return Instruction Fault Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IFSR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 5, 0, 1); + return result; +} + +/** \brief Set IFSR + \param [in] ifsr Instruction Fault Status value to set + */ +__STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr) +{ + __set_CP(15, 0, ifsr, 5, 0, 1); +} + +/** \brief Get ISR + \return Interrupt Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_ISR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 1, 0); + return result; +} + +/** \brief Get CBAR + \return Configuration Base Address register value + */ +__STATIC_FORCEINLINE uint32_t __get_CBAR(void) +{ + uint32_t result; + __get_CP(15, 4, result, 15, 0, 0); + return result; +} + +/** \brief Get TTBR0 + + This function returns the value of the Translation Table Base Register 0. + + \return Translation Table Base Register 0 value + */ +__STATIC_FORCEINLINE uint32_t __get_TTBR0(void) +{ + uint32_t result; + __get_CP(15, 0, result, 2, 0, 0); + return result; +} + +/** \brief Set TTBR0 + + This function assigns the given value to the Translation Table Base Register 0. + + \param [in] ttbr0 Translation Table Base Register 0 value to set + */ +__STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0) +{ + __set_CP(15, 0, ttbr0, 2, 0, 0); +} + +/** \brief Get DACR + + This function returns the value of the Domain Access Control Register. + + \return Domain Access Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_DACR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 3, 0, 0); + return result; +} + +/** \brief Set DACR + + This function assigns the given value to the Domain Access Control Register. + + \param [in] dacr Domain Access Control Register value to set + */ +__STATIC_FORCEINLINE void __set_DACR(uint32_t dacr) +{ + __set_CP(15, 0, dacr, 3, 0, 0); +} + +/** \brief Set SCTLR + + This function assigns the given value to the System Control Register. + + \param [in] sctlr System Control Register value to set + */ +__STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr) +{ + __set_CP(15, 0, sctlr, 1, 0, 0); +} + +/** \brief Get SCTLR + \return System Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_SCTLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 0); + return result; +} + +/** \brief Get MPIDR + + This function returns the value of the Multiprocessor Affinity Register. + + \return Multiprocessor Affinity Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MPIDR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 0, 5); + return result; +} + +/** \brief Get VBAR + + This function returns the value of the Vector Base Address Register. + + \return Vector Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_VBAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 0, 0); + return result; +} + +/** \brief Set VBAR + + This function assigns the given value to the Vector Base Address Register. + + \param [in] vbar Vector Base Address Register value to set + */ +__STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar) +{ + __set_CP(15, 0, vbar, 12, 0, 0); +} + +/** \brief Get MVBAR + + This function returns the value of the Monitor Vector Base Address Register. + + \return Monitor Vector Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_MVBAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 0, 1); + return result; +} + +/** \brief Set MVBAR + + This function assigns the given value to the Monitor Vector Base Address Register. + + \param [in] mvbar Monitor Vector Base Address Register value to set + */ +__STATIC_FORCEINLINE void __set_MVBAR(uint32_t mvbar) +{ + __set_CP(15, 0, mvbar, 12, 0, 1); +} + +#if (defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \ + defined(DOXYGEN) + +/** \brief Set CNTFRQ + + This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ). + + \param [in] value CNTFRQ Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value) +{ + __set_CP(15, 0, value, 14, 0, 0); +} + +/** \brief Get CNTFRQ + + This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ). + + \return CNTFRQ Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 0 , 0); + return result; +} + +/** \brief Set CNTP_TVAL + + This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL). + + \param [in] value CNTP_TVAL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 2, 0); +} + +/** \brief Get CNTP_TVAL + + This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL). + + \return CNTP_TVAL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 2, 0); + return result; +} + +/** \brief Get CNTPCT + + This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT). + + \return CNTPCT Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTPCT(void) +{ + uint64_t result; + __get_CP64(15, 0, result, 14); + return result; +} + +/** \brief Set CNTP_CVAL + + This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + + \param [in] value CNTP_CVAL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value) +{ + __set_CP64(15, 2, value, 14); +} + +/** \brief Get CNTP_CVAL + + This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + + \return CNTP_CVAL Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void) +{ + uint64_t result; + __get_CP64(15, 2, result, 14); + return result; +} + +/** \brief Set CNTP_CTL + + This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL). + + \param [in] value CNTP_CTL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 2, 1); +} + +/** \brief Get CNTP_CTL register + \return CNTP_CTL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 2, 1); + return result; +} + +/******************************* VIRTUAL TIMER *******************************/ +/** see [ARM DDI 0406C.d] : + . §B4.1.31 "CNTV_CTL, Counter-timer Virtual Timer Control register" + . §B4.1.32 "CNTV_CVAL, Counter-timer Virtual Timer CompareValue register" + . §B4.1.33 "CNTV_TVAL, Counter-timer Virtual Timer TimerValue register" + . §B4.1.34 "CNTVCT, Counter-timer Virtual Count register" +**/ +/** \brief Set CNTV_TVAL + This function assigns the given value to VL1 Virtual Timer Value Register (CNTV_TVAL). + \param [in] value CNTV_TVAL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTV_TVAL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 3, 0); +} + +/** \brief Get CNTV_TVAL + This function returns the value of the VL1 Virtual Timer Value Register (CNTV_TVAL). + \return CNTV_TVAL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTV_TVAL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 3, 0); + return result; +} + +/** \brief Get CNTVCT + This function returns the value of the 64 bits VL1 Virtual Count Register (CNTVCT). + \return CNTVCT Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTVCT(void) +{ + uint64_t result; + __get_CP64(15, 1, result, 14); + return result; +} + +/** \brief Set CNTV_CVAL + This function assigns the given value to 64bits VL1 Virtual Timer CompareValue Register (CNTV_CVAL). + \param [in] value CNTV_CVAL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTV_CVAL(uint64_t value) +{ + __set_CP64(15, 3, value, 14); +} + +/** \brief Get CNTV_CVAL + This function returns the value of the 64 bits VL1 Virtual Timer CompareValue Register (CNTV_CVAL). + \return CNTV_CVAL Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTV_CVAL(void) +{ + uint64_t result; + __get_CP64(15, 3, result, 14); + return result; +} + +/** \brief Set CNTV_CTL + This function assigns the given value to VL1 Virtual Timer Control Register (CNTV_CTL). + \param [in] value CNTV_CTL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTV_CTL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 3, 1); +} + +/** \brief Get CNTV_CTL register + \return CNTV_CTL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTV_CTL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 3, 1); + return result; +} + +/***************************** VIRTUAL TIMER END *****************************/ +#endif + +/** \brief Set TLBIALL + + TLB Invalidate All + */ +__STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value) +{ + __set_CP(15, 0, value, 8, 7, 0); +} + +/** \brief Set BPIALL. + + Branch Predictor Invalidate All + */ +__STATIC_FORCEINLINE void __set_BPIALL(uint32_t value) +{ + __set_CP(15, 0, value, 7, 5, 6); +} + +/** \brief Set ICIALLU + + Instruction Cache Invalidate All + */ +__STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value) +{ + __set_CP(15, 0, value, 7, 5, 0); +} + +/** \brief Set ICIMVAC + + Instruction Cache Invalidate + */ +__STATIC_FORCEINLINE void __set_ICIMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 5, 1); +} + +/** \brief Set DCCMVAC + + Data cache clean + */ +__STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 10, 1); +} + +/** \brief Set DCIMVAC + + Data cache invalidate + */ +__STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 6, 1); +} + +/** \brief Set DCCIMVAC + + Data cache clean and invalidate + */ +__STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 14, 1); +} + +/** \brief Set CSSELR + */ +__STATIC_FORCEINLINE void __set_CSSELR(uint32_t value) +{ + __set_CP(15, 2, value, 0, 0, 0); +} + +/** \brief Get CSSELR + \return CSSELR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CSSELR(void) +{ + uint32_t result; + __get_CP(15, 2, result, 0, 0, 0); + return result; +} + +/** \brief Get CCSIDR + \return CCSIDR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void) +{ + uint32_t result; + __get_CP(15, 1, result, 0, 0, 0); + return result; +} + +/** \brief Get CLIDR + \return CLIDR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CLIDR(void) +{ + uint32_t result; + __get_CP(15, 1, result, 0, 0, 1); + return result; +} + +/** \brief Set DCISW + */ +__STATIC_FORCEINLINE void __set_DCISW(uint32_t value) +{ + __set_CP(15, 0, value, 7, 6, 2); +} + +/** \brief Set DCCSW + */ +__STATIC_FORCEINLINE void __set_DCCSW(uint32_t value) +{ + __set_CP(15, 0, value, 7, 10, 2); +} + +/** \brief Set DCCISW + */ +__STATIC_FORCEINLINE void __set_DCCISW(uint32_t value) +{ + __set_CP(15, 0, value, 7, 14, 2); +} + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_gcc_a.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_gcc_a.h new file mode 100644 index 00000000000..5d2aaca75dd --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_gcc_a.h @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_A_H +#define __CMSIS_GCC_A_H + +#ifndef __CMSIS_GCC_H + #error "This file must not be included directly" +#endif + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + + +/** \defgroup CMSIS_Core_intrinsics CMSIS Core Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +/** \brief Get CPSR Register + \return CPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set + */ +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) +{ + __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory"); +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP(void) +{ + uint32_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP_usr(void) +{ + uint32_t cpsr = __get_CPSR(); + uint32_t result; + __ASM volatile( + "CPS #0x1F \n" + "MOV %0, sp " : "=r"(result) : : "memory" + ); + __set_CPSR(cpsr); + __ISB(); + return result; +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr = __get_CPSR(); + __ASM volatile( + "CPS #0x1F \n" + "MOV sp, %0 " : : "r" (topOfProcStack) : "memory" + ); + __set_CPSR(cpsr); + __ISB(); +} + +/** \brief Get FPEXC + \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); +#else + return(0); +#endif +} + +/** \brief Set FPEXC + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#endif +} + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +#include "cmsis_cp15.h" + +/** \brief Enable Floating Point Unit + + Critical section, called from undef handler, so systick is disabled + */ +__STATIC_INLINE void __FPU_Enable(void) +{ + // Permit access to VFP/NEON, registers by modifying CPACR + const uint32_t cpacr = __get_CPACR(); + __set_CPACR(cpacr | 0x00F00000ul); + __ISB(); + + // Enable VFP/NEON + const uint32_t fpexc = __get_FPEXC(); + __set_FPEXC(fpexc | 0x40000000ul); + + __ASM volatile( + // Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + + // Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" + +#if (defined(__ARM_NEON) && (__ARM_NEON == 1)) + // Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" +#endif + : : : "cc", "r2" + ); + + // Initialise FPSCR to a known state + const uint32_t fpscr = __get_FPSCR(); + __set_FPSCR(fpscr & 0x00086060ul); +} + +/*@} end of group CMSIS_Core_intrinsics */ + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_A_H */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_iccarm_a.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_iccarm_a.h new file mode 100644 index 00000000000..3ddd0ba79a4 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_iccarm_a.h @@ -0,0 +1,558 @@ +/* + * Copyright (c) 2017-2018 IAR Systems + * Copyright (c) 2018-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(A) Compiler ICCARM (IAR Compiler for Arm) Header File + */ + +#ifndef __CMSIS_ICCARM_A_H__ +#define __CMSIS_ICCARM_A_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#pragma language=extended + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_7A__ +/* Macro already defined */ +#else + #if defined(__ARM7A__) + #define __ARM_ARCH_7A__ 1 + #endif +#endif + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif + +#ifndef __UNALIGNED_UINT16_READ + #pragma language=save + #pragma language=extended + __IAR_FT uint16_t __iar_uint16_read(void const *ptr) + { + return *(__packed uint16_t*)(ptr); + } + #pragma language=restore + #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE + #pragma language=save + #pragma language=extended + __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) + { + *(__packed uint16_t*)(ptr) = val;; + } + #pragma language=restore + #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ + #pragma language=save + #pragma language=extended + __IAR_FT uint32_t __iar_uint32_read(void const *ptr) + { + return *(__packed uint32_t*)(ptr); + } + #pragma language=restore + #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE + #pragma language=save + #pragma language=extended + __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) + { + *(__packed uint32_t*)(ptr) = val;; + } + #pragma language=restore + #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_CPSR() (__arm_rsr("CPSR")) + #define __get_mode() (__get_CPSR() & 0x1FU) + + #define __set_CPSR(VALUE) (__arm_wsr("CPSR", (VALUE))) + #define __set_mode(VALUE) (__arm_wsr("CPSR_c", (VALUE))) + + + #define __get_FPEXC() (__arm_rsr("FPEXC")) + #define __set_FPEXC(VALUE) (__arm_wsr("FPEXC", VALUE)) + + #define __get_CP(cp, op1, RT, CRn, CRm, op2) \ + ((RT) = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2)) + + #define __set_CP(cp, op1, RT, CRn, CRm, op2) \ + (__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, (RT))) + + #define __get_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) + + #define __set_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + + #include "cmsis_cp15.h" + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #define __SSAT __iar_builtin_SSAT + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #define __USAT __iar_builtin_USAT + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if !((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if !((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))) + #define __get_FPSCR() (0) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + __IAR_FT void __set_mode(uint32_t mode) + { + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); + } + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + __IAR_FT uint32_t __get_FPEXC(void) + { + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); + #else + return(0); + #endif + } + + __IAR_FT void __set_FPEXC(uint32_t fpexc) + { + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); + #endif + } + + + #define __get_CP(cp, op1, Rt, CRn, CRm, op2) \ + __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) + #define __set_CP(cp, op1, Rt, CRn, CRm, op2) \ + __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) + #define __get_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) + #define __set_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + + #include "cmsis_cp15.h" + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + + +__IAR_FT uint32_t __get_SP_usr(void) +{ + uint32_t cpsr; + uint32_t result; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV %1, sp \n" + "MSR cpsr_c, %2 \n" // no effect in USR mode + "ISB" : "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory" + ); + return result; +} + +__IAR_FT void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV sp, %1 \n" + "MSR cpsr_c, %2 \n" // no effect in USR mode + "ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory" + ); +} + +#define __get_mode() (__get_CPSR() & 0x1FU) + +__STATIC_INLINE +void __FPU_Enable(void) +{ + __ASM volatile( + //Permit access to VFP/NEON, registers by modifying CPACR + " MRC p15,0,R1,c1,c0,2 \n" + " ORR R1,R1,#0x00F00000 \n" + " MCR p15,0,R1,c1,c0,2 \n" + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + " ISB \n" + + //Enable VFP/NEON + " VMRS R1,FPEXC \n" + " ORR R1,R1,#0x40000000 \n" + " VMSR FPEXC,R1 \n" + + //Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + + //Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" + +#ifdef __ARM_ADVANCED_SIMD__ + //Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" +#endif + + //Initialise FPSCR to a known state + " VMRS R1,FPSCR \n" + " MOV32 R2,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + " AND R1,R1,R2 \n" + " VMSR FPSCR,R1 \n" + : : : "cc", "r1", "r2" + ); +} + + + +#undef __IAR_FT +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_A_H__ */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/irq_ctrl.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/irq_ctrl.h new file mode 100644 index 00000000000..7264fb9367f --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/irq_ctrl.h @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2017-2020 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(A) Interrupt Controller API Header File + */ + +#ifndef IRQ_CTRL_H_ +#define IRQ_CTRL_H_ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#include + +#ifndef IRQHANDLER_T +#define IRQHANDLER_T +/// Interrupt handler data type +typedef void (*IRQHandler_t) (void); +#endif + +#ifndef IRQN_ID_T +#define IRQN_ID_T +/// Interrupt ID number data type +typedef int32_t IRQn_ID_t; +#endif + +/* Interrupt mode bit-masks */ +#define IRQ_MODE_TRIG_Pos (0U) +#define IRQ_MODE_TRIG_Msk (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) +#define IRQ_MODE_TRIG_LEVEL (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt +#define IRQ_MODE_TRIG_LEVEL_LOW (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt +#define IRQ_MODE_TRIG_LEVEL_HIGH (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt +#define IRQ_MODE_TRIG_EDGE (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt +#define IRQ_MODE_TRIG_EDGE_RISING (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt +#define IRQ_MODE_TRIG_EDGE_FALLING (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt +#define IRQ_MODE_TRIG_EDGE_BOTH (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt + +#define IRQ_MODE_TYPE_Pos (3U) +#define IRQ_MODE_TYPE_Msk (0x01UL << IRQ_MODE_TYPE_Pos) +#define IRQ_MODE_TYPE_IRQ (0x00UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU IRQ line +#define IRQ_MODE_TYPE_FIQ (0x01UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU FIQ line + +#define IRQ_MODE_DOMAIN_Pos (4U) +#define IRQ_MODE_DOMAIN_Msk (0x01UL << IRQ_MODE_DOMAIN_Pos) +#define IRQ_MODE_DOMAIN_NONSECURE (0x00UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting non-secure domain +#define IRQ_MODE_DOMAIN_SECURE (0x01UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting secure domain + +#define IRQ_MODE_CPU_Pos (5U) +#define IRQ_MODE_CPU_Msk (0xFFUL << IRQ_MODE_CPU_Pos) +#define IRQ_MODE_CPU_ALL (0x00UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets all CPUs +#define IRQ_MODE_CPU_0 (0x01UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 0 +#define IRQ_MODE_CPU_1 (0x02UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 1 +#define IRQ_MODE_CPU_2 (0x04UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 2 +#define IRQ_MODE_CPU_3 (0x08UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 3 +#define IRQ_MODE_CPU_4 (0x10UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 4 +#define IRQ_MODE_CPU_5 (0x20UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 5 +#define IRQ_MODE_CPU_6 (0x40UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 6 +#define IRQ_MODE_CPU_7 (0x80UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 7 + +// Encoding in some early GIC implementations +#define IRQ_MODE_MODEL_Pos (13U) +#define IRQ_MODE_MODEL_Msk (0x1UL << IRQ_MODE_MODEL_Pos) +#define IRQ_MODE_MODEL_NN (0x0UL << IRQ_MODE_MODEL_Pos) ///< Corresponding interrupt is handled using the N-N model +#define IRQ_MODE_MODEL_1N (0x1UL << IRQ_MODE_MODEL_Pos) ///< Corresponding interrupt is handled using the 1-N model + +#define IRQ_MODE_ERROR (0x80000000UL) ///< Bit indicating mode value error + +/* Interrupt priority bit-masks */ +#define IRQ_PRIORITY_Msk (0x0000FFFFUL) ///< Interrupt priority value bit-mask +#define IRQ_PRIORITY_ERROR (0x80000000UL) ///< Bit indicating priority value error + +/// Initialize interrupt controller. +/// \return 0 on success, -1 on error. +int32_t IRQ_Initialize (void); + +/// Register interrupt handler. +/// \param[in] irqn interrupt ID number +/// \param[in] handler interrupt handler function address +/// \return 0 on success, -1 on error. +int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler); + +/// Get the registered interrupt handler. +/// \param[in] irqn interrupt ID number +/// \return registered interrupt handler function address. +IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn); + +/// Enable interrupt. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_Enable (IRQn_ID_t irqn); + +/// Disable interrupt. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_Disable (IRQn_ID_t irqn); + +/// Get interrupt enable state. +/// \param[in] irqn interrupt ID number +/// \return 0 - interrupt is disabled, 1 - interrupt is enabled. +uint32_t IRQ_GetEnableState (IRQn_ID_t irqn); + +/// Configure interrupt request mode. +/// \param[in] irqn interrupt ID number +/// \param[in] mode mode configuration +/// \return 0 on success, -1 on error. +int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode); + +/// Get interrupt mode configuration. +/// \param[in] irqn interrupt ID number +/// \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set. +uint32_t IRQ_GetMode (IRQn_ID_t irqn); + +/// Get ID number of current interrupt request (IRQ). +/// \return interrupt ID number. +IRQn_ID_t IRQ_GetActiveIRQ (void); + +/// Get ID number of current fast interrupt request (FIQ). +/// \return interrupt ID number. +IRQn_ID_t IRQ_GetActiveFIQ (void); + +/// Signal end of interrupt processing. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn); + +/// Set interrupt pending flag. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPending (IRQn_ID_t irqn); + +/// Get interrupt pending flag. +/// \param[in] irqn interrupt ID number +/// \return 0 - interrupt is not pending, 1 - interrupt is pending. +uint32_t IRQ_GetPending (IRQn_ID_t irqn); + +/// Clear interrupt pending flag. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_ClearPending (IRQn_ID_t irqn); + +/// Set interrupt priority value. +/// \param[in] irqn interrupt ID number +/// \param[in] priority interrupt priority value +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority); + +/// Get interrupt priority. +/// \param[in] irqn interrupt ID number +/// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set. +uint32_t IRQ_GetPriority (IRQn_ID_t irqn); + +/// Set priority masking threshold. +/// \param[in] priority priority masking threshold value +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPriorityMask (uint32_t priority); + +/// Get priority masking threshold +/// \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set. +uint32_t IRQ_GetPriorityMask (void); + +/// Set priority grouping field split point +/// \param[in] bits number of MSB bits included in the group priority field comparison +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPriorityGroupBits (uint32_t bits); + +/// Get priority grouping field split point +/// \return current number of MSB bits included in the group priority field comparison with +/// optional IRQ_PRIORITY_ERROR bit set. +uint32_t IRQ_GetPriorityGroupBits (void); + +#endif // IRQ_CTRL_H_ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_armclang.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_armclang.h new file mode 100644 index 00000000000..446d21a918f --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_armclang.h @@ -0,0 +1,707 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V6.0.0 + * @date 27. July 2024 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#if (__ARM_ACLE >= 200) + #include +#else + #error Compiler must support ACLE V2.0 +#endif /* (__ARM_ACLE >= 200) */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif +#ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".bss.noinit"))) +#endif +#ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __nop() + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __wfi() + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __wfe() + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __sev() + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __rev(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __rev16(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) __revsh(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR(op1, op2) __ror(op1, op2) + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT(value) __rbit(value) + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ(value) __clz(value) + + +#if ((__ARM_FEATURE_SAT >= 1) && \ + (__ARM_ARCH_ISA_THUMB >= 2) ) +/* __ARM_FEATURE_SAT is wrong for Armv8-M Baseline devices */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(value, sat) __ssat(value, sat) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(value, sat) __usat(value, sat) + +#else /* (__ARM_FEATURE_SAT >= 1) */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return (max); + } + else if (val < min) + { + return (min); + } + } + return (val); +} + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return (max); + } + else if (val < 0) + { + return (0U); + } + } + return ((uint32_t)val); +} +#endif /* (__ARM_FEATURE_SAT >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 1) +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 2) +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 2) */ + + +#if (__ARM_FEATURE_LDREX >= 4) +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 4) */ + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); + return (result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return (result); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return (result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* (__ARM_ARCH >= 8) */ + +/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} +#endif + + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + return (__builtin_arm_get_fpscr()); +#else + return (0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + __builtin_arm_set_fpscr(fpscr); +#else + (void)fpscr; +#endif +} + +/** @} end of CMSIS_Core_RegAccFunctions */ + +// Include the profile specific settings: +#if __ARM_ARCH_PROFILE == 'A' + #include "./a-profile/cmsis_armclang_a.h" +#elif __ARM_ARCH_PROFILE == 'R' + #include "./r-profile/cmsis_armclang_r.h" +#elif __ARM_ARCH_PROFILE == 'M' + #include "./m-profile/cmsis_armclang_m.h" +#else + #error "Unknown Arm architecture profile" +#endif + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_clang.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_clang.h new file mode 100644 index 00000000000..872e16c838a --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_clang.h @@ -0,0 +1,708 @@ +/**************************************************************************//** + * @file cmsis_clang.h + * @brief CMSIS compiler LLVM/Clang header file + * @version V6.0.0 + * @date 27. July 2024 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_CLANG_H +#define __CMSIS_CLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#if (__ARM_ACLE >= 200) + #include +#else + #error Compiler must support ACLE V2.0 +#endif /* (__ARM_ACLE >= 200) */ + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif +#ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) +#endif +#ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __nop() + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __wfi() + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __wfe() + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __sev() + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __rev(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __rev16(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) __revsh(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR(op1, op2) __ror(op1, op2) + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT(value) __rbit(value) + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ(value) __clz(value) + + +#if ((__ARM_FEATURE_SAT >= 1) && \ + (__ARM_ARCH_ISA_THUMB >= 2) ) +/* __ARM_FEATURE_SAT is wrong for Armv8-M Baseline devices */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(value, sat) __ssat(value, sat) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(value, sat) __usat(value, sat) + +#else /* (__ARM_FEATURE_SAT >= 1) */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return (max); + } + else if (val < min) + { + return (min); + } + } + return (val); +} + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return (max); + } + else if (val < 0) + { + return (0U); + } + } + return ((uint32_t)val); +} +#endif /* (__ARM_FEATURE_SAT >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 1) +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 2) +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 2) */ + + +#if (__ARM_FEATURE_LDREX >= 4) +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 4) */ + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); + return (result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return (result); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return (result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* (__ARM_ARCH >= 8) */ + +/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} +#endif + + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + return (__builtin_arm_get_fpscr()); +#else + return (0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + __builtin_arm_set_fpscr(fpscr); +#else + (void)fpscr; +#endif +} + +/** @} end of CMSIS_Core_RegAccFunctions */ + +// Include the profile specific settings: +#if __ARM_ARCH_PROFILE == 'A' + #include "./a-profile/cmsis_clang_a.h" +#elif __ARM_ARCH_PROFILE == 'R' + #include "./r-profile/cmsis_clang_r.h" +#elif __ARM_ARCH_PROFILE == 'M' + #include "./m-profile/cmsis_clang_m.h" +#else + #error "Unknown Arm architecture profile" +#endif + +#endif /* __CMSIS_CLANG_H */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_compiler.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_compiler.h new file mode 100644 index 00000000000..cf3f5b027dd --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_compiler.h @@ -0,0 +1,292 @@ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Compiler Generic Header File + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler above 6.10.1 (armclang) + */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + +/* + * TI Arm Clang Compiler (tiarmclang) + */ +#elif defined (__ti__) + #include "cmsis_tiarmclang.h" + + +/* + * LLVM/Clang Compiler + */ +#elif defined ( __clang__ ) + #include "cmsis_clang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #if __ARM_ARCH_PROFILE == 'A' + #include "a-profile/cmsis_iccarm_a.h" + #elif __ARM_ARCH_PROFILE == 'R' + #include "r-profile/cmsis_iccarm_r.h" + #elif __ARM_ARCH_PROFILE == 'M' + #include "m-profile/cmsis_iccarm_m.h" + #else + #error "Unknown Arm architecture profile" + #endif + + +/* + * TI Arm Compiler (armcl) + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + #ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) + #endif + #ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) + #endif + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + #ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) + #endif + #ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) + #endif + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + #ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) + #endif + #ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) + #endif + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_gcc.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_gcc.h new file mode 100644 index 00000000000..4771466f065 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_gcc.h @@ -0,0 +1,1006 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V6.0.0 + * @date 27. July 2024 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +#pragma GCC system_header /* treat file as system include file */ + +#include + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif +#ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) +#endif +#ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ + return __builtin_bswap32(value); +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return (result); +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ + return (int16_t)__builtin_bswap16(value); +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if (__ARM_ARCH_ISA_THUMB >= 2) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return (result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if (__ARM_FEATURE_SAT >= 1) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(value, sat) __ssat(value, sat) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(value, sat) __usat(value, sat) + +#else /* (__ARM_FEATURE_SAT >= 1) */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return (max); + } + else if (val < min) + { + return (min); + } + } + return (val); +} + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return (max); + } + else if (val < 0) + { + return (0U); + } + } + return ((uint32_t)val); +} +#endif /* (__ARM_FEATURE_SAT >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 1) +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return (result); +} +#endif /* (__ARM_FEATURE_LDREX >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 2) +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return (result); +} +#endif /* (__ARM_FEATURE_LDREX >= 2) */ + + +#if (__ARM_FEATURE_LDREX >= 4) +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return (result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return (result); +} +#endif /* (__ARM_FEATURE_LDREX >= 4) */ + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); + return (result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return (result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return (result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return (result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return (result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return (result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return (result); +} + +#endif /* (__ARM_ARCH >= 8) */ + +/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + +#if (__ARM_ARCH_ISA_THUMB >= 2) + /** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ + __STATIC_FORCEINLINE void __enable_fault_irq(void) + { + __ASM volatile ("cpsie f" : : : "memory"); + } + + + /** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ + __STATIC_FORCEINLINE void __disable_fault_irq(void) + { + __ASM volatile ("cpsid f" : : : "memory"); + } +#endif + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + return (__builtin_arm_get_fpscr()); +#else + return (0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + __builtin_arm_set_fpscr(fpscr); +#else + (void)fpscr; +#endif +} + + +/** @} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + #define __SADD8 __sadd8 + #define __QADD8 __qadd8 + #define __SHADD8 __shadd8 + #define __UADD8 __uadd8 + #define __UQADD8 __uqadd8 + #define __UHADD8 __uhadd8 + #define __SSUB8 __ssub8 + #define __QSUB8 __qsub8 + #define __SHSUB8 __shsub8 + #define __USUB8 __usub8 + #define __UQSUB8 __uqsub8 + #define __UHSUB8 __uhsub8 + #define __SADD16 __sadd16 + #define __QADD16 __qadd16 + #define __SHADD16 __shadd16 + #define __UADD16 __uadd16 + #define __UQADD16 __uqadd16 + #define __UHADD16 __uhadd16 + #define __SSUB16 __ssub16 + #define __QSUB16 __qsub16 + #define __SHSUB16 __shsub16 + #define __USUB16 __usub16 + #define __UQSUB16 __uqsub16 + #define __UHSUB16 __uhsub16 + #define __SASX __sasx + #define __QASX __qasx + #define __SHASX __shasx + #define __UASX __uasx + #define __UQASX __uqasx + #define __UHASX __uhasx + #define __SSAX __ssax + #define __QSAX __qsax + #define __SHSAX __shsax + #define __USAX __usax + #define __UQSAX __uqsax + #define __UHSAX __uhsax + #define __USAD8 __usad8 + #define __USADA8 __usada8 + #define __SSAT16 __ssat16 + #define __USAT16 __usat16 + #define __UXTB16 __uxtb16 + #define __UXTAB16 __uxtab16 + #define __SXTB16 __sxtb16 + #define __SXTAB16 __sxtab16 + #define __SMUAD __smuad + #define __SMUADX __smuadx + #define __SMLAD __smlad + #define __SMLADX __smladx + #define __SMLALD __smlald + #define __SMLALDX __smlaldx + #define __SMUSD __smusd + #define __SMUSDX __smusdx + #define __SMLSD __smlsd + #define __SMLSDX __smlsdx + #define __SMLSLD __smlsld + #define __SMLSLDX __smlsldx + #define __SEL __sel + #define __QADD __qadd + #define __QSUB __qsub + + #define __PKHBT(ARG1,ARG2,ARG3) \ + __extension__ \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + #define __PKHTB(ARG1,ARG2,ARG3) \ + __extension__ \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + __STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) + { + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) + { + __ASM volatile("sxtb16 %0, %1, ROR %2" : "=r"(result) : "r"(op1), "i"(rotate)); + } + else + { + result = __SXTB16(__ROR(op1, rotate)); + } + return result; + } + + __STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) + { + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) + { + __ASM volatile("sxtab16 %0, %1, %2, ROR %3" : "=r"(result) : "r"(op1), "r"(op2), "i"(rotate)); + } + else + { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; + } + + __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) + { + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return (result); + } +#endif /* (__ARM_FEATURE_DSP == 1) */ +/** @} end of group CMSIS_SIMD_intrinsics */ + +// Include the profile specific settings: +#if __ARM_ARCH_PROFILE == 'A' + #include "a-profile/cmsis_gcc_a.h" +#elif __ARM_ARCH_PROFILE == 'R' + #include "r-profile/cmsis_gcc_r.h" +#elif __ARM_ARCH_PROFILE == 'M' + #include "m-profile/cmsis_gcc_m.h" +#else + #error "Unknown Arm architecture profile" +#endif + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_version.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_version.h new file mode 100644 index 00000000000..849a8a4a15d --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_version.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2009-2023 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Core Version Definitions + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS-Core(M) Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 6U) /*!< \brief [31:16] CMSIS-Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< \brief [15:0] CMSIS-Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< \brief CMSIS Core(M) version number */ + +/* CMSIS-Core(A) Version definitions */ +#define __CA_CMSIS_VERSION_MAIN ( 6U) /*!< \brief [31:16] CMSIS-Core(A) main version */ +#define __CA_CMSIS_VERSION_SUB ( 1U) /*!< \brief [15:0] CMSIS-Core(A) sub version */ +#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \ + __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */ + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_ca.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_ca.h new file mode 100644 index 00000000000..df5a95d7148 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_ca.h @@ -0,0 +1,3000 @@ +/* + * Copyright (c) 2009-2023 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-A Core Peripheral Access Layer Header File + */ + +#ifndef __CORE_CA_H_GENERIC +#define __CORE_CA_H_GENERIC + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ + +#include "cmsis_version.h" + +/* CMSIS CA definitions */ + +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CA_H_DEPENDANT +#define __CORE_CA_H_DEPENDANT + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + + /* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CA_REV + #define __CA_REV 0x0000U /*!< \brief Contains the core revision for a Cortex-A class device */ + #warning "__CA_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __GIC_PRESENT + #define __GIC_PRESENT 1U + #warning "__GIC_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __TIM_PRESENT + #define __TIM_PRESENT 1U + #warning "__TIM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __L2C_PRESENT + #define __L2C_PRESENT 0U + #warning "__L2C_PRESENT not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< \brief Defines 'read only' permissions */ +#else + #define __I volatile const /*!< \brief Defines 'read only' permissions */ +#endif +#define __O volatile /*!< \brief Defines 'write only' permissions */ +#define __IO volatile /*!< \brief Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*!< \brief Defines 'read only' structure member permissions */ +#define __OM volatile /*!< \brief Defines 'write only' structure member permissions */ +#define __IOM volatile /*!< \brief Defines 'read / write' structure member permissions */ +#define RESERVED(N, T) T RESERVED##N; // placeholder struct members used for "reserved" areas + + /******************************************************************************* + * Register Abstraction + Core Register contain: + - CPSR + - CP15 Registers + - L2C-310 Cache Controller + - Generic Interrupt Controller Distributor + - Generic Interrupt Controller Interface + ******************************************************************************/ + +/* Core Register CPSR */ +typedef union +{ + struct + { + uint32_t M:5; /*!< \brief bit: 0.. 4 Mode field */ + uint32_t T:1; /*!< \brief bit: 5 Thumb execution state bit */ + uint32_t F:1; /*!< \brief bit: 6 FIQ mask bit */ + uint32_t I:1; /*!< \brief bit: 7 IRQ mask bit */ + uint32_t A:1; /*!< \brief bit: 8 Asynchronous abort mask bit */ + uint32_t E:1; /*!< \brief bit: 9 Endianness execution state bit */ + uint32_t IT1:6; /*!< \brief bit: 10..15 If-Then execution state bits 2-7 */ + uint32_t GE:4; /*!< \brief bit: 16..19 Greater than or Equal flags */ + RESERVED(0:4, uint32_t) + uint32_t J:1; /*!< \brief bit: 24 Jazelle bit */ + uint32_t IT0:2; /*!< \brief bit: 25..26 If-Then execution state bits 0-1 */ + uint32_t Q:1; /*!< \brief bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< \brief bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< \brief bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< \brief bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< \brief bit: 31 Negative condition code flag */ + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CPSR_Type; + + + +/* CPSR Register Definitions */ +#define CPSR_N_Pos 31U /*!< \brief CPSR: N Position */ +#define CPSR_N_Msk (1UL << CPSR_N_Pos) /*!< \brief CPSR: N Mask */ + +#define CPSR_Z_Pos 30U /*!< \brief CPSR: Z Position */ +#define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /*!< \brief CPSR: Z Mask */ + +#define CPSR_C_Pos 29U /*!< \brief CPSR: C Position */ +#define CPSR_C_Msk (1UL << CPSR_C_Pos) /*!< \brief CPSR: C Mask */ + +#define CPSR_V_Pos 28U /*!< \brief CPSR: V Position */ +#define CPSR_V_Msk (1UL << CPSR_V_Pos) /*!< \brief CPSR: V Mask */ + +#define CPSR_Q_Pos 27U /*!< \brief CPSR: Q Position */ +#define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /*!< \brief CPSR: Q Mask */ + +#define CPSR_IT0_Pos 25U /*!< \brief CPSR: IT0 Position */ +#define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /*!< \brief CPSR: IT0 Mask */ + +#define CPSR_J_Pos 24U /*!< \brief CPSR: J Position */ +#define CPSR_J_Msk (1UL << CPSR_J_Pos) /*!< \brief CPSR: J Mask */ + +#define CPSR_GE_Pos 16U /*!< \brief CPSR: GE Position */ +#define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /*!< \brief CPSR: GE Mask */ + +#define CPSR_IT1_Pos 10U /*!< \brief CPSR: IT1 Position */ +#define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /*!< \brief CPSR: IT1 Mask */ + +#define CPSR_E_Pos 9U /*!< \brief CPSR: E Position */ +#define CPSR_E_Msk (1UL << CPSR_E_Pos) /*!< \brief CPSR: E Mask */ + +#define CPSR_A_Pos 8U /*!< \brief CPSR: A Position */ +#define CPSR_A_Msk (1UL << CPSR_A_Pos) /*!< \brief CPSR: A Mask */ + +#define CPSR_I_Pos 7U /*!< \brief CPSR: I Position */ +#define CPSR_I_Msk (1UL << CPSR_I_Pos) /*!< \brief CPSR: I Mask */ + +#define CPSR_F_Pos 6U /*!< \brief CPSR: F Position */ +#define CPSR_F_Msk (1UL << CPSR_F_Pos) /*!< \brief CPSR: F Mask */ + +#define CPSR_T_Pos 5U /*!< \brief CPSR: T Position */ +#define CPSR_T_Msk (1UL << CPSR_T_Pos) /*!< \brief CPSR: T Mask */ + +#define CPSR_M_Pos 0U /*!< \brief CPSR: M Position */ +#define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /*!< \brief CPSR: M Mask */ + +#define CPSR_M_USR 0x10U /*!< \brief CPSR: M User mode (PL0) */ +#define CPSR_M_FIQ 0x11U /*!< \brief CPSR: M Fast Interrupt mode (PL1) */ +#define CPSR_M_IRQ 0x12U /*!< \brief CPSR: M Interrupt mode (PL1) */ +#define CPSR_M_SVC 0x13U /*!< \brief CPSR: M Supervisor mode (PL1) */ +#define CPSR_M_MON 0x16U /*!< \brief CPSR: M Monitor mode (PL1) */ +#define CPSR_M_ABT 0x17U /*!< \brief CPSR: M Abort mode (PL1) */ +#define CPSR_M_HYP 0x1AU /*!< \brief CPSR: M Hypervisor mode (PL2) */ +#define CPSR_M_UND 0x1BU /*!< \brief CPSR: M Undefined mode (PL1) */ +#define CPSR_M_SYS 0x1FU /*!< \brief CPSR: M System mode (PL1) */ + +/* CP15 Register SCTLR */ +typedef union +{ + struct + { + uint32_t M:1; /*!< \brief bit: 0 MMU enable */ + uint32_t A:1; /*!< \brief bit: 1 Alignment check enable */ + uint32_t C:1; /*!< \brief bit: 2 Cache enable */ + RESERVED(0:2, uint32_t) + uint32_t CP15BEN:1; /*!< \brief bit: 5 CP15 barrier enable */ + RESERVED(1:1, uint32_t) + uint32_t B:1; /*!< \brief bit: 7 Endianness model */ + RESERVED(2:2, uint32_t) + uint32_t SW:1; /*!< \brief bit: 10 SWP and SWPB enable */ + uint32_t Z:1; /*!< \brief bit: 11 Branch prediction enable */ + uint32_t I:1; /*!< \brief bit: 12 Instruction cache enable */ + uint32_t V:1; /*!< \brief bit: 13 Vectors bit */ + uint32_t RR:1; /*!< \brief bit: 14 Round Robin select */ + RESERVED(3:2, uint32_t) + uint32_t HA:1; /*!< \brief bit: 17 Hardware Access flag enable */ + RESERVED(4:1, uint32_t) + uint32_t WXN:1; /*!< \brief bit: 19 Write permission implies XN */ + uint32_t UWXN:1; /*!< \brief bit: 20 Unprivileged write permission implies PL1 XN */ + uint32_t FI:1; /*!< \brief bit: 21 Fast interrupts configuration enable */ + uint32_t U:1; /*!< \brief bit: 22 Alignment model */ + RESERVED(5:1, uint32_t) + uint32_t VE:1; /*!< \brief bit: 24 Interrupt Vectors Enable */ + uint32_t EE:1; /*!< \brief bit: 25 Exception Endianness */ + RESERVED(6:1, uint32_t) + uint32_t NMFI:1; /*!< \brief bit: 27 Non-maskable FIQ (NMFI) support */ + uint32_t TRE:1; /*!< \brief bit: 28 TEX remap enable. */ + uint32_t AFE:1; /*!< \brief bit: 29 Access flag enable */ + uint32_t TE:1; /*!< \brief bit: 30 Thumb Exception enable */ + RESERVED(7:1, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} SCTLR_Type; + +#define SCTLR_TE_Pos 30U /*!< \brief SCTLR: TE Position */ +#define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /*!< \brief SCTLR: TE Mask */ + +#define SCTLR_AFE_Pos 29U /*!< \brief SCTLR: AFE Position */ +#define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /*!< \brief SCTLR: AFE Mask */ + +#define SCTLR_TRE_Pos 28U /*!< \brief SCTLR: TRE Position */ +#define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /*!< \brief SCTLR: TRE Mask */ + +#define SCTLR_NMFI_Pos 27U /*!< \brief SCTLR: NMFI Position */ +#define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /*!< \brief SCTLR: NMFI Mask */ + +#define SCTLR_EE_Pos 25U /*!< \brief SCTLR: EE Position */ +#define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /*!< \brief SCTLR: EE Mask */ + +#define SCTLR_VE_Pos 24U /*!< \brief SCTLR: VE Position */ +#define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /*!< \brief SCTLR: VE Mask */ + +#define SCTLR_U_Pos 22U /*!< \brief SCTLR: U Position */ +#define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /*!< \brief SCTLR: U Mask */ + +#define SCTLR_FI_Pos 21U /*!< \brief SCTLR: FI Position */ +#define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /*!< \brief SCTLR: FI Mask */ + +#define SCTLR_UWXN_Pos 20U /*!< \brief SCTLR: UWXN Position */ +#define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /*!< \brief SCTLR: UWXN Mask */ + +#define SCTLR_WXN_Pos 19U /*!< \brief SCTLR: WXN Position */ +#define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /*!< \brief SCTLR: WXN Mask */ + +#define SCTLR_HA_Pos 17U /*!< \brief SCTLR: HA Position */ +#define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /*!< \brief SCTLR: HA Mask */ + +#define SCTLR_RR_Pos 14U /*!< \brief SCTLR: RR Position */ +#define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /*!< \brief SCTLR: RR Mask */ + +#define SCTLR_V_Pos 13U /*!< \brief SCTLR: V Position */ +#define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /*!< \brief SCTLR: V Mask */ + +#define SCTLR_I_Pos 12U /*!< \brief SCTLR: I Position */ +#define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /*!< \brief SCTLR: I Mask */ + +#define SCTLR_Z_Pos 11U /*!< \brief SCTLR: Z Position */ +#define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /*!< \brief SCTLR: Z Mask */ + +#define SCTLR_SW_Pos 10U /*!< \brief SCTLR: SW Position */ +#define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /*!< \brief SCTLR: SW Mask */ + +#define SCTLR_B_Pos 7U /*!< \brief SCTLR: B Position */ +#define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /*!< \brief SCTLR: B Mask */ + +#define SCTLR_CP15BEN_Pos 5U /*!< \brief SCTLR: CP15BEN Position */ +#define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /*!< \brief SCTLR: CP15BEN Mask */ + +#define SCTLR_C_Pos 2U /*!< \brief SCTLR: C Position */ +#define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /*!< \brief SCTLR: C Mask */ + +#define SCTLR_A_Pos 1U /*!< \brief SCTLR: A Position */ +#define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /*!< \brief SCTLR: A Mask */ + +#define SCTLR_M_Pos 0U /*!< \brief SCTLR: M Position */ +#define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< \brief SCTLR: M Mask */ + +/* CP15 Register ACTLR */ +typedef union +{ +#if __CORTEX_A == 5 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A5 */ + struct + { + uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */ + RESERVED(0:5, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */ + RESERVED(1:2, uint32_t) + uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */ + uint32_t DWBST:1; /*!< \brief bit: 11 AXI data write bursts to Normal memory */ + uint32_t RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */ + uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */ + uint32_t BP:2; /*!< \brief bit:16..15 Branch prediction policy */ + uint32_t RSDIS:1; /*!< \brief bit: 17 Disable return stack operation */ + uint32_t BTDIS:1; /*!< \brief bit: 18 Disable indirect Branch Target Address Cache (BTAC) */ + RESERVED(3:9, uint32_t) + uint32_t DBDI:1; /*!< \brief bit: 28 Disable branch dual issue */ + RESERVED(7:3, uint32_t) + } b; +#endif +#if __CORTEX_A == 7 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A7 */ + struct + { + RESERVED(0:6, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + RESERVED(1:3, uint32_t) + uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */ + uint32_t L2RADIS:1; /*!< \brief bit: 11 L2 Data Cache read-allocate mode disable */ + uint32_t L1RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */ + uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */ + uint32_t DDVM:1; /*!< \brief bit: 15 Disable Distributed Virtual Memory (DVM) transactions */ + RESERVED(3:12, uint32_t) + uint32_t DDI:1; /*!< \brief bit: 28 Disable dual issue */ + RESERVED(7:3, uint32_t) + } b; +#endif +#if __CORTEX_A == 9 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A9 */ + struct + { + uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */ + RESERVED(0:1, uint32_t) + uint32_t L1PE:1; /*!< \brief bit: 2 Dside prefetch */ + uint32_t WFLZM:1; /*!< \brief bit: 3 Cache and TLB maintenance broadcast */ + RESERVED(1:2, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */ + uint32_t AOW:1; /*!< \brief bit: 8 Enable allocation in one cache way only */ + uint32_t PARITY:1; /*!< \brief bit: 9 Support for parity checking, if implemented */ + RESERVED(7:22, uint32_t) + } b; +#endif + uint32_t w; /*!< \brief Type used for word access */ +} ACTLR_Type; + +#define ACTLR_DDI_Pos 28U /*!< \brief ACTLR: DDI Position */ +#define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos) /*!< \brief ACTLR: DDI Mask */ + +#define ACTLR_DBDI_Pos 28U /*!< \brief ACTLR: DBDI Position */ +#define ACTLR_DBDI_Msk (1UL << ACTLR_DBDI_Pos) /*!< \brief ACTLR: DBDI Mask */ + +#define ACTLR_BTDIS_Pos 18U /*!< \brief ACTLR: BTDIS Position */ +#define ACTLR_BTDIS_Msk (1UL << ACTLR_BTDIS_Pos) /*!< \brief ACTLR: BTDIS Mask */ + +#define ACTLR_RSDIS_Pos 17U /*!< \brief ACTLR: RSDIS Position */ +#define ACTLR_RSDIS_Msk (1UL << ACTLR_RSDIS_Pos) /*!< \brief ACTLR: RSDIS Mask */ + +#define ACTLR_BP_Pos 15U /*!< \brief ACTLR: BP Position */ +#define ACTLR_BP_Msk (3UL << ACTLR_BP_Pos) /*!< \brief ACTLR: BP Mask */ + +#define ACTLR_DDVM_Pos 15U /*!< \brief ACTLR: DDVM Position */ +#define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos) /*!< \brief ACTLR: DDVM Mask */ + +#define ACTLR_L1PCTL_Pos 13U /*!< \brief ACTLR: L1PCTL Position */ +#define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos) /*!< \brief ACTLR: L1PCTL Mask */ + +#define ACTLR_RADIS_Pos 12U /*!< \brief ACTLR: RADIS Position */ +#define ACTLR_RADIS_Msk (1UL << ACTLR_RADIS_Pos) /*!< \brief ACTLR: RADIS Mask */ + +#define ACTLR_L1RADIS_Pos 12U /*!< \brief ACTLR: L1RADIS Position */ +#define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos) /*!< \brief ACTLR: L1RADIS Mask */ + +#define ACTLR_DWBST_Pos 11U /*!< \brief ACTLR: DWBST Position */ +#define ACTLR_DWBST_Msk (1UL << ACTLR_DWBST_Pos) /*!< \brief ACTLR: DWBST Mask */ + +#define ACTLR_L2RADIS_Pos 11U /*!< \brief ACTLR: L2RADIS Position */ +#define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos) /*!< \brief ACTLR: L2RADIS Mask */ + +#define ACTLR_DODMBS_Pos 10U /*!< \brief ACTLR: DODMBS Position */ +#define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos) /*!< \brief ACTLR: DODMBS Mask */ + +#define ACTLR_PARITY_Pos 9U /*!< \brief ACTLR: PARITY Position */ +#define ACTLR_PARITY_Msk (1UL << ACTLR_PARITY_Pos) /*!< \brief ACTLR: PARITY Mask */ + +#define ACTLR_AOW_Pos 8U /*!< \brief ACTLR: AOW Position */ +#define ACTLR_AOW_Msk (1UL << ACTLR_AOW_Pos) /*!< \brief ACTLR: AOW Mask */ + +#define ACTLR_EXCL_Pos 7U /*!< \brief ACTLR: EXCL Position */ +#define ACTLR_EXCL_Msk (1UL << ACTLR_EXCL_Pos) /*!< \brief ACTLR: EXCL Mask */ + +#define ACTLR_SMP_Pos 6U /*!< \brief ACTLR: SMP Position */ +#define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos) /*!< \brief ACTLR: SMP Mask */ + +#define ACTLR_WFLZM_Pos 3U /*!< \brief ACTLR: WFLZM Position */ +#define ACTLR_WFLZM_Msk (1UL << ACTLR_WFLZM_Pos) /*!< \brief ACTLR: WFLZM Mask */ + +#define ACTLR_L1PE_Pos 2U /*!< \brief ACTLR: L1PE Position */ +#define ACTLR_L1PE_Msk (1UL << ACTLR_L1PE_Pos) /*!< \brief ACTLR: L1PE Mask */ + +#define ACTLR_FW_Pos 0U /*!< \brief ACTLR: FW Position */ +#define ACTLR_FW_Msk (1UL << ACTLR_FW_Pos) /*!< \brief ACTLR: FW Mask */ + +/* CP15 Register CPACR */ +typedef union +{ + struct + { + uint32_t CP0:2; /*!< \brief bit: 0..1 Access rights for coprocessor 0 */ + uint32_t CP1:2; /*!< \brief bit: 2..3 Access rights for coprocessor 1 */ + uint32_t CP2:2; /*!< \brief bit: 4..5 Access rights for coprocessor 2 */ + uint32_t CP3:2; /*!< \brief bit: 6..7 Access rights for coprocessor 3 */ + uint32_t CP4:2; /*!< \brief bit: 8..9 Access rights for coprocessor 4 */ + uint32_t CP5:2; /*!< \brief bit:10..11 Access rights for coprocessor 5 */ + uint32_t CP6:2; /*!< \brief bit:12..13 Access rights for coprocessor 6 */ + uint32_t CP7:2; /*!< \brief bit:14..15 Access rights for coprocessor 7 */ + uint32_t CP8:2; /*!< \brief bit:16..17 Access rights for coprocessor 8 */ + uint32_t CP9:2; /*!< \brief bit:18..19 Access rights for coprocessor 9 */ + uint32_t CP10:2; /*!< \brief bit:20..21 Access rights for coprocessor 10 */ + uint32_t CP11:2; /*!< \brief bit:22..23 Access rights for coprocessor 11 */ + uint32_t CP12:2; /*!< \brief bit:24..25 Access rights for coprocessor 11 */ + uint32_t CP13:2; /*!< \brief bit:26..27 Access rights for coprocessor 11 */ + uint32_t TRCDIS:1; /*!< \brief bit: 28 Disable CP14 access to trace registers */ + RESERVED(0:1, uint32_t) + uint32_t D32DIS:1; /*!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file */ + uint32_t ASEDIS:1; /*!< \brief bit: 31 Disable Advanced SIMD Functionality */ + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CPACR_Type; + +#define CPACR_ASEDIS_Pos 31U /*!< \brief CPACR: ASEDIS Position */ +#define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /*!< \brief CPACR: ASEDIS Mask */ + +#define CPACR_D32DIS_Pos 30U /*!< \brief CPACR: D32DIS Position */ +#define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */ + +#define CPACR_TRCDIS_Pos 28U /*!< \brief CPACR: D32DIS Position */ +#define CPACR_TRCDIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */ + +#define CPACR_CP_Pos_(n) (n*2U) /*!< \brief CPACR: CPn Position */ +#define CPACR_CP_Msk_(n) (3UL << CPACR_CP_Pos_(n)) /*!< \brief CPACR: CPn Mask */ + +#define CPACR_CP_NA 0U /*!< \brief CPACR CPn field: Access denied. */ +#define CPACR_CP_PL1 1U /*!< \brief CPACR CPn field: Accessible from PL1 only. */ +#define CPACR_CP_FA 3U /*!< \brief CPACR CPn field: Full access. */ + +/* CP15 Register DFSR */ +typedef union +{ + struct + { + uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */ + uint32_t Domain:4; /*!< \brief bit: 4.. 7 Fault on which domain */ + RESERVED(0:1, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */ + uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */ + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */ + RESERVED(1:18, uint32_t) + } s; /*!< \brief Structure used for bit access in short format */ + struct + { + uint32_t STATUS:5; /*!< \brief bit: 0.. 5 Fault Status bits */ + RESERVED(0:3, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + RESERVED(1:1, uint32_t) + uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */ + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */ + RESERVED(2:18, uint32_t) + } l; /*!< \brief Structure used for bit access in long format */ + uint32_t w; /*!< \brief Type used for word access */ +} DFSR_Type; + +#define DFSR_CM_Pos 13U /*!< \brief DFSR: CM Position */ +#define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /*!< \brief DFSR: CM Mask */ + +#define DFSR_Ext_Pos 12U /*!< \brief DFSR: Ext Position */ +#define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /*!< \brief DFSR: Ext Mask */ + +#define DFSR_WnR_Pos 11U /*!< \brief DFSR: WnR Position */ +#define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /*!< \brief DFSR: WnR Mask */ + +#define DFSR_FS1_Pos 10U /*!< \brief DFSR: FS1 Position */ +#define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /*!< \brief DFSR: FS1 Mask */ + +#define DFSR_LPAE_Pos 9U /*!< \brief DFSR: LPAE Position */ +#define DFSR_LPAE_Msk (1UL << DFSR_LPAE_Pos) /*!< \brief DFSR: LPAE Mask */ + +#define DFSR_Domain_Pos 4U /*!< \brief DFSR: Domain Position */ +#define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /*!< \brief DFSR: Domain Mask */ + +#define DFSR_FS0_Pos 0U /*!< \brief DFSR: FS0 Position */ +#define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /*!< \brief DFSR: FS0 Mask */ + +#define DFSR_STATUS_Pos 0U /*!< \brief DFSR: STATUS Position */ +#define DFSR_STATUS_Msk (0x3FUL << DFSR_STATUS_Pos) /*!< \brief DFSR: STATUS Mask */ + +/* CP15 Register IFSR */ +typedef union +{ + struct + { + uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */ + RESERVED(0:5, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */ + RESERVED(1:1, uint32_t) + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + RESERVED(2:19, uint32_t) + } s; /*!< \brief Structure used for bit access in short format */ + struct + { + uint32_t STATUS:6; /*!< \brief bit: 0.. 5 Fault Status bits */ + RESERVED(0:3, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + RESERVED(1:2, uint32_t) + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + RESERVED(2:19, uint32_t) + } l; /*!< \brief Structure used for bit access in long format */ + uint32_t w; /*!< \brief Type used for word access */ +} IFSR_Type; + +#define IFSR_ExT_Pos 12U /*!< \brief IFSR: ExT Position */ +#define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /*!< \brief IFSR: ExT Mask */ + +#define IFSR_FS1_Pos 10U /*!< \brief IFSR: FS1 Position */ +#define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /*!< \brief IFSR: FS1 Mask */ + +#define IFSR_LPAE_Pos 9U /*!< \brief IFSR: LPAE Position */ +#define IFSR_LPAE_Msk (0x1UL << IFSR_LPAE_Pos) /*!< \brief IFSR: LPAE Mask */ + +#define IFSR_FS0_Pos 0U /*!< \brief IFSR: FS0 Position */ +#define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /*!< \brief IFSR: FS0 Mask */ + +#define IFSR_STATUS_Pos 0U /*!< \brief IFSR: STATUS Position */ +#define IFSR_STATUS_Msk (0x3FUL << IFSR_STATUS_Pos) /*!< \brief IFSR: STATUS Mask */ + +/* CP15 Register ISR */ +typedef union +{ + struct + { + RESERVED(0:6, uint32_t) + uint32_t F:1; /*!< \brief bit: 6 FIQ pending bit */ + uint32_t I:1; /*!< \brief bit: 7 IRQ pending bit */ + uint32_t A:1; /*!< \brief bit: 8 External abort pending bit */ + RESERVED(1:23, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} ISR_Type; + +#define ISR_A_Pos 13U /*!< \brief ISR: A Position */ +#define ISR_A_Msk (1UL << ISR_A_Pos) /*!< \brief ISR: A Mask */ + +#define ISR_I_Pos 12U /*!< \brief ISR: I Position */ +#define ISR_I_Msk (1UL << ISR_I_Pos) /*!< \brief ISR: I Mask */ + +#define ISR_F_Pos 11U /*!< \brief ISR: F Position */ +#define ISR_F_Msk (1UL << ISR_F_Pos) /*!< \brief ISR: F Mask */ + +/* DACR Register */ +#define DACR_D_Pos_(n) (2U*n) /*!< \brief DACR: Dn Position */ +#define DACR_D_Msk_(n) (3UL << DACR_D_Pos_(n)) /*!< \brief DACR: Dn Mask */ +#define DACR_Dn_NOACCESS 0U /*!< \brief DACR Dn field: No access */ +#define DACR_Dn_CLIENT 1U /*!< \brief DACR Dn field: Client */ +#define DACR_Dn_MANAGER 3U /*!< \brief DACR Dn field: Manager */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param [in] field Name of the register bit field. + \param [in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param [in] field Name of the register bit field. + \param [in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + + +/** + \brief Union type to access the L2C_310 Cache Controller. +*/ +#if (defined(__L2C_PRESENT) && (__L2C_PRESENT == 1U)) || \ + defined(DOXYGEN) +typedef struct +{ + __IM uint32_t CACHE_ID; /*!< \brief Offset: 0x0000 (R/ ) Cache ID Register */ + __IM uint32_t CACHE_TYPE; /*!< \brief Offset: 0x0004 (R/ ) Cache Type Register */ + RESERVED(0[0x3e], uint32_t) + __IOM uint32_t CONTROL; /*!< \brief Offset: 0x0100 (R/W) Control Register */ + __IOM uint32_t AUX_CNT; /*!< \brief Offset: 0x0104 (R/W) Auxiliary Control */ + RESERVED(1[0x3e], uint32_t) + __IOM uint32_t EVENT_CONTROL; /*!< \brief Offset: 0x0200 (R/W) Event Counter Control */ + __IOM uint32_t EVENT_COUNTER1_CONF; /*!< \brief Offset: 0x0204 (R/W) Event Counter 1 Configuration */ + __IOM uint32_t EVENT_COUNTER0_CONF; /*!< \brief Offset: 0x0208 (R/W) Event Counter 1 Configuration */ + RESERVED(2[0x2], uint32_t) + __IOM uint32_t INTERRUPT_MASK; /*!< \brief Offset: 0x0214 (R/W) Interrupt Mask */ + __IM uint32_t MASKED_INT_STATUS; /*!< \brief Offset: 0x0218 (R/ ) Masked Interrupt Status */ + __IM uint32_t RAW_INT_STATUS; /*!< \brief Offset: 0x021c (R/ ) Raw Interrupt Status */ + __OM uint32_t INTERRUPT_CLEAR; /*!< \brief Offset: 0x0220 ( /W) Interrupt Clear */ + RESERVED(3[0x143], uint32_t) + __IOM uint32_t CACHE_SYNC; /*!< \brief Offset: 0x0730 (R/W) Cache Sync */ + RESERVED(4[0xf], uint32_t) + __IOM uint32_t INV_LINE_PA; /*!< \brief Offset: 0x0770 (R/W) Invalidate Line By PA */ + RESERVED(6[2], uint32_t) + __IOM uint32_t INV_WAY; /*!< \brief Offset: 0x077c (R/W) Invalidate by Way */ + RESERVED(5[0xc], uint32_t) + __IOM uint32_t CLEAN_LINE_PA; /*!< \brief Offset: 0x07b0 (R/W) Clean Line by PA */ + RESERVED(7[1], uint32_t) + __IOM uint32_t CLEAN_LINE_INDEX_WAY; /*!< \brief Offset: 0x07b8 (R/W) Clean Line by Index/Way */ + __IOM uint32_t CLEAN_WAY; /*!< \brief Offset: 0x07bc (R/W) Clean by Way */ + RESERVED(8[0xc], uint32_t) + __IOM uint32_t CLEAN_INV_LINE_PA; /*!< \brief Offset: 0x07f0 (R/W) Clean and Invalidate Line by PA */ + RESERVED(9[1], uint32_t) + __IOM uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< \brief Offset: 0x07f8 (R/W) Clean and Invalidate Line by Index/Way */ + __IOM uint32_t CLEAN_INV_WAY; /*!< \brief Offset: 0x07fc (R/W) Clean and Invalidate by Way */ + RESERVED(10[0x40], uint32_t) + __IOM uint32_t DATA_LOCK_0_WAY; /*!< \brief Offset: 0x0900 (R/W) Data Lockdown 0 by Way */ + __IOM uint32_t INST_LOCK_0_WAY; /*!< \brief Offset: 0x0904 (R/W) Instruction Lockdown 0 by Way */ + __IOM uint32_t DATA_LOCK_1_WAY; /*!< \brief Offset: 0x0908 (R/W) Data Lockdown 1 by Way */ + __IOM uint32_t INST_LOCK_1_WAY; /*!< \brief Offset: 0x090c (R/W) Instruction Lockdown 1 by Way */ + __IOM uint32_t DATA_LOCK_2_WAY; /*!< \brief Offset: 0x0910 (R/W) Data Lockdown 2 by Way */ + __IOM uint32_t INST_LOCK_2_WAY; /*!< \brief Offset: 0x0914 (R/W) Instruction Lockdown 2 by Way */ + __IOM uint32_t DATA_LOCK_3_WAY; /*!< \brief Offset: 0x0918 (R/W) Data Lockdown 3 by Way */ + __IOM uint32_t INST_LOCK_3_WAY; /*!< \brief Offset: 0x091c (R/W) Instruction Lockdown 3 by Way */ + __IOM uint32_t DATA_LOCK_4_WAY; /*!< \brief Offset: 0x0920 (R/W) Data Lockdown 4 by Way */ + __IOM uint32_t INST_LOCK_4_WAY; /*!< \brief Offset: 0x0924 (R/W) Instruction Lockdown 4 by Way */ + __IOM uint32_t DATA_LOCK_5_WAY; /*!< \brief Offset: 0x0928 (R/W) Data Lockdown 5 by Way */ + __IOM uint32_t INST_LOCK_5_WAY; /*!< \brief Offset: 0x092c (R/W) Instruction Lockdown 5 by Way */ + __IOM uint32_t DATA_LOCK_6_WAY; /*!< \brief Offset: 0x0930 (R/W) Data Lockdown 5 by Way */ + __IOM uint32_t INST_LOCK_6_WAY; /*!< \brief Offset: 0x0934 (R/W) Instruction Lockdown 5 by Way */ + __IOM uint32_t DATA_LOCK_7_WAY; /*!< \brief Offset: 0x0938 (R/W) Data Lockdown 6 by Way */ + __IOM uint32_t INST_LOCK_7_WAY; /*!< \brief Offset: 0x093c (R/W) Instruction Lockdown 6 by Way */ + RESERVED(11[0x4], uint32_t) + __IOM uint32_t LOCK_LINE_EN; /*!< \brief Offset: 0x0950 (R/W) Lockdown by Line Enable */ + __IOM uint32_t UNLOCK_ALL_BY_WAY; /*!< \brief Offset: 0x0954 (R/W) Unlock All Lines by Way */ + RESERVED(12[0xaa], uint32_t) + __IOM uint32_t ADDRESS_FILTER_START; /*!< \brief Offset: 0x0c00 (R/W) Address Filtering Start */ + __IOM uint32_t ADDRESS_FILTER_END; /*!< \brief Offset: 0x0c04 (R/W) Address Filtering End */ + RESERVED(13[0xce], uint32_t) + __IOM uint32_t DEBUG_CONTROL; /*!< \brief Offset: 0x0f40 (R/W) Debug Control Register */ +} L2C_310_TypeDef; + +#define L2C_310 ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 register set access pointer */ +#endif + +#if (defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U)) || \ + defined(DOXYGEN) + +/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD) +*/ +typedef struct +{ + __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) Distributor Control Register */ + __IM uint32_t TYPER; /*!< \brief Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IM uint32_t IIDR; /*!< \brief Offset: 0x008 (R/ ) Distributor Implementer Identification Register */ + RESERVED(0, uint32_t) + __IOM uint32_t STATUSR; /*!< \brief Offset: 0x010 (R/W) Error Reporting Status Register, optional */ + RESERVED(1[11], uint32_t) + __OM uint32_t SETSPI_NSR; /*!< \brief Offset: 0x040 ( /W) Set SPI Register */ + RESERVED(2, uint32_t) + __OM uint32_t CLRSPI_NSR; /*!< \brief Offset: 0x048 ( /W) Clear SPI Register */ + RESERVED(3, uint32_t) + __OM uint32_t SETSPI_SR; /*!< \brief Offset: 0x050 ( /W) Set SPI, Secure Register */ + RESERVED(4, uint32_t) + __OM uint32_t CLRSPI_SR; /*!< \brief Offset: 0x058 ( /W) Clear SPI, Secure Register */ + RESERVED(5[9], uint32_t) + __IOM uint32_t IGROUPR[32]; /*!< \brief Offset: 0x080 (R/W) Interrupt Group Registers */ + __IOM uint32_t ISENABLER[32]; /*!< \brief Offset: 0x100 (R/W) Interrupt Set-Enable Registers */ + __IOM uint32_t ICENABLER[32]; /*!< \brief Offset: 0x180 (R/W) Interrupt Clear-Enable Registers */ + __IOM uint32_t ISPENDR[32]; /*!< \brief Offset: 0x200 (R/W) Interrupt Set-Pending Registers */ + __IOM uint32_t ICPENDR[32]; /*!< \brief Offset: 0x280 (R/W) Interrupt Clear-Pending Registers */ + __IOM uint32_t ISACTIVER[32]; /*!< \brief Offset: 0x300 (R/W) Interrupt Set-Active Registers */ + __IOM uint32_t ICACTIVER[32]; /*!< \brief Offset: 0x380 (R/W) Interrupt Clear-Active Registers */ + __IOM uint32_t IPRIORITYR[255]; /*!< \brief Offset: 0x400 (R/W) Interrupt Priority Registers */ + RESERVED(6, uint32_t) + __IOM uint32_t ITARGETSR[255]; /*!< \brief Offset: 0x800 (R/W) Interrupt Targets Registers */ + RESERVED(7, uint32_t) + __IOM uint32_t ICFGR[64]; /*!< \brief Offset: 0xC00 (R/W) Interrupt Configuration Registers */ + __IOM uint32_t IGRPMODR[32]; /*!< \brief Offset: 0xD00 (R/W) Interrupt Group Modifier Registers */ + RESERVED(8[32], uint32_t) + __IOM uint32_t NSACR[64]; /*!< \brief Offset: 0xE00 (R/W) Non-secure Access Control Registers */ + __OM uint32_t SGIR; /*!< \brief Offset: 0xF00 ( /W) Software Generated Interrupt Register */ + RESERVED(9[3], uint32_t) + __IOM uint32_t CPENDSGIR[4]; /*!< \brief Offset: 0xF10 (R/W) SGI Clear-Pending Registers */ + __IOM uint32_t SPENDSGIR[4]; /*!< \brief Offset: 0xF20 (R/W) SGI Set-Pending Registers */ + RESERVED(10[5236], uint32_t) + __IOM uint64_t IROUTER[988]; /*!< \brief Offset: 0x6100(R/W) Interrupt Routing Registers */ +} GICDistributor_Type; + +#define GICDistributor ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE ) /*!< \brief GIC Distributor register set access pointer */ + +/* GICDistributor CTLR Register */ +#define GICDistributor_CTLR_EnableGrp0_Pos 0U /*!< GICDistributor CTLR: EnableGrp0 Position */ +#define GICDistributor_CTLR_EnableGrp0_Msk (0x1U /*<< GICDistributor_CTLR_EnableGrp0_Pos*/) /*!< GICDistributor CTLR: EnableGrp0 Mask */ +#define GICDistributor_CTLR_EnableGrp0(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_CTLR_EnableGrp0_Pos*/)) & GICDistributor_CTLR_EnableGrp0_Msk) + +#define GICDistributor_CTLR_EnableGrp1_Pos 1U /*!< GICDistributor CTLR: EnableGrp1 Position */ +#define GICDistributor_CTLR_EnableGrp1_Msk (0x1U << GICDistributor_CTLR_EnableGrp1_Pos) /*!< GICDistributor CTLR: EnableGrp1 Mask */ +#define GICDistributor_CTLR_EnableGrp1(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_EnableGrp1_Pos)) & GICDistributor_CTLR_EnableGrp1_Msk) + +#define GICDistributor_CTLR_ARE_Pos 4U /*!< GICDistributor CTLR: ARE Position */ +#define GICDistributor_CTLR_ARE_Msk (0x1U << GICDistributor_CTLR_ARE_Pos) /*!< GICDistributor CTLR: ARE Mask */ +#define GICDistributor_CTLR_ARE(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_ARE_Pos)) & GICDistributor_CTLR_ARE_Msk) + +#define GICDistributor_CTLR_DC_Pos 6U /*!< GICDistributor CTLR: DC Position */ +#define GICDistributor_CTLR_DC_Msk (0x1U << GICDistributor_CTLR_DC_Pos) /*!< GICDistributor CTLR: DC Mask */ +#define GICDistributor_CTLR_DC(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_DC_Pos)) & GICDistributor_CTLR_DC_Msk) + +#define GICDistributor_CTLR_EINWF_Pos 7U /*!< GICDistributor CTLR: EINWF Position */ +#define GICDistributor_CTLR_EINWF_Msk (0x1U << GICDistributor_CTLR_EINWF_Pos) /*!< GICDistributor CTLR: EINWF Mask */ +#define GICDistributor_CTLR_EINWF(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_EINWF_Pos)) & GICDistributor_CTLR_EINWF_Msk) + +#define GICDistributor_CTLR_RWP_Pos 31U /*!< GICDistributor CTLR: RWP Position */ +#define GICDistributor_CTLR_RWP_Msk (0x1U << GICDistributor_CTLR_RWP_Pos) /*!< GICDistributor CTLR: RWP Mask */ +#define GICDistributor_CTLR_RWP(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_RWP_Pos)) & GICDistributor_CTLR_RWP_Msk) + +/* GICDistributor TYPER Register */ +#define GICDistributor_TYPER_ITLinesNumber_Pos 0U /*!< GICDistributor TYPER: ITLinesNumber Position */ +#define GICDistributor_TYPER_ITLinesNumber_Msk (0x1FU /*<< GICDistributor_TYPER_ITLinesNumber_Pos*/) /*!< GICDistributor TYPER: ITLinesNumber Mask */ +#define GICDistributor_TYPER_ITLinesNumber(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_TYPER_ITLinesNumber_Pos*/)) & GICDistributor_CTLR_ITLinesNumber_Msk) + +#define GICDistributor_TYPER_CPUNumber_Pos 5U /*!< GICDistributor TYPER: CPUNumber Position */ +#define GICDistributor_TYPER_CPUNumber_Msk (0x7U << GICDistributor_TYPER_CPUNumber_Pos) /*!< GICDistributor TYPER: CPUNumber Mask */ +#define GICDistributor_TYPER_CPUNumber(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_TYPER_CPUNumber_Pos)) & GICDistributor_TYPER_CPUNumber_Msk) + +#define GICDistributor_TYPER_SecurityExtn_Pos 10U /*!< GICDistributor TYPER: SecurityExtn Position */ +#define GICDistributor_TYPER_SecurityExtn_Msk (0x1U << GICDistributor_TYPER_SecurityExtn_Pos) /*!< GICDistributor TYPER: SecurityExtn Mask */ +#define GICDistributor_TYPER_SecurityExtn(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_TYPER_SecurityExtn_Pos)) & GICDistributor_TYPER_SecurityExtn_Msk) + +#define GICDistributor_TYPER_LSPI_Pos 11U /*!< GICDistributor TYPER: LSPI Position */ +#define GICDistributor_TYPER_LSPI_Msk (0x1FU << GICDistributor_TYPER_LSPI_Pos) /*!< GICDistributor TYPER: LSPI Mask */ +#define GICDistributor_TYPER_LSPI(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_TYPER_LSPI_Pos)) & GICDistributor_TYPER_LSPI_Msk) + +/* GICDistributor IIDR Register */ +#define GICDistributor_IIDR_Implementer_Pos 0U /*!< GICDistributor IIDR: Implementer Position */ +#define GICDistributor_IIDR_Implementer_Msk (0xFFFU /*<< GICDistributor_IIDR_Implementer_Pos*/) /*!< GICDistributor IIDR: Implementer Mask */ +#define GICDistributor_IIDR_Implementer(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_IIDR_Implementer_Pos*/)) & GICDistributor_IIDR_Implementer_Msk) + +#define GICDistributor_IIDR_Revision_Pos 12U /*!< GICDistributor IIDR: Revision Position */ +#define GICDistributor_IIDR_Revision_Msk (0xFU << GICDistributor_IIDR_Revision_Pos) /*!< GICDistributor IIDR: Revision Mask */ +#define GICDistributor_IIDR_Revision(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_IIDR_Revision_Pos)) & GICDistributor_IIDR_Revision_Msk) + +#define GICDistributor_IIDR_Variant_Pos 16U /*!< GICDistributor IIDR: Variant Position */ +#define GICDistributor_IIDR_Variant_Msk (0xFU << GICDistributor_IIDR_Variant_Pos) /*!< GICDistributor IIDR: Variant Mask */ +#define GICDistributor_IIDR_Variant(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_IIDR_Variant_Pos)) & GICDistributor_IIDR_Variant_Msk) + +#define GICDistributor_IIDR_ProductID_Pos 24U /*!< GICDistributor IIDR: ProductID Position */ +#define GICDistributor_IIDR_ProductID_Msk (0xFFU << GICDistributor_IIDR_ProductID_Pos) /*!< GICDistributor IIDR: ProductID Mask */ +#define GICDistributor_IIDR_ProductID(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_IIDR_ProductID_Pos)) & GICDistributor_IIDR_ProductID_Msk) + +/* GICDistributor STATUSR Register */ +#define GICDistributor_STATUSR_RRD_Pos 0U /*!< GICDistributor STATUSR: RRD Position */ +#define GICDistributor_STATUSR_RRD_Msk (0x1U /*<< GICDistributor_STATUSR_RRD_Pos*/) /*!< GICDistributor STATUSR: RRD Mask */ +#define GICDistributor_STATUSR_RRD(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_STATUSR_RRD_Pos*/)) & GICDistributor_STATUSR_RRD_Msk) + +#define GICDistributor_STATUSR_WRD_Pos 1U /*!< GICDistributor STATUSR: WRD Position */ +#define GICDistributor_STATUSR_WRD_Msk (0x1U << GICDistributor_STATUSR_WRD_Pos) /*!< GICDistributor STATUSR: WRD Mask */ +#define GICDistributor_STATUSR_WRD(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_STATUSR_WRD_Pos)) & GICDistributor_STATUSR_WRD_Msk) + +#define GICDistributor_STATUSR_RWOD_Pos 2U /*!< GICDistributor STATUSR: RWOD Position */ +#define GICDistributor_STATUSR_RWOD_Msk (0x1U << GICDistributor_STATUSR_RWOD_Pos) /*!< GICDistributor STATUSR: RWOD Mask */ +#define GICDistributor_STATUSR_RWOD(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_STATUSR_RWOD_Pos)) & GICDistributor_STATUSR_RWOD_Msk) + +#define GICDistributor_STATUSR_WROD_Pos 3U /*!< GICDistributor STATUSR: WROD Position */ +#define GICDistributor_STATUSR_WROD_Msk (0x1U << GICDistributor_STATUSR_WROD_Pos) /*!< GICDistributor STATUSR: WROD Mask */ +#define GICDistributor_STATUSR_WROD(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_STATUSR_WROD_Pos)) & GICDistributor_STATUSR_WROD_Msk) + +/* GICDistributor SETSPI_NSR Register */ +#define GICDistributor_SETSPI_NSR_INTID_Pos 0U /*!< GICDistributor SETSPI_NSR: INTID Position */ +#define GICDistributor_SETSPI_NSR_INTID_Msk (0x3FFU /*<< GICDistributor_SETSPI_NSR_INTID_Pos*/) /*!< GICDistributor SETSPI_NSR: INTID Mask */ +#define GICDistributor_SETSPI_NSR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_SETSPI_NSR_INTID_Pos*/)) & GICDistributor_SETSPI_NSR_INTID_Msk) + +/* GICDistributor CLRSPI_NSR Register */ +#define GICDistributor_CLRSPI_NSR_INTID_Pos 0U /*!< GICDistributor CLRSPI_NSR: INTID Position */ +#define GICDistributor_CLRSPI_NSR_INTID_Msk (0x3FFU /*<< GICDistributor_CLRSPI_NSR_INTID_Pos*/) /*!< GICDistributor CLRSPI_NSR: INTID Mask */ +#define GICDistributor_CLRSPI_NSR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_CLRSPI_NSR_INTID_Pos*/)) & GICDistributor_CLRSPI_NSR_INTID_Msk) + +/* GICDistributor SETSPI_SR Register */ +#define GICDistributor_SETSPI_SR_INTID_Pos 0U /*!< GICDistributor SETSPI_SR: INTID Position */ +#define GICDistributor_SETSPI_SR_INTID_Msk (0x3FFU /*<< GICDistributor_SETSPI_SR_INTID_Pos*/) /*!< GICDistributor SETSPI_SR: INTID Mask */ +#define GICDistributor_SETSPI_SR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_SETSPI_SR_INTID_Pos*/)) & GICDistributor_SETSPI_SR_INTID_Msk) + +/* GICDistributor CLRSPI_SR Register */ +#define GICDistributor_CLRSPI_SR_INTID_Pos 0U /*!< GICDistributor CLRSPI_SR: INTID Position */ +#define GICDistributor_CLRSPI_SR_INTID_Msk (0x3FFU /*<< GICDistributor_CLRSPI_SR_INTID_Pos*/) /*!< GICDistributor CLRSPI_SR: INTID Mask */ +#define GICDistributor_CLRSPI_SR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_CLRSPI_SR_INTID_Pos*/)) & GICDistributor_CLRSPI_SR_INTID_Msk) + +/* GICDistributor ITARGETSR Register */ +#define GICDistributor_ITARGETSR_CPU0_Pos 0U /*!< GICDistributor ITARGETSR: CPU0 Position */ +#define GICDistributor_ITARGETSR_CPU0_Msk (0x1U /*<< GICDistributor_ITARGETSR_CPU0_Pos*/) /*!< GICDistributor ITARGETSR: CPU0 Mask */ +#define GICDistributor_ITARGETSR_CPU0(x) (((uint8_t)(((uint8_t)(x)) /*<< GICDistributor_ITARGETSR_CPU0_Pos*/)) & GICDistributor_ITARGETSR_CPU0_Msk) + +#define GICDistributor_ITARGETSR_CPU1_Pos 1U /*!< GICDistributor ITARGETSR: CPU1 Position */ +#define GICDistributor_ITARGETSR_CPU1_Msk (0x1U << GICDistributor_ITARGETSR_CPU1_Pos) /*!< GICDistributor ITARGETSR: CPU1 Mask */ +#define GICDistributor_ITARGETSR_CPU1(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU1_Pos)) & GICDistributor_ITARGETSR_CPU1_Msk) + +#define GICDistributor_ITARGETSR_CPU2_Pos 2U /*!< GICDistributor ITARGETSR: CPU2 Position */ +#define GICDistributor_ITARGETSR_CPU2_Msk (0x1U << GICDistributor_ITARGETSR_CPU2_Pos) /*!< GICDistributor ITARGETSR: CPU2 Mask */ +#define GICDistributor_ITARGETSR_CPU2(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU2_Pos)) & GICDistributor_ITARGETSR_CPU2_Msk) + +#define GICDistributor_ITARGETSR_CPU3_Pos 3U /*!< GICDistributor ITARGETSR: CPU3 Position */ +#define GICDistributor_ITARGETSR_CPU3_Msk (0x1U << GICDistributor_ITARGETSR_CPU3_Pos) /*!< GICDistributor ITARGETSR: CPU3 Mask */ +#define GICDistributor_ITARGETSR_CPU3(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU3_Pos)) & GICDistributor_ITARGETSR_CPU3_Msk) + +#define GICDistributor_ITARGETSR_CPU4_Pos 4U /*!< GICDistributor ITARGETSR: CPU4 Position */ +#define GICDistributor_ITARGETSR_CPU4_Msk (0x1U << GICDistributor_ITARGETSR_CPU4_Pos) /*!< GICDistributor ITARGETSR: CPU4 Mask */ +#define GICDistributor_ITARGETSR_CPU4(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU4_Pos)) & GICDistributor_ITARGETSR_CPU4_Msk) + +#define GICDistributor_ITARGETSR_CPU5_Pos 5U /*!< GICDistributor ITARGETSR: CPU5 Position */ +#define GICDistributor_ITARGETSR_CPU5_Msk (0x1U << GICDistributor_ITARGETSR_CPU5_Pos) /*!< GICDistributor ITARGETSR: CPU5 Mask */ +#define GICDistributor_ITARGETSR_CPU5(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU5_Pos)) & GICDistributor_ITARGETSR_CPU5_Msk) + +#define GICDistributor_ITARGETSR_CPU6_Pos 6U /*!< GICDistributor ITARGETSR: CPU6 Position */ +#define GICDistributor_ITARGETSR_CPU6_Msk (0x1U << GICDistributor_ITARGETSR_CPU6_Pos) /*!< GICDistributor ITARGETSR: CPU6 Mask */ +#define GICDistributor_ITARGETSR_CPU6(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU6_Pos)) & GICDistributor_ITARGETSR_CPU6_Msk) + +#define GICDistributor_ITARGETSR_CPU7_Pos 7U /*!< GICDistributor ITARGETSR: CPU7 Position */ +#define GICDistributor_ITARGETSR_CPU7_Msk (0x1U << GICDistributor_ITARGETSR_CPU7_Pos) /*!< GICDistributor ITARGETSR: CPU7 Mask */ +#define GICDistributor_ITARGETSR_CPU7(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU7_Pos)) & GICDistributor_ITARGETSR_CPU7_Msk) + +/* GICDistributor SGIR Register */ +#define GICDistributor_SGIR_INTID_Pos 0U /*!< GICDistributor SGIR: INTID Position */ +#define GICDistributor_SGIR_INTID_Msk (0x7U /*<< GICDistributor_SGIR_INTID_Pos*/) /*!< GICDistributor SGIR: INTID Mask */ +#define GICDistributor_SGIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_SGIR_INTID_Pos*/)) & GICDistributor_SGIR_INTID_Msk) + +#define GICDistributor_SGIR_NSATT_Pos 15U /*!< GICDistributor SGIR: NSATT Position */ +#define GICDistributor_SGIR_NSATT_Msk (0x1U << GICDistributor_SGIR_NSATT_Pos) /*!< GICDistributor SGIR: NSATT Mask */ +#define GICDistributor_SGIR_NSATT(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_SGIR_NSATT_Pos)) & GICDistributor_SGIR_NSATT_Msk) + +#define GICDistributor_SGIR_CPUTargetList_Pos 16U /*!< GICDistributor SGIR: CPUTargetList Position */ +#define GICDistributor_SGIR_CPUTargetList_Msk (0xFFU << GICDistributor_SGIR_CPUTargetList_Pos) /*!< GICDistributor SGIR: CPUTargetList Mask */ +#define GICDistributor_SGIR_CPUTargetList(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_SGIR_CPUTargetList_Pos)) & GICDistributor_SGIR_CPUTargetList_Msk) + +#define GICDistributor_SGIR_TargetFilterList_Pos 24U /*!< GICDistributor SGIR: TargetFilterList Position */ +#define GICDistributor_SGIR_TargetFilterList_Msk (0x3U << GICDistributor_SGIR_TargetFilterList_Pos) /*!< GICDistributor SGIR: TargetFilterList Mask */ +#define GICDistributor_SGIR_TargetFilterList(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_SGIR_TargetFilterList_Pos)) & GICDistributor_SGIR_TargetFilterList_Msk) + +/* GICDistributor IROUTER Register */ +#define GICDistributor_IROUTER_Aff0_Pos 0UL /*!< GICDistributor IROUTER: Aff0 Position */ +#define GICDistributor_IROUTER_Aff0_Msk (0xFFUL /*<< GICDistributor_IROUTER_Aff0_Pos*/) /*!< GICDistributor IROUTER: Aff0 Mask */ +#define GICDistributor_IROUTER_Aff0(x) (((uint64_t)(((uint64_t)(x)) /*<< GICDistributor_IROUTER_Aff0_Pos*/)) & GICDistributor_IROUTER_Aff0_Msk) + +#define GICDistributor_IROUTER_Aff1_Pos 8UL /*!< GICDistributor IROUTER: Aff1 Position */ +#define GICDistributor_IROUTER_Aff1_Msk (0xFFUL << GICDistributor_IROUTER_Aff1_Pos) /*!< GICDistributor IROUTER: Aff1 Mask */ +#define GICDistributor_IROUTER_Aff1(x) (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_Aff1_Pos)) & GICDistributor_IROUTER_Aff1_Msk) + +#define GICDistributor_IROUTER_Aff2_Pos 16UL /*!< GICDistributor IROUTER: Aff2 Position */ +#define GICDistributor_IROUTER_Aff2_Msk (0xFFUL << GICDistributor_IROUTER_Aff2_Pos) /*!< GICDistributor IROUTER: Aff2 Mask */ +#define GICDistributor_IROUTER_Aff2(x) (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_Aff2_Pos)) & GICDistributor_IROUTER_Aff2_Msk) + +#define GICDistributor_IROUTER_IRM_Pos 31UL /*!< GICDistributor IROUTER: IRM Position */ +#define GICDistributor_IROUTER_IRM_Msk (0xFFUL << GICDistributor_IROUTER_IRM_Pos) /*!< GICDistributor IROUTER: IRM Mask */ +#define GICDistributor_IROUTER_IRM(x) (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_IRM_Pos)) & GICDistributor_IROUTER_IRM_Msk) + +#define GICDistributor_IROUTER_Aff3_Pos 32UL /*!< GICDistributor IROUTER: Aff3 Position */ +#define GICDistributor_IROUTER_Aff3_Msk (0xFFUL << GICDistributor_IROUTER_Aff3_Pos) /*!< GICDistributor IROUTER: Aff3 Mask */ +#define GICDistributor_IROUTER_Aff3(x) (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_Aff3_Pos)) & GICDistributor_IROUTER_Aff3_Msk) + + + +/** \brief Structure type to access the Generic Interrupt Controller Interface (GICC) +*/ +typedef struct +{ + __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) CPU Interface Control Register */ + __IOM uint32_t PMR; /*!< \brief Offset: 0x004 (R/W) Interrupt Priority Mask Register */ + __IOM uint32_t BPR; /*!< \brief Offset: 0x008 (R/W) Binary Point Register */ + __IM uint32_t IAR; /*!< \brief Offset: 0x00C (R/ ) Interrupt Acknowledge Register */ + __OM uint32_t EOIR; /*!< \brief Offset: 0x010 ( /W) End Of Interrupt Register */ + __IM uint32_t RPR; /*!< \brief Offset: 0x014 (R/ ) Running Priority Register */ + __IM uint32_t HPPIR; /*!< \brief Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register */ + __IOM uint32_t ABPR; /*!< \brief Offset: 0x01C (R/W) Aliased Binary Point Register */ + __IM uint32_t AIAR; /*!< \brief Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register */ + __OM uint32_t AEOIR; /*!< \brief Offset: 0x024 ( /W) Aliased End Of Interrupt Register */ + __IM uint32_t AHPPIR; /*!< \brief Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register */ + __IOM uint32_t STATUSR; /*!< \brief Offset: 0x02C (R/W) Error Reporting Status Register, optional */ + RESERVED(1[40], uint32_t) + __IOM uint32_t APR[4]; /*!< \brief Offset: 0x0D0 (R/W) Active Priority Register */ + __IOM uint32_t NSAPR[4]; /*!< \brief Offset: 0x0E0 (R/W) Non-secure Active Priority Register */ + RESERVED(2[3], uint32_t) + __IM uint32_t IIDR; /*!< \brief Offset: 0x0FC (R/ ) CPU Interface Identification Register */ + RESERVED(3[960], uint32_t) + __OM uint32_t DIR; /*!< \brief Offset: 0x1000( /W) Deactivate Interrupt Register */ +} GICInterface_Type; + +#define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE ) /*!< \brief GIC Interface register set access pointer */ + +/* GICInterface CTLR Register */ +#define GICInterface_CTLR_Enable_Pos 0U /*!< PTIM CTLR: Enable Position */ +#define GICInterface_CTLR_Enable_Msk (0x1U /*<< GICInterface_CTLR_Enable_Pos*/) /*!< PTIM CTLR: Enable Mask */ +#define GICInterface_CTLR_Enable(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_CTLR_Enable_Pos*/)) & GICInterface_CTLR_Enable_Msk) + +/* GICInterface PMR Register */ +#define GICInterface_PMR_Priority_Pos 0U /*!< PTIM PMR: Priority Position */ +#define GICInterface_PMR_Priority_Msk (0xFFU /*<< GICInterface_PMR_Priority_Pos*/) /*!< PTIM PMR: Priority Mask */ +#define GICInterface_PMR_Priority(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_PMR_Priority_Pos*/)) & GICInterface_PMR_Priority_Msk) + +/* GICInterface BPR Register */ +#define GICInterface_BPR_Binary_Point_Pos 0U /*!< PTIM BPR: Binary_Point Position */ +#define GICInterface_BPR_Binary_Point_Msk (0x7U /*<< GICInterface_BPR_Binary_Point_Pos*/) /*!< PTIM BPR: Binary_Point Mask */ +#define GICInterface_BPR_Binary_Point(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_BPR_Binary_Point_Pos*/)) & GICInterface_BPR_Binary_Point_Msk) + +/* GICInterface IAR Register */ +#define GICInterface_IAR_INTID_Pos 0U /*!< PTIM IAR: INTID Position */ +#define GICInterface_IAR_INTID_Msk (0xFFFFFFU /*<< GICInterface_IAR_INTID_Pos*/) /*!< PTIM IAR: INTID Mask */ +#define GICInterface_IAR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_IAR_INTID_Pos*/)) & GICInterface_IAR_INTID_Msk) + +/* GICInterface EOIR Register */ +#define GICInterface_EOIR_INTID_Pos 0U /*!< PTIM EOIR: INTID Position */ +#define GICInterface_EOIR_INTID_Msk (0xFFFFFFU /*<< GICInterface_EOIR_INTID_Pos*/) /*!< PTIM EOIR: INTID Mask */ +#define GICInterface_EOIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_EOIR_INTID_Pos*/)) & GICInterface_EOIR_INTID_Msk) + +/* GICInterface RPR Register */ +#define GICInterface_RPR_INTID_Pos 0U /*!< PTIM RPR: INTID Position */ +#define GICInterface_RPR_INTID_Msk (0xFFU /*<< GICInterface_RPR_INTID_Pos*/) /*!< PTIM RPR: INTID Mask */ +#define GICInterface_RPR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_RPR_INTID_Pos*/)) & GICInterface_RPR_INTID_Msk) + +/* GICInterface HPPIR Register */ +#define GICInterface_HPPIR_INTID_Pos 0U /*!< PTIM HPPIR: INTID Position */ +#define GICInterface_HPPIR_INTID_Msk (0xFFFFFFU /*<< GICInterface_HPPIR_INTID_Pos*/) /*!< PTIM HPPIR: INTID Mask */ +#define GICInterface_HPPIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_HPPIR_INTID_Pos*/)) & GICInterface_HPPIR_INTID_Msk) + +/* GICInterface ABPR Register */ +#define GICInterface_ABPR_Binary_Point_Pos 0U /*!< PTIM ABPR: Binary_Point Position */ +#define GICInterface_ABPR_Binary_Point_Msk (0x7U /*<< GICInterface_ABPR_Binary_Point_Pos*/) /*!< PTIM ABPR: Binary_Point Mask */ +#define GICInterface_ABPR_Binary_Point(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_ABPR_Binary_Point_Pos*/)) & GICInterface_ABPR_Binary_Point_Msk) + +/* GICInterface AIAR Register */ +#define GICInterface_AIAR_INTID_Pos 0U /*!< PTIM AIAR: INTID Position */ +#define GICInterface_AIAR_INTID_Msk (0xFFFFFFU /*<< GICInterface_AIAR_INTID_Pos*/) /*!< PTIM AIAR: INTID Mask */ +#define GICInterface_AIAR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_AIAR_INTID_Pos*/)) & GICInterface_AIAR_INTID_Msk) + +/* GICInterface AEOIR Register */ +#define GICInterface_AEOIR_INTID_Pos 0U /*!< PTIM AEOIR: INTID Position */ +#define GICInterface_AEOIR_INTID_Msk (0xFFFFFFU /*<< GICInterface_AEOIR_INTID_Pos*/) /*!< PTIM AEOIR: INTID Mask */ +#define GICInterface_AEOIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_AEOIR_INTID_Pos*/)) & GICInterface_AEOIR_INTID_Msk) + +/* GICInterface AHPPIR Register */ +#define GICInterface_AHPPIR_INTID_Pos 0U /*!< PTIM AHPPIR: INTID Position */ +#define GICInterface_AHPPIR_INTID_Msk (0xFFFFFFU /*<< GICInterface_AHPPIR_INTID_Pos*/) /*!< PTIM AHPPIR: INTID Mask */ +#define GICInterface_AHPPIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_AHPPIR_INTID_Pos*/)) & GICInterface_AHPPIR_INTID_Msk) + +/* GICInterface STATUSR Register */ +#define GICInterface_STATUSR_RRD_Pos 0U /*!< GICInterface STATUSR: RRD Position */ +#define GICInterface_STATUSR_RRD_Msk (0x1U /*<< GICInterface_STATUSR_RRD_Pos*/) /*!< GICInterface STATUSR: RRD Mask */ +#define GICInterface_STATUSR_RRD(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_STATUSR_RRD_Pos*/)) & GICInterface_STATUSR_RRD_Msk) + +#define GICInterface_STATUSR_WRD_Pos 1U /*!< GICInterface STATUSR: WRD Position */ +#define GICInterface_STATUSR_WRD_Msk (0x1U << GICInterface_STATUSR_WRD_Pos) /*!< GICInterface STATUSR: WRD Mask */ +#define GICInterface_STATUSR_WRD(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_WRD_Pos)) & GICInterface_STATUSR_WRD_Msk) + +#define GICInterface_STATUSR_RWOD_Pos 2U /*!< GICInterface STATUSR: RWOD Position */ +#define GICInterface_STATUSR_RWOD_Msk (0x1U << GICInterface_STATUSR_RWOD_Pos) /*!< GICInterface STATUSR: RWOD Mask */ +#define GICInterface_STATUSR_RWOD(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_RWOD_Pos)) & GICInterface_STATUSR_RWOD_Msk) + +#define GICInterface_STATUSR_WROD_Pos 3U /*!< GICInterface STATUSR: WROD Position */ +#define GICInterface_STATUSR_WROD_Msk (0x1U << GICInterface_STATUSR_WROD_Pos) /*!< GICInterface STATUSR: WROD Mask */ +#define GICInterface_STATUSR_WROD(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_WROD_Pos)) & GICInterface_STATUSR_WROD_Msk) + +#define GICInterface_STATUSR_ASV_Pos 4U /*!< GICInterface STATUSR: ASV Position */ +#define GICInterface_STATUSR_ASV_Msk (0x1U << GICInterface_STATUSR_ASV_Pos) /*!< GICInterface STATUSR: ASV Mask */ +#define GICInterface_STATUSR_ASV(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_ASV_Pos)) & GICInterface_STATUSR_ASV_Msk) + +/* GICInterface IIDR Register */ +#define GICInterface_IIDR_Implementer_Pos 0U /*!< GICInterface IIDR: Implementer Position */ +#define GICInterface_IIDR_Implementer_Msk (0xFFFU /*<< GICInterface_IIDR_Implementer_Pos*/) /*!< GICInterface IIDR: Implementer Mask */ +#define GICInterface_IIDR_Implementer(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_IIDR_Implementer_Pos*/)) & GICInterface_IIDR_Implementer_Msk) + +#define GICInterface_IIDR_Revision_Pos 12U /*!< GICInterface IIDR: Revision Position */ +#define GICInterface_IIDR_Revision_Msk (0xFU << GICInterface_IIDR_Revision_Pos) /*!< GICInterface IIDR: Revision Mask */ +#define GICInterface_IIDR_Revision(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_IIDR_Revision_Pos)) & GICInterface_IIDR_Revision_Msk) + +#define GICInterface_IIDR_Arch_version_Pos 16U /*!< GICInterface IIDR: Arch_version Position */ +#define GICInterface_IIDR_Arch_version_Msk (0xFU << GICInterface_IIDR_Arch_version_Pos) /*!< GICInterface IIDR: Arch_version Mask */ +#define GICInterface_IIDR_Arch_version(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_IIDR_Arch_version_Pos)) & GICInterface_IIDR_Arch_version_Msk) + +#define GICInterface_IIDR_ProductID_Pos 20U /*!< GICInterface IIDR: ProductID Position */ +#define GICInterface_IIDR_ProductID_Msk (0xFFFU << GICInterface_IIDR_ProductID_Pos) /*!< GICInterface IIDR: ProductID Mask */ +#define GICInterface_IIDR_ProductID(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_IIDR_ProductID_Pos)) & GICInterface_IIDR_ProductID_Msk) + +/* GICInterface DIR Register */ +#define GICInterface_DIR_INTID_Pos 0U /*!< PTIM DIR: INTID Position */ +#define GICInterface_DIR_INTID_Msk (0xFFFFFFU /*<< GICInterface_DIR_INTID_Pos*/) /*!< PTIM DIR: INTID Mask */ +#define GICInterface_DIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_DIR_INTID_Pos*/)) & GICInterface_DIR_INTID_Msk) +#endif /* (__GIC_PRESENT == 1U) || defined(DOXYGEN) */ + +#if (defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \ + defined(DOXYGEN) +#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) +/** \brief Structure type to access the Private Timer +*/ +typedef struct +{ + __IOM uint32_t LOAD; //!< \brief Offset: 0x000 (R/W) Private Timer Load Register + __IOM uint32_t COUNTER; //!< \brief Offset: 0x004 (R/W) Private Timer Counter Register + __IOM uint32_t CONTROL; //!< \brief Offset: 0x008 (R/W) Private Timer Control Register + __IOM uint32_t ISR; //!< \brief Offset: 0x00C (R/W) Private Timer Interrupt Status Register + RESERVED(0[4], uint32_t) + __IOM uint32_t WLOAD; //!< \brief Offset: 0x020 (R/W) Watchdog Load Register + __IOM uint32_t WCOUNTER; //!< \brief Offset: 0x024 (R/W) Watchdog Counter Register + __IOM uint32_t WCONTROL; //!< \brief Offset: 0x028 (R/W) Watchdog Control Register + __IOM uint32_t WISR; //!< \brief Offset: 0x02C (R/W) Watchdog Interrupt Status Register + __IOM uint32_t WRESET; //!< \brief Offset: 0x030 (R/W) Watchdog Reset Status Register + __OM uint32_t WDISABLE; //!< \brief Offset: 0x034 ( /W) Watchdog Disable Register +} Timer_Type; +#define PTIM ((Timer_Type *) TIMER_BASE ) /*!< \brief Timer register struct */ + +/* PTIM Control Register */ +#define PTIM_CONTROL_Enable_Pos 0U /*!< PTIM CONTROL: Enable Position */ +#define PTIM_CONTROL_Enable_Msk (0x1U /*<< PTIM_CONTROL_Enable_Pos*/) /*!< PTIM CONTROL: Enable Mask */ +#define PTIM_CONTROL_Enable(x) (((uint32_t)(((uint32_t)(x)) /*<< PTIM_CONTROL_Enable_Pos*/)) & PTIM_CONTROL_Enable_Msk) + +#define PTIM_CONTROL_AutoReload_Pos 1U /*!< PTIM CONTROL: Auto Reload Position */ +#define PTIM_CONTROL_AutoReload_Msk (0x1U << PTIM_CONTROL_AutoReload_Pos) /*!< PTIM CONTROL: Auto Reload Mask */ +#define PTIM_CONTROL_AutoReload(x) (((uint32_t)(((uint32_t)(x)) << PTIM_CONTROL_AutoReload_Pos)) & PTIM_CONTROL_AutoReload_Msk) + +#define PTIM_CONTROL_IRQenable_Pos 2U /*!< PTIM CONTROL: IRQ Enabel Position */ +#define PTIM_CONTROL_IRQenable_Msk (0x1U << PTIM_CONTROL_IRQenable_Pos) /*!< PTIM CONTROL: IRQ Enabel Mask */ +#define PTIM_CONTROL_IRQenable(x) (((uint32_t)(((uint32_t)(x)) << PTIM_CONTROL_IRQenable_Pos)) & PTIM_CONTROL_IRQenable_Msk) + +#define PTIM_CONTROL_Prescaler_Pos 8U /*!< PTIM CONTROL: Prescaler Position */ +#define PTIM_CONTROL_Prescaler_Msk (0xFFU << PTIM_CONTROL_Prescaler_Pos) /*!< PTIM CONTROL: Prescaler Mask */ +#define PTIM_CONTROL_Prescaler(x) (((uint32_t)(((uint32_t)(x)) << PTIM_CONTROL_Prescaler_Pos)) & PTIM_CONTROL_Prescaler_Msk) + +/* WCONTROL Watchdog Control Register */ +#define PTIM_WCONTROL_Enable_Pos 0U /*!< PTIM WCONTROL: Enable Position */ +#define PTIM_WCONTROL_Enable_Msk (0x1U /*<< PTIM_WCONTROL_Enable_Pos*/) /*!< PTIM WCONTROL: Enable Mask */ +#define PTIM_WCONTROL_Enable(x) (((uint32_t)(((uint32_t)(x)) /*<< PTIM_WCONTROL_Enable_Pos*/)) & PTIM_WCONTROL_Enable_Msk) + +#define PTIM_WCONTROL_AutoReload_Pos 1U /*!< PTIM WCONTROL: Auto Reload Position */ +#define PTIM_WCONTROL_AutoReload_Msk (0x1U << PTIM_WCONTROL_AutoReload_Pos) /*!< PTIM WCONTROL: Auto Reload Mask */ +#define PTIM_WCONTROL_AutoReload(x) (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_AutoReload_Pos)) & PTIM_WCONTROL_AutoReload_Msk) + +#define PTIM_WCONTROL_IRQenable_Pos 2U /*!< PTIM WCONTROL: IRQ Enable Position */ +#define PTIM_WCONTROL_IRQenable_Msk (0x1U << PTIM_WCONTROL_IRQenable_Pos) /*!< PTIM WCONTROL: IRQ Enable Mask */ +#define PTIM_WCONTROL_IRQenable(x) (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_IRQenable_Pos)) & PTIM_WCONTROL_IRQenable_Msk) + +#define PTIM_WCONTROL_Mode_Pos 3U /*!< PTIM WCONTROL: Watchdog Mode Position */ +#define PTIM_WCONTROL_Mode_Msk (0x1U << PTIM_WCONTROL_Mode_Pos) /*!< PTIM WCONTROL: Watchdog Mode Mask */ +#define PTIM_WCONTROL_Mode(x) (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_Mode_Pos)) & PTIM_WCONTROL_Mode_Msk) + +#define PTIM_WCONTROL_Presacler_Pos 8U /*!< PTIM WCONTROL: Prescaler Position */ +#define PTIM_WCONTROL_Presacler_Msk (0xFFU << PTIM_WCONTROL_Presacler_Pos) /*!< PTIM WCONTROL: Prescaler Mask */ +#define PTIM_WCONTROL_Presacler(x) (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_Presacler_Pos)) & PTIM_WCONTROL_Presacler_Msk) + +/* WISR Watchdog Interrupt Status Register */ +#define PTIM_WISR_EventFlag_Pos 0U /*!< PTIM WISR: Event Flag Position */ +#define PTIM_WISR_EventFlag_Msk (0x1U /*<< PTIM_WISR_EventFlag_Pos*/) /*!< PTIM WISR: Event Flag Mask */ +#define PTIM_WISR_EventFlag(x) (((uint32_t)(((uint32_t)(x)) /*<< PTIM_WISR_EventFlag_Pos*/)) & PTIM_WISR_EventFlag_Msk) + +/* WRESET Watchdog Reset Status */ +#define PTIM_WRESET_ResetFlag_Pos 0U /*!< PTIM WRESET: Reset Flag Position */ +#define PTIM_WRESET_ResetFlag_Msk (0x1U /*<< PTIM_WRESET_ResetFlag_Pos*/) /*!< PTIM WRESET: Reset Flag Mask */ +#define PTIM_WRESET_ResetFlag(x) (((uint32_t)(((uint32_t)(x)) /*<< PTIM_WRESET_ResetFlag_Pos*/)) & PTIM_WRESET_ResetFlag_Msk) + +#endif /* ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) */ +#endif /* (__TIM_PRESENT == 1U) || defined(DOXYGEN) */ + + /******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - L1 Cache Functions + - L2C-310 Cache Controller Functions + - PL1 Timer Functions + - GIC Functions + - MMU Functions + ******************************************************************************/ + +/* ########################## L1 Cache functions ################################# */ + +/** \brief Enable Caches by setting I and C bits in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_EnableCaches(void) { + __set_SCTLR( __get_SCTLR() | SCTLR_I_Msk | SCTLR_C_Msk); + __ISB(); +} + +/** \brief Disable Caches by clearing I and C bits in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_DisableCaches(void) { + __set_SCTLR( __get_SCTLR() & (~SCTLR_I_Msk) & (~SCTLR_C_Msk)); + __ISB(); +} + +/** \brief Enable Branch Prediction by setting Z bit in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_EnableBTAC(void) { + __set_SCTLR( __get_SCTLR() | SCTLR_Z_Msk); + __ISB(); +} + +/** \brief Disable Branch Prediction by clearing Z bit in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_DisableBTAC(void) { + __set_SCTLR( __get_SCTLR() & (~SCTLR_Z_Msk)); + __ISB(); +} + +/** \brief Invalidate entire branch predictor array +*/ +__STATIC_FORCEINLINE void L1C_InvalidateBTAC(void) { + __set_BPIALL(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new state +} + +/** \brief Clean instruction cache line by address. +* \param [in] va Pointer to instructions to clear the cache for. +*/ +__STATIC_FORCEINLINE void L1C_InvalidateICacheMVA(void *va) { + __set_ICIMVAC((uint32_t)va); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new I cache state +} + +/** \brief Invalidate the whole instruction cache +*/ +__STATIC_FORCEINLINE void L1C_InvalidateICacheAll(void) { + __set_ICIALLU(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new I cache state +} + +/** \brief Clean data cache line by address. +* \param [in] va Pointer to data to clear the cache for. +*/ +__STATIC_FORCEINLINE void L1C_CleanDCacheMVA(void *va) { + __set_DCCMVAC((uint32_t)va); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Invalidate data cache line by address. +* \param [in] va Pointer to data to invalidate the cache for. +*/ +__STATIC_FORCEINLINE void L1C_InvalidateDCacheMVA(void *va) { + __set_DCIMVAC((uint32_t)va); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Clean and Invalidate data cache by address. +* \param [in] va Pointer to data to invalidate the cache for. +*/ +__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheMVA(void *va) { + __set_DCCIMVAC((uint32_t)va); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Calculate log2 rounded up +* - log(0) => 0 +* - log(1) => 0 +* - log(2) => 1 +* - log(3) => 2 +* - log(4) => 2 +* - log(5) => 3 +* : : +* - log(16) => 4 +* - log(32) => 5 +* : : +* \param [in] n input value parameter +* \return log2(n) +*/ +__STATIC_FORCEINLINE uint8_t __log2_up(uint32_t n) +{ + if (n < 2U) { + return 0U; + } + uint8_t log = 0U; + uint32_t t = n; + while(t > 1U) + { + log++; + t >>= 1U; + } + if (n & 1U) { log++; } + return log; +} + +/** \brief Apply cache maintenance to given cache level. +* \param [in] level cache level to be maintained +* \param [in] maint 0 - invalidate, 1 - clean, otherwise - invalidate and clean +*/ +__STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint) +{ + uint32_t Dummy; + uint32_t ccsidr; + uint32_t num_sets; + uint32_t num_ways; + uint32_t shift_way; + uint32_t log2_linesize; + uint8_t log2_num_ways; + + Dummy = level << 1U; + /* set csselr, select ccsidr register */ + __set_CSSELR(Dummy); + /* get current ccsidr register */ + ccsidr = __get_CCSIDR(); + num_sets = ((ccsidr & 0x0FFFE000U) >> 13U) + 1U; + num_ways = ((ccsidr & 0x00001FF8U) >> 3U) + 1U; + log2_linesize = (ccsidr & 0x00000007U) + 2U + 2U; + log2_num_ways = __log2_up(num_ways); + if (log2_num_ways > 32U) { + return; // FATAL ERROR + } + shift_way = 32U - log2_num_ways; + for(int32_t way = num_ways-1; way >= 0; way--) + { + for(int32_t set = num_sets-1; set >= 0; set--) + { + Dummy = (level << 1U) | (((uint32_t)set) << log2_linesize) | (((uint32_t)way) << shift_way); + switch (maint) + { + case 0U: __set_DCISW(Dummy); break; + case 1U: __set_DCCSW(Dummy); break; + default: __set_DCCISW(Dummy); break; + } + } + } + __DMB(); +} + +/** \brief Clean and Invalidate the entire data or unified cache +* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean +*/ +__STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) { + uint32_t clidr; + uint32_t cache_type; + clidr = __get_CLIDR(); + for(uint32_t i = 0U; i<7U; i++) + { + cache_type = (clidr >> i*3U) & 0x7UL; + if ((cache_type >= 2U) && (cache_type <= 4U)) + { + __L1C_MaintainDCacheSetWay(i, op); + } + } +} + +/** \brief Invalidate the whole data cache. +*/ +__STATIC_FORCEINLINE void L1C_InvalidateDCacheAll(void) { + L1C_CleanInvalidateCache(0); +} + +/** \brief Clean the whole data cache. + */ +__STATIC_FORCEINLINE void L1C_CleanDCacheAll(void) { + L1C_CleanInvalidateCache(1); +} + +/** \brief Clean and invalidate the whole data cache. + */ +__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll(void) { + L1C_CleanInvalidateCache(2); +} + +/* ########################## L2 Cache functions ################################# */ +#if (defined(__L2C_PRESENT) && (__L2C_PRESENT == 1U)) || \ + defined(DOXYGEN) +/** \brief Cache Sync operation by writing CACHE_SYNC register. +*/ +__STATIC_INLINE void L2C_Sync(void) +{ + L2C_310->CACHE_SYNC = 0x0; +} + +/** \brief Read cache controller cache ID from CACHE_ID register. + * \return L2C_310_TypeDef::CACHE_ID + */ +__STATIC_INLINE int L2C_GetID (void) +{ + return L2C_310->CACHE_ID; +} + +/** \brief Read cache controller cache type from CACHE_TYPE register. +* \return L2C_310_TypeDef::CACHE_TYPE +*/ +__STATIC_INLINE int L2C_GetType (void) +{ + return L2C_310->CACHE_TYPE; +} + +/** \brief Invalidate all cache by way +*/ +__STATIC_INLINE void L2C_InvAllByWay (void) +{ + unsigned int assoc; + + if (L2C_310->AUX_CNT & (1U << 16U)) { + assoc = 16U; + } else { + assoc = 8U; + } + + L2C_310->INV_WAY = (1U << assoc) - 1U; + while(L2C_310->INV_WAY & ((1U << assoc) - 1U)); //poll invalidate + + L2C_Sync(); +} + +/** \brief Clean and Invalidate all cache by way +*/ +__STATIC_INLINE void L2C_CleanInvAllByWay (void) +{ + unsigned int assoc; + + if (L2C_310->AUX_CNT & (1U << 16U)) { + assoc = 16U; + } else { + assoc = 8U; + } + + L2C_310->CLEAN_INV_WAY = (1U << assoc) - 1U; + while(L2C_310->CLEAN_INV_WAY & ((1U << assoc) - 1U)); //poll invalidate + + L2C_Sync(); +} + +/** \brief Enable Level 2 Cache +*/ +__STATIC_INLINE void L2C_Enable(void) +{ + L2C_310->CONTROL = 0; + L2C_310->INTERRUPT_CLEAR = 0x000001FFuL; + L2C_310->DEBUG_CONTROL = 0; + L2C_310->DATA_LOCK_0_WAY = 0; + L2C_310->CACHE_SYNC = 0; + L2C_310->CONTROL = 0x01; + L2C_Sync(); +} + +/** \brief Disable Level 2 Cache +*/ +__STATIC_INLINE void L2C_Disable(void) +{ + L2C_310->CONTROL = 0x00; + L2C_Sync(); +} + +/** \brief Invalidate cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ +__STATIC_INLINE void L2C_InvPa (void *pa) +{ + L2C_310->INV_LINE_PA = (unsigned int)pa; + L2C_Sync(); +} + +/** \brief Clean cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ +__STATIC_INLINE void L2C_CleanPa (void *pa) +{ + L2C_310->CLEAN_LINE_PA = (unsigned int)pa; + L2C_Sync(); +} + +/** \brief Clean and invalidate cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ +__STATIC_INLINE void L2C_CleanInvPa (void *pa) +{ + L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa; + L2C_Sync(); +} +#endif + +/* ########################## GIC functions ###################################### */ +#if (defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U)) || \ + defined(DOXYGEN) + +/** \brief Enable the interrupt distributor using the GIC's CTLR register. +*/ +__STATIC_INLINE void GIC_EnableDistributor(void) +{ + GICDistributor->CTLR |= 1U; +} + +/** \brief Disable the interrupt distributor using the GIC's CTLR register. +*/ +__STATIC_INLINE void GIC_DisableDistributor(void) +{ + GICDistributor->CTLR &=~1U; +} + +/** \brief Read the GIC's TYPER register. +* \return GICDistributor_Type::TYPER +*/ +__STATIC_INLINE uint32_t GIC_DistributorInfo(void) +{ + return (GICDistributor->TYPER); +} + +/** \brief Reads the GIC's IIDR register. +* \return GICDistributor_Type::IIDR +*/ +__STATIC_INLINE uint32_t GIC_DistributorImplementer(void) +{ + return (GICDistributor->IIDR); +} + +/** \brief Sets the GIC's ITARGETSR register for the given interrupt. +* \param [in] IRQn Interrupt to be configured. +* \param [in] cpu_target CPU interfaces to assign this interrupt to. +*/ +__STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target) +{ + uint32_t mask = GICDistributor->ITARGETSR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); + GICDistributor->ITARGETSR[IRQn / 4U] = mask | ((cpu_target & 0xFFUL) << ((IRQn % 4U) * 8U)); +} + +/** \brief Read the GIC's ITARGETSR register. +* \param [in] IRQn Interrupt to acquire the configuration for. +* \return GICDistributor_Type::ITARGETSR +*/ +__STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn) +{ + return (GICDistributor->ITARGETSR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; +} + +/** \brief Enable the CPU's interrupt interface. +*/ +__STATIC_INLINE void GIC_EnableInterface(void) +{ + GICInterface->CTLR |= 1U; //enable interface +} + +/** \brief Disable the CPU's interrupt interface. +*/ +__STATIC_INLINE void GIC_DisableInterface(void) +{ + GICInterface->CTLR &=~1U; //disable distributor +} + +/** \brief Read the CPU's IAR register. +* \return GICInterface_Type::IAR +*/ +__STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void) +{ + return (IRQn_Type)(GICInterface->IAR); +} + +/** \brief Writes the given interrupt number to the CPU's EOIR register. +* \param [in] IRQn The interrupt to be signaled as finished. +*/ +__STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn) +{ + GICInterface->EOIR = IRQn; +} + +/** \brief Enables the given interrupt using GIC's ISENABLER register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn) +{ + GICDistributor->ISENABLER[IRQn / 32U] = 1U << (IRQn % 32U); +} + +/** \brief Get interrupt enable status using GIC's ISENABLER register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - interrupt is not enabled, 1 - interrupt is enabled. +*/ +__STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn) +{ + return (GICDistributor->ISENABLER[IRQn / 32U] >> (IRQn % 32U)) & 1UL; +} + +/** \brief Disables the given interrupt using GIC's ICENABLER register. +* \param [in] IRQn The interrupt to be disabled. +*/ +__STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn) +{ + GICDistributor->ICENABLER[IRQn / 32U] = 1U << (IRQn % 32U); +} + +/** \brief Get interrupt pending status from GIC's ISPENDR register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - interrupt is not pending, 1 - interrupt is pendig. +*/ +__STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn) +{ + uint32_t pend; + + if (IRQn >= 16U) { + pend = (GICDistributor->ISPENDR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; + } else { + // INTID 0-15 Software Generated Interrupt + pend = (GICDistributor->SPENDSGIR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; + // No CPU identification offered + if (pend != 0U) { + pend = 1U; + } else { + pend = 0U; + } + } + + return (pend); +} + +/** \brief Sets the given interrupt as pending using GIC's ISPENDR register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if (IRQn >= 16U) { + GICDistributor->ISPENDR[IRQn / 32U] = 1U << (IRQn % 32U); + } else { + // INTID 0-15 Software Generated Interrupt + // Forward the interrupt to the CPU interface that requested it + GICDistributor->SGIR = (IRQn | 0x02000000U); + } +} + +/** \brief Clears the given interrupt from being pending using GIC's ICPENDR register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if (IRQn >= 16U) { + GICDistributor->ICPENDR[IRQn / 32U] = 1U << (IRQn % 32U); + } else { + // INTID 0-15 Software Generated Interrupt + GICDistributor->CPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U); + } +} + +/** \brief Sets the interrupt configuration using GIC's ICFGR register. +* \param [in] IRQn The interrupt to be configured. +* \param [in] int_config Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) +* Bit 1: 0 - level sensitive, 1 - edge triggered +*/ +__STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config) +{ + uint32_t icfgr = GICDistributor->ICFGR[IRQn / 16U]; /* read current register content */ + uint32_t shift = (IRQn % 16U) << 1U; /* calculate shift value */ + + int_config &= 3U; /* only 2 bits are valid */ + icfgr &= (~(3U << shift)); /* clear bits to change */ + icfgr |= ( int_config << shift); /* set new configuration */ + + GICDistributor->ICFGR[IRQn / 16U] = icfgr; /* write new register content */ +} + +/** \brief Get the interrupt configuration from the GIC's ICFGR register. +* \param [in] IRQn Interrupt to acquire the configuration for. +* \return Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) +* Bit 1: 0 - level sensitive, 1 - edge triggered +*/ +__STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn) +{ + return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) >> 1U)); +} + +/** \brief Set the priority for the given interrupt in the GIC's IPRIORITYR register. +* \param [in] IRQn The interrupt to be configured. +* \param [in] priority The priority for the interrupt, lower values denote higher priorities. +*/ +__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + uint32_t mask = GICDistributor->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); + GICDistributor->IPRIORITYR[IRQn / 4U] = mask | ((priority & 0xFFUL) << ((IRQn % 4U) * 8U)); +} + +/** \brief Read the current interrupt priority from GIC's IPRIORITYR register. +* \param [in] IRQn The interrupt to be queried. +*/ +__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn) +{ + return (GICDistributor->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; +} + +/** \brief Set the interrupt priority mask using CPU's PMR register. +* \param [in] priority Priority mask to be set. +*/ +__STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority) +{ + GICInterface->PMR = priority & 0xFFUL; //set priority mask +} + +/** \brief Read the current interrupt priority mask from CPU's PMR register. +* \result GICInterface_Type::PMR +*/ +__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void) +{ + return GICInterface->PMR; +} + +/** \brief Configures the group priority and subpriority split point using CPU's BPR register. +* \param [in] binary_point Amount of bits used as subpriority. +*/ +__STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point) +{ + GICInterface->BPR = binary_point & 7U; //set binary point +} + +/** \brief Read the current group priority and subpriority split point from CPU's BPR register. +* \return GICInterface_Type::BPR +*/ +__STATIC_INLINE uint32_t GIC_GetBinaryPoint(void) +{ + return GICInterface->BPR; +} + +/** \brief Get the status for a given interrupt. +* \param [in] IRQn The interrupt to get status for. +* \return 0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active +*/ +__STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn) +{ + uint32_t pending, active; + + active = ((GICDistributor->ISACTIVER[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; + pending = ((GICDistributor->ISPENDR[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; + + return ((active<<1U) | pending); +} + +/** \brief Generate a software interrupt using GIC's SGIR register. +* \param [in] IRQn Software interrupt to be generated. +* \param [in] target_list List of CPUs the software interrupt should be forwarded to. +* \param [in] filter_list Filter to be applied to determine interrupt receivers. +*/ +__STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list) +{ + GICDistributor->SGIR = ((filter_list & 3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (IRQn & 0x0FUL); +} + +/** \brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register. +* \return GICInterface_Type::HPPIR +*/ +__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void) +{ + return GICInterface->HPPIR; +} + +/** \brief Provides information about the implementer and revision of the CPU interface. +* \return GICInterface_Type::IIDR +*/ +__STATIC_INLINE uint32_t GIC_GetInterfaceId(void) +{ + return GICInterface->IIDR; +} + +/** \brief Set the interrupt group from the GIC's IGROUPR register. +* \param [in] IRQn The interrupt to be queried. +* \param [in] group Interrupt group number: 0 - Group 0, 1 - Group 1 +*/ +__STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group) +{ + uint32_t igroupr = GICDistributor->IGROUPR[IRQn / 32U]; + uint32_t shift = (IRQn % 32U); + + igroupr &= (~(1U << shift)); + igroupr |= ( (group & 1U) << shift); + + GICDistributor->IGROUPR[IRQn / 32U] = igroupr; +} +#define GIC_SetSecurity GIC_SetGroup + +/** \brief Get the interrupt group from the GIC's IGROUPR register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - Group 0, 1 - Group 1 +*/ +__STATIC_INLINE uint32_t GIC_GetGroup(IRQn_Type IRQn) +{ + return (GICDistributor->IGROUPR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; +} +#define GIC_GetSecurity GIC_GetGroup + +/** \brief Initialize the interrupt distributor. +*/ +__STATIC_INLINE void GIC_DistInit(void) +{ + uint32_t i; + uint32_t num_irq = 0U; + uint32_t priority_field; + + //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, + //configuring all of the interrupts as Secure. + + //Disable interrupt forwarding + GIC_DisableDistributor(); + //Get the maximum number of interrupts that the GIC supports + num_irq = 32U * ((GIC_DistributorInfo() & 0x1FU) + 1U); + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an IPRIORITYR + priority field and read back the value stored.*/ + GIC_SetPriority((IRQn_Type)0U, 0xFFU); + priority_field = GIC_GetPriority((IRQn_Type)0U); + + for (i = 32U; i < num_irq; i++) + { + //Disable the SPI interrupt + GIC_DisableIRQ((IRQn_Type)i); + //Set level-sensitive (and N-N model) + GIC_SetConfiguration((IRQn_Type)i, 0U); + //Set priority + GIC_SetPriority((IRQn_Type)i, priority_field/2U); + //Set target list to CPU0 + GIC_SetTarget((IRQn_Type)i, 1U); + } + //Enable distributor + GIC_EnableDistributor(); +} + +/** \brief Initialize the CPU's interrupt interface +*/ +__STATIC_INLINE void GIC_CPUInterfaceInit(void) +{ + uint32_t i; + uint32_t priority_field; + + //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, + //configuring all of the interrupts as Secure. + + //Disable interrupt forwarding + GIC_DisableInterface(); + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an IPRIORITYR + priority field and read back the value stored.*/ + GIC_SetPriority((IRQn_Type)0U, 0xFFU); + priority_field = GIC_GetPriority((IRQn_Type)0U); + + //SGI and PPI + for (i = 0U; i < 32U; i++) + { + if(i > 15U) { + //Set level-sensitive (and N-N model) for PPI + GIC_SetConfiguration((IRQn_Type)i, 0U); + } + //Disable SGI and PPI interrupts + GIC_DisableIRQ((IRQn_Type)i); + //Set priority + GIC_SetPriority((IRQn_Type)i, priority_field/2U); + } + //Enable interface + GIC_EnableInterface(); + //Set binary point to 0 + GIC_SetBinaryPoint(0U); + //Set priority mask + GIC_SetInterfacePriorityMask(0xFFU); +} + +/** \brief Initialize and enable the GIC +*/ +__STATIC_INLINE void GIC_Enable(void) +{ + GIC_DistInit(); + GIC_CPUInterfaceInit(); //per CPU +} +#endif + +/* ########################## Generic Timer functions ############################ */ +#if (defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \ + defined(DOXYGEN) + +/* PL1 Physical Timer */ +#if (__CORTEX_A == 7U) || defined(DOXYGEN) + +/** \brief Physical Timer Control register */ +typedef union +{ + struct + { + uint32_t ENABLE:1; /*!< \brief bit: 0 Enables the timer. */ + uint32_t IMASK:1; /*!< \brief bit: 1 Timer output signal mask bit. */ + uint32_t ISTATUS:1; /*!< \brief bit: 2 The status of the timer. */ + RESERVED(0:29, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CNTP_CTL_Type; + +/** \brief Configures the frequency the timer shall run at. +* \param [in] value The timer frequency in Hz. +*/ +__STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value) +{ + __set_CNTFRQ(value); + __ISB(); +} + +/** \brief Sets the reset value of the timer. +* \param [in] value The value the timer is loaded with. +*/ +__STATIC_INLINE void PL1_SetLoadValue(uint32_t value) +{ + __set_CNTP_TVAL(value); + __ISB(); +} + +/** \brief Get the current counter value. +* \return Current counter value. +*/ +__STATIC_INLINE uint32_t PL1_GetCurrentValue(void) +{ + return(__get_CNTP_TVAL()); +} + +/** \brief Get the current physical counter value. +* \return Current physical counter value. +*/ +__STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue(void) +{ + return(__get_CNTPCT()); +} + +/** \brief Set the physical compare value. +* \param [in] value New physical timer compare value. +*/ +__STATIC_INLINE void PL1_SetPhysicalCompareValue(uint64_t value) +{ + __set_CNTP_CVAL(value); + __ISB(); +} + +/** \brief Get the physical compare value. +* \return Physical compare value. +*/ +__STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue(void) +{ + return(__get_CNTP_CVAL()); +} + +/** \brief Configure the timer by setting the control value. +* \param [in] value New timer control value. +*/ +__STATIC_INLINE void PL1_SetControl(uint32_t value) +{ + __set_CNTP_CTL(value); + __ISB(); +} + +/** \brief Get the control value. +* \return Control value. +*/ +__STATIC_INLINE uint32_t PL1_GetControl(void) +{ + return(__get_CNTP_CTL()); +} + +/******************************* VIRTUAL TIMER *******************************/ +/** \brief Virtual Timer Control register */ + +/** \brief Sets the reset value of the virtual timer. +* \param [in] value The value the virtual timer is loaded with. +*/ +__STATIC_INLINE void VL1_SetCurrentTimerValue(uint32_t value) +{ + __set_CNTV_TVAL(value); + __ISB(); +} + +/** \brief Get the current virtual timer value. +* \return Current virtual timer value. +*/ +__STATIC_INLINE uint32_t VL1_GetCurrentTimerValue(void) +{ + return(__get_CNTV_TVAL()); +} + +/** \brief Get the current virtual count value. +* \return Current virtual count value. +*/ +__STATIC_INLINE uint64_t VL1_GetCurrentCountValue(void) +{ + return(__get_CNTVCT()); +} + +/** \brief Set the virtual timer compare value. +* \param [in] value New virtual timer compare value. +*/ +__STATIC_INLINE void VL1_SetTimerCompareValue(uint64_t value) +{ + __set_CNTV_CVAL(value); + __ISB(); +} + +/** \brief Get the virtual timer compare value. +* \return Virtual timer compare value. +*/ +__STATIC_INLINE uint64_t VL1_GetTimerCompareValue(void) +{ + return(__get_CNTV_CVAL()); +} + +/** \brief Configure the virtual timer by setting the control value. +* \param [in] value New virtual timer control value. +*/ +__STATIC_INLINE void VL1_SetControl(uint32_t value) +{ + __set_CNTV_CTL(value); + __ISB(); +} + +/** \brief Get the virtual timer control value. +* \return Virtual timer control value. +*/ +__STATIC_INLINE uint32_t VL1_GetControl(void) +{ + return(__get_CNTV_CTL()); +} +/***************************** VIRTUAL TIMER END *****************************/ +#endif + +/* Private Timer */ +#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) +/** \brief Set the load value to timers LOAD register. +* \param [in] value The load value to be set. +*/ +__STATIC_INLINE void PTIM_SetLoadValue(uint32_t value) +{ + PTIM->LOAD = value; +} + +/** \brief Get the load value from timers LOAD register. +* \return Timer_Type::LOAD +*/ +__STATIC_INLINE uint32_t PTIM_GetLoadValue(void) +{ + return(PTIM->LOAD); +} + +/** \brief Set current counter value from its COUNTER register. +*/ +__STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value) +{ + PTIM->COUNTER = value; +} + +/** \brief Get current counter value from timers COUNTER register. +* \result Timer_Type::COUNTER +*/ +__STATIC_INLINE uint32_t PTIM_GetCurrentValue(void) +{ + return(PTIM->COUNTER); +} + +/** \brief Configure the timer using its CONTROL register. +* \param [in] value The new configuration value to be set. +*/ +__STATIC_INLINE void PTIM_SetControl(uint32_t value) +{ + PTIM->CONTROL = value; +} + +/** ref Timer_Type::CONTROL Get the current timer configuration from its CONTROL register. +* \return Timer_Type::CONTROL +*/ +__STATIC_INLINE uint32_t PTIM_GetControl(void) +{ + return(PTIM->CONTROL); +} + +/** ref Timer_Type::CONTROL Get the event flag in timers ISR register. +* \return 0 - flag is not set, 1- flag is set +*/ +__STATIC_INLINE uint32_t PTIM_GetEventFlag(void) +{ + return (PTIM->ISR & 1UL); +} + +/** ref Timer_Type::CONTROL Clears the event flag in timers ISR register. +*/ +__STATIC_INLINE void PTIM_ClearEventFlag(void) +{ + PTIM->ISR = 1; +} +#endif +#endif + +/* ########################## MMU functions ###################################### */ + +#define SECTION_DESCRIPTOR (0x2) +#define SECTION_MASK (0xFFFFFFFC) + +#define SECTION_TEXCB_MASK (0xFFFF8FF3) +#define SECTION_B_SHIFT (2) +#define SECTION_C_SHIFT (3) +#define SECTION_TEX0_SHIFT (12) +#define SECTION_TEX1_SHIFT (13) +#define SECTION_TEX2_SHIFT (14) + +#define SECTION_XN_MASK (0xFFFFFFEF) +#define SECTION_XN_SHIFT (4) + +#define SECTION_DOMAIN_MASK (0xFFFFFE1F) +#define SECTION_DOMAIN_SHIFT (5) + +#define SECTION_P_MASK (0xFFFFFDFF) +#define SECTION_P_SHIFT (9) + +#define SECTION_AP_MASK (0xFFFF73FF) +#define SECTION_AP_SHIFT (10) +#define SECTION_AP2_SHIFT (15) + +#define SECTION_S_MASK (0xFFFEFFFF) +#define SECTION_S_SHIFT (16) + +#define SECTION_NG_MASK (0xFFFDFFFF) +#define SECTION_NG_SHIFT (17) + +#define SECTION_NS_MASK (0xFFF7FFFF) +#define SECTION_NS_SHIFT (19) + +#define PAGE_L1_DESCRIPTOR (0x1) +#define PAGE_L1_MASK (0xFFFFFFFC) + +#define PAGE_L2_4K_DESC (0x2) +#define PAGE_L2_4K_MASK (0xFFFFFFFD) + +#define PAGE_L2_64K_DESC (0x1) +#define PAGE_L2_64K_MASK (0xFFFFFFFC) + +#define PAGE_4K_TEXCB_MASK (0xFFFFFE33) +#define PAGE_4K_B_SHIFT (2) +#define PAGE_4K_C_SHIFT (3) +#define PAGE_4K_TEX0_SHIFT (6) +#define PAGE_4K_TEX1_SHIFT (7) +#define PAGE_4K_TEX2_SHIFT (8) + +#define PAGE_64K_TEXCB_MASK (0xFFFF8FF3) +#define PAGE_64K_B_SHIFT (2) +#define PAGE_64K_C_SHIFT (3) +#define PAGE_64K_TEX0_SHIFT (12) +#define PAGE_64K_TEX1_SHIFT (13) +#define PAGE_64K_TEX2_SHIFT (14) + +#define PAGE_TEXCB_MASK (0xFFFF8FF3) +#define PAGE_B_SHIFT (2) +#define PAGE_C_SHIFT (3) +#define PAGE_TEX_SHIFT (12) + +#define PAGE_XN_4K_MASK (0xFFFFFFFE) +#define PAGE_XN_4K_SHIFT (0) +#define PAGE_XN_64K_MASK (0xFFFF7FFF) +#define PAGE_XN_64K_SHIFT (15) + +#define PAGE_DOMAIN_MASK (0xFFFFFE1F) +#define PAGE_DOMAIN_SHIFT (5) + +#define PAGE_P_MASK (0xFFFFFDFF) +#define PAGE_P_SHIFT (9) + +#define PAGE_AP_MASK (0xFFFFFDCF) +#define PAGE_AP_SHIFT (4) +#define PAGE_AP2_SHIFT (9) + +#define PAGE_S_MASK (0xFFFFFBFF) +#define PAGE_S_SHIFT (10) + +#define PAGE_NG_MASK (0xFFFFF7FF) +#define PAGE_NG_SHIFT (11) + +#define PAGE_NS_MASK (0xFFFFFFF7) +#define PAGE_NS_SHIFT (3) + +#define OFFSET_1M (0x00100000) +#define OFFSET_64K (0x00010000) +#define OFFSET_4K (0x00001000) + +#define DESCRIPTOR_FAULT (0x00000000) + +/* Attributes enumerations */ + +/* Region size attributes */ +typedef enum +{ + SECTION, + PAGE_4k, + PAGE_64k, +} mmu_region_size_Type; + +/* Region type attributes */ +typedef enum +{ + NORMAL, + DEVICE, + SHARED_DEVICE, + NON_SHARED_DEVICE, + STRONGLY_ORDERED +} mmu_memory_Type; + +/* Region cacheability attributes */ +typedef enum +{ + NON_CACHEABLE, + WB_WA, + WT, + WB_NO_WA, +} mmu_cacheability_Type; + +/* Region parity check attributes */ +typedef enum +{ + ECC_DISABLED, + ECC_ENABLED, +} mmu_ecc_check_Type; + +/* Region execution attributes */ +typedef enum +{ + EXECUTE, + NON_EXECUTE, +} mmu_execute_Type; + +/* Region global attributes */ +typedef enum +{ + GLOBAL, + NON_GLOBAL, +} mmu_global_Type; + +/* Region shareability attributes */ +typedef enum +{ + NON_SHARED, + SHARED, +} mmu_shared_Type; + +/* Region security attributes */ +typedef enum +{ + SECURE, + NON_SECURE, +} mmu_secure_Type; + +/* Region access attributes */ +typedef enum +{ + NO_ACCESS, + RW, + READ, +} mmu_access_Type; + +/* Memory Region definition */ +typedef struct RegionStruct { + mmu_region_size_Type rg_t; + mmu_memory_Type mem_t; + uint8_t domain; + mmu_cacheability_Type inner_norm_t; + mmu_cacheability_Type outer_norm_t; + mmu_ecc_check_Type e_t; + mmu_execute_Type xn_t; + mmu_global_Type g_t; + mmu_secure_Type sec_t; + mmu_access_Type priv_t; + mmu_access_Type user_t; + mmu_shared_Type sh_t; + +} mmu_region_attributes_Type; + +//Following macros define the descriptors and attributes +//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0 +#define section_normal(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_NC. Outer & inner non-cacheable, non-shareable, executable, rw, domain 0 +#define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0 +#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_RO. Sect_Normal_Cod, but not executable +#define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable +#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); +//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 +#define section_so(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0 +#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Device_RW. Sect_Device_RO, but writeable +#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); +//Page_4k_Device_RW. Shared device, not executable, rw, domain 0 +#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = SHARED_DEVICE; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region); + +//Page_64k_Device_RW. Shared device, not executable, rw, domain 0 +#define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = SHARED_DEVICE; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region); + +/** \brief Set section execution-never attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE. + + \return 0 +*/ +__STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn) +{ + *descriptor_l1 &= SECTION_XN_MASK; + *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT); + return 0; +} + +/** \brief Set section domain + + \param [out] descriptor_l1 L1 descriptor. + \param [in] domain Section domain + + \return 0 +*/ +__STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain) +{ + *descriptor_l1 &= SECTION_DOMAIN_MASK; + *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT); + return 0; +} + +/** \brief Set section parity check + + \param [out] descriptor_l1 L1 descriptor. + \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED + + \return 0 +*/ +__STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) +{ + *descriptor_l1 &= SECTION_P_MASK; + *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); + return 0; +} + +/** \brief Set section access privileges + + \param [out] descriptor_l1 L1 descriptor. + \param [in] user User Level Access: NO_ACCESS, RW, READ + \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ + \param [in] afe Access flag enable + + \return 0 +*/ +__STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) +{ + uint32_t ap = 0; + + if (afe == 0) { //full access + if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } + else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == READ)) { ap = 0x2; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + else { //Simplified access + if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + *descriptor_l1 &= SECTION_AP_MASK; + *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT; + *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT; + + return 0; +} + +/** \brief Set section shareability + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit Section shareability: NON_SHARED, SHARED + + \return 0 +*/ +__STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit) +{ + *descriptor_l1 &= SECTION_S_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT); + return 0; +} + +/** \brief Set section Global attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL + + \return 0 +*/ +__STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit) +{ + *descriptor_l1 &= SECTION_NG_MASK; + *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT); + return 0; +} + +/** \brief Set section Security attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit Section Security attribute: SECURE, NON_SECURE + + \return 0 +*/ +__STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit) +{ + *descriptor_l1 &= SECTION_NS_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT); + return 0; +} + +/* Page 4k or 64k */ +/** \brief Set 4k/64k page execution-never attribute + + \param [out] descriptor_l2 L2 descriptor. + \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE. + \param [in] page Page size: PAGE_4k, PAGE_64k, + + \return 0 +*/ +__STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page) +{ + if (page == PAGE_4k) + { + *descriptor_l2 &= PAGE_XN_4K_MASK; + *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT); + } + else + { + *descriptor_l2 &= PAGE_XN_64K_MASK; + *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT); + } + return 0; +} + +/** \brief Set 4k/64k page domain + + \param [out] descriptor_l1 L1 descriptor. + \param [in] domain Page domain + + \return 0 +*/ +__STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain) +{ + *descriptor_l1 &= PAGE_DOMAIN_MASK; + *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page parity check + + \param [out] descriptor_l1 L1 descriptor. + \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED + + \return 0 +*/ +__STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) +{ + *descriptor_l1 &= SECTION_P_MASK; + *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page access privileges + + \param [out] descriptor_l2 L2 descriptor. + \param [in] user User Level Access: NO_ACCESS, RW, READ + \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ + \param [in] afe Access flag enable + + \return 0 +*/ +__STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) +{ + uint32_t ap = 0; + + if (afe == 0) { //full access + if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } + else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == READ)) { ap = 0x2; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x6; } + } + + else { //Simplified access + if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + *descriptor_l2 &= PAGE_AP_MASK; + *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT; + *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT; + + return 0; +} + +/** \brief Set 4k/64k page shareability + + \param [out] descriptor_l2 L2 descriptor. + \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED + + \return 0 +*/ +__STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit) +{ + *descriptor_l2 &= PAGE_S_MASK; + *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page Global attribute + + \param [out] descriptor_l2 L2 descriptor. + \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL + + \return 0 +*/ +__STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit) +{ + *descriptor_l2 &= PAGE_NG_MASK; + *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page Security attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE + + \return 0 +*/ +__STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit) +{ + *descriptor_l1 &= PAGE_NS_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT); + return 0; +} + +/** \brief Set Section memory attributes + + \param [out] descriptor_l1 L1 descriptor. + \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED + \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + + \return 0 +*/ +__STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner) +{ + *descriptor_l1 &= SECTION_TEXCB_MASK; + + if (STRONGLY_ORDERED == mem) + { + return 0; + } + else if (SHARED_DEVICE == mem) + { + *descriptor_l1 |= (1 << SECTION_B_SHIFT); + } + else if (NON_SHARED_DEVICE == mem) + { + *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT); + } + else if (NORMAL == mem) + { + *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT; + switch(inner) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l1 |= (1 << SECTION_B_SHIFT); + break; + case WT: + *descriptor_l1 |= 1 << SECTION_C_SHIFT; + break; + case WB_NO_WA: + *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT); + break; + } + switch(outer) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT); + break; + case WT: + *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT; + break; + case WB_NO_WA: + *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT); + break; + } + } + return 0; +} + +/** \brief Set 4k/64k page memory attributes + + \param [out] descriptor_l2 L2 descriptor. + \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED + \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] page Page size + + \return 0 +*/ +__STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page) +{ + *descriptor_l2 &= PAGE_4K_TEXCB_MASK; + + if (page == PAGE_64k) + { + //same as section + MMU_MemorySection(descriptor_l2, mem, outer, inner); + } + else + { + if (STRONGLY_ORDERED == mem) + { + return 0; + } + else if (SHARED_DEVICE == mem) + { + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); + } + else if (NON_SHARED_DEVICE == mem) + { + *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT); + } + else if (NORMAL == mem) + { + *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT; + switch(inner) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); + break; + case WT: + *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT; + break; + case WB_NO_WA: + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT); + break; + } + switch(outer) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT); + break; + case WT: + *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT; + break; + case WB_NO_WA: + *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT); + break; + } + } + } + + return 0; +} + +/** \brief Create a L1 section descriptor + + \param [out] descriptor L1 descriptor + \param [in] reg Section attributes + + \return 0 +*/ +__STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg) +{ + *descriptor = 0; + + MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t); + MMU_XNSection(descriptor,reg.xn_t); + MMU_DomainSection(descriptor, reg.domain); + MMU_PSection(descriptor, reg.e_t); + MMU_APSection(descriptor, reg.user_t, reg.priv_t, 1); + MMU_SharedSection(descriptor,reg.sh_t); + MMU_GlobalSection(descriptor,reg.g_t); + MMU_SecureSection(descriptor,reg.sec_t); + *descriptor &= SECTION_MASK; + *descriptor |= SECTION_DESCRIPTOR; + + return 0; +} + + +/** \brief Create a L1 and L2 4k/64k page descriptor + + \param [out] descriptor L1 descriptor + \param [out] descriptor2 L2 descriptor + \param [in] reg 4k/64k page attributes + + \return 0 +*/ +__STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg) +{ + *descriptor = 0; + *descriptor2 = 0; + + switch (reg.rg_t) + { + case PAGE_4k: + MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k); + MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k); + MMU_DomainPage(descriptor, reg.domain); + MMU_PPage(descriptor, reg.e_t); + MMU_APPage(descriptor2, reg.user_t, reg.priv_t, 1); + MMU_SharedPage(descriptor2,reg.sh_t); + MMU_GlobalPage(descriptor2,reg.g_t); + MMU_SecurePage(descriptor,reg.sec_t); + *descriptor &= PAGE_L1_MASK; + *descriptor |= PAGE_L1_DESCRIPTOR; + *descriptor2 &= PAGE_L2_4K_MASK; + *descriptor2 |= PAGE_L2_4K_DESC; + break; + + case PAGE_64k: + MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k); + MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k); + MMU_DomainPage(descriptor, reg.domain); + MMU_PPage(descriptor, reg.e_t); + MMU_APPage(descriptor2, reg.user_t, reg.priv_t, 1); + MMU_SharedPage(descriptor2,reg.sh_t); + MMU_GlobalPage(descriptor2,reg.g_t); + MMU_SecurePage(descriptor,reg.sec_t); + *descriptor &= PAGE_L1_MASK; + *descriptor |= PAGE_L1_DESCRIPTOR; + *descriptor2 &= PAGE_L2_64K_MASK; + *descriptor2 |= PAGE_L2_64K_DESC; + break; + + case SECTION: + //error + break; + } + + return 0; +} + +/** \brief Create a 1MB Section + + \param [in] ttb Translation table base address + \param [in] base_address Section base address + \param [in] count Number of sections to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + +*/ +__STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1) +{ + uint32_t offset; + uint32_t entry; + uint32_t i; + + offset = base_address >> 20; + entry = (base_address & 0xFFF00000) | descriptor_l1; + + //4 bytes aligned + ttb = ttb + offset; + + for (i = 0; i < count; i++ ) + { + //4 bytes aligned + *ttb++ = entry; + entry += OFFSET_1M; + } +} + +/** \brief Create a 4k page entry + + \param [in] ttb L1 table base address + \param [in] base_address 4k base address + \param [in] count Number of 4k pages to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + \param [in] ttb_l2 L2 table base address + \param [in] descriptor_l2 L2 descriptor (region attributes) + +*/ +__STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) +{ + + uint32_t offset, offset2; + uint32_t entry, entry2; + uint32_t i; + + offset = base_address >> 20; + entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1; + + //4 bytes aligned + ttb += offset; + //create l1_entry + *ttb = entry; + + offset2 = (base_address & 0xff000) >> 12; + ttb_l2 += offset2; + entry2 = (base_address & 0xFFFFF000) | descriptor_l2; + for (i = 0; i < count; i++ ) + { + //4 bytes aligned + *ttb_l2++ = entry2; + entry2 += OFFSET_4K; + } +} + +/** \brief Create a 64k page entry + + \param [in] ttb L1 table base address + \param [in] base_address 64k base address + \param [in] count Number of 64k pages to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + \param [in] ttb_l2 L2 table base address + \param [in] descriptor_l2 L2 descriptor (region attributes) + +*/ +__STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) +{ + uint32_t offset, offset2; + uint32_t entry, entry2; + uint32_t i,j; + + + offset = base_address >> 20; + entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1; + + //4 bytes aligned + ttb += offset; + //create l1_entry + *ttb = entry; + + offset2 = (base_address & 0xff000) >> 12; + ttb_l2 += offset2; + entry2 = (base_address & 0xFFFF0000) | descriptor_l2; + for (i = 0; i < count; i++ ) + { + //create 16 entries + for (j = 0; j < 16; j++) + { + //4 bytes aligned + *ttb_l2++ = entry2; + } + entry2 += OFFSET_64K; + } +} + +/** \brief Enable MMU +*/ +__STATIC_INLINE void MMU_Enable(void) +{ + // Set M bit 0 to enable the MMU + // Set AFE bit to enable simplified access permissions model + // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking + __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29)); + __ISB(); +} + +/** \brief Disable MMU +*/ +__STATIC_INLINE void MMU_Disable(void) +{ + // Clear M bit 0 to disable the MMU + __set_SCTLR( __get_SCTLR() & ~1); + __ISB(); +} + +/** \brief Invalidate entire unified TLB +*/ + +__STATIC_INLINE void MMU_InvalidateTLB(void) +{ + __set_TLBIALL(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new state +} + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0.h new file mode 100644 index 00000000000..eeb599fc77f --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0.h @@ -0,0 +1,967 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M0 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/* NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0plus.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0plus.h new file mode 100644 index 00000000000..1ee9457560f --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0plus.h @@ -0,0 +1,1103 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/** \brief MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/* NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "m-profile/armv7m_mpu.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm1.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm1.h new file mode 100644 index 00000000000..d41cf05b336 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm1.h @@ -0,0 +1,992 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M1 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/** \brief SCnSCB Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm23.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm23.h new file mode 100644 index 00000000000..d6337a4848b --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm23.h @@ -0,0 +1,2253 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M23 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM23 definitions */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED14[992U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ +#define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU Periodic Synchronization Control Register Definitions */ +#define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */ +#define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */ +#define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */ +#define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */ +#define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */ +#define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */ + +#define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */ +#define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 0 Definitions */ +#define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ +#define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ +#define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ +#define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ + +#define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ +#define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */ +#define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/** \brief MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */ + +/** \brief MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/** \brief MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/** \brief SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/** \brief SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/** \brief SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/** \brief SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/** \brief SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/** \brief DCB Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/** \brief DCB Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/** \brief DIB SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/** \brief DIB SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/** \brief DIB Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/** \brief DIB SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/** \brief DIB SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; + __IOM uint32_t DSCSR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos DCB_DHCSR_S_RESTART_ST_Pos +#define CoreDebug_DHCSR_S_RESTART_ST_Msk DCB_DHCSR_S_RESTART_ST_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_DWTENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_DWTENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos DCB_DAUTHCTRL_INTSPNIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk DCB_DAUTHCTRL_INTSPNIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos DCB_DAUTHCTRL_SPNIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk DCB_DAUTHCTRL_SPNIDENSEL_Msk + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos DCB_DAUTHCTRL_INTSPIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk DCB_DAUTHCTRL_INTSPIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos DCB_DAUTHCTRL_SPIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk DCB_DAUTHCTRL_SPIDENSEL_Msk + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos DCB_DSCSR_CDS_Pos +#define CoreDebug_DSCSR_CDS_Msk DCB_DSCSR_CDS_Msk + +#define CoreDebug_DSCSR_SBRSEL_Pos DCB_DSCSR_SBRSEL_Pos +#define CoreDebug_DSCSR_SBRSEL_Msk DCB_DSCSR_SBRSEL_Msk + +#define CoreDebug_DSCSR_SBRSELEN_Pos DCB_DSCSR_SBRSELEN_Pos +#define CoreDebug_DSCSR_SBRSELEN_Msk DCB_DSCSR_SBRSELEN_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS) +#endif + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/* NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/* NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + + #include "m-profile/armv8m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm3.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm3.h new file mode 100644 index 00000000000..624b9f69b02 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm3.h @@ -0,0 +1,2045 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M3 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IPR[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/** \brief SCnSCB Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/** \brief SCnSCB Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Lock Status Register */ +} ITM_Type; + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Lock Status Register Definitions */ +#define ITM_LSR_BYTEACC_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_BYTEACC_Msk (1UL << ITM_LSR_BYTEACC_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_ACCESS_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_ACCESS_Msk (1UL << ITM_LSR_ACCESS_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_PRESENT_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_PRESENT_Msk (1UL /*<< ITM_LSR_PRESENT_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration ETM Data Register Definitions (FIFO0) */ +#define TPIU_FIFO0_ITM_ATVALID_Pos 29U /*!< TPIU FIFO0: ITM_ATVALID Position */ +#define TPIU_FIFO0_ITM_ATVALID_Msk (1UL << TPIU_FIFO0_ITM_ATVALID_Pos) /*!< TPIU FIFO0: ITM_ATVALID Mask */ + +#define TPIU_FIFO0_ITM_bytecount_Pos 27U /*!< TPIU FIFO0: ITM_bytecount Position */ +#define TPIU_FIFO0_ITM_bytecount_Msk (0x3UL << TPIU_FIFO0_ITM_bytecount_Pos) /*!< TPIU FIFO0: ITM_bytecount Mask */ + +#define TPIU_FIFO0_ETM_ATVALID_Pos 26U /*!< TPIU FIFO0: ETM_ATVALID Position */ +#define TPIU_FIFO0_ETM_ATVALID_Msk (1UL << TPIU_FIFO0_ETM_ATVALID_Pos) /*!< TPIU FIFO0: ETM_ATVALID Mask */ + +#define TPIU_FIFO0_ETM_bytecount_Pos 24U /*!< TPIU FIFO0: ETM_bytecount Position */ +#define TPIU_FIFO0_ETM_bytecount_Msk (0x3UL << TPIU_FIFO0_ETM_bytecount_Pos) /*!< TPIU FIFO0: ETM_bytecount Mask */ + +#define TPIU_FIFO0_ETM2_Pos 16U /*!< TPIU FIFO0: ETM2 Position */ +#define TPIU_FIFO0_ETM2_Msk (0xFFUL << TPIU_FIFO0_ETM2_Pos) /*!< TPIU FIFO0: ETM2 Mask */ + +#define TPIU_FIFO0_ETM1_Pos 8U /*!< TPIU FIFO0: ETM1 Position */ +#define TPIU_FIFO0_ETM1_Msk (0xFFUL << TPIU_FIFO0_ETM1_Pos) /*!< TPIU FIFO0: ETM1 Mask */ + +#define TPIU_FIFO0_ETM0_Pos 0U /*!< TPIU FIFO0: ETM0 Position */ +#define TPIU_FIFO0_ETM0_Msk (0xFFUL /*<< TPIU_FIFO0_ETM0_Pos*/) /*!< TPIU FIFO0: ETM0 Mask */ + +/** \brief TPIU ITATBCTR2 Register Definitions */ +#define TPIU_ITATBCTR2_ATREADY2_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2 Position */ +#define TPIU_ITATBCTR2_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2 Mask */ + +#define TPIU_ITATBCTR2_ATREADY1_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1 Position */ +#define TPIU_ITATBCTR2_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1 Mask */ + +/** \brief TPIU Integration ITM Data Register Definitions (FIFO1) */ +#define TPIU_FIFO1_ITM_ATVALID_Pos 29U /*!< TPIU FIFO1: ITM_ATVALID Position */ +#define TPIU_FIFO1_ITM_ATVALID_Msk (1UL << TPIU_FIFO1_ITM_ATVALID_Pos) /*!< TPIU FIFO1: ITM_ATVALID Mask */ + +#define TPIU_FIFO1_ITM_bytecount_Pos 27U /*!< TPIU FIFO1: ITM_bytecount Position */ +#define TPIU_FIFO1_ITM_bytecount_Msk (0x3UL << TPIU_FIFO1_ITM_bytecount_Pos) /*!< TPIU FIFO1: ITM_bytecount Mask */ + +#define TPIU_FIFO1_ETM_ATVALID_Pos 26U /*!< TPIU FIFO1: ETM_ATVALID Position */ +#define TPIU_FIFO1_ETM_ATVALID_Msk (1UL << TPIU_FIFO1_ETM_ATVALID_Pos) /*!< TPIU FIFO1: ETM_ATVALID Mask */ + +#define TPIU_FIFO1_ETM_bytecount_Pos 24U /*!< TPIU FIFO1: ETM_bytecount Position */ +#define TPIU_FIFO1_ETM_bytecount_Msk (0x3UL << TPIU_FIFO1_ETM_bytecount_Pos) /*!< TPIU FIFO1: ETM_bytecount Mask */ + +#define TPIU_FIFO1_ITM2_Pos 16U /*!< TPIU FIFO1: ITM2 Position */ +#define TPIU_FIFO1_ITM2_Msk (0xFFUL << TPIU_FIFO1_ITM2_Pos) /*!< TPIU FIFO1: ITM2 Mask */ + +#define TPIU_FIFO1_ITM1_Pos 8U /*!< TPIU FIFO1: ITM1 Position */ +#define TPIU_FIFO1_ITM1_Msk (0xFFUL << TPIU_FIFO1_ITM1_Pos) /*!< TPIU FIFO1: ITM1 Mask */ + +#define TPIU_FIFO1_ITM0_Pos 0U /*!< TPIU FIFO1: ITM0 Position */ +#define TPIU_FIFO1_ITM0_Msk (0xFFUL /*<< TPIU_FIFO1_ITM0_Pos*/) /*!< TPIU FIFO1: ITM0 Mask */ + +/** \brief TPIU ITATBCTR0 Register Definitions */ +#define TPIU_ITATBCTR0_ATREADY2_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2 Position */ +#define TPIU_ITATBCTR0_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2 Mask */ + +#define TPIU_ITATBCTR0_ATREADY1_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1 Position */ +#define TPIU_ITATBCTR0_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1 Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_MinBufSz_Pos 6U /*!< TPIU DEVID: MinBufSz Position */ +#define TPIU_DEVID_MinBufSz_Msk (0x7UL << TPIU_DEVID_MinBufSz_Pos) /*!< TPIU DEVID: MinBufSz Mask */ + +#define TPIU_DEVID_AsynClkIn_Pos 5U /*!< TPIU DEVID: AsynClkIn Position */ +#define TPIU_DEVID_AsynClkIn_Msk (1UL << TPIU_DEVID_AsynClkIn_Pos) /*!< TPIU DEVID: AsynClkIn Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/** \brief MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ +#define DCB_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ +#define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos +#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk + +#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos +#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk + +#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos +#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk + +#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos +#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos +#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk + +#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos +#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk + +#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos +#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk + +#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos +#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos +#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk + +#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos +#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "m-profile/armv7m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm33.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm33.h new file mode 100644 index 00000000000..5f7d9b1575c --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm33.h @@ -0,0 +1,3245 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M33 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/** \brief SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/** \brief SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/** \brief SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/** \brief SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/** \brief SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/** \brief SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/** \brief SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/** \brief SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/** \brief SCnSCB Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[27U]; + __IM uint32_t ITREAD; /*!< Offset: 0xEF0 (R/ ) Integration Read Register */ + uint32_t RESERVED4[1U]; + __OM uint32_t ITWRITE; /*!< Offset: 0xEF8 ( /W) Integration Write Register */ + uint32_t RESERVED5[1U]; + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control Register */ + uint32_t RESERVED6[46U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ + uint32_t RESERVED7[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} ITM_Type; + +/** \brief ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Integration Read Register Definitions */ +#define ITM_ITREAD_AFVALID_Pos 1U /*!< ITM ITREAD: AFVALID Position */ +#define ITM_ITREAD_AFVALID_Msk (1UL << ITM_ITREAD_AFVALID_Pos) /*!< ITM ITREAD: AFVALID Mask */ + +#define ITM_ITREAD_ATREADY_Pos 0U /*!< ITM ITREAD: ATREADY Position */ +#define ITM_ITREAD_ATREADY_Msk (1UL /*<< ITM_ITREAD_ATREADY_Pos*/) /*!< ITM ITREAD: ATREADY Mask */ + +/** \brief ITM Integration Write Register Definitions */ +#define ITM_ITWRITE_AFVALID_Pos 1U /*!< ITM ITWRITE: AFVALID Position */ +#define ITM_ITWRITE_AFVALID_Msk (1UL << ITM_ITWRITE_AFVALID_Pos) /*!< ITM ITWRITE: AFVALID Mask */ + +#define ITM_ITWRITE_ATREADY_Pos 0U /*!< ITM ITWRITE: ATREADY Position */ +#define ITM_ITWRITE_ATREADY_Msk (1UL /*<< ITM_ITWRITE_ATREADY_Pos*/) /*!< ITM ITWRITE: ATREADY Mask */ + +/** \brief ITM Integration Mode Control Register Definitions */ +#define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ +#define ITM_ITCTRL_IME_Msk (1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED14[984U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ + uint32_t RESERVED15[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ +#define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU Periodic Synchronization Control Register Definitions */ +#define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */ +#define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */ +#define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */ +#define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */ +#define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */ +#define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */ + +#define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */ +#define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 0 Definitions */ +#define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ +#define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ +#define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ +#define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ + +#define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ +#define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */ +#define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/** \brief MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */ + +/** \brief MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/** \brief MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/** \brief SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/** \brief SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/** \brief SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/** \brief SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/** \brief SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/** \brief SAU Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/** \brief FPU Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/** \brief FPU Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/** \brief FPU Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/** \brief FPU Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ + +#define FPU_MVFR0_FPShortvec_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_FPShortvec_Msk (0xFUL << FPU_MVFR0_FPShortvec_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPExceptrap_Pos 12U /*!< MVFR0: Exception trapping bits Position */ +#define FPU_MVFR0_FPExceptrap_Msk (0xFUL << FPU_MVFR0_FPExceptrap_Pos) /*!< MVFR0: Exception trapping bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ + +/** \brief FPU Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/** \brief FPU Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/** \brief DCB Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/** \brief DCB Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/** \brief DIB SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/** \brief DIB SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/** \brief DIB Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/** \brief DIB SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/** \brief DIB SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; + __IOM uint32_t DSCSR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos DCB_DHCSR_S_RESTART_ST_Pos +#define CoreDebug_DHCSR_S_RESTART_ST_Msk DCB_DHCSR_S_RESTART_ST_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos +#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk + +#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos +#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk + +#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos +#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk + +#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos +#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos +#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk + +#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos +#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk + +#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos +#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk + +#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos +#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos +#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk + +#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos +#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos DCB_DAUTHCTRL_INTSPNIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk DCB_DAUTHCTRL_INTSPNIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos DCB_DAUTHCTRL_SPNIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk DCB_DAUTHCTRL_SPNIDENSEL_Msk + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos DCB_DAUTHCTRL_INTSPIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk DCB_DAUTHCTRL_INTSPIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos DCB_DAUTHCTRL_SPIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk DCB_DAUTHCTRL_SPIDENSEL_Msk + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos DCB_DSCSR_CDS_Pos +#define CoreDebug_DSCSR_CDS_Msk DCB_DSCSR_CDS_Msk + +#define CoreDebug_DSCSR_SBRSEL_Pos DCB_DSCSR_SBRSEL_Pos +#define CoreDebug_DSCSR_SBRSEL_Msk DCB_DSCSR_SBRSEL_Msk + +#define CoreDebug_DSCSR_SBRSELEN_Pos DCB_DSCSR_SBRSELEN_Pos +#define CoreDebug_DSCSR_SBRSELEN_Msk DCB_DSCSR_SBRSELEN_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS) +#endif + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + + #include "m-profile/armv8m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm35p.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm35p.h new file mode 100644 index 00000000000..def2589fadb --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm35p.h @@ -0,0 +1,3245 @@ +/* + * Copyright (c) 2018-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M35P Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35 definitions */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/** \brief SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/** \brief SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/** \brief SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/** \brief SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/** \brief SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/** \brief SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/** \brief SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/** \brief SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/** \brief SCnSCB Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[27U]; + __IM uint32_t ITREAD; /*!< Offset: 0xEF0 (R/ ) Integration Read Register */ + uint32_t RESERVED4[1U]; + __OM uint32_t ITWRITE; /*!< Offset: 0xEF8 ( /W) Integration Write Register */ + uint32_t RESERVED5[1U]; + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control Register */ + uint32_t RESERVED6[46U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ + uint32_t RESERVED7[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} ITM_Type; + +/** \brief ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Integration Read Register Definitions */ +#define ITM_ITREAD_AFVALID_Pos 1U /*!< ITM ITREAD: AFVALID Position */ +#define ITM_ITREAD_AFVALID_Msk (1UL << ITM_ITREAD_AFVALID_Pos) /*!< ITM ITREAD: AFVALID Mask */ + +#define ITM_ITREAD_ATREADY_Pos 0U /*!< ITM ITREAD: ATREADY Position */ +#define ITM_ITREAD_ATREADY_Msk (1UL /*<< ITM_ITREAD_ATREADY_Pos*/) /*!< ITM ITREAD: ATREADY Mask */ + +/** \brief ITM Integration Write Register Definitions */ +#define ITM_ITWRITE_AFVALID_Pos 1U /*!< ITM ITWRITE: AFVALID Position */ +#define ITM_ITWRITE_AFVALID_Msk (1UL << ITM_ITWRITE_AFVALID_Pos) /*!< ITM ITWRITE: AFVALID Mask */ + +#define ITM_ITWRITE_ATREADY_Pos 0U /*!< ITM ITWRITE: ATREADY Position */ +#define ITM_ITWRITE_ATREADY_Msk (1UL /*<< ITM_ITWRITE_ATREADY_Pos*/) /*!< ITM ITWRITE: ATREADY Mask */ + +/** \brief ITM Integration Mode Control Register Definitions */ +#define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ +#define ITM_ITCTRL_IME_Msk (1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED14[984U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ + uint32_t RESERVED15[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ +#define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU Periodic Synchronization Control Register Definitions */ +#define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */ +#define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */ +#define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */ +#define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */ +#define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */ +#define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */ + +#define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */ +#define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 0 Definitions */ +#define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ +#define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ +#define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ +#define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ + +#define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ +#define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */ +#define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/** \brief MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */ + +/** \brief MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/** \brief MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/** \brief SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/** \brief SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/** \brief SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/** \brief SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/** \brief SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/** \brief SAU Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/** \brief FPU Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/** \brief FPU Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/** \brief FPU Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/** \brief FPU Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ + +#define FPU_MVFR0_FPShortvec_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_FPShortvec_Msk (0xFUL << FPU_MVFR0_FPShortvec_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPExceptrap_Pos 12U /*!< MVFR0: Exception trapping bits Position */ +#define FPU_MVFR0_FPExceptrap_Msk (0xFUL << FPU_MVFR0_FPExceptrap_Pos) /*!< MVFR0: Exception trapping bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ + +/** \brief FPU Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/** \brief FPU Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/** \brief DCB Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/** \brief DCB Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/** \brief DIB SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/** \brief DIB SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/** \brief DIB Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/** \brief DIB SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/** \brief DIB SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; + __IOM uint32_t DSCSR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos DCB_DHCSR_S_RESTART_ST_Pos +#define CoreDebug_DHCSR_S_RESTART_ST_Msk DCB_DHCSR_S_RESTART_ST_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos +#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk + +#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos +#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk + +#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos +#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk + +#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos +#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos +#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk + +#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos +#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk + +#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos +#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk + +#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos +#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos +#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk + +#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos +#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos DCB_DAUTHCTRL_INTSPNIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk DCB_DAUTHCTRL_INTSPNIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos DCB_DAUTHCTRL_SPNIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk DCB_DAUTHCTRL_SPNIDENSEL_Msk + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos DCB_DAUTHCTRL_INTSPIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk DCB_DAUTHCTRL_INTSPIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos DCB_DAUTHCTRL_SPIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk DCB_DAUTHCTRL_SPIDENSEL_Msk + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos DCB_DSCSR_CDS_Pos +#define CoreDebug_DSCSR_CDS_Msk DCB_DSCSR_CDS_Msk + +#define CoreDebug_DSCSR_SBRSEL_Pos DCB_DSCSR_SBRSEL_Pos +#define CoreDebug_DSCSR_SBRSEL_Msk DCB_DSCSR_SBRSEL_Msk + +#define CoreDebug_DSCSR_SBRSELEN_Pos DCB_DSCSR_SBRSELEN_Pos +#define CoreDebug_DSCSR_SBRSELEN_Msk DCB_DSCSR_SBRSELEN_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS) +#endif + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + + #include "m-profile/armv8m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm4.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm4.h new file mode 100644 index 00000000000..8354ccfbcff --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm4.h @@ -0,0 +1,2237 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M4 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IPR[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/** \brief SCnSCB Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/** \brief SCnSCB Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Lock Status Register */ +} ITM_Type; + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Lock Status Register Definitions */ +#define ITM_LSR_BYTEACC_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_BYTEACC_Msk (1UL << ITM_LSR_BYTEACC_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_ACCESS_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_ACCESS_Msk (1UL << ITM_LSR_ACCESS_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_PRESENT_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_PRESENT_Msk (1UL /*<< ITM_LSR_PRESENT_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration ETM Data Register Definitions (FIFO0) */ +#define TPIU_FIFO0_ITM_ATVALID_Pos 29U /*!< TPIU FIFO0: ITM_ATVALID Position */ +#define TPIU_FIFO0_ITM_ATVALID_Msk (1UL << TPIU_FIFO0_ITM_ATVALID_Pos) /*!< TPIU FIFO0: ITM_ATVALID Mask */ + +#define TPIU_FIFO0_ITM_bytecount_Pos 27U /*!< TPIU FIFO0: ITM_bytecount Position */ +#define TPIU_FIFO0_ITM_bytecount_Msk (0x3UL << TPIU_FIFO0_ITM_bytecount_Pos) /*!< TPIU FIFO0: ITM_bytecount Mask */ + +#define TPIU_FIFO0_ETM_ATVALID_Pos 26U /*!< TPIU FIFO0: ETM_ATVALID Position */ +#define TPIU_FIFO0_ETM_ATVALID_Msk (1UL << TPIU_FIFO0_ETM_ATVALID_Pos) /*!< TPIU FIFO0: ETM_ATVALID Mask */ + +#define TPIU_FIFO0_ETM_bytecount_Pos 24U /*!< TPIU FIFO0: ETM_bytecount Position */ +#define TPIU_FIFO0_ETM_bytecount_Msk (0x3UL << TPIU_FIFO0_ETM_bytecount_Pos) /*!< TPIU FIFO0: ETM_bytecount Mask */ + +#define TPIU_FIFO0_ETM2_Pos 16U /*!< TPIU FIFO0: ETM2 Position */ +#define TPIU_FIFO0_ETM2_Msk (0xFFUL << TPIU_FIFO0_ETM2_Pos) /*!< TPIU FIFO0: ETM2 Mask */ + +#define TPIU_FIFO0_ETM1_Pos 8U /*!< TPIU FIFO0: ETM1 Position */ +#define TPIU_FIFO0_ETM1_Msk (0xFFUL << TPIU_FIFO0_ETM1_Pos) /*!< TPIU FIFO0: ETM1 Mask */ + +#define TPIU_FIFO0_ETM0_Pos 0U /*!< TPIU FIFO0: ETM0 Position */ +#define TPIU_FIFO0_ETM0_Msk (0xFFUL /*<< TPIU_FIFO0_ETM0_Pos*/) /*!< TPIU FIFO0: ETM0 Mask */ + +/** \brief TPIU ITATBCTR2 Register Definitions */ +#define TPIU_ITATBCTR2_ATREADY2_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2 Position */ +#define TPIU_ITATBCTR2_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2 Mask */ + +#define TPIU_ITATBCTR2_ATREADY1_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1 Position */ +#define TPIU_ITATBCTR2_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1 Mask */ + +/** \brief TPIU Integration ITM Data Register Definitions (FIFO1) */ +#define TPIU_FIFO1_ITM_ATVALID_Pos 29U /*!< TPIU FIFO1: ITM_ATVALID Position */ +#define TPIU_FIFO1_ITM_ATVALID_Msk (1UL << TPIU_FIFO1_ITM_ATVALID_Pos) /*!< TPIU FIFO1: ITM_ATVALID Mask */ + +#define TPIU_FIFO1_ITM_bytecount_Pos 27U /*!< TPIU FIFO1: ITM_bytecount Position */ +#define TPIU_FIFO1_ITM_bytecount_Msk (0x3UL << TPIU_FIFO1_ITM_bytecount_Pos) /*!< TPIU FIFO1: ITM_bytecount Mask */ + +#define TPIU_FIFO1_ETM_ATVALID_Pos 26U /*!< TPIU FIFO1: ETM_ATVALID Position */ +#define TPIU_FIFO1_ETM_ATVALID_Msk (1UL << TPIU_FIFO1_ETM_ATVALID_Pos) /*!< TPIU FIFO1: ETM_ATVALID Mask */ + +#define TPIU_FIFO1_ETM_bytecount_Pos 24U /*!< TPIU FIFO1: ETM_bytecount Position */ +#define TPIU_FIFO1_ETM_bytecount_Msk (0x3UL << TPIU_FIFO1_ETM_bytecount_Pos) /*!< TPIU FIFO1: ETM_bytecount Mask */ + +#define TPIU_FIFO1_ITM2_Pos 16U /*!< TPIU FIFO1: ITM2 Position */ +#define TPIU_FIFO1_ITM2_Msk (0xFFUL << TPIU_FIFO1_ITM2_Pos) /*!< TPIU FIFO1: ITM2 Mask */ + +#define TPIU_FIFO1_ITM1_Pos 8U /*!< TPIU FIFO1: ITM1 Position */ +#define TPIU_FIFO1_ITM1_Msk (0xFFUL << TPIU_FIFO1_ITM1_Pos) /*!< TPIU FIFO1: ITM1 Mask */ + +#define TPIU_FIFO1_ITM0_Pos 0U /*!< TPIU FIFO1: ITM0 Position */ +#define TPIU_FIFO1_ITM0_Msk (0xFFUL /*<< TPIU_FIFO1_ITM0_Pos*/) /*!< TPIU FIFO1: ITM0 Mask */ + +/** \brief TPIU ITATBCTR0 Register Definitions */ +#define TPIU_ITATBCTR0_ATREADY2_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2 Position */ +#define TPIU_ITATBCTR0_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2 Mask */ + +#define TPIU_ITATBCTR0_ATREADY1_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1 Position */ +#define TPIU_ITATBCTR0_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1 Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_MinBufSz_Pos 6U /*!< TPIU DEVID: MinBufSz Position */ +#define TPIU_DEVID_MinBufSz_Msk (0x7UL << TPIU_DEVID_MinBufSz_Pos) /*!< TPIU DEVID: MinBufSz Mask */ + +#define TPIU_DEVID_AsynClkIn_Pos 5U /*!< TPIU DEVID: AsynClkIn Position */ +#define TPIU_DEVID_AsynClkIn_Msk (1UL << TPIU_DEVID_AsynClkIn_Pos) /*!< TPIU DEVID: AsynClkIn Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/** \brief MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/** \brief FPU Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/** \brief FPU Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/** \brief FPU Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/** \brief FPU Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ + +#define FPU_MVFR0_FPShortvec_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_FPShortvec_Msk (0xFUL << FPU_MVFR0_FPShortvec_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPExceptrap_Pos 12U /*!< MVFR0: Exception trapping bits Position */ +#define FPU_MVFR0_FPExceptrap_Msk (0xFUL << FPU_MVFR0_FPExceptrap_Pos) /*!< MVFR0: Exception trapping bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ + +/** \brief FPU Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/** \brief FPU Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ +#define DCB_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ +#define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos +#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk + +#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos +#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk + +#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos +#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk + +#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos +#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos +#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk + +#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos +#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk + +#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos +#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk + +#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos +#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos +#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk + +#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos +#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "m-profile/armv7m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm52.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm52.h new file mode 100644 index 00000000000..a6195940426 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm52.h @@ -0,0 +1,4783 @@ +/* + * Copyright (c) 2018-2024 Arm Limited. Copyright (c) 2024 Arm Technology (China) Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M52 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM52_H_GENERIC +#define __CORE_CM52_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M52 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM52 definitions */ + +#define __CORTEX_M (52U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM52_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM52_H_DEPENDANT +#define __CORE_CM52_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM52_REV + #define __CM52_REV 0x0002U + #warning "__CM52_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __UCACHE_PRESENT + #define __UCACHE_PRESENT 0U + #warning "__UCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M52 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core EWIC Interrupt Status Access Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:1; /*!< bit: 20 Reserved */ + uint32_t B:1; /*!< bit: 21 BTI active (read 0) */ + uint32_t _reserved2:2; /*!< bit: 22..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_B_Pos 21U /*!< xPSR: B Position */ +#define xPSR_B_Msk (1UL << xPSR_B_Pos) /*!< xPSR: B Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t BTI_EN:1; /*!< bit: 4 Privileged branch target identification enable */ + uint32_t UBTI_EN:1; /*!< bit: 5 Unprivileged branch target identification enable */ + uint32_t PAC_EN:1; /*!< bit: 6 Privileged pointer authentication enable */ + uint32_t UPAC_EN:1; /*!< bit: 7 Unprivileged pointer authentication enable */ + uint32_t _reserved1:24; /*!< bit: 8..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_UPAC_EN_Pos 7U /*!< CONTROL: UPAC_EN Position */ +#define CONTROL_UPAC_EN_Msk (1UL << CONTROL_UPAC_EN_Pos) /*!< CONTROL: UPAC_EN Mask */ + +#define CONTROL_PAC_EN_Pos 6U /*!< CONTROL: PAC_EN Position */ +#define CONTROL_PAC_EN_Msk (1UL << CONTROL_PAC_EN_Pos) /*!< CONTROL: PAC_EN Mask */ + +#define CONTROL_UBTI_EN_Pos 5U /*!< CONTROL: UBTI_EN Position */ +#define CONTROL_UBTI_EN_Msk (1UL << CONTROL_UBTI_EN_Pos) /*!< CONTROL: UBTI_EN Mask */ + +#define CONTROL_BTI_EN_Pos 4U /*!< CONTROL: BTI_EN Position */ +#define CONTROL_BTI_EN_Msk (1UL << CONTROL_BTI_EN_Pos) /*!< CONTROL: BTI_EN Mask */ + +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED0[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED1[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED2[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED3[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED4[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/** \brief SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/** \brief SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/** \brief SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +#define SCB_CLIDR_CTYPE1_Pos 0U +#define SCB_CLIDR_CTYPE1_Msk (7UL << SCB_CLIDR_CTYPE1_Pos) + +/** \brief SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/** \brief SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/** \brief SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/** \brief SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/** \brief SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/** \brief SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/** \brief SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + + +/** \brief SCB U-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_UC_WAY_Pos 31U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_UC_WAY_Msk (1UL << SCB_DCISW_UC_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_UC_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_UC_SET_Msk (0x3FFUL << SCB_DCISW_UC_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/** \brief SCB U-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_UC_WAY_Pos 31U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_UC_WAY_Msk (1UL << SCB_DCCSW_UC_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_UC_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_UC_SET_Msk (0x3FFUL << SCB_DCCSW_UC_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/** \brief SCB U-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_UC_WAY_Pos 31U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_UC_WAY_Msk (1UL << SCB_DCCISW_UC_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_UC_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_UC_SET_Msk (0x3FFUL << SCB_DCCISW_UC_SET_Pos) /*!< SCB DCCISW: Set Mask */ + + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/** \brief ICB Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define ICB_ACTLR_DISDI_Msk (3UL << ICB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define ICB_ACTLR_DISOLAP_Pos 7U /*!< ACTLR: DISOLAP Position */ +#define ICB_ACTLR_DISOLAP_Msk (1UL << ICB_ACTLR_DISOLAP_Pos) /*!< ACTLR: DISOLAP Mask */ + +#define ICB_ACTLR_DISOLAPS_Pos 6U /*!< ACTLR: DISOLAPS Position */ +#define ICB_ACTLR_DISOLAPS_Msk (1UL << ICB_ACTLR_DISOLAPS_Pos) /*!< ACTLR: DISOLAPS Mask */ + +#define ICB_ACTLR_DISLOBR_Pos 5U /*!< ACTLR: DISLOBR Position */ +#define ICB_ACTLR_DISLOBR_Msk (1UL << ICB_ACTLR_DISLOBR_Pos) /*!< ACTLR: DISLOBR Mask */ + +#define ICB_ACTLR_DISLO_Pos 4U /*!< ACTLR: DISLO Position */ +#define ICB_ACTLR_DISLO_Msk (1UL << ICB_ACTLR_DISLO_Pos) /*!< ACTLR: DISLO Mask */ + +#define ICB_ACTLR_DISLOLEP_Pos 3U /*!< ACTLR: DISLOLEP Position */ +#define ICB_ACTLR_DISLOLEP_Msk (1UL << ICB_ACTLR_DISLOLEP_Pos) /*!< ACTLR: DISLOLEP Mask */ + +#define ICB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define ICB_ACTLR_DISFOLD_Msk (1UL << ICB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +/** \brief ICB Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[27U]; + __IM uint32_t ITREAD; /*!< Offset: 0xEF0 (R/ ) Integration Read Register */ + uint32_t RESERVED4[1U]; + __OM uint32_t ITWRITE; /*!< Offset: 0xEF8 ( /W) Integration Write Register */ + uint32_t RESERVED5[1U]; + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control Register */ + uint32_t RESERVED6[46U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ + uint32_t RESERVED7[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} ITM_Type; + +/** \brief ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Integration Read Register Definitions */ +#define ITM_ITREAD_AFVALID_Pos 1U /*!< ITM ITREAD: AFVALID Position */ +#define ITM_ITREAD_AFVALID_Msk (1UL << ITM_ITREAD_AFVALID_Pos) /*!< ITM ITREAD: AFVALID Mask */ + +#define ITM_ITREAD_ATREADY_Pos 0U /*!< ITM ITREAD: ATREADY Position */ +#define ITM_ITREAD_ATREADY_Msk (1UL /*<< ITM_ITREAD_ATREADY_Pos*/) /*!< ITM ITREAD: ATREADY Mask */ + +/** \brief ITM Integration Write Register Definitions */ +#define ITM_ITWRITE_AFVALID_Pos 1U /*!< ITM ITWRITE: AFVALID Position */ +#define ITM_ITWRITE_AFVALID_Msk (1UL << ITM_ITWRITE_AFVALID_Pos) /*!< ITM ITWRITE: AFVALID Mask */ + +#define ITM_ITWRITE_ATREADY_Pos 0U /*!< ITM ITWRITE: ATREADY Position */ +#define ITM_ITWRITE_ATREADY_Msk (1UL /*<< ITM_ITWRITE_ATREADY_Pos*/) /*!< ITM ITWRITE: ATREADY Mask */ + +/** \brief ITM Integration Mode Control Register Definitions */ +#define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ +#define ITM_ITCTRL_IME_Msk (1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + __IOM uint32_t VMASK1; /*!< Offset: 0x03C (R/W) Comparator Value Mask 1 */ + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + __IOM uint32_t VMASK3; /*!< Offset: 0x05C (R/W) Comparator Value Mask 3 */ + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED14[968U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ + uint32_t RESERVED15[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + uint32_t RESERVED1[3U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/** \brief MemSysCtl Memory System Control Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos 4U /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */ +#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk (1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos) /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/** \brief MemSysCtl ITCM Control Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/** \brief MemSysCtl DTCM Control Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/** \brief MemSysCtl P-AHB Control Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/** \brief MemSysCtl ITGU Control Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/** \brief MemSysCtl ITGU Configuration Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/** \brief MemSysCtl DTGU Control Registers Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/** \brief MemSysCtl DTGU Configuration Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup DCAR_Type Direct Cache Access Registers + \brief Type definitions for the Direct Cache Access Registers (DCAR) + @{ + */ + +/** + \brief Structure type to access the Direct Cache Access Registers (DCAR). + */ +typedef struct +{ + __IM uint32_t DCADCRR; /*!< Offset: 0x000 (R/W) Direct Cache Access Data Cache Read Register */ + __IM uint32_t DCAICRR; /*!< Offset: 0x004 (R/W) Direct Cache Access Instruction Cache Read Register */ + uint32_t RESERVED1[2]; + __IOM uint32_t DCADCLR; /*!< Offset: 0x010 (R/W) Direct Cache Access Data Cache Location Registers */ + __IOM uint32_t DCAICLR; /*!< Offset: 0x014 (R/W) Direct Cache Access Instruction Cache Location Registers */ +} DCAR_Type; + +/*@}*/ /* end of group DCAR_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/** \brief PwrModCtl Core Power Domain Low Power State Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/** \brief PwrModCtl Debug Power Domain Low Power State Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __IOM uint32_t EWIC_CR; /*!< Offset: 0x000 (R/W) EWIC Control Register */ + __IOM uint32_t EWIC_ASCR; /*!< Offset: 0x004 (R/W) EWIC Automatic Sequence Control Register */ + __OM uint32_t EWIC_CLRMASK; /*!< Offset: 0x008 ( /W) EWIC Clear Mask Register */ + __IM uint32_t EWIC_NUMID; /*!< Offset: 0x00C (R/ ) EWIC Event Number ID Register */ + uint32_t RESERVED0[124U]; + __IOM uint32_t EWIC_MASKA; /*!< Offset: 0x200 (R/W) EWIC MaskA Register */ + __IOM uint32_t EWIC_MASKn[15]; /*!< Offset: 0x204 (R/W) EWIC Maskn Registers */ + uint32_t RESERVED1[112U]; + __IM uint32_t EWIC_PENDA; /*!< Offset: 0x400 (R/ ) EWIC PendA Event Register */ + __IOM uint32_t EWIC_PENDn[15]; /*!< Offset: 0x404 (R/W) EWIC Pendn Event Registers */ + uint32_t RESERVED2[112U]; + __IM uint32_t EWIC_PSR; /*!< Offset: 0x600 (R/ ) EWIC Pend Summary Register */ +} EWIC_Type; + +/** \brief EWIC Control Register Definitions */ +#define EWIC_EWIC_CR_EN_Pos 0U /*!< EWIC EWIC_CR: EN Position */ +#define EWIC_EWIC_CR_EN_Msk (1UL /*<< EWIC_EWIC_CR_EN_Pos*/) /*!< EWIC EWIC_CR: EN Mask */ + +/** \brief EWIC Automatic Sequence Control Register Definitions */ +#define EWIC_EWIC_ASCR_ASPU_Pos 1U /*!< EWIC EWIC_ASCR: ASPU Position */ +#define EWIC_EWIC_ASCR_ASPU_Msk (1UL << EWIC_EWIC_ASCR_ASPU_Pos) /*!< EWIC EWIC_ASCR: ASPU Mask */ + +#define EWIC_EWIC_ASCR_ASPD_Pos 0U /*!< EWIC EWIC_ASCR: ASPD Position */ +#define EWIC_EWIC_ASCR_ASPD_Msk (1UL /*<< EWIC_EWIC_ASCR_ASPD_Pos*/) /*!< EWIC EWIC_ASCR: ASPD Mask */ + +/** \brief EWIC Event Number ID Register Definitions */ +#define EWIC_EWIC_NUMID_NUMEVENT_Pos 0U /*!< EWIC_NUMID: NUMEVENT Position */ +#define EWIC_EWIC_NUMID_NUMEVENT_Msk (0xFFFFUL /*<< EWIC_EWIC_NUMID_NUMEVENT_Pos*/) /*!< EWIC_NUMID: NUMEVENT Mask */ + +/** \brief EWIC Mask A Register Definitions */ +#define EWIC_EWIC_MASKA_EDBGREQ_Pos 2U /*!< EWIC EWIC_MASKA: EDBGREQ Position */ +#define EWIC_EWIC_MASKA_EDBGREQ_Msk (1UL << EWIC_EWIC_MASKA_EDBGREQ_Pos) /*!< EWIC EWIC_MASKA: EDBGREQ Mask */ + +#define EWIC_EWIC_MASKA_NMI_Pos 1U /*!< EWIC EWIC_MASKA: NMI Position */ +#define EWIC_EWIC_MASKA_NMI_Msk (1UL << EWIC_EWIC_MASKA_NMI_Pos) /*!< EWIC EWIC_MASKA: NMI Mask */ + +#define EWIC_EWIC_MASKA_EVENT_Pos 0U /*!< EWIC EWIC_MASKA: EVENT Position */ +#define EWIC_EWIC_MASKA_EVENT_Msk (1UL /*<< EWIC_EWIC_MASKA_EVENT_Pos*/) /*!< EWIC EWIC_MASKA: EVENT Mask */ + +/** \brief EWIC Mask n Register Definitions */ +#define EWIC_EWIC_MASKn_IRQ_Pos 0U /*!< EWIC EWIC_MASKn: IRQ Position */ +#define EWIC_EWIC_MASKn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EWIC_MASKn_IRQ_Pos*/) /*!< EWIC EWIC_MASKn: IRQ Mask */ + +/** \brief EWIC Pend A Register Definitions */ +#define EWIC_EWIC_PENDA_EDBGREQ_Pos 2U /*!< EWIC EWIC_PENDA: EDBGREQ Position */ +#define EWIC_EWIC_PENDA_EDBGREQ_Msk (1UL << EWIC_EWIC_PENDA_EDBGREQ_Pos) /*!< EWIC EWIC_PENDA: EDBGREQ Mask */ + +#define EWIC_EWIC_PENDA_NMI_Pos 1U /*!< EWIC EWIC_PENDA: NMI Position */ +#define EWIC_EWIC_PENDA_NMI_Msk (1UL << EWIC_EWIC_PENDA_NMI_Pos) /*!< EWIC EWIC_PENDA: NMI Mask */ + +#define EWIC_EWIC_PENDA_EVENT_Pos 0U /*!< EWIC EWIC_PENDA: EVENT Position */ +#define EWIC_EWIC_PENDA_EVENT_Msk (1UL /*<< EWIC_EWIC_PENDA_EVENT_Pos*/) /*!< EWIC EWIC_PENDA: EVENT Mask */ + +/** \brief EWIC Pend n Register Definitions */ +#define EWIC_EWIC_PENDn_IRQ_Pos 0U /*!< EWIC EWIC_PENDn: IRQ Position */ +#define EWIC_EWIC_PENDn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EWIC_PENDn_IRQ_Pos*/) /*!< EWIC EWIC_PENDn: IRQ Mask */ + +/** \brief EWIC Pend Summary Register Definitions */ +#define EWIC_EWIC_PSR_NZ_Pos 1U /*!< EWIC EWIC_PSR: NZ Position */ +#define EWIC_EWIC_PSR_NZ_Msk (0x7FFFUL << EWIC_EWIC_PSR_NZ_Pos) /*!< EWIC EWIC_PSR: NZ Mask */ + +#define EWIC_EWIC_PSR_NZA_Pos 0U /*!< EWIC EWIC_PSR: NZA Position */ +#define EWIC_EWIC_PSR_NZA_Msk (1UL /*<< EWIC_EWIC_PSR_NZA_Pos*/) /*!< EWIC EWIC_PSR: NZA Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_ISA_Type External Wakeup Interrupt Controller (EWIC) interrupt status access registers + \brief Type definitions for the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/ ) Event Mask A Register */ + __IM uint32_t EVENTMASKn[15]; /*!< Offset: 0x084 (R/ ) Event Mask Register */ +} EWIC_ISA_Type; + +/** \brief EWIC_ISA Event Set Pending Register Definitions */ +#define EWIC_ISA_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC_ISA EVENTSPR: EDBGREQ Position */ +#define EWIC_ISA_EVENTSPR_EDBGREQ_Msk (1UL << EWIC_ISA_EVENTSPR_EDBGREQ_Pos) /*!< EWIC_ISA EVENTSPR: EDBGREQ Mask */ + +#define EWIC_ISA_EVENTSPR_NMI_Pos 1U /*!< EWIC_ISA EVENTSPR: NMI Position */ +#define EWIC_ISA_EVENTSPR_NMI_Msk (1UL << EWIC_ISA_EVENTSPR_NMI_Pos) /*!< EWIC_ISA EVENTSPR: NMI Mask */ + +#define EWIC_ISA_EVENTSPR_EVENT_Pos 0U /*!< EWIC_ISA EVENTSPR: EVENT Position */ +#define EWIC_ISA_EVENTSPR_EVENT_Msk (1UL /*<< EWIC_ISA_EVENTSPR_EVENT_Pos*/) /*!< EWIC_ISA EVENTSPR: EVENT Mask */ + +/** \brief EWIC_ISA Event Mask A Register Definitions */ +#define EWIC_ISA_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC_ISA EVENTMASKA: EDBGREQ Position */ +#define EWIC_ISA_EVENTMASKA_EDBGREQ_Msk (1UL << EWIC_ISA_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC_ISA EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_ISA_EVENTMASKA_NMI_Pos 1U /*!< EWIC_ISA EVENTMASKA: NMI Position */ +#define EWIC_ISA_EVENTMASKA_NMI_Msk (1UL << EWIC_ISA_EVENTMASKA_NMI_Pos) /*!< EWIC_ISA EVENTMASKA: NMI Mask */ + +#define EWIC_ISA_EVENTMASKA_EVENT_Pos 0U /*!< EWIC_ISA EVENTMASKA: EVENT Position */ +#define EWIC_ISA_EVENTMASKA_EVENT_Msk (1UL /*<< EWIC_ISA_EVENTMASKA_EVENT_Pos*/) /*!< EWIC_ISA EVENTMASKA: EVENT Mask */ + +/** \brief EWIC_ISA Event Mask n Register Definitions */ +#define EWIC_ISA_EVENTMASKn_IRQ_Pos 0U /*!< EWIC_ISA EVENTMASKn: IRQ Position */ +#define EWIC_ISA_EVENTMASKn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_ISA_EVENTMASKn_IRQ_Pos*/) /*!< EWIC_ISA EVENTMASKn: IRQ Mask */ + +/*@}*/ /* end of group EWIC_ISA_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + __IM uint32_t TEBRDATA0; /*!< Offset: 0x024 (RO) Storage for corrected data that is associated with an error.*/ + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ + __IM uint32_t TEBRDATA1; /*!< Offset: 0x02c (RO) Storage for corrected data that is associated with an error.*/ +} ErrBnk_Type; + +/** \brief ErrBnk Instruction Cache Error Bank Register 0 Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/** \brief ErrBnk Instruction Cache Error Bank Register 1 Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/** \brief ErrBnk Data Cache Error Bank Register 0 Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/** \brief ErrBnk Data Cache Error Bank Register 1 Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/** \brief ErrBnk TCM Error Bank Register 0 Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 27U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 26U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/** \brief ErrBnk TCM Error Bank Register 1 Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 27U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 26U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/** \brief PrcCfgInf Processor Configuration Information Selection Register Definitions */ + +/** \brief PrcCfgInf Processor Configuration Information Read Data Register Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup STL_Type Software Test Library Observation Registers + \brief Type definitions for the Software Test Library Observation Registerss (STL) + @{ + */ + +/** + \brief Structure type to access the Software Test Library Observation Registerss (STL). + */ +typedef struct +{ + __IM uint32_t STLNVICPENDOR; /*!< Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register */ + __IM uint32_t STLNVICACTVOR; /*!< Offset: 0x004 (R/ ) NVIC Active Priority Tree Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t STLIDMPUSR; /*!< Offset: 0x010 ( /W) MPU Sample Register */ + __IM uint32_t STLIMPUOR; /*!< Offset: 0x014 (R/ ) MPU Region Hit Register */ + __IM uint32_t STLDMPUOR; /*!< Offset: 0x018 (R/ ) MPU Memory Attributes Register */ + +} STL_Type; + +/** \brief STL NVIC Pending Priority Tree Register Definitions */ +#define STL_STLNVICPENDOR_VALID_Pos 18U /*!< STL STLNVICPENDOR: VALID Position */ +#define STL_STLNVICPENDOR_VALID_Msk (1UL << STL_STLNVICPENDOR_VALID_Pos) /*!< STL STLNVICPENDOR: VALID Mask */ + +#define STL_STLNVICPENDOR_TARGET_Pos 17U /*!< STL STLNVICPENDOR: TARGET Position */ +#define STL_STLNVICPENDOR_TARGET_Msk (1UL << STL_STLNVICPENDOR_TARGET_Pos) /*!< STL STLNVICPENDOR: TARGET Mask */ + +#define STL_STLNVICPENDOR_PRIORITY_Pos 9U /*!< STL STLNVICPENDOR: PRIORITY Position */ +#define STL_STLNVICPENDOR_PRIORITY_Msk (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos) /*!< STL STLNVICPENDOR: PRIORITY Mask */ + +#define STL_STLNVICPENDOR_INTNUM_Pos 0U /*!< STL STLNVICPENDOR: INTNUM Position */ +#define STL_STLNVICPENDOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */ + +/** \brief STL NVIC Active Priority Tree Register Definitions */ +#define STL_STLNVICACTVOR_VALID_Pos 18U /*!< STL STLNVICACTVOR: VALID Position */ +#define STL_STLNVICACTVOR_VALID_Msk (1UL << STL_STLNVICACTVOR_VALID_Pos) /*!< STL STLNVICACTVOR: VALID Mask */ + +#define STL_STLNVICACTVOR_TARGET_Pos 17U /*!< STL STLNVICACTVOR: TARGET Position */ +#define STL_STLNVICACTVOR_TARGET_Msk (1UL << STL_STLNVICACTVOR_TARGET_Pos) /*!< STL STLNVICACTVOR: TARGET Mask */ + +#define STL_STLNVICACTVOR_PRIORITY_Pos 9U /*!< STL STLNVICACTVOR: PRIORITY Position */ +#define STL_STLNVICACTVOR_PRIORITY_Msk (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos) /*!< STL STLNVICACTVOR: PRIORITY Mask */ + +#define STL_STLNVICACTVOR_INTNUM_Pos 0U /*!< STL STLNVICACTVOR: INTNUM Position */ +#define STL_STLNVICACTVOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */ + +/** \brief STL MPU Sample Register Definitions */ +#define STL_STLIDMPUSR_ADDR_Pos 5U /*!< STL STLIDMPUSR: ADDR Position */ +#define STL_STLIDMPUSR_ADDR_Msk (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos) /*!< STL STLIDMPUSR: ADDR Mask */ + +#define STL_STLIDMPUSR_INSTR_Pos 2U /*!< STL STLIDMPUSR: INSTR Position */ +#define STL_STLIDMPUSR_INSTR_Msk (1UL << STL_STLIDMPUSR_INSTR_Pos) /*!< STL STLIDMPUSR: INSTR Mask */ + +#define STL_STLIDMPUSR_DATA_Pos 1U /*!< STL STLIDMPUSR: DATA Position */ +#define STL_STLIDMPUSR_DATA_Msk (1UL << STL_STLIDMPUSR_DATA_Pos) /*!< STL STLIDMPUSR: DATA Mask */ + +/** \brief STL MPU Region Hit Register Definitions */ +#define STL_STLIMPUOR_HITREGION_Pos 9U /*!< STL STLIMPUOR: HITREGION Position */ +#define STL_STLIMPUOR_HITREGION_Msk (0xFFUL << STL_STLIMPUOR_HITREGION_Pos) /*!< STL STLIMPUOR: HITREGION Mask */ + +#define STL_STLIMPUOR_ATTR_Pos 0U /*!< STL STLIMPUOR: ATTR Position */ +#define STL_STLIMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/) /*!< STL STLIMPUOR: ATTR Mask */ + +/** \brief STL MPU Memory Attributes Register Definitions */ +#define STL_STLDMPUOR_HITREGION_Pos 9U /*!< STL STLDMPUOR: HITREGION Position */ +#define STL_STLDMPUOR_HITREGION_Msk (0xFFUL << STL_STLDMPUOR_HITREGION_Pos) /*!< STL STLDMPUOR: HITREGION Mask */ + +#define STL_STLDMPUOR_ATTR_Pos 0U /*!< STL STLDMPUOR: ATTR Position */ +#define STL_STLDMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLDMPUOR_ATTR_Pos*/) /*!< STL STLDMPUOR: ATTR Mask */ + +/*@}*/ /* end of group STL_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ +#define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU Periodic Synchronization Control Register Definitions */ +#define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */ +#define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */ +#define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */ +#define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */ +#define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */ +#define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */ + +#define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */ +#define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 0 Definitions */ +#define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ +#define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ +#define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ +#define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ + +#define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ +#define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU Claim Tag Set Register Definitions */ +#define TPIU_CLAIMSET_SET_Pos 0U /*!< TPIU CLAIMSET: SET Position */ +#define TPIU_CLAIMSET_SET_Msk (0xFUL /*<< TPIU_CLAIMSET_SET_Pos*/) /*!< TPIU CLAIMSET: SET Mask */ + +/** \brief TPIU Claim Tag Clear Register Definitions */ +#define TPIU_CLAIMCLR_CLR_Pos 0U /*!< TPIU CLAIMCLR: CLR Position */ +#define TPIU_CLAIMCLR_CLR_Msk (0xFUL /*<< TPIU_CLAIMCLR_CLR_Pos*/) /*!< TPIU CLAIMCLR: CLR Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */ +#define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) Device Type Register */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/** \brief MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */ + +/** \brief MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/** \brief MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/** \brief SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/** \brief SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/** \brief SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/** \brief SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/** \brief SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/** \brief SAU Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/** \brief FPU Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/** \brief FPU Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/** \brief FPU Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/** \brief FPU Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ + +/** \brief FPU Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/** \brief FPU Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/** \brief DCB Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/** \brief DCB Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/** \brief DCB Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + uint32_t RESERVED1[3U]; + __IM uint32_t DDEVTYPE; /*!< Offset: 0x01C (R/ ) SCS Device Type Register */ +} DIB_Type; + +/** \brief DIB Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/** \brief DIB SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/** \brief DIB SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define DCAR_BASE (0xE001E200UL) /*!< Direct Cache Access Registers */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_ISA_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller interrupt status access Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define STL_BASE (0xE001E800UL) /*!< Software Test Library Base Address */ + #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ + #define EWIC_BASE (0xE0047000UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define DCAR ((DCAR_Type *) DCAR_BASE ) /*!< Direct Read Access to the embedded RAM associated with the L1 instruction and data cache */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC_ISA ((EWIC_ISA_Type *) EWIC_ISA_BASE ) /*!< EWIC interrupt status access struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define STL ((STL_Type *) STL_BASE ) /*!< Software Test Library configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + + #include "m-profile/armv8m_mpu.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "m-profile/armv8m_pmu.h" + +/** + \brief Cortex-M52 PMU events + \note Architectural PMU events can be found in armv8m_pmu.h +*/ + +#define ARMCM52_PMU_ECC_ERR 0xC000 /*!< One or more Error Correcting Code (ECC) errors detected */ +#define ARMCM52_PMU_ECC_ERR_MBIT 0xC001 /*!< One or more multi-bit ECC errors detected */ +#define ARMCM52_PMU_ECC_ERR_DCACHE 0xC010 /*!< One or more ECC errors in the data cache */ +#define ARMCM52_PMU_ECC_ERR_ICACHE 0xC011 /*!< One or more ECC errors in the instruction cache */ +#define ARMCM52_PMU_ECC_ERR_MBIT_DCACHE 0xC012 /*!< One or more multi-bit ECC errors in the data cache */ +#define ARMCM52_PMU_ECC_ERR_MBIT_ICACHE 0xC013 /*!< One or more multi-bit ECC errors in the instruction cache */ +#define ARMCM52_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ +#define ARMCM52_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ +#define ARMCM52_PMU_ECC_ERR_MBIT_DTCM 0xC022 /*!< One or more multi-bit ECC errors in the DTCM */ +#define ARMCM52_PMU_ECC_ERR_MBIT_ITCM 0xC023 /*!< One or more multi-bit ECC errors in the ITCM */ +#define ARMCM52_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM52_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM52_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM52_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access to the P-AHB write interface */ +#define ARMCM52_PMU_AXI_SAHB_WRITE_ACCESS 0xC302 /*!< M-AXI configuration: Any beat access to the M-AXI write interface.M-AHB configuration: Any write beat access to the SYS-AHB interface */ +#define ARMCM52_PMU_AXI_SAHB_READ_ACCESS 0xC303 /*!< M-AXI configuration: Any beat access to the M-AXI read interface.M-AHB configuration: Any read beat access to the SYS-AHB interface */ +#define ARMCM52_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM52_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ +#define ARMCM52_PMU_CDE_INST_RETIRED 0xC402 /*!< CDE instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_CX1_INST_RETIRED 0xC404 /*!< CDE CX1 instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_CX2_INST_RETIRED 0xC406 /*!< CDE CX2 instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_CX3_INST_RETIRED 0xC408 /*!< CDE CX3 instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_VCX1_INST_RETIRED 0xC40A /*!< CDE VCX1 instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_VCX2_INST_RETIRED 0xC40C /*!< CDE VCX2 instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_VCX3_INST_RETIRED 0xC40E /*!< CDE VCX3 instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_VCX1_VEC_INST_RETIRED 0xC410 /*!< CDE VCX1 Vector instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_VCX2_VEC_INST_RETIRED 0xC412 /*!< CDE VCX2 Vector instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_VCX3_VEC_INST_RETIRED 0xC414 /*!< CDE VCX3 Vector instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_PRED 0xC416 /*!< Cycles where one or more predicated beats of a CDE instruction architecturally executed. */ +#define ARMCM52_PMU_CDE_STALL 0xC417 /*!< Stall cycles caused by a CDE instruction. */ +#define ARMCM52_PMU_CDE_STALL_RESOURCE 0xC418 /*!< Stall cycles caused by a CDE instruction because of resource conflicts */ +#define ARMCM52_PMU_CDE_STALL_DEPENDENCY 0xC419 /*!< Stall cycles caused by a CDE register dependency. */ +#define ARMCM52_PMU_CDE_STALL_CUSTOM 0xC41A /*!< Stall cycles caused by a CDE instruction are generated by the custom hardware. */ +#define ARMCM52_PMU_CDE_STALL_OTHER 0xC41B /*!< Stall cycles caused by a CDE instruction are not covered by the other counters. */ +#define ARMCM52_PMU_CAHB_WRITE_ACCESS 0xC420 /*!< M-AHB configuration: A Write beat transfer on Code-AHB */ +#define ARMCM52_PMU_CAHB_READ_ACCESS 0xC421 /*!< M-AHB configuration: A Read beat transfer on Code-AHB. */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + #include "m-profile/armv7m_cachel1.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################### PAC Key functions ########################### */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) +#include "m-profile/armv81m_pac.h" +#endif + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM52_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + + + + + diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm55.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm55.h new file mode 100644 index 00000000000..a7c9f7436b4 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm55.h @@ -0,0 +1,4895 @@ +/* + * Copyright (c) 2018-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M55 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM55_H_GENERIC +#define __CORE_CM55_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M55 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM55 definitions */ + +#define __CORTEX_M (55U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM55_H_DEPENDANT +#define __CORE_CM55_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM55_REV + #define __CM55_REV 0x0000U + #warning "__CM55_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M55 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core EWIC Interrupt Status Access Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/** \brief SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/** \brief SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/** \brief SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/** \brief SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/** \brief SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/** \brief SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/** \brief SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/** \brief SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/** \brief SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/** \brief SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/** \brief ICB Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define ICB_ACTLR_DISDI_Msk (3UL << ICB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define ICB_ACTLR_DISOLAP_Pos 7U /*!< ACTLR: DISOLAP Position */ +#define ICB_ACTLR_DISOLAP_Msk (1UL << ICB_ACTLR_DISOLAP_Pos) /*!< ACTLR: DISOLAP Mask */ + +#define ICB_ACTLR_DISOLAPS_Pos 6U /*!< ACTLR: DISOLAPS Position */ +#define ICB_ACTLR_DISOLAPS_Msk (1UL << ICB_ACTLR_DISOLAPS_Pos) /*!< ACTLR: DISOLAPS Mask */ + +#define ICB_ACTLR_DISLOBR_Pos 5U /*!< ACTLR: DISLOBR Position */ +#define ICB_ACTLR_DISLOBR_Msk (1UL << ICB_ACTLR_DISLOBR_Pos) /*!< ACTLR: DISLOBR Mask */ + +#define ICB_ACTLR_DISLO_Pos 4U /*!< ACTLR: DISLO Position */ +#define ICB_ACTLR_DISLO_Msk (1UL << ICB_ACTLR_DISLO_Pos) /*!< ACTLR: DISLO Mask */ + +#define ICB_ACTLR_DISLOLEP_Pos 3U /*!< ACTLR: DISLOLEP Position */ +#define ICB_ACTLR_DISLOLEP_Msk (1UL << ICB_ACTLR_DISLOLEP_Pos) /*!< ACTLR: DISLOLEP Mask */ + +#define ICB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define ICB_ACTLR_DISFOLD_Msk (1UL << ICB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +/** \brief ICB Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[27U]; + __IM uint32_t ITREAD; /*!< Offset: 0xEF0 (R/ ) Integration Read Register */ + uint32_t RESERVED4[1U]; + __OM uint32_t ITWRITE; /*!< Offset: 0xEF8 ( /W) Integration Write Register */ + uint32_t RESERVED5[1U]; + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control Register */ + uint32_t RESERVED6[46U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ + uint32_t RESERVED7[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} ITM_Type; + +/** \brief ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Integration Read Register Definitions */ +#define ITM_ITREAD_AFVALID_Pos 1U /*!< ITM ITREAD: AFVALID Position */ +#define ITM_ITREAD_AFVALID_Msk (1UL << ITM_ITREAD_AFVALID_Pos) /*!< ITM ITREAD: AFVALID Mask */ + +#define ITM_ITREAD_ATREADY_Pos 0U /*!< ITM ITREAD: ATREADY Position */ +#define ITM_ITREAD_ATREADY_Msk (1UL /*<< ITM_ITREAD_ATREADY_Pos*/) /*!< ITM ITREAD: ATREADY Mask */ + +/** \brief ITM Integration Write Register Definitions */ +#define ITM_ITWRITE_AFVALID_Pos 1U /*!< ITM ITWRITE: AFVALID Position */ +#define ITM_ITWRITE_AFVALID_Msk (1UL << ITM_ITWRITE_AFVALID_Pos) /*!< ITM ITWRITE: AFVALID Mask */ + +#define ITM_ITWRITE_ATREADY_Pos 0U /*!< ITM ITWRITE: ATREADY Position */ +#define ITM_ITWRITE_ATREADY_Msk (1UL /*<< ITM_ITWRITE_ATREADY_Pos*/) /*!< ITM ITWRITE: ATREADY Mask */ + +/** \brief ITM Integration Mode Control Register Definitions */ +#define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ +#define ITM_ITCTRL_IME_Msk (1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + __IOM uint32_t VMASK1; /*!< Offset: 0x03C (R/W) Comparator Value Mask 1 */ + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + __IOM uint32_t VMASK3; /*!< Offset: 0x05C (R/W) Comparator Value Mask 3 */ + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED14[968U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ + uint32_t RESERVED15[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/** \brief MemSysCtl Memory System Control Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos 4U /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */ +#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk (1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos) /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/** \brief MemSysCtl Prefetcher Control Register Definitions */ +#define MEMSYSCTL_PFCR_MAX_OS_Pos 7U /*!< MEMSYSCTL PFCR: MAX_OS Position */ +#define MEMSYSCTL_PFCR_MAX_OS_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_OS_Pos) /*!< MEMSYSCTL PFCR: MAX_OS Mask */ + +#define MEMSYSCTL_PFCR_MAX_LA_Pos 4U /*!< MEMSYSCTL PFCR: MAX_LA Position */ +#define MEMSYSCTL_PFCR_MAX_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_LA_Pos) /*!< MEMSYSCTL PFCR: MAX_LA Mask */ + +#define MEMSYSCTL_PFCR_MIN_LA_Pos 1U /*!< MEMSYSCTL PFCR: MIN_LA Position */ +#define MEMSYSCTL_PFCR_MIN_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MIN_LA_Pos) /*!< MEMSYSCTL PFCR: MIN_LA Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/** \brief MemSysCtl ITCM Control Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/** \brief MemSysCtl DTCM Control Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/** \brief MemSysCtl P-AHB Control Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/** \brief MemSysCtl ITGU Control Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/** \brief MemSysCtl ITGU Configuration Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/** \brief MemSysCtl DTGU Control Registers Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/** \brief MemSysCtl DTGU Configuration Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/** \brief PwrModCtl Core Power Domain Low Power State Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/** \brief PwrModCtl Debug Power Domain Low Power State Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __IOM uint32_t EWIC_CR; /*!< Offset: 0x000 (R/W) EWIC Control Register */ + __IOM uint32_t EWIC_ASCR; /*!< Offset: 0x004 (R/W) EWIC Automatic Sequence Control Register */ + __OM uint32_t EWIC_CLRMASK; /*!< Offset: 0x008 ( /W) EWIC Clear Mask Register */ + __IM uint32_t EWIC_NUMID; /*!< Offset: 0x00C (R/ ) EWIC Event Number ID Register */ + uint32_t RESERVED0[124U]; + __IOM uint32_t EWIC_MASKA; /*!< Offset: 0x200 (R/W) EWIC MaskA Register */ + __IOM uint32_t EWIC_MASKn[15]; /*!< Offset: 0x204 (R/W) EWIC Maskn Registers */ + uint32_t RESERVED1[112U]; + __IM uint32_t EWIC_PENDA; /*!< Offset: 0x400 (R/ ) EWIC PendA Event Register */ + __IOM uint32_t EWIC_PENDn[15]; /*!< Offset: 0x404 (R/W) EWIC Pendn Event Registers */ + uint32_t RESERVED2[112U]; + __IM uint32_t EWIC_PSR; /*!< Offset: 0x600 (R/ ) EWIC Pend Summary Register */ +} EWIC_Type; + +/** \brief EWIC Control Register Definitions */ +#define EWIC_EWIC_CR_EN_Pos 0U /*!< EWIC EWIC_CR: EN Position */ +#define EWIC_EWIC_CR_EN_Msk (1UL /*<< EWIC_EWIC_CR_EN_Pos*/) /*!< EWIC EWIC_CR: EN Mask */ + +/** \brief EWIC Automatic Sequence Control Register Definitions */ +#define EWIC_EWIC_ASCR_ASPU_Pos 1U /*!< EWIC EWIC_ASCR: ASPU Position */ +#define EWIC_EWIC_ASCR_ASPU_Msk (1UL << EWIC_EWIC_ASCR_ASPU_Pos) /*!< EWIC EWIC_ASCR: ASPU Mask */ + +#define EWIC_EWIC_ASCR_ASPD_Pos 0U /*!< EWIC EWIC_ASCR: ASPD Position */ +#define EWIC_EWIC_ASCR_ASPD_Msk (1UL /*<< EWIC_EWIC_ASCR_ASPD_Pos*/) /*!< EWIC EWIC_ASCR: ASPD Mask */ + +/** \brief EWIC Event Number ID Register Definitions */ +#define EWIC_EWIC_NUMID_NUMEVENT_Pos 0U /*!< EWIC_NUMID: NUMEVENT Position */ +#define EWIC_EWIC_NUMID_NUMEVENT_Msk (0xFFFFUL /*<< EWIC_EWIC_NUMID_NUMEVENT_Pos*/) /*!< EWIC_NUMID: NUMEVENT Mask */ + +/** \brief EWIC Mask A Register Definitions */ +#define EWIC_EWIC_MASKA_EDBGREQ_Pos 2U /*!< EWIC EWIC_MASKA: EDBGREQ Position */ +#define EWIC_EWIC_MASKA_EDBGREQ_Msk (1UL << EWIC_EWIC_MASKA_EDBGREQ_Pos) /*!< EWIC EWIC_MASKA: EDBGREQ Mask */ + +#define EWIC_EWIC_MASKA_NMI_Pos 1U /*!< EWIC EWIC_MASKA: NMI Position */ +#define EWIC_EWIC_MASKA_NMI_Msk (1UL << EWIC_EWIC_MASKA_NMI_Pos) /*!< EWIC EWIC_MASKA: NMI Mask */ + +#define EWIC_EWIC_MASKA_EVENT_Pos 0U /*!< EWIC EWIC_MASKA: EVENT Position */ +#define EWIC_EWIC_MASKA_EVENT_Msk (1UL /*<< EWIC_EWIC_MASKA_EVENT_Pos*/) /*!< EWIC EWIC_MASKA: EVENT Mask */ + +/** \brief EWIC Mask n Register Definitions */ +#define EWIC_EWIC_MASKn_IRQ_Pos 0U /*!< EWIC EWIC_MASKn: IRQ Position */ +#define EWIC_EWIC_MASKn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EWIC_MASKn_IRQ_Pos*/) /*!< EWIC EWIC_MASKn: IRQ Mask */ + +/** \brief EWIC Pend A Register Definitions */ +#define EWIC_EWIC_PENDA_EDBGREQ_Pos 2U /*!< EWIC EWIC_PENDA: EDBGREQ Position */ +#define EWIC_EWIC_PENDA_EDBGREQ_Msk (1UL << EWIC_EWIC_PENDA_EDBGREQ_Pos) /*!< EWIC EWIC_PENDA: EDBGREQ Mask */ + +#define EWIC_EWIC_PENDA_NMI_Pos 1U /*!< EWIC EWIC_PENDA: NMI Position */ +#define EWIC_EWIC_PENDA_NMI_Msk (1UL << EWIC_EWIC_PENDA_NMI_Pos) /*!< EWIC EWIC_PENDA: NMI Mask */ + +#define EWIC_EWIC_PENDA_EVENT_Pos 0U /*!< EWIC EWIC_PENDA: EVENT Position */ +#define EWIC_EWIC_PENDA_EVENT_Msk (1UL /*<< EWIC_EWIC_PENDA_EVENT_Pos*/) /*!< EWIC EWIC_PENDA: EVENT Mask */ + +/** \brief EWIC Pend n Register Definitions */ +#define EWIC_EWIC_PENDn_IRQ_Pos 0U /*!< EWIC EWIC_PENDn: IRQ Position */ +#define EWIC_EWIC_PENDn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EWIC_PENDn_IRQ_Pos*/) /*!< EWIC EWIC_PENDn: IRQ Mask */ + +/** \brief EWIC Pend Summary Register Definitions */ +#define EWIC_EWIC_PSR_NZ_Pos 1U /*!< EWIC EWIC_PSR: NZ Position */ +#define EWIC_EWIC_PSR_NZ_Msk (0x7FFFUL << EWIC_EWIC_PSR_NZ_Pos) /*!< EWIC EWIC_PSR: NZ Mask */ + +#define EWIC_EWIC_PSR_NZA_Pos 0U /*!< EWIC EWIC_PSR: NZA Position */ +#define EWIC_EWIC_PSR_NZA_Msk (1UL /*<< EWIC_EWIC_PSR_NZA_Pos*/) /*!< EWIC EWIC_PSR: NZA Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_ISA_Type External Wakeup Interrupt Controller (EWIC) interrupt status access registers + \brief Type definitions for the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/ ) Event Mask A Register */ + __IM uint32_t EVENTMASKn[15]; /*!< Offset: 0x084 (R/ ) Event Mask Register */ +} EWIC_ISA_Type; + +/** \brief EWIC_ISA Event Set Pending Register Definitions */ +#define EWIC_ISA_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC_ISA EVENTSPR: EDBGREQ Position */ +#define EWIC_ISA_EVENTSPR_EDBGREQ_Msk (1UL << EWIC_ISA_EVENTSPR_EDBGREQ_Pos) /*!< EWIC_ISA EVENTSPR: EDBGREQ Mask */ + +#define EWIC_ISA_EVENTSPR_NMI_Pos 1U /*!< EWIC_ISA EVENTSPR: NMI Position */ +#define EWIC_ISA_EVENTSPR_NMI_Msk (1UL << EWIC_ISA_EVENTSPR_NMI_Pos) /*!< EWIC_ISA EVENTSPR: NMI Mask */ + +#define EWIC_ISA_EVENTSPR_EVENT_Pos 0U /*!< EWIC_ISA EVENTSPR: EVENT Position */ +#define EWIC_ISA_EVENTSPR_EVENT_Msk (1UL /*<< EWIC_ISA_EVENTSPR_EVENT_Pos*/) /*!< EWIC_ISA EVENTSPR: EVENT Mask */ + +/** \brief EWIC_ISA Event Mask A Register Definitions */ +#define EWIC_ISA_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC_ISA EVENTMASKA: EDBGREQ Position */ +#define EWIC_ISA_EVENTMASKA_EDBGREQ_Msk (1UL << EWIC_ISA_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC_ISA EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_ISA_EVENTMASKA_NMI_Pos 1U /*!< EWIC_ISA EVENTMASKA: NMI Position */ +#define EWIC_ISA_EVENTMASKA_NMI_Msk (1UL << EWIC_ISA_EVENTMASKA_NMI_Pos) /*!< EWIC_ISA EVENTMASKA: NMI Mask */ + +#define EWIC_ISA_EVENTMASKA_EVENT_Pos 0U /*!< EWIC_ISA EVENTMASKA: EVENT Position */ +#define EWIC_ISA_EVENTMASKA_EVENT_Msk (1UL /*<< EWIC_ISA_EVENTMASKA_EVENT_Pos*/) /*!< EWIC_ISA EVENTMASKA: EVENT Mask */ + +/** \brief EWIC_ISA Event Mask n Register Definitions */ +#define EWIC_ISA_EVENTMASKn_IRQ_Pos 0U /*!< EWIC_ISA EVENTMASKn: IRQ Position */ +#define EWIC_ISA_EVENTMASKn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_ISA_EVENTMASKn_IRQ_Pos*/) /*!< EWIC_ISA EVENTMASKn: IRQ Mask */ + +/*@}*/ /* end of group EWIC_ISA_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/** \brief ErrBnk Instruction Cache Error Bank Register 0 Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/** \brief ErrBnk Instruction Cache Error Bank Register 1 Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/** \brief ErrBnk Data Cache Error Bank Register 0 Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/** \brief ErrBnk Data Cache Error Bank Register 1 Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/** \brief ErrBnk TCM Error Bank Register 0 Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x7UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/** \brief ErrBnk TCM Error Bank Register 1 Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x7UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/** \brief PrcCfgInf Processor Configuration Information Selection Register Definitions */ + +/** \brief PrcCfgInf Processor Configuration Information Read Data Register Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup STL_Type Software Test Library Observation Registers + \brief Type definitions for the Software Test Library Observation Registerss (STL) + @{ + */ + +/** + \brief Structure type to access the Software Test Library Observation Registerss (STL). + */ +typedef struct +{ + __IM uint32_t STLNVICPENDOR; /*!< Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register */ + __IM uint32_t STLNVICACTVOR; /*!< Offset: 0x004 (R/ ) NVIC Active Priority Tree Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t STLIDMPUSR; /*!< Offset: 0x010 ( /W) MPU Sample Register */ + __IM uint32_t STLIMPUOR; /*!< Offset: 0x014 (R/ ) MPU Region Hit Register */ + __IM uint32_t STLD0MPUOR; /*!< Offset: 0x018 (R/ ) MPU Memory Attributes Register 0 */ + __IM uint32_t STLD1MPUOR; /*!< Offset: 0x01C (R/ ) MPU Memory Attributes Register 1 */ + +} STL_Type; + +/** \brief STL NVIC Pending Priority Tree Register Definitions */ +#define STL_STLNVICPENDOR_VALID_Pos 18U /*!< STL STLNVICPENDOR: VALID Position */ +#define STL_STLNVICPENDOR_VALID_Msk (1UL << STL_STLNVICPENDOR_VALID_Pos) /*!< STL STLNVICPENDOR: VALID Mask */ + +#define STL_STLNVICPENDOR_TARGET_Pos 17U /*!< STL STLNVICPENDOR: TARGET Position */ +#define STL_STLNVICPENDOR_TARGET_Msk (1UL << STL_STLNVICPENDOR_TARGET_Pos) /*!< STL STLNVICPENDOR: TARGET Mask */ + +#define STL_STLNVICPENDOR_PRIORITY_Pos 9U /*!< STL STLNVICPENDOR: PRIORITY Position */ +#define STL_STLNVICPENDOR_PRIORITY_Msk (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos) /*!< STL STLNVICPENDOR: PRIORITY Mask */ + +#define STL_STLNVICPENDOR_INTNUM_Pos 0U /*!< STL STLNVICPENDOR: INTNUM Position */ +#define STL_STLNVICPENDOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */ + +/** \brief STL NVIC Active Priority Tree Register Definitions */ +#define STL_STLNVICACTVOR_VALID_Pos 18U /*!< STL STLNVICACTVOR: VALID Position */ +#define STL_STLNVICACTVOR_VALID_Msk (1UL << STL_STLNVICACTVOR_VALID_Pos) /*!< STL STLNVICACTVOR: VALID Mask */ + +#define STL_STLNVICACTVOR_TARGET_Pos 17U /*!< STL STLNVICACTVOR: TARGET Position */ +#define STL_STLNVICACTVOR_TARGET_Msk (1UL << STL_STLNVICACTVOR_TARGET_Pos) /*!< STL STLNVICACTVOR: TARGET Mask */ + +#define STL_STLNVICACTVOR_PRIORITY_Pos 9U /*!< STL STLNVICACTVOR: PRIORITY Position */ +#define STL_STLNVICACTVOR_PRIORITY_Msk (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos) /*!< STL STLNVICACTVOR: PRIORITY Mask */ + +#define STL_STLNVICACTVOR_INTNUM_Pos 0U /*!< STL STLNVICACTVOR: INTNUM Position */ +#define STL_STLNVICACTVOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */ + +/** \brief STL MPU Sample Register Definitions */ +#define STL_STLIDMPUSR_ADDR_Pos 5U /*!< STL STLIDMPUSR: ADDR Position */ +#define STL_STLIDMPUSR_ADDR_Msk (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos) /*!< STL STLIDMPUSR: ADDR Mask */ + +#define STL_STLIDMPUSR_INSTR_Pos 2U /*!< STL STLIDMPUSR: INSTR Position */ +#define STL_STLIDMPUSR_INSTR_Msk (1UL << STL_STLIDMPUSR_INSTR_Pos) /*!< STL STLIDMPUSR: INSTR Mask */ + +#define STL_STLIDMPUSR_DATA_Pos 1U /*!< STL STLIDMPUSR: DATA Position */ +#define STL_STLIDMPUSR_DATA_Msk (1UL << STL_STLIDMPUSR_DATA_Pos) /*!< STL STLIDMPUSR: DATA Mask */ + +/** \brief STL MPU Region Hit Register Definitions */ +#define STL_STLIMPUOR_HITREGION_Pos 9U /*!< STL STLIMPUOR: HITREGION Position */ +#define STL_STLIMPUOR_HITREGION_Msk (0xFFUL << STL_STLIMPUOR_HITREGION_Pos) /*!< STL STLIMPUOR: HITREGION Mask */ + +#define STL_STLIMPUOR_ATTR_Pos 0U /*!< STL STLIMPUOR: ATTR Position */ +#define STL_STLIMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/) /*!< STL STLIMPUOR: ATTR Mask */ + +/** \brief STL MPU Memory Attributes Register 0 Definitions */ +#define STL_STLD0MPUOR_HITREGION_Pos 9U /*!< STL STLD0MPUOR: HITREGION Position */ +#define STL_STLD0MPUOR_HITREGION_Msk (0xFFUL << STL_STLD0MPUOR_HITREGION_Pos) /*!< STL STLD0MPUOR: HITREGION Mask */ + +#define STL_STLD0MPUOR_ATTR_Pos 0U /*!< STL STLD0MPUOR: ATTR Position */ +#define STL_STLD0MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD0MPUOR_ATTR_Pos*/) /*!< STL STLD0MPUOR: ATTR Mask */ + +/** \brief STL MPU Memory Attributes Register 1 Definitions */ +#define STL_STLD1MPUOR_HITREGION_Pos 9U /*!< STL STLD1MPUOR: HITREGION Position */ +#define STL_STLD1MPUOR_HITREGION_Msk (0xFFUL << STL_STLD1MPUOR_HITREGION_Pos) /*!< STL STLD1MPUOR: HITREGION Mask */ + +#define STL_STLD1MPUOR_ATTR_Pos 0U /*!< STL STLD1MPUOR: ATTR Position */ +#define STL_STLD1MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD1MPUOR_ATTR_Pos*/) /*!< STL STLD1MPUOR: ATTR Mask */ + +/*@}*/ /* end of group STL_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ +#define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU Periodic Synchronization Control Register Definitions */ +#define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */ +#define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */ +#define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */ +#define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */ +#define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */ +#define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */ + +#define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */ +#define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 0 Definitions */ +#define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ +#define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ +#define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ +#define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ + +#define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ +#define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU Claim Tag Set Register Definitions */ +#define TPIU_CLAIMSET_SET_Pos 0U /*!< TPIU CLAIMSET: SET Position */ +#define TPIU_CLAIMSET_SET_Msk (0xFUL /*<< TPIU_CLAIMSET_SET_Pos*/) /*!< TPIU CLAIMSET: SET Mask */ + +/** \brief TPIU Claim Tag Clear Register Definitions */ +#define TPIU_CLAIMCLR_CLR_Pos 0U /*!< TPIU CLAIMCLR: CLR Position */ +#define TPIU_CLAIMCLR_CLR_Msk (0xFUL /*<< TPIU_CLAIMCLR_CLR_Pos*/) /*!< TPIU CLAIMCLR: CLR Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */ +#define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) Device Type Register */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/** \brief MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */ + +/** \brief MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/** \brief MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/** \brief SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/** \brief SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/** \brief SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/** \brief SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/** \brief SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/** \brief SAU Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/** \brief FPU Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/** \brief FPU Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/** \brief FPU Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/** \brief FPU Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ + +/** \brief FPU Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/** \brief FPU Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/** \brief DCB Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/** \brief DCB Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/** \brief DCB Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + uint32_t RESERVED1[3U]; + __IM uint32_t DDEVTYPE; /*!< Offset: 0x01C (R/ ) SCS Device Type Register */ +} DIB_Type; + +/** \brief DIB Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/** \brief DIB SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/** \brief DIB SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_ISA_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller interrupt status access Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define STL_BASE (0xE001E800UL) /*!< Software Test Library Base Address */ + #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ + #define EWIC_BASE (0xE0047000UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC_ISA ((EWIC_ISA_Type *) EWIC_ISA_BASE ) /*!< EWIC interrupt status access struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define STL ((STL_Type *) STL_BASE ) /*!< Software Test Library configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; + __OM uint32_t DSCEMCR; + __IOM uint32_t DAUTHCTRL; + __IOM uint32_t DSCSR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos DCB_DHCSR_S_RESTART_ST_Pos +#define CoreDebug_DHCSR_S_RESTART_ST_Msk DCB_DHCSR_S_RESTART_ST_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_FPD_Pos DCB_DHCSR_S_FPD_Pos +#define CoreDebug_DHCSR_S_FPD_Msk DCB_DHCSR_S_FPD_Msk + +#define CoreDebug_DHCSR_S_SUIDE_Pos DCB_DHCSR_S_SUIDE_Pos +#define CoreDebug_DHCSR_S_SUIDE_Msk DCB_DHCSR_S_SUIDE_Msk + +#define CoreDebug_DHCSR_S_NSUIDE_Pos DCB_DHCSR_S_NSUIDE_Pos +#define CoreDebug_DHCSR_S_NSUIDE_Msk DCB_DHCSR_S_NSUIDE_Msk + +#define CoreDebug_DHCSR_S_SDE_Pos DCB_DHCSR_S_SDE_Pos +#define CoreDebug_DHCSR_S_SDE_Msk DCB_DHCSR_S_SDE_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_PMOV_Pos DCB_DHCSR_C_PMOV_Pos +#define CoreDebug_DHCSR_C_PMOV_Msk DCB_DHCSR_C_PMOV_Msk + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos +#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk + +#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos +#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk + +#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos +#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk + +#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos +#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos +#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk + +#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos +#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk + +#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos +#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk + +#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos +#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos +#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk + +#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos +#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos DCB_DSCEMCR_CLR_MON_REQ_Pos +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk DCB_DSCEMCR_CLR_MON_REQ_Msk + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos DCB_DSCEMCR_CLR_MON_PEND_Pos +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk DCB_DSCEMCR_CLR_MON_PEND_Msk + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos DCB_DSCEMCR_SET_MON_REQ_Pos +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk DCB_DSCEMCR_SET_MON_REQ_Msk + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos DCB_DSCEMCR_SET_MON_PEND_Pos +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk DCB_DSCEMCR_SET_MON_PEND_Msk + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos DCB_DAUTHCTRL_UIDEN_Pos +#define CoreDebug_DAUTHCTRL_UIDEN_Msk DCB_DAUTHCTRL_UIDEN_Msk + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos DCB_DAUTHCTRL_UIDAPEN_Pos +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk DCB_DAUTHCTRL_UIDAPEN_Msk + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos DCB_DAUTHCTRL_FSDMA_Pos +#define CoreDebug_DAUTHCTRL_FSDMA_Msk DCB_DAUTHCTRL_FSDMA_Msk + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos DCB_DAUTHCTRL_INTSPNIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk DCB_DAUTHCTRL_INTSPNIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos DCB_DAUTHCTRL_SPNIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk DCB_DAUTHCTRL_SPNIDENSEL_Msk + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos DCB_DAUTHCTRL_INTSPIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk DCB_DAUTHCTRL_INTSPIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos DCB_DAUTHCTRL_SPIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk DCB_DAUTHCTRL_SPIDENSEL_Msk + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos DCB_DSCSR_CDS_Pos +#define CoreDebug_DSCSR_CDS_Msk DCB_DSCSR_CDS_Msk + +#define CoreDebug_DSCSR_SBRSEL_Pos DCB_DSCSR_SBRSEL_Pos +#define CoreDebug_DSCSR_SBRSEL_Msk DCB_DSCSR_SBRSEL_Msk + +#define CoreDebug_DSCSR_SBRSELEN_Pos DCB_DSCSR_SBRSELEN_Pos +#define CoreDebug_DSCSR_SBRSELEN_Msk DCB_DSCSR_SBRSELEN_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS) +#endif + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + + #include "m-profile/armv8m_mpu.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "m-profile/armv8m_pmu.h" + +/** + \brief Cortex-M55 PMU events + \note Architectural PMU events can be found in armv8m_pmu.h +*/ + +#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */ +#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */ +#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/ +#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */ +#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */ +#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */ +#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM55_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access to the P-AHB write interface */ +#define ARMCM55_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM55_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ +#define ARMCM55_PMU_CDE_INST_RETIRED 0xC402 /*!< CDE instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_CX1_INST_RETIRED 0xC404 /*!< CDE CX1 instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_CX2_INST_RETIRED 0xC406 /*!< CDE CX2 instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_CX3_INST_RETIRED 0xC408 /*!< CDE CX3 instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_VCX1_INST_RETIRED 0xC40A /*!< CDE VCX1 instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_VCX2_INST_RETIRED 0xC40C /*!< CDE VCX2 instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_VCX3_INST_RETIRED 0xC40E /*!< CDE VCX3 instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_VCX1_VEC_INST_RETIRED 0xC410 /*!< CDE VCX1 Vector instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_VCX2_VEC_INST_RETIRED 0xC412 /*!< CDE VCX2 Vector instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_VCX3_VEC_INST_RETIRED 0xC414 /*!< CDE VCX3 Vector instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_PRED 0xC416 /*!< Cycles where one or more predicated beats of a CDE instruction architecturally executed. */ +#define ARMCM55_PMU_CDE_STALL 0xC417 /*!< Stall cycles caused by a CDE instruction. */ +#define ARMCM55_PMU_CDE_STALL_RESOURCE 0xC418 /*!< Stall cycles caused by a CDE instruction because of resource conflicts */ +#define ARMCM55_PMU_CDE_STALL_DEPENDENCY 0xC419 /*!< Stall cycles caused by a CDE register dependency. */ +#define ARMCM55_PMU_CDE_STALL_CUSTOM 0xC41A /*!< Stall cycles caused by a CDE instruction are generated by the custom hardware. */ +#define ARMCM55_PMU_CDE_STALL_OTHER 0xC41B /*!< Stall cycles caused by a CDE instruction are not covered by the other counters. */ +#define ARMCM55_PMU_PF_LF_LA_1 0xC41C /*!< A data prefetcher line-fill request is made while the lookahead distance is 1. */ +#define ARMCM55_PMU_PF_LF_LA_2 0xC41D /*!< A data prefetcher line-fill request is made while the lookahead distance is 2. */ +#define ARMCM55_PMU_PF_LF_LA_3 0xC41E /*!< A data prefetcher line-fill request is made while the lookahead distance is 3. */ +#define ARMCM55_PMU_PF_LF_LA_4 0xC41F /*!< A data prefetcher line-fill request is made while the lookahead distance is 4. */ +#define ARMCM55_PMU_PF_LF_LA_5 0xC420 /*!< A data prefetcher line-fill request is made while the lookahead distance is 5. */ +#define ARMCM55_PMU_PF_LF_LA_6 0xC421 /*!< A data prefetcher line-fill request is made while the lookahead distance is 6. */ +#define ARMCM55_PMU_PF_BUFFER_FULL 0xC422 /*!< A data prefetcher request is made while the buffer is full. */ +#define ARMCM55_PMU_PF_BUFFER_MISS 0xC423 /*!< A load requires a line-fill which misses in the data prefetcher buffer. */ +#define ARMCM55_PMU_PF_BUFFER_HIT 0xC424 /*!< A load access hits in the data prefetcher buffer. */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + #include "m-profile/armv7m_cachel1.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm7.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm7.h new file mode 100644 index 00000000000..182081940b7 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm7.h @@ -0,0 +1,2468 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M7 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IPR[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ + uint32_t RESERVED7[5U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/** \brief SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/** \brief SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/** \brief SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/** \brief SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/** \brief SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/** \brief SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/** \brief SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/** \brief SCB Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/** \brief SCB Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/** \brief SCB AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/** \brief SCB L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCDIS_Pos 1U /*!< SCB CACR: ECCDIS Position */ +#define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) /*!< SCB CACR: ECCDIS Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/** \brief SCB AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/** \brief SCB Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/** \brief SCnSCB Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/** \brief SCnSCB Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Lock Status Register */ +} ITM_Type; + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Lock Status Register Definitions */ +#define ITM_LSR_BYTEACC_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_BYTEACC_Msk (1UL << ITM_LSR_BYTEACC_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_ACCESS_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_ACCESS_Msk (1UL << ITM_LSR_ACCESS_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_PRESENT_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_PRESENT_Msk (1UL /*<< ITM_LSR_PRESENT_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration ETM Data Register Definitions (FIFO0) */ +#define TPIU_FIFO0_ITM_ATVALID_Pos 29U /*!< TPIU FIFO0: ITM_ATVALID Position */ +#define TPIU_FIFO0_ITM_ATVALID_Msk (1UL << TPIU_FIFO0_ITM_ATVALID_Pos) /*!< TPIU FIFO0: ITM_ATVALID Mask */ + +#define TPIU_FIFO0_ITM_bytecount_Pos 27U /*!< TPIU FIFO0: ITM_bytecount Position */ +#define TPIU_FIFO0_ITM_bytecount_Msk (0x3UL << TPIU_FIFO0_ITM_bytecount_Pos) /*!< TPIU FIFO0: ITM_bytecount Mask */ + +#define TPIU_FIFO0_ETM_ATVALID_Pos 26U /*!< TPIU FIFO0: ETM_ATVALID Position */ +#define TPIU_FIFO0_ETM_ATVALID_Msk (1UL << TPIU_FIFO0_ETM_ATVALID_Pos) /*!< TPIU FIFO0: ETM_ATVALID Mask */ + +#define TPIU_FIFO0_ETM_bytecount_Pos 24U /*!< TPIU FIFO0: ETM_bytecount Position */ +#define TPIU_FIFO0_ETM_bytecount_Msk (0x3UL << TPIU_FIFO0_ETM_bytecount_Pos) /*!< TPIU FIFO0: ETM_bytecount Mask */ + +#define TPIU_FIFO0_ETM2_Pos 16U /*!< TPIU FIFO0: ETM2 Position */ +#define TPIU_FIFO0_ETM2_Msk (0xFFUL << TPIU_FIFO0_ETM2_Pos) /*!< TPIU FIFO0: ETM2 Mask */ + +#define TPIU_FIFO0_ETM1_Pos 8U /*!< TPIU FIFO0: ETM1 Position */ +#define TPIU_FIFO0_ETM1_Msk (0xFFUL << TPIU_FIFO0_ETM1_Pos) /*!< TPIU FIFO0: ETM1 Mask */ + +#define TPIU_FIFO0_ETM0_Pos 0U /*!< TPIU FIFO0: ETM0 Position */ +#define TPIU_FIFO0_ETM0_Msk (0xFFUL /*<< TPIU_FIFO0_ETM0_Pos*/) /*!< TPIU FIFO0: ETM0 Mask */ + +/** \brief TPIU ITATBCTR2 Register Definitions */ +#define TPIU_ITATBCTR2_ATREADY2_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2 Position */ +#define TPIU_ITATBCTR2_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2 Mask */ + +#define TPIU_ITATBCTR2_ATREADY1_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1 Position */ +#define TPIU_ITATBCTR2_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1 Mask */ + +/** \brief TPIU Integration ITM Data Register Definitions (FIFO1) */ +#define TPIU_FIFO1_ITM_ATVALID_Pos 29U /*!< TPIU FIFO1: ITM_ATVALID Position */ +#define TPIU_FIFO1_ITM_ATVALID_Msk (1UL << TPIU_FIFO1_ITM_ATVALID_Pos) /*!< TPIU FIFO1: ITM_ATVALID Mask */ + +#define TPIU_FIFO1_ITM_bytecount_Pos 27U /*!< TPIU FIFO1: ITM_bytecount Position */ +#define TPIU_FIFO1_ITM_bytecount_Msk (0x3UL << TPIU_FIFO1_ITM_bytecount_Pos) /*!< TPIU FIFO1: ITM_bytecount Mask */ + +#define TPIU_FIFO1_ETM_ATVALID_Pos 26U /*!< TPIU FIFO1: ETM_ATVALID Position */ +#define TPIU_FIFO1_ETM_ATVALID_Msk (1UL << TPIU_FIFO1_ETM_ATVALID_Pos) /*!< TPIU FIFO1: ETM_ATVALID Mask */ + +#define TPIU_FIFO1_ETM_bytecount_Pos 24U /*!< TPIU FIFO1: ETM_bytecount Position */ +#define TPIU_FIFO1_ETM_bytecount_Msk (0x3UL << TPIU_FIFO1_ETM_bytecount_Pos) /*!< TPIU FIFO1: ETM_bytecount Mask */ + +#define TPIU_FIFO1_ITM2_Pos 16U /*!< TPIU FIFO1: ITM2 Position */ +#define TPIU_FIFO1_ITM2_Msk (0xFFUL << TPIU_FIFO1_ITM2_Pos) /*!< TPIU FIFO1: ITM2 Mask */ + +#define TPIU_FIFO1_ITM1_Pos 8U /*!< TPIU FIFO1: ITM1 Position */ +#define TPIU_FIFO1_ITM1_Msk (0xFFUL << TPIU_FIFO1_ITM1_Pos) /*!< TPIU FIFO1: ITM1 Mask */ + +#define TPIU_FIFO1_ITM0_Pos 0U /*!< TPIU FIFO1: ITM0 Position */ +#define TPIU_FIFO1_ITM0_Msk (0xFFUL /*<< TPIU_FIFO1_ITM0_Pos*/) /*!< TPIU FIFO1: ITM0 Mask */ + +/** \brief TPIU ITATBCTR0 Register Definitions */ +#define TPIU_ITATBCTR0_ATREADY2_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2 Position */ +#define TPIU_ITATBCTR0_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2 Mask */ + +#define TPIU_ITATBCTR0_ATREADY1_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1 Position */ +#define TPIU_ITATBCTR0_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1 Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_MinBufSz_Pos 6U /*!< TPIU DEVID: MinBufSz Position */ +#define TPIU_DEVID_MinBufSz_Msk (0x7UL << TPIU_DEVID_MinBufSz_Pos) /*!< TPIU DEVID: MinBufSz Mask */ + +#define TPIU_DEVID_AsynClkIn_Pos 5U /*!< TPIU DEVID: AsynClkIn Position */ +#define TPIU_DEVID_AsynClkIn_Msk (1UL << TPIU_DEVID_AsynClkIn_Pos) /*!< TPIU DEVID: AsynClkIn Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/** \brief MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/** \brief FPU Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/** \brief FPU Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/** \brief FPU Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/** \brief FPU Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ + +#define FPU_MVFR0_FPShortvec_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_FPShortvec_Msk (0xFUL << FPU_MVFR0_FPShortvec_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPExceptrap_Pos 12U /*!< MVFR0: Exception trapping bits Position */ +#define FPU_MVFR0_FPExceptrap_Msk (0xFUL << FPU_MVFR0_FPExceptrap_Pos) /*!< MVFR0: Exception trapping bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ + +/** \brief FPU Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/** \brief FPU Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ +#define DCB_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ +#define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos +#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk + +#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos +#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk + +#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos +#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk + +#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos +#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos +#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk + +#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos +#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk + +#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos +#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk + +#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos +#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos +#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk + +#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos +#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "m-profile/armv7m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + #include "m-profile/armv7m_cachel1.h" +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm85.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm85.h new file mode 100644 index 00000000000..8a8b8954f95 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm85.h @@ -0,0 +1,4936 @@ +/* + * Copyright (c) 2022-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M85 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM85_H_GENERIC +#define __CORE_CM85_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M85 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM85 definitions */ + +#define __CORTEX_M (85U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM85_H_DEPENDANT +#define __CORE_CM85_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM85_REV + #define __CM85_REV 0x0001U + #warning "__CM85_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M85 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core EWIC Interrupt Status Access Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:1; /*!< bit: 20 Reserved */ + uint32_t B:1; /*!< bit: 21 BTI active (read 0) */ + uint32_t _reserved2:2; /*!< bit: 22..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_B_Pos 21U /*!< xPSR: B Position */ +#define xPSR_B_Msk (1UL << xPSR_B_Pos) /*!< xPSR: B Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t BTI_EN:1; /*!< bit: 4 Privileged branch target identification enable */ + uint32_t UBTI_EN:1; /*!< bit: 5 Unprivileged branch target identification enable */ + uint32_t PAC_EN:1; /*!< bit: 6 Privileged pointer authentication enable */ + uint32_t UPAC_EN:1; /*!< bit: 7 Unprivileged pointer authentication enable */ + uint32_t _reserved1:24; /*!< bit: 8..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_UPAC_EN_Pos 7U /*!< CONTROL: UPAC_EN Position */ +#define CONTROL_UPAC_EN_Msk (1UL << CONTROL_UPAC_EN_Pos) /*!< CONTROL: UPAC_EN Mask */ + +#define CONTROL_PAC_EN_Pos 6U /*!< CONTROL: PAC_EN Position */ +#define CONTROL_PAC_EN_Msk (1UL << CONTROL_PAC_EN_Pos) /*!< CONTROL: PAC_EN Mask */ + +#define CONTROL_UBTI_EN_Pos 5U /*!< CONTROL: UBTI_EN Position */ +#define CONTROL_UBTI_EN_Msk (1UL << CONTROL_UBTI_EN_Pos) /*!< CONTROL: UBTI_EN Mask */ + +#define CONTROL_BTI_EN_Pos 4U /*!< CONTROL: BTI_EN Position */ +#define CONTROL_BTI_EN_Msk (1UL << CONTROL_BTI_EN_Pos) /*!< CONTROL: BTI_EN Mask */ + +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/** \brief SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/** \brief SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/** \brief SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/** \brief SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/** \brief SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/** \brief SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/** \brief SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/** \brief SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/** \brief SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/** \brief SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/** \brief ICB Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +/** \brief ICB Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[27U]; + __IM uint32_t ITREAD; /*!< Offset: 0xEF0 (R/ ) Integration Read Register */ + uint32_t RESERVED4[1U]; + __OM uint32_t ITWRITE; /*!< Offset: 0xEF8 ( /W) Integration Write Register */ + uint32_t RESERVED5[1U]; + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control Register */ + uint32_t RESERVED6[46U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ + uint32_t RESERVED7[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} ITM_Type; + +/** \brief ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Integration Read Register Definitions */ +#define ITM_ITREAD_AFVALID_Pos 1U /*!< ITM ITREAD: AFVALID Position */ +#define ITM_ITREAD_AFVALID_Msk (1UL << ITM_ITREAD_AFVALID_Pos) /*!< ITM ITREAD: AFVALID Mask */ + +#define ITM_ITREAD_ATREADY_Pos 0U /*!< ITM ITREAD: ATREADY Position */ +#define ITM_ITREAD_ATREADY_Msk (1UL /*<< ITM_ITREAD_ATREADY_Pos*/) /*!< ITM ITREAD: ATREADY Mask */ + +/** \brief ITM Integration Write Register Definitions */ +#define ITM_ITWRITE_AFVALID_Pos 1U /*!< ITM ITWRITE: AFVALID Position */ +#define ITM_ITWRITE_AFVALID_Msk (1UL << ITM_ITWRITE_AFVALID_Pos) /*!< ITM ITWRITE: AFVALID Mask */ + +#define ITM_ITWRITE_ATREADY_Pos 0U /*!< ITM ITWRITE: ATREADY Position */ +#define ITM_ITWRITE_ATREADY_Msk (1UL /*<< ITM_ITWRITE_ATREADY_Pos*/) /*!< ITM ITWRITE: ATREADY Mask */ + +/** \brief ITM Integration Mode Control Register Definitions */ +#define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ +#define ITM_ITCTRL_IME_Msk (1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + __IOM uint32_t VMASK1; /*!< Offset: 0x03C (R/W) Comparator Value Mask 1 */ + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + __IOM uint32_t VMASK3; /*!< Offset: 0x05C (R/W) Comparator Value Mask 3 */ + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED14[968U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ + uint32_t RESERVED15[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/** \brief MemSysCtl Memory System Control Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos 4U /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */ +#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk (1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos) /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/** \brief MemSysCtl Prefetcher Control Register Definitions */ +#define MEMSYSCTL_PFCR_DIS_NLP_Pos 7U /*!< MEMSYSCTL PFCR: DIS_NLP Position */ +#define MEMSYSCTL_PFCR_DIS_NLP_Msk (1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos) /*!< MEMSYSCTL PFCR: DIS_NLP Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/** \brief MemSysCtl ITCM Control Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/** \brief MemSysCtl DTCM Control Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/** \brief MemSysCtl P-AHB Control Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/** \brief MemSysCtl ITGU Control Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/** \brief MemSysCtl ITGU Configuration Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/** \brief MemSysCtl DTGU Control Registers Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/** \brief MemSysCtl DTGU Configuration Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/** \brief PwrModCtl Core Power Domain Low Power State Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/** \brief PwrModCtl Debug Power Domain Low Power State Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __IOM uint32_t EWIC_CR; /*!< Offset: 0x000 (R/W) EWIC Control Register */ + __IOM uint32_t EWIC_ASCR; /*!< Offset: 0x004 (R/W) EWIC Automatic Sequence Control Register */ + __OM uint32_t EWIC_CLRMASK; /*!< Offset: 0x008 ( /W) EWIC Clear Mask Register */ + __IM uint32_t EWIC_NUMID; /*!< Offset: 0x00C (R/ ) EWIC Event Number ID Register */ + uint32_t RESERVED0[124U]; + __IOM uint32_t EWIC_MASKA; /*!< Offset: 0x200 (R/W) EWIC MaskA Register */ + __IOM uint32_t EWIC_MASKn[15]; /*!< Offset: 0x204 (R/W) EWIC Maskn Registers */ + uint32_t RESERVED1[112U]; + __IM uint32_t EWIC_PENDA; /*!< Offset: 0x400 (R/ ) EWIC PendA Event Register */ + __IOM uint32_t EWIC_PENDn[15]; /*!< Offset: 0x404 (R/W) EWIC Pendn Event Registers */ + uint32_t RESERVED2[112U]; + __IM uint32_t EWIC_PSR; /*!< Offset: 0x600 (R/ ) EWIC Pend Summary Register */ +} EWIC_Type; + +/** \brief EWIC Control Register Definitions */ +#define EWIC_EWIC_CR_EN_Pos 0U /*!< EWIC EWIC_CR: EN Position */ +#define EWIC_EWIC_CR_EN_Msk (1UL /*<< EWIC_EWIC_CR_EN_Pos*/) /*!< EWIC EWIC_CR: EN Mask */ + +/** \brief EWIC Automatic Sequence Control Register Definitions */ +#define EWIC_EWIC_ASCR_ASPU_Pos 1U /*!< EWIC EWIC_ASCR: ASPU Position */ +#define EWIC_EWIC_ASCR_ASPU_Msk (1UL << EWIC_EWIC_ASCR_ASPU_Pos) /*!< EWIC EWIC_ASCR: ASPU Mask */ + +#define EWIC_EWIC_ASCR_ASPD_Pos 0U /*!< EWIC EWIC_ASCR: ASPD Position */ +#define EWIC_EWIC_ASCR_ASPD_Msk (1UL /*<< EWIC_EWIC_ASCR_ASPD_Pos*/) /*!< EWIC EWIC_ASCR: ASPD Mask */ + +/** \brief EWIC Event Number ID Register Definitions */ +#define EWIC_EWIC_NUMID_NUMEVENT_Pos 0U /*!< EWIC_NUMID: NUMEVENT Position */ +#define EWIC_EWIC_NUMID_NUMEVENT_Msk (0xFFFFUL /*<< EWIC_EWIC_NUMID_NUMEVENT_Pos*/) /*!< EWIC_NUMID: NUMEVENT Mask */ + +/** \brief EWIC Mask A Register Definitions */ +#define EWIC_EWIC_MASKA_EDBGREQ_Pos 2U /*!< EWIC EWIC_MASKA: EDBGREQ Position */ +#define EWIC_EWIC_MASKA_EDBGREQ_Msk (1UL << EWIC_EWIC_MASKA_EDBGREQ_Pos) /*!< EWIC EWIC_MASKA: EDBGREQ Mask */ + +#define EWIC_EWIC_MASKA_NMI_Pos 1U /*!< EWIC EWIC_MASKA: NMI Position */ +#define EWIC_EWIC_MASKA_NMI_Msk (1UL << EWIC_EWIC_MASKA_NMI_Pos) /*!< EWIC EWIC_MASKA: NMI Mask */ + +#define EWIC_EWIC_MASKA_EVENT_Pos 0U /*!< EWIC EWIC_MASKA: EVENT Position */ +#define EWIC_EWIC_MASKA_EVENT_Msk (1UL /*<< EWIC_EWIC_MASKA_EVENT_Pos*/) /*!< EWIC EWIC_MASKA: EVENT Mask */ + +/** \brief EWIC Mask n Register Definitions */ +#define EWIC_EWIC_MASKn_IRQ_Pos 0U /*!< EWIC EWIC_MASKn: IRQ Position */ +#define EWIC_EWIC_MASKn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EWIC_MASKn_IRQ_Pos*/) /*!< EWIC EWIC_MASKn: IRQ Mask */ + +/** \brief EWIC Pend A Register Definitions */ +#define EWIC_EWIC_PENDA_EDBGREQ_Pos 2U /*!< EWIC EWIC_PENDA: EDBGREQ Position */ +#define EWIC_EWIC_PENDA_EDBGREQ_Msk (1UL << EWIC_EWIC_PENDA_EDBGREQ_Pos) /*!< EWIC EWIC_PENDA: EDBGREQ Mask */ + +#define EWIC_EWIC_PENDA_NMI_Pos 1U /*!< EWIC EWIC_PENDA: NMI Position */ +#define EWIC_EWIC_PENDA_NMI_Msk (1UL << EWIC_EWIC_PENDA_NMI_Pos) /*!< EWIC EWIC_PENDA: NMI Mask */ + +#define EWIC_EWIC_PENDA_EVENT_Pos 0U /*!< EWIC EWIC_PENDA: EVENT Position */ +#define EWIC_EWIC_PENDA_EVENT_Msk (1UL /*<< EWIC_EWIC_PENDA_EVENT_Pos*/) /*!< EWIC EWIC_PENDA: EVENT Mask */ + +/** \brief EWIC Pend n Register Definitions */ +#define EWIC_EWIC_PENDn_IRQ_Pos 0U /*!< EWIC EWIC_PENDn: IRQ Position */ +#define EWIC_EWIC_PENDn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EWIC_PENDn_IRQ_Pos*/) /*!< EWIC EWIC_PENDn: IRQ Mask */ + +/** \brief EWIC Pend Summary Register Definitions */ +#define EWIC_EWIC_PSR_NZ_Pos 1U /*!< EWIC EWIC_PSR: NZ Position */ +#define EWIC_EWIC_PSR_NZ_Msk (0x7FFFUL << EWIC_EWIC_PSR_NZ_Pos) /*!< EWIC EWIC_PSR: NZ Mask */ + +#define EWIC_EWIC_PSR_NZA_Pos 0U /*!< EWIC EWIC_PSR: NZA Position */ +#define EWIC_EWIC_PSR_NZA_Msk (1UL /*<< EWIC_EWIC_PSR_NZA_Pos*/) /*!< EWIC EWIC_PSR: NZA Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_ISA_Type External Wakeup Interrupt Controller (EWIC) interrupt status access registers + \brief Type definitions for the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/ ) Event Mask A Register */ + __IM uint32_t EVENTMASKn[15]; /*!< Offset: 0x084 (R/ ) Event Mask Register */ +} EWIC_ISA_Type; + +/** \brief EWIC_ISA Event Set Pending Register Definitions */ +#define EWIC_ISA_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC_ISA EVENTSPR: EDBGREQ Position */ +#define EWIC_ISA_EVENTSPR_EDBGREQ_Msk (1UL << EWIC_ISA_EVENTSPR_EDBGREQ_Pos) /*!< EWIC_ISA EVENTSPR: EDBGREQ Mask */ + +#define EWIC_ISA_EVENTSPR_NMI_Pos 1U /*!< EWIC_ISA EVENTSPR: NMI Position */ +#define EWIC_ISA_EVENTSPR_NMI_Msk (1UL << EWIC_ISA_EVENTSPR_NMI_Pos) /*!< EWIC_ISA EVENTSPR: NMI Mask */ + +#define EWIC_ISA_EVENTSPR_EVENT_Pos 0U /*!< EWIC_ISA EVENTSPR: EVENT Position */ +#define EWIC_ISA_EVENTSPR_EVENT_Msk (1UL /*<< EWIC_ISA_EVENTSPR_EVENT_Pos*/) /*!< EWIC_ISA EVENTSPR: EVENT Mask */ + +/** \brief EWIC_ISA Event Mask A Register Definitions */ +#define EWIC_ISA_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC_ISA EVENTMASKA: EDBGREQ Position */ +#define EWIC_ISA_EVENTMASKA_EDBGREQ_Msk (1UL << EWIC_ISA_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC_ISA EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_ISA_EVENTMASKA_NMI_Pos 1U /*!< EWIC_ISA EVENTMASKA: NMI Position */ +#define EWIC_ISA_EVENTMASKA_NMI_Msk (1UL << EWIC_ISA_EVENTMASKA_NMI_Pos) /*!< EWIC_ISA EVENTMASKA: NMI Mask */ + +#define EWIC_ISA_EVENTMASKA_EVENT_Pos 0U /*!< EWIC_ISA EVENTMASKA: EVENT Position */ +#define EWIC_ISA_EVENTMASKA_EVENT_Msk (1UL /*<< EWIC_ISA_EVENTMASKA_EVENT_Pos*/) /*!< EWIC_ISA EVENTMASKA: EVENT Mask */ + +/** \brief EWIC_ISA Event Mask n Register Definitions */ +#define EWIC_ISA_EVENTMASKn_IRQ_Pos 0U /*!< EWIC_ISA EVENTMASKn: IRQ Position */ +#define EWIC_ISA_EVENTMASKn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_ISA_EVENTMASKn_IRQ_Pos*/) /*!< EWIC_ISA EVENTMASKn: IRQ Mask */ + +/*@}*/ /* end of group EWIC_ISA_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/** \brief ErrBnk Instruction Cache Error Bank Register 0 Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/** \brief ErrBnk Instruction Cache Error Bank Register 1 Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/** \brief ErrBnk Data Cache Error Bank Register 0 Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/** \brief ErrBnk Data Cache Error Bank Register 1 Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/** \brief ErrBnk TCM Error Bank Register 0 Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x7UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/** \brief ErrBnk TCM Error Bank Register 1 Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x7UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/** \brief PrcCfgInf Processor Configuration Information Selection Register Definitions */ + +/** \brief PrcCfgInf Processor Configuration Information Read Data Register Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup STL_Type Software Test Library Observation Registers + \brief Type definitions for the Software Test Library Observation Registerss (STL) + @{ + */ + +/** + \brief Structure type to access the Software Test Library Observation Registerss (STL). + */ +typedef struct +{ + __IM uint32_t STLNVICPENDOR; /*!< Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register */ + __IM uint32_t STLNVICACTVOR; /*!< Offset: 0x004 (R/ ) NVIC Active Priority Tree Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t STLIDMPUSR; /*!< Offset: 0x010 ( /W) MPU Sample Register */ + __IM uint32_t STLIMPUOR; /*!< Offset: 0x014 (R/ ) MPU Region Hit Register */ + __IM uint32_t STLD0MPUOR; /*!< Offset: 0x018 (R/ ) MPU Memory Attributes Register 0 */ + __IM uint32_t STLD1MPUOR; /*!< Offset: 0x01C (R/ ) MPU Memory Attributes Register 1 */ + __IM uint32_t STLD2MPUOR; /*!< Offset: 0x020 (R/ ) MPU Memory Attributes Register 2 */ + __IM uint32_t STLD3MPUOR; /*!< Offset: 0x024 (R/ ) MPU Memory Attributes Register 3 */ + __IOM uint32_t STLSTBSLOTSR; /*!< Offset: 0x028 (R/W) STB Control Register */ + __IOM uint32_t STLLFDENTRYSR; /*!< Offset: 0x02C (R/W) LFD Control Register */ +} STL_Type; + +/** \brief STL NVIC Pending Priority Tree Register Definitions */ +#define STL_STLNVICPENDOR_VALID_Pos 18U /*!< STL STLNVICPENDOR: VALID Position */ +#define STL_STLNVICPENDOR_VALID_Msk (1UL << STL_STLNVICPENDOR_VALID_Pos) /*!< STL STLNVICPENDOR: VALID Mask */ + +#define STL_STLNVICPENDOR_TARGET_Pos 17U /*!< STL STLNVICPENDOR: TARGET Position */ +#define STL_STLNVICPENDOR_TARGET_Msk (1UL << STL_STLNVICPENDOR_TARGET_Pos) /*!< STL STLNVICPENDOR: TARGET Mask */ + +#define STL_STLNVICPENDOR_PRIORITY_Pos 9U /*!< STL STLNVICPENDOR: PRIORITY Position */ +#define STL_STLNVICPENDOR_PRIORITY_Msk (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos) /*!< STL STLNVICPENDOR: PRIORITY Mask */ + +#define STL_STLNVICPENDOR_INTNUM_Pos 0U /*!< STL STLNVICPENDOR: INTNUM Position */ +#define STL_STLNVICPENDOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */ + +/** \brief STL NVIC Active Priority Tree Register Definitions */ +#define STL_STLNVICACTVOR_VALID_Pos 18U /*!< STL STLNVICACTVOR: VALID Position */ +#define STL_STLNVICACTVOR_VALID_Msk (1UL << STL_STLNVICACTVOR_VALID_Pos) /*!< STL STLNVICACTVOR: VALID Mask */ + +#define STL_STLNVICACTVOR_TARGET_Pos 17U /*!< STL STLNVICACTVOR: TARGET Position */ +#define STL_STLNVICACTVOR_TARGET_Msk (1UL << STL_STLNVICACTVOR_TARGET_Pos) /*!< STL STLNVICACTVOR: TARGET Mask */ + +#define STL_STLNVICACTVOR_PRIORITY_Pos 9U /*!< STL STLNVICACTVOR: PRIORITY Position */ +#define STL_STLNVICACTVOR_PRIORITY_Msk (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos) /*!< STL STLNVICACTVOR: PRIORITY Mask */ + +#define STL_STLNVICACTVOR_INTNUM_Pos 0U /*!< STL STLNVICACTVOR: INTNUM Position */ +#define STL_STLNVICACTVOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */ + +/** \brief STL MPU Sample Register Definitions */ +#define STL_STLIDMPUSR_ADDR_Pos 5U /*!< STL STLIDMPUSR: ADDR Position */ +#define STL_STLIDMPUSR_ADDR_Msk (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos) /*!< STL STLIDMPUSR: ADDR Mask */ + +#define STL_STLIDMPUSR_INSTR_Pos 2U /*!< STL STLIDMPUSR: INSTR Position */ +#define STL_STLIDMPUSR_INSTR_Msk (1UL << STL_STLIDMPUSR_INSTR_Pos) /*!< STL STLIDMPUSR: INSTR Mask */ + +#define STL_STLIDMPUSR_DATA_Pos 1U /*!< STL STLIDMPUSR: DATA Position */ +#define STL_STLIDMPUSR_DATA_Msk (1UL << STL_STLIDMPUSR_DATA_Pos) /*!< STL STLIDMPUSR: DATA Mask */ + +/** \brief STL MPU Region Hit Register Definitions */ +#define STL_STLIMPUOR_HITREGION_Pos 9U /*!< STL STLIMPUOR: HITREGION Position */ +#define STL_STLIMPUOR_HITREGION_Msk (0xFFUL << STL_STLIMPUOR_HITREGION_Pos) /*!< STL STLIMPUOR: HITREGION Mask */ + +#define STL_STLIMPUOR_ATTR_Pos 0U /*!< STL STLIMPUOR: ATTR Position */ +#define STL_STLIMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/) /*!< STL STLIMPUOR: ATTR Mask */ + +/** \brief STL MPU Memory Attributes Register 0 Definitions */ +#define STL_STLD0MPUOR_HITREGION_Pos 9U /*!< STL STLD0MPUOR: HITREGION Position */ +#define STL_STLD0MPUOR_HITREGION_Msk (0xFFUL << STL_STLD0MPUOR_HITREGION_Pos) /*!< STL STLD0MPUOR: HITREGION Mask */ + +#define STL_STLD0MPUOR_ATTR_Pos 0U /*!< STL STLD0MPUOR: ATTR Position */ +#define STL_STLD0MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD0MPUOR_ATTR_Pos*/) /*!< STL STLD0MPUOR: ATTR Mask */ + +/** \brief STL MPU Memory Attributes Register 1 Definitions */ +#define STL_STLD1MPUOR_HITREGION_Pos 9U /*!< STL STLD1MPUOR: HITREGION Position */ +#define STL_STLD1MPUOR_HITREGION_Msk (0xFFUL << STL_STLD1MPUOR_HITREGION_Pos) /*!< STL STLD1MPUOR: HITREGION Mask */ + +#define STL_STLD1MPUOR_ATTR_Pos 0U /*!< STL STLD1MPUOR: ATTR Position */ +#define STL_STLD1MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD1MPUOR_ATTR_Pos*/) /*!< STL STLD1MPUOR: ATTR Mask */ + +/** \brief STL MPU Memory Attributes Register 2 Definitions */ +#define STL_STLD2MPUOR_HITREGION_Pos 9U /*!< STL STLD2MPUOR: HITREGION Position */ +#define STL_STLD2MPUOR_HITREGION_Msk (0xFFUL << STL_STLD2MPUOR_HITREGION_Pos) /*!< STL STLD2MPUOR: HITREGION Mask */ + +#define STL_STLD2MPUOR_ATTR_Pos 0U /*!< STL STLD2MPUOR: ATTR Position */ +#define STL_STLD2MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD2MPUOR_ATTR_Pos*/) /*!< STL STLD2MPUOR: ATTR Mask */ + +/** \brief STL MPU Memory Attributes Register 3 Definitions */ +#define STL_STLD3MPUOR_HITREGION_Pos 9U /*!< STL STLD3MPUOR: HITREGION Position */ +#define STL_STLD3MPUOR_HITREGION_Msk (0xFFUL << STL_STLD3MPUOR_HITREGION_Pos) /*!< STL STLD3MPUOR: HITREGION Mask */ + +#define STL_STLD3MPUOR_ATTR_Pos 0U /*!< STL STLD3MPUOR: ATTR Position */ +#define STL_STLD3MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD3MPUOR_ATTR_Pos*/) /*!< STL STLD3MPUOR: ATTR Mask */ + +/** \brief STL STB Control Register Definitions */ +#define STL_STLSTBSLOTSR_VALID_Pos 4U /*!< STL STLSTBSLOTSR: VALID Position */ +#define STL_STLSTBSLOTSR_VALID_Msk (1UL << STL_STLSTBSLOTSR_VALID_Pos) /*!< STL STLSTBSLOTSR: VALID Mask */ + +#define STL_STLSTBSLOTSR_STBSLOTNUM_Pos 0U /*!< STL STLSTBSLOTSR: STBSLOTNUM Position */ +#define STL_STLSTBSLOTSR_STBSLOTNUM_Msk (0xFUL /*<< STL_STLSTBSLOTSR_STBSLOTNUM_Pos*/) /*!< STL STLSTBSLOTSR: STBSLOTNUM Mask */ + +/** \brief STL LFD Control Register Definitions */ +#define STL_STLLFDENTRYSR_VALID_Pos 4U /*!< STL STLLFDENTRYSR: VALID Position */ +#define STL_STLLFDENTRYSR_VALID_Msk (1UL << STL_STLLFDENTRYSR_VALID_Pos) /*!< STL STLLFDENTRYSR: VALID Mask */ + +#define STL_STLLFDENTRYSR_LFDENTRYNUM_Pos 0U /*!< STL STLLFDENTRYSR: LFDENTRYNUM Position */ +#define STL_STLLFDENTRYSR_LFDENTRYNUM_Msk (0xFUL /*<< STL_STLLFDENTRYSR_LFDENTRYNUM_Pos*/) /*!< STL STLLFDENTRYSR: LFDENTRYNUM Mask */ +/*@}*/ /* end of group STL_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ +#define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU Periodic Synchronization Control Register Definitions */ +#define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */ +#define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */ +#define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */ +#define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */ +#define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */ +#define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */ + +#define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */ +#define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 0 Definitions */ +#define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ +#define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ +#define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ +#define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ + +#define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ +#define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU Claim Tag Set Register Definitions */ +#define TPIU_CLAIMSET_SET_Pos 0U /*!< TPIU CLAIMSET: SET Position */ +#define TPIU_CLAIMSET_SET_Msk (0xFUL /*<< TPIU_CLAIMSET_SET_Pos*/) /*!< TPIU CLAIMSET: SET Mask */ + +/** \brief TPIU Claim Tag Clear Register Definitions */ +#define TPIU_CLAIMCLR_CLR_Pos 0U /*!< TPIU CLAIMCLR: CLR Position */ +#define TPIU_CLAIMCLR_CLR_Msk (0xFUL /*<< TPIU_CLAIMCLR_CLR_Pos*/) /*!< TPIU CLAIMCLR: CLR Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */ +#define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) Device Type Register */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/** \brief MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */ + +/** \brief MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/** \brief MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/** \brief SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/** \brief SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/** \brief SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/** \brief SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/** \brief SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/** \brief SAU Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/** \brief FPU Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/** \brief FPU Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/** \brief FPU Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/** \brief FPU Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ + +/** \brief FPU Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/** \brief FPU Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/** \brief DCB Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/** \brief DCB Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/** \brief DCB Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + uint32_t RESERVED1[3U]; + __IM uint32_t DDEVTYPE; /*!< Offset: 0x01C (R/ ) SCS Device Type Register */ +} DIB_Type; + +/** \brief DIB Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/** \brief DIB SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/** \brief DIB SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_ISA_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller interrupt status access Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define STL_BASE (0xE001E800UL) /*!< Software Test Library Base Address */ + #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ + #define EWIC_BASE (0xE0047000UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC_ISA ((EWIC_ISA_Type *) EWIC_ISA_BASE ) /*!< EWIC interrupt status access struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define STL ((STL_Type *) STL_BASE ) /*!< Software Test Library configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; + __OM uint32_t DSCEMCR; + __IOM uint32_t DAUTHCTRL; + __IOM uint32_t DSCSR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos DCB_DHCSR_S_RESTART_ST_Pos +#define CoreDebug_DHCSR_S_RESTART_ST_Msk DCB_DHCSR_S_RESTART_ST_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_FPD_Pos DCB_DHCSR_S_FPD_Pos +#define CoreDebug_DHCSR_S_FPD_Msk DCB_DHCSR_S_FPD_Msk + +#define CoreDebug_DHCSR_S_SUIDE_Pos DCB_DHCSR_S_SUIDE_Pos +#define CoreDebug_DHCSR_S_SUIDE_Msk DCB_DHCSR_S_SUIDE_Msk + +#define CoreDebug_DHCSR_S_NSUIDE_Pos DCB_DHCSR_S_NSUIDE_Pos +#define CoreDebug_DHCSR_S_NSUIDE_Msk DCB_DHCSR_S_NSUIDE_Msk + +#define CoreDebug_DHCSR_S_SDE_Pos DCB_DHCSR_S_SDE_Pos +#define CoreDebug_DHCSR_S_SDE_Msk DCB_DHCSR_S_SDE_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_PMOV_Pos DCB_DHCSR_C_PMOV_Pos +#define CoreDebug_DHCSR_C_PMOV_Msk DCB_DHCSR_C_PMOV_Msk + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos +#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk + +#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos +#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk + +#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos +#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk + +#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos +#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos +#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk + +#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos +#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk + +#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos +#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk + +#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos +#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos +#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk + +#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos +#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos DCB_DSCEMCR_CLR_MON_REQ_Pos +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk DCB_DSCEMCR_CLR_MON_REQ_Msk + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos DCB_DSCEMCR_CLR_MON_PEND_Pos +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk DCB_DSCEMCR_CLR_MON_PEND_Msk + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos DCB_DSCEMCR_SET_MON_REQ_Pos +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk DCB_DSCEMCR_SET_MON_REQ_Msk + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos DCB_DSCEMCR_SET_MON_PEND_Pos +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk DCB_DSCEMCR_SET_MON_PEND_Msk + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos DCB_DAUTHCTRL_UIDEN_Pos +#define CoreDebug_DAUTHCTRL_UIDEN_Msk DCB_DAUTHCTRL_UIDEN_Msk + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos DCB_DAUTHCTRL_UIDAPEN_Pos +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk DCB_DAUTHCTRL_UIDAPEN_Msk + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos DCB_DAUTHCTRL_FSDMA_Pos +#define CoreDebug_DAUTHCTRL_FSDMA_Msk DCB_DAUTHCTRL_FSDMA_Msk + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos DCB_DAUTHCTRL_INTSPNIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk DCB_DAUTHCTRL_INTSPNIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos DCB_DAUTHCTRL_SPNIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk DCB_DAUTHCTRL_SPNIDENSEL_Msk + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos DCB_DAUTHCTRL_INTSPIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk DCB_DAUTHCTRL_INTSPIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos DCB_DAUTHCTRL_SPIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk DCB_DAUTHCTRL_SPIDENSEL_Msk + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos DCB_DSCSR_CDS_Pos +#define CoreDebug_DSCSR_CDS_Msk DCB_DSCSR_CDS_Msk + +#define CoreDebug_DSCSR_SBRSEL_Pos DCB_DSCSR_SBRSEL_Pos +#define CoreDebug_DSCSR_SBRSEL_Msk DCB_DSCSR_SBRSEL_Msk + +#define CoreDebug_DSCSR_SBRSELEN_Pos DCB_DSCSR_SBRSELEN_Pos +#define CoreDebug_DSCSR_SBRSELEN_Msk DCB_DSCSR_SBRSELEN_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS) +#endif + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + + #include "m-profile/armv8m_mpu.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "m-profile/armv8m_pmu.h" + +/** + \brief Cortex-M85 PMU events + \note Architectural PMU events can be found in armv8m_pmu.h +*/ + +#define ARMCM85_PMU_ECC_ERR 0xC000 /*!< One or more Error Correcting Code (ECC) errors detected */ +#define ARMCM85_PMU_ECC_ERR_MBIT 0xC001 /*!< One or more multi-bit ECC errors detected */ +#define ARMCM85_PMU_ECC_ERR_DCACHE 0xC010 /*!< One or more ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_ICACHE 0xC011 /*!< One or more ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DCACHE 0xC012 /*!< One or more multi-bit ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ICACHE 0xC013 /*!< One or more multi-bit ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_DTCM 0xC020 /*!< One or more ECC errors in the Data Tightly Coupled Memory (DTCM) */ +#define ARMCM85_PMU_ECC_ERR_ITCM 0xC021 /*!< One or more ECC errors in the Instruction Tightly Coupled Memory (ITCM) */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DTCM 0xC022 /*!< One or more multi-bit ECC errors in the DTCM */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ITCM 0xC023 /*!< One or more multi-bit ECC errors in the ITCM */ +#define ARMCM85_PMU_PF_LINEFILL 0xC100 /*!< The prefetcher starts a line-fill */ +#define ARMCM85_PMU_PF_CANCEL 0xC101 /*!< The prefetcher stops prefetching */ +#define ARMCM85_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM85_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM85_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM85_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM85_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access on the P-AHB write interface */ +#define ARMCM85_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM85_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM85_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM85_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ +#define ARMCM85_PMU_FUSED_INST_RETIRED 0xC500 /*!< Fused instructions architecturally executed */ +#define ARMCM85_PMU_BR_INDIRECT 0xC501 /*!< Indirect branch instruction architecturally executed */ +#define ARMCM85_PMU_BTAC_HIT 0xC502 /*!< BTAC branch predictor hit */ +#define ARMCM85_PMU_BTAC_HIT_RETURNS 0xC503 /*!< Return branch hits BTAC */ +#define ARMCM85_PMU_BTAC_HIT_CALLS 0xC504 /*!< Call branch hits BTAC */ +#define ARMCM85_PMU_BTAC_HIT_INDIRECT 0xC505 /*!< Indirect branch hits BTACT */ +#define ARMCM85_PMU_BTAC_NEW_ALLOC 0xC506 /*!< New allocation to BTAC */ +#define ARMCM85_PMU_BR_IND_MIS_PRED 0xC507 /*!< Indirect branch mis-predicted */ +#define ARMCM85_PMU_BR_RETURN_MIS_PRED 0xC508 /*!< Return branch mis-predicted */ +#define ARMCM85_PMU_BR_BTAC_OFFSET_OVERFLOW 0xC509 /*!< Branch does not allocate in BTAC due to offset overflow */ +#define ARMCM85_PMU_STB_FULL_STALL_AXI 0xC50A /*!< STore Buffer (STB) full with AXI requests causing CPU to stall */ +#define ARMCM85_PMU_STB_FULL_STALL_TCM 0xC50B /*!< STB full with TCM requests causing CPU to stall */ +#define ARMCM85_PMU_CPU_STALLED_AHBS 0xC50C /*!< CPU is stalled because TCM access through AHBS */ +#define ARMCM85_PMU_AHBS_STALLED_CPU 0xC50D /*!< AHBS is stalled due to TCM access by CPU */ +#define ARMCM85_PMU_BR_INTERSTATING_MIS_PRED 0xC50E /*!< Inter-stating branch is mis-predicted. */ +#define ARMCM85_PMU_DWT_STALL 0xC50F /*!< Data Watchpoint and Trace (DWT) stall */ +#define ARMCM85_PMU_DWT_FLUSH 0xC510 /*!< DWT flush */ +#define ARMCM85_PMU_ETM_STALL 0xC511 /*!< Embedded Trace Macrocell (ETM) stall */ +#define ARMCM85_PMU_ETM_FLUSH 0xC512 /*!< ETM flush */ +#define ARMCM85_PMU_ADDRESS_BANK_CONFLICT 0xC513 /*!< Bank conflict prevents memory instruction dual issue */ +#define ARMCM85_PMU_BLOCKED_DUAL_ISSUE 0xC514 /*!< Dual instruction issuing is prevented */ +#define ARMCM85_PMU_FP_CONTEXT_TRIGGER 0xC515 /*!< Floating Point Context is created */ +#define ARMCM85_PMU_TAIL_CHAIN 0xC516 /*!< New exception is handled without first unstacking */ +#define ARMCM85_PMU_LATE_ARRIVAL 0xC517 /*!< Late-arriving exception taken during exception entry */ +#define ARMCM85_PMU_INT_STALL_FAULT 0xC518 /*!< Delayed exception entry due to ongoing fault processing */ +#define ARMCM85_PMU_INT_STALL_DEV 0xC519 /*!< Delayed exception entry due to outstanding device access */ +#define ARMCM85_PMU_PAC_STALL 0xC51A /*!< Stall caused by authentication code computation */ +#define ARMCM85_PMU_PAC_RETIRED 0xC51B /*!< PAC instruction architecturally executed */ +#define ARMCM85_PMU_AUT_RETIRED 0xC51C /*!< AUT instruction architecturally executed */ +#define ARMCM85_PMU_BTI_RETIRED 0xC51D /*!< BTI instruction architecturally executed */ +#define ARMCM85_PMU_PF_NL_MODE 0xC51E /*!< Prefetch in next line mode */ +#define ARMCM85_PMU_PF_STREAM_MODE 0xC51F /*!< Prefetch in stream mode */ +#define ARMCM85_PMU_PF_BUFF_CACHE_HIT 0xC520 /*!< Prefetch request that hit in the cache */ +#define ARMCM85_PMU_PF_REQ_LFB_HIT 0xC521 /*!< Prefetch request that hit in line fill buffers */ +#define ARMCM85_PMU_PF_BUFF_FULL 0xC522 /*!< Number of times prefetch buffer is full */ +#define ARMCM85_PMU_PF_REQ_DCACHE_HIT 0xC523 /*!< Generated prefetch request address that hit in D-Cache */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + #include "m-profile/armv7m_cachel1.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################### PAC Key functions ########################### */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) +#include "m-profile/armv81m_pac.h" +#endif + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_sc000.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_sc000.h new file mode 100644 index 00000000000..4d85c48d081 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_sc000.h @@ -0,0 +1,1055 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS SC000 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ + +#define __CORTEX_SC (000U) /*!< Cortex Secure Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/** \brief SCnSCB Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/** \brief MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "m-profile/armv7m_mpu.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_sc300.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_sc300.h new file mode 100644 index 00000000000..670d9114133 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_sc300.h @@ -0,0 +1,2028 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS SC300 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ + +#define __CORTEX_SC (300U) /*!< Cortex Secure Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IPR[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/** \brief SCnSCB Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/** \brief SCnSCB Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Lock Status Register */ +} ITM_Type; + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Lock Status Register Definitions */ +#define ITM_LSR_BYTEACC_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_BYTEACC_Msk (1UL << ITM_LSR_BYTEACC_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_ACCESS_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_ACCESS_Msk (1UL << ITM_LSR_ACCESS_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_PRESENT_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_PRESENT_Msk (1UL /*<< ITM_LSR_PRESENT_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration ETM Data Register Definitions (FIFO0) */ +#define TPIU_FIFO0_ITM_ATVALID_Pos 29U /*!< TPIU FIFO0: ITM_ATVALID Position */ +#define TPIU_FIFO0_ITM_ATVALID_Msk (1UL << TPIU_FIFO0_ITM_ATVALID_Pos) /*!< TPIU FIFO0: ITM_ATVALID Mask */ + +#define TPIU_FIFO0_ITM_bytecount_Pos 27U /*!< TPIU FIFO0: ITM_bytecount Position */ +#define TPIU_FIFO0_ITM_bytecount_Msk (0x3UL << TPIU_FIFO0_ITM_bytecount_Pos) /*!< TPIU FIFO0: ITM_bytecount Mask */ + +#define TPIU_FIFO0_ETM_ATVALID_Pos 26U /*!< TPIU FIFO0: ETM_ATVALID Position */ +#define TPIU_FIFO0_ETM_ATVALID_Msk (1UL << TPIU_FIFO0_ETM_ATVALID_Pos) /*!< TPIU FIFO0: ETM_ATVALID Mask */ + +#define TPIU_FIFO0_ETM_bytecount_Pos 24U /*!< TPIU FIFO0: ETM_bytecount Position */ +#define TPIU_FIFO0_ETM_bytecount_Msk (0x3UL << TPIU_FIFO0_ETM_bytecount_Pos) /*!< TPIU FIFO0: ETM_bytecount Mask */ + +#define TPIU_FIFO0_ETM2_Pos 16U /*!< TPIU FIFO0: ETM2 Position */ +#define TPIU_FIFO0_ETM2_Msk (0xFFUL << TPIU_FIFO0_ETM2_Pos) /*!< TPIU FIFO0: ETM2 Mask */ + +#define TPIU_FIFO0_ETM1_Pos 8U /*!< TPIU FIFO0: ETM1 Position */ +#define TPIU_FIFO0_ETM1_Msk (0xFFUL << TPIU_FIFO0_ETM1_Pos) /*!< TPIU FIFO0: ETM1 Mask */ + +#define TPIU_FIFO0_ETM0_Pos 0U /*!< TPIU FIFO0: ETM0 Position */ +#define TPIU_FIFO0_ETM0_Msk (0xFFUL /*<< TPIU_FIFO0_ETM0_Pos*/) /*!< TPIU FIFO0: ETM0 Mask */ + +/** \brief TPIU ITATBCTR2 Register Definitions */ +#define TPIU_ITATBCTR2_ATREADY2_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2 Position */ +#define TPIU_ITATBCTR2_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2 Mask */ + +#define TPIU_ITATBCTR2_ATREADY1_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1 Position */ +#define TPIU_ITATBCTR2_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1 Mask */ + +/** \brief TPIU Integration ITM Data Register Definitions (FIFO1) */ +#define TPIU_FIFO1_ITM_ATVALID_Pos 29U /*!< TPIU FIFO1: ITM_ATVALID Position */ +#define TPIU_FIFO1_ITM_ATVALID_Msk (1UL << TPIU_FIFO1_ITM_ATVALID_Pos) /*!< TPIU FIFO1: ITM_ATVALID Mask */ + +#define TPIU_FIFO1_ITM_bytecount_Pos 27U /*!< TPIU FIFO1: ITM_bytecount Position */ +#define TPIU_FIFO1_ITM_bytecount_Msk (0x3UL << TPIU_FIFO1_ITM_bytecount_Pos) /*!< TPIU FIFO1: ITM_bytecount Mask */ + +#define TPIU_FIFO1_ETM_ATVALID_Pos 26U /*!< TPIU FIFO1: ETM_ATVALID Position */ +#define TPIU_FIFO1_ETM_ATVALID_Msk (1UL << TPIU_FIFO1_ETM_ATVALID_Pos) /*!< TPIU FIFO1: ETM_ATVALID Mask */ + +#define TPIU_FIFO1_ETM_bytecount_Pos 24U /*!< TPIU FIFO1: ETM_bytecount Position */ +#define TPIU_FIFO1_ETM_bytecount_Msk (0x3UL << TPIU_FIFO1_ETM_bytecount_Pos) /*!< TPIU FIFO1: ETM_bytecount Mask */ + +#define TPIU_FIFO1_ITM2_Pos 16U /*!< TPIU FIFO1: ITM2 Position */ +#define TPIU_FIFO1_ITM2_Msk (0xFFUL << TPIU_FIFO1_ITM2_Pos) /*!< TPIU FIFO1: ITM2 Mask */ + +#define TPIU_FIFO1_ITM1_Pos 8U /*!< TPIU FIFO1: ITM1 Position */ +#define TPIU_FIFO1_ITM1_Msk (0xFFUL << TPIU_FIFO1_ITM1_Pos) /*!< TPIU FIFO1: ITM1 Mask */ + +#define TPIU_FIFO1_ITM0_Pos 0U /*!< TPIU FIFO1: ITM0 Position */ +#define TPIU_FIFO1_ITM0_Msk (0xFFUL /*<< TPIU_FIFO1_ITM0_Pos*/) /*!< TPIU FIFO1: ITM0 Mask */ + +/** \brief TPIU ITATBCTR0 Register Definitions */ +#define TPIU_ITATBCTR0_ATREADY2_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2 Position */ +#define TPIU_ITATBCTR0_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2 Mask */ + +#define TPIU_ITATBCTR0_ATREADY1_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1 Position */ +#define TPIU_ITATBCTR0_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1 Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_MinBufSz_Pos 6U /*!< TPIU DEVID: MinBufSz Position */ +#define TPIU_DEVID_MinBufSz_Msk (0x7UL << TPIU_DEVID_MinBufSz_Pos) /*!< TPIU DEVID: MinBufSz Mask */ + +#define TPIU_DEVID_AsynClkIn_Pos 5U /*!< TPIU DEVID: AsynClkIn Position */ +#define TPIU_DEVID_AsynClkIn_Msk (1UL << TPIU_DEVID_AsynClkIn_Pos) /*!< TPIU DEVID: AsynClkIn Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/** \brief MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ +#define DCB_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ +#define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos +#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk + +#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos +#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk + +#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos +#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk + +#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos +#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos +#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk + +#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos +#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk + +#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos +#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk + +#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos +#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos +#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk + +#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos +#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "m-profile/armv7m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_starmc1.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_starmc1.h new file mode 100644 index 00000000000..3b4e93e4135 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/core_starmc1.h @@ -0,0 +1,3614 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. + * Copyright (c) 2018-2022 Arm China. + * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS ArmChina STAR-MC1 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_STAR_H_GENERIC +#define __CORE_STAR_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup STAR-MC1 + @{ + */ + +#include "cmsis_version.h" + +/* Macro Define for STAR-MC1 */ + +#define __STAR_MC (1U) /*!< STAR-MC Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_STAR_H_DEPENDANT +#define __CORE_STAR_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __STAR_REV + #define __STAR_REV 0x0000U + #warning "__STAR_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group STAR-MC1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for STAR-MC1 processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED_ADD1[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: F00-D00=0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +typedef struct +{ + __IOM uint32_t CACR; /*!< Offset: 0x0 (R/W) L1 Cache Control Register */ + __IOM uint32_t ITCMCR; /*!< Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers */ +} EMSS_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/** \brief SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/** \brief SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +#define SCB_CLIDR_IC_Pos 0U /*!< SCB CLIDR: IC Position */ +#define SCB_CLIDR_IC_Msk (1UL << SCB_CLIDR_IC_Pos) /*!< SCB CLIDR: IC Mask */ + +#define SCB_CLIDR_DC_Pos 1U /*!< SCB CLIDR: DC Position */ +#define SCB_CLIDR_DC_Msk (1UL << SCB_CLIDR_DC_Pos) /*!< SCB CLIDR: DC Mask */ + +/** \brief SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/** \brief SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/** \brief SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/** \brief SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/** \brief SCB D-Cache line Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_LEVEL_Pos 1U /*!< SCB DCISW: Level Position */ +#define SCB_DCISW_LEVEL_Msk (7UL << SCB_DCISW_LEVEL_Pos) /*!< SCB DCISW: Level Mask */ + +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0xFFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/** \brief SCB D-Cache Clean line by Set-way Register Definitions */ +#define SCB_DCCSW_LEVEL_Pos 1U /*!< SCB DCCSW: Level Position */ +#define SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos) /*!< SCB DCCSW: Level Mask */ + +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_LEVEL_Pos 1U /*!< SCB DCCISW: Level Position */ +#define SCB_DCCISW_LEVEL_Msk (7UL << SCB_DCCISW_LEVEL_Pos) /*!< SCB DCCISW: Level Mask */ + +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0xFFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* ArmChina: Implementation Defined */ +/** \brief Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/** \brief Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/** \brief L1 Cache Control Register Definitions */ +#define SCB_CACR_DCCLEAN_Pos 16U /*!< SCB CACR: DCCLEAN Position */ +#define SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCCLEAN Mask */ + +#define SCB_CACR_ICACTIVE_Pos 13U /*!< SCB CACR: ICACTIVE Position */ +#define SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: ICACTIVE Mask */ + +#define SCB_CACR_DCACTIVE_Pos 12U /*!< SCB CACR: DCACTIVE Position */ +#define SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCACTIVE Mask */ + +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/** \brief SCnSCB Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} ITM_Type; + +/** \brief ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ +#define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU Periodic Synchronization Control Register Definitions */ +#define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */ +#define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */ +#define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */ +#define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */ +#define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */ +#define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */ + +#define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */ +#define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 0 Definitions */ +#define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ +#define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ +#define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ +#define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ + +#define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ +#define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */ +#define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/** \brief MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */ + +/** \brief MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/** \brief MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/** \brief SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/** \brief SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/** \brief SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/** \brief SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/** \brief SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/** \brief SAU Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/** \brief FPU Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/** \brief FPU Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/** \brief FPU Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/** \brief FPU Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ + +#define FPU_MVFR0_FPShortvec_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_FPShortvec_Msk (0xFUL << FPU_MVFR0_FPShortvec_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPExceptrap_Pos 12U /*!< MVFR0: Exception trapping bits Position */ +#define FPU_MVFR0_FPExceptrap_Msk (0xFUL << FPU_MVFR0_FPExceptrap_Pos) /*!< MVFR0: Exception trapping bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ + +/** \brief FPU Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/** \brief FPU Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/** \brief DCB Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/** \brief DCB Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/** \brief DIB SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/** \brief DIB SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/** \brief DIB Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/** \brief DIB SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/** \brief DIB SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define EMSS_BASE (0xE001E000UL) /*!AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/** + \brief Software Reset + \details Initiates a system reset request to reset the CPU. + */ +__NO_RETURN __STATIC_INLINE void __SW_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk) | /* Keep BFHFNMINS unchanged. Use this Reset function in case your case need to keep it */ + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */ + SCB_AIRCR_SYSRESETREQ_Msk ); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + + #include "m-profile/armv8m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv7m_cachel1.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv7m_cachel1.h new file mode 100644 index 00000000000..d7338a72e0a --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv7m_cachel1.h @@ -0,0 +1,439 @@ +/* + * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Level 1 Cache API for Armv7-M and later + */ + +#ifndef ARM_ARMV7M_CACHEL1_H +#define ARM_ARMV7M_CACHEL1_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + struct { + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + } locals + #if ((defined(__GNUC__) || defined(__clang__)) && !defined(__OPTIMIZE__)) + __ALIGNED(__SCB_DCACHE_LINE_SIZE) + #endif + ; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + #if !defined(__OPTIMIZE__) + /* + * For the endless loop issue with no optimization builds. + * More details, see https://github.com/ARM-software/CMSIS_5/issues/620 + * + * The issue only happens when local variables are in stack. If + * local variables are saved in general purpose register, then the function + * is OK. + * + * When local variables are in stack, after disabling the cache, flush the + * local variables cache line for data consistency. + */ + /* Clean and invalidate the local variable cache. */ + #if defined(__ICCARM__) + /* As we can't align the stack to the cache line size, invalidate each of the variables */ + SCB->DCCIMVAC = (uint32_t)&locals.sets; + SCB->DCCIMVAC = (uint32_t)&locals.ways; + SCB->DCCIMVAC = (uint32_t)&locals.ccsidr; + #else + SCB->DCCIMVAC = (uint32_t)&locals; + #endif + __DSB(); + __ISB(); + #endif + + locals.ccsidr = SCB->CCSIDR; + /* clean & invalidate D-Cache */ + locals.sets = (uint32_t)(CCSIDR_SETS(locals.ccsidr)); + do { + locals.ways = (uint32_t)(CCSIDR_WAYS(locals.ccsidr)); + do { + SCB->DCCISW = (((locals.sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((locals.ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (locals.ways-- != 0U); + } while(locals.sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_ARMV7M_CACHEL1_H */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv7m_mpu.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv7m_mpu.h new file mode 100644 index 00000000000..5a4eba231c1 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv7m_mpu.h @@ -0,0 +1,273 @@ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) MPU API for Armv7-M MPU + */ + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv81m_pac.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv81m_pac.h new file mode 100644 index 00000000000..648cf886476 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv81m_pac.h @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) PAC key functions for Armv8.1-M PAC extension + */ + +#ifndef PAC_ARMV81_H +#define PAC_ARMV81_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +/* ################### PAC Key functions ########################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions + \brief Functions that access the PAC keys. + @{ + */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) + +/** + \brief read the PAC key used for privileged mode + \details Reads the PAC key stored in the PAC_KEY_P registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode + \details writes the given PAC key to the PAC_KEY_P registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode + \details Reads the PAC key stored in the PAC_KEY_U registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode + \details writes the given PAC key to the PAC_KEY_U registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + +/** + \brief read the PAC key used for privileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */ + +#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */ + +/*@} end of CMSIS_Core_PacKeyFunctions */ + + +#endif /* PAC_ARMV81_H */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv8m_mpu.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv8m_mpu.h new file mode 100644 index 00000000000..d743af12c78 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv8m_mpu.h @@ -0,0 +1,421 @@ +/* + * Copyright (c) 2017-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) MPU API for Armv8-M and Armv8.1-M MPU + */ + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for Normal memory, Outer and Inner cacheability. +* \param NT Non-Transient: Set to 1 for Non-transient data. Set to 0 for Transient data. +* \param WB Write-Back: Set to 1 to use a Write-Back policy. Set to 0 to use a Write-Through policy. +* \param RA Read Allocation: Set to 1 to enable cache allocation on read miss. Set to 0 to disable cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to enable cache allocation on write miss. Set to 0 to disable cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Normal memory outer-cacheable and inner-cacheable attributes +* WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate +*/ +#define MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE (0b0100) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA (0b0010) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_WA (0b0001) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA (0b0011) +#define MPU_ATTR_NORMAL_OUTER_WT_RA (0b1010) +#define MPU_ATTR_NORMAL_OUTER_WT_WA (0b1001) +#define MPU_ATTR_NORMAL_OUTER_WT_RA_WA (0b1011) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA (0b0101) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_WA (0b0110) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA (0b0111) +#define MPU_ATTR_NORMAL_OUTER_WB_RA (0b1101) +#define MPU_ATTR_NORMAL_OUTER_WB_WA (0b1110) +#define MPU_ATTR_NORMAL_OUTER_WB_RA_WA (0b1111) +#define MPU_ATTR_NORMAL_INNER_NON_CACHEABLE (0b0100) +#define MPU_ATTR_NORMAL_INNER_WT_TR_RA (0b0010) +#define MPU_ATTR_NORMAL_INNER_WT_TR_WA (0b0001) +#define MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA (0b0011) +#define MPU_ATTR_NORMAL_INNER_WT_RA (0b1010) +#define MPU_ATTR_NORMAL_INNER_WT_WA (0b1001) +#define MPU_ATTR_NORMAL_INNER_WT_RA_WA (0b1011) +#define MPU_ATTR_NORMAL_INNER_WB_TR_RA (0b0101) +#define MPU_ATTR_NORMAL_INNER_WB_TR_WA (0b0110) +#define MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA (0b0111) +#define MPU_ATTR_NORMAL_INNER_WB_RA (0b1101) +#define MPU_ATTR_NORMAL_INNER_WB_WA (0b1110) +#define MPU_ATTR_NORMAL_INNER_WB_RA_WA (0b1111) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/* \brief Specifies MAIR_ATTR number */ +#define MAIR_ATTR(x) ((x > 7 || x < 0) ? 0 : x) + +/** + * Shareability + */ +/** \brief Normal memory, non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory, outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory, inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** + * Access permissions + * AP = Access permission, RO = Read-only, RW = Read/Write, NP = Any privilege, PO = Privileged code only + */ +/** \brief Normal memory, read/write */ +#define ARM_MPU_AP_RW (0U) + +/** \brief Normal memory, read-only */ +#define ARM_MPU_AP_RO (1U) + +/** \brief Normal memory, any privilege level */ +#define ARM_MPU_AP_NP (1U) + +/** \brief Normal memory, privileged access only */ +#define ARM_MPU_AP_PO (0U) + +/* + * Execute-never + * XN = Execute-never, EX = Executable + */ +/** \brief Normal memory, Execution only permitted if read permitted */ +#define ARM_MPU_XN (1U) + +/** \brief Normal memory, Execution only permitted if read permitted */ +#define ARM_MPU_EX (0U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. Set to 0 for a read/write memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. Set to 0 for privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. Set to 0 for a read/write memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. Set to 0 for privileged memory region. +* \param XN eXecute Never: Set to 1 for a non-executable memory region. Set to 0 for an executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** + \brief Read MPU Type Register + \return Number of MPU regions +*/ +__STATIC_INLINE uint32_t ARM_MPU_TYPE() +{ + return ((MPU->TYPE) >> 8); +} + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv8m_pmu.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv8m_pmu.h new file mode 100644 index 00000000000..fb165331730 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv8m_pmu.h @@ -0,0 +1,335 @@ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) PMU API for Armv8.1-M PMU + */ + +#ifndef ARM_PMU_ARMV8_H +#define ARM_PMU_ARMV8_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +/** + * \brief PMU Events + * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. + * */ + +#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ +#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ +#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ +#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ +#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ +#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ +#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ +#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ +#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ +#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ +#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ +#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ +#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ +#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ +#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ +#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ +#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ +#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ +#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ +#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ +#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ +#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ +#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ +#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ +#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ +#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ +#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ +#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ +#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ +#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ +#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ +#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ +#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ +#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ +#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ +#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ +#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ +#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ +#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ +#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ +#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ +#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ +#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ +#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ +#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ +#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ +#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ +#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ +#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ +#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ +#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ +#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ +#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ +#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ +#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ +#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ +#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ +#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ +#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ +#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ +#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ +#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ +#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ +#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ +#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ +#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ +#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ +#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ +#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ +#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ +#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ +#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ +#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ +#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ +#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ + +/** \brief PMU Functions */ + +__STATIC_INLINE void ARM_PMU_Enable(void); +__STATIC_INLINE void ARM_PMU_Disable(void); + +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); + +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); + +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); + +/** + \brief Enable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Enable(void) +{ + PMU->CTRL |= PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Disable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Disable(void) +{ + PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Set event to count for PMU eventer counter + \param [in] num Event counter (0-30) to configure + \param [in] type Event to count +*/ +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) +{ + PMU->EVTYPER[num] = type; +} + +/** + \brief Reset cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; +} + +/** + \brief Reset all event counters +*/ +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; +} + +/** + \brief Enable counters + \param [in] mask Counters to enable + \note Enables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) +{ + PMU->CNTENSET = mask; +} + +/** + \brief Disable counters + \param [in] mask Counters to enable + \note Disables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) +{ + PMU->CNTENCLR = mask; +} + +/** + \brief Read cycle counter + \return Cycle count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) +{ + return PMU->CCNTR; +} + +/** + \brief Read event counter + \param [in] num Event counter (0-30) to read + \return Event count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) +{ + return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; +} + +/** + \brief Read counter overflow status + \return Counter overflow status bits for the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) +{ + return PMU->OVSSET; +} + +/** + \brief Clear counter overflow status + \param [in] mask Counter overflow status bits to clear + \note Clears overflow status bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) +{ + PMU->OVSCLR = mask; +} + +/** + \brief Enable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to set + \note Sets overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) +{ + PMU->INTENSET = mask; +} + +/** + \brief Disable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to clear + \note Clears overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) +{ + PMU->INTENCLR = mask; +} + +/** + \brief Software increment event counter + \param [in] mask Counters to increment + \note Software increment bits for one or more event counters (0-30) +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) +{ + PMU->SWINC = mask; +} + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_armclang_m.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_armclang_m.h new file mode 100644 index 00000000000..82fb6d46f43 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_armclang_m.h @@ -0,0 +1,818 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Compiler ARMClang (Arm Compiler 6) Header File + */ + +#ifndef __CMSIS_ARMCLANG_M_H +#define __CMSIS_ARMCLANG_M_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __CMSIS_ARMCLANG_H + #error "This file must not be included directly" +#endif + +#if (__ARM_ACLE >= 200) + #include +#else + #error Compiler must support ACLE V2.0 +#endif /* (__ARM_ACLE >= 200) */ + +/* ######################### Startup and Lowlevel Init ######################## */ +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if (__ARM_FEATURE_CMSE == 3) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; + } +#endif + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return (result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return (result); +#endif +} + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return (result); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif +#endif /* (__ARM_ARCH >= 8) */ +/** @} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return (result); +} +#endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */ + /** @} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_M_H */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_clang_m.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_clang_m.h new file mode 100644 index 00000000000..a594442664c --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_clang_m.h @@ -0,0 +1,824 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Compiler LLVM/Clang Header File + */ + +#ifndef __CMSIS_CLANG_M_H +#define __CMSIS_CLANG_M_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __CMSIS_CLANG_H + #error "This file must not be included directly" +#endif + +#if (__ARM_ACLE >= 200) + #include +#else + #error Compiler must support ACLE V2.0 +#endif /* (__ARM_ACLE >= 200) */ + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + + +/* ######################### Startup and Lowlevel Init ######################## */ +#ifndef __PROGRAM_START +#define __PROGRAM_START _start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __stack +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __stack_limit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if (__ARM_FEATURE_CMSE == 3) +#ifndef __STACK_SEAL +#define __STACK_SEAL __stack_seal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; + } +#endif + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return (result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return (result); +#endif +} + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return (result); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* (__ARM_ARCH >= 8) */ + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return (result); +} + +#endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */ + /** @} end of group CMSIS_SIMD_intrinsics */ +/** @} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CMSIS_CLANG_M_H */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_gcc_m.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_gcc_m.h new file mode 100644 index 00000000000..54d1f549577 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_gcc_m.h @@ -0,0 +1,717 @@ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Compiler GCC Header File + */ + +#ifndef __CMSIS_GCC_M_H +#define __CMSIS_GCC_M_H + +#ifndef __CMSIS_GCC_H + #error "This file must not be included directly" +#endif + +#include + +/* ######################### Startup and Lowlevel Init ######################## */ +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct __copy_table { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct __zero_table { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return (result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return (result); +#endif +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return (result); +#endif +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* (__ARM_ARCH >= 8) */ + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CMSIS_GCC_M_H */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h new file mode 100644 index 00000000000..cfc6f808365 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h @@ -0,0 +1,1043 @@ +/* + * Copyright (c) 2017-2021 IAR Systems + * Copyright (c) 2017-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Compiler ICCARM (IAR Compiler for Arm) Header File + */ + +#ifndef __CMSIS_ICCARM_M_H__ +#define __CMSIS_ICCARM_M_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ || __ARM_ARCH_8_1M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #elif __ARM_ARCH == 801 + #define __ARM_ARCH_8_1M_MAIN__ 1 + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) && !defined(__ARM_ARCH_8_1M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' && __ARM_ARCH == 801 + #define __ARM_ARCH_8_1M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + +#ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) +#endif +#ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) +#endif + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if defined(__cplusplus) && __cplusplus >= 201103L + #define __NO_RETURN [[noreturn]] + #elif defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L + #define __NO_RETURN _Noreturn + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #if (defined(__ARM_ARCH_ISA_THUMB) && __ARM_ARCH_ISA_THUMB >= 2) + __IAR_FT void __disable_fault_irq() + { + __ASM volatile ("CPSID F" ::: "memory"); + } + + __IAR_FT void __enable_fault_irq() + { + __ASM volatile ("CPSIE F" ::: "memory"); + } + #endif + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if (defined (__ARM_FP) && (__ARM_FP >= 1)) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + + /* + * __iar_builtin_CLREX can be reordered w.r.t. STREX during high optimizations. + * As a workaround we use inline assembly and a memory barrier. + * (IAR issue EWARM-11901) + */ + #define __CLREX() (__ASM volatile ("CLREX" ::: "memory")) + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!(defined (__ARM_FP) && (__ARM_FP >= 1))) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + __IAR_FT void __disable_fault_irq() + { + __ASM volatile ("CPSID F" ::: "memory"); + } + + __IAR_FT void __enable_fault_irq() + { + __ASM volatile ("CPSIE F" ::: "memory"); + } + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extension and secure, there is no stack limit check. + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions and secure, there is no stack limit check. + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions and secure, there is no stack limit check. + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions and secure, there is no stack limit check. + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ or __ARM_ARCH_8_1M_MAIN__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=&r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=&r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=&r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_M_H__ */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_tiarmclang_m.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_tiarmclang_m.h new file mode 100644 index 00000000000..5b193a17a5d --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_tiarmclang_m.h @@ -0,0 +1,1451 @@ +/* + * Copyright (c) 2023-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Compiler TIARMClang Header File + */ + +#ifndef __CMSIS_TIARMCLANG_M_H +#define __CMSIS_TIARMCLANG_M_H + +#pragma clang system_header /* treat file as system include file */ + +#if (__ARM_ACLE >= 200) + #include +#else + #error Compiler must support ACLE V2.0 +#endif /* (__ARM_ACLE >= 200) */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif +#ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) +#endif +#ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ +#ifndef __PROGRAM_START +#define __PROGRAM_START _c_int00 +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __STACK_END +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __STACK_SIZE +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".intvecs"))) +#endif + +#if (__ARM_FEATURE_CMSE == 3) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __nop() + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __wfi() + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __wfe() + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __sev() + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __rev(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __rev16(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) __revsh(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR(op1, op2) __ror(op1, op2) + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT(value) __rbit(value) + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ(value) __clz(value) + + +/* __ARM_FEATURE_SAT is wrong for for Armv8-M Baseline devices */ +#if ((__ARM_FEATURE_SAT >= 1) && \ + (__ARM_ARCH_ISA_THUMB >= 2) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(value, sat) __ssat(value, sat) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(value, sat) __usat(value, sat) + +#else /* (__ARM_FEATURE_SAT >= 1) */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return (max); + } + else if (val < min) + { + return (min); + } + } + return (val); +} + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return (max); + } + else if (val < 0) + { + return (0U); + } + } + return ((uint32_t)val); +} +#endif /* (__ARM_FEATURE_SAT >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 1) +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 2) +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 2) */ + + +#if (__ARM_FEATURE_LDREX >= 4) +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 4) */ + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); + return (result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return (result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return (result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* (__ARM_ARCH >= 8) */ + +/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return (result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return (result); +#endif +} + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return (result); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* (__ARM_ARCH >= 8) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + return (__builtin_arm_get_fpscr()); +#else + return (0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + __builtin_arm_set_fpscr(fpscr); +#else + (void)fpscr; +#endif +} + + +/** @} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__ARM_FEATURE_DSP == 1) +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return (result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/** @} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_TIARMCLANG_M_H */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_armclang_r.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_armclang_r.h new file mode 100644 index 00000000000..fd9f0e9a16f --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_armclang_r.h @@ -0,0 +1,161 @@ +/**************************************************************************//** + * @file cmsis_armclang_r.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V6.0.0 + * @date 04. December 2024 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCLANG_R_H +#define __CMSIS_ARMCLANG_R_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __CMSIS_ARMCLANG_H + #error "This file must not be included directly" +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** \brief Get CPSR Register + \return CPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set + */ +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) +{ + __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory"); +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP(void) +{ + uint32_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP_usr(void) +{ + uint32_t cpsr; + uint32_t result; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV %1, sp \n" + "MSR cpsr_c, %0 \n" // no effect in USR mode + "ISB" : "=r"(cpsr), "=r"(result) : : "memory" + ); + return result; +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV sp, %1 \n" + "MSR cpsr_c, %0 \n" // no effect in USR mode + "ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory" + ); +} + +/** \brief Get FPEXC + \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); +#else + return(0); +#endif +} + +/** \brief Set FPEXC + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#endif +} + +/** @} end of CMSIS_Core_RegAccFunctions */ + + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +#endif /* __CMSIS_ARMCLANG_R_H */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_clang_r.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_clang_r.h new file mode 100644 index 00000000000..f27eef08f6c --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_clang_r.h @@ -0,0 +1,161 @@ +/**************************************************************************//** + * @file cmsis_clang_r.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V6.0.0 + * @date 04. December 2024 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_CLANG_CORER_H +#define __CMSIS_CLANG_CORER_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __CMSIS_CLANG_H + #error "This file must not be included directly" +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** \brief Get CPSR Register + \return CPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set + */ +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) +{ + __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory"); +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP(void) +{ + uint32_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP_usr(void) +{ + uint32_t cpsr; + uint32_t result; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV %1, sp \n" + "MSR cpsr_c, %0 \n" // no effect in USR mode + "ISB" : "=r"(cpsr), "=r"(result) : : "memory" + ); + return result; +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV sp, %1 \n" + "MSR cpsr_c, %0 \n" // no effect in USR mode + "ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory" + ); +} + +/** \brief Get FPEXC + \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); +#else + return(0); +#endif +} + +/** \brief Set FPEXC + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#endif +} + +/** @} end of CMSIS_Core_RegAccFunctions */ + + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +#endif /* __CMSIS_CLANG_COREA_H */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_gcc_r.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_gcc_r.h new file mode 100644 index 00000000000..be2117c953e --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_gcc_r.h @@ -0,0 +1,163 @@ +/**************************************************************************//** + * @file cmsis_gcc_r.h + * @brief CMSIS compiler GCC header file + * @version V6.0.0 + * @date 4. August 2024 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_R_H +#define __CMSIS_GCC_R_H + +#ifndef __CMSIS_GCC_H + #error "This file must not be included directly" +#endif + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + + +/** \defgroup CMSIS_Core_intrinsics CMSIS Core Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +/** \brief Get CPSR Register + \return CPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set + */ +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) +{ + __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory"); +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP(void) +{ + uint32_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP_usr(void) +{ + uint32_t cpsr = __get_CPSR(); + uint32_t result; + __ASM volatile( + "CPS #0x1F \n" + "MOV %0, sp " : "=r"(result) : : "memory" + ); + __set_CPSR(cpsr); + __ISB(); + return result; +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr = __get_CPSR(); + __ASM volatile( + "CPS #0x1F \n" + "MOV sp, %0 " : : "r" (topOfProcStack) : "memory" + ); + __set_CPSR(cpsr); + __ISB(); +} + +/** \brief Get FPEXC + \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); +#else + return(0); +#endif +} + +/** \brief Set FPEXC + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#endif +} + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +/*@} end of group CMSIS_Core_intrinsics */ + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_R_H */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/tz_context.h b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/tz_context.h new file mode 100644 index 00000000000..e095956a8cb --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/CMSIS/Core/Include/tz_context.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2017-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Core(M) Context Management for Armv8-M TrustZone + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/LICENSE b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/LICENSE new file mode 100644 index 00000000000..8dada3edaf5 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/arm/CMSIS_6/LICENSE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright {yyyy} {name of copyright owner} + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/bsp_api.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/bsp_api.h new file mode 100644 index 00000000000..d912bc0ed45 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/bsp_api.h @@ -0,0 +1,101 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_API_H +#define BSP_API_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* FSP Common Includes. */ +#include "fsp_common_api.h" + +/* Gets MCU configuration information. */ +#include "bsp_cfg.h" + +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) + +/* Store warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */ + #pragma GCC diagnostic push + +/* CMSIS-CORE currently generates 2 warnings when compiling with GCC. One in core_cmInstr.h and one in core_cm4_simd.h. + * We are not modifying these files so we will ignore these warnings temporarily. */ + #pragma GCC diagnostic ignored "-Wconversion" + #pragma GCC diagnostic ignored "-Wsign-conversion" +#endif + +/* Vector information for this project. This is generated by the tooling. */ +#include "../../src/bsp/mcu/all/bsp_exceptions.h" +#include "vector_data.h" + +/* CMSIS-CORE Renesas Device Files. Must come after bsp_feature.h, which is included in bsp_cfg.h. */ +#include "../../src/bsp/cmsis/Device/RENESAS/Include/renesas.h" +#include "../../src/bsp/cmsis/Device/RENESAS/Include/system.h" + +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) + +/* Restore warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */ + #pragma GCC diagnostic pop +#endif + +#if defined(BSP_API_OVERRIDE) + #include BSP_API_OVERRIDE +#else + +/* BSP Common Includes. */ + #include "../../src/bsp/mcu/all/bsp_common.h" + +/* BSP MCU Specific Includes. */ + #include "../../src/bsp/mcu/all/bsp_register_protection.h" + #include "../../src/bsp/mcu/all/bsp_irq.h" + #include "../../src/bsp/mcu/all/bsp_io.h" + #include "../../src/bsp/mcu/all/bsp_group_irq.h" + #include "../../src/bsp/mcu/all/bsp_clocks.h" + #include "../../src/bsp/mcu/all/bsp_module_stop.h" + #include "../../src/bsp/mcu/all/bsp_security.h" + +/* Factory MCU information. */ + #include "../../inc/fsp_features.h" + +/* BSP Common Includes (Other than bsp_common.h) */ + #include "../../src/bsp/mcu/all/bsp_delay.h" + #include "../../src/bsp/mcu/all/bsp_mcu_api.h" + + #if __has_include("../../src/bsp/mcu/all/internal/bsp_internal.h") + #include "../../src/bsp/mcu/all/internal/bsp_internal.h" + #endif + +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +fsp_err_t R_FSP_VersionGet(fsp_pack_version_t * const p_version); + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/fsp_common_api.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/fsp_common_api.h new file mode 100644 index 00000000000..2f55005c567 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/fsp_common_api.h @@ -0,0 +1,387 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef FSP_COMMON_API_H +#define FSP_COMMON_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include + +/* Includes FSP version macros. */ +#include "fsp_version.h" + +/*******************************************************************************************************************//** + * @ingroup RENESAS_COMMON + * @defgroup RENESAS_ERROR_CODES Common Error Codes + * All FSP modules share these common error codes. + * @{ + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** This macro is used to suppress compiler messages about a parameter not being used in a function. The nice thing + * about using this implementation is that it does not take any extra RAM or ROM. */ + +#define FSP_PARAMETER_NOT_USED(p) (void) ((p)) + +/** Determine if a C++ compiler is being used. + * If so, ensure that standard C is used to process the API information. */ +#if defined(__cplusplus) + #define FSP_CPP_HEADER extern "C" { + #define FSP_CPP_FOOTER } +#else + #define FSP_CPP_HEADER + #define FSP_CPP_FOOTER +#endif + +/** FSP Header and Footer definitions */ +#define FSP_HEADER FSP_CPP_HEADER +#define FSP_FOOTER FSP_CPP_FOOTER + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/** Macro to be used when argument to function is ignored since function call is NSC and the parameter is statically + * defined on the Secure side. */ +#define FSP_SECURE_ARGUMENT (NULL) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Common error codes */ +typedef enum e_fsp_err +{ + FSP_SUCCESS = 0, + + FSP_ERR_ASSERTION = 1, ///< A critical assertion has failed + FSP_ERR_INVALID_POINTER = 2, ///< Pointer points to invalid memory location + FSP_ERR_INVALID_ARGUMENT = 3, ///< Invalid input parameter + FSP_ERR_INVALID_CHANNEL = 4, ///< Selected channel does not exist + FSP_ERR_INVALID_MODE = 5, ///< Unsupported or incorrect mode + FSP_ERR_UNSUPPORTED = 6, ///< Selected mode not supported by this API + FSP_ERR_NOT_OPEN = 7, ///< Requested channel is not configured or API not open + FSP_ERR_IN_USE = 8, ///< Channel/peripheral is running/busy + FSP_ERR_OUT_OF_MEMORY = 9, ///< Allocate more memory in the driver's cfg.h + FSP_ERR_HW_LOCKED = 10, ///< Hardware is locked + FSP_ERR_IRQ_BSP_DISABLED = 11, ///< IRQ not enabled in BSP + FSP_ERR_OVERFLOW = 12, ///< Hardware overflow + FSP_ERR_UNDERFLOW = 13, ///< Hardware underflow + FSP_ERR_ALREADY_OPEN = 14, ///< Requested channel is already open in a different configuration + FSP_ERR_APPROXIMATION = 15, ///< Could not set value to exact result + FSP_ERR_CLAMPED = 16, ///< Value had to be limited for some reason + FSP_ERR_INVALID_RATE = 17, ///< Selected rate could not be met + FSP_ERR_ABORTED = 18, ///< An operation was aborted + FSP_ERR_NOT_ENABLED = 19, ///< Requested operation is not enabled + FSP_ERR_TIMEOUT = 20, ///< Timeout error + FSP_ERR_INVALID_BLOCKS = 21, ///< Invalid number of blocks supplied + FSP_ERR_INVALID_ADDRESS = 22, ///< Invalid address supplied + FSP_ERR_INVALID_SIZE = 23, ///< Invalid size/length supplied for operation + FSP_ERR_WRITE_FAILED = 24, ///< Write operation failed + FSP_ERR_ERASE_FAILED = 25, ///< Erase operation failed + FSP_ERR_INVALID_CALL = 26, ///< Invalid function call is made + FSP_ERR_INVALID_HW_CONDITION = 27, ///< Detected hardware is in invalid condition + FSP_ERR_INVALID_FACTORY_FLASH = 28, ///< Factory flash is not available on this MCU + FSP_ERR_INVALID_STATE = 30, ///< API or command not valid in the current state + FSP_ERR_NOT_ERASED = 31, ///< Erase verification failed + FSP_ERR_SECTOR_RELEASE_FAILED = 32, ///< Sector release failed + FSP_ERR_NOT_INITIALIZED = 33, ///< Required initialization not complete + FSP_ERR_NOT_FOUND = 34, ///< The requested item could not be found + FSP_ERR_NO_CALLBACK_MEMORY = 35, ///< Non-secure callback memory not provided for non-secure callback + FSP_ERR_BUFFER_EMPTY = 36, ///< No data available in buffer + FSP_ERR_INVALID_DATA = 37, ///< Accuracy of data is not guaranteed + + /* Start of RTOS only error codes */ + FSP_ERR_INTERNAL = 100, ///< Internal error + FSP_ERR_WAIT_ABORTED = 101, ///< Wait aborted + + /* Start of UART specific */ + FSP_ERR_FRAMING = 200, ///< Framing error occurs + FSP_ERR_BREAK_DETECT = 201, ///< Break signal detects + FSP_ERR_PARITY = 202, ///< Parity error occurs + FSP_ERR_RXBUF_OVERFLOW = 203, ///< Receive queue overflow + FSP_ERR_QUEUE_UNAVAILABLE = 204, ///< Can't open s/w queue + FSP_ERR_INSUFFICIENT_SPACE = 205, ///< Not enough space in transmission circular buffer + FSP_ERR_INSUFFICIENT_DATA = 206, ///< Not enough data in receive circular buffer + + /* Start of SPI specific */ + FSP_ERR_TRANSFER_ABORTED = 300, ///< The data transfer was aborted. + FSP_ERR_MODE_FAULT = 301, ///< Mode fault error. + FSP_ERR_READ_OVERFLOW = 302, ///< Read overflow. + FSP_ERR_SPI_PARITY = 303, ///< Parity error. + FSP_ERR_OVERRUN = 304, ///< Overrun error. + + /* Start of CGC Specific */ + FSP_ERR_CLOCK_INACTIVE = 400, ///< Inactive clock specified as system clock. + FSP_ERR_CLOCK_ACTIVE = 401, ///< Active clock source cannot be modified without stopping first. + FSP_ERR_NOT_STABILIZED = 403, ///< Clock has not stabilized after its been turned on/off + FSP_ERR_PLL_SRC_INACTIVE = 404, ///< PLL initialization attempted when PLL source is turned off + FSP_ERR_OSC_STOP_DET_ENABLED = 405, ///< Illegal attempt to stop LOCO when Oscillation stop is enabled + FSP_ERR_OSC_STOP_DETECTED = 406, ///< The Oscillation stop detection status flag is set + FSP_ERR_OSC_STOP_CLOCK_ACTIVE = 407, ///< Attempt to clear Oscillation Stop Detect Status with PLL/MAIN_OSC active + FSP_ERR_CLKOUT_EXCEEDED = 408, ///< Output on target output clock pin exceeds maximum supported limit + FSP_ERR_USB_MODULE_ENABLED = 409, ///< USB clock configure request with USB Module enabled + FSP_ERR_HARDWARE_TIMEOUT = 410, ///< A register read or write timed out + FSP_ERR_LOW_VOLTAGE_MODE = 411, ///< Invalid clock setting attempted in low voltage mode + + /* Start of FLASH Specific */ + FSP_ERR_PE_FAILURE = 500, ///< Unable to enter Programming mode. + FSP_ERR_CMD_LOCKED = 501, ///< Peripheral in command locked state + FSP_ERR_FCLK = 502, ///< FCLK must be >= 4 MHz + FSP_ERR_INVALID_LINKED_ADDRESS = 503, ///< Function or data are linked at an invalid region of memory + FSP_ERR_BLANK_CHECK_FAILED = 504, ///< Blank check operation failed + FSP_ERR_HUK_ZEROIZATION = 505, ///< W-HUK zeroization is in progress + + /* Start of CAC Specific */ + FSP_ERR_INVALID_CAC_REF_CLOCK = 600, ///< Measured clock rate < reference clock rate + + /* Start of IIRFA Specific */ + FSP_ERR_INVALID_RESULT = 700, ///< The result of one or more calculations was +/- infinity. + + /* Start of GLCD Specific */ + FSP_ERR_CLOCK_GENERATION = 1000, ///< Clock cannot be specified as system clock + FSP_ERR_INVALID_TIMING_SETTING = 1001, ///< Invalid timing parameter + FSP_ERR_INVALID_LAYER_SETTING = 1002, ///< Invalid layer parameter + FSP_ERR_INVALID_ALIGNMENT = 1003, ///< Invalid memory alignment found + FSP_ERR_INVALID_GAMMA_SETTING = 1004, ///< Invalid gamma correction parameter + FSP_ERR_INVALID_LAYER_FORMAT = 1005, ///< Invalid color format in layer + FSP_ERR_INVALID_UPDATE_TIMING = 1006, ///< Invalid timing for register update + FSP_ERR_INVALID_CLUT_ACCESS = 1007, ///< Invalid access to CLUT entry + FSP_ERR_INVALID_FADE_SETTING = 1008, ///< Invalid fade-in/fade-out setting + FSP_ERR_INVALID_BRIGHTNESS_SETTING = 1009, ///< Invalid gamma correction parameter + + /* Start of JPEG Specific */ + FSP_ERR_JPEG_ERR = 1100, ///< JPEG error + FSP_ERR_JPEG_SOI_NOT_DETECTED = 1101, ///< SOI not detected until EOI detected. + FSP_ERR_JPEG_SOF1_TO_SOFF_DETECTED = 1102, ///< SOF1 to SOFF detected. + FSP_ERR_JPEG_UNSUPPORTED_PIXEL_FORMAT = 1103, ///< Unprovided pixel format detected. + FSP_ERR_JPEG_SOF_ACCURACY_ERROR = 1104, ///< SOF accuracy error: other than 8 detected. + FSP_ERR_JPEG_DQT_ACCURACY_ERROR = 1105, ///< DQT accuracy error: other than 0 detected. + FSP_ERR_JPEG_COMPONENT_ERROR1 = 1106, ///< Component error 1: the number of SOF0 header components detected is other than 1, 3, or 4. + FSP_ERR_JPEG_COMPONENT_ERROR2 = 1107, ///< Component error 2: the number of components differs between SOF0 header and SOS. + FSP_ERR_JPEG_SOF0_DQT_DHT_NOT_DETECTED = 1108, ///< SOF0, DQT, and DHT not detected when SOS detected. + FSP_ERR_JPEG_SOS_NOT_DETECTED = 1109, ///< SOS not detected: SOS not detected until EOI detected. + FSP_ERR_JPEG_EOI_NOT_DETECTED = 1110, ///< EOI not detected (default) + FSP_ERR_JPEG_RESTART_INTERVAL_DATA_NUMBER_ERROR = 1111, ///< Restart interval data number error detected. + FSP_ERR_JPEG_IMAGE_SIZE_ERROR = 1112, ///< Image size error detected. + FSP_ERR_JPEG_LAST_MCU_DATA_NUMBER_ERROR = 1113, ///< Last MCU data number error detected. + FSP_ERR_JPEG_BLOCK_DATA_NUMBER_ERROR = 1114, ///< Block data number error detected. + FSP_ERR_JPEG_BUFFERSIZE_NOT_ENOUGH = 1115, ///< User provided buffer size not enough + FSP_ERR_JPEG_UNSUPPORTED_IMAGE_SIZE = 1116, ///< JPEG Image size is not aligned with MCU + + /* Start of touch panel framework specific */ + FSP_ERR_CALIBRATE_FAILED = 1200, ///< Calibration failed + + /* Start of IIRFA specific */ + FSP_ERR_IIRFA_ECC_1BIT = 1300, ///< 1-bit ECC error detected + FSP_ERR_IIRFA_ECC_2BIT = 1301, ///< 2-bit ECC error detected + + /* Start of IP specific */ + FSP_ERR_IP_HARDWARE_NOT_PRESENT = 1400, ///< Requested IP does not exist on this device + FSP_ERR_IP_UNIT_NOT_PRESENT = 1401, ///< Requested unit does not exist on this device + FSP_ERR_IP_CHANNEL_NOT_PRESENT = 1402, ///< Requested channel does not exist on this device + + /* Start of USB specific */ + FSP_ERR_USB_FAILED = 1500, + FSP_ERR_USB_BUSY = 1501, + FSP_ERR_USB_SIZE_SHORT = 1502, + FSP_ERR_USB_SIZE_OVER = 1503, + FSP_ERR_USB_NOT_OPEN = 1504, + FSP_ERR_USB_NOT_SUSPEND = 1505, + FSP_ERR_USB_PARAMETER = 1506, + + /* Start of Message framework specific */ + FSP_ERR_NO_MORE_BUFFER = 2000, ///< No more buffer found in the memory block pool + FSP_ERR_ILLEGAL_BUFFER_ADDRESS = 2001, ///< Buffer address is out of block memory pool + FSP_ERR_INVALID_WORKBUFFER_SIZE = 2002, ///< Work buffer size is invalid + FSP_ERR_INVALID_MSG_BUFFER_SIZE = 2003, ///< Message buffer size is invalid + FSP_ERR_TOO_MANY_BUFFERS = 2004, ///< Number of buffer is too many + FSP_ERR_NO_SUBSCRIBER_FOUND = 2005, ///< No message subscriber found + FSP_ERR_MESSAGE_QUEUE_EMPTY = 2006, ///< No message found in the message queue + FSP_ERR_MESSAGE_QUEUE_FULL = 2007, ///< No room for new message in the message queue + FSP_ERR_ILLEGAL_SUBSCRIBER_LISTS = 2008, ///< Message subscriber lists is illegal + FSP_ERR_BUFFER_RELEASED = 2009, ///< Buffer has been released + + /* Start of 2DG Driver specific */ + FSP_ERR_D2D_ERROR_INIT = 3000, ///< D/AVE 2D has an error in the initialization + FSP_ERR_D2D_ERROR_DEINIT = 3001, ///< D/AVE 2D has an error in the initialization + FSP_ERR_D2D_ERROR_RENDERING = 3002, ///< D/AVE 2D has an error in the rendering + FSP_ERR_D2D_ERROR_SIZE = 3003, ///< D/AVE 2D has an error in the rendering + + /* Start of ETHER Driver specific */ + FSP_ERR_ETHER_ERROR_NO_DATA = 4000, ///< No Data in Receive buffer. + FSP_ERR_ETHER_ERROR_LINK = 4001, ///< ETHERC/EDMAC has an error in the Auto-negotiation + FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE = 4002, ///< As a Magic Packet is being detected, and transmission/reception is not enabled + FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL = 4003, ///< Transmit buffer is not empty + FSP_ERR_ETHER_ERROR_FILTERING = 4004, ///< Detect multicast frame when multicast frame filtering enable + FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION = 4005, ///< ETHERC/EDMAC has an error in the phy communication + FSP_ERR_ETHER_RECEIVE_BUFFER_ACTIVE = 4006, ///< Receive buffer is active. + + /* Start of ETHER_PHY Driver specific */ + FSP_ERR_ETHER_PHY_ERROR_LINK = 5000, ///< PHY is not link up. + FSP_ERR_ETHER_PHY_NOT_READY = 5001, ///< PHY has an error in the Auto-negotiation + + /* Start of BYTEQ library specific */ + FSP_ERR_QUEUE_FULL = 10000, ///< Queue is full, cannot queue another data + FSP_ERR_QUEUE_EMPTY = 10001, ///< Queue is empty, no data to dequeue + + /* Start of CTSU Driver specific */ + FSP_ERR_CTSU_SCANNING = 6000, ///< Scanning. + FSP_ERR_CTSU_NOT_GET_DATA = 6001, ///< Not processed previous scan data. + FSP_ERR_CTSU_INCOMPLETE_TUNING = 6002, ///< Incomplete initial offset tuning. + FSP_ERR_CTSU_DIAG_NOT_YET = 6003, ///< Diagnosis of data collected no yet. + FSP_ERR_CTSU_DIAG_LDO_OVER_VOLTAGE = 6004, ///< Diagnosis of LDO over voltage failed. + FSP_ERR_CTSU_DIAG_CCO_HIGH = 6005, ///< Diagnosis of CCO into 19.2uA failed. + FSP_ERR_CTSU_DIAG_CCO_LOW = 6006, ///< Diagnosis of CCO into 2.4uA failed. + FSP_ERR_CTSU_DIAG_SSCG = 6007, ///< Diagnosis of SSCG frequency failed. + FSP_ERR_CTSU_DIAG_DAC = 6008, ///< Diagnosis of non-touch count value failed. + FSP_ERR_CTSU_DIAG_OUTPUT_VOLTAGE = 6009, ///< Diagnosis of LDO output voltage failed. + FSP_ERR_CTSU_DIAG_OVER_VOLTAGE = 6010, ///< Diagnosis of over voltage detection circuit failed. + FSP_ERR_CTSU_DIAG_OVER_CURRENT = 6011, ///< Diagnosis of over current detection circuit failed. + FSP_ERR_CTSU_DIAG_LOAD_RESISTANCE = 6012, ///< Diagnosis of LDO internal resistance value failed. + FSP_ERR_CTSU_DIAG_CURRENT_SOURCE = 6013, ///< Diagnosis of Current source value failed. + FSP_ERR_CTSU_DIAG_SENSCLK_GAIN = 6014, ///< Diagnosis of SENSCLK frequency gain failed. + FSP_ERR_CTSU_DIAG_SUCLK_GAIN = 6015, ///< Diagnosis of SUCLK frequency gain failed. + FSP_ERR_CTSU_DIAG_CLOCK_RECOVERY = 6016, ///< Diagnosis of SUCLK clock recovery function failed. + FSP_ERR_CTSU_DIAG_CFC_GAIN = 6017, ///< Diagnosis of CFC oscillator gain failed. + + /* Start of SDMMC specific */ + FSP_ERR_CARD_INIT_FAILED = 40000, ///< SD card or eMMC device failed to initialize. + FSP_ERR_CARD_NOT_INSERTED = 40001, ///< SD card not installed. + FSP_ERR_DEVICE_BUSY = 40002, ///< Device is holding DAT0 low or another operation is ongoing. + FSP_ERR_CARD_NOT_INITIALIZED = 40004, ///< SD card was removed. + FSP_ERR_CARD_WRITE_PROTECTED = 40005, ///< Media is write protected. + FSP_ERR_TRANSFER_BUSY = 40006, ///< Transfer in progress. + FSP_ERR_RESPONSE = 40007, ///< Card did not respond or responded with an error. + + /* Start of FX_IO specific */ + FSP_ERR_MEDIA_FORMAT_FAILED = 50000, ///< Media format failed. + FSP_ERR_MEDIA_OPEN_FAILED = 50001, ///< Media open failed. + + /* Start of CAN specific */ + FSP_ERR_CAN_DATA_UNAVAILABLE = 60000, ///< No data available. + FSP_ERR_CAN_MODE_SWITCH_FAILED = 60001, ///< Switching operation modes failed. + FSP_ERR_CAN_INIT_FAILED = 60002, ///< Hardware initialization failed. + FSP_ERR_CAN_TRANSMIT_NOT_READY = 60003, ///< Transmit in progress. + FSP_ERR_CAN_RECEIVE_MAILBOX = 60004, ///< Mailbox is setup as a receive mailbox. + FSP_ERR_CAN_TRANSMIT_MAILBOX = 60005, ///< Mailbox is setup as a transmit mailbox. + FSP_ERR_CAN_MESSAGE_LOST = 60006, ///< Receive message has been overwritten or overrun. + FSP_ERR_CAN_TRANSMIT_FIFO_FULL = 60007, ///< Transmit FIFO is full. + + /* Start of SF_WIFI Specific */ + FSP_ERR_WIFI_CONFIG_FAILED = 70000, ///< WiFi module Configuration failed. + FSP_ERR_WIFI_INIT_FAILED = 70001, ///< WiFi module initialization failed. + FSP_ERR_WIFI_TRANSMIT_FAILED = 70002, ///< Transmission failed + FSP_ERR_WIFI_INVALID_MODE = 70003, ///< API called when provisioned in client mode + FSP_ERR_WIFI_FAILED = 70004, ///< WiFi Failed. + FSP_ERR_WIFI_SCAN_COMPLETE = 70005, ///< Wifi scan has completed. + FSP_ERR_WIFI_AP_NOT_CONNECTED = 70006, ///< WiFi module is not connected to access point + FSP_ERR_WIFI_UNKNOWN_AT_CMD = 70007, ///< DA16XXX Unknown AT command Error + FSP_ERR_WIFI_INSUF_PARAM = 70008, ///< DA16XXX Insufficient parameter + FSP_ERR_WIFI_TOO_MANY_PARAMS = 70009, ///< DA16XXX Too many parameters + FSP_ERR_WIFI_INV_PARAM_VAL = 70010, ///< DA16XXX Wrong parameter value + FSP_ERR_WIFI_NO_RESULT = 70011, ///< DA16XXX No result + FSP_ERR_WIFI_RSP_BUF_OVFLW = 70012, ///< DA16XXX Response buffer overflow + FSP_ERR_WIFI_FUNC_NOT_CONFIG = 70013, ///< DA16XXX Function is not configured + FSP_ERR_WIFI_NVRAM_WR_FAIL = 70014, ///< DA16XXX NVRAM write failure + FSP_ERR_WIFI_RET_MEM_WR_FAIL = 70015, ///< DA16XXX Retention memory write failure + FSP_ERR_WIFI_UNKNOWN_ERR = 70016, ///< DA16XXX unknown error + + /* Start of SF_CELLULAR Specific */ + FSP_ERR_CELLULAR_CONFIG_FAILED = 80000, ///< Cellular module Configuration failed. + FSP_ERR_CELLULAR_INIT_FAILED = 80001, ///< Cellular module initialization failed. + FSP_ERR_CELLULAR_TRANSMIT_FAILED = 80002, ///< Transmission failed + FSP_ERR_CELLULAR_FW_UPTODATE = 80003, ///< Firmware is uptodate + FSP_ERR_CELLULAR_FW_UPGRADE_FAILED = 80004, ///< Firmware upgrade failed + FSP_ERR_CELLULAR_FAILED = 80005, ///< Cellular Failed. + FSP_ERR_CELLULAR_INVALID_STATE = 80006, ///< API Called in invalid state. + FSP_ERR_CELLULAR_REGISTRATION_FAILED = 80007, ///< Cellular Network registration failed + + /* Start of SF_BLE specific */ + FSP_ERR_BLE_FAILED = 90001, ///< BLE operation failed + FSP_ERR_BLE_INIT_FAILED = 90002, ///< BLE device initialization failed + FSP_ERR_BLE_CONFIG_FAILED = 90003, ///< BLE device configuration failed + FSP_ERR_BLE_PRF_ALREADY_ENABLED = 90004, ///< BLE device Profile already enabled + FSP_ERR_BLE_PRF_NOT_ENABLED = 90005, ///< BLE device not enabled + + /* Start of SF_BLE_ABS specific */ + FSP_ERR_BLE_ABS_INVALID_OPERATION = 91001, ///< Invalid operation is executed. + FSP_ERR_BLE_ABS_NOT_FOUND = 91002, ///< Valid data or free space is not found. + + /* Start of Crypto specific (0x10000) @note Refer to sf_cryoto_err.h for Crypto error code. */ + FSP_ERR_CRYPTO_CONTINUE = 0x10000, ///< Continue executing function + FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT = 0x10001, ///< Hardware resource busy + FSP_ERR_CRYPTO_SCE_FAIL = 0x10002, ///< Internal I/O buffer is not empty + FSP_ERR_CRYPTO_SCE_HRK_INVALID_INDEX = 0x10003, ///< Invalid index + FSP_ERR_CRYPTO_SCE_RETRY = 0x10004, ///< Retry + FSP_ERR_CRYPTO_SCE_VERIFY_FAIL = 0x10005, ///< Verify is failed + FSP_ERR_CRYPTO_SCE_ALREADY_OPEN = 0x10006, ///< HW SCE module is already opened + FSP_ERR_CRYPTO_NOT_OPEN = 0x10007, ///< Hardware module is not initialized + FSP_ERR_CRYPTO_UNKNOWN = 0x10008, ///< Some unknown error occurred + FSP_ERR_CRYPTO_NULL_POINTER = 0x10009, ///< Null pointer input as a parameter + FSP_ERR_CRYPTO_NOT_IMPLEMENTED = 0x1000a, ///< Algorithm/size not implemented + FSP_ERR_CRYPTO_RNG_INVALID_PARAM = 0x1000b, ///< An invalid parameter is specified + FSP_ERR_CRYPTO_RNG_FATAL_ERROR = 0x1000c, ///< A fatal error occurred + FSP_ERR_CRYPTO_INVALID_SIZE = 0x1000d, ///< Size specified is invalid + FSP_ERR_CRYPTO_INVALID_STATE = 0x1000e, ///< Function used in an valid state + FSP_ERR_CRYPTO_ALREADY_OPEN = 0x1000f, ///< control block is already opened + FSP_ERR_CRYPTO_INSTALL_KEY_FAILED = 0x10010, ///< Specified input key is invalid. + FSP_ERR_CRYPTO_AUTHENTICATION_FAILED = 0x10011, ///< Authentication failed + FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL = 0x10012, ///< Failure to Init Cipher + FSP_ERR_CRYPTO_SCE_AUTHENTICATION = 0x10013, ///< Authentication failed + FSP_ERR_CRYPTO_SCE_PARAMETER = 0x10014, ///< Input date is illegal. + FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION = 0x10015, ///< An invalid function call occurred. + FSP_ERR_CRYPTO_SCE_PASS_1 = 0x10016, // Private SCE return code + FSP_ERR_CRYPTO_SCE_PASS_2 = 0x10017, // Private SCE return code + + FSP_ERR_CRYPTO_SCE_LBIST_CHECK_BUSY = 0x100ff, ///< LBIST Check BUSY + + /* Start of Crypto RSIP specific (0x10100) */ + FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT = 0x10100, ///< Hardware resource is busy + FSP_ERR_CRYPTO_RSIP_FATAL = 0x10101, ///< Hardware fatal error or unexpected return + FSP_ERR_CRYPTO_RSIP_FAIL = 0x10102, ///< Internal error + FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL = 0x10103, ///< Input key type is illegal + FSP_ERR_CRYPTO_RSIP_AUTHENTICATION = 0x10104, ///< Authentication failed + + FSP_ERR_CRYPTO_RSIP_LBIST_CHECK_BUSY = 0x101ff, ///< LBIST Check BUSY + + /* Start of SF_CRYPTO specific */ + FSP_ERR_CRYPTO_COMMON_NOT_OPENED = 0x20000, ///< Crypto Framework Common is not opened + FSP_ERR_CRYPTO_HAL_ERROR = 0x20001, ///< Cryoto HAL module returned an error + FSP_ERR_CRYPTO_KEY_BUF_NOT_ENOUGH = 0x20002, ///< Key buffer size is not enough to generate a key + FSP_ERR_CRYPTO_BUF_OVERFLOW = 0x20003, ///< Attempt to write data larger than what the buffer can hold + FSP_ERR_CRYPTO_INVALID_OPERATION_MODE = 0x20004, ///< Invalid operation mode. + FSP_ERR_MESSAGE_TOO_LONG = 0x20005, ///< Message for RSA encryption is too long. + FSP_ERR_RSA_DECRYPTION_ERROR = 0x20006, ///< RSA Decryption error. + + /** @note SF_CRYPTO APIs may return an error code starting from 0x10000 which is of Crypto module. + * Refer to sf_cryoto_err.h for Crypto error codes. + */ + + /* Start of Sensor specific */ + FSP_ERR_SENSOR_INVALID_DATA = 0x30000, ///< Data is invalid. + FSP_ERR_SENSOR_IN_STABILIZATION = 0x30001, ///< Sensor is stabilizing. + FSP_ERR_SENSOR_MEASUREMENT_NOT_FINISHED = 0x30002, ///< Measurement is not finished. + + /* Start of COMMS specific */ + FSP_ERR_COMMS_BUS_NOT_OPEN = 0x40000, ///< Bus is not open. +} fsp_err_t; + +/** @} */ + +/*********************************************************************************************************************** + * Function prototypes + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/inc/api/r_adc_api.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_adc_api.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/inc/api/r_adc_api.h rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_adc_api.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/inc/api/r_can_api.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_can_api.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/inc/api/r_can_api.h rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_can_api.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/inc/api/r_cgc_api.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_cgc_api.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/inc/api/r_cgc_api.h rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_cgc_api.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/inc/api/r_elc_api.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_elc_api.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/inc/api/r_elc_api.h rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_elc_api.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/inc/api/r_ether_api.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_ether_api.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/inc/api/r_ether_api.h rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_ether_api.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/inc/api/r_ether_phy_api.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_ether_phy_api.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/inc/api/r_ether_phy_api.h rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_ether_phy_api.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/inc/api/r_ether_switch_api.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_ether_switch_api.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/inc/api/r_ether_switch_api.h rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_ether_switch_api.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/inc/api/r_gptp_api.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_gptp_api.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/inc/api/r_gptp_api.h rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_gptp_api.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/inc/api/r_i2c_master_api.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_i2c_master_api.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/inc/api/r_i2c_master_api.h rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_i2c_master_api.h diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_ioport_api.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_ioport_api.h new file mode 100644 index 00000000000..dcb104b06df --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_ioport_api.h @@ -0,0 +1,192 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_SYSTEM_INTERFACES + * @defgroup IOPORT_API I/O Port Interface + * @brief Interface for accessing I/O ports and configuring I/O functionality. + * + * @section IOPORT_API_SUMMARY Summary + * The IOPort shared interface provides the ability to access the IOPorts of a device at both bit and port level. + * Port and pin direction can be changed. + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_IOPORT_API_H +#define R_IOPORT_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Common error codes and definitions. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +#ifndef BSP_OVERRIDE_IOPORT_SIZE_T + +/** IO port type used with ports */ +typedef uint16_t ioport_size_t; ///< IO port size +#endif + +/** Pin identifier and pin configuration value */ +typedef struct st_ioport_pin_cfg +{ + uint32_t pin_cfg; ///< Pin configuration - Use ioport_cfg_options_t parameters to configure + bsp_io_port_pin_t pin; ///< Pin identifier +} ioport_pin_cfg_t; + +/** Multiple pin configuration data for loading into registers by R_IOPORT_Open() */ +typedef struct st_ioport_cfg +{ + uint16_t number_of_pins; ///< Number of pins for which there is configuration data + ioport_pin_cfg_t const * p_pin_cfg_data; ///< Pin configuration data + const void * p_extend; ///< Pointer to hardware extend configuration +} ioport_cfg_t; + +/** IOPORT control block. Allocate an instance specific control block to pass into the IOPORT API calls. + */ +typedef void ioport_ctrl_t; + +/** IOPort driver structure. IOPort functions implemented at the HAL layer will follow this API. */ +typedef struct st_ioport_api +{ + /** Initialize internal driver data and initial pin configurations. Called during startup. Do + * not call this API during runtime. Use @ref ioport_api_t::pinsCfg for runtime reconfiguration of + * multiple pins. + * + * @param[in] p_ctrl Pointer to control structure. Must be declared by user. Elements set here. + * @param[in] p_cfg Pointer to pin configuration data array. + */ + fsp_err_t (* open)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); + + /** Close the API. + * + * @param[in] p_ctrl Pointer to control structure. + **/ + fsp_err_t (* close)(ioport_ctrl_t * const p_ctrl); + + /** Configure multiple pins. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_cfg Pointer to pin configuration data array. + */ + fsp_err_t (* pinsCfg)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); + + /** Configure settings for an individual pin. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] pin Pin to be read. + * @param[in] cfg Configuration options for the pin. + */ + fsp_err_t (* pinCfg)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg); + + /** Read the event input data of the specified pin and return the level. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] pin Pin to be read. + * @param[in] p_pin_event Pointer to return the event data. + */ + fsp_err_t (* pinEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event); + + /** Write pin event data. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] pin Pin event data is to be written to. + * @param[in] pin_value Level to be written to pin output event. + */ + fsp_err_t (* pinEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value); + + /** Read level of a pin. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] pin Pin to be read. + * @param[in] p_pin_value Pointer to return the pin level. + */ + fsp_err_t (* pinRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value); + + /** Write specified level to a pin. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] pin Pin to be written to. + * @param[in] level State to be written to the pin. + */ + fsp_err_t (* pinWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level); + + /** Set the direction of one or more pins on a port. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] port Port being configured. + * @param[in] direction_values Value controlling direction of pins on port. + * @param[in] mask Mask controlling which pins on the port are to be configured. + */ + fsp_err_t (* portDirectionSet)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t direction_values, + ioport_size_t mask); + + /** Read captured event data for a port. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] port Port to be read. + * @param[in] p_event_data Pointer to return the event data. + */ + fsp_err_t (* portEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data); + + /** Write event output data for a port. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] port Port event data will be written to. + * @param[in] event_data Data to be written as event data to specified port. + * @param[in] mask_value Each bit set to 1 in the mask corresponds to that bit's value in event data. + * being written to port. + */ + fsp_err_t (* portEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t event_data, + ioport_size_t mask_value); + + /** Read states of pins on the specified port. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] port Port to be read. + * @param[in] p_port_value Pointer to return the port value. + */ + fsp_err_t (* portRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value); + + /** Write to multiple pins on a port. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] port Port to be written to. + * @param[in] value Value to be written to the port. + * @param[in] mask Mask controlling which pins on the port are written to. + */ + fsp_err_t (* portWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask); +} ioport_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_ioport_instance +{ + ioport_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + ioport_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + ioport_api_t const * p_api; ///< Pointer to the API structure for this instance +} ioport_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup IOPORT_API) + **********************************************************************************************************************/ diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/inc/api/r_rtc_api.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_rtc_api.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/inc/api/r_rtc_api.h rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_rtc_api.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/inc/api/r_sdmmc_api.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_sdmmc_api.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/inc/api/r_sdmmc_api.h rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_sdmmc_api.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/inc/api/r_spi_api.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_spi_api.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/inc/api/r_spi_api.h rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_spi_api.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/inc/api/r_spi_flash_api.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_spi_flash_api.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/inc/api/r_spi_flash_api.h rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_spi_flash_api.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/inc/api/r_timer_api.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_timer_api.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/inc/api/r_timer_api.h rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_timer_api.h diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_transfer_api.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_transfer_api.h new file mode 100644 index 00000000000..92aeeabc2af --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_transfer_api.h @@ -0,0 +1,389 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_TRANSFER_INTERFACES + * @defgroup TRANSFER_API Transfer Interface + * + * @brief Interface for data transfer functions. + * + * @section TRANSFER_API_SUMMARY Summary + * The transfer interface supports background data transfer (no CPU intervention). + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_TRANSFER_API_H +#define R_TRANSFER_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Common error codes and definitions. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define TRANSFER_SETTINGS_MODE_BITS (30U) +#define TRANSFER_SETTINGS_SIZE_BITS (28U) +#define TRANSFER_SETTINGS_SRC_ADDR_BITS (26U) +#define TRANSFER_SETTINGS_CHAIN_MODE_BITS (22U) +#define TRANSFER_SETTINGS_IRQ_BITS (21U) +#define TRANSFER_SETTINGS_REPEAT_AREA_BITS (20U) +#define TRANSFER_SETTINGS_DEST_ADDR_BITS (18U) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Transfer control block. Allocate an instance specific control block to pass into the transfer API calls. + */ +typedef void transfer_ctrl_t; + +#ifndef BSP_OVERRIDE_TRANSFER_MODE_T + +/** Transfer mode describes what will happen when a transfer request occurs. */ +typedef enum e_transfer_mode +{ + /** In normal mode, each transfer request causes a transfer of @ref transfer_size_t from the source pointer to + * the destination pointer. The transfer length is decremented and the source and address pointers are + * updated according to @ref transfer_addr_mode_t. After the transfer length reaches 0, transfer requests + * will not cause any further transfers. */ + TRANSFER_MODE_NORMAL = 0, + + /** Repeat mode is like normal mode, except that when the transfer length reaches 0, the pointer to the + * repeat area and the transfer length will be reset to their initial values. If DMAC is used, the + * transfer repeats only transfer_info_t::num_blocks times. After the transfer repeats + * transfer_info_t::num_blocks times, transfer requests will not cause any further transfers. If DTC is + * used, the transfer repeats continuously (no limit to the number of repeat transfers). */ + TRANSFER_MODE_REPEAT = 1, + + /** In block mode, each transfer request causes transfer_info_t::length transfers of @ref transfer_size_t. + * After each individual transfer, the source and destination pointers are updated according to + * @ref transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is + * decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any + * further transfers. */ + TRANSFER_MODE_BLOCK = 2, + + /** In addition to block mode features, repeat-block mode supports a ring buffer of blocks and offsets + * within a block (to split blocks into arrays of their first data, second data, etc.) */ + TRANSFER_MODE_REPEAT_BLOCK = 3 +} transfer_mode_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_SIZE_T + +/** Transfer size specifies the size of each individual transfer. + * Total transfer length = transfer_size_t * transfer_length_t + */ +typedef enum e_transfer_size +{ + TRANSFER_SIZE_1_BYTE = 0, ///< Each transfer transfers a 8-bit value + TRANSFER_SIZE_2_BYTE = 1, ///< Each transfer transfers a 16-bit value + TRANSFER_SIZE_4_BYTE = 2, ///< Each transfer transfers a 32-bit value + TRANSFER_SIZE_8_BYTE = 3 ///< Each transfer transfers a 64-bit value +} transfer_size_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_ADDR_MODE_T + +/** Address mode specifies whether to modify (increment or decrement) pointer after each transfer. */ +typedef enum e_transfer_addr_mode +{ + /** Address pointer remains fixed after each transfer. */ + TRANSFER_ADDR_MODE_FIXED = 0, + + /** Offset is added to the address pointer after each transfer. */ + TRANSFER_ADDR_MODE_OFFSET = 1, + + /** Address pointer is incremented by associated @ref transfer_size_t after each transfer. */ + TRANSFER_ADDR_MODE_INCREMENTED = 2, + + /** Address pointer is decremented by associated @ref transfer_size_t after each transfer. */ + TRANSFER_ADDR_MODE_DECREMENTED = 3 +} transfer_addr_mode_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_REPEAT_AREA_T + +/** Repeat area options (source or destination). In @ref TRANSFER_MODE_REPEAT, the selected pointer returns to its + * original value after transfer_info_t::length transfers. In @ref TRANSFER_MODE_BLOCK and @ref TRANSFER_MODE_REPEAT_BLOCK, + * the selected pointer returns to its original value after each transfer. */ +typedef enum e_transfer_repeat_area +{ + /** Destination area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */ + TRANSFER_REPEAT_AREA_DESTINATION = 0, + + /** Source area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */ + TRANSFER_REPEAT_AREA_SOURCE = 1 +} transfer_repeat_area_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_CHAIN_MODE_T + +/** Chain transfer mode options. + * @note Only applies for DTC. */ +typedef enum e_transfer_chain_mode +{ + /** Chain mode not used. */ + TRANSFER_CHAIN_MODE_DISABLED = 0, + + /** Switch to next transfer after a single transfer from this @ref transfer_info_t. */ + TRANSFER_CHAIN_MODE_EACH = 2, + + /** Complete the entire transfer defined in this @ref transfer_info_t before chaining to next transfer. */ + TRANSFER_CHAIN_MODE_END = 3 +} transfer_chain_mode_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_IRQ_T + +/** Interrupt options. */ +typedef enum e_transfer_irq +{ + /** Interrupt occurs only after last transfer. If this transfer is chained to a subsequent transfer, + * the interrupt will occur only after subsequent chained transfer(s) are complete. + * @warning DTC triggers the interrupt of the activation source. Choosing TRANSFER_IRQ_END with DTC will + * prevent activation source interrupts until the transfer is complete. */ + TRANSFER_IRQ_END = 0, + + /** Interrupt occurs after each transfer. + * @note Not available in all HAL drivers. See HAL driver for details. */ + TRANSFER_IRQ_EACH = 1 +} transfer_irq_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_CALLBACK_ARGS_T + +/** Callback function parameter data. */ +typedef struct st_transfer_callback_args_t +{ + void * p_context; ///< Placeholder for user data. Set in @ref transfer_api_t::open function in ::transfer_cfg_t. +} transfer_callback_args_t; + +#endif + +/** Driver specific information. */ +typedef struct st_transfer_properties +{ + uint32_t block_count_max; ///< Maximum number of blocks + uint32_t block_count_remaining; ///< Number of blocks remaining + uint32_t transfer_length_max; ///< Maximum number of transfers + uint32_t transfer_length_remaining; ///< Number of transfers remaining +} transfer_properties_t; + +#ifndef BSP_OVERRIDE_TRANSFER_INFO_T + +/** This structure specifies the properties of the transfer. + * @warning When using DTC, this structure corresponds to the descriptor block registers required by the DTC. + * The following components may be modified by the driver: p_src, p_dest, num_blocks, and length. + * @warning When using DTC, do NOT reuse this structure to configure multiple transfers. Each transfer must + * have a unique transfer_info_t. + * @warning When using DTC, this structure must not be allocated in a temporary location. Any instance of this + * structure must remain in scope until the transfer it is used for is closed. + * @note When using DTC, consider placing instances of this structure in a protected section of memory. */ +typedef struct st_transfer_info +{ + union + { + struct + { + uint32_t : 16; + uint32_t : 2; + + /** Select what happens to destination pointer after each transfer. */ + transfer_addr_mode_t dest_addr_mode : 2; + + /** Select to repeat source or destination area, unused in @ref TRANSFER_MODE_NORMAL. */ + transfer_repeat_area_t repeat_area : 1; + + /** Select if interrupts should occur after each individual transfer or after the completion of all planned + * transfers. */ + transfer_irq_t irq : 1; + + /** Select when the chain transfer ends. */ + transfer_chain_mode_t chain_mode : 2; + + uint32_t : 2; + + /** Select what happens to source pointer after each transfer. */ + transfer_addr_mode_t src_addr_mode : 2; + + /** Select number of bytes to transfer at once. @see transfer_info_t::length. */ + transfer_size_t size : 2; + + /** Select mode from @ref transfer_mode_t. */ + transfer_mode_t mode : 2; + } transfer_settings_word_b; + + uint32_t transfer_settings_word; + }; + + void const * volatile p_src; ///< Source pointer + void * volatile p_dest; ///< Destination pointer + + /** Number of blocks to transfer when using @ref TRANSFER_MODE_BLOCK (both DTC an DMAC) or + * @ref TRANSFER_MODE_REPEAT (DMAC only) or + * @ref TRANSFER_MODE_REPEAT_BLOCK (DMAC only), unused in other modes. */ + volatile uint16_t num_blocks; + + /** Length of each transfer. Range limited for @ref TRANSFER_MODE_BLOCK, @ref TRANSFER_MODE_REPEAT, + * and @ref TRANSFER_MODE_REPEAT_BLOCK + * see HAL driver for details. */ + volatile uint16_t length; +} transfer_info_t; + +#endif + +/** Driver configuration set in @ref transfer_api_t::open. All elements except p_extend are required and must be + * initialized. */ +typedef struct st_transfer_cfg +{ + /** Pointer to transfer configuration options. If using chain transfer (DTC only), this can be a pointer to + * an array of chained transfers that will be completed in order. */ + transfer_info_t * p_info; + + void const * p_extend; ///< Extension parameter for hardware specific settings. +} transfer_cfg_t; + +/** Select whether to start single or repeated transfer with software start. */ +typedef enum e_transfer_start_mode +{ + TRANSFER_START_MODE_SINGLE = 0, ///< Software start triggers single transfer. + TRANSFER_START_MODE_REPEAT = 1 ///< Software start transfer continues until transfer is complete. +} transfer_start_mode_t; + +/** Transfer functions implemented at the HAL layer will follow this API. */ +typedef struct st_transfer_api +{ + /** Initial configuration. + * + * @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here. + * @param[in] p_cfg Pointer to configuration structure. All elements of this structure + * must be set by user. + */ + fsp_err_t (* open)(transfer_ctrl_t * const p_ctrl, transfer_cfg_t const * const p_cfg); + + /** Reconfigure the transfer. + * Enable the transfer if p_info is valid. + * + * @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here. + * @param[in] p_info Pointer to a new transfer info structure. + */ + fsp_err_t (* reconfigure)(transfer_ctrl_t * const p_ctrl, transfer_info_t * p_info); + + /** Reset source address pointer, destination address pointer, and/or length, keeping all other settings the same. + * Enable the transfer if p_src, p_dest, and length are valid. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[in] p_src Pointer to source. Set to NULL if source pointer should not change. + * @param[in] p_dest Pointer to destination. Set to NULL if destination pointer should not change. + * @param[in] num_transfers Transfer length in normal mode or number of blocks in block mode. In DMAC only, + * resets number of repeats (initially stored in transfer_info_t::num_blocks) in + * repeat mode. Not used in repeat mode for DTC. + */ + fsp_err_t (* reset)(transfer_ctrl_t * const p_ctrl, void const * p_src, void * p_dest, + uint16_t const num_transfers); + + /** Enable transfer. Transfers occur after the activation source event (or when + * @ref transfer_api_t::softwareStart is called if no peripheral event is chosen as activation source). + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + */ + fsp_err_t (* enable)(transfer_ctrl_t * const p_ctrl); + + /** Disable transfer. Transfers do not occur after the activation source event (or when + * @ref transfer_api_t::softwareStart is called if no peripheral event is chosen as the DMAC activation source). + * @note If a transfer is in progress, it will be completed. Subsequent transfer requests do not cause a + * transfer. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + */ + fsp_err_t (* disable)(transfer_ctrl_t * const p_ctrl); + + /** Start transfer in software. + * @warning Only works if no peripheral event is chosen as the DMAC activation source. + * @note Not supported for DTC. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[in] mode Select mode from @ref transfer_start_mode_t. + */ + fsp_err_t (* softwareStart)(transfer_ctrl_t * const p_ctrl, transfer_start_mode_t mode); + + /** Stop transfer in software. The transfer will stop after completion of the current transfer. + * @note Not supported for DTC. + * @note Only applies for transfers started with TRANSFER_START_MODE_REPEAT. + * @warning Only works if no peripheral event is chosen as the DMAC activation source. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + */ + fsp_err_t (* softwareStop)(transfer_ctrl_t * const p_ctrl); + + /** Provides information about this transfer. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[out] p_properties Driver specific information. + */ + fsp_err_t (* infoGet)(transfer_ctrl_t * const p_ctrl, transfer_properties_t * const p_properties); + + /** Releases hardware lock. This allows a transfer to be reconfigured using @ref transfer_api_t::open. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + */ + fsp_err_t (* close)(transfer_ctrl_t * const p_ctrl); + + /** To update next transfer information without interruption during transfer. + * Allow further transfer continuation. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[in] p_src Pointer to source. Set to NULL if source pointer should not change. + * @param[in] p_dest Pointer to destination. Set to NULL if destination pointer should not change. + * @param[in] num_transfers Transfer length in normal mode or block mode. + */ + fsp_err_t (* reload)(transfer_ctrl_t * const p_ctrl, void const * p_src, void * p_dest, + uint32_t const num_transfers); + + /** Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[in] p_callback Callback function to register + * @param[in] p_context Pointer to send to callback function + * @param[in] p_callback_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(transfer_ctrl_t * const p_ctrl, void (* p_callback)(transfer_callback_args_t *), + void * const p_context, transfer_callback_args_t * const p_callback_memory); +} transfer_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_transfer_instance +{ + transfer_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + transfer_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + transfer_api_t const * p_api; ///< Pointer to the API structure for this instance +} transfer_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup TRANSFER_API) + **********************************************************************************************************************/ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_uart_api.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_uart_api.h new file mode 100644 index 00000000000..db1a63a8478 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/api/r_uart_api.h @@ -0,0 +1,267 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_CONNECTIVITY_INTERFACES + * @defgroup UART_API UART Interface + * @brief Interface for UART communications. + * + * @section UART_INTERFACE_SUMMARY Summary + * The UART interface provides common APIs for UART HAL drivers. The UART interface supports the following features: + * - Full-duplex UART communication + * - Interrupt driven transmit/receive processing + * - Callback function with returned event code + * - Runtime baud-rate change + * - Hardware resource locking during a transaction + * - CTS/RTS hardware flow control support (with an associated IOPORT pin) + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_UART_API_H +#define R_UART_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" +#include "r_transfer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** UART Event codes */ +#ifndef BSP_OVERRIDE_UART_EVENT_T +typedef enum e_sf_event +{ + UART_EVENT_RX_COMPLETE = (1UL << 0), ///< Receive complete event + UART_EVENT_TX_COMPLETE = (1UL << 1), ///< Transmit complete event + UART_EVENT_RX_CHAR = (1UL << 2), ///< Character received + UART_EVENT_ERR_PARITY = (1UL << 3), ///< Parity error event + UART_EVENT_ERR_FRAMING = (1UL << 4), ///< Mode fault error event + UART_EVENT_ERR_OVERFLOW = (1UL << 5), ///< FIFO Overflow error event + UART_EVENT_BREAK_DETECT = (1UL << 6), ///< Break detect error event + UART_EVENT_TX_DATA_EMPTY = (1UL << 7), ///< Last byte is transmitting, ready for more data +} uart_event_t; +#endif +#ifndef BSP_OVERRIDE_UART_DATA_BITS_T + +/** UART Data bit length definition */ +typedef enum e_uart_data_bits +{ + UART_DATA_BITS_9 = 0U, ///< Data bits 9-bit + UART_DATA_BITS_8 = 2U, ///< Data bits 8-bit + UART_DATA_BITS_7 = 3U, ///< Data bits 7-bit +} uart_data_bits_t; +#endif +#ifndef BSP_OVERRIDE_UART_PARITY_T + +/** UART Parity definition */ +typedef enum e_uart_parity +{ + UART_PARITY_OFF = 0U, ///< No parity + UART_PARITY_ZERO = 1U, ///< Zero parity + UART_PARITY_EVEN = 2U, ///< Even parity + UART_PARITY_ODD = 3U, ///< Odd parity +} uart_parity_t; +#endif + +/** UART Stop bits definition */ +typedef enum e_uart_stop_bits +{ + UART_STOP_BITS_1 = 0U, ///< Stop bit 1-bit + UART_STOP_BITS_2 = 1U, ///< Stop bits 2-bit +} uart_stop_bits_t; + +/** UART transaction definition */ +typedef enum e_uart_dir +{ + UART_DIR_RX_TX = 3U, ///< Both RX and TX + UART_DIR_RX = 1U, ///< Only RX + UART_DIR_TX = 2U, ///< Only TX +} uart_dir_t; + +/** UART driver specific information */ +typedef struct st_uart_info +{ + /** Maximum bytes that can be written at this time. Only applies if uart_cfg_t::p_transfer_tx is not NULL. */ + uint32_t write_bytes_max; + + /** Maximum bytes that are available to read at one time. Only applies if uart_cfg_t::p_transfer_rx is not NULL. */ + uint32_t read_bytes_max; +} uart_info_t; + +/** UART Callback parameter definition */ +typedef struct st_uart_callback_arg +{ + uint32_t channel; ///< Device channel number + uart_event_t event; ///< Event code + + /** Contains the next character received for the events UART_EVENT_RX_CHAR, UART_EVENT_ERR_PARITY, + * UART_EVENT_ERR_FRAMING, or UART_EVENT_ERR_OVERFLOW. Otherwise unused. */ + uint32_t data; + void * p_context; ///< Context provided to user during callback +} uart_callback_args_t; + +/** UART Configuration */ +typedef struct st_uart_cfg +{ + /* UART generic configuration */ + uint8_t channel; ///< Select a channel corresponding to the channel number of the hardware. + uart_data_bits_t data_bits; ///< Data bit length (8 or 7 or 9) + uart_parity_t parity; ///< Parity type (none or odd or even) + uart_stop_bits_t stop_bits; ///< Stop bit length (1 or 2) + uint8_t rxi_ipl; ///< Receive interrupt priority + IRQn_Type rxi_irq; ///< Receive interrupt IRQ number + uint8_t txi_ipl; ///< Transmit interrupt priority + IRQn_Type txi_irq; ///< Transmit interrupt IRQ number + uint8_t tei_ipl; ///< Transmit end interrupt priority + IRQn_Type tei_irq; ///< Transmit end interrupt IRQ number + uint8_t eri_ipl; ///< Error interrupt priority + IRQn_Type eri_irq; ///< Error interrupt IRQ number + + /** Optional transfer instance used to receive multiple bytes without interrupts. Set to NULL if unused. + * If NULL, the number of bytes allowed in the read API is limited to one byte at a time. */ + transfer_instance_t const * p_transfer_rx; + + /** Optional transfer instance used to send multiple bytes without interrupts. Set to NULL if unused. + * If NULL, the number of bytes allowed in the write APIs is limited to one byte at a time. */ + transfer_instance_t const * p_transfer_tx; + + /* Configuration for UART Event processing */ + void (* p_callback)(uart_callback_args_t * p_args); ///< Pointer to callback function + void * p_context; ///< User defined context passed into callback function + + /* Pointer to UART peripheral specific configuration */ + void const * p_extend; ///< UART hardware dependent configuration +} uart_cfg_t; + +/** UART control block. Allocate an instance specific control block to pass into the UART API calls. + */ +typedef void uart_ctrl_t; + +/** Shared Interface definition for UART */ +typedef struct st_uart_api +{ + /** Open UART device. + * + * @param[in,out] p_ctrl Pointer to the UART control block. Must be declared by user. Value set here. + * @param[in] uart_cfg_t Pointer to UART configuration structure. All elements of this structure must be set by + * user. + */ + fsp_err_t (* open)(uart_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg); + + /** Read from UART device. The read buffer is used until the read is complete. When a transfer is complete, the + * callback is called with event UART_EVENT_RX_COMPLETE. Bytes received outside an active transfer are received in + * the callback function with event UART_EVENT_RX_CHAR. + * The maximum transfer size is reported by infoGet(). + * + * @param[in] p_ctrl Pointer to the UART control block for the channel. + * @param[in] p_dest Destination address to read data from. + * @param[in] bytes Read data length. + */ + fsp_err_t (* read)(uart_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes); + + /** Write to UART device. The write buffer is used until write is complete. Do not overwrite write buffer + * contents until the write is finished. When the write is complete (all bytes are fully transmitted on the wire), + * the callback called with event UART_EVENT_TX_COMPLETE. + * The maximum transfer size is reported by infoGet(). + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] p_src Source address to write data to. + * @param[in] bytes Write data length. + */ + fsp_err_t (* write)(uart_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint32_t const bytes); + + /** Change baud rate. + * @warning Calling this API aborts any in-progress transmission and disables reception until the new baud + * settings have been applied. + * + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] p_baudrate_info Pointer to module specific information for configuring baud rate. + */ + fsp_err_t (* baudSet)(uart_ctrl_t * const p_ctrl, void const * const p_baudrate_info); + + /** Get the driver specific information. + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[out] p_info Pointer to UART information structure. + */ + fsp_err_t (* infoGet)(uart_ctrl_t * const p_ctrl, uart_info_t * const p_info); + + /** + * Abort ongoing transfer. + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] communication_to_abort Type of abort request. + */ + fsp_err_t (* communicationAbort)(uart_ctrl_t * const p_ctrl, uart_dir_t communication_to_abort); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(uart_ctrl_t * const p_ctrl, void (* p_callback)(uart_callback_args_t *), + void * const p_context, uart_callback_args_t * const p_callback_memory); + + /** Close UART device. + * + * @param[in] p_ctrl Pointer to the UART control block. + */ + fsp_err_t (* close)(uart_ctrl_t * const p_ctrl); + + /** Stop ongoing read and return the number of bytes remaining in the read. + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in,out] remaining_bytes Pointer to location to store remaining bytes for read. + */ + fsp_err_t (* readStop)(uart_ctrl_t * const p_ctrl, uint32_t * remaining_bytes); + + /** Suspend RX operations for UART device. + * + * @param[in] p_ctrl Pointer to the UART control block. + */ + fsp_err_t (* receiveSuspend)(uart_ctrl_t * const p_ctrl); + + + /** Resume RX operations for UART device. + * + * @param[in] p_ctrl Pointer to the UART control block. + */ + fsp_err_t (* receiveResume)(uart_ctrl_t * const p_ctrl); +} uart_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_uart_instance +{ + uart_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + uart_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + uart_api_t const * p_api; ///< Pointer to the API structure for this instance +} uart_instance_t; + +/** @} (end defgroup UART_API) */ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/fsp_features.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/fsp_features.h new file mode 100644 index 00000000000..dd54197d7d8 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/fsp_features.h @@ -0,0 +1,297 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef FSP_FEATURES_H +#define FSP_FEATURES_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* C99 includes. */ +#include +#include +#include +#include + +/* Different compiler support. */ +#include "fsp_common_api.h" +#include "../../fsp/src/bsp/mcu/all/bsp_compiler_support.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Available modules. */ +typedef enum e_fsp_ip +{ + FSP_IP_CFLASH = 0, ///< Code Flash + FSP_IP_DFLASH = 1, ///< Data Flash + FSP_IP_RAM = 2, ///< RAM + FSP_IP_LVD = 3, ///< Low Voltage Detection + FSP_IP_CGC = 3, ///< Clock Generation Circuit + FSP_IP_LPM = 3, ///< Low Power Modes + FSP_IP_FCU = 4, ///< Flash Control Unit + FSP_IP_ICU = 6, ///< Interrupt Control Unit + FSP_IP_DMAC = 7, ///< DMA Controller + FSP_IP_DTC = 8, ///< Data Transfer Controller + FSP_IP_IOPORT = 9, ///< I/O Ports + FSP_IP_PFS = 10, ///< Pin Function Select + FSP_IP_ELC = 11, ///< Event Link Controller + FSP_IP_MPU = 13, ///< Memory Protection Unit + FSP_IP_MSTP = 14, ///< Module Stop + FSP_IP_MMF = 15, ///< Memory Mirror Function + FSP_IP_KEY = 16, ///< Key Interrupt Function + FSP_IP_CAC = 17, ///< Clock Frequency Accuracy Measurement Circuit + FSP_IP_DOC = 18, ///< Data Operation Circuit + FSP_IP_CRC = 19, ///< Cyclic Redundancy Check Calculator + FSP_IP_SCI = 20, ///< Serial Communications Interface + FSP_IP_IIC = 21, ///< I2C Bus Interface + FSP_IP_SPI = 22, ///< Serial Peripheral Interface + FSP_IP_CTSU = 23, ///< Capacitive Touch Sensing Unit + FSP_IP_SCE = 24, ///< Secure Cryptographic Engine + FSP_IP_SLCDC = 25, ///< Segment LCD Controller + FSP_IP_AES = 26, ///< Advanced Encryption Standard + FSP_IP_TRNG = 27, ///< True Random Number Generator + FSP_IP_FCACHE = 30, ///< Flash Cache + FSP_IP_SRAM = 31, ///< SRAM + FSP_IP_ADC = 32, ///< A/D Converter + FSP_IP_DAC = 33, ///< 12-Bit D/A Converter + FSP_IP_TSN = 34, ///< Temperature Sensor + FSP_IP_DAAD = 35, ///< D/A A/D Synchronous Unit + FSP_IP_ACMPHS = 36, ///< High Speed Analog Comparator + FSP_IP_ACMPLP = 37, ///< Low Power Analog Comparator + FSP_IP_OPAMP = 38, ///< Operational Amplifier + FSP_IP_SDADC = 39, ///< Sigma Delta A/D Converter + FSP_IP_RTC = 40, ///< Real Time Clock + FSP_IP_WDT = 41, ///< Watch Dog Timer + FSP_IP_IWDT = 42, ///< Independent Watch Dog Timer + FSP_IP_GPT = 43, ///< General PWM Timer + FSP_IP_POEG = 44, ///< Port Output Enable for GPT + FSP_IP_OPS = 45, ///< Output Phase Switch + FSP_IP_AGT = 47, ///< Asynchronous General-Purpose Timer + FSP_IP_CAN = 48, ///< Controller Area Network + FSP_IP_IRDA = 49, ///< Infrared Data Association + FSP_IP_QSPI = 50, ///< Quad Serial Peripheral Interface + FSP_IP_USBFS = 51, ///< USB Full Speed + FSP_IP_SDHI = 52, ///< SD/MMC Host Interface + FSP_IP_SRC = 53, ///< Sampling Rate Converter + FSP_IP_SSI = 54, ///< Serial Sound Interface + FSP_IP_DALI = 55, ///< Digital Addressable Lighting Interface + FSP_IP_ETHER = 64, ///< Ethernet MAC Controller + FSP_IP_EDMAC = 64, ///< Ethernet DMA Controller + FSP_IP_EPTPC = 65, ///< Ethernet PTP Controller + FSP_IP_PDC = 66, ///< Parallel Data Capture Unit + FSP_IP_GLCDC = 67, ///< Graphics LCD Controller + FSP_IP_DRW = 68, ///< 2D Drawing Engine + FSP_IP_JPEG = 69, ///< JPEG + FSP_IP_DAC8 = 70, ///< 8-Bit D/A Converter + FSP_IP_USBHS = 71, ///< USB High Speed + FSP_IP_OSPI = 72, ///< Octa Serial Peripheral Interface + FSP_IP_CEC = 73, ///< HDMI CEC + FSP_IP_TFU = 74, ///< Trigonometric Function Unit + FSP_IP_IIRFA = 75, ///< IIR Filter Accelerator + FSP_IP_CANFD = 76, ///< CAN-FD + FSP_IP_ULPT = 77, ///< Ultra Low Power Timer ULPT + FSP_IP_SAU = 78, ///< Serial Array Unit + FSP_IP_IICA = 79, ///< Serial Interface IICA + FSP_IP_UARTA = 80, ///< Serial Interface UARTA + FSP_IP_TAU = 81, ///< Timer Array Unit + FSP_IP_TML = 82, ///< 32-bit Interval Timer + FSP_IP_MACL = 83, ///< 32-bit Multiply-Accumulator + FSP_IP_USBCC = 84, ///< USB Type-C Controller +} fsp_ip_t; + +/** Signals that can be mapped to an interrupt. */ +typedef enum e_fsp_signal +{ + FSP_SIGNAL_ADC_COMPARE_MATCH = 0, ///< ADC COMPARE MATCH + FSP_SIGNAL_ADC_COMPARE_MISMATCH, ///< ADC COMPARE MISMATCH + FSP_SIGNAL_ADC_SCAN_END, ///< ADC SCAN END + FSP_SIGNAL_ADC_SCAN_END_B, ///< ADC SCAN END B + FSP_SIGNAL_ADC_WINDOW_A, ///< ADC WINDOW A + FSP_SIGNAL_ADC_WINDOW_B, ///< ADC WINDOW B + FSP_SIGNAL_AES_RDREQ = 0, ///< AES RDREQ + FSP_SIGNAL_AES_WRREQ, ///< AES WRREQ + FSP_SIGNAL_AGT_COMPARE_A = 0, ///< AGT COMPARE A + FSP_SIGNAL_AGT_COMPARE_B, ///< AGT COMPARE B + FSP_SIGNAL_AGT_INT, ///< AGT INT + FSP_SIGNAL_CAC_FREQUENCY_ERROR = 0, ///< CAC FREQUENCY ERROR + FSP_SIGNAL_CAC_MEASUREMENT_END, ///< CAC MEASUREMENT END + FSP_SIGNAL_CAC_OVERFLOW, ///< CAC OVERFLOW + FSP_SIGNAL_CAN_ERROR = 0, ///< CAN ERROR + FSP_SIGNAL_CAN_FIFO_RX, ///< CAN FIFO RX + FSP_SIGNAL_CAN_FIFO_TX, ///< CAN FIFO TX + FSP_SIGNAL_CAN_MAILBOX_RX, ///< CAN MAILBOX RX + FSP_SIGNAL_CAN_MAILBOX_TX, ///< CAN MAILBOX TX + FSP_SIGNAL_CGC_MOSC_STOP = 0, ///< CGC MOSC STOP + FSP_SIGNAL_LPM_SNOOZE_REQUEST, ///< LPM SNOOZE REQUEST + FSP_SIGNAL_LVD_LVD1, ///< LVD LVD1 + FSP_SIGNAL_LVD_LVD2, ///< LVD LVD2 + FSP_SIGNAL_VBATT_LVD, ///< VBATT LVD + FSP_SIGNAL_LVD_VBATT = FSP_SIGNAL_VBATT_LVD, ///< LVD VBATT + FSP_SIGNAL_ACMPHS_INT = 0, ///< ACMPHS INT + FSP_SIGNAL_ACMPLP_INT = 0, ///< ACMPLP INT + FSP_SIGNAL_CTSU_END = 0, ///< CTSU END + FSP_SIGNAL_CTSU_READ, ///< CTSU READ + FSP_SIGNAL_CTSU_WRITE, ///< CTSU WRITE + FSP_SIGNAL_DALI_DEI = 0, ///< DALI DEI + FSP_SIGNAL_DALI_CLI, ///< DALI CLI + FSP_SIGNAL_DALI_SDI, ///< DALI SDI + FSP_SIGNAL_DALI_BPI, ///< DALI BPI + FSP_SIGNAL_DALI_FEI, ///< DALI FEI + FSP_SIGNAL_DALI_SDI_OR_BPI, ///< DALI SDI OR BPI + FSP_SIGNAL_DMAC_INT = 0, ///< DMAC INT + FSP_SIGNAL_DOC_INT = 0, ///< DOC INT + FSP_SIGNAL_DRW_INT = 0, ///< DRW INT + FSP_SIGNAL_DTC_COMPLETE = 0, ///< DTC COMPLETE + FSP_SIGNAL_DTC_END, ///< DTC END + FSP_SIGNAL_EDMAC_EINT = 0, ///< EDMAC EINT + FSP_SIGNAL_ELC_SOFTWARE_EVENT_0 = 0, ///< ELC SOFTWARE EVENT 0 + FSP_SIGNAL_ELC_SOFTWARE_EVENT_1, ///< ELC SOFTWARE EVENT 1 + FSP_SIGNAL_EPTPC_IPLS = 0, ///< EPTPC IPLS + FSP_SIGNAL_EPTPC_MINT, ///< EPTPC MINT + FSP_SIGNAL_EPTPC_PINT, ///< EPTPC PINT + FSP_SIGNAL_EPTPC_TIMER0_FALL, ///< EPTPC TIMER0 FALL + FSP_SIGNAL_EPTPC_TIMER0_RISE, ///< EPTPC TIMER0 RISE + FSP_SIGNAL_EPTPC_TIMER1_FALL, ///< EPTPC TIMER1 FALL + FSP_SIGNAL_EPTPC_TIMER1_RISE, ///< EPTPC TIMER1 RISE + FSP_SIGNAL_EPTPC_TIMER2_FALL, ///< EPTPC TIMER2 FALL + FSP_SIGNAL_EPTPC_TIMER2_RISE, ///< EPTPC TIMER2 RISE + FSP_SIGNAL_EPTPC_TIMER3_FALL, ///< EPTPC TIMER3 FALL + FSP_SIGNAL_EPTPC_TIMER3_RISE, ///< EPTPC TIMER3 RISE + FSP_SIGNAL_EPTPC_TIMER4_FALL, ///< EPTPC TIMER4 FALL + FSP_SIGNAL_EPTPC_TIMER4_RISE, ///< EPTPC TIMER4 RISE + FSP_SIGNAL_EPTPC_TIMER5_FALL, ///< EPTPC TIMER5 FALL + FSP_SIGNAL_EPTPC_TIMER5_RISE, ///< EPTPC TIMER5 RISE + FSP_SIGNAL_FCU_FIFERR = 0, ///< FCU FIFERR + FSP_SIGNAL_FCU_FRDYI, ///< FCU FRDYI + FSP_SIGNAL_GLCDC_LINE_DETECT = 0, ///< GLCDC LINE DETECT + FSP_SIGNAL_GLCDC_UNDERFLOW_1, ///< GLCDC UNDERFLOW 1 + FSP_SIGNAL_GLCDC_UNDERFLOW_2, ///< GLCDC UNDERFLOW 2 + FSP_SIGNAL_GPT_CAPTURE_COMPARE_A = 0, ///< GPT CAPTURE COMPARE A + FSP_SIGNAL_GPT_CAPTURE_COMPARE_B, ///< GPT CAPTURE COMPARE B + FSP_SIGNAL_GPT_COMPARE_C, ///< GPT COMPARE C + FSP_SIGNAL_GPT_COMPARE_D, ///< GPT COMPARE D + FSP_SIGNAL_GPT_COMPARE_E, ///< GPT COMPARE E + FSP_SIGNAL_GPT_COMPARE_F, ///< GPT COMPARE F + FSP_SIGNAL_GPT_COUNTER_OVERFLOW, ///< GPT COUNTER OVERFLOW + FSP_SIGNAL_GPT_COUNTER_UNDERFLOW, ///< GPT COUNTER UNDERFLOW + FSP_SIGNAL_GPT_AD_TRIG_A, ///< GPT AD TRIG A + FSP_SIGNAL_GPT_AD_TRIG_B, ///< GPT AD TRIG B + FSP_SIGNAL_OPS_UVW_EDGE, ///< OPS UVW EDGE + FSP_SIGNAL_ICU_IRQ0 = 0, ///< ICU IRQ0 + FSP_SIGNAL_ICU_IRQ1, ///< ICU IRQ1 + FSP_SIGNAL_ICU_IRQ2, ///< ICU IRQ2 + FSP_SIGNAL_ICU_IRQ3, ///< ICU IRQ3 + FSP_SIGNAL_ICU_IRQ4, ///< ICU IRQ4 + FSP_SIGNAL_ICU_IRQ5, ///< ICU IRQ5 + FSP_SIGNAL_ICU_IRQ6, ///< ICU IRQ6 + FSP_SIGNAL_ICU_IRQ7, ///< ICU IRQ7 + FSP_SIGNAL_ICU_IRQ8, ///< ICU IRQ8 + FSP_SIGNAL_ICU_IRQ9, ///< ICU IRQ9 + FSP_SIGNAL_ICU_IRQ10, ///< ICU IRQ10 + FSP_SIGNAL_ICU_IRQ11, ///< ICU IRQ11 + FSP_SIGNAL_ICU_IRQ12, ///< ICU IRQ12 + FSP_SIGNAL_ICU_IRQ13, ///< ICU IRQ13 + FSP_SIGNAL_ICU_IRQ14, ///< ICU IRQ14 + FSP_SIGNAL_ICU_IRQ15, ///< ICU IRQ15 + FSP_SIGNAL_ICU_SNOOZE_CANCEL, ///< ICU SNOOZE CANCEL + FSP_SIGNAL_IIC_ERI = 0, ///< IIC ERI + FSP_SIGNAL_IIC_RXI, ///< IIC RXI + FSP_SIGNAL_IIC_TEI, ///< IIC TEI + FSP_SIGNAL_IIC_TXI, ///< IIC TXI + FSP_SIGNAL_IIC_WUI, ///< IIC WUI + FSP_SIGNAL_IOPORT_EVENT_1 = 0, ///< IOPORT EVENT 1 + FSP_SIGNAL_IOPORT_EVENT_2, ///< IOPORT EVENT 2 + FSP_SIGNAL_IOPORT_EVENT_3, ///< IOPORT EVENT 3 + FSP_SIGNAL_IOPORT_EVENT_4, ///< IOPORT EVENT 4 + FSP_SIGNAL_IOPORT_EVENT_B = 0, ///< IOPORT EVENT B + FSP_SIGNAL_IOPORT_EVENT_C, ///< IOPORT EVENT C + FSP_SIGNAL_IOPORT_EVENT_D, ///< IOPORT EVENT D + FSP_SIGNAL_IOPORT_EVENT_E, ///< IOPORT EVENT E + FSP_SIGNAL_IWDT_UNDERFLOW = 0, ///< IWDT UNDERFLOW + FSP_SIGNAL_JPEG_JDTI = 0, ///< JPEG JDTI + FSP_SIGNAL_JPEG_JEDI, ///< JPEG JEDI + FSP_SIGNAL_KEY_INT = 0, ///< KEY INT + FSP_SIGNAL_PDC_FRAME_END = 0, ///< PDC FRAME END + FSP_SIGNAL_PDC_INT, ///< PDC INT + FSP_SIGNAL_PDC_RECEIVE_DATA_READY, ///< PDC RECEIVE DATA READY + FSP_SIGNAL_POEG_EVENT = 0, ///< POEG EVENT + FSP_SIGNAL_QSPI_INT = 0, ///< QSPI INT + FSP_SIGNAL_RTC_ALARM = 0, ///< RTC ALARM + FSP_SIGNAL_RTC_PERIOD, ///< RTC PERIOD + FSP_SIGNAL_RTC_CARRY, ///< RTC CARRY + FSP_SIGNAL_SCE_INTEGRATE_RDRDY = 0, ///< SCE INTEGRATE RDRDY + FSP_SIGNAL_SCE_INTEGRATE_WRRDY, ///< SCE INTEGRATE WRRDY + FSP_SIGNAL_SCE_LONG_PLG, ///< SCE LONG PLG + FSP_SIGNAL_SCE_PROC_BUSY, ///< SCE PROC BUSY + FSP_SIGNAL_SCE_RDRDY_0, ///< SCE RDRDY 0 + FSP_SIGNAL_SCE_RDRDY_1, ///< SCE RDRDY 1 + FSP_SIGNAL_SCE_ROMOK, ///< SCE ROMOK + FSP_SIGNAL_SCE_TEST_BUSY, ///< SCE TEST BUSY + FSP_SIGNAL_SCE_WRRDY_0, ///< SCE WRRDY 0 + FSP_SIGNAL_SCE_WRRDY_1, ///< SCE WRRDY 1 + FSP_SIGNAL_SCE_WRRDY_4, ///< SCE WRRDY 4 + FSP_SIGNAL_SCI_AM = 0, ///< SCI AM + FSP_SIGNAL_SCI_ERI, ///< SCI ERI + FSP_SIGNAL_SCI_RXI, ///< SCI RXI + FSP_SIGNAL_SCI_RXI_OR_ERI, ///< SCI RXI OR ERI + FSP_SIGNAL_SCI_TEI, ///< SCI TEI + FSP_SIGNAL_SCI_TXI, ///< SCI TXI + FSP_SIGNAL_SDADC_ADI = 0, ///< SDADC ADI + FSP_SIGNAL_SDADC_SCANEND, ///< SDADC SCANEND + FSP_SIGNAL_SDADC_CALIEND, ///< SDADC CALIEND + FSP_SIGNAL_SDHIMMC_ACCS = 0, ///< SDHIMMC ACCS + FSP_SIGNAL_SDHIMMC_CARD, ///< SDHIMMC CARD + FSP_SIGNAL_SDHIMMC_DMA_REQ, ///< SDHIMMC DMA REQ + FSP_SIGNAL_SDHIMMC_SDIO, ///< SDHIMMC SDIO + FSP_SIGNAL_SPI_ERI = 0, ///< SPI ERI + FSP_SIGNAL_SPI_IDLE, ///< SPI IDLE + FSP_SIGNAL_SPI_RXI, ///< SPI RXI + FSP_SIGNAL_SPI_TEI, ///< SPI TEI + FSP_SIGNAL_SPI_TXI, ///< SPI TXI + FSP_SIGNAL_SRC_CONVERSION_END = 0, ///< SRC CONVERSION END + FSP_SIGNAL_SRC_INPUT_FIFO_EMPTY, ///< SRC INPUT FIFO EMPTY + FSP_SIGNAL_SRC_OUTPUT_FIFO_FULL, ///< SRC OUTPUT FIFO FULL + FSP_SIGNAL_SRC_OUTPUT_FIFO_OVERFLOW, ///< SRC OUTPUT FIFO OVERFLOW + FSP_SIGNAL_SRC_OUTPUT_FIFO_UNDERFLOW, ///< SRC OUTPUT FIFO UNDERFLOW + FSP_SIGNAL_SSI_INT = 0, ///< SSI INT + FSP_SIGNAL_SSI_RXI, ///< SSI RXI + FSP_SIGNAL_SSI_TXI, ///< SSI TXI + FSP_SIGNAL_SSI_TXI_RXI, ///< SSI TXI RXI + FSP_SIGNAL_TRNG_RDREQ = 0, ///< TRNG RDREQ + FSP_SIGNAL_USB_FIFO_0 = 0, ///< USB FIFO 0 + FSP_SIGNAL_USB_FIFO_1, ///< USB FIFO 1 + FSP_SIGNAL_USB_INT, ///< USB INT + FSP_SIGNAL_USB_RESUME, ///< USB RESUME + FSP_SIGNAL_USB_USB_INT_RESUME, ///< USB USB INT RESUME + FSP_SIGNAL_WDT_UNDERFLOW = 0, ///< WDT UNDERFLOW + FSP_SIGNAL_ULPT_COMPARE_A = 0, ///< ULPT COMPARE A + FSP_SIGNAL_ULPT_COMPARE_B, ///< ULPT COMPARE B + FSP_SIGNAL_ULPT_INT, ///< ULPT INT +} fsp_signal_t; + +typedef void (* fsp_vector_t)(void); + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/fsp_version.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/fsp_version.h new file mode 100644 index 00000000000..49bab014b88 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/fsp_version.h @@ -0,0 +1,76 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef FSP_VERSION_H + #define FSP_VERSION_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ + #include "bsp_api.h" + +/*******************************************************************************************************************//** + * @addtogroup RENESAS_COMMON + * @{ + **********************************************************************************************************************/ + + #ifdef __cplusplus +extern "C" { + #endif + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** FSP pack major version. */ + #define FSP_VERSION_MAJOR (6U) + +/** FSP pack minor version. */ + #define FSP_VERSION_MINOR (2U) + +/** FSP pack patch version. */ + #define FSP_VERSION_PATCH (0U) + +/** FSP pack version build number (currently unused). */ + #define FSP_VERSION_BUILD (0U) + +/** Public FSP version name. */ + #define FSP_VERSION_STRING ("6.2.0") + +/** Unique FSP version ID. */ + #define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 6.2.0") + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** FSP Pack version structure */ +typedef union st_fsp_pack_version +{ + /** Version id */ + uint32_t version_id; + + /** + * Code version parameters, little endian order. + */ + struct version_id_b_s + { + uint8_t build; ///< Build version of FSP Pack + uint8_t patch; ///< Patch version of FSP Pack + uint8_t minor; ///< Minor version of FSP Pack + uint8_t major; ///< Major version of FSP Pack + } version_id_b; +} fsp_pack_version_t; + +/** @} */ + + #ifdef __cplusplus +} + #endif + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/inc/instances/r_adc_b.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/instances/r_adc_b.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/inc/instances/r_adc_b.h rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/instances/r_adc_b.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/inc/instances/r_canfd.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/instances/r_canfd.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/inc/instances/r_canfd.h rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/instances/r_canfd.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/inc/instances/r_dmac.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/instances/r_dmac.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/inc/instances/r_dmac.h rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/instances/r_dmac.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/inc/instances/r_gpt.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/instances/r_gpt.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/inc/instances/r_gpt.h rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/instances/r_gpt.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/inc/instances/r_iic_master.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/instances/r_iic_master.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/inc/instances/r_iic_master.h rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/instances/r_iic_master.h diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/instances/r_ioport.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/instances/r_ioport.h new file mode 100644 index 00000000000..05a35c81cf6 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/instances/r_ioport.h @@ -0,0 +1,543 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup IOPORT + * @{ + **********************************************************************************************************************/ + +#ifndef R_IOPORT_H +#define R_IOPORT_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#include "r_ioport_api.h" +#if __has_include("r_ioport_cfg.h") + #include "r_ioport_cfg.h" +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Private definition to set enumeration values. */ +#define IOPORT_PRV_PFS_PSEL_OFFSET (24) +#define IOPORT_PRV_CCD_PIN_COUNT (8) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** IOPORT private control block. DO NOT MODIFY. Initialization occurs when R_IOPORT_Open() is called. */ +typedef struct st_ioport_instance_ctrl +{ + uint32_t open; + void * p_context; +} ioport_instance_ctrl_t; + +/* This typedef is here temporarily. See SWFLEX-144 for details. */ +/** Superset list of all possible IO port pins. */ +typedef enum e_ioport_port_pin_t +{ + IOPORT_PORT_00_PIN_00 = 0x0000, ///< IO port 0 pin 0 + IOPORT_PORT_00_PIN_01 = 0x0001, ///< IO port 0 pin 1 + IOPORT_PORT_00_PIN_02 = 0x0002, ///< IO port 0 pin 2 + IOPORT_PORT_00_PIN_03 = 0x0003, ///< IO port 0 pin 3 + IOPORT_PORT_00_PIN_04 = 0x0004, ///< IO port 0 pin 4 + IOPORT_PORT_00_PIN_05 = 0x0005, ///< IO port 0 pin 5 + IOPORT_PORT_00_PIN_06 = 0x0006, ///< IO port 0 pin 6 + IOPORT_PORT_00_PIN_07 = 0x0007, ///< IO port 0 pin 7 + IOPORT_PORT_00_PIN_08 = 0x0008, ///< IO port 0 pin 8 + IOPORT_PORT_00_PIN_09 = 0x0009, ///< IO port 0 pin 9 + IOPORT_PORT_00_PIN_10 = 0x000A, ///< IO port 0 pin 10 + IOPORT_PORT_00_PIN_11 = 0x000B, ///< IO port 0 pin 11 + IOPORT_PORT_00_PIN_12 = 0x000C, ///< IO port 0 pin 12 + IOPORT_PORT_00_PIN_13 = 0x000D, ///< IO port 0 pin 13 + IOPORT_PORT_00_PIN_14 = 0x000E, ///< IO port 0 pin 14 + IOPORT_PORT_00_PIN_15 = 0x000F, ///< IO port 0 pin 15 + + IOPORT_PORT_01_PIN_00 = 0x0100, ///< IO port 1 pin 0 + IOPORT_PORT_01_PIN_01 = 0x0101, ///< IO port 1 pin 1 + IOPORT_PORT_01_PIN_02 = 0x0102, ///< IO port 1 pin 2 + IOPORT_PORT_01_PIN_03 = 0x0103, ///< IO port 1 pin 3 + IOPORT_PORT_01_PIN_04 = 0x0104, ///< IO port 1 pin 4 + IOPORT_PORT_01_PIN_05 = 0x0105, ///< IO port 1 pin 5 + IOPORT_PORT_01_PIN_06 = 0x0106, ///< IO port 1 pin 6 + IOPORT_PORT_01_PIN_07 = 0x0107, ///< IO port 1 pin 7 + IOPORT_PORT_01_PIN_08 = 0x0108, ///< IO port 1 pin 8 + IOPORT_PORT_01_PIN_09 = 0x0109, ///< IO port 1 pin 9 + IOPORT_PORT_01_PIN_10 = 0x010A, ///< IO port 1 pin 10 + IOPORT_PORT_01_PIN_11 = 0x010B, ///< IO port 1 pin 11 + IOPORT_PORT_01_PIN_12 = 0x010C, ///< IO port 1 pin 12 + IOPORT_PORT_01_PIN_13 = 0x010D, ///< IO port 1 pin 13 + IOPORT_PORT_01_PIN_14 = 0x010E, ///< IO port 1 pin 14 + IOPORT_PORT_01_PIN_15 = 0x010F, ///< IO port 1 pin 15 + + IOPORT_PORT_02_PIN_00 = 0x0200, ///< IO port 2 pin 0 + IOPORT_PORT_02_PIN_01 = 0x0201, ///< IO port 2 pin 1 + IOPORT_PORT_02_PIN_02 = 0x0202, ///< IO port 2 pin 2 + IOPORT_PORT_02_PIN_03 = 0x0203, ///< IO port 2 pin 3 + IOPORT_PORT_02_PIN_04 = 0x0204, ///< IO port 2 pin 4 + IOPORT_PORT_02_PIN_05 = 0x0205, ///< IO port 2 pin 5 + IOPORT_PORT_02_PIN_06 = 0x0206, ///< IO port 2 pin 6 + IOPORT_PORT_02_PIN_07 = 0x0207, ///< IO port 2 pin 7 + IOPORT_PORT_02_PIN_08 = 0x0208, ///< IO port 2 pin 8 + IOPORT_PORT_02_PIN_09 = 0x0209, ///< IO port 2 pin 9 + IOPORT_PORT_02_PIN_10 = 0x020A, ///< IO port 2 pin 10 + IOPORT_PORT_02_PIN_11 = 0x020B, ///< IO port 2 pin 11 + IOPORT_PORT_02_PIN_12 = 0x020C, ///< IO port 2 pin 12 + IOPORT_PORT_02_PIN_13 = 0x020D, ///< IO port 2 pin 13 + IOPORT_PORT_02_PIN_14 = 0x020E, ///< IO port 2 pin 14 + IOPORT_PORT_02_PIN_15 = 0x020F, ///< IO port 2 pin 15 + + IOPORT_PORT_03_PIN_00 = 0x0300, ///< IO port 3 pin 0 + IOPORT_PORT_03_PIN_01 = 0x0301, ///< IO port 3 pin 1 + IOPORT_PORT_03_PIN_02 = 0x0302, ///< IO port 3 pin 2 + IOPORT_PORT_03_PIN_03 = 0x0303, ///< IO port 3 pin 3 + IOPORT_PORT_03_PIN_04 = 0x0304, ///< IO port 3 pin 4 + IOPORT_PORT_03_PIN_05 = 0x0305, ///< IO port 3 pin 5 + IOPORT_PORT_03_PIN_06 = 0x0306, ///< IO port 3 pin 6 + IOPORT_PORT_03_PIN_07 = 0x0307, ///< IO port 3 pin 7 + IOPORT_PORT_03_PIN_08 = 0x0308, ///< IO port 3 pin 8 + IOPORT_PORT_03_PIN_09 = 0x0309, ///< IO port 3 pin 9 + IOPORT_PORT_03_PIN_10 = 0x030A, ///< IO port 3 pin 10 + IOPORT_PORT_03_PIN_11 = 0x030B, ///< IO port 3 pin 11 + IOPORT_PORT_03_PIN_12 = 0x030C, ///< IO port 3 pin 12 + IOPORT_PORT_03_PIN_13 = 0x030D, ///< IO port 3 pin 13 + IOPORT_PORT_03_PIN_14 = 0x030E, ///< IO port 3 pin 14 + IOPORT_PORT_03_PIN_15 = 0x030F, ///< IO port 3 pin 15 + + IOPORT_PORT_04_PIN_00 = 0x0400, ///< IO port 4 pin 0 + IOPORT_PORT_04_PIN_01 = 0x0401, ///< IO port 4 pin 1 + IOPORT_PORT_04_PIN_02 = 0x0402, ///< IO port 4 pin 2 + IOPORT_PORT_04_PIN_03 = 0x0403, ///< IO port 4 pin 3 + IOPORT_PORT_04_PIN_04 = 0x0404, ///< IO port 4 pin 4 + IOPORT_PORT_04_PIN_05 = 0x0405, ///< IO port 4 pin 5 + IOPORT_PORT_04_PIN_06 = 0x0406, ///< IO port 4 pin 6 + IOPORT_PORT_04_PIN_07 = 0x0407, ///< IO port 4 pin 7 + IOPORT_PORT_04_PIN_08 = 0x0408, ///< IO port 4 pin 8 + IOPORT_PORT_04_PIN_09 = 0x0409, ///< IO port 4 pin 9 + IOPORT_PORT_04_PIN_10 = 0x040A, ///< IO port 4 pin 10 + IOPORT_PORT_04_PIN_11 = 0x040B, ///< IO port 4 pin 11 + IOPORT_PORT_04_PIN_12 = 0x040C, ///< IO port 4 pin 12 + IOPORT_PORT_04_PIN_13 = 0x040D, ///< IO port 4 pin 13 + IOPORT_PORT_04_PIN_14 = 0x040E, ///< IO port 4 pin 14 + IOPORT_PORT_04_PIN_15 = 0x040F, ///< IO port 4 pin 15 + + IOPORT_PORT_05_PIN_00 = 0x0500, ///< IO port 5 pin 0 + IOPORT_PORT_05_PIN_01 = 0x0501, ///< IO port 5 pin 1 + IOPORT_PORT_05_PIN_02 = 0x0502, ///< IO port 5 pin 2 + IOPORT_PORT_05_PIN_03 = 0x0503, ///< IO port 5 pin 3 + IOPORT_PORT_05_PIN_04 = 0x0504, ///< IO port 5 pin 4 + IOPORT_PORT_05_PIN_05 = 0x0505, ///< IO port 5 pin 5 + IOPORT_PORT_05_PIN_06 = 0x0506, ///< IO port 5 pin 6 + IOPORT_PORT_05_PIN_07 = 0x0507, ///< IO port 5 pin 7 + IOPORT_PORT_05_PIN_08 = 0x0508, ///< IO port 5 pin 8 + IOPORT_PORT_05_PIN_09 = 0x0509, ///< IO port 5 pin 9 + IOPORT_PORT_05_PIN_10 = 0x050A, ///< IO port 5 pin 10 + IOPORT_PORT_05_PIN_11 = 0x050B, ///< IO port 5 pin 11 + IOPORT_PORT_05_PIN_12 = 0x050C, ///< IO port 5 pin 12 + IOPORT_PORT_05_PIN_13 = 0x050D, ///< IO port 5 pin 13 + IOPORT_PORT_05_PIN_14 = 0x050E, ///< IO port 5 pin 14 + IOPORT_PORT_05_PIN_15 = 0x050F, ///< IO port 5 pin 15 + + IOPORT_PORT_06_PIN_00 = 0x0600, ///< IO port 6 pin 0 + IOPORT_PORT_06_PIN_01 = 0x0601, ///< IO port 6 pin 1 + IOPORT_PORT_06_PIN_02 = 0x0602, ///< IO port 6 pin 2 + IOPORT_PORT_06_PIN_03 = 0x0603, ///< IO port 6 pin 3 + IOPORT_PORT_06_PIN_04 = 0x0604, ///< IO port 6 pin 4 + IOPORT_PORT_06_PIN_05 = 0x0605, ///< IO port 6 pin 5 + IOPORT_PORT_06_PIN_06 = 0x0606, ///< IO port 6 pin 6 + IOPORT_PORT_06_PIN_07 = 0x0607, ///< IO port 6 pin 7 + IOPORT_PORT_06_PIN_08 = 0x0608, ///< IO port 6 pin 8 + IOPORT_PORT_06_PIN_09 = 0x0609, ///< IO port 6 pin 9 + IOPORT_PORT_06_PIN_10 = 0x060A, ///< IO port 6 pin 10 + IOPORT_PORT_06_PIN_11 = 0x060B, ///< IO port 6 pin 11 + IOPORT_PORT_06_PIN_12 = 0x060C, ///< IO port 6 pin 12 + IOPORT_PORT_06_PIN_13 = 0x060D, ///< IO port 6 pin 13 + IOPORT_PORT_06_PIN_14 = 0x060E, ///< IO port 6 pin 14 + IOPORT_PORT_06_PIN_15 = 0x060F, ///< IO port 6 pin 15 + + IOPORT_PORT_07_PIN_00 = 0x0700, ///< IO port 7 pin 0 + IOPORT_PORT_07_PIN_01 = 0x0701, ///< IO port 7 pin 1 + IOPORT_PORT_07_PIN_02 = 0x0702, ///< IO port 7 pin 2 + IOPORT_PORT_07_PIN_03 = 0x0703, ///< IO port 7 pin 3 + IOPORT_PORT_07_PIN_04 = 0x0704, ///< IO port 7 pin 4 + IOPORT_PORT_07_PIN_05 = 0x0705, ///< IO port 7 pin 5 + IOPORT_PORT_07_PIN_06 = 0x0706, ///< IO port 7 pin 6 + IOPORT_PORT_07_PIN_07 = 0x0707, ///< IO port 7 pin 7 + IOPORT_PORT_07_PIN_08 = 0x0708, ///< IO port 7 pin 8 + IOPORT_PORT_07_PIN_09 = 0x0709, ///< IO port 7 pin 9 + IOPORT_PORT_07_PIN_10 = 0x070A, ///< IO port 7 pin 10 + IOPORT_PORT_07_PIN_11 = 0x070B, ///< IO port 7 pin 11 + IOPORT_PORT_07_PIN_12 = 0x070C, ///< IO port 7 pin 12 + IOPORT_PORT_07_PIN_13 = 0x070D, ///< IO port 7 pin 13 + IOPORT_PORT_07_PIN_14 = 0x070E, ///< IO port 7 pin 14 + IOPORT_PORT_07_PIN_15 = 0x070F, ///< IO port 7 pin 15 + + IOPORT_PORT_08_PIN_00 = 0x0800, ///< IO port 8 pin 0 + IOPORT_PORT_08_PIN_01 = 0x0801, ///< IO port 8 pin 1 + IOPORT_PORT_08_PIN_02 = 0x0802, ///< IO port 8 pin 2 + IOPORT_PORT_08_PIN_03 = 0x0803, ///< IO port 8 pin 3 + IOPORT_PORT_08_PIN_04 = 0x0804, ///< IO port 8 pin 4 + IOPORT_PORT_08_PIN_05 = 0x0805, ///< IO port 8 pin 5 + IOPORT_PORT_08_PIN_06 = 0x0806, ///< IO port 8 pin 6 + IOPORT_PORT_08_PIN_07 = 0x0807, ///< IO port 8 pin 7 + IOPORT_PORT_08_PIN_08 = 0x0808, ///< IO port 8 pin 8 + IOPORT_PORT_08_PIN_09 = 0x0809, ///< IO port 8 pin 9 + IOPORT_PORT_08_PIN_10 = 0x080A, ///< IO port 8 pin 10 + IOPORT_PORT_08_PIN_11 = 0x080B, ///< IO port 8 pin 11 + IOPORT_PORT_08_PIN_12 = 0x080C, ///< IO port 8 pin 12 + IOPORT_PORT_08_PIN_13 = 0x080D, ///< IO port 8 pin 13 + IOPORT_PORT_08_PIN_14 = 0x080E, ///< IO port 8 pin 14 + IOPORT_PORT_08_PIN_15 = 0x080F, ///< IO port 8 pin 15 + + IOPORT_PORT_09_PIN_00 = 0x0900, ///< IO port 9 pin 0 + IOPORT_PORT_09_PIN_01 = 0x0901, ///< IO port 9 pin 1 + IOPORT_PORT_09_PIN_02 = 0x0902, ///< IO port 9 pin 2 + IOPORT_PORT_09_PIN_03 = 0x0903, ///< IO port 9 pin 3 + IOPORT_PORT_09_PIN_04 = 0x0904, ///< IO port 9 pin 4 + IOPORT_PORT_09_PIN_05 = 0x0905, ///< IO port 9 pin 5 + IOPORT_PORT_09_PIN_06 = 0x0906, ///< IO port 9 pin 6 + IOPORT_PORT_09_PIN_07 = 0x0907, ///< IO port 9 pin 7 + IOPORT_PORT_09_PIN_08 = 0x0908, ///< IO port 9 pin 8 + IOPORT_PORT_09_PIN_09 = 0x0909, ///< IO port 9 pin 9 + IOPORT_PORT_09_PIN_10 = 0x090A, ///< IO port 9 pin 10 + IOPORT_PORT_09_PIN_11 = 0x090B, ///< IO port 9 pin 11 + IOPORT_PORT_09_PIN_12 = 0x090C, ///< IO port 9 pin 12 + IOPORT_PORT_09_PIN_13 = 0x090D, ///< IO port 9 pin 13 + IOPORT_PORT_09_PIN_14 = 0x090E, ///< IO port 9 pin 14 + IOPORT_PORT_09_PIN_15 = 0x090F, ///< IO port 9 pin 15 + + IOPORT_PORT_10_PIN_00 = 0x0A00, ///< IO port 10 pin 0 + IOPORT_PORT_10_PIN_01 = 0x0A01, ///< IO port 10 pin 1 + IOPORT_PORT_10_PIN_02 = 0x0A02, ///< IO port 10 pin 2 + IOPORT_PORT_10_PIN_03 = 0x0A03, ///< IO port 10 pin 3 + IOPORT_PORT_10_PIN_04 = 0x0A04, ///< IO port 10 pin 4 + IOPORT_PORT_10_PIN_05 = 0x0A05, ///< IO port 10 pin 5 + IOPORT_PORT_10_PIN_06 = 0x0A06, ///< IO port 10 pin 6 + IOPORT_PORT_10_PIN_07 = 0x0A07, ///< IO port 10 pin 7 + IOPORT_PORT_10_PIN_08 = 0x0A08, ///< IO port 10 pin 8 + IOPORT_PORT_10_PIN_09 = 0x0A09, ///< IO port 10 pin 9 + IOPORT_PORT_10_PIN_10 = 0x0A0A, ///< IO port 10 pin 10 + IOPORT_PORT_10_PIN_11 = 0x0A0B, ///< IO port 10 pin 11 + IOPORT_PORT_10_PIN_12 = 0x0A0C, ///< IO port 10 pin 12 + IOPORT_PORT_10_PIN_13 = 0x0A0D, ///< IO port 10 pin 13 + IOPORT_PORT_10_PIN_14 = 0x0A0E, ///< IO port 10 pin 14 + IOPORT_PORT_10_PIN_15 = 0x0A0F, ///< IO port 10 pin 15 + + IOPORT_PORT_11_PIN_00 = 0x0B00, ///< IO port 11 pin 0 + IOPORT_PORT_11_PIN_01 = 0x0B01, ///< IO port 11 pin 1 + IOPORT_PORT_11_PIN_02 = 0x0B02, ///< IO port 11 pin 2 + IOPORT_PORT_11_PIN_03 = 0x0B03, ///< IO port 11 pin 3 + IOPORT_PORT_11_PIN_04 = 0x0B04, ///< IO port 11 pin 4 + IOPORT_PORT_11_PIN_05 = 0x0B05, ///< IO port 11 pin 5 + IOPORT_PORT_11_PIN_06 = 0x0B06, ///< IO port 11 pin 6 + IOPORT_PORT_11_PIN_07 = 0x0B07, ///< IO port 11 pin 7 + IOPORT_PORT_11_PIN_08 = 0x0B08, ///< IO port 11 pin 8 + IOPORT_PORT_11_PIN_09 = 0x0B09, ///< IO port 11 pin 9 + IOPORT_PORT_11_PIN_10 = 0x0B0A, ///< IO port 11 pin 10 + IOPORT_PORT_11_PIN_11 = 0x0B0B, ///< IO port 11 pin 11 + IOPORT_PORT_11_PIN_12 = 0x0B0C, ///< IO port 11 pin 12 + IOPORT_PORT_11_PIN_13 = 0x0B0D, ///< IO port 11 pin 13 + IOPORT_PORT_11_PIN_14 = 0x0B0E, ///< IO port 11 pin 14 + IOPORT_PORT_11_PIN_15 = 0x0B0F, ///< IO port 11 pin 15 + + IOPORT_PORT_12_PIN_00 = 0x0C00, ///< IO port 12 pin 0 + IOPORT_PORT_12_PIN_01 = 0x0C01, ///< IO port 12 pin 1 + IOPORT_PORT_12_PIN_02 = 0x0C02, ///< IO port 12 pin 2 + IOPORT_PORT_12_PIN_03 = 0x0C03, ///< IO port 12 pin 3 + IOPORT_PORT_12_PIN_04 = 0x0C04, ///< IO port 12 pin 4 + IOPORT_PORT_12_PIN_05 = 0x0C05, ///< IO port 12 pin 5 + IOPORT_PORT_12_PIN_06 = 0x0C06, ///< IO port 12 pin 6 + IOPORT_PORT_12_PIN_07 = 0x0C07, ///< IO port 12 pin 7 + IOPORT_PORT_12_PIN_08 = 0x0C08, ///< IO port 12 pin 8 + IOPORT_PORT_12_PIN_09 = 0x0C09, ///< IO port 12 pin 9 + IOPORT_PORT_12_PIN_10 = 0x0C0A, ///< IO port 12 pin 10 + IOPORT_PORT_12_PIN_11 = 0x0C0B, ///< IO port 12 pin 11 + IOPORT_PORT_12_PIN_12 = 0x0C0C, ///< IO port 12 pin 12 + IOPORT_PORT_12_PIN_13 = 0x0C0D, ///< IO port 12 pin 13 + IOPORT_PORT_12_PIN_14 = 0x0C0E, ///< IO port 12 pin 14 + IOPORT_PORT_12_PIN_15 = 0x0C0F, ///< IO port 12 pin 15 + + IOPORT_PORT_13_PIN_00 = 0x0D00, ///< IO port 13 pin 0 + IOPORT_PORT_13_PIN_01 = 0x0D01, ///< IO port 13 pin 1 + IOPORT_PORT_13_PIN_02 = 0x0D02, ///< IO port 13 pin 2 + IOPORT_PORT_13_PIN_03 = 0x0D03, ///< IO port 13 pin 3 + IOPORT_PORT_13_PIN_04 = 0x0D04, ///< IO port 13 pin 4 + IOPORT_PORT_13_PIN_05 = 0x0D05, ///< IO port 13 pin 5 + IOPORT_PORT_13_PIN_06 = 0x0D06, ///< IO port 13 pin 6 + IOPORT_PORT_13_PIN_07 = 0x0D07, ///< IO port 13 pin 7 + IOPORT_PORT_13_PIN_08 = 0x0D08, ///< IO port 13 pin 8 + IOPORT_PORT_13_PIN_09 = 0x0D09, ///< IO port 13 pin 9 + IOPORT_PORT_13_PIN_10 = 0x0D0A, ///< IO port 13 pin 10 + IOPORT_PORT_13_PIN_11 = 0x0D0B, ///< IO port 13 pin 11 + IOPORT_PORT_13_PIN_12 = 0x0D0C, ///< IO port 13 pin 12 + IOPORT_PORT_13_PIN_13 = 0x0D0D, ///< IO port 13 pin 13 + IOPORT_PORT_13_PIN_14 = 0x0D0E, ///< IO port 13 pin 14 + IOPORT_PORT_13_PIN_15 = 0x0D0F, ///< IO port 13 pin 15 + + IOPORT_PORT_14_PIN_00 = 0x0E00, ///< IO port 14 pin 0 + IOPORT_PORT_14_PIN_01 = 0x0E01, ///< IO port 14 pin 1 + IOPORT_PORT_14_PIN_02 = 0x0E02, ///< IO port 14 pin 2 + IOPORT_PORT_14_PIN_03 = 0x0E03, ///< IO port 14 pin 3 + IOPORT_PORT_14_PIN_04 = 0x0E04, ///< IO port 14 pin 4 + IOPORT_PORT_14_PIN_05 = 0x0E05, ///< IO port 14 pin 5 + IOPORT_PORT_14_PIN_06 = 0x0E06, ///< IO port 14 pin 6 + IOPORT_PORT_14_PIN_07 = 0x0E07, ///< IO port 14 pin 7 + IOPORT_PORT_14_PIN_08 = 0x0E08, ///< IO port 14 pin 8 + IOPORT_PORT_14_PIN_09 = 0x0E09, ///< IO port 14 pin 9 + IOPORT_PORT_14_PIN_10 = 0x0E0A, ///< IO port 14 pin 10 + IOPORT_PORT_14_PIN_11 = 0x0E0B, ///< IO port 14 pin 11 + IOPORT_PORT_14_PIN_12 = 0x0E0C, ///< IO port 14 pin 12 + IOPORT_PORT_14_PIN_13 = 0x0E0D, ///< IO port 14 pin 13 + IOPORT_PORT_14_PIN_14 = 0x0E0E, ///< IO port 14 pin 14 + IOPORT_PORT_14_PIN_15 = 0x0E0F, ///< IO port 14 pin 15 +} ioport_port_pin_t; + +#ifndef BSP_OVERRIDE_IOPORT_PERIPHERAL_T + +/** Superset of all peripheral functions. */ +typedef enum e_ioport_peripheral +{ + /** Pin will functions as an IO pin */ + IOPORT_PERIPHERAL_IO = 0x00, + + /** Pin will function as a DEBUG pin */ + IOPORT_PERIPHERAL_DEBUG = (0x00UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an AGT peripheral pin */ + IOPORT_PERIPHERAL_AGT = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an AGT peripheral pin */ + IOPORT_PERIPHERAL_AGTW = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an AGT peripheral pin */ + IOPORT_PERIPHERAL_AGT1 = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a GPT peripheral pin */ + IOPORT_PERIPHERAL_GPT0 = (0x02UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a GPT peripheral pin */ + IOPORT_PERIPHERAL_GPT1 = (0x03UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SCI peripheral pin */ + IOPORT_PERIPHERAL_SCI0_2_4_6_8 = (0x04UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SCI peripheral pin */ + IOPORT_PERIPHERAL_SCI1_3_5_7_9 = (0x05UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a SPI peripheral pin */ + IOPORT_PERIPHERAL_SPI = (0x06UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a IIC peripheral pin */ + IOPORT_PERIPHERAL_IIC = (0x07UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a KEY peripheral pin */ + IOPORT_PERIPHERAL_KEY = (0x08UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a clock/comparator/RTC peripheral pin */ + IOPORT_PERIPHERAL_CLKOUT_COMP_RTC = (0x09UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CAC/ADC peripheral pin */ + IOPORT_PERIPHERAL_CAC_AD = (0x0AUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a BUS peripheral pin */ + IOPORT_PERIPHERAL_BUS = (0x0BUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CTSU peripheral pin */ + IOPORT_PERIPHERAL_CTSU = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CMPHS peripheral pin */ + IOPORT_PERIPHERAL_ACMPHS = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a segment LCD peripheral pin */ + IOPORT_PERIPHERAL_LCDC = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + #if BSP_FEATURE_SCI_UART_DE_IS_INVERTED + + /** Pin will function as an SCI peripheral DEn pin */ + IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SCI DEn peripheral pin */ + IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), + #else + + /** Pin will function as an SCI peripheral DEn pin */ + IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SCI DEn peripheral pin */ + IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), + #endif + + /** Pin will function as a DALI peripheral pin */ + IOPORT_PERIPHERAL_DALI = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CEU peripheral pin */ + IOPORT_PERIPHERAL_CEU = (0x0FUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CAN peripheral pin */ + IOPORT_PERIPHERAL_CAN = (0x10UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a QSPI peripheral pin */ + IOPORT_PERIPHERAL_QSPI = (0x11UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SSI peripheral pin */ + IOPORT_PERIPHERAL_SSI = (0x12UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a USB full speed peripheral pin */ + IOPORT_PERIPHERAL_USB_FS = (0x13UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a USB high speed peripheral pin */ + IOPORT_PERIPHERAL_USB_HS = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a GPT peripheral pin */ + IOPORT_PERIPHERAL_GPT2 = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SD/MMC peripheral pin */ + IOPORT_PERIPHERAL_SDHI_MMC = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a GPT peripheral pin */ + IOPORT_PERIPHERAL_GPT3 = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an Ethernet MMI peripheral pin */ + IOPORT_PERIPHERAL_ETHER_MII = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a GPT peripheral pin */ + IOPORT_PERIPHERAL_GPT4 = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a GPT peripheral pin */ + IOPORT_PERIPHERAL_GPT5 = (0x1BUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an Ethernet RMMI peripheral pin */ + IOPORT_PERIPHERAL_ETHER_RMII = (0x17UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a PDC peripheral pin */ + IOPORT_PERIPHERAL_PDC = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a graphics LCD peripheral pin */ + IOPORT_PERIPHERAL_LCD_GRAPHICS = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CAC peripheral pin */ + IOPORT_PERIPHERAL_CAC = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a debug trace peripheral pin */ + IOPORT_PERIPHERAL_TRACE = (0x1AUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a OSPI peripheral pin */ + IOPORT_PERIPHERAL_OSPI = (0x1CUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CEC peripheral pin */ + IOPORT_PERIPHERAL_CEC = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a PGAOUT peripheral pin */ + IOPORT_PERIPHERAL_PGAOUT0 = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a PGAOUT peripheral pin */ + IOPORT_PERIPHERAL_PGAOUT1 = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a ULPT peripheral pin */ + IOPORT_PERIPHERAL_ULPT = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a MIPI DSI peripheral pin */ + IOPORT_PERIPHERAL_MIPI = (0x1FUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an UARTA peripheral pin */ + IOPORT_PERIPHERAL_UARTA = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), +} ioport_peripheral_t; +#endif + +#ifndef BSP_OVERRIDE_IOPORT_CFG_OPTIONS_T + +/** Options to configure pin functions */ +typedef enum e_ioport_cfg_options +{ + IOPORT_CFG_PORT_DIRECTION_INPUT = 0x00000000, ///< Sets the pin direction to input (default) + IOPORT_CFG_PORT_DIRECTION_OUTPUT = 0x00000004, ///< Sets the pin direction to output + IOPORT_CFG_PORT_OUTPUT_LOW = 0x00000000, ///< Sets the pin level to low + IOPORT_CFG_PORT_OUTPUT_HIGH = 0x00000001, ///< Sets the pin level to high + IOPORT_CFG_PULLUP_ENABLE = 0x00000010, ///< Enables the pin's internal pull-up + IOPORT_CFG_PIM_TTL = 0x00000020, ///< Enables the pin's input mode + IOPORT_CFG_NMOS_ENABLE = 0x00000040, ///< Enables the pin's NMOS open-drain output + IOPORT_CFG_PMOS_ENABLE = 0x00000080, ///< Enables the pin's PMOS open-drain output + IOPORT_CFG_DRIVE_MID = 0x00000400, ///< Sets pin drive output to medium + IOPORT_CFG_DRIVE_HS_HIGH = 0x00000800, ///< Sets pin drive output to high along with supporting high speed + IOPORT_CFG_DRIVE_MID_IIC = 0x00000800, ///< Sets pin to drive output needed for IIC on a 20mA port + IOPORT_CFG_DRIVE_HIGH = 0x00000C00, ///< Sets pin drive output to high + IOPORT_CFG_EVENT_RISING_EDGE = 0x00001000, ///< Sets pin event trigger to rising edge + IOPORT_CFG_EVENT_FALLING_EDGE = 0x00002000, ///< Sets pin event trigger to falling edge + IOPORT_CFG_EVENT_BOTH_EDGES = 0x00003000, ///< Sets pin event trigger to both edges + IOPORT_CFG_IRQ_ENABLE = 0x00004000, ///< Sets pin as an IRQ pin + IOPORT_CFG_ANALOG_ENABLE = 0x00008000, ///< Enables pin to operate as an analog pin + IOPORT_CFG_PERIPHERAL_PIN = 0x00010000 ///< Enables pin to operate as a peripheral pin +} ioport_cfg_options_t; +#endif + +/** Output current settings for CCD pins */ +typedef enum e_ioport_output_current_t +{ + IOPORT_OUTPUT_CURRENT_HI_Z = 0, ///< High-impedance state + IOPORT_OUTPUT_CURRENT_2_MA = 1, ///< 2 mA output current + IOPORT_OUTPUT_CURRENT_5_MA = 2, ///< 5 mA output current + IOPORT_OUTPUT_CURRENT_10_MA = 3, ///< 10 mA output current + IOPORT_OUTPUT_CURRENT_15_MA = 4, ///< 15 mA output current + IOPORT_OUTPUT_CURRENT_DISABLE = -1, ///< Disables output current control +} ioport_output_current_t; + +/** R_IOPORT extended configuration */ +typedef struct st_ioport_extended_cfg +{ + ioport_output_current_t const ccd_pin_cfg_data[IOPORT_PRV_CCD_PIN_COUNT]; ///< Low-level output current for the CCD pins +} ioport_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const ioport_api_t g_ioport_on_ioport; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ + +fsp_err_t R_IOPORT_Open(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); +fsp_err_t R_IOPORT_Close(ioport_ctrl_t * const p_ctrl); +fsp_err_t R_IOPORT_PinsCfg(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); +fsp_err_t R_IOPORT_PinCfg(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg); +fsp_err_t R_IOPORT_PinEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event); +fsp_err_t R_IOPORT_PinEventOutputWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value); +fsp_err_t R_IOPORT_PinRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value); +fsp_err_t R_IOPORT_PinWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level); +fsp_err_t R_IOPORT_PortDirectionSet(ioport_ctrl_t * const p_ctrl, + bsp_io_port_t port, + ioport_size_t direction_values, + ioport_size_t mask); +fsp_err_t R_IOPORT_PortEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * event_data); +fsp_err_t R_IOPORT_PortEventOutputWrite(ioport_ctrl_t * const p_ctrl, + bsp_io_port_t port, + ioport_size_t event_data, + ioport_size_t mask_value); +fsp_err_t R_IOPORT_PortRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value); +fsp_err_t R_IOPORT_PortWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask); + +/*******************************************************************************************************************//** + * @} (end defgroup IOPORT) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_IOPORT_H diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/inc/instances/r_layer3_switch.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/instances/r_layer3_switch.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/inc/instances/r_layer3_switch.h rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/instances/r_layer3_switch.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/inc/instances/r_ospi_b.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/instances/r_ospi_b.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/inc/instances/r_ospi_b.h rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/instances/r_ospi_b.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/inc/instances/r_rmac.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/instances/r_rmac.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/inc/instances/r_rmac.h rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/instances/r_rmac.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/inc/instances/r_rmac_phy.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/instances/r_rmac_phy.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/inc/instances/r_rmac_phy.h rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/instances/r_rmac_phy.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/inc/instances/r_rtc.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/instances/r_rtc.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/inc/instances/r_rtc.h rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/instances/r_rtc.h diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/instances/r_sci_b_uart.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/instances/r_sci_b_uart.h new file mode 100644 index 00000000000..913a92d872e --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/instances/r_sci_b_uart.h @@ -0,0 +1,219 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_SCI_B_UART_H +#define R_SCI_B_UART_H + +/*******************************************************************************************************************//** + * @addtogroup SCI_B_UART + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_uart_api.h" +#include "r_sci_b_uart_cfg.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Enumeration for SCI clock source */ +typedef enum e_sci_b_clk_src +{ + SCI_B_UART_CLOCK_INT, ///< Use internal clock for baud generation + SCI_B_UART_CLOCK_INT_WITH_BAUDRATE_OUTPUT, ///< Use internal clock for baud generation and output on SCK + SCI_B_UART_CLOCK_EXT8X, ///< Use external clock 8x baud rate + SCI_B_UART_CLOCK_EXT16X ///< Use external clock 16x baud rate +} sci_b_clk_src_t; + +/** UART flow control mode definition */ +typedef enum e_sci_b_uart_flow_control +{ + SCI_B_UART_FLOW_CONTROL_RTS = 0U, ///< Use CTSn_RTSn pin for RTS + SCI_B_UART_FLOW_CONTROL_CTS = 1U, ///< Use CTSn_RTSn pin for CTS + SCI_B_UART_FLOW_CONTROL_HARDWARE_CTSRTS = 3U, ///< Use CTSn pin for CTS, CTSn_RTSn pin for RTS + SCI_B_UART_FLOW_CONTROL_CTSRTS = 5U, ///< Use SCI pin for CTS, external pin for RTS +} sci_b_uart_flow_control_t; + +/** UART instance control block. */ +typedef struct st_sci_b_uart_instance_ctrl +{ + /* Parameters to control UART peripheral device */ + uint8_t fifo_depth; // FIFO depth of the UART channel + uint8_t rx_transfer_in_progress; // Set to 1 if a receive transfer is in progress, 0 otherwise + uint8_t data_bytes : 2; // 1 byte for 7 or 8 bit data, 2 bytes for 9 bit data + uint8_t bitrate_modulation : 1; // 1 if bit rate modulation is enabled, 0 otherwise + uint32_t open; // Used to determine if the channel is configured + + bsp_io_port_pin_t flow_pin; + + /* Source buffer pointer used to fill hardware FIFO from transmit ISR. */ + uint8_t const * p_tx_src; + + /* Size of source buffer pointer used to fill hardware FIFO from transmit ISR. */ + uint32_t tx_src_bytes; + + /* Destination buffer pointer used for receiving data. */ + uint8_t const * p_rx_dest; + + /* Size of destination buffer pointer used for receiving data. */ + uint32_t rx_dest_bytes; + + /* Pointer to the configuration block. */ + uart_cfg_t const * p_cfg; + + /* Base register for this channel */ + R_SCI_B0_Type * p_reg; + + void (* p_callback)(uart_callback_args_t *); // Pointer to callback that is called when a uart_event_t occurs. + uart_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. + + /* Pointer to context to be passed into callback function */ + void * p_context; +} sci_b_uart_instance_ctrl_t; + +/** Receive FIFO trigger configuration. */ +typedef enum e_sci_b_uart_rx_fifo_trigger +{ + SCI_B_UART_RX_FIFO_TRIGGER_1 = 0x1, ///< Callback after each byte is received without buffering + SCI_B_UART_RX_FIFO_TRIGGER_2 = 0x2, ///< Callback when FIFO having 2 bytes + SCI_B_UART_RX_FIFO_TRIGGER_3 = 0x3, ///< Callback when FIFO having 3 bytes + SCI_B_UART_RX_FIFO_TRIGGER_4 = 0x4, ///< Callback when FIFO having 4 bytes + SCI_B_UART_RX_FIFO_TRIGGER_5 = 0x5, ///< Callback when FIFO having 5 bytes + SCI_B_UART_RX_FIFO_TRIGGER_6 = 0x6, ///< Callback when FIFO having 6 bytes + SCI_B_UART_RX_FIFO_TRIGGER_7 = 0x7, ///< Callback when FIFO having 7 bytes + SCI_B_UART_RX_FIFO_TRIGGER_8 = 0x8, ///< Callback when FIFO having 8 bytes + SCI_B_UART_RX_FIFO_TRIGGER_9 = 0x9, ///< Callback when FIFO having 9 bytes + SCI_B_UART_RX_FIFO_TRIGGER_10 = 0xA, ///< Callback when FIFO having 10 bytes + SCI_B_UART_RX_FIFO_TRIGGER_11 = 0xB, ///< Callback when FIFO having 11 bytes + SCI_B_UART_RX_FIFO_TRIGGER_12 = 0xC, ///< Callback when FIFO having 12 bytes + SCI_B_UART_RX_FIFO_TRIGGER_13 = 0xD, ///< Callback when FIFO having 13 bytes + SCI_B_UART_RX_FIFO_TRIGGER_14 = 0xE, ///< Callback when FIFO having 14 bytes + SCI_B_UART_RX_FIFO_TRIGGER_MAX = 0xF, ///< Callback when FIFO is full or after 15 bit times with no data (fewer interrupts) +} sci_b_uart_rx_fifo_trigger_t; + +/** Asynchronous Start Bit Edge Detection configuration. */ +typedef enum e_sci_b_uart_start_bit_detect +{ + SCI_B_UART_START_BIT_LOW_LEVEL = 0x0, ///< Detect low level on RXDn pin as start bit + SCI_B_UART_START_BIT_FALLING_EDGE = 0x1, ///< Detect falling level on RXDn pin as start bit +} sci_b_uart_start_bit_detect_t; + +/** Noise cancellation configuration. */ +typedef enum e_sci_b_uart_noise_cancellation +{ + SCI_B_UART_NOISE_CANCELLATION_DISABLE = 0x0, ///< Disable noise cancellation + SCI_B_UART_NOISE_CANCELLATION_ENABLE = 0x1, ///< Enable noise cancellation +} sci_b_uart_noise_cancellation_t; + +/** RS-485 Enable/Disable. */ +typedef enum e_sci_b_uart_rs485_enable +{ + SCI_B_UART_RS485_DISABLE = 0, ///< RS-485 disabled. + SCI_B_UART_RS485_ENABLE = 1, ///< RS-485 enabled. +} sci_b_uart_rs485_enable_t; + +/** The polarity of the RS-485 DE signal. */ +typedef enum e_sci_b_uart_rs485_de_polarity +{ + SCI_B_UART_RS485_DE_POLARITY_HIGH = 0, ///< The DE signal is high when a write transfer is in progress. + SCI_B_UART_RS485_DE_POLARITY_LOW = 1, ///< The DE signal is low when a write transfer is in progress. +} sci_b_uart_rs485_de_polarity_t; + +/** Register settings to achieve a desired baud rate and modulation duty. */ +typedef struct st_sci_b_baud_setting_t +{ + union + { + uint32_t baudrate_bits; + + struct + { + uint32_t : 3; + uint32_t : 1; + uint32_t bgdm : 1; ///< Baud Rate Generator Double-Speed Mode Select + uint32_t abcs : 1; ///< Asynchronous Mode Base Clock Select + uint32_t abcse : 1; ///< Asynchronous Mode Extended Base Clock Select 1 + uint32_t : 1; + uint32_t brr : 8; ///< Bit Rate Register setting + uint32_t brme : 1; ///< Bit Rate Modulation Enable + uint32_t : 3; + uint32_t cks : 2; ///< CKS value to get divisor (CKS = N) + uint32_t : 2; + uint32_t mddr : 8; ///< Modulation Duty Register setting + } baudrate_bits_b; + }; +} sci_b_baud_setting_t; + +/** Configuration settings for controlling the DE signal for RS-485. */ +typedef struct st_sci_b_uart_rs485_setting +{ + sci_b_uart_rs485_enable_t enable; ///< Enable the DE signal. + sci_b_uart_rs485_de_polarity_t polarity; ///< DE signal polarity. + uint8_t assertion_time : 5; ///< Time in baseclock units after assertion of the DE signal and before the start of the write transfer. + uint8_t negation_time : 5; ///< Time in baseclock units after the end of a write transfer and before the DE signal is negated. +} sci_b_uart_rs485_setting_t; + +/** UART on SCI device Configuration */ +typedef struct st_sci_b_uart_extended_cfg +{ + sci_b_clk_src_t clock; ///< The source clock for the baud-rate generator. If internal optionally output baud rate on SCK + sci_b_uart_start_bit_detect_t rx_edge_start; ///< Start reception on falling edge + sci_b_uart_noise_cancellation_t noise_cancel; ///< Noise cancellation setting + sci_b_baud_setting_t * p_baud_setting; ///< Register settings for a desired baud rate. + sci_b_uart_rx_fifo_trigger_t rx_fifo_trigger; ///< Receive FIFO trigger level, unused if channel has no FIFO or if DTC is used. + bsp_io_port_pin_t flow_control_pin; ///< UART Driver Enable pin + sci_b_uart_flow_control_t flow_control; ///< CTS/RTS function of the SSn pin + sci_b_uart_rs485_setting_t rs485_setting; ///< RS-485 settings. +} sci_b_uart_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const uart_api_t g_uart_on_sci_b; + +/** @endcond */ + +fsp_err_t R_SCI_B_UART_Open(uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const p_cfg); +fsp_err_t R_SCI_B_UART_Read(uart_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes); +fsp_err_t R_SCI_B_UART_Write(uart_ctrl_t * const p_api_ctrl, uint8_t const * const p_src, uint32_t const bytes); +fsp_err_t R_SCI_B_UART_BaudSet(uart_ctrl_t * const p_api_ctrl, void const * const p_baud_setting); +fsp_err_t R_SCI_B_UART_InfoGet(uart_ctrl_t * const p_api_ctrl, uart_info_t * const p_info); +fsp_err_t R_SCI_B_UART_Close(uart_ctrl_t * const p_api_ctrl); +fsp_err_t R_SCI_B_UART_Abort(uart_ctrl_t * const p_api_ctrl, uart_dir_t communication_to_abort); +fsp_err_t R_SCI_B_UART_BaudCalculate(uint32_t baudrate, + bool bitrate_modulation, + uint32_t baud_rate_error_x_1000, + sci_b_baud_setting_t * const p_baud_setting); +fsp_err_t R_SCI_B_UART_CallbackSet(uart_ctrl_t * const p_api_ctrl, + void ( * p_callback)(uart_callback_args_t *), + void * const p_context, + uart_callback_args_t * const p_callback_memory); +fsp_err_t R_SCI_B_UART_ReadStop(uart_ctrl_t * const p_api_ctrl, uint32_t * remaining_bytes); +fsp_err_t R_SCI_B_UART_ReceiveSuspend(uart_ctrl_t * const p_api_ctrl); +fsp_err_t R_SCI_B_UART_ReceiveResume(uart_ctrl_t * const p_api_ctrl); + +/*******************************************************************************************************************//** + * @} (end addtogroup SCI_B_UART) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/inc/instances/r_sdhi.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/instances/r_sdhi.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/inc/instances/r_sdhi.h rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/instances/r_sdhi.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/inc/instances/r_spi_b.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/instances/r_spi_b.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/inc/instances/r_spi_b.h rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/inc/instances/r_spi_b.h diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7KA8P1KF_core0.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7KA8P1KF_core0.h new file mode 100644 index 00000000000..ea862def798 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7KA8P1KF_core0.h @@ -0,0 +1,94177 @@ +/* + * Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause + * + * @file ./out/R7KA8P1KF_core0.h + * @brief CMSIS HeaderFile + * @version 0.1 + */ + +/** @addtogroup Renesas + * @{ + */ + +/** @addtogroup R7KA8P1KF_core0 + * @{ + */ + +#ifndef R7KA8P1KF_CORE0_H + #define R7KA8P1KF_CORE0_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M85 Processor and Core Peripherals =========================== */ + #define __CM85_REV 0x0002U /*!< CM85 Core Revision */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ + #define __MPU_PRESENT 1 /*!< MPU present */ + #define __FPU_PRESENT 1 /*!< FPU present */ + #define __FPU_DP 0 /*!< Double Precision FPU */ + #define __DSP_PRESENT 1 /*!< DSP extension present */ + #define __ICACHE_PRESENT 1 /*!< Instruction Cache present */ + #define __DCACHE_PRESENT 1 /*!< Data Cache present */ + #define __SAUREGION_PRESENT 1 /*!< SAU region present */ + #define __PMU_PRESENT 1 /*!< PMU present */ + #define __PMU_NUM_EVENTCNT 8 /*!< PMU Event Counters */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + #include "core_cm85.h" /*!< ARM Cortex-M85 processor and core peripherals */ + #include "system.h" /*!< R7KA8P1KF_core0 System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_BUS_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ + + struct + { + __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint8_t : 3; + __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ + uint8_t : 2; + } SDCCR_b; + }; + + union + { + __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ + + struct + { + __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ + uint8_t : 7; + } SDCMOD_b; + }; + + union + { + __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ + + struct + { + __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ + uint8_t : 7; + } SDAMOD_b; + }; + __IM uint8_t RESERVED; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ + + struct + { + __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ + uint8_t : 7; + } SDSELF_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ + + struct + { + __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ + __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count + * Setting. ( REFW+1 Cycles ) */ + } SDRFCR_b; + }; + + union + { + __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ + + struct + { + __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ + uint8_t : 7; + } SDRFEN_b; + }; + __IM uint8_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ + } ADD_b; + }; + + union + { + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ + + struct + { + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ + + struct + { + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; + } STAT_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x00000004) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ + + struct + { + __IOM uint8_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint8_t : 7; + } IRQEN_b; + }; + __IM uint8_t RESERVED2[7]; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ + + struct + { + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; + }; + __IM uint8_t RESERVED1[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ + + struct + { + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; + }; +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ + +/** + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t SPI0BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t SPI1BI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU1TCMBI_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t PBBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; + }; + __IM uint32_t RESERVED13; + + union + { + __IOM uint32_t PABI; /*!< (@ 0x00000080) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t PIBI; /*!< (@ 0x00000088) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; + __IM uint32_t RESERVED15; + + union + { + __IOM uint32_t PSBI; /*!< (@ 0x00000090) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; + }; +} R_BUS_BUSSABT0_Type; /*!< Size = 148 (0x94) */ + +/** + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; + + union + { + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; + }; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; + }; +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ + +/** + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ + + struct + { + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ + + struct + { + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ + + struct + { + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; + }; + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; + }; +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ + +/** + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ + uint16_t : 10; + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status) + */ +typedef struct +{ + union + { + __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */ + + struct + { + __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */ + __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */ + __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */ + __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */ + } NCFG_b; + }; + + union + { + __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */ + + struct + { + __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */ + __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */ + __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */ + uint32_t : 4; + __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */ + __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */ + __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */ + __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */ + __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */ + __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */ + __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */ + __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */ + __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */ + __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */ + __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */ + __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt + * enable */ + uint32_t : 1; + __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */ + __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */ + __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */ + __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */ + uint32_t : 3; + __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */ + __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */ + } CTR_b; + }; + + union + { + __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */ + + struct + { + __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */ + __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */ + __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */ + __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */ + __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */ + __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */ + __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */ + __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */ + __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */ + uint32_t : 7; + __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */ + __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */ + } STS_b; + }; + + union + { + __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */ + + struct + { + __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */ + __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */ + __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */ + __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */ + __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */ + __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */ + __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */ + __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */ + __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */ + __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */ + __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */ + __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */ + __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */ + __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */ + __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */ + uint32_t : 1; + __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */ + uint32_t : 1; + } ERFL_b; + }; +} R_CANFD_CFDC_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */ + + struct + { + __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */ + __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */ + uint32_t : 3; + __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */ + uint32_t : 4; + __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */ + uint32_t : 4; + } DCFG_b; + }; + + union + { + __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */ + + struct + { + __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */ + uint32_t : 5; + __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */ + __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */ + __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */ + uint32_t : 5; + __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */ + uint32_t : 4; + __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */ + __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */ + __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */ + uint32_t : 1; + } FDCFG_b; + }; + + union + { + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */ + + struct + { + __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */ + __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */ + uint32_t : 30; + } FDCTR_b; + }; + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */ + + struct + { + __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */ + __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */ + __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */ + uint32_t : 5; + __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */ + __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */ + __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */ + } FDSTS_b; + }; + + union + { + __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */ + + struct + { + __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */ + uint32_t : 3; + __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */ + uint32_t : 4; + } FDCRC_b; + }; + __IM uint32_t RESERVED[3]; +} R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers */ + + struct + { + __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */ + __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */ + __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */ + __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */ + } ID_b; + }; + + union + { + __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers */ + + struct + { + __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */ + __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */ + __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */ + __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */ + } M_b; + }; + + union + { + __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers */ + + struct + { + __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */ + uint32_t : 3; + __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */ + __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction + * Pointer */ + uint32_t : 2; + __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */ + __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */ + } P0_b; + }; + + union + { + __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */ + + struct + { + __IOM uint32_t GAFLFDP : 9; /*!< [8..0] Global Acceptance Filter List FIFO Direction Pointer */ + uint32_t : 23; + } P1_b; + }; +} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List) + */ +typedef struct +{ + union + { + __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */ + + struct + { + __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */ + __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */ + uint32_t : 6; + __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */ + } ACC0_b; + }; + + union + { + __IOM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */ + + struct + { + __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */ + __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */ + uint32_t : 14; + } ACC1_b; + }; +} R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */ + + struct + { + __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */ + __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */ + + struct + { + __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */ + uint32_t : 12; + __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */ + + struct + { + __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */ + + struct + { + __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDRF_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */ + + struct + { + __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ + __IOM uint32_t THLEN : 1; /*!< [29..29] THL Entry enable */ + __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ + __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */ + + struct + { + __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */ + uint32_t : 12; + __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */ + + struct + { + __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */ + + struct + { + __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDCF_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */ + + struct + { + __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ + __IOM uint32_t THLEN : 1; /*!< [29..29] Tx History List Entry */ + __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ + __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */ + + struct + { + __IOM uint32_t TMTS : 16; /*!< [15..0] TX Message Buffer Timestamp Field */ + uint32_t : 12; + __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */ + + struct + { + __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */ + } FDCTR_b; + }; + + union + { + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */ + + struct + { + __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDTM_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDRM_RM [RM] (RX Message Buffer Access Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ + + struct + { + __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */ + __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ + + struct + { + __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ + uint32_t : 12; + __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ + + struct + { + __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */ + + struct + { + __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDRM_RM_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Clusters) + */ +typedef struct +{ + __IOM R_CANFD_CFDRM_RM_Type RM[8]; /*!< (@ 0x00000000) RX Message Buffer Access Registers */ + __IM uint32_t RESERVED[104]; +} R_CANFD_CFDRM_Type; /*!< Size = 1024 (0x400) */ + +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + + struct + { + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; + }; + __IM uint8_t RESERVED[3]; +} R_ELC_ELSEGR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..52]) + */ +typedef struct +{ + union + { + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + + struct + { + __IOM uint16_t ELS : 10; /*!< [9..0] Event Link Select */ + uint16_t : 6; + } HA_b; + }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_GLCDC_BG [BG] (Background Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t EN; /*!< (@ 0x00000000) Background Plane Setting Operation Control Register */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Background plane generation module operation enable */ + uint32_t : 7; + __IOM uint32_t VEN : 1; /*!< [8..8] Control of LCDC internal register value reflection to + * internal operations */ + uint32_t : 7; + __IOM uint32_t SWRST : 1; /*!< [16..16] Entire module SW reset control */ + uint32_t : 15; + } EN_b; + }; + + union + { + __IOM uint32_t PERI; /*!< (@ 0x00000004) Background Plane Setting Free-Running Period + * Register */ + + struct + { + __IOM uint32_t FH : 11; /*!< [10..0] Background plane horizontal synchronization signal period + * on the basis of pixel clock (PXCLK). */ + uint32_t : 5; + __IOM uint32_t FV : 11; /*!< [26..16] Background plane vertical synchronization signal period + * on the basis of line. */ + uint32_t : 5; + } PERI_b; + }; + + union + { + __IOM uint32_t SYNC; /*!< (@ 0x00000008) Background Plane Setting Synchronization Position + * Register */ + + struct + { + __IOM uint32_t HP : 4; /*!< [3..0] Background plane horizontal synchronization signal assertion + * position on the basis of pixel clock (PXCLK). */ + uint32_t : 12; + __IOM uint32_t VP : 4; /*!< [19..16] Background plane vertical synchronization signal assertion + * position on the basis of line. */ + uint32_t : 12; + } SYNC_b; + }; + + union + { + __IOM uint32_t VSIZE; /*!< (@ 0x0000000C) Background Plane Setting Full Image Vertical + * Size Register */ + + struct + { + __IOM uint32_t VW : 11; /*!< [10..0] Background plane vertical valid pixel width on the basis + * of line */ + uint32_t : 5; + __IOM uint32_t VP : 11; /*!< [26..16] Background plane vertical valid pixel start position + * on the basis of line */ + uint32_t : 5; + } VSIZE_b; + }; + + union + { + __IOM uint32_t HSIZE; /*!< (@ 0x00000010) Background Plane Setting Full Image Horizontal + * Size Register */ + + struct + { + __IOM uint32_t HW : 11; /*!< [10..0] Background plane horizontall valid pixel width on the + * basis of pixel clock (PXCLK) Note: When serial RGB is selected + * as the output format for the output control block, add + * two to the horizontal enable signal width and set the resulting + * value to this field. */ + uint32_t : 5; + __IOM uint32_t HP : 11; /*!< [26..16] Background plane horizontal valid pixel start position + * on the basis of pixel clock (PXCLK). */ + uint32_t : 5; + } HSIZE_b; + }; + + union + { + __IOM uint32_t BGC; /*!< (@ 0x00000014) Background Plane Setting Background Color Register */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B value for background plane valid pixel area Unsigned; + * 8-bit integer */ + __IOM uint32_t G : 8; /*!< [15..8] G value for background plane valid pixel area Unsigned; + * 8-bit integer */ + __IOM uint32_t R : 8; /*!< [23..16] R value for background plane valid pixel area. Unsigned; + * 8-bit integer. */ + uint32_t : 8; + } BGC_b; + }; + + union + { + __IM uint32_t MON; /*!< (@ 0x00000018) Background Plane Setting Status Monitor Register */ + + struct + { + __IM uint32_t EN : 1; /*!< [0..0] Background plane generation module operation state monitor. */ + uint32_t : 7; + __IM uint32_t VEN : 1; /*!< [8..8] Entire module internal operation reflection control signal + * monitor. The signal state for controlling reflection of + * the register values to the internal operations upon assertion + * of the vertical synchronization signal. */ + uint32_t : 7; + __IM uint32_t SWRST : 1; /*!< [16..16] Entire module SW reset state monitor. */ + uint32_t : 15; + } MON_b; + }; +} R_GLCDC_BG_Type; /*!< Size = 28 (0x1c) */ + +/** + * @brief R_GLCDC_GR [GR] (Layer Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t VEN; /*!< (@ 0x00000000) Graphics Register Update Control Register */ + + struct + { + __IOM uint32_t PVEN : 1; /*!< [0..0] Control of graphics n module register value reflection + * to internal operations. Reflection of the register values + * to the internal operation at the assertion of the vertical + * synchronization signal (VS). */ + uint32_t : 31; + } VEN_b; + }; + + union + { + __IOM uint32_t FLMRD; /*!< (@ 0x00000004) Graphics Frame Buffer Read Control Register */ + + struct + { + __IOM uint32_t RENB : 1; /*!< [0..0] Graphics data (frame buffer data) read enable. */ + uint32_t : 31; + } FLMRD_b; + }; + + union + { + __IM uint32_t FLM1; /*!< (@ 0x00000008) Graphics Frame Buffer Control Register 1 */ + + struct + { + __IM uint32_t BSTMD : 2; /*!< [1..0] Burst transfer control for graphics data (frame buffer + * data) access */ + uint32_t : 30; + } FLM1_b; + }; + + union + { + __IOM uint32_t FLM2; /*!< (@ 0x0000000C) Graphics Frame Buffer Control Register 2 */ + + struct + { + __IOM uint32_t BASE : 32; /*!< [31..0] Base address for accessing graphics data (frame buffer + * data) Set the head address in the frame buffer where graphics + * data is to be stored. GRn_FLM2.BASE[5:0] should be fixed + * to 0 during 64-byte burst transfer. */ + } FLM2_b; + }; + + union + { + __IOM uint32_t FLM3; /*!< (@ 0x00000010) Graphics Frame Buffer Control Register 3 */ + + struct + { + uint32_t : 16; + __IOM uint32_t LNOFF : 16; /*!< [31..16] Macro line offset address for accessing graphics data + * (frame buffer data) Signed; 16-bit integer */ + } FLM3_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t FLM5; /*!< (@ 0x00000018) Graphics Frame Buffer Control Register 5 */ + + struct + { + __IOM uint32_t DATANUM : 16; /*!< [15..0] Number of data transfer times per line for accessing + * graphics data (frame buffer data), where one transfer is + * defined as 16-beat burst access (64-byte boundary) */ + __IOM uint32_t LNNUM : 11; /*!< [26..16] Number of lines per frame for accessing graphics data + * (frame buffer data). */ + uint32_t : 5; + } FLM5_b; + }; + + union + { + __IOM uint32_t FLM6; /*!< (@ 0x0000001C) Graphics Frame Buffer Control Register 6 */ + + struct + { + uint32_t : 28; + __IOM uint32_t FORMAT : 3; /*!< [30..28] Data format for accessing graphics data (frame buffer + * data). */ + uint32_t : 1; + } FLM6_b; + }; + + union + { + __IOM uint32_t AB1; /*!< (@ 0x00000020) Graphics Alpha Blending Control Register 1 */ + + struct + { + __IOM uint32_t DISPSEL : 2; /*!< [1..0] Graphics display plane control. */ + uint32_t : 2; + __IOM uint32_t GRCDISPON : 1; /*!< [4..4] Graphics image area border display control. */ + uint32_t : 3; + __IOM uint32_t ARCDISPON : 1; /*!< [8..8] Image area border display control for rectangular area + * alpha blending. */ + uint32_t : 3; + __IOM uint32_t ARCON : 1; /*!< [12..12] Rectangular area alpha blending control. */ + uint32_t : 19; + } AB1_b; + }; + + union + { + __IOM uint32_t AB2; /*!< (@ 0x00000024) Graphics Alpha Blending Control Register 2 */ + + struct + { + __IOM uint32_t GRCVW : 11; /*!< [10..0] Vertical width of graphics image area. */ + uint32_t : 5; + __IOM uint32_t GRCVS : 11; /*!< [26..16] Vertical start position of graphics image area. */ + uint32_t : 5; + } AB2_b; + }; + + union + { + __IOM uint32_t AB3; /*!< (@ 0x00000028) Graphics Alpha Blending Control Register 3 */ + + struct + { + __IOM uint32_t GRCHW : 11; /*!< [10..0] Horizontal width of graphics image area. */ + uint32_t : 5; + __IOM uint32_t GRCHS : 11; /*!< [26..16] Horizontal start position of graphics image area. */ + uint32_t : 5; + } AB3_b; + }; + + union + { + __IOM uint32_t AB4; /*!< (@ 0x0000002C) Graphics Alpha Blending Control Register 4 */ + + struct + { + __IOM uint32_t ARCVW : 11; /*!< [10..0] Vertical width of rectangular area alpha blending image + * area. */ + uint32_t : 5; + __IOM uint32_t ARCVS : 11; /*!< [26..16] Vertical start position of rectangular area alpha blending + * image area */ + uint32_t : 5; + } AB4_b; + }; + + union + { + __IOM uint32_t AB5; /*!< (@ 0x00000030) Graphics Alpha Blending Control Register 5 */ + + struct + { + __IOM uint32_t ARCHW : 11; /*!< [10..0] Horizontal width of rectangular area alpha blending + * image area. */ + uint32_t : 5; + __IOM uint32_t ARCHS : 11; /*!< [26..16] Horizontal start position of rectangular area alpha + * blending image area. */ + uint32_t : 5; + } AB5_b; + }; + + union + { + __IOM uint32_t AB6; /*!< (@ 0x00000034) Graphics Alpha Blending Control Register 6 */ + + struct + { + __IOM uint32_t ARCRATE : 8; /*!< [7..0] Frame rate for alpha blending in rectangular area. */ + uint32_t : 8; + __IOM uint32_t ARCCOEF : 9; /*!< [24..16] Alpha coefficient for alpha blending in rectangular + * area (-255 to 255). [8]: Sign (0: addition, 1: subtraction) + * [7:0]: Variation (absolute value) */ + uint32_t : 7; + } AB6_b; + }; + + union + { + __IOM uint32_t AB7; /*!< (@ 0x00000038) Graphics Alpha Blending Control Register 7 */ + + struct + { + __IOM uint32_t CKON : 1; /*!< [0..0] RGB-index chroma-key processing control. */ + uint32_t : 15; + __IOM uint32_t ARCDEF : 8; /*!< [23..16] Initial alpha value for alpha blending in rectangular + * area. */ + uint32_t : 8; + } AB7_b; + }; + + union + { + __IOM uint32_t AB8; /*!< (@ 0x0000003C) Graphics Alpha Blending Control Register 8 */ + + struct + { + __IOM uint32_t CKKR : 8; /*!< [7..0] R signal for RGB-index chroma-key processing Unsigned; + * 8 bits. */ + __IOM uint32_t CKKB : 8; /*!< [15..8] B signal for RGB-index chroma-key processing Unsigned; + * 8 bits. */ + __IOM uint32_t CKKG : 8; /*!< [23..16] G signal for RGB-index chroma-key processing Unsigned; + * 8 bits. */ + uint32_t : 8; + } AB8_b; + }; + + union + { + __IOM uint32_t AB9; /*!< (@ 0x00000040) Graphics Alpha Blending Control Register 9 */ + + struct + { + __IOM uint32_t CKR : 8; /*!< [7..0] R value after RGB-index chroma-key processing replacement + * Unsigned; 8 bits. */ + __IOM uint32_t CKB : 8; /*!< [15..8] B value after RGB-index chroma-key processing replacement + * Unsigned; 8 bits. */ + __IOM uint32_t CKG : 8; /*!< [23..16] G value after RGB-index chroma-key processing replacement + * Unsigned; 8 bits. */ + __IOM uint32_t CKA : 8; /*!< [31..24] A value after RGB-index chroma-key processing replacement. */ + } AB9_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t BASE; /*!< (@ 0x0000004C) Graphics Background Color Control Register */ + + struct + { + __IOM uint32_t R : 8; /*!< [7..0] Background color R value Unsigned; 8 bits */ + __IOM uint32_t B : 8; /*!< [15..8] Background color B value Unsigned; 8 bits */ + __IOM uint32_t G : 8; /*!< [23..16] Background color G value Unsigned; 8 bits */ + uint32_t : 8; + } BASE_b; + }; + + union + { + __IOM uint32_t CLUTINT; /*!< (@ 0x00000050) Graphics CLUT Table Interrupt Control Register */ + + struct + { + __IOM uint32_t LINE : 11; /*!< [10..0] Number of detection lines */ + uint32_t : 5; + __IOM uint32_t SEL : 1; /*!< [16..16] CLUT table control */ + uint32_t : 15; + } CLUTINT_b; + }; + + union + { + __IM uint32_t MON; /*!< (@ 0x00000054) Graphics Status Monitor Register */ + + struct + { + __IM uint32_t ARCST : 1; /*!< [0..0] Status monitor for alpha blending in rectangular area */ + uint32_t : 15; + __IM uint32_t UNDFLST : 1; /*!< [16..16] Status monitor for underflow */ + uint32_t : 15; + } MON_b; + }; + __IM uint32_t RESERVED2[42]; +} R_GLCDC_GR_Type; /*!< Size = 256 (0x100) */ + +/** + * @brief R_GLCDC_GAM [GAM] (Gamma Settings) + */ +typedef struct +{ + union + { + __IOM uint32_t LATCH; /*!< (@ 0x00000000) Gamma Register Update Control Register */ + + struct + { + __IOM uint32_t VEN : 1; /*!< [0..0] Control of gamma correction x module register value reflection + * to internal operations. The register values to be reflected + * to the internal operations at the assertion of the vertical + * synchronization signal (VS). */ + uint32_t : 31; + } LATCH_b; + }; + + union + { + __IOM uint32_t GAM_SW; /*!< (@ 0x00000004) Gamma Correction Block Function Switch Register */ + + struct + { + __IOM uint32_t GAMON : 1; /*!< [0..0] Gamma correction on/off control */ + uint32_t : 31; + } GAM_SW_b; + }; + + union + { + __IOM uint32_t LUT[8]; /*!< (@ 0x00000008) Gamma Correction Block Table Setting Register */ + + struct + { + __IOM uint32_t _HIGH : 11; /*!< [10..0] Gain value of area 0. Unsigned 11-bit fixed point. */ + uint32_t : 5; + __IOM uint32_t _LOW : 11; /*!< [26..16] Gain value of area 0. Unsigned 11-bit fixed point. */ + uint32_t : 5; + } LUT_b[8]; + }; + + union + { + __IOM uint32_t AREA[5]; /*!< (@ 0x00000028) Gamma Correction Block Area Setting Register */ + + struct + { + __IOM uint32_t _HIGH : 10; /*!< [9..0] Start threshold of area 1 Unsigned 10-bit integer */ + __IOM uint32_t _MID : 10; /*!< [19..10] Start threshold of area 1 Unsigned 10-bit integer */ + __IOM uint32_t _LOW : 10; /*!< [29..20] Start threshold of area 1 Unsigned 10-bit integer */ + uint32_t : 2; + } AREA_b[5]; + }; + __IM uint32_t RESERVED; +} R_GLCDC_GAM_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_GLCDC_OUT [OUT] (Output Control Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t VLATCH; /*!< (@ 0x00000000) Output Control Block Register Update Control + * Register */ + + struct + { + __IOM uint32_t VEN : 1; /*!< [0..0] Control of output control module register value reflection + * to internal operations. The register values to be reflected + * to the internal operations at the assertion of the vertical + * synchronization signal (VS). */ + uint32_t : 31; + } VLATCH_b; + }; + + union + { + __IOM uint32_t SET; /*!< (@ 0x00000004) Output Control Block Output Interface Register */ + + struct + { + __IOM uint32_t PHASE : 2; /*!< [1..0] Data delay in serial RGB format (based on OUTCLK) */ + uint32_t : 2; + __IOM uint32_t DIRSEL : 1; /*!< [4..4] Invalid data position control in serial RGB format */ + uint32_t : 3; + __IOM uint32_t FRQSEL : 2; /*!< [9..8] Clock frequency division control */ + uint32_t : 2; + __IOM uint32_t FORMAT : 2; /*!< [13..12] Output format select */ + uint32_t : 10; + __IOM uint32_t SWAPON : 1; /*!< [24..24] Pixel order control */ + uint32_t : 3; + __IOM uint32_t ENDIANON : 1; /*!< [28..28] Bit endian change control */ + uint32_t : 3; + } SET_b; + }; + + union + { + __IOM uint32_t BRIGHT1; /*!< (@ 0x00000008) Output Control Block Brightness Correction Register + * 1 */ + + struct + { + __IOM uint32_t BRTG : 10; /*!< [9..0] Brightness (DC) adjustment of G signal Unsigned; 10 bits; + +512 with offset; integer */ + uint32_t : 22; + } BRIGHT1_b; + }; + + union + { + __IOM uint32_t BRIGHT2; /*!< (@ 0x0000000C) Output Control Block Brightness Correction Register + * 2 */ + + struct + { + __IOM uint32_t BRTR : 10; /*!< [9..0] Brightness (DC) adjustment of R signal Unsigned; 10 bits; + +512 with offset; integer */ + uint32_t : 6; + __IOM uint32_t BRTB : 10; /*!< [25..16] Brightness (DC) adjustment of B signal Unsigned; 10 + * bits; +512 with offset; integer */ + uint32_t : 6; + } BRIGHT2_b; + }; + + union + { + __IOM uint32_t CONTRAST; /*!< (@ 0x00000010) Output Control Block Contrast Correction Register */ + + struct + { + __IOM uint32_t CONTR : 8; /*!< [7..0] Contrast (GAIN) adjustment of R signal Unsigned; 8 bits + * fixed point */ + __IOM uint32_t CONTB : 8; /*!< [15..8] Contrast (GAIN) adjustment of B signal Unsigned; 8 bits + * fixed point */ + __IOM uint32_t CONTG : 8; /*!< [23..16] Contrast (GAIN) adjustment of G signal Unsigned; 8 + * bits fixed point. */ + uint32_t : 8; + } CONTRAST_b; + }; + + union + { + __IOM uint32_t PDTHA; /*!< (@ 0x00000014) Output Control Block Panel Dither Correction + * Register */ + + struct + { + __IOM uint32_t PD : 2; /*!< [1..0] Pattern value (D) of 2 x 2 pattern dither Unsigned 2-bit + * integer */ + uint32_t : 2; + __IOM uint32_t PC : 2; /*!< [5..4] Pattern value (C) of 2 x 2 pattern dither Unsigned 2-bit + * integer */ + uint32_t : 2; + __IOM uint32_t PB : 2; /*!< [9..8] Pattern value (B) of 2 x 2 pattern dither Unsigned 2-bit + * integer */ + uint32_t : 2; + __IOM uint32_t PA : 2; /*!< [13..12] Pattern value (A) of 2 x 2 pattern dither Unsigned + * 2-bit integer */ + uint32_t : 2; + __IOM uint32_t FORM : 2; /*!< [17..16] Output format select */ + uint32_t : 2; + __IOM uint32_t SEL : 2; /*!< [21..20] Operation mode */ + uint32_t : 10; + } PDTHA_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t CLKPHASE; /*!< (@ 0x00000024) Output Control Block Output Phase Control Register */ + + struct + { + uint32_t : 3; + __IOM uint32_t TCON3EDGE : 1; /*!< [3..3] LCD_TCON3 Output Phase Control */ + __IOM uint32_t TCON2EDGE : 1; /*!< [4..4] LCD_TCON2 Output Phase Control */ + __IOM uint32_t TCON1EDGE : 1; /*!< [5..5] LCD_TCON1 Output Phase Control */ + __IOM uint32_t TCON0EDGE : 1; /*!< [6..6] LCD_TCON0 Output Phase Control */ + uint32_t : 1; + __IOM uint32_t LCDEDGE : 1; /*!< [8..8] LCD_DATA Output Phase Control */ + uint32_t : 3; + __IOM uint32_t FRONTGAM : 1; /*!< [12..12] Correction control */ + uint32_t : 19; + } CLKPHASE_b; + }; +} R_GLCDC_OUT_Type; /*!< Size = 40 (0x28) */ + +/** + * @brief R_GLCDC_TCON [TCON] (Timing Control Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t TIM; /*!< (@ 0x00000004) TCON Reference Timing Setting Register */ + + struct + { + __IOM uint32_t OFFSET : 11; /*!< [10..0] Horizontal synchronization signal generation reference + * timing Sets the offset from the assertion of the internal + * horizontal synchronization signal in terms of pixels. */ + uint32_t : 5; + __IOM uint32_t HALF : 11; /*!< [26..16] Vertical synchronization signal generation change timing + * Sets the delay from the assertion of the internal horizontal + * synchronization signal in terms of pixels. */ + uint32_t : 5; + } TIM_b; + }; + + union + { + __IOM uint32_t STVA1; /*!< (@ 0x00000008) TCON Vertical Timing Setting Register A1 */ + + struct + { + __IOM uint32_t VW : 11; /*!< [10..0] STVx1 second change timing Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t VS : 11; /*!< [26..16] STVx1 first change timing */ + uint32_t : 5; + } STVA1_b; + }; + + union + { + __IOM uint32_t STVA2; /*!< (@ 0x0000000C) TCON Vertical Timing Setting Register A2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for VSOUT (controlled by + * TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2 + * register) pin */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control */ + uint32_t : 27; + } STVA2_b; + }; + + union + { + __IOM uint32_t STVB1; /*!< (@ 0x00000010) TCON Vertical Timing Setting Register B1 */ + + struct + { + __IOM uint32_t VW : 11; /*!< [10..0] STVx1 second change timing Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t VS : 11; /*!< [26..16] STVx1 first change timing */ + uint32_t : 5; + } STVB1_b; + }; + + union + { + __IOM uint32_t STVB2; /*!< (@ 0x00000014) TCON Vertical Timing Setting Register B2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for VSOUT (controlled by + * TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2 + * register) pin */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control */ + uint32_t : 27; + } STVB2_b; + }; + + union + { + __IOM uint32_t STHA1; /*!< (@ 0x00000018) TCON Horizontal Timing Setting Register STHA1 */ + + struct + { + __IOM uint32_t HW : 11; /*!< [10..0] STHx1 second change timing. Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t HS : 11; /*!< [26..16] STHx1 first change timing */ + uint32_t : 5; + } STHA1_b; + }; + + union + { + __IOM uint32_t STHA2; /*!< (@ 0x0000001C) TCON Horizontal Timing Setting Register STHA2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for LCD_TCON2 (controlled + * by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2 + * register) pin. */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control. */ + uint32_t : 3; + __IOM uint32_t HSSEL : 1; /*!< [8..8] STHx signal generation reference timing control. */ + uint32_t : 23; + } STHA2_b; + }; + + union + { + __IOM uint32_t STHB1; /*!< (@ 0x00000020) TCON Horizontal Timing Setting Register STHB1 */ + + struct + { + __IOM uint32_t HW : 11; /*!< [10..0] STHx1 second change timing. Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t HS : 11; /*!< [26..16] STHx1 first change timing */ + uint32_t : 5; + } STHB1_b; + }; + + union + { + __IOM uint32_t STHB2; /*!< (@ 0x00000024) TCON Horizontal Timing Setting Register STHB2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for LCD_TCON2 (controlled + * by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2 + * register) pin. */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control. */ + uint32_t : 3; + __IOM uint32_t HSSEL : 1; /*!< [8..8] STHx signal generation reference timing control. */ + uint32_t : 23; + } STHB2_b; + }; + + union + { + __IOM uint32_t DE; /*!< (@ 0x00000028) TCON Data Enable Polarity Setting Register */ + + struct + { + __IOM uint32_t INV : 1; /*!< [0..0] DE signal polarity inversion control. */ + uint32_t : 31; + } DE_b; + }; +} R_GLCDC_TCON_Type; /*!< Size = 44 (0x2c) */ + +/** + * @brief R_GLCDC_SYSCNT [SYSCNT] (GLCDC System Control Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t DTCTEN; /*!< (@ 0x00000000) System control block State Detection Control + * Register */ + + struct + { + __IOM uint32_t VPOSDTC : 1; /*!< [0..0] Specified line detection control */ + __IOM uint32_t L1UNDFDTC : 1; /*!< [1..1] Graphics 1 underflow detection control */ + __IOM uint32_t L2UNDFDTC : 1; /*!< [2..2] Graphics 2 underflow detection control */ + uint32_t : 29; + } DTCTEN_b; + }; + + union + { + __IOM uint32_t INTEN; /*!< (@ 0x00000004) System control block Interrupt Request Enable + * Control Register */ + + struct + { + __IOM uint32_t VPOSINTEN : 1; /*!< [0..0] Interrupt request signal GLCDC_VPOS enable control. */ + __IOM uint32_t L1UNDFINTEN : 1; /*!< [1..1] Interrupt request signal GLCDC_L1UNDF enable control. */ + __IOM uint32_t L2UNDFINTEN : 1; /*!< [2..2] Interrupt request signal GLCDC_L2UNDF enable control. */ + uint32_t : 29; + } INTEN_b; + }; + + union + { + __IOM uint32_t STCLR; /*!< (@ 0x00000008) System control block Status Clear Register */ + + struct + { + __IOM uint32_t VPOSCLR : 1; /*!< [0..0] Graphics 2 specified line detection flag clear field */ + __IOM uint32_t L1UNDFCLR : 1; /*!< [1..1] Graphics 1 underflow detection flag clear field */ + __IOM uint32_t L2UNDFCLR : 1; /*!< [2..2] Graphics 2 underflow detection flag clear field */ + uint32_t : 29; + } STCLR_b; + }; + + union + { + __IM uint32_t STMON; /*!< (@ 0x0000000C) System control block Status Monitor Register */ + + struct + { + __IM uint32_t VPOS : 1; /*!< [0..0] Graphics 2 specified line detection flag */ + __IM uint32_t L1UNDF : 1; /*!< [1..1] Graphics 1 underflow detection flag */ + __IM uint32_t L2UNDF : 1; /*!< [2..2] Graphics 2 underflow detection flag */ + uint32_t : 29; + } STMON_b; + }; + + union + { + __IOM uint32_t PANEL_CLK; /*!< (@ 0x00000010) System control block Version and Panel Clock + * Control Register */ + + struct + { + __IOM uint32_t DCDR : 6; /*!< [5..0] Clock division ratio setting control Refer toTable 2.7.1 + * for details about setting value. Note: Settings that are + * not listed in table 2.7.1 are prohibited. */ + __IOM uint32_t CLKEN : 1; /*!< [6..6] Panel clock output enable control Note: Before changing + * the PIXSEL,CLKSEL or DCDR bit, this bit must be set to + * 0. */ + uint32_t : 1; + __IOM uint32_t CLKSEL : 1; /*!< [8..8] Panel clock supply source select */ + uint32_t : 3; + __IOM uint32_t PIXSEL : 1; /*!< [12..12] Pixel clock select control. Must be set to the same + * value as OUT_SET.FRQSEL[1]. */ + uint32_t : 3; + __IM uint32_t VER : 16; /*!< [31..16] Version information Version information of the GLCDC */ + } PANEL_CLK_b; + }; +} R_GLCDC_SYSCNT_Type; /*!< Size = 20 (0x14) */ + +/** + * @brief R_GPT_ODC_GTDLYR [GTDLYR] (PWM DELAY RISING) + */ +typedef struct +{ + union + { + __IOM uint16_t A; /*!< (@ 0x00000000) GTIOCA Output Delay Register */ + + struct + { + __IOM uint16_t DLY : 7; /*!< [6..0] GTIOCnA Output Rising Edge Delay Setting */ + uint16_t : 9; + } A_b; + }; + + union + { + __IOM uint16_t B; /*!< (@ 0x00000002) GTIOCB Output Delay Register */ + + struct + { + __IOM uint16_t DLY : 7; /*!< [6..0] GTIOCnB Output Rising Edge Delay Setting */ + uint16_t : 9; + } B_b; + }; +} R_GPT_ODC_GTDLYR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + + struct + { + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control) + */ +typedef struct +{ + union + { + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ + __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ + __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ + __IOM uint16_t PP : 1; /*!< [3..3] Privilege protection */ + uint16_t : 12; + } AC_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + + struct + { + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ + } S_b; + }; + + union + { + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + + struct + { + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ + } E_b; + }; + __IM uint32_t RESERVED1; +} R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t EN; /*!< (@ 0x00000000) MMPU enable register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } EN_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t ENPT; /*!< (@ 0x00000004) MMPU enable protect register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } ENPT_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t RPT; /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t RPT_SEC; /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only) */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_SEC_b; + }; + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4[60]; + __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control */ + __IM uint32_t RESERVED5[32]; +} R_MPU_MMPU_GROUP_Type; /*!< Size = 512 (0x200) */ + +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; + }; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + uint32_t : 1; + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Event on Rising. */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + uint16_t : 1; + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Event on Rising. */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + uint8_t : 1; + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ + __IM uint16_t RESERVED; +} R_PMISC_PMSAR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ + union + { + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + + struct + { + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 1; + __IOM uint8_t TCEN : 1; /*!< [7..7] Time Capture Event Input Pin Enable */ + } RTCCR_b; + }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; + + union + { + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union + { + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union + { + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ + + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union + { + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3[3]; + + union + { + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ + + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union + { + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + + struct + { + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; + }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) PIPE Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter ClearSetting this bit to 1 allows + * clearing the transaction counter to 0. */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter EnableEnables or disables the transaction + * counter function. */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) PIPE Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction CounterWhen writing to: Specify the number + * of total packets (number of transactions) to be received + * by the relevant PIPE.When read from: When TRENB = 0: Indicate + * the specified number of transactions.When TRENB = 1: Indicate + * the number of currently counted transactions. */ + } N_b; + }; +} R_USB_HS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_XSPI0_CMCFGCS [CMCFGCS] (xSPI Command Map Configuration registers) + */ +typedef struct +{ + union + { + __IOM uint32_t CMCFG0; /*!< (@ 0x00000000) xSPI Command Map Configuration register 0 */ + + struct + { + __IOM uint32_t FFMT : 2; /*!< [1..0] Frame format */ + __IOM uint32_t ADDSIZE : 2; /*!< [3..2] Address size */ + __IOM uint32_t WPBSTMD : 1; /*!< [4..4] Wrapping burst mode */ + __IOM uint32_t ARYAMD : 1; /*!< [5..5] Array address mode */ + uint32_t : 10; + __IOM uint32_t ADDRPEN : 8; /*!< [23..16] Address Replace Enable */ + __IOM uint32_t ADDRPCD : 8; /*!< [31..24] Address Replace Code */ + } CMCFG0_b; + }; + + union + { + __IOM uint32_t CMCFG1; /*!< (@ 0x00000004) xSPI Command Map Configuration register 1 */ + + struct + { + __IOM uint32_t RDCMD : 16; /*!< [15..0] Read command */ + __IOM uint32_t RDLATE : 5; /*!< [20..16] Read latency cycle */ + uint32_t : 11; + } CMCFG1_b; + }; + + union + { + __IOM uint32_t CMCFG2; /*!< (@ 0x00000008) xSPI Command Map Configuration register 2 */ + + struct + { + __IOM uint32_t WRCMD : 16; /*!< [15..0] Write command */ + __IOM uint32_t WRLATE : 5; /*!< [20..16] Write latency cycle */ + uint32_t : 11; + } CMCFG2_b; + }; + __IM uint32_t RESERVED; +} R_XSPI0_CMCFGCS_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_XSPI0_CDBUF [CDBUF] (xSPI BUF register) + */ +typedef struct +{ + union + { + __IOM uint32_t CDT; /*!< (@ 0x00000000) xSPI Command Manual Type buf */ + + struct + { + __IOM uint32_t CMDSIZE : 2; /*!< [1..0] Command Size */ + __IOM uint32_t ADDSIZE : 3; /*!< [4..2] Address size */ + __IOM uint32_t DATASIZE : 4; /*!< [8..5] Write/Read Data Size */ + __IOM uint32_t LATE : 5; /*!< [13..9] Latency cycle */ + uint32_t : 1; + __IOM uint32_t TRTYPE : 1; /*!< [15..15] Transaction Type */ + __IOM uint32_t CMD : 16; /*!< [31..16] Command (1-2byte) */ + } CDT_b; + }; + + union + { + __IOM uint32_t CDA; /*!< (@ 0x00000004) xSPI Command Manual Address buf */ + + struct + { + __IOM uint32_t ADD : 32; /*!< [31..0] Address */ + } CDA_b; + }; + + union + { + __IOM uint32_t CDD0; /*!< (@ 0x00000008) xSPI Command Manual Data 0 buf */ + + struct + { + __IOM uint32_t DATA : 32; /*!< [31..0] Write/Read Data */ + } CDD0_b; + }; + + union + { + __IOM uint32_t CDD1; /*!< (@ 0x0000000C) xSPI Command Manual Data 1 buf */ + + struct + { + __IOM uint32_t DATA : 32; /*!< [31..0] Write/Read Data */ + } CDD1_b; + }; +} R_XSPI0_CDBUF_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_XSPI0_CCCTLCS [CCCTLCS] (xSPI CS register) + */ +typedef struct +{ + union + { + __IOM uint32_t CCCTL0; /*!< (@ 0x00000000) xSPI Command Calibration Control register 0 */ + + struct + { + __IOM uint32_t CAEN : 1; /*!< [0..0] Automatic Calibration Enable */ + __IOM uint32_t CANOWR : 1; /*!< [1..1] Calibration no write mode */ + uint32_t : 6; + __IOM uint32_t CAITV : 5; /*!< [12..8] Calibration interval */ + uint32_t : 3; + __IOM uint32_t CASFTSTA : 5; /*!< [20..16] Calibration DS shift start value */ + uint32_t : 3; + __IOM uint32_t CASFTEND : 5; /*!< [28..24] Calibration DS shift end value */ + uint32_t : 3; + } CCCTL0_b; + }; + + union + { + __IOM uint32_t CCCTL1; /*!< (@ 0x00000004) xSPI Command Calibration Control register 1 */ + + struct + { + __IOM uint32_t CACMDSIZE : 2; /*!< [1..0] Command Size */ + __IOM uint32_t CAADDSIZE : 3; /*!< [4..2] Address size */ + __IOM uint32_t CADATASIZE : 4; /*!< [8..5] Write/Read Data Size */ + uint32_t : 7; + __IOM uint32_t CAWRLATE : 5; /*!< [20..16] Write Latency cycle */ + uint32_t : 3; + __IOM uint32_t CARDLATE : 5; /*!< [28..24] Read Latency cycle */ + uint32_t : 3; + } CCCTL1_b; + }; + + union + { + __IOM uint32_t CCCTL2; /*!< (@ 0x00000008) xSPI Command Calibration Control register 2 */ + + struct + { + __IOM uint32_t CAWRCMD : 16; /*!< [15..0] Calibration pattern write command */ + __IOM uint32_t CARDCMD : 16; /*!< [31..16] Calibration pattern read command */ + } CCCTL2_b; + }; + + union + { + __IOM uint32_t CCCTL3; /*!< (@ 0x0000000C) xSPI Command Calibration Control register 3 */ + + struct + { + __IOM uint32_t CAADD : 32; /*!< [31..0] Calibration pattern address */ + } CCCTL3_b; + }; + + union + { + __IOM uint32_t CCCTL4; /*!< (@ 0x00000010) xSPI Command Calibration Control register 4 */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL4_b; + }; + + union + { + __IOM uint32_t CCCTL5; /*!< (@ 0x00000014) xSPI Command Calibration Control register 5 */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL5_b; + }; + + union + { + __IOM uint32_t CCCTL6; /*!< (@ 0x00000018) xSPI Command Calibration Control register 6 */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL6_b; + }; + + union + { + __IOM uint32_t CCCTL7; /*!< (@ 0x0000001C) xSPI Command Calibration Control register 7 */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL7_b; + }; +} R_XSPI0_CCCTLCS_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) + */ +typedef struct +{ + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; + }; + + union + { + __IOM uint8_t AGTMR2; /*!< (@ 0x00000002) AGT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; + }; + + union + { + __IOM uint8_t AGTIOSEL_ALT; /*!< (@ 0x00000003) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_ALT_b; + }; + + union + { + __IOM uint8_t AGTIOC; /*!< (@ 0x00000004) AGT I/O Control Register */ + + struct + { + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; + }; + + union + { + __IOM uint8_t AGTISR; /*!< (@ 0x00000005) AGT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; + }; + + union + { + __IOM uint8_t AGTCMSR; /*!< (@ 0x00000006) AGT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; + }; + + union + { + __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000007) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; + }; +} R_AGTX0_AGT16_CTRL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers) + */ +typedef struct +{ + union + { + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + + struct + { + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + + struct + { + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + + struct + { + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IM uint16_t RESERVED; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL */ +} R_AGTX0_AGT16_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers) + */ +typedef struct +{ + union + { + __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT 32-bit Counter Register */ + + struct + { + __IOM uint32_t AGT : 32; /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ + + struct + { + __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ + + struct + { + __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL */ +} R_AGTX0_AGT32_Type; /*!< Size = 20 (0x14) */ + +/** + * @brief R_COMA_CABPPPFLC [CABPPPFLC] ([0..2]) + */ +typedef struct +{ + union + { + __IOM uint32_t LEVEL0; /*!< (@ 0x00000000) Port 0 Buffer Pointer Pause Frame Level 0 Configuration + * Register */ + + struct + { + __IOM uint32_t PPDL : 10; /*!< [9..0] Pause De-Assertion Level */ + uint32_t : 6; + __IOM uint32_t PPAL : 10; /*!< [25..16] Pause Assertion Level */ + uint32_t : 6; + } LEVEL0_b; + }; + + union + { + __IOM uint32_t LEVEL1; /*!< (@ 0x00000004) Port 0 Buffer Pointer Pause Frame Level 1 Configuration + * Register */ + + struct + { + __IOM uint32_t PPDL : 10; /*!< [9..0] Pause De-Assertion Level */ + uint32_t : 6; + __IOM uint32_t PPAL : 10; /*!< [25..16] Pause Assertion Level */ + uint32_t : 6; + } LEVEL1_b; + }; +} R_COMA_CABPPPFLC_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_IPC_IPCNMI [IPCNMI] (Inter-Processor NMI Registers) + */ +typedef struct +{ + union + { + __IM uint32_t STA; /*!< (@ 0x00000000) NMI Request Status Register */ + + struct + { + __IM uint32_t NMI : 1; /*!< [0..0] Status of the interrupt request */ + uint32_t : 31; + } STA_b; + }; + + union + { + __OM uint32_t SET; /*!< (@ 0x00000004) NMI Request Set Register */ + + struct + { + __OM uint32_t SET : 1; /*!< [0..0] Sets the NMI request */ + uint32_t : 31; + } SET_b; + }; + + union + { + __OM uint32_t CLR; /*!< (@ 0x00000008) NMI Request Clear Register */ + + struct + { + __OM uint32_t CLR : 1; /*!< [0..0] Clears the NMI request */ + uint32_t : 31; + } CLR_b; + }; + __IM uint32_t RESERVED; +} R_IPC_IPCNMI_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_IPC_IPC_CH [CH] (Inter-Processor Communications Channel Registers) + */ +typedef struct +{ + union + { + __IM uint32_t STA; /*!< (@ 0x00000000) Inter-Processor Status Register */ + + struct + { + __IM uint32_t IRQ0 : 1; /*!< [0..0] Indicates the status of the interrupt request */ + __IM uint32_t IRQ1 : 1; /*!< [1..1] Indicates the status of the interrupt request */ + __IM uint32_t IRQ2 : 1; /*!< [2..2] Indicates the status of the interrupt request */ + __IM uint32_t IRQ3 : 1; /*!< [3..3] Indicates the status of the interrupt request */ + __IM uint32_t IRQ4 : 1; /*!< [4..4] Indicates the status of the interrupt request */ + __IM uint32_t IRQ5 : 1; /*!< [5..5] Indicates the status of the interrupt request */ + __IM uint32_t IRQ6 : 1; /*!< [6..6] Indicates the status of the interrupt request */ + __IM uint32_t IRQ7 : 1; /*!< [7..7] Indicates the status of the interrupt request */ + uint32_t : 8; + __IM uint32_t RDY : 1; /*!< [16..16] This bit is set when FIFO is not empty */ + __IM uint32_t FULL : 1; /*!< [17..17] FIFO is full */ + uint32_t : 6; + __IM uint32_t RERR : 1; /*!< [24..24] Indicates that the message FIFO 00 tried to read Data + * despite Empty */ + __IM uint32_t FERR : 1; /*!< [25..25] Indicates that the message FIFO 00 tried to send more + * data even though it was full */ + uint32_t : 6; + } STA_b; + }; + + union + { + __OM uint32_t SET; /*!< (@ 0x00000004) Inter-Processor IRQ Request Set Register */ + + struct + { + __OM uint32_t SET0 : 1; /*!< [0..0] Sets IPCmSTA0.IRQn */ + __OM uint32_t SET1 : 1; /*!< [1..1] Sets IPCmSTA0.IRQn */ + __OM uint32_t SET2 : 1; /*!< [2..2] Sets IPCmSTA0.IRQn */ + __OM uint32_t SET3 : 1; /*!< [3..3] Sets IPCmSTA0.IRQn */ + __OM uint32_t SET4 : 1; /*!< [4..4] Sets IPCmSTA0.IRQn */ + __OM uint32_t SET5 : 1; /*!< [5..5] Sets IPCmSTA0.IRQn */ + __OM uint32_t SET6 : 1; /*!< [6..6] Sets IPCmSTA0.IRQn */ + __OM uint32_t SET7 : 1; /*!< [7..7] Sets IPCmSTA0.IRQn */ + uint32_t : 24; + } SET_b; + }; + + union + { + __OM uint32_t TXD; /*!< (@ 0x00000008) Inter-Processor FIFO Transfer Data Register */ + + struct + { + __OM uint32_t TXD : 32; /*!< [31..0] Transfer data */ + } TXD_b; + }; + + union + { + __IM uint32_t RXD; /*!< (@ 0x0000000C) Inter-Processor FIFO Receive Data Register */ + + struct + { + __IM uint32_t RXD : 32; /*!< [31..0] Receive data */ + } RXD_b; + }; + + union + { + __OM uint32_t CLR; /*!< (@ 0x00000010) Inter-Processor Clear Register */ + + struct + { + __OM uint32_t CLR0 : 1; /*!< [0..0] Clears the interrupt request for IPCmSTA0.IRQn */ + __OM uint32_t CLR1 : 1; /*!< [1..1] Clears the interrupt request for IPCmSTA0.IRQn */ + __OM uint32_t CLR2 : 1; /*!< [2..2] Clears the interrupt request for IPCmSTA0.IRQn */ + __OM uint32_t CLR3 : 1; /*!< [3..3] Clears the interrupt request for IPCmSTA0.IRQn */ + __OM uint32_t CLR4 : 1; /*!< [4..4] Clears the interrupt request for IPCmSTA0.IRQn */ + __OM uint32_t CLR5 : 1; /*!< [5..5] Clears the interrupt request for IPCmSTA0.IRQn */ + __OM uint32_t CLR6 : 1; /*!< [6..6] Clears the interrupt request for IPCmSTA0.IRQn */ + __OM uint32_t CLR7 : 1; /*!< [7..7] Clears the interrupt request for IPCmSTA0.IRQn */ + uint32_t : 8; + __OM uint32_t RST : 1; /*!< [16..16] Resets message FIFO */ + uint32_t : 7; + __OM uint32_t RCLR : 1; /*!< [24..24] Resets IPCmSTA0.RERR */ + __OM uint32_t FCLR : 1; /*!< [25..25] Resets IPCmSTA0.FERR */ + uint32_t : 6; + } CLR_b; + }; + __IM uint32_t RESERVED[3]; +} R_IPC_IPC_CH_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_IPC_IPC [IPC] (Inter-Processor Registers) + */ +typedef struct +{ + __IOM R_IPC_IPC_CH_Type CH[2]; /*!< (@ 0x00000000) Inter-Processor Communications Channel Registers */ +} R_IPC_IPC_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PDM_CH [CH] (PDM Channel-Specific Registers) + */ +typedef struct +{ + union + { + __OM uint32_t PDSTRTR; /*!< (@ 0x00000000) Software Start Trigger Register */ + + struct + { + __OM uint32_t STRTRG : 1; /*!< [0..0] Start trigger */ + uint32_t : 31; + } PDSTRTR_b; + }; + + union + { + __OM uint32_t PDSTPTR; /*!< (@ 0x00000004) Software Stop Trigger Register */ + + struct + { + __OM uint32_t STPTRG : 1; /*!< [0..0] Stop trigger */ + uint32_t : 31; + } PDSTPTR_b; + }; + + union + { + __OM uint32_t PDCHGTR; /*!< (@ 0x00000008) Software Change Trigger Register */ + + struct + { + __OM uint32_t CHGTRG : 1; /*!< [0..0] Change trigger */ + uint32_t : 31; + } PDCHGTR_b; + }; + + union + { + __IOM uint32_t PDICR; /*!< (@ 0x0000000C) Interrupt Control Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t ISDE : 1; /*!< [1..1] Sound detection interrupt enable bit */ + __IOM uint32_t IDRE : 1; /*!< [2..2] Data reception interrupt enable bit */ + uint32_t : 13; + __IOM uint32_t IEDE : 1; /*!< [16..16] Error detection interrupt enable bit */ + uint32_t : 15; + } PDICR_b; + }; + + union + { + __IOM uint32_t PDSDCR; /*!< (@ 0x00000010) Status Detection Control Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t SDE : 1; /*!< [1..1] Sound detection enable bit */ + uint32_t : 14; + __IOM uint32_t SCDE : 1; /*!< [16..16] Short circuit detection enable bit */ + __IOM uint32_t OVLDE : 1; /*!< [17..17] Overvoltage lower limit exceeded detection enable bit */ + __IOM uint32_t OVUDE : 1; /*!< [18..18] Overvoltage upper limit exceeded detection enable bit */ + uint32_t : 8; + __IOM uint32_t BFOWDE : 1; /*!< [27..27] Buffer overwriting detection enable bit */ + uint32_t : 4; + } PDSDCR_b; + }; + + union + { + __IM uint32_t PDSR; /*!< (@ 0x00000014) Status Register */ + + struct + { + __IM uint32_t STATE : 1; /*!< [0..0] State */ + __IM uint32_t SDF : 1; /*!< [1..1] Sound detection flag */ + __IM uint32_t DRF : 1; /*!< [2..2] Data reception flag */ + uint32_t : 13; + __IM uint32_t SCDF : 1; /*!< [16..16] Short circuit detection flag */ + __IM uint32_t OVLDF : 1; /*!< [17..17] Overvoltage lower limit exceeded detection flag */ + __IM uint32_t OVUDF : 1; /*!< [18..18] Overvoltage upper limit exceeded detection flag */ + uint32_t : 8; + __IM uint32_t BFOWDF : 1; /*!< [27..27] Buffer overwriting detection flag */ + uint32_t : 4; + } PDSR_b; + }; + + union + { + __OM uint32_t PDSCR; /*!< (@ 0x00000018) Status Clear Register */ + + struct + { + uint32_t : 1; + __OM uint32_t SDFC : 1; /*!< [1..1] Sound detection flag clear */ + uint32_t : 14; + __OM uint32_t SCDFC : 1; /*!< [16..16] Short circuit detection flag clear */ + __OM uint32_t OVLDFC : 1; /*!< [17..17] Overvoltage lower limit exceeded detection flag clear */ + __OM uint32_t OVUDFC : 1; /*!< [18..18] Overvoltage upper limit exceeded detection flag clear */ + uint32_t : 8; + __OM uint32_t BFOWDFC : 1; /*!< [27..27] Buffer overwriting detection flag clear */ + uint32_t : 4; + } PDSCR_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t PDMDSR; /*!< (@ 0x00000020) Mode Setting Register */ + + struct + { + __IOM uint32_t INPSEL : 1; /*!< [0..0] Input data select */ + uint32_t : 3; + __IOM uint32_t SFMD : 3; /*!< [6..4] Sinc filter mode setting */ + uint32_t : 1; + __IOM uint32_t HFIS : 2; /*!< [9..8] High-pass filter input shift setting */ + uint32_t : 2; + __IOM uint32_t CFIS : 2; /*!< [13..12] Compensation filter input shift setting */ + uint32_t : 2; + __IOM uint32_t LFIS : 2; /*!< [17..16] Low-pass (half-band decimation) filter input shift + * setting */ + uint32_t : 6; + __IOM uint32_t SDMAMD : 2; /*!< [25..24] Moving average mode for sound detection data */ + uint32_t : 2; + __IOM uint32_t DBIS : 4; /*!< [31..28] Data buffer input shift setting */ + } PDMDSR_b; + }; + + union + { + __IOM uint32_t PDSFCR; /*!< (@ 0x00000024) Sinc filter Control Register */ + + struct + { + __IOM uint32_t CKDIV : 4; /*!< [3..0] PDM_CLKn's dividend ratio to core clock */ + uint32_t : 12; + __IOM uint32_t SINCDEC : 8; /*!< [23..16] Sinc filter decimation ratio */ + __IOM uint32_t SINCRNG : 5; /*!< [28..24] Sinc filter output valid range */ + uint32_t : 3; + } PDSFCR_b; + }; + + union + { + __IOM uint32_t PDHFCS0R; /*!< (@ 0x00000028) High-pass filter Coefficient s(0) Register */ + + struct + { + __IOM uint32_t HFS0 : 16; /*!< [15..0] High-pass filter coefficient s(0) */ + uint32_t : 16; + } PDHFCS0R_b; + }; + + union + { + __IOM uint32_t PDHFCK1R; /*!< (@ 0x0000002C) High-pass filter Coefficient k(1) Register */ + + struct + { + __IOM uint32_t HFK1 : 16; /*!< [15..0] High-pass filter coefficient k(1) */ + uint32_t : 16; + } PDHFCK1R_b; + }; + + union + { + __IOM uint32_t PDHFCHR[2]; /*!< (@ 0x00000030) High-pass filter Coefficient h([0..1]) Registers */ + + struct + { + __IOM uint32_t HFHn : 16; /*!< [15..0] High-pass filter coefficient h(n) */ + uint32_t : 16; + } PDHFCHR_b[2]; + }; + + union + { + __IOM uint32_t PDCFCHR[11]; /*!< (@ 0x00000038) Compensation filter Coefficient h([0..10]) Registers */ + + struct + { + __IOM uint32_t CFHn : 13; /*!< [12..0] Compensation filter coefficient h(n) */ + uint32_t : 19; + } PDCFCHR_b[11]; + }; + + union + { + __IOM uint32_t PDLFCH010R; /*!< (@ 0x00000064) Low-pass filter Coefficient h0(10) Register */ + + struct + { + __IOM uint32_t LFH010 : 13; /*!< [12..0] Low-pass (half-band decimation) filter coefficient h0(10) */ + uint32_t : 19; + } PDLFCH010R_b; + }; + + union + { + __IOM uint32_t PDLFCH1R[20]; /*!< (@ 0x00000068) Low-pass filter Coefficient h1([0..19]) Registers */ + + struct + { + __IOM uint32_t LFH1n : 13; /*!< [12..0] Low-pass (half-band decimation) filter coefficient h1(n) */ + uint32_t : 19; + } PDLFCH1R_b[20]; + }; + + union + { + __IOM uint32_t PDSDLTR; /*!< (@ 0x000000B8) Sound Detection Lower Threshold Register */ + + struct + { + __IOM uint32_t SDETL : 20; /*!< [19..0] Sound detection lower limit */ + uint32_t : 12; + } PDSDLTR_b; + }; + + union + { + __IOM uint32_t PDSDUTR; /*!< (@ 0x000000BC) Sound Detection Upper Threshold Register */ + + struct + { + __IOM uint32_t SDETU : 20; /*!< [19..0] Sound detection upper limit */ + uint32_t : 12; + } PDSDUTR_b; + }; + + union + { + __IOM uint32_t PDDBCR; /*!< (@ 0x000000C0) Data Buffer Control Register */ + + struct + { + __IOM uint32_t DATRITHR : 3; /*!< [2..0] Data reception interrupt threshold */ + uint32_t : 29; + } PDDBCR_b; + }; + + union + { + __IOM uint32_t PDSCTSR; /*!< (@ 0x000000C4) Short Circuit Threshold Setting Register */ + + struct + { + __IOM uint32_t SCDL : 13; /*!< [12..0] Short circuit detection Low Continuous detection count */ + uint32_t : 3; + __IOM uint32_t SCDH : 13; /*!< [28..16] Short circuit detection High Continuous detection count */ + uint32_t : 3; + } PDSCTSR_b; + }; + + union + { + __IOM uint32_t PDOVLTR; /*!< (@ 0x000000C8) Overvoltage Lower Threshold Register */ + + struct + { + __IOM uint32_t OVDL : 20; /*!< [19..0] Overvoltage detection lower limit */ + uint32_t : 12; + } PDOVLTR_b; + }; + + union + { + __IOM uint32_t PDOVUTR; /*!< (@ 0x000000CC) Overvoltage Upper Threshold Register */ + + struct + { + __IOM uint32_t OVDU : 20; /*!< [19..0] Overvoltage detection upper limit */ + uint32_t : 12; + } PDOVUTR_b; + }; + __IM uint32_t RESERVED1[4]; + + union + { + __IOM uint32_t PDDRCR; /*!< (@ 0x000000E0) Data Read Control Register */ + + struct + { + __IOM uint32_t DATRE : 1; /*!< [0..0] Data read enable bit */ + uint32_t : 31; + } PDDRCR_b; + }; + + union + { + __OM uint32_t PDDCR; /*!< (@ 0x000000E4) Data Clear Register */ + + struct + { + __OM uint32_t DATC : 1; /*!< [0..0] Data clear */ + uint32_t : 31; + } PDDCR_b; + }; + + union + { + __IM uint32_t PDDRR; /*!< (@ 0x000000E8) Data Read Register */ + + struct + { + __IM uint32_t DAT : 20; /*!< [19..0] Data */ + uint32_t : 12; + } PDDRR_b; + }; + + union + { + __IM uint32_t PDDSR; /*!< (@ 0x000000EC) Data Status Register */ + + struct + { + __IM uint32_t DATNUM : 8; /*!< [7..0] Number of data stored in buffer */ + uint32_t : 24; + } PDDSR_b; + }; + __IM uint32_t RESERVED2[4]; +} R_PDM_CH_Type; /*!< Size = 256 (0x100) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief High-Speed Analog Comparator (R_ACMPHS0) + */ + +typedef struct /*!< (@ 0x40236000) R_ACMPHS0 Structure */ +{ + union + { + __IOM uint8_t CMPCTL; /*!< (@ 0x00000000) Comparator Control Register */ + + struct + { + __IOM uint8_t CINV : 1; /*!< [0..0] Comparator output polarity selection */ + __IOM uint8_t COE : 1; /*!< [1..1] Comparator output enable */ + __IOM uint8_t CSTEN : 1; /*!< [2..2] Interrupt Select */ + __IOM uint8_t CEG : 2; /*!< [4..3] Selection of valid edge (Edge selector) */ + __IOM uint8_t CDFS : 2; /*!< [6..5] Noise filter selection */ + __IOM uint8_t HCMPON : 1; /*!< [7..7] Comparator operation control */ + } CMPCTL_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t CMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ + + struct + { + __IOM uint8_t CMPSEL : 4; /*!< [3..0] Comparator Input Selection */ + uint8_t : 4; + } CMPSEL0_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t CMPSEL1; /*!< (@ 0x00000008) Comparator Reference Voltage Select Register */ + + struct + { + __IOM uint8_t CRVS : 6; /*!< [5..0] Reference Voltage Selection */ + uint8_t : 2; + } CMPSEL1_b; + }; + __IM uint8_t RESERVED2[3]; + + union + { + __IM uint8_t CMPMON; /*!< (@ 0x0000000C) Comparator Output Monitor Register */ + + struct + { + __IM uint8_t CMPMON : 1; /*!< [0..0] Comparator output monitor */ + uint8_t : 7; + } CMPMON_b; + }; + __IM uint8_t RESERVED3[3]; + + union + { + __IOM uint8_t CPIOC; /*!< (@ 0x00000010) Comparator Output Control Register */ + + struct + { + __IOM uint8_t CPOE : 1; /*!< [0..0] Comparator output selection */ + uint8_t : 6; + __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ + } CPIOC_b; + }; + __IM uint8_t RESERVED4[47]; + + union + { + __IOM uint8_t CPINTCTL; /*!< (@ 0x00000040) Comparator Interrupt Control Register */ + + struct + { + __IOM uint8_t MSKE : 1; /*!< [0..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 7; + } CPINTCTL_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t CPMSKCTL; /*!< (@ 0x00000044) Comparator Interrupt Mask Control Register */ + + struct + { + __IOM uint8_t MSKSEL : 3; /*!< [2..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 5; + } CPMSKCTL_b; + }; +} R_ACMPHS0_Type; /*!< Size = 69 (0x45) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Peripheral Security Control Unit (R_PSCU) + */ + +typedef struct /*!< (@ 0x40204000) R_PSCU Structure */ +{ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + + struct + { + __IOM uint32_t PSARB0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARB1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARB2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARB3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARB4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARB5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARB6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARB7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARB8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARB9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARB10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARB11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARB12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARB13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARB14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARB15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARB16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARB17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARB18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARB19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARB20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARB21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARB22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARB23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARB24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARB25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARB26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARB27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARB28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARB29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARB30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARB31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ + } PSARB_b; + }; + + union + { + __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ + + struct + { + __IOM uint32_t PSARC0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARC1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARC2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARC3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARC4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARC5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARC6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARC7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARC8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARC9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARC10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARC11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARC12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARC13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARC14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARC15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARC16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARC17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARC18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARC19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARC20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARC21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARC22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARC23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARC24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARC25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARC26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARC27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARC28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARC29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARC30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARC31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ + } PSARC_b; + }; + + union + { + __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ + + struct + { + __IOM uint32_t PSARD0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARD1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARD2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARD3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARD4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARD5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARD6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARD7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARD8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARD9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARD10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARD11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARD12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARD13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARD14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARD15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARD16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARD17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARD18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARD19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARD20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARD21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARD22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARD23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARD24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARD25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARD26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARD27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARD28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARD29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARD30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARD31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ + } PSARD_b; + }; + + union + { + __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ + + struct + { + __IOM uint32_t PSARE0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARE1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARE2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARE3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARE4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARE5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARE6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARE7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARE8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARE9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARE10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARE11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARE12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARE13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARE14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARE15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARE16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARE17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARE18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARE19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARE20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARE21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARE22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARE23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARE24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARE25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARE26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARE27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARE28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARE29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARE30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARE31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ + } PSARE_b; + }; + + union + { + __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ + + struct + { + __IOM uint32_t MSSAR0 : 1; /*!< [0..0] Module stop security attribution bit 0 */ + __IOM uint32_t MSSAR1 : 1; /*!< [1..1] Module stop security attribution bit 1 */ + __IOM uint32_t MSSAR2 : 1; /*!< [2..2] Module stop security attribution bit 2 */ + __IOM uint32_t MSSAR3 : 1; /*!< [3..3] Module stop security attribution bit 3 */ + __IOM uint32_t MSSAR4 : 1; /*!< [4..4] Module stop security attribution bit 4 */ + __IOM uint32_t MSSAR5 : 1; /*!< [5..5] Module stop security attribution bit 5 */ + __IOM uint32_t MSSAR6 : 1; /*!< [6..6] Module stop security attribution bit 6 */ + __IOM uint32_t MSSAR7 : 1; /*!< [7..7] Module stop security attribution bit 7 */ + __IOM uint32_t MSSAR8 : 1; /*!< [8..8] Module stop security attribution bit 8 */ + __IOM uint32_t MSSAR9 : 1; /*!< [9..9] Module stop security attribution bit 9 */ + __IOM uint32_t MSSAR10 : 1; /*!< [10..10] Module stop security attribution bit 10 */ + __IOM uint32_t MSSAR11 : 1; /*!< [11..11] Module stop security attribution bit 11 */ + __IOM uint32_t MSSAR12 : 1; /*!< [12..12] Module stop security attribution bit 12 */ + __IOM uint32_t MSSAR13 : 1; /*!< [13..13] Module stop security attribution bit 13 */ + __IOM uint32_t MSSAR14 : 1; /*!< [14..14] Module stop security attribution bit 14 */ + __IOM uint32_t MSSAR15 : 1; /*!< [15..15] Module stop security attribution bit 15 */ + __IOM uint32_t MSSAR16 : 1; /*!< [16..16] Module stop security attribution bit 16 */ + __IOM uint32_t MSSAR17 : 1; /*!< [17..17] Module stop security attribution bit 17 */ + __IOM uint32_t MSSAR18 : 1; /*!< [18..18] Module stop security attribution bit 18 */ + __IOM uint32_t MSSAR19 : 1; /*!< [19..19] Module stop security attribution bit 19 */ + __IOM uint32_t MSSAR20 : 1; /*!< [20..20] Module stop security attribution bit 20 */ + __IOM uint32_t MSSAR21 : 1; /*!< [21..21] Module stop security attribution bit 21 */ + __IOM uint32_t MSSAR22 : 1; /*!< [22..22] Module stop security attribution bit 22 */ + __IOM uint32_t MSSAR23 : 1; /*!< [23..23] Module stop security attribution bit 23 */ + __IOM uint32_t MSSAR24 : 1; /*!< [24..24] Module stop security attribution bit 24 */ + __IOM uint32_t MSSAR25 : 1; /*!< [25..25] Module stop security attribution bit 25 */ + __IOM uint32_t MSSAR26 : 1; /*!< [26..26] Module stop security attribution bit 26 */ + __IOM uint32_t MSSAR27 : 1; /*!< [27..27] Module stop security attribution bit 27 */ + __IOM uint32_t MSSAR28 : 1; /*!< [28..28] Module stop security attribution bit 28 */ + __IOM uint32_t MSSAR29 : 1; /*!< [29..29] Module stop security attribution bit 29 */ + __IOM uint32_t MSSAR30 : 1; /*!< [30..30] Module stop security attribution bit 30 */ + __IOM uint32_t MSSAR31 : 1; /*!< [31..31] Module stop security attribution bit 31 */ + } MSSAR_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t PPARB; /*!< (@ 0x0000001C) Peripheral Privilege Attribution Register B */ + + struct + { + __IOM uint32_t PPARB0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARB1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARB2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARB3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARB4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARB5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARB6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARB7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARB8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARB9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARB10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARB11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARB12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARB13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARB14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARB15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARB16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARB17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARB18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARB19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARB20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARB21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARB22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARB23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARB24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARB25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARB26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARB27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARB28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARB29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARB30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARB31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ + } PPARB_b; + }; + + union + { + __IOM uint32_t PPARC; /*!< (@ 0x00000020) Peripheral Privilege Attribution Register C */ + + struct + { + __IOM uint32_t PPARC0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARC1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARC2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARC3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARC4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARC5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARC6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARC7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARC8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARC9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARC10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARC11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARC12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARC13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARC14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARC15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARC16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARC17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARC18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARC19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARC20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARC21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARC22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARC23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARC24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARC25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARC26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARC27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARC28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARC29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARC30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARC31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ + } PPARC_b; + }; + + union + { + __IOM uint32_t PPARD; /*!< (@ 0x00000024) Peripheral Privilege Attribution Register D */ + + struct + { + __IOM uint32_t PPARD0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARD1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARD2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARD3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARD4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARD5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARD6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARD7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARD8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARD9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARD10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARD11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARD12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARD13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARD14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARD15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARD16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARD17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARD18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARD19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARD20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARD21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARD22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARD23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARD24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARD25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARD26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARD27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARD28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARD29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARD30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARD31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ + } PPARD_b; + }; + + union + { + __IOM uint32_t PPARE; /*!< (@ 0x00000028) Peripheral Privilege Attribution Register E */ + + struct + { + __IOM uint32_t PPARE0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARE1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARE2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARE3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARE4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARE5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARE6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARE7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARE8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARE9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARE10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARE11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARE12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARE13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARE14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARE15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARE16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARE17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARE18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARE19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARE20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARE21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARE22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARE23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARE24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARE25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARE26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARE27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARE28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARE29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARE30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARE31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ + } PPARE_b; + }; + + union + { + __IOM uint32_t MSPAR; /*!< (@ 0x0000002C) Module Stop Privilege Attribution Register */ + + struct + { + __IOM uint32_t MSPAR0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t MSPAR1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t MSPAR2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t MSPAR3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t MSPAR4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t MSPAR5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t MSPAR6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t MSPAR7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t MSPAR8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t MSPAR9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t MSPAR10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t MSPAR11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t MSPAR12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t MSPAR13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t MSPAR14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t MSPAR15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t MSPAR16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t MSPAR17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t MSPAR18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t MSPAR19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t MSPAR20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t MSPAR21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t MSPAR22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t MSPAR23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t MSPAR24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t MSPAR25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t MSPAR26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t MSPAR27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t MSPAR28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t MSPAR29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t MSPAR30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t MSPAR31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ + } MSPAR_b; + }; + + union + { + __IM uint32_t CFSAMONA; /*!< (@ 0x00000030) Code MRAM Security Attribution Monitor Register */ + + struct + { + uint32_t : 15; + __IM uint32_t CFS2 : 9; /*!< [23..15] Code Secure area */ + uint32_t : 8; + } CFSAMONA_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IM uint32_t DLMMON; /*!< (@ 0x00000038) Device Lifecycle Management State Monitor Register */ + + struct + { + __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ + uint32_t : 28; + } DLMMON_b; + }; + + union + { + __IM uint32_t SFSAMON; /*!< (@ 0x0000003C) SiP Flash Security Attribution Monitor Register */ + + struct + { + uint32_t : 15; + __IM uint32_t SFS : 9; /*!< [23..15] SiP Flash Secure Area */ + uint32_t : 8; + } SFSAMON_b; + }; +} R_PSCU_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + + union + { + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ + }; + __IM uint32_t RESERVED4[58]; + + union + { + union + { + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + }; + __IM uint32_t RESERVED5[46]; + + union + { + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ + }; + __IM uint32_t RESERVED6[27]; + + union + { + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ + + struct + { + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; + }; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED10[16]; + + union + { + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ + }; + __IM uint32_t RESERVED11[28]; + + union + { + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ + }; + __IM uint32_t RESERVED12[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6924 (0x1b0c) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40202400) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; + }; + + union + { + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + + struct + { + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; + }; + + union + { + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + + struct + { + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; + }; + + union + { + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + + struct + { + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; + }; + + union + { + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + + struct + { + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; + }; + + union + { + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; + }; + + union + { + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + + struct + { + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; + }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CANFD0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD0) + */ + +typedef struct /*!< (@ 0x40380000) R_CANFD0 Structure */ +{ + __IOM R_CANFD_CFDC_Type CFDC[1]; /*!< (@ 0x00000000) Channel Control/Status */ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CFDGCFG; /*!< (@ 0x00000014) Global Configuration Register */ + + struct + { + __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */ + __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */ + __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */ + __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */ + __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */ + __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD message Payload overflow configuration */ + uint32_t : 2; + __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */ + __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */ + uint32_t : 3; + __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */ + } CFDGCFG_b; + }; + + union + { + __IOM uint32_t CFDGCTR; /*!< (@ 0x00000018) Global Control Register */ + + struct + { + __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */ + __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */ + uint32_t : 5; + __IOM uint32_t DEIE : 1; /*!< [8..8] DLC check Interrupt Enable */ + __IOM uint32_t MEIE : 1; /*!< [9..9] Message lost Error Interrupt Enable */ + __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */ + __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable */ + uint32_t : 4; + __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */ + uint32_t : 15; + } CFDGCTR_b; + }; + + union + { + __IOM uint32_t CFDGSTS; /*!< (@ 0x0000001C) Global Status Register */ + + struct + { + __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */ + __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */ + __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */ + __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation */ + uint32_t : 28; + } CFDGSTS_b; + }; + + union + { + __IOM uint32_t CFDGERFL; /*!< (@ 0x00000020) Global Error Flag Register */ + + struct + { + __IOM uint32_t DEF : 1; /*!< [0..0] DLC Error Flag */ + __IM uint32_t MES : 1; /*!< [1..1] Message Lost Error Status */ + __IM uint32_t THLES : 1; /*!< [2..2] TX History List Entry Lost Error Status */ + __IOM uint32_t CMPOF : 1; /*!< [3..3] CAN-FD message payload overflow Flag */ + uint32_t : 12; + __IOM uint32_t EEF0 : 1; /*!< [16..16] ECC Error Flag for Channel 0 */ + uint32_t : 15; + } CFDGERFL_b; + }; + + union + { + __IOM uint32_t CFDGTSC; /*!< (@ 0x00000024) Global Timestamp Counter Register */ + + struct + { + __IM uint32_t TS : 16; /*!< [15..0] Timestamp Value */ + uint32_t : 16; + } CFDGTSC_b; + }; + + union + { + __IOM uint32_t CFDGAFLECTR; /*!< (@ 0x00000028) Global Acceptance Filter List Entry Control Register */ + + struct + { + __IOM uint32_t AFLPN : 4; /*!< [3..0] Acceptance Filter List Page Number */ + uint32_t : 4; + __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable */ + uint32_t : 23; + } CFDGAFLECTR_b; + }; + + union + { + __IOM uint32_t CFDGAFLCFG0; /*!< (@ 0x0000002C) Global Acceptance Filter List Configuration Register + * 0 */ + + struct + { + __IOM uint32_t RNC1 : 9; /*!< [8..0] Rule Number for Channel 1 */ + uint32_t : 7; + __IOM uint32_t RNC0 : 9; /*!< [24..16] Rule Number for Channel 0 */ + uint32_t : 7; + } CFDGAFLCFG0_b; + }; + + union + { + __IOM uint32_t CFDRMNB; /*!< (@ 0x00000030) RX Message Buffer Number Register */ + + struct + { + __IOM uint32_t NRXMB : 8; /*!< [7..0] Number of RX Message Buffers */ + __IOM uint32_t RMPLS : 3; /*!< [10..8] Reception Message Buffer Payload Data Size */ + uint32_t : 21; + } CFDRMNB_b; + }; + + union + { + __IOM uint32_t CFDRMND0; /*!< (@ 0x00000034) RX Message Buffer New Data Register 0 */ + + struct + { + __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status */ + } CFDRMND0_b; + }; + + union + { + __IOM uint32_t CFDRMIEC; /*!< (@ 0x00000038) RX Message Buffer Interrupt Enable Configuration + * Register */ + + struct + { + __IOM uint32_t RMIE : 32; /*!< [31..0] RX Message Buffer Interrupt Enable */ + } CFDRMIEC_b; + }; + + union + { + __IOM uint32_t CFDRFCC[2]; /*!< (@ 0x0000003C) RX FIFO Configuration / Control Registers */ + + struct + { + __IOM uint32_t RFE : 1; /*!< [0..0] RX FIFO Enable */ + __IOM uint32_t RFIE : 1; /*!< [1..1] RX FIFO Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t RFPLS : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration */ + uint32_t : 1; + __IOM uint32_t RFDC : 3; /*!< [10..8] RX FIFO Depth Configuration */ + uint32_t : 1; + __IOM uint32_t RFIM : 1; /*!< [12..12] RX FIFO Interrupt Mode */ + __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value */ + uint32_t : 16; + } CFDRFCC_b[2]; + }; + + union + { + __IOM uint32_t CFDRFSTS[2]; /*!< (@ 0x00000044) RX FIFO Status Registers */ + + struct + { + __IM uint32_t RFEMP : 1; /*!< [0..0] RX FIFO Empty */ + __IM uint32_t RFFLL : 1; /*!< [1..1] RX FIFO Full */ + __IOM uint32_t RFMLT : 1; /*!< [2..2] RX FIFO Message Lost */ + __IOM uint32_t RFIF : 1; /*!< [3..3] RX FIFO Interrupt Flag */ + uint32_t : 4; + __IM uint32_t RFMC : 8; /*!< [15..8] RX FIFO Message Count */ + uint32_t : 16; + } CFDRFSTS_b[2]; + }; + + union + { + __IOM uint32_t CFDRFPCTR[2]; /*!< (@ 0x0000004C) RX FIFO Pointer Control Registers */ + + struct + { + __OM uint32_t RFPC : 8; /*!< [7..0] RX FIFO Pointer Control */ + uint32_t : 24; + } CFDRFPCTR_b[2]; + }; + + union + { + __IOM uint32_t CFDCFCC[1]; /*!< (@ 0x00000054) Common FIFO Configuration / Control Registers */ + + struct + { + __IOM uint32_t CFE : 1; /*!< [0..0] Common FIFO Enable */ + __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable */ + __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CFPLS : 3; /*!< [6..4] Common FIFO Payload Data size configuration */ + uint32_t : 1; + __IOM uint32_t CFM : 2; /*!< [9..8] Common FIFO Mode */ + __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select */ + __IOM uint32_t CFITR : 1; /*!< [11..11] Common FIFO Interval Timer Resolution */ + __IOM uint32_t CFIM : 1; /*!< [12..12] Common FIFO Interrupt Mode */ + __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value */ + __IOM uint32_t CFTML : 5; /*!< [20..16] Common FIFO TX Message Buffer Link */ + __IOM uint32_t CFDC : 3; /*!< [23..21] Common FIFO Depth Configuration */ + __IOM uint32_t CFITT : 8; /*!< [31..24] Common FIFO Interval Transmission Time */ + } CFDCFCC_b[1]; + }; + + union + { + __IOM uint32_t CFDCFSTS[1]; /*!< (@ 0x00000058) Common FIFO Status Registers */ + + struct + { + __IM uint32_t CFEMP : 1; /*!< [0..0] Common FIFO Empty */ + __IM uint32_t CFFLL : 1; /*!< [1..1] Common FIFO Full */ + __IOM uint32_t CFMLT : 1; /*!< [2..2] Common FIFO Message Lost */ + __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag */ + __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag */ + uint32_t : 3; + __IM uint32_t CFMC : 8; /*!< [15..8] Common FIFO Message Count */ + uint32_t : 16; + } CFDCFSTS_b[1]; + }; + + union + { + __IOM uint32_t CFDCFPCTR[1]; /*!< (@ 0x0000005C) Common FIFO Pointer Control Registers */ + + struct + { + __OM uint32_t CFPC : 8; /*!< [7..0] Common FIFO Pointer Control */ + uint32_t : 24; + } CFDCFPCTR_b[1]; + }; + + union + { + __IM uint32_t CFDFESTS; /*!< (@ 0x00000060) FIFO Empty Status Register */ + + struct + { + __IM uint32_t RFXEMP : 2; /*!< [1..0] RX FIF0 Empty Status */ + uint32_t : 6; + __IM uint32_t CFXEMP : 1; /*!< [8..8] Common FIF0 Empty Status */ + uint32_t : 23; + } CFDFESTS_b; + }; + + union + { + __IM uint32_t CFDFFSTS; /*!< (@ 0x00000064) FIFO Full Status Register */ + + struct + { + __IM uint32_t RFXFLL : 2; /*!< [1..0] RX FIF0 Full Status */ + uint32_t : 6; + __IM uint32_t CFXFLL : 1; /*!< [8..8] Common FIF0 Full Status */ + uint32_t : 23; + } CFDFFSTS_b; + }; + + union + { + __IM uint32_t CFDFMSTS; /*!< (@ 0x00000068) FIFO Message Lost Status Register */ + + struct + { + __IM uint32_t RFXMLT : 2; /*!< [1..0] RX FIFO Msg Lost Status */ + uint32_t : 6; + __IM uint32_t CFXMLT : 1; /*!< [8..8] Common FIFO Msg Lost Status */ + uint32_t : 23; + } CFDFMSTS_b; + }; + + union + { + __IOM uint32_t CFDRFISTS; /*!< (@ 0x0000006C) RX FIFO Interrupt Flag Status Register */ + + struct + { + __IM uint32_t RFXIF : 2; /*!< [1..0] RX FIFO[x] Interrupt Flag Status */ + uint32_t : 30; + } CFDRFISTS_b; + }; + + union + { + __IOM uint8_t CFDTMC[4]; /*!< (@ 0x00000070) TX Message Buffer Control Registers */ + + struct + { + __IOM uint8_t TMTR : 1; /*!< [0..0] TX Message Buffer Transmission Request */ + __IOM uint8_t TMTAR : 1; /*!< [1..1] TX Message Buffer Transmission abort Request */ + __IOM uint8_t TMOM : 1; /*!< [2..2] TX Message Buffer One-shot Mode */ + uint8_t : 5; + } CFDTMC_b[4]; + }; + + union + { + __IOM uint8_t CFDTMSTS[4]; /*!< (@ 0x00000074) TX Message Buffer Status Registers */ + + struct + { + __IM uint8_t TMTSTS : 1; /*!< [0..0] TX Message Buffer Transmission Status */ + __IOM uint8_t TMTRF : 2; /*!< [2..1] TX Message Buffer Transmission Result Flag */ + __IM uint8_t TMTRM : 1; /*!< [3..3] TX Message Buffer Transmission Request Mirrored */ + __IM uint8_t TMTARM : 1; /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored */ + uint8_t : 3; + } CFDTMSTS_b[4]; + }; + + union + { + __IM uint32_t CFDTMTRSTS[1]; /*!< (@ 0x00000078) TX Message Buffer Transmission Request Status + * Register */ + + struct + { + __IM uint32_t CFDTMTRSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Request Status */ + uint32_t : 28; + } CFDTMTRSTS_b[1]; + }; + + union + { + __IM uint32_t CFDTMTARSTS[1]; /*!< (@ 0x0000007C) TX Message Buffer Transmission Abort Request + * Status Register */ + + struct + { + __IM uint32_t CFDTMTARSTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Request Status */ + uint32_t : 28; + } CFDTMTARSTS_b[1]; + }; + + union + { + __IM uint32_t CFDTMTCSTS[1]; /*!< (@ 0x00000080) TX Message Buffer Transmission Completion Status + * Register */ + + struct + { + __IM uint32_t CFDTMTCSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Completion Status */ + uint32_t : 28; + } CFDTMTCSTS_b[1]; + }; + + union + { + __IM uint32_t CFDTMTASTS[1]; /*!< (@ 0x00000084) TX Message Buffer Transmission Abort Status Register */ + + struct + { + __IM uint32_t CFDTMTASTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Status */ + uint32_t : 28; + } CFDTMTASTS_b[1]; + }; + + union + { + __IOM uint32_t CFDTMIEC[1]; /*!< (@ 0x00000088) TX Message Buffer Interrupt Enable Configuration + * Register */ + + struct + { + __IOM uint32_t TMIEg : 4; /*!< [3..0] TX Message Buffer Interrupt Enable */ + uint32_t : 28; + } CFDTMIEC_b[1]; + }; + + union + { + __IOM uint32_t CFDTXQCC0[1]; /*!< (@ 0x0000008C) TX Queue Configuration / Control Registers 0 */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + uint32_t : 4; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 2; /*!< [9..8] TX Queue Depth Configuration */ + uint32_t : 22; + } CFDTXQCC0_b[1]; + }; + + union + { + __IOM uint32_t CFDTXQSTS0[1]; /*!< (@ 0x00000090) TX Queue Status Registers 0 */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 18; + } CFDTXQSTS0_b[1]; + }; + + union + { + __IOM uint32_t CFDTXQPCTR0[1]; /*!< (@ 0x00000094) TX Queue Pointer Control Registers 0 */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR0_b[1]; + }; + + union + { + __IOM uint32_t CFDTHLCC[1]; /*!< (@ 0x00000098) TX History List Configuration / Control Register */ + + struct + { + __IOM uint32_t THLE : 1; /*!< [0..0] TX History List Enable */ + uint32_t : 7; + __IOM uint32_t THLIE : 1; /*!< [8..8] TX History List Interrupt Enable */ + __IOM uint32_t THLIM : 1; /*!< [9..9] TX History List Interrupt Mode */ + __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable */ + uint32_t : 21; + } CFDTHLCC_b[1]; + }; + + union + { + __IOM uint32_t CFDTHLSTS[1]; /*!< (@ 0x0000009C) TX History List Status Register */ + + struct + { + __IM uint32_t THLEMP : 1; /*!< [0..0] TX History List Empty */ + __IM uint32_t THLFLL : 1; /*!< [1..1] TX History List Full */ + __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost */ + __IOM uint32_t THLIF : 1; /*!< [3..3] TX History List Interrupt Flag */ + uint32_t : 4; + __IM uint32_t THLMC : 6; /*!< [13..8] TX History List Message Count */ + uint32_t : 18; + } CFDTHLSTS_b[1]; + }; + + union + { + __IOM uint32_t CFDTHLPCTR[1]; /*!< (@ 0x000000A0) TX History List Pointer Control Registers */ + + struct + { + __OM uint32_t THLPC : 8; /*!< [7..0] TX History List Pointer Control */ + uint32_t : 24; + } CFDTHLPCTR_b[1]; + }; + + union + { + __IOM uint32_t CFDGTINTSTS0; /*!< (@ 0x000000A4) Global TX Interrupt Status Register 0 */ + + struct + { + __IM uint32_t TSIF0 : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0 */ + __IM uint32_t TAIF0 : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0 */ + __IM uint32_t TQIF0 : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0 */ + __IM uint32_t CFTIF0 : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0 */ + __IM uint32_t THIF0 : 1; /*!< [4..4] TX History List Interrupt Channel 0 */ + uint32_t : 27; + } CFDGTINTSTS0_b; + }; + + union + { + __IOM uint32_t CFDGTSTCFG; /*!< (@ 0x000000A8) Global Test Configuration Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select */ + uint32_t : 6; + } CFDGTSTCFG_b; + }; + + union + { + __IOM uint32_t CFDGTSTCTR; /*!< (@ 0x000000AC) Global Test Control Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t RTME : 1; /*!< [2..2] RAM Test Mode Enable */ + uint32_t : 29; + } CFDGTSTCTR_b; + }; + + union + { + __IOM uint32_t CFDGFDCFG; /*!< (@ 0x000000B0) Global FD Configuration register */ + + struct + { + __IOM uint32_t RPED : 1; /*!< [0..0] RES bit Protocol exception disable */ + uint32_t : 7; + __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration */ + uint32_t : 22; + } CFDGFDCFG_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t CFDGLOCKK; /*!< (@ 0x000000B8) Global Lock Key Register */ + + struct + { + __OM uint32_t LOCK : 16; /*!< [15..0] Lock Key */ + uint32_t : 16; + } CFDGLOCKK_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFDGAFLIGNENT; /*!< (@ 0x000000C0) Global AFL Ignore Entry Register */ + + struct + { + __IOM uint32_t IRN : 5; /*!< [4..0] Ignore Rule Number */ + uint32_t : 27; + } CFDGAFLIGNENT_b; + }; + + union + { + __IOM uint32_t CFDGAFLIGNCTR; /*!< (@ 0x000000C4) Global AFL Ignore Control Register */ + + struct + { + __IOM uint32_t IREN : 1; /*!< [0..0] Ignore Rule Enable */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key code */ + uint32_t : 16; + } CFDGAFLIGNCTR_b; + }; + + union + { + __IOM uint32_t CFDCDTCT; /*!< (@ 0x000000C8) DMA Transfer Control Register */ + + struct + { + __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0 */ + __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1 */ + uint32_t : 6; + __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0 */ + uint32_t : 23; + } CFDCDTCT_b; + }; + + union + { + __IM uint32_t CFDCDTSTS; /*!< (@ 0x000000CC) DMA Transfer Status Register */ + + struct + { + __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0 */ + __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1 */ + uint32_t : 6; + __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel + * 0 */ + uint32_t : 23; + } CFDCDTSTS_b; + }; + __IM uint32_t RESERVED3[2]; + + union + { + __IOM uint32_t CFDGRSTC; /*!< (@ 0x000000D8) Global SW reset Register */ + + struct + { + __IOM uint32_t SRST : 1; /*!< [0..0] SW reset */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key code */ + uint32_t : 16; + } CFDGRSTC_b; + }; + __IM uint32_t RESERVED4[9]; + __IOM R_CANFD_CFDC2_Type CFDC2[1]; /*!< (@ 0x00000100) Channel Configuration Registers */ + __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00000120) Global Acceptance Filter List Registers */ + __IM uint32_t RESERVED5[24]; + + union + { + __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00000280) RAM Test Page Access Registers */ + + struct + { + __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */ + } CFDRPGACC_b[64]; + }; + __IM uint32_t RESERVED6[104]; + __IOM R_CANFD_CFDRF_Type CFDRF[2]; /*!< (@ 0x00000520) RX FIFO Access Registers */ + __IOM R_CANFD_CFDCF_Type CFDCF[1]; /*!< (@ 0x000005B8) Common FIFO Access Registers */ + __IOM R_CANFD_CFDTM_Type CFDTM[4]; /*!< (@ 0x00000604) TX Message Buffer Access Registers */ + __IM uint32_t RESERVED7[3]; + __IOM R_CANFD_CFDTHL_Type CFDTHL[1]; /*!< (@ 0x00000740) Channel TX History List */ + __IM uint32_t RESERVED8[118]; + __IOM R_CANFD_CFDRM_Type CFDRM[4]; /*!< (@ 0x00000920) RX Message Buffer Access Clusters */ +} R_CANFD_Type; /*!< Size = 6432 (0x1920) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40310000) R_CRC Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + + union + { + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + + struct + { + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union + { + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union + { + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; + }; + + union + { + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + + struct + { + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; + }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC_B0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief 12-bit D/A converter (R_DAC_B0) + */ + +typedef struct /*!< (@ 0x40233000) R_DAC_B0 Structure */ +{ + union + { + __IOM uint16_t DADR; /*!< (@ 0x00000000) D/A Data Register */ + + struct + { + __IOM uint16_t DADR : 16; /*!< [15..0] D/A converted data */ + } DADR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint32_t DACR0; /*!< (@ 0x00000004) D/A Control Register 0 */ + + struct + { + __IOM uint32_t DACEN : 1; /*!< [0..0] DA enable bit */ + uint32_t : 14; + __IOM uint32_t DAE : 1; /*!< [15..15] DA batch conversion control bit */ + uint32_t : 15; + __IOM uint32_t DAOUTDIS : 1; /*!< [31..31] Analog output disable bit */ + } DACR0_b; + }; + + union + { + __IOM uint32_t DACR1; /*!< (@ 0x00000008) D/A Control Register 1 */ + + struct + { + uint32_t : 16; + __IOM uint32_t DPSEL : 1; /*!< [16..16] Data placement selection bit */ + uint32_t : 15; + } DACR1_b; + }; + + union + { + __IOM uint32_t DACR2; /*!< (@ 0x0000000C) D/A Control Register 2 */ + + struct + { + uint32_t : 8; + __IOM uint32_t OFSSEL : 1; /*!< [8..8] DAC-HM operating voltage mode select bit */ + uint32_t : 23; + } DACR2_b; + }; +} R_DAC_B0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ + +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ + union + { + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + + struct + { + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + + struct + { + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT1 : 1; /*!< [2..2] Mask bit for WDT1 reset/interrupt in the OCD run mode */ + uint32_t : 11; + __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ + __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + __IOM uint32_t DBGSTOP_NVMERR : 1; /*!< [26..26] Mask bit for MRAM ECC error reset/interrupt */ + uint32_t : 1; + __IOM uint32_t DBGSTOP_CTERR0 : 1; /*!< [28..28] Mask bit for CPU0's Cache/TCM ECC error reset */ + __IOM uint32_t DBGSTOP_CTERR1 : 1; /*!< [29..29] This bit is reserved. It can be R/W but no effect */ + uint32_t : 1; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t DBGAUTH0; /*!< (@ 0x00000020) Debug Authentication Control Register0 */ + + struct + { + __IOM uint32_t DBGEN0 : 1; /*!< [0..0] CPU0 invasive debug enable */ + __IOM uint32_t DBGEN1 : 1; /*!< [1..1] CPU1 invasive debug enable */ + uint32_t : 2; + __IOM uint32_t NIDEN0 : 1; /*!< [4..4] CPU0 non-invasive debug enable */ + __IOM uint32_t NIDEN1 : 1; /*!< [5..5] CPU1 non-invasive debug enable */ + uint32_t : 10; + __IOM uint32_t DEVICEEN : 1; /*!< [16..16] APB-AP (AP1) authentication */ + uint32_t : 14; + __IM uint32_t SWDBG : 1; /*!< [31..31] Software control of debug function */ + } DBGAUTH0_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t TRPORTCR; /*!< (@ 0x00000030) Trace Port Control Register */ + + struct + { + __IOM uint32_t OE : 1; /*!< [0..0] Data Out Enable bit indicates whether Trace Clock, Trace + * Data and SWO outputs are enabled or not. */ + uint32_t : 1; + __IOM uint32_t DRV : 2; /*!< [3..2] Port Drive Capability Control indicate trace port buffer + * speed */ + uint32_t : 4; + __IOM uint32_t PORTSEL : 2; /*!< [9..8] None */ + uint32_t : 6; + __IOM uint32_t SWOSEL : 1; /*!< [16..16] Select SWO between CPU0 and CPU1 */ + uint32_t : 15; + } TRPORTCR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t TRPORTSZ; /*!< (@ 0x00000038) Trace Port Size Control Register */ + + struct + { + __IOM uint32_t PORTSIZE : 32; /*!< [31..0] Indicates how many pins of TRACEDATA are available. */ + } TRPORTSZ_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t CACHEDBGCR; /*!< (@ 0x00000040) Cache Debug Control Register */ + + struct + { + __IOM uint32_t L1RSTDIS : 1; /*!< [0..0] Disable L1 cache automatic invalidation of CPU0 */ + uint32_t : 31; + } CACHEDBGCR_b; + }; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint32_t DBGNVMCR; /*!< (@ 0x00000050) Debug Non-volatile Memory Control Register */ + + struct + { + __IOM uint32_t NVMWE : 1; /*!< [0..0] Non-volatile memory write enable */ + uint32_t : 31; + } DBGNVMCR_b; + }; + __IM uint32_t RESERVED6[43]; + + union + { + __IOM uint32_t ALCTRL; /*!< (@ 0x00000100) Authentication Level Control Register */ + + struct + { + __IOM uint32_t AL : 8; /*!< [7..0] AL monitor */ + uint32_t : 22; + __IOM uint32_t FAILCNT : 2; /*!< [31..30] Number of times responding incorrect response data */ + } ALCTRL_b; + }; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ + + struct + { + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; + }; +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller Common (R_DMA) + */ + +typedef struct /*!< (@ 0x4000A800) R_DMA Structure */ +{ + union + { + __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ + + struct + { + __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ + uint8_t : 7; + } DMAST_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ + + struct + { + __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ + uint8_t : 3; + __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ + uint8_t : 3; + } DMCTL_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[11]; + + union + { + __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ + + struct + { + __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ + uint32_t : 4; + __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ + uint32_t : 7; + __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ + uint32_t : 15; + } DMECHR_b; + }; + __IM uint32_t RESERVED6[15]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000080) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] DMAC Event Link Select */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; +} R_DMA_Type; /*!< Size = 160 (0xa0) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller (R_DMAC0) + */ + +typedef struct /*!< (@ 0x4000A000) R_DMAC0 Structure */ +{ + union + { + __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ + + struct + { + __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ + } DMSAR_b; + }; + + union + { + __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ + + struct + { + __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ + } DMDAR_b; + }; + + union + { + __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ + __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ + uint32_t : 6; + } DMCRA_b; + }; + + union + { + __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block + * transfer counter. */ + __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or + * repeat transfer operations. */ + } DMCRB_b; + }; + + union + { + __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ + + struct + { + __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ + uint16_t : 6; + __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ + __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ + uint16_t : 1; + __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ + __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ + } DMTMD_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ + + struct + { + __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ + __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ + __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ + uint8_t : 3; + } DMINT_b; + }; + + union + { + __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ + + struct + { + __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the + * extended repeat area on the destination address. For details + * on the settings. */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ + __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended + * repeat area on the source address. For details on the settings. */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ + } DMAMD_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ + + struct + { + __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected + * as the address update mode for transfer source or destination. */ + } DMOFR_b; + }; + + union + { + __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ + + struct + { + __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ + uint8_t : 7; + } DMCNT_b; + }; + + union + { + __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ + + struct + { + __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ + uint8_t : 3; + __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ + uint8_t : 3; + } DMREQ_b; + }; + + union + { + __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ + + struct + { + __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ + uint8_t : 3; + __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ + uint8_t : 2; + __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ + } DMSTS_b; + }; + __IM uint8_t RESERVED2; + __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ + __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ + + union + { + __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ + + struct + { + __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMSBS_b; + }; + + union + { + __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ + + struct + { + __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMDBS_b; + }; + + union + { + __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ + + struct + { + __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ + uint8_t : 7; + } DMBWR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DMAC0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x40311000) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + + struct + { + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; + }; + + union + { + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + + struct + { + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; + }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_DRW ================ */ +/* =========================================================================================================================== */ + +/** + * @brief 2D Drawing Engine (R_DRW) + */ + +typedef struct /*!< (@ 0x40444000) R_DRW Structure */ +{ + union + { + union + { + __OM uint32_t CONTROL; /*!< (@ 0x00000000) Geometry Control Register */ + + struct + { + __OM uint32_t LIM1ENABLE : 1; /*!< [0..0] Enable limiter 1 */ + __OM uint32_t LIM2ENABLE : 1; /*!< [1..1] Enable limiter 2 */ + __OM uint32_t LIM3ENABLE : 1; /*!< [2..2] Enable limiter 3 */ + __OM uint32_t LIM4ENABLE : 1; /*!< [3..3] Enable limiter 4 */ + __OM uint32_t LIM5ENABLE : 1; /*!< [4..4] Enable limiter 5 */ + __OM uint32_t LIM6ENABLE : 1; /*!< [5..5] Enable limiter 6 */ + __OM uint32_t QUAD1ENABLE : 1; /*!< [6..6] Enable quadratic coupling of limiters 1 and 2 */ + __OM uint32_t QUAD2ENABLE : 1; /*!< [7..7] Enable quadratic coupling of limiters 3 and 4 */ + __OM uint32_t QUAD3ENABLE : 1; /*!< [8..8] Enable quadratic coupling of limiters 5 and 6 */ + __OM uint32_t LIM1THRESHOLD : 1; /*!< [9..9] Enable limiter 1 threshold mode */ + __OM uint32_t LIM2THRESHOLD : 1; /*!< [10..10] Enable limiter 2 threshold mode */ + __OM uint32_t LIM3THRESHOLD : 1; /*!< [11..11] Enable limiter 3 threshold mode */ + __OM uint32_t LIM4THRESHOLD : 1; /*!< [12..12] Enable limiter 4 threshold mode */ + __OM uint32_t LIM5THRESHOLD : 1; /*!< [13..13] Enable limiter 5 threshold mode */ + __OM uint32_t LIM6THRESHOLD : 1; /*!< [14..14] Enable limiter 6 threshold mode */ + __OM uint32_t BAND1ENABLE : 1; /*!< [15..15] Enable band postprocess for limiter 1 (see L1BAND) */ + __OM uint32_t BAND2ENABLE : 1; /*!< [16..16] Enable band postprocess for limiter 1 (see L1BAND) */ + __OM uint32_t UNION12 : 1; /*!< [17..17] Combine limter 1 & 2 as union (output is called A) */ + __OM uint32_t UNION34 : 1; /*!< [18..18] Combine limter 3 & 4 as union (output is called B) */ + __OM uint32_t UNION56 : 1; /*!< [19..19] Combine limter 5 & 6 as union (output is called D) */ + __OM uint32_t UNIONAB : 1; /*!< [20..20] Combine outputs A & B as union (output is called C) */ + __OM uint32_t UNIONCD : 1; /*!< [21..21] Combine outputs C & D as union (output is final) */ + __OM uint32_t SPANABORT : 1; /*!< [22..22] Shape is horizontally convex, only a single span per + * scanline */ + __OM uint32_t SPANSTORE : 1; /*!< [23..23] Nextline span start is always equal or left to current-line + * span start */ + uint32_t : 8; + } CONTROL_b; + }; + + union + { + __IM uint32_t STATUS; /*!< (@ 0x00000000) Status Control Register */ + + struct + { + __IM uint32_t BUSYENUM : 1; /*!< [0..0] Enumeration unit status */ + __IM uint32_t BUSYWRITE : 1; /*!< [1..1] Framebuffer writeback status */ + __IM uint32_t CACHEDIRTY : 1; /*!< [2..2] Framebuffer cache status */ + __IM uint32_t DLISTACTIVE : 1; /*!< [3..3] Display list reader status */ + __IM uint32_t ENUMIRQ : 1; /*!< [4..4] enumeration finished interrupt triggered */ + __IM uint32_t DLISTIRQ : 1; /*!< [5..5] display list finished interrupt triggered */ + __IM uint32_t BUSIRQ : 1; /*!< [6..6] bus error interrupt triggered */ + uint32_t : 1; + __IM uint32_t BUSERRMFB : 1; /*!< [8..8] framebuffer bus error interrupt triggered */ + __IM uint32_t BUSERRMTXMRL : 1; /*!< [9..9] texture bus error interrupt triggered */ + __IM uint32_t BUSERRMDL : 1; /*!< [10..10] display list bus error interrupt triggered */ + uint32_t : 21; + } STATUS_b; + }; + }; + + union + { + union + { + __OM uint32_t CONTROL2; /*!< (@ 0x00000004) Surface Control Register */ + + struct + { + __OM uint32_t PATTERNENABLE : 1; /*!< [0..0] Pixel source is a pattern color (blend of COLOR1 and + * COLOR2 depending on PATTERN and pattern index) */ + __OM uint32_t TEXTUREENABLE : 1; /*!< [1..1] Pixel source is read from texture and used as an alpha + * to blend between COLOR1 and COLOR2 */ + __OM uint32_t PATTERNSOURCEL5 : 1; /*!< [2..2] Limiter 5 is used as pattern index instead of the default + * U limiter.Limiter 5 can be combined with limiter 6 to form + * a quadratic limiter which can be used to make quadratic + * pattern functions to draw radial patterns. */ + __OM uint32_t USEACB : 1; /*!< [3..3] Alpha blend mode */ + __OM uint32_t READFORMAT32 : 2; /*!< [5..4] Bit 4 and 3 of the texture buffer format.See READFORMAT + * above for description */ + __OM uint32_t BSFA : 1; /*!< [6..6] Blend source factor for alpha channel in alpha channel + * blending mode (USEACB = 1) */ + __OM uint32_t BDFA : 1; /*!< [7..7] Blend destinetion factor for alpha channel in alpha channel + * blending mode (USEACB = 1) */ + __OM uint32_t WRITEFORMAT2 : 1; /*!< [8..8] Bit 3 of framebuffer pixel formatSee WRITEFORMAT above + * description. */ + __OM uint32_t BSF : 1; /*!< [9..9] Blend source factorsrc factor is alpha (factor is 1 per + * default) */ + __OM uint32_t BDF : 1; /*!< [10..10] Blend destination factordst factor is alpha (factor + * is 1 per default) */ + __OM uint32_t BSI : 1; /*!< [11..11] Blend source factor is invertedsrc factor will be inverted + * (meaning 1-a or 1-1 depending on BSF) */ + __OM uint32_t BDI : 1; /*!< [12..12] Blend destination factor is inverteddst factor will + * be inverted (meaning 1-a or 1-1 depending on BDF) */ + __OM uint32_t BC2 : 1; /*!< [13..13] Blend color 2 instead of framebuffer pixel */ + __OM uint32_t TEXTURECLAMPX : 1; /*!< [14..14] Calculating U limiter outside use textureThe bit describes + * what happens if the U limiter (x direction in texture space) + * calculates a U value outside of the used texture */ + __OM uint32_t TEXTURECLAMPY : 1; /*!< [15..15] Calculating V limiter outside use textureThe bit describes + * what happens if the V limiter (y direction in texture space) + * calculates a V value outside of the used texture */ + __OM uint32_t TEXTUREFILTERX : 1; /*!< [16..16] Linear filtering on texture U axis */ + __OM uint32_t TEXTUREFILTERY : 1; /*!< [17..17] Linear filtering on texture V axis */ + __OM uint32_t READFORMAT10 : 2; /*!< [19..18] Pixel format of the texture buffer{READFORMAT32,READFORMAT10}0000: + * 8 bpp a(8)0001: 16 bpp RGB(565)0010: 32 bpp aRGB(8888)0011: + * 16 bpp aRGB(4444)0100: 16 bpp aRGB(1555)0101: 8 bpp aCLUT(44) + * 4 bit alpha and 4 bit indexed color1001: 8 bpp CLUT(8)/I(8), + * 8 bit indexed color/luminance1010: 4 bpp CLUT(4)/I(4), + * 4 bit indexed color/luminance1011: 2 bpp CLUT(2)/I(2), + * 2 bit indexed color/luminance 1100: 1 bpp CLUT(1)/I(1), + * 1 bit indexed color/luminance */ + __OM uint32_t WRITEFORMAT10 : 2; /*!< [21..20] Pixel format of the framebuffer */ + __OM uint32_t WRITEALPHA : 2; /*!< [23..22] Writeback alpha source for framebufferSet the 'alpha + * source' for the framebuffer(USEACB = 0)Blend alpha in color + * 2 instead of framebuffer alpha((USEACB = 1))In not alpha + * channel blending mode (USEACB = 0):Set the 'alpha source' + * for the framebuffer.In alpha channel blending mode (USEACB + * = 1):Blend alpha in color 2 instead of framebuffer alpha00B: + * BC2A = 1: use alpha from framebuffer as destination (DST_A)else: + * BC2A = 0: use alpha in color 2 as destination (DST_A) */ + __OM uint32_t RLEENABLE : 1; /*!< [24..24] RLE enable */ + __OM uint32_t CLUTENABLE : 1; /*!< [25..25] CLUT enable */ + __OM uint32_t COLKEYENABLE : 1; /*!< [26..26] color keying enable */ + __OM uint32_t CLUTFORMAT : 1; /*!< [27..27] Format of the CLUT */ + __OM uint32_t BSIA : 1; /*!< [28..28] Blend source factor inverted in alpha channel (USEACB + * = 1) */ + __OM uint32_t BDIA : 1; /*!< [29..29] Blend destination factor inverted in alpha channel + * (USEACB = 1) */ + __OM uint32_t RLEPIXELWIDTH : 2; /*!< [31..30] Texel width for RLE unit */ + } CONTROL2_b; + }; + + union + { + __IM uint32_t HWREVISION; /*!< (@ 0x00000004) Hardware Version and Feature Set ID Register */ + + struct + { + __IM uint32_t REV : 12; /*!< [11..0] Revision number */ + uint32_t : 5; + __IM uint32_t DLR : 1; /*!< [17..17] Display list reader feature */ + __IM uint32_t FBCACHE : 1; /*!< [18..18] Framebuffer cache feature */ + __IM uint32_t TXCACHE : 1; /*!< [19..19] Texture cache feature */ + __IM uint32_t PERFCOUNT : 1; /*!< [20..20] Two performance counter feature */ + __IM uint32_t TEXCLU : 1; /*!< [21..21] Texture CLUT with 16 or 256 entries feature */ + uint32_t : 1; + __IM uint32_t RLEUNIT : 1; /*!< [23..23] RLE unit feature */ + __IM uint32_t TEXCLUT256 : 1; /*!< [24..24] Texture CLUT feature */ + __IM uint32_t COLORKEY : 1; /*!< [25..25] Colorkey feature */ + uint32_t : 1; + __IM uint32_t ACBLEND : 1; /*!< [27..27] Alpha channel blending feature */ + uint32_t : 4; + } HWREVISION_b; + }; + }; + __IM uint32_t RESERVED[2]; + + union + { + __OM uint32_t L1START; /*!< (@ 0x00000010) Limiter 1 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L1START_b; + }; + + union + { + __OM uint32_t L2START; /*!< (@ 0x00000014) Limiter 2 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L2START_b; + }; + + union + { + __OM uint32_t L3START; /*!< (@ 0x00000018) Limiter 3 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L3START_b; + }; + + union + { + __OM uint32_t L4START; /*!< (@ 0x0000001C) Limiter 4 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L4START_b; + }; + + union + { + __OM uint32_t L5START; /*!< (@ 0x00000020) Limiter 5 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L5START_b; + }; + + union + { + __OM uint32_t L6START; /*!< (@ 0x00000024) Limiter 6 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L6START_b; + }; + + union + { + __OM uint32_t L1XADD; /*!< (@ 0x00000028) Limiter 1 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L1XADD_b; + }; + + union + { + __OM uint32_t L2XADD; /*!< (@ 0x0000002C) Limiter 2 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L2XADD_b; + }; + + union + { + __OM uint32_t L3XADD; /*!< (@ 0x00000030) Limiter 3 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L3XADD_b; + }; + + union + { + __OM uint32_t L4XADD; /*!< (@ 0x00000034) Limiter 4 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L4XADD_b; + }; + + union + { + __OM uint32_t L5XADD; /*!< (@ 0x00000038) Limiter 5 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L5XADD_b; + }; + + union + { + __OM uint32_t L6XADD; /*!< (@ 0x0000003C) Limiter 6 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L6XADD_b; + }; + + union + { + __OM uint32_t L1YADD; /*!< (@ 0x00000040) Limiter 1 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L1YADD_b; + }; + + union + { + __OM uint32_t L2YADD; /*!< (@ 0x00000044) Limiter 2 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L2YADD_b; + }; + + union + { + __OM uint32_t L3YADD; /*!< (@ 0x00000048) Limiter 3 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L3YADD_b; + }; + + union + { + __OM uint32_t L4YADD; /*!< (@ 0x0000004C) Limiter 4 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L4YADD_b; + }; + + union + { + __OM uint32_t L5YADD; /*!< (@ 0x00000050) Limiter 5 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L5YADD_b; + }; + + union + { + __OM uint32_t L6YADD; /*!< (@ 0x00000054) Limiter 6 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L6YADD_b; + }; + + union + { + __OM uint32_t L1BAND; /*!< (@ 0x00000058) Limiter 1 Band Width Parameter Register */ + + struct + { + __OM uint32_t LBAND : 32; /*!< [31..0] Limiter m band width parameter */ + } L1BAND_b; + }; + + union + { + __OM uint32_t L2BAND; /*!< (@ 0x0000005C) Limiter 2 Band Width Parameter Register */ + + struct + { + __OM uint32_t LBAND : 32; /*!< [31..0] Limiter m band width parameter */ + } L2BAND_b; + }; + __IM uint32_t RESERVED1; + + union + { + __OM uint32_t COLOR1; /*!< (@ 0x00000064) Base Color Register */ + + struct + { + __OM uint32_t COLOR1B : 8; /*!< [7..0] Blue channel of color 1 */ + __OM uint32_t COLOR1G : 8; /*!< [15..8] Green channel of color 1 */ + __OM uint32_t COLOR1R : 8; /*!< [23..16] Red channel of color 1 */ + __OM uint32_t COLOR1A : 8; /*!< [31..24] Alpha channel of color 1(0x00: transparent. . . 0xFF: + * opaque) */ + } COLOR1_b; + }; + + union + { + __OM uint32_t COLOR2; /*!< (@ 0x00000068) Secondary Color Register */ + + struct + { + __OM uint32_t COLOR2B : 8; /*!< [7..0] Blue channel of color 2 */ + __OM uint32_t COLOR2G : 8; /*!< [15..8] Green channel of color 2 */ + __OM uint32_t COLOR2R : 8; /*!< [23..16] Red channel of color 2 */ + __OM uint32_t COLOR2A : 8; /*!< [31..24] Alpha channel of color 2(0x00: transparent. . . 0xFF: + * opaque) */ + } COLOR2_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __OM uint32_t PATTERN; /*!< (@ 0x00000074) Pattern Register */ + + struct + { + __OM uint32_t PATTERN : 8; /*!< [7..0] Bitmap of the pattern */ + uint32_t : 24; + } PATTERN_b; + }; + + union + { + __OM uint32_t SIZE; /*!< (@ 0x00000078) Bounding Box Dimension Register */ + + struct + { + __OM uint32_t SIZEX : 16; /*!< [15..0] Width of the bounding box in pixelsvalid range: 0 to + * 1024 */ + __OM uint32_t SIZEY : 16; /*!< [31..16] Height of the bounding box in pixelsvalid range: 0 + * to 1024 */ + } SIZE_b; + }; + + union + { + __OM uint32_t PITCH; /*!< (@ 0x0000007C) Framebuffer Pitch And Spanstore Delay Register */ + + struct + { + __OM uint32_t PITCH : 16; /*!< [15..0] pitch of the framebuffer. A negative width can be used + * to render bottom-up instead of top-down */ + __OM uint32_t SSD : 16; /*!< [31..16] Spanstore delay */ + } PITCH_b; + }; + + union + { + __OM uint32_t ORIGIN; /*!< (@ 0x00000080) Framebuffer Base Address Register */ + + struct + { + __OM uint32_t ORIGIN : 32; /*!< [31..0] Address of the first pixel in framebuffer */ + } ORIGIN_b; + }; + __IM uint32_t RESERVED3[3]; + + union + { + __OM uint32_t LUSTART; /*!< (@ 0x00000090) U Limiter Start Value Register */ + + struct + { + __OM uint32_t LUSTART : 32; /*!< [31..0] U limiter start value */ + } LUSTART_b; + }; + + union + { + __OM uint32_t LUXADD; /*!< (@ 0x00000094) U Limiter X-Axis Increment Register */ + + struct + { + __OM uint32_t LUXADD : 32; /*!< [31..0] U limiter x-axis increment */ + } LUXADD_b; + }; + + union + { + __OM uint32_t LUYADD; /*!< (@ 0x00000098) U Limiter Y-Axis Increment Register */ + + struct + { + __OM uint32_t LUYADD : 32; /*!< [31..0] U limiter y-axis increment */ + } LUYADD_b; + }; + + union + { + __OM uint32_t LVSTARTI; /*!< (@ 0x0000009C) V Limiter Start Value Integer Part Register */ + + struct + { + __OM uint32_t LVSTARTI : 32; /*!< [31..0] V limiter start value integer part */ + } LVSTARTI_b; + }; + + union + { + __OM uint32_t LVSTARTF; /*!< (@ 0x000000A0) V Limiter Start Value Fractional Part Register */ + + struct + { + __OM uint32_t LVSTARTF : 16; /*!< [15..0] V limiter start value fractional part */ + uint32_t : 16; + } LVSTARTF_b; + }; + + union + { + __OM uint32_t LVXADDI; /*!< (@ 0x000000A4) V Limiter X-Axis Increment Integer Part Register */ + + struct + { + __OM uint32_t LVXADDI : 32; /*!< [31..0] V limiter x-axis increment integer part */ + } LVXADDI_b; + }; + + union + { + __OM uint32_t LVYADDI; /*!< (@ 0x000000A8) V Limiter Y-Axis Increment Integer Part Register */ + + struct + { + __OM uint32_t LVYADDI : 32; /*!< [31..0] V limiter y-axis increment integer part */ + } LVYADDI_b; + }; + + union + { + __OM uint32_t LVYXADDF; /*!< (@ 0x000000AC) V Limiter Increment Fractional Parts Register */ + + struct + { + __OM uint32_t LVXADDF : 16; /*!< [15..0] V xlimiter increment fractional part */ + __OM uint32_t LVYADDF : 16; /*!< [31..16] V y limiter increment fractional part */ + } LVYXADDF_b; + }; + __IM uint32_t RESERVED4; + + union + { + __OM uint32_t TEXPITCH; /*!< (@ 0x000000B4) Texels Per Texture Line Register */ + + struct + { + __OM uint32_t TEXPITCH : 32; /*!< [31..0] Texels per texture linevalid range: 0 to 2048 */ + } TEXPITCH_b; + }; + + union + { + __OM uint32_t TEXMASK; /*!< (@ 0x000000B8) Texture Size or Texture Address Mask Register */ + + struct + { + __OM uint32_t TEXUMASK : 11; /*!< [10..0] U maskSet TEXUMASK[10:0] = texture_width -1In texture + * wrapping mode (CONTROL2.TEXTURECLAMPX = 0): texture_width + * must be a power of 2.In texture clamping mode (CONTROL2.TEXTURECLAMPX + * = 1):all widths up to 2048 are allowed. */ + __OM uint32_t TEXVMASK : 21; /*!< [31..11] V maskSet TEXVMASK[20:0] = TEXPITCH * (texture_height + * - 1).In texture wrapping mode (CONTROL2.TEXTURECLAMPY = + * 0): texture_height must be a power of 2In texture clamping + * mode (CONTROL2.TEXTURECLAMPY = 1):all heights up to 1024 + * are allowed. */ + } TEXMASK_b; + }; + + union + { + __OM uint32_t TEXORIGIN; /*!< (@ 0x000000BC) Texture Base Address Register */ + + struct + { + __OM uint32_t TEXORIGIN : 32; /*!< [31..0] Texture base address */ + } TEXORIGIN_b; + }; + + union + { + __OM uint32_t IRQCTL; /*!< (@ 0x000000C0) Interrupt Control Register */ + + struct + { + __OM uint32_t ENUMIRQEN : 1; /*!< [0..0] ENUMIRQ interrupt mask enable */ + __OM uint32_t DLISTIRQEN : 1; /*!< [1..1] DLISTIRQ interrupt mask enable */ + __OM uint32_t ENUMIRQCLR : 1; /*!< [2..2] Clear enumeration interrupt ENUMIRQ */ + __OM uint32_t DLISTIRQCLR : 1; /*!< [3..3] Clear display list interrupt DLISTIRQ */ + __OM uint32_t BUSIRQEN : 1; /*!< [4..4] BUSIRQ interrupt mask enable */ + __OM uint32_t BUSIRQCLR : 1; /*!< [5..5] Clear bus error interrupt BUSIRQ */ + uint32_t : 26; + } IRQCTL_b; + }; + + union + { + __OM uint32_t CACHECTL; /*!< (@ 0x000000C4) Cache Control Register */ + + struct + { + __OM uint32_t CENABLEFX : 1; /*!< [0..0] Framebuffer cache enable */ + __OM uint32_t CFLUSHFX : 1; /*!< [1..1] Flush framebuffer cache */ + __OM uint32_t CENABLETX : 1; /*!< [2..2] Texture cache enable */ + __OM uint32_t CFLUSHTX : 1; /*!< [3..3] Flush texture cache */ + uint32_t : 28; + } CACHECTL_b; + }; + + union + { + __OM uint32_t DLISTSTART; /*!< (@ 0x000000C8) Display List Start Address Register */ + + struct + { + __OM uint32_t DLISTSTART : 32; /*!< [31..0] Display list start address */ + } DLISTSTART_b; + }; + + union + { + __IOM uint32_t PERFCOUNT1; /*!< (@ 0x000000CC) Performance Counter 1 */ + + struct + { + __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT + * = 0000 0000H. */ + } PERFCOUNT1_b; + }; + + union + { + __IOM uint32_t PERFCOUNT2; /*!< (@ 0x000000D0) Performance Counter 2 */ + + struct + { + __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT + * = 0000 0000H. */ + } PERFCOUNT2_b; + }; + + union + { + __OM uint32_t PERFTRIGGER; /*!< (@ 0x000000D4) Performance Counters Control Register */ + + struct + { + __OM uint32_t PERFTRIGGER1 : 16; /*!< [15..0] Selects the internal event that will increment PERFCOUNT1 + * register. */ + __OM uint32_t PERFTRIGGER2 : 16; /*!< [31..16] Selects the internal event that will increment PERFCOUNT2 + * register */ + } PERFTRIGGER_b; + }; + __IM uint32_t RESERVED5; + + union + { + __OM uint32_t TEXCLADDR; /*!< (@ 0x000000DC) CLUT Start Address Register */ + + struct + { + __OM uint32_t CLADDR : 8; /*!< [7..0] Texture CLUT start address for indexed texture format */ + uint32_t : 24; + } TEXCLADDR_b; + }; + + union + { + __OM uint32_t TEXCLDATA; /*!< (@ 0x000000E0) CLUT Data Register */ + + struct + { + __OM uint32_t CLDATA : 32; /*!< [31..0] Texture CLUT data for Indexed texture format */ + } TEXCLDATA_b; + }; + + union + { + __OM uint32_t TEXCLOFFSET; /*!< (@ 0x000000E4) CLUT Offset Register */ + + struct + { + __OM uint32_t CLOFFSET : 8; /*!< [7..0] Texture CLUT offset for Indexed texture format. CLOFFSET[7:0] + * is or'ed with the original index */ + uint32_t : 24; + } TEXCLOFFSET_b; + }; + + union + { + __OM uint32_t COLKEY; /*!< (@ 0x000000E8) Color Key Register */ + + struct + { + __OM uint32_t COLKEYB : 8; /*!< [7..0] Blue channel of color key */ + __OM uint32_t COLKEYG : 8; /*!< [15..8] Green channel of color key */ + __OM uint32_t COLKEYR : 8; /*!< [23..16] Red channel of color key */ + uint32_t : 8; + } COLKEY_b; + }; + __IM uint32_t RESERVED6[5]; + + union + { + __IOM uint32_t DBWER; /*!< (@ 0x00000100) DRW Bufferable Write Enable Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t BWE : 1; /*!< [2..2] Bufferable Write Enable */ + uint32_t : 29; + } DBWER_b; + }; +} R_DRW_Type; /*!< Size = 260 (0x104) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ + +typedef struct /*!< (@ 0x4000AC00) R_DTC Structure */ +{ + union + { + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_b; + }; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + + struct + { + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + + struct + { + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; + }; + + union + { + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_SEC_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + + struct + { + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; + }; + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Event Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x40201000) R_ELC Structure */ +{ + union + { + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IOM R_ELC_ELSEGR_Type ELSEGR[4]; /*!< (@ 0x00000004) Event Link Software Event Generation Register */ + __IM uint32_t RESERVED2[3]; + __IOM R_ELC_ELSR_Type ELSR[53]; /*!< (@ 0x00000020) Event Link Setting Register [0..52] */ + __IM uint32_t RESERVED3[3]; + + union + { + __IOM uint32_t ELCSARA; /*!< (@ 0x00000100) Event Link Controller Security Attribution Register + * A */ + + struct + { + __IOM uint32_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint32_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint32_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1 Security + * Attribution */ + __IOM uint32_t ELSEGR2 : 1; /*!< [3..3] Event Link Software Event Generation Register 2 Security + * Attribution */ + __IOM uint32_t ELSEGR3 : 1; /*!< [4..4] Event Link Software Event Generation Register 3 Security + * Attribution */ + uint32_t : 27; + } ELCSARA_b; + }; + + union + { + __IOM uint32_t ELCSARB; /*!< (@ 0x00000104) Event Link Controller Security Attribution Register + * B */ + + struct + { + __IOM uint32_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0 Security Attribution */ + __IOM uint32_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1 Security Attribution */ + __IOM uint32_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2 Security Attribution */ + __IOM uint32_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3 Security Attribution */ + __IOM uint32_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4 Security Attribution */ + __IOM uint32_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5 Security Attribution */ + __IOM uint32_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6 Security Attribution */ + __IOM uint32_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7 Security Attribution */ + __IOM uint32_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8 Security Attribution */ + __IOM uint32_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9 Security Attribution */ + __IOM uint32_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10 Security Attribution */ + __IOM uint32_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11 Security Attribution */ + __IOM uint32_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12 Security Attribution */ + __IOM uint32_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13 Security Attribution */ + __IOM uint32_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14 Security Attribution */ + __IOM uint32_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15 Security Attribution */ + __IOM uint32_t ELSR16 : 1; /*!< [16..16] Event Link Setting Register 16 Security Attribution */ + __IOM uint32_t ELSR17 : 1; /*!< [17..17] Event Link Setting Register 17 Security Attribution */ + __IOM uint32_t ELSR18 : 1; /*!< [18..18] Event Link Setting Register 18 Security Attribution */ + __IOM uint32_t ELSR19 : 1; /*!< [19..19] Event Link Setting Register 19 Security Attribution */ + __IOM uint32_t ELSR20 : 1; /*!< [20..20] Event Link Setting Register 20 Security Attribution */ + __IOM uint32_t ELSR21 : 1; /*!< [21..21] Event Link Setting Register 21 Security Attribution */ + __IOM uint32_t ELSR22 : 1; /*!< [22..22] Event Link Setting Register 22 Security Attribution */ + __IOM uint32_t ELSR23 : 1; /*!< [23..23] Event Link Setting Register 23 Security Attribution */ + __IOM uint32_t ELSR24 : 1; /*!< [24..24] Event Link Setting Register 24 Security Attribution */ + __IOM uint32_t ELSR25 : 1; /*!< [25..25] Event Link Setting Register 25 Security Attribution */ + __IOM uint32_t ELSR26 : 1; /*!< [26..26] Event Link Setting Register 26 Security Attribution */ + __IOM uint32_t ELSR27 : 1; /*!< [27..27] Event Link Setting Register 27 Security Attribution */ + __IOM uint32_t ELSR28 : 1; /*!< [28..28] Event Link Setting Register 28 Security Attribution */ + __IOM uint32_t ELSR29 : 1; /*!< [29..29] Event Link Setting Register 29 Security Attribution */ + __IOM uint32_t ELSR30 : 1; /*!< [30..30] Event Link Setting Register 30 Security Attribution */ + __IOM uint32_t ELSR31 : 1; /*!< [31..31] Event Link Setting Register 31 Security Attribution */ + } ELCSARB_b; + }; + + union + { + __IOM uint32_t ELCSARC; /*!< (@ 0x00000108) Event Link Controller Security Attribution Register + * C */ + + struct + { + __IOM uint32_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0 Security Attribution */ + __IOM uint32_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1 Security Attribution */ + __IOM uint32_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2 Security Attribution */ + __IOM uint32_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3 Security Attribution */ + __IOM uint32_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4 Security Attribution */ + __IOM uint32_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5 Security Attribution */ + __IOM uint32_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6 Security Attribution */ + __IOM uint32_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7 Security Attribution */ + __IOM uint32_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8 Security Attribution */ + __IOM uint32_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9 Security Attribution */ + __IOM uint32_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10 Security Attribution */ + __IOM uint32_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11 Security Attribution */ + __IOM uint32_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12 Security Attribution */ + __IOM uint32_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13 Security Attribution */ + __IOM uint32_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14 Security Attribution */ + __IOM uint32_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15 Security Attribution */ + __IOM uint32_t ELSR16 : 1; /*!< [16..16] Event Link Setting Register 16 Security Attribution */ + __IOM uint32_t ELSR17 : 1; /*!< [17..17] Event Link Setting Register 17 Security Attribution */ + __IOM uint32_t ELSR18 : 1; /*!< [18..18] Event Link Setting Register 18 Security Attribution */ + __IOM uint32_t ELSR19 : 1; /*!< [19..19] Event Link Setting Register 19 Security Attribution */ + __IOM uint32_t ELSR20 : 1; /*!< [20..20] Event Link Setting Register 20 Security Attribution */ + __IOM uint32_t ELSR21 : 1; /*!< [21..21] Event Link Setting Register 21 Security Attribution */ + __IOM uint32_t ELSR22 : 1; /*!< [22..22] Event Link Setting Register 22 Security Attribution */ + __IOM uint32_t ELSR23 : 1; /*!< [23..23] Event Link Setting Register 23 Security Attribution */ + __IOM uint32_t ELSR24 : 1; /*!< [24..24] Event Link Setting Register 24 Security Attribution */ + __IOM uint32_t ELSR25 : 1; /*!< [25..25] Event Link Setting Register 25 Security Attribution */ + __IOM uint32_t ELSR26 : 1; /*!< [26..26] Event Link Setting Register 26 Security Attribution */ + __IOM uint32_t ELSR27 : 1; /*!< [27..27] Event Link Setting Register 27 Security Attribution */ + __IOM uint32_t ELSR28 : 1; /*!< [28..28] Event Link Setting Register 28 Security Attribution */ + __IOM uint32_t ELSR29 : 1; /*!< [29..29] Event Link Setting Register 29 Security Attribution */ + __IOM uint32_t ELSR30 : 1; /*!< [30..30] Event Link Setting Register 30 Security Attribution */ + __IOM uint32_t ELSR31 : 1; /*!< [31..31] Event Link Setting Register 31 Security Attribution */ + } ELCSARC_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t ELCPARA; /*!< (@ 0x00000110) Event Link Controller Privilege Attribution Register + * A */ + + struct + { + __IOM uint32_t ELCR : 1; /*!< [0..0] Event Link Controller Register Privilege Attribution */ + __IOM uint32_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Privilege + * Attribution */ + __IOM uint32_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1 Privilege + * Attribution */ + __IOM uint32_t ELSEGR2 : 1; /*!< [3..3] Event Link Software Event Generation Register 2 Privilege + * Attribution */ + __IOM uint32_t ELSEGR3 : 1; /*!< [4..4] Event Link Software Event Generation Register 3 Privilege + * Attribution */ + uint32_t : 27; + } ELCPARA_b; + }; + + union + { + __IOM uint32_t ELCPARB; /*!< (@ 0x00000114) Event Link Controller Privilege Attribution Register + * B */ + + struct + { + __IOM uint32_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0 Privilege Attribution */ + __IOM uint32_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1 Privilege Attribution */ + __IOM uint32_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2 Privilege Attribution */ + __IOM uint32_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3 Privilege Attribution */ + __IOM uint32_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4 Privilege Attribution */ + __IOM uint32_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5 Privilege Attribution */ + __IOM uint32_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6 Privilege Attribution */ + __IOM uint32_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7 Privilege Attribution */ + __IOM uint32_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8 Privilege Attribution */ + __IOM uint32_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9 Privilege Attribution */ + __IOM uint32_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10 Privilege Attribution */ + __IOM uint32_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11 Privilege Attribution */ + __IOM uint32_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12 Privilege Attribution */ + __IOM uint32_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13 Privilege Attribution */ + __IOM uint32_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14 Privilege Attribution */ + __IOM uint32_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15 Privilege Attribution */ + __IOM uint32_t ELSR16 : 1; /*!< [16..16] Event Link Setting Register 16 Privilege Attribution */ + __IOM uint32_t ELSR17 : 1; /*!< [17..17] Event Link Setting Register 17 Privilege Attribution */ + __IOM uint32_t ELSR18 : 1; /*!< [18..18] Event Link Setting Register 18 Privilege Attribution */ + __IOM uint32_t ELSR19 : 1; /*!< [19..19] Event Link Setting Register 19 Privilege Attribution */ + __IOM uint32_t ELSR20 : 1; /*!< [20..20] Event Link Setting Register 20 Privilege Attribution */ + __IOM uint32_t ELSR21 : 1; /*!< [21..21] Event Link Setting Register 21 Privilege Attribution */ + __IOM uint32_t ELSR22 : 1; /*!< [22..22] Event Link Setting Register 22 Privilege Attribution */ + __IOM uint32_t ELSR23 : 1; /*!< [23..23] Event Link Setting Register 23 Privilege Attribution */ + __IOM uint32_t ELSR24 : 1; /*!< [24..24] Event Link Setting Register 24 Privilege Attribution */ + __IOM uint32_t ELSR25 : 1; /*!< [25..25] Event Link Setting Register 25 Privilege Attribution */ + __IOM uint32_t ELSR26 : 1; /*!< [26..26] Event Link Setting Register 26 Privilege Attribution */ + __IOM uint32_t ELSR27 : 1; /*!< [27..27] Event Link Setting Register 27 Privilege Attribution */ + __IOM uint32_t ELSR28 : 1; /*!< [28..28] Event Link Setting Register 28 Privilege Attribution */ + __IOM uint32_t ELSR29 : 1; /*!< [29..29] Event Link Setting Register 29 Privilege Attribution */ + __IOM uint32_t ELSR30 : 1; /*!< [30..30] Event Link Setting Register 30 Privilege Attribution */ + __IOM uint32_t ELSR31 : 1; /*!< [31..31] Event Link Setting Register 31 Privilege Attribution */ + } ELCPARB_b; + }; + + union + { + __IOM uint32_t ELCPARC; /*!< (@ 0x00000118) Event Link Controller Privilege Attribution Register + * C */ + + struct + { + __IOM uint32_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0 Privilege Attribution */ + __IOM uint32_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1 Privilege Attribution */ + __IOM uint32_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2 Privilege Attribution */ + __IOM uint32_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3 Privilege Attribution */ + __IOM uint32_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4 Privilege Attribution */ + __IOM uint32_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5 Privilege Attribution */ + __IOM uint32_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6 Privilege Attribution */ + __IOM uint32_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7 Privilege Attribution */ + __IOM uint32_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8 Privilege Attribution */ + __IOM uint32_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9 Privilege Attribution */ + __IOM uint32_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10 Privilege Attribution */ + __IOM uint32_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11 Privilege Attribution */ + __IOM uint32_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12 Privilege Attribution */ + __IOM uint32_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13 Privilege Attribution */ + __IOM uint32_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14 Privilege Attribution */ + __IOM uint32_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15 Privilege Attribution */ + __IOM uint32_t ELSR16 : 1; /*!< [16..16] Event Link Setting Register 16 Privilege Attribution */ + __IOM uint32_t ELSR17 : 1; /*!< [17..17] Event Link Setting Register 17 Privilege Attribution */ + __IOM uint32_t ELSR18 : 1; /*!< [18..18] Event Link Setting Register 18 Privilege Attribution */ + __IOM uint32_t ELSR19 : 1; /*!< [19..19] Event Link Setting Register 19 Privilege Attribution */ + __IOM uint32_t ELSR20 : 1; /*!< [20..20] Event Link Setting Register 20 Privilege Attribution */ + __IOM uint32_t ELSR21 : 1; /*!< [21..21] Event Link Setting Register 21 Privilege Attribution */ + __IOM uint32_t ELSR22 : 1; /*!< [22..22] Event Link Setting Register 22 Privilege Attribution */ + __IOM uint32_t ELSR23 : 1; /*!< [23..23] Event Link Setting Register 23 Privilege Attribution */ + __IOM uint32_t ELSR24 : 1; /*!< [24..24] Event Link Setting Register 24 Privilege Attribution */ + __IOM uint32_t ELSR25 : 1; /*!< [25..25] Event Link Setting Register 25 Privilege Attribution */ + __IOM uint32_t ELSR26 : 1; /*!< [26..26] Event Link Setting Register 26 Privilege Attribution */ + __IOM uint32_t ELSR27 : 1; /*!< [27..27] Event Link Setting Register 27 Privilege Attribution */ + __IOM uint32_t ELSR28 : 1; /*!< [28..28] Event Link Setting Register 28 Privilege Attribution */ + __IOM uint32_t ELSR29 : 1; /*!< [29..29] Event Link Setting Register 29 Privilege Attribution */ + __IOM uint32_t ELSR30 : 1; /*!< [30..30] Event Link Setting Register 30 Privilege Attribution */ + __IOM uint32_t ELSR31 : 1; /*!< [31..31] Event Link Setting Register 31 Privilege Attribution */ + } ELCPARC_b; + }; +} R_ELC_Type; /*!< Size = 284 (0x11c) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EDMAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet DMA Controller (R_ETHERC_EDMAC) + */ + +typedef struct /*!< (@ 0x40354000) R_ETHERC_EDMAC Structure */ +{ + union + { + __IOM uint32_t EDMR; /*!< (@ 0x00000000) EDMAC Mode Register */ + + struct + { + __OM uint32_t SWR : 1; /*!< [0..0] Software Reset */ + uint32_t : 3; + __IOM uint32_t DL : 2; /*!< [5..4] Transmit/Receive DescriptorLength */ + __IOM uint32_t DE : 1; /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting + * applies to data for the transmit/receive buffer. It does + * not apply to transmit/receive descriptors and registers. */ + uint32_t : 25; + } EDMR_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t EDTRR; /*!< (@ 0x00000008) EDMAC Transmit Request Register */ + + struct + { + __OM uint32_t TR : 1; /*!< [0..0] Transmit Request */ + uint32_t : 31; + } EDTRR_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t EDRRR; /*!< (@ 0x00000010) EDMAC Receive Request Register */ + + struct + { + __IOM uint32_t RR : 1; /*!< [0..0] Receive Request */ + uint32_t : 31; + } EDRRR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t TDLAR; /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register */ + + struct + { + __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } TDLAR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t RDLAR; /*!< (@ 0x00000020) Receive Descriptor List Start Address Register */ + + struct + { + __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } RDLAR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t EESR; /*!< (@ 0x00000028) ETHERC/EDMAC Status Register */ + + struct + { + __IOM uint32_t CERF : 1; /*!< [0..0] CRC Error Flag */ + __IOM uint32_t PRE : 1; /*!< [1..1] PHY-LSI Receive Error Flag */ + __IOM uint32_t RTSF : 1; /*!< [2..2] Frame-Too-Short Error Flag */ + __IOM uint32_t RTLF : 1; /*!< [3..3] Frame-Too-Long Error Flag */ + __IOM uint32_t RRF : 1; /*!< [4..4] Alignment Error Flag */ + uint32_t : 2; + __IOM uint32_t RMAF : 1; /*!< [7..7] Multicast Address Frame Receive Flag */ + __IOM uint32_t TRO : 1; /*!< [8..8] Transmit Retry Over Flag */ + __IOM uint32_t CD : 1; /*!< [9..9] Late Collision Detect Flag */ + __IOM uint32_t DLC : 1; /*!< [10..10] Loss of Carrier Detect Flag */ + __IOM uint32_t CND : 1; /*!< [11..11] Carrier Not Detect Flag */ + uint32_t : 4; + __IOM uint32_t RFOF : 1; /*!< [16..16] Receive FIFO Overflow Flag */ + __IOM uint32_t RDE : 1; /*!< [17..17] Receive Descriptor Empty Flag */ + __IOM uint32_t FR : 1; /*!< [18..18] Frame Receive Flag */ + __IOM uint32_t TFUF : 1; /*!< [19..19] Transmit FIFO Underflow Flag */ + __IOM uint32_t TDE : 1; /*!< [20..20] Transmit Descriptor Empty Flag */ + __IOM uint32_t TC : 1; /*!< [21..21] Frame Transfer Complete Flag */ + __IM uint32_t ECI : 1; /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source + * in the ETHERCn.ECSR register is cleared, the ECI flag is + * also cleared. */ + __IOM uint32_t ADE : 1; /*!< [23..23] Address Error Flag */ + __IOM uint32_t RFCOF : 1; /*!< [24..24] Receive Frame Counter Overflow Flag */ + __IOM uint32_t RABT : 1; /*!< [25..25] Receive Abort Detect Flag */ + __IOM uint32_t TABT : 1; /*!< [26..26] Transmit Abort Detect Flag */ + uint32_t : 3; + __IOM uint32_t TWB : 1; /*!< [30..30] Write-Back Complete Flag */ + uint32_t : 1; + } EESR_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t EESIPR; /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register */ + + struct + { + __IOM uint32_t CERFIP : 1; /*!< [0..0] CRC Error Interrupt Request Enable */ + __IOM uint32_t PREIP : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable */ + __IOM uint32_t RTSFIP : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable */ + __IOM uint32_t RTLFIP : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable */ + __IOM uint32_t RRFIP : 1; /*!< [4..4] Alignment Error Interrupt Request Enable */ + uint32_t : 2; + __IOM uint32_t RMAFIP : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable */ + __IOM uint32_t TROIP : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable */ + __IOM uint32_t CDIP : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable */ + __IOM uint32_t DLCIP : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable */ + __IOM uint32_t CNDIP : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable */ + uint32_t : 4; + __IOM uint32_t RFOFIP : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable */ + __IOM uint32_t RDEIP : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t FRIP : 1; /*!< [18..18] Frame Receive Interrupt Request Enable */ + __IOM uint32_t TFUFIP : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable */ + __IOM uint32_t TDEIP : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t TCIP : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable */ + __IOM uint32_t ECIIP : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable */ + __IOM uint32_t ADEIP : 1; /*!< [23..23] Address Error Interrupt Request Enable */ + __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable */ + __IOM uint32_t RABTIP : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable */ + __IOM uint32_t TABTIP : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable */ + uint32_t : 3; + __IOM uint32_t TWBIP : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable */ + uint32_t : 1; + } EESIPR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t TRSCER; /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable + * Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t RRFCE : 1; /*!< [4..4] RRF Flag Copy Enable */ + uint32_t : 2; + __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable */ + uint32_t : 24; + } TRSCER_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t RMFCR; /*!< (@ 0x00000040) Missed-Frame Counter Register */ + + struct + { + __IOM uint32_t MFC : 16; /*!< [15..0] Missed-Frame CounterThese bits indicate the number of + * frames that are discarded and not transferred to the receive + * buffer during reception. */ + uint32_t : 16; + } RMFCR_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t TFTR; /*!< (@ 0x00000048) Transmit FIFO Threshold Register */ + + struct + { + __IOM uint32_t TFT : 11; /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is + * the set value multiplied by 4. Example: 00Dh: 52 bytes + * 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes */ + uint32_t : 21; + } TFTR_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t FDR; /*!< (@ 0x00000050) Transmit FIFO Threshold Register */ + + struct + { + __IOM uint32_t RFD : 5; /*!< [4..0] Transmit FIFO Depth */ + uint32_t : 3; + __IOM uint32_t TFD : 5; /*!< [12..8] Receive FIFO Depth */ + uint32_t : 19; + } FDR_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t RMCR; /*!< (@ 0x00000058) Receive Method Control Register */ + + struct + { + __IOM uint32_t RNR : 1; /*!< [0..0] Receive Request Reset */ + uint32_t : 31; + } RMCR_b; + }; + __IM uint32_t RESERVED11[2]; + + union + { + __IOM uint32_t TFUCR; /*!< (@ 0x00000064) Transmit FIFO Underflow Counter */ + + struct + { + __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how + * many times the transmit FIFO has underflowed. The counter + * stops when the counter value reaches FFFFh. */ + uint32_t : 16; + } TFUCR_b; + }; + + union + { + __IOM uint32_t RFOCR; /*!< (@ 0x00000068) Receive FIFO Overflow Counter */ + + struct + { + __IOM uint32_t OVER : 16; /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many + * times the receive FIFO has overflowed. The counter stops + * when the counter value reaches FFFFh. */ + uint32_t : 16; + } RFOCR_b; + }; + + union + { + __IOM uint32_t IOSR; /*!< (@ 0x0000006C) Independent Output Signal Setting Register */ + + struct + { + __IOM uint32_t ELB : 1; /*!< [0..0] External Loopback Mode */ + uint32_t : 31; + } IOSR_b; + }; + + union + { + __IOM uint32_t FCFTR; /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register */ + + struct + { + __IOM uint32_t RFDO : 3; /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 + * bytes of data is stored in the receive FIFO.) */ + uint32_t : 13; + __IOM uint32_t RFFO : 3; /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) + * receive frames have been stored in the receive FIFO.) */ + uint32_t : 13; + } FCFTR_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t RPADIR; /*!< (@ 0x00000078) Receive Data Padding Insert Register */ + + struct + { + __IOM uint32_t PADR : 6; /*!< [5..0] Padding Slot */ + uint32_t : 10; + __IOM uint32_t PADS : 2; /*!< [17..16] Padding Size */ + uint32_t : 14; + } RPADIR_b; + }; + + union + { + __IOM uint32_t TRIMD; /*!< (@ 0x0000007C) Transmit Interrupt Setting Register */ + + struct + { + __IOM uint32_t TIS : 1; /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in + * the mode selected by the TIM bit to notify an interrupt. */ + uint32_t : 3; + __IOM uint32_t TIM : 1; /*!< [4..4] Transmit Interrupt Mode */ + uint32_t : 27; + } TRIMD_b; + }; + __IM uint32_t RESERVED13[18]; + + union + { + __IOM uint32_t RBWAR; /*!< (@ 0x000000C8) Receive Buffer Write Address Register */ + + struct + { + __IM uint32_t RBWAR : 32; /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register + * indicates the last address that the EDMAC has written data + * to when writing to the receive buffer.Refer to the address + * indicated by the RBWAR register to recognize which address + * in the receive buffer the EDMAC is writing data to. Note + * that the address that the EDMAC is outputting to the receive + * buffer may not match the read value of the RBWAR register + * during data reception. */ + } RBWAR_b; + }; + + union + { + __IOM uint32_t RDFAR; /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register */ + + struct + { + __IM uint32_t RDFAR : 32; /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register + * indicates the start address of the last fetched receive + * descriptor when the EDMAC fetches descriptor information + * from the receive descriptor.Refer to the address indicated + * by the RDFAR register to recognize which receive descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the receive descriptor that the + * EDMAC fetches may not match the read value of the RDFAR + * register during data reception. */ + } RDFAR_b; + }; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t TBRAR; /*!< (@ 0x000000D4) Transmit Buffer Read Address Register */ + + struct + { + __IM uint32_t TBRAR : 32; /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register + * indicates the last address that the EDMAC has read data + * from when reading data from the transmit buffer.Refer to + * the address indicated by the TBRAR register to recognize + * which address in the transmit buffer the EDMAC is reading + * from. Note that the address that the EDMAC is outputting + * to the transmit buffer may not match the read value of + * the TBRAR register. */ + } TBRAR_b; + }; + + union + { + __IM uint32_t TDFAR; /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register */ + + struct + { + __IM uint32_t TDFAR : 32; /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR + * register indicates the start address of the last fetched + * transmit descriptor when the EDMAC fetches descriptor information + * from the transmit descriptor.Refer to the address indicated + * by the TDFAR register to recognize which transmit descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the transmit descriptor that the + * EDMAC fetches may not match the read value of the TDFAR + * register. */ + } TDFAR_b; + }; +} R_ETHERC_EDMAC_Type; /*!< Size = 220 (0xdc) */ + +/* =========================================================================================================================== */ +/* ================ R_GLCDC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Graphics LCD Controller (R_GLCDC) + */ + +typedef struct /*!< (@ 0x40342000) R_GLCDC Structure */ +{ + union + { + __IOM uint32_t GR1_CLUT0[256]; /*!< (@ 0x00000000) Color Palette 0 Plane for Graphics 1 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR1_CLUT0_b[256]; + }; + + union + { + __IOM uint32_t GR1_CLUT1[256]; /*!< (@ 0x00000400) Color Palette 1 Plane for Graphics 1 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR1_CLUT1_b[256]; + }; + + union + { + __IOM uint32_t GR2_CLUT0[256]; /*!< (@ 0x00000800) Color Palette 0 Plane for Graphics 2 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR2_CLUT0_b[256]; + }; + + union + { + __IOM uint32_t GR2_CLUT1[256]; /*!< (@ 0x00000C00) Color Palette 1 Plane for Graphics 2 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR2_CLUT1_b[256]; + }; + __IOM R_GLCDC_BG_Type BG; /*!< (@ 0x00001000) Background Registers */ + __IM uint32_t RESERVED[57]; + __IOM R_GLCDC_GR_Type GR[2]; /*!< (@ 0x00001100) Layer Registers */ + __IOM R_GLCDC_GAM_Type GAM[3]; /*!< (@ 0x00001300) Gamma Settings */ + __IOM R_GLCDC_OUT_Type OUT; /*!< (@ 0x000013C0) Output Control Registers */ + __IM uint32_t RESERVED1[6]; + __IOM R_GLCDC_TCON_Type TCON; /*!< (@ 0x00001400) Timing Control Registers */ + __IM uint32_t RESERVED2[5]; + __IOM R_GLCDC_SYSCNT_Type SYSCNT; /*!< (@ 0x00001440) GLCDC System Control Registers */ +} R_GLCDC_Type; /*!< Size = 5204 (0x1454) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40322000) R_GPT0 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + __OM uint32_t CCLR14 : 1; /*!< [14..14] Channel GTCNT Count Clear */ + __OM uint32_t CCLR15 : 1; /*!< [15..15] Channel GTCNT Count Clear */ + __OM uint32_t CCLR16 : 1; /*!< [16..16] Channel GTCNT Count Clear */ + __OM uint32_t CCLR17 : 1; /*!< [17..17] Channel GTCNT Count Clear */ + __OM uint32_t CCLR18 : 1; /*!< [18..18] Channel GTCNT Count Clear */ + __OM uint32_t CCLR19 : 1; /*!< [19..19] Channel GTCNT Count Clear */ + __OM uint32_t CCLR20 : 1; /*!< [20..20] Channel GTCNT Count Clear */ + __OM uint32_t CCLR21 : 1; /*!< [21..21] Channel GTCNT Count Clear */ + __OM uint32_t CCLR22 : 1; /*!< [22..22] Channel GTCNT Count Clear */ + __OM uint32_t CCLR23 : 1; /*!< [23..23] Channel GTCNT Count Clear */ + __OM uint32_t CCLR24 : 1; /*!< [24..24] Channel GTCNT Count Clear */ + __OM uint32_t CCLR25 : 1; /*!< [25..25] Channel GTCNT Count Clear */ + __OM uint32_t CCLR26 : 1; /*!< [26..26] Channel GTCNT Count Clear */ + __OM uint32_t CCLR27 : 1; /*!< [27..27] Channel GTCNT Count Clear */ + __OM uint32_t CCLR28 : 1; /*!< [28..28] Channel GTCNT Count Clear */ + __OM uint32_t CCLR29 : 1; /*!< [29..29] Channel GTCNT Count Clear */ + __OM uint32_t CCLR30 : 1; /*!< [30..30] Channel GTCNT Count Clear */ + __OM uint32_t CCLR31 : 1; /*!< [31..31] Channel GTCNT Count Clear */ + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; + __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ + __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ + __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ + __IOM uint32_t CPSCD : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable */ + uint32_t : 2; + __IOM uint32_t SSCEN : 1; /*!< [15..15] Synchronous Set/Clear Enable */ + __IOM uint32_t MD : 4; /*!< [19..16] Mode Select */ + uint32_t : 3; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + __IOM uint32_t CKEG : 2; /*!< [28..27] Clock Edge Select */ + uint32_t : 3; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + uint32_t : 1; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + * Clear Enable */ + __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous + * Clear Enable */ + __IOM uint32_t SCFC : 1; /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFD : 1; /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFE : 1; /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFF : 1; /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFPO : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable */ + __IOM uint32_t SCFPU : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable */ + __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion + * Start Request Enable */ + __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D + * Conversion Start Request Enable */ + __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion + * Start Request Enable */ + __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D + * Conversion Start Request Enable */ + uint32_t : 4; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 4; + __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable */ + uint32_t : 1; + __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable */ + uint32_t : 5; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + + struct + { + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + + struct + { + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; + }; + + union + { + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + + struct + { + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + + struct + { + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + + struct + { + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + + struct + { + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ + + struct + { + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + + struct + { + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + + struct + { + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + struct + { + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + + struct + { + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + + struct + { + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + + union + { + __IOM uint32_t GTADSMR; /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request + * Signal Monitoring Register */ + + struct + { + __IOM uint32_t ADSMS0 : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output + * Enabling */ + uint32_t : 7; + __IOM uint32_t ADSMS1 : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output + * Enabling */ + uint32_t : 7; + } GTADSMR_b; + }; + + union + { + __IOM uint32_t GTEITC; /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping + * Counter Control Register */ + + struct + { + __IOM uint32_t EIVTC1 : 2; /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t EIVTT1 : 4; /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting */ + uint32_t : 4; + __IM uint32_t EITCNT1 : 4; /*!< [15..12] Extended Interrupt Skipping Counter 1 */ + __IOM uint32_t EIVTC2 : 2; /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source + * select */ + uint32_t : 2; + __IOM uint32_t EIVTT2 : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting */ + __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value */ + __IM uint32_t EITCNT2 : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2 */ + } GTEITC_b; + }; + + union + { + __IOM uint32_t GTEITLI1; /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping + * Setting Register 1 */ + + struct + { + __IOM uint32_t EITLA : 3; /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLB : 3; /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLC : 3; /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLD : 3; /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLE : 3; /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLF : 3; /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLV : 3; /*!< [26..24] Overflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLU : 3; /*!< [30..28] Underflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + } GTEITLI1_b; + }; + + union + { + __IOM uint32_t GTEITLI2; /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping + * Setting Register 2 */ + + struct + { + __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended + * Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended + * Skipping Function Select */ + uint32_t : 25; + } GTEITLI2_b; + }; + + union + { + __IOM uint32_t GTEITLB; /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping + * Setting Register */ + + struct + { + __IOM uint32_t EBTLCA : 3; /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLCB : 3; /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLPR : 3; /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 5; + __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + } GTEITLB_b; + }; + + union + { + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ + + struct + { + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; + }; + + union + { + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + + struct + { + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; + }; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDAE : 1; /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDDE : 1; /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable */ + uint32_t : 4; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDAD : 1; /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDDD : 1; /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable */ + uint32_t : 4; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + __IOM uint32_t SSCE : 1; /*!< [17..17] Synchronous Set/Clear Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + __IOM uint32_t SSCD : 1; /*!< [25..25] Synchronous Set/Clear Simultaneous Disable */ + uint32_t : 6; + } GTSECR_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t GTBER2; /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2 */ + + struct + { + __IOM uint32_t CCTCA : 1; /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTCB : 1; /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTPR : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable */ + __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTDV : 1; /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer + * Disable */ + uint32_t : 2; + __IOM uint32_t CMTCA : 2; /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer + * Enable */ + __IOM uint32_t CMTCB : 2; /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer + * Enable */ + uint32_t : 1; + __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer + * Enable */ + __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer + * Enable */ + uint32_t : 1; + __IOM uint32_t CPTCA : 1; /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTCB : 1; /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTPR : 1; /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTDV : 1; /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer + * Transfer Disable */ + uint32_t : 2; + __IOM uint32_t CP3DB : 1; /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select */ + __IOM uint32_t CPBTD : 1; /*!< [25..25] Complementary PWM mode Buffer Transfer Disable */ + __IOM uint32_t OLTTA : 2; /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select */ + __IOM uint32_t OLTTB : 2; /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select */ + uint32_t : 2; + } GTBER2_b; + }; + + union + { + __IOM uint32_t GTOLBR; /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register */ + + struct + { + __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits */ + uint32_t : 11; + __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits */ + uint32_t : 11; + } GTOLBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t GTICCR; /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input + * Capture Control Register */ + + struct + { + __IOM uint32_t ICAFA : 1; /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture + * to Other Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFB : 1; /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture + * to Other Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFC : 1; /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFD : 1; /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFE : 1; /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFF : 1; /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture + * Source Enable */ + __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture + * Source Enable */ + __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input + * Capture Source Enable */ + uint32_t : 5; + __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select */ + __IOM uint32_t ICBFA : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture + * to Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFB : 1; /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture + * to Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFC : 1; /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFD : 1; /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFE : 1; /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to + * Other Channel GTCCRb Input Capture Source Enable */ + __IOM uint32_t ICBFF : 1; /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture + * Source Enable */ + __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input + * Capture Source Enable */ + __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input + * Capture Source Enable */ + uint32_t : 5; + __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select */ + } GTICCR_b; + }; +} R_GPT0_Type; /*!< Size = 240 (0xf0) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_GTCLK ================ */ +/* =========================================================================================================================== */ + +/** + * @brief GTCLK (R_GPT_GTCLK) + */ + +typedef struct /*!< (@ 0x40323F10) R_GPT_GTCLK Structure */ +{ + union + { + __IOM uint32_t GTCLKCR; /*!< (@ 0x00000000) General PWM Timer Clock Control Register */ + + struct + { + __IOM uint32_t BPEN : 1; /*!< [0..0] Synchronization Circuit Bypass Enable */ + uint32_t : 31; + } GTCLKCR_b; + }; +} R_GPT_GTCLK_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_ODC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief PWM Delay Generation Circuit (R_GPT_ODC) + */ + +typedef struct /*!< (@ 0x40324000) R_GPT_ODC Structure */ +{ + union + { + __IOM uint16_t GTDLYCR1; /*!< (@ 0x00000000) PWM Output Delay Control Register1 */ + + struct + { + __IOM uint16_t DLLEN : 1; /*!< [0..0] DLL Operation Enable */ + __IOM uint16_t DLYRST : 1; /*!< [1..1] PWM Delay Generation Circuit Reset */ + uint16_t : 6; + __IOM uint16_t FRANGE : 2; /*!< [9..8] GPT core clock Frequency Range */ + uint16_t : 6; + } GTDLYCR1_b; + }; + + union + { + __IOM uint16_t GTDLYCR2; /*!< (@ 0x00000002) PWM Output Delay Control Register2 */ + + struct + { + __IOM uint16_t DLYBS0 : 1; /*!< [0..0] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS1 : 1; /*!< [1..1] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS2 : 1; /*!< [2..2] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS3 : 1; /*!< [3..3] PWM Delay Generation Circuit bypass */ + uint16_t : 4; + __IOM uint16_t DLYEN0 : 1; /*!< [8..8] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYEN1 : 1; /*!< [9..9] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYEN2 : 1; /*!< [10..10] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYEN3 : 1; /*!< [11..11] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYDENB0 : 1; /*!< [12..12] PWM Delay Generation Circuit Disenable for GTIOCB */ + uint16_t : 3; + } GTDLYCR2_b; + }; + __IM uint16_t RESERVED[10]; + __IOM R_GPT_ODC_GTDLYR_Type GTDLYR[4]; /*!< (@ 0x00000018) PWM DELAY RISING */ + __IOM R_GPT_ODC_GTDLYR_Type GTDLYF[4]; /*!< (@ 0x00000028) PWM DELAY FALLING */ +} R_GPT_ODC_Type; /*!< Size = 56 (0x38) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Output Phase Switching for GPT (R_GPT_OPS) + */ + +typedef struct /*!< (@ 0x40323F00) R_GPT_OPS Structure */ +{ + union + { + __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ + + struct + { + __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + uint32_t : 1; + __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ + uint32_t : 7; + __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the + * input phase from the software settings and external input. */ + __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ + __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ + __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ + __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ + __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ + uint32_t : 2; + __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ + __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ + uint32_t : 2; + __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter + * sampling clock setting of the external input. */ + } OPSCR_b; + }; +} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ + +typedef struct /*!< (@ 0x40212000) R_GPT_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; + }; + __IM uint32_t RESERVED[15]; + + union + { + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ + + struct + { + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ + + struct + { + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; + }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ + union + { + __IOM uint8_t IRQCRa[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCRa_b[16]; + }; + + union + { + __IM uint8_t NMICR; /*!< (@ 0x00000010) NMI Pin Interrupt Control Register */ + + struct + { + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint8_t IRQCRb[16]; /*!< (@ 0x00000014) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCRb_b[16]; + }; + __IM uint32_t RESERVED2[7]; + + union + { + __IOM uint32_t INTSELR[32]; /*!< (@ 0x00000040) Interrupt request select Register */ + + struct + { + __IOM uint32_t IS0 : 1; /*!< [0..0] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS1 : 1; /*!< [1..1] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS2 : 1; /*!< [2..2] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS3 : 1; /*!< [3..3] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS4 : 1; /*!< [4..4] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS5 : 1; /*!< [5..5] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS6 : 1; /*!< [6..6] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS7 : 1; /*!< [7..7] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS8 : 1; /*!< [8..8] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS9 : 1; /*!< [9..9] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS10 : 1; /*!< [10..10] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS11 : 1; /*!< [11..11] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS12 : 1; /*!< [12..12] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS13 : 1; /*!< [13..13] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS14 : 1; /*!< [14..14] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS15 : 1; /*!< [15..15] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS16 : 1; /*!< [16..16] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS17 : 1; /*!< [17..17] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS18 : 1; /*!< [18..18] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS19 : 1; /*!< [19..19] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS20 : 1; /*!< [20..20] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS21 : 1; /*!< [21..21] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS22 : 1; /*!< [22..22] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS23 : 1; /*!< [23..23] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS24 : 1; /*!< [24..24] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS25 : 1; /*!< [25..25] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS26 : 1; /*!< [26..26] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS27 : 1; /*!< [27..27] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS28 : 1; /*!< [28..28] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS29 : 1; /*!< [29..29] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS30 : 1; /*!< [30..30] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS31 : 1; /*!< [31..31] Selects which CPU receives interrupt requests */ + } INTSELR_b[32]; + }; + __IM uint32_t RESERVED3[6160]; + + union + { + __IOM uint32_t NMIER; /*!< (@ 0x00006100) Non-Maskable Interrupt Enable Register */ + + struct + { + __IOM uint32_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint32_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint32_t PVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint32_t PVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t SOSTEN : 1; /*!< [5..5] Sub Oscillation Stop Detection Interrupt Enable */ + __IOM uint32_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint32_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + uint32_t : 4; + __IOM uint32_t BUSEN : 1; /*!< [12..12] BUS error Interrupt Enable */ + __IOM uint32_t CMEN : 1; /*!< [13..13] Common Memory error Interrupt Enable */ + __IOM uint32_t LMEN : 1; /*!< [14..14] Local Memory Error Interrupt Enable */ + __IOM uint32_t LUEN : 1; /*!< [15..15] LockUp Interrupt Enable */ + __IOM uint32_t FPUFLTEN : 1; /*!< [16..16] FPU FAULT Interrupt Enable */ + __IOM uint32_t MRCRDEN : 1; /*!< [17..17] MRAM MRC read Error Interrupt Enable */ + __IOM uint32_t MRERDEN : 1; /*!< [18..18] MRAM MRE read Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t IPCEN : 1; /*!< [20..20] IPC NMI CPU mutual Interrupt Enable */ + uint32_t : 11; + } NMIER_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IOM uint32_t NMICLR; /*!< (@ 0x00006110) Non-Maskable Interrupt Status Clear Register */ + + struct + { + __IOM uint32_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __IOM uint32_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __IOM uint32_t PVD1CLR : 1; /*!< [2..2] PVD1 Clear */ + __IOM uint32_t PVD2CLR : 1; /*!< [3..3] PVD2 Clear */ + uint32_t : 1; + __IOM uint32_t SOSTCLR : 1; /*!< [5..5] Sub OST Clear */ + __IOM uint32_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __IOM uint32_t NMICLR : 1; /*!< [7..7] NMI Clear */ + uint32_t : 4; + __IOM uint32_t BUSCLR : 1; /*!< [12..12] Bus Clear */ + __IOM uint32_t CMCLR : 1; /*!< [13..13] CM Clear */ + __IOM uint32_t LMCLR : 1; /*!< [14..14] LM Clear */ + __IOM uint32_t LUCLR : 1; /*!< [15..15] LU Clear */ + __IOM uint32_t FPUFLTCLR : 1; /*!< [16..16] FPU FAULT Clear */ + __IOM uint32_t MRCRDCLR : 1; /*!< [17..17] MRAM MRC read Error Interrupt Clear */ + __IOM uint32_t MRERDCLR : 1; /*!< [18..18] MRAM MRE read Error Interrupt Clear */ + uint32_t : 1; + __IOM uint32_t IPCCLR : 1; /*!< [20..20] IPC NMI CPU mutual Interrupt Clear */ + uint32_t : 11; + } NMICLR_b; + }; + __IM uint32_t RESERVED5[3]; + + union + { + __IM uint32_t NMISR; /*!< (@ 0x00006120) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint32_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint32_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint32_t PVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint32_t PVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + uint32_t : 1; + __IM uint32_t SOSTST : 1; /*!< [5..5] Sub Oscillation Stop Detection Interrupt Status Flag */ + __IM uint32_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint32_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + uint32_t : 4; + __IM uint32_t BUSST : 1; /*!< [12..12] BUS error Interrupt Status Flag */ + __IM uint32_t CMST : 1; /*!< [13..13] Common Memory error Interrupt Status Flag */ + __IM uint32_t LMST : 1; /*!< [14..14] Local Memory Error Interrupt Status Flag */ + __IM uint32_t LUST : 1; /*!< [15..15] LockUp Interrupt Status Flag */ + __IM uint32_t FPUFLTST : 1; /*!< [16..16] FPU FAULT Interrupt Status Flag */ + __IM uint32_t MRCRDST : 1; /*!< [17..17] MRAM MRC read Error Interrupt Status Flag */ + __IM uint32_t MRERDST : 1; /*!< [18..18] MRAM MRE read Error Interrupt Status Flag */ + uint32_t : 1; + __IM uint32_t IPCST : 1; /*!< [20..20] IPC NMI CPU mutual Interrupt Status Flag */ + uint32_t : 11; + } NMISR_b; + }; + __IM uint32_t RESERVED6[31]; + + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000061A0) Wake Up Interrupt Enable Register 0 */ + + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ0 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ1 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ2 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ3 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ4 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ5 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ6 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ7 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ8 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ9 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ10 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ11 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ12 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ13 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ14 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ15 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t WUPEN0 : 1; /*!< [16..16] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 0 */ + __IOM uint32_t WUPEN1 : 1; /*!< [17..17] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 1 */ + __IOM uint32_t WUPEN2 : 1; /*!< [18..18] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 2 */ + __IOM uint32_t WUPEN3 : 1; /*!< [19..19] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 3 */ + __IOM uint32_t WUPEN4 : 1; /*!< [20..20] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 4 */ + __IOM uint32_t WUPEN5 : 1; /*!< [21..21] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 5 */ + __IOM uint32_t WUPEN6 : 1; /*!< [22..22] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 6 */ + __IOM uint32_t WUPEN7 : 1; /*!< [23..23] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 7 */ + __IOM uint32_t WUPEN8 : 1; /*!< [24..24] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 8 */ + __IOM uint32_t WUPEN9 : 1; /*!< [25..25] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 9 */ + __IOM uint32_t WUPEN10 : 1; /*!< [26..26] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 10 */ + __IOM uint32_t WUPEN11 : 1; /*!< [27..27] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 11 */ + __IOM uint32_t WUPEN12 : 1; /*!< [28..28] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 12 */ + __IOM uint32_t WUPEN13 : 1; /*!< [29..29] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 13 */ + __IOM uint32_t WUPEN14 : 1; /*!< [30..30] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 14 */ + __IOM uint32_t WUPEN15 : 1; /*!< [31..31] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 15 */ + } WUPEN_b; + }; + + union + { + __IOM uint32_t WUPEN1; /*!< (@ 0x000061A4) Wake Up Interrupt Enable Register 1 */ + + struct + { + __IOM uint32_t WUPEN16 : 1; /*!< [0..0] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 16 */ + __IOM uint32_t WUPEN17 : 1; /*!< [1..1] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 17 */ + __IOM uint32_t WUPEN18 : 1; /*!< [2..2] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 18 */ + __IOM uint32_t WUPEN19 : 1; /*!< [3..3] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 19 */ + __IOM uint32_t WUPEN20 : 1; /*!< [4..4] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 20 */ + __IOM uint32_t WUPEN21 : 1; /*!< [5..5] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 21 */ + __IOM uint32_t WUPEN22 : 1; /*!< [6..6] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 22 */ + __IOM uint32_t WUPEN23 : 1; /*!< [7..7] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 23 */ + __IOM uint32_t WUPEN24 : 1; /*!< [8..8] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 24 */ + __IOM uint32_t WUPEN25 : 1; /*!< [9..9] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 25 */ + __IOM uint32_t WUPEN26 : 1; /*!< [10..10] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 26 */ + __IOM uint32_t WUPEN27 : 1; /*!< [11..11] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 27 */ + __IOM uint32_t WUPEN28 : 1; /*!< [12..12] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 28 */ + __IOM uint32_t WUPEN29 : 1; /*!< [13..13] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 29 */ + __IOM uint32_t WUPEN30 : 1; /*!< [14..14] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 30 */ + __IOM uint32_t WUPEN31 : 1; /*!< [15..15] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 31 */ + __IOM uint32_t IRQWUPEN16 : 1; /*!< [16..16] IRQ16 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN17 : 1; /*!< [17..17] IRQ17 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN18 : 1; /*!< [18..18] IRQ18 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN19 : 1; /*!< [19..19] IRQ19 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN20 : 1; /*!< [20..20] IRQ20 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN21 : 1; /*!< [21..21] IRQ21 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN22 : 1; /*!< [22..22] IRQ22 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN23 : 1; /*!< [23..23] IRQ23 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN24 : 1; /*!< [24..24] IRQ24 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN25 : 1; /*!< [25..25] IRQ25 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN26 : 1; /*!< [26..26] IRQ26 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN27 : 1; /*!< [27..27] IRQ27 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN28 : 1; /*!< [28..28] IRQ28 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN29 : 1; /*!< [29..29] IRQ29 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN30 : 1; /*!< [30..30] IRQ30 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN31 : 1; /*!< [31..31] IRQ31 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + } WUPEN1_b; + }; + __IM uint32_t RESERVED7[26]; + + union + { + __IOM uint32_t DSLPWUPIRQEN[3]; /*!< (@ 0x00006210) Deep Sleep Wake Up IRQ Enable Register */ + + struct + { + __IOM uint32_t IRQ0 : 1; /*!< [0..0] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ1 : 1; /*!< [1..1] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ2 : 1; /*!< [2..2] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ3 : 1; /*!< [3..3] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ4 : 1; /*!< [4..4] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ5 : 1; /*!< [5..5] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ6 : 1; /*!< [6..6] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ7 : 1; /*!< [7..7] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ8 : 1; /*!< [8..8] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ9 : 1; /*!< [9..9] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ10 : 1; /*!< [10..10] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ11 : 1; /*!< [11..11] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ12 : 1; /*!< [12..12] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ13 : 1; /*!< [13..13] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ14 : 1; /*!< [14..14] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ15 : 1; /*!< [15..15] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ16 : 1; /*!< [16..16] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ17 : 1; /*!< [17..17] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ18 : 1; /*!< [18..18] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ19 : 1; /*!< [19..19] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ20 : 1; /*!< [20..20] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ21 : 1; /*!< [21..21] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ22 : 1; /*!< [22..22] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ23 : 1; /*!< [23..23] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ24 : 1; /*!< [24..24] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ25 : 1; /*!< [25..25] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ26 : 1; /*!< [26..26] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ27 : 1; /*!< [27..27] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ28 : 1; /*!< [28..28] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ29 : 1; /*!< [29..29] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ30 : 1; /*!< [30..30] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ31 : 1; /*!< [31..31] IRQ Deep Sleep Returns Enable bit */ + } DSLPWUPIRQEN_b[3]; + }; + __IM uint32_t RESERVED8[25]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00006280) DMAC Event Link Setting Registers */ + + struct + { + __IOM uint32_t DELS : 10; /*!< [9..0] DMAC Event Link Select */ + uint32_t : 6; + __IOM uint32_t IR : 1; /*!< [16..16] DMAC Activation Request Status Flag */ + uint32_t : 15; + } DELSR_b[8]; + }; + __IM uint32_t RESERVED9[24]; + + union + { + __IOM uint32_t IELSR[96]; /*!< (@ 0x00006300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 10; /*!< [9..0] ICU Event Link Select */ + uint32_t : 6; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; + }; +} R_ICU_Type; /*!< Size = 25728 (0x6480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ + +typedef struct /*!< (@ 0x4025E000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40202200) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t IWDTCR; /*!< (@ 0x00000002) IWDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } IWDTCR_b; + }; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; + + union + { + __IOM uint8_t IWDTRCR; /*!< (@ 0x00000006) IWDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } IWDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t IWDTCSTPR; /*!< (@ 0x00000008) IWDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } IWDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_IWDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_I3C0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I3C Bus Interface (R_I3C0) + */ + +typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure */ +{ + union + { + __IOM uint32_t PRTS; /*!< (@ 0x00000000) Protocol Selection Register */ + + struct + { + __IOM uint32_t PRTMD : 1; /*!< [0..0] Protocol Mode */ + uint32_t : 31; + } PRTS_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t CECTL; /*!< (@ 0x00000010) Clock Enable Control Resisters */ + + struct + { + __IOM uint32_t CLKE : 1; /*!< [0..0] Clock Enable */ + uint32_t : 31; + } CECTL_b; + }; + + union + { + __IOM uint32_t BCTL; /*!< (@ 0x00000014) Bus Control Register */ + + struct + { + __IOM uint32_t INCBA : 1; /*!< [0..0] Include I3C Broadcast Address */ + uint32_t : 6; + __IOM uint32_t BMDS : 1; /*!< [7..7] Bus Mode Selection */ + __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control */ + uint32_t : 20; + __IOM uint32_t ABT : 1; /*!< [29..29] Abort */ + __IOM uint32_t RSM : 1; /*!< [30..30] Resume */ + __IOM uint32_t BUSE : 1; /*!< [31..31] Bus Enable */ + } BCTL_b; + }; + + union + { + __IOM uint32_t MSDVAD; /*!< (@ 0x00000018) Master Device Address Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t MDYAD : 7; /*!< [22..16] Master Dynamic Address */ + uint32_t : 8; + __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid */ + } MSDVAD_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ + + struct + { + __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ + __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ + __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ + __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ + __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ + __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ + __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ + uint32_t : 2; + __IOM uint32_t HCMDQRST : 1; /*!< [9..9] High Priority Command Queue Software Reset */ + __IOM uint32_t HRSPQRST : 1; /*!< [10..10] High Priority Response Queue Software Rese */ + __IOM uint32_t HTDBRST : 1; /*!< [11..11] High Priority Tx Data Buffer Software Reset */ + __IOM uint32_t HRDBRST : 1; /*!< [12..12] High Priority Rx Data Buffer Software Reset */ + uint32_t : 3; + __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ + uint32_t : 15; + } RSTCTL_b; + }; + + union + { + __IOM uint32_t PRSST; /*!< (@ 0x00000024) Present State Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t CRMS : 1; /*!< [2..2] Current Master */ + uint32_t : 1; + __IM uint32_t TRMD : 1; /*!< [4..4] Transmit/Receive Mode */ + uint32_t : 2; + __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect */ + uint32_t : 24; + } PRSST_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t INST; /*!< (@ 0x00000030) Internal Status Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEF : 1; /*!< [10..10] Internal Error Flag */ + uint32_t : 21; + } INST_b; + }; + + union + { + __IOM uint32_t INSTE; /*!< (@ 0x00000034) Internal Status Enable Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEE : 1; /*!< [10..10] Internal Error Enable */ + uint32_t : 21; + } INSTE_b; + }; + + union + { + __IOM uint32_t INIE; /*!< (@ 0x00000038) Internal Interrupt Enable Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEIE : 1; /*!< [10..10] Internal Error Interrupt Enable */ + uint32_t : 21; + } INIE_b; + }; + + union + { + __IOM uint32_t INSTFC; /*!< (@ 0x0000003C) Internal Status Force Register */ + + struct + { + uint32_t : 10; + __OM uint32_t INEFC : 1; /*!< [10..10] Internal Error Force */ + uint32_t : 21; + } INSTFC_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IM uint32_t DVCT; /*!< (@ 0x00000044) Device Characteristic Table Register */ + + struct + { + uint32_t : 19; + __IM uint32_t IDX : 5; /*!< [23..19] DCT Table Index */ + uint32_t : 8; + } DVCT_b; + }; + __IM uint32_t RESERVED4[4]; + + union + { + __IOM uint32_t IBINCTL; /*!< (@ 0x00000058) IBI Notify Control Register */ + + struct + { + __IOM uint32_t NRHJCTL : 1; /*!< [0..0] Notify Rejected Hot-Join Control */ + __IOM uint32_t NRMRCTL : 1; /*!< [1..1] Notify Rejected Master Request Control */ + uint32_t : 1; + __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control */ + uint32_t : 28; + } IBINCTL_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t BFCTL; /*!< (@ 0x00000060) Bus Function Control Register */ + + struct + { + __IOM uint32_t MALE : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable */ + __IOM uint32_t NALE : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint32_t SALE : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable */ + uint32_t : 5; + __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable */ + uint32_t : 3; + __IOM uint32_t SMBS : 1; /*!< [12..12] SMBus/I2C Bus Selection */ + uint32_t : 1; + __IOM uint32_t FMPE : 1; /*!< [14..14] Fast-mode Plus Enable */ + __IOM uint32_t HSME : 1; /*!< [15..15] High Speed Mode Enable */ + uint32_t : 16; + } BFCTL_b; + }; + + union + { + __IOM uint32_t SVCTL; /*!< (@ 0x00000064) Slave Control Register */ + + struct + { + __IOM uint32_t GCAE : 1; /*!< [0..0] General Call Address Enable */ + uint32_t : 4; + __IOM uint32_t HSMCE : 1; /*!< [5..5] Hs-mode Master Code Enable */ + __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ + uint32_t : 8; + __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ + __IOM uint32_t SVAEn : 3; /*!< [18..16] Slave Address Enable */ + uint32_t : 13; + } SVCTL_b; + }; + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t REFCKCTL; /*!< (@ 0x00000070) Reference Clock Control Register */ + + struct + { + __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection */ + uint32_t : 29; + } REFCKCTL_b; + }; + + union + { + __IOM uint32_t STDBR; /*!< (@ 0x00000074) Standard Bit Rate Register */ + + struct + { + __IOM uint32_t SBRLO : 8; /*!< [7..0] Count value of the Low-level period of SCL clock */ + __IOM uint32_t SBRHO : 8; /*!< [15..8] Count value of the High-level period of SCL clock */ + __IOM uint32_t SBRLP : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull */ + uint32_t : 2; + __IOM uint32_t SBRHP : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull */ + uint32_t : 1; + __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain */ + } STDBR_b; + }; + + union + { + __IOM uint32_t EXTBR; /*!< (@ 0x00000078) Extended Bit Rate Register */ + + struct + { + __IOM uint32_t EBRLO : 8; /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain */ + __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ + __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ + uint32_t : 2; + __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate High-Level Period Push-Pull */ + uint32_t : 2; + } EXTBR_b; + }; + + union + { + __IOM uint32_t BFRECDT; /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register */ + + struct + { + __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle */ + uint32_t : 23; + } BFRECDT_b; + }; + + union + { + __IOM uint32_t BAVLCDT; /*!< (@ 0x00000080) Bus Available Condition Detection Time Register */ + + struct + { + __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle */ + uint32_t : 23; + } BAVLCDT_b; + }; + + union + { + __IOM uint32_t BIDLCDT; /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register */ + + struct + { + __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle */ + uint32_t : 14; + } BIDLCDT_b; + }; + + union + { + __IOM uint32_t OUTCTL; /*!< (@ 0x00000088) Output Control Register */ + + struct + { + __IOM uint32_t SDOC : 1; /*!< [0..0] SDA Output Control */ + __IOM uint32_t SCOC : 1; /*!< [1..1] SCL Output Control */ + __OM uint32_t SOCWP : 1; /*!< [2..2] SCL/SDA Output Control Write Protect */ + uint32_t : 1; + __IOM uint32_t EXCYC : 1; /*!< [4..4] Extra SCL Clock Cycle Output */ + uint32_t : 3; + __IOM uint32_t SDOD : 3; /*!< [10..8] SDA Output Delay */ + uint32_t : 4; + __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection */ + uint32_t : 16; + } OUTCTL_b; + }; + + union + { + __IOM uint32_t INCTL; /*!< (@ 0x0000008C) Input Control Register */ + + struct + { + __IOM uint32_t DNFS : 4; /*!< [3..0] Digital Noise Filter Stage Selection */ + __IOM uint32_t DNFE : 1; /*!< [4..4] Digital Noise Filter Circuit Enable */ + uint32_t : 27; + } INCTL_b; + }; + + union + { + __IOM uint32_t TMOCTL; /*!< (@ 0x00000090) Timeout Control Register */ + + struct + { + __IOM uint32_t TODTS : 2; /*!< [1..0] Timeout Detection Time Selection */ + uint32_t : 2; + __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control */ + __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control */ + __IOM uint32_t TOMDS : 2; /*!< [7..6] Timeout Operation Mode Selection */ + uint32_t : 24; + } TMOCTL_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t WUCTL; /*!< (@ 0x00000098) Wake Up Unit Control Register */ + + struct + { + __IOM uint32_t WUACKS : 1; /*!< [0..0] Wake-Up Acknowledge Selection */ + uint32_t : 3; + __IOM uint32_t WUANFS : 1; /*!< [4..4] Wake-Up Analog Noise Filter Selection */ + uint32_t : 1; + __IOM uint32_t WUFSYNE : 1; /*!< [6..6] Wake-Up function PCLKA Synchronous Enable */ + __IOM uint32_t WUFE : 1; /*!< [7..7] Wake-Up function Enable. */ + uint32_t : 24; + } WUCTL_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t ACKCTL; /*!< (@ 0x000000A0) Acknowledge Control Register */ + + struct + { + __IM uint32_t ACKR : 1; /*!< [0..0] Acknowledge Reception */ + __IOM uint32_t ACKT : 1; /*!< [1..1] Acknowledge Transmission */ + __OM uint32_t ACKTWP : 1; /*!< [2..2] ACKT Write Protect */ + uint32_t : 29; + } ACKCTL_b; + }; + + union + { + __IOM uint32_t SCSTRCTL; /*!< (@ 0x000000A4) SCL Stretch Control Register */ + + struct + { + __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable */ + __IOM uint32_t RWE : 1; /*!< [1..1] Receive Wait Enable */ + uint32_t : 30; + } SCSTRCTL_b; + }; + __IM uint32_t RESERVED9[2]; + + union + { + __IOM uint32_t SCSTLCTL; /*!< (@ 0x000000B0) SCL Stalling Control Register */ + + struct + { + __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle */ + uint32_t : 12; + __IOM uint32_t AAPE : 1; /*!< [28..28] Assigend Address Phase Enable */ + __IOM uint32_t TRAPE : 1; /*!< [29..29] Transition Phase Enable */ + __IOM uint32_t PARPE : 1; /*!< [30..30] Parity Phase Enable */ + __IOM uint32_t ACKPE : 1; /*!< [31..31] ACK phase Enable */ + } SCSTLCTL_b; + }; + __IM uint32_t RESERVED10[3]; + + union + { + __IOM uint32_t SVTDLG0; /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0 */ + + struct + { + uint32_t : 16; + __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ + } SVTDLG0_b; + }; + __IM uint32_t RESERVED11[23]; + + union + { + __IOM uint32_t STCTL; /*!< (@ 0x00000120) Synchronous Timing Control Register */ + + struct + { + __IOM uint32_t STOE : 1; /*!< [0..0] Synchronous Timing output Enable */ + uint32_t : 31; + } STCTL_b; + }; + + union + { + __IOM uint32_t ATCTL; /*!< (@ 0x00000124) Asynchronous Timing Control Register */ + + struct + { + __IOM uint32_t ATTRGS : 1; /*!< [0..0] Asynchronous Timing Trigger Select */ + __IOM uint32_t MREFOE : 1; /*!< [1..1] MREF Output Enable (Capture Event / Counter Overflow) */ + __IOM uint32_t AMEOE : 1; /*!< [2..2] Additional Master-initiated bus Event Output Enable */ + uint32_t : 5; + __IOM uint32_t CDIV : 8; /*!< [15..8] TCLK Counter Divide Setting */ + uint32_t : 16; + } ATCTL_b; + }; + + union + { + __IOM uint32_t ATTRG; /*!< (@ 0x00000128) Asynchronous Timing Trigger Register */ + + struct + { + __OM uint32_t ATSTRG : 1; /*!< [0..0] Asynchronous Timing Software Trigger */ + uint32_t : 31; + } ATTRG_b; + }; + + union + { + __IOM uint32_t ATCCNTE; /*!< (@ 0x0000012C) Asynchronous Timing Contorol Counter enable Register */ + + struct + { + __IOM uint32_t ATCE : 1; /*!< [0..0] Asynchronous Timing Counter Enable for MREF, MC2, SC1, + * SC2. */ + uint32_t : 31; + } ATCCNTE_b; + }; + __IM uint32_t RESERVED12[4]; + + union + { + __IOM uint32_t CNDCTL; /*!< (@ 0x00000140) Condition Control Register */ + + struct + { + __IOM uint32_t STCND : 1; /*!< [0..0] START (S) Condition Issuance */ + __IOM uint32_t SRCND : 1; /*!< [1..1] Repeated START (Sr) Condition Issuance */ + __IOM uint32_t SPCND : 1; /*!< [2..2] STOP (P) Condition Issuance */ + uint32_t : 29; + } CNDCTL_b; + }; + __IM uint32_t RESERVED13[3]; + __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ + __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ + __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ + __IM uint32_t RESERVED14[8]; + __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ + __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ + + union + { + __OM uint32_t HCMDQP; /*!< (@ 0x00000184) High Priority Command Queue Port Register */ + + struct + { + __OM uint32_t HCMDQP : 32; /*!< [31..0] High Priority Command Queue Port */ + } HCMDQP_b; + }; + + union + { + __IM uint32_t HRSPQP; /*!< (@ 0x00000188) High Priority Response Queue Port Register */ + + struct + { + __IM uint32_t HRSPQP : 32; /*!< [31..0] High Priority Response Queue Port */ + } HRSPQP_b; + }; + + union + { + __IOM uint32_t HTDTBP; /*!< (@ 0x0000018C) High Priority Transfer Data Buffer Port Register */ + + struct + { + __IOM uint32_t HTDTBP : 32; /*!< [31..0] High Priority Transfer Data Buffer Port */ + } HTDTBP_b; + }; + + union + { + __IOM uint32_t NQTHCTL; /*!< (@ 0x00000190) Normal Queue Threshold Control Register */ + + struct + { + __IOM uint32_t CMDQTH : 8; /*!< [7..0] Normal Command Ready Queue Threshold */ + __IOM uint32_t RSPQTH : 8; /*!< [15..8] Normal Response Queue Threshold */ + __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size */ + __IOM uint32_t IBIQTH : 8; /*!< [31..24] Normal IBI Queue Threshold */ + } NQTHCTL_b; + }; + + union + { + __IOM uint32_t NTBTHCTL0; /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control + * Register 0 */ + + struct + { + __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold */ + uint32_t : 5; + __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold */ + uint32_t : 5; + } NTBTHCTL0_b; + }; + __IM uint32_t RESERVED15[10]; + + union + { + __IOM uint32_t NRQTHCTL; /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control + * Register */ + + struct + { + __IOM uint32_t RSQTH : 8; /*!< [7..0] Normal Receive Status Queue Threshold */ + uint32_t : 24; + } NRQTHCTL_b; + }; + + union + { + __IOM uint32_t HQTHCTL; /*!< (@ 0x000001C4) High Priority Queue Threshold Control Register */ + + struct + { + __IOM uint32_t CMDQTH : 8; /*!< [7..0] High Priority Command Queue Threshold */ + __IOM uint32_t RSPQTH : 8; /*!< [15..8] High Priority Response Queue Threshold */ + uint32_t : 16; + } HQTHCTL_b; + }; + + union + { + __IOM uint32_t HTBTHCTL; /*!< (@ 0x000001C8) High Priority Transfer Data Buffer Threshold + * Control Register */ + + struct + { + __IOM uint32_t TXDBTH : 3; /*!< [2..0] High Priority Tx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t RXDBTH : 3; /*!< [10..8] High Priority Rx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t TXSTTH : 3; /*!< [18..16] High Priority Tx Start Threshold */ + uint32_t : 5; + __IOM uint32_t RXSTTH : 3; /*!< [26..24] High Priority Rx Start Threshold */ + uint32_t : 5; + } HTBTHCTL_b; + }; + __IM uint32_t RESERVED16; + + union + { + __IOM uint32_t BST; /*!< (@ 0x000001D0) Bus Status Register */ + + struct + { + __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag */ + __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag */ + __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag */ + uint32_t : 1; + __IOM uint32_t NACKDF : 1; /*!< [4..4] NACK Detection Flag */ + uint32_t : 3; + __IOM uint32_t TENDF : 1; /*!< [8..8] Transmit End Flag */ + uint32_t : 7; + __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ + uint32_t : 3; + __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ + uint32_t : 3; + __IOM uint32_t WUCNDDF : 1; /*!< [24..24] Wake-Up Condition Detection Flag */ + uint32_t : 7; + } BST_b; + }; + + union + { + __IOM uint32_t BSTE; /*!< (@ 0x000001D4) Bus Status Enable Register */ + + struct + { + __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable */ + __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable */ + __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable */ + uint32_t : 1; + __IOM uint32_t NACKDE : 1; /*!< [4..4] NACK Detection Enable */ + uint32_t : 3; + __IOM uint32_t TENDE : 1; /*!< [8..8] Transmit End Enable */ + uint32_t : 7; + __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ + uint32_t : 3; + __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ + uint32_t : 3; + __IOM uint32_t WUCNDDE : 1; /*!< [24..24] Wake-up Condition Detection Enable */ + uint32_t : 7; + } BSTE_b; + }; + + union + { + __IOM uint32_t BIE; /*!< (@ 0x000001D8) Bus Interrupt Enable Register */ + + struct + { + __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable */ + __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable */ + __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t NACKDIE : 1; /*!< [4..4] NACK Detection Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TENDIE : 1; /*!< [8..8] Transmit End Interrupt Enable */ + uint32_t : 7; + __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t WUCNDDIE : 1; /*!< [24..24] Wake-Up Condition Detection Interrupt Enable */ + uint32_t : 7; + } BIE_b; + }; + + union + { + __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ + + struct + { + __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ + __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ + __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ + uint32_t : 1; + __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ + uint32_t : 3; + __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ + uint32_t : 7; + __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ + uint32_t : 3; + __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ + uint32_t : 3; + __IOM uint32_t WUCNDDFC : 1; /*!< [24..24] Wake-Up Condition Detection Force */ + uint32_t : 7; + } BSTFC_b; + }; + + union + { + __IOM uint32_t NTST; /*!< (@ 0x000001E0) Normal Transfer Status Register */ + + struct + { + __IOM uint32_t TDBEF0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0 */ + __IOM uint32_t RDBFF0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0 */ + __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag */ + __IOM uint32_t CMDQEF : 1; /*!< [3..3] Normal Command Queue Empty Flag */ + __IOM uint32_t RSPQFF : 1; /*!< [4..4] Normal Response Queue Full Flag */ + __IOM uint32_t TABTF : 1; /*!< [5..5] Normal Transfer Abort Flag */ + uint32_t : 3; + __IOM uint32_t TEF : 1; /*!< [9..9] Normal Transfer Error Flag */ + uint32_t : 10; + __IOM uint32_t RSQFF : 1; /*!< [20..20] Normal Receive Status Queue Full Flag */ + uint32_t : 11; + } NTST_b; + }; + + union + { + __IOM uint32_t NTSTE; /*!< (@ 0x000001E4) Normal Transfer Status Enable Register */ + + struct + { + __IOM uint32_t TDBEE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0 */ + __IOM uint32_t RDBFE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0 */ + __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable */ + __IOM uint32_t CMDQEE : 1; /*!< [3..3] Normal Command Queue Empty Enable */ + __IOM uint32_t RSPQFE : 1; /*!< [4..4] Normal Response Queue Full Enable */ + __IOM uint32_t TABTE : 1; /*!< [5..5] Normal Transfer Abort Enable */ + uint32_t : 3; + __IOM uint32_t TEE : 1; /*!< [9..9] Normal Transfer Error Enable */ + uint32_t : 10; + __IOM uint32_t RSQFE : 1; /*!< [20..20] Normal Receive Status Queue Full Enable */ + uint32_t : 11; + } NTSTE_b; + }; + + union + { + __IOM uint32_t NTIE; /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register */ + + struct + { + __IOM uint32_t TDBEIE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0 */ + __IOM uint32_t RDBFIE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0 */ + __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable */ + __IOM uint32_t CMDQEIE : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable */ + __IOM uint32_t RSPQFIE : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable */ + __IOM uint32_t TABTIE : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TEIE : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable */ + uint32_t : 10; + __IOM uint32_t RSQFIE : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable */ + uint32_t : 11; + } NTIE_b; + }; + + union + { + __IOM uint32_t NTSTFC; /*!< (@ 0x000001EC) Normal Transfer Status Force Register */ + + struct + { + __OM uint32_t TDBEFC0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0 */ + __OM uint32_t RDBFFC0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0 */ + __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force */ + __OM uint32_t CMDQEFC : 1; /*!< [3..3] Normal Command Queue Empty Force */ + __OM uint32_t RSPQFFC : 1; /*!< [4..4] Normal Response Queue Full Force */ + __OM uint32_t TABTFC : 1; /*!< [5..5] Normal Transfer Abort Force */ + uint32_t : 3; + __OM uint32_t TEFC : 1; /*!< [9..9] Normal Transfer Error Force */ + uint32_t : 10; + __OM uint32_t RSQFFC : 1; /*!< [20..20] Normal Receive Status Queue Full Force */ + uint32_t : 11; + } NTSTFC_b; + }; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint32_t HTST; /*!< (@ 0x00000200) High Priority Transfer Status Register */ + + struct + { + __IOM uint32_t TDBEF : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Flag */ + __IOM uint32_t RDBFF : 1; /*!< [1..1] High Priority Rx Data Buffer Full Flag */ + uint32_t : 1; + __IOM uint32_t CMDQEF : 1; /*!< [3..3] High Priority Command Queue Empty Flag */ + __IOM uint32_t RSPQFF : 1; /*!< [4..4] High Priority Response Queue Full Flag */ + __IOM uint32_t TABTF : 1; /*!< [5..5] High Priority Transfer Abort Flag */ + uint32_t : 3; + __IOM uint32_t TEF : 1; /*!< [9..9] High Priority Transfer Error Flag */ + uint32_t : 22; + } HTST_b; + }; + + union + { + __IOM uint32_t HTSTE; /*!< (@ 0x00000204) High Priority Transfer Status Enable Register */ + + struct + { + __IOM uint32_t TDBEE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Enable */ + __IOM uint32_t RDBFE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEE : 1; /*!< [3..3] High Priority Command Queue Empty Enable */ + __IOM uint32_t RSPQFE : 1; /*!< [4..4] High Priority Response Queue Full Enable */ + __IOM uint32_t TABTE : 1; /*!< [5..5] High Priority Transfer Abort Enable */ + uint32_t : 3; + __IOM uint32_t TEE : 1; /*!< [9..9] High Priority Transfer Error Enable */ + uint32_t : 22; + } HTSTE_b; + }; + + union + { + __IOM uint32_t HTIE; /*!< (@ 0x00000208) High Priority Transfer Interrupt Enable Register */ + + struct + { + __IOM uint32_t TDBEIE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Interrupt Enable */ + __IOM uint32_t RDBFIE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEIE : 1; /*!< [3..3] High Priority Command Queue Empty Interrupt Enable */ + __IOM uint32_t RSPQFIE : 1; /*!< [4..4] High Priority Response Queue Full Interrupt Enable */ + __IOM uint32_t TABTIE : 1; /*!< [5..5] High Priority Transfer Abort Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TEIE : 1; /*!< [9..9] High Priority Transfer Error Interrupt Enable */ + uint32_t : 22; + } HTIE_b; + }; + + union + { + __IOM uint32_t HTSTFC; /*!< (@ 0x0000020C) High Priority Transfer Status Force Register */ + + struct + { + __OM uint32_t TDBEFC : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Force */ + __OM uint32_t RDBFFC : 1; /*!< [1..1] High Priority Rx Data Buffer Full Force */ + uint32_t : 1; + __OM uint32_t CMDQEFC : 1; /*!< [3..3] High Priority Command Queue Empty Force */ + __OM uint32_t RSPQFFC : 1; /*!< [4..4] High Priority Response Queue Full Force */ + __OM uint32_t TABTFC : 1; /*!< [5..5] High Priority Transfer Abort Force */ + uint32_t : 3; + __OM uint32_t TEFC : 1; /*!< [9..9] High Priority Transfer Error Force */ + uint32_t : 22; + } HTSTFC_b; + }; + + union + { + __IM uint32_t BCST; /*!< (@ 0x00000210) Bus Condition Status Register */ + + struct + { + __IM uint32_t BFREF : 1; /*!< [0..0] Bus Free Detection Flag */ + __IM uint32_t BAVLF : 1; /*!< [1..1] Bus Available Detection Flag */ + __IM uint32_t BIDLF : 1; /*!< [2..2] Bus Idle Detection Flag */ + uint32_t : 29; + } BCST_b; + }; + + union + { + __IOM uint32_t SVST; /*!< (@ 0x00000214) Slave Status Register */ + + struct + { + __IOM uint32_t GCAF : 1; /*!< [0..0] General Call Address Detection Flag */ + uint32_t : 4; + __IOM uint32_t HSMCF : 1; /*!< [5..5] Hs-mode Master Code Detection Flag */ + __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ + uint32_t : 8; + __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ + __IOM uint32_t SVAFn : 3; /*!< [18..16] Slave Address Detection Flag */ + uint32_t : 13; + } SVST_b; + }; + + union + { + __IM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Operating Status Register */ + + struct + { + __IM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ + uint32_t : 31; + } WUST_b; + }; + + union + { + __IM uint32_t MRCCPT; /*!< (@ 0x0000021C) MsyncCNT Counter Capture Register */ + + struct + { + __IM uint32_t MRCCPT : 32; /*!< [31..0] MSyncCNT Counter Capture */ + } MRCCPT_b; + }; + __IM uint32_t RESERVED18; + + union + { + __IOM uint32_t DATBAS0; /*!< (@ 0x00000224) Device Address Table Basic Register 0 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS0_b; + }; + __IM uint32_t RESERVED19; + + union + { + __IOM uint32_t DATBAS1; /*!< (@ 0x0000022C) Device Address Table Basic Register 1 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS1_b; + }; + __IM uint32_t RESERVED20; + + union + { + __IOM uint32_t DATBAS2; /*!< (@ 0x00000234) Device Address Table Basic Register 2 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS2_b; + }; + __IM uint32_t RESERVED21; + + union + { + __IOM uint32_t DATBAS3; /*!< (@ 0x0000023C) Device Address Table Basic Register 3 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS3_b; + }; + __IM uint32_t RESERVED22; + + union + { + __IOM uint32_t DATBAS4; /*!< (@ 0x00000244) Device Address Table Basic Register 4 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS4_b; + }; + __IM uint32_t RESERVED23; + + union + { + __IOM uint32_t DATBAS5; /*!< (@ 0x0000024C) Device Address Table Basic Register 5 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS5_b; + }; + __IM uint32_t RESERVED24; + + union + { + __IOM uint32_t DATBAS6; /*!< (@ 0x00000254) Device Address Table Basic Register 6 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS6_b; + }; + __IM uint32_t RESERVED25; + + union + { + __IOM uint32_t DATBAS7; /*!< (@ 0x0000025C) Device Address Table Basic Register 7 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS7_b; + }; + __IM uint32_t RESERVED26[16]; + + union + { + __IOM uint32_t EXDATBAS; /*!< (@ 0x000002A0) Extended Device Address Table Basic Register */ + + struct + { + __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address */ + uint32_t : 9; + __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count */ + __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ + } EXDATBAS_b; + }; + __IM uint32_t RESERVED27[3]; + + union + { + __IOM uint32_t SDATBAS0; /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS0_b; + }; + + union + { + __IOM uint32_t SDATBAS1; /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS1_b; + }; + + union + { + __IOM uint32_t SDATBAS2; /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS2_b; + }; + __IM uint32_t RESERVED28[5]; + + union + { + __IOM uint32_t MSDCT0; /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT0_b; + }; + + union + { + __IOM uint32_t MSDCT1; /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT1_b; + }; + + union + { + __IOM uint32_t MSDCT2; /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT2_b; + }; + + union + { + __IOM uint32_t MSDCT3; /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT3_b; + }; + + union + { + __IOM uint32_t MSDCT4; /*!< (@ 0x000002E0) Master Device Characteristic Table Register 4 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT4_b; + }; + + union + { + __IOM uint32_t MSDCT5; /*!< (@ 0x000002E4) Master Device Characteristic Table Register 5 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT5_b; + }; + + union + { + __IOM uint32_t MSDCT6; /*!< (@ 0x000002E8) Master Device Characteristic Table Register 6 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT6_b; + }; + + union + { + __IOM uint32_t MSDCT7; /*!< (@ 0x000002EC) Master Device Characteristic Table Register 7 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT7_b; + }; + __IM uint32_t RESERVED29[12]; + + union + { + __IOM uint32_t SVDCT; /*!< (@ 0x00000320) Slave Device Characteristic Table Register */ + + struct + { + __IOM uint32_t TDCR : 8; /*!< [7..0] Transfar Device Characteristic Register */ + __IOM uint32_t TBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t TBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t TBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } SVDCT_b; + }; + __IOM uint32_t SDCTPIDL; /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional + * ID Low Register */ + __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional + * ID High Register */ + __IM uint32_t RESERVED30; + + union + { + __IM uint32_t SVDVAD0; /*!< (@ 0x00000330) Slave Device Address Register 0 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD0_b; + }; + + union + { + __IM uint32_t SVDVAD1; /*!< (@ 0x00000334) Slave Device Address Register 1 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD1_b; + }; + + union + { + __IM uint32_t SVDVAD2; /*!< (@ 0x00000338) Slave Device Address Register 2 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD2_b; + }; + __IM uint32_t RESERVED31[5]; + + union + { + __IOM uint32_t CSECMD; /*!< (@ 0x00000350) CCC Slave Events Command Register */ + + struct + { + __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable */ + __IOM uint32_t MSRQE : 1; /*!< [1..1] Mastership Requests Enable */ + uint32_t : 1; + __IOM uint32_t HJEVE : 1; /*!< [3..3] Hot-Join Event Enable */ + uint32_t : 28; + } CSECMD_b; + }; + + union + { + __IOM uint32_t CEACTST; /*!< (@ 0x00000354) CCC Enter Activity State Register */ + + struct + { + __IOM uint32_t ACTST : 4; /*!< [3..0] Activity State */ + uint32_t : 28; + } CEACTST_b; + }; + + union + { + __IOM uint32_t CMWLG; /*!< (@ 0x00000358) CCC Max Write Length Register */ + + struct + { + __IOM uint32_t MWLG : 16; /*!< [15..0] Max Write Length */ + uint32_t : 16; + } CMWLG_b; + }; + + union + { + __IOM uint32_t CMRLG; /*!< (@ 0x0000035C) CCC Max Read Length Register */ + + struct + { + __IOM uint32_t MRLG : 16; /*!< [15..0] Max Read Length */ + __IOM uint32_t IBIPSZ : 8; /*!< [23..16] IBI Payload Size */ + uint32_t : 8; + } CMRLG_b; + }; + + union + { + __IM uint32_t CETSTMD; /*!< (@ 0x00000360) CCC Enter Test Mode Register */ + + struct + { + __IM uint32_t TSTMD : 8; /*!< [7..0] Test Mode */ + uint32_t : 24; + } CETSTMD_b; + }; + + union + { + __IOM uint32_t CGDVST; /*!< (@ 0x00000364) CCC Get Device Status Register */ + + struct + { + __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt */ + uint32_t : 1; + __IOM uint32_t PRTE : 1; /*!< [5..5] Protocol Error */ + __IOM uint32_t ACTMD : 2; /*!< [7..6] Slave Device's current Activity Mode */ + __IOM uint32_t VDRSV : 8; /*!< [15..8] Vendor Reserved */ + uint32_t : 16; + } CGDVST_b; + }; + + union + { + __IOM uint32_t CMDSPW; /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register */ + + struct + { + __IOM uint32_t MSWDR : 3; /*!< [2..0] Maximum Sustained Write Data Rate */ + uint32_t : 29; + } CMDSPW_b; + }; + + union + { + __IOM uint32_t CMDSPR; /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register */ + + struct + { + __IOM uint32_t MSRDR : 3; /*!< [2..0] Maximum Sustained Read Data Rate */ + __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO) */ + uint32_t : 26; + } CMDSPR_b; + }; + + union + { + __IOM uint32_t CMDSPT; /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register */ + + struct + { + __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time */ + uint32_t : 7; + __IOM uint32_t MRTE : 1; /*!< [31..31] Maximum Read Turnaround Time Enable */ + } CMDSPT_b; + }; + + union + { + __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) + * Register */ + + struct + { + __IOM uint32_t SPTSYN : 1; /*!< [0..0] Supports Sync Mode */ + __IOM uint32_t SPTASYN0 : 1; /*!< [1..1] Support Async Mode 0 */ + __IOM uint32_t SPTASYN1 : 1; /*!< [2..2] Support Async Mode 1 */ + uint32_t : 5; + __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ + __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ + uint32_t : 8; + } CETSM_b; + }; + + union + { + __IOM uint32_t CETSS; /*!< (@ 0x00000378) CCC Exchange Timing Support Information S (State) + * Register */ + + struct + { + __IOM uint32_t SYNE : 1; /*!< [0..0] Sync Mode Enabled */ + __IOM uint32_t ASYNE : 2; /*!< [2..1] Async Mode Enabled */ + uint32_t : 4; + __IOM uint32_t ICOVF : 1; /*!< [7..7] Internal Counter Overflow */ + uint32_t : 24; + } CETSS_b; + }; + + union + { + __IOM uint32_t CGHDRCAP; /*!< (@ 0x0000037C) CCC Get HDR Capability Register */ + + struct + { + __IOM uint32_t DDREN : 1; /*!< [0..0] HDR-DDR Operation Enable */ + __IOM uint32_t TSPEN : 1; /*!< [1..1] HDR-TSP Operation Enable */ + __IOM uint32_t TSLEN : 1; /*!< [2..2] HDR-TSL Operation Enable */ + uint32_t : 29; + } CGHDRCAP_b; + }; + + union + { + __IOM uint32_t BITCNT; /*!< (@ 0x00000380) Bit Count Register */ + + struct + { + __IOM uint32_t BCNT : 5; /*!< [4..0] Bit Counter */ + uint32_t : 2; + __OM uint32_t BCNTWP : 1; /*!< [7..7] BCNT Write Protect */ + uint32_t : 24; + } BITCNT_b; + }; + __IM uint32_t RESERVED32[4]; + + union + { + __IM uint32_t NQSTLV; /*!< (@ 0x00000394) Normal Queue Status Level Register */ + + struct + { + __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level */ + __IM uint32_t RSPQLV : 8; /*!< [15..8] Normal Response Queue Level */ + __IM uint32_t IBIQLV : 8; /*!< [23..16] Normal IBI Queue Level */ + __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count */ + uint32_t : 3; + } NQSTLV_b; + }; + + union + { + __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register 0 */ + + struct + { + __IM uint32_t TDBFLV : 8; /*!< [7..0] Normal Transmit Data Buffer Free Level */ + __IM uint32_t RDBLV : 8; /*!< [15..8] Normal Receive Data Buffer Level */ + uint32_t : 16; + } NDBSTLV0_b; + }; + __IM uint32_t RESERVED33[9]; + + union + { + __IM uint32_t NRSQSTLV; /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register */ + + struct + { + __IM uint32_t RSQLV : 8; /*!< [7..0] Normal Receive Status Queue Level */ + uint32_t : 24; + } NRSQSTLV_b; + }; + + union + { + __IM uint32_t HQSTLV; /*!< (@ 0x000003C4) High Priority Queue Status Level Register */ + + struct + { + __IM uint32_t CMDQLV : 8; /*!< [7..0] High Priority Command Queue Level */ + __IM uint32_t RSPQLV : 8; /*!< [15..8] High Priority Response Queue Level */ + uint32_t : 16; + } HQSTLV_b; + }; + + union + { + __IM uint32_t HDBSTLV; /*!< (@ 0x000003C8) High Priority Data Buffer Status Level Register */ + + struct + { + __IM uint32_t TDBFLV : 8; /*!< [7..0] High Priority Tx Data Buffer Free Level */ + __IM uint32_t RDBLV : 8; /*!< [15..8] High Priority Rx Data Buffer Level */ + uint32_t : 16; + } HDBSTLV_b; + }; + + union + { + __IM uint32_t PRSTDBG; /*!< (@ 0x000003CC) Present State Debug Register */ + + struct + { + __IM uint32_t SCILV : 1; /*!< [0..0] SCL Line Signal Level */ + __IM uint32_t SDILV : 1; /*!< [1..1] SDA Line Signal Level */ + __IM uint32_t SCOLV : 1; /*!< [2..2] SCL Output Level */ + __IM uint32_t SDOLV : 1; /*!< [3..3] SDA Output Level */ + uint32_t : 28; + } PRSTDBG_b; + }; + + union + { + __IM uint32_t MSERRCNT; /*!< (@ 0x000003D0) Master Error Counters Register */ + + struct + { + __IM uint32_t M2ECNT : 8; /*!< [7..0] M2 Error Counter */ + uint32_t : 24; + } MSERRCNT_b; + }; + __IM uint32_t RESERVED34[3]; + + union + { + __IM uint32_t SC1CPT; /*!< (@ 0x000003E0) SC1 Capture monitor Register */ + + struct + { + __IM uint32_t SC1C : 16; /*!< [15..0] SC1 Capture */ + uint32_t : 16; + } SC1CPT_b; + }; + + union + { + __IM uint32_t SC2CPT; /*!< (@ 0x000003E4) SC2 Capture monitor Register */ + + struct + { + __IM uint32_t SC2C : 16; /*!< [15..0] SC2 Capture */ + uint32_t : 16; + } SC2CPT_b; + }; +} R_I3C0_Type; /*!< Size = 1000 (0x3e8) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Master MPU (R_MPU_MMPU) + */ + +typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) MMPU Operation After Detection Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t OADPT; /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OADPT_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[62]; + __IOM R_MPU_MMPU_GROUP_Type DMAC0; /*!< (@ 0x00000100) DMAC0 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DMAC1; /*!< (@ 0x00000300) DMAC1 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type EDMAC; /*!< (@ 0x00000500) EDMAC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type GLCDC; /*!< (@ 0x00000700) GLCDC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type NPU; /*!< (@ 0x00001100) NPU MMPU Registers */ +} R_MPU_MMPU_Type; /*!< Size = 4864 (0x1300) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40203000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + + struct + { + __IOM uint32_t MSTPB0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPB4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPD4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRD_b; + }; + + union + { + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + + struct + { + __IOM uint32_t MSTPE0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPE1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPE2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPE3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPE5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPE6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPE7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPE8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPE9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRE_b; + }; + + union + { + __IOM uint16_t LSMRWDIS; /*!< (@ 0x00000010) Low Speed Module R/W Disable Control Register */ + + struct + { + __IOM uint16_t RTCRWDIS : 1; /*!< [0..0] RTC Register R/W Enable Control */ + __IOM uint16_t WDTDIS : 1; /*!< [1..1] WDT Operate Clock Control */ + __IOM uint16_t IWDTIDS : 1; /*!< [2..2] IWDT Register Clock Control */ + uint16_t : 4; + __IOM uint16_t WREN : 1; /*!< [7..7] Write Enable for bits [2:0] */ + __OM uint16_t PRKEY : 8; /*!< [15..8] LSMRWDIS Key Code */ + } LSMRWDIS_b; + }; + }; +} R_MSTP_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (R_PORT0) + */ + +typedef struct /*!< (@ 0x40400000) R_PORT0 Structure */ +{ + union + { + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; + + struct + { + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000000) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000002) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + }; + }; + + union + { + union + { + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; + + struct + { + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000004) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000006) Event input data register */ + + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + }; + }; + + union + { + union + { + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t POSR; /*!< (@ 0x00000008) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + + union + { + __OM uint16_t PORR; /*!< (@ 0x0000000A) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; + + struct + { + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000C) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000E) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + }; + }; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x40400800) R_PFS Structure */ +{ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-MISC (R_PMISC) + */ + +typedef struct /*!< (@ 0x40400D00) R_PMISC Structure */ +{ + union + { + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint8_t PWPR; /*!< (@ 0x0000000C) Write-Protect Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3[3]; + + union + { + __IOM uint8_t PWPRS; /*!< (@ 0x00000014) Write-Protect Register for Secure */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5[13]; + __IOM R_PMISC_PMSAR_Type PMSAR[15]; /*!< (@ 0x00000030) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 108 (0x6c) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Realtime Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x40202000) R_RTC Structure */ +{ + union + { + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + + struct + { + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ + __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using + * time error adjustment function inlow-consumption clock + * mode. */ + } R64CNT_b; + }; + __IM uint8_t RESERVED; + + union + { + union + { + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ + + struct + { + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; + }; + + union + { + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ + + struct + { + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ + + struct + { + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; + }; + + union + { + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ + + struct + { + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; + }; + + union + { + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; + }; + }; + __IM uint8_t RESERVED3; + + union + { + union + { + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ + + struct + { + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; + }; + + union + { + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; + }; + + union + { + union + { + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ + + struct + { + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; + }; + + union + { + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ + + struct + { + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; + }; + }; + __IM uint8_t RESERVED7; + + union + { + union + { + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ + + struct + { + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; + }; + + union + { + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; + }; + }; + __IM uint8_t RESERVED8; + + union + { + union + { + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; + + union + { + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; + }; + }; + __IM uint8_t RESERVED9; + + union + { + union + { + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ + + struct + { + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; + }; + + union + { + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; + }; + }; + __IM uint8_t RESERVED10; + + union + { + union + { + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; + + union + { + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; + }; + __IM uint8_t RESERVED11; + + union + { + union + { + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; + }; + + union + { + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; + }; + }; + __IM uint8_t RESERVED12; + + union + { + union + { + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; + + union + { + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; + }; + + union + { + union + { + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; + + union + { + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ + + struct + { + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ + + struct + { + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + + struct + { + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + + struct + { + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; + }; + + union + { + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + + struct + { + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; + }; + + union + { + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + + struct + { + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; + }; + __IM uint8_t RESERVED19; + + union + { + __IOM uint16_t RADJ2; /*!< (@ 0x00000030) Time Error Adjustment Register 2 */ + + struct + { + uint16_t : 5; + __IOM uint16_t FADJ : 11; /*!< [15..5] Fractional Adjust Value */ + } RADJ2_b; + }; + __IM uint16_t RESERVED20[7]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ + +typedef struct /*!< (@ 0x40358000) R_SCI0 Structure */ +{ + union + { + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + + struct + { + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; + }; + + union + { + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union + { + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + + struct + { + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; + }; + + union + { + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union + { + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_MANC; /*!< (@ 0x00000004) Serial Status Register for Manchester Mode (SCMR.SMIF + * = 0, and MMR.MANEN = 1) */ + + struct + { + __IOM uint8_t MER : 1; /*!< [0..0] Manchester Error Flag Valid for Manchester mode only */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_MANC_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; + }; + + union + { + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + + struct + { + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; + }; + + union + { + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + + struct + { + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; + }; + + union + { + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + + struct + { + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; + }; + + union + { + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + + struct + { + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; + }; + + union + { + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + + struct + { + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; + }; + + union + { + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + + struct + { + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; + }; + + union + { + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + + struct + { + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; + }; + + union + { + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + + struct + { + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; + }; + + union + { + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + + struct + { + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; + }; + + union + { + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union + { + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; + + union + { + __IOM uint16_t TDRHL_MAN; /*!< (@ 0x0000000E) Transmit Data Register for Manchester Mode (MMR.MANEN + * = 1) */ + + struct + { + __IOM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data */ + __IOM uint16_t MPBT : 1; /*!< [9..9] Multi-processor Transfer Bit Flag */ + uint16_t : 2; + __IOM uint16_t TSYNC : 1; /*!< [12..12] Transmit SYNC data bit */ + uint16_t : 3; + } TDRHL_MAN_b; + }; + + struct + { + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; + + union + { + __IM uint16_t RDRHL_MAN; /*!< (@ 0x00000010) Receive Data Register for Manchester Mode (MMR.MANEN + * = 1) */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial Receive Data */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor Bit */ + uint16_t : 2; + __IM uint16_t RSYNC : 1; /*!< [12..12] Receive SYNC data bit */ + uint16_t : 3; + } RDRHL_MAN_b; + }; + + struct + { + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; + + union + { + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + + struct + { + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; + }; + + union + { + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + + struct + { + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; + }; + + union + { + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + + struct + { + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; + }; + + union + { + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + + struct + { + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; + }; + + union + { + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + + struct + { + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; + }; + + union + { + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + + struct + { + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; + }; + + union + { + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + + struct + { + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; + }; + + union + { + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + + struct + { + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + + struct + { + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; + }; + + union + { + __IOM uint8_t MMR; /*!< (@ 0x00000020) Manchester Mode Register */ + + struct + { + __IOM uint8_t RMPOL : 1; /*!< [0..0] Polarity of Received Manchester Code */ + __IOM uint8_t TMPOL : 1; /*!< [1..1] Polarity of Transmit Manchester Code */ + __IOM uint8_t ERTEN : 1; /*!< [2..2] Manchester Edge Retiming Enable */ + uint8_t : 1; + __IOM uint8_t SYNVAL : 1; /*!< [4..4] SYNC Value Setting */ + __IOM uint8_t SYNSEL : 1; /*!< [5..5] SYNC Select */ + __IOM uint8_t SBSEL : 1; /*!< [6..6] Start Bit Select */ + __IOM uint8_t MANEN : 1; /*!< [7..7] Manchester Mode Enable */ + } MMR_b; + }; + }; + + union + { + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + + struct + { + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; + }; + + union + { + union + { + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + + struct + { + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; + }; + + union + { + __IOM uint8_t TMPR; /*!< (@ 0x00000022) Transmit Manchester Preface Setting Register */ + + struct + { + __IOM uint8_t TPLEN : 4; /*!< [3..0] Transmit Preface Length */ + __IOM uint8_t TPPAT : 2; /*!< [5..4] Transmit Preface Pattern */ + uint8_t : 2; + } TMPR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + + struct + { + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; + }; + + union + { + __IOM uint8_t RMPR; /*!< (@ 0x00000023) Receive Manchester Preface Setting Register */ + + struct + { + __IOM uint8_t RPLEN : 4; /*!< [3..0] Receive Preface Length */ + __IOM uint8_t RPPAT : 2; /*!< [5..4] Receive Preface Pattern */ + uint8_t : 2; + } RMPR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + + struct + { + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; + }; + + union + { + __IOM uint8_t MESR; /*!< (@ 0x00000024) Manchester Extended Error Status Register */ + + struct + { + __IOM uint8_t PFER : 1; /*!< [0..0] Preface Error Flag */ + __IOM uint8_t SYER : 1; /*!< [1..1] SYNC Error Flag */ + __IOM uint8_t SBER : 1; /*!< [2..2] Start Bit Error Flag */ + uint8_t : 5; + } MESR_b; + }; + }; + + union + { + union + { + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + + struct + { + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; + }; + + union + { + __IOM uint8_t MECR; /*!< (@ 0x00000025) Manchester Extended Error Control Register */ + + struct + { + __IOM uint8_t PFEREN : 1; /*!< [0..0] Preface Error Flag */ + __IOM uint8_t SYEREN : 1; /*!< [1..1] Receive SYNC Error Enable */ + __IOM uint8_t SBEREN : 1; /*!< [2..2] Start Bit Error Enable */ + uint8_t : 5; + } MECR_b; + }; + }; + + union + { + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + + struct + { + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; + }; + + union + { + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + + struct + { + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; + }; + + union + { + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + + struct + { + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; + }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + + union + { + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + + struct + { + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; + }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + + union + { + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + + struct + { + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; + }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + + struct + { + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; + }; + + union + { + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + + struct + { + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; + }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ + __IM uint16_t RESERVED1[4]; + + union + { + __IOM uint8_t SCIMSKEN; /*!< (@ 0x0000003C) SCI5 TXD Output Mask Enable Register */ + + struct + { + __IOM uint8_t MSKEN : 1; /*!< [0..0] SCI5 TXD Output Mask Enable */ + uint8_t : 7; + } SCIMSKEN_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_SCI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SD/MMC Host Interface (R_SDHI0) + */ + +typedef struct /*!< (@ 0x40252000) R_SDHI0 Structure */ +{ + union + { + __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ + + struct + { + __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] + * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: + * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ + __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ + __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used + * in normal mode, see section 1.4.10, Example of SD_CMD Register + * Setting to select mode/response type. */ + __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ + __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data + * is handled) */ + __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command + * with data is handled) */ + __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block + * transfer) */ + uint32_t : 16; + } SD_CMD_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ + + struct + { + __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ + } SD_ARG_b; + }; + + union + { + __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ + + struct + { + __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ + uint32_t : 16; + } SD_ARG1_b; + }; + + union + { + __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ + + struct + { + __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, + * CMD12 is issued to halt the transfer through the SD host + * interface.However, if a command sequence is halted because + * of a communications error or timeout, CMD12 is not issued. + * Although continued buffer access is possible even after + * STP has been set to 1, the buffer access error bit (ERR5 + * or ERR4) in SD_INFO2 will be set accordingly.- When STP + * has been set to 1 during transfer for single block write, + * the access end flag is set when SD_BUF becomes emp */ + uint32_t : 7; + __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When + * SD_CMD is set as follows to start the command sequence + * while SEC is set to 1, CMD12 is automatically issued to + * stop multi-block transfer with the number of blocks which + * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] + * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is + * automatically issued, multiple block transfer)When the + * command sequence is halted because of a communications + * error or timeout, CMD12 is not automatically i */ + uint32_t : 23; + } SD_STOP_b; + }; + + union + { + __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ + + struct + { + __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value + * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ + } SD_SECCNT_b; + }; + + union + { + __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ + + struct + { + __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP10_b; + }; + + union + { + __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ + + struct + { + __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP1_b; + }; + + union + { + __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ + + struct + { + __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP32_b; + }; + + union + { + __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ + + struct + { + __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP3_b; + }; + + union + { + __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ + + struct + { + __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP54_b; + }; + + union + { + __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ + + struct + { + __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP5_b; + }; + + union + { + __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ + + struct + { + __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ + uint32_t : 8; + } SD_RSP76_b; + }; + + union + { + __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ + + struct + { + __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ + uint32_t : 24; + } SD_RSP7_b; + }; + + union + { + __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ + uint32_t : 1; + __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ + __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ + __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ + __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ + uint32_t : 1; + __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ + __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ + __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ + __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ + uint32_t : 21; + } SD_INFO1_b; + }; + + union + { + __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ + + struct + { + __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ + __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ + __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ + __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ + __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ + __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ + __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ + __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified + * by SD_PORTSEL. */ + __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ + __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ + uint32_t : 3; + __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, + * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN + * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 + * cycles of SDCLK have elapsed after setting of the CBSY + * bit to 0 due to completion of the command sequence. */ + __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ + __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ + uint32_t : 16; + } SD_INFO2_b; + }; + + union + { + __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ + __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ + __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ + uint32_t : 3; + __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ + __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ + uint32_t : 22; + } SD_INFO1_MASK_b; + }; + + union + { + __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ + + struct + { + __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ + __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ + __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ + __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ + __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ + __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ + __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ + __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ + uint32_t : 5; + __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ + uint32_t : 16; + } SD_INFO2_MASK_b; + }; + + union + { + __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ + + struct + { + __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ + __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ + __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ + uint32_t : 22; + } SD_CLK_CTRL_b; + }; + + union + { + __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ + + struct + { + __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 + * and 512 bytes for the transfer of single blocks.In cases + * of multiple block transfer with automatic issuing of CMD12 + * (CMD18 and CMD25), the only specifiable transfer data size + * is 512 bytes. Furthermore, in cases of multiple block transfer + * without automatic issuing of CMD12, as well as 512 bytes, + * 32, 64, 128, and 256 bytes are specifiable. However, in + * the reading of 32, 64, 128, and 256 bytes for the transfer + * of multiple blocks, this is restricted to mult */ + uint32_t : 22; + } SD_SIZE_b; + }; + + union + { + __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ + + struct + { + __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ + __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ + __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating + * timeout, software reset should be executed to terminate + * command sequence. */ + uint32_t : 4; + __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ + uint32_t : 1; + __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset + * and when the SOFT_RST.SDRST flag is 0. */ + uint32_t : 16; + } SD_OPTION_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ + + struct + { + __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command + * issued within a command sequence */ + __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by + * setting a command index in SD_CMD, this is Indicated in + * CMDE0. */ + __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to + * a command issued within a command sequence */ + __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is + * issued by setting a command index in SD_CMD, this is indicated + * in RSPLENE0. */ + __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ + __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ + uint32_t : 2; + __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a + * command issued within a command sequence */ + __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued + * by setting a command index in SD_CMD, this is indicated + * in RSPCRCE0. */ + __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ + __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ + __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal + * value is 010b) */ + uint32_t : 17; + } SD_ERR_STS1_b; + }; + + union + { + __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ + + struct + { + __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ + __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ + __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ + __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ + __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ + __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ + __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ + uint32_t : 25; + } SD_ERR_STS2_b; + }; + + union + { + __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ + + struct + { + __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write + * data is written to this register. When reading from the + * SD card, the read data is read from this register. This + * register is internally connected to two 512-byte buffers.If + * both buffers are not empty when executing multiple block + * read, SD/MMC clock is stopped to suspend receiving data. + * When one of buffers is empty, SD/MMC clock is supplied + * to resume receiving data. */ + } SD_BUF0_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ + + struct + { + __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ + uint32_t : 1; + __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ + uint32_t : 5; + __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ + __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ + uint32_t : 22; + } SDIO_MODE_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ + uint32_t : 13; + __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ + __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ + uint32_t : 16; + } SDIO_INFO1_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ + uint32_t : 13; + __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ + __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ + uint32_t : 16; + } SDIO_INFO1_MASK_b; + }; + __IM uint32_t RESERVED3[79]; + + union + { + __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ + uint32_t : 30; + } SD_DMAEN_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ + + struct + { + __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ + uint32_t : 31; + } SOFT_RST_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ + uint32_t : 23; + } SDIF_MODE_b; + }; + __IM uint32_t RESERVED6[4]; + + union + { + __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ + + struct + { + uint32_t : 6; + __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ + __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ + uint32_t : 24; + } EXT_SWAP_b; + }; +} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ + +typedef struct /*!< (@ 0x4035C000) R_SPI0 Structure */ +{ + union + { + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + + struct + { + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + + struct + { + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; + }; + + union + { + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + + struct + { + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; + }; + + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; + }; + + union + { + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + + struct + { + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; + }; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ + +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ + union + { + __IOM uint16_t SRAMPRCR; /*!< (@ 0x00000000) SRAM Protection Control Register for Secure */ + + struct + { + __IOM uint16_t PR : 1; /*!< [0..0] Register Write Control */ + uint16_t : 7; + __OM uint16_t KW : 8; /*!< [15..8] Write Key Code */ + } SRAMPRCR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t SRAMPRCR_NS; /*!< (@ 0x00000004) SRAM Protection Control Register for Non-Secure */ + + struct + { + __IOM uint16_t PR : 1; /*!< [0..0] Register Write Control */ + uint16_t : 7; + __OM uint16_t KW : 8; /*!< [15..8] Write Key Code */ + } SRAMPRCR_NS_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) SRAM Wait State Control Register */ + + struct + { + __IOM uint8_t WTEN : 1; /*!< [0..0] SRAM wait enable */ + uint8_t : 7; + } SRAMWTSC_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4; + + union + { + __IOM uint8_t SRAMCR0; /*!< (@ 0x00000010) SRAM Control Register 0 */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after error detection */ + uint8_t : 1; + __IOM uint8_t ECCMOD : 2; /*!< [3..2] ECC Operating Mode Select */ + __IOM uint8_t E1STSEN : 1; /*!< [4..4] ECC 1-bit Error Update Enable */ + uint8_t : 2; + __IOM uint8_t TSTBYP : 1; /*!< [7..7] ECC Test Enable / ECC Bypass Select */ + } SRAMCR0_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint8_t SRAMCR1; /*!< (@ 0x00000014) SRAM Control Register 1 */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after error detection */ + uint8_t : 1; + __IOM uint8_t ECCMOD : 2; /*!< [3..2] ECC Operating Mode Select */ + __IOM uint8_t E1STSEN : 1; /*!< [4..4] ECC 1-bit Error Update Enable */ + uint8_t : 2; + __IOM uint8_t TSTBYP : 1; /*!< [7..7] ECC Test Enable / ECC Bypass Select */ + } SRAMCR1_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + + union + { + __IOM uint8_t SRAMCR2; /*!< (@ 0x00000018) SRAM Control Register 2 */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after error detection */ + uint8_t : 1; + __IOM uint8_t ECCMOD : 2; /*!< [3..2] ECC Operating Mode Select */ + __IOM uint8_t E1STSEN : 1; /*!< [4..4] ECC 1-bit Error Update Enable */ + uint8_t : 2; + __IOM uint8_t TSTBYP : 1; /*!< [7..7] ECC Test Enable / ECC Bypass Select */ + } SRAMCR2_b; + }; + __IM uint8_t RESERVED9; + __IM uint16_t RESERVED10; + + union + { + __IOM uint8_t SRAMCR3; /*!< (@ 0x0000001C) SRAM Control Register 3 */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after error detection */ + uint8_t : 1; + __IOM uint8_t ECCMOD : 2; /*!< [3..2] ECC Operating Mode Select */ + __IOM uint8_t E1STSEN : 1; /*!< [4..4] ECC 1-bit Error Update Enable */ + uint8_t : 2; + __IOM uint8_t TSTBYP : 1; /*!< [7..7] ECC Test Enable / ECC Bypass Select */ + } SRAMCR3_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[4]; + + union + { + __IOM uint8_t SRAMECCRGN0; /*!< (@ 0x00000030) SRAM ECC Region Control Register 0 */ + + struct + { + __IOM uint8_t ECCRGN : 3; /*!< [2..0] ECC target Region select */ + uint8_t : 5; + } SRAMECCRGN0_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; + + union + { + __IOM uint8_t SRAMECCRGN1; /*!< (@ 0x00000034) SRAM ECC Region Control Register 1 */ + + struct + { + __IOM uint8_t ECCRGN : 3; /*!< [2..0] ECC target Region select */ + uint8_t : 5; + } SRAMECCRGN1_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t SRAMECCRGN2; /*!< (@ 0x00000038) SRAM ECC Region Control Register 2 */ + + struct + { + __IOM uint8_t ECCRGN : 3; /*!< [2..0] ECC target Region select */ + uint8_t : 5; + } SRAMECCRGN2_b; + }; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; + + union + { + __IOM uint8_t SRAMECCRGN3; /*!< (@ 0x0000003C) SRAM ECC Region Control Register 3 */ + + struct + { + __IOM uint8_t ECCRGN : 3; /*!< [2..0] ECC target Region select */ + uint8_t : 5; + } SRAMECCRGN3_b; + }; + __IM uint8_t RESERVED20; + __IM uint16_t RESERVED21; + + union + { + __IM uint16_t SRAMESR; /*!< (@ 0x00000040) SRAM Error Status Register For ECC RAM */ + + struct + { + __IM uint16_t ERR00 : 1; /*!< [0..0] SRAM0 1-bit ECC Error Status */ + __IM uint16_t ERR01 : 1; /*!< [1..1] SRAM0 2-bit ECC Error Status */ + __IM uint16_t ERR10 : 1; /*!< [2..2] SRAM1 1-bit ECC Error Status */ + __IM uint16_t ERR11 : 1; /*!< [3..3] SRAM1 2-bit ECC Error Status */ + __IM uint16_t ERR20 : 1; /*!< [4..4] SRAM2 1-bit ECC Error Status */ + __IM uint16_t ERR21 : 1; /*!< [5..5] SRAM2 2-bit ECC Error Status */ + __IM uint16_t ERR30 : 1; /*!< [6..6] SRAM3 1-bit ECC Error Status */ + __IM uint16_t ERR31 : 1; /*!< [7..7] SRAM3 2-bit ECC Error Status */ + uint16_t : 8; + } SRAMESR_b; + }; + __IM uint16_t RESERVED22; + __IM uint32_t RESERVED23; + + union + { + __OM uint16_t SRAMESCLR; /*!< (@ 0x00000048) SRAM Error Status Clear Register For ECC RAM */ + + struct + { + __OM uint16_t CLR00 : 1; /*!< [0..0] SRAM0 1-bit ECC Error Status Clear */ + __OM uint16_t CLR01 : 1; /*!< [1..1] SRAM0 2-bit ECC Error Status Clear */ + __OM uint16_t CLR10 : 1; /*!< [2..2] SRAM1 1-bit ECC Error Status Clear */ + __OM uint16_t CLR11 : 1; /*!< [3..3] SRAM1 2-bit ECC Error Status Clear */ + __OM uint16_t CLR20 : 1; /*!< [4..4] SRAM2 1-bit ECC Error Status Clear */ + __OM uint16_t CLR21 : 1; /*!< [5..5] SRAM2 2-bit ECC Error Status Clear */ + __OM uint16_t CLR30 : 1; /*!< [6..6] SRAM3 1-bit ECC Error Status Clear */ + __OM uint16_t CLR31 : 1; /*!< [7..7] SRAM3 2-bit ECC Error Status Clear */ + uint16_t : 8; + } SRAMESCLR_b; + }; + __IM uint16_t RESERVED24; + __IM uint32_t RESERVED25; + + union + { + __IM uint32_t SRAMEAR00; /*!< (@ 0x00000050) SRAM Error Address Register 00 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR00_b; + }; + + union + { + __IM uint32_t SRAMEAR01; /*!< (@ 0x00000054) SRAM Error Address Register 01 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR01_b; + }; + __IM uint32_t RESERVED26[2]; + + union + { + __IM uint32_t SRAMEAR10; /*!< (@ 0x00000060) SRAM Error Address Register 10 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR10_b; + }; + + union + { + __IM uint32_t SRAMEAR11; /*!< (@ 0x00000064) SRAM Error Address Register 11 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR11_b; + }; + __IM uint32_t RESERVED27[2]; + + union + { + __IM uint32_t SRAMEAR20; /*!< (@ 0x00000070) SRAM Error Address Register 20 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR20_b; + }; + + union + { + __IM uint32_t SRAMEAR21; /*!< (@ 0x00000074) SRAM Error Address Register 21 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR21_b; + }; + __IM uint32_t RESERVED28[2]; + + union + { + __IM uint32_t SRAMEAR30; /*!< (@ 0x00000080) SRAM Error Address Register 30 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR30_b; + }; + + union + { + __IM uint32_t SRAMEAR31; /*!< (@ 0x00000084) SRAM Error Address Register 31 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR31_b; + }; +} R_SRAM_Type; /*!< Size = 136 (0x88) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0) + */ + +typedef struct /*!< (@ 0x4025D000) R_SSI0 Structure */ +{ + union + { + __IOM uint32_t SSICR; /*!< (@ 0x00000000) Control Register */ + + struct + { + __IOM uint32_t REN : 1; /*!< [0..0] Receive Enable */ + __IOM uint32_t TEN : 1; /*!< [1..1] Transmit Enable */ + uint32_t : 1; + __IOM uint32_t MUEN : 1; /*!< [3..3] Mute EnableNOTE: When this module is muted, the value + * of outputting serial data is rewritten to 0 but data transmission + * is not stopped. Write dummy data to the SSIFTDR not to + * generate a transmit underflow because the number of data + * in the transmit FIFO is decreasing. */ + __IOM uint32_t CKDV : 4; /*!< [7..4] Serial Oversampling Clock Division Ratio */ + __IOM uint32_t DEL : 1; /*!< [8..8] Serial Data Delay */ + __IOM uint32_t PDTA : 1; /*!< [9..9] Parallel Data Alignment */ + __IOM uint32_t SDTA : 1; /*!< [10..10] Serial Data Alignment */ + __IOM uint32_t SPDP : 1; /*!< [11..11] Serial Padding Polarity */ + __IOM uint32_t LRCKP : 1; /*!< [12..12] Serial WS Polarity */ + __IOM uint32_t BCKP : 1; /*!< [13..13] Serial Bit Clock Polarity */ + __IOM uint32_t MST : 1; /*!< [14..14] Serial WS Direction NOTE: Only the following settings + * are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings + * are prohibited. */ + uint32_t : 1; + __IOM uint32_t SWL : 3; /*!< [18..16] System Word LengthSet the system word length to the + * bit clock frequency/2 fs. */ + __IOM uint32_t DWL : 3; /*!< [21..19] Data Word Length */ + __IOM uint32_t FRM : 2; /*!< [23..22] Channels */ + uint32_t : 1; + __IOM uint32_t IIEN : 1; /*!< [25..25] Idle Mode Interrupt Enable */ + __IOM uint32_t ROIEN : 1; /*!< [26..26] Receive Overflow Interrupt Enable */ + __IOM uint32_t RUIEN : 1; /*!< [27..27] Receive Underflow Interrupt Enable */ + __IOM uint32_t TOIEN : 1; /*!< [28..28] Transmit Overflow Interrupt Enable */ + __IOM uint32_t TUIEN : 1; /*!< [29..29] Transmit Underflow Interrupt Enable */ + __IOM uint32_t CKS : 1; /*!< [30..30] Oversampling Clock Select */ + uint32_t : 1; + } SSICR_b; + }; + + union + { + __IOM uint32_t SSISR; /*!< (@ 0x00000004) Status Register */ + + struct + { + __IM uint32_t IDST : 1; /*!< [0..0] Idle Mode Status Flag */ + __IM uint32_t RSWNO : 1; /*!< [1..1] Receive Serial Word Number */ + __IM uint32_t RCHNO : 2; /*!< [3..2] Receive Channel Number.These bits are read as 00b. */ + __IM uint32_t TSWNO : 1; /*!< [4..4] Transmit Serial Word Number */ + __IM uint32_t TCHNO : 2; /*!< [6..5] Transmit Channel Number */ + uint32_t : 18; + __IM uint32_t IIRQ : 1; /*!< [25..25] Idle Mode Interrupt Status Flag */ + __IOM uint32_t ROIRQ : 1; /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t RUIRQ : 1; /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TOIRQ : 1; /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TUIRQ : 1; /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + uint32_t : 2; + } SSISR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t SSIFCR; /*!< (@ 0x00000010) FIFO Control Register */ + + struct + { + __IOM uint32_t RFRST : 1; /*!< [0..0] Receive FIFO Data Register Reset */ + __IOM uint32_t TFRST : 1; /*!< [1..1] Transmit FIFO Data Register Reset */ + __IOM uint32_t RIE : 1; /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by + * clearing either the RDF flag (see the description of the + * RDF bit for details) or RIE bit. */ + __IOM uint32_t TIE : 1; /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by + * clearing either the TDE flag (see the description of the + * TDE bit for details) or TIE bit. */ + __IOM uint32_t RTRG : 2; /*!< [5..4] Receive Data Trigger Number */ + __IOM uint32_t TTRG : 2; /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis + * are the number of empty stages in SSIFTDR at which the + * TDE flag is set. */ + uint32_t : 3; + __IOM uint32_t BSW : 1; /*!< [11..11] Byte Swap Enable */ + uint32_t : 4; + __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset */ + uint32_t : 14; + __IOM uint32_t AUCKE : 1; /*!< [31..31] Oversampling Clock Enable */ + } SSIFCR_b; + }; + + union + { + __IOM uint32_t SSIFSR; /*!< (@ 0x00000014) FIFO Status Register */ + + struct + { + __IOM uint32_t RDF : 1; /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register + * is a 32-byte FIFO register, the maximum number of data + * bytes that can be read from it while the RDF flag is 1 + * is indicated in the RDC[3:0] flags. If reading data from + * the SSIFRDR register is continued after all the data is + * read, undefined values will be read. */ + uint32_t : 7; + __IM uint32_t RDC : 6; /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data + * units stored in SSIFRDR) */ + uint32_t : 2; + __IOM uint32_t TDE : 1; /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register + * is a 32-byte FIFO register, the maximum number of bytes + * that can be written to it while the TDE flag is 1 is 8 + * - TDC[3:0]. If writing data to the SSIFTDR register is + * continued after all the data is written, writing will be + * invalid and an overflow occurs. */ + uint32_t : 7; + __IM uint32_t TDC : 6; /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of + * data units stored in SSIFTDR) */ + uint32_t : 2; + } SSIFSR_b; + }; + + union + { + union + { + __OM uint32_t SSIFTDR; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + + struct + { + __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of + * eight stages of 32-bit registers for storing data to be + * serially transmitted. NOTE: that when the SSIFTDR register + * is full of data (32 bytes), the next data cannot be written + * to it. If writing is attempted, it will be ignored and + * an overflow occurs. */ + } SSIFTDR_b; + }; + __OM uint16_t SSIFTDR16; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + __OM uint8_t SSIFTDR8; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + }; + + union + { + union + { + __IM uint32_t SSIFRDR; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + + struct + { + __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight + * stages of 32-bit registers for storing serially received + * data. */ + } SSIFRDR_b; + }; + __IM uint16_t SSIFRDR16; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + __IM uint8_t SSIFRDR8; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + }; + + union + { + __IOM uint32_t SSIOFR; /*!< (@ 0x00000020) Audio Format Register */ + + struct + { + __IOM uint32_t OMOD : 2; /*!< [1..0] Audio Format Select */ + uint32_t : 6; + __IOM uint32_t LRCONT : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation */ + __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in + * Idle Status */ + uint32_t : 22; + } SSIOFR_b; + }; + + union + { + __IOM uint32_t SSISCR; /*!< (@ 0x00000024) Status Control Register */ + + struct + { + __IOM uint32_t RDFS : 5; /*!< [4..0] RDF Setting Condition Select */ + uint32_t : 3; + __IOM uint32_t TDES : 5; /*!< [12..8] TDE Setting Condition Select */ + uint32_t : 19; + } SSISCR_b; + }; +} R_SSI0_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Pins (R_SYSTEM) + */ + +typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint8_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t OPE : 1; /*!< [6..6] Output Port Enable */ + uint8_t : 1; + } SBYCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t SSCR2; /*!< (@ 0x0000000E) Software Standby Control Register 2 */ + + struct + { + __IOM uint8_t SS2FSR : 1; /*!< [0..0] Software Standby 2 Fast Return */ + uint8_t : 7; + } SSCR2_b; + }; + __IM uint8_t RESERVED2; + + union + { + __IM uint8_t MRSCR; /*!< (@ 0x00000010) MRAM Standby Control Register */ + + struct + { + __IM uint8_t MRSWCF : 1; /*!< [0..0] MRAM Stabilization wait completion flag */ + uint8_t : 7; + } MRSCR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t VSCR; /*!< (@ 0x00000014) Voltage Scaling Control Register */ + + struct + { + __IOM uint8_t VSCM : 3; /*!< [2..0] Voltage Scaling Control Mode */ + uint8_t : 1; + __IOM uint8_t VSCMTSF : 1; /*!< [4..4] Voltage Scaling Control Mode Transition Status Flag */ + uint8_t : 3; + } VSCR_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint8_t SRMONR; /*!< (@ 0x00000018) SRAM Monitor Register */ + + struct + { + __IOM uint8_t MON : 2; /*!< [1..0] SRAM Voltage Monitor */ + uint8_t : 6; + } SRMONR_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ + + struct + { + __IOM uint32_t PCKD : 4; /*!< [3..0] Peripheral Module Clock D (PCLKD) Select */ + __IOM uint32_t PCKC : 4; /*!< [7..4] Peripheral Module Clock C (PCLKC) Select */ + __IOM uint32_t PCKB : 4; /*!< [11..8] Peripheral Module Clock B (PCLKB) Select */ + __IOM uint32_t PCKA : 4; /*!< [15..12] Peripheral Module Clock A (PCLKA) Select */ + __IOM uint32_t BCK : 4; /*!< [19..16] External Bus Clock (BCLK) Select */ + __IOM uint32_t PCKE : 4; /*!< [23..20] Peripheral Module Clock E (PCLKE) Select */ + __IOM uint32_t ICK : 4; /*!< [27..24] System Clock (ICLK) Select */ + __IOM uint32_t FCK : 4; /*!< [31..28] MRAM Clock (MRPCLK) Select */ + } SCKDIVCR_b; + }; + + union + { + __IOM uint16_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ + + struct + { + __IOM uint16_t CPUCK : 4; /*!< [3..0] CPU0 Clock (CPUCLK0) Select */ + __IOM uint16_t CPUCK1 : 4; /*!< [7..4] CPU1 Clock (CPUCLK1) Select */ + __IOM uint16_t NPUCK : 4; /*!< [11..8] NPU Clock (NPUCLK) Select */ + __IOM uint16_t MRICK : 4; /*!< [15..12] MRAM bus Clock (MRICLK) Select */ + } SCKDIVCR2_b; + }; + + union + { + __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ + + struct + { + __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ + uint8_t : 5; + } SCKSCR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL1 Control Register */ + + struct + { + __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL1 Stop Control */ + uint8_t : 7; + } PLLCR_b; + }; + __IM uint8_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ + + struct + { + __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ + uint8_t : 6; + __IOM uint8_t EBCKASEL : 1; /*!< [7..7] External Bus Asynchronous Select */ + } BCKCR_b; + }; + + union + { + __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ + + struct + { + __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT + * is prohibited when SCKDIVCR.ICK selects division by 1 and + * SCKSCR.CKSEL[2:0] bits select thesystem clock source that + * is faster than 32 MHz (ICLK > 32 MHz). */ + uint8_t : 7; + } MEMWAIT_b; + }; + + union + { + __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ + uint8_t : 7; + } MOSCCR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; + + union + { + __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ + uint8_t : 7; + } HOCOCR_b; + }; + __IM uint8_t RESERVED16; + + union + { + __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ + uint8_t : 7; + } MOCOCR_b; + }; + + union + { + __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ + + struct + { + __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ + uint8_t : 7; + } FLLCR1_b; + }; + + union + { + __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ + + struct + { + __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication Control */ + uint16_t : 5; + } FLLCR2_b; + }; + + union + { + __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ + + struct + { + __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF + * bit value after a reset is 1 when the OFS1.HOCOEN bit is + * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ + uint8_t : 2; + __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + uint8_t : 1; + __IM uint8_t PLLSF : 1; /*!< [5..5] PLL1 Clock Oscillation Stabilization Flag */ + __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ + uint8_t : 1; + } OSCSF_b; + }; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ + + struct + { + __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock Out source select */ + uint8_t : 1; + __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ + __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ + } CKOCR_b; + }; + + union + { + __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ + + struct + { + __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ + __IOM uint8_t TRCKSEL : 1; /*!< [4..4] Trace Clock Control Register */ + uint8_t : 2; + __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ + } TRCKCR_b; + }; + + union + { + __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ + + struct + { + __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ + } OSTDCR_b; + }; + + union + { + __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ + uint8_t : 7; + } OSTDSR_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IM uint8_t OSCMONR; /*!< (@ 0x00000043) Oscillator Monitor Register */ + + struct + { + uint8_t : 1; + __IM uint8_t MOCOMON : 1; /*!< [1..1] MOCO operation monitor */ + __IM uint8_t LOCOMON : 1; /*!< [2..2] LOCO operation monitor */ + uint8_t : 5; + } OSCMONR_b; + }; + __IM uint32_t RESERVED19; + __IM uint16_t RESERVED20; + + union + { + __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ + + struct + { + __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ + uint8_t : 7; + } PLL2CR_b; + }; + __IM uint8_t RESERVED21; + + union + { + union + { + __IOM uint16_t PLLCCR2; /*!< (@ 0x0000004C) PLL1 Clock Control Register 2 */ + + struct + { + __IOM uint16_t PLODIVP : 4; /*!< [3..0] PLL1 Output Frequency Division Ratio Select for output + * clock P */ + __IOM uint16_t PLODIVQ : 4; /*!< [7..4] PLL1 Output Frequency Division Ratio Select for output + * clock Q */ + __IOM uint16_t PLODIVR : 4; /*!< [11..8] PLL1 Output Frequency Division Ratio Select for output + * clock R */ + uint16_t : 4; + } PLLCCR2_b; + }; + + union + { + __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */ + + struct + { + __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock + * (valid only when LPOPTEN = 1) */ + __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */ + __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W + * clock (valid only when LPOPT.LPOPTEN = 1) */ + uint8_t : 3; + __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */ + } LPOPT_b; + }; + }; + + union + { + __IOM uint16_t PLL2CCR2; /*!< (@ 0x0000004E) PLL2 Clock Control Register 2 */ + + struct + { + __IOM uint16_t PL2ODIVP : 4; /*!< [3..0] PLL2 Output Frequency Division Ratio Select for output + * clock P */ + __IOM uint16_t PL2ODIVQ : 4; /*!< [7..4] PLL2 Output Frequency Division Ratio Select for output + * clock Q */ + __IOM uint16_t PL2ODIVR : 4; /*!< [11..8] PLL2 Output Frequency Division Ratio Select for output + * clock R */ + uint16_t : 4; + } PLL2CCR2_b; + }; + + union + { + __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ + + struct + { + __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ + uint8_t : 4; + __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ + } SLCDSCKCR_b; + }; + __IM uint8_t RESERVED22; + + union + { + __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ + + struct + { + __IOM uint8_t EBCKOEN : 1; /*!< [0..0] EBCLK Pin Output Control */ + uint8_t : 7; + } EBCKOCR_b; + }; + + union + { + __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ + + struct + { + __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ + uint8_t : 7; + } SDCKOCR_b; + }; + + union + { + __IOM uint8_t SCICKDIVCR; /*!< (@ 0x00000054) SCI clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] SCI clock (SCICLK) Division Select */ + uint8_t : 4; + } SCICKDIVCR_b; + }; + + union + { + __IOM uint8_t SCICKCR; /*!< (@ 0x00000055) SCI clock control register */ + + struct + { + __IOM uint8_t SCICKSEL : 4; /*!< [3..0] SCI clock (SCICLK) Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] SCI clock (SCICLK) Switching Request */ + __IM uint8_t CKSRDY : 1; /*!< [7..7] SCI clock (SCICLK) Switching Ready state flag */ + } SCICKCR_b; + }; + + union + { + __IOM uint8_t SPICKDIVCR; /*!< (@ 0x00000056) SPI clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] SPI clock (SPICLK) Division Select */ + uint8_t : 4; + } SPICKDIVCR_b; + }; + + union + { + __IOM uint8_t SPICKCR; /*!< (@ 0x00000057) SPI clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] SPI clock (SPICLK) Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] SPI clock (SPICLK) Switching Request */ + __IM uint8_t CKSRDY : 1; /*!< [7..7] SPI clock (SPICLK) Switching Ready state flag */ + } SPICKCR_b; + }; + __IM uint16_t RESERVED23; + + union + { + __IOM uint8_t ADCCKDIVCR; /*!< (@ 0x0000005A) ADC clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] Clock Division Select */ + uint8_t : 4; + } ADCCKDIVCR_b; + }; + + union + { + __IOM uint8_t ADCCKCR; /*!< (@ 0x0000005B) ADC clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } ADCCKCR_b; + }; + + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000005C) GPT Clock Division Control Register */ + + struct + { + __IOM uint8_t GPTCKDIV : 4; /*!< [3..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 4; + } GPTCKDIVCR_b; + }; + + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x0000005D) GPT clock control register */ + + struct + { + __IOM uint8_t GPTCKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } GPTCKCR_b; + }; + + union + { + __IOM uint8_t LCDCKDIVCR; /*!< (@ 0x0000005E) LCD clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] LCD clock (LCDCLK) Division Select */ + uint8_t : 4; + } LCDCKDIVCR_b; + }; + + union + { + __IOM uint8_t LCDCKCR; /*!< (@ 0x0000005F) LCD clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] LCD clock (LCDCLK) Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] LCD clock (LCDCLK) Switching Request */ + __IM uint8_t CKSRDY : 1; /*!< [7..7] LCD clock (LCDCLK) Switching Ready state flag */ + } LCDCKCR_b; + }; + __IM uint8_t RESERVED24; + + union + { + __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming */ + } MOCOUTCR_b; + }; + + union + { + __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming */ + } HOCOUTCR_b; + }; + __IM uint8_t RESERVED25; + __IM uint32_t RESERVED26[2]; + + union + { + __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ + + struct + { + __IOM uint8_t USBCKDIV : 4; /*!< [3..0] USB Clock (USBCLK) Division Select */ + uint8_t : 4; + } USBCKDIVCR_b; + }; + + union + { + __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t OCTACKDIV : 4; /*!< [3..0] Octal-SPI Clock (OCTACLK) Division Select */ + uint8_t : 4; + } OCTACKDIVCR_b; + }; + + union + { + __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ + + struct + { + __IOM uint8_t CANFDCKDIV : 4; /*!< [3..0] CANFD Clock (CANFDCLK) Division Select */ + uint8_t : 4; + } CANFDCKDIVCR_b; + }; + + union + { + __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */ + + struct + { + __IOM uint8_t USB60CKDIV : 4; /*!< [3..0] USB clock (USB60CLK) Division Select */ + uint8_t : 4; + } USB60CKDIVCR_b; + }; + + union + { + __IOM uint8_t I3CCKDIVCR; /*!< (@ 0x00000070) I3C Clock Division control register */ + + struct + { + __IOM uint8_t I3CCKDIV : 4; /*!< [3..0] I3C clock (I3CCLK) Division Select */ + uint8_t : 4; + } I3CCKDIVCR_b; + }; + __IM uint8_t RESERVED27; + __IM uint16_t RESERVED28; + + union + { + __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCKSEL : 4; /*!< [3..0] USB Clock (USBCLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ + __IOM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ + } USBCKCR_b; + }; + + union + { + __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ + + struct + { + __IOM uint8_t OCTACKSEL : 4; /*!< [3..0] Octal-SPI Clock (OCTACLK) Source Select */ + uint8_t : 2; + __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ + __IOM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ + } OCTACKCR_b; + }; + + union + { + __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ + + struct + { + __IOM uint8_t CANFDCKSEL : 4; /*!< [3..0] CANFD Clock (CANFDCLK) Source Select */ + uint8_t : 2; + __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ + __IOM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ + } CANFDCKCR_b; + }; + + union + { + __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ + + struct + { + __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ + __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ + } USB60CKCR_b; + }; + + union + { + __IOM uint8_t I3CCKCR; /*!< (@ 0x00000078) I3C Clock Control Register */ + + struct + { + __IOM uint8_t I3CCKSEL : 4; /*!< [3..0] I3C clock (I3CCLK) source select */ + uint8_t : 2; + __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */ + __IOM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */ + } I3CCKCR_b; + }; + __IM uint8_t RESERVED29; + __IM uint16_t RESERVED30; + + union + { + __IOM uint8_t MOSCSCR; /*!< (@ 0x0000007C) Main Clock Oscillator Standby Control Register */ + + struct + { + __IOM uint8_t MOSCSOKP : 1; /*!< [0..0] Main Clock Oscillator Standby Oscillation Keep select */ + uint8_t : 7; + } MOSCSCR_b; + }; + + union + { + __IOM uint8_t HOCOSCR; /*!< (@ 0x0000007D) High-Speed On-Chip Oscillator Standby Control + * Register */ + + struct + { + __IOM uint8_t HOSCSOKP : 1; /*!< [0..0] HOCO Standby Oscillation Keep select */ + uint8_t : 7; + } HOCOSCR_b; + }; + __IM uint16_t RESERVED31; + __IM uint32_t RESERVED32; + + union + { + __IOM uint8_t MOCOSCR; /*!< (@ 0x00000084) Middle-Speed On-Chip Oscillator Standby Control + * Register */ + + struct + { + __IOM uint8_t MOCOSOKP : 1; /*!< [0..0] MOCO Standby Oscillation Keep select */ + uint8_t : 7; + } MOCOSCR_b; + }; + __IM uint8_t RESERVED33; + __IM uint16_t RESERVED34; + __IM uint32_t RESERVED35[5]; + __IM uint16_t RESERVED36; + + union + { + __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ + + struct + { + __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ + uint8_t : 3; + __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ + uint8_t : 3; + } FLSTOP_b; + }; + + union + { + __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ + + struct + { + __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ + uint8_t : 6; + } PSMCR_b; + }; + + union + { + __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ + + struct + { + __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ + uint8_t : 2; + __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } OPCCR_b; + }; + __IM uint8_t RESERVED37; + + union + { + __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ + + struct + { + __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ + uint8_t : 4; + } MOSCWTCR_b; + }; + __IM uint8_t RESERVED38[2]; + + union + { + __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ + + struct + { + __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of + * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ + uint8_t : 5; + } HOCOWTCR_b; + }; + __IM uint16_t RESERVED39[2]; + + union + { + __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ + + struct + { + __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ + uint8_t : 3; + __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } SOPCCR_b; + }; + __IM uint8_t RESERVED40; + + union + { + __IOM uint32_t PLLCCR; /*!< (@ 0x000000AC) PLL1 Clock Control Register */ + + struct + { + __IOM uint32_t PLIDIV : 2; /*!< [1..0] PLL1 Input Frequency Division Ratio Select */ + uint32_t : 2; + __IOM uint32_t PLSRCSEL : 1; /*!< [4..4] PLL1 Clock Source Select */ + uint32_t : 1; + __IOM uint32_t PLLMULNF : 2; /*!< [7..6] PLL1 Frequency Multiplication Fractional Factor Select */ + __IOM uint32_t PLLMUL : 9; /*!< [16..8] PLL1 Frequency Multiplication Factor Select */ + uint32_t : 15; + } PLLCCR_b; + }; + __IM uint32_t RESERVED41[4]; + + union + { + __IOM uint32_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ + + struct + { + __IOM uint32_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect Flag */ + __IOM uint32_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect Flag */ + __IOM uint32_t SWRF : 1; /*!< [2..2] Software Reset Detect Flag */ + uint32_t : 1; + __IOM uint32_t CLURF : 1; /*!< [4..4] CPU0 Lockup Reset Detect flags */ + __IOM uint32_t LM0RF : 1; /*!< [5..5] Local memory 0 error Reset Detect Flag */ + uint32_t : 4; + __IOM uint32_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect Flag */ + uint32_t : 3; + __IOM uint32_t CMRF : 1; /*!< [14..14] Common memory error Reset Detect Flag */ + uint32_t : 2; + __IOM uint32_t WDT1RF : 1; /*!< [17..17] Watchdog Timer1 Reset Detect Flag */ + uint32_t : 2; + __IOM uint32_t CLU1RF : 1; /*!< [20..20] CPU1 Lockup Reset Detect Flag */ + __IOM uint32_t LM1RF : 1; /*!< [21..21] Local memory 1 error Reset Detect Flag */ + __IOM uint32_t NWRF : 1; /*!< [22..22] Network Reset Detect Flag */ + uint32_t : 9; + } RSTSR1_b; + }; + __IM uint32_t RESERVED42; + + union + { + __IOM uint32_t PLL2CCR; /*!< (@ 0x000000C8) PLL2 Clock Control Register */ + + struct + { + __IOM uint32_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ + uint32_t : 2; + __IOM uint32_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ + uint32_t : 1; + __IOM uint32_t PLL2MULNF : 2; /*!< [7..6] PLL2 Frequency Multiplication Fractional Factor Select */ + __IOM uint32_t PLL2MUL : 9; /*!< [16..8] PLL2 Frequency Multiplication Factor Select */ + uint32_t : 15; + } PLL2CCR_b; + }; + + union + { + __IM uint8_t SYRACCR; /*!< (@ 0x000000CC) System Register Access Control Register */ + + struct + { + __IM uint8_t BUSY : 1; /*!< [0..0] Access Ready Monitor */ + uint8_t : 7; + } SYRACCR_b; + }; + __IM uint8_t RESERVED43; + __IM uint16_t RESERVED44; + + union + { + __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock + * (UCLK). */ + uint8_t : 7; + } USBCKCR_ALT_b; + }; + + union + { + __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control + * Register */ + + struct + { + __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ + uint8_t : 6; + __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ + } SDADCCKCR_b; + }; + __IM uint16_t RESERVED45; + + union + { + __IOM uint8_t BCKADIVCR; /*!< (@ 0x000000D4) Asynchronous external Bus clock Division control + * register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] Clock Division Select */ + uint8_t : 4; + } BCKADIVCR_b; + }; + + union + { + __IOM uint8_t ESWCKDIVCR; /*!< (@ 0x000000D5) EtherSW clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] Clock Division Select */ + uint8_t : 4; + } ESWCKDIVCR_b; + }; + + union + { + __IOM uint8_t ESWPCKDIVCR; /*!< (@ 0x000000D6) EtherSW-PHY clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] Clock Division Select */ + uint8_t : 4; + } ESWPCKDIVCR_b; + }; + + union + { + __IOM uint8_t ESCCKDIVCR; /*!< (@ 0x000000D7) EtherCAT clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] Clock Division Select */ + uint8_t : 4; + } ESCCKDIVCR_b; + }; + + union + { + __IOM uint8_t ETHPCKDIVCR; /*!< (@ 0x000000D8) Ether-PHY clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] Clock Division Select */ + uint8_t : 4; + } ETHPCKDIVCR_b; + }; + __IM uint8_t RESERVED46; + + union + { + __IOM uint8_t BCKACR; /*!< (@ 0x000000DA) Asynchronous external bus clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IOM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } BCKACR_b; + }; + + union + { + __IOM uint8_t ESWCKCR; /*!< (@ 0x000000DB) EtherSW clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IOM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } ESWCKCR_b; + }; + + union + { + __IOM uint8_t ESWPCKCR; /*!< (@ 0x000000DC) EtherSW-PHY clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IOM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } ESWPCKCR_b; + }; + + union + { + __IOM uint8_t ESCCKCR; /*!< (@ 0x000000DD) EtherCAT clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IOM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } ESCCKCR_b; + }; + + union + { + __IOM uint8_t ETHPCKCR; /*!< (@ 0x000000DE) Ether-PHY clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IOM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } ETHPCKCR_b; + }; + __IM uint8_t RESERVED47; + + union + { + __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD1CR1_b; + }; + + union + { + __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD1SR_b; + }; + + union + { + __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD2CR1_b; + }; + + union + { + __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD2SR_b; + }; + + union + { + __IOM uint8_t LVD3CR1; /*!< (@ 0x000000E4) Voltage Monitor 3 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD3CR1_b; + }; + + union + { + __IOM uint8_t LVD3SR; /*!< (@ 0x000000E5) Voltage Monitor 3 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD3SR_b; + }; + + union + { + __IOM uint8_t LVD4CR1; /*!< (@ 0x000000E6) Voltage Monitor 4 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD4CR1_b; + }; + __IM uint8_t RESERVED48; + + union + { + __IOM uint8_t LVD5CR1; /*!< (@ 0x000000E8) Voltage Monitor 5 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD5CR1_b; + }; + __IM uint8_t RESERVED49; + __IM uint16_t RESERVED50; + __IM uint32_t RESERVED51; + + union + { + __IOM uint8_t CRVSYSCR; /*!< (@ 0x000000F0) Clock Recovery System Control Register */ + + struct + { + __IOM uint8_t CRVEN : 1; /*!< [0..0] Clock Recovery Enable */ + uint8_t : 7; + } CRVSYSCR_b; + }; + __IM uint8_t RESERVED52; + __IM uint16_t RESERVED53; + __IM uint32_t RESERVED54[3]; + + union + { + __IOM uint8_t CPUDSCR; /*!< (@ 0x00000100) CPU Deep Sleep Control Register */ + + struct + { + __IOM uint8_t PGD0 : 1; /*!< [0..0] Power Gating Disable for CPU0 */ + __IOM uint8_t PGD1 : 1; /*!< [1..1] Power Gating Disable for CPU1 */ + uint8_t : 6; + } CPUDSCR_b; + }; + __IM uint8_t RESERVED55; + __IM uint16_t RESERVED56; + __IM uint32_t RESERVED57[3]; + + union + { + __IOM uint8_t PDCTRGD; /*!< (@ 0x00000110) General Power Domain GD Control Register */ + + struct + { + __IOM uint8_t PDDE : 1; /*!< [0..0] Power control enable */ + uint8_t : 5; + __IOM uint8_t PDCSF : 1; /*!< [6..6] Power control status flag */ + __IOM uint8_t PDPGSF : 1; /*!< [7..7] Power gating status flag */ + } PDCTRGD_b; + }; + __IM uint8_t RESERVED58; + __IM uint16_t RESERVED59; + + union + { + __IOM uint8_t PDCTRNPU; /*!< (@ 0x00000114) General Power Domain NPU Control Register */ + + struct + { + __IOM uint8_t PDDE : 1; /*!< [0..0] Power control enable */ + uint8_t : 5; + __IOM uint8_t PDCSF : 1; /*!< [6..6] Power control status flag */ + __IOM uint8_t PDPGSF : 1; /*!< [7..7] Power gating status flag */ + } PDCTRNPU_b; + }; + __IM uint8_t RESERVED60; + __IM uint16_t RESERVED61; + + union + { + __IOM uint8_t PDCTRESWM; /*!< (@ 0x00000118) General Power Domain ESWM Control Register */ + + struct + { + __IOM uint8_t PDDE : 1; /*!< [0..0] Power control enable */ + uint8_t : 5; + __IOM uint8_t PDCSF : 1; /*!< [6..6] Power control status flag */ + __IOM uint8_t PDPGSF : 1; /*!< [7..7] Power gating status flag */ + } PDCTRESWM_b; + }; + __IM uint8_t RESERVED62; + __IM uint16_t RESERVED63; + __IM uint32_t RESERVED64[9]; + + union + { + __IOM uint16_t PDRAMSCR0; /*!< (@ 0x00000140) SRAM power domain Standby Control Register 0 */ + + struct + { + __IOM uint16_t RKEEP0 : 1; /*!< [0..0] RAM Retention bit 0 */ + __IOM uint16_t RKEEP1 : 1; /*!< [1..1] RAM Retention bit 1 */ + __IOM uint16_t RKEEP2 : 1; /*!< [2..2] RAM Retention bit 2 */ + __IOM uint16_t RKEEP3 : 1; /*!< [3..3] RAM Retention bit 3 */ + __IOM uint16_t RKEEP4 : 1; /*!< [4..4] RAM Retention bit 4 */ + __IOM uint16_t RKEEP5 : 1; /*!< [5..5] RAM Retention bit 5 */ + __IOM uint16_t RKEEP6 : 1; /*!< [6..6] RAM Retention bit 6 */ + __IOM uint16_t RKEEP7 : 1; /*!< [7..7] RAM Retention bit 7 */ + __IOM uint16_t RKEEP8 : 1; /*!< [8..8] RAM Retention bit 8 */ + __IOM uint16_t RKEEP9 : 1; /*!< [9..9] RAM Retention bit 9 */ + __IOM uint16_t RKEEP10 : 1; /*!< [10..10] RAM Retention bit 10 */ + __IOM uint16_t RKEEP11 : 1; /*!< [11..11] RAM Retention bit 11 */ + __IOM uint16_t RKEEP12 : 1; /*!< [12..12] RAM Retention bit 12 */ + __IOM uint16_t RKEEP13 : 1; /*!< [13..13] RAM Retention bit 13 */ + __IOM uint16_t RKEEP14 : 1; /*!< [14..14] RAM Retention bit 14 */ + __IOM uint16_t RKEEP15 : 1; /*!< [15..15] RAM Retention bit 15 */ + } PDRAMSCR0_b; + }; + + union + { + __IOM uint8_t PDRAMSCR1; /*!< (@ 0x00000142) SRAM power domain Standby Control Register 1 */ + + struct + { + __IOM uint8_t RKEEP0 : 1; /*!< [0..0] RAM Retention bit 0 */ + __IOM uint8_t RKEEP1 : 1; /*!< [1..1] RAM Retention bit 1 */ + __IOM uint8_t RKEEP2 : 1; /*!< [2..2] RAM Retention bit 2 */ + __IOM uint8_t RKEEP3 : 1; /*!< [3..3] RAM Retention bit 3 */ + __IOM uint8_t RKEEP4 : 1; /*!< [4..4] RAM Retention bit 4 */ + __IOM uint8_t RKEEP5 : 1; /*!< [5..5] RAM Retention bit 5 */ + __IOM uint8_t RKEEP6 : 1; /*!< [6..6] RAM Retention bit 6 */ + __IOM uint8_t RKEEP7 : 1; /*!< [7..7] RAM Retention bit 7 */ + } PDRAMSCR1_b; + }; + __IM uint8_t RESERVED65; + __IM uint32_t RESERVED66[155]; + + union + { + __IOM uint16_t VBRSABAR; /*!< (@ 0x000003B0) VBATT Backup Register Security Attribute Boundary + * Address Register */ + + struct + { + __IOM uint16_t SABA : 16; /*!< [15..0] Security Attribute Boundary Address */ + } VBRSABAR_b; + }; + __IM uint16_t RESERVED67; + + union + { + __IOM uint16_t VBRPABARS; /*!< (@ 0x000003B4) VBATT Backup Register Privilege Attribute Boundary + * Address Register for Secure Region */ + + struct + { + __IOM uint16_t PABAS : 16; /*!< [15..0] Privilege Attribute Boundary Address for Secure Region */ + } VBRPABARS_b; + }; + __IM uint16_t RESERVED68; + + union + { + __IOM uint16_t VBRPABARNS; /*!< (@ 0x000003B8) VBATT Backup Register Privilege Attribute Boundary + * Address Register for Non-secure Region */ + + struct + { + __IOM uint16_t PABANS : 16; /*!< [15..0] Privilege Attribute Boundary Address for Non-secure + * Region */ + } VBRPABARNS_b; + }; + __IM uint16_t RESERVED69; + __IM uint32_t RESERVED70; + + union + { + __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute + * Register */ + + struct + { + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ + } CGFSAR_b; + }; + + union + { + __IOM uint32_t RSTSAR; /*!< (@ 0x000003C4) Reset Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + uint32_t : 27; + } RSTSAR_b; + }; + + union + { + __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC5 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC6 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC7 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ + } LPMSAR_b; + }; + + union + { + __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + uint32_t : 30; + } LVDSAR_b; + }; + + union + { + __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non-secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non-secure Attribute bit 2 */ + __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non-secure Attribute bit 3 */ + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non-secure Attribute bit 4 */ + __IOM uint32_t NONSEC5 : 1; /*!< [5..5] Non-secure Attribute bit 5 */ + __IOM uint32_t NONSEC6 : 1; /*!< [6..6] Non-secure Attribute bit 6 */ + __IOM uint32_t NONSEC7 : 1; /*!< [7..7] Non-secure Attribute bit 7 */ + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non-secure Attribute bit 8 */ + uint32_t : 23; + } BBFSAR_b; + }; + __IM uint32_t RESERVED71; + + union + { + __IOM uint32_t PGCSAR; /*!< (@ 0x000003D8) Power Gating Control Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non-secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non-secure Attribute bit 2 */ + __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non-secure Attribute bit 3 */ + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non-secure Attribute bit 4 */ + __IOM uint32_t NONSEC5 : 1; /*!< [5..5] Non-secure Attribute bit 5 */ + __IOM uint32_t NONSEC6 : 1; /*!< [6..6] Non-secure Attribute bit 6 */ + __IOM uint32_t NONSEC7 : 1; /*!< [7..7] Non-secure Attribute bit 7 */ + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non-secure Attribute bit 8 */ + __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non-secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non-secure Attribute bit 10 */ + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non-secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non-secure Attribute bit 12 */ + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non-secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non-secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non-secure Attribute bit 15 */ + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non-secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non-secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non-secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non-secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non-secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non-secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non-secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non-secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non-secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non-secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non-secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non-secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non-secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non-secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non-secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non-secure Attribute bit 31 */ + } PGCSAR_b; + }; + __IM uint32_t RESERVED72; + + union + { + __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution + * Register */ + + struct + { + __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit + * 0 */ + __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit + * 1 */ + __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit + * 2 */ + __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit + * 3 */ + __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit + * 4 */ + __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit + * 5 */ + __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit + * 6 */ + __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit + * 7 */ + __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit + * 8 */ + __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit + * 9 */ + __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit + * 10 */ + __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit + * 11 */ + __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit + * 12 */ + __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit + * 13 */ + __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit + * 14 */ + __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit + * 15 */ + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + __IOM uint32_t DPFSA21 : 1; /*!< [21..21] Deep Standby Interrupt Factor Security Attribute bit + * 21 */ + __IOM uint32_t DPFSA22 : 1; /*!< [22..22] Deep Standby Interrupt Factor Security Attribute bit + * 22 */ + __IOM uint32_t DPFSA23 : 1; /*!< [23..23] Deep Standby Interrupt Factor Security Attribute bit + * 23 */ + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + __IOM uint32_t DPFSA25 : 1; /*!< [25..25] Deep Standby Interrupt Factor Security Attribute bit + * 25 */ + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + __IOM uint32_t DPFSA28 : 1; /*!< [28..28] Deep Standby Interrupt Factor Security Attribute bit + * 28 */ + __IOM uint32_t DPFSA29 : 1; /*!< [29..29] Deep Standby Interrupt Factor Security Attribute bit + * 29 */ + __IOM uint32_t DPFSA30 : 1; /*!< [30..30] Deep Standby Interrupt Factor Security Attribute bit + * 30 */ + __IOM uint32_t DPFSA31 : 1; /*!< [31..31] Deep Standby Interrupt Factor Security Attribute bit + * 31 */ + } DPFSAR_b; + }; + + union + { + __IOM uint32_t RSCSAR; /*!< (@ 0x000003E4) RAM Standby Control Security Attribution Register */ + + struct + { + __IOM uint32_t RSCSA0 : 1; /*!< [0..0] RAM Standby Control Security Attribute bit 0 */ + __IOM uint32_t RSCSA1 : 1; /*!< [1..1] RAM Standby Control Security Attribute bit 1 */ + __IOM uint32_t RSCSA2 : 1; /*!< [2..2] RAM Standby Control Security Attribute bit 2 */ + __IOM uint32_t RSCSA3 : 1; /*!< [3..3] RAM Standby Control Security Attribute bit 3 */ + __IOM uint32_t RSCSA4 : 1; /*!< [4..4] RAM Standby Control Security Attribute bit 4 */ + __IOM uint32_t RSCSA5 : 1; /*!< [5..5] RAM Standby Control Security Attribute bit 5 */ + __IOM uint32_t RSCSA6 : 1; /*!< [6..6] RAM Standby Control Security Attribute bit 6 */ + __IOM uint32_t RSCSA7 : 1; /*!< [7..7] RAM Standby Control Security Attribute bit 7 */ + __IOM uint32_t RSCSA8 : 1; /*!< [8..8] RAM Standby Control Security Attribute bit 8 */ + __IOM uint32_t RSCSA9 : 1; /*!< [9..9] RAM Standby Control Security Attribute bit 9 */ + __IOM uint32_t RSCSA10 : 1; /*!< [10..10] RAM Standby Control Security Attribute bit 10 */ + __IOM uint32_t RSCSA11 : 1; /*!< [11..11] RAM Standby Control Security Attribute bit 11 */ + __IOM uint32_t RSCSA12 : 1; /*!< [12..12] RAM Standby Control Security Attribute bit 12 */ + __IOM uint32_t RSCSA13 : 1; /*!< [13..13] RAM Standby Control Security Attribute bit 13 */ + __IOM uint32_t RSCSA14 : 1; /*!< [14..14] RAM Standby Control Security Attribute bit 14 */ + __IOM uint32_t RSCSA15 : 1; /*!< [15..15] RAM Standby Control Security Attribute bit 15 */ + __IOM uint32_t RSCSA16 : 1; /*!< [16..16] RAM Standby Control Security Attribute bit 16 */ + __IOM uint32_t RSCSA17 : 1; /*!< [17..17] RAM Standby Control Security Attribute bit 17 */ + __IOM uint32_t RSCSA18 : 1; /*!< [18..18] RAM Standby Control Security Attribute bit 18 */ + __IOM uint32_t RSCSA19 : 1; /*!< [19..19] RAM Standby Control Security Attribute bit 19 */ + __IOM uint32_t RSCSA20 : 1; /*!< [20..20] RAM Standby Control Security Attribute bit 20 */ + __IOM uint32_t RSCSA21 : 1; /*!< [21..21] RAM Standby Control Security Attribute bit 21 */ + __IOM uint32_t RSCSA22 : 1; /*!< [22..22] RAM Standby Control Security Attribute bit 22 */ + __IOM uint32_t RSCSA23 : 1; /*!< [23..23] RAM Standby Control Security Attribute bit 23 */ + __IOM uint32_t RSCSA24 : 1; /*!< [24..24] RAM Standby Control Security Attribute bit 24 */ + __IOM uint32_t RSCSA25 : 1; /*!< [25..25] RAM Standby Control Security Attribute bit 25 */ + __IOM uint32_t RSCSA26 : 1; /*!< [26..26] RAM Standby Control Security Attribute bit 26 */ + __IOM uint32_t RSCSA27 : 1; /*!< [27..27] RAM Standby Control Security Attribute bit 27 */ + __IOM uint32_t RSCSA28 : 1; /*!< [28..28] RAM Standby Control Security Attribute bit 28 */ + __IOM uint32_t RSCSA29 : 1; /*!< [29..29] RAM Standby Control Security Attribute bit 29 */ + __IOM uint32_t RSCSA30 : 1; /*!< [30..30] RAM Standby Control Security Attribute bit 30 */ + __IOM uint32_t RSCSA31 : 1; /*!< [31..31] RAM Standby Control Security Attribute bit 31 */ + } RSCSAR_b; + }; + + union + { + __IOM uint32_t DPFSAR1; /*!< (@ 0x000003E8) Deep Standby Interrupt Factor Security Attribution + * Register 1 */ + + struct + { + __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit + * 0 */ + __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit + * 1 */ + __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit + * 2 */ + __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit + * 3 */ + __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit + * 4 */ + __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit + * 5 */ + __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit + * 6 */ + __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit + * 7 */ + __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit + * 8 */ + __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit + * 9 */ + __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit + * 10 */ + __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit + * 11 */ + __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit + * 12 */ + __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit + * 13 */ + __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit + * 14 */ + __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit + * 15 */ + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + __IOM uint32_t DPFSA21 : 1; /*!< [21..21] Deep Standby Interrupt Factor Security Attribute bit + * 21 */ + __IOM uint32_t DPFSA22 : 1; /*!< [22..22] Deep Standby Interrupt Factor Security Attribute bit + * 22 */ + __IOM uint32_t DPFSA23 : 1; /*!< [23..23] Deep Standby Interrupt Factor Security Attribute bit + * 23 */ + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + __IOM uint32_t DPFSA25 : 1; /*!< [25..25] Deep Standby Interrupt Factor Security Attribute bit + * 25 */ + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + __IOM uint32_t DPFSA28 : 1; /*!< [28..28] Deep Standby Interrupt Factor Security Attribute bit + * 28 */ + __IOM uint32_t DPFSA29 : 1; /*!< [29..29] Deep Standby Interrupt Factor Security Attribute bit + * 29 */ + __IOM uint32_t DPFSA30 : 1; /*!< [30..30] Deep Standby Interrupt Factor Security Attribute bit + * 30 */ + __IOM uint32_t DPFSA31 : 1; /*!< [31..31] Deep Standby Interrupt Factor Security Attribute bit + * 31 */ + } DPFSAR1_b; + }; + __IM uint32_t RESERVED73[3]; + __IM uint16_t RESERVED74; + + union + { + __IOM uint16_t PRCR; /*!< (@ 0x000003FA) Protect Register for Secure Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power modes, and the battery backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the PVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] Enables writing to the registers related to the security + * and privilege setting registers. */ + __IOM uint16_t PRC5 : 1; /*!< [5..5] Enables writing to the registers related the reset control. */ + uint16_t : 2; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRC Key Code */ + } PRCR_b; + }; + __IM uint16_t RESERVED75; + + union + { + __IOM uint16_t PRCR_NS; /*!< (@ 0x000003FE) Protect Register for Non-secure Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power modes, and the battery backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the PVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] Enables writing to the registers related to the privilege + * setting registers. */ + uint16_t : 3; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRC Key Code */ + } PRCR_NS_b; + }; + + union + { + __IOM uint8_t LOCOCR; /*!< (@ 0x00000400) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint8_t : 7; + } LOCOCR_b; + }; + __IM uint8_t RESERVED76; + + union + { + __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000402) LOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming */ + } LOCOUTCR_b; + }; + __IM uint8_t RESERVED77; + __IM uint32_t RESERVED78[2]; + __IM uint16_t RESERVED79; + __IM uint8_t RESERVED80; + + union + { + __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ + + struct + { + __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ + uint8_t : 6; + } STCONR_b; + }; + __IM uint32_t RESERVED81; + __IM uint16_t RESERVED82; + + union + { + __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ + + struct + { + __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ + uint8_t : 6; + } FWEPROR_b; + }; + __IM uint8_t RESERVED83; + __IM uint32_t RESERVED84; + __IM uint16_t RESERVED85; + + union + { + __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ + + struct + { + __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ + uint8_t : 7; + } VBATTMONR_b; + }; + + union + { + __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ + uint8_t : 7; + } VBTCR1_b; + }; + __IM uint32_t RESERVED86[8]; + + union + { + __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ + + struct + { + __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ + __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ + uint8_t : 2; + __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ + __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ + __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ + __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ + } DCDCCTL_b; + }; + + union + { + __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ + + struct + { + __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ + uint8_t : 6; + } VCCSEL_b; + }; + __IM uint16_t RESERVED87; + __IM uint32_t RESERVED88[15]; + __IM uint16_t RESERVED89; + + union + { + __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ + + struct + { + __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ + uint8_t : 6; + } SOMRG_b; + }; + __IM uint8_t RESERVED90; + __IM uint32_t RESERVED91[11]; + + union + { + __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ + uint8_t : 1; + __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ + } VBTCR2_b; + }; + + union + { + __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ + + struct + { + __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ + __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ + uint8_t : 2; + __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ + uint8_t : 3; + } VBTSR_b; + }; + + union + { + __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ + + struct + { + __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ + uint8_t : 7; + } VBTCMPCR_b; + }; + __IM uint8_t RESERVED92; + + union + { + __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control + * Register */ + + struct + { + __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ + __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ + uint8_t : 6; + } VBTLVDICR_b; + }; + __IM uint8_t RESERVED93; + + union + { + __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ + + struct + { + __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ + uint8_t : 7; + } VBTWCTLR_b; + }; + __IM uint8_t RESERVED94; + + union + { + __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ + __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH0OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH1OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ + __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH2OTSR_b; + }; + __IM uint8_t RESERVED95; + + union + { + __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ + + struct + { + __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ + __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ + __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ + __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ + __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ + __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ + uint8_t : 2; + } VBTOCTLR_b; + }; + + union + { + __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ + + struct + { + __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ + __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ + __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ + __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ + __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ + __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWTER_b; + }; + + union + { + __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ + + struct + { + __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ + uint8_t : 5; + } VBTWEGR_b; + }; + + union + { + __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ + + struct + { + __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ + __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ + __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ + __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ + __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ + __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ + uint8_t : 2; + } VBTWFR_b; + }; + __IM uint32_t RESERVED96[336]; + + union + { + __IOM uint8_t DPSBYCR; /*!< (@ 0x00000A00) Deep Standby Control Register */ + + struct + { + __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ + __IOM uint8_t DCSSMODE : 2; /*!< [3..2] DCDC SSMODE */ + uint8_t : 2; + __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ + __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ + } DPSBYCR_b; + }; + __IM uint8_t RESERVED97; + __IM uint16_t RESERVED98; + __IM uint32_t RESERVED99; + + union + { + __IOM uint8_t DPSIER0; /*!< (@ 0x00000A08) Deep Standby Interrupt Enable Register 0 */ + + struct + { + __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER0_b; + }; + __IM uint8_t RESERVED100; + __IM uint16_t RESERVED101; + + union + { + __IOM uint8_t DPSIER1; /*!< (@ 0x00000A0C) Deep Standby Interrupt Enable Register 1 */ + + struct + { + __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER1_b; + }; + __IM uint8_t RESERVED102; + __IM uint16_t RESERVED103; + + union + { + __IOM uint8_t DPSIER2; /*!< (@ 0x00000A10) Deep Standby Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t DPVD1IE : 1; /*!< [0..0] PVD1 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DPVD2IE : 1; /*!< [1..1] PVD2 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ + __IOM uint8_t DPVD3IE : 1; /*!< [5..5] PVD3 Deep Standby Cancel Signal Enable */ + uint8_t : 2; + } DPSIER2_b; + }; + __IM uint8_t RESERVED104; + __IM uint16_t RESERVED105; + + union + { + __IOM uint8_t DPSIER3; /*!< (@ 0x00000A14) Deep Standby Interrupt Enable Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DULPT0IE : 1; /*!< [2..2] ULPT0 Overflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DULPT1IE : 1; /*!< [3..3] ULPT1 Overflow Deep Standby Cancel Signal Enable */ + uint8_t : 1; + __IOM uint8_t DIWDTIE : 1; /*!< [5..5] IWDT Overflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DSOSTDIE : 1; /*!< [6..6] Sub-clock Oscillation stop detection Deep Standby Cancel + * Signal Enable */ + __IOM uint8_t DVBATTADIE : 1; /*!< [7..7] VBATT Tamper Detection Deep Standby Cancel Signal Enable */ + } DPSIER3_b; + }; + __IM uint8_t RESERVED106; + __IM uint16_t RESERVED107; + + union + { + __IOM uint8_t DPSIFR0; /*!< (@ 0x00000A18) Deep Standby Interrupt Flag Register 0 */ + + struct + { + __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR0_b; + }; + __IM uint8_t RESERVED108; + __IM uint16_t RESERVED109; + + union + { + __IOM uint8_t DPSIFR1; /*!< (@ 0x00000A1C) Deep Standby Interrupt Flag Register 1 */ + + struct + { + __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR1_b; + }; + __IM uint8_t RESERVED110; + __IM uint16_t RESERVED111; + + union + { + __IOM uint8_t DPSIFR2; /*!< (@ 0x00000A20) Deep Standby Interrupt Flag Register 2 */ + + struct + { + __IOM uint8_t DPVD1IF : 1; /*!< [0..0] PVD1 Deep Standby Cancel Flag */ + __IOM uint8_t DPVD2IF : 1; /*!< [1..1] PVD2 Deep Standby Cancel Flag */ + __IOM uint8_t DRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ + __IOM uint8_t DPVD3IF : 1; /*!< [5..5] PVD5 Deep Standby Cancel Flag */ + uint8_t : 2; + } DPSIFR2_b; + }; + __IM uint8_t RESERVED112; + __IM uint16_t RESERVED113; + + union + { + __IOM uint8_t DPSIFR3; /*!< (@ 0x00000A24) Deep Standby Interrupt Flag Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DULPT0IF : 1; /*!< [2..2] ULPT0 Overflow Deep Standby Cancel Flag */ + __IOM uint8_t DULPT1IF : 1; /*!< [3..3] ULPT1 Overflow Deep Standby Cancel Flag */ + uint8_t : 1; + __IOM uint8_t DIWDTIF : 1; /*!< [5..5] IWDT Overflow Deep Standby Cancel Flag */ + __IOM uint8_t DSOSTDIF : 1; /*!< [6..6] Sub-clock Oscillation stop detection Deep Standby Cancel + * Flag */ + __IOM uint8_t DVBATTADIF : 1; /*!< [7..7] VBATT Tamper Detection Deep Standby Cancel Flag */ + } DPSIFR3_b; + }; + __IM uint8_t RESERVED114; + __IM uint16_t RESERVED115; + + union + { + __IOM uint8_t DPSIEGR0; /*!< (@ 0x00000A28) Deep Standby Interrupt Edge Register 0 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR0_b; + }; + __IM uint8_t RESERVED116; + __IM uint16_t RESERVED117; + + union + { + __IOM uint8_t DPSIEGR1; /*!< (@ 0x00000A2C) Deep Standby Interrupt Edge Register 1 */ + + struct + { + __IOM uint8_t DIRQ8EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ9EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ10EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ11EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ12EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ13EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ14EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ15EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR1_b; + }; + __IM uint8_t RESERVED118; + __IM uint16_t RESERVED119; + + union + { + __IOM uint8_t DPSIEGR2; /*!< (@ 0x00000A30) Deep Standby Interrupt Edge Register 2 */ + + struct + { + __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ + __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ + uint8_t : 2; + __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ + __IOM uint8_t DLVD3IEG : 1; /*!< [5..5] LVD3 Edge Select */ + uint8_t : 2; + } DPSIEGR2_b; + }; + __IM uint8_t RESERVED120; + __IM uint16_t RESERVED121; + + union + { + __IOM uint8_t DPSIEGR3; /*!< (@ 0x00000A34) Deep Standby Interrupt Edge Register 3 */ + + struct + { + __IOM uint8_t DIRQ16EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ17EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ18EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ19EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ20EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ21EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ22EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ23EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR3_b; + }; + __IM uint8_t RESERVED122; + __IM uint16_t RESERVED123; + + union + { + __IOM uint8_t SYOCDCR; /*!< (@ 0x00000A38) System Control OCD Control Register */ + + struct + { + __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ + uint8_t : 6; + __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ + } SYOCDCR_b; + }; + __IM uint8_t RESERVED124; + __IM uint16_t RESERVED125; + __IM uint32_t RESERVED126; + + union + { + __IOM uint8_t RSTSR0; /*!< (@ 0x00000A40) Reset Status Register 0 */ + + struct + { + __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect Flag */ + __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect Flag */ + __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect Flag */ + __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect Flag */ + uint8_t : 1; + __IOM uint8_t LVD4RF : 1; /*!< [5..5] Voltage Monitor 4 Reset Detect Flag */ + __IOM uint8_t LVD5RF : 1; /*!< [6..6] Voltage Monitor 5 Reset Detect Flag */ + __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset Flag */ + } RSTSR0_b; + }; + __IM uint8_t RESERVED127; + __IM uint16_t RESERVED128; + + union + { + __IOM uint8_t RSTSR2; /*!< (@ 0x00000A44) Reset Status Register 2 */ + + struct + { + __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ + uint8_t : 7; + } RSTSR2_b; + }; + __IM uint8_t RESERVED129; + __IM uint16_t RESERVED130; + + union + { + __IOM uint8_t RSTSR3; /*!< (@ 0x00000A48) Reset Status Register 3 */ + + struct + { + __IOM uint8_t CVMRF : 1; /*!< [0..0] Core Voltage Monitor Reset Detect Flag */ + uint8_t : 3; + __IOM uint8_t OCPRF : 1; /*!< [4..4] Overcurrent Protection Reset Detect Flag */ + uint8_t : 2; + __IOM uint8_t TEMPRF : 1; /*!< [7..7] Temperature Monitor Reset Detect Flag */ + } RSTSR3_b; + }; + __IM uint8_t RESERVED131; + __IM uint16_t RESERVED132; + __IM uint32_t RESERVED133; + + union + { + __IOM uint8_t MOMCR; /*!< (@ 0x00000A50) Main Clock Oscillator Mode Oscillation Control + * Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t MODRV0 : 3; /*!< [3..1] Main Clock Oscillator Drive Capability 0 Switching */ + uint8_t : 2; + __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ + uint8_t : 1; + } MOMCR_b; + }; + __IM uint8_t RESERVED134; + __IM uint16_t RESERVED135; + __IM uint32_t RESERVED136; + + union + { + __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000A58) Voltage Monitoring 1 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 5; /*!< [4..0] Detection Voltage Level Select(Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection Enable */ + } LVD1CMPCR_b; + }; + __IM uint8_t RESERVED137; + __IM uint16_t RESERVED138; + + union + { + __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000A5C) Voltage Monitoring 2 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 5; /*!< [4..0] Detection Voltage Level Select(Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection Enable */ + } LVD2CMPCR_b; + }; + __IM uint8_t RESERVED139; + __IM uint16_t RESERVED140; + + union + { + __IOM uint8_t LVD3CMPCR; /*!< (@ 0x00000A60) Voltage Monitoring 3 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 5; /*!< [4..0] Detection Voltage Level Select(Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection Enable */ + } LVD3CMPCR_b; + }; + __IM uint8_t RESERVED141; + __IM uint16_t RESERVED142; + + union + { + __IOM uint8_t LVD4CMPCR; /*!< (@ 0x00000A64) Voltage Monitoring 4 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 5; /*!< [4..0] Detection Voltage Level Select(Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection Enable */ + } LVD4CMPCR_b; + }; + __IM uint8_t RESERVED143; + __IM uint16_t RESERVED144; + + union + { + __IOM uint8_t LVD5CMPCR; /*!< (@ 0x00000A68) Voltage Monitoring 5 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 5; /*!< [4..0] Detection Voltage Level Select(Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection Enable */ + } LVD5CMPCR_b; + }; + __IM uint8_t RESERVED145; + __IM uint16_t RESERVED146; + __IM uint32_t RESERVED147; + + union + { + __IOM uint8_t LVD1CR0; /*!< (@ 0x00000A70) Voltage Monitor 1 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD1CR0_b; + }; + __IM uint8_t RESERVED148; + __IM uint16_t RESERVED149; + + union + { + __IOM uint8_t LVD2CR0; /*!< (@ 0x00000A74) Voltage Monitor 2 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD2CR0_b; + }; + __IM uint8_t RESERVED150; + __IM uint16_t RESERVED151; + + union + { + __IOM uint8_t LVD3CR0; /*!< (@ 0x00000A78) Voltage Monitor 3 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD3CR0_b; + }; + __IM uint8_t RESERVED152; + __IM uint16_t RESERVED153; + + union + { + __IOM uint8_t LVD4CR0; /*!< (@ 0x00000A7C) Voltage Monitor 4 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD4CR0_b; + }; + __IM uint8_t RESERVED154; + __IM uint16_t RESERVED155; + + union + { + __IOM uint8_t LVD5CR0; /*!< (@ 0x00000A80) Voltage Monitor 5 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD5CR0_b; + }; + __IM uint8_t RESERVED156; + __IM uint16_t RESERVED157; + + union + { + __IOM uint8_t VBATTMNSELR; /*!< (@ 0x00000A84) Battery Backup Voltage Monitor Function Select + * Register */ + + struct + { + __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ + uint8_t : 7; + } VBATTMNSELR_b; + }; + __IM uint8_t RESERVED158; + __IM uint16_t RESERVED159; + + union + { + __IOM uint8_t VBTBPCR1; /*!< (@ 0x00000A88) VBATT Battery Power Supply Control Register 1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power Supply Switch Stop */ + uint8_t : 7; + } VBTBPCR1_b; + }; + __IM uint8_t RESERVED160; + __IM uint16_t RESERVED161; + __IM uint32_t RESERVED162; + + union + { + __IOM uint8_t LPSCR; /*!< (@ 0x00000A90) Low Power State Control Register */ + + struct + { + __IOM uint8_t LPMD : 4; /*!< [3..0] Low power mode setting bit */ + uint8_t : 4; + } LPSCR_b; + }; + __IM uint8_t RESERVED163; + __IM uint16_t RESERVED164; + __IM uint32_t RESERVED165; + + union + { + __IOM uint8_t SSCR1; /*!< (@ 0x00000A98) Software Standby Control Register 1 */ + + struct + { + __IOM uint8_t SS2FR : 1; /*!< [0..0] Software Standby 2 Fast Return */ + uint8_t : 1; + __IOM uint8_t SS2LP : 2; /*!< [3..2] Software Standby 2 Low Power Select */ + uint8_t : 4; + } SSCR1_b; + }; + __IM uint8_t RESERVED166; + __IM uint16_t RESERVED167; + + union + { + __IOM uint8_t SVSCR; /*!< (@ 0x00000A9C) SSTBY Voltage Scaling Control Register */ + + struct + { + __IOM uint8_t SVSCM : 3; /*!< [2..0] SSTBY Voltage Scaling Control Mode */ + uint8_t : 5; + } SVSCR_b; + }; + __IM uint8_t RESERVED168; + __IM uint16_t RESERVED169; + __IM uint32_t RESERVED170[4]; + + union + { + __IOM uint8_t LVOCR; /*!< (@ 0x00000AB0) Low Voltage Operation Control Register */ + + struct + { + __IOM uint8_t LVO0E : 1; /*!< [0..0] Low Voltage Operation 0 Enable */ + __IOM uint8_t LVO1E : 1; /*!< [1..1] Low Voltage Operation 1 Enable */ + uint8_t : 6; + } LVOCR_b; + }; + __IM uint8_t RESERVED171; + __IM uint16_t RESERVED172; + + union + { + __IOM uint8_t MWMCR; /*!< (@ 0x00000AB4) MRAM-OTP Write Mode Control Register */ + + struct + { + __IOM uint8_t MWM : 2; /*!< [1..0] MRAM-OTP Write Mode */ + uint8_t : 6; + } MWMCR_b; + }; + __IM uint8_t RESERVED173; + __IM uint16_t RESERVED174; + __IM uint32_t RESERVED175[6]; + + union + { + __IOM uint8_t SYRSTMSK0; /*!< (@ 0x00000AD0) System Reset Mask Control Register 0 */ + + struct + { + __IOM uint8_t IWDTMASK : 1; /*!< [0..0] Independent Watchdog Timer Reset Mask */ + __IOM uint8_t WDT0MASK : 1; /*!< [1..1] Watchdog Timer Reset Mask */ + __IOM uint8_t SWMASK : 1; /*!< [2..2] Software Reset Mask */ + uint8_t : 1; + __IOM uint8_t CLU0MASK : 1; /*!< [4..4] CPU Lockup Reset Mask */ + __IOM uint8_t LM0MASK : 1; /*!< [5..5] Local Memory 0 Error Reset Mask */ + __IOM uint8_t CMMASK : 1; /*!< [6..6] Common Memory Error Reset Mask */ + __IOM uint8_t BUSMASK : 1; /*!< [7..7] Bus Error Reset Mask */ + } SYRSTMSK0_b; + }; + __IM uint8_t RESERVED176; + __IM uint16_t RESERVED177; + + union + { + __IOM uint8_t SYRSTMSK1; /*!< (@ 0x00000AD4) System Reset Mask Control Register 1 */ + + struct + { + uint8_t : 1; + __IOM uint8_t WDT1MASK : 1; /*!< [1..1] CPU1 Watchdog Timer Reset Mask */ + uint8_t : 2; + __IOM uint8_t CLU1MASK : 1; /*!< [4..4] CPU1 Lockup Reset Mask */ + __IOM uint8_t LM1MASK : 1; /*!< [5..5] Local Memory 1 Error Reset Mask */ + uint8_t : 2; + } SYRSTMSK1_b; + }; + __IM uint8_t RESERVED178; + __IM uint16_t RESERVED179; + + union + { + __IOM uint8_t SYRSTMSK2; /*!< (@ 0x00000AD8) System Reset Mask Control Register 2 */ + + struct + { + __IOM uint8_t PVD1MASK : 1; /*!< [0..0] Voltage Monitor 1 Reset Mask */ + __IOM uint8_t PVD2MASK : 1; /*!< [1..1] Voltage Monitor 2 Reset Mask */ + uint8_t : 6; + } SYRSTMSK2_b; + }; + __IM uint8_t RESERVED180; + __IM uint16_t RESERVED181; + + union + { + __IOM uint8_t TEMPRCR; /*!< (@ 0x00000ADC) Temperature Monitor Reset Control Register */ + + struct + { + __IOM uint8_t TEMPREN : 1; /*!< [0..0] Temperature Monitor Reset Enable */ + __IOM uint8_t TSNEN : 1; /*!< [1..1] Temperature Monitor Sensor Enable */ + __IOM uint8_t CMPEN : 1; /*!< [2..2] Comparator Enable */ + __IOM uint8_t TSNKEEP : 1; /*!< [3..3] Temperature Monitor Sensor Latch Control */ + uint8_t : 4; + } TEMPRCR_b; + }; + __IM uint8_t RESERVED182; + __IM uint16_t RESERVED183; + + union + { + __IOM uint8_t TEMPRLR; /*!< (@ 0x00000AE0) Temperature Monitor Reset Lock Register */ + + struct + { + __IOM uint8_t LOCK : 1; /*!< [0..0] Temperature Monitor Reset Control Register Lock */ + uint8_t : 7; + } TEMPRLR_b; + }; + __IM uint8_t RESERVED184; + __IM uint16_t RESERVED185; + __IM uint32_t RESERVED186[7]; + + union + { + __IOM uint8_t LDOSCR; /*!< (@ 0x00000B00) LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */ + __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */ + __IOM uint8_t LDOSTP2 : 1; /*!< [2..2] LDO2 Stop */ + __IOM uint8_t LDOSTP3 : 1; /*!< [3..3] LDO3 Stop */ + __IOM uint8_t LDOSTP4 : 1; /*!< [4..4] LDO4 Stop */ + __IOM uint8_t LDOSTP5 : 1; /*!< [5..5] LDO5 Stop */ + __IOM uint8_t LDOSTP6 : 1; /*!< [6..6] LDO6 Stop */ + __IOM uint8_t LDOSTP7 : 1; /*!< [7..7] LDO7 Stop */ + } LDOSCR_b; + }; + __IM uint8_t RESERVED187; + __IM uint16_t RESERVED188; + + union + { + __IOM uint8_t PLL1LDOCR; /*!< (@ 0x00000B04) PLL1-LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP : 1; /*!< [0..0] LDO Stop */ + __IOM uint8_t SKEEP : 1; /*!< [1..1] STBY Keep */ + uint8_t : 6; + } PLL1LDOCR_b; + }; + __IM uint8_t RESERVED189; + __IM uint16_t RESERVED190; + + union + { + __IOM uint8_t PLL2LDOCR; /*!< (@ 0x00000B08) PLL2-LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP : 1; /*!< [0..0] LDO Stop */ + __IOM uint8_t SKEEP : 1; /*!< [1..1] STBY Keep */ + uint8_t : 6; + } PLL2LDOCR_b; + }; + __IM uint8_t RESERVED191; + __IM uint16_t RESERVED192; + + union + { + __IOM uint8_t HOCOLDOCR; /*!< (@ 0x00000B0C) HOCO-LDO Control Register */ + + struct + { + __IOM uint8_t LDOSTP : 1; /*!< [0..0] LDO0 Stop */ + __IOM uint8_t SKEEP : 1; /*!< [1..1] STBY Keep */ + uint8_t : 6; + } HOCOLDOCR_b; + }; + __IM uint8_t RESERVED193; + __IM uint16_t RESERVED194; + + union + { + __IOM uint8_t MOMCR2; /*!< (@ 0x00000B10) Main Clock Oscillator Mode Oscillation Control + * Register 2 */ + + struct + { + __IOM uint8_t MOMODE : 1; /*!< [0..0] Main Clock Oscillator Mode Select */ + uint8_t : 7; + } MOMCR2_b; + }; + __IM uint8_t RESERVED195; + __IM uint16_t RESERVED196; + __IM uint32_t RESERVED197[3]; + + union + { + __IOM uint8_t LVD1FCR; /*!< (@ 0x00000B20) Voltage Monitor 1 Function Control Register */ + + struct + { + __IOM uint8_t RHSEL : 1; /*!< [0..0] Rise Hysteresis Select */ + uint8_t : 7; + } LVD1FCR_b; + }; + __IM uint8_t RESERVED198; + __IM uint16_t RESERVED199; + + union + { + __IOM uint8_t LVD2FCR; /*!< (@ 0x00000B24) Voltage Monitor 2 Function Control Register */ + + struct + { + __IOM uint8_t RHSEL : 1; /*!< [0..0] Rise Hysteresis Select */ + uint8_t : 7; + } LVD2FCR_b; + }; + __IM uint8_t RESERVED200; + __IM uint16_t RESERVED201; + + union + { + __IOM uint8_t LVD3FCR; /*!< (@ 0x00000B28) Voltage Monitor 3 Function Control Register */ + + struct + { + __IOM uint8_t RHSEL : 1; /*!< [0..0] Rise Hysteresis Select */ + uint8_t : 7; + } LVD3FCR_b; + }; + __IM uint8_t RESERVED202; + __IM uint16_t RESERVED203; + + union + { + __IOM uint8_t LVD4FCR; /*!< (@ 0x00000B2C) Voltage Monitor 4 Function Control Register */ + + struct + { + __IOM uint8_t RHSEL : 1; /*!< [0..0] Rise Hysteresis Select */ + uint8_t : 7; + } LVD4FCR_b; + }; + __IM uint8_t RESERVED204; + __IM uint16_t RESERVED205; + + union + { + __IOM uint8_t LVD5FCR; /*!< (@ 0x00000B30) Voltage Monitor 5 Function Control Register */ + + struct + { + __IOM uint8_t RHSEL : 1; /*!< [0..0] Rise Hysteresis Select */ + uint8_t : 7; + } LVD5FCR_b; + }; + __IM uint8_t RESERVED206; + __IM uint16_t RESERVED207; + + union + { + __IOM uint8_t PVDLR; /*!< (@ 0x00000B34) Voltage Monitor Lock Register */ + + struct + { + __IOM uint8_t LOCK : 1; /*!< [0..0] LOCK control */ + uint8_t : 7; + } PVDLR_b; + }; + __IM uint8_t RESERVED208; + __IM uint16_t RESERVED209; + __IM uint32_t RESERVED210[2]; + + union + { + __IOM uint8_t DPSIER4; /*!< (@ 0x00000B40) Deep Standby Interrupt Enable Register 4 */ + + struct + { + __IOM uint8_t DIRQ16E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ17E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ18E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ19E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ20E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ21E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ22E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ23E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER4_b; + }; + __IM uint8_t RESERVED211; + __IM uint16_t RESERVED212; + + union + { + __IOM uint8_t DPSIER5; /*!< (@ 0x00000B44) Deep Standby Interrupt Enable Register 5 */ + + struct + { + __IOM uint8_t DIRQ24E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ25E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ26E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ27E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ28E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ29E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ30E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ31E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER5_b; + }; + __IM uint8_t RESERVED213; + __IM uint16_t RESERVED214; + + union + { + __IOM uint8_t DPSIFR4; /*!< (@ 0x00000B48) Deep Standby Interrupt Flag Register 4 */ + + struct + { + __IOM uint8_t DIRQ16F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ17F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ18F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ19F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ20F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ21F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ22F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ23F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR4_b; + }; + __IM uint8_t RESERVED215; + __IM uint16_t RESERVED216; + + union + { + __IOM uint8_t DPSIFR5; /*!< (@ 0x00000B4C) Deep Standby Interrupt Flag Register 5 */ + + struct + { + __IOM uint8_t DIRQ24F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ25F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ26F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ27F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ28F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ29F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ30F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ31F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR5_b; + }; + __IM uint8_t RESERVED217; + __IM uint16_t RESERVED218; + + union + { + __IOM uint8_t DPSIEGR4; /*!< (@ 0x00000B50) Deep Standby Interrupt Edge Register 4 */ + + struct + { + __IOM uint8_t DIRQ24EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ25EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ26EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ27EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ28EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ29EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ30EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ31EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR4_b; + }; + __IM uint8_t RESERVED219; + __IM uint16_t RESERVED220; + __IM uint32_t RESERVED221[3]; + + union + { + __IOM uint8_t VBTSWMON; /*!< (@ 0x00000B60) LVDVBATSW control Monitor Register */ + + struct + { + __IOM uint8_t VLVLMON : 3; /*!< [2..0] VDETBAT Level Monitor */ + uint8_t : 1; + __IOM uint8_t VDETEMON : 1; /*!< [4..4] Voltage drop detection enable Monitor */ + uint8_t : 3; + } VBTSWMON_b; + }; + __IM uint8_t RESERVED222; + __IM uint16_t RESERVED223; + + union + { + __IOM uint8_t VBTSWSCR; /*!< (@ 0x00000B64) LVDVBATSW Start-up stable wait Control Register */ + + struct + { + __IOM uint8_t VBTSWE : 1; /*!< [0..0] LVDVBATSW output enable */ + uint8_t : 7; + } VBTSWSCR_b; + }; + __IM uint8_t RESERVED224; + __IM uint16_t RESERVED225; + __IM uint32_t RESERVED226[38]; + + union + { + __IOM uint8_t SOSCCR; /*!< (@ 0x00000C00) Sub-Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ + uint8_t : 7; + } SOSCCR_b; + }; + + union + { + __IOM uint8_t SOMCR; /*!< (@ 0x00000C01) Sub Clock Oscillator Mode Control Register */ + + struct + { + __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ + uint8_t : 4; + __IOM uint8_t SOSEL : 1; /*!< [6..6] Sub-Clock Oscillator Switching */ + uint8_t : 1; + } SOMCR_b; + }; + __IM uint16_t RESERVED227; + + union + { + __IOM uint8_t SOSTDCR; /*!< (@ 0x00000C04) Sub-clock Oscillation Stop Detection Control + * Register */ + + struct + { + __IOM uint8_t SOSTDIE : 1; /*!< [0..0] Sub-clock Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t SOSTDE : 1; /*!< [7..7] Sub-clock Oscillation Stop Detection Function Enable */ + } SOSTDCR_b; + }; + + union + { + __IOM uint8_t SOSTDSR; /*!< (@ 0x00000C05) Sub-clock Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t SOSTDF : 1; /*!< [0..0] Sub-clock Oscillation Stop Detection Flag */ + uint8_t : 7; + } SOSTDSR_b; + }; + __IM uint16_t RESERVED228; + __IM uint32_t RESERVED229[14]; + + union + { + __IOM uint8_t VBTBER; /*!< (@ 0x00000C40) VBATT Backup Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ + uint8_t : 4; + } VBTBER_b; + }; + __IM uint8_t RESERVED230; + __IM uint16_t RESERVED231; + __IM uint8_t RESERVED232; + + union + { + __IOM uint8_t VBTBPCR2; /*!< (@ 0x00000C45) VBATT Battery Power Supply Control Register 2 */ + + struct + { + __IOM uint8_t VDETLVL : 3; /*!< [2..0] VDETBAT Level Select */ + uint8_t : 1; + __IOM uint8_t VDETE : 1; /*!< [4..4] Voltage drop detection enable */ + uint8_t : 3; + } VBTBPCR2_b; + }; + + union + { + __IOM uint8_t VBTBPSR; /*!< (@ 0x00000C46) VBATT Battery Power Supply Status Register */ + + struct + { + __IOM uint8_t VBPORF : 1; /*!< [0..0] VBATT_POR Flag */ + uint8_t : 3; + __IOM uint8_t VBPORM : 1; /*!< [4..4] VBATT_POR Monitor */ + __IOM uint8_t BPWSWM : 1; /*!< [5..5] Battery Power Supply Switch Status Monitor */ + uint8_t : 2; + } VBTBPSR_b; + }; + __IM uint8_t RESERVED233; + + union + { + __IOM uint8_t VBTADSR; /*!< (@ 0x00000C48) VBATT Tamper detection Status Register */ + + struct + { + __IOM uint8_t VBTADF0 : 1; /*!< [0..0] VBATT Tamper Detection flag 0 */ + __IOM uint8_t VBTADF1 : 1; /*!< [1..1] VBATT Tamper Detection flag 1 */ + __IOM uint8_t VBTADF2 : 1; /*!< [2..2] VBATT Tamper Detection flag 2 */ + uint8_t : 5; + } VBTADSR_b; + }; + + union + { + __IOM uint8_t VBTADCR1; /*!< (@ 0x00000C49) VBATT Tamper detection Control Register 1 */ + + struct + { + __IOM uint8_t VBTADIE0 : 1; /*!< [0..0] VBATT Tamper Detection Interrupt Enable 0 */ + __IOM uint8_t VBTADIE1 : 1; /*!< [1..1] VBATT Tamper Detection Interrupt Enable 1 */ + __IOM uint8_t VBTADIE2 : 1; /*!< [2..2] VBATT Tamper Detection Interrupt Enable 2 */ + uint8_t : 1; + __IOM uint8_t VBTADCLE0 : 1; /*!< [4..4] VBATT Tamper Detection Backup Register Clear Enable 0 */ + __IOM uint8_t VBTADCLE1 : 1; /*!< [5..5] VBATT Tamper Detection Backup Register Clear Enable 1 */ + __IOM uint8_t VBTADCLE2 : 1; /*!< [6..6] VBATT Tamper Detection Backup Register Clear Enable 2 */ + uint8_t : 1; + } VBTADCR1_b; + }; + + union + { + __IOM uint8_t VBTADCR2; /*!< (@ 0x00000C4A) VBATT Tamper detection Control Register 2 */ + + struct + { + __IOM uint8_t VBRTCES0 : 1; /*!< [0..0] VBATT RTC Time Capture Event Source Select 0 */ + __IOM uint8_t VBRTCES1 : 1; /*!< [1..1] VBATT RTC Time Capture Event Source Select 1 */ + __IOM uint8_t VBRTCES2 : 1; /*!< [2..2] VBATT RTC Time Capture Event Source Select 2 */ + uint8_t : 5; + } VBTADCR2_b; + }; + __IM uint8_t RESERVED234; + + union + { + __IOM uint8_t VBTICTLR; /*!< (@ 0x00000C4C) VBATT Input Control Register */ + + struct + { + __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ + __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ + __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ + uint8_t : 5; + } VBTICTLR_b; + }; + + union + { + __IOM uint8_t VBTICTLR2; /*!< (@ 0x00000C4D) VBATT Input Control Register 2 */ + + struct + { + __IOM uint8_t VCH0NCE : 1; /*!< [0..0] VBATT CH0 Input Noise Canceler Enable */ + __IOM uint8_t VCH1NCE : 1; /*!< [1..1] VBATT CH1 Input Noise Canceler Enable */ + __IOM uint8_t VCH2NCE : 1; /*!< [2..2] VBATT CH2 Input Noise Canceler Enable */ + uint8_t : 1; + __IOM uint8_t VCH0EG : 1; /*!< [4..4] VBATT CH0 Input Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [5..5] VBATT CH1 Input Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [6..6] VBATT CH2 Input Edge Select */ + uint8_t : 1; + } VBTICTLR2_b; + }; + + union + { + __IOM uint8_t VBTIMONR; /*!< (@ 0x00000C4E) VBATT Input Monitor Register */ + + struct + { + __IOM uint8_t VCH0MON : 1; /*!< [0..0] VBATT CH0 Input monitor */ + __IOM uint8_t VCH1MON : 1; /*!< [1..1] VBATT CH1 Input monitor */ + __IOM uint8_t VCH2MON : 1; /*!< [2..2] VBATT CH2 Input monitor */ + uint8_t : 5; + } VBTIMONR_b; + }; + __IM uint8_t RESERVED235; + + union + { + __IOM uint8_t VBTNCWCR; /*!< (@ 0x00000C50) VBATT Noise Canceler Width Control Register */ + + struct + { + __IOM uint8_t VINCW : 3; /*!< [2..0] VBATT Input Noise Canceler Width select */ + uint8_t : 5; + } VBTNCWCR_b; + }; + __IM uint8_t RESERVED236; + __IM uint16_t RESERVED237; + + union + { + __IOM uint8_t VBTADCR3; /*!< (@ 0x00000C54) VBATT Tamper detection Control Register 3 */ + + struct + { + __IOM uint8_t VBTADZE0 : 1; /*!< [0..0] VBATT Tamper Detection Zeroization Enable 0 */ + __IOM uint8_t VBTADZE1 : 1; /*!< [1..1] VBATT Tamper Detection Zeroization Enable 1 */ + __IOM uint8_t VBTADZE2 : 1; /*!< [2..2] VBATT Tamper Detection Zeroization Enable 2 */ + uint8_t : 5; + } VBTADCR3_b; + }; + __IM uint8_t RESERVED238; + __IM uint16_t RESERVED239; + __IM uint32_t RESERVED240[42]; + + union + { + __IOM uint8_t VBTBKR[128]; /*!< (@ 0x00000D00) VBATT Backup Register [0..127] */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store + * data powered by VBATT.The value of this register is retained + * even when VCC is not powered but VBATT is powered.VBTBKR + * is initialized by VBATT selected voltage power-on-reset. */ + } VBTBKR_b[128]; + }; +} R_SYSTEM_Type; /*!< Size = 3456 (0xd80) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CAL) + */ + +typedef struct /*!< (@ 0x02C1EDA0) R_TSN_CAL Structure */ +{ + union + { + __IM uint32_t TSCDR; /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register */ + + struct + { + __IM uint32_t TSCDR : 32; /*!< [31..0] The 32 bit TSCDR register stores temperature sensor + * calibration converted value. */ + } TSCDR_b; + }; +} R_TSN_CAL_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CTRL) + */ + +typedef struct /*!< (@ 0x40235000) R_TSN_CTRL Structure */ +{ + union + { + __IOM uint8_t TSCR; /*!< (@ 0x00000000) Temperature Sensor Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t TSOE : 1; /*!< [4..4] Temperature Sensor Enable */ + uint8_t : 2; + __IOM uint8_t TSEN : 1; /*!< [7..7] Temperature Sensor Output Enable */ + } TSCR_b; + }; +} R_TSN_CTRL_Type; /*!< Size = 1 (0x1) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 Module (R_USB_FS0) + */ + +typedef struct /*!< (@ 0x40250000) R_USB_FS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 2; + __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */ + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + uint16_t : 1; + __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ + uint16_t : 1; + __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ + uint16_t : 5; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is + * used when switching from device B to device A while in + * OTG mode. If the HNPBTOA bit is 1, the internal function + * control keeps the suspended state until the HNP processing + * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is + * set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 4; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } DVCHGR_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate + * the USB address assigned by the host when the USBHS processed + * the SET_ADDRESS request successfully. */ + uint16_t : 1; + __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ + uint16_t : 4; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType + * value. */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount + * of data (maximum packet size) in payloads for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 2; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + + struct + { + __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ + uint16_t : 12; + } PIPESEL_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number + * for the selected pipe.Setting 0000b means unused pipe. */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + uint16_t : 1; + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to + * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes + * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and + * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to + * 64 bytes (040h) (Bits [8:7] are not provided.) */ + uint16_t : 3; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval + * error detection timing for the selected pipe in terms of + * frames, which is expressed as nth power of 2. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */ + + struct + { + __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */ + __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */ + __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ + __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */ + uint16_t : 1; + __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ + __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */ + __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */ + uint16_t : 6; + } USBBCCTRL0_b; + }; + __IM uint16_t RESERVED16; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */ + + struct + { + __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */ + uint16_t : 15; + } UCKSEL_b; + }; + __IM uint16_t RESERVED18; + __IM uint32_t RESERVED19; + + union + { + __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */ + + struct + { + __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */ + uint16_t : 6; + __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */ + uint16_t : 8; + } USBMC_b; + }; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */ + + struct + { + __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */ + __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */ + uint32_t : 28; + } PHYSLEW_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED23[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED25[5]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; + __IM uint32_t RESERVED26[165]; + + union + { + __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin + * Monitor Register */ + + struct + { + __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */ + __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */ + uint32_t : 1; + __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */ + __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */ + uint32_t : 11; + __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ + __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */ + uint32_t : 2; + __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal + * of the USB. */ + __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal + * of the USB. */ + uint32_t : 1; + __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the + * USB. */ + uint32_t : 8; + } DPUSR0R_FS_b; + }; + + union + { + __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt + * Register */ + + struct + { + __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */ + __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */ + uint32_t : 2; + __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */ + __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */ + uint32_t : 1; + __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */ + uint32_t : 8; + __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */ + __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */ + uint32_t : 2; + __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */ + __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */ + uint32_t : 1; + __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */ + uint32_t : 8; + } DPUSR1R_FS_b; + }; +} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */ + +/* =========================================================================================================================== */ +/* ================ R_VIN ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Video Input Module (R_VIN) + */ + +typedef struct /*!< (@ 0x40347400) R_VIN Structure */ +{ + union + { + __IOM uint32_t MC; /*!< (@ 0x00000000) Main Control Register */ + + struct + { + __IOM uint32_t ME : 1; /*!< [0..0] Module Enable */ + __IOM uint32_t BPS : 1; /*!< [1..1] Color Space Conversion Bypass Mode */ + uint32_t : 1; + __IOM uint32_t IM : 2; /*!< [4..3] Interlace Mode */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [6..6] Endian Type */ + uint32_t : 7; + __IOM uint32_t DC : 2; /*!< [15..14] Dithering Mode Control */ + __IOM uint32_t INF : 3; /*!< [18..16] Input Interface Format */ + uint32_t : 1; + __IOM uint32_t LUTE : 1; /*!< [20..20] Lookup Table Enable */ + uint32_t : 1; + __OM uint32_t ST : 1; /*!< [22..22] Initialization control at STartup */ + uint32_t : 1; + __IOM uint32_t DC2 : 1; /*!< [24..24] Dithering mode Control 2 */ + __IOM uint32_t YUV444 : 1; /*!< [25..25] YUV444 conversion */ + __IOM uint32_t SCLE : 1; /*!< [26..26] This bit is used to enable or disable scaling by the + * UDS. */ + uint32_t : 1; + __IOM uint32_t CLP : 2; /*!< [29..28] Pixel Data Clipping */ + uint32_t : 2; + } MC_b; + }; + + union + { + __IM uint32_t MS; /*!< (@ 0x00000004) Module Status Register */ + + struct + { + __IM uint32_t CA : 1; /*!< [0..0] Video Capture Active Status */ + __IM uint32_t AV : 1; /*!< [1..1] Active Video Status */ + __IM uint32_t FS : 1; /*!< [2..2] Field Status */ + __IM uint32_t FBS : 2; /*!< [4..3] Frame Buffer Status */ + uint32_t : 11; + __IM uint32_t MA : 1; /*!< [16..16] External frame Memory capture Active status */ + uint32_t : 2; + __IM uint32_t FMS : 2; /*!< [20..19] External Frame Memory buffer Status */ + uint32_t : 11; + } MS_b; + }; + + union + { + __IOM uint32_t FC; /*!< (@ 0x00000008) Frame Capture Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC : 1; /*!< [1..1] Continuous Frame Capture Mode */ + uint32_t : 30; + } FC_b; + }; + + union + { + __IOM uint32_t SLPRC; /*!< (@ 0x0000000C) Start Line Pre-Clip Register */ + + struct + { + __IOM uint32_t SLPRC : 12; /*!< [11..0] Start Line PRe-Clip */ + uint32_t : 20; + } SLPRC_b; + }; + + union + { + __IOM uint32_t ELPRC; /*!< (@ 0x00000010) End Line Pre-Clip Register */ + + struct + { + __IOM uint32_t ELPRC : 12; /*!< [11..0] End Line PRe-Clip */ + uint32_t : 20; + } ELPRC_b; + }; + + union + { + __IOM uint32_t SPPRC; /*!< (@ 0x00000014) Start Pixel Pre-Clip Register */ + + struct + { + __IOM uint32_t SPPRC : 12; /*!< [11..0] Start Pixel Pre-Clip */ + uint32_t : 20; + } SPPRC_b; + }; + + union + { + __IOM uint32_t EPPRC; /*!< (@ 0x00000018) End Pixel Pre-Clip Register */ + + struct + { + __IOM uint32_t EPPRC : 12; /*!< [11..0] End Pixel PRe-Clip */ + uint32_t : 20; + } EPPRC_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CSI_IFMD; /*!< (@ 0x00000020) CSI2 Interface Mode Register */ + + struct + { + __IOM uint32_t VC_SEL : 4; /*!< [3..0] Virtual Channel SELect */ + uint32_t : 4; + __IOM uint32_t DT : 6; /*!< [13..8] Data Type select */ + uint32_t : 11; + __IOM uint32_t DES0 : 1; /*!< [25..25] Data Extension Select */ + uint32_t : 6; + } CSI_IFMD_b; + }; + + union + { + __IOM uint32_t CSIFLD; /*!< (@ 0x00000024) Field detection control Register */ + + struct + { + __IOM uint32_t FLD_EN : 1; /*!< [0..0] FieLD detect ENable */ + uint32_t : 3; + __IOM uint32_t FLD_SEL : 2; /*!< [5..4] even FieLD DETect SELect */ + uint32_t : 10; + __IOM uint32_t FLD_NUM : 1; /*!< [16..16] even FieLD NUMber setting */ + uint32_t : 15; + } CSIFLD_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t IS; /*!< (@ 0x0000002C) Image Stride Register */ + + struct + { + __IOM uint32_t IS : 13; /*!< [12..0] Image Stride (Setting unit: pixel) */ + uint32_t : 19; + } IS_b; + }; + + union + { + __IOM uint32_t MB1; /*!< (@ 0x00000030) Memory Base 1 Register */ + + struct + { + uint32_t : 7; + __IOM uint32_t MB1 : 25; /*!< [31..7] Memory Base Address 1 */ + } MB1_b; + }; + + union + { + __IOM uint32_t MB2; /*!< (@ 0x00000034) Memory Base 2 Register */ + + struct + { + uint32_t : 7; + __IOM uint32_t MB2 : 25; /*!< [31..7] Memory Base Address 2 */ + } MB2_b; + }; + + union + { + __IOM uint32_t MB3; /*!< (@ 0x00000038) Memory Base 3 Register */ + + struct + { + uint32_t : 7; + __IOM uint32_t MB3 : 25; /*!< [31..7] Memory Base Address 3 */ + } MB3_b; + }; + + union + { + __IM uint32_t LC; /*!< (@ 0x0000003C) Line Count Register */ + + struct + { + __IM uint32_t LC : 12; /*!< [11..0] Line Count */ + uint32_t : 20; + } LC_b; + }; + + union + { + __IOM uint32_t IE; /*!< (@ 0x00000040) Interrupt Enable Register */ + + struct + { + __IOM uint32_t FOE : 1; /*!< [0..0] FIFO Overflow Interrupt Enable */ + __IOM uint32_t EFE : 1; /*!< [1..1] End of Frame Interrupt Enable */ + __IOM uint32_t SIE : 1; /*!< [2..2] Scanline Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t FIE : 1; /*!< [4..4] Field Interrupt Enable */ + __IOM uint32_t FME : 1; /*!< [5..5] Frame Memory write completion interrupt Enable */ + uint32_t : 2; + __IOM uint32_t PRCLIPHEE : 1; /*!< [8..8] PRCLIPH Error interrupt Enable */ + __IOM uint32_t PRCLIPVEE : 1; /*!< [9..9] PRCLIPV Error interrupt Enable */ + uint32_t : 4; + __IOM uint32_t ROE : 1; /*!< [14..14] Response Overflow interrupt Enable */ + __IOM uint32_t AREE : 1; /*!< [15..15] Axi Resp Error interrupt Enable */ + __IOM uint32_t VRE : 1; /*!< [16..16] VSYNC Deasserting Detect Interrupt Enable */ + __IOM uint32_t VFE : 1; /*!< [17..17] Vsync asserting detect interrupt Enable */ + uint32_t : 13; + __IOM uint32_t FIE2 : 1; /*!< [31..31] Field Interrupt Enable 2 */ + } IE_b; + }; + + union + { + __IOM uint32_t INTS; /*!< (@ 0x00000044) Interrupt Status Register */ + + struct + { + __IOM uint32_t FOS : 1; /*!< [0..0] FIFO Overflow Interrupt Status */ + __IOM uint32_t EFS : 1; /*!< [1..1] End of Frame Interrupt Status */ + __IOM uint32_t SIS : 1; /*!< [2..2] Scanline Interrupt Status */ + uint32_t : 1; + __IOM uint32_t FIS : 1; /*!< [4..4] Field Interrupt Status */ + __IOM uint32_t FMS : 1; /*!< [5..5] Frame Memory write completion interrupt Status */ + uint32_t : 2; + __IOM uint32_t PRCLIPHES : 1; /*!< [8..8] PRCLIPH Error interrupt Status */ + __IOM uint32_t PRCLIPVES : 1; /*!< [9..9] PRCLIPV Error interrupt Status */ + uint32_t : 4; + __IOM uint32_t ROS : 1; /*!< [14..14] Response Overflow interrupt Status */ + __IOM uint32_t ARES : 1; /*!< [15..15] Axi Resp Error interrupt Status */ + __IOM uint32_t VRS : 1; /*!< [16..16] VSYNC Deasserting Detect Interrupt Status */ + __IOM uint32_t VFS : 1; /*!< [17..17] VSYNC Asserting Detect Interrupt Status */ + uint32_t : 13; + __IOM uint32_t FIS2 : 1; /*!< [31..31] Field Interrupt Status 2 */ + } INTS_b; + }; + + union + { + __IOM uint32_t SI; /*!< (@ 0x00000048) Scanline Interrupt Register */ + + struct + { + __IOM uint32_t SI : 12; /*!< [11..0] Scanline Interrupt Setting */ + uint32_t : 20; + } SI_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t MTCSTOP; /*!< (@ 0x00000054) AXI transfer stop control register */ + + struct + { + __IOM uint32_t STOPREQ : 1; /*!< [0..0] axi forced STOP REQuest */ + __IM uint32_t STOPACK : 1; /*!< [1..1] for axi forced STOP request, ACKnowledgement */ + uint32_t : 14; + __IM uint32_t OUTSTAND : 6; /*!< [21..16] OUTSTANDing current number */ + uint32_t : 10; + } MTCSTOP_b; + }; + + union + { + __IOM uint32_t DMR; /*!< (@ 0x00000058) Data Mode Register */ + + struct + { + __IOM uint32_t DTMD : 2; /*!< [1..0] Data Conversion Mode */ + __IOM uint32_t ABIT : 1; /*!< [2..2] Alpha Bit */ + uint32_t : 1; + __IOM uint32_t BPSM : 1; /*!< [4..4] Output Data Byte Swap Mode */ + uint32_t : 3; + __IOM uint32_t EXRGB : 1; /*!< [8..8] Extension RGB Conversion Mode */ + uint32_t : 2; + __IOM uint32_t YC_THR : 1; /*!< [11..11] YC Data Through Mode */ + __IOM uint32_t YMODE : 3; /*!< [14..12] YC Data Transfer Mode */ + uint32_t : 9; + __IOM uint32_t A8BIT : 8; /*!< [31..24] Alpha 8 */ + } DMR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t UVAOF; /*!< (@ 0x00000060) UV Address Offset Register */ + + struct + { + uint32_t : 7; + __IOM uint32_t UVAOF : 25; /*!< [31..7] UV Data Address Offset */ + } UVAOF_b; + }; + __IM uint32_t RESERVED4[7]; + + union + { + __IOM uint32_t UDS_CTRL; /*!< (@ 0x00000080) Scaling Control Registers */ + + struct + { + uint32_t : 16; + __IOM uint32_t NE_BCB : 1; /*!< [16..16] B/Cb Interpolation Method When Bilinear/Nearest Neighbor + * Interpolation is Selected */ + __IOM uint32_t NE_GY : 1; /*!< [17..17] G/Y Interpolation Method When Bilinear/Nearest Neighbor + * Interpolation is Selected */ + __IOM uint32_t NE_RCR : 1; /*!< [18..18] R/Cr Interpolation Method When Bilinear/Nearest Neighbor + * Interpolation is Selected */ + uint32_t : 1; + __IOM uint32_t BC : 1; /*!< [20..20] Pixel Component Interpolation Method at Scale-Up/Down */ + uint32_t : 7; + __IOM uint32_t BLADV : 1; /*!< [28..28] BiLinear or nearest neighbor interpolation characteristic + * ADVanced mode */ + uint32_t : 1; + __IOM uint32_t AMD : 1; /*!< [30..30] Advanced MoDe: Pixel Count at Scale-Up */ + uint32_t : 1; + } UDS_CTRL_b; + }; + + union + { + __IOM uint32_t UDS_SCALE; /*!< (@ 0x00000084) Scaling Factor Registers */ + + struct + { + __IOM uint32_t VFRAC : 12; /*!< [11..0] Multiplier (Fractional Part) of Vertical Scaling Factor */ + __IOM uint32_t VMANT : 4; /*!< [15..12] Multiplier (Integral Part) of Vertical Scaling Factor */ + __IOM uint32_t HFRAC : 12; /*!< [27..16] Multiplier (Fractional Part) of Horizontal Scaling + * Factor */ + __IOM uint32_t HMANT : 4; /*!< [31..28] Multiplier (Integral Part) of Horizontal Scaling Factor */ + } UDS_SCALE_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t UDS_PASS_BWIDTH; /*!< (@ 0x00000090) Passband Registers */ + + struct + { + __IOM uint32_t BWIDTH_V : 7; /*!< [6..0] Vertical Signal Passband at Image Scale-Up/Down */ + uint32_t : 9; + __IOM uint32_t BWIDTH_H : 7; /*!< [22..16] Horizontal Signal Passband at Image Scale-Up/Down */ + uint32_t : 9; + } UDS_PASS_BWIDTH_b; + }; + __IM uint32_t RESERVED6[4]; + + union + { + __IOM uint32_t UDS_CLIP_SIZE; /*!< (@ 0x000000A4) UDS Output Size Clipping Registers */ + + struct + { + __IOM uint32_t CL_VSIZE : 12; /*!< [11..0] Clipping Size of Vertical Pixel Count after Scale-Up/-Down */ + uint32_t : 4; + __IOM uint32_t CL_HSIZE : 12; /*!< [27..16] Clipping Size of Horizontal Pixel Count after Scale-Up/-Down */ + uint32_t : 4; + } UDS_CLIP_SIZE_b; + }; + __IM uint32_t RESERVED7[22]; + + union + { + __IOM uint32_t LUTP; /*!< (@ 0x00000100) Lookup Table Pointer Register */ + + struct + { + __IOM uint32_t LTCRPR : 10; /*!< [9..0] Lookup Table Cr Pointer */ + __IOM uint32_t LTCBPR : 10; /*!< [19..10] Lookup Table Cb Pointer */ + __IOM uint32_t LTYPR : 10; /*!< [29..20] Lookup Table Y Pointer */ + uint32_t : 2; + } LUTP_b; + }; + + union + { + __IOM uint32_t LUTD; /*!< (@ 0x00000104) Lookup Table Data Register */ + + struct + { + __IOM uint32_t LTCRDT : 8; /*!< [7..0] Lookup Table Cr Data */ + __IOM uint32_t LTCBDT : 8; /*!< [15..8] Lookup Table Cb Data */ + __IOM uint32_t LTYDT : 8; /*!< [23..16] Lookup Table Y Data */ + uint32_t : 8; + } LUTD_b; + }; + __IM uint32_t RESERVED8[72]; + + union + { + __IOM uint32_t YCCR1; /*!< (@ 0x00000228) RGB to Y Calculation Setting Register 1 */ + + struct + { + __IOM uint32_t YCLRP : 13; /*!< [12..0] R Multiplication Coefficient for Y Calculation */ + uint32_t : 19; + } YCCR1_b; + }; + + union + { + __IOM uint32_t YCCR2; /*!< (@ 0x0000022C) RGB to Y Calculation Setting Register 2 */ + + struct + { + __IOM uint32_t YCLGP : 13; /*!< [12..0] G Multiplication Coefficient for Y Calculation */ + uint32_t : 3; + __IOM uint32_t YCLBP : 13; /*!< [28..16] B Multiplication Coefficient for Y Calculation */ + uint32_t : 3; + } YCCR2_b; + }; + + union + { + __IOM uint32_t YCCR3; /*!< (@ 0x00000230) RGB to Y Calculation Setting Register 3 */ + + struct + { + __IOM uint32_t YCLAP : 12; /*!< [11..0] Y Calculation Data Normalized Additional Value */ + uint32_t : 11; + __IOM uint32_t YCLHEN : 1; /*!< [23..23] Y Calculation Shift Down Result Round-Off Enable */ + __IOM uint32_t YCLSFT : 5; /*!< [28..24] Y Calculation Shift Down Volume */ + uint32_t : 3; + } YCCR3_b; + }; + + union + { + __IOM uint32_t CBCCR1; /*!< (@ 0x00000234) RGB to Cb Calculation Setting Register 1 */ + + struct + { + __IOM uint32_t CBCLRP : 13; /*!< [12..0] R Multiplication Coefficient for Cb Calculation */ + uint32_t : 19; + } CBCCR1_b; + }; + + union + { + __IOM uint32_t CBCCR2; /*!< (@ 0x00000238) RGB to Cb Calculation Setting Register 2 */ + + struct + { + __IOM uint32_t CBCLGP : 13; /*!< [12..0] G Multiplication Coefficient for Cb Calculation */ + uint32_t : 3; + __IOM uint32_t CBCLBP : 13; /*!< [28..16] B Multiplication Coefficient for Cb Calculation */ + uint32_t : 3; + } CBCCR2_b; + }; + + union + { + __IOM uint32_t CBCCR3; /*!< (@ 0x0000023C) RGB to Cb Calculation Setting Register 3 */ + + struct + { + __IOM uint32_t CBCLAP : 12; /*!< [11..0] Cb Calculation Data Normalized Additional Value */ + uint32_t : 11; + __IOM uint32_t CBCLHEN : 1; /*!< [23..23] Cb Calculation Shift Down Result Round-Off Enable */ + __IOM uint32_t CBCLSFT : 5; /*!< [28..24] Cb Calculation Shift Down Volume */ + uint32_t : 3; + } CBCCR3_b; + }; + + union + { + __IOM uint32_t CRCCR1; /*!< (@ 0x00000240) RGB to Cr Calculation Setting Register 1 */ + + struct + { + __IOM uint32_t CRCLRP : 13; /*!< [12..0] R Multiplication Coefficient for Cr Calculation */ + uint32_t : 19; + } CRCCR1_b; + }; + + union + { + __IOM uint32_t CRCCR2; /*!< (@ 0x00000244) RGB to Cr Calculation Setting Register 2 */ + + struct + { + __IOM uint32_t CRCLGP : 13; /*!< [12..0] G Multiplication Coefficient for Cr Calculation */ + uint32_t : 3; + __IOM uint32_t CRCLBP : 13; /*!< [28..16] B Multiplication Coefficient for Cr Calculation */ + uint32_t : 3; + } CRCCR2_b; + }; + + union + { + __IOM uint32_t CRCCR3; /*!< (@ 0x00000248) RGB to Cr Calculation Setting Register 3 */ + + struct + { + __IOM uint32_t CRCLAP : 12; /*!< [11..0] Cr Calculation Data Normalized Additional Value */ + uint32_t : 11; + __IOM uint32_t CRCLHEN : 1; /*!< [23..23] Cr Calculation Shift Down Result Round-Off Enable */ + __IOM uint32_t CRCLSFT : 5; /*!< [28..24] Cr Calculation Shift Down Volume */ + uint32_t : 3; + } CRCCR3_b; + }; + __IM uint32_t RESERVED9[45]; + + union + { + __IOM uint32_t CSCE1; /*!< (@ 0x00000300) YC to RGB Calculation Setting Extension Register + * 1 */ + + struct + { + __IOM uint32_t YMUL2 : 14; /*!< [13..0] Y Multiplication Coefficient 2 for RGB Calculation */ + uint32_t : 2; + __IOM uint32_t ROUND : 1; /*!< [16..16] ROUND off enable */ + uint32_t : 15; + } CSCE1_b; + }; + + union + { + __IOM uint32_t CSCE2; /*!< (@ 0x00000304) YC to RGB Calculation Setting Extension Register + * 2 */ + + struct + { + __IOM uint32_t CSUB2 : 12; /*!< [11..0] CbCr Subtraction Coefficient 2 for RGB Calculation */ + uint32_t : 4; + __IOM uint32_t YSUB2 : 12; /*!< [27..16] Y Subtraction Coefficient 2 for RGB Calculation */ + uint32_t : 4; + } CSCE2_b; + }; + + union + { + __IOM uint32_t CSCE3; /*!< (@ 0x00000308) YC to RGB Calculation Setting Extension Register + * 3 */ + + struct + { + __IOM uint32_t GCRMUL2 : 14; /*!< [13..0] Cr Multiplication Coefficient 2 for G Calculation */ + uint32_t : 2; + __IOM uint32_t RCRMUL2 : 14; /*!< [29..16] Cr Multiplication Coefficient 2 for R Calculation */ + uint32_t : 2; + } CSCE3_b; + }; + + union + { + __IOM uint32_t CSCE4; /*!< (@ 0x0000030C) YC to RGB Calculation Setting Extension Register + * 4 */ + + struct + { + __IOM uint32_t BCBMUL2 : 14; /*!< [13..0] Cb Multiplication Coefficient 2 for B Calculation */ + uint32_t : 2; + __IOM uint32_t GCBMUL2 : 14; /*!< [29..16] Cb Multiplication Coefficient 2 for G Calculation */ + uint32_t : 2; + } CSCE4_b; + }; +} R_VIN_Type; /*!< Size = 784 (0x310) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer (R_WDT) + */ + +typedef struct /*!< (@ 0x40202600) R_WDT Structure */ +{ + union + { + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + + struct + { + __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter + * of the WDT. */ + } WDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } WDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_WDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU System Security Control Unit (R_CPSCU) + */ + +typedef struct /*!< (@ 0x40008000) R_CPSCU Structure */ +{ + union + { + __IOM uint32_t CSAR; /*!< (@ 0x00000000) Cache Security Attribution Register */ + + struct + { + __IOM uint32_t CACHESA : 1; /*!< [0..0] Security Attributes of Registers for Cache Control */ + __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration */ + __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error */ + uint32_t : 29; + } CSAR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t SRAMSAR; /*!< (@ 0x00000010) SRAM Security Attribution Register */ + + struct + { + __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] SRAM0 Register Security Attribution */ + __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] SRAM1 Register Security Attribution */ + __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] SRAM2 Register Security Attribution */ + __IOM uint32_t SRAMSA3 : 1; /*!< [3..3] SRAM3 Register Security Attribution */ + uint32_t : 4; + __IOM uint32_t SRAMWTSA : 1; /*!< [8..8] Security attribution for SRAMWTSC */ + uint32_t : 23; + } SRAMSAR_b; + }; + + union + { + __IOM uint32_t STBRAMSAR; /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register */ + + struct + { + __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM */ + uint32_t : 28; + } STBRAMSAR_b; + }; + __IM uint32_t RESERVED1[6]; + + union + { + __IOM uint32_t DTCSAR; /*!< (@ 0x00000030) DTC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DTCSTSA0 : 1; /*!< [0..0] DTC0 Security Attribution */ + uint32_t : 15; + __IOM uint32_t DTCSTSA1 : 1; /*!< [16..16] DTC1 Security Attribution */ + uint32_t : 15; + } DTCSAR_b; + }; + + union + { + __IOM uint32_t DMACSAR; /*!< (@ 0x00000034) DMAC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DMASTSA0 : 1; /*!< [0..0] DMAC0 DMAST Security Attribution */ + uint32_t : 15; + __IOM uint32_t DMASTSA1 : 1; /*!< [16..16] DMAC1 DMAST Security Attribution */ + uint32_t : 15; + } DMACSAR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t ICUSARA; /*!< (@ 0x00000040) Interrupt Controller Unit Security Attribution + * Register A */ + + struct + { + __IOM uint32_t SAIRQCR0 : 1; /*!< [0..0] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR1 : 1; /*!< [1..1] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR2 : 1; /*!< [2..2] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR3 : 1; /*!< [3..3] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR4 : 1; /*!< [4..4] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR5 : 1; /*!< [5..5] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR6 : 1; /*!< [6..6] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR7 : 1; /*!< [7..7] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR8 : 1; /*!< [8..8] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR9 : 1; /*!< [9..9] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR10 : 1; /*!< [10..10] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR11 : 1; /*!< [11..11] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR12 : 1; /*!< [12..12] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR13 : 1; /*!< [13..13] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR14 : 1; /*!< [14..14] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR15 : 1; /*!< [15..15] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR16 : 1; /*!< [16..16] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR17 : 1; /*!< [17..17] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR18 : 1; /*!< [18..18] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR19 : 1; /*!< [19..19] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR20 : 1; /*!< [20..20] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR21 : 1; /*!< [21..21] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR22 : 1; /*!< [22..22] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR23 : 1; /*!< [23..23] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR24 : 1; /*!< [24..24] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR25 : 1; /*!< [25..25] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR26 : 1; /*!< [26..26] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR27 : 1; /*!< [27..27] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR28 : 1; /*!< [28..28] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR29 : 1; /*!< [29..29] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR30 : 1; /*!< [30..30] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR31 : 1; /*!< [31..31] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + } ICUSARA_b; + }; + + union + { + __IOM uint32_t ICUSARB; /*!< (@ 0x00000044) Interrupt Controller Unit Security Attribution + * Register B */ + + struct + { + __IOM uint32_t SANMI0 : 1; /*!< [0..0] Security Attributes of registers */ + __IOM uint32_t SANMI1 : 1; /*!< [1..1] Security Attributes of registers */ + __IOM uint32_t SANMI2 : 1; /*!< [2..2] Security Attributes of registers */ + uint32_t : 29; + } ICUSARB_b; + }; + + union + { + __IOM uint32_t ICUSARC; /*!< (@ 0x00000048) ICU Security Attribution Register C */ + + struct + { + __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel */ + uint32_t : 24; + } ICUSARC_b; + }; + + union + { + __IOM uint32_t ICUSARD; /*!< (@ 0x0000004C) ICU Security Attribution Register D */ + + struct + { + __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0 */ + uint32_t : 31; + } ICUSARD_b; + }; + + union + { + __IOM uint32_t ICUSARE; /*!< (@ 0x00000050) Interrupt Controller Unit Security Attribution + * Register E */ + + struct + { + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security attributes of registers for WUPEN0.b16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b19 */ + __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security attributes of registers for WUPEN0.b20 */ + uint32_t : 3; + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security attributes of registers for WUPEN0.b24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security attributes of registers for WUPEN0.b25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security attributes of registers for WUPEN0.b27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security attributes of registers for WUPEN0.b28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security attributes of registers for WUPEN0.b29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security attributes of registers for WUPEN0.b30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security attributes of registers for WUPEN0.b31 */ + } ICUSARE_b; + }; + + union + { + __IOM uint32_t ICUSARF; /*!< (@ 0x00000054) Interrupt Controller Unit Security Attribution + * Register F */ + + struct + { + __IOM uint32_t SAAGT3UDWUP : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0 */ + __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ + __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ + __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b3 */ + uint32_t : 3; + __IOM uint32_t SASOSCWUP : 1; /*!< [7..7] Security attributes of registers for WUPEN1.b7 */ + __IOM uint32_t SAULP0UWUP : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b8 */ + __IOM uint32_t SAULP0AWUP : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b9 */ + __IOM uint32_t SAULP0BWUP : 1; /*!< [10..10] Security attributes of registers for WUPEN1.b10 */ + __IOM uint32_t SAI3CWUP : 1; /*!< [11..11] Security attributes of registers for WUPEN1.b11 */ + __IOM uint32_t SAULP1UWUP : 1; /*!< [12..12] Security attributes of registers for WUPEN1.b12 */ + __IOM uint32_t SAULP1AWUP : 1; /*!< [13..13] Security attributes of registers for WUPEN1.b13 */ + __IOM uint32_t SAULP1BWUP : 1; /*!< [14..14] Security attributes of registers for WUPEN1.b14 */ + __IOM uint32_t SAPDMWUP : 1; /*!< [15..15] Security attributes of registers for WUPEN1.b15 */ + uint32_t : 16; + } ICUSARF_b; + }; + __IM uint32_t RESERVED3[6]; + + union + { + __IOM uint32_t ICUSARG; /*!< (@ 0x00000070) Interrupt Controller Unit Security Attribution + * Register G */ + + struct + { + __IOM uint32_t SAIELSR0 : 1; /*!< [0..0] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR1 : 1; /*!< [1..1] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR2 : 1; /*!< [2..2] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR3 : 1; /*!< [3..3] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR4 : 1; /*!< [4..4] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR5 : 1; /*!< [5..5] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR6 : 1; /*!< [6..6] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR7 : 1; /*!< [7..7] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR8 : 1; /*!< [8..8] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR9 : 1; /*!< [9..9] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR10 : 1; /*!< [10..10] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR11 : 1; /*!< [11..11] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR12 : 1; /*!< [12..12] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR13 : 1; /*!< [13..13] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR14 : 1; /*!< [14..14] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR15 : 1; /*!< [15..15] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR16 : 1; /*!< [16..16] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR17 : 1; /*!< [17..17] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR18 : 1; /*!< [18..18] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR19 : 1; /*!< [19..19] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR20 : 1; /*!< [20..20] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR21 : 1; /*!< [21..21] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR22 : 1; /*!< [22..22] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR23 : 1; /*!< [23..23] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR24 : 1; /*!< [24..24] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR25 : 1; /*!< [25..25] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR26 : 1; /*!< [26..26] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR27 : 1; /*!< [27..27] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR28 : 1; /*!< [28..28] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR29 : 1; /*!< [29..29] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR30 : 1; /*!< [30..30] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR31 : 1; /*!< [31..31] Security attributes of registers for ICU0 event link + * setting0 */ + } ICUSARG_b; + }; + + union + { + __IOM uint32_t ICUSARH; /*!< (@ 0x00000074) Interrupt Controller Unit Security Attribution + * Register H */ + + struct + { + __IOM uint32_t SAIELSR32 : 1; /*!< [0..0] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR33 : 1; /*!< [1..1] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR34 : 1; /*!< [2..2] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR35 : 1; /*!< [3..3] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR36 : 1; /*!< [4..4] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR37 : 1; /*!< [5..5] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR38 : 1; /*!< [6..6] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR39 : 1; /*!< [7..7] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR40 : 1; /*!< [8..8] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR41 : 1; /*!< [9..9] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR42 : 1; /*!< [10..10] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR43 : 1; /*!< [11..11] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR44 : 1; /*!< [12..12] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR45 : 1; /*!< [13..13] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR46 : 1; /*!< [14..14] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR47 : 1; /*!< [15..15] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR48 : 1; /*!< [16..16] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR49 : 1; /*!< [17..17] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR50 : 1; /*!< [18..18] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR51 : 1; /*!< [19..19] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR52 : 1; /*!< [20..20] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR53 : 1; /*!< [21..21] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR54 : 1; /*!< [22..22] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR55 : 1; /*!< [23..23] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR56 : 1; /*!< [24..24] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR57 : 1; /*!< [25..25] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR58 : 1; /*!< [26..26] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR59 : 1; /*!< [27..27] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR60 : 1; /*!< [28..28] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR61 : 1; /*!< [29..29] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR62 : 1; /*!< [30..30] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR63 : 1; /*!< [31..31] Security attributes of registers for ICU0 event link + * setting1 */ + } ICUSARH_b; + }; + + union + { + __IOM uint32_t ICUSARI; /*!< (@ 0x00000078) Interrupt Controller Unit Security Attribution + * Register I */ + + struct + { + __IOM uint32_t SAIELSR64 : 1; /*!< [0..0] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR65 : 1; /*!< [1..1] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR66 : 1; /*!< [2..2] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR67 : 1; /*!< [3..3] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR68 : 1; /*!< [4..4] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR69 : 1; /*!< [5..5] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR70 : 1; /*!< [6..6] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR71 : 1; /*!< [7..7] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR72 : 1; /*!< [8..8] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR73 : 1; /*!< [9..9] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR74 : 1; /*!< [10..10] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR75 : 1; /*!< [11..11] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR76 : 1; /*!< [12..12] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR77 : 1; /*!< [13..13] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR78 : 1; /*!< [14..14] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR79 : 1; /*!< [15..15] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR80 : 1; /*!< [16..16] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR81 : 1; /*!< [17..17] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR82 : 1; /*!< [18..18] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR83 : 1; /*!< [19..19] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR84 : 1; /*!< [20..20] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR85 : 1; /*!< [21..21] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR86 : 1; /*!< [22..22] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR87 : 1; /*!< [23..23] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR88 : 1; /*!< [24..24] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR89 : 1; /*!< [25..25] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR90 : 1; /*!< [26..26] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR91 : 1; /*!< [27..27] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR92 : 1; /*!< [28..28] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR93 : 1; /*!< [29..29] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR94 : 1; /*!< [30..30] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR95 : 1; /*!< [31..31] Security attributes of registers for ICU0 event link + * setting2 */ + } ICUSARI_b; + }; + + union + { + __IOM uint32_t ICUSARJ; /*!< (@ 0x0000007C) Interrupt Controller Unit Security Attribution + * Register J */ + + struct + { + __IOM uint32_t SAIELSR0 : 1; /*!< [0..0] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR1 : 1; /*!< [1..1] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR2 : 1; /*!< [2..2] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR3 : 1; /*!< [3..3] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR4 : 1; /*!< [4..4] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR5 : 1; /*!< [5..5] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR6 : 1; /*!< [6..6] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR7 : 1; /*!< [7..7] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR8 : 1; /*!< [8..8] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR9 : 1; /*!< [9..9] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR10 : 1; /*!< [10..10] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR11 : 1; /*!< [11..11] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR12 : 1; /*!< [12..12] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR13 : 1; /*!< [13..13] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR14 : 1; /*!< [14..14] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR15 : 1; /*!< [15..15] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR16 : 1; /*!< [16..16] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR17 : 1; /*!< [17..17] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR18 : 1; /*!< [18..18] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR19 : 1; /*!< [19..19] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR20 : 1; /*!< [20..20] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR21 : 1; /*!< [21..21] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR22 : 1; /*!< [22..22] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR23 : 1; /*!< [23..23] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR24 : 1; /*!< [24..24] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR25 : 1; /*!< [25..25] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR26 : 1; /*!< [26..26] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR27 : 1; /*!< [27..27] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR28 : 1; /*!< [28..28] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR29 : 1; /*!< [29..29] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR30 : 1; /*!< [30..30] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR31 : 1; /*!< [31..31] Security attributes of registers for ICU1 event link + * setting0 */ + } ICUSARJ_b; + }; + + union + { + __IOM uint32_t ICUSARK; /*!< (@ 0x00000080) Interrupt Controller Unit Security Attribution + * Register K */ + + struct + { + __IOM uint32_t SAIELSR32 : 1; /*!< [0..0] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR33 : 1; /*!< [1..1] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR34 : 1; /*!< [2..2] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR35 : 1; /*!< [3..3] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR36 : 1; /*!< [4..4] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR37 : 1; /*!< [5..5] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR38 : 1; /*!< [6..6] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR39 : 1; /*!< [7..7] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR40 : 1; /*!< [8..8] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR41 : 1; /*!< [9..9] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR42 : 1; /*!< [10..10] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR43 : 1; /*!< [11..11] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR44 : 1; /*!< [12..12] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR45 : 1; /*!< [13..13] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR46 : 1; /*!< [14..14] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR47 : 1; /*!< [15..15] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR48 : 1; /*!< [16..16] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR49 : 1; /*!< [17..17] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR50 : 1; /*!< [18..18] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR51 : 1; /*!< [19..19] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR52 : 1; /*!< [20..20] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR53 : 1; /*!< [21..21] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR54 : 1; /*!< [22..22] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR55 : 1; /*!< [23..23] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR56 : 1; /*!< [24..24] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR57 : 1; /*!< [25..25] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR58 : 1; /*!< [26..26] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR59 : 1; /*!< [27..27] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR60 : 1; /*!< [28..28] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR61 : 1; /*!< [29..29] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR62 : 1; /*!< [30..30] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR63 : 1; /*!< [31..31] Security attributes of registers for ICU1 event link + * setting1 */ + } ICUSARK_b; + }; + + union + { + __IOM uint32_t ICUSARL; /*!< (@ 0x00000084) Interrupt Controller Unit Security Attribution + * Register L */ + + struct + { + __IOM uint32_t SAIELSR64 : 1; /*!< [0..0] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR65 : 1; /*!< [1..1] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR66 : 1; /*!< [2..2] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR67 : 1; /*!< [3..3] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR68 : 1; /*!< [4..4] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR69 : 1; /*!< [5..5] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR70 : 1; /*!< [6..6] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR71 : 1; /*!< [7..7] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR72 : 1; /*!< [8..8] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR73 : 1; /*!< [9..9] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR74 : 1; /*!< [10..10] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR75 : 1; /*!< [11..11] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR76 : 1; /*!< [12..12] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR77 : 1; /*!< [13..13] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR78 : 1; /*!< [14..14] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR79 : 1; /*!< [15..15] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR80 : 1; /*!< [16..16] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR81 : 1; /*!< [17..17] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR82 : 1; /*!< [18..18] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR83 : 1; /*!< [19..19] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR84 : 1; /*!< [20..20] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR85 : 1; /*!< [21..21] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR86 : 1; /*!< [22..22] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR87 : 1; /*!< [23..23] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR88 : 1; /*!< [24..24] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR89 : 1; /*!< [25..25] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR90 : 1; /*!< [26..26] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR91 : 1; /*!< [27..27] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR92 : 1; /*!< [28..28] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR93 : 1; /*!< [29..29] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR94 : 1; /*!< [30..30] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR95 : 1; /*!< [31..31] Security attributes of registers for ICU1 event link + * setting2 */ + } ICUSARL_b; + }; + __IM uint32_t RESERVED4[30]; + + union + { + __IOM uint32_t BUSSARA; /*!< (@ 0x00000100) Bus Security Attribution Register A */ + + struct + { + __IOM uint32_t BUSSA0 : 1; /*!< [0..0] Bus Security Attribution A0 */ + uint32_t : 31; + } BUSSARA_b; + }; + + union + { + __IOM uint32_t BUSSARB; /*!< (@ 0x00000104) Bus Security Attribution Register B */ + + struct + { + __IOM uint32_t BUSSB0 : 1; /*!< [0..0] Bus Security Attribution B0 */ + uint32_t : 31; + } BUSSARB_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t BUSSARC; /*!< (@ 0x00000110) Bus Security Attribution Register C */ + + struct + { + __IOM uint32_t BUSSC0 : 1; /*!< [0..0] Bus Security Attribution C0 */ + uint32_t : 31; + } BUSSARC_b; + }; + + union + { + __IOM uint32_t BUSPARC; /*!< (@ 0x00000114) Bus Privileged Attribution Register C */ + + struct + { + __IOM uint32_t BUSPA0 : 1; /*!< [0..0] External bus controller privilege attribution */ + uint32_t : 31; + } BUSPARC_b; + }; + __IM uint32_t RESERVED6[2]; + + union + { + __IM uint32_t NMISR; /*!< (@ 0x00000120) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint32_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Status Flag */ + __IM uint32_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Status Flag */ + __IM uint32_t PVD1ST : 1; /*!< [2..2] Voltage Monitor 1 Interrupt Status Flag */ + __IM uint32_t PVD2ST : 1; /*!< [3..3] Voltage Monitor 2 Interrupt Status Flag */ + uint32_t : 1; + __IM uint32_t SOSTST : 1; /*!< [5..5] Sub Oscillation Stop Detection Interrupt Status Flag */ + __IM uint32_t OSTST : 1; /*!< [6..6] Main Clock Oscillation Stop Detection Interrupt Status + * Flag */ + __IM uint32_t NMIST : 1; /*!< [7..7] NMI Pin Interrupt Status Flag */ + uint32_t : 4; + __IM uint32_t BUSST : 1; /*!< [12..12] Bus Error Interrupt Status Flag */ + __IM uint32_t CMST : 1; /*!< [13..13] Common Memory Error Interrupt Status Flag */ + __IM uint32_t LMST : 1; /*!< [14..14] Local Memory Error Interrupt Status Flag */ + __IM uint32_t LUST : 1; /*!< [15..15] LockUp Error Interrupt Status Flag */ + __IM uint32_t FPUEXCST : 1; /*!< [16..16] FPU Exception Interrupt Status Flag */ + __IM uint32_t MRCRDST : 1; /*!< [17..17] MRAM MRC read Error Interrupt Status Flag */ + __IM uint32_t MRERDST : 1; /*!< [18..18] MRAM MRE read Error Interrupt Status Flag */ + uint32_t : 1; + __IM uint32_t IPCST : 1; /*!< [20..20] IPC NMI CPU mutual Interrupt Status Flag */ + uint32_t : 11; + } NMISR_b; + }; + __IM uint32_t RESERVED7[3]; + + union + { + __IOM uint32_t MMPUSARA; /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution + * Register A */ + + struct + { + __IOM uint32_t MMPUASA0 : 1; /*!< [0..0] MMPUA0 Security Attribution */ + __IOM uint32_t MMPUASA1 : 1; /*!< [1..1] MMPUA1 Security Attribution */ + __IOM uint32_t MMPUASA2 : 1; /*!< [2..2] MMPUA2 Security Attribution */ + __IOM uint32_t MMPUASA3 : 1; /*!< [3..3] MMPUA3 Security Attribution */ + __IOM uint32_t MMPUASA4 : 1; /*!< [4..4] MMPUA4 Security Attribution */ + __IOM uint32_t MMPUASA5 : 1; /*!< [5..5] MMPUA5 Security Attribution */ + __IOM uint32_t MMPUASA6 : 1; /*!< [6..6] MMPUA6 Security Attribution */ + __IOM uint32_t MMPUASA7 : 1; /*!< [7..7] MMPUA7 Security Attribution */ + __IOM uint32_t MMPUASA8 : 1; /*!< [8..8] MMPUA8 Security Attribution */ + __IOM uint32_t MMPUASA9 : 1; /*!< [9..9] MMPUA9 Security Attribution */ + __IOM uint32_t MMPUASA10 : 1; /*!< [10..10] MMPUA10 Security Attribution */ + __IOM uint32_t MMPUASA11 : 1; /*!< [11..11] MMPUA11 Security Attribution */ + __IOM uint32_t MMPUASA12 : 1; /*!< [12..12] MMPUA12 Security Attribution */ + __IOM uint32_t MMPUASA13 : 1; /*!< [13..13] MMPUA13 Security Attribution */ + __IOM uint32_t MMPUASA14 : 1; /*!< [14..14] MMPUA14 Security Attribution */ + __IOM uint32_t MMPUASA15 : 1; /*!< [15..15] MMPUA15 Security Attribution */ + __IOM uint32_t MMPUASA16 : 1; /*!< [16..16] MMPUA16 Security Attribution */ + __IOM uint32_t MMPUASA17 : 1; /*!< [17..17] MMPUA17 Security Attribution */ + __IOM uint32_t MMPUASA18 : 1; /*!< [18..18] MMPUA18 Security Attribution */ + __IOM uint32_t MMPUASA19 : 1; /*!< [19..19] MMPUA19 Security Attribution */ + __IOM uint32_t MMPUASA20 : 1; /*!< [20..20] MMPUA20 Security Attribution */ + __IOM uint32_t MMPUASA21 : 1; /*!< [21..21] MMPUA21 Security Attribution */ + __IOM uint32_t MMPUASA22 : 1; /*!< [22..22] MMPUA22 Security Attribution */ + __IOM uint32_t MMPUASA23 : 1; /*!< [23..23] MMPUA23 Security Attribution */ + __IOM uint32_t MMPUASA24 : 1; /*!< [24..24] MMPUA24 Security Attribution */ + __IOM uint32_t MMPUASA25 : 1; /*!< [25..25] MMPUA25 Security Attribution */ + __IOM uint32_t MMPUASA26 : 1; /*!< [26..26] MMPUA26 Security Attribution */ + __IOM uint32_t MMPUASA27 : 1; /*!< [27..27] MMPUA27 Security Attribution */ + __IOM uint32_t MMPUASA28 : 1; /*!< [28..28] MMPUA28 Security Attribution */ + __IOM uint32_t MMPUASA29 : 1; /*!< [29..29] MMPUA29 Security Attribution */ + __IOM uint32_t MMPUASA30 : 1; /*!< [30..30] MMPUA30 Security Attribution */ + __IOM uint32_t MMPUASA31 : 1; /*!< [31..31] MMPUA31 Security Attribution */ + } MMPUSARA_b; + }; + + union + { + __IOM uint32_t MMPUSARB; /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution + * Register B */ + + struct + { + __IOM uint32_t MMPUBSA0 : 1; /*!< [0..0] MMPUB0 Security Attribution */ + __IOM uint32_t MMPUBSA1 : 1; /*!< [1..1] MMPUB1 Security Attribution */ + __IOM uint32_t MMPUBSA2 : 1; /*!< [2..2] MMPUB2 Security Attribution */ + __IOM uint32_t MMPUBSA3 : 1; /*!< [3..3] MMPUB3 Security Attribution */ + __IOM uint32_t MMPUBSA4 : 1; /*!< [4..4] MMPUB4 Security Attribution */ + __IOM uint32_t MMPUBSA5 : 1; /*!< [5..5] MMPUB5 Security Attribution */ + __IOM uint32_t MMPUBSA6 : 1; /*!< [6..6] MMPUB6 Security Attribution */ + __IOM uint32_t MMPUBSA7 : 1; /*!< [7..7] MMPUB7 Security Attribution */ + __IOM uint32_t MMPUBSA8 : 1; /*!< [8..8] MMPUB8 Security Attribution */ + __IOM uint32_t MMPUBSA9 : 1; /*!< [9..9] MMPUB9 Security Attribution */ + __IOM uint32_t MMPUBSA10 : 1; /*!< [10..10] MMPUB10 Security Attribution */ + __IOM uint32_t MMPUBSA11 : 1; /*!< [11..11] MMPUB11 Security Attribution */ + __IOM uint32_t MMPUBSA12 : 1; /*!< [12..12] MMPUB12 Security Attribution */ + __IOM uint32_t MMPUBSA13 : 1; /*!< [13..13] MMPUB13 Security Attribution */ + __IOM uint32_t MMPUBSA14 : 1; /*!< [14..14] MMPUB14 Security Attribution */ + __IOM uint32_t MMPUBSA15 : 1; /*!< [15..15] MMPUB15 Security Attribution */ + __IOM uint32_t MMPUBSA16 : 1; /*!< [16..16] MMPUB16 Security Attribution */ + __IOM uint32_t MMPUBSA17 : 1; /*!< [17..17] MMPUB17 Security Attribution */ + __IOM uint32_t MMPUBSA18 : 1; /*!< [18..18] MMPUB18 Security Attribution */ + __IOM uint32_t MMPUBSA19 : 1; /*!< [19..19] MMPUB19 Security Attribution */ + __IOM uint32_t MMPUBSA20 : 1; /*!< [20..20] MMPUB20 Security Attribution */ + __IOM uint32_t MMPUBSA21 : 1; /*!< [21..21] MMPUB21 Security Attribution */ + __IOM uint32_t MMPUBSA22 : 1; /*!< [22..22] MMPUB22 Security Attribution */ + __IOM uint32_t MMPUBSA23 : 1; /*!< [23..23] MMPUB23 Security Attribution */ + __IOM uint32_t MMPUBSA24 : 1; /*!< [24..24] MMPUB24 Security Attribution */ + __IOM uint32_t MMPUBSA25 : 1; /*!< [25..25] MMPUB25 Security Attribution */ + __IOM uint32_t MMPUBSA26 : 1; /*!< [26..26] MMPUB26 Security Attribution */ + __IOM uint32_t MMPUBSA27 : 1; /*!< [27..27] MMPUB27 Security Attribution */ + __IOM uint32_t MMPUBSA28 : 1; /*!< [28..28] MMPUB28 Security Attribution */ + __IOM uint32_t MMPUBSA29 : 1; /*!< [29..29] MMPUB29 Security Attribution */ + __IOM uint32_t MMPUBSA30 : 1; /*!< [30..30] MMPUB30 Security Attribution */ + __IOM uint32_t MMPUBSA31 : 1; /*!< [31..31] MMPUB31 Security Attribution */ + } MMPUSARB_b; + }; + __IM uint32_t RESERVED8[14]; + + union + { + __IOM uint32_t CPUSAR; /*!< (@ 0x00000170) CPU Security Attribution Register */ + + struct + { + __IOM uint32_t CPUSA0 : 1; /*!< [0..0] CPU Security Attribution 0 */ + __IOM uint32_t CPUSA1 : 1; /*!< [1..1] CPU Security Attribution 1 */ + uint32_t : 30; + } CPUSAR_b; + }; + __IM uint32_t RESERVED9[3]; + + union + { + __IOM uint32_t DEBUGSAR; /*!< (@ 0x00000180) Debug Security Attribution Register */ + + struct + { + __IOM uint32_t DBGSA0 : 1; /*!< [0..0] Debug Security Attribution 0 */ + uint32_t : 31; + } DEBUGSAR_b; + }; + __IM uint32_t RESERVED10[7]; + + union + { + __IOM uint32_t DMACCHSAR; /*!< (@ 0x000001A0) DMAC channel Security Attribution Register */ + + struct + { + __IOM uint32_t SADMAC00 : 1; /*!< [0..0] Security attributes of registers for DMAC0 channel */ + __IOM uint32_t SADMAC01 : 1; /*!< [1..1] Security attributes of registers for DMAC0 channel */ + __IOM uint32_t SADMAC02 : 1; /*!< [2..2] Security attributes of registers for DMAC0 channel */ + __IOM uint32_t SADMAC03 : 1; /*!< [3..3] Security attributes of registers for DMAC0 channel */ + __IOM uint32_t SADMAC04 : 1; /*!< [4..4] Security attributes of registers for DMAC0 channel */ + __IOM uint32_t SADMAC05 : 1; /*!< [5..5] Security attributes of registers for DMAC0 channel */ + __IOM uint32_t SADMAC06 : 1; /*!< [6..6] Security attributes of registers for DMAC0 channel */ + __IOM uint32_t SADMAC07 : 1; /*!< [7..7] Security attributes of registers for DMAC0 channel */ + uint32_t : 8; + __IOM uint32_t SADMAC10 : 1; /*!< [16..16] Security attributes of registers for DMAC1 channel */ + __IOM uint32_t SADMAC11 : 1; /*!< [17..17] Security attributes of registers for DMAC1 channel */ + __IOM uint32_t SADMAC12 : 1; /*!< [18..18] Security attributes of registers for DMAC1 channel */ + __IOM uint32_t SADMAC13 : 1; /*!< [19..19] Security attributes of registers for DMAC1 channel */ + __IOM uint32_t SADMAC14 : 1; /*!< [20..20] Security attributes of registers for DMAC1 channel */ + __IOM uint32_t SADMAC15 : 1; /*!< [21..21] Security attributes of registers for DMAC1 channel */ + __IOM uint32_t SADMAC16 : 1; /*!< [22..22] Security attributes of registers for DMAC1 channel */ + __IOM uint32_t SADMAC17 : 1; /*!< [23..23] Security attributes of registers for DMAC1 channel */ + uint32_t : 8; + } DMACCHSAR_b; + }; + __IM uint32_t RESERVED11[3]; + + union + { + __IOM uint32_t CPUDSAR; /*!< (@ 0x000001B0) CPU Debug Security Attribution Register */ + + struct + { + __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0 */ + uint32_t : 31; + } CPUDSAR_b; + }; + __IM uint32_t RESERVED12[15]; + + union + { + __IOM uint32_t DMACCHPAR; /*!< (@ 0x000001F0) DMA Channel Privilege Attribution Register */ + + struct + { + __IOM uint32_t PADMAC00 : 1; /*!< [0..0] Privilege attributes of outputs and registers for DMAC0 + * channel */ + __IOM uint32_t PADMAC01 : 1; /*!< [1..1] Privilege attributes of outputs and registers for DMAC0 + * channel */ + __IOM uint32_t PADMAC02 : 1; /*!< [2..2] Privilege attributes of outputs and registers for DMAC0 + * channel */ + __IOM uint32_t PADMAC03 : 1; /*!< [3..3] Privilege attributes of outputs and registers for DMAC0 + * channel */ + __IOM uint32_t PADMAC04 : 1; /*!< [4..4] Privilege attributes of outputs and registers for DMAC0 + * channel */ + __IOM uint32_t PADMAC05 : 1; /*!< [5..5] Privilege attributes of outputs and registers for DMAC0 + * channel */ + __IOM uint32_t PADMAC06 : 1; /*!< [6..6] Privilege attributes of outputs and registers for DMAC0 + * channel */ + __IOM uint32_t PADMAC07 : 1; /*!< [7..7] Privilege attributes of outputs and registers for DMAC0 + * channel */ + uint32_t : 8; + __IOM uint32_t PADMAC10 : 1; /*!< [16..16] Privilege attributes of outputs and registers for DMAC1 + * channel */ + __IOM uint32_t PADMAC11 : 1; /*!< [17..17] Privilege attributes of outputs and registers for DMAC1 + * channel */ + __IOM uint32_t PADMAC12 : 1; /*!< [18..18] Privilege attributes of outputs and registers for DMAC1 + * channel */ + __IOM uint32_t PADMAC13 : 1; /*!< [19..19] Privilege attributes of outputs and registers for DMAC1 + * channel */ + __IOM uint32_t PADMAC14 : 1; /*!< [20..20] Privilege attributes of outputs and registers for DMAC1 + * channel */ + __IOM uint32_t PADMAC15 : 1; /*!< [21..21] Privilege attributes of outputs and registers for DMAC1 + * channel */ + __IOM uint32_t PADMAC16 : 1; /*!< [22..22] Privilege attributes of outputs and registers for DMAC1 + * channel */ + __IOM uint32_t PADMAC17 : 1; /*!< [23..23] Privilege attributes of outputs and registers for DMAC1 + * channel */ + uint32_t : 8; + } DMACCHPAR_b; + }; + __IM uint32_t RESERVED13[131]; + + union + { + __IOM uint32_t SRAMSABAR0; /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure */ + uint32_t : 11; + } SRAMSABAR0_b; + }; + + union + { + __IOM uint32_t SRAMSABAR1; /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure */ + uint32_t : 11; + } SRAMSABAR1_b; + }; + + union + { + __IOM uint32_t SRAMSABAR2; /*!< (@ 0x00000408) SRAM Security Attribute Boundary Address Register */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure */ + uint32_t : 11; + } SRAMSABAR2_b; + }; + + union + { + __IOM uint32_t SRAMSABAR3; /*!< (@ 0x0000040C) SRAM Security Attribute Boundary Address Register */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure */ + uint32_t : 11; + } SRAMSABAR3_b; + }; + __IM uint32_t RESERVED14[60]; + + union + { + __IOM uint32_t CACHESAR; /*!< (@ 0x00000500) Cache Security Attribution Register */ + + struct + { + __IOM uint32_t CACHESA : 1; /*!< [0..0] Security attributes of registers for CACHE Control */ + uint32_t : 1; + __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security attributes of registers for CACHE Error */ + uint32_t : 29; + } CACHESAR_b; + }; + + union + { + __IOM uint32_t TCMSAR; /*!< (@ 0x00000504) TCM Security Attribution Register */ + + struct + { + __IOM uint32_t TCMSA : 1; /*!< [0..0] Security attributes of registers for TCM Control */ + uint32_t : 31; + } TCMSAR_b; + }; + + union + { + __IOM uint32_t TCMSABARC; /*!< (@ 0x00000508) TCM Security Attribute Boundary Address Register */ + + struct + { + uint32_t : 13; + __IOM uint32_t TCMSABA : 6; /*!< [18..13] Boundary address between secure and non-secure. (Start + * address of non-secure region) */ + uint32_t : 13; + } TCMSABARC_b; + }; + + union + { + __IOM uint32_t TCMSABARS; /*!< (@ 0x0000050C) TCM Security Attribute Boundary Address Register */ + + struct + { + uint32_t : 13; + __IOM uint32_t TCMSABA : 6; /*!< [18..13] Boundary address between secure and non-secure. (Start + * address of non-secure region) */ + uint32_t : 13; + } TCMSABARS_b; + }; + + union + { + __IOM uint32_t SRAMESAR; /*!< (@ 0x00000510) SRAM ECC region Security Attribute Register */ + + struct + { + __IOM uint32_t SRAMESA : 1; /*!< [0..0] ECC region Security Attribution */ + uint32_t : 31; + } SRAMESAR_b; + }; + __IM uint32_t RESERVED15[59]; + + union + { + __IOM uint32_t TEVTRCR; /*!< (@ 0x00000600) Trusted Event Route Control Register */ + + struct + { + __IOM uint32_t TEVTE : 1; /*!< [0..0] Trusted Event Route Control Register for ELC */ + __IOM uint32_t TEVTEICU0 : 1; /*!< [1..1] Trusted Event Route Control Register for ICU0 */ + __IOM uint32_t TEVTEICU1 : 1; /*!< [2..2] Trusted Event Route Control Register for ICU1 */ + uint32_t : 29; + } TEVTRCR_b; + }; + __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint32_t IPCSAR; /*!< (@ 0x00000610) IPC Security Attribution Register */ + + struct + { + __IOM uint32_t SAIPCSEM0 : 1; /*!< [0..0] Security attributes of registers for IPCSEMn */ + __IOM uint32_t SAIPCSEM1 : 1; /*!< [1..1] Security attributes of registers for IPCSEMn */ + uint32_t : 6; + __IOM uint32_t SAIPCNMI0 : 1; /*!< [8..8] Security attributes of the registers */ + __IOM uint32_t SAIPCNMI1 : 1; /*!< [9..9] Security attributes of the registers */ + uint32_t : 6; + __IOM uint32_t SAIPCIR0 : 1; /*!< [16..16] Security attributes of registers for IPC0STA0, IPC0ISET0, + * IPC0TXD0, IPC0RXD0 and IPC0CLR0 */ + __IOM uint32_t SAIPCIR1 : 1; /*!< [17..17] Security attributes of registers for IPC0STA1, IPC0ISET1, + * IPC0TXD1, IPC0RXD1 and IPC0CLR1 */ + __IOM uint32_t SAIPCIR2 : 1; /*!< [18..18] Security attributes of registers for IPC1STA0, IPC1ISET0, + * IPC1TXD0, IPC1RXD0 and IPC1CLR0 */ + __IOM uint32_t SAIPCIR3 : 1; /*!< [19..19] Security attributes of registers for IPC1STA1, IPC1ISET1, + * IPC1TXD1, IPC1RXD1 and IPC1CLR1 */ + uint32_t : 12; + } IPCSAR_b; + }; + + union + { + __IOM uint32_t IPCPAR; /*!< (@ 0x00000614) IPC Privileged Attribution Register */ + + struct + { + __IOM uint32_t PAIPCSEM0 : 1; /*!< [0..0] Privileged attributes of registers for IPCSEMn */ + __IOM uint32_t PAIPCSEM1 : 1; /*!< [1..1] Privileged attributes of registers for IPCSEMn */ + uint32_t : 6; + __IOM uint32_t PAIPCNMI0 : 1; /*!< [8..8] Privileged attributes of registers */ + __IOM uint32_t PAIPCNMI1 : 1; /*!< [9..9] Privileged attributes of registers */ + uint32_t : 6; + __IOM uint32_t PAIPCIR0 : 1; /*!< [16..16] Privileged attributes of registers for IPC0STA0, IPC0ISET0, + * IPC0TXD0, IPC0RXD0 and IPC0CLR0 */ + __IOM uint32_t PAIPCIR1 : 1; /*!< [17..17] Privileged attributes of registers for IPC0STA1, IPC0ISET1, + * IPC0TXD1, IPC0RXD1 and IPC0CLR1 */ + __IOM uint32_t PAIPCIR2 : 1; /*!< [18..18] Privileged attributes of registers for IPC1STA0, IPC1ISET0, + * IPC1TXD0, IPC1RXD0 and IPC1CLR0 */ + __IOM uint32_t PAIPCIR3 : 1; /*!< [19..19] Privileged attributes of registers for IPC1STA1, IPC1ISET1, + * IPC1TXD1, IPC1RXD1 and IPC1CLR1 */ + uint32_t : 12; + } IPCPAR_b; + }; +} R_CPSCU_Type; /*!< Size = 1560 (0x618) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC_B0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief 12-bit A/D Converter (R_ADC_B0) + */ + +typedef struct /*!< (@ 0x40338000) R_ADC_B0 Structure */ +{ + union + { + __IOM uint32_t ADCLKENR; /*!< (@ 0x00000000) A/D Conversion Clock Enable Register */ + + struct + { + __IOM uint32_t CLKEN : 1; /*!< [0..0] ADCLK Operating Enable bit */ + uint32_t : 31; + } ADCLKENR_b; + }; + + union + { + __IM uint32_t ADCLKSR; /*!< (@ 0x00000004) A/D Conversion Clock Status Register */ + + struct + { + __IM uint32_t CLKSR : 1; /*!< [0..0] ADCLK status bit */ + uint32_t : 31; + } ADCLKSR_b; + }; + + union + { + __IOM uint32_t ADCLKCR; /*!< (@ 0x00000008) A/D Conversion Clock Control Register */ + + struct + { + __IOM uint32_t CLKSEL : 2; /*!< [1..0] ADCLK Clock Source Select */ + uint32_t : 14; + __IOM uint32_t DIVR : 3; /*!< [18..16] Clock Division Ratio Select */ + uint32_t : 13; + } ADCLKCR_b; + }; + + union + { + __IOM uint32_t ADSYCR; /*!< (@ 0x0000000C) A/D Converter Synchronous Operation Control Register */ + + struct + { + __IOM uint32_t ADSYCYC : 11; /*!< [10..0] A/D Converter Synchronous Operation Period Cycle */ + uint32_t : 5; + __IOM uint32_t ADSYDIS0 : 1; /*!< [16..16] ADC0 Synchronous Operation Select */ + __IOM uint32_t ADSYDIS1 : 1; /*!< [17..17] ADC1 Synchronous Operation Select */ + uint32_t : 14; + } ADSYCR_b; + }; + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t ADERINTCR; /*!< (@ 0x00000020) A/D Conversion Error Interrupt Enable Register */ + + struct + { + __IOM uint32_t ADEIE0 : 1; /*!< [0..0] ADC0 A/D Conversion Error Interrupt Enable */ + __IOM uint32_t ADEIE1 : 1; /*!< [1..1] ADC1 A/D Conversion Error Interrupt Enable */ + uint32_t : 30; + } ADERINTCR_b; + }; + + union + { + __IOM uint32_t ADOVFINTCR; /*!< (@ 0x00000024) A/D Conversion Overflow Interrupt Enable Register */ + + struct + { + __IOM uint32_t ADOVFIE0 : 1; /*!< [0..0] ADC0 A/D Conversion Overflow Interrupt Enable */ + __IOM uint32_t ADOVFIE1 : 1; /*!< [1..1] ADC1 A/D Conversion Overflow Interrupt Enable */ + uint32_t : 30; + } ADOVFINTCR_b; + }; + + union + { + __IOM uint32_t ADCALINTCR; /*!< (@ 0x00000028) Calibration interrupt Enable Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t CALENDIE0 : 1; /*!< [16..16] ADC0 Calibration End Interrupt Enable */ + __IOM uint32_t CALENDIE1 : 1; /*!< [17..17] ADC1 Calibration End Interrupt Enable */ + uint32_t : 14; + } ADCALINTCR_b; + }; + __IM uint32_t RESERVED1[5]; + + union + { + __IOM uint32_t ADMDR; /*!< (@ 0x00000040) A/D Converter Mode Selection Register */ + + struct + { + __IOM uint32_t ADMD0 : 4; /*!< [3..0] ADC0 Mode Selection */ + uint32_t : 4; + __IOM uint32_t ADMD1 : 4; /*!< [11..8] ADC1 Mode Selection */ + uint32_t : 20; + } ADMDR_b; + }; + + union + { + __IOM uint32_t ADGSPCR; /*!< (@ 0x00000044) A/D Group scan Priority Control Register */ + + struct + { + __IOM uint32_t PGS0 : 1; /*!< [0..0] ADC0 Group Priority Control Setting */ + __IOM uint32_t RSCN0 : 1; /*!< [1..1] ADC0 Group Priority Control Setting 2 */ + __IOM uint32_t LGRRS0 : 1; /*!< [2..2] ADC0 Group Priority Control Setting 3 */ + __IOM uint32_t GRP0 : 1; /*!< [3..3] ADC0 Group Priority Control Setting 4 */ + uint32_t : 4; + __IOM uint32_t PGS1 : 1; /*!< [8..8] ADC1 Group Priority Control Setting */ + __IOM uint32_t RSCN1 : 1; /*!< [9..9] ADC1 Group Priority Control Setting 2 */ + __IOM uint32_t LGRRS1 : 1; /*!< [10..10] ADC1 Group Priority Control Setting 3 */ + __IOM uint32_t GRP1 : 1; /*!< [11..11] ADC1 Group Priority Control Setting 4 */ + uint32_t : 20; + } ADGSPCR_b; + }; + + union + { + __IOM uint32_t ADSGER; /*!< (@ 0x00000048) Scan Group Enable Register */ + + struct + { + __IOM uint32_t SGREn : 9; /*!< [8..0] Scan Group n Enable */ + uint32_t : 23; + } ADSGER_b; + }; + + union + { + __IOM uint32_t ADSGCR0; /*!< (@ 0x0000004C) Scan Group Control Register 0 */ + + struct + { + __IOM uint32_t SGADS0 : 2; /*!< [1..0] Scan Group 0 A/D Converter Selection */ + uint32_t : 6; + __IOM uint32_t SGADS1 : 2; /*!< [9..8] Scan Group 1 A/D Converter Selection */ + uint32_t : 6; + __IOM uint32_t SGADS2 : 2; /*!< [17..16] Scan Group 2 A/D Converter Selection */ + uint32_t : 6; + __IOM uint32_t SGADS3 : 2; /*!< [25..24] Scan Group 3 A/D Converter Selection */ + uint32_t : 6; + } ADSGCR0_b; + }; + + union + { + __IOM uint32_t ADSGCR1; /*!< (@ 0x00000050) Scan Group Control Register 1 */ + + struct + { + __IOM uint32_t SGADS4 : 2; /*!< [1..0] Scan Group 4 A/D Converter Selection */ + uint32_t : 6; + __IOM uint32_t SGADS5 : 2; /*!< [9..8] Scan Group 5 A/D Converter Selection */ + uint32_t : 6; + __IOM uint32_t SGADS6 : 2; /*!< [17..16] Scan Group 6 A/D Converter Selection */ + uint32_t : 6; + __IOM uint32_t SGADS7 : 2; /*!< [25..24] Scan Group 7 A/D Converter Selection */ + uint32_t : 6; + } ADSGCR1_b; + }; + + union + { + __IOM uint32_t ADSGCR2; /*!< (@ 0x00000054) Scan Group Control Register 2 */ + + struct + { + __IOM uint32_t SGADS8 : 2; /*!< [1..0] Scan Group 8 A/D Converter Selection */ + uint32_t : 30; + } ADSGCR2_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t ADINTCR; /*!< (@ 0x0000005C) Scan End Interrupt Enable Register */ + + struct + { + __IOM uint32_t ADIEn : 9; /*!< [8..0] Scan Group n Scan End Interrupt Enable */ + uint32_t : 23; + } ADINTCR_b; + }; + __IM uint32_t RESERVED3[24]; + + union + { + __IOM uint32_t ADTRGEXT0; /*!< (@ 0x000000C0) External Trigger Enable Register 0 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT0_b; + }; + + union + { + __IOM uint32_t ADTRGELC0; /*!< (@ 0x000000C4) ELC Trigger Enable Register 0 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC0_b; + }; + + union + { + __IOM uint32_t ADTRGGPT0; /*!< (@ 0x000000C8) GPT Trigger Enable Register 0 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT0_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t ADTRGEXT1; /*!< (@ 0x000000D0) External Trigger Enable Register 1 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT1_b; + }; + + union + { + __IOM uint32_t ADTRGELC1; /*!< (@ 0x000000D4) ELC Trigger Enable Register 1 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC1_b; + }; + + union + { + __IOM uint32_t ADTRGGPT1; /*!< (@ 0x000000D8) GPT Trigger Enable Register 1 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT1_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t ADTRGEXT2; /*!< (@ 0x000000E0) External Trigger Enable Register 2 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT2_b; + }; + + union + { + __IOM uint32_t ADTRGELC2; /*!< (@ 0x000000E4) ELC Trigger Enable Register 2 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC2_b; + }; + + union + { + __IOM uint32_t ADTRGGPT2; /*!< (@ 0x000000E8) GPT Trigger Enable Register 2 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT2_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t ADTRGEXT3; /*!< (@ 0x000000F0) External Trigger Enable Register 3 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT3_b; + }; + + union + { + __IOM uint32_t ADTRGELC3; /*!< (@ 0x000000F4) ELC Trigger Enable Register 3 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC3_b; + }; + + union + { + __IOM uint32_t ADTRGGPT3; /*!< (@ 0x000000F8) GPT Trigger Enable Register 3 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT3_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t ADTRGEXT4; /*!< (@ 0x00000100) External Trigger Enable Register 4 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT4_b; + }; + + union + { + __IOM uint32_t ADTRGELC4; /*!< (@ 0x00000104) ELC Trigger Enable Register 4 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC4_b; + }; + + union + { + __IOM uint32_t ADTRGGPT4; /*!< (@ 0x00000108) GPT Trigger Enable Register 4 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT4_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t ADTRGEXT5; /*!< (@ 0x00000110) External Trigger Enable Register 5 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT5_b; + }; + + union + { + __IOM uint32_t ADTRGELC5; /*!< (@ 0x00000114) ELC Trigger Enable Register 5 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC5_b; + }; + + union + { + __IOM uint32_t ADTRGGPT5; /*!< (@ 0x00000118) GPT Trigger Enable Register 5 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT5_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t ADTRGEXT6; /*!< (@ 0x00000120) External Trigger Enable Register 6 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT6_b; + }; + + union + { + __IOM uint32_t ADTRGELC6; /*!< (@ 0x00000124) ELC Trigger Enable Register 6 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC6_b; + }; + + union + { + __IOM uint32_t ADTRGGPT6; /*!< (@ 0x00000128) GPT Trigger Enable Register 6 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT6_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t ADTRGEXT7; /*!< (@ 0x00000130) External Trigger Enable Register 7 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT7_b; + }; + + union + { + __IOM uint32_t ADTRGELC7; /*!< (@ 0x00000134) ELC Trigger Enable Register 7 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC7_b; + }; + + union + { + __IOM uint32_t ADTRGGPT7; /*!< (@ 0x00000138) GPT Trigger Enable Register 7 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT7_b; + }; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t ADTRGEXT8; /*!< (@ 0x00000140) External Trigger Enable Register 8 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT8_b; + }; + + union + { + __IOM uint32_t ADTRGELC8; /*!< (@ 0x00000144) ELC Trigger Enable Register 8 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC8_b; + }; + + union + { + __IOM uint32_t ADTRGGPT8; /*!< (@ 0x00000148) GPT Trigger Enable Register 8 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT8_b; + }; + __IM uint32_t RESERVED12[29]; + + union + { + __IOM uint32_t ADTRGDLR0; /*!< (@ 0x000001C0) A/D Conversion Start Trigger Delay Register 0 */ + + struct + { + __IOM uint32_t TRGDLY0 : 8; /*!< [7..0] Scan Group 0 Trigger Input Delay Configuration */ + uint32_t : 8; + __IOM uint32_t TRGDLY1 : 8; /*!< [23..16] Scan Group 1 Trigger Input Delay Configuration */ + uint32_t : 8; + } ADTRGDLR0_b; + }; + + union + { + __IOM uint32_t ADTRGDLR1; /*!< (@ 0x000001C4) A/D Conversion Start Trigger Delay Register 1 */ + + struct + { + __IOM uint32_t TRGDLY2 : 8; /*!< [7..0] Scan Group 2 Trigger Input Delay Configuration */ + uint32_t : 8; + __IOM uint32_t TRGDLY3 : 8; /*!< [23..16] Scan Group 3 Trigger Input Delay Configuration */ + uint32_t : 8; + } ADTRGDLR1_b; + }; + + union + { + __IOM uint32_t ADTRGDLR2; /*!< (@ 0x000001C8) A/D Conversion Start Trigger Delay Register 2 */ + + struct + { + __IOM uint32_t TRGDLY4 : 8; /*!< [7..0] Scan Group 4 Trigger Input Delay Configuration */ + uint32_t : 8; + __IOM uint32_t TRGDLY5 : 8; /*!< [23..16] Scan Group 5 Trigger Input Delay Configuration */ + uint32_t : 8; + } ADTRGDLR2_b; + }; + + union + { + __IOM uint32_t ADTRGDLR3; /*!< (@ 0x000001CC) A/D Conversion Start Trigger Delay Register 3 */ + + struct + { + __IOM uint32_t TRGDLY6 : 8; /*!< [7..0] Scan Group 6 Trigger Input Delay Configuration */ + uint32_t : 8; + __IOM uint32_t TRGDLY7 : 8; /*!< [23..16] Scan Group 7 Trigger Input Delay Configuration */ + uint32_t : 8; + } ADTRGDLR3_b; + }; + + union + { + __IOM uint32_t ADTRGDLR4; /*!< (@ 0x000001D0) A/D Conversion Start Trigger Delay Register 4 */ + + struct + { + __IOM uint32_t TRGDLY8 : 8; /*!< [7..0] Scan Group 8 Trigger Input Delay Configuration */ + uint32_t : 24; + } ADTRGDLR4_b; + }; + __IM uint32_t RESERVED13[11]; + + union + { + __IOM uint32_t ADSGDCR0; /*!< (@ 0x00000200) Scan Group Diagnosis Function Control Register + * 0 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR0_b; + }; + + union + { + __IOM uint32_t ADSGDCR1; /*!< (@ 0x00000204) Scan Group Diagnosis Function Control Register + * 1 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR1_b; + }; + + union + { + __IOM uint32_t ADSGDCR2; /*!< (@ 0x00000208) Scan Group Diagnosis Function Control Register + * 2 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR2_b; + }; + + union + { + __IOM uint32_t ADSGDCR3; /*!< (@ 0x0000020C) Scan Group Diagnosis Function Control Register + * 3 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR3_b; + }; + + union + { + __IOM uint32_t ADSGDCR4; /*!< (@ 0x00000210) Scan Group Diagnosis Function Control Register + * 4 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR4_b; + }; + + union + { + __IOM uint32_t ADSGDCR5; /*!< (@ 0x00000214) Scan Group Diagnosis Function Control Register + * 5 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR5_b; + }; + + union + { + __IOM uint32_t ADSGDCR6; /*!< (@ 0x00000218) Scan Group Diagnosis Function Control Register + * 6 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR6_b; + }; + + union + { + __IOM uint32_t ADSGDCR7; /*!< (@ 0x0000021C) Scan Group Diagnosis Function Control Register + * 7 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR7_b; + }; + + union + { + __IOM uint32_t ADSGDCR8; /*!< (@ 0x00000220) Scan Group Diagnosis Function Control Register + * 8 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR8_b; + }; + __IM uint32_t RESERVED14[7]; + + union + { + __IOM uint32_t ADSSTR0; /*!< (@ 0x00000240) Sampling State Table Register 0 */ + + struct + { + __IOM uint32_t SST0 : 10; /*!< [9..0] Sampling State Table 0 */ + uint32_t : 6; + __IOM uint32_t SST1 : 10; /*!< [25..16] Sampling State Table 1 */ + uint32_t : 6; + } ADSSTR0_b; + }; + + union + { + __IOM uint32_t ADSSTR1; /*!< (@ 0x00000244) Sampling State Table Register 1 */ + + struct + { + __IOM uint32_t SST2 : 10; /*!< [9..0] Sampling State Table 2 */ + uint32_t : 6; + __IOM uint32_t SST3 : 10; /*!< [25..16] Sampling State Table 3 */ + uint32_t : 6; + } ADSSTR1_b; + }; + + union + { + __IOM uint32_t ADSSTR2; /*!< (@ 0x00000248) Sampling State Table Register 2 */ + + struct + { + __IOM uint32_t SST4 : 10; /*!< [9..0] Sampling State Table 4 */ + uint32_t : 6; + __IOM uint32_t SST5 : 10; /*!< [25..16] Sampling State Table 5 */ + uint32_t : 6; + } ADSSTR2_b; + }; + + union + { + __IOM uint32_t ADSSTR3; /*!< (@ 0x0000024C) Sampling State Table Register 3 */ + + struct + { + __IOM uint32_t SST6 : 10; /*!< [9..0] Sampling State Table 6 */ + uint32_t : 6; + __IOM uint32_t SST7 : 10; /*!< [25..16] Sampling State Table 7 */ + uint32_t : 6; + } ADSSTR3_b; + }; + + union + { + __IOM uint32_t ADSSTR4; /*!< (@ 0x00000250) Sampling State Table Register 4 */ + + struct + { + __IOM uint32_t SST8 : 10; /*!< [9..0] Sampling State Table 8 */ + uint32_t : 6; + __IOM uint32_t SST9 : 10; /*!< [25..16] Sampling State Table 9 */ + uint32_t : 6; + } ADSSTR4_b; + }; + + union + { + __IOM uint32_t ADSSTR5; /*!< (@ 0x00000254) Sampling State Table Register 5 */ + + struct + { + __IOM uint32_t SST10 : 10; /*!< [9..0] Sampling State Table 10 */ + uint32_t : 6; + __IOM uint32_t SST11 : 10; /*!< [25..16] Sampling State Table 11 */ + uint32_t : 6; + } ADSSTR5_b; + }; + + union + { + __IOM uint32_t ADSSTR6; /*!< (@ 0x00000258) Sampling State Table Register 6 */ + + struct + { + __IOM uint32_t SST12 : 10; /*!< [9..0] Sampling State Table 12 */ + uint32_t : 6; + __IOM uint32_t SST13 : 10; /*!< [25..16] Sampling State Table 13 */ + uint32_t : 6; + } ADSSTR6_b; + }; + + union + { + __IOM uint32_t ADSSTR7; /*!< (@ 0x0000025C) Sampling State Table Register 7 */ + + struct + { + __IOM uint32_t SST14 : 10; /*!< [9..0] Sampling State Table 14 */ + uint32_t : 6; + __IOM uint32_t SST15 : 10; /*!< [25..16] Sampling State Table 15 */ + uint32_t : 6; + } ADSSTR7_b; + }; + + union + { + __IOM uint32_t ADCNVSTR; /*!< (@ 0x00000260) A/D Conversion State Register */ + + struct + { + __IOM uint32_t CST0 : 6; /*!< [5..0] A/D Converter Unit 0 (ADC0) */ + uint32_t : 2; + __IOM uint32_t CST1 : 6; /*!< [13..8] A/D Converter Unit 1 (ADC1) */ + uint32_t : 18; + } ADCNVSTR_b; + }; + + union + { + __IOM uint32_t ADCALSTCR; /*!< (@ 0x00000264) A/D Converter Calibration State Register */ + + struct + { + __IOM uint32_t CALADSST : 10; /*!< [9..0] A/D Converter Calibration Sampling Time Configuration */ + uint32_t : 6; + __IOM uint32_t CALADCST : 6; /*!< [21..16] A/D Converter Calibration Conversion Time Configuration. */ + uint32_t : 10; + } ADCALSTCR_b; + }; + __IM uint32_t RESERVED15[6]; + + union + { + __IOM uint32_t ADSHCR0; /*!< (@ 0x00000280) Channel-Dedicated Sample-and-Hold Circuit Control + * Register 0 */ + + struct + { + __IOM uint32_t SHEN0 : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Unit 0 Select */ + __IOM uint32_t SHEN1 : 1; /*!< [1..1] Channel-Dedicated Sample-and-Hold Circuit Unit 1 Select */ + __IOM uint32_t SHEN2 : 1; /*!< [2..2] Channel-Dedicated Sample-and-Hold Circuit Unit 2 Select */ + uint32_t : 13; + __IOM uint32_t SHMD0 : 1; /*!< [16..16] Channel-dedicated Sample-and-hold Circuit Unit 0 Input + * Mode Select */ + __IOM uint32_t SHMD1 : 1; /*!< [17..17] Channel-dedicated Sample-and-hold Circuit Unit 1 Input + * Mode Select */ + __IOM uint32_t SHMD2 : 1; /*!< [18..18] Channel-dedicated Sample-and-hold Circuit Unit 2 Input + * Mode Select */ + uint32_t : 13; + } ADSHCR0_b; + }; + __IM uint32_t RESERVED16; + + union + { + __IOM uint32_t ADSHSTR0; /*!< (@ 0x00000288) Channel-Dedicated Sample & Hold Circuit State + * Register 0 */ + + struct + { + __IOM uint32_t SHSST : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Unit 0 to 2 */ + uint32_t : 8; + __IOM uint32_t SHHST : 3; /*!< [18..16] Channel-Dedicated Sample-and-Hold Circuit Unit 0 to + * 2 */ + uint32_t : 13; + } ADSHSTR0_b; + }; + + union + { + __IOM uint32_t ADSHCR1; /*!< (@ 0x0000028C) Channel-Dedicated Sample-and-Hold Circuit Control + * Register 1 */ + + struct + { + __IOM uint32_t SHEN4 : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Unit 4 Select */ + __IOM uint32_t SHEN5 : 1; /*!< [1..1] Channel-Dedicated Sample-and-Hold Circuit Unit 5 Select */ + __IOM uint32_t SHEN6 : 1; /*!< [2..2] Channel-Dedicated Sample-and-Hold Circuit Unit 6 Select */ + uint32_t : 13; + __IOM uint32_t SHMD4 : 1; /*!< [16..16] Channel-dedicated Sample-and-hold Circuit Unit 4 Input + * Mode Select */ + __IOM uint32_t SHMD5 : 1; /*!< [17..17] Channel-dedicated Sample-and-hold Circuit Unit 5 Input + * Mode Select */ + __IOM uint32_t SHMD6 : 1; /*!< [18..18] Channel-dedicated Sample-and-hold Circuit Unit 6 Input + * Mode Select */ + uint32_t : 13; + } ADSHCR1_b; + }; + __IM uint32_t RESERVED17; + + union + { + __IOM uint32_t ADSHSTR1; /*!< (@ 0x00000294) Channel-Dedicated Sample & Hold Circuit State + * Register 1 */ + + struct + { + __IOM uint32_t SHSST : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Unit 4 to 6 */ + uint32_t : 8; + __IOM uint32_t SHHST : 3; /*!< [18..16] Channel-Dedicated Sample-and-Hold Circuit Unit 4 to + * 6 */ + uint32_t : 13; + } ADSHSTR1_b; + }; + __IM uint32_t RESERVED18[6]; + + union + { + __IOM uint32_t ADCALSHCR; /*!< (@ 0x000002B0) Channel-Dedicated Sample & Hold Circuit Calibration + * State Register */ + + struct + { + __IOM uint32_t CALSHSST : 8; /*!< [7..0] Channel-Dedicated Sample & Hold Circuit Calibration Sampling + * Time Configuration */ + uint32_t : 8; + __IOM uint32_t CALSHHST : 3; /*!< [18..16] Channel-Dedicated Sample & Hold Circuit Calibration + * Holding Time Configuration */ + uint32_t : 13; + } ADCALSHCR_b; + }; + __IM uint32_t RESERVED19[27]; + + union + { + __IOM uint32_t ADREFCR; /*!< (@ 0x00000320) Internal Reference Voltage Monitor Enable Register */ + + struct + { + __IOM uint32_t VDE : 1; /*!< [0..0] Internal Reference Voltage A/D Conversion Select */ + uint32_t : 31; + } ADREFCR_b; + }; + __IM uint32_t RESERVED20[7]; + + union + { + __IOM uint32_t ADDFSR0; /*!< (@ 0x00000340) A/D Converter Digital Filter Selection Register + * 0 */ + + struct + { + __IOM uint32_t DFSEL0 : 2; /*!< [1..0] A/D Converter unit the 1st digital filter characteristic + * selection. */ + uint32_t : 6; + __IOM uint32_t DFSEL1 : 2; /*!< [9..8] A/D Converter unit the 2nd digital filter characteristic + * selection. */ + uint32_t : 6; + __IOM uint32_t DFSEL2 : 2; /*!< [17..16] A/D Converter unit the 2nd digital filter characteristic + * selection. */ + uint32_t : 6; + __IOM uint32_t DFSEL3 : 2; /*!< [25..24] A/D Converter unit the 4th digital filter characteristic + * selection. */ + uint32_t : 6; + } ADDFSR0_b; + }; + + union + { + __IOM uint32_t ADDFSR1; /*!< (@ 0x00000344) A/D Converter Digital Filter Selection Register + * 1 */ + + struct + { + __IOM uint32_t DFSEL0 : 2; /*!< [1..0] A/D Converter unit the 1st digital filter characteristic + * selection. */ + uint32_t : 6; + __IOM uint32_t DFSEL1 : 2; /*!< [9..8] A/D Converter unit the 2nd digital filter characteristic + * selection. */ + uint32_t : 6; + __IOM uint32_t DFSEL2 : 2; /*!< [17..16] A/D Converter unit the 2nd digital filter characteristic + * selection. */ + uint32_t : 6; + __IOM uint32_t DFSEL3 : 2; /*!< [25..24] A/D Converter unit the 4th digital filter characteristic + * selection. */ + uint32_t : 6; + } ADDFSR1_b; + }; + __IM uint32_t RESERVED21[6]; + + union + { + __IOM uint32_t ADUOFTR0; /*!< (@ 0x00000360) User Offset Table Register 0 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR0_b; + }; + + union + { + __IOM uint32_t ADUOFTR1; /*!< (@ 0x00000364) User Offset Table Register 1 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR1_b; + }; + + union + { + __IOM uint32_t ADUOFTR2; /*!< (@ 0x00000368) User Offset Table Register 2 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR2_b; + }; + + union + { + __IOM uint32_t ADUOFTR3; /*!< (@ 0x0000036C) User Offset Table Register 3 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR3_b; + }; + + union + { + __IOM uint32_t ADUOFTR4; /*!< (@ 0x00000370) User Offset Table Register 4 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR4_b; + }; + + union + { + __IOM uint32_t ADUOFTR5; /*!< (@ 0x00000374) User Offset Table Register 5 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR5_b; + }; + + union + { + __IOM uint32_t ADUOFTR6; /*!< (@ 0x00000378) User Offset Table Register 6 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR6_b; + }; + + union + { + __IOM uint32_t ADUOFTR7; /*!< (@ 0x0000037C) User Offset Table Register 7 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR7_b; + }; + + union + { + __IOM uint32_t ADUGTR0; /*!< (@ 0x00000380) User Gain Table Register 0 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR0_b; + }; + + union + { + __IOM uint32_t ADUGTR1; /*!< (@ 0x00000384) User Gain Table Register 1 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR1_b; + }; + + union + { + __IOM uint32_t ADUGTR2; /*!< (@ 0x00000388) User Gain Table Register 2 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR2_b; + }; + + union + { + __IOM uint32_t ADUGTR3; /*!< (@ 0x0000038C) User Gain Table Register 3 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR3_b; + }; + + union + { + __IOM uint32_t ADUGTR4; /*!< (@ 0x00000390) User Gain Table Register 4 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR4_b; + }; + + union + { + __IOM uint32_t ADUGTR5; /*!< (@ 0x00000394) User Gain Table Register 5 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR5_b; + }; + + union + { + __IOM uint32_t ADUGTR6; /*!< (@ 0x00000398) User Gain Table Register 6 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR6_b; + }; + + union + { + __IOM uint32_t ADUGTR7; /*!< (@ 0x0000039C) User Gain Table Register 7 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR7_b; + }; + + union + { + __IOM uint32_t ADLIMINTCR; /*!< (@ 0x000003A0) Limiter Clip Interrupt Enable Register */ + + struct + { + __IOM uint32_t LIMIEn : 9; /*!< [8..0] Limiter Clip Interrupt n Enable bit */ + uint32_t : 23; + } ADLIMINTCR_b; + }; + + union + { + __IOM uint32_t ADLIMTR0; /*!< (@ 0x000003A4) Limiter Clip Table Register 0 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR0_b; + }; + + union + { + __IOM uint32_t ADLIMTR1; /*!< (@ 0x000003A8) Limiter Clip Table Register 1 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR1_b; + }; + + union + { + __IOM uint32_t ADLIMTR2; /*!< (@ 0x000003AC) Limiter Clip Table Register 2 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR2_b; + }; + + union + { + __IOM uint32_t ADLIMTR3; /*!< (@ 0x000003B0) Limiter Clip Table Register 3 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR3_b; + }; + + union + { + __IOM uint32_t ADLIMTR4; /*!< (@ 0x000003B4) Limiter Clip Table Register 4 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR4_b; + }; + + union + { + __IOM uint32_t ADLIMTR5; /*!< (@ 0x000003B8) Limiter Clip Table Register 5 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR5_b; + }; + + union + { + __IOM uint32_t ADLIMTR6; /*!< (@ 0x000003BC) Limiter Clip Table Register 6 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR6_b; + }; + + union + { + __IOM uint32_t ADLIMTR7; /*!< (@ 0x000003C0) Limiter Clip Table Register 7 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR7_b; + }; + __IM uint32_t RESERVED22[15]; + + union + { + __IOM uint32_t ADCMPENR; /*!< (@ 0x00000400) Compare Match Enable Register */ + + struct + { + __IOM uint32_t CMPENn : 8; /*!< [7..0] Compare Match n Enable */ + uint32_t : 24; + } ADCMPENR_b; + }; + + union + { + __IOM uint32_t ADCMPINTCR; /*!< (@ 0x00000404) Compare Match Interrupt Enable Register */ + + struct + { + __IOM uint32_t CMPIEn : 4; /*!< [3..0] Compare Match Interrupt n Enable */ + uint32_t : 28; + } ADCMPINTCR_b; + }; + + union + { + __IOM uint32_t ADCCMPCR0; /*!< (@ 0x00000408) Composite Compare Match Configuration Register + * 0 */ + + struct + { + __IOM uint32_t CCMPCND : 2; /*!< [1..0] Composite Compare Match Condition Selection */ + uint32_t : 14; + __IOM uint32_t CCMPTBLm : 8; /*!< [23..16] Composite Compare Match Condition Table Selection */ + uint32_t : 8; + } ADCCMPCR0_b; + }; + + union + { + __IOM uint32_t ADCCMPCR1; /*!< (@ 0x0000040C) Composite Compare Match Configuration Register + * 1 */ + + struct + { + __IOM uint32_t CCMPCND : 2; /*!< [1..0] Composite Compare Match Condition Selection */ + uint32_t : 14; + __IOM uint32_t CCMPTBLm : 8; /*!< [23..16] Composite Compare Match Condition Table Selection */ + uint32_t : 8; + } ADCCMPCR1_b; + }; + __IM uint32_t RESERVED23[14]; + + union + { + __IOM uint32_t ADCMPMDR0; /*!< (@ 0x00000448) Compare Match Mode Selection Register 0 */ + + struct + { + __IOM uint32_t CMPMD0 : 2; /*!< [1..0] Compare Match 0 : Match Mode Selection */ + uint32_t : 6; + __IOM uint32_t CMPMD1 : 2; /*!< [9..8] Compare Match 1 : Match Mode Selection */ + uint32_t : 6; + __IOM uint32_t CMPMD2 : 2; /*!< [17..16] Compare Match 2 : Match Mode Selection */ + uint32_t : 6; + __IOM uint32_t CMPMD3 : 2; /*!< [25..24] Compare Match 3 : Match Mode Selection */ + uint32_t : 6; + } ADCMPMDR0_b; + }; + + union + { + __IOM uint32_t ADCMPMDR1; /*!< (@ 0x0000044C) Compare Match Mode Selection Register 1 */ + + struct + { + __IOM uint32_t CMPMD4 : 2; /*!< [1..0] Compare Match 4 : Match Mode Selection */ + uint32_t : 6; + __IOM uint32_t CMPMD5 : 2; /*!< [9..8] Compare Match 5 : Match Mode Selection */ + uint32_t : 6; + __IOM uint32_t CMPMD6 : 2; /*!< [17..16] Compare Match 6 : Match Mode Selection */ + uint32_t : 6; + __IOM uint32_t CMPMD7 : 2; /*!< [25..24] Compare Match 7 : Match Mode Selection */ + uint32_t : 6; + } ADCMPMDR1_b; + }; + __IM uint32_t RESERVED24[2]; + + union + { + __IOM uint32_t ADCMPTBR0; /*!< (@ 0x00000458) Compare Match Table Register 0 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR0_b; + }; + + union + { + __IOM uint32_t ADCMPTBR1; /*!< (@ 0x0000045C) Compare Match Table Register 1 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR1_b; + }; + + union + { + __IOM uint32_t ADCMPTBR2; /*!< (@ 0x00000460) Compare Match Table Register 2 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR2_b; + }; + + union + { + __IOM uint32_t ADCMPTBR3; /*!< (@ 0x00000464) Compare Match Table Register 3 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR3_b; + }; + + union + { + __IOM uint32_t ADCMPTBR4; /*!< (@ 0x00000468) Compare Match Table Register 4 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR4_b; + }; + + union + { + __IOM uint32_t ADCMPTBR5; /*!< (@ 0x0000046C) Compare Match Table Register 5 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR5_b; + }; + + union + { + __IOM uint32_t ADCMPTBR6; /*!< (@ 0x00000470) Compare Match Table Register 6 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR6_b; + }; + + union + { + __IOM uint32_t ADCMPTBR7; /*!< (@ 0x00000474) Compare Match Table Register 7 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR7_b; + }; + __IM uint32_t RESERVED25[18]; + + union + { + __IOM uint32_t ADFIFOCR; /*!< (@ 0x000004C0) FIFO Control Register */ + + struct + { + __IOM uint32_t FIFOEN0 : 1; /*!< [0..0] Scan Group 0 FIFO Enable */ + __IOM uint32_t FIFOEN1 : 1; /*!< [1..1] Scan Group 1 FIFO Enable */ + __IOM uint32_t FIFOEN2 : 1; /*!< [2..2] Scan Group 2 FIFO Enable */ + __IOM uint32_t FIFOEN3 : 1; /*!< [3..3] Scan Group 3 FIFO Enable */ + __IOM uint32_t FIFOEN4 : 1; /*!< [4..4] Scan Group 4 FIFO Enable */ + __IOM uint32_t FIFOEN5 : 1; /*!< [5..5] Scan Group 5 FIFO Enable */ + __IOM uint32_t FIFOEN6 : 1; /*!< [6..6] Scan Group 6 FIFO Enable */ + __IOM uint32_t FIFOEN7 : 1; /*!< [7..7] Scan Group 7 FIFO Enable */ + __IOM uint32_t FIFOEN8 : 1; /*!< [8..8] Scan Group 8 FIFO Enable */ + uint32_t : 23; + } ADFIFOCR_b; + }; + + union + { + __IOM uint32_t ADFIFOINTCR; /*!< (@ 0x000004C4) FIFO Interrupt Control Register */ + + struct + { + __IOM uint32_t FIFOIE0 : 1; /*!< [0..0] Scan Group 0 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE1 : 1; /*!< [1..1] Scan Group 1 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE2 : 1; /*!< [2..2] Scan Group 2 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE3 : 1; /*!< [3..3] Scan Group 3 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE4 : 1; /*!< [4..4] Scan Group 4 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE5 : 1; /*!< [5..5] Scan Group 5 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE6 : 1; /*!< [6..6] Scan Group 6 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE7 : 1; /*!< [7..7] Scan Group 7 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE8 : 1; /*!< [8..8] Scan Group 8 FIFO Interrupt Enable */ + uint32_t : 23; + } ADFIFOINTCR_b; + }; + + union + { + __IOM uint32_t ADFIFOINTLR0; /*!< (@ 0x000004C8) FIFO Interrupt Generation Level Register 0 */ + + struct + { + __IOM uint32_t FIFOILV0 : 4; /*!< [3..0] Scan Group 0 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + __IOM uint32_t FIFOILV1 : 4; /*!< [19..16] Scan Group 1 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + } ADFIFOINTLR0_b; + }; + + union + { + __IOM uint32_t ADFIFOINTLR1; /*!< (@ 0x000004CC) FIFO Interrupt Generation Level Register 1 */ + + struct + { + __IOM uint32_t FIFOILV2 : 4; /*!< [3..0] Scan Group 2 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + __IOM uint32_t FIFOILV3 : 4; /*!< [19..16] Scan Group 3 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + } ADFIFOINTLR1_b; + }; + + union + { + __IOM uint32_t ADFIFOINTLR2; /*!< (@ 0x000004D0) FIFO Interrupt Generation Level Register 2 */ + + struct + { + __IOM uint32_t FIFOILV4 : 4; /*!< [3..0] Scan Group 4 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + __IOM uint32_t FIFOILV5 : 4; /*!< [19..16] Scan Group 5 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + } ADFIFOINTLR2_b; + }; + + union + { + __IOM uint32_t ADFIFOINTLR3; /*!< (@ 0x000004D4) FIFO Interrupt Generation Level Register 3 */ + + struct + { + __IOM uint32_t FIFOILV6 : 4; /*!< [3..0] Scan Group 6 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + __IOM uint32_t FIFOILV7 : 4; /*!< [19..16] Scan Group 7 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + } ADFIFOINTLR3_b; + }; + + union + { + __IOM uint32_t ADFIFOINTLR4; /*!< (@ 0x000004D8) FIFO Interrupt Generation Level Register 4 */ + + struct + { + __IOM uint32_t FIFOILV8 : 4; /*!< [3..0] Scan Group 8 FIFO Interrupt Output Timing Setting */ + uint32_t : 28; + } ADFIFOINTLR4_b; + }; + __IM uint32_t RESERVED26[73]; + + union + { + __IOM uint32_t ADCHCR0; /*!< (@ 0x00000600) A/D Conversion Channel Configuration Register + * 0 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR0_b; + }; + + union + { + __IOM uint32_t ADDOPCRA0; /*!< (@ 0x00000604) A/D Conversion Data Operation Control A Register + * 0 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA0_b; + }; + + union + { + __IOM uint32_t ADDOPCRB0; /*!< (@ 0x00000608) A/D Conversion Data Operation Control B Register + * 0 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB0_b; + }; + + union + { + __IOM uint32_t ADDOPCRC0; /*!< (@ 0x0000060C) A/D Conversion Data Operation Control C Register + * 0 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC0_b; + }; + + union + { + __IOM uint32_t ADCHCR1; /*!< (@ 0x00000610) A/D Conversion Channel Configuration Register + * 1 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR1_b; + }; + + union + { + __IOM uint32_t ADDOPCRA1; /*!< (@ 0x00000614) A/D Conversion Data Operation Control A Register + * 1 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA1_b; + }; + + union + { + __IOM uint32_t ADDOPCRB1; /*!< (@ 0x00000618) A/D Conversion Data Operation Control B Register + * 1 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB1_b; + }; + + union + { + __IOM uint32_t ADDOPCRC1; /*!< (@ 0x0000061C) A/D Conversion Data Operation Control C Register + * 1 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC1_b; + }; + + union + { + __IOM uint32_t ADCHCR2; /*!< (@ 0x00000620) A/D Conversion Channel Configuration Register + * 2 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR2_b; + }; + + union + { + __IOM uint32_t ADDOPCRA2; /*!< (@ 0x00000624) A/D Conversion Data Operation Control A Register + * 2 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA2_b; + }; + + union + { + __IOM uint32_t ADDOPCRB2; /*!< (@ 0x00000628) A/D Conversion Data Operation Control B Register + * 2 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB2_b; + }; + + union + { + __IOM uint32_t ADDOPCRC2; /*!< (@ 0x0000062C) A/D Conversion Data Operation Control C Register + * 2 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC2_b; + }; + + union + { + __IOM uint32_t ADCHCR3; /*!< (@ 0x00000630) A/D Conversion Channel Configuration Register + * 3 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR3_b; + }; + + union + { + __IOM uint32_t ADDOPCRA3; /*!< (@ 0x00000634) A/D Conversion Data Operation Control A Register + * 3 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA3_b; + }; + + union + { + __IOM uint32_t ADDOPCRB3; /*!< (@ 0x00000638) A/D Conversion Data Operation Control B Register + * 3 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB3_b; + }; + + union + { + __IOM uint32_t ADDOPCRC3; /*!< (@ 0x0000063C) A/D Conversion Data Operation Control C Register + * 3 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC3_b; + }; + + union + { + __IOM uint32_t ADCHCR4; /*!< (@ 0x00000640) A/D Conversion Channel Configuration Register + * 4 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR4_b; + }; + + union + { + __IOM uint32_t ADDOPCRA4; /*!< (@ 0x00000644) A/D Conversion Data Operation Control A Register + * 4 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA4_b; + }; + + union + { + __IOM uint32_t ADDOPCRB4; /*!< (@ 0x00000648) A/D Conversion Data Operation Control B Register + * 4 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB4_b; + }; + + union + { + __IOM uint32_t ADDOPCRC4; /*!< (@ 0x0000064C) A/D Conversion Data Operation Control C Register + * 4 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC4_b; + }; + + union + { + __IOM uint32_t ADCHCR5; /*!< (@ 0x00000650) A/D Conversion Channel Configuration Register + * 5 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR5_b; + }; + + union + { + __IOM uint32_t ADDOPCRA5; /*!< (@ 0x00000654) A/D Conversion Data Operation Control A Register + * 5 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA5_b; + }; + + union + { + __IOM uint32_t ADDOPCRB5; /*!< (@ 0x00000658) A/D Conversion Data Operation Control B Register + * 5 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB5_b; + }; + + union + { + __IOM uint32_t ADDOPCRC5; /*!< (@ 0x0000065C) A/D Conversion Data Operation Control C Register + * 5 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC5_b; + }; + + union + { + __IOM uint32_t ADCHCR6; /*!< (@ 0x00000660) A/D Conversion Channel Configuration Register + * 6 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR6_b; + }; + + union + { + __IOM uint32_t ADDOPCRA6; /*!< (@ 0x00000664) A/D Conversion Data Operation Control A Register + * 6 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA6_b; + }; + + union + { + __IOM uint32_t ADDOPCRB6; /*!< (@ 0x00000668) A/D Conversion Data Operation Control B Register + * 6 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB6_b; + }; + + union + { + __IOM uint32_t ADDOPCRC6; /*!< (@ 0x0000066C) A/D Conversion Data Operation Control C Register + * 6 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC6_b; + }; + + union + { + __IOM uint32_t ADCHCR7; /*!< (@ 0x00000670) A/D Conversion Channel Configuration Register + * 7 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR7_b; + }; + + union + { + __IOM uint32_t ADDOPCRA7; /*!< (@ 0x00000674) A/D Conversion Data Operation Control A Register + * 7 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA7_b; + }; + + union + { + __IOM uint32_t ADDOPCRB7; /*!< (@ 0x00000678) A/D Conversion Data Operation Control B Register + * 7 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB7_b; + }; + + union + { + __IOM uint32_t ADDOPCRC7; /*!< (@ 0x0000067C) A/D Conversion Data Operation Control C Register + * 7 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC7_b; + }; + + union + { + __IOM uint32_t ADCHCR8; /*!< (@ 0x00000680) A/D Conversion Channel Configuration Register + * 8 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR8_b; + }; + + union + { + __IOM uint32_t ADDOPCRA8; /*!< (@ 0x00000684) A/D Conversion Data Operation Control A Register + * 8 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA8_b; + }; + + union + { + __IOM uint32_t ADDOPCRB8; /*!< (@ 0x00000688) A/D Conversion Data Operation Control B Register + * 8 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB8_b; + }; + + union + { + __IOM uint32_t ADDOPCRC8; /*!< (@ 0x0000068C) A/D Conversion Data Operation Control C Register + * 8 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC8_b; + }; + + union + { + __IOM uint32_t ADCHCR9; /*!< (@ 0x00000690) A/D Conversion Channel Configuration Register + * 9 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR9_b; + }; + + union + { + __IOM uint32_t ADDOPCRA9; /*!< (@ 0x00000694) A/D Conversion Data Operation Control A Register + * 9 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA9_b; + }; + + union + { + __IOM uint32_t ADDOPCRB9; /*!< (@ 0x00000698) A/D Conversion Data Operation Control B Register + * 9 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB9_b; + }; + + union + { + __IOM uint32_t ADDOPCRC9; /*!< (@ 0x0000069C) A/D Conversion Data Operation Control C Register + * 9 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC9_b; + }; + + union + { + __IOM uint32_t ADCHCR10; /*!< (@ 0x000006A0) A/D Conversion Channel Configuration Register + * 10 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR10_b; + }; + + union + { + __IOM uint32_t ADDOPCRA10; /*!< (@ 0x000006A4) A/D Conversion Data Operation Control A Register + * 10 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA10_b; + }; + + union + { + __IOM uint32_t ADDOPCRB10; /*!< (@ 0x000006A8) A/D Conversion Data Operation Control B Register + * 10 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB10_b; + }; + + union + { + __IOM uint32_t ADDOPCRC10; /*!< (@ 0x000006AC) A/D Conversion Data Operation Control C Register + * 10 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC10_b; + }; + + union + { + __IOM uint32_t ADCHCR11; /*!< (@ 0x000006B0) A/D Conversion Channel Configuration Register + * 11 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR11_b; + }; + + union + { + __IOM uint32_t ADDOPCRA11; /*!< (@ 0x000006B4) A/D Conversion Data Operation Control A Register + * 11 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA11_b; + }; + + union + { + __IOM uint32_t ADDOPCRB11; /*!< (@ 0x000006B8) A/D Conversion Data Operation Control B Register + * 11 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB11_b; + }; + + union + { + __IOM uint32_t ADDOPCRC11; /*!< (@ 0x000006BC) A/D Conversion Data Operation Control C Register + * 11 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC11_b; + }; + + union + { + __IOM uint32_t ADCHCR12; /*!< (@ 0x000006C0) A/D Conversion Channel Configuration Register + * 12 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR12_b; + }; + + union + { + __IOM uint32_t ADDOPCRA12; /*!< (@ 0x000006C4) A/D Conversion Data Operation Control A Register + * 12 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA12_b; + }; + + union + { + __IOM uint32_t ADDOPCRB12; /*!< (@ 0x000006C8) A/D Conversion Data Operation Control B Register + * 12 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB12_b; + }; + + union + { + __IOM uint32_t ADDOPCRC12; /*!< (@ 0x000006CC) A/D Conversion Data Operation Control C Register + * 12 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC12_b; + }; + + union + { + __IOM uint32_t ADCHCR13; /*!< (@ 0x000006D0) A/D Conversion Channel Configuration Register + * 13 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR13_b; + }; + + union + { + __IOM uint32_t ADDOPCRA13; /*!< (@ 0x000006D4) A/D Conversion Data Operation Control A Register + * 13 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA13_b; + }; + + union + { + __IOM uint32_t ADDOPCRB13; /*!< (@ 0x000006D8) A/D Conversion Data Operation Control B Register + * 13 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB13_b; + }; + + union + { + __IOM uint32_t ADDOPCRC13; /*!< (@ 0x000006DC) A/D Conversion Data Operation Control C Register + * 13 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC13_b; + }; + + union + { + __IOM uint32_t ADCHCR14; /*!< (@ 0x000006E0) A/D Conversion Channel Configuration Register + * 14 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR14_b; + }; + + union + { + __IOM uint32_t ADDOPCRA14; /*!< (@ 0x000006E4) A/D Conversion Data Operation Control A Register + * 14 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA14_b; + }; + + union + { + __IOM uint32_t ADDOPCRB14; /*!< (@ 0x000006E8) A/D Conversion Data Operation Control B Register + * 14 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB14_b; + }; + + union + { + __IOM uint32_t ADDOPCRC14; /*!< (@ 0x000006EC) A/D Conversion Data Operation Control C Register + * 14 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC14_b; + }; + + union + { + __IOM uint32_t ADCHCR15; /*!< (@ 0x000006F0) A/D Conversion Channel Configuration Register + * 15 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR15_b; + }; + + union + { + __IOM uint32_t ADDOPCRA15; /*!< (@ 0x000006F4) A/D Conversion Data Operation Control A Register + * 15 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA15_b; + }; + + union + { + __IOM uint32_t ADDOPCRB15; /*!< (@ 0x000006F8) A/D Conversion Data Operation Control B Register + * 15 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB15_b; + }; + + union + { + __IOM uint32_t ADDOPCRC15; /*!< (@ 0x000006FC) A/D Conversion Data Operation Control C Register + * 15 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC15_b; + }; + + union + { + __IOM uint32_t ADCHCR16; /*!< (@ 0x00000700) A/D Conversion Channel Configuration Register + * 16 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR16_b; + }; + + union + { + __IOM uint32_t ADDOPCRA16; /*!< (@ 0x00000704) A/D Conversion Data Operation Control A Register + * 16 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA16_b; + }; + + union + { + __IOM uint32_t ADDOPCRB16; /*!< (@ 0x00000708) A/D Conversion Data Operation Control B Register + * 16 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB16_b; + }; + + union + { + __IOM uint32_t ADDOPCRC16; /*!< (@ 0x0000070C) A/D Conversion Data Operation Control C Register + * 16 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC16_b; + }; + + union + { + __IOM uint32_t ADCHCR17; /*!< (@ 0x00000710) A/D Conversion Channel Configuration Register + * 17 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR17_b; + }; + + union + { + __IOM uint32_t ADDOPCRA17; /*!< (@ 0x00000714) A/D Conversion Data Operation Control A Register + * 17 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA17_b; + }; + + union + { + __IOM uint32_t ADDOPCRB17; /*!< (@ 0x00000718) A/D Conversion Data Operation Control B Register + * 17 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB17_b; + }; + + union + { + __IOM uint32_t ADDOPCRC17; /*!< (@ 0x0000071C) A/D Conversion Data Operation Control C Register + * 17 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC17_b; + }; + + union + { + __IOM uint32_t ADCHCR18; /*!< (@ 0x00000720) A/D Conversion Channel Configuration Register + * 18 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR18_b; + }; + + union + { + __IOM uint32_t ADDOPCRA18; /*!< (@ 0x00000724) A/D Conversion Data Operation Control A Register + * 18 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA18_b; + }; + + union + { + __IOM uint32_t ADDOPCRB18; /*!< (@ 0x00000728) A/D Conversion Data Operation Control B Register + * 18 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB18_b; + }; + + union + { + __IOM uint32_t ADDOPCRC18; /*!< (@ 0x0000072C) A/D Conversion Data Operation Control C Register + * 18 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC18_b; + }; + + union + { + __IOM uint32_t ADCHCR19; /*!< (@ 0x00000730) A/D Conversion Channel Configuration Register + * 19 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR19_b; + }; + + union + { + __IOM uint32_t ADDOPCRA19; /*!< (@ 0x00000734) A/D Conversion Data Operation Control A Register + * 19 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA19_b; + }; + + union + { + __IOM uint32_t ADDOPCRB19; /*!< (@ 0x00000738) A/D Conversion Data Operation Control B Register + * 19 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB19_b; + }; + + union + { + __IOM uint32_t ADDOPCRC19; /*!< (@ 0x0000073C) A/D Conversion Data Operation Control C Register + * 19 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC19_b; + }; + + union + { + __IOM uint32_t ADCHCR20; /*!< (@ 0x00000740) A/D Conversion Channel Configuration Register + * 20 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR20_b; + }; + + union + { + __IOM uint32_t ADDOPCRA20; /*!< (@ 0x00000744) A/D Conversion Data Operation Control A Register + * 20 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA20_b; + }; + + union + { + __IOM uint32_t ADDOPCRB20; /*!< (@ 0x00000748) A/D Conversion Data Operation Control B Register + * 20 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB20_b; + }; + + union + { + __IOM uint32_t ADDOPCRC20; /*!< (@ 0x0000074C) A/D Conversion Data Operation Control C Register + * 20 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC20_b; + }; + + union + { + __IOM uint32_t ADCHCR21; /*!< (@ 0x00000750) A/D Conversion Channel Configuration Register + * 21 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR21_b; + }; + + union + { + __IOM uint32_t ADDOPCRA21; /*!< (@ 0x00000754) A/D Conversion Data Operation Control A Register + * 21 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA21_b; + }; + + union + { + __IOM uint32_t ADDOPCRB21; /*!< (@ 0x00000758) A/D Conversion Data Operation Control B Register + * 21 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB21_b; + }; + + union + { + __IOM uint32_t ADDOPCRC21; /*!< (@ 0x0000075C) A/D Conversion Data Operation Control C Register + * 21 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC21_b; + }; + + union + { + __IOM uint32_t ADCHCR22; /*!< (@ 0x00000760) A/D Conversion Channel Configuration Register + * 22 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR22_b; + }; + + union + { + __IOM uint32_t ADDOPCRA22; /*!< (@ 0x00000764) A/D Conversion Data Operation Control A Register + * 22 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA22_b; + }; + + union + { + __IOM uint32_t ADDOPCRB22; /*!< (@ 0x00000768) A/D Conversion Data Operation Control B Register + * 22 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB22_b; + }; + + union + { + __IOM uint32_t ADDOPCRC22; /*!< (@ 0x0000076C) A/D Conversion Data Operation Control C Register + * 22 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC22_b; + }; + + union + { + __IOM uint32_t ADCHCR23; /*!< (@ 0x00000770) A/D Conversion Channel Configuration Register + * 23 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR23_b; + }; + + union + { + __IOM uint32_t ADDOPCRA23; /*!< (@ 0x00000774) A/D Conversion Data Operation Control A Register + * 23 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA23_b; + }; + + union + { + __IOM uint32_t ADDOPCRB23; /*!< (@ 0x00000778) A/D Conversion Data Operation Control B Register + * 23 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB23_b; + }; + + union + { + __IOM uint32_t ADDOPCRC23; /*!< (@ 0x0000077C) A/D Conversion Data Operation Control C Register + * 23 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC23_b; + }; + + union + { + __IOM uint32_t ADCHCR24; /*!< (@ 0x00000780) A/D Conversion Channel Configuration Register + * 24 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR24_b; + }; + + union + { + __IOM uint32_t ADDOPCRA24; /*!< (@ 0x00000784) A/D Conversion Data Operation Control A Register + * 24 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA24_b; + }; + + union + { + __IOM uint32_t ADDOPCRB24; /*!< (@ 0x00000788) A/D Conversion Data Operation Control B Register + * 24 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB24_b; + }; + + union + { + __IOM uint32_t ADDOPCRC24; /*!< (@ 0x0000078C) A/D Conversion Data Operation Control C Register + * 24 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC24_b; + }; + + union + { + __IOM uint32_t ADCHCR25; /*!< (@ 0x00000790) A/D Conversion Channel Configuration Register + * 25 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR25_b; + }; + + union + { + __IOM uint32_t ADDOPCRA25; /*!< (@ 0x00000794) A/D Conversion Data Operation Control A Register + * 25 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA25_b; + }; + + union + { + __IOM uint32_t ADDOPCRB25; /*!< (@ 0x00000798) A/D Conversion Data Operation Control B Register + * 25 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB25_b; + }; + + union + { + __IOM uint32_t ADDOPCRC25; /*!< (@ 0x0000079C) A/D Conversion Data Operation Control C Register + * 25 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC25_b; + }; + + union + { + __IOM uint32_t ADCHCR26; /*!< (@ 0x000007A0) A/D Conversion Channel Configuration Register + * 26 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR26_b; + }; + + union + { + __IOM uint32_t ADDOPCRA26; /*!< (@ 0x000007A4) A/D Conversion Data Operation Control A Register + * 26 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA26_b; + }; + + union + { + __IOM uint32_t ADDOPCRB26; /*!< (@ 0x000007A8) A/D Conversion Data Operation Control B Register + * 26 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB26_b; + }; + + union + { + __IOM uint32_t ADDOPCRC26; /*!< (@ 0x000007AC) A/D Conversion Data Operation Control C Register + * 26 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC26_b; + }; + + union + { + __IOM uint32_t ADCHCR27; /*!< (@ 0x000007B0) A/D Conversion Channel Configuration Register + * 27 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR27_b; + }; + + union + { + __IOM uint32_t ADDOPCRA27; /*!< (@ 0x000007B4) A/D Conversion Data Operation Control A Register + * 27 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA27_b; + }; + + union + { + __IOM uint32_t ADDOPCRB27; /*!< (@ 0x000007B8) A/D Conversion Data Operation Control B Register + * 27 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB27_b; + }; + + union + { + __IOM uint32_t ADDOPCRC27; /*!< (@ 0x000007BC) A/D Conversion Data Operation Control C Register + * 27 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC27_b; + }; + + union + { + __IOM uint32_t ADCHCR28; /*!< (@ 0x000007C0) A/D Conversion Channel Configuration Register + * 28 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR28_b; + }; + + union + { + __IOM uint32_t ADDOPCRA28; /*!< (@ 0x000007C4) A/D Conversion Data Operation Control A Register + * 28 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA28_b; + }; + + union + { + __IOM uint32_t ADDOPCRB28; /*!< (@ 0x000007C8) A/D Conversion Data Operation Control B Register + * 28 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB28_b; + }; + + union + { + __IOM uint32_t ADDOPCRC28; /*!< (@ 0x000007CC) A/D Conversion Data Operation Control C Register + * 28 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC28_b; + }; + + union + { + __IOM uint32_t ADCHCR29; /*!< (@ 0x000007D0) A/D Conversion Channel Configuration Register + * 29 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR29_b; + }; + + union + { + __IOM uint32_t ADDOPCRA29; /*!< (@ 0x000007D4) A/D Conversion Data Operation Control A Register + * 29 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA29_b; + }; + + union + { + __IOM uint32_t ADDOPCRB29; /*!< (@ 0x000007D8) A/D Conversion Data Operation Control B Register + * 29 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB29_b; + }; + + union + { + __IOM uint32_t ADDOPCRC29; /*!< (@ 0x000007DC) A/D Conversion Data Operation Control C Register + * 29 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC29_b; + }; + + union + { + __IOM uint32_t ADCHCR30; /*!< (@ 0x000007E0) A/D Conversion Channel Configuration Register + * 30 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR30_b; + }; + + union + { + __IOM uint32_t ADDOPCRA30; /*!< (@ 0x000007E4) A/D Conversion Data Operation Control A Register + * 30 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA30_b; + }; + + union + { + __IOM uint32_t ADDOPCRB30; /*!< (@ 0x000007E8) A/D Conversion Data Operation Control B Register + * 30 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB30_b; + }; + + union + { + __IOM uint32_t ADDOPCRC30; /*!< (@ 0x000007EC) A/D Conversion Data Operation Control C Register + * 30 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC30_b; + }; + + union + { + __IOM uint32_t ADCHCR31; /*!< (@ 0x000007F0) A/D Conversion Channel Configuration Register + * 31 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR31_b; + }; + + union + { + __IOM uint32_t ADDOPCRA31; /*!< (@ 0x000007F4) A/D Conversion Data Operation Control A Register + * 31 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA31_b; + }; + + union + { + __IOM uint32_t ADDOPCRB31; /*!< (@ 0x000007F8) A/D Conversion Data Operation Control B Register + * 31 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB31_b; + }; + + union + { + __IOM uint32_t ADDOPCRC31; /*!< (@ 0x000007FC) A/D Conversion Data Operation Control C Register + * 31 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC31_b; + }; + + union + { + __IOM uint32_t ADCHCR32; /*!< (@ 0x00000800) A/D Conversion Channel Configuration Register + * 32 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR32_b; + }; + + union + { + __IOM uint32_t ADDOPCRA32; /*!< (@ 0x00000804) A/D Conversion Data Operation Control A Register + * 32 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA32_b; + }; + + union + { + __IOM uint32_t ADDOPCRB32; /*!< (@ 0x00000808) A/D Conversion Data Operation Control B Register + * 32 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB32_b; + }; + + union + { + __IOM uint32_t ADDOPCRC32; /*!< (@ 0x0000080C) A/D Conversion Data Operation Control C Register + * 32 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC32_b; + }; + __IM uint32_t RESERVED27[252]; + + union + { + __OM uint32_t ADCALSTR; /*!< (@ 0x00000C00) A/D Converter Calibration Start Register */ + + struct + { + __OM uint32_t ADCALST0 : 3; /*!< [2..0] A/D Converter Unit 0 (ADC0) Calibration Start Control + * bits */ + uint32_t : 5; + __OM uint32_t ADCALST1 : 3; /*!< [10..8] A/D Converter Unit 1 (ADC1) Calibration Start Control + * bits */ + uint32_t : 21; + } ADCALSTR_b; + }; + __IM uint32_t RESERVED28; + + union + { + __IOM uint32_t ADTRGENR; /*!< (@ 0x00000C08) A/D Conversion Start Trigger Enable Register */ + + struct + { + __IOM uint32_t STTRGENn : 9; /*!< [8..0] Scan Group n A/D Conversion Start Trigger Enable */ + uint32_t : 23; + } ADTRGENR_b; + }; + __IM uint32_t RESERVED29; + + union + { + __OM uint32_t ADSYSTR; /*!< (@ 0x00000C10) A/D Conversion Synchronous Software Start Register */ + + struct + { + __OM uint32_t ADSYSTn : 9; /*!< [8..0] Scan Group n : A/D Conversion start */ + uint32_t : 23; + } ADSYSTR_b; + }; + __IM uint32_t RESERVED30[3]; + + union + { + __OM uint32_t ADSTR[9]; /*!< (@ 0x00000C20) A/D Conversion Software Start Register [0..8] */ + + struct + { + __OM uint32_t ADST : 1; /*!< [0..0] Scan Group n A/D Conversion Start */ + uint32_t : 31; + } ADSTR_b[9]; + }; + __IM uint32_t RESERVED31[7]; + + union + { + __OM uint32_t ADSTOPR; /*!< (@ 0x00000C60) A/D Conversion Stop Register */ + + struct + { + __OM uint32_t ADSTOP0 : 1; /*!< [0..0] A/D Converter Unit 0 Force Stop bit */ + uint32_t : 7; + __OM uint32_t ADSTOP1 : 1; /*!< [8..8] A/D Converter Unit 1 Force Stop bit */ + uint32_t : 23; + } ADSTOPR_b; + }; + __IM uint32_t RESERVED32[7]; + + union + { + __IM uint32_t ADSR; /*!< (@ 0x00000C80) A/D Conversion Status Register */ + + struct + { + __IM uint32_t ADACT0 : 1; /*!< [0..0] A/D Converter Unit 0 (ADC0) A/D Conversion Status */ + __IM uint32_t ADACT1 : 1; /*!< [1..1] A/D Converter Unit 1 (ADC1) A/D Conversion Status */ + uint32_t : 14; + __IM uint32_t CALACT0 : 1; /*!< [16..16] A/D Converter Unit 0 (ADC0) : Calibration Status */ + __IM uint32_t CALACT1 : 1; /*!< [17..17] A/D Converter Unit 1 (ADC1) : Calibration Status */ + uint32_t : 14; + } ADSR_b; + }; + + union + { + __IM uint32_t ADGRSR; /*!< (@ 0x00000C84) Scan Group Status Register */ + + struct + { + __IM uint32_t ACTGRn : 9; /*!< [8..0] Scan Group n Status */ + uint32_t : 23; + } ADGRSR_b; + }; + + union + { + __IM uint32_t ADERSR; /*!< (@ 0x00000C88) A/D Conversion Error Status Register */ + + struct + { + __IM uint32_t ADERF0 : 1; /*!< [0..0] A/D Converter Unit 0 (ADC0) Error Flag */ + __IM uint32_t ADERF1 : 1; /*!< [1..1] A/D Converter Unit 1 (ADC1) Error Flag */ + uint32_t : 30; + } ADERSR_b; + }; + + union + { + __OM uint32_t ADERSCR; /*!< (@ 0x00000C8C) A/D Conversion Error Status Clear Register */ + + struct + { + __OM uint32_t ADERCLR0 : 1; /*!< [0..0] A/D Converter Unit 0 Error Flag Clear */ + __OM uint32_t ADERCLR1 : 1; /*!< [1..1] A/D Converter Unit 1 Error Flag Clear */ + uint32_t : 30; + } ADERSCR_b; + }; + __IM uint32_t RESERVED33[2]; + + union + { + __IM uint32_t ADCALENDSR; /*!< (@ 0x00000C98) A/D Converter Calibration End Status Register */ + + struct + { + __IM uint32_t CALENDF0 : 1; /*!< [0..0] A/D Converter Unit 0 Calibration End flag */ + __IM uint32_t CALENDF1 : 1; /*!< [1..1] A/D Converter Unit 1 Calibration End flag */ + uint32_t : 30; + } ADCALENDSR_b; + }; + + union + { + __OM uint32_t ADCALENDSCR; /*!< (@ 0x00000C9C) A/D Converter Calibration End Status Clear Register */ + + struct + { + __OM uint32_t CALENDC0 : 1; /*!< [0..0] A/D Converter Unit 0 Calibration End Flag Clear */ + __OM uint32_t CALENDC1 : 1; /*!< [1..1] A/D Converter Unit 1 Calibration End Flag Clear */ + uint32_t : 30; + } ADCALENDSCR_b; + }; + + union + { + __IM uint32_t ADOVFERSR; /*!< (@ 0x00000CA0) A/D Conversion Overflow Error Status Register */ + + struct + { + __IM uint32_t ADOVFEF0 : 1; /*!< [0..0] A/D Converter Unit 0 (ADC0) Overflow Error Flag */ + __IM uint32_t ADOVFEF1 : 1; /*!< [1..1] A/D Converter Unit 1 (ADC1) Overflow Error Flag */ + uint32_t : 30; + } ADOVFERSR_b; + }; + + union + { + __IM uint32_t ADOVFCHSR0; /*!< (@ 0x00000CA4) A/D Conversion Overflow Channel Status Register + * 0 */ + + struct + { + __IM uint32_t OVFCHFn : 23; /*!< [22..0] Analog Input Channel No. n : Overflow Flag */ + uint32_t : 9; + } ADOVFCHSR0_b; + }; + __IM uint32_t RESERVED34[2]; + + union + { + __IM uint32_t ADOVFEXSR; /*!< (@ 0x00000CB0) Extended Analog A/D Conversion Overflow Status + * Register */ + + struct + { + __IM uint32_t OVFEXF0 : 1; /*!< [0..0] Self-diagnosis Channel for A/D unit 0: Overflow Flag */ + __IM uint32_t OVFEXF1 : 1; /*!< [1..1] Self-diagnosis Channel for A/D unit 1: Overflow Flag */ + uint32_t : 2; + __IM uint32_t OVFEXF4 : 1; /*!< [4..4] Temperature Sensor Channel: Overflow Flag */ + __IM uint32_t OVFEXF5 : 1; /*!< [5..5] Internal Reference Voltage Channel: Overflow Flag */ + __IM uint32_t OVFEXF6 : 1; /*!< [6..6] VBATT 1/3 voltage monitor output Channel: Overflow Flag */ + uint32_t : 1; + __IM uint32_t OVFEXF8 : 1; /*!< [8..8] D/A Converter 0 Channel: Overflow Flag */ + __IM uint32_t OVFEXF9 : 1; /*!< [9..9] D/A Converter 1 Channel: Overflow Flag */ + uint32_t : 6; + __IM uint32_t OVFEXF16 : 1; /*!< [16..16] Self-diagnosis Channel for Sample-and-hold circuit + * unit0: Overflow Flag */ + __IM uint32_t OVFEXF17 : 1; /*!< [17..17] Self-diagnosis Channel for Sample-and-hold circuit + * unit1: Overflow Flag */ + __IM uint32_t OVFEXF18 : 1; /*!< [18..18] Self-diagnosis Channel for Sample-and-hold circuit + * unit2: Overflow Flag */ + uint32_t : 1; + __IM uint32_t OVFEXF20 : 1; /*!< [20..20] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Overflow Flag */ + __IM uint32_t OVFEXF21 : 1; /*!< [21..21] Self-diagnosis Channel for Sample-and-hold circuit + * unit5: Overflow Flag */ + __IM uint32_t OVFEXF22 : 1; /*!< [22..22] Self-diagnosis Channel for Sample-and-hold circuit + * unit6: Overflow Flag */ + uint32_t : 9; + } ADOVFEXSR_b; + }; + + union + { + __OM uint32_t ADOVFERSCR; /*!< (@ 0x00000CB4) A/D Conversion Overflow Error Status Clear Register */ + + struct + { + __OM uint32_t ADOVFEC0 : 1; /*!< [0..0] A/D Converter Unit 0 (ADC0) Overflow Error Flag Clear */ + __OM uint32_t ADOVFEC1 : 1; /*!< [1..1] A/D Converter Unit 1 (ADC1) Overflow Error Flag Clear */ + uint32_t : 30; + } ADOVFERSCR_b; + }; + + union + { + __OM uint32_t ADOVFCHSCR0; /*!< (@ 0x00000CB8) A/D Conversion Overflow Channel Status Clear + * Register 0 */ + + struct + { + __OM uint32_t OVFCHCn : 23; /*!< [22..0] Analog Input Channel No. n : Overflow Flag Clear */ + uint32_t : 9; + } ADOVFCHSCR0_b; + }; + __IM uint32_t RESERVED35[2]; + + union + { + __OM uint32_t ADOVFEXSCR; /*!< (@ 0x00000CC4) Extended Analog A/D Conversion Overflow Status + * Clear Register */ + + struct + { + __OM uint32_t OVFEXC0 : 1; /*!< [0..0] Self-diagnosis Channel for A/D unit 0: Compare Match + * Flag Clear */ + __OM uint32_t OVFEXC1 : 1; /*!< [1..1] Self-diagnosis Channel for A/D unit 1: Compare Match + * Flag Clear */ + uint32_t : 2; + __OM uint32_t OVFEXC4 : 1; /*!< [4..4] Temperature Sensor Channel: Compare Match Flag Clear */ + __OM uint32_t OVFEXC5 : 1; /*!< [5..5] Internal Reference Voltage Channel: Compare Match Flag + * Clear */ + __OM uint32_t OVFEXC6 : 1; /*!< [6..6] VBATT 1/3 voltage monitor output Channel: Compare Match + * Flag Clear */ + uint32_t : 1; + __OM uint32_t OVFEXC8 : 1; /*!< [8..8] D/A Converter 0 Channel: Compare Match Flag Clear */ + __OM uint32_t OVFEXC9 : 1; /*!< [9..9] D/A Converter 1 Channel: Compare Match Flag Clear */ + uint32_t : 6; + __OM uint32_t OVFEXC16 : 1; /*!< [16..16] Self-diagnosis Channel for Sample-and-hold circuit + * unit0: Compare Match Flag Clear */ + __OM uint32_t OVFEXC17 : 1; /*!< [17..17] Self-diagnosis Channel for Sample-and-hold circuit + * unit1: Compare Match Flag Clear */ + __OM uint32_t OVFEXC18 : 1; /*!< [18..18] Self-diagnosis Channel for Sample-and-hold circuit + * unit2: Compare Match Flag Clear */ + uint32_t : 1; + __OM uint32_t OVFEXC20 : 1; /*!< [20..20] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Compare Match Flag Clear */ + __OM uint32_t OVFEXC21 : 1; /*!< [21..21] Self-diagnosis Channel for Sample-and-hold circuit + * unit5: Compare Match Flag Clear */ + __OM uint32_t OVFEXC22 : 1; /*!< [22..22] Self-diagnosis Channel for Sample-and-hold circuit + * unit6: Compare Match Flag Clear */ + uint32_t : 9; + } ADOVFEXSCR_b; + }; + __IM uint32_t RESERVED36[2]; + + union + { + __IM uint32_t ADFIFOSR0; /*!< (@ 0x00000CD0) FIFO Status Register 0 */ + + struct + { + __IM uint32_t FIFOST0 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 0 */ + uint32_t : 12; + __IM uint32_t FIFOST1 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 1 */ + uint32_t : 12; + } ADFIFOSR0_b; + }; + + union + { + __IM uint32_t ADFIFOSR1; /*!< (@ 0x00000CD4) FIFO Status Register 1 */ + + struct + { + __IM uint32_t FIFOST2 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 2 */ + uint32_t : 12; + __IM uint32_t FIFOST3 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 3 */ + uint32_t : 12; + } ADFIFOSR1_b; + }; + + union + { + __IM uint32_t ADFIFOSR2; /*!< (@ 0x00000CD8) FIFO Status Register 2 */ + + struct + { + __IM uint32_t FIFOST4 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 4 */ + uint32_t : 12; + __IM uint32_t FIFOST5 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 5 */ + uint32_t : 12; + } ADFIFOSR2_b; + }; + + union + { + __IM uint32_t ADFIFOSR3; /*!< (@ 0x00000CDC) FIFO Status Register 3 */ + + struct + { + __IM uint32_t FIFOST6 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 6 */ + uint32_t : 12; + __IM uint32_t FIFOST7 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 7 */ + uint32_t : 12; + } ADFIFOSR3_b; + }; + + union + { + __IM uint32_t ADFIFOSR4; /*!< (@ 0x00000CE0) FIFO Status Register 4 */ + + struct + { + __IM uint32_t FIFOST8 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 8 */ + uint32_t : 28; + } ADFIFOSR4_b; + }; + __IM uint32_t RESERVED37[3]; + + union + { + __OM uint32_t ADFIFODCR; /*!< (@ 0x00000CF0) FIFO Data Clear Register */ + + struct + { + __OM uint32_t FIFODCn : 9; /*!< [8..0] Scan Group n FIFO Data Clear */ + uint32_t : 23; + } ADFIFODCR_b; + }; + + union + { + __IM uint32_t ADFIFOERSR; /*!< (@ 0x00000CF4) FIFO Error Status Register */ + + struct + { + __IM uint32_t FIFOOVFn : 9; /*!< [8..0] Scan Group n FIFO Overflow Flag */ + uint32_t : 7; + __IM uint32_t FIFOFLFn : 9; /*!< [24..16] Scan Group n FIFO Data Full Flag */ + uint32_t : 7; + } ADFIFOERSR_b; + }; + + union + { + __OM uint32_t ADFIFOERSCR; /*!< (@ 0x00000CF8) FIFO Error Status Clear Register */ + + struct + { + __OM uint32_t FIFOOVFCn : 9; /*!< [8..0] Scan Group n FIFO Overflow Flag Clear */ + uint32_t : 7; + __OM uint32_t FIFOFLCn : 9; /*!< [24..16] Scan Group n FIFO Data Full Flag Clear */ + uint32_t : 7; + } ADFIFOERSCR_b; + }; + __IM uint32_t RESERVED38; + + union + { + __IM uint32_t ADCMPTBSR; /*!< (@ 0x00000D00) Compare Match Table Status Register */ + + struct + { + __IM uint32_t CMPTBFn : 8; /*!< [7..0] Compare Match Table n Match Flag */ + uint32_t : 24; + } ADCMPTBSR_b; + }; + + union + { + __OM uint32_t ADCMPTBSCR; /*!< (@ 0x00000D04) Compare Match Table Status Clear Register */ + + struct + { + __OM uint32_t CMPTBCn : 8; /*!< [7..0] Compare Match Table n : Match Flag Clear */ + uint32_t : 24; + } ADCMPTBSCR_b; + }; + + union + { + __IM uint32_t ADCMPCHSR0; /*!< (@ 0x00000D08) Compare Match Channel Status Register 0 */ + + struct + { + __IM uint32_t CMPCHFn : 23; /*!< [22..0] Analog Channel No. n : Compare Match Flag */ + uint32_t : 9; + } ADCMPCHSR0_b; + }; + __IM uint32_t RESERVED39[2]; + + union + { + __IM uint32_t ADCMPEXSR; /*!< (@ 0x00000D14) Extended Analog Compare Match Status Register */ + + struct + { + __IM uint32_t CMPEXF0 : 1; /*!< [0..0] Self-diagnosis Channel for A/D unit 0: Compare Match + * Flag */ + __IM uint32_t CMPEXF1 : 1; /*!< [1..1] Self-diagnosis Channel for A/D unit 1: Compare Match + * Flag */ + uint32_t : 2; + __IM uint32_t CMPEXF4 : 1; /*!< [4..4] Temperature Sensor Channel: Compare Match Flag */ + __IM uint32_t CMPEXF5 : 1; /*!< [5..5] Internal Reference Voltage Channel: Compare Match Flag */ + __IM uint32_t CMPEXF6 : 1; /*!< [6..6] VBATT 1/3 voltage monitor output Channel: Compare Match + * Flag */ + uint32_t : 1; + __IM uint32_t CMPEXF8 : 1; /*!< [8..8] D/A Converter 0 Channel : Compare Match Flag */ + __IM uint32_t CMPEXF9 : 1; /*!< [9..9] D/A Converter 1 Channel: Compare Match Flag */ + uint32_t : 6; + __IM uint32_t CMPEXF16 : 1; /*!< [16..16] Self-diagnosis Channel for Sample-and-hold circuit + * unit0: Compare Match Flag */ + __IM uint32_t CMPEXF17 : 1; /*!< [17..17] Self-diagnosis Channel for Sample-and-hold circuit + * unit1: Compare Match Flag */ + __IM uint32_t CMPEXF18 : 1; /*!< [18..18] Self-diagnosis Channel for Sample-and-hold circuit + * unit2: Compare Match Flag */ + uint32_t : 1; + __IM uint32_t CMPEXF20 : 1; /*!< [20..20] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Compare Match Flag */ + __IM uint32_t CMPEXF21 : 1; /*!< [21..21] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Compare Match Flag */ + __IM uint32_t CMPEXF22 : 1; /*!< [22..22] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Compare Match Flag */ + uint32_t : 9; + } ADCMPEXSR_b; + }; + + union + { + __OM uint32_t ADCMPCHSCR0; /*!< (@ 0x00000D18) Compare Match Channel Status Clear Register 0 */ + + struct + { + __OM uint32_t CMPCHCn : 23; /*!< [22..0] Analog Channel No. n : Compare Match Flag Clear bit */ + uint32_t : 9; + } ADCMPCHSCR0_b; + }; + __IM uint32_t RESERVED40[2]; + + union + { + __OM uint32_t ADCMPEXSCR; /*!< (@ 0x00000D24) Extended Analog Compare Match Status Clear Register */ + + struct + { + __OM uint32_t CMPEXC0 : 1; /*!< [0..0] Self-diagnosis Channel for A/D unit 0: Compare Match + * Flag Clear */ + __OM uint32_t CMPEXC1 : 1; /*!< [1..1] Self-diagnosis Channel for A/D unit 1: Compare Match + * Flag Clear */ + uint32_t : 2; + __OM uint32_t CMPEXC4 : 1; /*!< [4..4] Temperature Sensor Channel: Compare Match Flag Clear */ + __OM uint32_t CMPEXC5 : 1; /*!< [5..5] Internal Reference Voltage Channel: Compare Match Flag + * Clear */ + __OM uint32_t CMPEXC6 : 1; /*!< [6..6] VBATT 1/3 voltage monitor output Channel: Compare Match + * Flag Clear */ + uint32_t : 1; + __OM uint32_t CMPEXC8 : 1; /*!< [8..8] D/A Converter 0 Channel: Compare Match Flag Clear */ + __OM uint32_t CMPEXC9 : 1; /*!< [9..9] D/A Converter 1 Channel : Compare Match Flag Clear */ + uint32_t : 6; + __OM uint32_t CMPEXC16 : 1; /*!< [16..16] Self-diagnosis Channel for Sample-and-hold circuit + * unit0: Compare Match Flag Clear */ + __OM uint32_t CMPEXC17 : 1; /*!< [17..17] Self-diagnosis Channel for Sample-and-hold circuit + * unit1: Compare Match Flag Clear */ + __OM uint32_t CMPEXC18 : 1; /*!< [18..18] Self-diagnosis Channel for Sample-and-hold circuit + * unit2: Compare Match Flag Clear */ + uint32_t : 1; + __OM uint32_t CMPEXC20 : 1; /*!< [20..20] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Compare Match Flag Clear */ + __OM uint32_t CMPEXC21 : 1; /*!< [21..21] Self-diagnosis Channel for Sample-and-hold circuit + * unit5: Compare Match Flag Clear */ + __OM uint32_t CMPEXC22 : 1; /*!< [22..22] Self-diagnosis Channel for Sample-and-hold circuit + * unit6: Compare Match Flag Clear */ + uint32_t : 9; + } ADCMPEXSCR_b; + }; + + union + { + __IM uint32_t ADLIMGRSR; /*!< (@ 0x00000D28) Limiter Clip Scan Group Status Register */ + + struct + { + __IM uint32_t LIMGRFn : 9; /*!< [8..0] Scan Group n Limiter Clip Flag */ + uint32_t : 23; + } ADLIMGRSR_b; + }; + + union + { + __IM uint32_t ADLIMCHSR0; /*!< (@ 0x00000D2C) Limiter Clip Channel Status Register 0 */ + + struct + { + __IM uint32_t LIMCHFn : 23; /*!< [22..0] Analog Channel No. n : Limiter Clip Flag bit */ + uint32_t : 9; + } ADLIMCHSR0_b; + }; + __IM uint32_t RESERVED41[2]; + + union + { + __IM uint32_t ADLIMEXSR; /*!< (@ 0x00000D38) Extended Analog Limiter Clip Status Register */ + + struct + { + __IM uint32_t LIMEXF0 : 1; /*!< [0..0] Self-diagnosis Channel for A/D unit 0: Limiter Clip Flag */ + __IM uint32_t LIMEXF1 : 1; /*!< [1..1] Temperature Sensor Channel for A/D unit 1: Limiter Clip + * Flag */ + uint32_t : 2; + __IM uint32_t LIMEXF4 : 1; /*!< [4..4] Temperature Sensor Channel: Limiter Clip Flag */ + __IM uint32_t LIMEXF5 : 1; /*!< [5..5] Internal Reference Voltage Channel: Limiter Clip Flag */ + __IM uint32_t LIMEXF6 : 1; /*!< [6..6] VBATT 1/3 voltage monitor output Channel: Limiter Clip + * Flag */ + uint32_t : 1; + __IM uint32_t LIMEXF8 : 1; /*!< [8..8] D/A Converter 0 Channel: Limiter Clip Flag */ + __IM uint32_t LIMEXF9 : 1; /*!< [9..9] D/A Converter 1 Channel: Limiter Clip Flag */ + uint32_t : 6; + __IM uint32_t LIMEXF16 : 1; /*!< [16..16] Self-diagnosis Channel for Sample-and-hold circuit + * unit0: Limiter Clip Flag */ + __IM uint32_t LIMEXF17 : 1; /*!< [17..17] Self-diagnosis Channel for Sample-and-hold circuit + * unit1: Limiter Clip Flag */ + __IM uint32_t LIMEXF18 : 1; /*!< [18..18] Self-diagnosis Channel for Sample-and-hold circuit + * unit2: Limiter Clip Flag */ + uint32_t : 1; + __IM uint32_t LIMEXF20 : 1; /*!< [20..20] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Limiter Clip Flag */ + __IM uint32_t LIMEXF21 : 1; /*!< [21..21] Self-diagnosis Channel for Sample-and-hold circuit + * unit5: Limiter Clip Flag */ + __IM uint32_t LIMEXF22 : 1; /*!< [22..22] Self-diagnosis Channel for Sample-and-hold circuit + * unit6: Limiter Clip Flag */ + uint32_t : 9; + } ADLIMEXSR_b; + }; + + union + { + __OM uint32_t ADLIMGRSCR; /*!< (@ 0x00000D3C) Limiter Clip Scan Group Status Clear Register */ + + struct + { + __OM uint32_t LIMGRCn : 9; /*!< [8..0] Scan Group n Limiter Clip Flag Clear */ + uint32_t : 23; + } ADLIMGRSCR_b; + }; + + union + { + __OM uint32_t ADLIMCHSCR0; /*!< (@ 0x00000D40) Limiter Clip Channel Status Clear Register 0 */ + + struct + { + __OM uint32_t LIMCHCn : 23; /*!< [22..0] Analog Channel No. n Limiter Clip Flag Clear bit */ + uint32_t : 9; + } ADLIMCHSCR0_b; + }; + __IM uint32_t RESERVED42[2]; + + union + { + __OM uint32_t ADLIMEXSCR; /*!< (@ 0x00000D4C) Extended Analog Limiter Clip Status Clear Register */ + + struct + { + __OM uint32_t LIMEXF0 : 1; /*!< [0..0] Self-diagnosis Channel for A/D unit 0: Limiter Clip Flag + * Clear */ + __OM uint32_t LIMEXF1 : 1; /*!< [1..1] Self-diagnosis Channel for A/D unit 1: Limiter Clip Flag + * Clear */ + uint32_t : 2; + __OM uint32_t LIMEXF4 : 1; /*!< [4..4] Temperature Sensor Channel: Limiter Clip Flag Clear */ + __OM uint32_t LIMEXF5 : 1; /*!< [5..5] Internal Reference Voltage Channel: Limiter Clip Flag + * Clear */ + __OM uint32_t LIMEXF6 : 1; /*!< [6..6] VBATT 1/3 voltage monitor output Channel: Limiter Clip + * Flag Clear */ + uint32_t : 1; + __OM uint32_t LIMEXF8 : 1; /*!< [8..8] D/A Converter 0 Channel: Limiter Clip Flag Clear */ + __OM uint32_t LIMEXF9 : 1; /*!< [9..9] D/A Converter 1 Channel: Limiter Clip Flag Clear */ + uint32_t : 6; + __OM uint32_t LIMEXF16 : 1; /*!< [16..16] Self-diagnosis Channel for Sample-and-hold circuit + * unit0: Limiter Clip Flag Clear */ + __OM uint32_t LIMEXF17 : 1; /*!< [17..17] Self-diagnosis Channel for Sample-and-hold circuit + * unit1: Limiter Clip Flag Clear */ + __OM uint32_t LIMEXF18 : 1; /*!< [18..18] Self-diagnosis Channel for Sample-and-hold circuit + * unit2: Limiter Clip Flag Clear */ + uint32_t : 1; + __OM uint32_t LIMEXF20 : 1; /*!< [20..20] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Limiter Clip Flag Clear */ + __OM uint32_t LIMEXF21 : 1; /*!< [21..21] Self-diagnosis Channel for Sample-and-hold circuit + * unit5: Limiter Clip Flag Clear */ + __OM uint32_t LIMEXF22 : 1; /*!< [22..22] Self-diagnosis Channel for Sample-and-hold circuit + * unit6: Limiter Clip Flag Clear */ + uint32_t : 9; + } ADLIMEXSCR_b; + }; + + union + { + __IM uint32_t ADSCANENDSR; /*!< (@ 0x00000D50) Scan End Status Register */ + + struct + { + __IM uint32_t SCENDFn : 9; /*!< [8..0] Scan Group n Scan End Flag */ + uint32_t : 23; + } ADSCANENDSR_b; + }; + + union + { + __OM uint32_t ADSCANENDSCR; /*!< (@ 0x00000D54) Scan End Status Clear Register */ + + struct + { + __OM uint32_t SCENDCn : 9; /*!< [8..0] Scan Group n Scan End Flag Clear */ + uint32_t : 23; + } ADSCANENDSCR_b; + }; + __IM uint32_t RESERVED43[1194]; + + union + { + __IM uint32_t ADDR[23]; /*!< (@ 0x00002000) A/D Data Register [0..22] */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D conversion data */ + uint32_t : 15; + __IM uint32_t ERR : 1; /*!< [31..31] A/D conversion data error status */ + } ADDR_b[23]; + }; + __IM uint32_t RESERVED44[73]; + + union + { + __IM uint32_t ADEXDR[23]; /*!< (@ 0x00002180) A/D Extended Analog Data Register [0..22] */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D conversion data */ + uint32_t : 8; + __IM uint32_t DIAGSR : 3; /*!< [26..24] Self-Diagnosis Status */ + uint32_t : 4; + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Error Status */ + } ADEXDR_b[23]; + }; + __IM uint32_t RESERVED45[9]; + + union + { + __IM uint32_t ADFIFODR0; /*!< (@ 0x00002200) FIFO Data Register 0 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR0_b; + }; + + union + { + __IM uint32_t ADFIFODR1; /*!< (@ 0x00002204) FIFO Data Register 1 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR1_b; + }; + + union + { + __IM uint32_t ADFIFODR2; /*!< (@ 0x00002208) FIFO Data Register 2 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR2_b; + }; + + union + { + __IM uint32_t ADFIFODR3; /*!< (@ 0x0000220C) FIFO Data Register 3 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR3_b; + }; + + union + { + __IM uint32_t ADFIFODR4; /*!< (@ 0x00002210) FIFO Data Register 4 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR4_b; + }; + + union + { + __IM uint32_t ADFIFODR5; /*!< (@ 0x00002214) FIFO Data Register 5 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR5_b; + }; + + union + { + __IM uint32_t ADFIFODR6; /*!< (@ 0x00002218) FIFO Data Register 6 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR6_b; + }; + + union + { + __IM uint32_t ADFIFODR7; /*!< (@ 0x0000221C) FIFO Data Register 7 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR7_b; + }; + + union + { + __IM uint32_t ADFIFODR8; /*!< (@ 0x00002220) FIFO Data Register 8 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR8_b; + }; +} R_ADC_B0_Type; /*!< Size = 8740 (0x2224) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC_B ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC_B) + */ + +typedef struct /*!< (@ 0x40311000) R_DOC_B Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t DOBW : 1; /*!< [3..3] Data Operation Bit Width Select */ + __IOM uint8_t DCSEL : 3; /*!< [6..4] Detection Condition Select */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint8_t DOSR; /*!< (@ 0x00000004) DOC Flag Status Register */ + + struct + { + __IM uint8_t DOPCF : 1; /*!< [0..0] Data Operation Circuit Flag */ + uint8_t : 7; + } DOSR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t DOSCR; /*!< (@ 0x00000008) DOC Flag Status Clear Register */ + + struct + { + __OM uint8_t DOPCFCL : 1; /*!< [0..0] DOPCF Clear */ + uint8_t : 7; + } DOSCR_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DODIR; /*!< (@ 0x0000000C) DOC Data Input Register */ + __IOM uint32_t DODSR0; /*!< (@ 0x00000010) DOC Data Setting Register 0 */ + __IOM uint32_t DODSR1; /*!< (@ 0x00000014) DOC Data Setting Register 1 */ +} R_DOC_B_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI_B0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communication Interface 0 (R_SCI_B0) + */ + +typedef struct /*!< (@ 0x40358000) R_SCI_B0 Structure */ +{ + union + { + union + { + __IM uint32_t RDR; /*!< (@ 0x00000000) Receive Data Register */ + + struct + { + __IM uint32_t RDAT : 9; /*!< [8..0] Serial receive data */ + __IM uint32_t MPB : 1; /*!< [9..9] Multi-processor flag */ + __IM uint32_t DR : 1; /*!< [10..10] Receive data ready flag */ + __IM uint32_t FPER : 1; /*!< [11..11] FIFO parity error flag */ + __IM uint32_t FFER : 1; /*!< [12..12] FIFO framing error flag */ + uint32_t : 11; + __IM uint32_t ORER : 1; /*!< [24..24] Overrun Error flag */ + uint32_t : 2; + __IM uint32_t PER : 1; /*!< [27..27] Parity error flag */ + __IM uint32_t FER : 1; /*!< [28..28] Framing error flag */ + uint32_t : 3; + } RDR_b; + }; + + union + { + __IOM uint8_t RDR_BY; /*!< (@ 0x00000000) Receive Data Register (byte access) */ + + struct + { + __IOM uint8_t RDAT : 8; /*!< [7..0] Serial receive data */ + } RDR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t TDR; /*!< (@ 0x00000004) Transmit Data Register */ + + struct + { + __IOM uint32_t TDAT : 9; /*!< [8..0] Serial transmit data */ + __IOM uint32_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag */ + uint32_t : 2; + __IOM uint32_t TSYNC : 1; /*!< [12..12] Transmit SYNC data */ + uint32_t : 19; + } TDR_b; + }; + + union + { + __IOM uint8_t TDR_BY; /*!< (@ 0x00000004) Transmit Data Register (byte access) */ + + struct + { + __IOM uint8_t TDAT : 8; /*!< [7..0] Serial transmit data */ + } TDR_BY_b; + }; + }; + + union + { + __IOM uint32_t CCR0; /*!< (@ 0x00000008) Common Control Register 0 */ + + struct + { + __IOM uint32_t RE : 1; /*!< [0..0] Receive Enable */ + uint32_t : 3; + __IOM uint32_t TE : 1; /*!< [4..4] Transmit Enable */ + uint32_t : 3; + __IOM uint32_t MPIE : 1; /*!< [8..8] Multi-Processor Interrupt Enable */ + __IOM uint32_t DCME : 1; /*!< [9..9] Data Compare Match Enable */ + __IOM uint32_t IDSEL : 1; /*!< [10..10] ID frame select */ + uint32_t : 5; + __IOM uint32_t RIE : 1; /*!< [16..16] Receive Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TIE : 1; /*!< [20..20] Transmit Interrupt Enable */ + __IOM uint32_t TEIE : 1; /*!< [21..21] Transmit End Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SSE : 1; /*!< [24..24] SSn Pin Function Enable */ + uint32_t : 7; + } CCR0_b; + }; + + union + { + __IOM uint32_t CCR1; /*!< (@ 0x0000000C) Common Control Register 1 */ + + struct + { + __IOM uint32_t CTSE : 1; /*!< [0..0] CTS Enable */ + __IOM uint32_t CTSPEN : 1; /*!< [1..1] CTS external pin Enable */ + uint32_t : 2; + __IOM uint32_t SPB2DT : 1; /*!< [4..4] Serial port break data select */ + __IOM uint32_t SPB2IO : 1; /*!< [5..5] Serial port break I/O */ + uint32_t : 2; + __IOM uint32_t PE : 1; /*!< [8..8] Parity Enable */ + __IOM uint32_t PM : 1; /*!< [9..9] Parity Mode */ + uint32_t : 2; + __IOM uint32_t TINV : 1; /*!< [12..12] TXD invert */ + __IOM uint32_t RINV : 1; /*!< [13..13] RXD invert */ + uint32_t : 2; + __IOM uint32_t SPLP : 1; /*!< [16..16] Loopback Control */ + uint32_t : 3; + __IOM uint32_t SHARPS : 1; /*!< [20..20] Half-duplex communication select */ + uint32_t : 3; + __IOM uint32_t NFCS : 3; /*!< [26..24] Noise Filter Clock Select */ + uint32_t : 1; + __IOM uint32_t NFEN : 1; /*!< [28..28] Digital Noise Filter Function Enable */ + uint32_t : 3; + } CCR1_b; + }; + + union + { + __IOM uint32_t CCR2; /*!< (@ 0x00000010) Common Control Register 2 */ + + struct + { + __IOM uint32_t BCP : 3; /*!< [2..0] Base Clock Pulse */ + uint32_t : 1; + __IOM uint32_t BGDM : 1; /*!< [4..4] Baud Rate Generator Double-Speed Mode Select */ + __IOM uint32_t ABCS : 1; /*!< [5..5] Asynchronous Mode Base Clock Select */ + __IOM uint32_t ABCSE : 1; /*!< [6..6] Asynchronous Mode Extended Base Clock Select */ + uint32_t : 1; + __IOM uint32_t BRR : 8; /*!< [15..8] Bit rate setting */ + __IOM uint32_t BRME : 1; /*!< [16..16] Bit Modulation Enable */ + uint32_t : 3; + __IOM uint32_t CKS : 2; /*!< [21..20] Clock Select */ + uint32_t : 2; + __IOM uint32_t MDDR : 8; /*!< [31..24] Modulation Duty Setting */ + } CCR2_b; + }; + + union + { + __IOM uint32_t CCR3; /*!< (@ 0x00000014) Common Control Register 3 */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] Clock Phase Select */ + __IOM uint32_t CPOL : 1; /*!< [1..1] Clock Polarity Select */ + uint32_t : 5; + __IOM uint32_t BPEN : 1; /*!< [7..7] Synchronizer bypass enable */ + __IOM uint32_t CHR : 2; /*!< [9..8] Character Length */ + uint32_t : 2; + __IOM uint32_t LSBF : 1; /*!< [12..12] LSB First select */ + __IOM uint32_t SINV : 1; /*!< [13..13] Transmitted/Received Data Invert */ + __IOM uint32_t STP : 1; /*!< [14..14] Stop Bit Length */ + __IOM uint32_t RXDESEL : 1; /*!< [15..15] Asynchronous Start Bit Edge Detection Select */ + __IOM uint32_t MOD : 3; /*!< [18..16] Communication mode select */ + __IOM uint32_t MP : 1; /*!< [19..19] Multi-Processor Mode */ + __IOM uint32_t FM : 1; /*!< [20..20] FIFO Mode select */ + __IOM uint32_t DEN : 1; /*!< [21..21] Driver enable */ + uint32_t : 2; + __IOM uint32_t CKE : 2; /*!< [25..24] Clock enable */ + uint32_t : 2; + __IOM uint32_t GM : 1; /*!< [28..28] GSM Mode */ + __IOM uint32_t BLK : 1; /*!< [29..29] Block Transfer Mode */ + uint32_t : 2; + } CCR3_b; + }; + + union + { + __IOM uint32_t CCR4; /*!< (@ 0x00000018) Common Control Register 4 */ + + struct + { + __IOM uint32_t CMPD : 9; /*!< [8..0] Compare Match Data */ + uint32_t : 7; + __IOM uint32_t ASEN : 1; /*!< [16..16] Adjust receive sampling timing enable */ + __IOM uint32_t ATEN : 1; /*!< [17..17] Adjust transmit timing enable */ + uint32_t : 1; + __IOM uint32_t SCKSEL : 1; /*!< [19..19] Master receive clock selection bit. */ + uint32_t : 4; + __IOM uint32_t AST : 3; /*!< [26..24] Adjustment value for receive Sampling Timing */ + __IOM uint32_t AJD : 1; /*!< [27..27] Adjustment Direction for receive sampling timing */ + __IOM uint32_t ATT : 3; /*!< [30..28] Adjustment value for Transmit timing */ + __IOM uint32_t AET : 1; /*!< [31..31] Adjustment edge for transmit timing */ + } CCR4_b; + }; + + union + { + __IM uint8_t CESR; /*!< (@ 0x0000001C) Communication Enable Status Register */ + + struct + { + __IM uint8_t RIST : 1; /*!< [0..0] RE Internal status */ + uint8_t : 3; + __IM uint8_t TIST : 1; /*!< [4..4] TE Internal status */ + uint8_t : 3; + } CESR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t ICR; /*!< (@ 0x00000020) Simple I2C Control Register */ + + struct + { + __IOM uint32_t IICDL : 5; /*!< [4..0] SDA Delay Output Select */ + uint32_t : 3; + __IOM uint32_t IICINTM : 1; /*!< [8..8] IIC Interrupt Mode Select */ + __IOM uint32_t IICCSC : 1; /*!< [9..9] Clock Synchronization */ + uint32_t : 3; + __IOM uint32_t IICACKT : 1; /*!< [13..13] ACK Transmission Data */ + uint32_t : 2; + __IOM uint32_t IICSTAREQ : 1; /*!< [16..16] Start Condition Generation */ + __IOM uint32_t IICRSTAREQ : 1; /*!< [17..17] Restart Condition Generation */ + __IOM uint32_t IICSTPREQ : 1; /*!< [18..18] Stop Condition Generation */ + uint32_t : 1; + __IOM uint32_t IICSDAS : 2; /*!< [21..20] SDA Output Select */ + __IOM uint32_t IICSCLS : 2; /*!< [23..22] SCL Output Select */ + uint32_t : 8; + } ICR_b; + }; + + union + { + __IOM uint32_t FCR; /*!< (@ 0x00000024) FIFO Control Register */ + + struct + { + __IOM uint32_t DRES : 1; /*!< [0..0] Receive data ready error select bit */ + uint32_t : 7; + __IOM uint32_t TTRG : 5; /*!< [12..8] Transmit FIFO data trigger number */ + uint32_t : 2; + __OM uint32_t TFRST : 1; /*!< [15..15] Transmit FIFO Data Register Reset */ + __IOM uint32_t RTRG : 5; /*!< [20..16] Receive FIFO data trigger number */ + uint32_t : 2; + __OM uint32_t RFRST : 1; /*!< [23..23] Receive FIFO Data Register Reset */ + __IOM uint32_t RSTRG : 5; /*!< [28..24] RTS Output Active Trigger Number Select */ + uint32_t : 3; + } FCR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t MCR; /*!< (@ 0x0000002C) Manchester Control Register */ + + struct + { + __IOM uint32_t RMPOL : 1; /*!< [0..0] Polarity of Received Manchester Code */ + __IOM uint32_t TMPOL : 1; /*!< [1..1] Polarity of Transmit Manchester Code */ + __IOM uint32_t ERTEN : 1; /*!< [2..2] Manchester Edge Retiming Enable */ + uint32_t : 1; + __IOM uint32_t SYNVAL : 1; /*!< [4..4] SYNC value Setting */ + __IOM uint32_t SYNSEL : 1; /*!< [5..5] SYNC Select */ + __IOM uint32_t SBSEL : 1; /*!< [6..6] Start Bit Select */ + uint32_t : 1; + __IOM uint32_t TPLEN : 4; /*!< [11..8] Transmit preface length */ + __IOM uint32_t TPPAT : 2; /*!< [13..12] Transmit preface pattern */ + uint32_t : 2; + __IOM uint32_t RPLEN : 4; /*!< [19..16] Receive Preface Length */ + __IOM uint32_t RPPAT : 2; /*!< [21..20] Receive Preface Pattern */ + uint32_t : 2; + __IOM uint32_t PFEREN : 1; /*!< [24..24] Preface Error Enable */ + __IOM uint32_t SYEREN : 1; /*!< [25..25] Receive SYNC Error Enable */ + __IOM uint32_t SBEREN : 1; /*!< [26..26] Start Bit Error Enable */ + uint32_t : 5; + } MCR_b; + }; + + union + { + __IOM uint32_t DCR; /*!< (@ 0x00000030) Driver Control Register */ + + struct + { + __IOM uint32_t DEPOL : 1; /*!< [0..0] Driver effective polarity select */ + uint32_t : 7; + __IOM uint32_t DEAST : 5; /*!< [12..8] Driver Assertion Time */ + uint32_t : 3; + __IOM uint32_t DENGT : 5; /*!< [20..16] Driver negate time */ + uint32_t : 11; + } DCR_b; + }; + + union + { + __IOM uint32_t XCR0; /*!< (@ 0x00000034) Simple LIN(SCIX) Control Register 0 */ + + struct + { + __IOM uint32_t TCSS : 2; /*!< [1..0] Timer count clock source selection */ + uint32_t : 6; + __IOM uint32_t BFE : 1; /*!< [8..8] Break Field enable */ + __IOM uint32_t CF0RE : 1; /*!< [9..9] Control Field 0 enable */ + __IOM uint32_t CF1DS : 2; /*!< [11..10] Control Field1 compare data select */ + __IOM uint32_t PIBE : 1; /*!< [12..12] Priority interrupt bit enable */ + __IOM uint32_t PIBS : 3; /*!< [15..13] Priority interrupt bit select */ + __IOM uint32_t BFOIE : 1; /*!< [16..16] Break Field output completion interrupt enable */ + __IOM uint32_t BCDIE : 1; /*!< [17..17] Bus conflict detection interrupt enable */ + uint32_t : 2; + __IOM uint32_t BFDIE : 1; /*!< [20..20] Break Field detection interrupt enable */ + __IOM uint32_t COFIE : 1; /*!< [21..21] Counter overflow interrupt enable */ + __IOM uint32_t AEDIE : 1; /*!< [22..22] Active edge detection interrupt enable */ + uint32_t : 1; + __IOM uint32_t BCCS : 2; /*!< [25..24] Bus conflict detection clock selection */ + uint32_t : 6; + } XCR0_b; + }; + + union + { + __IOM uint32_t XCR1; /*!< (@ 0x00000038) Simple LIN(SCIX) Control Register 1 */ + + struct + { + __IOM uint32_t TCST : 1; /*!< [0..0] Break Field output timer count start trigger */ + uint32_t : 3; + __IOM uint32_t SDST : 1; /*!< [4..4] Start Frame detection enable */ + __IOM uint32_t BMEN : 1; /*!< [5..5] Bit rate measurement enable */ + uint32_t : 2; + __IOM uint32_t PCF1D : 8; /*!< [15..8] Priority compare data for Control Field 1 */ + __IOM uint32_t SCF1D : 8; /*!< [23..16] Secondary compare data for Control Field 1 */ + __IOM uint32_t CF1CE : 8; /*!< [31..24] Control Field 1 compare bit enable */ + } XCR1_b; + }; + + union + { + __IOM uint32_t XCR2; /*!< (@ 0x0000003C) Simple LIN(SCIX) Control Register 2 */ + + struct + { + __IOM uint32_t CF0D : 8; /*!< [7..0] Control Field 0compare data */ + __IOM uint32_t CF0CE : 8; /*!< [15..8] Control Field 0 compare bit enable */ + __IOM uint32_t BFLW : 16; /*!< [31..16] Break Field length setting */ + } XCR2_b; + }; + __IM uint32_t RESERVED3[2]; + + union + { + __IM uint32_t CSR; /*!< (@ 0x00000048) Common Status Register */ + + struct + { + uint32_t : 4; + __IM uint32_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + uint32_t : 10; + __IM uint32_t RXDMON : 1; /*!< [15..15] Serial input data monitor bit */ + __IM uint32_t DCMF : 1; /*!< [16..16] Data Compare Match Flag */ + __IM uint32_t DPER : 1; /*!< [17..17] Data Compare Match Parity Error Flag */ + __IM uint32_t DFER : 1; /*!< [18..18] Data Compare Match Framing Error Flag */ + uint32_t : 5; + __IM uint32_t ORER : 1; /*!< [24..24] Overrun Error Flag */ + uint32_t : 1; + __IM uint32_t MFF : 1; /*!< [26..26] Mode Fault Flag */ + __IM uint32_t PER : 1; /*!< [27..27] Parity Error Flag */ + __IM uint32_t FER : 1; /*!< [28..28] Framing Error Flag */ + __IM uint32_t TDRE : 1; /*!< [29..29] Transmit Data Empty Flag */ + __IM uint32_t TEND : 1; /*!< [30..30] Transmit End Flag */ + __IM uint32_t RDRF : 1; /*!< [31..31] Receive Data Full Flag */ + } CSR_b; + }; + + union + { + __IM uint32_t ISR; /*!< (@ 0x0000004C) Simple I2C Status Register */ + + struct + { + __IM uint32_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint32_t : 2; + __IM uint32_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag */ + uint32_t : 28; + } ISR_b; + }; + + union + { + __IM uint32_t FRSR; /*!< (@ 0x00000050) FIFO Receive Status Register */ + + struct + { + __IM uint32_t DR : 1; /*!< [0..0] Receive Data Ready flag */ + uint32_t : 7; + __IM uint32_t R : 6; /*!< [13..8] Receive-FIFO Data Count */ + uint32_t : 2; + __IM uint32_t PNUM : 6; /*!< [21..16] Parity Error Count */ + uint32_t : 2; + __IM uint32_t FNUM : 6; /*!< [29..24] Framing Error Count */ + uint32_t : 2; + } FRSR_b; + }; + + union + { + __IM uint32_t FTSR; /*!< (@ 0x00000054) FIFO Transmit Status Register */ + + struct + { + __IM uint32_t T : 6; /*!< [5..0] Transmit-FIFO Data Count */ + uint32_t : 26; + } FTSR_b; + }; + + union + { + __IM uint32_t MSR; /*!< (@ 0x00000058) Manchester Status Register */ + + struct + { + __IM uint32_t PFER : 1; /*!< [0..0] Preface Error flag */ + __IM uint32_t SYER : 1; /*!< [1..1] SYNC Error flag */ + __IM uint32_t SBER : 1; /*!< [2..2] Start Bit Error flag */ + uint32_t : 1; + __IM uint32_t MER : 1; /*!< [4..4] Manchester Error Flag */ + uint32_t : 1; + __IM uint32_t RSYNC : 1; /*!< [6..6] Receive SYNC data bit */ + uint32_t : 25; + } MSR_b; + }; + + union + { + __IM uint32_t XSR0; /*!< (@ 0x0000005C) Simple LIN (SCIX) Status Register 0 */ + + struct + { + __IM uint32_t SFSF : 1; /*!< [0..0] Start Frame Status flag */ + __IM uint32_t RXDSF : 1; /*!< [1..1] RXDn input status flag */ + uint32_t : 6; + __IM uint32_t BFOF : 1; /*!< [8..8] Break Field Output completion flag */ + __IM uint32_t BCDF : 1; /*!< [9..9] Bus Conflict detection flag */ + __IM uint32_t BFDF : 1; /*!< [10..10] Break Field detection flag */ + __IM uint32_t CF0MF : 1; /*!< [11..11] Control Field 0 compare match flag */ + __IM uint32_t CF1MF : 1; /*!< [12..12] Control Field 1 compare match flag */ + __IM uint32_t PIBDF : 1; /*!< [13..13] Priority interrupt bit detection flag */ + __IM uint32_t COF : 1; /*!< [14..14] Counter Overflow flag */ + __IM uint32_t AEDF : 1; /*!< [15..15] Active Edge detection flag */ + __IM uint32_t CF0RD : 8; /*!< [23..16] Control Field 0 received data */ + __IM uint32_t CF1RD : 8; /*!< [31..24] Control Field 1 received data */ + } XSR0_b; + }; + + union + { + __IM uint32_t XSR1; /*!< (@ 0x00000060) Simple LIN(SCIX) Status Register 1 */ + + struct + { + __IM uint32_t TCNT : 16; /*!< [15..0] Timer Count Capture value */ + uint32_t : 16; + } XSR1_b; + }; + __IM uint32_t RESERVED4; + + union + { + __OM uint32_t CFCLR; /*!< (@ 0x00000068) Common Flag Clear Register */ + + struct + { + uint32_t : 4; + __OM uint32_t ERSC : 1; /*!< [4..4] ERS clear bit */ + uint32_t : 11; + __OM uint32_t DCMFC : 1; /*!< [16..16] DCMF clear bit */ + __OM uint32_t DPERC : 1; /*!< [17..17] DPER clear bit */ + __OM uint32_t DFERC : 1; /*!< [18..18] DFER clear bit */ + uint32_t : 5; + __OM uint32_t ORERC : 1; /*!< [24..24] ORER clear bit */ + uint32_t : 1; + __OM uint32_t MFFC : 1; /*!< [26..26] MFF clear bit */ + __OM uint32_t PERC : 1; /*!< [27..27] PER clear bit */ + __OM uint32_t FERC : 1; /*!< [28..28] FER clear bit */ + __OM uint32_t TDREC : 1; /*!< [29..29] TDRE clear bit */ + uint32_t : 1; + __OM uint32_t RDRFC : 1; /*!< [31..31] RDRF clear bit */ + } CFCLR_b; + }; + + union + { + __OM uint32_t ICFCLR; /*!< (@ 0x0000006C) Simple I2C Flag Clear Register */ + + struct + { + uint32_t : 3; + __OM uint32_t IICSTIFC : 1; /*!< [3..3] IICSTIF clear bit */ + uint32_t : 28; + } ICFCLR_b; + }; + + union + { + __OM uint32_t FFCLR; /*!< (@ 0x00000070) FIFO Flag Clear Register */ + + struct + { + __OM uint32_t DRC : 1; /*!< [0..0] DR clear bit */ + uint32_t : 31; + } FFCLR_b; + }; + + union + { + __OM uint32_t MFCLR; /*!< (@ 0x00000074) Manchester Flag Clear Register */ + + struct + { + __OM uint32_t PFERC : 1; /*!< [0..0] PFER clear bit */ + __OM uint32_t SYERC : 1; /*!< [1..1] SYER clear bit */ + __OM uint32_t SBERC : 1; /*!< [2..2] SBER clear bit */ + uint32_t : 1; + __OM uint32_t MERC : 1; /*!< [4..4] MER clear bit */ + uint32_t : 27; + } MFCLR_b; + }; + + union + { + __OM uint32_t XFCLR; /*!< (@ 0x00000078) Simple LIN(SCIX) Flag Clear Register */ + + struct + { + uint32_t : 8; + __OM uint32_t BFOC : 1; /*!< [8..8] BFOF clear bit */ + __OM uint32_t BCDC : 1; /*!< [9..9] BCDF clear bit */ + __OM uint32_t BFDC : 1; /*!< [10..10] BFDF clear bit */ + __OM uint32_t CF0MC : 1; /*!< [11..11] CF0MF clear bit */ + __OM uint32_t CF1MC : 1; /*!< [12..12] CF1MF clear bit */ + __OM uint32_t PIBDC : 1; /*!< [13..13] PIBDF clear bit */ + __OM uint32_t COFC : 1; /*!< [14..14] COFF clear bit */ + __OM uint32_t AEDC : 1; /*!< [15..15] AEDF clear bit */ + uint32_t : 16; + } XFCLR_b; + }; +} R_SCI_B0_Type; /*!< Size = 124 (0x7c) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI_B0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface 0 (R_SPI_B0) + */ + +typedef struct /*!< (@ 0x4035C000) R_SPI_B0 Structure */ +{ + __IOM uint32_t SPDR; /*!< (@ 0x00000000) RSPI Data Register */ + + union + { + __IOM uint32_t SPDECR; /*!< (@ 0x00000004) RSPI Delay Control Register */ + + struct + { + __IOM uint32_t SCKDL : 3; /*!< [2..0] RSPCK Delay */ + uint32_t : 5; + __IOM uint32_t SLNDL : 3; /*!< [10..8] SSL Negation Delay */ + uint32_t : 5; + __IOM uint32_t SPNDL : 3; /*!< [18..16] RSPI Next-Access Delay */ + uint32_t : 5; + __IOM uint32_t ARST : 3; /*!< [26..24] Receive Sampling Timing Adjustment bits */ + uint32_t : 5; + } SPDECR_b; + }; + + union + { + __IOM uint32_t SPCR; /*!< (@ 0x00000008) RSPI Control Register */ + + struct + { + __IOM uint32_t SPE : 1; /*!< [0..0] RSPI Function Enable */ + uint32_t : 6; + __IOM uint32_t SPSCKSEL : 1; /*!< [7..7] RSPI Master Receive Clock Select */ + __IOM uint32_t SPPE : 1; /*!< [8..8] Parity Enable */ + __IOM uint32_t SPOE : 1; /*!< [9..9] Parity Mode */ + uint32_t : 1; + __IOM uint32_t PTE : 1; /*!< [11..11] Parity Self-Diagnosis Enable */ + __IOM uint32_t SCKASE : 1; /*!< [12..12] RSPCK Auto-Stop Function Enable */ + __IOM uint32_t BFDS : 1; /*!< [13..13] Between Burst Transfer Frames Delay Select */ + __IOM uint32_t MODFEN : 1; /*!< [14..14] Mode Fault Error Detection Enable */ + uint32_t : 1; + __IOM uint32_t SPEIE : 1; /*!< [16..16] RSPI Error Interrupt Enable */ + __IOM uint32_t SPRIE : 1; /*!< [17..17] RSPI Receive Buffer Full Interrupt Enable */ + __IOM uint32_t SPIIE : 1; /*!< [18..18] RSPI Idle Interrupt Enable */ + __IOM uint32_t SPDRES : 1; /*!< [19..19] RSPI receive data ready error select */ + __IOM uint32_t SPTIE : 1; /*!< [20..20] RSPI Transmit Buffer Empty Interrupt Enable */ + __IOM uint32_t CENDIE : 1; /*!< [21..21] RSPI Communication End Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SPMS : 1; /*!< [24..24] RSPI Mode Select */ + __IOM uint32_t SPFRF : 1; /*!< [25..25] RSPI Frame Format Select */ + uint32_t : 2; + __IOM uint32_t TXMD : 2; /*!< [29..28] Communication Mode Select */ + __IOM uint32_t MSTR : 1; /*!< [30..30] RSPI Master/Slave Mode Select */ + __IOM uint32_t BPEN : 1; /*!< [31..31] Synchronization Circuit Bypass Enable */ + } SPCR_b; + }; + + union + { + __IOM uint32_t SPCR2; /*!< (@ 0x0000000C) RSPI Control Register 2 */ + + struct + { + __IOM uint32_t RMFM : 5; /*!< [4..0] Frame processing count setting in Master Receive only */ + uint32_t : 1; + __OM uint32_t RMEDTG : 1; /*!< [6..6] End Trigger in Master Receive only */ + __OM uint32_t RMSTTG : 1; /*!< [7..7] Start Trigger in Master Receive only */ + __IOM uint32_t SPDRC : 8; /*!< [15..8] RSPI received data ready detect adjustment */ + __IOM uint32_t SPLP : 1; /*!< [16..16] RSPI Loopback */ + __IOM uint32_t SPLP2 : 1; /*!< [17..17] RSPI Loopback 2 */ + uint32_t : 2; + __IOM uint32_t MOIFV : 1; /*!< [20..20] MOSI Idle Fixed Value */ + __IOM uint32_t MOIFE : 1; /*!< [21..21] MOSI Idle Fixed Value Enable */ + uint32_t : 10; + } SPCR2_b; + }; + + union + { + __IOM uint32_t SPCR3; /*!< (@ 0x00000010) RSPI Control Register 3 */ + + struct + { + __IOM uint32_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity */ + __IOM uint32_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity */ + __IOM uint32_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity */ + __IOM uint32_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity */ + uint32_t : 4; + __IOM uint32_t SPBR : 8; /*!< [15..8] SPI Bit Rate */ + uint32_t : 8; + __IOM uint32_t SPSLN : 3; /*!< [26..24] RSPI Sequence Length */ + uint32_t : 5; + } SPCR3_b; + }; + + union + { + __IOM uint32_t SPCMD0; /*!< (@ 0x00000014) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD0_b; + }; + + union + { + __IOM uint32_t SPCMD1; /*!< (@ 0x00000018) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD1_b; + }; + + union + { + __IOM uint32_t SPCMD2; /*!< (@ 0x0000001C) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD2_b; + }; + + union + { + __IOM uint32_t SPCMD3; /*!< (@ 0x00000020) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD3_b; + }; + + union + { + __IOM uint32_t SPCMD4; /*!< (@ 0x00000024) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD4_b; + }; + + union + { + __IOM uint32_t SPCMD5; /*!< (@ 0x00000028) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD5_b; + }; + + union + { + __IOM uint32_t SPCMD6; /*!< (@ 0x0000002C) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD6_b; + }; + + union + { + __IOM uint32_t SPCMD7; /*!< (@ 0x00000030) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD7_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t SPDCR; /*!< (@ 0x00000040) RSPI Data Control Register */ + + struct + { + __IOM uint32_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + uint32_t : 2; + __IOM uint32_t SPRDTD : 1; /*!< [3..3] RSPI Receive Data or Transmit Data Select */ + __IOM uint32_t SINV : 1; /*!< [4..4] Serial data invert bit */ + uint32_t : 3; + __IOM uint32_t SPFC : 2; /*!< [9..8] Frame Count */ + uint32_t : 22; + } SPDCR_b; + }; + + union + { + __IOM uint32_t SPDCR2; /*!< (@ 0x00000044) RSPI Data Control Register 2 */ + + struct + { + __IOM uint32_t RTRG : 2; /*!< [1..0] Receive FIFO threshold setting */ + uint32_t : 6; + __IOM uint32_t TTRG : 2; /*!< [9..8] Transmission FIFO threshold setting */ + uint32_t : 22; + } SPDCR2_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IM uint32_t SPSR; /*!< (@ 0x00000050) SPI Status Register */ + + struct + { + uint32_t : 8; + __IM uint32_t SPCP : 3; /*!< [10..8] RSPI Command Pointer */ + uint32_t : 1; + __IM uint32_t SPECM : 3; /*!< [14..12] RSPI Error Command */ + uint32_t : 8; + __IM uint32_t SPDRF : 1; /*!< [23..23] RSPI Receive Data Ready Flag */ + __IM uint32_t OVRF : 1; /*!< [24..24] Overrun Error Flag */ + __IM uint32_t IDLNF : 1; /*!< [25..25] RSPI Idle Flag */ + __IM uint32_t MODF : 1; /*!< [26..26] Mode Fault Error Flag */ + __IM uint32_t PERF : 1; /*!< [27..27] Parity Error Flag */ + __IM uint32_t UDRF : 1; /*!< [28..28] Underrun Error Flag */ + __IM uint32_t SPTEF : 1; /*!< [29..29] RSPI Transmit Buffer Empty Flag */ + __IM uint32_t CENDF : 1; /*!< [30..30] Communication End Flag */ + __IM uint32_t SPRF : 1; /*!< [31..31] RSPI Receive Buffer Full Flag */ + } SPSR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IM uint32_t SPTFSR; /*!< (@ 0x00000058) RSPI Transfer FIFO Status Register */ + + struct + { + __IM uint32_t TFDN : 3; /*!< [2..0] Transmit FIFO data empty stage number */ + uint32_t : 29; + } SPTFSR_b; + }; + + union + { + __IM uint32_t SPRFSR; /*!< (@ 0x0000005C) RSPI Receive FIFO Status Register */ + + struct + { + __IM uint32_t RFDN : 3; /*!< [2..0] Receive FIFO data store stage number */ + uint32_t : 29; + } SPRFSR_b; + }; + + union + { + __IM uint32_t SPPSR; /*!< (@ 0x00000060) RSPI Poling Register */ + + struct + { + __IM uint32_t SPEPS : 1; /*!< [0..0] RSPI Poling Status */ + uint32_t : 31; + } SPPSR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t SPSRC; /*!< (@ 0x00000068) RSPI Status Clear Register */ + + struct + { + uint32_t : 23; + __OM uint32_t SPDRFC : 1; /*!< [23..23] RSPI Receive Data Ready Flag Clear */ + __OM uint32_t OVRFC : 1; /*!< [24..24] Overrun Error Flag Clear */ + uint32_t : 1; + __OM uint32_t MODFC : 1; /*!< [26..26] Mode Fault Error Flag Clear */ + __OM uint32_t PERFC : 1; /*!< [27..27] Parity Error Flag Clear */ + __OM uint32_t UDRFC : 1; /*!< [28..28] Underrun Error Flag Clear */ + __OM uint32_t SPTEFC : 1; /*!< [29..29] RSPI Transmit Buffer Empty Flag Clear */ + __OM uint32_t CENDFC : 1; /*!< [30..30] Communication End Flag Clear */ + __OM uint32_t SPRFC : 1; /*!< [31..31] RSPI Receive Buffer Full Flag Clear */ + } SPSRC_b; + }; + + union + { + __IOM uint32_t SPFCR; /*!< (@ 0x0000006C) RSPI FIFO Clear Register */ + + struct + { + __OM uint32_t SPFRST : 1; /*!< [0..0] RSPI FIFO clear */ + uint32_t : 31; + } SPFCR_b; + }; +} R_SPI_B0_Type; /*!< Size = 112 (0x70) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_HS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 High-Speed Module (R_USB_HS0) + */ + +typedef struct /*!< (@ 0x40351000) R_USB_HS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 3; + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + __IOM uint16_t HSE : 1; /*!< [7..7] High-Speed Operation Enable */ + __IOM uint16_t CNEN : 1; /*!< [8..8] Single End Receiver Enable */ + uint16_t : 7; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] ID0 Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB1_OVRCURA/USB1_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Operation Enable for the Host Controller Operation */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Signal Output for the Host Controller Operation */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output for the Host Controller Operation */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Remote Wakeup Detection Enable for the Host Controller + * Operation */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Remote Wakeup Output for the Device Controller Operation */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USBHS_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USBHS_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control Use this bit + * when switching from device B to device A in OTGmode. If + * the HNPBTOA bit is 1, the internal function controlremains + * in the Suspend state until the HNP processing endseven + * if SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port.Read receive data from the FIFO buffer or + * write transmit data to the FIFO buffer by accessing these + * bits. */ + } CFIFO_b; + }; + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port Read receive data from the FIFO buffer or + * write transmit data to the FIFO buffer by accessing these + * bits. */ + } D0FIFO_b; + }; + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO PortRead receive data from the FIFO buffer or write + * transmit data to the FIFO buffer by accessing these bits. */ + } D1FIFO_b; + }; + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] FIFO Port Access Direction when DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t LPMENDE : 1; /*!< [8..8] LPM Transaction End Interrupt Enable */ + __IOM uint16_t L1RSMENDE : 1; /*!< [9..9] L1 Resume End Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] OVRCRE Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPEBRDYE : 10; /*!< [9..0] BRDY Interrupt Enable for Each Pipe */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPENRDYE : 10; /*!< [9..0] NRDY Interrupt Enable for Each Pipe */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPEBEMPE : 10; /*!< [9..0] BEMP Interrupt Enable for Each Pipe */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Pin Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Interrupt Edge Processing Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] PIPEBRDY Interrupt Status Clear Timing.This bit can be + * set only in the initial setting (before communications).The + * setting cannot be changed once communication starts. */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select.The transfer efficiency + * can be improved by setting this bit to 1 if no low-speed + * device is connected directly or via FS-HUB to the USB port. */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] USB Connection Detection Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPEBRDY : 10; /*!< [9..0] BRDY Interrupt Status for Each Pipe */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPENRDY : 10; /*!< [9..0] NRDY Interrupt Status for Each Pipe */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPEBEMP : 10; /*!< [9..0] BEMP Interrupt Status for Each Pipe */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame Number.Indicate the latest frame number. */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] CRC Error Detection Status */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + + struct + { + __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } UFRMNUM_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ + uint16_t : 5; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] USB request bmRequestType value Finction controller selected + * : read-only Host controller selected : read-write */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] USB request bRequest value Finction controller selected + * : read-only Host controller selected : read-write */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] Value of USB request wValue Finction controller selected + * : read-only Host controller selected : read-write */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] Value of USB request wIndex Finction controller selected + * : read-only Host controller selected : read-write */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] Value of USB request wLength Finction controller selected + * : read-only Host controller selected : read-write */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Blocking on End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits specify the maximum data + * payload (maximum packet size) for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the + * destination function device for control transfer when the + * host controller function is selected. */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 1; + __IOM uint16_t PINGE : 1; /*!< [4..4] PING Token Issue Enable */ + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + __IM uint16_t CSSTS : 1; /*!< [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] Split Transaction CSPLIT Status Clear */ + __IOM uint16_t SUREQ : 1; /*!< [14..14] SETUP Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint Number */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + + union + { + __IOM uint16_t PIPEBUF; /*!< (@ 0x0000006A) Pipe Buffer Register */ + + struct + { + __IOM uint16_t BUFNMB : 8; /*!< [7..0] Buffer NumberThese bits specify the FIFO buffer number + * of the selected pipe (04h to 87h). */ + uint16_t : 2; + __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes */ + uint16_t : 1; + } PIPEBUF_b; + }; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 11; /*!< [10..0] Maximum Packet SizeThese bits specify the maximum data + * payload (maximum packet size) for the selected pipe.A size + * of 1h to 40h bytes can be set for PIPE6 to PIPE9. */ + uint16_t : 1; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the + * peripheral device when the host controller function is + * selected. */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalThese bits specify the + * transfer interval timing for the selected pipe as n-th + * power of 2 of the frame timing. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) PIPE Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PIDThese bits specify the response type for + * the next transaction of the relevant pipe. */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe BusyThis bit indicates whether the relevant pipe + * is being used for the USB bus */ + __IM uint16_t SQMON : 1; /*!< [6..6] Toggle Bit ConfirmationThis bit indicates the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit SetThis bit is set to 1 when the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe is set for DATA1 */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit ClearThis bit is set to 1 when the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe is cleared to DATA0 */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear ModeThis bit enables or disables auto + * buffer clear mode for the relevant pipe */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response ModeThis bit enables or disables auto + * response mode for the relevant pipe. */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer MonitorThis bit indicates the FIFO + * buffer status for the relevant pipe in the transmitting + * direction. */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer StatusThis bit indicates the FIFO buffer status + * for the relevant pipe. */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[3]; + __IOM R_USB_HS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED14[11]; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED15[7]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED16[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED17; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED18; + + union + { + __IOM uint16_t PHYTRIM1; /*!< (@ 0x00000150) PHY Timing Register 1 */ + + struct + { + __IOM uint16_t DRISE : 2; /*!< [1..0] FS/LS Rising-Edge Output Waveform Adjustment Function */ + __IOM uint16_t DFALL : 2; /*!< [3..2] FS/LS Falling-Edge Output Waveform Adjustment Function */ + uint16_t : 3; + __IOM uint16_t PCOMPENB : 1; /*!< [7..7] PVDD Start-up Detection */ + __IOM uint16_t HSIUP : 4; /*!< [11..8] HS Output Level Setting */ + __IOM uint16_t IMPOFFSET : 3; /*!< [14..12] terminating resistance offset value setting.Offset + * value for adjusting the terminating resistance. */ + uint16_t : 1; + } PHYTRIM1_b; + }; + + union + { + __IOM uint16_t PHYTRIM2; /*!< (@ 0x00000152) PHY Timing Register 2 */ + + struct + { + __IOM uint16_t SQU : 4; /*!< [3..0] Squelch Detection Level */ + uint16_t : 3; + __IOM uint16_t HSRXENMO : 1; /*!< [7..7] HS Receive Enable Control Mode */ + __IOM uint16_t PDR : 2; /*!< [9..8] HS Output Adjustment Function */ + uint16_t : 2; + __IOM uint16_t DIS : 3; /*!< [14..12] Disconnect Detection Level */ + uint16_t : 1; + } PHYTRIM2_b; + }; + __IM uint32_t RESERVED19[3]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; +} R_USB_HS0_Type; /*!< Size = 364 (0x16c) */ + +/* =========================================================================================================================== */ +/* ================ R_XSPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief eXpanded SPI (R_XSPI0) + */ + +typedef struct /*!< (@ 0x40268000) R_XSPI0 Structure */ +{ + union + { + __IOM uint32_t WRAPCFG; /*!< (@ 0x00000000) xSPI Wrapper Configuration register */ + + struct + { + __IOM uint32_t CKSFTCS0 : 5; /*!< [4..0] CK shift for slave0 */ + uint32_t : 3; + __IOM uint32_t DSSFTCS0 : 5; /*!< [12..8] DS shift for slave0 */ + uint32_t : 3; + __IOM uint32_t CKSFTCS1 : 5; /*!< [20..16] CK shift for slave1 */ + uint32_t : 3; + __IOM uint32_t DSSFTCS1 : 5; /*!< [28..24] DS shift for slave1 */ + uint32_t : 3; + } WRAPCFG_b; + }; + + union + { + __IOM uint32_t COMCFG; /*!< (@ 0x00000004) xSPI Common Configuration register */ + + struct + { + __IOM uint32_t ARBMD : 2; /*!< [1..0] Channel arbitration mode */ + uint32_t : 2; + __IOM uint32_t ECSINTOUTEN : 2; /*!< [5..4] ECS/INT Output Enable */ + uint32_t : 10; + __IOM uint32_t OEASTEX : 1; /*!< [16..16] Output Enable Asserting extension */ + __IOM uint32_t OENEGEX : 1; /*!< [17..17] Output Enable Negating extension */ + uint32_t : 14; + } COMCFG_b; + }; + + union + { + __IOM uint32_t BMCFGCH[2]; /*!< (@ 0x00000008) xSPI Bridge Map Configuration register */ + + struct + { + __IOM uint32_t WRMD : 1; /*!< [0..0] AHB Write Response mode */ + uint32_t : 6; + __IOM uint32_t MWRCOMB : 1; /*!< [7..7] Memory Write Combination mode */ + __IOM uint32_t MWRSIZE : 8; /*!< [15..8] Memory Write Size */ + __IOM uint32_t PREEN : 1; /*!< [16..16] Prefetch enable */ + uint32_t : 7; + __IOM uint32_t CMBTIM : 8; /*!< [31..24] Combination timer */ + } BMCFGCH_b[2]; + }; + __IOM R_XSPI0_CMCFGCS_Type CMCFGCS[2]; /*!< (@ 0x00000010) xSPI Command Map Configuration registers */ + __IM uint32_t RESERVED[8]; + + union + { + __IOM uint32_t LIOCFGCS[2]; /*!< (@ 0x00000050) xSPI Link I/O Configuration register CS[0..1] */ + + struct + { + __IOM uint32_t PRTMD : 10; /*!< [9..0] Protocol mode */ + __IOM uint32_t LATEMD : 1; /*!< [10..10] Latency mode */ + __IOM uint32_t WRMSKMD : 1; /*!< [11..11] Write mask mode */ + uint32_t : 4; + __IOM uint32_t CSMIN : 4; /*!< [19..16] CS minimum idle term */ + __IOM uint32_t CSASTEX : 1; /*!< [20..20] CS asserting extension */ + __IOM uint32_t CSNEGEX : 1; /*!< [21..21] CS negating extension */ + __IOM uint32_t SDRDRV : 1; /*!< [22..22] SDR driving timing */ + __IOM uint32_t SDRSMPMD : 1; /*!< [23..23] SDR Sampling mode */ + __IOM uint32_t SDRSMPSFT : 4; /*!< [27..24] SDR Sampling window shift */ + __IOM uint32_t DDRSMPEX : 4; /*!< [31..28] DDR sampling window extend */ + } LIOCFGCS_b[2]; + }; + + union + { + __IOM uint32_t ABMCFG; /*!< (@ 0x00000058) xSPI AXI Bridge Map Config */ + + struct + { + __IOM uint32_t ODRMD : 2; /*!< [1..0] AXI Transfer Ordering Mode */ + uint32_t : 14; + __IOM uint32_t CHSEL : 16; /*!< [31..16] AXI ID to Bridge Channel Select */ + } ABMCFG_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t BMCTL0; /*!< (@ 0x00000060) xSPI Bridge Map Control register 0 */ + + struct + { + __IOM uint32_t CH0CS0ACC : 2; /*!< [1..0] System bus ch0 to slave0 memory area access enable */ + __IOM uint32_t CH0CS1ACC : 2; /*!< [3..2] System bus ch0 to slave1 memory area access enable */ + __IOM uint32_t CH1CS0ACC : 2; /*!< [5..4] System bus ch1 to slave0 memory area access enable */ + __IOM uint32_t CH1CS1ACC : 2; /*!< [7..6] System bus ch1 to slave1 memory area access enable */ + uint32_t : 24; + } BMCTL0_b; + }; + + union + { + __OM uint32_t BMCTL1; /*!< (@ 0x00000064) xSPI Bridge Map Control register 1 */ + + struct + { + uint32_t : 8; + __OM uint32_t MWRPUSHCH0 : 1; /*!< [8..8] Memory Write Data Push for ch0 */ + __OM uint32_t MWRPUSHCH1 : 1; /*!< [9..9] Memory Write Data Push for ch1 */ + __OM uint32_t PBUFCLRCH0 : 1; /*!< [10..10] Prefetch Buffer clear for ch0 */ + __OM uint32_t PBUFCLRCH1 : 1; /*!< [11..11] Prefetch Buffer clear for ch1 */ + uint32_t : 20; + } BMCTL1_b; + }; + + union + { + __IOM uint32_t CMCTLCH[2]; /*!< (@ 0x00000068) xSPI Command Map Control register */ + + struct + { + __IOM uint32_t XIPENCODE : 8; /*!< [7..0] XiP mode enter code */ + __IOM uint32_t XIPEXCODE : 8; /*!< [15..8] XiP mode exit code */ + __IOM uint32_t XIPEN : 1; /*!< [16..16] XiP mode enable */ + uint32_t : 15; + } CMCTLCH_b[2]; + }; + + union + { + __IOM uint32_t CDCTL0; /*!< (@ 0x00000070) xSPI Command Manual Control register 0 */ + + struct + { + __IOM uint32_t TRREQ : 1; /*!< [0..0] Transaction request */ + __IOM uint32_t PERMD : 1; /*!< [1..1] Periodic mode */ + uint32_t : 1; + __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */ + __IOM uint32_t TRNUM : 2; /*!< [5..4] Transaction number */ + uint32_t : 10; + __IOM uint32_t PERITV : 5; /*!< [20..16] Periodic transaction interval */ + uint32_t : 3; + __IOM uint32_t PERREP : 4; /*!< [27..24] Periodic transaction repeat */ + uint32_t : 4; + } CDCTL0_b; + }; + + union + { + __IOM uint32_t CDCTL1; /*!< (@ 0x00000074) xSPI Command Manual Control register 1 */ + + struct + { + __IOM uint32_t PEREXP : 32; /*!< [31..0] Periodic transaction expected value */ + } CDCTL1_b; + }; + + union + { + __IOM uint32_t CDCTL2; /*!< (@ 0x00000078) xSPI Command Manual Control register 2 */ + + struct + { + __IOM uint32_t PERMSK : 32; /*!< [31..0] Periodic transaction masked value */ + } CDCTL2_b; + }; + __IM uint32_t RESERVED2; + __IOM R_XSPI0_CDBUF_Type CDBUF[4]; /*!< (@ 0x00000080) xSPI BUF register */ + __IM uint32_t RESERVED3[16]; + + union + { + __IOM uint32_t LPCTL0; /*!< (@ 0x00000100) xSPI Link Pattern Control register 0 */ + + struct + { + __IOM uint32_t PATREQ : 1; /*!< [0..0] Pattern request */ + uint32_t : 2; + __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */ + __IOM uint32_t XDPIN : 2; /*!< [5..4] XiP Disable pattern pin */ + uint32_t : 10; + __IOM uint32_t XD1LEN : 5; /*!< [20..16] XiP Disable pattern 1st phase length */ + uint32_t : 2; + __IOM uint32_t XD1VAL : 1; /*!< [23..23] XiP Disable pattern 1st phase value */ + __IOM uint32_t XD2LEN : 5; /*!< [28..24] XiP Disable pattern 2nd phase length */ + uint32_t : 2; + __IOM uint32_t XD2VAL : 1; /*!< [31..31] XiP Disable pattern 2nd phase value */ + } LPCTL0_b; + }; + + union + { + __IOM uint32_t LPCTL1; /*!< (@ 0x00000104) xSPI Link Pattern Control register 1 */ + + struct + { + __IOM uint32_t PATREQ : 2; /*!< [1..0] Pattern request */ + uint32_t : 1; + __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */ + __IOM uint32_t RSTREP : 2; /*!< [5..4] Reset pattern repeat */ + uint32_t : 2; + __IOM uint32_t RSTWID : 3; /*!< [10..8] Reset pattern width */ + uint32_t : 1; + __IOM uint32_t RSTSU : 3; /*!< [14..12] Reset pattern data output setup time */ + uint32_t : 17; + } LPCTL1_b; + }; + + union + { + __IOM uint32_t LIOCTL; /*!< (@ 0x00000108) xSPI Link I/O Control register */ + + struct + { + __IOM uint32_t WPCS0 : 1; /*!< [0..0] WP drive for slave 0 */ + __IOM uint32_t WPCS1 : 1; /*!< [1..1] WP drive for slave 1 */ + uint32_t : 14; + __IOM uint32_t RSTCS0 : 1; /*!< [16..16] Reset drive for slave 0 */ + __IOM uint32_t RSTCS1 : 1; /*!< [17..17] Reset drive for slave 1 */ + uint32_t : 14; + } LIOCTL_b; + }; + __IM uint32_t RESERVED4[9]; + __IOM R_XSPI0_CCCTLCS_Type CCCTLCS[2]; /*!< (@ 0x00000130) xSPI CS register */ + __IM uint32_t RESERVED5[4]; + + union + { + __IM uint32_t VERSTT; /*!< (@ 0x00000180) xSPI Version register */ + + struct + { + __IM uint32_t VER : 32; /*!< [31..0] Version */ + } VERSTT_b; + }; + + union + { + __IM uint32_t COMSTT; /*!< (@ 0x00000184) xSPI Common Status register */ + + struct + { + __IM uint32_t MEMACCCH0 : 1; /*!< [0..0] Memory access ongoing from ch0 */ + __IM uint32_t MEMACCCH1 : 1; /*!< [1..1] Memory access ongoing from ch1 */ + uint32_t : 2; + __IM uint32_t PBUFNECH0 : 1; /*!< [4..4] Prefetch Buffer Not Empty for ch0 */ + __IM uint32_t PBUFNECH1 : 1; /*!< [5..5] Prefetch Buffer Not Empty for ch1 */ + __IM uint32_t WRBUFNECH0 : 1; /*!< [6..6] Write Buffer Not Empty for ch0 */ + __IM uint32_t WRBUFNECH1 : 1; /*!< [7..7] Write Buffer Not Empty for ch1 */ + uint32_t : 8; + __IM uint32_t ECSCS0 : 1; /*!< [16..16] ECS monitor for slave0 */ + __IM uint32_t INTCS0 : 1; /*!< [17..17] INT monitor for slave0 */ + __IM uint32_t RSTOCS0 : 1; /*!< [18..18] RSTO monitor for slave0 */ + uint32_t : 1; + __IM uint32_t ECSCS1 : 1; /*!< [20..20] ECS monitor for slave1 */ + __IM uint32_t INTCS1 : 1; /*!< [21..21] INT monitor for slave1 */ + __IM uint32_t RSTOCS1 : 1; /*!< [22..22] RSTO monitor for slave1 */ + uint32_t : 9; + } COMSTT_b; + }; + + union + { + __IM uint32_t CASTTCS[2]; /*!< (@ 0x00000188) xSPI Calibration Status register */ + + struct + { + __IM uint32_t CASUC : 32; /*!< [31..0] Calibration Success */ + } CASTTCS_b[2]; + }; + + union + { + __IM uint32_t INTS; /*!< (@ 0x00000190) xSPI Interrupt Status register */ + + struct + { + __IM uint32_t CMDCMP : 1; /*!< [0..0] Command Completed */ + __IM uint32_t PATCMP : 1; /*!< [1..1] Pattern Completed */ + __IM uint32_t INICMP : 1; /*!< [2..2] Initial Sequence Completed */ + __IM uint32_t PERTO : 1; /*!< [3..3] Periodic transaction timeout */ + __IM uint32_t DSTOCS0 : 1; /*!< [4..4] DS timeout for slave0 */ + __IM uint32_t DSTOCS1 : 1; /*!< [5..5] DS timeout for slave1 */ + uint32_t : 2; + __IM uint32_t ECSCS0 : 1; /*!< [8..8] ECC error detection for slave0 */ + __IM uint32_t ECSCS1 : 1; /*!< [9..9] ECC error detection for slave1 */ + uint32_t : 2; + __IM uint32_t INTCS0 : 1; /*!< [12..12] Interrupt detection for slave0 */ + __IM uint32_t INTCS1 : 1; /*!< [13..13] Interrupt detection for slave1 */ + uint32_t : 2; + __IM uint32_t BRGOFCH0 : 1; /*!< [16..16] Bridge Buffer overflow for CH0 */ + __IM uint32_t BRGOFCH1 : 1; /*!< [17..17] Bridge Buffer overflow for CH1 */ + __IM uint32_t BRGUFCH0 : 1; /*!< [18..18] Bridge Buffer underflow for CH0 */ + __IM uint32_t BRGUFCH1 : 1; /*!< [19..19] Bridge Buffer underflow for CH1 */ + __IM uint32_t BUSERRCH0 : 1; /*!< [20..20] AHB bus error for CH0 */ + __IM uint32_t BUSERRCH1 : 1; /*!< [21..21] AHB bus error for CH1 */ + uint32_t : 6; + __IM uint32_t CAFAILCS0 : 1; /*!< [28..28] Calibration failed for slave0 */ + __IM uint32_t CAFAILCS1 : 1; /*!< [29..29] Calibration failed for slave1 */ + __IM uint32_t CASUCCS0 : 1; /*!< [30..30] Calibration success for slave0 */ + __IM uint32_t CASUCCS1 : 1; /*!< [31..31] Calibration success for slave1 */ + } INTS_b; + }; + + union + { + __OM uint32_t INTC; /*!< (@ 0x00000194) xSPI Interrupt Clear register */ + + struct + { + __OM uint32_t CMDCMPC : 1; /*!< [0..0] Command Completed interrupt clear */ + __OM uint32_t PATCMPC : 1; /*!< [1..1] Pattern Completed interrupt clear */ + __OM uint32_t INICMPC : 1; /*!< [2..2] Initial Sequence Completed interrupt clear */ + __OM uint32_t PERTOC : 1; /*!< [3..3] Periodic transaction timeout interrupt clear */ + __OM uint32_t DSTOCS0C : 1; /*!< [4..4] DS timeout for slave0 interrupt clear */ + __OM uint32_t DSTOCS1C : 1; /*!< [5..5] DS timeout for slave1 interrupt clear */ + uint32_t : 2; + __OM uint32_t ECSCS0C : 1; /*!< [8..8] ECC error detection for slave0 interrupt clear */ + __OM uint32_t ECSCS1C : 1; /*!< [9..9] ECC error detection for slave1 interrupt clear */ + uint32_t : 2; + __OM uint32_t INTCS0C : 1; /*!< [12..12] Interrupt detection for slave0 interrupt clear */ + __OM uint32_t INTCS1C : 1; /*!< [13..13] Interrupt detection for slave1 interrupt clear */ + uint32_t : 2; + __OM uint32_t BRGOFCH0C : 1; /*!< [16..16] Bridge Buffer overflow for CH0 interrupt clear */ + __OM uint32_t BRGOFCH1C : 1; /*!< [17..17] Bridge Buffer overflow for CH1 interrupt clear */ + __OM uint32_t BRGUFCH0C : 1; /*!< [18..18] Bridge Buffer underflow for CH0 interrupt clear */ + __OM uint32_t BRGUFCH1C : 1; /*!< [19..19] Bridge Buffer underflow for CH1 interrupt clear */ + __OM uint32_t BUSERRCH0C : 1; /*!< [20..20] AHB bus error for CH0 interrupt clear */ + __OM uint32_t BUSERRCH1C : 1; /*!< [21..21] AHB bus error for CH1 interrupt clear */ + uint32_t : 6; + __OM uint32_t CAFAILCS0C : 1; /*!< [28..28] Calibration failed for slave0 interrupt clear */ + __OM uint32_t CAFAILCS1C : 1; /*!< [29..29] Calibration failed for slave1 interrupt clear */ + __OM uint32_t CASUCCS0C : 1; /*!< [30..30] Calibration success for slave0 interrupt clear */ + __OM uint32_t CASUCCS1C : 1; /*!< [31..31] Calibration success for slave1 interrupt clear */ + } INTC_b; + }; + + union + { + __IOM uint32_t INTE; /*!< (@ 0x00000198) xSPI Interrupt Enable register */ + + struct + { + __IOM uint32_t CMDCMPE : 1; /*!< [0..0] Command Completed interrupt enable */ + __IOM uint32_t PATCMPE : 1; /*!< [1..1] Pattern Completed interrupt enable */ + __IOM uint32_t INICMPE : 1; /*!< [2..2] Initial Sequence Completed interrupt enable */ + __IOM uint32_t PERTOE : 1; /*!< [3..3] Periodic transaction timeout interrupt enable */ + __IOM uint32_t DSTOCS0E : 1; /*!< [4..4] DS timeout for slave0 interrupt enable */ + __IOM uint32_t DSTOCS1E : 1; /*!< [5..5] DS timeout for slave1 interrupt enable */ + uint32_t : 2; + __IOM uint32_t ECSCS0E : 1; /*!< [8..8] ECC error detection for slave0 interrupt enable */ + __IOM uint32_t ECSCS1E : 1; /*!< [9..9] ECC error detection for slave1 interrupt enable */ + uint32_t : 2; + __IOM uint32_t INTCS0E : 1; /*!< [12..12] Interrupt detection for slave0 interrupt enable */ + __IOM uint32_t INTCS1E : 1; /*!< [13..13] Interrupt detection for slave1 interrupt enable */ + uint32_t : 2; + __IOM uint32_t BRGOFCH0E : 1; /*!< [16..16] Bridge Buffer overflow for CH0 interrupt enable */ + __IOM uint32_t BRGOFCH1E : 1; /*!< [17..17] Bridge Buffer overflow for CH1 interrupt enable */ + __IOM uint32_t BRGUFCH0E : 1; /*!< [18..18] Bridge Buffer underflow for CH0 interrupt enable */ + __IOM uint32_t BRGUFCH1E : 1; /*!< [19..19] Bridge Buffer underflow for CH1 interrupt enable */ + __IOM uint32_t BUSERRCH0E : 1; /*!< [20..20] AHB bus error for CH0 interrupt enable */ + __IOM uint32_t BUSERRCH1E : 1; /*!< [21..21] AHB bus error for CH1 interrupt enable */ + uint32_t : 6; + __IOM uint32_t CAFAILCS0E : 1; /*!< [28..28] Calibration failed for slave0 interrupt enable */ + __IOM uint32_t CAFAILCS1E : 1; /*!< [29..29] Calibration failed for slave1 interrupt enable */ + __IOM uint32_t CASUCCS0E : 1; /*!< [30..30] Calibration success for slave0 interrupt enable */ + __IOM uint32_t CASUCCS1E : 1; /*!< [31..31] Calibration success for slave1 interrupt enable */ + } INTE_b; + }; +} R_XSPI0_Type; /*!< Size = 412 (0x19c) */ + +/* =========================================================================================================================== */ +/* ================ R_MIPI_PHY ================ */ +/* =========================================================================================================================== */ + +/** + * @brief D-PHY Controller Top (R_MIPI_PHY) + */ + +typedef struct /*!< (@ 0x40346C00) R_MIPI_PHY Structure */ +{ + union + { + __IOM uint32_t DPHYREFCR; /*!< (@ 0x00000000) D-PHY Reference Clock Setting Register */ + + struct + { + __IOM uint32_t RFREQ : 8; /*!< [7..0] Reference Clock Frequency Setting */ + uint32_t : 24; + } DPHYREFCR_b; + }; + + union + { + __IOM uint32_t DPHYPLFCR; /*!< (@ 0x00000004) D-PHY PLL Frequency Control Register */ + + struct + { + __IOM uint32_t IDIV : 2; /*!< [1..0] D-PHY PLL Input Frequency Division Ratio Select */ + uint32_t : 6; + __IOM uint32_t NFMUL : 2; /*!< [9..8] D-PHY PLL Frequency Multiplication Factor Select (Fractional + * Part) */ + uint32_t : 2; + __IOM uint32_t PMUL : 2; /*!< [13..12] D-PHY PLL Output Frequency Division Ratio Select */ + uint32_t : 2; + __IOM uint32_t NMUL : 9; /*!< [24..16] D-PHY PLL Frequency Multiplication Factor Select (Integer + * Part) */ + uint32_t : 7; + } DPHYPLFCR_b; + }; + + union + { + __IOM uint32_t DPHYPLOCR; /*!< (@ 0x00000008) D-PHY PLL Operation Control Register */ + + struct + { + __IOM uint32_t PLLSTP : 1; /*!< [0..0] D-PHY PLL Operation Control */ + uint32_t : 31; + } DPHYPLOCR_b; + }; + + union + { + __IOM uint32_t DPHYESCCR; /*!< (@ 0x0000000C) D-PHY Escape Mode Clock Control Register */ + + struct + { + __IOM uint32_t ESCDIV : 5; /*!< [4..0] Escape Mode Transfer Clock Division Ratio */ + uint32_t : 27; + } DPHYESCCR_b; + }; + + union + { + __IOM uint32_t DPHYPWRCR; /*!< (@ 0x00000010) D-PHY Power Supplying Control Register */ + + struct + { + __IOM uint32_t PWRSEN : 1; /*!< [0..0] D-PHY Power Supplying Control */ + uint32_t : 31; + } DPHYPWRCR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IM uint32_t DPHYSFR; /*!< (@ 0x0000001C) D-PHY Status Flag Register */ + + struct + { + __IM uint32_t PWRSF : 1; /*!< [0..0] D-PHY LDO Power-on Status Flag */ + uint32_t : 7; + __IM uint32_t PLLSF : 1; /*!< [8..8] D-PHY PLL Oscillation Stabilization Flag */ + uint32_t : 23; + } DPHYSFR_b; + }; + + union + { + __IOM uint32_t DPHYOCR; /*!< (@ 0x00000020) D-PHY Operation Control Register */ + + struct + { + __IOM uint32_t DPHYEN : 1; /*!< [0..0] D-PHY Operation Control */ + uint32_t : 31; + } DPHYOCR_b; + }; + + union + { + __IOM uint32_t DPHYTIM1; /*!< (@ 0x00000024) D-PHY Timing Control Register 1 */ + + struct + { + __IOM uint32_t TINIT : 19; /*!< [18..0] D-PHY T_INIT Parameter Setting */ + uint32_t : 13; + } DPHYTIM1_b; + }; + + union + { + __IOM uint32_t DPHYTIM2; /*!< (@ 0x00000028) D-PHY Timing Control Register 2 */ + + struct + { + __IOM uint32_t TCLKPREP : 8; /*!< [7..0] D-PHY T_CLK_PREPARE Parameter Setting */ + __IOM uint32_t TCLKSETT : 8; /*!< [15..8] D-PHY T_CLK_SETTLE Parameter Setting */ + __IOM uint32_t TCLKMISS : 8; /*!< [23..16] D-PHY T_CLK_MISS Parameter Setting */ + uint32_t : 8; + } DPHYTIM2_b; + }; + + union + { + __IOM uint32_t DPHYTIM3; /*!< (@ 0x0000002C) D-PHY Timing Control Register 3 */ + + struct + { + __IOM uint32_t THSPREP : 8; /*!< [7..0] D-PHY T_THS_PREPARE Parameter Setting */ + __IOM uint32_t THSSETT : 8; /*!< [15..8] D-PHY T_THS_SETTLE Parameter Setting */ + uint32_t : 16; + } DPHYTIM3_b; + }; + + union + { + __IOM uint32_t DPHYTIM4; /*!< (@ 0x00000030) D-PHY Timing Control Register 4 */ + + struct + { + __IOM uint32_t TCLKZERO : 8; /*!< [7..0] D-PHY T_CLK_ZERO Parameter Setting */ + __IOM uint32_t TCLKPRE : 8; /*!< [15..8] D-PHY T_TCLK_PRE Parameter Setting */ + __IOM uint32_t TCLKPOST : 8; /*!< [23..16] D-PHY T_TCLK_POST Parameter Setting */ + __IOM uint32_t TCLKTRL : 8; /*!< [31..24] D-PHY T_TCLK_TRAIL Parameter Setting */ + } DPHYTIM4_b; + }; + + union + { + __IOM uint32_t DPHYTIM5; /*!< (@ 0x00000034) D-PHY Timing Control Register 5 */ + + struct + { + __IOM uint32_t THSZERO : 8; /*!< [7..0] D-PHY T_THS_ZERO Parameter Setting */ + __IOM uint32_t THSTRL : 8; /*!< [15..8] D-PHY T_THS_TRAIL Parameter Setting */ + __IOM uint32_t THSEXIT : 8; /*!< [23..16] D-PHY T_THS_EXIT Parameter Setting */ + uint32_t : 8; + } DPHYTIM5_b; + }; + + union + { + __IOM uint32_t DPHYTIM6; /*!< (@ 0x00000038) D-PHY Timing Control Register 6 */ + + struct + { + __IOM uint32_t TLPX : 8; /*!< [7..0] D-PHY T_TLPX Parameter Setting */ + uint32_t : 24; + } DPHYTIM6_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t DPHYMDC; /*!< (@ 0x00000048) D-PHY Mode Control Register */ + + struct + { + __IOM uint32_t MASTEREN : 1; /*!< [0..0] D-PHY Master/Slave Select */ + uint32_t : 31; + } DPHYMDC_b; + }; +} R_MIPI_PHY_Type; /*!< Size = 76 (0x4c) */ + +/* =========================================================================================================================== */ +/* ================ R_MIPI_CSI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief MIPI_CSI Register area (R_MIPI_CSI) + */ + +typedef struct /*!< (@ 0x40347000) R_MIPI_CSI Structure */ +{ + union + { + __IM uint32_t MCG; /*!< (@ 0x00000000) Module Configuration Register */ + + struct + { + __IM uint32_t VER : 4; /*!< [3..0] VERsion of this ip */ + uint32_t : 4; + __IM uint32_t SDLN : 4; /*!< [11..8] Number of Supported Data Lanes */ + uint32_t : 4; + __IM uint32_t GSNM : 8; /*!< [23..16] NuMber of Generic Short packt FIFO */ + uint32_t : 8; + } MCG_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t MCT0; /*!< (@ 0x00000010) Module Control Register 0 */ + + struct + { + __IOM uint32_t VDLN : 4; /*!< [3..0] Numer of Valid Data Lanes */ + uint32_t : 12; + __IOM uint32_t ZLMD : 1; /*!< [16..16] Zero Length long packet output MoDe */ + __IOM uint32_t EDMD : 1; /*!< [17..17] ErrframeData notification MoDe */ + uint32_t : 1; + __IOM uint32_t RVMD : 1; /*!< [19..19] ReserVed packet reception MoDe */ + __IOM uint32_t GRMD : 1; /*!< [20..20] Generic csi-2 Rule MoDe */ + uint32_t : 3; + __IOM uint32_t ECCV13 : 1; /*!< [24..24] ECC check csi-2 Ver 1.3 mode */ + __IOM uint32_t LFSREN : 1; /*!< [25..25] LFSR Enable mode */ + uint32_t : 6; + } MCT0_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t MCT2; /*!< (@ 0x00000018) Module Control Register 2 */ + + struct + { + __IOM uint32_t FRRCLK : 9; /*!< [8..0] clock FRequency Rate to judge packet reception end */ + uint32_t : 7; + __IOM uint32_t FRRSKW : 9; /*!< [24..16] clock FRequency Rate to adjust data lane SKew */ + uint32_t : 7; + } MCT2_b; + }; + + union + { + __IOM uint32_t MCT3; /*!< (@ 0x0000001C) Module Control Register 3 */ + + struct + { + __IOM uint32_t RXEN : 1; /*!< [0..0] RX (reception) Enable */ + uint32_t : 31; + } MCT3_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __OM uint32_t RTCT; /*!< (@ 0x00000028) Reset Control Register */ + + struct + { + __OM uint32_t VSRST : 1; /*!< [0..0] Video pixel interface Software ReSeT */ + uint32_t : 31; + } RTCT_b; + }; + + union + { + __IM uint32_t RTST; /*!< (@ 0x0000002C) Reset Status Register */ + + struct + { + __IM uint32_t VSRSTS : 1; /*!< [0..0] Video pixel interface Software ReSeT Status */ + uint32_t : 31; + } RTST_b; + }; + __IM uint32_t RESERVED3[4]; + + union + { + __IOM uint32_t EPCT; /*!< (@ 0x00000040) EPD Option Control Register */ + + struct + { + __IOM uint32_t SLP : 15; /*!< [14..0] Long Packet Spacers */ + __IOM uint32_t EPDOP : 1; /*!< [15..15] EPD OPtion select */ + __IOM uint32_t SSP : 15; /*!< [30..16] epd Short Packet Spacers */ + __IOM uint32_t EPDEN : 1; /*!< [31..31] ENable EPD operation */ + } EPCT_b; + }; + + union + { + __IOM uint32_t EMCT; /*!< (@ 0x00000044) EPD Misc Option Control Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t VLSIEN : 2; /*!< [5..4] ENable Variable-Length Spacer Insertions */ + __IOM uint32_t EOTPEN : 1; /*!< [6..6] ENable EOTP */ + uint32_t : 25; + } EMCT_b; + }; + __IM uint32_t RESERVED4[2]; + + union + { + __IM uint32_t MIST; /*!< (@ 0x00000050) Module Interrupt Status Register */ + + struct + { + __IM uint32_t DL0S : 1; /*!< [0..0] interrupt Status related to Data Lane 0 */ + __IM uint32_t DL1S : 1; /*!< [1..1] interrupt Status related to Data Lane 1 */ + uint32_t : 6; + __IM uint32_t PMS : 1; /*!< [8..8] interrupt Status related to Power Management */ + __IM uint32_t GSTS : 1; /*!< [9..9] interrupt Status related to Generic ShorT packet */ + __IM uint32_t RXS : 1; /*!< [10..10] interrupt Status related to RX (Reception) */ + uint32_t : 5; + __IM uint32_t VC0S : 1; /*!< [16..16] interrupt Status related to Vitrtual Channel 0 */ + __IM uint32_t VC1S : 1; /*!< [17..17] interrupt Status related to Vitrtual Channel 1 */ + __IM uint32_t VC2S : 1; /*!< [18..18] interrupt Status related to Vitrtual Channel 2 */ + __IM uint32_t VC3S : 1; /*!< [19..19] interrupt Status related to Vitrtual Channel 3 */ + __IM uint32_t VC4S : 1; /*!< [20..20] interrupt Status related to Vitrtual Channel 4 */ + __IM uint32_t VC5S : 1; /*!< [21..21] interrupt Status related to Vitrtual Channel 5 */ + __IM uint32_t VC6S : 1; /*!< [22..22] interrupt Status related to Vitrtual Channel 6 */ + __IM uint32_t VC7S : 1; /*!< [23..23] interrupt Status related to Vitrtual Channel 7 */ + __IM uint32_t VC8S : 1; /*!< [24..24] interrupt Status related to Vitrtual Channel 8 */ + __IM uint32_t VC9S : 1; /*!< [25..25] interrupt Status related to Vitrtual Channel 9 */ + __IM uint32_t VC10S : 1; /*!< [26..26] interrupt Status related to Vitrtual Channel 10 */ + __IM uint32_t VC11S : 1; /*!< [27..27] interrupt Status related to Vitrtual Channel 11 */ + __IM uint32_t VC12S : 1; /*!< [28..28] interrupt Status related to Vitrtual Channel 12 */ + __IM uint32_t VC13S : 1; /*!< [29..29] interrupt Status related to Vitrtual Channel 13 */ + __IM uint32_t VC14S : 1; /*!< [30..30] interrupt Status related to Vitrtual Channel 14 */ + __IM uint32_t VC15S : 1; /*!< [31..31] interrupt Status related to Vitrtual Channel 15 */ + } MIST_b; + }; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint32_t DTEL; /*!< (@ 0x00000060) Receive Data Type Enable Low Register */ + + struct + { + __IOM uint32_t DTEN : 32; /*!< [31..0] Data Type ENable (DT = 0x00 to 0x1F) */ + } DTEL_b; + }; + + union + { + __IOM uint32_t DTEH; /*!< (@ 0x00000064) Receive Data Type Enable High Register */ + + struct + { + __IOM uint32_t DTEN : 32; /*!< [31..0] Data Type ENable (DT = 0x20 to 0x3F) */ + } DTEH_b; + }; + __IM uint32_t RESERVED6[2]; + + union + { + __IM uint32_t RXST; /*!< (@ 0x00000070) Receive Status Register */ + + struct + { + __IM uint32_t FRM0 : 1; /*!< [0..0] FRaMe of virtual channel 0 active */ + __IM uint32_t FRM1 : 1; /*!< [1..1] FRaMe of virtual channel 1 active */ + __IM uint32_t FRM2 : 1; /*!< [2..2] FRaMe of virtual channel 2 active */ + __IM uint32_t FRM3 : 1; /*!< [3..3] FRaMe of virtual channel 3 active */ + __IM uint32_t FRM4 : 1; /*!< [4..4] FRaMe of virtual channel 4 active */ + __IM uint32_t FRM5 : 1; /*!< [5..5] FRaMe of virtual channel 5 active */ + __IM uint32_t FRM6 : 1; /*!< [6..6] FRaMe of virtual channel 6 active */ + __IM uint32_t FRM7 : 1; /*!< [7..7] FRaMe of virtual channel 7 active */ + __IM uint32_t FRM8 : 1; /*!< [8..8] FRaMe of virtual channel 8 active */ + __IM uint32_t FRM9 : 1; /*!< [9..9] FRaMe of virtual channel 9 active */ + __IM uint32_t FRM10 : 1; /*!< [10..10] FRaMe of virtual channel 10 active */ + __IM uint32_t FRM11 : 1; /*!< [11..11] FRaMe of virtual channel 11 active */ + __IM uint32_t FRM12 : 1; /*!< [12..12] FRaMe of virtual channel 12 active */ + __IM uint32_t FRM13 : 1; /*!< [13..13] FRaMe of virtual channel 13 active */ + __IM uint32_t FRM14 : 1; /*!< [14..14] FRaMe of virtual channel 14 active */ + __IM uint32_t FRM15 : 1; /*!< [15..15] FRaMe of virtual channel 15 active */ + __IM uint32_t RACT : 1; /*!< [16..16] Rx (Reception) ACTive status */ + __IM uint32_t RACTDET : 1; /*!< [17..17] Rx (Reception) ACTive DETect */ + uint32_t : 14; + } RXST_b; + }; + + union + { + __OM uint32_t RXSC; /*!< (@ 0x00000074) Receive Status Clear Register */ + + struct + { + uint32_t : 17; + __OM uint32_t RACTDETC : 1; /*!< [17..17] Rx (Reception) ACTive DETect status Clear */ + uint32_t : 14; + } RXSC_b; + }; + + union + { + __IOM uint32_t RXIE; /*!< (@ 0x00000078) Receive Interrupt Enable Register */ + + struct + { + uint32_t : 17; + __IOM uint32_t RACTDETE : 1; /*!< [17..17] Rx (Reception) ACTive DETect interrupt Enable */ + uint32_t : 14; + } RXIE_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IM uint32_t DLST0; /*!< (@ 0x00000080) Data Lane (N) Status Register */ + + struct + { + __IM uint32_t ESH : 1; /*!< [0..0] ErrSotHs detect on data lane (N) status */ + __IM uint32_t ESS : 1; /*!< [1..1] ErrSotSynchs detect on data lane (N) status */ + __IM uint32_t ECT : 1; /*!< [2..2] ErrConTrol detect on data lane (N) status */ + __IM uint32_t EES : 1; /*!< [3..3] ErrESc detect on data lane (N) status */ + uint32_t : 12; + __IM uint32_t EUL : 1; /*!< [16..16] Exit from ULps detect on data lane (N) status */ + __IM uint32_t RUL : 1; /*!< [17..17] entry to ULps detect on data lane (N) status */ + uint32_t : 6; + __IM uint32_t ULP : 1; /*!< [24..24] rxULPsesc of data lane (N) status */ + uint32_t : 7; + } DLST0_b; + }; + + union + { + __OM uint32_t DLSC0; /*!< (@ 0x00000084) Data Lane (N) Status Clear Register */ + + struct + { + __OM uint32_t ESHC : 1; /*!< [0..0] ErrSotHs detect on data lane (N) status Clear */ + __OM uint32_t ESSC : 1; /*!< [1..1] ErrSotSynchs detect on data lane (N) status Clear */ + __OM uint32_t ECTC : 1; /*!< [2..2] ErrConTrol detect on data lane (N) status Clear */ + __OM uint32_t EESC : 1; /*!< [3..3] ErrESc detect on data lane (N) status Clear */ + uint32_t : 12; + __OM uint32_t EULC : 1; /*!< [16..16] Exit from ULps detect on data lane (N) status Clear */ + __OM uint32_t RULC : 1; /*!< [17..17] Entry to ULps detect on data lane (N) status Clear */ + uint32_t : 14; + } DLSC0_b; + }; + + union + { + __IOM uint32_t DLIE0; /*!< (@ 0x00000088) Data Lane (N) Interrupt Enable Register */ + + struct + { + __IOM uint32_t ESHE : 1; /*!< [0..0] ErrSotHs detect on data lane (N) interrupt Enable */ + __IOM uint32_t ESSE : 1; /*!< [1..1] ErrSotSynchs detect on data lane (N) interrupt Enable */ + __IOM uint32_t ECTE : 1; /*!< [2..2] ErrConTrol detect on data lane (N) interrupt Enable */ + __IOM uint32_t EESE : 1; /*!< [3..3] ErrESc detect on data lane (N) interrupt Enable */ + uint32_t : 12; + __IOM uint32_t EULE : 1; /*!< [16..16] Exit to ULps detect on data lane (N) interrupt Enable */ + __IOM uint32_t RULE : 1; /*!< [17..17] Entry to ULps detect on data lane (N) interrupt Enable */ + uint32_t : 14; + } DLIE0_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IM uint32_t DLST1; /*!< (@ 0x00000090) Data Lane (N) Status Register */ + + struct + { + __IM uint32_t ESH : 1; /*!< [0..0] ErrSotHs detect on data lane (N) status */ + __IM uint32_t ESS : 1; /*!< [1..1] ErrSotSynchs detect on data lane (N) status */ + __IM uint32_t ECT : 1; /*!< [2..2] ErrConTrol detect on data lane (N) status */ + __IM uint32_t EES : 1; /*!< [3..3] ErrESc detect on data lane (N) status */ + uint32_t : 12; + __IM uint32_t EUL : 1; /*!< [16..16] Exit from ULps detect on data lane (N) status */ + __IM uint32_t RUL : 1; /*!< [17..17] entry to ULps detect on data lane (N) status */ + uint32_t : 6; + __IM uint32_t ULP : 1; /*!< [24..24] rxULPsesc of data lane (N) status */ + uint32_t : 7; + } DLST1_b; + }; + + union + { + __OM uint32_t DLSC1; /*!< (@ 0x00000094) Data Lane (N) Status Clear Register */ + + struct + { + __OM uint32_t ESHC : 1; /*!< [0..0] ErrSotHs detect on data lane (N) status Clear */ + __OM uint32_t ESSC : 1; /*!< [1..1] ErrSotSynchs detect on data lane (N) status Clear */ + __OM uint32_t ECTC : 1; /*!< [2..2] ErrConTrol detect on data lane (N) status Clear */ + __OM uint32_t EESC : 1; /*!< [3..3] ErrESc detect on data lane (N) status Clear */ + uint32_t : 12; + __OM uint32_t EULC : 1; /*!< [16..16] Exit from ULps detect on data lane (N) status Clear */ + __OM uint32_t RULC : 1; /*!< [17..17] Entry to ULps detect on data lane (N) status Clear */ + uint32_t : 14; + } DLSC1_b; + }; + + union + { + __IOM uint32_t DLIE1; /*!< (@ 0x00000098) Data Lane (N) Interrupt Enable Register */ + + struct + { + __IOM uint32_t ESHE : 1; /*!< [0..0] ErrSotHs detect on data lane (N) interrupt Enable */ + __IOM uint32_t ESSE : 1; /*!< [1..1] ErrSotSynchs detect on data lane (N) interrupt Enable */ + __IOM uint32_t ECTE : 1; /*!< [2..2] ErrConTrol detect on data lane (N) interrupt Enable */ + __IOM uint32_t EESE : 1; /*!< [3..3] ErrESc detect on data lane (N) interrupt Enable */ + uint32_t : 12; + __IOM uint32_t EULE : 1; /*!< [16..16] Exit to ULps detect on data lane (N) interrupt Enable */ + __IOM uint32_t RULE : 1; /*!< [17..17] Entry to ULps detect on data lane (N) interrupt Enable */ + uint32_t : 14; + } DLIE1_b; + }; + __IM uint32_t RESERVED9[25]; + + union + { + __IM uint32_t VCST0; /*!< (@ 0x00000100) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST0_b; + }; + + union + { + __OM uint32_t VCSC0; /*!< (@ 0x00000104) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC0_b; + }; + + union + { + __IOM uint32_t VCIE0; /*!< (@ 0x00000108) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE0_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IM uint32_t VCST1; /*!< (@ 0x00000110) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST1_b; + }; + + union + { + __OM uint32_t VCSC1; /*!< (@ 0x00000114) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC1_b; + }; + + union + { + __IOM uint32_t VCIE1; /*!< (@ 0x00000118) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE1_b; + }; + __IM uint32_t RESERVED11; + + union + { + __IM uint32_t VCST2; /*!< (@ 0x00000120) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST2_b; + }; + + union + { + __OM uint32_t VCSC2; /*!< (@ 0x00000124) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC2_b; + }; + + union + { + __IOM uint32_t VCIE2; /*!< (@ 0x00000128) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE2_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IM uint32_t VCST3; /*!< (@ 0x00000130) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST3_b; + }; + + union + { + __OM uint32_t VCSC3; /*!< (@ 0x00000134) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC3_b; + }; + + union + { + __IOM uint32_t VCIE3; /*!< (@ 0x00000138) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE3_b; + }; + __IM uint32_t RESERVED13; + + union + { + __IM uint32_t VCST4; /*!< (@ 0x00000140) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST4_b; + }; + + union + { + __OM uint32_t VCSC4; /*!< (@ 0x00000144) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC4_b; + }; + + union + { + __IOM uint32_t VCIE4; /*!< (@ 0x00000148) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE4_b; + }; + __IM uint32_t RESERVED14; + + union + { + __IM uint32_t VCST5; /*!< (@ 0x00000150) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST5_b; + }; + + union + { + __OM uint32_t VCSC5; /*!< (@ 0x00000154) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC5_b; + }; + + union + { + __IOM uint32_t VCIE5; /*!< (@ 0x00000158) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE5_b; + }; + __IM uint32_t RESERVED15; + + union + { + __IM uint32_t VCST6; /*!< (@ 0x00000160) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST6_b; + }; + + union + { + __OM uint32_t VCSC6; /*!< (@ 0x00000164) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC6_b; + }; + + union + { + __IOM uint32_t VCIE6; /*!< (@ 0x00000168) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE6_b; + }; + __IM uint32_t RESERVED16; + + union + { + __IM uint32_t VCST7; /*!< (@ 0x00000170) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST7_b; + }; + + union + { + __OM uint32_t VCSC7; /*!< (@ 0x00000174) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC7_b; + }; + + union + { + __IOM uint32_t VCIE7; /*!< (@ 0x00000178) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE7_b; + }; + __IM uint32_t RESERVED17; + + union + { + __IM uint32_t VCST8; /*!< (@ 0x00000180) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST8_b; + }; + + union + { + __OM uint32_t VCSC8; /*!< (@ 0x00000184) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC8_b; + }; + + union + { + __IOM uint32_t VCIE8; /*!< (@ 0x00000188) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE8_b; + }; + __IM uint32_t RESERVED18; + + union + { + __IM uint32_t VCST9; /*!< (@ 0x00000190) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST9_b; + }; + + union + { + __OM uint32_t VCSC9; /*!< (@ 0x00000194) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC9_b; + }; + + union + { + __IOM uint32_t VCIE9; /*!< (@ 0x00000198) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE9_b; + }; + __IM uint32_t RESERVED19; + + union + { + __IM uint32_t VCST10; /*!< (@ 0x000001A0) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST10_b; + }; + + union + { + __OM uint32_t VCSC10; /*!< (@ 0x000001A4) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC10_b; + }; + + union + { + __IOM uint32_t VCIE10; /*!< (@ 0x000001A8) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE10_b; + }; + __IM uint32_t RESERVED20; + + union + { + __IM uint32_t VCST11; /*!< (@ 0x000001B0) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST11_b; + }; + + union + { + __OM uint32_t VCSC11; /*!< (@ 0x000001B4) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC11_b; + }; + + union + { + __IOM uint32_t VCIE11; /*!< (@ 0x000001B8) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE11_b; + }; + __IM uint32_t RESERVED21; + + union + { + __IM uint32_t VCST12; /*!< (@ 0x000001C0) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST12_b; + }; + + union + { + __OM uint32_t VCSC12; /*!< (@ 0x000001C4) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC12_b; + }; + + union + { + __IOM uint32_t VCIE12; /*!< (@ 0x000001C8) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE12_b; + }; + __IM uint32_t RESERVED22; + + union + { + __IM uint32_t VCST13; /*!< (@ 0x000001D0) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST13_b; + }; + + union + { + __OM uint32_t VCSC13; /*!< (@ 0x000001D4) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC13_b; + }; + + union + { + __IOM uint32_t VCIE13; /*!< (@ 0x000001D8) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE13_b; + }; + __IM uint32_t RESERVED23; + + union + { + __IM uint32_t VCST14; /*!< (@ 0x000001E0) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST14_b; + }; + + union + { + __OM uint32_t VCSC14; /*!< (@ 0x000001E4) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC14_b; + }; + + union + { + __IOM uint32_t VCIE14; /*!< (@ 0x000001E8) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE14_b; + }; + __IM uint32_t RESERVED24; + + union + { + __IM uint32_t VCST15; /*!< (@ 0x000001F0) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST15_b; + }; + + union + { + __OM uint32_t VCSC15; /*!< (@ 0x000001F4) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC15_b; + }; + + union + { + __IOM uint32_t VCIE15; /*!< (@ 0x000001F8) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE15_b; + }; + __IM uint32_t RESERVED25; + + union + { + __IM uint32_t PMST; /*!< (@ 0x00000200) Power Management Status Register */ + + struct + { + __IM uint32_t DSX : 1; /*!< [0..0] eXit from Stop state detect on all valid Data lanes status */ + __IM uint32_t DSN : 1; /*!< [1..1] eNtry to Stop state detect on all valid Data lanes status */ + __IM uint32_t CSX : 1; /*!< [2..2] eXit from Stop state detect on Clock lane status */ + __IM uint32_t CSN : 1; /*!< [3..3] eNtry to Stop state detect on Clock lane status */ + __IM uint32_t DUX : 1; /*!< [4..4] eXit from Ulps detect on all valid Data lanes status */ + __IM uint32_t DUN : 1; /*!< [5..5] eNtry to Ulps detect on all valid Data lanes status */ + __IM uint32_t CUX : 1; /*!< [6..6] eXit frum Ulps detect on Clock lane status */ + __IM uint32_t CUN : 1; /*!< [7..7] eNtry to Ulps detect on Clock lane status */ + uint32_t : 6; + __IM uint32_t CLSS : 1; /*!< [14..14] Stop State of Clock Lane status */ + __IM uint32_t CLUL : 1; /*!< [15..15] rxULpsclknot (inverted) of Clock Lane status */ + __IM uint32_t DLSS : 2; /*!< [17..16] Stop State of Data Lanes status */ + uint32_t : 6; + __IM uint32_t DLUL : 2; /*!< [25..24] rxULpsesc of Data Lanes status */ + uint32_t : 6; + } PMST_b; + }; + + union + { + __OM uint32_t PMSC; /*!< (@ 0x00000204) Power Management Status Clear Register */ + + struct + { + __OM uint32_t DSXC : 1; /*!< [0..0] eXit from Stop state detect on all valid Data lanes status + * Clear */ + __OM uint32_t DSNC : 1; /*!< [1..1] eNtry to Stop state detect on all valid Data lanes status + * Clear */ + __OM uint32_t CSXC : 1; /*!< [2..2] eXit from Stop state detect on Clock lane status Clear */ + __OM uint32_t CSNC : 1; /*!< [3..3] eNtry to Stop state detect on Clock lane status Clear */ + __OM uint32_t DUXC : 1; /*!< [4..4] eXit from Ulps detect on all valid Data lanes status + * Clear */ + __OM uint32_t DUNC : 1; /*!< [5..5] eNtry to Ulps detect on all valid Data lanes status Clear */ + __OM uint32_t CUXC : 1; /*!< [6..6] eXit frum Ulps detect on Clock lane status Clear */ + __OM uint32_t CUNC : 1; /*!< [7..7] eNtry to Ulps detect on Clock lane status Clear */ + uint32_t : 24; + } PMSC_b; + }; + + union + { + __IOM uint32_t PMIE; /*!< (@ 0x00000208) Power Management Interrupt Enable Register */ + + struct + { + __IOM uint32_t DSXE : 1; /*!< [0..0] eXit from Stop state detect on all valid Data lanes interrupt + * Enable */ + __IOM uint32_t DSNE : 1; /*!< [1..1] eNtry to Stop state detect on all valid Data lanes interrupt + * Enable */ + __IOM uint32_t CSXE : 1; /*!< [2..2] eXit from Stop state detect on Clock lane interrupt Enable */ + __IOM uint32_t CSNE : 1; /*!< [3..3] eNtry to Stop state detect on Clock lane interrupt Enable */ + __IOM uint32_t DUXE : 1; /*!< [4..4] eXit from Ulps detect on all valid Data lanes interrupt + * Enable */ + __IOM uint32_t DUNE : 1; /*!< [5..5] eNtry to Ulps detect on all valid Data lanes interrupt + * Enable */ + __IOM uint32_t CUXE : 1; /*!< [6..6] eXit from Ulps detect on Clock lane interrupt Enable */ + __IOM uint32_t CUNE : 1; /*!< [7..7] eNtry to Ulps detect on Clock lane interrupt Enable */ + uint32_t : 24; + } PMIE_b; + }; + __IM uint32_t RESERVED26[29]; + + union + { + __IOM uint32_t GSCT; /*!< (@ 0x00000280) Generic Short Packet Control Register */ + + struct + { + __IOM uint32_t SHTH : 7; /*!< [6..0] Stored generic short packet THreshold */ + uint32_t : 9; + __IOM uint32_t GFIF : 1; /*!< [16..16] Generic short packet store in FIFo */ + uint32_t : 15; + } GSCT_b; + }; + + union + { + __IM uint32_t GSST; /*!< (@ 0x00000284) Generic Short Packet Status Register */ + + struct + { + __IM uint32_t GNE : 1; /*!< [0..0] Generic short packet fifo Not Empty */ + __IM uint32_t GTH : 1; /*!< [1..1] more than THreshold Generic short packets existed in + * fifo */ + uint32_t : 2; + __IM uint32_t GOV : 1; /*!< [4..4] Generic short packet fifo OVerflow status */ + uint32_t : 3; + __IM uint32_t PNUM : 8; /*!< [15..8] NUMber of stored generic short Packets in fifo */ + __IM uint32_t GCD : 1; /*!< [16..16] Generic short packet fifo Clear status */ + __IM uint32_t STRDS : 1; /*!< [17..17] generic short packet SToRe DiSable */ + uint32_t : 14; + } GSST_b; + }; + + union + { + __OM uint32_t GSSC; /*!< (@ 0x00000288) Generic Short Packet Status Clear Register */ + + struct + { + uint32_t : 4; + __OM uint32_t GOVC : 1; /*!< [4..4] Generic short packet fifo OVerflow status Clear */ + uint32_t : 27; + } GSSC_b; + }; + + union + { + __IOM uint32_t GSIE; /*!< (@ 0x0000028C) Generic Short Packet Interrupt Enable Register */ + + struct + { + __IOM uint32_t GNEE : 1; /*!< [0..0] Generic short packet fifo Not Empty interrupt Enable */ + __IOM uint32_t GTHE : 1; /*!< [1..1] more than THreshold Generic short packets existed in + * fifo interrupt Enable */ + uint32_t : 2; + __IOM uint32_t GOVE : 1; /*!< [4..4] Generic short packet fifo OVerflow interrupt Enable */ + uint32_t : 27; + } GSIE_b; + }; + + union + { + __IM uint32_t GSHT; /*!< (@ 0x00000290) Generic Short Packet Register */ + + struct + { + __IM uint32_t SPDT : 16; /*!< [15..0] Stored Packet DaTa */ + __IM uint32_t DTYP : 6; /*!< [21..16] Stored packet Data TYPe */ + uint32_t : 2; + __IM uint32_t SPVC : 4; /*!< [27..24] Stored Packet Virtual Channel */ + uint32_t : 4; + } GSHT_b; + }; + + union + { + __IOM uint32_t GSIU; /*!< (@ 0x00000294) Generic Short Packet Information Update Register */ + + struct + { + __OM uint32_t FINC : 1; /*!< [0..0] generic short packet Fifo update (INCrement internal + * pointer) */ + uint32_t : 7; + __IOM uint32_t GFCLR : 1; /*!< [8..8] Generic short packet Fifo CLeaR */ + uint32_t : 7; + __OM uint32_t GFEN : 1; /*!< [16..16] Generic short packet Fifo ENable */ + uint32_t : 15; + } GSIU_b; + }; +} R_MIPI_CSI_Type; /*!< Size = 664 (0x298) */ + +/* =========================================================================================================================== */ +/* ================ R_CEU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Capture Engine Unit (R_CEU) + */ + +typedef struct /*!< (@ 0x40348000) R_CEU Structure */ +{ + union + { + __IOM uint32_t CAPSR; /*!< (@ 0x00000000) Capture Start Register */ + + struct + { + __IOM uint32_t CE : 1; /*!< [0..0] Capture enable */ + uint32_t : 15; + __IOM uint32_t CPKIL : 1; /*!< [16..16] Write 1 to this bit to perform a software reset of + * capturing. */ + uint32_t : 15; + } CAPSR_b; + }; + + union + { + __IOM uint32_t CAPCR; /*!< (@ 0x00000004) Capture Control Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t CTNCP : 1; /*!< [16..16] When capturing is started with this bit set to 1, capturing + * continues until the CE bit in CAPSR is cleared to 0 or + * a software reset is initiated by the CPKIL bit in CAPSR + * (see ). Continuous capture must be set before capturing + * is started. */ + uint32_t : 3; + __IOM uint32_t MTCM : 2; /*!< [21..20] Specify the unit for transferring data to a bus bridge + * module. */ + uint32_t : 2; + __IOM uint32_t FDRP : 8; /*!< [31..24] Set the frame drop interval in continuous-frame capture. */ + } CAPCR_b; + }; + + union + { + __IOM uint32_t CAMCR; /*!< (@ 0x00000008) Capture interface control register */ + + struct + { + __IOM uint32_t HDPOL : 1; /*!< [0..0] Sets the polarity for detection of the horizontal sync + * signal input from an external module. */ + __IOM uint32_t VDPOL : 1; /*!< [1..1] Sets the polarity for detection of the vertical sync + * signal input from an external module. */ + uint32_t : 2; + __IOM uint32_t JPG : 2; /*!< [5..4] These bits select the fetched data type. */ + uint32_t : 2; + __IOM uint32_t DTARY : 2; /*!< [9..8] Set the input order of the luminance component and chrominance + * component. */ + uint32_t : 2; + __IOM uint32_t DTIF : 1; /*!< [12..12] Sets the digital image input pins from which data is + * to be captured. */ + uint32_t : 3; + __IOM uint32_t FLDPOL : 1; /*!< [16..16] Sets the polarity of the field identification signal + * (FLD) from an external module. */ + uint32_t : 7; + __IOM uint32_t DSEL : 1; /*!< [24..24] Sets the edge for fetching the image data (D7 to D0) + * from an external module. */ + __IOM uint32_t FLDSEL : 1; /*!< [25..25] Sets the edge for capturing the field identification + * signal (FLD) from an external module. */ + __IOM uint32_t HDSEL : 1; /*!< [26..26] Sets the edge for capturing the horizontal sync signal + * (HD) from an external module. */ + __IOM uint32_t VDSEL : 1; /*!< [27..27] Sets the edge for capturing the vertical sync signal + * (VD) from an external module. */ + uint32_t : 4; + } CAMCR_b; + }; + + union + { + __IOM uint32_t CMCYR; /*!< (@ 0x0000000C) Capture Interface Cycle Register */ + + struct + { + __IOM uint32_t HCYL : 14; /*!< [13..0] Horizontal Cycle Count of External Module */ + uint32_t : 2; + __IOM uint32_t VCYL : 14; /*!< [29..16] Vertical HD Count of External Module */ + uint32_t : 2; + } CMCYR_b; + }; + + union + { + __IOM uint32_t CAMOR; /*!< (@ 0x00000010) Capture Interface Offset Register */ + + struct + { + __IOM uint32_t HOFST : 13; /*!< [12..0] Specify the capture start location in terms of the number + * of clock cycles from a horizontal sync signal (1-cycle + * units). */ + uint32_t : 3; + __IOM uint32_t VOFST : 12; /*!< [27..16] Specify the capture start location in terms of the + * HD count from a vertical sync signal (1-HD units). */ + uint32_t : 4; + } CAMOR_b; + }; + + union + { + __IOM uint32_t CAPWR; /*!< (@ 0x00000014) Capture Interface Width Register */ + + struct + { + __IOM uint32_t HWDTH : 13; /*!< [12..0] Specify the horizontal capture period. */ + uint32_t : 3; + __IOM uint32_t VWDTH : 12; /*!< [27..16] Specify the vertical capture period (4-HD units). */ + uint32_t : 4; + } CAPWR_b; + }; + + union + { + __IOM uint32_t CAIFR; /*!< (@ 0x00000018) Capture Interface Input Format Register */ + + struct + { + __IOM uint32_t FCI : 2; /*!< [1..0] Set the timing to start capturing. */ + uint32_t : 2; + __IOM uint32_t CIM : 1; /*!< [4..4] Sets the images to be captured. */ + uint32_t : 3; + __IOM uint32_t IFS : 1; /*!< [8..8] Sets the input mode for capturing images. */ + uint32_t : 23; + } CAIFR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t CRCNTR; /*!< (@ 0x00000028) CEU Register Control Register */ + + struct + { + __IOM uint32_t RC : 1; /*!< [0..0] Specifies switching of the register plane used by the + * CEU in synchronization with VD. */ + __IOM uint32_t RS : 1; /*!< [1..1] Specifies which register plane is used by the CEU in + * synchronization with VD. */ + uint32_t : 2; + __IOM uint32_t RVS : 1; /*!< [4..4] Sets the timing to switch the register plane in both-field + * capture. */ + uint32_t : 27; + } CRCNTR_b; + }; + + union + { + __IOM uint32_t CRCMPR; /*!< (@ 0x0000002C) CEU Register Forcible Control Register */ + + struct + { + __IOM uint32_t RA : 1; /*!< [0..0] Indicates the register plane currently specified. */ + uint32_t : 31; + } CRCMPR_b; + }; + + union + { + __IOM uint32_t CFLCR; /*!< (@ 0x00000030) Capture Filter Control Register */ + + struct + { + __IOM uint32_t HFRAC : 12; /*!< [11..0] Fraction Part of Horizontal Scale-Down Factor */ + __IOM uint32_t HMANT : 4; /*!< [15..12] Mantissa Part of Horizontal Scale-Down Factor */ + __IOM uint32_t VFRAC : 12; /*!< [27..16] Fraction Part of Vertical Scale-Down Factor */ + __IOM uint32_t VMANT : 4; /*!< [31..28] Mantissa Part of Vertical Scale-Down Factor */ + } CFLCR_b; + }; + + union + { + __IOM uint32_t CFSZR; /*!< (@ 0x00000034) Capture Filter Size Clip Register */ + + struct + { + __IOM uint32_t HFCLP : 12; /*!< [11..0] Specify the horizontal clipping value of the filter + * output size (4-pixel units). */ + uint32_t : 4; + __IOM uint32_t VFCLP : 12; /*!< [27..16] Set the vertical clipping value of the filter output + * size (4-pixel units). */ + uint32_t : 4; + } CFSZR_b; + }; + + union + { + __IOM uint32_t CDWDR; /*!< (@ 0x00000038) Capture Destination Width Register */ + + struct + { + __IOM uint32_t CHDW : 13; /*!< [12..0] Specify the horizontal image size in the memory area + * where the captured image is to be stored (4-byte units). */ + uint32_t : 19; + } CDWDR_b; + }; + + union + { + __IOM uint32_t CDAYR; /*!< (@ 0x0000003C) Capture Data Address Y Register */ + + struct + { + __IOM uint32_t CAYR : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR_b; + }; + + union + { + __IOM uint32_t CDACR; /*!< (@ 0x00000040) Capture Data Address C Register */ + + struct + { + __IOM uint32_t CACR : 32; /*!< [31..0] Capture Data Address C */ + } CDACR_b; + }; + + union + { + __IOM uint32_t CDBYR; /*!< (@ 0x00000044) Capture Data Bottom-Field Address Y Register */ + + struct + { + __IOM uint32_t CBYR : 32; /*!< [31..0] Set the address for storing the Y (luminance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBYR_b; + }; + + union + { + __IOM uint32_t CDBCR; /*!< (@ 0x00000048) Capture Data Bottom-Field Address C Register */ + + struct + { + __IOM uint32_t CBCR : 32; /*!< [31..0] Set the address for storing the C (chrominance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBCR_b; + }; + + union + { + __IOM uint32_t CBDSR; /*!< (@ 0x0000004C) Capture Bundle Destination Size Register */ + + struct + { + __IOM uint32_t CBVS : 23; /*!< [22..0] Select the number of lines or number of bytes for output + * to the memory in a bundle write. */ + uint32_t : 9; + } CBDSR_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t CFWCR; /*!< (@ 0x0000005C) Firewall Operation Control Register */ + + struct + { + __IOM uint32_t FWE : 1; /*!< [0..0] With the setting of FWE = 1, when an address exceeds + * the value set with FWV, the address is retained and an + * interrupt source FWF is set. After this, the address is + * not incremented and data is overwritten on the upper limit + * address. */ + uint32_t : 4; + __IOM uint32_t FWV : 27; /*!< [31..5] Specify the upper limit of a write address. */ + } CFWCR_b; + }; + + union + { + __IOM uint32_t CLFCR; /*!< (@ 0x00000060) Capture Low-Pass Filter Control Register */ + + struct + { + __IOM uint32_t LPF : 1; /*!< [0..0] Enables or disables operation of the low-pass filter. */ + uint32_t : 31; + } CLFCR_b; + }; + + union + { + __IOM uint32_t CDOCR; /*!< (@ 0x00000064) Capture Data Output Control Register */ + + struct + { + __IOM uint32_t COBS : 1; /*!< [0..0] Controls swapping in 8-bit units for data output from + * the CEU. */ + __IOM uint32_t COWS : 1; /*!< [1..1] Controls swapping in 16-bit units for data output from + * the CEU. */ + __IOM uint32_t COLS : 1; /*!< [2..2] Controls swapping in 32-bit units for data output from + * the CEU. */ + uint32_t : 1; + __IOM uint32_t CDS : 1; /*!< [4..4] Sets the image format when outputting the image data + * captured in the YCbCr422 format to the memory. */ + uint32_t : 11; + __IOM uint32_t CBE : 1; /*!< [16..16] Controls the number of lines of captured data to be + * written to the memory. */ + uint32_t : 15; + } CDOCR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t CEIER; /*!< (@ 0x00000070) Capture Event Interrupt Enable Register */ + + struct + { + __IOM uint32_t CPEIE : 1; /*!< [0..0] One-Frame Capture End Interrupt Enable */ + __IOM uint32_t CFEIE : 1; /*!< [1..1] CFE Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t IGRWIE : 1; /*!< [4..4] Register-Access-During-Capture Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t HDIE : 1; /*!< [8..8] HD Interrupt Enable */ + __IOM uint32_t VDIE : 1; /*!< [9..9] VD Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t CPBE1IE : 1; /*!< [12..12] CPBE1 Interrupt Enable */ + __IOM uint32_t CPBE2IE : 1; /*!< [13..13] CPBE2 Interrupt Enable */ + __IOM uint32_t CPBE3IE : 1; /*!< [14..14] CPBE3 Interrupt Enable */ + __IOM uint32_t CPBE4IE : 1; /*!< [15..15] CPBE4 Interrupt Enable */ + __IOM uint32_t CDTOFIE : 1; /*!< [16..16] CDTOF Interrupt Enable */ + __IOM uint32_t IGHSIE : 1; /*!< [17..17] IGHS Interrupt Enable */ + __IOM uint32_t IGVSIE : 1; /*!< [18..18] IGVS Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t VBPIE : 1; /*!< [20..20] VBP Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t FWFIE : 1; /*!< [23..23] FWF Interrupt Enable */ + __IOM uint32_t NHDIE : 1; /*!< [24..24] Non-HD Interrupt Enable */ + __IOM uint32_t NVDIE : 1; /*!< [25..25] Non-VD Interrupt Enable */ + uint32_t : 6; + } CEIER_b; + }; + + union + { + __IOM uint32_t CETCR; /*!< (@ 0x00000074) Capture Event Flag Clear Register */ + + struct + { + __IOM uint32_t CPE : 1; /*!< [0..0] An interrupt indicating that capturing of one frame from + * an external module has finished. */ + __IOM uint32_t CFE : 1; /*!< [1..1] An interrupt indicating that capturing of one field from + * an external module has finished. */ + uint32_t : 2; + __IOM uint32_t IGRW : 1; /*!< [4..4] An interrupt indicating that during capturing, access + * was attempted to a register to which writing during operation + * is prohibited. */ + uint32_t : 3; + __IOM uint32_t HD : 1; /*!< [8..8] An interrupt indicating that HD (horizontal sync signal) + * was input from an external module. */ + __IOM uint32_t VD : 1; /*!< [9..9] An interrupt indicating that VD (vertical sync signal) + * was input from an external module. */ + uint32_t : 2; + __IOM uint32_t CPBE1 : 1; /*!< [12..12] An interrupt indicating that writing to CDAYR and CDACR + * in a bundle write has finished. */ + __IOM uint32_t CPBE2 : 1; /*!< [13..13] An interrupt indicating that writing to CDAYR2 and + * CDACR2 in a bundle write has finished. */ + __IOM uint32_t CPBE3 : 1; /*!< [14..14] An interrupt indicating that writing to CDBYR and CDBCR + * in a bundle write has finished. */ + __IOM uint32_t CPBE4 : 1; /*!< [15..15] An interrupt indicating that writing to CDBYR2 and + * CDBCR2 in a bundle write has finished. */ + __IOM uint32_t CDTOF : 1; /*!< [16..16] An interrupt indicating that data overflowed in the + * CRAM of the write buffer */ + __IOM uint32_t IGHS : 1; /*!< [17..17] An interrupt generated when the number of HD cycles + * set in CMCYR differ from the number of HD cycles input + * from an external module. */ + __IOM uint32_t IGVS : 1; /*!< [18..18] An interrupt generated when the number of VD cycles + * set in CMCYR differ from the number of VD cycles input + * from an external module. */ + uint32_t : 1; + __IOM uint32_t VBP : 1; /*!< [20..20] An interrupt indicating that VD has been input while + * the CEU holds data (insufficient vertical-sync front porch). */ + uint32_t : 2; + __IOM uint32_t FWF : 1; /*!< [23..23] The interrupt is generated when data is written to + * the address that exceeds the value specified with CFWCR.FMV. */ + __IOM uint32_t NHD : 1; /*!< [24..24] An interrupt indicating that no HD was input. */ + __IOM uint32_t NVD : 1; /*!< [25..25] An interrupt indicating that no VD was input. */ + uint32_t : 6; + } CETCR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IM uint32_t CSTSR; /*!< (@ 0x0000007C) Capture Status Register */ + + struct + { + __IM uint32_t CPTON : 1; /*!< [0..0] Indicates that the CEU is operating. */ + uint32_t : 15; + __IM uint32_t CPFLD : 1; /*!< [16..16] Indicates which field is being captured. */ + uint32_t : 7; + __IM uint32_t CRST : 1; /*!< [24..24] Indicates which register plane is currently used. */ + uint32_t : 7; + } CSTSR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IM uint32_t CDSSR; /*!< (@ 0x00000084) Capture Data Size Register */ + + struct + { + __IM uint32_t CDSS : 32; /*!< [31..0] Indicate the size of data written to the memory in data + * enable fetch. */ + } CDSSR_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t CDAYR2; /*!< (@ 0x00000090) Capture Data Address Y Register 2 */ + + struct + { + __IOM uint32_t CAYR2 : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR2_b; + }; + + union + { + __IOM uint32_t CDACR2; /*!< (@ 0x00000094) Capture Data Address C Register 2 */ + + struct + { + __IOM uint32_t CACR2 : 32; /*!< [31..0] Capture Data Address C2 */ + } CDACR2_b; + }; + + union + { + __IOM uint32_t CDBYR2; /*!< (@ 0x00000098) Capture Data Bottom-Field Address Y Register + * 2 */ + + struct + { + __IOM uint32_t CBYR2 : 32; /*!< [31..0] Set the address for storing the Y component data of + * the captured bottom-field data (4-pixel units). */ + } CDBYR2_b; + }; + + union + { + __IOM uint32_t CDBCR2; /*!< (@ 0x0000009C) Capture Data Bottom-Field Address C Register + * 2 */ + + struct + { + __IOM uint32_t CBCR2 : 32; /*!< [31..0] Set the address for storing the C component data of + * the captured bottom-field data (4-pixel units). */ + } CDBCR2_b; + }; + + union + { + __IOM uint32_t AXIBUSCTL2; /*!< (@ 0x000000A0) AXI Bus Control Register 2 */ + + struct + { + __IOM uint32_t AWCACHE : 4; /*!< [3..0] AWCACHE[3:0] Signals for Capture Engine Unit */ + uint32_t : 28; + } AXIBUSCTL2_b; + }; + __IM uint32_t RESERVED6[987]; + + union + { + __IOM uint32_t CAMOR_B; /*!< (@ 0x00001010) Capture Interface Offset Register */ + + struct + { + __IOM uint32_t HOFST : 13; /*!< [12..0] Specify the capture start location in terms of the number + * of clock cycles from a horizontal sync signal (1-cycle + * units). */ + uint32_t : 3; + __IOM uint32_t VOFST : 12; /*!< [27..16] Specify the capture start location in terms of the + * HD count from a vertical sync signal (1-HD units). */ + uint32_t : 4; + } CAMOR_B_b; + }; + + union + { + __IOM uint32_t CAPWR_B; /*!< (@ 0x00001014) Capture Interface Width Register */ + + struct + { + __IOM uint32_t HWDTH : 13; /*!< [12..0] Specify the horizontal capture period. */ + uint32_t : 3; + __IOM uint32_t VWDTH : 12; /*!< [27..16] Specify the vertical capture period (4-HD units). */ + uint32_t : 4; + } CAPWR_B_b; + }; + __IM uint32_t RESERVED7[6]; + + union + { + __IOM uint32_t CFLCR_B; /*!< (@ 0x00001030) Capture Filter Control Register */ + + struct + { + __IOM uint32_t HFRAC : 12; /*!< [11..0] Fraction Part of Horizontal Scale-Down Factor */ + __IOM uint32_t HMANT : 4; /*!< [15..12] Mantissa Part of Horizontal Scale-Down Factor */ + __IOM uint32_t VFRAC : 12; /*!< [27..16] Fraction Part of Vertical Scale-Down Factor */ + __IOM uint32_t VMANT : 4; /*!< [31..28] Mantissa Part of Vertical Scale-Down Factor */ + } CFLCR_B_b; + }; + + union + { + __IOM uint32_t CFSZR_B; /*!< (@ 0x00001034) Capture Filter Size Clip Register */ + + struct + { + __IOM uint32_t HFCLP : 12; /*!< [11..0] Specify the horizontal clipping value of the filter + * output size (4-pixel units). */ + uint32_t : 4; + __IOM uint32_t VFCLP : 12; /*!< [27..16] Set the vertical clipping value of the filter output + * size (4-pixel units). */ + uint32_t : 4; + } CFSZR_B_b; + }; + + union + { + __IOM uint32_t CDWDR_B; /*!< (@ 0x00001038) Capture Destination Width Register */ + + struct + { + __IOM uint32_t CHDW : 13; /*!< [12..0] Specify the horizontal image size in the memory area + * where the captured image is to be stored (4-byte units). */ + uint32_t : 19; + } CDWDR_B_b; + }; + + union + { + __IOM uint32_t CDAYR_B; /*!< (@ 0x0000103C) Capture Data Address Y Register */ + + struct + { + __IOM uint32_t CAYR : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR_B_b; + }; + + union + { + __IOM uint32_t CDACR_B; /*!< (@ 0x00001040) Capture Data Address C Register */ + + struct + { + __IOM uint32_t CACR : 32; /*!< [31..0] Capture Data Address C */ + } CDACR_B_b; + }; + + union + { + __IOM uint32_t CDBYR_B; /*!< (@ 0x00001044) Capture Data Bottom-Field Address Y Register */ + + struct + { + __IOM uint32_t CBYR : 32; /*!< [31..0] Set the address for storing the Y (luminance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBYR_B_b; + }; + + union + { + __IOM uint32_t CDBCR_B; /*!< (@ 0x00001048) Capture Data Bottom-Field Address C Register */ + + struct + { + __IOM uint32_t CBCR : 32; /*!< [31..0] Set the address for storing the C (chrominance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBCR_B_b; + }; + + union + { + __IOM uint32_t CBDSR_B; /*!< (@ 0x0000104C) Capture Bundle Destination Size Register */ + + struct + { + __IOM uint32_t CBVS : 23; /*!< [22..0] Select the number of lines or number of bytes for output + * to the memory in a bundle write. */ + uint32_t : 9; + } CBDSR_B_b; + }; + __IM uint32_t RESERVED8[4]; + + union + { + __IOM uint32_t CLFCR_B; /*!< (@ 0x00001060) Capture Low-Pass Filter Control Register */ + + struct + { + __IOM uint32_t LPF : 1; /*!< [0..0] Enables or disables operation of the low-pass filter. */ + uint32_t : 31; + } CLFCR_B_b; + }; + + union + { + __IOM uint32_t CDOCR_B; /*!< (@ 0x00001064) Capture Data Output Control Register */ + + struct + { + __IOM uint32_t COBS : 1; /*!< [0..0] Controls swapping in 8-bit units for data output from + * the CEU. */ + __IOM uint32_t COWS : 1; /*!< [1..1] Controls swapping in 16-bit units for data output from + * the CEU. */ + __IOM uint32_t COLS : 1; /*!< [2..2] Controls swapping in 32-bit units for data output from + * the CEU. */ + uint32_t : 1; + __IOM uint32_t CDS : 1; /*!< [4..4] Sets the image format when outputting the image data + * captured in the YCbCr422 format to the memory. */ + uint32_t : 11; + __IOM uint32_t CBE : 1; /*!< [16..16] Controls the number of lines of captured data to be + * written to the memory. */ + uint32_t : 15; + } CDOCR_B_b; + }; + __IM uint32_t RESERVED9[10]; + + union + { + __IOM uint32_t CDAYR2_B; /*!< (@ 0x00001090) Capture Data Address Y Register 2 */ + + struct + { + __IOM uint32_t CAYR2 : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR2_B_b; + }; + + union + { + __IOM uint32_t CDACR2_B; /*!< (@ 0x00001094) Capture Data Address C Register 2 */ + + struct + { + __IOM uint32_t CACR2 : 32; /*!< [31..0] Capture Data Address C2 */ + } CDACR2_B_b; + }; + + union + { + __IOM uint32_t CDBYR2_B; /*!< (@ 0x00001098) Capture Data Bottom-Field Address Y Register + * 2 */ + + struct + { + __IOM uint32_t CBYR2 : 32; /*!< [31..0] Set the address for storing the Y component data of + * the captured bottom-field data (4-pixel units). */ + } CDBYR2_B_b; + }; + + union + { + __IOM uint32_t CDBCR2_B; /*!< (@ 0x0000109C) Capture Data Bottom-Field Address C Register + * 2 */ + + struct + { + __IOM uint32_t CBCR2 : 32; /*!< [31..0] Set the address for storing the C component data of + * the captured bottom-field data (4-pixel units). */ + } CDBCR2_B_b; + }; + __IM uint32_t RESERVED10[988]; + + union + { + __IOM uint32_t CAMOR_M; /*!< (@ 0x00002010) Capture Interface Offset Register */ + + struct + { + __IOM uint32_t HOFST : 13; /*!< [12..0] Specify the capture start location in terms of the number + * of clock cycles from a horizontal sync signal (1-cycle + * units). */ + uint32_t : 3; + __IOM uint32_t VOFST : 12; /*!< [27..16] Specify the capture start location in terms of the + * HD count from a vertical sync signal (1-HD units). */ + uint32_t : 4; + } CAMOR_M_b; + }; + + union + { + __IOM uint32_t CAPWR_M; /*!< (@ 0x00002014) Capture Interface Width Register */ + + struct + { + __IOM uint32_t HWDTH : 13; /*!< [12..0] Specify the horizontal capture period. */ + uint32_t : 3; + __IOM uint32_t VWDTH : 12; /*!< [27..16] Specify the vertical capture period (4-HD units). */ + uint32_t : 4; + } CAPWR_M_b; + }; + __IM uint32_t RESERVED11[6]; + + union + { + __IOM uint32_t CFLCR_M; /*!< (@ 0x00002030) Capture Filter Control Register */ + + struct + { + __IOM uint32_t HFRAC : 12; /*!< [11..0] Fraction Part of Horizontal Scale-Down Factor */ + __IOM uint32_t HMANT : 4; /*!< [15..12] Mantissa Part of Horizontal Scale-Down Factor */ + __IOM uint32_t VFRAC : 12; /*!< [27..16] Fraction Part of Vertical Scale-Down Factor */ + __IOM uint32_t VMANT : 4; /*!< [31..28] Mantissa Part of Vertical Scale-Down Factor */ + } CFLCR_M_b; + }; + + union + { + __IOM uint32_t CFSZR_M; /*!< (@ 0x00002034) Capture Filter Size Clip Register */ + + struct + { + __IOM uint32_t HFCLP : 12; /*!< [11..0] Specify the horizontal clipping value of the filter + * output size (4-pixel units). */ + uint32_t : 4; + __IOM uint32_t VFCLP : 12; /*!< [27..16] Set the vertical clipping value of the filter output + * size (4-pixel units). */ + uint32_t : 4; + } CFSZR_M_b; + }; + + union + { + __IOM uint32_t CDWDR_M; /*!< (@ 0x00002038) Capture Destination Width Register */ + + struct + { + __IOM uint32_t CHDW : 13; /*!< [12..0] Specify the horizontal image size in the memory area + * where the captured image is to be stored (4-byte units). */ + uint32_t : 19; + } CDWDR_M_b; + }; + + union + { + __IOM uint32_t CDAYR_M; /*!< (@ 0x0000203C) Capture Data Address Y Register */ + + struct + { + __IOM uint32_t CAYR : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR_M_b; + }; + + union + { + __IOM uint32_t CDACR_M; /*!< (@ 0x00002040) Capture Data Address C Register */ + + struct + { + __IOM uint32_t CACR : 32; /*!< [31..0] Capture Data Address C */ + } CDACR_M_b; + }; + + union + { + __IOM uint32_t CDBYR_M; /*!< (@ 0x00002044) Capture Data Bottom-Field Address Y Register */ + + struct + { + __IOM uint32_t CBYR : 32; /*!< [31..0] Set the address for storing the Y (luminance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBYR_M_b; + }; + + union + { + __IOM uint32_t CDBCR_M; /*!< (@ 0x00002048) Capture Data Bottom-Field Address C Register */ + + struct + { + __IOM uint32_t CBCR : 32; /*!< [31..0] Set the address for storing the C (chrominance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBCR_M_b; + }; + + union + { + __IOM uint32_t CBDSR_M; /*!< (@ 0x0000204C) Capture Bundle Destination Size Register */ + + struct + { + __IOM uint32_t CBVS : 23; /*!< [22..0] Select the number of lines or number of bytes for output + * to the memory in a bundle write. */ + uint32_t : 9; + } CBDSR_M_b; + }; + __IM uint32_t RESERVED12[4]; + + union + { + __IOM uint32_t CLFCR_M; /*!< (@ 0x00002060) Capture Low-Pass Filter Control Register */ + + struct + { + __IOM uint32_t LPF : 1; /*!< [0..0] Enables or disables operation of the low-pass filter. */ + uint32_t : 31; + } CLFCR_M_b; + }; + + union + { + __IOM uint32_t CDOCR_M; /*!< (@ 0x00002064) Capture Data Output Control Register */ + + struct + { + __IOM uint32_t COBS : 1; /*!< [0..0] Controls swapping in 8-bit units for data output from + * the CEU. */ + __IOM uint32_t COWS : 1; /*!< [1..1] Controls swapping in 16-bit units for data output from + * the CEU. */ + __IOM uint32_t COLS : 1; /*!< [2..2] Controls swapping in 32-bit units for data output from + * the CEU. */ + uint32_t : 1; + __IOM uint32_t CDS : 1; /*!< [4..4] Sets the image format when outputting the image data + * captured in the YCbCr422 format to the memory. */ + uint32_t : 11; + __IOM uint32_t CBE : 1; /*!< [16..16] Controls the number of lines of captured data to be + * written to the memory. */ + uint32_t : 15; + } CDOCR_M_b; + }; + __IM uint32_t RESERVED13[10]; + + union + { + __IOM uint32_t CDAYR2_M; /*!< (@ 0x00002090) Capture Data Address Y Register 2 */ + + struct + { + __IOM uint32_t CAYR2 : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR2_M_b; + }; + + union + { + __IOM uint32_t CDACR2_M; /*!< (@ 0x00002094) Capture Data Address C Register 2 */ + + struct + { + __IOM uint32_t CACR2 : 32; /*!< [31..0] Capture Data Address C2 */ + } CDACR2_M_b; + }; + + union + { + __IOM uint32_t CDBYR2_M; /*!< (@ 0x00002098) Capture Data Bottom-Field Address Y Register + * 2 */ + + struct + { + __IOM uint32_t CBYR2 : 32; /*!< [31..0] Set the address for storing the Y component data of + * the captured bottom-field data (4-pixel units). */ + } CDBYR2_M_b; + }; + + union + { + __IOM uint32_t CDBCR2_M; /*!< (@ 0x0000209C) Capture Data Bottom-Field Address C Register + * 2 */ + + struct + { + __IOM uint32_t CBCR2 : 32; /*!< [31..0] Set the address for storing the C component data of + * the captured bottom-field data (4-pixel units). */ + } CDBCR2_M_b; + }; +} R_CEU_Type; /*!< Size = 8352 (0x20a0) */ + +/* =========================================================================================================================== */ +/* ================ R_ULPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ultra-Low Power Timer 0 (R_ULPT0) + */ + +typedef struct /*!< (@ 0x40220000) R_ULPT0 Structure */ +{ + union + { + __IOM uint32_t ULPTCNT; /*!< (@ 0x00000000) ULPT Counter Register */ + + struct + { + __IOM uint32_t ULPTCNT : 32; /*!< [31..0] 32bit counter and reload registerNOTE : When 1 is written + * to the TSTOP bit in the ULPTCR register, the 32-bit counter + * is forcibly stopped and set to FFFFFFFFH. */ + } ULPTCNT_b; + }; + + union + { + __IOM uint32_t ULPTCMA; /*!< (@ 0x00000004) ULPT Compare Match A Register */ + + struct + { + __IOM uint32_t ULPTCMA : 32; /*!< [31..0] ULPT Compare Match A RegisterNOTE : When 1 is written + * to the TSTOP bit in the ULPTCR register, set to FFFFFFFFH */ + } ULPTCMA_b; + }; + + union + { + __IOM uint32_t ULPTCMB; /*!< (@ 0x00000008) ULPT Compare Match B Register */ + + struct + { + __IOM uint32_t ULPTCMB : 32; /*!< [31..0] AGT Compare Match B RegisterNOTE : When 1 is written + * to the TSTOP bit in the ULPTCR register, set to FFFFFFFFH */ + } ULPTCMB_b; + }; + + union + { + __IOM uint8_t ULPTCR; /*!< (@ 0x0000000C) ULPT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] ULPT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] ULPT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] ULPT count forced stop */ + uint8_t : 2; + __IOM uint8_t TUNDF : 1; /*!< [5..5] ULPT underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] ULPT compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] ULPT compare match B flag */ + } ULPTCR_b; + }; + + union + { + __IOM uint8_t ULPTMR1; /*!< (@ 0x0000000D) ULPT Mode Register 1 */ + + struct + { + uint8_t : 1; + __IOM uint8_t TMOD1 : 1; /*!< [1..1] ULPT operating mode select */ + uint8_t : 1; + __IOM uint8_t TEDGPL : 1; /*!< [3..3] ULPTEVI edge polarity select */ + uint8_t : 1; + __IOM uint8_t TCK1 : 1; /*!< [5..5] ULPT count source select */ + uint8_t : 2; + } ULPTMR1_b; + }; + + union + { + __IOM uint8_t ULPTMR2; /*!< (@ 0x0000000E) ULPT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] fsub/LOCO count source clock frequency division ratio + * select */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] ULPT Low Power Mode */ + } ULPTMR2_b; + }; + + union + { + __IOM uint8_t ULPTMR3; /*!< (@ 0x0000000F) ULPT Mode Register 3 */ + + struct + { + __IOM uint8_t TCNTCTL : 1; /*!< [0..0] ULPT count function select */ + __IOM uint8_t TEVPOL : 1; /*!< [1..1] ULPTEVI polarity switch */ + __IOM uint8_t TOPOL : 1; /*!< [2..2] ULPTO polarity select */ + uint8_t : 1; + __IOM uint8_t TEECTL : 2; /*!< [5..4] ULPTEE function select */ + __IOM uint8_t TEEPOL : 2; /*!< [7..6] ULPTEE edge polarity select */ + } ULPTMR3_b; + }; + + union + { + __IOM uint8_t ULPTIOC; /*!< (@ 0x00000010) ULPT I/O Control Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t TOE : 1; /*!< [2..2] ULPTO output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] ULPTEVI input filter select */ + __IOM uint8_t TIOGT0 : 1; /*!< [6..6] ULPTEVI count control */ + uint8_t : 1; + } ULPTIOC_b; + }; + + union + { + __IOM uint8_t ULPTISR; /*!< (@ 0x00000011) ULPT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t RCCPSEL2 : 1; /*!< [2..2] ULPTEE polarty selection */ + uint8_t : 5; + } ULPTISR_b; + }; + + union + { + __IOM uint8_t ULPTCMSR; /*!< (@ 0x00000012) ULPT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] ULPTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] ULPTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] ULPTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] ULPTOB polarity select */ + uint8_t : 1; + } ULPTCMSR_b; + }; + __IM uint8_t RESERVED; +} R_ULPT0_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG_OCD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief On-Chip Debug Function (R_DEBUG_OCD) + */ + +typedef struct /*!< (@ 0x40011000) R_DEBUG_OCD Structure */ +{ + union + { + __IM uint32_t MCUERRSTAT; /*!< (@ 0x00000000) MCU Error Status Register */ + + struct + { + __IM uint32_t ZERO : 1; /*!< [0..0] Zeroization status flag */ + uint32_t : 31; + } MCUERRSTAT_b; + }; + + union + { + __IOM uint32_t MCUCTRL; /*!< (@ 0x00000004) MCU Control Register */ + + struct + { + __IOM uint32_t EDBGRQ0 : 1; /*!< [0..0] External Debug Request for CPU0 */ + __IOM uint32_t EDBGRQ1 : 1; /*!< [1..1] External Debug Request for CPU1 */ + uint32_t : 6; + __IOM uint32_t DBIRQ0 : 1; /*!< [8..8] Writing 1 to the bit wakes up the CPU0 from Deep Sleep + * mode or the MCU from Software Standby Mode or Deep Software + * Standby mode */ + __IOM uint32_t DBIRQ1 : 1; /*!< [9..9] Writing 1 to the bit wakes up the CPU1 from Deep Sleep + * mode or the MCU from Software Standby Mode or Deep Software + * Standby mode */ + uint32_t : 6; + __IOM uint32_t CPUWAIT0 : 1; /*!< [16..16] CPU0 WAIT SETTING */ + __IOM uint32_t CPUWAIT1 : 1; /*!< [17..17] CPU1 WAIT SETTING */ + uint32_t : 14; + } MCUCTRL_b; + }; + __IM uint32_t RESERVED[62]; + + union + { + __IOM uint32_t JBMDR; /*!< (@ 0x00000100) JTAG Boot Mode Entry Register */ + + struct + { + __IOM uint32_t KEY : 8; /*!< [7..0] Mode entry key */ + uint32_t : 24; + } JBMDR_b; + }; + __IM uint32_t RESERVED1[7]; + + union + { + __IOM uint32_t JBRDR; /*!< (@ 0x00000120) JTAG Boot Receive Data Register */ + + struct + { + __IOM uint32_t RDAT : 32; /*!< [31..0] Received data register */ + } JBRDR_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t JBTDR; /*!< (@ 0x00000130) JTAG Boot Transmit Data Register */ + + struct + { + __IOM uint32_t TDAT : 32; /*!< [31..0] Transmitted data register */ + } JBTDR_b; + }; + __IM uint32_t RESERVED3[3]; + + union + { + __IOM uint32_t JBSTR; /*!< (@ 0x00000140) JTAG Boot Status Register */ + + struct + { + __IOM uint32_t RDF : 1; /*!< [0..0] Receive buffer full */ + __IOM uint32_t TDE : 1; /*!< [1..1] Transmit data empty */ + uint32_t : 30; + } JBSTR_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IOM uint32_t JBICR; /*!< (@ 0x00000150) JTAG Boot Interrupt Control Register */ + + struct + { + __IOM uint32_t RDFIE : 1; /*!< [0..0] Receive buffer full interrupt enabled */ + uint32_t : 31; + } JBICR_b; + }; + __IM uint32_t RESERVED5[107]; + + union + { + __IM uint32_t FSBLSTATM; /*!< (@ 0x00000300) First Stage Boot Loader Status Monitor Register */ + + struct + { + __IM uint32_t CS : 1; /*!< [0..0] FSBL completion status */ + __IM uint32_t RS : 1; /*!< [1..1] FSBL result status */ + uint32_t : 30; + } FSBLSTATM_b; + }; +} R_DEBUG_OCD_Type; /*!< Size = 772 (0x304) */ + +/* =========================================================================================================================== */ +/* ================ R_DOTF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Decryption On The Fly (R_DOTF) + */ + +typedef struct /*!< (@ 0x40268800) R_DOTF Structure */ +{ + union + { + __IOM uint32_t CONVAREAST; /*!< (@ 0x00000000) DOTF Conversion Area Start Address Register */ + + struct + { + uint32_t : 12; + __IOM uint32_t CONVAREAST : 20; /*!< [31..12] First address of decryption processing area */ + } CONVAREAST_b; + }; + + union + { + __IOM uint32_t CONVAREAD; /*!< (@ 0x00000004) DOTF Conversion Area End Address Register */ + + struct + { + uint32_t : 12; + __IOM uint32_t CONVAREAD : 20; /*!< [31..12] End address of decryption processing area */ + } CONVAREAD_b; + }; + __IM uint32_t RESERVED[30]; + + union + { + __IOM uint32_t REG00; /*!< (@ 0x00000080) Register 0 */ + + struct + { + uint32_t : 9; + __IOM uint32_t B09 : 1; /*!< [9..9] Bit 09 */ + uint32_t : 6; + __IOM uint32_t B16 : 1; /*!< [16..16] Bit 09 */ + __IOM uint32_t B17 : 1; /*!< [17..17] Bit 17 */ + uint32_t : 2; + __IOM uint32_t B20 : 1; /*!< [20..20] Bit 20 */ + uint32_t : 3; + __IOM uint32_t B24 : 2; /*!< [25..24] Bit24-25 */ + uint32_t : 2; + __IOM uint32_t B28 : 2; /*!< [29..28] Bit28-29 */ + uint32_t : 2; + } REG00_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t REG03; /*!< (@ 0x0000008C) Register 03 */ + + struct + { + __IOM uint32_t B00 : 32; /*!< [31..0] Bit 0 */ + } REG03_b; + }; +} R_DOTF_Type; /*!< Size = 144 (0x90) */ + +/* =========================================================================================================================== */ +/* ================ R_AGTX0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGTX0) + */ + +typedef struct /*!< (@ 0x40221000) R_AGTX0 Structure */ +{ + union + { + __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers */ + __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers */ + }; +} R_AGTX0_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_COMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Common Agent (R_COMA) + */ + +typedef struct /*!< (@ 0x403C9000) R_COMA Structure */ +{ + union + { + __IM uint32_t RIPV; /*!< (@ 0x00000000) IP Version Register */ + + struct + { + __IM uint32_t TIPV : 4; /*!< [3..0] Top Module IP Version Number */ + __IM uint32_t GWIPV : 4; /*!< [7..4] Gateway CPU Agent IP Version Number */ + __IM uint32_t FWIPV : 4; /*!< [11..8] Forwarding Engine IP Version Number */ + __IM uint32_t EAIPV : 4; /*!< [15..12] Ethernet Agent IP Version Number */ + __IM uint32_t FBIPV : 4; /*!< [19..16] Fabric Bus IP Version Number */ + __IM uint32_t CAIPV : 4; /*!< [23..20] Common Agent IP Version Number */ + uint32_t : 8; + } RIPV_b; + }; + + union + { + __IOM uint32_t RRC; /*!< (@ 0x00000004) Reset Configuration Register */ + + struct + { + __IOM uint32_t RR : 1; /*!< [0..0] Software Reset */ + uint32_t : 31; + } RRC_b; + }; + + union + { + __IOM uint32_t RCEC; /*!< (@ 0x00000008) Clock Enable Configuration Register */ + + struct + { + __IOM uint32_t ACE : 7; /*!< [6..0] Agent Clock Enable */ + uint32_t : 9; + __IOM uint32_t RCE : 1; /*!< [16..16] Clock Enable */ + uint32_t : 15; + } RCEC_b; + }; + + union + { + __IM uint32_t RCDC; /*!< (@ 0x0000000C) Clock Disable Configuration Register */ + + struct + { + __IM uint32_t ACD : 7; /*!< [6..0] Agent Clock Disable */ + uint32_t : 9; + __IM uint32_t RCD : 1; /*!< [16..16] Clock Disable */ + uint32_t : 15; + } RCDC_b; + }; + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t CABPIBWMC[8]; /*!< (@ 0x00000020) Buffer Pool IPV Based Watermark Configuration + * Register [0..7] */ + + struct + { + __IOM uint32_t IBUWMPN : 10; /*!< [9..0] IPV Based Unsecure Watermark Pointer Number */ + uint32_t : 6; + __IOM uint32_t IBSWMPN : 10; /*!< [25..16] IPV Based Secure Watermark Pointer Number */ + uint32_t : 6; + } CABPIBWMC_b[8]; + }; + + union + { + __IOM uint32_t CABPWMLC; /*!< (@ 0x00000040) Buffer Pool Watermark Level Configuration Register */ + + struct + { + __IOM uint32_t WMFL : 13; /*!< [12..0] Watermark Flush Level */ + uint32_t : 3; + __IOM uint32_t WMCL : 13; /*!< [28..16] Watermark Critical Level */ + uint32_t : 3; + } CABPWMLC_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t CABPPFLC[2]; /*!< (@ 0x00000050) Buffer Pointer Pause Frame Level [0..1] Configuration + * Register */ + + struct + { + __IOM uint32_t PDL : 13; /*!< [12..0] Pause De-Assertion Level */ + uint32_t : 3; + __IOM uint32_t PAL : 13; /*!< [28..16] Pause Assertion Level */ + uint32_t : 3; + } CABPPFLC_b[2]; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t CABPPWMLC[3]; /*!< (@ 0x00000060) Port [0..2] Buffer Pool Watermark Level Configuration + * Register */ + + struct + { + __IOM uint32_t PWMFL : 13; /*!< [12..0] Watermark Flush Level */ + uint32_t : 3; + __IOM uint32_t PWMCL : 13; /*!< [28..16] Watermark Critical Level */ + uint32_t : 3; + } CABPPWMLC_b[3]; + }; + __IM uint32_t RESERVED3[13]; + __IOM R_COMA_CABPPPFLC_Type CABPPPFLC0; /*!< (@ 0x000000A0) 0 */ + __IOM R_COMA_CABPPPFLC_Type CABPPPFLC1; /*!< (@ 0x000000A8) 1 */ + __IOM R_COMA_CABPPPFLC_Type CABPPPFLC2; /*!< (@ 0x000000B0) 2 */ + __IM uint32_t RESERVED4[18]; + + union + { + __IOM uint32_t CABPULC[3]; /*!< (@ 0x00000100) Buffer Pointer Utilization Level Configuration + * Register [0..2] */ + + struct + { + __IOM uint32_t MXNPN : 13; /*!< [12..0] Maximum Number of Pointer for Port */ + uint32_t : 3; + __IOM uint32_t MNNPN : 13; /*!< [28..16] Minimum Number of Pointer for Port */ + uint32_t : 3; + } CABPULC_b[3]; + }; + __IM uint32_t RESERVED5[13]; + + union + { + __IOM uint32_t CABPIRM; /*!< (@ 0x00000140) Buffer Pool Initialization Register Monitoring + * Register */ + + struct + { + __IOM uint32_t BPIOG : 1; /*!< [0..0] Buffer Pool Initialization Ongoing */ + __IOM uint32_t BPR : 1; /*!< [1..1] Buffer Pool Ready */ + uint32_t : 30; + } CABPIRM_b; + }; + + union + { + __IM uint32_t CABPPCM; /*!< (@ 0x00000144) Buffer Pool Pointer Count Monitoring Register */ + + struct + { + __IM uint32_t RPC : 13; /*!< [12..0] Remaining Pointer Count */ + uint32_t : 3; + __IM uint32_t TPC : 13; /*!< [28..16] Total Pointer Count */ + uint32_t : 3; + } CABPPCM_b; + }; + + union + { + __IM uint32_t CABPLCM; /*!< (@ 0x00000148) Buffer Pool Pointer Least Count Monitoring Register */ + + struct + { + __IM uint32_t LRC : 13; /*!< [12..0] Least Remaining Pointer Count */ + uint32_t : 19; + } CABPLCM_b; + }; + __IM uint32_t RESERVED6[13]; + + union + { + __IM uint32_t CABPCPM[3]; /*!< (@ 0x00000180) Port [0..2] Buffer Pointer Count Monitoring Register */ + + struct + { + __IM uint32_t RPCP : 13; /*!< [12..0] Received Pointer Count */ + uint32_t : 19; + } CABPCPM_b[3]; + }; + __IM uint32_t RESERVED7[29]; + + union + { + __IM uint32_t CABPMCPM[3]; /*!< (@ 0x00000200) Port [0..2] Buffer Pointer Maximum Count Monitoring + * Register */ + + struct + { + __IM uint32_t RPMCP : 13; /*!< [12..0] Received Pointer Maximum Count */ + uint32_t : 19; + } CABPMCPM_b[3]; + }; + __IM uint32_t RESERVED8[61]; + + union + { + __IM uint32_t CARDNM; /*!< (@ 0x00000300) Rejected Descriptor Number Monitoring Register */ + + struct + { + __IM uint32_t RDNRR : 13; /*!< [12..0] Rejected Descriptor Number in Reject RAM */ + uint32_t : 19; + } CARDNM_b; + }; + + union + { + __IM uint32_t CARDMNM; /*!< (@ 0x00000304) Rejected Descriptor Maximum Number Monitoring + * Register */ + + struct + { + __IM uint32_t RDMNRR : 13; /*!< [12..0] Rejected Descriptor Maximum Number in Reject RAM */ + uint32_t : 19; + } CARDMNM_b; + }; + __IM uint32_t RESERVED9[2]; + + union + { + __IM uint32_t CARDCN; /*!< (@ 0x00000310) Rejected Descriptor Counter Register */ + + struct + { + __IM uint32_t RDN : 32; /*!< [31..0] Rejected Descriptor Number */ + } CARDCN_b; + }; + __IM uint32_t RESERVED10[59]; + + union + { + __IOM uint32_t CAEIS0; /*!< (@ 0x00000400) Error Interrupt Status Register 0 */ + + struct + { + __IOM uint32_t PECCES : 1; /*!< [0..0] Pointer ECC Error Interrupt Status */ + __IOM uint32_t DSECCES : 1; /*!< [1..1] Descriptor ECC Error Interrupt Status */ + __IOM uint32_t BPECCES : 1; /*!< [2..2] Buffer Pool ECC Error Interrupt Status */ + uint32_t : 5; + __IOM uint32_t BPOPS : 1; /*!< [8..8] Buffer Pool Out of Pointer Status */ + __IOM uint32_t WMCLOS : 1; /*!< [9..9] Watermark Critical Level Overtook Status */ + __IOM uint32_t WMFLOS : 1; /*!< [10..10] Watermark Flush Level Overtook Status */ + uint32_t : 5; + __IM uint32_t EEIPLN : 4; /*!< [19..16] ECC Error Inducing Pointer Loss Number */ + uint32_t : 12; + } CAEIS0_b; + }; + + union + { + __IOM uint32_t CAEIE0; /*!< (@ 0x00000404) Error Interrupt Enable Register 0 */ + + struct + { + __IOM uint32_t PECCEE : 1; /*!< [0..0] Pointer ECC Error Interrupt Enable */ + __IOM uint32_t DSECCEE : 1; /*!< [1..1] Descriptor ECC Error Interrupt Enable */ + __IOM uint32_t BPECCEE : 1; /*!< [2..2] Buffer Pool ECC Error Interrupt Enable */ + uint32_t : 5; + __IOM uint32_t BPOPE : 1; /*!< [8..8] Buffer Pool Out of Pointer Enable */ + __IOM uint32_t WMCLOE : 1; /*!< [9..9] Watermark Critical Level Overtook Enable */ + __IOM uint32_t WMFLOE : 1; /*!< [10..10] Watermark Flush Level Overtook Enable */ + uint32_t : 21; + } CAEIE0_b; + }; + + union + { + __IM uint32_t CAEID0; /*!< (@ 0x00000408) Error Interrupt Disable Register 0 */ + + struct + { + __IM uint32_t PECCED : 1; /*!< [0..0] Pointer ECC Error Interrupt Disable */ + __IM uint32_t DSECCED : 1; /*!< [1..1] Descriptor ECC Error Interrupt Disable */ + __IM uint32_t BPECCED : 1; /*!< [2..2] Buffer Pool ECC Error Interrupt Disable */ + uint32_t : 5; + __IM uint32_t BPOPD : 1; /*!< [8..8] Buffer Pool Out of Pointer Disable */ + __IM uint32_t WMCLOD : 1; /*!< [9..9] Watermark Critical Level Overtook Disable */ + __IM uint32_t WMFLOD : 1; /*!< [10..10] Watermark Flush Level Overtook Disable */ + uint32_t : 21; + } CAEID0_b; + }; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t CAEIS1; /*!< (@ 0x00000410) Error Interrupt Status Register 1 */ + + struct + { + __IOM uint32_t PWMCLOS : 7; /*!< [6..0] Port Watermark Critical Level Overtook Status */ + uint32_t : 9; + __IOM uint32_t PWMFLOS : 7; /*!< [22..16] Port Watermark Flush Level Overtook Status */ + uint32_t : 9; + } CAEIS1_b; + }; + + union + { + __IOM uint32_t CAEIE1; /*!< (@ 0x00000414) Error Interrupt Enable Register 1 */ + + struct + { + __IOM uint32_t PWMCLOE : 7; /*!< [6..0] Port Watermark Critical Level Overtook Enable */ + uint32_t : 9; + __IOM uint32_t PWMFLOE : 7; /*!< [22..16] Port Watermark Flush Level Overtook Enable */ + uint32_t : 9; + } CAEIE1_b; + }; + + union + { + __IM uint32_t CAEID1; /*!< (@ 0x00000418) Error Interrupt Disable Register 1 */ + + struct + { + __IM uint32_t PWMCLOD : 7; /*!< [6..0] Port Watermark Critical Level Overtook Disable */ + uint32_t : 9; + __IM uint32_t PWMFLOD : 7; /*!< [22..16] Port Watermark Flush Level Overtook Disable */ + uint32_t : 9; + } CAEID1_b; + }; + __IM uint32_t RESERVED12[9]; + + union + { + __IOM uint32_t CAMIS0; /*!< (@ 0x00000440) Monitoring Interrupt Status Register 0 */ + + struct + { + __IOM uint32_t PFS : 2; /*!< [1..0] Pause Frame Status */ + uint32_t : 30; + } CAMIS0_b; + }; + + union + { + __IOM uint32_t CAMIE0; /*!< (@ 0x00000444) Monitoring Interrupt Enable Register 0 */ + + struct + { + __IOM uint32_t PFE : 2; /*!< [1..0] Pause Frame Enable */ + uint32_t : 30; + } CAMIE0_b; + }; + + union + { + __IM uint32_t CAMID0; /*!< (@ 0x00000448) Monitoring Interrupt Disable Register 0 */ + + struct + { + __IM uint32_t PFD : 2; /*!< [1..0] Pause Frame Disable */ + uint32_t : 30; + } CAMID0_b; + }; + __IM uint32_t RESERVED13; + + union + { + __IOM uint32_t CAMIS1; /*!< (@ 0x00000450) Monitoring Interrupt Status Register 1 */ + + struct + { + __IOM uint32_t PPFS : 14; /*!< [13..0] Port Pause Frame Status */ + uint32_t : 18; + } CAMIS1_b; + }; + + union + { + __IOM uint32_t CAMIE1; /*!< (@ 0x00000454) Monitoring Interrupt Enable Register 1 */ + + struct + { + __IOM uint32_t PPFE : 14; /*!< [13..0] Port Pause Frame Enable */ + uint32_t : 18; + } CAMIE1_b; + }; + + union + { + __IM uint32_t CAMID1; /*!< (@ 0x00000458) Monitoring Interrupt Disable Register 1 */ + + struct + { + __IM uint32_t PPFD : 14; /*!< [13..0] Port Pause Frame Disable */ + uint32_t : 18; + } CAMID1_b; + }; +} R_COMA_Type; /*!< Size = 1116 (0x45c) */ + +/* =========================================================================================================================== */ +/* ================ R_CPU_CTRL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Individual CPU Control (R_CPU_CTRL) + */ + +typedef struct /*!< (@ 0x4000F000) R_CPU_CTRL Structure */ +{ + __IM uint32_t RESERVED[12]; + + union + { + __IOM uint8_t CPU0LCKUPCR; /*!< (@ 0x00000030) CPU0 Lockup Control Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after detection of CPUn lockup */ + uint8_t : 7; + } CPU0LCKUPCR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t CPU1LCKUPCR; /*!< (@ 0x00000034) CPU1 Lockup Control Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after detection of CPUn lockup */ + uint8_t : 7; + } CPU1LCKUPCR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t CPU0INITVTOR; /*!< (@ 0x00000040) CPU0 Initial Vector Base Address Register */ + + struct + { + __IOM uint32_t CPUnINITVTOR : 32; /*!< [31..0] CPUn Initial Vector Base Address */ + } CPU0INITVTOR_b; + }; + + union + { + __IOM uint32_t CPU1INITVTOR; /*!< (@ 0x00000044) CPU1 Initial Vector Base Address Register */ + + struct + { + __IOM uint32_t CPUnINITVTOR : 32; /*!< [31..0] CPUn Initial Vector Base Address */ + } CPU1INITVTOR_b; + }; + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint8_t CPU0WAITCR; /*!< (@ 0x00000050) CPU0 CPUWAIT Control Register */ + + struct + { + __IOM uint8_t CPUWAIT : 1; /*!< [0..0] Writing 1 to stall the CPUn when it is out of reset */ + uint8_t : 7; + } CPU0WAITCR_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + + union + { + __IOM uint8_t CPU1WAITCR; /*!< (@ 0x00000054) CPU1 CPUWAIT Control Register */ + + struct + { + __IOM uint8_t CPUWAIT : 1; /*!< [0..0] Writing 1 to stall the CPUn when it is out of reset */ + uint8_t : 7; + } CPU1WAITCR_b; + }; + __IM uint8_t RESERVED9; + __IM uint16_t RESERVED10; + __IM uint32_t RESERVED11[2]; + + union + { + __IOM uint16_t CPU0ACTCSR; /*!< (@ 0x00000060) CPU0 Activation Control and Status Register */ + + struct + { + __IOM uint16_t ACTREQ : 1; /*!< [0..0] CPUn activation request */ + uint16_t : 6; + __IM uint16_t ACT : 1; /*!< [7..7] CPUn activation state */ + __IOM uint16_t KEY : 8; /*!< [15..8] Key code */ + } CPU0ACTCSR_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t CPU1ACTCSR; /*!< (@ 0x00000064) CPU1 Activation Control and Status Register */ + + struct + { + __IOM uint16_t ACTREQ : 1; /*!< [0..0] CPUn activation request */ + uint16_t : 6; + __IM uint16_t ACT : 1; /*!< [7..7] CPUn activation state */ + __IOM uint16_t KEY : 8; /*!< [15..8] Key code */ + } CPU1ACTCSR_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[2]; + + union + { + __IOM uint8_t CPU0LMECR; /*!< (@ 0x00000070) CPU0 Local Memory Error Control Register */ + + struct + { + __IOM uint8_t SYRSTEN : 1; /*!< [0..0] System Reset request enable */ + uint8_t : 7; + } CPU0LMECR_b; + }; + __IM uint8_t RESERVED15; + __IM uint16_t RESERVED16; + __IM uint32_t RESERVED17; + + union + { + __IOM uint8_t CPUIDR; /*!< (@ 0x00000078) CPU Identification Register */ + + struct + { + __IM uint8_t CPUID : 1; /*!< [0..0] CPU Identification */ + uint8_t : 7; + } CPUIDR_b; + }; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; + __IM uint32_t RESERVED20; + + union + { + __IOM uint8_t CPU0STATM; /*!< (@ 0x00000080) CPU0 Status Monitor Register */ + + struct + { + __IM uint8_t SLEEPING : 1; /*!< [0..0] Sleeping State */ + __IM uint8_t SLEEPDEEP : 1; /*!< [1..1] Indicates that the processor is at a Deep Sleep mode */ + uint8_t : 2; + __IM uint8_t SAHBSTP : 1; /*!< [4..4] S-AHB Status Flag */ + uint8_t : 3; + } CPU0STATM_b; + }; + __IM uint8_t RESERVED21; + __IM uint16_t RESERVED22; + + union + { + __IOM uint8_t CPU1STATM; /*!< (@ 0x00000084) CPU1 Status Monitor Register */ + + struct + { + __IM uint8_t SLEEPING : 1; /*!< [0..0] Sleeping State */ + __IM uint8_t SLEEPDEEP : 1; /*!< [1..1] Indicates that the processor is at a Deep Sleep mode */ + uint8_t : 2; + __IM uint8_t SAHBSTP : 1; /*!< [4..4] S-AHB Status Flag */ + uint8_t : 3; + } CPU1STATM_b; + }; + __IM uint8_t RESERVED23; + __IM uint16_t RESERVED24; + __IM uint32_t RESERVED25[2]; + + union + { + __IOM uint8_t SECEXTMON; /*!< (@ 0x00000090) CPU SECEXT Monitor Register */ + + struct + { + __IM uint8_t SECEXT0 : 1; /*!< [0..0] CPU0 Security Extension */ + __IM uint8_t SECEXT1 : 1; /*!< [1..1] CPU1 Security Extension */ + uint8_t : 6; + } SECEXTMON_b; + }; + __IM uint8_t RESERVED26; + __IM uint16_t RESERVED27; + + union + { + __IOM uint32_t NSCPUCR; /*!< (@ 0x00000094) Non-secure CPU Control Register */ + + struct + { + __IOM uint32_t RSTREQEN : 1; /*!< [0..0] System Reset Request Enable */ + uint32_t : 31; + } NSCPUCR_b; + }; + __IM uint32_t RESERVED28[218]; + + union + { + __IOM uint8_t CPU0LOCKCR; /*!< (@ 0x00000400) CPU0 Function Lock Control Register */ + + struct + { + __IOM uint8_t LCKSVTAIR : 1; /*!< [0..0] Disables writes to secure registers VTOR_S, AIRCR.PRIS, + * AIRCR.BFHFNMINS */ + __IOM uint8_t LCKSMPU : 1; /*!< [1..1] Disables writes to registers that are associated with + * the Secure MPU region */ + __IOM uint8_t LCKSAU : 1; /*!< [2..2] Disables writes to registers that are associated with + * the SAU region */ + __IOM uint8_t LCKITGU : 1; /*!< [3..3] Disables writes to registers that are associated with + * the ITCM interface */ + __IOM uint8_t LCKDTGU : 1; /*!< [4..4] Disables writes to registers that are associated with + * the DTCM interface */ + __IOM uint8_t LCKDCAIC : 1; /*!< [5..5] Disable access to the instruction cache direct cache + * access registers DCAICLR and DCAICRR */ + uint8_t : 2; + } CPU0LOCKCR_b; + }; + __IM uint8_t RESERVED29; + __IM uint16_t RESERVED30; + + union + { + __IOM uint8_t CPU1LOCKCR; /*!< (@ 0x00000404) CPU1 Function Lock Control Register */ + + struct + { + __IOM uint8_t LCKSVTAIR : 1; /*!< [0..0] Disables writes to secure registers VTOR_S, AIRCR.PRIS, + * AIRCR.BFHFNMINS */ + __IOM uint8_t LCKSMPU : 1; /*!< [1..1] Disables writes to registers that are associated with + * the Secure MPU region */ + __IOM uint8_t LCKSAU : 1; /*!< [2..2] Disables writes to registers that are associated with + * the SAU region */ + __IOM uint8_t LCKITGU : 1; /*!< [3..3] Disables writes to registers that are associated with + * the ITCM interface */ + __IOM uint8_t LCKDTGU : 1; /*!< [4..4] Disables writes to registers that are associated with + * the DTCM interface */ + __IOM uint8_t LCKDCAIC : 1; /*!< [5..5] Disable access to the instruction cache direct cache + * access registers DCAICLR and DCAICRR */ + uint8_t : 2; + } CPU1LOCKCR_b; + }; + __IM uint8_t RESERVED31; + __IM uint16_t RESERVED32; + __IM uint32_t RESERVED33[62]; + + union + { + __IOM uint8_t CPU0LOCKCRNS; /*!< (@ 0x00000500) CPU0 Non-secure Function Lock Control Register */ + + struct + { + __IOM uint8_t LCKNSVTOR : 1; /*!< [0..0] Disables writes to the VTOR_NS register */ + __IOM uint8_t LCKNSMPU : 1; /*!< [1..1] Disables writes to registers that are associated with + * the Non-secure MPU region */ + uint8_t : 6; + } CPU0LOCKCRNS_b; + }; + __IM uint8_t RESERVED34; + __IM uint16_t RESERVED35; + + union + { + __IOM uint8_t CPU1LOCKCRNS; /*!< (@ 0x00000504) CPU1 Non-secure Function Lock Control Register */ + + struct + { + __IOM uint8_t LCKNSVTOR : 1; /*!< [0..0] Disables writes to the VTOR_NS register */ + __IOM uint8_t LCKNSMPU : 1; /*!< [1..1] Disables writes to registers that are associated with + * the Non-secure MPU region */ + uint8_t : 6; + } CPU1LOCKCRNS_b; + }; + __IM uint8_t RESERVED36; + __IM uint16_t RESERVED37; + __IM uint32_t RESERVED38[206]; + + union + { + __IOM uint16_t CPU0CRPT; /*!< (@ 0x00000840) CPU0 Control Register Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key to enable/disable writing to PROTECT */ + } CPU0CRPT_b; + }; + __IM uint16_t RESERVED39; + + union + { + __IOM uint16_t CPU1CRPT; /*!< (@ 0x00000844) CPU1 Control Register Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key to enable/disable writing to PROTECT */ + } CPU1CRPT_b; + }; + __IM uint16_t RESERVED40; +} R_CPU_CTRL_Type; /*!< Size = 2120 (0x848) */ + +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CANFD ECC (R_ECCMB0) + */ + +typedef struct /*!< (@ 0x4036F200) R_ECCMB0 Structure */ +{ + union + { + __IOM uint32_t EC710CTL; /*!< (@ 0x00000000) ECC Control Register */ + + struct + { + __IM uint32_t ECEMF : 1; /*!< [0..0] ECC Error Message Flag */ + __IM uint32_t ECER1F : 1; /*!< [1..1] ECC Error Detection and Correction Flag */ + __IM uint32_t ECER2F : 1; /*!< [2..2] 2-bit ECC Error Detection Flag */ + __IOM uint32_t EC1EDIC : 1; /*!< [3..3] ECC 1-bit Error Detection Interrupt Control */ + __IOM uint32_t EC2EDIC : 1; /*!< [4..4] ECC 2-bit Error Detection Interrupt Control */ + __IOM uint32_t EC1ECP : 1; /*!< [5..5] ECC 1-bit Error Correction Permission */ + __IOM uint32_t ECERVF : 1; /*!< [6..6] ECC Error Judgment Enable Flag */ + uint32_t : 2; + __IOM uint32_t ECER1C : 1; /*!< [9..9] Accumulating ECC Error Detection and Correction Flag + * Clear */ + __IOM uint32_t ECER2C : 1; /*!< [10..10] 2-bit ECC Error Detection Flag Clear */ + __IM uint32_t ECOVFF : 1; /*!< [11..11] ECC Overflow Detection Flag */ + uint32_t : 2; + __IOM uint32_t EMCA : 2; /*!< [15..14] Access Control to ECC Mode Select bit */ + __IM uint32_t ECSEDF0 : 1; /*!< [16..16] ECC Single bit Error Address Detection Flag */ + __IM uint32_t ECDEDF0 : 1; /*!< [17..17] ECC Dual Bit Error Address Detection Flag */ + uint32_t : 14; + } EC710CTL_b; + }; + + union + { + __IOM uint16_t EC710TMC; /*!< (@ 0x00000004) ECC Test Mode Control Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ECDCS : 1; /*!< [1..1] ECC Decode Input Select */ + uint16_t : 5; + __IOM uint16_t ECTMCE : 1; /*!< [7..7] ECC Test Mode Control Enable */ + uint16_t : 6; + __IOM uint16_t ETMA : 2; /*!< [15..14] ECC Test Mode Bit Access Control */ + } EC710TMC_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t EC710TED; /*!< (@ 0x0000000C) ECC Test Substitute Data Register */ + + struct + { + __IOM uint32_t ECEDB : 32; /*!< [31..0] ECC Test Substitute Data */ + } EC710TED_b; + }; + + union + { + __IM uint32_t EC710EAD0; /*!< (@ 0x00000010) ECC Error Address Register */ + + struct + { + __IM uint32_t ECEAD : 10; /*!< [9..0] ECC Error Address */ + uint32_t : 22; + } EC710EAD0_b; + }; +} R_ECCMB0_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_ESWM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Layer 3 Ethernet Switch Module (R_ESWM) + */ + +typedef struct /*!< (@ 0x403C8000) R_ESWM Structure */ +{ + union + { + __IOM uint32_t TPEMIMC0; /*!< (@ 0x00000000) Error and Monitoring Interrupt Mapping Configuration + * Register 0 */ + + struct + { + __IOM uint32_t SEIM : 1; /*!< [0..0] Switch Error Interrupt Mapping */ + __IOM uint32_t SEIGM : 1; /*!< [1..1] Switch Error Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t SEICM : 3; /*!< [6..4] Switch Error Interrupt Core Mapping */ + uint32_t : 9; + __IOM uint32_t SSIM0 : 1; /*!< [16..16] Switch Status Interrupt 0 Mapping */ + __IOM uint32_t SSIGM0 : 1; /*!< [17..17] Switch Status Interrupt 0 GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t SSICM0 : 3; /*!< [22..20] Switch Status Interrupt 0 Core Mapping */ + uint32_t : 1; + __IOM uint32_t SSIM1 : 1; /*!< [24..24] Switch Status Interrupt 1 Mapping */ + __IOM uint32_t SSIGM1 : 1; /*!< [25..25] Switch Status Interrupt 1 GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t SSICM1 : 3; /*!< [30..28] Switch Status Interrupt 1 Core Mapping */ + uint32_t : 1; + } TPEMIMC0_b; + }; + + union + { + __IOM uint32_t TPEMIMC1; /*!< (@ 0x00000004) Error and Monitoring Interrupt Mapping Configuration + * Register 1 */ + + struct + { + __IOM uint32_t FEIM : 1; /*!< [0..0] MFWD Error Interrupt Mapping */ + __IOM uint32_t FEIGM : 1; /*!< [1..1] MFWD Error Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t FEICM : 3; /*!< [6..4] MFWD Error Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t FSIM : 1; /*!< [8..8] MFWD Status Interrupt Mapping */ + __IOM uint32_t FSIGM : 1; /*!< [9..9] MFWD Status Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t FSICM : 3; /*!< [14..12] MFWD Status Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t CEIM : 1; /*!< [16..16] COMA Error Interrupt Mapping */ + __IOM uint32_t CEIGM : 1; /*!< [17..17] COMA Error Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t CEICM : 3; /*!< [22..20] COMA Error Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t CSIM : 1; /*!< [24..24] COMA Status Interrupt Mapping */ + __IOM uint32_t CSIGM : 1; /*!< [25..25] COMA Status Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t CSICM : 3; /*!< [30..28] COMA Status Interrupt Core Mapping */ + uint32_t : 1; + } TPEMIMC1_b; + }; + + union + { + __IOM uint32_t TPEMIMC2; /*!< (@ 0x00000008) Error and Monitoring Interrupt Mapping Configuration + * Register 2 */ + + struct + { + __IOM uint32_t GEIM0 : 1; /*!< [0..0] GWCA0 Error Interrupt Mapping */ + __IOM uint32_t GEIGM0 : 1; /*!< [1..1] GWCA0 Error Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t GEICM0 : 3; /*!< [6..4] GWCA0 Error Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t GSIM0 : 1; /*!< [8..8] GWCA0 Status Interrupt Mapping */ + __IOM uint32_t GSIGM0 : 1; /*!< [9..9] GWCA0 Status Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t GSICM0 : 3; /*!< [14..12] GWCA0 Status Interrupt Core Mapping */ + uint32_t : 17; + } TPEMIMC2_b; + }; + + union + { + __IOM uint32_t TPEMIMC3; /*!< (@ 0x0000000C) Error and Monitoring Interrupt Mapping Configuration + * Register 3 */ + + struct + { + __IOM uint32_t EEIM0 : 1; /*!< [0..0] ETHA0 Error Interrupt Mapping */ + __IOM uint32_t EEIGM0 : 1; /*!< [1..1] ETHA0 Error Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t EEICM0 : 3; /*!< [6..4] ETHA0 Error Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t ESIM0 : 1; /*!< [8..8] ETHA0 Status Interrupt Mapping */ + __IOM uint32_t ESIGM0 : 1; /*!< [9..9] ETHA0 Status Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t ESICM0 : 3; /*!< [14..12] ETHA0 Status Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t RSIM0 : 1; /*!< [16..16] RMAC0 Status Interrupt Mapping */ + __IOM uint32_t RSIGM0 : 1; /*!< [17..17] RMAC0 Status Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t RSICM0 : 3; /*!< [22..20] RMAC0 Status Interrupt Core Mapping */ + uint32_t : 9; + } TPEMIMC3_b; + }; + + union + { + __IOM uint32_t TPEMIMC4; /*!< (@ 0x00000010) Error and Monitoring Interrupt Mapping Configuration + * Register 4 */ + + struct + { + __IOM uint32_t EEIM1 : 1; /*!< [0..0] ETHA1 Error Interrupt Mapping */ + __IOM uint32_t EEIGM1 : 1; /*!< [1..1] ETHA1 Error Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t EEICM1 : 3; /*!< [6..4] ETHA1 Error Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t ESIM1 : 1; /*!< [8..8] ETHA1 Status Interrupt Mapping */ + __IOM uint32_t ESIGM1 : 1; /*!< [9..9] ETHA1 Status Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t ESICM1 : 3; /*!< [14..12] ETHA1 Status Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t RSIM1 : 1; /*!< [16..16] RMAC1 Status Interrupt Mapping */ + __IOM uint32_t RSIGM1 : 1; /*!< [17..17] RMAC1 Status Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t RSICM1 : 3; /*!< [22..20] RMAC1 Status Interrupt Core Mapping */ + uint32_t : 9; + } TPEMIMC4_b; + }; + __IM uint32_t RESERVED[27]; + + union + { + __IOM uint32_t TPEMIMC60; /*!< (@ 0x00000080) Error and Monitoring Interrupt Mapping Configuration + * Register 60 */ + + struct + { + __IOM uint32_t GTSIM0 : 1; /*!< [0..0] GWCA0 Timestamp Interrupt Mapping */ + __IOM uint32_t GTSICM0 : 3; /*!< [3..1] GWCA0 Timestamp Interrupt Core Mapping */ + uint32_t : 28; + } TPEMIMC60_b; + }; + + union + { + __IOM uint32_t TPEMIMC61; /*!< (@ 0x00000084) Error and Monitoring Interrupt Mapping Configuration + * Register 61 */ + + struct + { + __IOM uint32_t GTSIM0 : 1; /*!< [0..0] GWCA0 Timestamp Interrupt Mapping */ + __IOM uint32_t GTSICM0 : 3; /*!< [3..1] GWCA0 Timestamp Interrupt Core Mapping */ + uint32_t : 28; + } TPEMIMC61_b; + }; + + union + { + __IOM uint32_t TPEMIMC62; /*!< (@ 0x00000088) Error and Monitoring Interrupt Mapping Configuration + * Register 62 */ + + struct + { + __IOM uint32_t GTSIM0 : 1; /*!< [0..0] GWCA0 Timestamp Interrupt Mapping */ + __IOM uint32_t GTSICM0 : 3; /*!< [3..1] GWCA0 Timestamp Interrupt Core Mapping */ + uint32_t : 28; + } TPEMIMC62_b; + }; + + union + { + __IOM uint32_t TPEMIMC63; /*!< (@ 0x0000008C) Error and Monitoring Interrupt Mapping Configuration + * Register 63 */ + + struct + { + __IOM uint32_t GTSIM0 : 1; /*!< [0..0] GWCA0 Timestamp Interrupt Mapping */ + __IOM uint32_t GTSICM0 : 3; /*!< [3..1] GWCA0 Timestamp Interrupt Core Mapping */ + uint32_t : 28; + } TPEMIMC63_b; + }; + + union + { + __IOM uint32_t TPEMIMC64; /*!< (@ 0x00000090) Error and Monitoring Interrupt Mapping Configuration + * Register 64 */ + + struct + { + __IOM uint32_t GTSIM0 : 1; /*!< [0..0] GWCA0 Timestamp Interrupt Mapping */ + __IOM uint32_t GTSICM0 : 3; /*!< [3..1] GWCA0 Timestamp Interrupt Core Mapping */ + uint32_t : 28; + } TPEMIMC64_b; + }; + __IM uint32_t RESERVED1[27]; + + union + { + __IOM uint32_t TPEMIMC70; /*!< (@ 0x00000100) Error and Monitoring Interrupt Mapping Configuration + * Register 70 */ + + struct + { + __IOM uint32_t GDICM0 : 3; /*!< [2..0] GWCA0 Data Interrupt Core Mapping */ + uint32_t : 29; + } TPEMIMC70_b; + }; + + union + { + __IOM uint32_t TPEMIMC71; /*!< (@ 0x00000104) Error and Monitoring Interrupt Mapping Configuration + * Register 71 */ + + struct + { + __IOM uint32_t GDICM0 : 3; /*!< [2..0] GWCA0 Data Interrupt Core Mapping */ + uint32_t : 29; + } TPEMIMC71_b; + }; + + union + { + __IOM uint32_t TPEMIMC72; /*!< (@ 0x00000108) Error and Monitoring Interrupt Mapping Configuration + * Register 72 */ + + struct + { + __IOM uint32_t GDICM0 : 3; /*!< [2..0] GWCA0 Data Interrupt Core Mapping */ + uint32_t : 29; + } TPEMIMC72_b; + }; + + union + { + __IOM uint32_t TPEMIMC73; /*!< (@ 0x0000010C) Error and Monitoring Interrupt Mapping Configuration + * Register 73 */ + + struct + { + __IOM uint32_t GDICM0 : 3; /*!< [2..0] GWCA0 Data Interrupt Core Mapping */ + uint32_t : 29; + } TPEMIMC73_b; + }; + + union + { + __IOM uint32_t TPEMIMC74; /*!< (@ 0x00000110) Error and Monitoring Interrupt Mapping Configuration + * Register 74 */ + + struct + { + __IOM uint32_t GDICM0 : 3; /*!< [2..0] GWCA0 Data Interrupt Core Mapping */ + uint32_t : 29; + } TPEMIMC74_b; + }; + __IM uint32_t RESERVED2[379]; + + union + { + __IM uint32_t TSIM; /*!< (@ 0x00000700) Summarized Interrupt Mirroring Register */ + + struct + { + __IM uint32_t FIM : 1; /*!< [0..0] MFWD Interrupt Mirroring */ + __IM uint32_t CIM : 1; /*!< [1..1] COMA Interrupt Mirroring */ + __IM uint32_t GIM0 : 1; /*!< [2..2] GWCA0 Interrupt Monitoring */ + __IM uint32_t GIM1 : 1; /*!< [3..3] GWCA1 Interrupt Monitoring */ + __IM uint32_t EIM0 : 1; /*!< [4..4] ETHA0 Interrupt Monitoring */ + __IM uint32_t EIM1 : 1; /*!< [5..5] ETHA1 Interrupt Monitoring */ + __IM uint32_t EIM2 : 1; /*!< [6..6] ETHA2 Interrupt Monitoring */ + uint32_t : 25; + } TSIM_b; + }; + + union + { + __IM uint32_t TFIM; /*!< (@ 0x00000704) MFWD Interrupt Mirroring Register */ + + struct + { + __IM uint32_t FWEISIM0 : 1; /*!< [0..0] FWEIS0 Interrupt Mirroring */ + __IM uint32_t FWEISIM1 : 1; /*!< [1..1] FWEIS1 Interrupt Mirroring */ + __IM uint32_t FWEISIM2 : 1; /*!< [2..2] FWEIS2 Interrupt Mirroring */ + __IM uint32_t FWEISIM3 : 1; /*!< [3..3] FWEIS3 Interrupt Mirroring */ + __IM uint32_t FWEISIM4 : 1; /*!< [4..4] FWEIS4 Interrupt Mirroring */ + __IM uint32_t FWEISIM5 : 1; /*!< [5..5] FWEIS5 Interrupt Mirroring */ + __IM uint32_t FWEISIM6 : 1; /*!< [6..6] FWEIS6 Interrupt Mirroring */ + __IM uint32_t FWEISIM7 : 1; /*!< [7..7] FWEIS7 Interrupt Mirroring */ + __IM uint32_t FWEISIM8 : 1; /*!< [8..8] FWEIS8 Interrupt Mirroring */ + __IM uint32_t FWMISIM0 : 1; /*!< [9..9] FWMIS0 Interrupt Mirroring */ + uint32_t : 22; + } TFIM_b; + }; + + union + { + __IM uint32_t TCIM; /*!< (@ 0x00000708) COMA Interrupt Mirroring Register */ + + struct + { + __IM uint32_t RSSISIM : 1; /*!< [0..0] RSSIS Interrupt Mirroring */ + __IM uint32_t CAEISIM0 : 1; /*!< [1..1] CAEIS0 Interrupt Mirroring */ + __IM uint32_t CAEISIM1 : 1; /*!< [2..2] CAEIS1 Interrupt Mirroring */ + __IM uint32_t CAMISIM0 : 1; /*!< [3..3] CAMIS0 Interrupt Mirroring */ + __IM uint32_t CAMISIM1 : 1; /*!< [4..4] CAMIS1 Interrupt Mirroring */ + uint32_t : 27; + } TCIM_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IM uint32_t TGIM0; /*!< (@ 0x00000710) GWCA0 Interrupt Mirroring Register */ + + struct + { + __IM uint32_t GWDISIM : 1; /*!< [0..0] GWDIS Interrupt Mirroring */ + __IM uint32_t GWTSDISIM : 1; /*!< [1..1] GWTSDIS Interrupt Mirroring */ + __IM uint32_t GWEISIM0 : 1; /*!< [2..2] GWEIS0 Interrupt Mirroring */ + __IM uint32_t GWEISIM1 : 1; /*!< [3..3] GWEIS1 Interrupt Mirroring */ + __IM uint32_t GWEISIM2 : 1; /*!< [4..4] GWEIS2 Interrupt Mirroring */ + __IM uint32_t GWEISIM3 : 1; /*!< [5..5] GWEIS3 Interrupt Mirroring */ + __IM uint32_t GWEISIM4 : 1; /*!< [6..6] GWEIS4 Interrupt Mirroring */ + __IM uint32_t GWEISIM5 : 1; /*!< [7..7] GWEIS5 Interrupt Mirroring */ + uint32_t : 24; + } TGIM0_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IM uint32_t TEIM0; /*!< (@ 0x00000720) ETHA0 Interrupt Mirroring Register */ + + struct + { + __IM uint32_t EAEISIM0 : 1; /*!< [0..0] EAEIS0 Interrupt Mirroring */ + __IM uint32_t EAEISIM1 : 1; /*!< [1..1] EAEIS1 Interrupt Mirroring */ + __IM uint32_t EAEISIM2 : 1; /*!< [2..2] EAEIS2 Interrupt Mirroring */ + __IM uint32_t MEISIM : 1; /*!< [3..3] MEIS Interrupt Mirroring */ + __IM uint32_t MMISIM : 1; /*!< [4..4] MMIS0 Interrupt Mirroring */ + uint32_t : 27; + } TEIM0_b; + }; + + union + { + __IM uint32_t TEIM1; /*!< (@ 0x00000724) ETHA1 Interrupt Mirroring Register */ + + struct + { + __IM uint32_t EAEISIM0 : 1; /*!< [0..0] EAEIS0 Interrupt Mirroring */ + __IM uint32_t EAEISIM1 : 1; /*!< [1..1] EAEIS1 Interrupt Mirroring */ + __IM uint32_t EAEISIM2 : 1; /*!< [2..2] EAEIS2 Interrupt Mirroring */ + __IM uint32_t MEISIM : 1; /*!< [3..3] MEIS Interrupt Mirroring */ + __IM uint32_t MMISIM : 1; /*!< [4..4] MMIS0 Interrupt Mirroring */ + uint32_t : 27; + } TEIM1_b; + }; + __IM uint32_t RESERVED5[25398]; + + union + { + __IOM uint32_t MIIRR; /*!< (@ 0x00019400) Media Interface Reset Register */ + + struct + { + __IOM uint32_t RGRST0 : 1; /*!< [0..0] RGMII0 Interface Reset */ + __IOM uint32_t RGRST1 : 1; /*!< [1..1] RGMII1 Interface Reset */ + uint32_t : 6; + __IOM uint32_t RMRST0 : 1; /*!< [8..8] RMII0 Interface Reset */ + __IOM uint32_t RMRST1 : 1; /*!< [9..9] RMII1 Interface Reset */ + uint32_t : 22; + } MIIRR_b; + }; + + union + { + __IOM uint32_t MIICR0; /*!< (@ 0x00019404) Media Interface Control Register 0 */ + + struct + { + __IOM uint32_t MIISEL : 2; /*!< [1..0] MII Select */ + uint32_t : 6; + __IOM uint32_t DIVSTP : 1; /*!< [8..8] Clock Divider Stop */ + uint32_t : 3; + __IOM uint32_t TXCIDE : 1; /*!< [12..12] TXC Internal Delay Enable in RGMII */ + uint32_t : 19; + } MIICR0_b; + }; + + union + { + __IOM uint32_t MIICR1; /*!< (@ 0x00019408) Media Interface Control Register 1 */ + + struct + { + __IOM uint32_t MIISEL : 2; /*!< [1..0] MII Select */ + uint32_t : 6; + __IOM uint32_t DIVSTP : 1; /*!< [8..8] Clock Divider Stop */ + uint32_t : 3; + __IOM uint32_t TXCIDE : 1; /*!< [12..12] TXC Internal Delay Enable in RGMII */ + uint32_t : 19; + } MIICR1_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t MCCESR; /*!< (@ 0x00019410) Media Clock Capture Event Select Register */ + + struct + { + __IOM uint32_t MCCES0 : 1; /*!< [0..0] Media Clock Capture Event Select 0 */ + __IOM uint32_t MCCES1 : 1; /*!< [1..1] Media Clock Capture Event Select 1 */ + uint32_t : 30; + } MCCESR_b; + }; + __IM uint32_t RESERVED7[3]; + + union + { + __IOM uint32_t TASSTSR; /*!< (@ 0x00019420) TAS Status Monitor Signal Select Register */ + + struct + { + __IOM uint32_t MSS0 : 5; /*!< [4..0] Select signal to output ET_TAS_STA pin from race_etha0_tas_gate_state[8 + * 0] and race_etha1_tas_gate_state[8:0] */ + uint32_t : 3; + __IOM uint32_t MSS1 : 5; /*!< [12..8] Select signal to output ET_TAS_STA pin from race_etha0_tas_gate_state[ + * :0] and race_etha1_tas_gate_state[8:0] */ + uint32_t : 3; + __IOM uint32_t MSS2 : 5; /*!< [20..16] Select signal to output ET_TAS_STA pin from race_etha0_tas_gate_state + * 8:0] and race_etha1_tas_gate_state[8:0] */ + uint32_t : 3; + __IOM uint32_t MSS3 : 5; /*!< [28..24] Select signal to output ET_TAS_STA pin from race_etha0_tas_gate_state + * 8:0] and race_etha1_tas_gate_state[8:0] */ + uint32_t : 3; + } TASSTSR_b; + }; +} R_ESWM_Type; /*!< Size = 103460 (0x19424) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHA0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet Agent (R_ETHA0) + */ + +typedef struct /*!< (@ 0x403CA000) R_ETHA0 Structure */ +{ + union + { + __IOM uint32_t EAMC; /*!< (@ 0x00000000) Ethernet Agent Mode Configuration Register (EAMC) */ + + struct + { + __IOM uint32_t OPC : 2; /*!< [1..0] OPC */ + uint32_t : 30; + } EAMC_b; + }; + + union + { + __IOM uint32_t EAMS; /*!< (@ 0x00000004) Ethernet Agent Mode Status Register (EAMS) */ + + struct + { + __IOM uint32_t OPS : 2; /*!< [1..0] OPS */ + uint32_t : 30; + } EAMS_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t EAIRC; /*!< (@ 0x00000010) Ethernet Agent IPV Remapping Configuration Register + * [802.1Q] (EAIRC) */ + + struct + { + __IOM uint32_t IPVR0 : 3; /*!< [2..0] IPVR0 */ + uint32_t : 1; + __IOM uint32_t IPVR1 : 3; /*!< [6..4] IPVR1 */ + uint32_t : 1; + __IOM uint32_t IPVR2 : 3; /*!< [10..8] IPVR2 */ + uint32_t : 1; + __IOM uint32_t IPVR3 : 3; /*!< [14..12] IPVR3 */ + uint32_t : 1; + __IOM uint32_t IPVR4 : 3; /*!< [18..16] IPVR4 */ + uint32_t : 1; + __IOM uint32_t IPVR5 : 3; /*!< [22..20] IPVR5 */ + uint32_t : 1; + __IOM uint32_t IPVR6 : 3; /*!< [26..24] IPVR6 */ + uint32_t : 1; + __IOM uint32_t IPVR7 : 3; /*!< [30..28] IPVR7 */ + uint32_t : 1; + } EAIRC_b; + }; + + union + { + __IOM uint32_t EATDQSC; /*!< (@ 0x00000014) Ethernet Agent TX Descriptor Queue Security Configuration + * Register (EATDQSC) */ + + struct + { + __IOM uint32_t TDQSL0 : 1; /*!< [0..0] TDQSL0 */ + __IOM uint32_t TDQSL1 : 1; /*!< [1..1] TDQSL1 */ + __IOM uint32_t TDQSL2 : 1; /*!< [2..2] TDQSL2 */ + __IOM uint32_t TDQSL3 : 1; /*!< [3..3] TDQSL3 */ + __IOM uint32_t TDQSL4 : 1; /*!< [4..4] TDQSL4 */ + __IOM uint32_t TDQSL5 : 1; /*!< [5..5] TDQSL5 */ + __IOM uint32_t TDQSL6 : 1; /*!< [6..6] TDQSL6 */ + __IOM uint32_t TDQSL7 : 1; /*!< [7..7] TDQSL7 */ + uint32_t : 24; + } EATDQSC_b; + }; + + union + { + __IOM uint32_t EATDQC; /*!< (@ 0x00000018) Ethernet Agent TX Descriptor Queue Configuration + * Register (EATDQC) */ + + struct + { + __IOM uint32_t TDQD0 : 1; /*!< [0..0] TDQD0 */ + __IOM uint32_t TDQD1 : 1; /*!< [1..1] TDQD1 */ + __IOM uint32_t TDQD2 : 1; /*!< [2..2] TDQD2 */ + __IOM uint32_t TDQD3 : 1; /*!< [3..3] TDQD3 */ + __IOM uint32_t TDQD4 : 1; /*!< [4..4] TDQD4 */ + __IOM uint32_t TDQD5 : 1; /*!< [5..5] TDQD5 */ + __IOM uint32_t TDQD6 : 1; /*!< [6..6] TDQD6 */ + __IOM uint32_t TDQD7 : 1; /*!< [7..7] TDQD7 */ + __IOM uint32_t TCTDQD : 1; /*!< [8..8] TCTDQD */ + uint32_t : 7; + __IOM uint32_t TDQP0 : 1; /*!< [16..16] TDQP0 */ + __IOM uint32_t TDQP1 : 1; /*!< [17..17] TDQP1 */ + __IOM uint32_t TDQP2 : 1; /*!< [18..18] TDQP2 */ + __IOM uint32_t TDQP3 : 1; /*!< [19..19] TDQP3 */ + __IOM uint32_t TDQP4 : 1; /*!< [20..20] TDQP4 */ + __IOM uint32_t TDQP5 : 1; /*!< [21..21] TDQP5 */ + __IOM uint32_t TDQP6 : 1; /*!< [22..22] TDQP6 */ + __IOM uint32_t TDQP7 : 1; /*!< [23..23] TDQP7 */ + uint32_t : 8; + } EATDQC_b; + }; + + union + { + __IOM uint32_t EATDQAC; /*!< (@ 0x0000001C) Ethernet Agent TX Descriptor Queue Arbitration + * Configuration Register (EATDQAC) */ + + struct + { + __IOM uint32_t TDQA0 : 4; /*!< [3..0] TDQA0 */ + __IOM uint32_t TDQA1 : 4; /*!< [7..4] TDQA1 */ + __IOM uint32_t TDQA2 : 4; /*!< [11..8] TDQA2 */ + __IOM uint32_t TDQA3 : 4; /*!< [15..12] TDQA3 */ + __IOM uint32_t TDQA4 : 4; /*!< [19..16] TDQA4 */ + __IOM uint32_t TDQA5 : 4; /*!< [23..20] TDQA5 */ + __IOM uint32_t TDQA6 : 4; /*!< [27..24] TDQA6 */ + __IOM uint32_t TDQA7 : 4; /*!< [31..28] TDQA7 */ + } EATDQAC_b; + }; + + union + { + __IOM uint32_t EATPEC; /*!< (@ 0x00000020) Ethernet Agent TX Pre-Emption Configuration Register + * (EATPEC) */ + + struct + { + __IOM uint32_t TTQ0 : 1; /*!< [0..0] TTQ0 */ + __IOM uint32_t TTQ1 : 1; /*!< [1..1] TTQ1 */ + __IOM uint32_t TTQ2 : 1; /*!< [2..2] TTQ2 */ + __IOM uint32_t TTQ3 : 1; /*!< [3..3] TTQ3 */ + __IOM uint32_t TTQ4 : 1; /*!< [4..4] TTQ4 */ + __IOM uint32_t TTQ5 : 1; /*!< [5..5] TTQ5 */ + __IOM uint32_t TTQ6 : 1; /*!< [6..6] TTQ6 */ + __IOM uint32_t TTQ7 : 1; /*!< [7..7] TTQ7 */ + __IOM uint32_t TTQ8 : 1; /*!< [8..8] TTQ8 */ + __IOM uint32_t TTQ9 : 1; /*!< [9..9] TTQ9 */ + uint32_t : 6; + __IOM uint32_t AFS : 2; /*!< [17..16] AFS */ + uint32_t : 14; + } EATPEC_b; + }; + __IM uint32_t RESERVED1[7]; + + union + { + __IOM uint32_t EATMFSC0; /*!< (@ 0x00000040) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC0_b; + }; + + union + { + __IOM uint32_t EATMFSC1; /*!< (@ 0x00000044) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC1_b; + }; + + union + { + __IOM uint32_t EATMFSC2; /*!< (@ 0x00000048) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC2_b; + }; + + union + { + __IOM uint32_t EATMFSC3; /*!< (@ 0x0000004C) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC3_b; + }; + + union + { + __IOM uint32_t EATMFSC4; /*!< (@ 0x00000050) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC4_b; + }; + + union + { + __IOM uint32_t EATMFSC5; /*!< (@ 0x00000054) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC5_b; + }; + + union + { + __IOM uint32_t EATMFSC6; /*!< (@ 0x00000058) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC6_b; + }; + + union + { + __IOM uint32_t EATMFSC7; /*!< (@ 0x0000005C) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC7_b; + }; + + union + { + __IOM uint32_t EATDQDC0; /*!< (@ 0x00000060) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC0_b; + }; + + union + { + __IOM uint32_t EATDQDC1; /*!< (@ 0x00000064) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC1_b; + }; + + union + { + __IOM uint32_t EATDQDC2; /*!< (@ 0x00000068) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC2_b; + }; + + union + { + __IOM uint32_t EATDQDC3; /*!< (@ 0x0000006C) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC3_b; + }; + + union + { + __IOM uint32_t EATDQDC4; /*!< (@ 0x00000070) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC4_b; + }; + + union + { + __IOM uint32_t EATDQDC5; /*!< (@ 0x00000074) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC5_b; + }; + + union + { + __IOM uint32_t EATDQDC6; /*!< (@ 0x00000078) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC6_b; + }; + + union + { + __IOM uint32_t EATDQDC7; /*!< (@ 0x0000007C) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC7_b; + }; + + union + { + __IOM uint32_t EATDQM0; /*!< (@ 0x00000080) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM0_b; + }; + + union + { + __IOM uint32_t EATDQM1; /*!< (@ 0x00000084) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM1_b; + }; + + union + { + __IOM uint32_t EATDQM2; /*!< (@ 0x00000088) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM2_b; + }; + + union + { + __IOM uint32_t EATDQM3; /*!< (@ 0x0000008C) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM3_b; + }; + + union + { + __IOM uint32_t EATDQM4; /*!< (@ 0x00000090) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM4_b; + }; + + union + { + __IOM uint32_t EATDQM5; /*!< (@ 0x00000094) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM5_b; + }; + + union + { + __IOM uint32_t EATDQM6; /*!< (@ 0x00000098) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM6_b; + }; + + union + { + __IOM uint32_t EATDQM7; /*!< (@ 0x0000009C) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM7_b; + }; + + union + { + __IOM uint32_t EATDQMLM0; /*!< (@ 0x000000A0) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM0_b; + }; + + union + { + __IOM uint32_t EATDQMLM1; /*!< (@ 0x000000A4) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM1_b; + }; + + union + { + __IOM uint32_t EATDQMLM2; /*!< (@ 0x000000A8) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM2_b; + }; + + union + { + __IOM uint32_t EATDQMLM3; /*!< (@ 0x000000AC) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM3_b; + }; + + union + { + __IOM uint32_t EATDQMLM4; /*!< (@ 0x000000B0) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM4_b; + }; + + union + { + __IOM uint32_t EATDQMLM5; /*!< (@ 0x000000B4) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM5_b; + }; + + union + { + __IOM uint32_t EATDQMLM6; /*!< (@ 0x000000B8) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM6_b; + }; + + union + { + __IOM uint32_t EATDQMLM7; /*!< (@ 0x000000BC) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM7_b; + }; + __IM uint32_t RESERVED2[16]; + + union + { + __IOM uint32_t EACTQC; /*!< (@ 0x00000100) Ethernet Agent Cut-Through Queue Configuration + * Register (EACTQC) */ + + struct + { + __IOM uint32_t CTQD : 16; /*!< [15..0] CTQD */ + uint32_t : 16; + } EACTQC_b; + }; + + union + { + __IOM uint32_t EACTDQDC; /*!< (@ 0x00000104) Ethernet Agent Cut-Through Descriptor Queue Depth + * Configuration Register (EACTDQDC) */ + + struct + { + __IOM uint32_t CTDQD : 4; /*!< [3..0] CTDQD */ + uint32_t : 28; + } EACTDQDC_b; + }; + + union + { + __IOM uint32_t EACTDQM; /*!< (@ 0x00000108) Ethernet Agent Cut-Through Descriptor Queue Monitoring + * Register (EACTDQM) */ + + struct + { + __IOM uint32_t CTQDN : 10; /*!< [9..0] CTQDN */ + uint32_t : 22; + } EACTDQM_b; + }; + + union + { + __IOM uint32_t EACTDQMLM; /*!< (@ 0x0000010C) Ethernet Agent Cut-Through Descriptor Queue Max + * Level Monitoring Register (EACTDQMLM) */ + + struct + { + __IOM uint32_t CTDMLQ : 4; /*!< [3..0] CTDMLQ */ + uint32_t : 28; + } EACTDQMLM_b; + }; + __IM uint32_t RESERVED3[8]; + + union + { + __IOM uint32_t EAVCC; /*!< (@ 0x00000130) Ethernet Agent VLAN Control Configuration Register + * (EAVCC) */ + + struct + { + __IOM uint32_t VIM : 1; /*!< [0..0] VIM */ + uint32_t : 15; + __IOM uint32_t VEM : 3; /*!< [18..16] VEM */ + uint32_t : 13; + } EAVCC_b; + }; + + union + { + __IOM uint32_t EAVTC; /*!< (@ 0x00000134) Ethernet Agent VLAN TAG Configuration Register + * (EAVTC) */ + + struct + { + __IOM uint32_t CTV : 12; /*!< [11..0] CTV */ + __IOM uint32_t CTP : 3; /*!< [14..12] CTP */ + __IOM uint32_t CTD : 1; /*!< [15..15] CTD */ + __IOM uint32_t STV : 12; /*!< [27..16] STV */ + __IOM uint32_t STP : 3; /*!< [30..28] STP */ + __IOM uint32_t STD : 1; /*!< [31..31] STD */ + } EAVTC_b; + }; + + union + { + __IOM uint32_t EARTFC; /*!< (@ 0x00000138) Ethernet Agent Reception TAG Filtering Configuration + * Register (EARTFC) */ + + struct + { + __IOM uint32_t NT : 1; /*!< [0..0] NT */ + __IOM uint32_t RT : 1; /*!< [1..1] RT */ + __IOM uint32_t CST : 1; /*!< [2..2] CST */ + __IOM uint32_t CSRT : 1; /*!< [3..3] CSRT */ + __IOM uint32_t CT : 1; /*!< [4..4] CT */ + __IOM uint32_t CRT : 1; /*!< [5..5] CRT */ + __IOM uint32_t SCT : 1; /*!< [6..6] SCT */ + __IOM uint32_t SCRT : 1; /*!< [7..7] SCRT */ + __IOM uint32_t UT : 1; /*!< [8..8] UT */ + uint32_t : 23; + } EARTFC_b; + }; + __IM uint32_t RESERVED4[49]; + + union + { + __IOM uint32_t EACAEC; /*!< (@ 0x00000200) Ethernet Agent CBS Admin Enable Configuration + * Register (EACAEC) */ + + struct + { + __IOM uint32_t CE0 : 1; /*!< [0..0] CE0 */ + __IOM uint32_t CE1 : 1; /*!< [1..1] CE1 */ + __IOM uint32_t CE2 : 1; /*!< [2..2] CE2 */ + __IOM uint32_t CE3 : 1; /*!< [3..3] CE3 */ + __IOM uint32_t CE4 : 1; /*!< [4..4] CE4 */ + __IOM uint32_t CE5 : 1; /*!< [5..5] CE5 */ + __IOM uint32_t CE6 : 1; /*!< [6..6] CE6 */ + __IOM uint32_t CE7 : 1; /*!< [7..7] CE7 */ + uint32_t : 24; + } EACAEC_b; + }; + + union + { + __IOM uint32_t EACC; /*!< (@ 0x00000204) Ethernet Agent CBS Configuration Register (EACC) */ + + struct + { + __IOM uint32_t CC0 : 1; /*!< [0..0] CC0 */ + __IOM uint32_t CC1 : 1; /*!< [1..1] CC1 */ + __IOM uint32_t CC2 : 1; /*!< [2..2] CC2 */ + __IOM uint32_t CC3 : 1; /*!< [3..3] CC3 */ + __IOM uint32_t CC4 : 1; /*!< [4..4] CC4 */ + __IOM uint32_t CC5 : 1; /*!< [5..5] CC5 */ + __IOM uint32_t CC6 : 1; /*!< [6..6] CC6 */ + __IOM uint32_t CC7 : 1; /*!< [7..7] CC7 */ + uint32_t : 24; + } EACC_b; + }; + __IM uint32_t RESERVED5[6]; + + union + { + __IOM uint32_t EACAIVC0; /*!< (@ 0x00000220) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC0_b; + }; + + union + { + __IOM uint32_t EACAIVC1; /*!< (@ 0x00000224) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC1_b; + }; + + union + { + __IOM uint32_t EACAIVC2; /*!< (@ 0x00000228) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC2_b; + }; + + union + { + __IOM uint32_t EACAIVC3; /*!< (@ 0x0000022C) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC3_b; + }; + + union + { + __IOM uint32_t EACAIVC4; /*!< (@ 0x00000230) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC4_b; + }; + + union + { + __IOM uint32_t EACAIVC5; /*!< (@ 0x00000234) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC5_b; + }; + + union + { + __IOM uint32_t EACAIVC6; /*!< (@ 0x00000238) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC6_b; + }; + + union + { + __IOM uint32_t EACAIVC7; /*!< (@ 0x0000023C) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC7_b; + }; + + union + { + __IOM uint32_t EACAULC0; /*!< (@ 0x00000240) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC0_b; + }; + + union + { + __IOM uint32_t EACAULC1; /*!< (@ 0x00000244) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC1_b; + }; + + union + { + __IOM uint32_t EACAULC2; /*!< (@ 0x00000248) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC2_b; + }; + + union + { + __IOM uint32_t EACAULC3; /*!< (@ 0x0000024C) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC3_b; + }; + + union + { + __IOM uint32_t EACAULC4; /*!< (@ 0x00000250) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC4_b; + }; + + union + { + __IOM uint32_t EACAULC5; /*!< (@ 0x00000254) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC5_b; + }; + + union + { + __IOM uint32_t EACAULC6; /*!< (@ 0x00000258) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC6_b; + }; + + union + { + __IOM uint32_t EACAULC7; /*!< (@ 0x0000025C) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC7_b; + }; + + union + { + __IOM uint32_t EACOEM; /*!< (@ 0x00000260) Ethernet Agent CBS Oper Enable Monitoring Register + * (EACOEM) */ + + struct + { + __IOM uint32_t CE0 : 1; /*!< [0..0] CE0 */ + __IOM uint32_t CE1 : 1; /*!< [1..1] CE1 */ + __IOM uint32_t CE2 : 1; /*!< [2..2] CE2 */ + __IOM uint32_t CE3 : 1; /*!< [3..3] CE3 */ + __IOM uint32_t CE4 : 1; /*!< [4..4] CE4 */ + __IOM uint32_t CE5 : 1; /*!< [5..5] CE5 */ + __IOM uint32_t CE6 : 1; /*!< [6..6] CE6 */ + __IOM uint32_t CE7 : 1; /*!< [7..7] CE7 */ + uint32_t : 24; + } EACOEM_b; + }; + __IM uint32_t RESERVED6[7]; + + union + { + __IOM uint32_t EACOIVM0; /*!< (@ 0x00000280) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM0_b; + }; + + union + { + __IOM uint32_t EACOIVM1; /*!< (@ 0x00000284) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM1_b; + }; + + union + { + __IOM uint32_t EACOIVM2; /*!< (@ 0x00000288) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM2_b; + }; + + union + { + __IOM uint32_t EACOIVM3; /*!< (@ 0x0000028C) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM3_b; + }; + + union + { + __IOM uint32_t EACOIVM4; /*!< (@ 0x00000290) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM4_b; + }; + + union + { + __IOM uint32_t EACOIVM5; /*!< (@ 0x00000294) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM5_b; + }; + + union + { + __IOM uint32_t EACOIVM6; /*!< (@ 0x00000298) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM6_b; + }; + + union + { + __IOM uint32_t EACOIVM7; /*!< (@ 0x0000029C) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM7_b; + }; + + union + { + __IOM uint32_t EACOULM0; /*!< (@ 0x000002A0) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM0_b; + }; + + union + { + __IOM uint32_t EACOULM1; /*!< (@ 0x000002A4) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM1_b; + }; + + union + { + __IOM uint32_t EACOULM2; /*!< (@ 0x000002A8) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM2_b; + }; + + union + { + __IOM uint32_t EACOULM3; /*!< (@ 0x000002AC) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM3_b; + }; + + union + { + __IOM uint32_t EACOULM4; /*!< (@ 0x000002B0) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM4_b; + }; + + union + { + __IOM uint32_t EACOULM5; /*!< (@ 0x000002B4) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM5_b; + }; + + union + { + __IOM uint32_t EACOULM6; /*!< (@ 0x000002B8) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM6_b; + }; + + union + { + __IOM uint32_t EACOULM7; /*!< (@ 0x000002BC) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM7_b; + }; + + union + { + __IOM uint32_t EACGSM; /*!< (@ 0x000002C0) Ethernet Agent CBS Gate State Monitoring Register + * (EACGSM) */ + + struct + { + __IOM uint32_t CGS0 : 1; /*!< [0..0] CGS0 */ + __IOM uint32_t CGS1 : 1; /*!< [1..1] CGS1 */ + __IOM uint32_t CGS2 : 1; /*!< [2..2] CGS2 */ + __IOM uint32_t CGS3 : 1; /*!< [3..3] CGS3 */ + __IOM uint32_t CGS4 : 1; /*!< [4..4] CGS4 */ + __IOM uint32_t CGS5 : 1; /*!< [5..5] CGS5 */ + __IOM uint32_t CGS6 : 1; /*!< [6..6] CGS6 */ + __IOM uint32_t CGS7 : 1; /*!< [7..7] CGS7 */ + uint32_t : 24; + } EACGSM_b; + }; + __IM uint32_t RESERVED7[15]; + + union + { + __IOM uint32_t EATASC; /*!< (@ 0x00000300) Ethernet Agent TAS Configuration Register (EATASC) */ + + struct + { + __IOM uint32_t TASE : 1; /*!< [0..0] TASE */ + __IOM uint32_t TASCC : 1; /*!< [1..1] TASCC */ + __IOM uint32_t TASCI : 1; /*!< [2..2] TASCI */ + uint32_t : 5; + __IOM uint32_t TASTS : 1; /*!< [8..8] TASTS */ + uint32_t : 7; + __IOM uint32_t TASCA : 8; /*!< [23..16] TASCA */ + uint32_t : 8; + } EATASC_b; + }; + + union + { + __IOM uint32_t EATASIGSC; /*!< (@ 0x00000304) Ethernet Agent TAS Initial Gate State Configuration + * Register (EATASIGSC) */ + + struct + { + __IOM uint32_t TASIGS0 : 1; /*!< [0..0] TASIGS0 */ + __IOM uint32_t TASIGS1 : 1; /*!< [1..1] TASIGS1 */ + __IOM uint32_t TASIGS2 : 1; /*!< [2..2] TASIGS2 */ + __IOM uint32_t TASIGS3 : 1; /*!< [3..3] TASIGS3 */ + __IOM uint32_t TASIGS4 : 1; /*!< [4..4] TASIGS4 */ + __IOM uint32_t TASIGS5 : 1; /*!< [5..5] TASIGS5 */ + __IOM uint32_t TASIGS6 : 1; /*!< [6..6] TASIGS6 */ + __IOM uint32_t TASIGS7 : 1; /*!< [7..7] TASIGS7 */ + __IOM uint32_t TASCTIGS : 1; /*!< [8..8] TASCTIGS */ + uint32_t : 23; + } EATASIGSC_b; + }; + __IM uint32_t RESERVED8[6]; + + union + { + __IOM uint32_t EATASENC0; /*!< (@ 0x00000320) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC0_b; + }; + + union + { + __IOM uint32_t EATASENC1; /*!< (@ 0x00000324) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC1_b; + }; + + union + { + __IOM uint32_t EATASENC2; /*!< (@ 0x00000328) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC2_b; + }; + + union + { + __IOM uint32_t EATASENC3; /*!< (@ 0x0000032C) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC3_b; + }; + + union + { + __IOM uint32_t EATASENC4; /*!< (@ 0x00000330) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC4_b; + }; + + union + { + __IOM uint32_t EATASENC5; /*!< (@ 0x00000334) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC5_b; + }; + + union + { + __IOM uint32_t EATASENC6; /*!< (@ 0x00000338) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC6_b; + }; + + union + { + __IOM uint32_t EATASENC7; /*!< (@ 0x0000033C) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC7_b; + }; + + union + { + __IOM uint32_t EATASCTENC; /*!< (@ 0x00000340) Ethernet Agent TAS Cut-Through Entry Number Configuration + * Register (EATASCTENC) */ + + struct + { + __IOM uint32_t TASCTAEN : 9; /*!< [8..0] TASCTAEN */ + uint32_t : 23; + } EATASCTENC_b; + }; + __IM uint32_t RESERVED9[7]; + + union + { + __IOM uint32_t EATASENM0; /*!< (@ 0x00000360) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM0_b; + }; + + union + { + __IOM uint32_t EATASENM1; /*!< (@ 0x00000364) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM1_b; + }; + + union + { + __IOM uint32_t EATASENM2; /*!< (@ 0x00000368) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM2_b; + }; + + union + { + __IOM uint32_t EATASENM3; /*!< (@ 0x0000036C) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM3_b; + }; + + union + { + __IOM uint32_t EATASENM4; /*!< (@ 0x00000370) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM4_b; + }; + + union + { + __IOM uint32_t EATASENM5; /*!< (@ 0x00000374) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM5_b; + }; + + union + { + __IOM uint32_t EATASENM6; /*!< (@ 0x00000378) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM6_b; + }; + + union + { + __IOM uint32_t EATASENM7; /*!< (@ 0x0000037C) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM7_b; + }; + + union + { + __IOM uint32_t EATASCTENM; /*!< (@ 0x00000380) Ethernet Agent TAS Cut-Through Entry Number Monitoring + * Register (EATASCTENM) */ + + struct + { + __IOM uint32_t TASCTOEN : 9; /*!< [8..0] TASCTOEN */ + uint32_t : 23; + } EATASCTENM_b; + }; + __IM uint32_t RESERVED10[7]; + + union + { + __IOM uint32_t EATASCSTC0; /*!< (@ 0x000003A0) Ethernet Agent TAS Cycle Start Time Configuration + * Register 0 (EATASCSTC0) */ + + struct + { + __IOM uint32_t TASACSTP0 : 32; /*!< [31..0] TASACSTP0 */ + } EATASCSTC0_b; + }; + + union + { + __IOM uint32_t EATASCSTC1; /*!< (@ 0x000003A4) Ethernet Agent TAS Cycle Start Time Configuration + * Register 1 (EATASCSTC1) */ + + struct + { + __IOM uint32_t TASACSTP1 : 32; /*!< [31..0] TASACSTP1 */ + } EATASCSTC1_b; + }; + + union + { + __IOM uint32_t EATASCSTM0; /*!< (@ 0x000003A8) Ethernet Agent TAS Cycle Start Time Monitoring + * Register 0 (EATASCSTM0) */ + + struct + { + __IOM uint32_t TASOCSTP0 : 32; /*!< [31..0] TASOCSTP0 */ + } EATASCSTM0_b; + }; + + union + { + __IOM uint32_t EATASCSTM1; /*!< (@ 0x000003AC) Ethernet Agent TAS Cycle Start Time Monitoring + * Register 1 (EATASCSTM1) */ + + struct + { + __IOM uint32_t TASOCSTP1 : 32; /*!< [31..0] TASOCSTP1 */ + } EATASCSTM1_b; + }; + + union + { + __IOM uint32_t EATASCTC; /*!< (@ 0x000003B0) Ethernet Agent TAS Cycle Time Configuration Register + * (EATASCTC) */ + + struct + { + __IOM uint32_t TASACT : 32; /*!< [31..0] TASACT */ + } EATASCTC_b; + }; + + union + { + __IOM uint32_t EATASCTM; /*!< (@ 0x000003B4) Ethernet Agent TAS Cycle Time Monitoring Register + * (EATASCTM) */ + + struct + { + __IOM uint32_t TASOCT : 32; /*!< [31..0] TASOCT */ + } EATASCTM_b; + }; + __IM uint32_t RESERVED11[2]; + + union + { + __IOM uint32_t EATASGL0; /*!< (@ 0x000003C0) Ethernet Agent TAS Gate Learn Register 0 (EATASGL0) */ + + struct + { + __IOM uint32_t TASGAL : 8; /*!< [7..0] TASGAL */ + uint32_t : 24; + } EATASGL0_b; + }; + + union + { + __IOM uint32_t EATASGL1; /*!< (@ 0x000003C4) Ethernet Agent TAS Gate Learn Register 1 (EATASGL1) */ + + struct + { + __IOM uint32_t TASGTL : 28; /*!< [27..0] TASGTL */ + __IOM uint32_t TASGSL : 1; /*!< [28..28] TASGSL */ + uint32_t : 3; + } EATASGL1_b; + }; + + union + { + __IOM uint32_t EATASGLR; /*!< (@ 0x000003C8) Ethernet Agent TAS Gate Learn Result Register + * (EATASGLR) */ + + struct + { + uint32_t : 31; + __IOM uint32_t GL : 1; /*!< [31..31] GL */ + } EATASGLR_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t EATASGR; /*!< (@ 0x000003D0) Ethernet Agent TAS Gate Read Register (EATASGR) */ + + struct + { + __IOM uint32_t TASGAR : 8; /*!< [7..0] TASGAR */ + uint32_t : 24; + } EATASGR_b; + }; + + union + { + __IOM uint32_t EATASGRR; /*!< (@ 0x000003D4) Ethernet Agent TAS Gate Read Result Register + * (EATASGRR) */ + + struct + { + __IOM uint32_t TASGTR : 28; /*!< [27..0] TASGTR */ + __IOM uint32_t TASGSR : 1; /*!< [28..28] TASGSR */ + __IOM uint32_t TASREF : 1; /*!< [29..29] TASREF */ + uint32_t : 1; + __IOM uint32_t GR : 1; /*!< [31..31] GR */ + } EATASGRR_b; + }; + __IM uint32_t RESERVED13[2]; + + union + { + __IOM uint32_t EATASHCC; /*!< (@ 0x000003E0) Ethernet Agent TAS Hardware Calibration Configuration + * Register (EATASHCC) */ + + struct + { + __IOM uint32_t TASJ : 16; /*!< [15..0] TASJ */ + uint32_t : 16; + } EATASHCC_b; + }; + + union + { + __IOM uint32_t EATASRIRM; /*!< (@ 0x000003E4) Ethernet Agent TAS RAM Initialization Register + * Monitoring Register (EATASRIRM) */ + + struct + { + __IOM uint32_t TASRIOG : 1; /*!< [0..0] TASRIOG */ + __IOM uint32_t TASRR : 1; /*!< [1..1] TASRR */ + uint32_t : 30; + } EATASRIRM_b; + }; + + union + { + __IOM uint32_t EATASSM; /*!< (@ 0x000003E8) Ethernet Agent TAS Status Monitoring Register + * (EATASSM) */ + + struct + { + __IOM uint32_t TASGS0 : 1; /*!< [0..0] TASGS0 */ + __IOM uint32_t TASGS1 : 1; /*!< [1..1] TASGS1 */ + __IOM uint32_t TASGS2 : 1; /*!< [2..2] TASGS2 */ + __IOM uint32_t TASGS3 : 1; /*!< [3..3] TASGS3 */ + __IOM uint32_t TASGS4 : 1; /*!< [4..4] TASGS4 */ + __IOM uint32_t TASGS5 : 1; /*!< [5..5] TASGS5 */ + __IOM uint32_t TASGS6 : 1; /*!< [6..6] TASGS6 */ + __IOM uint32_t TASGS7 : 1; /*!< [7..7] TASGS7 */ + __IOM uint32_t TASCTGS : 1; /*!< [8..8] TASCTGS */ + uint32_t : 7; + __IOM uint32_t TASSO : 1; /*!< [16..16] TASSO */ + uint32_t : 15; + } EATASSM_b; + }; + __IM uint32_t RESERVED14[5]; + + union + { + __IOM uint32_t EAUSMFSECN; /*!< (@ 0x00000400) Ethernet Agent Switch Minimum Frame Size Error + * Counter Register (EAUSMFSECN) */ + + struct + { + __IOM uint32_t USMFSEN : 16; /*!< [15..0] USMFSEN */ + uint32_t : 16; + } EAUSMFSECN_b; + }; + + union + { + __IOM uint32_t EATFECN; /*!< (@ 0x00000404) Ethernet Agent TAG Filtering Error Counter Register + * (EATFECN) */ + + struct + { + __IOM uint32_t TFEN : 16; /*!< [15..0] TFEN */ + uint32_t : 16; + } EATFECN_b; + }; + + union + { + __IOM uint32_t EAFSECN; /*!< (@ 0x00000408) Ethernet Agent Frame Size Error Counter Register + * (EAFSECN) */ + + struct + { + __IOM uint32_t FSEN : 16; /*!< [15..0] FSEN */ + uint32_t : 16; + } EAFSECN_b; + }; + + union + { + __IOM uint32_t EADQOECN; /*!< (@ 0x0000040C) Ethernet Agent Descriptor Queue Overflow Error + * Counter Register (EADQOECN) */ + + struct + { + __IOM uint32_t DQOEN : 16; /*!< [15..0] DQOEN */ + uint32_t : 16; + } EADQOECN_b; + }; + + union + { + __IOM uint32_t EADQSECN; /*!< (@ 0x00000410) Ethernet Agent Descriptor Queue Security Error + * Counter Register (EADQSECN) */ + + struct + { + __IOM uint32_t DQSEN : 16; /*!< [15..0] DQSEN */ + uint32_t : 16; + } EADQSECN_b; + }; + __IM uint32_t RESERVED15[59]; + + union + { + __IOM uint32_t EAEIS0; /*!< (@ 0x00000500) Ethernet Agent Error Interrupt Status Register + * 0 (EAEIS0) */ + + struct + { + __IOM uint32_t DECCES : 1; /*!< [0..0] DECCES */ + __IOM uint32_t TECCES : 1; /*!< [1..1] TECCES */ + __IOM uint32_t PECCES : 1; /*!< [2..2] PECCES */ + __IOM uint32_t DSECCES : 1; /*!< [3..3] DSECCES */ + __IOM uint32_t L23UECCES : 1; /*!< [4..4] L23UECCES */ + __IOM uint32_t USMFSES : 1; /*!< [5..5] USMFSES */ + __IOM uint32_t TFES : 1; /*!< [6..6] TFES */ + uint32_t : 1; + __IOM uint32_t FSES0 : 1; /*!< [8..8] FSES0 */ + __IOM uint32_t FSES1 : 1; /*!< [9..9] FSES1 */ + __IOM uint32_t FSES2 : 1; /*!< [10..10] FSES2 */ + __IOM uint32_t FSES3 : 1; /*!< [11..11] FSES3 */ + __IOM uint32_t FSES4 : 1; /*!< [12..12] FSES4 */ + __IOM uint32_t FSES5 : 1; /*!< [13..13] FSES5 */ + __IOM uint32_t FSES6 : 1; /*!< [14..14] FSES6 */ + __IOM uint32_t FSES7 : 1; /*!< [15..15] FSES7 */ + __IOM uint32_t TASGEES0 : 1; /*!< [16..16] TASGEES0 */ + __IOM uint32_t TASGEES1 : 1; /*!< [17..17] TASGEES1 */ + __IOM uint32_t TASGEES2 : 1; /*!< [18..18] TASGEES2 */ + __IOM uint32_t TASGEES3 : 1; /*!< [19..19] TASGEES3 */ + __IOM uint32_t TASGEES4 : 1; /*!< [20..20] TASGEES4 */ + __IOM uint32_t TASGEES5 : 1; /*!< [21..21] TASGEES5 */ + __IOM uint32_t TASGEES6 : 1; /*!< [22..22] TASGEES6 */ + __IOM uint32_t TASGEES7 : 1; /*!< [23..23] TASGEES7 */ + __IOM uint32_t TASCTGEES : 1; /*!< [24..24] TASCTGEES */ + uint32_t : 7; + } EAEIS0_b; + }; + + union + { + __IOM uint32_t EAEIE0; /*!< (@ 0x00000504) Ethernet Agent Error Interrupt Enable Register + * 0 (EAEIE0) */ + + struct + { + __IOM uint32_t DECCEE : 1; /*!< [0..0] DECCEE */ + __IOM uint32_t TECCEE : 1; /*!< [1..1] TECCEE */ + __IOM uint32_t PECCEE : 1; /*!< [2..2] PECCEE */ + __IOM uint32_t DSECCEE : 1; /*!< [3..3] DSECCEE */ + __IOM uint32_t L23UECCEE : 1; /*!< [4..4] L23UECCEE */ + __IOM uint32_t USMFSEE : 1; /*!< [5..5] USMFSEE */ + __IOM uint32_t TFEE : 1; /*!< [6..6] TFEE */ + uint32_t : 1; + __IOM uint32_t FSEE0 : 1; /*!< [8..8] FSEE0 */ + __IOM uint32_t FSEE1 : 1; /*!< [9..9] FSEE1 */ + __IOM uint32_t FSEE2 : 1; /*!< [10..10] FSEE2 */ + __IOM uint32_t FSEE3 : 1; /*!< [11..11] FSEE3 */ + __IOM uint32_t FSEE4 : 1; /*!< [12..12] FSEE4 */ + __IOM uint32_t FSEE5 : 1; /*!< [13..13] FSEE5 */ + __IOM uint32_t FSEE6 : 1; /*!< [14..14] FSEE6 */ + __IOM uint32_t FSEE7 : 1; /*!< [15..15] FSEE7 */ + __IOM uint32_t TASGEEE0 : 1; /*!< [16..16] TASGEEE0 */ + __IOM uint32_t TASGEEE1 : 1; /*!< [17..17] TASGEEE1 */ + __IOM uint32_t TASGEEE2 : 1; /*!< [18..18] TASGEEE2 */ + __IOM uint32_t TASGEEE3 : 1; /*!< [19..19] TASGEEE3 */ + __IOM uint32_t TASGEEE4 : 1; /*!< [20..20] TASGEEE4 */ + __IOM uint32_t TASGEEE5 : 1; /*!< [21..21] TASGEEE5 */ + __IOM uint32_t TASGEEE6 : 1; /*!< [22..22] TASGEEE6 */ + __IOM uint32_t TASGEEE7 : 1; /*!< [23..23] TASGEEE7 */ + __IOM uint32_t TASCTGEEE : 1; /*!< [24..24] TASCTGEEE */ + uint32_t : 7; + } EAEIE0_b; + }; + + union + { + __IOM uint32_t EAEID0; /*!< (@ 0x00000508) Ethernet Agent Error Interrupt Disable Register + * 0 (EAEID0) */ + + struct + { + __IOM uint32_t DECCED : 1; /*!< [0..0] DECCED */ + __IOM uint32_t TECCED : 1; /*!< [1..1] TECCED */ + __IOM uint32_t PECCED : 1; /*!< [2..2] PECCED */ + __IOM uint32_t DSECCED : 1; /*!< [3..3] DSECCED */ + __IOM uint32_t L23UECCED : 1; /*!< [4..4] L23UECCED */ + __IOM uint32_t USMFSED : 1; /*!< [5..5] USMFSED */ + __IOM uint32_t TFED : 1; /*!< [6..6] TFED */ + uint32_t : 1; + __IOM uint32_t FSED0 : 1; /*!< [8..8] FSED0 */ + __IOM uint32_t FSED1 : 1; /*!< [9..9] FSED1 */ + __IOM uint32_t FSED2 : 1; /*!< [10..10] FSED2 */ + __IOM uint32_t FSED3 : 1; /*!< [11..11] FSED3 */ + __IOM uint32_t FSED4 : 1; /*!< [12..12] FSED4 */ + __IOM uint32_t FSED5 : 1; /*!< [13..13] FSED5 */ + __IOM uint32_t FSED6 : 1; /*!< [14..14] FSED6 */ + __IOM uint32_t FSED7 : 1; /*!< [15..15] FSED7 */ + __IOM uint32_t TASGEED0 : 1; /*!< [16..16] TASGEED0 */ + __IOM uint32_t TASGEED1 : 1; /*!< [17..17] TASGEED1 */ + __IOM uint32_t TASGEED2 : 1; /*!< [18..18] TASGEED2 */ + __IOM uint32_t TASGEED3 : 1; /*!< [19..19] TASGEED3 */ + __IOM uint32_t TASGEED4 : 1; /*!< [20..20] TASGEED4 */ + __IOM uint32_t TASGEED5 : 1; /*!< [21..21] TASGEED5 */ + __IOM uint32_t TASGEED6 : 1; /*!< [22..22] TASGEED6 */ + __IOM uint32_t TASGEED7 : 1; /*!< [23..23] TASGEED7 */ + __IOM uint32_t TASCTGEED : 1; /*!< [24..24] TASCTGEED */ + uint32_t : 7; + } EAEID0_b; + }; + __IM uint32_t RESERVED16; + + union + { + __IOM uint32_t EAEIS1; /*!< (@ 0x00000510) Ethernet Agent Error Interrupt Status Register + * 1 (EAEIS1) */ + + struct + { + __IOM uint32_t CULES0 : 1; /*!< [0..0] CULES0 */ + __IOM uint32_t CULES1 : 1; /*!< [1..1] CULES1 */ + __IOM uint32_t CULES2 : 1; /*!< [2..2] CULES2 */ + __IOM uint32_t CULES3 : 1; /*!< [3..3] CULES3 */ + __IOM uint32_t CULES4 : 1; /*!< [4..4] CULES4 */ + __IOM uint32_t CULES5 : 1; /*!< [5..5] CULES5 */ + __IOM uint32_t CULES6 : 1; /*!< [6..6] CULES6 */ + __IOM uint32_t CULES7 : 1; /*!< [7..7] CULES7 */ + uint32_t : 8; + __IOM uint32_t TASGES0 : 1; /*!< [16..16] TASGES0 */ + __IOM uint32_t TASGES1 : 1; /*!< [17..17] TASGES1 */ + __IOM uint32_t TASGES2 : 1; /*!< [18..18] TASGES2 */ + __IOM uint32_t TASGES3 : 1; /*!< [19..19] TASGES3 */ + __IOM uint32_t TASGES4 : 1; /*!< [20..20] TASGES4 */ + __IOM uint32_t TASGES5 : 1; /*!< [21..21] TASGES5 */ + __IOM uint32_t TASGES6 : 1; /*!< [22..22] TASGES6 */ + __IOM uint32_t TASGES7 : 1; /*!< [23..23] TASGES7 */ + __IOM uint32_t TASCTGES : 1; /*!< [24..24] TASCTGES */ + uint32_t : 7; + } EAEIS1_b; + }; + + union + { + __IOM uint32_t EAEIE1; /*!< (@ 0x00000514) Ethernet Agent Error Interrupt Enable Register + * 1 (EAEIE1) */ + + struct + { + __IOM uint32_t CULEE0 : 1; /*!< [0..0] CULEE0 */ + __IOM uint32_t CULEE1 : 1; /*!< [1..1] CULEE1 */ + __IOM uint32_t CULEE2 : 1; /*!< [2..2] CULEE2 */ + __IOM uint32_t CULEE3 : 1; /*!< [3..3] CULEE3 */ + __IOM uint32_t CULEE4 : 1; /*!< [4..4] CULEE4 */ + __IOM uint32_t CULEE5 : 1; /*!< [5..5] CULEE5 */ + __IOM uint32_t CULEE6 : 1; /*!< [6..6] CULEE6 */ + __IOM uint32_t CULEE7 : 1; /*!< [7..7] CULEE7 */ + uint32_t : 8; + __IOM uint32_t TASGEE0 : 1; /*!< [16..16] TASGEE0 */ + __IOM uint32_t TASGEE1 : 1; /*!< [17..17] TASGEE1 */ + __IOM uint32_t TASGEE2 : 1; /*!< [18..18] TASGEE2 */ + __IOM uint32_t TASGEE3 : 1; /*!< [19..19] TASGEE3 */ + __IOM uint32_t TASGEE4 : 1; /*!< [20..20] TASGEE4 */ + __IOM uint32_t TASGEE5 : 1; /*!< [21..21] TASGEE5 */ + __IOM uint32_t TASGEE6 : 1; /*!< [22..22] TASGEE6 */ + __IOM uint32_t TASGEE7 : 1; /*!< [23..23] TASGEE7 */ + __IOM uint32_t TASCTGEE : 1; /*!< [24..24] TASCTGEE */ + uint32_t : 7; + } EAEIE1_b; + }; + + union + { + __IOM uint32_t EAEID1; /*!< (@ 0x00000518) Ethernet Agent Error Interrupt Disable Register + * 1 (EAEID1) */ + + struct + { + __IOM uint32_t CULED0 : 1; /*!< [0..0] CULED0 */ + __IOM uint32_t CULED1 : 1; /*!< [1..1] CULED1 */ + __IOM uint32_t CULED2 : 1; /*!< [2..2] CULED2 */ + __IOM uint32_t CULED3 : 1; /*!< [3..3] CULED3 */ + __IOM uint32_t CULED4 : 1; /*!< [4..4] CULED4 */ + __IOM uint32_t CULED5 : 1; /*!< [5..5] CULED5 */ + __IOM uint32_t CULED6 : 1; /*!< [6..6] CULED6 */ + __IOM uint32_t CULED7 : 1; /*!< [7..7] CULED7 */ + uint32_t : 8; + __IOM uint32_t TASGED0 : 1; /*!< [16..16] TASGED0 */ + __IOM uint32_t TASGED1 : 1; /*!< [17..17] TASGED1 */ + __IOM uint32_t TASGED2 : 1; /*!< [18..18] TASGED2 */ + __IOM uint32_t TASGED3 : 1; /*!< [19..19] TASGED3 */ + __IOM uint32_t TASGED4 : 1; /*!< [20..20] TASGED4 */ + __IOM uint32_t TASGED5 : 1; /*!< [21..21] TASGED5 */ + __IOM uint32_t TASGED6 : 1; /*!< [22..22] TASGED6 */ + __IOM uint32_t TASGED7 : 1; /*!< [23..23] TASGED7 */ + __IOM uint32_t TASCTGED : 1; /*!< [24..24] TASCTGED */ + uint32_t : 7; + } EAEID1_b; + }; + __IM uint32_t RESERVED17; + + union + { + __IOM uint32_t EAEIS2; /*!< (@ 0x00000520) Ethernet Agent Error Interrupt Status Register + * 2 (EAEIS2) */ + + struct + { + __IOM uint32_t DQOES0 : 1; /*!< [0..0] DQOES0 */ + __IOM uint32_t DQOES1 : 1; /*!< [1..1] DQOES1 */ + __IOM uint32_t DQOES2 : 1; /*!< [2..2] DQOES2 */ + __IOM uint32_t DQOES3 : 1; /*!< [3..3] DQOES3 */ + __IOM uint32_t DQOES4 : 1; /*!< [4..4] DQOES4 */ + __IOM uint32_t DQOES5 : 1; /*!< [5..5] DQOES5 */ + __IOM uint32_t DQOES6 : 1; /*!< [6..6] DQOES6 */ + __IOM uint32_t DQOES7 : 1; /*!< [7..7] DQOES7 */ + __IOM uint32_t CTDQOES : 1; /*!< [8..8] CTDQOES */ + uint32_t : 7; + __IOM uint32_t DQSES0 : 1; /*!< [16..16] DQSES0 */ + __IOM uint32_t DQSES1 : 1; /*!< [17..17] DQSES1 */ + __IOM uint32_t DQSES2 : 1; /*!< [18..18] DQSES2 */ + __IOM uint32_t DQSES3 : 1; /*!< [19..19] DQSES3 */ + __IOM uint32_t DQSES4 : 1; /*!< [20..20] DQSES4 */ + __IOM uint32_t DQSES5 : 1; /*!< [21..21] DQSES5 */ + __IOM uint32_t DQSES6 : 1; /*!< [22..22] DQSES6 */ + __IOM uint32_t DQSES7 : 1; /*!< [23..23] DQSES7 */ + uint32_t : 8; + } EAEIS2_b; + }; + + union + { + __IOM uint32_t EAEIE2; /*!< (@ 0x00000524) Ethernet Agent Error Interrupt Enable Register + * 2 (EAEIE2) */ + + struct + { + __IOM uint32_t DQOEE0 : 1; /*!< [0..0] DQOEE0 */ + __IOM uint32_t DQOEE1 : 1; /*!< [1..1] DQOEE1 */ + __IOM uint32_t DQOEE2 : 1; /*!< [2..2] DQOEE2 */ + __IOM uint32_t DQOEE3 : 1; /*!< [3..3] DQOEE3 */ + __IOM uint32_t DQOEE4 : 1; /*!< [4..4] DQOEE4 */ + __IOM uint32_t DQOEE5 : 1; /*!< [5..5] DQOEE5 */ + __IOM uint32_t DQOEE6 : 1; /*!< [6..6] DQOEE6 */ + __IOM uint32_t DQOEE7 : 1; /*!< [7..7] DQOEE7 */ + __IOM uint32_t CTDQOEE : 1; /*!< [8..8] CTDQOEE */ + uint32_t : 7; + __IOM uint32_t DQSEE0 : 1; /*!< [16..16] DQSEE0 */ + __IOM uint32_t DQSEE1 : 1; /*!< [17..17] DQSEE1 */ + __IOM uint32_t DQSEE2 : 1; /*!< [18..18] DQSEE2 */ + __IOM uint32_t DQSEE3 : 1; /*!< [19..19] DQSEE3 */ + __IOM uint32_t DQSEE4 : 1; /*!< [20..20] DQSEE4 */ + __IOM uint32_t DQSEE5 : 1; /*!< [21..21] DQSEE5 */ + __IOM uint32_t DQSEE6 : 1; /*!< [22..22] DQSEE6 */ + __IOM uint32_t DQSEE7 : 1; /*!< [23..23] DQSEE7 */ + uint32_t : 8; + } EAEIE2_b; + }; + + union + { + __IOM uint32_t EAEID2; /*!< (@ 0x00000528) Ethernet Agent Error Interrupt Disable Register + * 2 (EAEID2) */ + + struct + { + __IOM uint32_t DQOED0 : 1; /*!< [0..0] DQOED0 */ + __IOM uint32_t DQOED1 : 1; /*!< [1..1] DQOED1 */ + __IOM uint32_t DQOED2 : 1; /*!< [2..2] DQOED2 */ + __IOM uint32_t DQOED3 : 1; /*!< [3..3] DQOED3 */ + __IOM uint32_t DQOED4 : 1; /*!< [4..4] DQOED4 */ + __IOM uint32_t DQOED5 : 1; /*!< [5..5] DQOED5 */ + __IOM uint32_t DQOED6 : 1; /*!< [6..6] DQOED6 */ + __IOM uint32_t DQOED7 : 1; /*!< [7..7] DQOED7 */ + __IOM uint32_t CTDQOED : 1; /*!< [8..8] CTDQOED */ + uint32_t : 7; + __IOM uint32_t DQSED0 : 1; /*!< [16..16] DQSED0 */ + __IOM uint32_t DQSED1 : 1; /*!< [17..17] DQSED1 */ + __IOM uint32_t DQSED2 : 1; /*!< [18..18] DQSED2 */ + __IOM uint32_t DQSED3 : 1; /*!< [19..19] DQSED3 */ + __IOM uint32_t DQSED4 : 1; /*!< [20..20] DQSED4 */ + __IOM uint32_t DQSED5 : 1; /*!< [21..21] DQSED5 */ + __IOM uint32_t DQSED6 : 1; /*!< [22..22] DQSED6 */ + __IOM uint32_t DQSED7 : 1; /*!< [23..23] DQSED7 */ + uint32_t : 8; + } EAEID2_b; + }; + __IM uint32_t RESERVED18[21]; + + union + { + __IOM uint32_t EASCR; /*!< (@ 0x00000580) Ethernet Agent Security Configuration Register + * (EASCR) */ + + struct + { + __IOM uint32_t MRSL : 1; /*!< [0..0] MRSL */ + __IOM uint32_t TRSL : 1; /*!< [1..1] TRSL */ + __IOM uint32_t MCRSL : 1; /*!< [2..2] MCRSL */ + __IOM uint32_t TGRSL : 1; /*!< [3..3] TGRSL */ + __IOM uint32_t TASRSL : 1; /*!< [4..4] TASRSL */ + __IOM uint32_t EIRSL : 1; /*!< [5..5] EIRSL */ + __IOM uint32_t CRSL : 1; /*!< [6..6] CRSL */ + uint32_t : 9; + __IOM uint32_t DQRSL0 : 1; /*!< [16..16] DQRSL0 */ + __IOM uint32_t DQRSL1 : 1; /*!< [17..17] DQRSL1 */ + __IOM uint32_t DQRSL2 : 1; /*!< [18..18] DQRSL2 */ + __IOM uint32_t DQRSL3 : 1; /*!< [19..19] DQRSL3 */ + __IOM uint32_t DQRSL4 : 1; /*!< [20..20] DQRSL4 */ + __IOM uint32_t DQRSL5 : 1; /*!< [21..21] DQRSL5 */ + __IOM uint32_t DQRSL6 : 1; /*!< [22..22] DQRSL6 */ + __IOM uint32_t DQRSL7 : 1; /*!< [23..23] DQRSL7 */ + uint32_t : 8; + } EASCR_b; + }; +} R_ETHA0_Type; /*!< Size = 1412 (0x584) */ + +/* =========================================================================================================================== */ +/* ================ R_GPTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Generic PTP Timer (R_GPTP) + */ + +typedef struct /*!< (@ 0x403E0000) R_GPTP Structure */ +{ + union + { + __IM uint32_t PTPIPV; /*!< (@ 0x00000000) IP Version Register */ + + struct + { + __IM uint32_t IPV : 32; /*!< [31..0] IP Version */ + } PTPIPV_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t PTPTMEC; /*!< (@ 0x00000010) Timer Enable Configuration Register */ + + struct + { + __IOM uint32_t TE : 2; /*!< [1..0] Timer Enable */ + uint32_t : 30; + } PTPTMEC_b; + }; + + union + { + __IOM uint32_t PTPTMDC; /*!< (@ 0x00000014) Timer Disable Configuration Register */ + + struct + { + __OM uint32_t TD : 2; /*!< [1..0] Timer Disable */ + uint32_t : 30; + } PTPTMDC_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t PTPTIVC0; /*!< (@ 0x00000020) Timer Increment Value Configuration Register + * 0 */ + + struct + { + __IOM uint32_t TIV : 32; /*!< [31..0] Timer Increment Value */ + } PTPTIVC0_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t PTPTOVCL0; /*!< (@ 0x00000030) Timer Offset Value Configuration Register L0 */ + + struct + { + __IOM uint32_t TOVL : 30; /*!< [29..0] Timer Offset Value Lower Part */ + uint32_t : 2; + } PTPTOVCL0_b; + }; + + union + { + __IOM uint32_t PTPTOVCM0; /*!< (@ 0x00000034) Timer Offset Value Configuration Register M0 */ + + struct + { + __IOM uint32_t TOVM : 32; /*!< [31..0] Timer Offset Value Middle Part */ + } PTPTOVCM0_b; + }; + + union + { + __IOM uint32_t PTPTOVCU0; /*!< (@ 0x00000038) Timer Offset Value Configuration Register U0 */ + + struct + { + __IOM uint32_t TOVU : 16; /*!< [15..0] Timer Offset Value Upper Part */ + uint32_t : 16; + } PTPTOVCU0_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IM uint32_t PTPAVTPTML0; /*!< (@ 0x00000040) AVTP Timer Monitoring Register L0 */ + + struct + { + __IM uint32_t AVTPL : 32; /*!< [31..0] AVTP Timer Value Lower Part */ + } PTPAVTPTML0_b; + }; + + union + { + __IM uint32_t PTPAVTPTMU0; /*!< (@ 0x00000044) AVTP Timer Monitoring Register U0 */ + + struct + { + __IM uint32_t AVTPU : 32; /*!< [31..0] AVTP Timer Value Upper Part */ + } PTPAVTPTMU0_b; + }; + __IM uint32_t RESERVED4[2]; + + union + { + __IM uint32_t PTPGPTPTML0; /*!< (@ 0x00000050) GPTP Timer Monitoring Register L0 */ + + struct + { + __IM uint32_t GPTPL : 30; /*!< [29..0] GPTP Timer Value Lower Part */ + uint32_t : 2; + } PTPGPTPTML0_b; + }; + + union + { + __IM uint32_t PTPGPTPTMM0; /*!< (@ 0x00000054) GPTP Timer Monitoring Register M0 */ + + struct + { + __IM uint32_t GPTPM : 32; /*!< [31..0] GPTP Timer Value Middle Part */ + } PTPGPTPTMM0_b; + }; + + union + { + __IM uint32_t PTPGPTPTMU0; /*!< (@ 0x00000058) GPTP Timer Monitoring Register U0 */ + + struct + { + __IM uint32_t GPTPU : 16; /*!< [15..0] GPTP Timer Value Upper Part */ + uint32_t : 16; + } PTPGPTPTMU0_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t PTPTIVC1; /*!< (@ 0x00000060) Timer Increment Value Configuration Register + * 1 */ + + struct + { + __IOM uint32_t TIV : 32; /*!< [31..0] Timer Increment Value */ + } PTPTIVC1_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t PTPTOVCL1; /*!< (@ 0x00000070) Timer Offset Value Configuration Register L1 */ + + struct + { + __IOM uint32_t TOVL : 30; /*!< [29..0] Timer Offset Value Lower Part */ + uint32_t : 2; + } PTPTOVCL1_b; + }; + + union + { + __IOM uint32_t PTPTOVCM1; /*!< (@ 0x00000074) Timer Offset Value Configuration Register M1 */ + + struct + { + __IOM uint32_t TOVM : 32; /*!< [31..0] Timer Offset Value Middle Part */ + } PTPTOVCM1_b; + }; + + union + { + __IOM uint32_t PTPTOVCU1; /*!< (@ 0x00000078) Timer Offset Value Configuration Register U1 */ + + struct + { + __IOM uint32_t TOVU : 16; /*!< [15..0] Timer Offset Value Upper Part */ + uint32_t : 16; + } PTPTOVCU1_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IM uint32_t PTPAVTPTML1; /*!< (@ 0x00000080) AVTP Timer Monitoring Register L1 */ + + struct + { + __IM uint32_t AVTPL : 32; /*!< [31..0] AVTP Timer Value Lower Part */ + } PTPAVTPTML1_b; + }; + + union + { + __IM uint32_t PTPAVTPTMU1; /*!< (@ 0x00000084) AVTP Timer Monitoring Register U1 */ + + struct + { + __IM uint32_t AVTPU : 32; /*!< [31..0] AVTP Timer Value Upper Part */ + } PTPAVTPTMU1_b; + }; + __IM uint32_t RESERVED8[2]; + + union + { + __IM uint32_t PTPGPTPTML1; /*!< (@ 0x00000090) GPTP Timer Monitoring Register L1 */ + + struct + { + __IM uint32_t GPTPL : 30; /*!< [29..0] GPTP Timer Value Lower Part */ + uint32_t : 2; + } PTPGPTPTML1_b; + }; + + union + { + __IM uint32_t PTPGPTPTMM1; /*!< (@ 0x00000094) GPTP Timer Monitoring Register M1 */ + + struct + { + __IM uint32_t GPTPM : 32; /*!< [31..0] GPTP Timer Value Middle Part */ + } PTPGPTPTMM1_b; + }; + + union + { + __IM uint32_t PTPGPTPTMU1; /*!< (@ 0x00000098) GPTP Timer Monitoring Register U1 */ + + struct + { + __IM uint32_t GPTPU : 16; /*!< [15..0] GPTP Timer Value Upper Part */ + uint32_t : 16; + } PTPGPTPTMU1_b; + }; + __IM uint32_t RESERVED9[89]; + + union + { + __IOM uint32_t PTPMCCC0; /*!< (@ 0x00000200) Media Clock Capture Configuration Register 0 */ + + struct + { + __IOM uint32_t MCPEE : 1; /*!< [0..0] Media Clock Capture Positive Edge Enable */ + __IOM uint32_t MCNEE : 1; /*!< [1..1] Media Clock Capture Negative Edge Enable */ + __IOM uint32_t MCTTS : 1; /*!< [2..2] Media Clock Capture Timer Type Select */ + __IOM uint32_t MCTNS : 1; /*!< [3..3] Media Clock Capture Timer Number Select */ + uint32_t : 12; + __IOM uint32_t MCCR : 1; /*!< [16..16] Media Clock Capture Request */ + uint32_t : 15; + } PTPMCCC0_b; + }; + + union + { + __IM uint32_t PTPMCCML0; /*!< (@ 0x00000204) Media Clock Capture Monitoring Register L0 */ + + struct + { + __IM uint32_t MCCTVL : 32; /*!< [31..0] Media Clock Captured Timer Value Lower Part */ + } PTPMCCML0_b; + }; + + union + { + __IM uint32_t PTPMCCMM0; /*!< (@ 0x00000208) Media Clock Capture Monitoring Register M0 */ + + struct + { + __IM uint32_t MCCTVM : 32; /*!< [31..0] Media Clock Captured Timer Value Middle Part */ + } PTPMCCMM0_b; + }; + + union + { + __IM uint32_t PTPMCCMU0; /*!< (@ 0x0000020C) Media Clock Capture Monitoring Register U0 */ + + struct + { + __IM uint32_t MCCTVU : 16; /*!< [15..0] Media Clock Captured Timer Value Upper Part */ + __IM uint32_t MCPEC : 1; /*!< [16..16] Media Clock Positive Edge Captured */ + __IM uint32_t MCNEC : 1; /*!< [17..17] Media Clock Negative Edge Captured */ + __IM uint32_t MCSWC : 1; /*!< [18..18] Media Clock SoftWare Captured */ + uint32_t : 5; + __IM uint32_t MCCN : 2; /*!< [25..24] Media Clock Capture Number */ + uint32_t : 6; + } PTPMCCMU0_b; + }; + + union + { + __IOM uint32_t PTPMCCC1; /*!< (@ 0x00000210) Media Clock Capture Configuration Register 1 */ + + struct + { + __IOM uint32_t MCPEE : 1; /*!< [0..0] Media Clock Capture Positive Edge Enable */ + __IOM uint32_t MCNEE : 1; /*!< [1..1] Media Clock Capture Negative Edge Enable */ + __IOM uint32_t MCTTS : 1; /*!< [2..2] Media Clock Capture Timer Type Select */ + __IOM uint32_t MCTNS : 1; /*!< [3..3] Media Clock Capture Timer Number Select */ + uint32_t : 12; + __IOM uint32_t MCCR : 1; /*!< [16..16] Media Clock Capture Request */ + uint32_t : 15; + } PTPMCCC1_b; + }; + + union + { + __IM uint32_t PTPMCCML1; /*!< (@ 0x00000214) Media Clock Capture Monitoring Register L1 */ + + struct + { + __IM uint32_t MCCTVL : 32; /*!< [31..0] Media Clock Captured Timer Value Lower Part */ + } PTPMCCML1_b; + }; + + union + { + __IM uint32_t PTPMCCMM1; /*!< (@ 0x00000218) Media Clock Capture Monitoring Register M1 */ + + struct + { + __IM uint32_t MCCTVM : 32; /*!< [31..0] Media Clock Captured Timer Value Middle Part */ + } PTPMCCMM1_b; + }; + + union + { + __IM uint32_t PTPMCCMU1; /*!< (@ 0x0000021C) Media Clock Capture Monitoring Register U1 */ + + struct + { + __IM uint32_t MCCTVU : 16; /*!< [15..0] Media Clock Captured Timer Value Upper Part */ + __IM uint32_t MCPEC : 1; /*!< [16..16] Media Clock Positive Edge Captured */ + __IM uint32_t MCNEC : 1; /*!< [17..17] Media Clock Negative Edge Captured */ + __IM uint32_t MCSWC : 1; /*!< [18..18] Media Clock SoftWare Captured */ + uint32_t : 5; + __IM uint32_t MCCN : 2; /*!< [25..24] Media Clock Capture Number */ + uint32_t : 6; + } PTPMCCMU1_b; + }; + __IM uint32_t RESERVED10[56]; + + union + { + __IOM uint32_t PTPMCRC0; /*!< (@ 0x00000300) Media Clock Recovery Configuration Register 0 */ + + struct + { + __IOM uint32_t MRTTS : 1; /*!< [0..0] Media Clock Recovery Timer Type Select */ + __IOM uint32_t MRAMS : 1; /*!< [1..1] Media Clock Recovery AVTP Mode Select */ + __IOM uint32_t MRTNS : 1; /*!< [2..2] Media Clock Recovery Timer Number Select */ + uint32_t : 13; + __IOM uint32_t MRPL : 16; /*!< [31..16] Media Clock Recovery Pulse Length */ + } PTPMCRC0_b; + }; + + union + { + __IOM uint32_t PTPMCRTCL0; /*!< (@ 0x00000304) Media Clock Recovery Time Configuration Register + * L0 */ + + struct + { + __IOM uint32_t MRTVL : 32; /*!< [31..0] Media Clock Recovery Timer Value Lower Part */ + } PTPMCRTCL0_b; + }; + + union + { + __IOM uint32_t PTPMCRTCM0; /*!< (@ 0x00000308) Media Clock Recovery Time Configuration Register + * M0 */ + + struct + { + __IOM uint32_t MRTVM : 32; /*!< [31..0] Media Clock Recovery Timer Value Middle Part */ + } PTPMCRTCM0_b; + }; + + union + { + __IOM uint32_t PTPMCRTCU0; /*!< (@ 0x0000030C) Media Clock Recovery Time Configuration Register + * U0 */ + + struct + { + __IOM uint32_t MRTVU : 16; /*!< [15..0] Media Clock Recovery Timer Value Upper Part */ + __IOM uint32_t MRTT : 2; /*!< [17..16] Media Clock Recovery Trigger Type */ + __IM uint32_t MCRN : 3; /*!< [20..18] Media Clock Recovery Number */ + uint32_t : 10; + __IM uint32_t MRBCR : 1; /*!< [31..31] Media Clock Recovery Buffer Clear Request */ + } PTPMCRTCU0_b; + }; + + union + { + __IOM uint32_t PTPMCRC1; /*!< (@ 0x00000310) Media Clock Recovery Configuration Register 1 */ + + struct + { + __IOM uint32_t MRTTS : 1; /*!< [0..0] Media Clock Recovery Timer Type Select */ + __IOM uint32_t MRAMS : 1; /*!< [1..1] Media Clock Recovery AVTP Mode Select */ + __IOM uint32_t MRTNS : 1; /*!< [2..2] Media Clock Recovery Timer Number Select */ + uint32_t : 13; + __IOM uint32_t MRPL : 16; /*!< [31..16] Media Clock Recovery Pulse Length */ + } PTPMCRC1_b; + }; + + union + { + __IOM uint32_t PTPMCRTCL1; /*!< (@ 0x00000314) Media Clock Recovery Time Configuration Register + * L1 */ + + struct + { + __IOM uint32_t MRTVL : 32; /*!< [31..0] Media Clock Recovery Timer Value Lower Part */ + } PTPMCRTCL1_b; + }; + + union + { + __IOM uint32_t PTPMCRTCM1; /*!< (@ 0x00000318) Media Clock Recovery Time Configuration Register + * M1 */ + + struct + { + __IOM uint32_t MRTVM : 32; /*!< [31..0] Media Clock Recovery Timer Value Middle Part */ + } PTPMCRTCM1_b; + }; + + union + { + __IOM uint32_t PTPMCRTCU1; /*!< (@ 0x0000031C) Media Clock Recovery Time Configuration Register + * U1 */ + + struct + { + __IOM uint32_t MRTVU : 16; /*!< [15..0] Media Clock Recovery Timer Value Upper Part */ + __IOM uint32_t MRTT : 2; /*!< [17..16] Media Clock Recovery Trigger Type */ + __IM uint32_t MCRN : 3; /*!< [20..18] Media Clock Recovery Number */ + uint32_t : 10; + __IM uint32_t MRBCR : 1; /*!< [31..31] Media Clock Recovery Buffer Clear Request */ + } PTPMCRTCU1_b; + }; + __IM uint32_t RESERVED11[56]; + + union + { + __IOM uint32_t PTPMCPC0; /*!< (@ 0x00000400) Media Clock Pin Configuration Register 0 */ + + struct + { + __IOM uint32_t PE : 1; /*!< [0..0] Pin Enable */ + __IOM uint32_t MRS : 1; /*!< [1..1] Media Clock Recovery Select */ + uint32_t : 30; + } PTPMCPC0_b; + }; + + union + { + __IOM uint32_t PTPMCPC1; /*!< (@ 0x00000404) Media Clock Pin Configuration Register 1 */ + + struct + { + __IOM uint32_t PE : 1; /*!< [0..0] Pin Enable */ + __IOM uint32_t MRS : 1; /*!< [1..1] Media Clock Recovery Select */ + uint32_t : 30; + } PTPMCPC1_b; + }; + __IM uint32_t RESERVED12[62]; + + union + { + __IOM uint32_t PTPCCC00; /*!< (@ 0x00000500) Cyclic Compare Configuration Register 00 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC00_b; + }; + + union + { + __IOM uint32_t PTPCCC10; /*!< (@ 0x00000504) Cyclic Compare Configuration Register 10 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC10_b; + }; + + union + { + __IOM uint32_t PTPCCC01; /*!< (@ 0x00000508) Cyclic Compare Configuration Register 01 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC01_b; + }; + + union + { + __IOM uint32_t PTPCCC11; /*!< (@ 0x0000050C) Cyclic Compare Configuration Register 11 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC11_b; + }; + + union + { + __IOM uint32_t PTPCCC02; /*!< (@ 0x00000510) Cyclic Compare Configuration Register 02 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC02_b; + }; + + union + { + __IOM uint32_t PTPCCC12; /*!< (@ 0x00000514) Cyclic Compare Configuration Register 12 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC12_b; + }; + + union + { + __IOM uint32_t PTPCCC03; /*!< (@ 0x00000518) Cyclic Compare Configuration Register 03 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC03_b; + }; + + union + { + __IOM uint32_t PTPCCC13; /*!< (@ 0x0000051C) Cyclic Compare Configuration Register 13 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC13_b; + }; + + union + { + __IOM uint32_t PTPCCC04; /*!< (@ 0x00000520) Cyclic Compare Configuration Register 04 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC04_b; + }; + + union + { + __IOM uint32_t PTPCCC14; /*!< (@ 0x00000524) Cyclic Compare Configuration Register 14 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC14_b; + }; + + union + { + __IOM uint32_t PTPCCC05; /*!< (@ 0x00000528) Cyclic Compare Configuration Register 05 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC05_b; + }; + + union + { + __IOM uint32_t PTPCCC15; /*!< (@ 0x0000052C) Cyclic Compare Configuration Register 15 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC15_b; + }; + + union + { + __IOM uint32_t PTPCCC06; /*!< (@ 0x00000530) Cyclic Compare Configuration Register 06 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC06_b; + }; + + union + { + __IOM uint32_t PTPCCC16; /*!< (@ 0x00000534) Cyclic Compare Configuration Register 16 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC16_b; + }; + + union + { + __IOM uint32_t PTPCCC07; /*!< (@ 0x00000538) Cyclic Compare Configuration Register 07 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC07_b; + }; + + union + { + __IOM uint32_t PTPCCC17; /*!< (@ 0x0000053C) Cyclic Compare Configuration Register 17 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC17_b; + }; + __IM uint32_t RESERVED13[112]; + + union + { + __IOM uint32_t PTPIS0; /*!< (@ 0x00000700) Interrupt Status Register 0 */ + + struct + { + __IOM uint32_t MCCS : 2; /*!< [1..0] Media Clock Capture Status */ + uint32_t : 14; + __IOM uint32_t MCCOES : 2; /*!< [17..16] Media Clock Capture Overflow Error Status */ + uint32_t : 14; + } PTPIS0_b; + }; + + union + { + __IOM uint32_t PTPIE0; /*!< (@ 0x00000704) Interrupt Enable Register 0 */ + + struct + { + __IOM uint32_t MCCE : 2; /*!< [1..0] Media Clock Capture Enable */ + uint32_t : 14; + __IOM uint32_t MCCOEE : 2; /*!< [17..16] Media Clock Capture Overflow Error Enable */ + uint32_t : 14; + } PTPIE0_b; + }; + + union + { + __IM uint32_t PTPID0; /*!< (@ 0x00000708) Interrupt Disable Register 0 */ + + struct + { + __IM uint32_t MCCD : 2; /*!< [1..0] Media Clock Capture Disable */ + uint32_t : 14; + __IM uint32_t MCCOED : 2; /*!< [17..16] Media Clock Capture Overflow Error Disable */ + uint32_t : 14; + } PTPID0_b; + }; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t PTPIS1; /*!< (@ 0x00000710) Interrupt Status Register 1 */ + + struct + { + __IOM uint32_t MCRMS : 2; /*!< [1..0] Media Clock Recovery Match Status */ + uint32_t : 30; + } PTPIS1_b; + }; + + union + { + __IOM uint32_t PTPIE1; /*!< (@ 0x00000714) Interrupt Enable Register 1 */ + + struct + { + __IOM uint32_t MCRME : 2; /*!< [1..0] Media Clock Recovery Match Enable */ + uint32_t : 30; + } PTPIE1_b; + }; + + union + { + __IM uint32_t PTPID1; /*!< (@ 0x00000718) Interrupt Disable Register 1 */ + + struct + { + __IM uint32_t MCRMD : 2; /*!< [1..0] Media Clock Recovery Match Disable */ + uint32_t : 30; + } PTPID1_b; + }; + __IM uint32_t RESERVED15[25]; + + union + { + __IOM uint32_t PTPSCR0; /*!< (@ 0x00000780) Security Configuration Register 0 */ + + struct + { + __IOM uint32_t TRSL : 2; /*!< [1..0] TRSL */ + uint32_t : 14; + __IOM uint32_t MCRSL : 2; /*!< [17..16] MCRSL */ + uint32_t : 14; + } PTPSCR0_b; + }; + + union + { + __IOM uint32_t PTPSCR1; /*!< (@ 0x00000784) Security Configuration Register 1 */ + + struct + { + __IOM uint32_t MRRSL : 2; /*!< [1..0] MRRSL */ + uint32_t : 14; + __IOM uint32_t MRRRSL : 2; /*!< [17..16] MRRRSL */ + uint32_t : 14; + } PTPSCR1_b; + }; + + union + { + __IOM uint32_t PTPSCR2; /*!< (@ 0x00000788) Security Configuration Register 2 */ + + struct + { + __IOM uint32_t CCRSL : 2; /*!< [1..0] CCRSL */ + uint32_t : 14; + __IOM uint32_t VRSL : 1; /*!< [16..16] VRSL */ + uint32_t : 15; + } PTPSCR2_b; + }; + __IM uint32_t RESERVED16[541]; + + union + { + __IOM uint32_t POTCFGR; /*!< (@ 0x00001000) Pulse Output Timer Configuration Register */ + + struct + { + __IOM uint32_t REFSEL : 1; /*!< [0..0] Reference Timer Select */ + uint32_t : 31; + } POTCFGR_b; + }; + + union + { + __IOM uint32_t POTCR0; /*!< (@ 0x00001004) Pulse Output Timer Control Register 0 */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] Pulse Output Enable */ + uint32_t : 31; + } POTCR0_b; + }; + __IOM uint32_t POTSTRU0; /*!< (@ 0x00001008) Pulse Output Start Time Setting Register U0 */ + __IOM uint32_t POTSTRM0; /*!< (@ 0x0000100C) Pulse Output Start Time Setting Register M0 */ + __IOM uint32_t POTSTRL0; /*!< (@ 0x00001010) Pulse Output Start Time Setting Register L0 */ + __IOM uint32_t POTPERU0; /*!< (@ 0x00001014) Period Setting Register U0 */ + __IOM uint32_t POTPERM0; /*!< (@ 0x00001018) Period Setting Register M0 */ + __IOM uint32_t POTPERL0; /*!< (@ 0x0000101C) Period Setting Register L0 */ + __IOM uint32_t POTPWR0; /*!< (@ 0x00001020) Pulse Width Setting Register 0 */ + __IM uint32_t RESERVED17; + __IM uint32_t POTCPRU0; /*!< (@ 0x00001028) Time Capture Register U0 */ + __IM uint32_t POTCPRM0; /*!< (@ 0x0000102C) Time Capture Register M0 */ + __IM uint32_t POTCPRL0; /*!< (@ 0x00001030) Time Capture Register L0 */ + + union + { + __IOM uint32_t POTCR1; /*!< (@ 0x00001034) Pulse Output Timer Control Register 1 */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] Pulse Output Enable */ + uint32_t : 31; + } POTCR1_b; + }; + __IOM uint32_t POTSTRU1; /*!< (@ 0x00001038) Pulse Output Start Time Setting Register U1 */ + __IOM uint32_t POTSTRM1; /*!< (@ 0x0000103C) Pulse Output Start Time Setting Register M1 */ + __IOM uint32_t POTSTRL1; /*!< (@ 0x00001040) Pulse Output Start Time Setting Register L1 */ + __IOM uint32_t POTPERU1; /*!< (@ 0x00001044) Period Setting Register U1 */ + __IOM uint32_t POTPERM1; /*!< (@ 0x00001048) Period Setting Register M1 */ + __IOM uint32_t POTPERL1; /*!< (@ 0x0000104C) Period Setting Register L1 */ + __IOM uint32_t POTPWR1; /*!< (@ 0x00001050) Pulse Width Setting Register 1 */ + __IM uint32_t RESERVED18; + __IM uint32_t POTCPRU1; /*!< (@ 0x00001058) Time Capture Register U1 */ + __IM uint32_t POTCPRM1; /*!< (@ 0x0000105C) Time Capture Register M1 */ + __IM uint32_t POTCPRL1; /*!< (@ 0x00001060) Time Capture Register L1 */ + + union + { + __IOM uint32_t POTCR2; /*!< (@ 0x00001064) Pulse Output Timer Control Register 2 */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] Pulse Output Enable */ + uint32_t : 31; + } POTCR2_b; + }; + __IOM uint32_t POTSTRU2; /*!< (@ 0x00001068) Pulse Output Start Time Setting Register U2 */ + __IOM uint32_t POTSTRM2; /*!< (@ 0x0000106C) Pulse Output Start Time Setting Register M2 */ + __IOM uint32_t POTSTRL2; /*!< (@ 0x00001070) Pulse Output Start Time Setting Register L2 */ + __IOM uint32_t POTPERU2; /*!< (@ 0x00001074) Period Setting Register U2 */ + __IOM uint32_t POTPERM2; /*!< (@ 0x00001078) Period Setting Register M2 */ + __IOM uint32_t POTPERL2; /*!< (@ 0x0000107C) Period Setting Register L2 */ + __IOM uint32_t POTPWR2; /*!< (@ 0x00001080) Pulse Width Setting Register 2 */ + __IM uint32_t RESERVED19; + __IM uint32_t POTCPRU2; /*!< (@ 0x00001088) Time Capture Register U2 */ + __IM uint32_t POTCPRM2; /*!< (@ 0x0000108C) Time Capture Register M2 */ + __IM uint32_t POTCPRL2; /*!< (@ 0x00001090) Time Capture Register L2 */ + + union + { + __IOM uint32_t POTCR3; /*!< (@ 0x00001094) Pulse Output Timer Control Register 3 */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] Pulse Output Enable */ + uint32_t : 31; + } POTCR3_b; + }; + __IOM uint32_t POTSTRU3; /*!< (@ 0x00001098) Pulse Output Start Time Setting Register U3 */ + __IOM uint32_t POTSTRM3; /*!< (@ 0x0000109C) Pulse Output Start Time Setting Register M3 */ + __IOM uint32_t POTSTRL3; /*!< (@ 0x000010A0) Pulse Output Start Time Setting Register L3 */ + __IOM uint32_t POTPERU3; /*!< (@ 0x000010A4) Period Setting Register U3 */ + __IOM uint32_t POTPERM3; /*!< (@ 0x000010A8) Period Setting Register M3 */ + __IOM uint32_t POTPERL3; /*!< (@ 0x000010AC) Period Setting Register L3 */ + __IOM uint32_t POTPWR3; /*!< (@ 0x000010B0) Pulse Width Setting Register 3 */ + __IM uint32_t RESERVED20; + __IM uint32_t POTCPRU3; /*!< (@ 0x000010B8) Time Capture Register U3 */ + __IM uint32_t POTCPRM3; /*!< (@ 0x000010BC) Time Capture Register M3 */ + __IM uint32_t POTCPRL3; /*!< (@ 0x000010C0) Time Capture Register L3 */ +} R_GPTP_Type; /*!< Size = 4292 (0x10c4) */ + +/* =========================================================================================================================== */ +/* ================ R_GWCA0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Gateway CPU Agent (R_GWCA0) + */ + +typedef struct /*!< (@ 0x403CE000) R_GWCA0 Structure */ +{ + union + { + __IOM uint32_t GWMC; /*!< (@ 0x00000000) GWCA Mode Configuration Register (GWMC) */ + + struct + { + __IOM uint32_t OPC : 2; /*!< [1..0] OPC */ + uint32_t : 30; + } GWMC_b; + }; + + union + { + __IOM uint32_t GWMS; /*!< (@ 0x00000004) GWCA Mode Status Register (GWMS) */ + + struct + { + __IOM uint32_t OPS : 2; /*!< [1..0] OPS */ + uint32_t : 30; + } GWMS_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t GWIRC; /*!< (@ 0x00000010) GWCA IPV Remapping Configuration Register [802.1Q] + * (GWIRC) */ + + struct + { + __IOM uint32_t IPVR0 : 3; /*!< [2..0] IPVR0 */ + uint32_t : 1; + __IOM uint32_t IPVR1 : 3; /*!< [6..4] IPVR1 */ + uint32_t : 1; + __IOM uint32_t IPVR2 : 3; /*!< [10..8] IPVR2 */ + uint32_t : 1; + __IOM uint32_t IPVR3 : 3; /*!< [14..12] IPVR3 */ + uint32_t : 1; + __IOM uint32_t IPVR4 : 3; /*!< [18..16] IPVR4 */ + uint32_t : 1; + __IOM uint32_t IPVR5 : 3; /*!< [22..20] IPVR5 */ + uint32_t : 1; + __IOM uint32_t IPVR6 : 3; /*!< [26..24] IPVR6 */ + uint32_t : 1; + __IOM uint32_t IPVR7 : 3; /*!< [30..28] IPVR7 */ + uint32_t : 1; + } GWIRC_b; + }; + + union + { + __IOM uint32_t GWRDQSC; /*!< (@ 0x00000014) GWCA RX Descriptor Queue Security Configuration + * Register (GWRDQSC) */ + + struct + { + __IOM uint32_t RDQSL0 : 1; /*!< [0..0] RDQSL0 */ + __IOM uint32_t RDQSL1 : 1; /*!< [1..1] RDQSL1 */ + __IOM uint32_t RDQSL2 : 1; /*!< [2..2] RDQSL2 */ + __IOM uint32_t RDQSL3 : 1; /*!< [3..3] RDQSL3 */ + __IOM uint32_t RDQSL4 : 1; /*!< [4..4] RDQSL4 */ + __IOM uint32_t RDQSL5 : 1; /*!< [5..5] RDQSL5 */ + __IOM uint32_t RDQSL6 : 1; /*!< [6..6] RDQSL6 */ + __IOM uint32_t RDQSL7 : 1; /*!< [7..7] RDQSL7 */ + uint32_t : 24; + } GWRDQSC_b; + }; + + union + { + __IOM uint32_t GWRDQC; /*!< (@ 0x00000018) GWCA RX Descriptor Queue Control Register (GWRDQC) */ + + struct + { + __IOM uint32_t RDQD0 : 1; /*!< [0..0] RDQD0 */ + __IOM uint32_t RDQD1 : 1; /*!< [1..1] RDQD1 */ + __IOM uint32_t RDQD2 : 1; /*!< [2..2] RDQD2 */ + __IOM uint32_t RDQD3 : 1; /*!< [3..3] RDQD3 */ + __IOM uint32_t RDQD4 : 1; /*!< [4..4] RDQD4 */ + __IOM uint32_t RDQD5 : 1; /*!< [5..5] RDQD5 */ + __IOM uint32_t RDQD6 : 1; /*!< [6..6] RDQD6 */ + __IOM uint32_t RDQD7 : 1; /*!< [7..7] RDQD7 */ + uint32_t : 8; + __IOM uint32_t RDQP0 : 1; /*!< [16..16] RDQP0 */ + __IOM uint32_t RDQP1 : 1; /*!< [17..17] RDQP1 */ + __IOM uint32_t RDQP2 : 1; /*!< [18..18] RDQP2 */ + __IOM uint32_t RDQP3 : 1; /*!< [19..19] RDQP3 */ + __IOM uint32_t RDQP4 : 1; /*!< [20..20] RDQP4 */ + __IOM uint32_t RDQP5 : 1; /*!< [21..21] RDQP5 */ + __IOM uint32_t RDQP6 : 1; /*!< [22..22] RDQP6 */ + __IOM uint32_t RDQP7 : 1; /*!< [23..23] RDQP7 */ + uint32_t : 8; + } GWRDQC_b; + }; + + union + { + __IOM uint32_t GWRDQAC; /*!< (@ 0x0000001C) GWCA RX Descriptor Queue Arbitration Control + * Register (GWRDQAC) */ + + struct + { + __IOM uint32_t RDQA0 : 4; /*!< [3..0] RDQA0 */ + __IOM uint32_t RDQA1 : 4; /*!< [7..4] RDQA1 */ + __IOM uint32_t RDQA2 : 4; /*!< [11..8] RDQA2 */ + __IOM uint32_t RDQA3 : 4; /*!< [15..12] RDQA3 */ + __IOM uint32_t RDQA4 : 4; /*!< [19..16] RDQA4 */ + __IOM uint32_t RDQA5 : 4; /*!< [23..20] RDQA5 */ + __IOM uint32_t RDQA6 : 4; /*!< [27..24] RDQA6 */ + __IOM uint32_t RDQA7 : 4; /*!< [31..28] RDQA7 */ + } GWRDQAC_b; + }; + + union + { + __IOM uint32_t GWRGC; /*!< (@ 0x00000020) GWCA RX General Configuration Register (GWRGC) */ + + struct + { + __IOM uint32_t RCPT : 1; /*!< [0..0] RCPT */ + uint32_t : 31; + } GWRGC_b; + }; + __IM uint32_t RESERVED1[7]; + + union + { + __IOM uint32_t GWRMFSC0; /*!< (@ 0x00000040) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC0_b; + }; + + union + { + __IOM uint32_t GWRMFSC1; /*!< (@ 0x00000044) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC1_b; + }; + + union + { + __IOM uint32_t GWRMFSC2; /*!< (@ 0x00000048) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC2_b; + }; + + union + { + __IOM uint32_t GWRMFSC3; /*!< (@ 0x0000004C) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC3_b; + }; + + union + { + __IOM uint32_t GWRMFSC4; /*!< (@ 0x00000050) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC4_b; + }; + + union + { + __IOM uint32_t GWRMFSC5; /*!< (@ 0x00000054) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC5_b; + }; + + union + { + __IOM uint32_t GWRMFSC6; /*!< (@ 0x00000058) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC6_b; + }; + + union + { + __IOM uint32_t GWRMFSC7; /*!< (@ 0x0000005C) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC7_b; + }; + + union + { + __IOM uint32_t GWRDQDC0; /*!< (@ 0x00000060) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC0_b; + }; + + union + { + __IOM uint32_t GWRDQDC1; /*!< (@ 0x00000064) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC1_b; + }; + + union + { + __IOM uint32_t GWRDQDC2; /*!< (@ 0x00000068) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC2_b; + }; + + union + { + __IOM uint32_t GWRDQDC3; /*!< (@ 0x0000006C) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC3_b; + }; + + union + { + __IOM uint32_t GWRDQDC4; /*!< (@ 0x00000070) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC4_b; + }; + + union + { + __IOM uint32_t GWRDQDC5; /*!< (@ 0x00000074) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC5_b; + }; + + union + { + __IOM uint32_t GWRDQDC6; /*!< (@ 0x00000078) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC6_b; + }; + + union + { + __IOM uint32_t GWRDQDC7; /*!< (@ 0x0000007C) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC7_b; + }; + + union + { + __IOM uint32_t GWRDQM0; /*!< (@ 0x00000080) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM0_b; + }; + + union + { + __IOM uint32_t GWRDQM1; /*!< (@ 0x00000084) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM1_b; + }; + + union + { + __IOM uint32_t GWRDQM2; /*!< (@ 0x00000088) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM2_b; + }; + + union + { + __IOM uint32_t GWRDQM3; /*!< (@ 0x0000008C) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM3_b; + }; + + union + { + __IOM uint32_t GWRDQM4; /*!< (@ 0x00000090) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM4_b; + }; + + union + { + __IOM uint32_t GWRDQM5; /*!< (@ 0x00000094) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM5_b; + }; + + union + { + __IOM uint32_t GWRDQM6; /*!< (@ 0x00000098) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM6_b; + }; + + union + { + __IOM uint32_t GWRDQM7; /*!< (@ 0x0000009C) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM7_b; + }; + + union + { + __IOM uint32_t GWRDQMLM0; /*!< (@ 0x000000A0) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM0_b; + }; + + union + { + __IOM uint32_t GWRDQMLM1; /*!< (@ 0x000000A4) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM1_b; + }; + + union + { + __IOM uint32_t GWRDQMLM2; /*!< (@ 0x000000A8) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM2_b; + }; + + union + { + __IOM uint32_t GWRDQMLM3; /*!< (@ 0x000000AC) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM3_b; + }; + + union + { + __IOM uint32_t GWRDQMLM4; /*!< (@ 0x000000B0) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM4_b; + }; + + union + { + __IOM uint32_t GWRDQMLM5; /*!< (@ 0x000000B4) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM5_b; + }; + + union + { + __IOM uint32_t GWRDQMLM6; /*!< (@ 0x000000B8) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM6_b; + }; + + union + { + __IOM uint32_t GWRDQMLM7; /*!< (@ 0x000000BC) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM7_b; + }; + __IM uint32_t RESERVED2[16]; + + union + { + __IOM uint32_t GWMTIRM; /*!< (@ 0x00000100) GWCA Multicast Table Initialization Register + * Monitoring Register (GWMTIRM) */ + + struct + { + __IOM uint32_t MTIOG : 1; /*!< [0..0] MTIOG */ + __IOM uint32_t MTR : 1; /*!< [1..1] MTR */ + uint32_t : 30; + } GWMTIRM_b; + }; + + union + { + __IOM uint32_t GWMSTLS; /*!< (@ 0x00000104) GWCA Multicast Table Learning Setting Register + * (GWMSTLS) */ + + struct + { + __IOM uint32_t MNRCNL : 7; /*!< [6..0] MNRCNL */ + uint32_t : 1; + __IOM uint32_t MNL : 3; /*!< [10..8] MNL */ + uint32_t : 5; + __IOM uint32_t MSENL : 7; /*!< [22..16] MSENL */ + uint32_t : 9; + } GWMSTLS_b; + }; + + union + { + __IOM uint32_t GWMSTLR; /*!< (@ 0x00000108) GWCA Multicast Table Learning Result Register + * (GWMSTLR) */ + + struct + { + __IOM uint32_t MTLF : 1; /*!< [0..0] MTLF */ + uint32_t : 30; + __IOM uint32_t MTL : 1; /*!< [31..31] MTL */ + } GWMSTLR_b; + }; + + union + { + __IOM uint32_t GWMSTSS; /*!< (@ 0x0000010C) GWCA Multicast Table Searching Setting Register + * (GWMSTSS) */ + + struct + { + __IOM uint32_t MSENS : 7; /*!< [6..0] MSENS */ + uint32_t : 25; + } GWMSTSS_b; + }; + + union + { + __IOM uint32_t GWMSTSR; /*!< (@ 0x00000110) GWCA Multicast Table Searching Result Register + * (GWMSTSR) */ + + struct + { + __IOM uint32_t MNRCNR : 7; /*!< [6..0] MNRCNR */ + uint32_t : 1; + __IOM uint32_t MNR : 3; /*!< [10..8] MNR */ + uint32_t : 5; + __IOM uint32_t MTSEF : 1; /*!< [16..16] MTSEF */ + uint32_t : 14; + __IOM uint32_t MTS : 1; /*!< [31..31] MTS */ + } GWMSTSR_b; + }; + __IM uint32_t RESERVED3[3]; + + union + { + __IOM uint32_t GWMAC0; /*!< (@ 0x00000120) GWCA MAC Address Configuration Register 0 (GWMAC0) */ + + struct + { + __IOM uint32_t MAUP : 16; /*!< [15..0] MAUP */ + uint32_t : 16; + } GWMAC0_b; + }; + + union + { + __IOM uint32_t GWMAC1; /*!< (@ 0x00000124) GWCA MAC Address Configuration Register 1 (GWMAC1) */ + + struct + { + __IOM uint32_t MADP : 32; /*!< [31..0] MADP */ + } GWMAC1_b; + }; + __IM uint32_t RESERVED4[2]; + + union + { + __IOM uint32_t GWVCC; /*!< (@ 0x00000130) GWCA VLAN Control Configuration Register (GWVCC) */ + + struct + { + __IOM uint32_t VIM : 1; /*!< [0..0] VIM */ + uint32_t : 7; + __IOM uint32_t CTVUM : 1; /*!< [8..8] CTVUM */ + uint32_t : 7; + __IOM uint32_t VEM : 3; /*!< [18..16] VEM */ + uint32_t : 13; + } GWVCC_b; + }; + + union + { + __IOM uint32_t GWVTC; /*!< (@ 0x00000134) GWCA VLAN TAG Configuration Register (GWVTC) */ + + struct + { + __IOM uint32_t CTV : 12; /*!< [11..0] CTV */ + __IOM uint32_t CTP : 3; /*!< [14..12] CTP */ + __IOM uint32_t CTD : 1; /*!< [15..15] CTD */ + __IOM uint32_t STV : 12; /*!< [27..16] STV */ + __IOM uint32_t STP : 3; /*!< [30..28] STP */ + __IOM uint32_t STD : 1; /*!< [31..31] STD */ + } GWVTC_b; + }; + + union + { + __IOM uint32_t GWTTFC; /*!< (@ 0x00000138) GWCA Transmission TAG Filtering Configuration + * Register (GWTTFC) */ + + struct + { + __IOM uint32_t NT : 1; /*!< [0..0] NT */ + __IOM uint32_t RT : 1; /*!< [1..1] RT */ + __IOM uint32_t CST : 1; /*!< [2..2] CST */ + __IOM uint32_t CSRT : 1; /*!< [3..3] CSRT */ + __IOM uint32_t CT : 1; /*!< [4..4] CT */ + __IOM uint32_t CRT : 1; /*!< [5..5] CRT */ + __IOM uint32_t SCT : 1; /*!< [6..6] SCT */ + __IOM uint32_t SCRT : 1; /*!< [7..7] SCRT */ + __IOM uint32_t UT : 1; /*!< [8..8] UT */ + uint32_t : 23; + } GWTTFC_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t GWTDCAC00; /*!< (@ 0x00000140) GWCA Timestamp Descriptor Chain Address Configuration + * Register 0s (GWTDCAC0s) (s = 0, 1) */ + + struct + { + __IOM uint32_t TSCCAUP : 8; /*!< [7..0] TSCCAUP */ + uint32_t : 24; + } GWTDCAC00_b; + }; + + union + { + __IOM uint32_t GWTDCAC10; /*!< (@ 0x00000144) GWCA Timestamp Descriptor Chain Address Configuration + * Register 1s (GWTDCAC1s) (s = 0, 1) */ + + struct + { + __IOM uint32_t TSCCADP : 32; /*!< [31..0] TSCCADP */ + } GWTDCAC10_b; + }; + + union + { + __IOM uint32_t GWTDCAC01; /*!< (@ 0x00000148) GWCA Timestamp Descriptor Chain Address Configuration + * Register 0s (GWTDCAC0s) (s = 0, 1) */ + + struct + { + __IOM uint32_t TSCCAUP : 8; /*!< [7..0] TSCCAUP */ + uint32_t : 24; + } GWTDCAC01_b; + }; + + union + { + __IOM uint32_t GWTDCAC11; /*!< (@ 0x0000014C) GWCA Timestamp Descriptor Chain Address Configuration + * Register 1s (GWTDCAC1s) (s = 0, 1) */ + + struct + { + __IOM uint32_t TSCCADP : 32; /*!< [31..0] TSCCADP */ + } GWTDCAC11_b; + }; + __IM uint32_t RESERVED6[4]; + + union + { + __IOM uint32_t GWTSDCC0; /*!< (@ 0x00000160) GWCA Timestamp Descriptor Chain Configuration + * Register s (GWTSDCCs) (s = 0, 1) */ + + struct + { + __IOM uint32_t TE : 1; /*!< [0..0] TE */ + __IOM uint32_t DCS : 2; /*!< [2..1] DCS */ + uint32_t : 5; + __IOM uint32_t OSID : 3; /*!< [10..8] OSID */ + uint32_t : 21; + } GWTSDCC0_b; + }; + + union + { + __IOM uint32_t GWTSDCC1; /*!< (@ 0x00000164) GWCA Timestamp Descriptor Chain Configuration + * Register s (GWTSDCCs) (s = 0, 1) */ + + struct + { + __IOM uint32_t TE : 1; /*!< [0..0] TE */ + __IOM uint32_t DCS : 2; /*!< [2..1] DCS */ + uint32_t : 5; + __IOM uint32_t OSID : 3; /*!< [10..8] OSID */ + uint32_t : 21; + } GWTSDCC1_b; + }; + __IM uint32_t RESERVED7[6]; + + union + { + __IOM uint32_t GWTSNM; /*!< (@ 0x00000180) GWCA Timestamp Number Monitoring Register (GWTSNM) */ + + struct + { + __IOM uint32_t TNTR : 8; /*!< [7..0] TNTR */ + uint32_t : 24; + } GWTSNM_b; + }; + + union + { + __IOM uint32_t GWTSMNM; /*!< (@ 0x00000184) GWCA Timestamp Maximum Number Monitoring Register + * (GWTSMNM) */ + + struct + { + __IOM uint32_t TMNTR : 8; /*!< [7..0] TMNTR */ + uint32_t : 24; + } GWTSMNM_b; + }; + __IM uint32_t RESERVED8[2]; + + union + { + __IOM uint32_t GWAC; /*!< (@ 0x00000190) GWCA AXI Control Register (GWAC) */ + + struct + { + __IOM uint32_t AMPR : 1; /*!< [0..0] AMPR */ + __IOM uint32_t AMP : 1; /*!< [1..1] AMP */ + uint32_t : 30; + } GWAC_b; + }; + + union + { + __IOM uint32_t GWDCBAC0; /*!< (@ 0x00000194) GWCA Descriptor Chain Base Address Configuration + * Register 0 (GWDCBAC0) */ + + struct + { + __IOM uint32_t DCBAUP : 8; /*!< [7..0] DCBAUP */ + uint32_t : 24; + } GWDCBAC0_b; + }; + + union + { + __IOM uint32_t GWDCBAC1; /*!< (@ 0x00000198) GWCA Descriptor Chain Base Address Configuration + * Register 1 (GWDCBAC1) */ + + struct + { + __IOM uint32_t DCBADP : 32; /*!< [31..0] DCBADP */ + } GWDCBAC1_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t GWMDNC; /*!< (@ 0x000001A0) GWCA Maximum Descriptor Number Configuration + * Register (GWMDNC) */ + + struct + { + __IOM uint32_t RXDMN : 5; /*!< [4..0] RXDMN */ + uint32_t : 3; + __IOM uint32_t TXDMN : 5; /*!< [12..8] TXDMN */ + uint32_t : 3; + __IOM uint32_t TSDMN : 2; /*!< [17..16] TSDMN */ + uint32_t : 14; + } GWMDNC_b; + }; + __IM uint32_t RESERVED10[23]; + __IOM uint32_t GWTRC0; /*!< (@ 0x00000200) GWCA Transmission Request Configuration Register + * i (GWTRCi) (i = 0, 1) */ + __IOM uint32_t GWTRC1; /*!< (@ 0x00000204) GWCA Transmission Request Configuration Register + * i (GWTRCi) (i = 0, 1) */ + __IM uint32_t RESERVED11[62]; + + union + { + __IOM uint32_t GWTPC0; /*!< (@ 0x00000300) GWCA Transmission Pause Configuration Register + * p (GWTPCp) (p = 0, 1) */ + + struct + { + __IOM uint32_t PPPL0 : 1; /*!< [0..0] PPPL0 */ + __IOM uint32_t PPPL1 : 1; /*!< [1..1] PPPL1 */ + __IOM uint32_t PPPL2 : 1; /*!< [2..2] PPPL2 */ + __IOM uint32_t PPPL3 : 1; /*!< [3..3] PPPL3 */ + __IOM uint32_t PPPL4 : 1; /*!< [4..4] PPPL4 */ + __IOM uint32_t PPPL5 : 1; /*!< [5..5] PPPL5 */ + __IOM uint32_t PPPL6 : 1; /*!< [6..6] PPPL6 */ + __IOM uint32_t PPPL7 : 1; /*!< [7..7] PPPL7 */ + __IOM uint32_t PPPL8 : 1; /*!< [8..8] PPPL8 */ + uint32_t : 23; + } GWTPC0_b; + }; + + union + { + __IOM uint32_t GWTPC1; /*!< (@ 0x00000304) GWCA Transmission Pause Configuration Register + * p (GWTPCp) (p = 0, 1) */ + + struct + { + __IOM uint32_t PPPL0 : 1; /*!< [0..0] PPPL0 */ + __IOM uint32_t PPPL1 : 1; /*!< [1..1] PPPL1 */ + __IOM uint32_t PPPL2 : 1; /*!< [2..2] PPPL2 */ + __IOM uint32_t PPPL3 : 1; /*!< [3..3] PPPL3 */ + __IOM uint32_t PPPL4 : 1; /*!< [4..4] PPPL4 */ + __IOM uint32_t PPPL5 : 1; /*!< [5..5] PPPL5 */ + __IOM uint32_t PPPL6 : 1; /*!< [6..6] PPPL6 */ + __IOM uint32_t PPPL7 : 1; /*!< [7..7] PPPL7 */ + __IOM uint32_t PPPL8 : 1; /*!< [8..8] PPPL8 */ + uint32_t : 23; + } GWTPC1_b; + }; + __IM uint32_t RESERVED12[30]; + + union + { + __IOM uint32_t GWARIRM; /*!< (@ 0x00000380) GWCA AXI RAM Initialization Register Monitoring + * Register (GWARIRM) */ + + struct + { + __IOM uint32_t ARIOG : 1; /*!< [0..0] ARIOG */ + __IOM uint32_t ARR : 1; /*!< [1..1] ARR */ + uint32_t : 30; + } GWARIRM_b; + }; + __IM uint32_t RESERVED13[31]; + + union + { + __IOM uint32_t GWDCC0; /*!< (@ 0x00000400) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC0_b; + }; + + union + { + __IOM uint32_t GWDCC1; /*!< (@ 0x00000404) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC1_b; + }; + + union + { + __IOM uint32_t GWDCC2; /*!< (@ 0x00000408) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC2_b; + }; + + union + { + __IOM uint32_t GWDCC3; /*!< (@ 0x0000040C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC3_b; + }; + + union + { + __IOM uint32_t GWDCC4; /*!< (@ 0x00000410) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC4_b; + }; + + union + { + __IOM uint32_t GWDCC5; /*!< (@ 0x00000414) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC5_b; + }; + + union + { + __IOM uint32_t GWDCC6; /*!< (@ 0x00000418) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC6_b; + }; + + union + { + __IOM uint32_t GWDCC7; /*!< (@ 0x0000041C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC7_b; + }; + + union + { + __IOM uint32_t GWDCC8; /*!< (@ 0x00000420) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC8_b; + }; + + union + { + __IOM uint32_t GWDCC9; /*!< (@ 0x00000424) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC9_b; + }; + + union + { + __IOM uint32_t GWDCC10; /*!< (@ 0x00000428) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC10_b; + }; + + union + { + __IOM uint32_t GWDCC11; /*!< (@ 0x0000042C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC11_b; + }; + + union + { + __IOM uint32_t GWDCC12; /*!< (@ 0x00000430) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC12_b; + }; + + union + { + __IOM uint32_t GWDCC13; /*!< (@ 0x00000434) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC13_b; + }; + + union + { + __IOM uint32_t GWDCC14; /*!< (@ 0x00000438) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC14_b; + }; + + union + { + __IOM uint32_t GWDCC15; /*!< (@ 0x0000043C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC15_b; + }; + + union + { + __IOM uint32_t GWDCC16; /*!< (@ 0x00000440) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC16_b; + }; + + union + { + __IOM uint32_t GWDCC17; /*!< (@ 0x00000444) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC17_b; + }; + + union + { + __IOM uint32_t GWDCC18; /*!< (@ 0x00000448) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC18_b; + }; + + union + { + __IOM uint32_t GWDCC19; /*!< (@ 0x0000044C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC19_b; + }; + + union + { + __IOM uint32_t GWDCC20; /*!< (@ 0x00000450) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC20_b; + }; + + union + { + __IOM uint32_t GWDCC21; /*!< (@ 0x00000454) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC21_b; + }; + + union + { + __IOM uint32_t GWDCC22; /*!< (@ 0x00000458) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC22_b; + }; + + union + { + __IOM uint32_t GWDCC23; /*!< (@ 0x0000045C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC23_b; + }; + + union + { + __IOM uint32_t GWDCC24; /*!< (@ 0x00000460) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC24_b; + }; + + union + { + __IOM uint32_t GWDCC25; /*!< (@ 0x00000464) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC25_b; + }; + + union + { + __IOM uint32_t GWDCC26; /*!< (@ 0x00000468) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC26_b; + }; + + union + { + __IOM uint32_t GWDCC27; /*!< (@ 0x0000046C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC27_b; + }; + + union + { + __IOM uint32_t GWDCC28; /*!< (@ 0x00000470) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC28_b; + }; + + union + { + __IOM uint32_t GWDCC29; /*!< (@ 0x00000474) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC29_b; + }; + + union + { + __IOM uint32_t GWDCC30; /*!< (@ 0x00000478) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC30_b; + }; + + union + { + __IOM uint32_t GWDCC31; /*!< (@ 0x0000047C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC31_b; + }; + + union + { + __IOM uint32_t GWDCC32; /*!< (@ 0x00000480) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC32_b; + }; + + union + { + __IOM uint32_t GWDCC33; /*!< (@ 0x00000484) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC33_b; + }; + + union + { + __IOM uint32_t GWDCC34; /*!< (@ 0x00000488) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC34_b; + }; + + union + { + __IOM uint32_t GWDCC35; /*!< (@ 0x0000048C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC35_b; + }; + + union + { + __IOM uint32_t GWDCC36; /*!< (@ 0x00000490) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC36_b; + }; + + union + { + __IOM uint32_t GWDCC37; /*!< (@ 0x00000494) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC37_b; + }; + + union + { + __IOM uint32_t GWDCC38; /*!< (@ 0x00000498) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC38_b; + }; + + union + { + __IOM uint32_t GWDCC39; /*!< (@ 0x0000049C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC39_b; + }; + + union + { + __IOM uint32_t GWDCC40; /*!< (@ 0x000004A0) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC40_b; + }; + + union + { + __IOM uint32_t GWDCC41; /*!< (@ 0x000004A4) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC41_b; + }; + + union + { + __IOM uint32_t GWDCC42; /*!< (@ 0x000004A8) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC42_b; + }; + + union + { + __IOM uint32_t GWDCC43; /*!< (@ 0x000004AC) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC43_b; + }; + + union + { + __IOM uint32_t GWDCC44; /*!< (@ 0x000004B0) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC44_b; + }; + + union + { + __IOM uint32_t GWDCC45; /*!< (@ 0x000004B4) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC45_b; + }; + + union + { + __IOM uint32_t GWDCC46; /*!< (@ 0x000004B8) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC46_b; + }; + + union + { + __IOM uint32_t GWDCC47; /*!< (@ 0x000004BC) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC47_b; + }; + + union + { + __IOM uint32_t GWDCC48; /*!< (@ 0x000004C0) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC48_b; + }; + + union + { + __IOM uint32_t GWDCC49; /*!< (@ 0x000004C4) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC49_b; + }; + + union + { + __IOM uint32_t GWDCC50; /*!< (@ 0x000004C8) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC50_b; + }; + + union + { + __IOM uint32_t GWDCC51; /*!< (@ 0x000004CC) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC51_b; + }; + + union + { + __IOM uint32_t GWDCC52; /*!< (@ 0x000004D0) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC52_b; + }; + + union + { + __IOM uint32_t GWDCC53; /*!< (@ 0x000004D4) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC53_b; + }; + + union + { + __IOM uint32_t GWDCC54; /*!< (@ 0x000004D8) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC54_b; + }; + + union + { + __IOM uint32_t GWDCC55; /*!< (@ 0x000004DC) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC55_b; + }; + + union + { + __IOM uint32_t GWDCC56; /*!< (@ 0x000004E0) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC56_b; + }; + + union + { + __IOM uint32_t GWDCC57; /*!< (@ 0x000004E4) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC57_b; + }; + + union + { + __IOM uint32_t GWDCC58; /*!< (@ 0x000004E8) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC58_b; + }; + + union + { + __IOM uint32_t GWDCC59; /*!< (@ 0x000004EC) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC59_b; + }; + + union + { + __IOM uint32_t GWDCC60; /*!< (@ 0x000004F0) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC60_b; + }; + + union + { + __IOM uint32_t GWDCC61; /*!< (@ 0x000004F4) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC61_b; + }; + + union + { + __IOM uint32_t GWDCC62; /*!< (@ 0x000004F8) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC62_b; + }; + + union + { + __IOM uint32_t GWDCC63; /*!< (@ 0x000004FC) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC63_b; + }; + __IM uint32_t RESERVED14[192]; + + union + { + __IOM uint32_t GWAARSS; /*!< (@ 0x00000800) GWCA AXI Address RAM Searching Setting Register + * (GWAARSS) */ + + struct + { + __IOM uint32_t AARA : 7; /*!< [6..0] AARA */ + uint32_t : 25; + } GWAARSS_b; + }; + + union + { + __IOM uint32_t GWAARSR0; /*!< (@ 0x00000804) GWCA AXI Address RAM Searching Result Register + * 0 (GWAARSR0) */ + + struct + { + __IOM uint32_t ACARU : 8; /*!< [7..0] ACARU */ + uint32_t : 8; + __IOM uint32_t AARSEF : 1; /*!< [16..16] AARSEF */ + __IOM uint32_t AARSSF : 1; /*!< [17..17] AARSSF */ + uint32_t : 13; + __IOM uint32_t AARS : 1; /*!< [31..31] AARS */ + } GWAARSR0_b; + }; + + union + { + __IOM uint32_t GWAARSR1; /*!< (@ 0x00000808) GWCA AXI Address RAM Searching Result Register + * 1 (GWAARSR1) */ + + struct + { + __IOM uint32_t ACARD : 32; /*!< [31..0] ACARD */ + } GWAARSR1_b; + }; + __IM uint32_t RESERVED15[13]; + + union + { + __IOM uint32_t GWIDAUAS0; /*!< (@ 0x00000840) GWCA Incremental Data Area Used Area Size Register + * i (GWIDAUASi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAUAS : 24; /*!< [23..0] IDAUAS */ + uint32_t : 8; + } GWIDAUAS0_b; + }; + + union + { + __IOM uint32_t GWIDAUAS1; /*!< (@ 0x00000844) GWCA Incremental Data Area Used Area Size Register + * i (GWIDAUASi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAUAS : 24; /*!< [23..0] IDAUAS */ + uint32_t : 8; + } GWIDAUAS1_b; + }; + + union + { + __IOM uint32_t GWIDAUAS2; /*!< (@ 0x00000848) GWCA Incremental Data Area Used Area Size Register + * i (GWIDAUASi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAUAS : 24; /*!< [23..0] IDAUAS */ + uint32_t : 8; + } GWIDAUAS2_b; + }; + + union + { + __IOM uint32_t GWIDAUAS3; /*!< (@ 0x0000084C) GWCA Incremental Data Area Used Area Size Register + * i (GWIDAUASi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAUAS : 24; /*!< [23..0] IDAUAS */ + uint32_t : 8; + } GWIDAUAS3_b; + }; + __IM uint32_t RESERVED16[12]; + + union + { + __IOM uint32_t GWIDASM0; /*!< (@ 0x00000880) GWCA Incremental Data Area Size Monitoring Register + * i (GWIDASMi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAS : 24; /*!< [23..0] IDAS */ + uint32_t : 8; + } GWIDASM0_b; + }; + + union + { + __IOM uint32_t GWIDASM1; /*!< (@ 0x00000884) GWCA Incremental Data Area Size Monitoring Register + * i (GWIDASMi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAS : 24; /*!< [23..0] IDAS */ + uint32_t : 8; + } GWIDASM1_b; + }; + + union + { + __IOM uint32_t GWIDASM2; /*!< (@ 0x00000888) GWCA Incremental Data Area Size Monitoring Register + * i (GWIDASMi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAS : 24; /*!< [23..0] IDAS */ + uint32_t : 8; + } GWIDASM2_b; + }; + + union + { + __IOM uint32_t GWIDASM3; /*!< (@ 0x0000088C) GWCA Incremental Data Area Size Monitoring Register + * i (GWIDASMi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAS : 24; /*!< [23..0] IDAS */ + uint32_t : 8; + } GWIDASM3_b; + }; + __IM uint32_t RESERVED17[28]; + + union + { + __IOM uint32_t GWIDASAM00; /*!< (@ 0x00000900) GWCA Incremental Data Area Start Address Monitoring + * Register 0i (GWIDASAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAU : 8; /*!< [7..0] IDASAU */ + uint32_t : 24; + } GWIDASAM00_b; + }; + + union + { + __IOM uint32_t GWIDASAM10; /*!< (@ 0x00000904) GWCA Incremental Data Area Start Address Monitoring + * Register 1i (GWIDASAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAL : 32; /*!< [31..0] IDASAL */ + } GWIDASAM10_b; + }; + + union + { + __IOM uint32_t GWIDASAM01; /*!< (@ 0x00000908) GWCA Incremental Data Area Start Address Monitoring + * Register 0i (GWIDASAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAU : 8; /*!< [7..0] IDASAU */ + uint32_t : 24; + } GWIDASAM01_b; + }; + + union + { + __IOM uint32_t GWIDASAM11; /*!< (@ 0x0000090C) GWCA Incremental Data Area Start Address Monitoring + * Register 1i (GWIDASAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAL : 32; /*!< [31..0] IDASAL */ + } GWIDASAM11_b; + }; + + union + { + __IOM uint32_t GWIDASAM02; /*!< (@ 0x00000910) GWCA Incremental Data Area Start Address Monitoring + * Register 0i (GWIDASAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAU : 8; /*!< [7..0] IDASAU */ + uint32_t : 24; + } GWIDASAM02_b; + }; + + union + { + __IOM uint32_t GWIDASAM12; /*!< (@ 0x00000914) GWCA Incremental Data Area Start Address Monitoring + * Register 1i (GWIDASAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAL : 32; /*!< [31..0] IDASAL */ + } GWIDASAM12_b; + }; + + union + { + __IOM uint32_t GWIDASAM03; /*!< (@ 0x00000918) GWCA Incremental Data Area Start Address Monitoring + * Register 0i (GWIDASAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAU : 8; /*!< [7..0] IDASAU */ + uint32_t : 24; + } GWIDASAM03_b; + }; + + union + { + __IOM uint32_t GWIDASAM13; /*!< (@ 0x0000091C) GWCA Incremental Data Area Start Address Monitoring + * Register 1i (GWIDASAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAL : 32; /*!< [31..0] IDASAL */ + } GWIDASAM13_b; + }; + __IM uint32_t RESERVED18[24]; + + union + { + __IOM uint32_t GWIDACAM00; /*!< (@ 0x00000980) GWCA Incremental Data Area Current Address Monitoring + * Register 0i (GWIDACAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAU : 8; /*!< [7..0] IDACAU */ + uint32_t : 24; + } GWIDACAM00_b; + }; + + union + { + __IOM uint32_t GWIDACAM10; /*!< (@ 0x00000984) GWCA Incremental Data Area Current Address Monitoring + * Register 1i (GWIDACAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAL : 32; /*!< [31..0] IDACAL */ + } GWIDACAM10_b; + }; + + union + { + __IOM uint32_t GWIDACAM01; /*!< (@ 0x00000988) GWCA Incremental Data Area Current Address Monitoring + * Register 0i (GWIDACAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAU : 8; /*!< [7..0] IDACAU */ + uint32_t : 24; + } GWIDACAM01_b; + }; + + union + { + __IOM uint32_t GWIDACAM11; /*!< (@ 0x0000098C) GWCA Incremental Data Area Current Address Monitoring + * Register 1i (GWIDACAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAL : 32; /*!< [31..0] IDACAL */ + } GWIDACAM11_b; + }; + + union + { + __IOM uint32_t GWIDACAM02; /*!< (@ 0x00000990) GWCA Incremental Data Area Current Address Monitoring + * Register 0i (GWIDACAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAU : 8; /*!< [7..0] IDACAU */ + uint32_t : 24; + } GWIDACAM02_b; + }; + + union + { + __IOM uint32_t GWIDACAM12; /*!< (@ 0x00000994) GWCA Incremental Data Area Current Address Monitoring + * Register 1i (GWIDACAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAL : 32; /*!< [31..0] IDACAL */ + } GWIDACAM12_b; + }; + + union + { + __IOM uint32_t GWIDACAM03; /*!< (@ 0x00000998) GWCA Incremental Data Area Current Address Monitoring + * Register 0i (GWIDACAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAU : 8; /*!< [7..0] IDACAU */ + uint32_t : 24; + } GWIDACAM03_b; + }; + + union + { + __IOM uint32_t GWIDACAM13; /*!< (@ 0x0000099C) GWCA Incremental Data Area Current Address Monitoring + * Register 1i (GWIDACAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAL : 32; /*!< [31..0] IDACAL */ + } GWIDACAM13_b; + }; + __IM uint32_t RESERVED19[24]; + + union + { + __IOM uint32_t GWGRLC; /*!< (@ 0x00000A00) GWCA Global Rate Limiter Configuration Register + * (GWGRLC) */ + + struct + { + __IOM uint32_t GRLIV : 16; /*!< [15..0] GRLIV */ + __IOM uint32_t GRLE : 1; /*!< [16..16] GRLE */ + __IOM uint32_t GRLULRS : 1; /*!< [17..17] GRLULRS */ + uint32_t : 14; + } GWGRLC_b; + }; + + union + { + __IOM uint32_t GWGRLULC; /*!< (@ 0x00000A04) GWCA Global Rate Limiter Upper Limit Configuration + * Register (GWGRLULC) */ + + struct + { + __IOM uint32_t GRLUL : 24; /*!< [23..0] GRLUL */ + uint32_t : 8; + } GWGRLULC_b; + }; + __IM uint32_t RESERVED20[30]; + + union + { + __IOM uint32_t GWRLC0; /*!< (@ 0x00000A80) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC0_b; + }; + + union + { + __IOM uint32_t GWRLULC0; /*!< (@ 0x00000A84) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC0_b; + }; + + union + { + __IOM uint32_t GWRLC1; /*!< (@ 0x00000A88) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC1_b; + }; + + union + { + __IOM uint32_t GWRLULC1; /*!< (@ 0x00000A8C) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC1_b; + }; + + union + { + __IOM uint32_t GWRLC2; /*!< (@ 0x00000A90) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC2_b; + }; + + union + { + __IOM uint32_t GWRLULC2; /*!< (@ 0x00000A94) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC2_b; + }; + + union + { + __IOM uint32_t GWRLC3; /*!< (@ 0x00000A98) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC3_b; + }; + + union + { + __IOM uint32_t GWRLULC3; /*!< (@ 0x00000A9C) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC3_b; + }; + + union + { + __IOM uint32_t GWRLC4; /*!< (@ 0x00000AA0) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC4_b; + }; + + union + { + __IOM uint32_t GWRLULC4; /*!< (@ 0x00000AA4) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC4_b; + }; + + union + { + __IOM uint32_t GWRLC5; /*!< (@ 0x00000AA8) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC5_b; + }; + + union + { + __IOM uint32_t GWRLULC5; /*!< (@ 0x00000AAC) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC5_b; + }; + + union + { + __IOM uint32_t GWRLC6; /*!< (@ 0x00000AB0) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC6_b; + }; + + union + { + __IOM uint32_t GWRLULC6; /*!< (@ 0x00000AB4) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC6_b; + }; + + union + { + __IOM uint32_t GWRLC7; /*!< (@ 0x00000AB8) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC7_b; + }; + + union + { + __IOM uint32_t GWRLULC7; /*!< (@ 0x00000ABC) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC7_b; + }; + __IM uint32_t RESERVED21[48]; + + union + { + __IOM uint32_t GWIDPC; /*!< (@ 0x00000B80) GWCA Interrupt Delay Prescaler Configuration + * Register (GWIDPC) */ + + struct + { + __IOM uint32_t IDPV : 10; /*!< [9..0] IDPV */ + uint32_t : 22; + } GWIDPC_b; + }; + __IM uint32_t RESERVED22[31]; + + union + { + __IOM uint32_t GWIDC0; /*!< (@ 0x00000C00) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC0_b; + }; + + union + { + __IOM uint32_t GWIDC1; /*!< (@ 0x00000C04) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC1_b; + }; + + union + { + __IOM uint32_t GWIDC2; /*!< (@ 0x00000C08) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC2_b; + }; + + union + { + __IOM uint32_t GWIDC3; /*!< (@ 0x00000C0C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC3_b; + }; + + union + { + __IOM uint32_t GWIDC4; /*!< (@ 0x00000C10) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC4_b; + }; + + union + { + __IOM uint32_t GWIDC5; /*!< (@ 0x00000C14) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC5_b; + }; + + union + { + __IOM uint32_t GWIDC6; /*!< (@ 0x00000C18) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC6_b; + }; + + union + { + __IOM uint32_t GWIDC7; /*!< (@ 0x00000C1C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC7_b; + }; + + union + { + __IOM uint32_t GWIDC8; /*!< (@ 0x00000C20) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC8_b; + }; + + union + { + __IOM uint32_t GWIDC9; /*!< (@ 0x00000C24) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC9_b; + }; + + union + { + __IOM uint32_t GWIDC10; /*!< (@ 0x00000C28) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC10_b; + }; + + union + { + __IOM uint32_t GWIDC11; /*!< (@ 0x00000C2C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC11_b; + }; + + union + { + __IOM uint32_t GWIDC12; /*!< (@ 0x00000C30) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC12_b; + }; + + union + { + __IOM uint32_t GWIDC13; /*!< (@ 0x00000C34) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC13_b; + }; + + union + { + __IOM uint32_t GWIDC14; /*!< (@ 0x00000C38) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC14_b; + }; + + union + { + __IOM uint32_t GWIDC15; /*!< (@ 0x00000C3C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC15_b; + }; + + union + { + __IOM uint32_t GWIDC16; /*!< (@ 0x00000C40) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC16_b; + }; + + union + { + __IOM uint32_t GWIDC17; /*!< (@ 0x00000C44) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC17_b; + }; + + union + { + __IOM uint32_t GWIDC18; /*!< (@ 0x00000C48) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC18_b; + }; + + union + { + __IOM uint32_t GWIDC19; /*!< (@ 0x00000C4C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC19_b; + }; + + union + { + __IOM uint32_t GWIDC20; /*!< (@ 0x00000C50) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC20_b; + }; + + union + { + __IOM uint32_t GWIDC21; /*!< (@ 0x00000C54) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC21_b; + }; + + union + { + __IOM uint32_t GWIDC22; /*!< (@ 0x00000C58) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC22_b; + }; + + union + { + __IOM uint32_t GWIDC23; /*!< (@ 0x00000C5C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC23_b; + }; + + union + { + __IOM uint32_t GWIDC24; /*!< (@ 0x00000C60) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC24_b; + }; + + union + { + __IOM uint32_t GWIDC25; /*!< (@ 0x00000C64) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC25_b; + }; + + union + { + __IOM uint32_t GWIDC26; /*!< (@ 0x00000C68) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC26_b; + }; + + union + { + __IOM uint32_t GWIDC27; /*!< (@ 0x00000C6C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC27_b; + }; + + union + { + __IOM uint32_t GWIDC28; /*!< (@ 0x00000C70) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC28_b; + }; + + union + { + __IOM uint32_t GWIDC29; /*!< (@ 0x00000C74) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC29_b; + }; + + union + { + __IOM uint32_t GWIDC30; /*!< (@ 0x00000C78) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC30_b; + }; + + union + { + __IOM uint32_t GWIDC31; /*!< (@ 0x00000C7C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC31_b; + }; + + union + { + __IOM uint32_t GWIDC32; /*!< (@ 0x00000C80) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC32_b; + }; + + union + { + __IOM uint32_t GWIDC33; /*!< (@ 0x00000C84) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC33_b; + }; + + union + { + __IOM uint32_t GWIDC34; /*!< (@ 0x00000C88) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC34_b; + }; + + union + { + __IOM uint32_t GWIDC35; /*!< (@ 0x00000C8C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC35_b; + }; + + union + { + __IOM uint32_t GWIDC36; /*!< (@ 0x00000C90) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC36_b; + }; + + union + { + __IOM uint32_t GWIDC37; /*!< (@ 0x00000C94) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC37_b; + }; + + union + { + __IOM uint32_t GWIDC38; /*!< (@ 0x00000C98) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC38_b; + }; + + union + { + __IOM uint32_t GWIDC39; /*!< (@ 0x00000C9C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC39_b; + }; + + union + { + __IOM uint32_t GWIDC40; /*!< (@ 0x00000CA0) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC40_b; + }; + + union + { + __IOM uint32_t GWIDC41; /*!< (@ 0x00000CA4) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC41_b; + }; + + union + { + __IOM uint32_t GWIDC42; /*!< (@ 0x00000CA8) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC42_b; + }; + + union + { + __IOM uint32_t GWIDC43; /*!< (@ 0x00000CAC) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC43_b; + }; + + union + { + __IOM uint32_t GWIDC44; /*!< (@ 0x00000CB0) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC44_b; + }; + + union + { + __IOM uint32_t GWIDC45; /*!< (@ 0x00000CB4) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC45_b; + }; + + union + { + __IOM uint32_t GWIDC46; /*!< (@ 0x00000CB8) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC46_b; + }; + + union + { + __IOM uint32_t GWIDC47; /*!< (@ 0x00000CBC) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC47_b; + }; + + union + { + __IOM uint32_t GWIDC48; /*!< (@ 0x00000CC0) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC48_b; + }; + + union + { + __IOM uint32_t GWIDC49; /*!< (@ 0x00000CC4) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC49_b; + }; + + union + { + __IOM uint32_t GWIDC50; /*!< (@ 0x00000CC8) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC50_b; + }; + + union + { + __IOM uint32_t GWIDC51; /*!< (@ 0x00000CCC) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC51_b; + }; + + union + { + __IOM uint32_t GWIDC52; /*!< (@ 0x00000CD0) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC52_b; + }; + + union + { + __IOM uint32_t GWIDC53; /*!< (@ 0x00000CD4) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC53_b; + }; + + union + { + __IOM uint32_t GWIDC54; /*!< (@ 0x00000CD8) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC54_b; + }; + + union + { + __IOM uint32_t GWIDC55; /*!< (@ 0x00000CDC) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC55_b; + }; + + union + { + __IOM uint32_t GWIDC56; /*!< (@ 0x00000CE0) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC56_b; + }; + + union + { + __IOM uint32_t GWIDC57; /*!< (@ 0x00000CE4) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC57_b; + }; + + union + { + __IOM uint32_t GWIDC58; /*!< (@ 0x00000CE8) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC58_b; + }; + + union + { + __IOM uint32_t GWIDC59; /*!< (@ 0x00000CEC) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC59_b; + }; + + union + { + __IOM uint32_t GWIDC60; /*!< (@ 0x00000CF0) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC60_b; + }; + + union + { + __IOM uint32_t GWIDC61; /*!< (@ 0x00000CF4) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC61_b; + }; + + union + { + __IOM uint32_t GWIDC62; /*!< (@ 0x00000CF8) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC62_b; + }; + + union + { + __IOM uint32_t GWIDC63; /*!< (@ 0x00000CFC) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC63_b; + }; + + union + { + __IOM uint32_t GWIDC64; /*!< (@ 0x00000D00) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC64_b; + }; + __IM uint32_t RESERVED23[191]; + + union + { + __IOM uint32_t GWRDCN; /*!< (@ 0x00001000) GWCA Received Data Counter Register (GWRDCN) */ + + struct + { + __IOM uint32_t RDN : 32; /*!< [31..0] RDN */ + } GWRDCN_b; + }; + + union + { + __IOM uint32_t GWTDCN; /*!< (@ 0x00001004) GWCA Transmitted Data Counter Register (GWTDCN) */ + + struct + { + __IOM uint32_t TDN : 32; /*!< [31..0] TDN */ + } GWTDCN_b; + }; + + union + { + __IOM uint32_t GWTSCN; /*!< (@ 0x00001008) GWCA Timestamp Counter Register (GWTSCN) */ + + struct + { + __IOM uint32_t TN : 32; /*!< [31..0] TN */ + } GWTSCN_b; + }; + + union + { + __IOM uint32_t GWTSOVFECN; /*!< (@ 0x0000100C) GWCA Timestamp Overflow Error Counter Register + * (GWTSOVFECN) */ + + struct + { + __IOM uint32_t TSOVFEN : 16; /*!< [15..0] TSOVFEN */ + uint32_t : 16; + } GWTSOVFECN_b; + }; + + union + { + __IOM uint32_t GWUSMFSECN; /*!< (@ 0x00001010) GWCA Under Switch Minimum Frame Size Error Counter + * Register (GWUSMFSECN) */ + + struct + { + __IOM uint32_t USMFSEN : 16; /*!< [15..0] USMFSEN */ + uint32_t : 16; + } GWUSMFSECN_b; + }; + + union + { + __IOM uint32_t GWTFECN; /*!< (@ 0x00001014) GWCA TAG Filtering Error Counter Register (GWTFECN) */ + + struct + { + __IOM uint32_t TFEN : 16; /*!< [15..0] TFEN */ + uint32_t : 16; + } GWTFECN_b; + }; + + union + { + __IOM uint32_t GWSEQECN; /*!< (@ 0x00001018) GWCA Sequence Error Counter Register (GWSEQECN) */ + + struct + { + __IOM uint32_t SEQEN : 16; /*!< [15..0] SEQEN */ + uint32_t : 16; + } GWSEQECN_b; + }; + __IM uint32_t RESERVED24; + + union + { + __IOM uint32_t GWTXDNECN; /*!< (@ 0x00001020) GWCA TX Descriptor Number Error Counter Register + * (GWTXDNECN) */ + + struct + { + __IOM uint32_t TXDNEN : 16; /*!< [15..0] TXDNEN */ + uint32_t : 16; + } GWTXDNECN_b; + }; + + union + { + __IOM uint32_t GWFSECN; /*!< (@ 0x00001024) GWCA Frame Size Error Counter Register (GWFSECN) */ + + struct + { + __IOM uint32_t FSEN : 16; /*!< [15..0] FSEN */ + uint32_t : 16; + } GWFSECN_b; + }; + + union + { + __IOM uint32_t GWTDFECN; /*!< (@ 0x00001028) GWCA Timestamp Descriptor Full Error Counter + * Register (GWTDFECN) */ + + struct + { + __IOM uint32_t TDFEN : 16; /*!< [15..0] TDFEN */ + uint32_t : 16; + } GWTDFECN_b; + }; + + union + { + __IOM uint32_t GWTSDNECN; /*!< (@ 0x0000102C) GWCA Timestamp Descriptor Number Error Counter + * Register (GWTSDNECN) */ + + struct + { + __IOM uint32_t TSDNEN : 16; /*!< [15..0] TSDNEN */ + uint32_t : 16; + } GWTSDNECN_b; + }; + + union + { + __IOM uint32_t GWDQOECN; /*!< (@ 0x00001030) GWCA Descriptor Queue Overflow Error Counter + * Register (GWDQOECN) */ + + struct + { + __IOM uint32_t DQOEN : 16; /*!< [15..0] DQOEN */ + uint32_t : 16; + } GWDQOECN_b; + }; + + union + { + __IOM uint32_t GWDQSECN; /*!< (@ 0x00001034) GWCA Descriptor Queue Security Error Counter + * Register (GWDQSECN) */ + + struct + { + __IOM uint32_t DQSEN : 16; /*!< [15..0] DQSEN */ + uint32_t : 16; + } GWDQSECN_b; + }; + + union + { + __IOM uint32_t GWDFECN; /*!< (@ 0x00001038) GWCA Descriptor Full Error Counter Register (GWDFECN) */ + + struct + { + __IOM uint32_t DFEN : 16; /*!< [15..0] DFEN */ + uint32_t : 16; + } GWDFECN_b; + }; + + union + { + __IOM uint32_t GWDSECN; /*!< (@ 0x0000103C) GWCA Descriptor Security Error Counter Register + * (GWDSECN) */ + + struct + { + __IOM uint32_t DSEN : 16; /*!< [15..0] DSEN */ + uint32_t : 16; + } GWDSECN_b; + }; + + union + { + __IOM uint32_t GWDSZECN; /*!< (@ 0x00001040) GWCA Data Size Error Counter Register (GWDSZECN) */ + + struct + { + __IOM uint32_t DSZEN : 16; /*!< [15..0] DSZEN */ + uint32_t : 16; + } GWDSZECN_b; + }; + + union + { + __IOM uint32_t GWDCTECN; /*!< (@ 0x00001044) GWCA Descriptor Chain Type Error Counter Register + * (GWDCTECN) */ + + struct + { + __IOM uint32_t DCTEN : 16; /*!< [15..0] DCTEN */ + uint32_t : 16; + } GWDCTECN_b; + }; + + union + { + __IOM uint32_t GWRXDNECN; /*!< (@ 0x00001048) GWCA RX Descriptor Number Error Counter Register + * (GWRXDNECN) */ + + struct + { + __IOM uint32_t RXDNEN : 16; /*!< [15..0] RXDNEN */ + uint32_t : 16; + } GWRXDNECN_b; + }; + __IM uint32_t RESERVED25[45]; + __IOM uint32_t GWDIS0; /*!< (@ 0x00001100) GWCA Data Interrupt Status Register i (GWDISi) + * (i = 0, 1) */ + __IOM uint32_t GWDIE0; /*!< (@ 0x00001104) GWCA Data Interrupt Enable Register i (GWDIEi) + * (i = 0, 1) */ + __IOM uint32_t GWDID0; /*!< (@ 0x00001108) GWCA Data Interrupt Disable Register i (GWDIDi) + * (i = 0, 1) */ + __IOM uint32_t GWDIDS0; /*!< (@ 0x0000110C) GWCA Data Interrupt Delayed Status Register i + * (GWDIDSi) (i = 0, 1) */ + __IOM uint32_t GWDIS1; /*!< (@ 0x00001110) GWCA Data Interrupt Status Register i (GWDISi) + * (i = 0, 1) */ + __IOM uint32_t GWDIE1; /*!< (@ 0x00001114) GWCA Data Interrupt Enable Register i (GWDIEi) + * (i = 0, 1) */ + __IOM uint32_t GWDID1; /*!< (@ 0x00001118) GWCA Data Interrupt Disable Register i (GWDIDi) + * (i = 0, 1) */ + __IOM uint32_t GWDIDS1; /*!< (@ 0x0000111C) GWCA Data Interrupt Delayed Status Register i + * (GWDIDSi) (i = 0, 1) */ + __IM uint32_t RESERVED26[24]; + + union + { + __IOM uint32_t GWTSDIS; /*!< (@ 0x00001180) GWCA Timestamp Data Interrupt Status Register + * (GWTSDIS) */ + + struct + { + __IOM uint32_t TSDIS0 : 1; /*!< [0..0] TSDIS0 */ + __IOM uint32_t TSDIS1 : 1; /*!< [1..1] TSDIS1 */ + uint32_t : 30; + } GWTSDIS_b; + }; + + union + { + __IOM uint32_t GWTSDIE; /*!< (@ 0x00001184) GWCA Timestamp Data Interrupt Enable Register + * (GWTSDIE) */ + + struct + { + __IOM uint32_t TSDIE0 : 1; /*!< [0..0] TSDIE0 */ + __IOM uint32_t TSDIE1 : 1; /*!< [1..1] TSDIE1 */ + uint32_t : 30; + } GWTSDIE_b; + }; + + union + { + __IOM uint32_t GWTSDID; /*!< (@ 0x00001188) GWCA Timestamp Data Interrupt Disable Register + * (GWTSDID) */ + + struct + { + __IOM uint32_t TSDID0 : 1; /*!< [0..0] TSDID0 */ + __IOM uint32_t TSDID1 : 1; /*!< [1..1] TSDID1 */ + uint32_t : 30; + } GWTSDID_b; + }; + __IM uint32_t RESERVED27; + + union + { + __IOM uint32_t GWEIS0; /*!< (@ 0x00001190) GWCA Error Interrupt Status Register 0 (GWEIS0) */ + + struct + { + __IOM uint32_t AES : 1; /*!< [0..0] AES */ + __IOM uint32_t DECCES : 1; /*!< [1..1] DECCES */ + __IOM uint32_t TECCES : 1; /*!< [2..2] TECCES */ + __IOM uint32_t PECCES : 1; /*!< [3..3] PECCES */ + __IOM uint32_t DSECCES : 1; /*!< [4..4] DSECCES */ + __IOM uint32_t MECCES : 1; /*!< [5..5] MECCES */ + __IOM uint32_t AECCES : 1; /*!< [6..6] AECCES */ + __IOM uint32_t TSECCES : 1; /*!< [7..7] TSECCES */ + __IOM uint32_t L23UECCES : 1; /*!< [8..8] L23UECCES */ + __IOM uint32_t TSOVFES : 1; /*!< [9..9] TSOVFES */ + __IOM uint32_t USMFSES : 1; /*!< [10..10] USMFSES */ + __IOM uint32_t TFES : 1; /*!< [11..11] TFES */ + __IOM uint32_t SEQES : 1; /*!< [12..12] SEQES */ + uint32_t : 1; + __IOM uint32_t TXDNES : 1; /*!< [14..14] TXDNES */ + __IOM uint32_t TSHES : 1; /*!< [15..15] TSHES */ + __IOM uint32_t FSES0 : 1; /*!< [16..16] FSES0 */ + __IOM uint32_t FSES1 : 1; /*!< [17..17] FSES1 */ + __IOM uint32_t FSES2 : 1; /*!< [18..18] FSES2 */ + __IOM uint32_t FSES3 : 1; /*!< [19..19] FSES3 */ + __IOM uint32_t FSES4 : 1; /*!< [20..20] FSES4 */ + __IOM uint32_t FSES5 : 1; /*!< [21..21] FSES5 */ + __IOM uint32_t FSES6 : 1; /*!< [22..22] FSES6 */ + __IOM uint32_t FSES7 : 1; /*!< [23..23] FSES7 */ + __IOM uint32_t TDFES0 : 1; /*!< [24..24] TDFES0 */ + __IOM uint32_t TDFES1 : 1; /*!< [25..25] TDFES1 */ + uint32_t : 2; + __IOM uint32_t TSDNES0 : 1; /*!< [28..28] TSDNES0 */ + __IOM uint32_t TSDNES1 : 1; /*!< [29..29] TSDNES1 */ + uint32_t : 2; + } GWEIS0_b; + }; + + union + { + __IOM uint32_t GWEIE0; /*!< (@ 0x00001194) GWCA Error Interrupt Enable Register 0 (GWEIE0) */ + + struct + { + __IOM uint32_t AEE : 1; /*!< [0..0] AEE */ + __IOM uint32_t DECCEE : 1; /*!< [1..1] DECCEE */ + __IOM uint32_t TECCEE : 1; /*!< [2..2] TECCEE */ + __IOM uint32_t PECCEE : 1; /*!< [3..3] PECCEE */ + __IOM uint32_t DSECCEE : 1; /*!< [4..4] DSECCEE */ + __IOM uint32_t MECCEE : 1; /*!< [5..5] MECCEE */ + __IOM uint32_t AECCEE : 1; /*!< [6..6] AECCEE */ + __IOM uint32_t TSECCEE : 1; /*!< [7..7] TSECCEE */ + __IOM uint32_t L23UECCEE : 1; /*!< [8..8] L23UECCEE */ + __IOM uint32_t TSOVFEE : 1; /*!< [9..9] TSOVFEE */ + __IOM uint32_t USMFSEE : 1; /*!< [10..10] USMFSEE */ + __IOM uint32_t TFEE : 1; /*!< [11..11] TFEE */ + __IOM uint32_t SEQEE : 1; /*!< [12..12] SEQEE */ + uint32_t : 1; + __IOM uint32_t TXDNEE : 1; /*!< [14..14] TXDNEE */ + __IOM uint32_t TSHEE : 1; /*!< [15..15] TSHEE */ + __IOM uint32_t FSEE0 : 1; /*!< [16..16] FSEE0 */ + __IOM uint32_t FSEE1 : 1; /*!< [17..17] FSEE1 */ + __IOM uint32_t FSEE2 : 1; /*!< [18..18] FSEE2 */ + __IOM uint32_t FSEE3 : 1; /*!< [19..19] FSEE3 */ + __IOM uint32_t FSEE4 : 1; /*!< [20..20] FSEE4 */ + __IOM uint32_t FSEE5 : 1; /*!< [21..21] FSEE5 */ + __IOM uint32_t FSEE6 : 1; /*!< [22..22] FSEE6 */ + __IOM uint32_t FSEE7 : 1; /*!< [23..23] FSEE7 */ + __IOM uint32_t TDFEE0 : 1; /*!< [24..24] TDFEE0 */ + __IOM uint32_t TDFEE1 : 1; /*!< [25..25] TDFEE1 */ + uint32_t : 2; + __IOM uint32_t TSDNEE0 : 1; /*!< [28..28] TSDNEE0 */ + __IOM uint32_t TSDNEE1 : 1; /*!< [29..29] TSDNEE1 */ + uint32_t : 2; + } GWEIE0_b; + }; + + union + { + __IOM uint32_t GWEID0; /*!< (@ 0x00001198) GWCA Error Interrupt Disable Register 0 (GWEID0) */ + + struct + { + __IOM uint32_t AED : 1; /*!< [0..0] AED */ + __IOM uint32_t TECCED : 1; /*!< [1..1] TECCED */ + __IOM uint32_t DECCED : 1; /*!< [2..2] DECCED */ + __IOM uint32_t PECCED : 1; /*!< [3..3] PECCED */ + __IOM uint32_t DSECCED : 1; /*!< [4..4] DSECCED */ + __IOM uint32_t MECCED : 1; /*!< [5..5] MECCED */ + __IOM uint32_t AECCED : 1; /*!< [6..6] AECCED */ + __IOM uint32_t TSECCED : 1; /*!< [7..7] TSECCED */ + __IOM uint32_t L23UECCED : 1; /*!< [8..8] L23UECCED */ + __IOM uint32_t TSOVFED : 1; /*!< [9..9] TSOVFED */ + __IOM uint32_t USMFSED : 1; /*!< [10..10] USMFSED */ + __IOM uint32_t TFED : 1; /*!< [11..11] TFED */ + __IOM uint32_t SEQED : 1; /*!< [12..12] SEQED */ + __IOM uint32_t IIPED : 1; /*!< [13..13] IIPED */ + __IOM uint32_t TXDNED : 1; /*!< [14..14] TXDNED */ + __IOM uint32_t TSHED : 1; /*!< [15..15] TSHED */ + __IOM uint32_t FSED0 : 1; /*!< [16..16] FSED0 */ + __IOM uint32_t FSED1 : 1; /*!< [17..17] FSED1 */ + __IOM uint32_t FSED2 : 1; /*!< [18..18] FSED2 */ + __IOM uint32_t FSED3 : 1; /*!< [19..19] FSED3 */ + __IOM uint32_t FSED4 : 1; /*!< [20..20] FSED4 */ + __IOM uint32_t FSED5 : 1; /*!< [21..21] FSED5 */ + __IOM uint32_t FSED6 : 1; /*!< [22..22] FSED6 */ + __IOM uint32_t FSED7 : 1; /*!< [23..23] FSED7 */ + __IOM uint32_t TDFED0 : 1; /*!< [24..24] TDFED0 */ + __IOM uint32_t TDFED1 : 1; /*!< [25..25] TDFED1 */ + uint32_t : 2; + __IOM uint32_t TSDNED0 : 1; /*!< [28..28] TSDNED0 */ + __IOM uint32_t TSDNED1 : 1; /*!< [29..29] TSDNED1 */ + uint32_t : 2; + } GWEID0_b; + }; + __IM uint32_t RESERVED28; + + union + { + __IOM uint32_t GWEIS1; /*!< (@ 0x000011A0) GWCA Error Interrupt Status Register 1 (GWEIS1) */ + + struct + { + __IOM uint32_t DQOES0 : 1; /*!< [0..0] DQOES0 */ + __IOM uint32_t DQOES1 : 1; /*!< [1..1] DQOES1 */ + __IOM uint32_t DQOES2 : 1; /*!< [2..2] DQOES2 */ + __IOM uint32_t DQOES3 : 1; /*!< [3..3] DQOES3 */ + __IOM uint32_t DQOES4 : 1; /*!< [4..4] DQOES4 */ + __IOM uint32_t DQOES5 : 1; /*!< [5..5] DQOES5 */ + __IOM uint32_t DQOES6 : 1; /*!< [6..6] DQOES6 */ + __IOM uint32_t DQOES7 : 1; /*!< [7..7] DQOES7 */ + uint32_t : 8; + __IOM uint32_t DQSES0 : 1; /*!< [16..16] DQSES0 */ + __IOM uint32_t DQSES1 : 1; /*!< [17..17] DQSES1 */ + __IOM uint32_t DQSES2 : 1; /*!< [18..18] DQSES2 */ + __IOM uint32_t DQSES3 : 1; /*!< [19..19] DQSES3 */ + __IOM uint32_t DQSES4 : 1; /*!< [20..20] DQSES4 */ + __IOM uint32_t DQSES5 : 1; /*!< [21..21] DQSES5 */ + __IOM uint32_t DQSES6 : 1; /*!< [22..22] DQSES6 */ + __IOM uint32_t DQSES7 : 1; /*!< [23..23] DQSES7 */ + uint32_t : 8; + } GWEIS1_b; + }; + + union + { + __IOM uint32_t GWEIE1; /*!< (@ 0x000011A4) GWCA Error Interrupt Enable Register 1 (GWEIE1) */ + + struct + { + __IOM uint32_t DQOEE0 : 1; /*!< [0..0] DQOEE0 */ + __IOM uint32_t DQOEE1 : 1; /*!< [1..1] DQOEE1 */ + __IOM uint32_t DQOEE2 : 1; /*!< [2..2] DQOEE2 */ + __IOM uint32_t DQOEE3 : 1; /*!< [3..3] DQOEE3 */ + __IOM uint32_t DQOEE4 : 1; /*!< [4..4] DQOEE4 */ + __IOM uint32_t DQOEE5 : 1; /*!< [5..5] DQOEE5 */ + __IOM uint32_t DQOEE6 : 1; /*!< [6..6] DQOEE6 */ + __IOM uint32_t DQOEE7 : 1; /*!< [7..7] DQOEE7 */ + uint32_t : 8; + __IOM uint32_t DQSEE0 : 1; /*!< [16..16] DQSEE0 */ + __IOM uint32_t DQSEE1 : 1; /*!< [17..17] DQSEE1 */ + __IOM uint32_t DQSEE2 : 1; /*!< [18..18] DQSEE2 */ + __IOM uint32_t DQSEE3 : 1; /*!< [19..19] DQSEE3 */ + __IOM uint32_t DQSEE4 : 1; /*!< [20..20] DQSEE4 */ + __IOM uint32_t DQSEE5 : 1; /*!< [21..21] DQSEE5 */ + __IOM uint32_t DQSEE6 : 1; /*!< [22..22] DQSEE6 */ + __IOM uint32_t DQSEE7 : 1; /*!< [23..23] DQSEE7 */ + uint32_t : 8; + } GWEIE1_b; + }; + + union + { + __IOM uint32_t GWEID1; /*!< (@ 0x000011A8) GWCA Error Interrupt Disable Register 1 (GWEID1) */ + + struct + { + __IOM uint32_t DQOED0 : 1; /*!< [0..0] DQOED0 */ + __IOM uint32_t DQOED1 : 1; /*!< [1..1] DQOED1 */ + __IOM uint32_t DQOED2 : 1; /*!< [2..2] DQOED2 */ + __IOM uint32_t DQOED3 : 1; /*!< [3..3] DQOED3 */ + __IOM uint32_t DQOED4 : 1; /*!< [4..4] DQOED4 */ + __IOM uint32_t DQOED5 : 1; /*!< [5..5] DQOED5 */ + __IOM uint32_t DQOED6 : 1; /*!< [6..6] DQOED6 */ + __IOM uint32_t DQOED7 : 1; /*!< [7..7] DQOED7 */ + uint32_t : 8; + __IOM uint32_t DQSED0 : 1; /*!< [16..16] DQSED0 */ + __IOM uint32_t DQSED1 : 1; /*!< [17..17] DQSED1 */ + __IOM uint32_t DQSED2 : 1; /*!< [18..18] DQSED2 */ + __IOM uint32_t DQSED3 : 1; /*!< [19..19] DQSED3 */ + __IOM uint32_t DQSED4 : 1; /*!< [20..20] DQSED4 */ + __IOM uint32_t DQSED5 : 1; /*!< [21..21] DQSED5 */ + __IOM uint32_t DQSED6 : 1; /*!< [22..22] DQSED6 */ + __IOM uint32_t DQSED7 : 1; /*!< [23..23] DQSED7 */ + uint32_t : 8; + } GWEID1_b; + }; + __IM uint32_t RESERVED29[21]; + __IOM uint32_t GWEIS20; /*!< (@ 0x00001200) GWCA Error Interrupt Status Register 2i (GWEIS2i) + * (i = 0, 1) */ + __IOM uint32_t GWEIE20; /*!< (@ 0x00001204) GWCA Error Interrupt Enable Register 2i (GWEIE2i) + * (i = 0, 1) */ + __IOM uint32_t GWEID20; /*!< (@ 0x00001208) GWCA Error Interrupt Disable Register 2i (GWEID2i) + * (i = 0, 1) */ + __IM uint32_t RESERVED30; + __IOM uint32_t GWEIS21; /*!< (@ 0x00001210) GWCA Error Interrupt Status Register 2i (GWEIS2i) + * (i = 0, 1) */ + __IOM uint32_t GWEIE21; /*!< (@ 0x00001214) GWCA Error Interrupt Enable Register 2i (GWEIE2i) + * (i = 0, 1) */ + __IOM uint32_t GWEID21; /*!< (@ 0x00001218) GWCA Error Interrupt Disable Register 2i (GWEID2i) + * (i = 0, 1) */ + __IM uint32_t RESERVED31[25]; + + union + { + __IOM uint32_t GWEIS3; /*!< (@ 0x00001280) GWCA Error Interrupt Status Register 3 (GWEIS3) */ + + struct + { + __IOM uint32_t IAOES0 : 1; /*!< [0..0] IAOES0 */ + __IOM uint32_t IAOES1 : 1; /*!< [1..1] IAOES1 */ + __IOM uint32_t IAOES2 : 1; /*!< [2..2] IAOES2 */ + __IOM uint32_t IAOES3 : 1; /*!< [3..3] IAOES3 */ + __IOM uint32_t IAOES4 : 1; /*!< [4..4] IAOES4 */ + uint32_t : 27; + } GWEIS3_b; + }; + + union + { + __IOM uint32_t GWEIE3; /*!< (@ 0x00001284) GWCA Error Interrupt Enable Register 3 (GWEIE3) */ + + struct + { + __IOM uint32_t IAOEE0 : 1; /*!< [0..0] IAOEE0 */ + __IOM uint32_t IAOEE1 : 1; /*!< [1..1] IAOEE1 */ + __IOM uint32_t IAOEE2 : 1; /*!< [2..2] IAOEE2 */ + __IOM uint32_t IAOEE3 : 1; /*!< [3..3] IAOEE3 */ + __IOM uint32_t IAOEE4 : 1; /*!< [4..4] IAOEE4 */ + uint32_t : 27; + } GWEIE3_b; + }; + + union + { + __IOM uint32_t GWEID3; /*!< (@ 0x00001288) GWCA Error Interrupt Disable Register 3 (GWEID3) */ + + struct + { + __IOM uint32_t IAOED0 : 1; /*!< [0..0] IAOED0 */ + __IOM uint32_t IAOED1 : 1; /*!< [1..1] IAOED1 */ + __IOM uint32_t IAOED2 : 1; /*!< [2..2] IAOED2 */ + __IOM uint32_t IAOED3 : 1; /*!< [3..3] IAOED3 */ + __IOM uint32_t IAOED4 : 1; /*!< [4..4] IAOED4 */ + uint32_t : 27; + } GWEID3_b; + }; + __IM uint32_t RESERVED32; + + union + { + __IOM uint32_t GWEIS4; /*!< (@ 0x00001290) GWCA Error Interrupt Status Register 4 (GWEIS4) */ + + struct + { + __IOM uint32_t DSSES : 1; /*!< [0..0] DSSES */ + __IOM uint32_t DSSEIOS : 1; /*!< [1..1] DSSEIOS */ + uint32_t : 6; + __IOM uint32_t DSSECN : 6; /*!< [13..8] DSSECN */ + uint32_t : 2; + __IOM uint32_t DSES : 1; /*!< [16..16] DSES */ + __IOM uint32_t DSEIOS : 1; /*!< [17..17] DSEIOS */ + uint32_t : 6; + __IOM uint32_t DSECN : 6; /*!< [29..24] DSECN */ + uint32_t : 2; + } GWEIS4_b; + }; + + union + { + __IOM uint32_t GWEIE4; /*!< (@ 0x00001294) GWCA Error Interrupt Enable Register 4 (GWEIE4) */ + + struct + { + __IOM uint32_t DSSEE : 1; /*!< [0..0] DSSEE */ + __IOM uint32_t DSSEIOE : 1; /*!< [1..1] DSSEIOE */ + uint32_t : 14; + __IOM uint32_t DSEE : 1; /*!< [16..16] DSEE */ + __IOM uint32_t DSEIOE : 1; /*!< [17..17] DSEIOE */ + uint32_t : 14; + } GWEIE4_b; + }; + + union + { + __IOM uint32_t GWEID4; /*!< (@ 0x00001298) GWCA Error Interrupt Disable Register 4 (GWEID4) */ + + struct + { + __IOM uint32_t DSSED : 1; /*!< [0..0] DSSED */ + __IOM uint32_t DSSEIOD : 1; /*!< [1..1] DSSEIOD */ + uint32_t : 14; + __IOM uint32_t DSED : 1; /*!< [16..16] DSED */ + __IOM uint32_t DSEIOD : 1; /*!< [17..17] DSEIOD */ + uint32_t : 14; + } GWEID4_b; + }; + __IM uint32_t RESERVED33; + + union + { + __IOM uint32_t GWEIS5; /*!< (@ 0x000012A0) GWCA Error Interrupt Status Register 5 (GWEIS5) */ + + struct + { + __IOM uint32_t DCTES : 1; /*!< [0..0] DCTES */ + __IOM uint32_t DCTEIOS : 1; /*!< [1..1] DCTEIOS */ + uint32_t : 6; + __IOM uint32_t DCTECN : 6; /*!< [13..8] DCTECN */ + uint32_t : 2; + __IOM uint32_t RXDNES : 1; /*!< [16..16] RXDNES */ + __IOM uint32_t RXDNEIOS : 1; /*!< [17..17] RXDNEIOS */ + uint32_t : 14; + } GWEIS5_b; + }; + + union + { + __IOM uint32_t GWEIE5; /*!< (@ 0x000012A4) GWCA Error Interrupt Enable Register 5 (GWEIE5) */ + + struct + { + __IOM uint32_t DCTEE : 1; /*!< [0..0] DCTEE */ + __IOM uint32_t DCTEIOE : 1; /*!< [1..1] DCTEIOE */ + uint32_t : 14; + __IOM uint32_t RXDNEE : 1; /*!< [16..16] RXDNEE */ + __IOM uint32_t RXDNEIOE : 1; /*!< [17..17] RXDNEIOE */ + uint32_t : 14; + } GWEIE5_b; + }; + + union + { + __IOM uint32_t GWEID5; /*!< (@ 0x000012A8) GWCA Error Interrupt Disable Register 5 (GWEID5) */ + + struct + { + __IOM uint32_t DCTED : 1; /*!< [0..0] DCTED */ + __IOM uint32_t DCTEIOD : 1; /*!< [1..1] DCTEIOD */ + uint32_t : 13; + __IOM uint32_t RXDNED : 1; /*!< [15..15] RXDNED */ + __IOM uint32_t RXDNEIOD : 1; /*!< [16..16] RXDNEIOD */ + uint32_t : 15; + } GWEID5_b; + }; +} R_GWCA0_Type; /*!< Size = 4780 (0x12ac) */ + +/* =========================================================================================================================== */ +/* ================ R_IPC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Inter-Processor Communication (R_IPC) + */ + +typedef struct /*!< (@ 0x40020000) R_IPC Structure */ +{ + union + { + __IOM uint32_t IPCSEM[16]; /*!< (@ 0x00000000) Semaphore Registers */ + + struct + { + __IOM uint32_t LOCK : 1; /*!< [0..0] Indicates the shared resource is locked */ + uint32_t : 31; + } IPCSEM_b[16]; + }; + __IM uint32_t RESERVED[16]; + __IOM R_IPC_IPCNMI_Type IPC0NMI; /*!< (@ 0x00000080) Inter-Processor NMI Registers */ + __IOM R_IPC_IPCNMI_Type IPC1NMI; /*!< (@ 0x00000090) Inter-Processor NMI Registers */ + __IM uint32_t RESERVED1[8]; + __IOM R_IPC_IPC_Type IPC0; /*!< (@ 0x000000C0) Inter-Processor Registers */ + __IOM R_IPC_IPC_Type IPC1; /*!< (@ 0x00000100) Inter-Processor Registers */ +} R_IPC_Type; /*!< Size = 320 (0x140) */ + +/* =========================================================================================================================== */ +/* ================ R_MFWD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Message Forwarding Engine (R_MFWD) + */ + +typedef struct /*!< (@ 0x403C0000) R_MFWD Structure */ +{ + union + { + __IOM uint32_t FWGC; /*!< (@ 0x00000000) General Configuration Register */ + + struct + { + __IOM uint32_t SVM : 2; /*!< [1..0] Switch VLAN Mode */ + uint32_t : 30; + } FWGC_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t FWTTC0; /*!< (@ 0x00000010) TAG TPID Configuration Register 0 */ + + struct + { + __IOM uint32_t CTT : 16; /*!< [15..0] C-TAG TPID */ + __IOM uint32_t STT : 16; /*!< [31..16] S-TAG TPID */ + } FWTTC0_b; + }; + + union + { + __IOM uint32_t FWTTC1; /*!< (@ 0x00000014) TAG TPID Configuration Register 1 */ + + struct + { + __IOM uint32_t RTT : 16; /*!< [15..0] R-TAG TPID */ + uint32_t : 16; + } FWTTC1_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t FWCEPTC; /*!< (@ 0x00000020) CPU Exceptional Path Target Configuration Register */ + + struct + { + __IOM uint32_t EPCSD : 7; /*!< [6..0] Exceptional Path CPU Sub Destination */ + uint32_t : 5; + __IOM uint32_t EPIPV : 3; /*!< [14..12] Exceptional Path Internal Priority Value */ + uint32_t : 1; + __IOM uint32_t EPCS : 2; /*!< [17..16] Exceptional Path CPU Select */ + uint32_t : 6; + __IOM uint32_t EPSL : 1; /*!< [24..24] Exceptional Path Security Level */ + uint32_t : 7; + } FWCEPTC_b; + }; + + union + { + __IOM uint32_t FWCEPRC0; /*!< (@ 0x00000024) CPU Exceptional Path Reason Configuration Register + * 0 */ + + struct + { + __IOM uint32_t EPHYEEF : 1; /*!< [0..0] Ethernet PHY Error Exceptional Forwarding */ + __IOM uint32_t EPCRCEEF : 1; /*!< [1..1] Ethernet PCH CRC Error Exceptional Forwarding */ + __IOM uint32_t ENIBEEF : 1; /*!< [2..2] Ethernet Nibble Error Exceptional Forwarding */ + __IOM uint32_t EFCSEEF : 1; /*!< [3..3] Ethernet FCS Error Exceptional Forwarding */ + __IOM uint32_t EFFMEEF : 1; /*!< [4..4] Ethernet Final Fragment Missing Error Exceptional Forwarding */ + __IOM uint32_t ECFSEEF : 1; /*!< [5..5] Ethernet C-Fragment SMD Error Exceptional Forwarding */ + __IOM uint32_t ECFFCEEF : 1; /*!< [6..6] Ethernet C-Fragment FRAG_COUNT Error Exceptional Forwarding */ + __IOM uint32_t ERFFEF : 1; /*!< [7..7] Ethernet RMAC Frame Filtered Exceptional Forwarding */ + __IOM uint32_t ERPOOEF : 1; /*!< [8..8] Ethernet Reception Partially Out of Operation Exceptional + * Forwarding */ + __IOM uint32_t EBOEEF : 1; /*!< [9..9] Ethernet Buffer Overflow Error Exceptional Forwarding */ + __IOM uint32_t EUEEF : 1; /*!< [10..10] Ethernet Undersize Error Exceptional Forwarding */ + __IOM uint32_t EOEEF : 1; /*!< [11..11] Ethernet Oversize Error Exceptional Forwarding */ + __IOM uint32_t ETFEF : 1; /*!< [12..12] Ethernet TAG Filtering Exceptional Forwarding */ + uint32_t : 3; + __IOM uint32_t GAREEEF : 1; /*!< [16..16] GWCA AXI RAM ECC Error Exceptional Forwarding */ + __IOM uint32_t GAXEEF : 1; /*!< [17..17] GWCA AXI Error Exceptional Forwarding */ + __IOM uint32_t GSEQEEF : 1; /*!< [18..18] GWCA Sequence Error Exceptional Forwarding */ + uint32_t : 1; + __IOM uint32_t GTFEF : 1; /*!< [20..20] GWCA TAG Filtering Exceptional Forwarding */ + __IOM uint32_t GDNEEF : 1; /*!< [21..21] GWCA Descriptor Number Error Exceptional Forwarding */ + uint32_t : 2; + __IOM uint32_t DDEEF : 1; /*!< [24..24] Direct Descriptor Error Exceptional Forwarding */ + uint32_t : 1; + __IOM uint32_t DDFSFEF : 1; /*!< [26..26] Direct Descriptor Format Security Filtering Exceptional + * Forwarding */ + uint32_t : 5; + } FWCEPRC0_b; + }; + + union + { + __IOM uint32_t FWCEPRC1; /*!< (@ 0x00000028) CPU Exceptional Path Reason Configuration Register + * 1 */ + + struct + { + __IOM uint32_t FMSDUFEF : 1; /*!< [0..0] MSDU Filtering Exceptional Forwarding */ + uint32_t : 1; + __IOM uint32_t FMTRFEF : 1; /*!< [2..2] Meter Filtering Exceptional Forwarding */ + uint32_t : 5; + __IOM uint32_t FIFFEF : 1; /*!< [8..8] Individual FRER Filtering Exceptional Forwarding */ + __IOM uint32_t FSFFEF : 1; /*!< [9..9] Sequence FRER Filtering Exceptional Forwarding */ + uint32_t : 22; + } FWCEPRC1_b; + }; + + union + { + __IOM uint32_t FWCEPRC2; /*!< (@ 0x0000002C) CPU Exceptional Path Reason Configuration Register + * 2 */ + + struct + { + __IOM uint32_t FLTHUFEF : 1; /*!< [0..0] Layer 3 Unknown Filtering Exceptional Forwarding */ + uint32_t : 2; + __IOM uint32_t FDMACUFEF : 1; /*!< [3..3] Destination MAC Unknown Filtering Exceptional Forwarding */ + __IOM uint32_t FSMACUFEF : 1; /*!< [4..4] Source MAC Unknown Filtering Exceptional Forwarding */ + __IOM uint32_t FVLANUFEF : 1; /*!< [5..5] VLAN Unknown Filtering Exceptional Forwarding */ + uint32_t : 2; + __IOM uint32_t FDDNTFEF : 1; /*!< [8..8] Direct Descriptor No Target Filtering Exceptional Forwarding */ + __IOM uint32_t FLTHNTFEF : 1; /*!< [9..9] Layer 3 No Target Filtering Exceptional Forwarding */ + uint32_t : 1; + __IOM uint32_t FLTWNTFEF : 1; /*!< [11..11] Layer 2 No Target Filtering Exceptional Forwarding */ + __IOM uint32_t FPBNTFEF : 1; /*!< [12..12] Port Based No Target Filtering Exceptional Forwarding */ + uint32_t : 3; + __IOM uint32_t FLTHSLFEF : 1; /*!< [16..16] Layer 3 Source Lock Filtering Exceptional Forwarding */ + uint32_t : 2; + __IOM uint32_t FDMACSLFEF : 1; /*!< [19..19] Destination MAC Source Lock Filtering Exceptional Forwarding */ + __IOM uint32_t FSMACSLFEF : 1; /*!< [20..20] Source MAC Source Lock Filtering Exceptional Forwarding */ + __IOM uint32_t FVLANSLFEF : 1; /*!< [21..21] VLAN Source Lock Filtering Exceptional Forwarding */ + uint32_t : 4; + __IOM uint32_t FWMFEF : 1; /*!< [26..26] Watermark Filtering Exceptional Forwarding */ + uint32_t : 5; + } FWCEPRC2_b; + }; + + union + { + __IOM uint32_t FWCLPTC; /*!< (@ 0x00000030) CPU Learning Path Target Configuration Register */ + + struct + { + __IOM uint32_t LPCSD : 7; /*!< [6..0] Learning Path CPU Sub Destination */ + uint32_t : 5; + __IOM uint32_t LPIPV : 3; /*!< [14..12] Learning Path Internal Priority Value */ + uint32_t : 1; + __IOM uint32_t LPCS : 2; /*!< [17..16] Learning Path CPU Select */ + uint32_t : 6; + __IOM uint32_t LPSL : 1; /*!< [24..24] Learning Path Security Level */ + uint32_t : 7; + } FWCLPTC_b; + }; + + union + { + __IOM uint32_t FWCLPRC; /*!< (@ 0x00000034) CPU Learning Path Reason Configuration Register */ + + struct + { + __IOM uint32_t USIDLF : 1; /*!< [0..0] Unknown Stream ID Learning Forwarding */ + uint32_t : 3; + __IOM uint32_t UDMACLF : 1; /*!< [4..4] Unknown Destination MAC Learning Forwarding */ + __IOM uint32_t USMACLF : 1; /*!< [5..5] Unknown Source MAC Learning Forwarding */ + __IOM uint32_t UPSMACLF : 1; /*!< [6..6] Unknown Port for Source MAC Learning Forwarding */ + __IOM uint32_t UVLANLF : 1; /*!< [7..7] Unknown VLAN Learning Forwarding */ + uint32_t : 24; + } FWCLPRC_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t FWCMPTC; /*!< (@ 0x00000040) CPU Mirroring Path Target Configuration Register */ + + struct + { + __IOM uint32_t CMPCSD : 7; /*!< [6..0] CPU Mirroring Path CPU Sub Destination */ + uint32_t : 5; + __IOM uint32_t CMPIPV : 3; /*!< [14..12] CPU Mirroring Path Internal Priority Value */ + __IOM uint32_t CMPIPU : 1; /*!< [15..15] CPU Mirroring Path Internal Priority Update */ + __IOM uint32_t CMPCS : 2; /*!< [17..16] CPU Mirroring Path CPU Select */ + uint32_t : 6; + __IOM uint32_t CMPSL : 1; /*!< [24..24] CPU Mirroring Path Security Level */ + uint32_t : 7; + } FWCMPTC_b; + }; + + union + { + __IOM uint32_t FWEMPTC; /*!< (@ 0x00000044) Ethernet Mirroring Path Target Configuration + * Register */ + + struct + { + uint32_t : 12; + __IOM uint32_t EMPIPV : 3; /*!< [14..12] Ethernet Mirroring Path Internal Priority Value */ + __IOM uint32_t EMPIPU : 1; /*!< [15..15] Ethernet Mirroring Path Internal Priority Update */ + __IOM uint32_t EMPPS : 2; /*!< [17..16] Ethernet Mirroring Path CPU Select */ + uint32_t : 6; + __IOM uint32_t EMPSL : 1; /*!< [24..24] Ethernet Mirroring Path Security Level */ + uint32_t : 7; + } FWEMPTC_b; + }; + __IM uint32_t RESERVED3[2]; + + union + { + __IOM uint32_t FWSDMPTC; /*!< (@ 0x00000050) Source-Destination Mirroring Path Target Configuration + * Register */ + + struct + { + __IOM uint32_t SDMPCSD : 7; /*!< [6..0] Source-Destination Mirroring Path CPU Sub Destination */ + uint32_t : 5; + __IOM uint32_t SDMPIPV : 3; /*!< [14..12] Source-Destination Mirroring Path Internal Priority + * Value */ + __IOM uint32_t SDMPIPU : 1; /*!< [15..15] Source-Destination Mirroring Path Internal Priority + * Update */ + __IOM uint32_t SDMPPS : 2; /*!< [17..16] Source-Destination Mirroring Path CPU Select */ + uint32_t : 6; + __IOM uint32_t SDMPSL : 1; /*!< [24..24] Source-Destination Mirroring Path Security Level */ + uint32_t : 7; + } FWSDMPTC_b; + }; + + union + { + __IOM uint32_t FWSDMPVC; /*!< (@ 0x00000054) Source-Destination Mirroring Path Vector Configuration + * Register */ + + struct + { + __IOM uint32_t SDMDV : 7; /*!< [6..0] Source-Destination Mirroring Destination Vector */ + uint32_t : 9; + __IOM uint32_t SDMSV : 7; /*!< [22..16] Source-Destination Mirroring Source Vector */ + uint32_t : 9; + } FWSDMPVC_b; + }; + __IM uint32_t RESERVED4[10]; + + union + { + __IOM uint32_t FWLBWMC0; /*!< (@ 0x00000080) Level Based Watermark Configuration Register + * 0 */ + + struct + { + __IOM uint32_t WMCLPR : 16; /*!< [15..0] Watermark Critical Level Priority Rejected */ + __IOM uint32_t WMFLPR : 16; /*!< [31..16] Watermark Flush Level Priority Rejected */ + } FWLBWMC0_b; + }; + + union + { + __IOM uint32_t FWLBWMC1; /*!< (@ 0x00000084) Level Based Watermark Configuration Register + * 1 */ + + struct + { + __IOM uint32_t WMCLPR : 16; /*!< [15..0] Watermark Critical Level Priority Rejected */ + __IOM uint32_t WMFLPR : 16; /*!< [31..16] Watermark Flush Level Priority Rejected */ + } FWLBWMC1_b; + }; + + union + { + __IOM uint32_t FWLBWMC2; /*!< (@ 0x00000088) Level Based Watermark Configuration Register + * 2 */ + + struct + { + __IOM uint32_t WMCLPR : 16; /*!< [15..0] Watermark Critical Level Priority Rejected */ + __IOM uint32_t WMFLPR : 16; /*!< [31..16] Watermark Flush Level Priority Rejected */ + } FWLBWMC2_b; + }; + __IM uint32_t RESERVED5[29]; + + union + { + __IOM uint32_t FWPC00; /*!< (@ 0x00000100) Port Configuration Register 00 */ + + struct + { + __IOM uint32_t LTHTA : 1; /*!< [0..0] L3 Table Active */ + __IOM uint32_t LTHRUS : 1; /*!< [1..1] L3 Reject Unknown Streams */ + __IOM uint32_t LTHRUSS : 1; /*!< [2..2] L3 Reject Unknown Secure Streams */ + __IOM uint32_t IP4UE : 1; /*!< [3..3] IPv4 UDP Enabled */ + __IOM uint32_t IP4TE : 1; /*!< [4..4] IPv4 TCP Enabled */ + __IOM uint32_t IP4OE : 1; /*!< [5..5] IPv4 Other Enabled */ + __IOM uint32_t IP6UE : 1; /*!< [6..6] IPv6 UDP Enabled */ + __IOM uint32_t IP6TE : 1; /*!< [7..7] IPv6 TCP Enabled */ + __IOM uint32_t IP6OE : 1; /*!< [8..8] IPv6 Other Enabled */ + __IOM uint32_t L2SE : 1; /*!< [9..9] L2 Stream Enable */ + uint32_t : 10; + __IOM uint32_t MACDSA : 1; /*!< [20..20] MAC Destination Search Active */ + __IOM uint32_t MACRUDA : 1; /*!< [21..21] MAC Reject Unknown Destination Addresses */ + __IOM uint32_t MACRUDSA : 1; /*!< [22..22] MAC Reject Unknown Destination Secure Addresses */ + __IOM uint32_t MACSSA : 1; /*!< [23..23] MAC Source Search Active */ + __IOM uint32_t MACRUSA : 1; /*!< [24..24] MAC Reject Unknown Source Addresses */ + __IOM uint32_t MACRUSSA : 1; /*!< [25..25] MAC Reject Unknown Source Secure Addresses */ + __IOM uint32_t MACHLA : 1; /*!< [26..26] MAC Hardware Learning Active */ + __IOM uint32_t MACHMA : 1; /*!< [27..27] MAC Hardware Migration Active */ + __IOM uint32_t VLANSA : 1; /*!< [28..28] VLAN Search Active */ + __IOM uint32_t VLANRU : 1; /*!< [29..29] VLAN Reject Unknown */ + __IOM uint32_t VLANRUS : 1; /*!< [30..30] VLAN Reject Unknown Secure */ + uint32_t : 1; + } FWPC00_b; + }; + + union + { + __IOM uint32_t FWPC10; /*!< (@ 0x00000104) Port Configuration Register 10 */ + + struct + { + __IOM uint32_t DDE : 1; /*!< [0..0] Direct Descriptor Enable */ + __IOM uint32_t DDSL : 1; /*!< [1..1] Direct Descriptor Security Level */ + uint32_t : 14; + __IOM uint32_t LTHFM : 7; /*!< [22..16] Layer 3 Forwarding Mask */ + uint32_t : 9; + } FWPC10_b; + }; + + union + { + __IOM uint32_t FWPC20; /*!< (@ 0x00000108) Port Configuration Register 20 */ + + struct + { + uint32_t : 16; + __IOM uint32_t LTWFM : 7; /*!< [22..16] Layer 2 Forwarding Mask */ + uint32_t : 9; + } FWPC20_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t FWPC01; /*!< (@ 0x00000110) Port Configuration Register 01 */ + + struct + { + __IOM uint32_t LTHTA : 1; /*!< [0..0] L3 Table Active */ + __IOM uint32_t LTHRUS : 1; /*!< [1..1] L3 Reject Unknown Streams */ + __IOM uint32_t LTHRUSS : 1; /*!< [2..2] L3 Reject Unknown Secure Streams */ + __IOM uint32_t IP4UE : 1; /*!< [3..3] IPv4 UDP Enabled */ + __IOM uint32_t IP4TE : 1; /*!< [4..4] IPv4 TCP Enabled */ + __IOM uint32_t IP4OE : 1; /*!< [5..5] IPv4 Other Enabled */ + __IOM uint32_t IP6UE : 1; /*!< [6..6] IPv6 UDP Enabled */ + __IOM uint32_t IP6TE : 1; /*!< [7..7] IPv6 TCP Enabled */ + __IOM uint32_t IP6OE : 1; /*!< [8..8] IPv6 Other Enabled */ + __IOM uint32_t L2SE : 1; /*!< [9..9] L2 Stream Enable */ + uint32_t : 10; + __IOM uint32_t MACDSA : 1; /*!< [20..20] MAC Destination Search Active */ + __IOM uint32_t MACRUDA : 1; /*!< [21..21] MAC Reject Unknown Destination Addresses */ + __IOM uint32_t MACRUDSA : 1; /*!< [22..22] MAC Reject Unknown Destination Secure Addresses */ + __IOM uint32_t MACSSA : 1; /*!< [23..23] MAC Source Search Active */ + __IOM uint32_t MACRUSA : 1; /*!< [24..24] MAC Reject Unknown Source Addresses */ + __IOM uint32_t MACRUSSA : 1; /*!< [25..25] MAC Reject Unknown Source Secure Addresses */ + __IOM uint32_t MACHLA : 1; /*!< [26..26] MAC Hardware Learning Active */ + __IOM uint32_t MACHMA : 1; /*!< [27..27] MAC Hardware Migration Active */ + __IOM uint32_t VLANSA : 1; /*!< [28..28] VLAN Search Active */ + __IOM uint32_t VLANRU : 1; /*!< [29..29] VLAN Reject Unknown */ + __IOM uint32_t VLANRUS : 1; /*!< [30..30] VLAN Reject Unknown Secure */ + uint32_t : 1; + } FWPC01_b; + }; + + union + { + __IOM uint32_t FWPC11; /*!< (@ 0x00000114) Port Configuration Register 11 */ + + struct + { + __IOM uint32_t DDE : 1; /*!< [0..0] Direct Descriptor Enable */ + __IOM uint32_t DDSL : 1; /*!< [1..1] Direct Descriptor Security Level */ + uint32_t : 14; + __IOM uint32_t LTHFM : 7; /*!< [22..16] Layer 3 Forwarding Mask */ + uint32_t : 9; + } FWPC11_b; + }; + + union + { + __IOM uint32_t FWPC21; /*!< (@ 0x00000118) Port Configuration Register 21 */ + + struct + { + uint32_t : 16; + __IOM uint32_t LTWFM : 7; /*!< [22..16] Layer 2 Forwarding Mask */ + uint32_t : 9; + } FWPC21_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t FWPC02; /*!< (@ 0x00000120) Port Configuration Register 02 */ + + struct + { + __IOM uint32_t LTHTA : 1; /*!< [0..0] L3 Table Active */ + __IOM uint32_t LTHRUS : 1; /*!< [1..1] L3 Reject Unknown Streams */ + __IOM uint32_t LTHRUSS : 1; /*!< [2..2] L3 Reject Unknown Secure Streams */ + __IOM uint32_t IP4UE : 1; /*!< [3..3] IPv4 UDP Enabled */ + __IOM uint32_t IP4TE : 1; /*!< [4..4] IPv4 TCP Enabled */ + __IOM uint32_t IP4OE : 1; /*!< [5..5] IPv4 Other Enabled */ + __IOM uint32_t IP6UE : 1; /*!< [6..6] IPv6 UDP Enabled */ + __IOM uint32_t IP6TE : 1; /*!< [7..7] IPv6 TCP Enabled */ + __IOM uint32_t IP6OE : 1; /*!< [8..8] IPv6 Other Enabled */ + __IOM uint32_t L2SE : 1; /*!< [9..9] L2 Stream Enable */ + uint32_t : 10; + __IOM uint32_t MACDSA : 1; /*!< [20..20] MAC Destination Search Active */ + __IOM uint32_t MACRUDA : 1; /*!< [21..21] MAC Reject Unknown Destination Addresses */ + __IOM uint32_t MACRUDSA : 1; /*!< [22..22] MAC Reject Unknown Destination Secure Addresses */ + __IOM uint32_t MACSSA : 1; /*!< [23..23] MAC Source Search Active */ + __IOM uint32_t MACRUSA : 1; /*!< [24..24] MAC Reject Unknown Source Addresses */ + __IOM uint32_t MACRUSSA : 1; /*!< [25..25] MAC Reject Unknown Source Secure Addresses */ + __IOM uint32_t MACHLA : 1; /*!< [26..26] MAC Hardware Learning Active */ + __IOM uint32_t MACHMA : 1; /*!< [27..27] MAC Hardware Migration Active */ + __IOM uint32_t VLANSA : 1; /*!< [28..28] VLAN Search Active */ + __IOM uint32_t VLANRU : 1; /*!< [29..29] VLAN Reject Unknown */ + __IOM uint32_t VLANRUS : 1; /*!< [30..30] VLAN Reject Unknown Secure */ + uint32_t : 1; + } FWPC02_b; + }; + + union + { + __IOM uint32_t FWPC12; /*!< (@ 0x00000124) Port Configuration Register 12 */ + + struct + { + __IOM uint32_t DDE : 1; /*!< [0..0] Direct Descriptor Enable */ + __IOM uint32_t DDSL : 1; /*!< [1..1] Direct Descriptor Security Level */ + uint32_t : 14; + __IOM uint32_t LTHFM : 7; /*!< [22..16] Layer 3 Forwarding Mask */ + uint32_t : 9; + } FWPC12_b; + }; + + union + { + __IOM uint32_t FWPC22; /*!< (@ 0x00000128) Port Configuration Register 22 */ + + struct + { + uint32_t : 16; + __IOM uint32_t LTWFM : 7; /*!< [22..16] Layer 2 Forwarding Mask */ + uint32_t : 9; + } FWPC22_b; + }; + __IM uint32_t RESERVED8[181]; + + union + { + __IOM uint32_t FWCTGC00; /*!< (@ 0x00000400) Cut-Through General Configuration Register 00 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC00_b; + }; + + union + { + __IOM uint32_t FWCTGC10; /*!< (@ 0x00000404) Cut-Through General Configuration Register 10 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC10_b; + }; + + union + { + __IOM uint32_t FWCTTC00; /*!< (@ 0x00000408) Cut-Through Target Configuration Register 00 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC00_b; + }; + + union + { + __IOM uint32_t FWCTTC10; /*!< (@ 0x0000040C) Cut-Through Target Configuration Register 10 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC10_b; + }; + + union + { + __IOM uint32_t FWCTTC200; /*!< (@ 0x00000410) Cut-Through Target Configuration Register 200 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC200_b; + }; + __IM uint32_t RESERVED9[3]; + + union + { + __IOM uint32_t FWCTSC00; /*!< (@ 0x00000420) Cut-Through Separation Configuration Register + * 00 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC00_b; + }; + + union + { + __IOM uint32_t FWCTSC10; /*!< (@ 0x00000424) Cut-Through Separation Configuration Register + * 10 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC10_b; + }; + + union + { + __IOM uint32_t FWCTSC20; /*!< (@ 0x00000428) Cut-Through Separation Configuration Register + * 20 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC20_b; + }; + + union + { + __IOM uint32_t FWCTSC30; /*!< (@ 0x0000042C) Cut-Through Separation Configuration Register + * 30 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC30_b; + }; + + union + { + __IOM uint32_t FWCTSC40; /*!< (@ 0x00000430) Cut-Through Separation Configuration Register + * 40 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC40_b; + }; + __IM uint32_t RESERVED10[3]; + + union + { + __IOM uint32_t FWCTGC01; /*!< (@ 0x00000440) Cut-Through General Configuration Register 01 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC01_b; + }; + + union + { + __IOM uint32_t FWCTGC11; /*!< (@ 0x00000444) Cut-Through General Configuration Register 11 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC11_b; + }; + + union + { + __IOM uint32_t FWCTTC01; /*!< (@ 0x00000448) Cut-Through Target Configuration Register 01 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC01_b; + }; + + union + { + __IOM uint32_t FWCTTC11; /*!< (@ 0x0000044C) Cut-Through Target Configuration Register 11 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC11_b; + }; + + union + { + __IOM uint32_t FWCTTC201; /*!< (@ 0x00000450) Cut-Through Target Configuration Register 201 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC201_b; + }; + __IM uint32_t RESERVED11[3]; + + union + { + __IOM uint32_t FWCTSC01; /*!< (@ 0x00000460) Cut-Through Separation Configuration Register + * 01 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC01_b; + }; + + union + { + __IOM uint32_t FWCTSC11; /*!< (@ 0x00000464) Cut-Through Separation Configuration Register + * 11 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC11_b; + }; + + union + { + __IOM uint32_t FWCTSC21; /*!< (@ 0x00000468) Cut-Through Separation Configuration Register + * 21 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC21_b; + }; + + union + { + __IOM uint32_t FWCTSC31; /*!< (@ 0x0000046C) Cut-Through Separation Configuration Register + * 31 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC31_b; + }; + + union + { + __IOM uint32_t FWCTSC41; /*!< (@ 0x00000470) Cut-Through Separation Configuration Register + * 41 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC41_b; + }; + __IM uint32_t RESERVED12[3]; + + union + { + __IOM uint32_t FWCTGC02; /*!< (@ 0x00000480) Cut-Through General Configuration Register 02 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC02_b; + }; + + union + { + __IOM uint32_t FWCTGC12; /*!< (@ 0x00000484) Cut-Through General Configuration Register 12 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC12_b; + }; + + union + { + __IOM uint32_t FWCTTC02; /*!< (@ 0x00000488) Cut-Through Target Configuration Register 02 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC02_b; + }; + + union + { + __IOM uint32_t FWCTTC12; /*!< (@ 0x0000048C) Cut-Through Target Configuration Register 12 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC12_b; + }; + + union + { + __IOM uint32_t FWCTTC202; /*!< (@ 0x00000490) Cut-Through Target Configuration Register 202 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC202_b; + }; + __IM uint32_t RESERVED13[3]; + + union + { + __IOM uint32_t FWCTSC02; /*!< (@ 0x000004A0) Cut-Through Separation Configuration Register + * 02 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC02_b; + }; + + union + { + __IOM uint32_t FWCTSC12; /*!< (@ 0x000004A4) Cut-Through Separation Configuration Register + * 12 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC12_b; + }; + + union + { + __IOM uint32_t FWCTSC22; /*!< (@ 0x000004A8) Cut-Through Separation Configuration Register + * 22 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC22_b; + }; + + union + { + __IOM uint32_t FWCTSC32; /*!< (@ 0x000004AC) Cut-Through Separation Configuration Register + * 32 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC32_b; + }; + + union + { + __IOM uint32_t FWCTSC42; /*!< (@ 0x000004B0) Cut-Through Separation Configuration Register + * 42 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC42_b; + }; + __IM uint32_t RESERVED14[3]; + + union + { + __IOM uint32_t FWCTGC03; /*!< (@ 0x000004C0) Cut-Through General Configuration Register 03 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC03_b; + }; + + union + { + __IOM uint32_t FWCTGC13; /*!< (@ 0x000004C4) Cut-Through General Configuration Register 13 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC13_b; + }; + + union + { + __IOM uint32_t FWCTTC03; /*!< (@ 0x000004C8) Cut-Through Target Configuration Register 03 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC03_b; + }; + + union + { + __IOM uint32_t FWCTTC13; /*!< (@ 0x000004CC) Cut-Through Target Configuration Register 13 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC13_b; + }; + + union + { + __IOM uint32_t FWCTTC203; /*!< (@ 0x000004D0) Cut-Through Target Configuration Register 203 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC203_b; + }; + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint32_t FWCTSC03; /*!< (@ 0x000004E0) Cut-Through Separation Configuration Register + * 03 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC03_b; + }; + + union + { + __IOM uint32_t FWCTSC13; /*!< (@ 0x000004E4) Cut-Through Separation Configuration Register + * 13 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC13_b; + }; + + union + { + __IOM uint32_t FWCTSC23; /*!< (@ 0x000004E8) Cut-Through Separation Configuration Register + * 23 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC23_b; + }; + + union + { + __IOM uint32_t FWCTSC33; /*!< (@ 0x000004EC) Cut-Through Separation Configuration Register + * 33 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC33_b; + }; + + union + { + __IOM uint32_t FWCTSC43; /*!< (@ 0x000004F0) Cut-Through Separation Configuration Register + * 43 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC43_b; + }; + __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint32_t FWCTGC04; /*!< (@ 0x00000500) Cut-Through General Configuration Register 04 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC04_b; + }; + + union + { + __IOM uint32_t FWCTGC14; /*!< (@ 0x00000504) Cut-Through General Configuration Register 14 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC14_b; + }; + + union + { + __IOM uint32_t FWCTTC04; /*!< (@ 0x00000508) Cut-Through Target Configuration Register 04 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC04_b; + }; + + union + { + __IOM uint32_t FWCTTC14; /*!< (@ 0x0000050C) Cut-Through Target Configuration Register 14 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC14_b; + }; + + union + { + __IOM uint32_t FWCTTC204; /*!< (@ 0x00000510) Cut-Through Target Configuration Register 204 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC204_b; + }; + __IM uint32_t RESERVED17[3]; + + union + { + __IOM uint32_t FWCTSC04; /*!< (@ 0x00000520) Cut-Through Separation Configuration Register + * 04 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC04_b; + }; + + union + { + __IOM uint32_t FWCTSC14; /*!< (@ 0x00000524) Cut-Through Separation Configuration Register + * 14 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC14_b; + }; + + union + { + __IOM uint32_t FWCTSC24; /*!< (@ 0x00000528) Cut-Through Separation Configuration Register + * 24 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC24_b; + }; + + union + { + __IOM uint32_t FWCTSC34; /*!< (@ 0x0000052C) Cut-Through Separation Configuration Register + * 34 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC34_b; + }; + + union + { + __IOM uint32_t FWCTSC44; /*!< (@ 0x00000530) Cut-Through Separation Configuration Register + * 44 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC44_b; + }; + __IM uint32_t RESERVED18[3]; + + union + { + __IOM uint32_t FWCTGC05; /*!< (@ 0x00000540) Cut-Through General Configuration Register 05 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC05_b; + }; + + union + { + __IOM uint32_t FWCTGC15; /*!< (@ 0x00000544) Cut-Through General Configuration Register 15 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC15_b; + }; + + union + { + __IOM uint32_t FWCTTC05; /*!< (@ 0x00000548) Cut-Through Target Configuration Register 05 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC05_b; + }; + + union + { + __IOM uint32_t FWCTTC15; /*!< (@ 0x0000054C) Cut-Through Target Configuration Register 15 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC15_b; + }; + + union + { + __IOM uint32_t FWCTTC205; /*!< (@ 0x00000550) Cut-Through Target Configuration Register 205 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC205_b; + }; + __IM uint32_t RESERVED19[3]; + + union + { + __IOM uint32_t FWCTSC05; /*!< (@ 0x00000560) Cut-Through Separation Configuration Register + * 05 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC05_b; + }; + + union + { + __IOM uint32_t FWCTSC15; /*!< (@ 0x00000564) Cut-Through Separation Configuration Register + * 15 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC15_b; + }; + + union + { + __IOM uint32_t FWCTSC25; /*!< (@ 0x00000568) Cut-Through Separation Configuration Register + * 25 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC25_b; + }; + + union + { + __IOM uint32_t FWCTSC35; /*!< (@ 0x0000056C) Cut-Through Separation Configuration Register + * 35 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC35_b; + }; + + union + { + __IOM uint32_t FWCTSC45; /*!< (@ 0x00000570) Cut-Through Separation Configuration Register + * 45 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC45_b; + }; + __IM uint32_t RESERVED20[3]; + + union + { + __IOM uint32_t FWCTGC06; /*!< (@ 0x00000580) Cut-Through General Configuration Register 06 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC06_b; + }; + + union + { + __IOM uint32_t FWCTGC16; /*!< (@ 0x00000584) Cut-Through General Configuration Register 16 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC16_b; + }; + + union + { + __IOM uint32_t FWCTTC06; /*!< (@ 0x00000588) Cut-Through Target Configuration Register 06 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC06_b; + }; + + union + { + __IOM uint32_t FWCTTC16; /*!< (@ 0x0000058C) Cut-Through Target Configuration Register 16 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC16_b; + }; + + union + { + __IOM uint32_t FWCTTC206; /*!< (@ 0x00000590) Cut-Through Target Configuration Register 206 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC206_b; + }; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t FWCTSC06; /*!< (@ 0x000005A0) Cut-Through Separation Configuration Register + * 06 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC06_b; + }; + + union + { + __IOM uint32_t FWCTSC16; /*!< (@ 0x000005A4) Cut-Through Separation Configuration Register + * 16 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC16_b; + }; + + union + { + __IOM uint32_t FWCTSC26; /*!< (@ 0x000005A8) Cut-Through Separation Configuration Register + * 26 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC26_b; + }; + + union + { + __IOM uint32_t FWCTSC36; /*!< (@ 0x000005AC) Cut-Through Separation Configuration Register + * 36 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC36_b; + }; + + union + { + __IOM uint32_t FWCTSC46; /*!< (@ 0x000005B0) Cut-Through Separation Configuration Register + * 46 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC46_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint32_t FWCTGC07; /*!< (@ 0x000005C0) Cut-Through General Configuration Register 07 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC07_b; + }; + + union + { + __IOM uint32_t FWCTGC17; /*!< (@ 0x000005C4) Cut-Through General Configuration Register 17 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC17_b; + }; + + union + { + __IOM uint32_t FWCTTC07; /*!< (@ 0x000005C8) Cut-Through Target Configuration Register 07 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC07_b; + }; + + union + { + __IOM uint32_t FWCTTC17; /*!< (@ 0x000005CC) Cut-Through Target Configuration Register 17 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC17_b; + }; + + union + { + __IOM uint32_t FWCTTC207; /*!< (@ 0x000005D0) Cut-Through Target Configuration Register 207 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC207_b; + }; + __IM uint32_t RESERVED23[3]; + + union + { + __IOM uint32_t FWCTSC07; /*!< (@ 0x000005E0) Cut-Through Separation Configuration Register + * 07 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC07_b; + }; + + union + { + __IOM uint32_t FWCTSC17; /*!< (@ 0x000005E4) Cut-Through Separation Configuration Register + * 17 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC17_b; + }; + + union + { + __IOM uint32_t FWCTSC27; /*!< (@ 0x000005E8) Cut-Through Separation Configuration Register + * 27 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC27_b; + }; + + union + { + __IOM uint32_t FWCTSC37; /*!< (@ 0x000005EC) Cut-Through Separation Configuration Register + * 37 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC37_b; + }; + + union + { + __IOM uint32_t FWCTSC47; /*!< (@ 0x000005F0) Cut-Through Separation Configuration Register + * 47 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC47_b; + }; + __IM uint32_t RESERVED24[643]; + + union + { + __IOM uint32_t FWTWBFC0; /*!< (@ 0x00001000) Two-Byte Filter Configuration Register 0 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC0_b; + }; + + union + { + __IOM uint32_t FWTWBFVC0; /*!< (@ 0x00001004) Two-Byte Filter Value Configuration Register + * 0 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC0_b; + }; + __IM uint32_t RESERVED25[2]; + + union + { + __IOM uint32_t FWTWBFC1; /*!< (@ 0x00001010) Two-Byte Filter Configuration Register 1 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC1_b; + }; + + union + { + __IOM uint32_t FWTWBFVC1; /*!< (@ 0x00001014) Two-Byte Filter Value Configuration Register + * 1 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC1_b; + }; + __IM uint32_t RESERVED26[2]; + + union + { + __IOM uint32_t FWTWBFC2; /*!< (@ 0x00001020) Two-Byte Filter Configuration Register 2 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC2_b; + }; + + union + { + __IOM uint32_t FWTWBFVC2; /*!< (@ 0x00001024) Two-Byte Filter Value Configuration Register + * 2 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC2_b; + }; + __IM uint32_t RESERVED27[2]; + + union + { + __IOM uint32_t FWTWBFC3; /*!< (@ 0x00001030) Two-Byte Filter Configuration Register 3 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC3_b; + }; + + union + { + __IOM uint32_t FWTWBFVC3; /*!< (@ 0x00001034) Two-Byte Filter Value Configuration Register + * 3 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC3_b; + }; + __IM uint32_t RESERVED28[2]; + + union + { + __IOM uint32_t FWTWBFC4; /*!< (@ 0x00001040) Two-Byte Filter Configuration Register 4 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC4_b; + }; + + union + { + __IOM uint32_t FWTWBFVC4; /*!< (@ 0x00001044) Two-Byte Filter Value Configuration Register + * 4 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC4_b; + }; + __IM uint32_t RESERVED29[2]; + + union + { + __IOM uint32_t FWTWBFC5; /*!< (@ 0x00001050) Two-Byte Filter Configuration Register 5 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC5_b; + }; + + union + { + __IOM uint32_t FWTWBFVC5; /*!< (@ 0x00001054) Two-Byte Filter Value Configuration Register + * 5 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC5_b; + }; + __IM uint32_t RESERVED30[2]; + + union + { + __IOM uint32_t FWTWBFC6; /*!< (@ 0x00001060) Two-Byte Filter Configuration Register 6 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC6_b; + }; + + union + { + __IOM uint32_t FWTWBFVC6; /*!< (@ 0x00001064) Two-Byte Filter Value Configuration Register + * 6 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC6_b; + }; + __IM uint32_t RESERVED31[2]; + + union + { + __IOM uint32_t FWTWBFC7; /*!< (@ 0x00001070) Two-Byte Filter Configuration Register 7 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC7_b; + }; + + union + { + __IOM uint32_t FWTWBFVC7; /*!< (@ 0x00001074) Two-Byte Filter Value Configuration Register + * 7 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC7_b; + }; + __IM uint32_t RESERVED32[2]; + + union + { + __IOM uint32_t FWTWBFC8; /*!< (@ 0x00001080) Two-Byte Filter Configuration Register 8 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC8_b; + }; + + union + { + __IOM uint32_t FWTWBFVC8; /*!< (@ 0x00001084) Two-Byte Filter Value Configuration Register + * 8 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC8_b; + }; + __IM uint32_t RESERVED33[2]; + + union + { + __IOM uint32_t FWTWBFC9; /*!< (@ 0x00001090) Two-Byte Filter Configuration Register 9 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC9_b; + }; + + union + { + __IOM uint32_t FWTWBFVC9; /*!< (@ 0x00001094) Two-Byte Filter Value Configuration Register + * 9 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC9_b; + }; + __IM uint32_t RESERVED34[2]; + + union + { + __IOM uint32_t FWTWBFC10; /*!< (@ 0x000010A0) Two-Byte Filter Configuration Register 10 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC10_b; + }; + + union + { + __IOM uint32_t FWTWBFVC10; /*!< (@ 0x000010A4) Two-Byte Filter Value Configuration Register + * 10 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC10_b; + }; + __IM uint32_t RESERVED35[2]; + + union + { + __IOM uint32_t FWTWBFC11; /*!< (@ 0x000010B0) Two-Byte Filter Configuration Register 11 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC11_b; + }; + + union + { + __IOM uint32_t FWTWBFVC11; /*!< (@ 0x000010B4) Two-Byte Filter Value Configuration Register + * 11 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC11_b; + }; + __IM uint32_t RESERVED36[2]; + + union + { + __IOM uint32_t FWTWBFC12; /*!< (@ 0x000010C0) Two-Byte Filter Configuration Register 12 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC12_b; + }; + + union + { + __IOM uint32_t FWTWBFVC12; /*!< (@ 0x000010C4) Two-Byte Filter Value Configuration Register + * 12 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC12_b; + }; + __IM uint32_t RESERVED37[2]; + + union + { + __IOM uint32_t FWTWBFC13; /*!< (@ 0x000010D0) Two-Byte Filter Configuration Register 13 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC13_b; + }; + + union + { + __IOM uint32_t FWTWBFVC13; /*!< (@ 0x000010D4) Two-Byte Filter Value Configuration Register + * 13 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC13_b; + }; + __IM uint32_t RESERVED38[2]; + + union + { + __IOM uint32_t FWTWBFC14; /*!< (@ 0x000010E0) Two-Byte Filter Configuration Register 14 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC14_b; + }; + + union + { + __IOM uint32_t FWTWBFVC14; /*!< (@ 0x000010E4) Two-Byte Filter Value Configuration Register + * 14 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC14_b; + }; + __IM uint32_t RESERVED39[2]; + + union + { + __IOM uint32_t FWTWBFC15; /*!< (@ 0x000010F0) Two-Byte Filter Configuration Register 15 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC15_b; + }; + + union + { + __IOM uint32_t FWTWBFVC15; /*!< (@ 0x000010F4) Two-Byte Filter Value Configuration Register + * 15 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC15_b; + }; + __IM uint32_t RESERVED40[194]; + + union + { + __IOM uint32_t FWTHBFC0; /*!< (@ 0x00001400) Three-Byte Filter Configuration Register 0 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC0_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C0; /*!< (@ 0x00001404) Three-Byte Filter Value 0 Configuration Register + * 0 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C0_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C0; /*!< (@ 0x00001408) Three-Byte Filter Value 1 Configuration Register + * 0 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C0_b; + }; + __IM uint32_t RESERVED41; + + union + { + __IOM uint32_t FWTHBFC1; /*!< (@ 0x00001410) Three-Byte Filter Configuration Register 1 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC1_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C1; /*!< (@ 0x00001414) Three-Byte Filter Value 0 Configuration Register + * 1 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C1_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C1; /*!< (@ 0x00001418) Three-Byte Filter Value 1 Configuration Register + * 1 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C1_b; + }; + __IM uint32_t RESERVED42; + + union + { + __IOM uint32_t FWTHBFC2; /*!< (@ 0x00001420) Three-Byte Filter Configuration Register 2 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC2_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C2; /*!< (@ 0x00001424) Three-Byte Filter Value 0 Configuration Register + * 2 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C2_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C2; /*!< (@ 0x00001428) Three-Byte Filter Value 1 Configuration Register + * 2 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C2_b; + }; + __IM uint32_t RESERVED43; + + union + { + __IOM uint32_t FWTHBFC3; /*!< (@ 0x00001430) Three-Byte Filter Configuration Register 3 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC3_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C3; /*!< (@ 0x00001434) Three-Byte Filter Value 0 Configuration Register + * 3 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C3_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C3; /*!< (@ 0x00001438) Three-Byte Filter Value 1 Configuration Register + * 3 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C3_b; + }; + __IM uint32_t RESERVED44; + + union + { + __IOM uint32_t FWTHBFC4; /*!< (@ 0x00001440) Three-Byte Filter Configuration Register 4 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC4_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C4; /*!< (@ 0x00001444) Three-Byte Filter Value 0 Configuration Register + * 4 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C4_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C4; /*!< (@ 0x00001448) Three-Byte Filter Value 1 Configuration Register + * 4 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C4_b; + }; + __IM uint32_t RESERVED45; + + union + { + __IOM uint32_t FWTHBFC5; /*!< (@ 0x00001450) Three-Byte Filter Configuration Register 5 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC5_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C5; /*!< (@ 0x00001454) Three-Byte Filter Value 0 Configuration Register + * 5 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C5_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C5; /*!< (@ 0x00001458) Three-Byte Filter Value 1 Configuration Register + * 5 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C5_b; + }; + __IM uint32_t RESERVED46; + + union + { + __IOM uint32_t FWTHBFC6; /*!< (@ 0x00001460) Three-Byte Filter Configuration Register 6 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC6_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C6; /*!< (@ 0x00001464) Three-Byte Filter Value 0 Configuration Register + * 6 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C6_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C6; /*!< (@ 0x00001468) Three-Byte Filter Value 1 Configuration Register + * 6 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C6_b; + }; + __IM uint32_t RESERVED47; + + union + { + __IOM uint32_t FWTHBFC7; /*!< (@ 0x00001470) Three-Byte Filter Configuration Register 7 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC7_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C7; /*!< (@ 0x00001474) Three-Byte Filter Value 0 Configuration Register + * 7 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C7_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C7; /*!< (@ 0x00001478) Three-Byte Filter Value 1 Configuration Register + * 7 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C7_b; + }; + __IM uint32_t RESERVED48; + + union + { + __IOM uint32_t FWTHBFC8; /*!< (@ 0x00001480) Three-Byte Filter Configuration Register 8 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC8_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C8; /*!< (@ 0x00001484) Three-Byte Filter Value 0 Configuration Register + * 8 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C8_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C8; /*!< (@ 0x00001488) Three-Byte Filter Value 1 Configuration Register + * 8 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C8_b; + }; + __IM uint32_t RESERVED49; + + union + { + __IOM uint32_t FWTHBFC9; /*!< (@ 0x00001490) Three-Byte Filter Configuration Register 9 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC9_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C9; /*!< (@ 0x00001494) Three-Byte Filter Value 0 Configuration Register + * 9 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C9_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C9; /*!< (@ 0x00001498) Three-Byte Filter Value 1 Configuration Register + * 9 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C9_b; + }; + __IM uint32_t RESERVED50; + + union + { + __IOM uint32_t FWTHBFC10; /*!< (@ 0x000014A0) Three-Byte Filter Configuration Register 10 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC10_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C10; /*!< (@ 0x000014A4) Three-Byte Filter Value 0 Configuration Register + * 10 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C10_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C10; /*!< (@ 0x000014A8) Three-Byte Filter Value 1 Configuration Register + * 10 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C10_b; + }; + __IM uint32_t RESERVED51; + + union + { + __IOM uint32_t FWTHBFC11; /*!< (@ 0x000014B0) Three-Byte Filter Configuration Register 11 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC11_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C11; /*!< (@ 0x000014B4) Three-Byte Filter Value 0 Configuration Register + * 11 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C11_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C11; /*!< (@ 0x000014B8) Three-Byte Filter Value 1 Configuration Register + * 11 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C11_b; + }; + __IM uint32_t RESERVED52; + + union + { + __IOM uint32_t FWTHBFC12; /*!< (@ 0x000014C0) Three-Byte Filter Configuration Register 12 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC12_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C12; /*!< (@ 0x000014C4) Three-Byte Filter Value 0 Configuration Register + * 12 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C12_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C12; /*!< (@ 0x000014C8) Three-Byte Filter Value 1 Configuration Register + * 12 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C12_b; + }; + __IM uint32_t RESERVED53; + + union + { + __IOM uint32_t FWTHBFC13; /*!< (@ 0x000014D0) Three-Byte Filter Configuration Register 13 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC13_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C13; /*!< (@ 0x000014D4) Three-Byte Filter Value 0 Configuration Register + * 13 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C13_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C13; /*!< (@ 0x000014D8) Three-Byte Filter Value 1 Configuration Register + * 13 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C13_b; + }; + __IM uint32_t RESERVED54; + + union + { + __IOM uint32_t FWTHBFC14; /*!< (@ 0x000014E0) Three-Byte Filter Configuration Register 14 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC14_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C14; /*!< (@ 0x000014E4) Three-Byte Filter Value 0 Configuration Register + * 14 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C14_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C14; /*!< (@ 0x000014E8) Three-Byte Filter Value 1 Configuration Register + * 14 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C14_b; + }; + __IM uint32_t RESERVED55; + + union + { + __IOM uint32_t FWTHBFC15; /*!< (@ 0x000014F0) Three-Byte Filter Configuration Register 15 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC15_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C15; /*!< (@ 0x000014F4) Three-Byte Filter Value 0 Configuration Register + * 15 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C15_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C15; /*!< (@ 0x000014F8) Three-Byte Filter Value 1 Configuration Register + * 15 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C15_b; + }; + __IM uint32_t RESERVED56[193]; + + union + { + __IOM uint32_t FWFOBFC0; /*!< (@ 0x00001800) Four-Byte Filter Configuration Register 0 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC0_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C0; /*!< (@ 0x00001804) Four-Byte Filter Value 0 Configuration Register + * 0 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C0_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C0; /*!< (@ 0x00001808) Four-Byte Filter Value 1 Configuration Register + * 0 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C0_b; + }; + __IM uint32_t RESERVED57; + + union + { + __IOM uint32_t FWFOBFC1; /*!< (@ 0x00001810) Four-Byte Filter Configuration Register 1 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC1_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C1; /*!< (@ 0x00001814) Four-Byte Filter Value 0 Configuration Register + * 1 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C1_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C1; /*!< (@ 0x00001818) Four-Byte Filter Value 1 Configuration Register + * 1 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C1_b; + }; + __IM uint32_t RESERVED58; + + union + { + __IOM uint32_t FWFOBFC2; /*!< (@ 0x00001820) Four-Byte Filter Configuration Register 2 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC2_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C2; /*!< (@ 0x00001824) Four-Byte Filter Value 0 Configuration Register + * 2 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C2_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C2; /*!< (@ 0x00001828) Four-Byte Filter Value 1 Configuration Register + * 2 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C2_b; + }; + __IM uint32_t RESERVED59; + + union + { + __IOM uint32_t FWFOBFC3; /*!< (@ 0x00001830) Four-Byte Filter Configuration Register 3 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC3_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C3; /*!< (@ 0x00001834) Four-Byte Filter Value 0 Configuration Register + * 3 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C3_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C3; /*!< (@ 0x00001838) Four-Byte Filter Value 1 Configuration Register + * 3 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C3_b; + }; + __IM uint32_t RESERVED60; + + union + { + __IOM uint32_t FWFOBFC4; /*!< (@ 0x00001840) Four-Byte Filter Configuration Register 4 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC4_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C4; /*!< (@ 0x00001844) Four-Byte Filter Value 0 Configuration Register + * 4 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C4_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C4; /*!< (@ 0x00001848) Four-Byte Filter Value 1 Configuration Register + * 4 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C4_b; + }; + __IM uint32_t RESERVED61; + + union + { + __IOM uint32_t FWFOBFC5; /*!< (@ 0x00001850) Four-Byte Filter Configuration Register 5 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC5_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C5; /*!< (@ 0x00001854) Four-Byte Filter Value 0 Configuration Register + * 5 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C5_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C5; /*!< (@ 0x00001858) Four-Byte Filter Value 1 Configuration Register + * 5 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C5_b; + }; + __IM uint32_t RESERVED62; + + union + { + __IOM uint32_t FWFOBFC6; /*!< (@ 0x00001860) Four-Byte Filter Configuration Register 6 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC6_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C6; /*!< (@ 0x00001864) Four-Byte Filter Value 0 Configuration Register + * 6 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C6_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C6; /*!< (@ 0x00001868) Four-Byte Filter Value 1 Configuration Register + * 6 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C6_b; + }; + __IM uint32_t RESERVED63; + + union + { + __IOM uint32_t FWFOBFC7; /*!< (@ 0x00001870) Four-Byte Filter Configuration Register 7 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC7_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C7; /*!< (@ 0x00001874) Four-Byte Filter Value 0 Configuration Register + * 7 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C7_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C7; /*!< (@ 0x00001878) Four-Byte Filter Value 1 Configuration Register + * 7 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C7_b; + }; + __IM uint32_t RESERVED64; + + union + { + __IOM uint32_t FWFOBFC8; /*!< (@ 0x00001880) Four-Byte Filter Configuration Register 8 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC8_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C8; /*!< (@ 0x00001884) Four-Byte Filter Value 0 Configuration Register + * 8 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C8_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C8; /*!< (@ 0x00001888) Four-Byte Filter Value 1 Configuration Register + * 8 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C8_b; + }; + __IM uint32_t RESERVED65; + + union + { + __IOM uint32_t FWFOBFC9; /*!< (@ 0x00001890) Four-Byte Filter Configuration Register 9 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC9_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C9; /*!< (@ 0x00001894) Four-Byte Filter Value 0 Configuration Register + * 9 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C9_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C9; /*!< (@ 0x00001898) Four-Byte Filter Value 1 Configuration Register + * 9 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C9_b; + }; + __IM uint32_t RESERVED66; + + union + { + __IOM uint32_t FWFOBFC10; /*!< (@ 0x000018A0) Four-Byte Filter Configuration Register 10 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC10_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C10; /*!< (@ 0x000018A4) Four-Byte Filter Value 0 Configuration Register + * 10 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C10_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C10; /*!< (@ 0x000018A8) Four-Byte Filter Value 1 Configuration Register + * 10 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C10_b; + }; + __IM uint32_t RESERVED67; + + union + { + __IOM uint32_t FWFOBFC11; /*!< (@ 0x000018B0) Four-Byte Filter Configuration Register 11 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC11_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C11; /*!< (@ 0x000018B4) Four-Byte Filter Value 0 Configuration Register + * 11 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C11_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C11; /*!< (@ 0x000018B8) Four-Byte Filter Value 1 Configuration Register + * 11 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C11_b; + }; + __IM uint32_t RESERVED68; + + union + { + __IOM uint32_t FWFOBFC12; /*!< (@ 0x000018C0) Four-Byte Filter Configuration Register 12 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC12_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C12; /*!< (@ 0x000018C4) Four-Byte Filter Value 0 Configuration Register + * 12 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C12_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C12; /*!< (@ 0x000018C8) Four-Byte Filter Value 1 Configuration Register + * 12 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C12_b; + }; + __IM uint32_t RESERVED69; + + union + { + __IOM uint32_t FWFOBFC13; /*!< (@ 0x000018D0) Four-Byte Filter Configuration Register 13 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC13_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C13; /*!< (@ 0x000018D4) Four-Byte Filter Value 0 Configuration Register + * 13 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C13_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C13; /*!< (@ 0x000018D8) Four-Byte Filter Value 1 Configuration Register + * 13 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C13_b; + }; + __IM uint32_t RESERVED70; + + union + { + __IOM uint32_t FWFOBFC14; /*!< (@ 0x000018E0) Four-Byte Filter Configuration Register 14 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC14_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C14; /*!< (@ 0x000018E4) Four-Byte Filter Value 0 Configuration Register + * 14 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C14_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C14; /*!< (@ 0x000018E8) Four-Byte Filter Value 1 Configuration Register + * 14 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C14_b; + }; + __IM uint32_t RESERVED71; + + union + { + __IOM uint32_t FWFOBFC15; /*!< (@ 0x000018F0) Four-Byte Filter Configuration Register 15 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC15_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C15; /*!< (@ 0x000018F4) Four-Byte Filter Value 0 Configuration Register + * 15 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C15_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C15; /*!< (@ 0x000018F8) Four-Byte Filter Value 1 Configuration Register + * 15 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C15_b; + }; + __IM uint32_t RESERVED72[193]; + + union + { + __IOM uint32_t FWRFC0; /*!< (@ 0x00001C00) Range Filter Configuration Register 0 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RFM : 1; /*!< [8..8] Range Filtering Mode */ + uint32_t : 7; + __IOM uint32_t RFOV : 8; /*!< [23..16] Range Filter Offset Value */ + uint32_t : 8; + } FWRFC0_b; + }; + + union + { + __IOM uint32_t FWRFVC0; /*!< (@ 0x00001C04) Range Filter Value Configuration Register 0 */ + + struct + { + __IOM uint32_t RFSV0 : 8; /*!< [7..0] Range Filter Start Value 0 */ + __IOM uint32_t RFSV1 : 8; /*!< [15..8] Range Filter Start Value 1 */ + __IOM uint32_t RFRV : 4; /*!< [19..16] Range Filter Range Value */ + uint32_t : 12; + } FWRFVC0_b; + }; + __IM uint32_t RESERVED73[2]; + + union + { + __IOM uint32_t FWRFC1; /*!< (@ 0x00001C10) Range Filter Configuration Register 1 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RFM : 1; /*!< [8..8] Range Filtering Mode */ + uint32_t : 7; + __IOM uint32_t RFOV : 8; /*!< [23..16] Range Filter Offset Value */ + uint32_t : 8; + } FWRFC1_b; + }; + + union + { + __IOM uint32_t FWRFVC1; /*!< (@ 0x00001C14) Range Filter Value Configuration Register 1 */ + + struct + { + __IOM uint32_t RFSV0 : 8; /*!< [7..0] Range Filter Start Value 0 */ + __IOM uint32_t RFSV1 : 8; /*!< [15..8] Range Filter Start Value 1 */ + __IOM uint32_t RFRV : 4; /*!< [19..16] Range Filter Range Value */ + uint32_t : 12; + } FWRFVC1_b; + }; + __IM uint32_t RESERVED74[250]; + + union + { + __IOM uint32_t FWCFC0; /*!< (@ 0x00002000) Cascade Filter Configuration Register 0 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC0_b; + }; + + union + { + __IOM uint32_t FWCFMC00; /*!< (@ 0x00002004) Cascade Filter Mapping Configuration Register + * 00 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC00_b; + }; + + union + { + __IOM uint32_t FWCFMC01; /*!< (@ 0x00002008) Cascade Filter Mapping Configuration Register + * 01 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC01_b; + }; + + union + { + __IOM uint32_t FWCFMC02; /*!< (@ 0x0000200C) Cascade Filter Mapping Configuration Register + * 02 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC02_b; + }; + + union + { + __IOM uint32_t FWCFMC03; /*!< (@ 0x00002010) Cascade Filter Mapping Configuration Register + * 03 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC03_b; + }; + + union + { + __IOM uint32_t FWCFMC04; /*!< (@ 0x00002014) Cascade Filter Mapping Configuration Register + * 04 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC04_b; + }; + + union + { + __IOM uint32_t FWCFMC05; /*!< (@ 0x00002018) Cascade Filter Mapping Configuration Register + * 05 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC05_b; + }; + + union + { + __IOM uint32_t FWCFMC06; /*!< (@ 0x0000201C) Cascade Filter Mapping Configuration Register + * 06 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC06_b; + }; + __IM uint32_t RESERVED75[8]; + + union + { + __IOM uint32_t FWCFC1; /*!< (@ 0x00002040) Cascade Filter Configuration Register 1 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC1_b; + }; + + union + { + __IOM uint32_t FWCFMC10; /*!< (@ 0x00002044) Cascade Filter Mapping Configuration Register + * 10 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC10_b; + }; + + union + { + __IOM uint32_t FWCFMC11; /*!< (@ 0x00002048) Cascade Filter Mapping Configuration Register + * 11 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC11_b; + }; + + union + { + __IOM uint32_t FWCFMC12; /*!< (@ 0x0000204C) Cascade Filter Mapping Configuration Register + * 12 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC12_b; + }; + + union + { + __IOM uint32_t FWCFMC13; /*!< (@ 0x00002050) Cascade Filter Mapping Configuration Register + * 13 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC13_b; + }; + + union + { + __IOM uint32_t FWCFMC14; /*!< (@ 0x00002054) Cascade Filter Mapping Configuration Register + * 14 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC14_b; + }; + + union + { + __IOM uint32_t FWCFMC15; /*!< (@ 0x00002058) Cascade Filter Mapping Configuration Register + * 15 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC15_b; + }; + + union + { + __IOM uint32_t FWCFMC16; /*!< (@ 0x0000205C) Cascade Filter Mapping Configuration Register + * 16 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC16_b; + }; + __IM uint32_t RESERVED76[8]; + + union + { + __IOM uint32_t FWCFC2; /*!< (@ 0x00002080) Cascade Filter Configuration Register 2 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC2_b; + }; + + union + { + __IOM uint32_t FWCFMC20; /*!< (@ 0x00002084) Cascade Filter Mapping Configuration Register + * 20 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC20_b; + }; + + union + { + __IOM uint32_t FWCFMC21; /*!< (@ 0x00002088) Cascade Filter Mapping Configuration Register + * 21 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC21_b; + }; + + union + { + __IOM uint32_t FWCFMC22; /*!< (@ 0x0000208C) Cascade Filter Mapping Configuration Register + * 22 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC22_b; + }; + + union + { + __IOM uint32_t FWCFMC23; /*!< (@ 0x00002090) Cascade Filter Mapping Configuration Register + * 23 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC23_b; + }; + + union + { + __IOM uint32_t FWCFMC24; /*!< (@ 0x00002094) Cascade Filter Mapping Configuration Register + * 24 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC24_b; + }; + + union + { + __IOM uint32_t FWCFMC25; /*!< (@ 0x00002098) Cascade Filter Mapping Configuration Register + * 25 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC25_b; + }; + + union + { + __IOM uint32_t FWCFMC26; /*!< (@ 0x0000209C) Cascade Filter Mapping Configuration Register + * 26 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC26_b; + }; + __IM uint32_t RESERVED77[8]; + + union + { + __IOM uint32_t FWCFC3; /*!< (@ 0x000020C0) Cascade Filter Configuration Register 3 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC3_b; + }; + + union + { + __IOM uint32_t FWCFMC30; /*!< (@ 0x000020C4) Cascade Filter Mapping Configuration Register + * 30 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC30_b; + }; + + union + { + __IOM uint32_t FWCFMC31; /*!< (@ 0x000020C8) Cascade Filter Mapping Configuration Register + * 31 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC31_b; + }; + + union + { + __IOM uint32_t FWCFMC32; /*!< (@ 0x000020CC) Cascade Filter Mapping Configuration Register + * 32 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC32_b; + }; + + union + { + __IOM uint32_t FWCFMC33; /*!< (@ 0x000020D0) Cascade Filter Mapping Configuration Register + * 33 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC33_b; + }; + + union + { + __IOM uint32_t FWCFMC34; /*!< (@ 0x000020D4) Cascade Filter Mapping Configuration Register + * 34 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC34_b; + }; + + union + { + __IOM uint32_t FWCFMC35; /*!< (@ 0x000020D8) Cascade Filter Mapping Configuration Register + * 35 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC35_b; + }; + + union + { + __IOM uint32_t FWCFMC36; /*!< (@ 0x000020DC) Cascade Filter Mapping Configuration Register + * 36 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC36_b; + }; + __IM uint32_t RESERVED78[8]; + + union + { + __IOM uint32_t FWCFC4; /*!< (@ 0x00002100) Cascade Filter Configuration Register 4 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC4_b; + }; + + union + { + __IOM uint32_t FWCFMC40; /*!< (@ 0x00002104) Cascade Filter Mapping Configuration Register + * 40 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC40_b; + }; + + union + { + __IOM uint32_t FWCFMC41; /*!< (@ 0x00002108) Cascade Filter Mapping Configuration Register + * 41 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC41_b; + }; + + union + { + __IOM uint32_t FWCFMC42; /*!< (@ 0x0000210C) Cascade Filter Mapping Configuration Register + * 42 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC42_b; + }; + + union + { + __IOM uint32_t FWCFMC43; /*!< (@ 0x00002110) Cascade Filter Mapping Configuration Register + * 43 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC43_b; + }; + + union + { + __IOM uint32_t FWCFMC44; /*!< (@ 0x00002114) Cascade Filter Mapping Configuration Register + * 44 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC44_b; + }; + + union + { + __IOM uint32_t FWCFMC45; /*!< (@ 0x00002118) Cascade Filter Mapping Configuration Register + * 45 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC45_b; + }; + + union + { + __IOM uint32_t FWCFMC46; /*!< (@ 0x0000211C) Cascade Filter Mapping Configuration Register + * 46 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC46_b; + }; + __IM uint32_t RESERVED79[8]; + + union + { + __IOM uint32_t FWCFC5; /*!< (@ 0x00002140) Cascade Filter Configuration Register 5 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC5_b; + }; + + union + { + __IOM uint32_t FWCFMC50; /*!< (@ 0x00002144) Cascade Filter Mapping Configuration Register + * 50 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC50_b; + }; + + union + { + __IOM uint32_t FWCFMC51; /*!< (@ 0x00002148) Cascade Filter Mapping Configuration Register + * 51 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC51_b; + }; + + union + { + __IOM uint32_t FWCFMC52; /*!< (@ 0x0000214C) Cascade Filter Mapping Configuration Register + * 52 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC52_b; + }; + + union + { + __IOM uint32_t FWCFMC53; /*!< (@ 0x00002150) Cascade Filter Mapping Configuration Register + * 53 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC53_b; + }; + + union + { + __IOM uint32_t FWCFMC54; /*!< (@ 0x00002154) Cascade Filter Mapping Configuration Register + * 54 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC54_b; + }; + + union + { + __IOM uint32_t FWCFMC55; /*!< (@ 0x00002158) Cascade Filter Mapping Configuration Register + * 55 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC55_b; + }; + + union + { + __IOM uint32_t FWCFMC56; /*!< (@ 0x0000215C) Cascade Filter Mapping Configuration Register + * 56 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC56_b; + }; + __IM uint32_t RESERVED80[8]; + + union + { + __IOM uint32_t FWCFC6; /*!< (@ 0x00002180) Cascade Filter Configuration Register 6 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC6_b; + }; + + union + { + __IOM uint32_t FWCFMC60; /*!< (@ 0x00002184) Cascade Filter Mapping Configuration Register + * 60 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC60_b; + }; + + union + { + __IOM uint32_t FWCFMC61; /*!< (@ 0x00002188) Cascade Filter Mapping Configuration Register + * 61 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC61_b; + }; + + union + { + __IOM uint32_t FWCFMC62; /*!< (@ 0x0000218C) Cascade Filter Mapping Configuration Register + * 62 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC62_b; + }; + + union + { + __IOM uint32_t FWCFMC63; /*!< (@ 0x00002190) Cascade Filter Mapping Configuration Register + * 63 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC63_b; + }; + + union + { + __IOM uint32_t FWCFMC64; /*!< (@ 0x00002194) Cascade Filter Mapping Configuration Register + * 64 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC64_b; + }; + + union + { + __IOM uint32_t FWCFMC65; /*!< (@ 0x00002198) Cascade Filter Mapping Configuration Register + * 65 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC65_b; + }; + + union + { + __IOM uint32_t FWCFMC66; /*!< (@ 0x0000219C) Cascade Filter Mapping Configuration Register + * 66 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC66_b; + }; + __IM uint32_t RESERVED81[8]; + + union + { + __IOM uint32_t FWCFC7; /*!< (@ 0x000021C0) Cascade Filter Configuration Register 7 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC7_b; + }; + + union + { + __IOM uint32_t FWCFMC70; /*!< (@ 0x000021C4) Cascade Filter Mapping Configuration Register + * 70 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC70_b; + }; + + union + { + __IOM uint32_t FWCFMC71; /*!< (@ 0x000021C8) Cascade Filter Mapping Configuration Register + * 71 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC71_b; + }; + + union + { + __IOM uint32_t FWCFMC72; /*!< (@ 0x000021CC) Cascade Filter Mapping Configuration Register + * 72 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC72_b; + }; + + union + { + __IOM uint32_t FWCFMC73; /*!< (@ 0x000021D0) Cascade Filter Mapping Configuration Register + * 73 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC73_b; + }; + + union + { + __IOM uint32_t FWCFMC74; /*!< (@ 0x000021D4) Cascade Filter Mapping Configuration Register + * 74 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC74_b; + }; + + union + { + __IOM uint32_t FWCFMC75; /*!< (@ 0x000021D8) Cascade Filter Mapping Configuration Register + * 75 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC75_b; + }; + + union + { + __IOM uint32_t FWCFMC76; /*!< (@ 0x000021DC) Cascade Filter Mapping Configuration Register + * 76 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC76_b; + }; + __IM uint32_t RESERVED82[8]; + + union + { + __IOM uint32_t FWCFC8; /*!< (@ 0x00002200) Cascade Filter Configuration Register 8 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC8_b; + }; + + union + { + __IOM uint32_t FWCFMC80; /*!< (@ 0x00002204) Cascade Filter Mapping Configuration Register + * 80 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC80_b; + }; + + union + { + __IOM uint32_t FWCFMC81; /*!< (@ 0x00002208) Cascade Filter Mapping Configuration Register + * 81 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC81_b; + }; + + union + { + __IOM uint32_t FWCFMC82; /*!< (@ 0x0000220C) Cascade Filter Mapping Configuration Register + * 82 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC82_b; + }; + + union + { + __IOM uint32_t FWCFMC83; /*!< (@ 0x00002210) Cascade Filter Mapping Configuration Register + * 83 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC83_b; + }; + + union + { + __IOM uint32_t FWCFMC84; /*!< (@ 0x00002214) Cascade Filter Mapping Configuration Register + * 84 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC84_b; + }; + + union + { + __IOM uint32_t FWCFMC85; /*!< (@ 0x00002218) Cascade Filter Mapping Configuration Register + * 85 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC85_b; + }; + + union + { + __IOM uint32_t FWCFMC86; /*!< (@ 0x0000221C) Cascade Filter Mapping Configuration Register + * 86 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC86_b; + }; + __IM uint32_t RESERVED83[8]; + + union + { + __IOM uint32_t FWCFC9; /*!< (@ 0x00002240) Cascade Filter Configuration Register 9 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC9_b; + }; + + union + { + __IOM uint32_t FWCFMC90; /*!< (@ 0x00002244) Cascade Filter Mapping Configuration Register + * 90 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC90_b; + }; + + union + { + __IOM uint32_t FWCFMC91; /*!< (@ 0x00002248) Cascade Filter Mapping Configuration Register + * 91 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC91_b; + }; + + union + { + __IOM uint32_t FWCFMC92; /*!< (@ 0x0000224C) Cascade Filter Mapping Configuration Register + * 92 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC92_b; + }; + + union + { + __IOM uint32_t FWCFMC93; /*!< (@ 0x00002250) Cascade Filter Mapping Configuration Register + * 93 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC93_b; + }; + + union + { + __IOM uint32_t FWCFMC94; /*!< (@ 0x00002254) Cascade Filter Mapping Configuration Register + * 94 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC94_b; + }; + + union + { + __IOM uint32_t FWCFMC95; /*!< (@ 0x00002258) Cascade Filter Mapping Configuration Register + * 95 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC95_b; + }; + + union + { + __IOM uint32_t FWCFMC96; /*!< (@ 0x0000225C) Cascade Filter Mapping Configuration Register + * 96 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC96_b; + }; + __IM uint32_t RESERVED84[8]; + + union + { + __IOM uint32_t FWCFC10; /*!< (@ 0x00002280) Cascade Filter Configuration Register 10 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC10_b; + }; + + union + { + __IOM uint32_t FWCFMC100; /*!< (@ 0x00002284) Cascade Filter Mapping Configuration Register + * 100 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC100_b; + }; + + union + { + __IOM uint32_t FWCFMC101; /*!< (@ 0x00002288) Cascade Filter Mapping Configuration Register + * 101 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC101_b; + }; + + union + { + __IOM uint32_t FWCFMC102; /*!< (@ 0x0000228C) Cascade Filter Mapping Configuration Register + * 102 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC102_b; + }; + + union + { + __IOM uint32_t FWCFMC103; /*!< (@ 0x00002290) Cascade Filter Mapping Configuration Register + * 103 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC103_b; + }; + + union + { + __IOM uint32_t FWCFMC104; /*!< (@ 0x00002294) Cascade Filter Mapping Configuration Register + * 104 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC104_b; + }; + + union + { + __IOM uint32_t FWCFMC105; /*!< (@ 0x00002298) Cascade Filter Mapping Configuration Register + * 105 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC105_b; + }; + + union + { + __IOM uint32_t FWCFMC106; /*!< (@ 0x0000229C) Cascade Filter Mapping Configuration Register + * 106 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC106_b; + }; + __IM uint32_t RESERVED85[8]; + + union + { + __IOM uint32_t FWCFC11; /*!< (@ 0x000022C0) Cascade Filter Configuration Register 11 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC11_b; + }; + + union + { + __IOM uint32_t FWCFMC110; /*!< (@ 0x000022C4) Cascade Filter Mapping Configuration Register + * 110 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC110_b; + }; + + union + { + __IOM uint32_t FWCFMC111; /*!< (@ 0x000022C8) Cascade Filter Mapping Configuration Register + * 111 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC111_b; + }; + + union + { + __IOM uint32_t FWCFMC112; /*!< (@ 0x000022CC) Cascade Filter Mapping Configuration Register + * 112 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC112_b; + }; + + union + { + __IOM uint32_t FWCFMC113; /*!< (@ 0x000022D0) Cascade Filter Mapping Configuration Register + * 113 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC113_b; + }; + + union + { + __IOM uint32_t FWCFMC114; /*!< (@ 0x000022D4) Cascade Filter Mapping Configuration Register + * 114 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC114_b; + }; + + union + { + __IOM uint32_t FWCFMC115; /*!< (@ 0x000022D8) Cascade Filter Mapping Configuration Register + * 115 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC115_b; + }; + + union + { + __IOM uint32_t FWCFMC116; /*!< (@ 0x000022DC) Cascade Filter Mapping Configuration Register + * 116 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC116_b; + }; + __IM uint32_t RESERVED86[8]; + + union + { + __IOM uint32_t FWCFC12; /*!< (@ 0x00002300) Cascade Filter Configuration Register 12 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC12_b; + }; + + union + { + __IOM uint32_t FWCFMC120; /*!< (@ 0x00002304) Cascade Filter Mapping Configuration Register + * 120 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC120_b; + }; + + union + { + __IOM uint32_t FWCFMC121; /*!< (@ 0x00002308) Cascade Filter Mapping Configuration Register + * 121 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC121_b; + }; + + union + { + __IOM uint32_t FWCFMC122; /*!< (@ 0x0000230C) Cascade Filter Mapping Configuration Register + * 122 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC122_b; + }; + + union + { + __IOM uint32_t FWCFMC123; /*!< (@ 0x00002310) Cascade Filter Mapping Configuration Register + * 123 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC123_b; + }; + + union + { + __IOM uint32_t FWCFMC124; /*!< (@ 0x00002314) Cascade Filter Mapping Configuration Register + * 124 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC124_b; + }; + + union + { + __IOM uint32_t FWCFMC125; /*!< (@ 0x00002318) Cascade Filter Mapping Configuration Register + * 125 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC125_b; + }; + + union + { + __IOM uint32_t FWCFMC126; /*!< (@ 0x0000231C) Cascade Filter Mapping Configuration Register + * 126 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC126_b; + }; + __IM uint32_t RESERVED87[8]; + + union + { + __IOM uint32_t FWCFC13; /*!< (@ 0x00002340) Cascade Filter Configuration Register 13 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC13_b; + }; + + union + { + __IOM uint32_t FWCFMC130; /*!< (@ 0x00002344) Cascade Filter Mapping Configuration Register + * 130 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC130_b; + }; + + union + { + __IOM uint32_t FWCFMC131; /*!< (@ 0x00002348) Cascade Filter Mapping Configuration Register + * 131 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC131_b; + }; + + union + { + __IOM uint32_t FWCFMC132; /*!< (@ 0x0000234C) Cascade Filter Mapping Configuration Register + * 132 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC132_b; + }; + + union + { + __IOM uint32_t FWCFMC133; /*!< (@ 0x00002350) Cascade Filter Mapping Configuration Register + * 133 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC133_b; + }; + + union + { + __IOM uint32_t FWCFMC134; /*!< (@ 0x00002354) Cascade Filter Mapping Configuration Register + * 134 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC134_b; + }; + + union + { + __IOM uint32_t FWCFMC135; /*!< (@ 0x00002358) Cascade Filter Mapping Configuration Register + * 135 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC135_b; + }; + + union + { + __IOM uint32_t FWCFMC136; /*!< (@ 0x0000235C) Cascade Filter Mapping Configuration Register + * 136 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC136_b; + }; + __IM uint32_t RESERVED88[8]; + + union + { + __IOM uint32_t FWCFC14; /*!< (@ 0x00002380) Cascade Filter Configuration Register 14 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC14_b; + }; + + union + { + __IOM uint32_t FWCFMC140; /*!< (@ 0x00002384) Cascade Filter Mapping Configuration Register + * 140 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC140_b; + }; + + union + { + __IOM uint32_t FWCFMC141; /*!< (@ 0x00002388) Cascade Filter Mapping Configuration Register + * 141 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC141_b; + }; + + union + { + __IOM uint32_t FWCFMC142; /*!< (@ 0x0000238C) Cascade Filter Mapping Configuration Register + * 142 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC142_b; + }; + + union + { + __IOM uint32_t FWCFMC143; /*!< (@ 0x00002390) Cascade Filter Mapping Configuration Register + * 143 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC143_b; + }; + + union + { + __IOM uint32_t FWCFMC144; /*!< (@ 0x00002394) Cascade Filter Mapping Configuration Register + * 144 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC144_b; + }; + + union + { + __IOM uint32_t FWCFMC145; /*!< (@ 0x00002398) Cascade Filter Mapping Configuration Register + * 145 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC145_b; + }; + + union + { + __IOM uint32_t FWCFMC146; /*!< (@ 0x0000239C) Cascade Filter Mapping Configuration Register + * 146 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC146_b; + }; + __IM uint32_t RESERVED89[8]; + + union + { + __IOM uint32_t FWCFC15; /*!< (@ 0x000023C0) Cascade Filter Configuration Register 15 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC15_b; + }; + + union + { + __IOM uint32_t FWCFMC150; /*!< (@ 0x000023C4) Cascade Filter Mapping Configuration Register + * 150 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC150_b; + }; + + union + { + __IOM uint32_t FWCFMC151; /*!< (@ 0x000023C8) Cascade Filter Mapping Configuration Register + * 151 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC151_b; + }; + + union + { + __IOM uint32_t FWCFMC152; /*!< (@ 0x000023CC) Cascade Filter Mapping Configuration Register + * 152 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC152_b; + }; + + union + { + __IOM uint32_t FWCFMC153; /*!< (@ 0x000023D0) Cascade Filter Mapping Configuration Register + * 153 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC153_b; + }; + + union + { + __IOM uint32_t FWCFMC154; /*!< (@ 0x000023D4) Cascade Filter Mapping Configuration Register + * 154 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC154_b; + }; + + union + { + __IOM uint32_t FWCFMC155; /*!< (@ 0x000023D8) Cascade Filter Mapping Configuration Register + * 155 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC155_b; + }; + + union + { + __IOM uint32_t FWCFMC156; /*!< (@ 0x000023DC) Cascade Filter Mapping Configuration Register + * 156 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC156_b; + }; + __IM uint32_t RESERVED90[1802]; + + union + { + __IOM uint32_t FWIP4SC; /*!< (@ 0x00004008) IPv4 Stream Configuration Register */ + + struct + { + __IOM uint32_t IP4IMDH : 1; /*!< [0..0] IPv4 Include MAC Destination in Hash */ + __IOM uint32_t IP4IMSH : 1; /*!< [1..1] IPv4 Include MAC Source in Hash */ + __IOM uint32_t IP4ISVH : 1; /*!< [2..2] IPv4 Include S-TAG VLAN ID in Hash */ + __IOM uint32_t IP4ISPH : 1; /*!< [3..3] IPv4 Include S-TAG PCP in Hash */ + __IOM uint32_t IP4ISDH : 1; /*!< [4..4] IPv4 Include S-TAG DEI in Hash */ + __IOM uint32_t IP4ICVH : 1; /*!< [5..5] IPv4 Include C-TAG VLAN ID in Hash */ + __IOM uint32_t IP4ICPH : 1; /*!< [6..6] IPv4 Include C-TAG PCP in Hash */ + __IOM uint32_t IP4ICDH : 1; /*!< [7..7] IPv4 Include C-TAG DEI in Hash */ + __IOM uint32_t IP4IISH : 1; /*!< [8..8] IPv4 Include IP Source in Hash */ + __IOM uint32_t IP4IIDH : 1; /*!< [9..9] IPv4 Include IP Destination in Hash */ + __IOM uint32_t IP4IPH : 1; /*!< [10..10] IPv4 Include Protocol in Hash */ + __IOM uint32_t IP4ISPTH : 1; /*!< [11..11] IPv4 Include Source Port in Hash */ + __IOM uint32_t IP4IDPTH : 1; /*!< [12..12] IPv4 Include Destination Port in Hash */ + uint32_t : 3; + __IOM uint32_t IP4ISVS : 1; /*!< [16..16] IPv4 Include S-TAG VLAN ID in Stream */ + __IOM uint32_t IP4ISPS : 1; /*!< [17..17] IPv4 Include S-TAG PCP in Stream */ + __IOM uint32_t IP4ISDS : 1; /*!< [18..18] IPv4 Include S-TAG DEI in Stream */ + __IOM uint32_t IP4ICVS : 1; /*!< [19..19] IPv4 Include C-TAG VLAN ID in Stream */ + __IOM uint32_t IP4ICPS : 1; /*!< [20..20] IPv4 Include C-TAG PCP in Stream */ + __IOM uint32_t IP4ICDS : 1; /*!< [21..21] IPv4 Include C-TAG DEI in Stream */ + __IOM uint32_t IP4IISS : 1; /*!< [22..22] IPv4 Include IP Source in Stream */ + __IOM uint32_t IP4IIDS : 1; /*!< [23..23] IPv4 Include IP Destination in Stream */ + __IOM uint32_t IP4IDPTS : 1; /*!< [24..24] IPv4 Include Destination Port in Stream */ + uint32_t : 7; + } FWIP4SC_b; + }; + __IM uint32_t RESERVED91[3]; + + union + { + __IOM uint32_t FWIP6SC; /*!< (@ 0x00004018) IPv6 Stream Configuration Register */ + + struct + { + __IOM uint32_t IP6IMDH : 1; /*!< [0..0] IPv6 Include MAC Destination in Hash */ + __IOM uint32_t IP6IMSH : 1; /*!< [1..1] IPv6 Include MAC Source in Hash */ + __IOM uint32_t IP6ISVH : 1; /*!< [2..2] IPv6 Include S-TAG VLAN ID in Hash */ + __IOM uint32_t IP6ISPH : 1; /*!< [3..3] IPv6 Include S-TAG PCP in Hash */ + __IOM uint32_t IP6ISDH : 1; /*!< [4..4] IPv6 Include S-TAG DEI in Hash */ + __IOM uint32_t IP6ICVH : 1; /*!< [5..5] IPv6 Include C-TAG VLAN ID in Hash */ + __IOM uint32_t IP6ICPH : 1; /*!< [6..6] IPv6 Include C-TAG PCP in Hash */ + __IOM uint32_t IP6ICDH : 1; /*!< [7..7] IPv6 Include C-TAG DEI in Hash */ + __IOM uint32_t IP6IISH : 1; /*!< [8..8] IPv6 Include IP Source in Hash */ + __IOM uint32_t IP6IIDH : 1; /*!< [9..9] IPv6 Include IP Destination in Hash */ + __IOM uint32_t IP6IPH : 1; /*!< [10..10] IPv6 Include Protocol in Hash */ + __IOM uint32_t IP6ISPTH : 1; /*!< [11..11] IPv6 Include Source Port in Hash */ + __IOM uint32_t IP6IDPTH : 1; /*!< [12..12] IPv6 Include Destination Port in Hash */ + uint32_t : 3; + __IOM uint32_t IP6ISVS : 1; /*!< [16..16] IPv6 Include S-TAG VLAN ID in Stream */ + __IOM uint32_t IP6ISPS : 1; /*!< [17..17] IPv6 Include S-TAG PCP in Stream */ + __IOM uint32_t IP6ISDS : 1; /*!< [18..18] IPv6 Include S-TAG DEI in Stream */ + __IOM uint32_t IP6ICVS : 1; /*!< [19..19] IPv6 Include C-TAG VLAN ID in Stream */ + __IOM uint32_t IP6ICPS : 1; /*!< [20..20] IPv6 Include C-TAG PCP in Stream */ + __IOM uint32_t IP6ICDS : 1; /*!< [21..21] IPv6 Include C-TAG DEI in Stream */ + __IOM uint32_t IP6II0S : 1; /*!< [22..22] IPv6 Include IP 0 in Stream */ + __IOM uint32_t IP6II1S : 1; /*!< [23..23] IPv6 Include IP 1 in Stream */ + __IOM uint32_t IP6IDPTS : 1; /*!< [24..24] IPv6 Include Destination Port in Stream */ + uint32_t : 7; + } FWIP6SC_b; + }; + + union + { + __IOM uint32_t FWIP6OC; /*!< (@ 0x0000401C) IPv6 Offset Configuration Register */ + + struct + { + __IOM uint32_t IP6IPOM0 : 1; /*!< [0..0] IPv6 IP Offset mode 0 */ + uint32_t : 3; + __IOM uint32_t IP6IPO0 : 4; /*!< [7..4] IPv6 IP Offset 0 */ + uint32_t : 8; + __IOM uint32_t IP6IPOM1 : 1; /*!< [16..16] IPv6 IP Offset mode 1 */ + uint32_t : 3; + __IOM uint32_t IP6IPO1 : 4; /*!< [23..20] IPv6 IP Offset 1 */ + uint32_t : 8; + } FWIP6OC_b; + }; + + union + { + __IOM uint32_t FWL2SC; /*!< (@ 0x00004020) Layer 2 Stream Configuration Register */ + + struct + { + __IOM uint32_t L2IMDS : 1; /*!< [0..0] Layer 2 Include MAC Destination in Stream */ + __IOM uint32_t L2IMSS : 1; /*!< [1..1] Layer 2 Include MAC Source in Stream */ + __IOM uint32_t L2ISVS : 1; /*!< [2..2] Layer 2 Include S-TAG VLAN ID in Stream */ + __IOM uint32_t L2ISPS : 1; /*!< [3..3] Layer 2 Include S-TAG PCP ID in Stream */ + __IOM uint32_t L2ISDS : 1; /*!< [4..4] Layer 2 Include S-TAG DEI in Stream */ + __IOM uint32_t L2ICVS : 1; /*!< [5..5] Layer 2 Include C-TAG VLAN ID in Stream */ + __IOM uint32_t L2ICPS : 1; /*!< [6..6] Layer 2 Include C-TAG PCP ID in Stream */ + __IOM uint32_t L2ICDS : 1; /*!< [7..7] Layer 2 Include C-TAG DEI in Stream */ + uint32_t : 24; + } FWL2SC_b; + }; + __IM uint32_t RESERVED92[3]; + + union + { + __IOM uint32_t FWSFHEC; /*!< (@ 0x00004030) Stream Filter Hash Equation Configuration Register */ + + struct + { + __IOM uint32_t IP4HE : 16; /*!< [15..0] Stream Filter Hash Equation */ + __IOM uint32_t IP6HE : 16; /*!< [31..16] Stream Filter Hash Equation */ + } FWSFHEC_b; + }; + __IM uint32_t RESERVED93[3]; + + union + { + __IOM uint32_t FWSHCR0; /*!< (@ 0x00004040) Software Hash Calculation Request Register 0 */ + + struct + { + __IOM uint32_t SHCMDP0 : 32; /*!< [31..0] Software Hash Calculation MAC Destination Part 0 */ + } FWSHCR0_b; + }; + + union + { + __IOM uint32_t FWSHCR1; /*!< (@ 0x00004044) Software Hash Calculation Request Register 1 */ + + struct + { + __IOM uint32_t SHCMSP0 : 16; /*!< [15..0] Software Hash Calculation MAC Source Part 0 */ + __IOM uint32_t SHCMDP1 : 16; /*!< [31..16] Software Hash Calculation MAC Destination Part 1 */ + } FWSHCR1_b; + }; + + union + { + __IOM uint32_t FWSHCR2; /*!< (@ 0x00004048) Software Hash Calculation Request Register 2 */ + + struct + { + __IOM uint32_t SHCMSP1 : 32; /*!< [31..0] Software Hash Calculation MAC Source Part 1 */ + } FWSHCR2_b; + }; + + union + { + __IOM uint32_t FWSHCR3; /*!< (@ 0x0000404C) Software Hash Calculation Request Register 3 */ + + struct + { + __IOM uint32_t SHCCV : 12; /*!< [11..0] Software Hash Calculation C-TAG VLAN */ + __IOM uint32_t SHCCD : 1; /*!< [12..12] Software Hash Calculation C-TAG DEI */ + __IOM uint32_t SHCCP : 3; /*!< [15..13] Software Hash Calculation C-TAG PCP */ + __IOM uint32_t SHCSV : 12; /*!< [27..16] Software Hash Calculation S-TAG VLANs */ + __IOM uint32_t SHCSD : 1; /*!< [28..28] Software Hash Calculation S-TAG DEI */ + __IOM uint32_t SHCSP : 3; /*!< [31..29] Software Hash Calculation S-TAG PCP */ + } FWSHCR3_b; + }; + + union + { + __IOM uint32_t FWSHCR4; /*!< (@ 0x00004050) Software Hash Calculation Request Register 4 */ + + struct + { + __IOM uint32_t SHCP : 8; /*!< [7..0] Software Hash Calculation Protocol (NextHeader for IPv6) */ + uint32_t : 8; + __IOM uint32_t SHCFF : 1; /*!< [16..16] Software Hash Calculation Frame Format */ + uint32_t : 15; + } FWSHCR4_b; + }; + + union + { + __IOM uint32_t FWSHCR5; /*!< (@ 0x00004054) Software Hash Calculation Request Register 5 */ + + struct + { + __IOM uint32_t SHCISP0 : 32; /*!< [31..0] Software Hash Calculation IP Source Part 0 */ + } FWSHCR5_b; + }; + + union + { + __IOM uint32_t FWSHCR6; /*!< (@ 0x00004058) Software Hash Calculation Request Register 6 */ + + struct + { + __IOM uint32_t SHCISP1 : 32; /*!< [31..0] Software Hash Calculation IP Source Part 1 */ + } FWSHCR6_b; + }; + + union + { + __IOM uint32_t FWSHCR7; /*!< (@ 0x0000405C) Software Hash Calculation Request Register 7 */ + + struct + { + __IOM uint32_t SHCISP2 : 32; /*!< [31..0] Software Hash Calculation IP Source Part 2 */ + } FWSHCR7_b; + }; + + union + { + __IOM uint32_t FWSHCR8; /*!< (@ 0x00004060) Software Hash Calculation Request Register 8 */ + + struct + { + __IOM uint32_t SHCISP3 : 32; /*!< [31..0] Software Hash Calculation IP Source Part 3 */ + } FWSHCR8_b; + }; + + union + { + __IOM uint32_t FWSHCR9; /*!< (@ 0x00004064) Software Hash Calculation Request Register 9 */ + + struct + { + __IOM uint32_t SHCIDP0 : 32; /*!< [31..0] Software Hash Calculation IP Destination Part 0 */ + } FWSHCR9_b; + }; + + union + { + __IOM uint32_t FWSHCR10; /*!< (@ 0x00004068) Software Hash Calculation Request Register 10 */ + + struct + { + __IOM uint32_t SHCIDP1 : 32; /*!< [31..0] Software Hash Calculation IP Destination Part 1 */ + } FWSHCR10_b; + }; + + union + { + __IOM uint32_t FWSHCR11; /*!< (@ 0x0000406C) Software Hash Calculation Request Register 11 */ + + struct + { + __IOM uint32_t SHCIDP2 : 32; /*!< [31..0] Software Hash Calculation IP Destination Part 2 */ + } FWSHCR11_b; + }; + + union + { + __IOM uint32_t FWSHCR12; /*!< (@ 0x00004070) Software Hash Calculation Request Register 12 */ + + struct + { + __IOM uint32_t SHCIDP3 : 32; /*!< [31..0] Software Hash Calculation IP Destination Part 3 */ + } FWSHCR12_b; + }; + + union + { + __IOM uint32_t FWSHCR13; /*!< (@ 0x00004074) Software Hash Calculation Request Register 13 */ + + struct + { + __IOM uint32_t SHCDP : 16; /*!< [15..0] Software Hash Calculation Destination Port */ + __IOM uint32_t SHCSP : 16; /*!< [31..16] Software Hash Calculation Source Port */ + } FWSHCR13_b; + }; + + union + { + __IM uint32_t FWSHCRR; /*!< (@ 0x00004078) Software Hash Calculation Request Result Register */ + + struct + { + __IM uint32_t SHCR : 16; /*!< [15..0] Software Hash Calculation Result */ + uint32_t : 15; + __IM uint32_t SHC : 1; /*!< [31..31] Software Hash Calculation */ + } FWSHCRR_b; + }; + __IM uint32_t RESERVED94[5]; + + union + { + __IOM uint32_t FWLTHHEC; /*!< (@ 0x00004090) L3 Hash Entry Configuration Register */ + + struct + { + __IOM uint32_t LTHHMC : 10; /*!< [9..0] L3 Hash Maximum Collision */ + uint32_t : 6; + __IOM uint32_t LTHHMUE : 11; /*!< [26..16] L3 Hash Maximum Unsecure Entry */ + uint32_t : 5; + } FWLTHHEC_b; + }; + + union + { + __IOM uint32_t FWLTHHC; /*!< (@ 0x00004094) L3 Hash Configuration Register */ + + struct + { + __IOM uint32_t LTHHE : 10; /*!< [9..0] L3 Hash Equation */ + uint32_t : 22; + } FWLTHHC_b; + }; + __IM uint32_t RESERVED95[2]; + + union + { + __IOM uint32_t FWLTHTL0; /*!< (@ 0x000040A0) L3 Table Learn Register 0 */ + + struct + { + __IOM uint32_t LTHSLP0 : 3; /*!< [2..0] L3 Stream Learn Part 0 */ + uint32_t : 5; + __IOM uint32_t LTHSLL : 1; /*!< [8..8] L3 Security Level Learn */ + uint32_t : 7; + __IOM uint32_t LTHED : 1; /*!< [16..16] L3 Entry Delete */ + uint32_t : 15; + } FWLTHTL0_b; + }; + + union + { + __IOM uint32_t FWLTHTL1; /*!< (@ 0x000040A4) L3 Table Learn Register 1 */ + + struct + { + __IOM uint32_t LTHSLP1 : 32; /*!< [31..0] L3 Stream Learn Part 1 */ + } FWLTHTL1_b; + }; + + union + { + __IOM uint32_t FWLTHTL2; /*!< (@ 0x000040A8) L3 Table Learn Register 2 */ + + struct + { + __IOM uint32_t LTHSLP2 : 32; /*!< [31..0] L3 Stream Learn Part 2 */ + } FWLTHTL2_b; + }; + + union + { + __IOM uint32_t FWLTHTL3; /*!< (@ 0x000040AC) L3 Table Learn Register 3 */ + + struct + { + __IOM uint32_t LTHSLP3 : 32; /*!< [31..0] L3 Stream Learn Part 3 */ + } FWLTHTL3_b; + }; + + union + { + __IOM uint32_t FWLTHTL4; /*!< (@ 0x000040B0) L3 Table Learn Register 4 */ + + struct + { + __IOM uint32_t LTHSLP4 : 32; /*!< [31..0] L3 Stream Learn Part 4 */ + } FWLTHTL4_b; + }; + + union + { + __IOM uint32_t FWLTHTL5; /*!< (@ 0x000040B4) L3 Table Learn Register 5 */ + + struct + { + uint32_t : 16; + __IOM uint32_t LTHMSDUNL : 4; /*!< [19..16] L3 MSDU Number Learn */ + uint32_t : 11; + __IOM uint32_t LTHMSDUVL : 1; /*!< [31..31] L3 MSDU Valid Learn */ + } FWLTHTL5_b; + }; + + union + { + __IOM uint32_t FWLTHTL6; /*!< (@ 0x000040B8) L3 Table Learn Register 6 */ + + struct + { + __IOM uint32_t LTHFRERNL : 7; /*!< [6..0] L3 FRER Number Learn */ + uint32_t : 8; + __IOM uint32_t LTHFRERVL : 1; /*!< [15..15] L3 FRER Valid Learn */ + __IOM uint32_t LTHMTRNL : 5; /*!< [20..16] L3 MeTeR Number Learn */ + uint32_t : 10; + __IOM uint32_t LTHMTRVL : 1; /*!< [31..31] L3 MeTeR Valid Learn */ + } FWLTHTL6_b; + }; + + union + { + __IOM uint32_t FWLTHTL7; /*!< (@ 0x000040BC) L3 Table Learn Register 7 */ + + struct + { + __IOM uint32_t LTHRNL : 8; /*!< [7..0] L3 Routing Number Learn */ + uint32_t : 7; + __IOM uint32_t LTHRVL : 1; /*!< [15..15] L3 Routing Valid Learn */ + __IOM uint32_t LTHSLVL : 7; /*!< [22..16] L3 Source Lock Vector Learn */ + uint32_t : 9; + } FWLTHTL7_b; + }; + + union + { + __IOM uint32_t FWLTHTL80; /*!< (@ 0x000040C0) L3 Table Learn Register 80 */ + + struct + { + __IOM uint32_t LTHCSDL : 7; /*!< [6..0] L3 CPU Sub-Destination Learn */ + uint32_t : 25; + } FWLTHTL80_b; + }; + __IM uint32_t RESERVED96[3]; + + union + { + __IOM uint32_t FWLTHTL9; /*!< (@ 0x000040D0) L3 Table Learn Register 9 */ + + struct + { + __IOM uint32_t LTHDVL : 7; /*!< [6..0] L3 Destination Vector Learn */ + uint32_t : 9; + __IOM uint32_t LTHIPVL : 3; /*!< [18..16] L3 Internal Priority Value Learn */ + __IOM uint32_t LTHIPUL : 1; /*!< [19..19] L3 Internal Priority Update Learn */ + __IOM uint32_t LTHEMEL : 1; /*!< [20..20] L3 Ethernet Mirroring Enable Learn */ + __IOM uint32_t LTHCMEL : 1; /*!< [21..21] L3 CPU Mirroring Enable Learn */ + uint32_t : 10; + } FWLTHTL9_b; + }; + + union + { + __IM uint32_t FWLTHTLR; /*!< (@ 0x000040D4) L3 Table Learn Result Register */ + + struct + { + __IM uint32_t LTHLF : 1; /*!< [0..0] L3 Learn Fail */ + __IM uint32_t LTHLSF : 1; /*!< [1..1] L3 Learn Security Fail */ + __IM uint32_t LTHLEF : 1; /*!< [2..2] L3 Learn ECC Fail */ + __IM uint32_t LTHLO : 1; /*!< [3..3] L3 Learn Overwrite */ + uint32_t : 12; + __IM uint32_t LTHLCN : 10; /*!< [25..16] L3 Learn Collision Number */ + uint32_t : 5; + __IM uint32_t LTHTL : 1; /*!< [31..31] L3 Table Learn */ + } FWLTHTLR_b; + }; + __IM uint32_t RESERVED97[2]; + + union + { + __IOM uint32_t FWLTHTIM; /*!< (@ 0x000040E0) L3 Table Initialization Monitoring Register */ + + struct + { + __IOM uint32_t LTHTIOG : 1; /*!< [0..0] L3 Table Initialization Ongoing */ + __IM uint32_t LTHTR : 1; /*!< [1..1] L3 Table Ready */ + uint32_t : 30; + } FWLTHTIM_b; + }; + + union + { + __IM uint32_t FWLTHTEM; /*!< (@ 0x000040E4) L3 Table Entry Monitoring Register */ + + struct + { + __IM uint32_t LTHTEN : 11; /*!< [10..0] L3 Table Entry Number */ + uint32_t : 5; + __IM uint32_t LTHTUEN : 11; /*!< [26..16] L3 Table Unsecure Entry Number */ + uint32_t : 5; + } FWLTHTEM_b; + }; + __IM uint32_t RESERVED98[6]; + + union + { + __IOM uint32_t FWLTHTS0; /*!< (@ 0x00004100) L3 Table Search Register 0 */ + + struct + { + __IOM uint32_t LTHSSP0 : 3; /*!< [2..0] L3 Stream Search Part 0 */ + uint32_t : 21; + __IOM uint32_t LTHSSPFS : 1; /*!< [24..24] L3 Stream Search Perfect Filter Select */ + uint32_t : 7; + } FWLTHTS0_b; + }; + + union + { + __IOM uint32_t FWLTHTS1; /*!< (@ 0x00004104) L3 Table Search Register 1 */ + + struct + { + __IOM uint32_t LTHSSP1 : 32; /*!< [31..0] L3 Stream Search Part 1 */ + } FWLTHTS1_b; + }; + + union + { + __IOM uint32_t FWLTHTS2; /*!< (@ 0x00004108) L3 Table Search Register 2 */ + + struct + { + __IOM uint32_t LTHSSP2 : 32; /*!< [31..0] L3 Stream Search Part 2 */ + } FWLTHTS2_b; + }; + + union + { + __IOM uint32_t FWLTHTS3; /*!< (@ 0x0000410C) L3 Table Search Register 3 */ + + struct + { + __IOM uint32_t LTHSSP3 : 32; /*!< [31..0] L3 Stream Search Part 3 */ + } FWLTHTS3_b; + }; + + union + { + __IOM uint32_t FWLTHTS4; /*!< (@ 0x00004110) L3 Table Search Register 4 */ + + struct + { + __IOM uint32_t LTHSSP4 : 32; /*!< [31..0] L3 Stream Search Part 4 */ + } FWLTHTS4_b; + }; + __IM uint32_t RESERVED99[3]; + + union + { + __IOM uint32_t FWLTHTSR0; /*!< (@ 0x00004120) L3 Table Search Result Register 0 */ + + struct + { + __IOM uint32_t LTHSEF : 1; /*!< [0..0] L3 Search ECC Fail */ + __IM uint32_t LTHSNF : 1; /*!< [1..1] L3 Search Not found */ + uint32_t : 6; + __IM uint32_t LTHSLS : 1; /*!< [8..8] L3 Security Level Search */ + uint32_t : 7; + __IM uint32_t LTHSCN : 10; /*!< [25..16] L3 Search Collision Number */ + uint32_t : 5; + __IM uint32_t LTHTS : 1; /*!< [31..31] L3 Table Search */ + } FWLTHTSR0_b; + }; + + union + { + __IM uint32_t FWLTHTSR1; /*!< (@ 0x00004124) L3 Table Search Result Register 1 */ + + struct + { + uint32_t : 16; + __IM uint32_t LTHMSDUNS : 4; /*!< [19..16] L3 MSDU Number Search */ + uint32_t : 11; + __IM uint32_t LTHMSDUVS : 1; /*!< [31..31] L3 MSDU Valid Search */ + } FWLTHTSR1_b; + }; + + union + { + __IM uint32_t FWLTHTSR2; /*!< (@ 0x00004128) L3 Table Search Result Register 2 */ + + struct + { + __IM uint32_t LTHFRERNS : 6; /*!< [5..0] L3 FRER Number Search */ + uint32_t : 9; + __IM uint32_t LTHFRERVS : 1; /*!< [15..15] L3 FRER Valid Search */ + __IM uint32_t LTHMTRNS : 5; /*!< [20..16] L3 MeTeR Number Search */ + uint32_t : 10; + __IM uint32_t LTHMTRVS : 1; /*!< [31..31] L3 MeTeR Valid Search */ + } FWLTHTSR2_b; + }; + + union + { + __IM uint32_t FWLTHTSR3; /*!< (@ 0x0000412C) L3 Table Search Result Register 3 */ + + struct + { + __IM uint32_t LTHRNS : 8; /*!< [7..0] L3 Routing Number Search */ + uint32_t : 7; + __IM uint32_t LTHRVS : 1; /*!< [15..15] L3 Routing Valid Search */ + __IM uint32_t LTHSLVS : 7; /*!< [22..16] L3 Source Lock Vector Search */ + uint32_t : 9; + } FWLTHTSR3_b; + }; + + union + { + __IM uint32_t FWLTHTSR40; /*!< (@ 0x00004130) L3 Table Search Result Register 40 */ + + struct + { + __IM uint32_t LTHCSDS : 7; /*!< [6..0] L3 CPU Sub-Destination Search */ + uint32_t : 25; + } FWLTHTSR40_b; + }; + __IM uint32_t RESERVED100[3]; + + union + { + __IM uint32_t FWLTHTSR5; /*!< (@ 0x00004140) L3 Table Search Result Register 5 */ + + struct + { + __IM uint32_t LTHDVS : 7; /*!< [6..0] L3 Destination Vector Search */ + uint32_t : 9; + __IM uint32_t LTHIPVS : 3; /*!< [18..16] L3 Internal Priority Value Search */ + __IM uint32_t LTHIPUS : 1; /*!< [19..19] L3 Internal Priority Update Search */ + __IM uint32_t LTHEMES : 1; /*!< [20..20] L3 Ethernet Mirroring Enable Search */ + __IM uint32_t LTHCMES : 1; /*!< [21..21] L3 CPU Mirroring Enable Search */ + uint32_t : 10; + } FWLTHTSR5_b; + }; + __IM uint32_t RESERVED101[3]; + + union + { + __IOM uint32_t FWLTHTR; /*!< (@ 0x00004150) L3 Table Read Register */ + + struct + { + __IOM uint32_t LTHAR : 10; /*!< [9..0] L3 Address Read */ + uint32_t : 22; + } FWLTHTR_b; + }; + + union + { + __IM uint32_t FWLTHTRR0; /*!< (@ 0x00004154) L3 Table Read Result Register 0 */ + + struct + { + __IM uint32_t LTHREF : 1; /*!< [0..0] L3 Read ECC Fail */ + __IM uint32_t LTHEVR : 1; /*!< [1..1] L3 Entry Valid Read */ + uint32_t : 29; + __IM uint32_t LTHTR : 1; /*!< [31..31] L3 Table Read */ + } FWLTHTRR0_b; + }; + + union + { + __IM uint32_t FWLTHTRR1; /*!< (@ 0x00004158) L3 Table Read Result Register 1 */ + + struct + { + __IM uint32_t LTHSRP0 : 3; /*!< [2..0] L3 Stream Read Part 0 */ + uint32_t : 5; + __IM uint32_t LTHSLR : 1; /*!< [8..8] L3 Security Level Read */ + uint32_t : 23; + } FWLTHTRR1_b; + }; + + union + { + __IM uint32_t FWLTHTRR2; /*!< (@ 0x0000415C) L3 Table Read Result Register 2 */ + + struct + { + __IM uint32_t LTHSRP1 : 32; /*!< [31..0] L3 Stream Read Part 1 */ + } FWLTHTRR2_b; + }; + + union + { + __IM uint32_t FWLTHTRR3; /*!< (@ 0x00004160) L3 Table Read Result Register 3 */ + + struct + { + __IM uint32_t LTHSRP2 : 32; /*!< [31..0] L3 Stream Read Part 2 */ + } FWLTHTRR3_b; + }; + + union + { + __IM uint32_t FWLTHTRR4; /*!< (@ 0x00004164) L3 Table Read Result Register 4 */ + + struct + { + __IM uint32_t LTHSRP3 : 32; /*!< [31..0] L3 Stream Read Part 3 */ + } FWLTHTRR4_b; + }; + + union + { + __IM uint32_t FWLTHTRR5; /*!< (@ 0x00004168) L3 Table Read Result Register 5 */ + + struct + { + __IM uint32_t LTHSRP4 : 32; /*!< [31..0] L3 Stream Read Part 4 */ + } FWLTHTRR5_b; + }; + + union + { + __IM uint32_t FWLTHTRR6; /*!< (@ 0x0000416C) L3 Table Read Result Register 6 */ + + struct + { + uint32_t : 16; + __IM uint32_t LTHMSDUNR : 4; /*!< [19..16] L3 MSDU Number Read */ + uint32_t : 11; + __IM uint32_t LTHMSDUVR : 1; /*!< [31..31] L3 MSDU Valid Read */ + } FWLTHTRR6_b; + }; + + union + { + __IM uint32_t FWLTHTRR7; /*!< (@ 0x00004170) L3 Table Read Result Register 7 */ + + struct + { + __IM uint32_t LTHFRERNR : 6; /*!< [5..0] L3 FRER Number Read */ + uint32_t : 9; + __IM uint32_t LTHFRERVR : 1; /*!< [15..15] L3 FRER Valid Read */ + __IM uint32_t LTHMTRNR : 5; /*!< [20..16] L3 MeTeR Number Read */ + uint32_t : 10; + __IM uint32_t LTHMTRVR : 1; /*!< [31..31] L3 MeTeR Valid Read */ + } FWLTHTRR7_b; + }; + + union + { + __IM uint32_t FWLTHTRR8; /*!< (@ 0x00004174) L3 Table Read Result Register 8 */ + + struct + { + __IM uint32_t LTHRNR : 8; /*!< [7..0] L3 Routing Number Read */ + uint32_t : 7; + __IM uint32_t LTHRVR : 1; /*!< [15..15] L3 Routing Valid Read */ + __IM uint32_t LTHSLVR : 7; /*!< [22..16] L3 Source Lock Vector Read */ + uint32_t : 9; + } FWLTHTRR8_b; + }; + __IM uint32_t RESERVED102[2]; + + union + { + __IM uint32_t FWLTHTRR90; /*!< (@ 0x00004180) L3 Table Read Result Register 90 */ + + struct + { + __IM uint32_t LTHCSDR : 7; /*!< [6..0] L3 CPU Sub-Destination Read */ + uint32_t : 25; + } FWLTHTRR90_b; + }; + __IM uint32_t RESERVED103[3]; + + union + { + __IM uint32_t FWLTHTRR10; /*!< (@ 0x00004190) L3 Table Read Result Register 10 */ + + struct + { + __IM uint32_t LTHDVR : 7; /*!< [6..0] L3 Destination Vector Read */ + uint32_t : 9; + __IM uint32_t LTHIPVR : 3; /*!< [18..16] L3 Internal Priority Value Read */ + __IM uint32_t LTHIPUR : 1; /*!< [19..19] L3 Internal Priority Update Read */ + __IM uint32_t LTHEMER : 1; /*!< [20..20] L3 Ethernet Mirroring Enable Read */ + __IM uint32_t LTHCMER : 1; /*!< [21..21] L3 CPU Mirroring Enable Read */ + uint32_t : 10; + } FWLTHTRR10_b; + }; + __IM uint32_t RESERVED104[291]; + + union + { + __IOM uint32_t FWMACHEC; /*!< (@ 0x00004620) MAC Hash Entry Configuration Register */ + + struct + { + __IOM uint32_t MACHMC : 11; /*!< [10..0] MAC Hash Maximum Collision */ + uint32_t : 5; + __IOM uint32_t MACHMUE : 12; /*!< [27..16] MAC Hash Maximum Unsecure Entry */ + uint32_t : 4; + } FWMACHEC_b; + }; + + union + { + __IOM uint32_t FWMACHC; /*!< (@ 0x00004624) MAC Hash Configuration Register */ + + struct + { + __IOM uint32_t MACHE : 11; /*!< [10..0] MAC Hash Equation */ + uint32_t : 21; + } FWMACHC_b; + }; + __IM uint32_t RESERVED105[2]; + + union + { + __IOM uint32_t FWMACTL0; /*!< (@ 0x00004630) MAC Table Learn Register 0 */ + + struct + { + uint32_t : 8; + __IOM uint32_t MACSLL : 1; /*!< [8..8] MAC Security Level Learn */ + __IOM uint32_t MACDEL : 1; /*!< [9..9] MAC Dynamic Entry Limit */ + __IOM uint32_t MACHLDL : 1; /*!< [10..10] MAC Hardware Learning Disable Learn */ + uint32_t : 5; + __IOM uint32_t MACED : 1; /*!< [16..16] MAC Entry Delete */ + uint32_t : 15; + } FWMACTL0_b; + }; + + union + { + __IOM uint32_t FWMACTL1; /*!< (@ 0x00004634) MAC Table Learn Register 1 */ + + struct + { + __IOM uint32_t MACMALP0 : 16; /*!< [15..0] MAC MAC address Learn Part 0 */ + uint32_t : 16; + } FWMACTL1_b; + }; + + union + { + __IOM uint32_t FWMACTL2; /*!< (@ 0x00004638) MAC Table Learn Register 2 */ + + struct + { + __IOM uint32_t MACMALP1 : 32; /*!< [31..0] MAC MAC address Learn Part 1 */ + } FWMACTL2_b; + }; + + union + { + __IOM uint32_t FWMACTL3; /*!< (@ 0x0000463C) MAC Table Learn Register 3 */ + + struct + { + __IOM uint32_t MACSSLVL : 7; /*!< [6..0] MAC Source Source Lock Vector Learn */ + uint32_t : 9; + __IOM uint32_t MACDSLVL : 7; /*!< [22..16] MAC Destination Source Lock Vector Learn */ + uint32_t : 9; + } FWMACTL3_b; + }; + + union + { + __IOM uint32_t FWMACTL40; /*!< (@ 0x00004640) MAC Table Learn Register 40 */ + + struct + { + __IOM uint32_t MACCSDL : 7; /*!< [6..0] MAC CPU Sub-Destination Learn */ + uint32_t : 25; + } FWMACTL40_b; + }; + __IM uint32_t RESERVED106[3]; + + union + { + __IOM uint32_t FWMACTL5; /*!< (@ 0x00004650) MAC Table Learn Register 5 */ + + struct + { + __IOM uint32_t MACDVL : 7; /*!< [6..0] MAC Destination Vector Learn */ + uint32_t : 9; + __IOM uint32_t MACIPVL : 3; /*!< [18..16] MAC Internal Priority Value Learn */ + __IOM uint32_t MACIPUL : 1; /*!< [19..19] MAC Internal Priority Update Learn */ + __IOM uint32_t MACEMEL : 1; /*!< [20..20] MAC Ethernet Mirroring Enable Learn */ + __IOM uint32_t MACCMEL : 1; /*!< [21..21] MAC CPU Mirroring Enable Learn */ + uint32_t : 10; + } FWMACTL5_b; + }; + + union + { + __IM uint32_t FWMACTLR; /*!< (@ 0x00004654) MAC Table Learn Result Register */ + + struct + { + __IM uint32_t MACLF : 1; /*!< [0..0] MAC Learn Fail */ + __IM uint32_t MACLSF : 1; /*!< [1..1] MAC Learn Security Fail */ + __IM uint32_t MACLEF : 1; /*!< [2..2] MAC Learn ECC Fail */ + __IM uint32_t MACLO : 1; /*!< [3..3] MAC Learn Overwrite */ + uint32_t : 12; + __IM uint32_t MACLCN : 10; /*!< [25..16] MAC Learn Collision Number */ + uint32_t : 5; + __IM uint32_t MACTL : 1; /*!< [31..31] MAC Table Learn */ + } FWMACTLR_b; + }; + __IM uint32_t RESERVED107[2]; + + union + { + __IOM uint32_t FWMACTIM; /*!< (@ 0x00004660) MAC Table Initialization Monitoring Register */ + + struct + { + __IOM uint32_t MACTIOG : 1; /*!< [0..0] MAC Table Initialization Ongoing */ + __IM uint32_t MACTR : 1; /*!< [1..1] MAC Table Ready */ + uint32_t : 30; + } FWMACTIM_b; + }; + + union + { + __IM uint32_t FWMACTEM; /*!< (@ 0x00004664) MAC Table Entry Monitoring Register */ + + struct + { + __IM uint32_t MACTEN : 11; /*!< [10..0] MAC Table Entry Number */ + uint32_t : 5; + __IM uint32_t MACTUEN : 11; /*!< [26..16] MAC Table Unsecure Entry Number */ + uint32_t : 5; + } FWMACTEM_b; + }; + __IM uint32_t RESERVED108[2]; + + union + { + __IOM uint32_t FWMACTS0; /*!< (@ 0x00004670) MAC Table Search Register 0 */ + + struct + { + __IOM uint32_t MACMASP0 : 16; /*!< [15..0] MAC MAC Address Search Part 0 */ + uint32_t : 16; + } FWMACTS0_b; + }; + + union + { + __IOM uint32_t FWMACTS1; /*!< (@ 0x00004674) MAC Table Search Register 1 */ + + struct + { + __IOM uint32_t MACMASP1 : 32; /*!< [31..0] MAC MAC Address Search Part 1 */ + } FWMACTS1_b; + }; + + union + { + __IOM uint32_t FWMACTSR0; /*!< (@ 0x00004678) MAC Table Search Result Register 0 */ + + struct + { + __IOM uint32_t MACSEF : 1; /*!< [0..0] MAC Search ECC Fail */ + __IM uint32_t MACSNF : 1; /*!< [1..1] MAC Search Not found */ + uint32_t : 6; + __IM uint32_t MACSLS : 1; /*!< [8..8] MAC Security Level Search */ + __IM uint32_t MACDES : 1; /*!< [9..9] MAC Dynamic Entry Search */ + __IM uint32_t MACHLDS : 1; /*!< [10..10] MAC Hardware Learning Disable Search */ + uint32_t : 5; + __IM uint32_t MACSCN : 10; /*!< [25..16] MAC Search Collision Number */ + uint32_t : 5; + __IM uint32_t MACTS : 1; /*!< [31..31] MAC Table Search */ + } FWMACTSR0_b; + }; + + union + { + __IM uint32_t FWMACTSR1; /*!< (@ 0x0000467C) MAC Table Search Result Register 1 */ + + struct + { + __IM uint32_t MACSSLVS : 7; /*!< [6..0] MAC Source Source Lock Vector Search */ + uint32_t : 9; + __IM uint32_t MACDSLVS : 7; /*!< [22..16] MAC Destination Source Lock Vector Search */ + uint32_t : 9; + } FWMACTSR1_b; + }; + + union + { + __IM uint32_t FWMACTSR20; /*!< (@ 0x00004680) MAC Table Search Result Register 20 */ + + struct + { + __IM uint32_t MACCSDS : 7; /*!< [6..0] MAC CPU Sub-Destination Search */ + uint32_t : 25; + } FWMACTSR20_b; + }; + __IM uint32_t RESERVED109[3]; + + union + { + __IM uint32_t FWMACTSR3; /*!< (@ 0x00004690) MAC Table Search Result Register 3 */ + + struct + { + __IM uint32_t MACDVS : 7; /*!< [6..0] MAC Destination Vector Search */ + uint32_t : 9; + __IM uint32_t MACIPVS : 3; /*!< [18..16] MAC Internal Priority Value Search */ + __IM uint32_t MACIPUS : 1; /*!< [19..19] MAC Internal Priority Update Search */ + __IM uint32_t MACEMES : 1; /*!< [20..20] MAC Ethernet Mirroring Enable Search */ + __IM uint32_t MACCMES : 1; /*!< [21..21] MAC CPU Mirroring Enable Search */ + uint32_t : 10; + } FWMACTSR3_b; + }; + __IM uint32_t RESERVED110[3]; + + union + { + __IOM uint32_t FWMACTR; /*!< (@ 0x000046A0) MAC Table Read Register */ + + struct + { + __IOM uint32_t MACAR : 10; /*!< [9..0] MAC Address Read */ + uint32_t : 22; + } FWMACTR_b; + }; + + union + { + __IM uint32_t FWMACTRR0; /*!< (@ 0x000046A4) MAC Table Read Result Register 0 */ + + struct + { + __IM uint32_t MACEVR : 1; /*!< [0..0] MAC Entry Valid Read */ + __IM uint32_t MACREF : 1; /*!< [1..1] MAC Read ECC Fail */ + uint32_t : 29; + __IM uint32_t MACTR : 1; /*!< [31..31] MAC Table Read */ + } FWMACTRR0_b; + }; + + union + { + __IM uint32_t FWMACTRR1; /*!< (@ 0x000046A8) MAC Table Read Result Register 1 */ + + struct + { + uint32_t : 8; + __IM uint32_t MACSLR : 1; /*!< [8..8] MAC Security Level Read */ + __IM uint32_t MACDER : 1; /*!< [9..9] MAC Dynamic Entry Read */ + __IM uint32_t MACHLDR : 1; /*!< [10..10] MAC Hardware Learn Disable Read */ + __IM uint32_t MACABR : 1; /*!< [11..11] MAC Aging Bit Read */ + uint32_t : 20; + } FWMACTRR1_b; + }; + + union + { + __IM uint32_t FWMACTRR2; /*!< (@ 0x000046AC) MAC Table Read Result Register 2 */ + + struct + { + __IM uint32_t MACMARP0 : 16; /*!< [15..0] MAC MAC address Read Part 0 */ + uint32_t : 16; + } FWMACTRR2_b; + }; + + union + { + __IM uint32_t FWMACTRR3; /*!< (@ 0x000046B0) MAC Table Read Result Register 3 */ + + struct + { + __IM uint32_t MACMARP1 : 32; /*!< [31..0] MAC MAC address Read Part 1 */ + } FWMACTRR3_b; + }; + + union + { + __IM uint32_t FWMACTRR4; /*!< (@ 0x000046B4) MAC Table Read Result Register 4 */ + + struct + { + __IM uint32_t MACSSLVR : 7; /*!< [6..0] MAC Source Source Lock Vector Read */ + uint32_t : 9; + __IM uint32_t MACDSLVR : 7; /*!< [22..16] MAC Destination Source Lock Vector Read */ + uint32_t : 9; + } FWMACTRR4_b; + }; + __IM uint32_t RESERVED111[2]; + + union + { + __IM uint32_t FWMACTRR50; /*!< (@ 0x000046C0) MAC Table Read Result Register 50 */ + + struct + { + __IM uint32_t MACCSDR : 7; /*!< [6..0] MAC CPU Sub-Destination Read */ + uint32_t : 25; + } FWMACTRR50_b; + }; + __IM uint32_t RESERVED112[3]; + + union + { + __IM uint32_t FWMACTRR6; /*!< (@ 0x000046D0) MAC Table Read Result Register 6 */ + + struct + { + __IM uint32_t MACDVR : 7; /*!< [6..0] MAC Destination Vector Read */ + uint32_t : 9; + __IM uint32_t MACIPVR : 3; /*!< [18..16] MAC Internal Priority Value Read */ + __IM uint32_t MACIPUR : 1; /*!< [19..19] MAC Internal Priority Update Read */ + __IM uint32_t MACEMER : 1; /*!< [20..20] MAC Ethernet Mirroring Enable Read */ + __IM uint32_t MACCMER : 1; /*!< [21..21] MAC CPU Mirroring Enable Read */ + uint32_t : 10; + } FWMACTRR6_b; + }; + __IM uint32_t RESERVED113[107]; + + union + { + __IOM uint32_t FWMACAGUSPC; /*!< (@ 0x00004880) MAC Aging US Prescaler Configuration Register */ + + struct + { + __IOM uint32_t MACAGUSP : 10; /*!< [9..0] MAC Aging US prescaler */ + uint32_t : 22; + } FWMACAGUSPC_b; + }; + + union + { + __IOM uint32_t FWMACAGC; /*!< (@ 0x00004884) MAC Aging Configuration Register */ + + struct + { + __IOM uint32_t MACAGT : 16; /*!< [15..0] MAC Aging Time */ + __IOM uint32_t MACAGE : 1; /*!< [16..16] MAC Aging Enable */ + __IOM uint32_t MACAGSL : 1; /*!< [17..17] MAC Aging Security Level */ + __IOM uint32_t MACAGPM : 1; /*!< [18..18] MAC Aging Polling Mode */ + uint32_t : 5; + __IM uint32_t MACDES : 1; /*!< [24..24] MAC Dynamic Entry Suppression */ + uint32_t : 3; + __IM uint32_t MACAGOG : 1; /*!< [28..28] MAC Aging OnGoing */ + __IM uint32_t MACDESOG : 1; /*!< [29..29] MAC Dynamic Entry Suppression OnGoing */ + uint32_t : 2; + } FWMACAGC_b; + }; + + union + { + __IM uint32_t FWMACAGM0; /*!< (@ 0x00004888) MAC Aging Monitoring Register 0 */ + + struct + { + __IM uint32_t AGMACAP0 : 16; /*!< [15..0] Aged MAC Address Part 0 */ + uint32_t : 16; + } FWMACAGM0_b; + }; + + union + { + __IM uint32_t FWMACAGM1; /*!< (@ 0x0000488C) MAC Aging Monitoring Register 1 */ + + struct + { + __IM uint32_t AGMACAP1 : 32; /*!< [31..0] Aged MAC Address Part 1 */ + } FWMACAGM1_b; + }; + __IM uint32_t RESERVED114[28]; + + union + { + __IOM uint32_t FWVLANTEC; /*!< (@ 0x00004900) VLAN Table Entry Configuration Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t VLANTMUE : 13; /*!< [28..16] VLAN Table Maximum Unsecure Entry */ + uint32_t : 3; + } FWVLANTEC_b; + }; + __IM uint32_t RESERVED115[3]; + + union + { + __IOM uint32_t FWVLANTL0; /*!< (@ 0x00004910) VLAN Table Learn Register 0 */ + + struct + { + uint32_t : 8; + __IOM uint32_t VLANSLL : 1; /*!< [8..8] VLAN Security Level Learn */ + uint32_t : 1; + __IOM uint32_t VLANHLDL : 1; /*!< [10..10] VLAN Hardware Learning Disable Learn */ + uint32_t : 5; + __IOM uint32_t VLANED : 1; /*!< [16..16] VLAN Entry Delete */ + uint32_t : 15; + } FWVLANTL0_b; + }; + + union + { + __IOM uint32_t FWVLANTL1; /*!< (@ 0x00004914) VLAN Table Learn Register 1 */ + + struct + { + __IOM uint32_t VLANVIDL : 12; /*!< [11..0] VLAN VID Learn */ + uint32_t : 20; + } FWVLANTL1_b; + }; + + union + { + __IOM uint32_t FWVLANTL2; /*!< (@ 0x00004918) VLAN Table Learn Register 2 */ + + struct + { + __IOM uint32_t VLANSLVL : 7; /*!< [6..0] VLAN Source Lock Vector Learn */ + uint32_t : 25; + } FWVLANTL2_b; + }; + __IM uint32_t RESERVED116; + + union + { + __IOM uint32_t FWVLANTL30; /*!< (@ 0x00004920) VLAN Table Learn Register 30 */ + + struct + { + __IOM uint32_t VLANCSDL : 7; /*!< [6..0] VLAN CPU Sub-Destination Learn */ + uint32_t : 25; + } FWVLANTL30_b; + }; + __IM uint32_t RESERVED117[3]; + + union + { + __IOM uint32_t FWVLANTL4; /*!< (@ 0x00004930) VLAN Table Learn Register 4 */ + + struct + { + __IOM uint32_t VLANDVL : 7; /*!< [6..0] VLAN Destination Vector Learn */ + uint32_t : 9; + __IOM uint32_t VLANIPVL : 3; /*!< [18..16] VLAN Internal Priority Value Learn */ + __IOM uint32_t VLANIPUL : 1; /*!< [19..19] VLAN Internal Priority Update Learn */ + __IOM uint32_t VLANEMEL : 1; /*!< [20..20] VLAN Ethernet Mirroring Enable Learn */ + __IOM uint32_t VLANCMEL : 1; /*!< [21..21] VLAN CPU Mirroring Enable Learn */ + uint32_t : 10; + } FWVLANTL4_b; + }; + + union + { + __IM uint32_t FWVLANTLR; /*!< (@ 0x00004934) VLAN Table Learn Result Register */ + + struct + { + __IM uint32_t VLANLF : 1; /*!< [0..0] VLAN Learn Fail */ + __IM uint32_t VLANLSF : 1; /*!< [1..1] VLAN Learn Security Fail */ + __IM uint32_t VLANLEF : 1; /*!< [2..2] VLAN Learn ECC Fail */ + __IM uint32_t VLANLO : 1; /*!< [3..3] VLAN Learn Overwrite */ + uint32_t : 27; + __IM uint32_t VLANTL : 1; /*!< [31..31] VLAN Table Learn */ + } FWVLANTLR_b; + }; + __IM uint32_t RESERVED118[2]; + + union + { + __IOM uint32_t FWVLANTIM; /*!< (@ 0x00004940) VLAN Table Initialization Monitoring Register */ + + struct + { + __IOM uint32_t VLANTIOG : 1; /*!< [0..0] VLAN Table Initialization Ongoing */ + __IM uint32_t VLANTR : 1; /*!< [1..1] VLAN Table Ready */ + uint32_t : 30; + } FWVLANTIM_b; + }; + + union + { + __IM uint32_t FWVLANTEM; /*!< (@ 0x00004944) VLAN Table Entry Monitoring Register */ + + struct + { + __IM uint32_t VLANTEN : 13; /*!< [12..0] VLAN Table Entry Number */ + uint32_t : 3; + __IM uint32_t VLANTUEN : 13; /*!< [28..16] VLAN Table Unsecure Entry Number */ + uint32_t : 3; + } FWVLANTEM_b; + }; + __IM uint32_t RESERVED119[2]; + + union + { + __IOM uint32_t FWVLANTS; /*!< (@ 0x00004950) VLAN Table Search Register */ + + struct + { + __IOM uint32_t VLANVIDS : 12; /*!< [11..0] VLAN VID Search */ + uint32_t : 20; + } FWVLANTS_b; + }; + + union + { + __IM uint32_t FWVLANTSR0; /*!< (@ 0x00004954) VLAN Table Search Result Register 0 */ + + struct + { + __IM uint32_t VLANSEF : 1; /*!< [0..0] VLAN Search ECC Fail */ + __IM uint32_t VLANSNF : 1; /*!< [1..1] VLAN Search Not found */ + uint32_t : 6; + __IM uint32_t VLANSLS : 1; /*!< [8..8] VLAN Security Level Search */ + uint32_t : 1; + __IM uint32_t VLANHLDS : 1; /*!< [10..10] VLAN Hardware Learning Disable Search */ + uint32_t : 20; + __IM uint32_t VLANTS : 1; /*!< [31..31] VLAN Table Search */ + } FWVLANTSR0_b; + }; + + union + { + __IM uint32_t FWVLANTSR1; /*!< (@ 0x00004958) VLAN Table Search Result Register 1 */ + + struct + { + __IM uint32_t VLANSLVS : 7; /*!< [6..0] VLAN Source Lock Vector Search */ + uint32_t : 25; + } FWVLANTSR1_b; + }; + __IM uint32_t RESERVED120; + + union + { + __IM uint32_t FWVLANTSR20; /*!< (@ 0x00004960) VLAN Table Search Result Register 20 */ + + struct + { + __IM uint32_t VLANCSDS : 7; /*!< [6..0] VLAN CPU Sub-Destination Search */ + uint32_t : 25; + } FWVLANTSR20_b; + }; + __IM uint32_t RESERVED121[3]; + + union + { + __IM uint32_t FWVLANTSR3; /*!< (@ 0x00004970) VLAN Table Search Result Register 3 */ + + struct + { + __IM uint32_t VLANDVS : 7; /*!< [6..0] VLAN Destination Vector Search */ + uint32_t : 9; + __IM uint32_t VLANIPVS : 3; /*!< [18..16] VLAN Internal Priority Value Search */ + __IM uint32_t VLANIPUS : 1; /*!< [19..19] VLAN Internal Priority Update Search */ + __IM uint32_t VLANEMES : 1; /*!< [20..20] VLAN Ethernet Mirroring Enable Search */ + __IM uint32_t VLANCMES : 1; /*!< [21..21] VLAN CPU Mirroring Enable Search */ + uint32_t : 10; + } FWVLANTSR3_b; + }; + __IM uint32_t RESERVED122[35]; + + union + { + __IOM uint32_t FWPBFC0; /*!< (@ 0x00004A00) Port Based Forwarding Configuration Register + * 0 */ + + struct + { + __IOM uint32_t PBDV : 7; /*!< [6..0] Port Based Destination Vector */ + uint32_t : 9; + __IOM uint32_t PBIPV : 3; /*!< [18..16] Port Based Internal Priority Value */ + __IOM uint32_t PBIPU : 1; /*!< [19..19] Port Based Internal Priority Update */ + __IOM uint32_t PBEME : 1; /*!< [20..20] Port Based Ethernet Mirroring Enabled */ + __IOM uint32_t PBCME : 1; /*!< [21..21] Port Based CPU Mirroring Enabled */ + __IOM uint32_t PBSL : 1; /*!< [22..22] Port Based Security Level */ + __IOM uint32_t IP4PDE : 1; /*!< [23..23] IPv4 Priority Decode Enable */ + __IOM uint32_t IP4PDM : 1; /*!< [24..24] IPv4 Priority Decode Mode */ + __IOM uint32_t IP6PDE : 1; /*!< [25..25] IPv6 Priority Decode Enable */ + __IOM uint32_t FAIFP : 1; /*!< [26..26] Force All Input Frame Priority Enable */ + uint32_t : 5; + } FWPBFC0_b; + }; + + union + { + __IOM uint32_t FWPBFCSDC00; /*!< (@ 0x00004A04) Port Based Forwarding CSD Configuration Register + * 00 */ + + struct + { + __IOM uint32_t PBCSD : 7; /*!< [6..0] Port Based CPU Sub Destination */ + uint32_t : 25; + } FWPBFCSDC00_b; + }; + __IM uint32_t RESERVED123[2]; + + union + { + __IOM uint32_t FWPBFC1; /*!< (@ 0x00004A10) Port Based Forwarding Configuration Register + * 1 */ + + struct + { + __IOM uint32_t PBDV : 7; /*!< [6..0] Port Based Destination Vector */ + uint32_t : 9; + __IOM uint32_t PBIPV : 3; /*!< [18..16] Port Based Internal Priority Value */ + __IOM uint32_t PBIPU : 1; /*!< [19..19] Port Based Internal Priority Update */ + __IOM uint32_t PBEME : 1; /*!< [20..20] Port Based Ethernet Mirroring Enabled */ + __IOM uint32_t PBCME : 1; /*!< [21..21] Port Based CPU Mirroring Enabled */ + __IOM uint32_t PBSL : 1; /*!< [22..22] Port Based Security Level */ + __IOM uint32_t IP4PDE : 1; /*!< [23..23] IPv4 Priority Decode Enable */ + __IOM uint32_t IP4PDM : 1; /*!< [24..24] IPv4 Priority Decode Mode */ + __IOM uint32_t IP6PDE : 1; /*!< [25..25] IPv6 Priority Decode Enable */ + __IOM uint32_t FAIFP : 1; /*!< [26..26] Force All Input Frame Priority Enable */ + uint32_t : 5; + } FWPBFC1_b; + }; + + union + { + __IOM uint32_t FWPBFCSDC01; /*!< (@ 0x00004A14) Port Based Forwarding CSD Configuration Register + * 01 */ + + struct + { + __IOM uint32_t PBCSD : 7; /*!< [6..0] Port Based CPU Sub Destination */ + uint32_t : 25; + } FWPBFCSDC01_b; + }; + __IM uint32_t RESERVED124[2]; + + union + { + __IOM uint32_t FWPBFC2; /*!< (@ 0x00004A20) Port Based Forwarding Configuration Register + * 2 */ + + struct + { + __IOM uint32_t PBDV : 7; /*!< [6..0] Port Based Destination Vector */ + uint32_t : 9; + __IOM uint32_t PBIPV : 3; /*!< [18..16] Port Based Internal Priority Value */ + __IOM uint32_t PBIPU : 1; /*!< [19..19] Port Based Internal Priority Update */ + __IOM uint32_t PBEME : 1; /*!< [20..20] Port Based Ethernet Mirroring Enabled */ + __IOM uint32_t PBCME : 1; /*!< [21..21] Port Based CPU Mirroring Enabled */ + __IOM uint32_t PBSL : 1; /*!< [22..22] Port Based Security Level */ + __IOM uint32_t IP4PDE : 1; /*!< [23..23] IPv4 Priority Decode Enable */ + __IOM uint32_t IP4PDM : 1; /*!< [24..24] IPv4 Priority Decode Mode */ + __IOM uint32_t IP6PDE : 1; /*!< [25..25] IPv6 Priority Decode Enable */ + __IOM uint32_t FAIFP : 1; /*!< [26..26] Force All Input Frame Priority Enable */ + uint32_t : 5; + } FWPBFC2_b; + }; + + union + { + __IOM uint32_t FWPBFCSDC02; /*!< (@ 0x00004A24) Port Based Forwarding CSD Configuration Register + * 02 */ + + struct + { + __IOM uint32_t PBCSD : 7; /*!< [6..0] Port Based CPU Sub Destination */ + uint32_t : 25; + } FWPBFCSDC02_b; + }; + __IM uint32_t RESERVED125[246]; + + union + { + __IOM uint32_t FWL23URL0; /*!< (@ 0x00004E00) Layer 2/Layer 3 Update Rule Learn Register 0 */ + + struct + { + __IOM uint32_t L23URNL : 8; /*!< [7..0] Layer 2/Layer 3 Update Routing Number Learn */ + uint32_t : 8; + __IOM uint32_t L23URPVL : 7; /*!< [22..16] Layer 2/Layer 3 Update Routing Port Valid Learn */ + uint32_t : 9; + } FWL23URL0_b; + }; + + union + { + __IOM uint32_t FWL23URL1; /*!< (@ 0x00004E04) Layer 2/Layer 3 Update Rule Learn Register 1 */ + + struct + { + __IOM uint32_t L23UMDALP0 : 16; /*!< [15..0] Layer 2/Layer 3 Update MAC Destination Address Learn + * Part 0 */ + __IOM uint32_t L23UTTLUL : 1; /*!< [16..16] Layer 2/Layer 3 Update Time To Live Update Learn */ + __IOM uint32_t L23UMDAUL : 1; /*!< [17..17] Layer 2/Layer 3 Update MAC Destination Address Update + * Learn */ + __IOM uint32_t L23UMSAUL : 1; /*!< [18..18] Layer 2/Layer 3 Update MAC Source Address Update Learn */ + __IOM uint32_t L23UCVIDUL : 1; /*!< [19..19] Layer 2/Layer 3 Update C-TAG VID Update Learn */ + __IOM uint32_t L23UCPCPUL : 1; /*!< [20..20] Layer 2/Layer 3 Update C-TAG PCP Update Learn */ + __IOM uint32_t L23UCDEIUL : 1; /*!< [21..21] Layer 2/Layer 3 Update C-TAG DEI Update Learn */ + __IOM uint32_t L23USVIDUL : 1; /*!< [22..22] Layer 2/Layer 3 Update S-TAG VID Update Learn */ + __IOM uint32_t L23USPCPUL : 1; /*!< [23..23] Layer 2/Layer 3 Update S-TAG PCP Update Learn */ + __IOM uint32_t L23USDEIUL : 1; /*!< [24..24] Layer 2/Layer 3 Update S-TAG DEI Update Learn */ + __IOM uint32_t L23URTUL : 2; /*!< [26..25] Layer 2/Layer 3 Update R-TAG Update Learn */ + uint32_t : 5; + } FWL23URL1_b; + }; + + union + { + __IOM uint32_t FWL23URL2; /*!< (@ 0x00004E08) Layer 2/Layer 3 Update Rule Learn Register 2 */ + + struct + { + __IOM uint32_t L23UMDALP1 : 32; /*!< [31..0] Layer 2/Layer 3 Update MAC Destination Address Learn + * Part 1 */ + } FWL23URL2_b; + }; + + union + { + __IOM uint32_t FWL23URL3; /*!< (@ 0x00004E0C) Layer 2/Layer 3 Update Rule Learn Register 3 */ + + struct + { + __IOM uint32_t L23UCVIDL : 12; /*!< [11..0] Layer 2/Layer 3 Update C-TAG VID Learn */ + __IOM uint32_t L23UCPCPL : 3; /*!< [14..12] Layer 2/Layer 3 Update C-TAG PCP Learn */ + __IOM uint32_t L23UCDEIL : 1; /*!< [15..15] Layer 2/Layer 3 Update C-TAG DEI Learn */ + __IOM uint32_t L23USVIDL : 12; /*!< [27..16] Layer 2/Layer 3 Update S-TAG VID Learn */ + __IOM uint32_t L23USPCPL : 3; /*!< [30..28] Layer 2/Layer 3 Update S-TAG PCP Learn */ + __IOM uint32_t L23USDEIL : 1; /*!< [31..31] Layer 2/Layer 3 Update S-TAG DEI Learn */ + } FWL23URL3_b; + }; + + union + { + __IM uint32_t FWL23URLR; /*!< (@ 0x00004E10) Layer 2/Layer 3 Update Rule Learn Result Register */ + + struct + { + __IM uint32_t L23ULF : 1; /*!< [0..0] Layer 2/Layer 3 Update Learn Fail */ + uint32_t : 30; + __IM uint32_t L23URL : 1; /*!< [31..31] Layer 2/Layer 3 Update Rule Learn */ + } FWL23URLR_b; + }; + __IM uint32_t RESERVED126[3]; + + union + { + __IOM uint32_t FWL23UTIM; /*!< (@ 0x00004E20) Layer 2/Layer 3 Update Table Initialization Monitoring + * Register */ + + struct + { + __IOM uint32_t L23UTIOG : 1; /*!< [0..0] Layer 2/Layer 3 Update Table Initialization Ongoing */ + __IM uint32_t L23UTR : 1; /*!< [1..1] Layer 2/Layer 3 Update Table Ready */ + uint32_t : 30; + } FWL23UTIM_b; + }; + __IM uint32_t RESERVED127[3]; + + union + { + __IOM uint32_t FWL23URR; /*!< (@ 0x00004E30) Layer 2/Layer 3 Update Rule Read Register */ + + struct + { + __IOM uint32_t L23RNR : 8; /*!< [7..0] Layer 2/Layer 3 Routing Number Read */ + uint32_t : 24; + } FWL23URR_b; + }; + + union + { + __IM uint32_t FWL23URRR0; /*!< (@ 0x00004E34) Layer 2/Layer 3 Update Rule Read Result Register + * 0 */ + + struct + { + __IM uint32_t L23URPVR : 7; /*!< [6..0] Layer 2/Layer 3 Update Routing Port Valid Read */ + uint32_t : 9; + __IM uint32_t L23UREF : 1; /*!< [16..16] Layer 2/Layer 3 Update Read ECC Fail */ + uint32_t : 14; + __IM uint32_t L23URR : 1; /*!< [31..31] Layer 2/Layer 3 Update Rule Read */ + } FWL23URRR0_b; + }; + + union + { + __IM uint32_t FWL23URRR1; /*!< (@ 0x00004E38) Layer 2/Layer 3 Update Rule Read Result Register + * 1 */ + + struct + { + __IM uint32_t L23UMDARP0 : 16; /*!< [15..0] Layer 2/Layer 3 MAC Destination Address Read Part 0 */ + __IM uint32_t L23UTTLUR : 1; /*!< [16..16] Layer 2/Layer 3 Time To Live Update Read */ + __IM uint32_t L23UMDAUR : 1; /*!< [17..17] Layer 2/Layer 3 MAC Destination Address Update Read */ + __IM uint32_t L23UMSAUR : 1; /*!< [18..18] Layer 2/Layer 3 MAC Source Address Update Read */ + __IM uint32_t L23UCVIDUR : 1; /*!< [19..19] Layer 2/Layer 3 C-TAG VID Update Read */ + __IM uint32_t L23UCPCPUR : 1; /*!< [20..20] Layer 2/Layer 3 C-TAG PCP Update Read */ + __IM uint32_t L23UCDEIUR : 1; /*!< [21..21] Layer 2/Layer 3 C-TAG DEI Update Read */ + __IM uint32_t L23USVIDUR : 1; /*!< [22..22] Layer 2/Layer 3 S-TAG VID Update Read */ + __IM uint32_t L23USPCPUR : 1; /*!< [23..23] Layer 2/Layer 3 S-TAG PCP Update Read */ + __IM uint32_t L23USDEIUR : 1; /*!< [24..24] Layer 2/Layer 3 S-TAG DEI Update Read */ + __IM uint32_t L23URTUR : 2; /*!< [26..25] Layer 2/Layer 3 R-TAG Update Read */ + uint32_t : 5; + } FWL23URRR1_b; + }; + + union + { + __IM uint32_t FWL23URRR2; /*!< (@ 0x00004E3C) Layer 2/Layer 3 Update Rule Read Result Register + * 2 */ + + struct + { + __IM uint32_t L23UMDARP1 : 32; /*!< [31..0] Layer 2/Layer 3 MAC Destination Address Read Part 1 */ + } FWL23URRR2_b; + }; + + union + { + __IM uint32_t FWL23URRR3; /*!< (@ 0x00004E40) Layer 2/Layer 3 Update Rule Read Result Register + * 3 */ + + struct + { + __IM uint32_t L23UCVIDR : 12; /*!< [11..0] Layer 2/Layer 3 Update MAC C-TAG VID Read */ + __IM uint32_t L23UCPCPR : 3; /*!< [14..12] Layer 2/Layer 3 Update MAC C-TAG PCP Read */ + __IM uint32_t L23UCDEIR : 1; /*!< [15..15] Layer 2/Layer 3 Update MAC C-TAG DEI Read */ + __IM uint32_t L23USVIDR : 12; /*!< [27..16] Layer 2/Layer 3 Update MAC S-TAG VID Read */ + __IM uint32_t L23USPCPR : 3; /*!< [30..28] Layer 2/Layer 3 Update MAC S-TAG PCP Read */ + __IM uint32_t L23USDEIR : 1; /*!< [31..31] Layer 2/Layer 3 Update MAC S-TAG DEI Read */ + } FWL23URRR3_b; + }; + __IM uint32_t RESERVED128[47]; + + union + { + __IOM uint32_t FWL23URMC0; /*!< (@ 0x00004F00) Layer 2/Layer 3 Update ReMapping Configuration + * Register 0 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC0_b; + }; + + union + { + __IOM uint32_t FWL23URMC1; /*!< (@ 0x00004F04) Layer 2/Layer 3 Update ReMapping Configuration + * Register 1 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC1_b; + }; + + union + { + __IOM uint32_t FWL23URMC2; /*!< (@ 0x00004F08) Layer 2/Layer 3 Update ReMapping Configuration + * Register 2 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC2_b; + }; + + union + { + __IOM uint32_t FWL23URMC3; /*!< (@ 0x00004F0C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 3 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC3_b; + }; + + union + { + __IOM uint32_t FWL23URMC4; /*!< (@ 0x00004F10) Layer 2/Layer 3 Update ReMapping Configuration + * Register 4 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC4_b; + }; + + union + { + __IOM uint32_t FWL23URMC5; /*!< (@ 0x00004F14) Layer 2/Layer 3 Update ReMapping Configuration + * Register 5 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC5_b; + }; + + union + { + __IOM uint32_t FWL23URMC6; /*!< (@ 0x00004F18) Layer 2/Layer 3 Update ReMapping Configuration + * Register 6 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC6_b; + }; + + union + { + __IOM uint32_t FWL23URMC7; /*!< (@ 0x00004F1C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 7 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC7_b; + }; + + union + { + __IOM uint32_t FWL23URMC8; /*!< (@ 0x00004F20) Layer 2/Layer 3 Update ReMapping Configuration + * Register 8 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC8_b; + }; + + union + { + __IOM uint32_t FWL23URMC9; /*!< (@ 0x00004F24) Layer 2/Layer 3 Update ReMapping Configuration + * Register 9 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC9_b; + }; + + union + { + __IOM uint32_t FWL23URMC10; /*!< (@ 0x00004F28) Layer 2/Layer 3 Update ReMapping Configuration + * Register 10 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC10_b; + }; + + union + { + __IOM uint32_t FWL23URMC11; /*!< (@ 0x00004F2C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 11 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC11_b; + }; + + union + { + __IOM uint32_t FWL23URMC12; /*!< (@ 0x00004F30) Layer 2/Layer 3 Update ReMapping Configuration + * Register 12 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC12_b; + }; + + union + { + __IOM uint32_t FWL23URMC13; /*!< (@ 0x00004F34) Layer 2/Layer 3 Update ReMapping Configuration + * Register 13 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC13_b; + }; + + union + { + __IOM uint32_t FWL23URMC14; /*!< (@ 0x00004F38) Layer 2/Layer 3 Update ReMapping Configuration + * Register 14 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC14_b; + }; + + union + { + __IOM uint32_t FWL23URMC15; /*!< (@ 0x00004F3C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 15 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC15_b; + }; + + union + { + __IOM uint32_t FWL23URMC16; /*!< (@ 0x00004F40) Layer 2/Layer 3 Update ReMapping Configuration + * Register 16 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC16_b; + }; + + union + { + __IOM uint32_t FWL23URMC17; /*!< (@ 0x00004F44) Layer 2/Layer 3 Update ReMapping Configuration + * Register 17 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC17_b; + }; + + union + { + __IOM uint32_t FWL23URMC18; /*!< (@ 0x00004F48) Layer 2/Layer 3 Update ReMapping Configuration + * Register 18 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC18_b; + }; + + union + { + __IOM uint32_t FWL23URMC19; /*!< (@ 0x00004F4C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 19 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC19_b; + }; + + union + { + __IOM uint32_t FWL23URMC20; /*!< (@ 0x00004F50) Layer 2/Layer 3 Update ReMapping Configuration + * Register 20 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC20_b; + }; + + union + { + __IOM uint32_t FWL23URMC21; /*!< (@ 0x00004F54) Layer 2/Layer 3 Update ReMapping Configuration + * Register 21 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC21_b; + }; + + union + { + __IOM uint32_t FWL23URMC22; /*!< (@ 0x00004F58) Layer 2/Layer 3 Update ReMapping Configuration + * Register 22 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC22_b; + }; + + union + { + __IOM uint32_t FWL23URMC23; /*!< (@ 0x00004F5C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 23 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC23_b; + }; + + union + { + __IOM uint32_t FWL23URMC24; /*!< (@ 0x00004F60) Layer 2/Layer 3 Update ReMapping Configuration + * Register 24 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC24_b; + }; + + union + { + __IOM uint32_t FWL23URMC25; /*!< (@ 0x00004F64) Layer 2/Layer 3 Update ReMapping Configuration + * Register 25 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC25_b; + }; + + union + { + __IOM uint32_t FWL23URMC26; /*!< (@ 0x00004F68) Layer 2/Layer 3 Update ReMapping Configuration + * Register 26 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC26_b; + }; + + union + { + __IOM uint32_t FWL23URMC27; /*!< (@ 0x00004F6C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 27 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC27_b; + }; + + union + { + __IOM uint32_t FWL23URMC28; /*!< (@ 0x00004F70) Layer 2/Layer 3 Update ReMapping Configuration + * Register 28 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC28_b; + }; + + union + { + __IOM uint32_t FWL23URMC29; /*!< (@ 0x00004F74) Layer 2/Layer 3 Update ReMapping Configuration + * Register 29 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC29_b; + }; + + union + { + __IOM uint32_t FWL23URMC30; /*!< (@ 0x00004F78) Layer 2/Layer 3 Update ReMapping Configuration + * Register 30 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC30_b; + }; + + union + { + __IOM uint32_t FWL23URMC31; /*!< (@ 0x00004F7C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 31 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC31_b; + }; + __IM uint32_t RESERVED129[32]; + + union + { + __IOM uint32_t FWPMFGC0; /*!< (@ 0x00005000) PSFP MSDU Filter Global Configuration Register + * 0 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC0_b; + }; + + union + { + __IOM uint32_t FWPMFGC1; /*!< (@ 0x00005004) PSFP MSDU Filter Global Configuration Register + * 1 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC1_b; + }; + + union + { + __IOM uint32_t FWPMFGC2; /*!< (@ 0x00005008) PSFP MSDU Filter Global Configuration Register + * 2 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC2_b; + }; + + union + { + __IOM uint32_t FWPMFGC3; /*!< (@ 0x0000500C) PSFP MSDU Filter Global Configuration Register + * 3 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC3_b; + }; + + union + { + __IOM uint32_t FWPMFGC4; /*!< (@ 0x00005010) PSFP MSDU Filter Global Configuration Register + * 4 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC4_b; + }; + + union + { + __IOM uint32_t FWPMFGC5; /*!< (@ 0x00005014) PSFP MSDU Filter Global Configuration Register + * 5 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC5_b; + }; + + union + { + __IOM uint32_t FWPMFGC6; /*!< (@ 0x00005018) PSFP MSDU Filter Global Configuration Register + * 6 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC6_b; + }; + + union + { + __IOM uint32_t FWPMFGC7; /*!< (@ 0x0000501C) PSFP MSDU Filter Global Configuration Register + * 7 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC7_b; + }; + + union + { + __IOM uint32_t FWPMFGC8; /*!< (@ 0x00005020) PSFP MSDU Filter Global Configuration Register + * 8 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC8_b; + }; + + union + { + __IOM uint32_t FWPMFGC9; /*!< (@ 0x00005024) PSFP MSDU Filter Global Configuration Register + * 9 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC9_b; + }; + + union + { + __IOM uint32_t FWPMFGC10; /*!< (@ 0x00005028) PSFP MSDU Filter Global Configuration Register + * 10 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC10_b; + }; + + union + { + __IOM uint32_t FWPMFGC11; /*!< (@ 0x0000502C) PSFP MSDU Filter Global Configuration Register + * 11 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC11_b; + }; + + union + { + __IOM uint32_t FWPMFGC12; /*!< (@ 0x00005030) PSFP MSDU Filter Global Configuration Register + * 12 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC12_b; + }; + + union + { + __IOM uint32_t FWPMFGC13; /*!< (@ 0x00005034) PSFP MSDU Filter Global Configuration Register + * 13 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC13_b; + }; + + union + { + __IOM uint32_t FWPMFGC14; /*!< (@ 0x00005038) PSFP MSDU Filter Global Configuration Register + * 14 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC14_b; + }; + + union + { + __IOM uint32_t FWPMFGC15; /*!< (@ 0x0000503C) PSFP MSDU Filter Global Configuration Register + * 15 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC15_b; + }; + __IM uint32_t RESERVED130[368]; + + union + { + __IOM uint32_t FWPMTRFC0; /*!< (@ 0x00005600) PSFP Meter Filter Configuration Register 0 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC0_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC0; /*!< (@ 0x00005604) PSFP Meter CBS Configuration Register 0 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC0_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC0; /*!< (@ 0x00005608) PSFP Meter CIR Configuration Register 0 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC0_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC0; /*!< (@ 0x0000560C) PSFP Meter EBS Configuration Register 0 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC0_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC0; /*!< (@ 0x00005610) PSFP Meter EIR Configuration Register 0 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC0_b; + }; + + union + { + __IM uint32_t FWPMTRFM0; /*!< (@ 0x00005614) PSFP Meter Filter Monitoring Register 0 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM0_b; + }; + __IM uint32_t RESERVED131[2]; + + union + { + __IOM uint32_t FWPMTRFC1; /*!< (@ 0x00005620) PSFP Meter Filter Configuration Register 1 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC1_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC1; /*!< (@ 0x00005624) PSFP Meter CBS Configuration Register 1 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC1_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC1; /*!< (@ 0x00005628) PSFP Meter CIR Configuration Register 1 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC1_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC1; /*!< (@ 0x0000562C) PSFP Meter EBS Configuration Register 1 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC1_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC1; /*!< (@ 0x00005630) PSFP Meter EIR Configuration Register 1 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC1_b; + }; + + union + { + __IM uint32_t FWPMTRFM1; /*!< (@ 0x00005634) PSFP Meter Filter Monitoring Register 1 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM1_b; + }; + __IM uint32_t RESERVED132[2]; + + union + { + __IOM uint32_t FWPMTRFC2; /*!< (@ 0x00005640) PSFP Meter Filter Configuration Register 2 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC2_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC2; /*!< (@ 0x00005644) PSFP Meter CBS Configuration Register 2 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC2_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC2; /*!< (@ 0x00005648) PSFP Meter CIR Configuration Register 2 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC2_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC2; /*!< (@ 0x0000564C) PSFP Meter EBS Configuration Register 2 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC2_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC2; /*!< (@ 0x00005650) PSFP Meter EIR Configuration Register 2 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC2_b; + }; + + union + { + __IM uint32_t FWPMTRFM2; /*!< (@ 0x00005654) PSFP Meter Filter Monitoring Register 2 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM2_b; + }; + __IM uint32_t RESERVED133[2]; + + union + { + __IOM uint32_t FWPMTRFC3; /*!< (@ 0x00005660) PSFP Meter Filter Configuration Register 3 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC3_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC3; /*!< (@ 0x00005664) PSFP Meter CBS Configuration Register 3 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC3_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC3; /*!< (@ 0x00005668) PSFP Meter CIR Configuration Register 3 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC3_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC3; /*!< (@ 0x0000566C) PSFP Meter EBS Configuration Register 3 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC3_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC3; /*!< (@ 0x00005670) PSFP Meter EIR Configuration Register 3 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC3_b; + }; + + union + { + __IM uint32_t FWPMTRFM3; /*!< (@ 0x00005674) PSFP Meter Filter Monitoring Register 3 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM3_b; + }; + __IM uint32_t RESERVED134[2]; + + union + { + __IOM uint32_t FWPMTRFC4; /*!< (@ 0x00005680) PSFP Meter Filter Configuration Register 4 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC4_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC4; /*!< (@ 0x00005684) PSFP Meter CBS Configuration Register 4 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC4_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC4; /*!< (@ 0x00005688) PSFP Meter CIR Configuration Register 4 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC4_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC4; /*!< (@ 0x0000568C) PSFP Meter EBS Configuration Register 4 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC4_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC4; /*!< (@ 0x00005690) PSFP Meter EIR Configuration Register 4 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC4_b; + }; + + union + { + __IM uint32_t FWPMTRFM4; /*!< (@ 0x00005694) PSFP Meter Filter Monitoring Register 4 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM4_b; + }; + __IM uint32_t RESERVED135[2]; + + union + { + __IOM uint32_t FWPMTRFC5; /*!< (@ 0x000056A0) PSFP Meter Filter Configuration Register 5 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC5_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC5; /*!< (@ 0x000056A4) PSFP Meter CBS Configuration Register 5 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC5_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC5; /*!< (@ 0x000056A8) PSFP Meter CIR Configuration Register 5 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC5_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC5; /*!< (@ 0x000056AC) PSFP Meter EBS Configuration Register 5 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC5_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC5; /*!< (@ 0x000056B0) PSFP Meter EIR Configuration Register 5 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC5_b; + }; + + union + { + __IM uint32_t FWPMTRFM5; /*!< (@ 0x000056B4) PSFP Meter Filter Monitoring Register 5 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM5_b; + }; + __IM uint32_t RESERVED136[2]; + + union + { + __IOM uint32_t FWPMTRFC6; /*!< (@ 0x000056C0) PSFP Meter Filter Configuration Register 6 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC6_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC6; /*!< (@ 0x000056C4) PSFP Meter CBS Configuration Register 6 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC6_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC6; /*!< (@ 0x000056C8) PSFP Meter CIR Configuration Register 6 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC6_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC6; /*!< (@ 0x000056CC) PSFP Meter EBS Configuration Register 6 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC6_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC6; /*!< (@ 0x000056D0) PSFP Meter EIR Configuration Register 6 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC6_b; + }; + + union + { + __IM uint32_t FWPMTRFM6; /*!< (@ 0x000056D4) PSFP Meter Filter Monitoring Register 6 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM6_b; + }; + __IM uint32_t RESERVED137[2]; + + union + { + __IOM uint32_t FWPMTRFC7; /*!< (@ 0x000056E0) PSFP Meter Filter Configuration Register 7 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC7_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC7; /*!< (@ 0x000056E4) PSFP Meter CBS Configuration Register 7 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC7_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC7; /*!< (@ 0x000056E8) PSFP Meter CIR Configuration Register 7 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC7_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC7; /*!< (@ 0x000056EC) PSFP Meter EBS Configuration Register 7 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC7_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC7; /*!< (@ 0x000056F0) PSFP Meter EIR Configuration Register 7 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC7_b; + }; + + union + { + __IM uint32_t FWPMTRFM7; /*!< (@ 0x000056F4) PSFP Meter Filter Monitoring Register 7 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM7_b; + }; + __IM uint32_t RESERVED138[2]; + + union + { + __IOM uint32_t FWPMTRFC8; /*!< (@ 0x00005700) PSFP Meter Filter Configuration Register 8 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC8_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC8; /*!< (@ 0x00005704) PSFP Meter CBS Configuration Register 8 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC8_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC8; /*!< (@ 0x00005708) PSFP Meter CIR Configuration Register 8 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC8_b; + }; + __IM uint32_t RESERVED139[2]; + + union + { + __IM uint32_t FWPMTRFM8; /*!< (@ 0x00005714) PSFP Meter Filter Monitoring Register 8 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM8_b; + }; + __IM uint32_t RESERVED140[2]; + + union + { + __IOM uint32_t FWPMTRFC9; /*!< (@ 0x00005720) PSFP Meter Filter Configuration Register 9 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC9_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC9; /*!< (@ 0x00005724) PSFP Meter CBS Configuration Register 9 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC9_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC9; /*!< (@ 0x00005728) PSFP Meter CIR Configuration Register 9 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC9_b; + }; + __IM uint32_t RESERVED141[2]; + + union + { + __IM uint32_t FWPMTRFM9; /*!< (@ 0x00005734) PSFP Meter Filter Monitoring Register 9 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM9_b; + }; + __IM uint32_t RESERVED142[2]; + + union + { + __IOM uint32_t FWPMTRFC10; /*!< (@ 0x00005740) PSFP Meter Filter Configuration Register 10 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC10_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC10; /*!< (@ 0x00005744) PSFP Meter CBS Configuration Register 10 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC10_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC10; /*!< (@ 0x00005748) PSFP Meter CIR Configuration Register 10 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC10_b; + }; + __IM uint32_t RESERVED143[2]; + + union + { + __IM uint32_t FWPMTRFM10; /*!< (@ 0x00005754) PSFP Meter Filter Monitoring Register 10 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM10_b; + }; + __IM uint32_t RESERVED144[2]; + + union + { + __IOM uint32_t FWPMTRFC11; /*!< (@ 0x00005760) PSFP Meter Filter Configuration Register 11 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC11_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC11; /*!< (@ 0x00005764) PSFP Meter CBS Configuration Register 11 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC11_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC11; /*!< (@ 0x00005768) PSFP Meter CIR Configuration Register 11 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC11_b; + }; + __IM uint32_t RESERVED145[2]; + + union + { + __IM uint32_t FWPMTRFM11; /*!< (@ 0x00005774) PSFP Meter Filter Monitoring Register 11 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM11_b; + }; + __IM uint32_t RESERVED146[2]; + + union + { + __IOM uint32_t FWPMTRFC12; /*!< (@ 0x00005780) PSFP Meter Filter Configuration Register 12 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC12_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC12; /*!< (@ 0x00005784) PSFP Meter CBS Configuration Register 12 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC12_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC12; /*!< (@ 0x00005788) PSFP Meter CIR Configuration Register 12 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC12_b; + }; + __IM uint32_t RESERVED147[2]; + + union + { + __IM uint32_t FWPMTRFM12; /*!< (@ 0x00005794) PSFP Meter Filter Monitoring Register 12 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM12_b; + }; + __IM uint32_t RESERVED148[2]; + + union + { + __IOM uint32_t FWPMTRFC13; /*!< (@ 0x000057A0) PSFP Meter Filter Configuration Register 13 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC13_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC13; /*!< (@ 0x000057A4) PSFP Meter CBS Configuration Register 13 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC13_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC13; /*!< (@ 0x000057A8) PSFP Meter CIR Configuration Register 13 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC13_b; + }; + __IM uint32_t RESERVED149[2]; + + union + { + __IM uint32_t FWPMTRFM13; /*!< (@ 0x000057B4) PSFP Meter Filter Monitoring Register 13 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM13_b; + }; + __IM uint32_t RESERVED150[2]; + + union + { + __IOM uint32_t FWPMTRFC14; /*!< (@ 0x000057C0) PSFP Meter Filter Configuration Register 14 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC14_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC14; /*!< (@ 0x000057C4) PSFP Meter CBS Configuration Register 14 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC14_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC14; /*!< (@ 0x000057C8) PSFP Meter CIR Configuration Register 14 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC14_b; + }; + __IM uint32_t RESERVED151[2]; + + union + { + __IM uint32_t FWPMTRFM14; /*!< (@ 0x000057D4) PSFP Meter Filter Monitoring Register 14 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM14_b; + }; + __IM uint32_t RESERVED152[2]; + + union + { + __IOM uint32_t FWPMTRFC15; /*!< (@ 0x000057E0) PSFP Meter Filter Configuration Register 15 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC15_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC15; /*!< (@ 0x000057E4) PSFP Meter CBS Configuration Register 15 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC15_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC15; /*!< (@ 0x000057E8) PSFP Meter CIR Configuration Register 15 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC15_b; + }; + __IM uint32_t RESERVED153[2]; + + union + { + __IM uint32_t FWPMTRFM15; /*!< (@ 0x000057F4) PSFP Meter Filter Monitoring Register 15 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM15_b; + }; + __IM uint32_t RESERVED154[2]; + + union + { + __IOM uint32_t FWPMTRFC16; /*!< (@ 0x00005800) PSFP Meter Filter Configuration Register 16 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC16_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC16; /*!< (@ 0x00005804) PSFP Meter CBS Configuration Register 16 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC16_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC16; /*!< (@ 0x00005808) PSFP Meter CIR Configuration Register 16 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC16_b; + }; + __IM uint32_t RESERVED155[2]; + + union + { + __IM uint32_t FWPMTRFM16; /*!< (@ 0x00005814) PSFP Meter Filter Monitoring Register 16 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM16_b; + }; + __IM uint32_t RESERVED156[2]; + + union + { + __IOM uint32_t FWPMTRFC17; /*!< (@ 0x00005820) PSFP Meter Filter Configuration Register 17 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC17_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC17; /*!< (@ 0x00005824) PSFP Meter CBS Configuration Register 17 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC17_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC17; /*!< (@ 0x00005828) PSFP Meter CIR Configuration Register 17 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC17_b; + }; + __IM uint32_t RESERVED157[2]; + + union + { + __IM uint32_t FWPMTRFM17; /*!< (@ 0x00005834) PSFP Meter Filter Monitoring Register 17 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM17_b; + }; + __IM uint32_t RESERVED158[2]; + + union + { + __IOM uint32_t FWPMTRFC18; /*!< (@ 0x00005840) PSFP Meter Filter Configuration Register 18 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC18_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC18; /*!< (@ 0x00005844) PSFP Meter CBS Configuration Register 18 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC18_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC18; /*!< (@ 0x00005848) PSFP Meter CIR Configuration Register 18 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC18_b; + }; + __IM uint32_t RESERVED159[2]; + + union + { + __IM uint32_t FWPMTRFM18; /*!< (@ 0x00005854) PSFP Meter Filter Monitoring Register 18 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM18_b; + }; + __IM uint32_t RESERVED160[2]; + + union + { + __IOM uint32_t FWPMTRFC19; /*!< (@ 0x00005860) PSFP Meter Filter Configuration Register 19 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC19_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC19; /*!< (@ 0x00005864) PSFP Meter CBS Configuration Register 19 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC19_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC19; /*!< (@ 0x00005868) PSFP Meter CIR Configuration Register 19 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC19_b; + }; + __IM uint32_t RESERVED161[2]; + + union + { + __IM uint32_t FWPMTRFM19; /*!< (@ 0x00005874) PSFP Meter Filter Monitoring Register 19 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM19_b; + }; + __IM uint32_t RESERVED162[2]; + + union + { + __IOM uint32_t FWPMTRFC20; /*!< (@ 0x00005880) PSFP Meter Filter Configuration Register 20 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC20_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC20; /*!< (@ 0x00005884) PSFP Meter CBS Configuration Register 20 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC20_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC20; /*!< (@ 0x00005888) PSFP Meter CIR Configuration Register 20 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC20_b; + }; + __IM uint32_t RESERVED163[2]; + + union + { + __IM uint32_t FWPMTRFM20; /*!< (@ 0x00005894) PSFP Meter Filter Monitoring Register 20 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM20_b; + }; + __IM uint32_t RESERVED164[2]; + + union + { + __IOM uint32_t FWPMTRFC21; /*!< (@ 0x000058A0) PSFP Meter Filter Configuration Register 21 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC21_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC21; /*!< (@ 0x000058A4) PSFP Meter CBS Configuration Register 21 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC21_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC21; /*!< (@ 0x000058A8) PSFP Meter CIR Configuration Register 21 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC21_b; + }; + __IM uint32_t RESERVED165[2]; + + union + { + __IM uint32_t FWPMTRFM21; /*!< (@ 0x000058B4) PSFP Meter Filter Monitoring Register 21 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM21_b; + }; + __IM uint32_t RESERVED166[2]; + + union + { + __IOM uint32_t FWPMTRFC22; /*!< (@ 0x000058C0) PSFP Meter Filter Configuration Register 22 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC22_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC22; /*!< (@ 0x000058C4) PSFP Meter CBS Configuration Register 22 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC22_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC22; /*!< (@ 0x000058C8) PSFP Meter CIR Configuration Register 22 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC22_b; + }; + __IM uint32_t RESERVED167[2]; + + union + { + __IM uint32_t FWPMTRFM22; /*!< (@ 0x000058D4) PSFP Meter Filter Monitoring Register 22 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM22_b; + }; + __IM uint32_t RESERVED168[2]; + + union + { + __IOM uint32_t FWPMTRFC23; /*!< (@ 0x000058E0) PSFP Meter Filter Configuration Register 23 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC23_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC23; /*!< (@ 0x000058E4) PSFP Meter CBS Configuration Register 23 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC23_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC23; /*!< (@ 0x000058E8) PSFP Meter CIR Configuration Register 23 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC23_b; + }; + __IM uint32_t RESERVED169[2]; + + union + { + __IM uint32_t FWPMTRFM23; /*!< (@ 0x000058F4) PSFP Meter Filter Monitoring Register 23 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM23_b; + }; + __IM uint32_t RESERVED170[2]; + + union + { + __IOM uint32_t FWPMTRFC24; /*!< (@ 0x00005900) PSFP Meter Filter Configuration Register 24 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC24_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC24; /*!< (@ 0x00005904) PSFP Meter CBS Configuration Register 24 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC24_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC24; /*!< (@ 0x00005908) PSFP Meter CIR Configuration Register 24 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC24_b; + }; + __IM uint32_t RESERVED171[2]; + + union + { + __IM uint32_t FWPMTRFM24; /*!< (@ 0x00005914) PSFP Meter Filter Monitoring Register 24 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM24_b; + }; + __IM uint32_t RESERVED172[2]; + + union + { + __IOM uint32_t FWPMTRFC25; /*!< (@ 0x00005920) PSFP Meter Filter Configuration Register 25 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC25_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC25; /*!< (@ 0x00005924) PSFP Meter CBS Configuration Register 25 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC25_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC25; /*!< (@ 0x00005928) PSFP Meter CIR Configuration Register 25 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC25_b; + }; + __IM uint32_t RESERVED173[2]; + + union + { + __IM uint32_t FWPMTRFM25; /*!< (@ 0x00005934) PSFP Meter Filter Monitoring Register 25 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM25_b; + }; + __IM uint32_t RESERVED174[2]; + + union + { + __IOM uint32_t FWPMTRFC26; /*!< (@ 0x00005940) PSFP Meter Filter Configuration Register 26 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC26_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC26; /*!< (@ 0x00005944) PSFP Meter CBS Configuration Register 26 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC26_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC26; /*!< (@ 0x00005948) PSFP Meter CIR Configuration Register 26 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC26_b; + }; + __IM uint32_t RESERVED175[2]; + + union + { + __IM uint32_t FWPMTRFM26; /*!< (@ 0x00005954) PSFP Meter Filter Monitoring Register 26 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM26_b; + }; + __IM uint32_t RESERVED176[2]; + + union + { + __IOM uint32_t FWPMTRFC27; /*!< (@ 0x00005960) PSFP Meter Filter Configuration Register 27 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC27_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC27; /*!< (@ 0x00005964) PSFP Meter CBS Configuration Register 27 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC27_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC27; /*!< (@ 0x00005968) PSFP Meter CIR Configuration Register 27 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC27_b; + }; + __IM uint32_t RESERVED177[2]; + + union + { + __IM uint32_t FWPMTRFM27; /*!< (@ 0x00005974) PSFP Meter Filter Monitoring Register 27 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM27_b; + }; + __IM uint32_t RESERVED178[2]; + + union + { + __IOM uint32_t FWPMTRFC28; /*!< (@ 0x00005980) PSFP Meter Filter Configuration Register 28 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC28_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC28; /*!< (@ 0x00005984) PSFP Meter CBS Configuration Register 28 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC28_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC28; /*!< (@ 0x00005988) PSFP Meter CIR Configuration Register 28 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC28_b; + }; + __IM uint32_t RESERVED179[2]; + + union + { + __IM uint32_t FWPMTRFM28; /*!< (@ 0x00005994) PSFP Meter Filter Monitoring Register 28 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM28_b; + }; + __IM uint32_t RESERVED180[2]; + + union + { + __IOM uint32_t FWPMTRFC29; /*!< (@ 0x000059A0) PSFP Meter Filter Configuration Register 29 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC29_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC29; /*!< (@ 0x000059A4) PSFP Meter CBS Configuration Register 29 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC29_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC29; /*!< (@ 0x000059A8) PSFP Meter CIR Configuration Register 29 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC29_b; + }; + __IM uint32_t RESERVED181[2]; + + union + { + __IM uint32_t FWPMTRFM29; /*!< (@ 0x000059B4) PSFP Meter Filter Monitoring Register 29 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM29_b; + }; + __IM uint32_t RESERVED182[2]; + + union + { + __IOM uint32_t FWPMTRFC30; /*!< (@ 0x000059C0) PSFP Meter Filter Configuration Register 30 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC30_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC30; /*!< (@ 0x000059C4) PSFP Meter CBS Configuration Register 30 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC30_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC30; /*!< (@ 0x000059C8) PSFP Meter CIR Configuration Register 30 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC30_b; + }; + __IM uint32_t RESERVED183[2]; + + union + { + __IM uint32_t FWPMTRFM30; /*!< (@ 0x000059D4) PSFP Meter Filter Monitoring Register 30 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM30_b; + }; + __IM uint32_t RESERVED184[2]; + + union + { + __IOM uint32_t FWPMTRFC31; /*!< (@ 0x000059E0) PSFP Meter Filter Configuration Register 31 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC31_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC31; /*!< (@ 0x000059E4) PSFP Meter CBS Configuration Register 31 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC31_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC31; /*!< (@ 0x000059E8) PSFP Meter CIR Configuration Register 31 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC31_b; + }; + __IM uint32_t RESERVED185[2]; + + union + { + __IM uint32_t FWPMTRFM31; /*!< (@ 0x000059F4) PSFP Meter Filter Monitoring Register 31 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM31_b; + }; + __IM uint32_t RESERVED186[386]; + + union + { + __IOM uint32_t FWFTL0; /*!< (@ 0x00006000) FRER Table Learn Register 0 */ + + struct + { + __IOM uint32_t FEAL : 7; /*!< [6..0] FRER Entry Address Learn */ + uint32_t : 9; + __IOM uint32_t FSRPL : 7; /*!< [22..16] FRER Sequence Recovery Pointer Learn */ + uint32_t : 9; + } FWFTL0_b; + }; + + union + { + __IOM uint32_t FWFTL1; /*!< (@ 0x00006004) FRER Table Learn Register 1 */ + + struct + { + __IOM uint32_t FSHLL : 4; /*!< [3..0] FRER Sequence History Length Learn */ + uint32_t : 4; + __IOM uint32_t FTNSL : 1; /*!< [8..8] FRER Take No Sequence Learn */ + __IOM uint32_t FSRPVL : 1; /*!< [9..9] FRER Sequence Recovery Pointer Valid Learn */ + uint32_t : 6; + __IOM uint32_t FSRRTL : 10; /*!< [25..16] FRER Sequence Recovery Remaining Ticks Learn */ + uint32_t : 6; + } FWFTL1_b; + }; + + union + { + __IM uint32_t FWFTLR; /*!< (@ 0x00006008) FRER Table Learn Result Register */ + + struct + { + __IM uint32_t FLF : 1; /*!< [0..0] FRER Learn Fail */ + uint32_t : 30; + __IM uint32_t FTL : 1; /*!< [31..31] FRER Table Learn */ + } FWFTLR_b; + }; + __IM uint32_t RESERVED187; + + union + { + __IOM uint32_t FWFTOC; /*!< (@ 0x00006010) FRER Timeout Configuration Register */ + + struct + { + __IOM uint32_t TOT : 16; /*!< [15..0] Timeout Time (ms) */ + __IOM uint32_t TOCE : 1; /*!< [16..16] Timeout Check Enable */ + __IOM uint32_t TOOG : 1; /*!< [17..17] Timeout Ongoing */ + uint32_t : 14; + } FWFTOC_b; + }; + + union + { + __IOM uint32_t FWFTOPC; /*!< (@ 0x00006014) FRER Timeout Prescaler Configuration Register + * 0 */ + + struct + { + __IOM uint32_t USP : 10; /*!< [9..0] Microsecond Prescaler */ + uint32_t : 22; + } FWFTOPC_b; + }; + __IM uint32_t RESERVED188[2]; + + union + { + __IOM uint32_t FWFTIM; /*!< (@ 0x00006020) FRER Table Initialization Monitoring Register */ + + struct + { + __IOM uint32_t FTIOG : 1; /*!< [0..0] FRER Table Initialization Ongoing */ + __IM uint32_t FTR : 1; /*!< [1..1] FRER Table Ready */ + uint32_t : 30; + } FWFTIM_b; + }; + __IM uint32_t RESERVED189[3]; + + union + { + __IOM uint32_t FWFTR; /*!< (@ 0x00006030) FRER Table Read Register */ + + struct + { + __IOM uint32_t FEAR : 7; /*!< [6..0] FRER Entry Address Read */ + uint32_t : 25; + } FWFTR_b; + }; + + union + { + __IM uint32_t FWFTRR0; /*!< (@ 0x00006034) FRER Table Read Result Register 0 */ + + struct + { + __IM uint32_t FSHLR : 4; /*!< [3..0] FRER Sequence History Length Read */ + uint32_t : 4; + __IM uint32_t FTNSR : 1; /*!< [8..8] FRER Take No Sequence Read */ + __IM uint32_t FSRPVR : 1; /*!< [9..9] FRER Sequence Recovery Pointer Valid Read */ + uint32_t : 6; + __IM uint32_t FSRRTR : 10; /*!< [25..16] FRER Set Recovery Remaining Ticks Read */ + uint32_t : 4; + __IM uint32_t FTREF : 1; /*!< [30..30] FRER Table Read ECC Fail */ + __IM uint32_t FTR : 1; /*!< [31..31] FRER Table Read */ + } FWFTRR0_b; + }; + + union + { + __IM uint32_t FWFTRR1; /*!< (@ 0x00006038) FRER Table Read Result Register 1 */ + + struct + { + __IM uint32_t FSHR : 15; /*!< [14..0] FRER Sequence History Read */ + uint32_t : 1; + __IM uint32_t FSRPR : 7; /*!< [22..16] FRER Sequence Recovery Pointer Read */ + uint32_t : 9; + } FWFTRR1_b; + }; + + union + { + __IM uint32_t FWFTRR2; /*!< (@ 0x0000603C) FRER Table Read Result Register 2 */ + + struct + { + __IM uint32_t FRSNR : 16; /*!< [15..0] FRER Recovery Sequence Number Read */ + __IM uint32_t FRRTR : 10; /*!< [25..16] FRER Recovery Remaining Ticks Read */ + uint32_t : 6; + } FWFTRR2_b; + }; + __IM uint32_t RESERVED190[48]; + + union + { + __IOM uint32_t FWSEQNGC0; /*!< (@ 0x00006100) Sequence Number Generation Configuration Register + * 0 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC0_b; + }; + + union + { + __IM uint32_t FWSEQNGM0; /*!< (@ 0x00006104) Sequence Number Generation Monitoring Register + * 0 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM0_b; + }; + + union + { + __IOM uint32_t FWSEQNGC1; /*!< (@ 0x00006108) Sequence Number Generation Configuration Register + * 1 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC1_b; + }; + + union + { + __IM uint32_t FWSEQNGM1; /*!< (@ 0x0000610C) Sequence Number Generation Monitoring Register + * 1 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM1_b; + }; + + union + { + __IOM uint32_t FWSEQNGC2; /*!< (@ 0x00006110) Sequence Number Generation Configuration Register + * 2 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC2_b; + }; + + union + { + __IM uint32_t FWSEQNGM2; /*!< (@ 0x00006114) Sequence Number Generation Monitoring Register + * 2 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM2_b; + }; + + union + { + __IOM uint32_t FWSEQNGC3; /*!< (@ 0x00006118) Sequence Number Generation Configuration Register + * 3 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC3_b; + }; + + union + { + __IM uint32_t FWSEQNGM3; /*!< (@ 0x0000611C) Sequence Number Generation Monitoring Register + * 3 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM3_b; + }; + + union + { + __IOM uint32_t FWSEQNGC4; /*!< (@ 0x00006120) Sequence Number Generation Configuration Register + * 4 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC4_b; + }; + + union + { + __IM uint32_t FWSEQNGM4; /*!< (@ 0x00006124) Sequence Number Generation Monitoring Register + * 4 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM4_b; + }; + + union + { + __IOM uint32_t FWSEQNGC5; /*!< (@ 0x00006128) Sequence Number Generation Configuration Register + * 5 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC5_b; + }; + + union + { + __IM uint32_t FWSEQNGM5; /*!< (@ 0x0000612C) Sequence Number Generation Monitoring Register + * 5 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM5_b; + }; + + union + { + __IOM uint32_t FWSEQNGC6; /*!< (@ 0x00006130) Sequence Number Generation Configuration Register + * 6 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC6_b; + }; + + union + { + __IM uint32_t FWSEQNGM6; /*!< (@ 0x00006134) Sequence Number Generation Monitoring Register + * 6 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM6_b; + }; + + union + { + __IOM uint32_t FWSEQNGC7; /*!< (@ 0x00006138) Sequence Number Generation Configuration Register + * 7 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC7_b; + }; + + union + { + __IM uint32_t FWSEQNGM7; /*!< (@ 0x0000613C) Sequence Number Generation Monitoring Register + * 7 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM7_b; + }; + + union + { + __IOM uint32_t FWSEQNGC8; /*!< (@ 0x00006140) Sequence Number Generation Configuration Register + * 8 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC8_b; + }; + + union + { + __IM uint32_t FWSEQNGM8; /*!< (@ 0x00006144) Sequence Number Generation Monitoring Register + * 8 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM8_b; + }; + + union + { + __IOM uint32_t FWSEQNGC9; /*!< (@ 0x00006148) Sequence Number Generation Configuration Register + * 9 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC9_b; + }; + + union + { + __IM uint32_t FWSEQNGM9; /*!< (@ 0x0000614C) Sequence Number Generation Monitoring Register + * 9 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM9_b; + }; + + union + { + __IOM uint32_t FWSEQNGC10; /*!< (@ 0x00006150) Sequence Number Generation Configuration Register + * 10 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC10_b; + }; + + union + { + __IM uint32_t FWSEQNGM10; /*!< (@ 0x00006154) Sequence Number Generation Monitoring Register + * 10 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM10_b; + }; + + union + { + __IOM uint32_t FWSEQNGC11; /*!< (@ 0x00006158) Sequence Number Generation Configuration Register + * 11 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC11_b; + }; + + union + { + __IM uint32_t FWSEQNGM11; /*!< (@ 0x0000615C) Sequence Number Generation Monitoring Register + * 11 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM11_b; + }; + + union + { + __IOM uint32_t FWSEQNGC12; /*!< (@ 0x00006160) Sequence Number Generation Configuration Register + * 12 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC12_b; + }; + + union + { + __IM uint32_t FWSEQNGM12; /*!< (@ 0x00006164) Sequence Number Generation Monitoring Register + * 12 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM12_b; + }; + + union + { + __IOM uint32_t FWSEQNGC13; /*!< (@ 0x00006168) Sequence Number Generation Configuration Register + * 13 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC13_b; + }; + + union + { + __IM uint32_t FWSEQNGM13; /*!< (@ 0x0000616C) Sequence Number Generation Monitoring Register + * 13 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM13_b; + }; + + union + { + __IOM uint32_t FWSEQNGC14; /*!< (@ 0x00006170) Sequence Number Generation Configuration Register + * 14 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC14_b; + }; + + union + { + __IM uint32_t FWSEQNGM14; /*!< (@ 0x00006174) Sequence Number Generation Monitoring Register + * 14 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM14_b; + }; + + union + { + __IOM uint32_t FWSEQNGC15; /*!< (@ 0x00006178) Sequence Number Generation Configuration Register + * 15 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC15_b; + }; + + union + { + __IM uint32_t FWSEQNGM15; /*!< (@ 0x0000617C) Sequence Number Generation Monitoring Register + * 15 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM15_b; + }; + + union + { + __IOM uint32_t FWSEQNGC16; /*!< (@ 0x00006180) Sequence Number Generation Configuration Register + * 16 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC16_b; + }; + + union + { + __IM uint32_t FWSEQNGM16; /*!< (@ 0x00006184) Sequence Number Generation Monitoring Register + * 16 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM16_b; + }; + + union + { + __IOM uint32_t FWSEQNGC17; /*!< (@ 0x00006188) Sequence Number Generation Configuration Register + * 17 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC17_b; + }; + + union + { + __IM uint32_t FWSEQNGM17; /*!< (@ 0x0000618C) Sequence Number Generation Monitoring Register + * 17 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM17_b; + }; + + union + { + __IOM uint32_t FWSEQNGC18; /*!< (@ 0x00006190) Sequence Number Generation Configuration Register + * 18 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC18_b; + }; + + union + { + __IM uint32_t FWSEQNGM18; /*!< (@ 0x00006194) Sequence Number Generation Monitoring Register + * 18 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM18_b; + }; + + union + { + __IOM uint32_t FWSEQNGC19; /*!< (@ 0x00006198) Sequence Number Generation Configuration Register + * 19 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC19_b; + }; + + union + { + __IM uint32_t FWSEQNGM19; /*!< (@ 0x0000619C) Sequence Number Generation Monitoring Register + * 19 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM19_b; + }; + + union + { + __IOM uint32_t FWSEQNGC20; /*!< (@ 0x000061A0) Sequence Number Generation Configuration Register + * 20 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC20_b; + }; + + union + { + __IM uint32_t FWSEQNGM20; /*!< (@ 0x000061A4) Sequence Number Generation Monitoring Register + * 20 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM20_b; + }; + + union + { + __IOM uint32_t FWSEQNGC21; /*!< (@ 0x000061A8) Sequence Number Generation Configuration Register + * 21 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC21_b; + }; + + union + { + __IM uint32_t FWSEQNGM21; /*!< (@ 0x000061AC) Sequence Number Generation Monitoring Register + * 21 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM21_b; + }; + + union + { + __IOM uint32_t FWSEQNGC22; /*!< (@ 0x000061B0) Sequence Number Generation Configuration Register + * 22 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC22_b; + }; + + union + { + __IM uint32_t FWSEQNGM22; /*!< (@ 0x000061B4) Sequence Number Generation Monitoring Register + * 22 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM22_b; + }; + + union + { + __IOM uint32_t FWSEQNGC23; /*!< (@ 0x000061B8) Sequence Number Generation Configuration Register + * 23 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC23_b; + }; + + union + { + __IM uint32_t FWSEQNGM23; /*!< (@ 0x000061BC) Sequence Number Generation Monitoring Register + * 23 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM23_b; + }; + + union + { + __IOM uint32_t FWSEQNGC24; /*!< (@ 0x000061C0) Sequence Number Generation Configuration Register + * 24 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC24_b; + }; + + union + { + __IM uint32_t FWSEQNGM24; /*!< (@ 0x000061C4) Sequence Number Generation Monitoring Register + * 24 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM24_b; + }; + + union + { + __IOM uint32_t FWSEQNGC25; /*!< (@ 0x000061C8) Sequence Number Generation Configuration Register + * 25 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC25_b; + }; + + union + { + __IM uint32_t FWSEQNGM25; /*!< (@ 0x000061CC) Sequence Number Generation Monitoring Register + * 25 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM25_b; + }; + + union + { + __IOM uint32_t FWSEQNGC26; /*!< (@ 0x000061D0) Sequence Number Generation Configuration Register + * 26 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC26_b; + }; + + union + { + __IM uint32_t FWSEQNGM26; /*!< (@ 0x000061D4) Sequence Number Generation Monitoring Register + * 26 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM26_b; + }; + + union + { + __IOM uint32_t FWSEQNGC27; /*!< (@ 0x000061D8) Sequence Number Generation Configuration Register + * 27 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC27_b; + }; + + union + { + __IM uint32_t FWSEQNGM27; /*!< (@ 0x000061DC) Sequence Number Generation Monitoring Register + * 27 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM27_b; + }; + + union + { + __IOM uint32_t FWSEQNGC28; /*!< (@ 0x000061E0) Sequence Number Generation Configuration Register + * 28 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC28_b; + }; + + union + { + __IM uint32_t FWSEQNGM28; /*!< (@ 0x000061E4) Sequence Number Generation Monitoring Register + * 28 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM28_b; + }; + + union + { + __IOM uint32_t FWSEQNGC29; /*!< (@ 0x000061E8) Sequence Number Generation Configuration Register + * 29 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC29_b; + }; + + union + { + __IM uint32_t FWSEQNGM29; /*!< (@ 0x000061EC) Sequence Number Generation Monitoring Register + * 29 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM29_b; + }; + + union + { + __IOM uint32_t FWSEQNGC30; /*!< (@ 0x000061F0) Sequence Number Generation Configuration Register + * 30 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC30_b; + }; + + union + { + __IM uint32_t FWSEQNGM30; /*!< (@ 0x000061F4) Sequence Number Generation Monitoring Register + * 30 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM30_b; + }; + + union + { + __IOM uint32_t FWSEQNGC31; /*!< (@ 0x000061F8) Sequence Number Generation Configuration Register + * 31 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC31_b; + }; + + union + { + __IM uint32_t FWSEQNGM31; /*!< (@ 0x000061FC) Sequence Number Generation Monitoring Register + * 31 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM31_b; + }; + + union + { + __OM uint32_t FWSEQNRC; /*!< (@ 0x00006200) Sequence Number Reset Configuration Register */ + + struct + { + __OM uint32_t SEQNR : 32; /*!< [31..0] Sequence Number Generation Reset */ + } FWSEQNRC_b; + }; + __IM uint32_t RESERVED191[63]; + + union + { + __IM uint32_t FWCTFDCN0; /*!< (@ 0x00006300) Cut-Through Forwarded Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t CTFDN : 32; /*!< [31..0] Cut-Through Forwarded Descriptor Number */ + } FWCTFDCN0_b; + }; + + union + { + __IM uint32_t FWLTHFDCN0; /*!< (@ 0x00006304) Layer 3 Forwarded Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t LTHFDN : 32; /*!< [31..0] Layer 3 Forwarded Descriptor Number */ + } FWLTHFDCN0_b; + }; + __IM uint32_t RESERVED192; + + union + { + __IM uint32_t FWLTWFDCN0; /*!< (@ 0x0000630C) Layer 2 Forwarded Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t LTWFDN : 32; /*!< [31..0] Layer 2 Forwarded Descriptor Number */ + } FWLTWFDCN0_b; + }; + + union + { + __IM uint32_t FWPBFDCN0; /*!< (@ 0x00006310) Port Based Forwarded Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t PBFDN : 32; /*!< [31..0] Port Based Forwarded Descriptor Number */ + } FWPBFDCN0_b; + }; + + union + { + __IM uint32_t FWMHLCN0; /*!< (@ 0x00006314) MAC Hardware Learn Counter Register 0 */ + + struct + { + __IM uint32_t MHLN : 32; /*!< [31..0] MAC Hardware Learn Number */ + } FWMHLCN0_b; + }; + __IM uint32_t RESERVED193[2]; + + union + { + __IM uint32_t FWCTFDCN1; /*!< (@ 0x00006320) Cut-Through Forwarded Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t CTFDN : 32; /*!< [31..0] Cut-Through Forwarded Descriptor Number */ + } FWCTFDCN1_b; + }; + + union + { + __IM uint32_t FWLTHFDCN1; /*!< (@ 0x00006324) Layer 3 Forwarded Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t LTHFDN : 32; /*!< [31..0] Layer 3 Forwarded Descriptor Number */ + } FWLTHFDCN1_b; + }; + __IM uint32_t RESERVED194; + + union + { + __IM uint32_t FWLTWFDCN1; /*!< (@ 0x0000632C) Layer 2 Forwarded Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t LTWFDN : 32; /*!< [31..0] Layer 2 Forwarded Descriptor Number */ + } FWLTWFDCN1_b; + }; + + union + { + __IM uint32_t FWPBFDCN1; /*!< (@ 0x00006330) Port Based Forwarded Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t PBFDN : 32; /*!< [31..0] Port Based Forwarded Descriptor Number */ + } FWPBFDCN1_b; + }; + + union + { + __IM uint32_t FWMHLCN1; /*!< (@ 0x00006334) MAC Hardware Learn Counter Register 1 */ + + struct + { + __IM uint32_t MHLN : 32; /*!< [31..0] MAC Hardware Learn Number */ + } FWMHLCN1_b; + }; + __IM uint32_t RESERVED195[2]; + + union + { + __IM uint32_t FWDDFDCN0; /*!< (@ 0x00006340) Direct Descriptor Forwarded Descriptor Counter + * Register 0 */ + + struct + { + __IM uint32_t DDFDN : 32; /*!< [31..0] Direct Descriptor Forwarded Descriptor Number */ + } FWDDFDCN0_b; + }; + + union + { + __IM uint32_t FWLTHFDCN2; /*!< (@ 0x00006344) Layer 3 Forwarded Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t LTHFDN : 32; /*!< [31..0] Layer 3 Forwarded Descriptor Number */ + } FWLTHFDCN2_b; + }; + __IM uint32_t RESERVED196; + + union + { + __IM uint32_t FWLTWFDCN2; /*!< (@ 0x0000634C) Layer 2 Forwarded Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t LTWFDN : 32; /*!< [31..0] Layer 2 Forwarded Descriptor Number */ + } FWLTWFDCN2_b; + }; + + union + { + __IM uint32_t FWPBFDCN2; /*!< (@ 0x00006350) Port Based Forwarded Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t PBFDN : 32; /*!< [31..0] Port Based Forwarded Descriptor Number */ + } FWPBFDCN2_b; + }; + + union + { + __IM uint32_t FWMHLCN2; /*!< (@ 0x00006354) MAC Hardware Learn Counter Register 2 */ + + struct + { + __IM uint32_t MHLN : 32; /*!< [31..0] MAC Hardware Learn Number */ + } FWMHLCN2_b; + }; + __IM uint32_t RESERVED197[107]; + + union + { + __IM uint32_t FWWMRDCN0; /*!< (@ 0x00006504) Watermark Rejected Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t WMRDN : 16; /*!< [15..0] Watermark rejected Descriptor Number */ + uint32_t : 16; + } FWWMRDCN0_b; + }; + + union + { + __IM uint32_t FWCTRDCN0; /*!< (@ 0x00006508) Cut-Through Rejected Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t CTRDN : 16; /*!< [15..0] Cut-through rejected Descriptor Number */ + uint32_t : 16; + } FWCTRDCN0_b; + }; + + union + { + __IM uint32_t FWLTHRDCN0; /*!< (@ 0x0000650C) Layer 3 Rejected Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t LTHRDN : 16; /*!< [15..0] Layer 3 rejected Descriptor Number */ + uint32_t : 16; + } FWLTHRDCN0_b; + }; + __IM uint32_t RESERVED198; + + union + { + __IM uint32_t FWLTWRDCN0; /*!< (@ 0x00006514) Layer 2 Rejected Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t LTWRDN : 16; /*!< [15..0] Layer 2 rejected Descriptor Number */ + uint32_t : 16; + } FWLTWRDCN0_b; + }; + + union + { + __IM uint32_t FWPBRDCN0; /*!< (@ 0x00006518) Port Based Rejected Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t PBRDN : 16; /*!< [15..0] Port Based rejected Descriptor Number */ + uint32_t : 16; + } FWPBRDCN0_b; + }; + __IM uint32_t RESERVED199[2]; + + union + { + __IM uint32_t FWWMRDCN1; /*!< (@ 0x00006524) Watermark Rejected Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t WMRDN : 16; /*!< [15..0] Watermark rejected Descriptor Number */ + uint32_t : 16; + } FWWMRDCN1_b; + }; + + union + { + __IM uint32_t FWCTRDCN1; /*!< (@ 0x00006528) Cut-Through Rejected Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t CTRDN : 16; /*!< [15..0] Cut-through rejected Descriptor Number */ + uint32_t : 16; + } FWCTRDCN1_b; + }; + + union + { + __IM uint32_t FWLTHRDCN1; /*!< (@ 0x0000652C) Layer 3 Rejected Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t LTHRDN : 16; /*!< [15..0] Layer 3 rejected Descriptor Number */ + uint32_t : 16; + } FWLTHRDCN1_b; + }; + __IM uint32_t RESERVED200; + + union + { + __IM uint32_t FWLTWRDCN1; /*!< (@ 0x00006534) Layer 2 Rejected Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t LTWRDN : 16; /*!< [15..0] Layer 2 rejected Descriptor Number */ + uint32_t : 16; + } FWLTWRDCN1_b; + }; + + union + { + __IM uint32_t FWPBRDCN1; /*!< (@ 0x00006538) Port Based Rejected Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t PBRDN : 16; /*!< [15..0] Port Based rejected Descriptor Number */ + uint32_t : 16; + } FWPBRDCN1_b; + }; + __IM uint32_t RESERVED201[2]; + + union + { + __IM uint32_t FWWMRDCN2; /*!< (@ 0x00006544) Watermark Rejected Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t WMRDN : 16; /*!< [15..0] Watermark rejected Descriptor Number */ + uint32_t : 16; + } FWWMRDCN2_b; + }; + + union + { + __IM uint32_t FWDDRDCN0; /*!< (@ 0x00006548) Direct Descriptor Rejected Descriptor Counter + * Register 0 */ + + struct + { + __IM uint32_t DDRDN : 16; /*!< [15..0] Direct Descriptor rejected Descriptor Number */ + uint32_t : 16; + } FWDDRDCN0_b; + }; + + union + { + __IM uint32_t FWLTHRDCN2; /*!< (@ 0x0000654C) Layer 3 Rejected Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t LTHRDN : 16; /*!< [15..0] Layer 3 rejected Descriptor Number */ + uint32_t : 16; + } FWLTHRDCN2_b; + }; + __IM uint32_t RESERVED202; + + union + { + __IM uint32_t FWLTWRDCN2; /*!< (@ 0x00006554) Layer 2 Rejected Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t LTWRDN : 16; /*!< [15..0] Layer 2 rejected Descriptor Number */ + uint32_t : 16; + } FWLTWRDCN2_b; + }; + + union + { + __IM uint32_t FWPBRDCN2; /*!< (@ 0x00006558) Port Based Rejected Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t PBRDN : 16; /*!< [15..0] Port Based rejected Descriptor Number */ + uint32_t : 16; + } FWPBRDCN2_b; + }; + __IM uint32_t RESERVED203[105]; + + union + { + __IM uint32_t FWPMFDCN0; /*!< (@ 0x00006700) PSFP MSDU Filtered Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN0_b; + }; + + union + { + __IM uint32_t FWPMFDCN1; /*!< (@ 0x00006704) PSFP MSDU Filtered Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN1_b; + }; + + union + { + __IM uint32_t FWPMFDCN2; /*!< (@ 0x00006708) PSFP MSDU Filtered Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN2_b; + }; + + union + { + __IM uint32_t FWPMFDCN3; /*!< (@ 0x0000670C) PSFP MSDU Filtered Descriptor Counter Register + * 3 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN3_b; + }; + + union + { + __IM uint32_t FWPMFDCN4; /*!< (@ 0x00006710) PSFP MSDU Filtered Descriptor Counter Register + * 4 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN4_b; + }; + + union + { + __IM uint32_t FWPMFDCN5; /*!< (@ 0x00006714) PSFP MSDU Filtered Descriptor Counter Register + * 5 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN5_b; + }; + + union + { + __IM uint32_t FWPMFDCN6; /*!< (@ 0x00006718) PSFP MSDU Filtered Descriptor Counter Register + * 6 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN6_b; + }; + + union + { + __IM uint32_t FWPMFDCN7; /*!< (@ 0x0000671C) PSFP MSDU Filtered Descriptor Counter Register + * 7 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN7_b; + }; + + union + { + __IM uint32_t FWPMFDCN8; /*!< (@ 0x00006720) PSFP MSDU Filtered Descriptor Counter Register + * 8 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN8_b; + }; + + union + { + __IM uint32_t FWPMFDCN9; /*!< (@ 0x00006724) PSFP MSDU Filtered Descriptor Counter Register + * 9 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN9_b; + }; + + union + { + __IM uint32_t FWPMFDCN10; /*!< (@ 0x00006728) PSFP MSDU Filtered Descriptor Counter Register + * 10 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN10_b; + }; + + union + { + __IM uint32_t FWPMFDCN11; /*!< (@ 0x0000672C) PSFP MSDU Filtered Descriptor Counter Register + * 11 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN11_b; + }; + + union + { + __IM uint32_t FWPMFDCN12; /*!< (@ 0x00006730) PSFP MSDU Filtered Descriptor Counter Register + * 12 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN12_b; + }; + + union + { + __IM uint32_t FWPMFDCN13; /*!< (@ 0x00006734) PSFP MSDU Filtered Descriptor Counter Register + * 13 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN13_b; + }; + + union + { + __IM uint32_t FWPMFDCN14; /*!< (@ 0x00006738) PSFP MSDU Filtered Descriptor Counter Register + * 14 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN14_b; + }; + + union + { + __IM uint32_t FWPMFDCN15; /*!< (@ 0x0000673C) PSFP MSDU Filtered Descriptor Counter Register + * 15 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN15_b; + }; + __IM uint32_t RESERVED204[48]; + + union + { + __IM uint32_t FWPMGDCN0; /*!< (@ 0x00006800) PSFP Meter Green Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN0_b; + }; + + union + { + __IM uint32_t FWPMYDCN0; /*!< (@ 0x00006804) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN0_b; + }; + + union + { + __IM uint32_t FWPMRDCN0; /*!< (@ 0x00006808) PSFP Meter Red Descriptor Counter Register 0 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN0_b; + }; + __IM uint32_t RESERVED205; + + union + { + __IM uint32_t FWPMGDCN1; /*!< (@ 0x00006810) PSFP Meter Green Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN1_b; + }; + + union + { + __IM uint32_t FWPMYDCN1; /*!< (@ 0x00006814) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN1_b; + }; + + union + { + __IM uint32_t FWPMRDCN1; /*!< (@ 0x00006818) PSFP Meter Red Descriptor Counter Register 1 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN1_b; + }; + __IM uint32_t RESERVED206; + + union + { + __IM uint32_t FWPMGDCN2; /*!< (@ 0x00006820) PSFP Meter Green Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN2_b; + }; + + union + { + __IM uint32_t FWPMYDCN2; /*!< (@ 0x00006824) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN2_b; + }; + + union + { + __IM uint32_t FWPMRDCN2; /*!< (@ 0x00006828) PSFP Meter Red Descriptor Counter Register 2 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN2_b; + }; + __IM uint32_t RESERVED207; + + union + { + __IM uint32_t FWPMGDCN3; /*!< (@ 0x00006830) PSFP Meter Green Descriptor Counter Register + * 3 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN3_b; + }; + + union + { + __IM uint32_t FWPMYDCN3; /*!< (@ 0x00006834) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN3_b; + }; + + union + { + __IM uint32_t FWPMRDCN3; /*!< (@ 0x00006838) PSFP Meter Red Descriptor Counter Register 3 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN3_b; + }; + __IM uint32_t RESERVED208; + + union + { + __IM uint32_t FWPMGDCN4; /*!< (@ 0x00006840) PSFP Meter Green Descriptor Counter Register + * 4 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN4_b; + }; + + union + { + __IM uint32_t FWPMYDCN4; /*!< (@ 0x00006844) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN4_b; + }; + + union + { + __IM uint32_t FWPMRDCN4; /*!< (@ 0x00006848) PSFP Meter Red Descriptor Counter Register 4 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN4_b; + }; + __IM uint32_t RESERVED209; + + union + { + __IM uint32_t FWPMGDCN5; /*!< (@ 0x00006850) PSFP Meter Green Descriptor Counter Register + * 5 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN5_b; + }; + + union + { + __IM uint32_t FWPMYDCN5; /*!< (@ 0x00006854) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN5_b; + }; + + union + { + __IM uint32_t FWPMRDCN5; /*!< (@ 0x00006858) PSFP Meter Red Descriptor Counter Register 5 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN5_b; + }; + __IM uint32_t RESERVED210; + + union + { + __IM uint32_t FWPMGDCN6; /*!< (@ 0x00006860) PSFP Meter Green Descriptor Counter Register + * 6 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN6_b; + }; + + union + { + __IM uint32_t FWPMYDCN6; /*!< (@ 0x00006864) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN6_b; + }; + + union + { + __IM uint32_t FWPMRDCN6; /*!< (@ 0x00006868) PSFP Meter Red Descriptor Counter Register 6 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN6_b; + }; + __IM uint32_t RESERVED211; + + union + { + __IM uint32_t FWPMGDCN7; /*!< (@ 0x00006870) PSFP Meter Green Descriptor Counter Register + * 7 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN7_b; + }; + + union + { + __IM uint32_t FWPMYDCN7; /*!< (@ 0x00006874) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN7_b; + }; + + union + { + __IM uint32_t FWPMRDCN7; /*!< (@ 0x00006878) PSFP Meter Red Descriptor Counter Register 7 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN7_b; + }; + __IM uint32_t RESERVED212; + + union + { + __IM uint32_t FWPMGDCN8; /*!< (@ 0x00006880) PSFP Meter Green Descriptor Counter Register + * 8 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN8_b; + }; + __IM uint32_t RESERVED213; + + union + { + __IM uint32_t FWPMRDCN8; /*!< (@ 0x00006888) PSFP Meter Red Descriptor Counter Register 8 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN8_b; + }; + __IM uint32_t RESERVED214; + + union + { + __IM uint32_t FWPMGDCN9; /*!< (@ 0x00006890) PSFP Meter Green Descriptor Counter Register + * 9 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN9_b; + }; + __IM uint32_t RESERVED215; + + union + { + __IM uint32_t FWPMRDCN9; /*!< (@ 0x00006898) PSFP Meter Red Descriptor Counter Register 9 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN9_b; + }; + __IM uint32_t RESERVED216; + + union + { + __IM uint32_t FWPMGDCN10; /*!< (@ 0x000068A0) PSFP Meter Green Descriptor Counter Register + * 10 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN10_b; + }; + __IM uint32_t RESERVED217; + + union + { + __IM uint32_t FWPMRDCN10; /*!< (@ 0x000068A8) PSFP Meter Red Descriptor Counter Register 10 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN10_b; + }; + __IM uint32_t RESERVED218; + + union + { + __IM uint32_t FWPMGDCN11; /*!< (@ 0x000068B0) PSFP Meter Green Descriptor Counter Register + * 11 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN11_b; + }; + __IM uint32_t RESERVED219; + + union + { + __IM uint32_t FWPMRDCN11; /*!< (@ 0x000068B8) PSFP Meter Red Descriptor Counter Register 11 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN11_b; + }; + __IM uint32_t RESERVED220; + + union + { + __IM uint32_t FWPMGDCN12; /*!< (@ 0x000068C0) PSFP Meter Green Descriptor Counter Register + * 12 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN12_b; + }; + __IM uint32_t RESERVED221; + + union + { + __IM uint32_t FWPMRDCN12; /*!< (@ 0x000068C8) PSFP Meter Red Descriptor Counter Register 12 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN12_b; + }; + __IM uint32_t RESERVED222; + + union + { + __IM uint32_t FWPMGDCN13; /*!< (@ 0x000068D0) PSFP Meter Green Descriptor Counter Register + * 13 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN13_b; + }; + __IM uint32_t RESERVED223; + + union + { + __IM uint32_t FWPMRDCN13; /*!< (@ 0x000068D8) PSFP Meter Red Descriptor Counter Register 13 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN13_b; + }; + __IM uint32_t RESERVED224; + + union + { + __IM uint32_t FWPMGDCN14; /*!< (@ 0x000068E0) PSFP Meter Green Descriptor Counter Register + * 14 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN14_b; + }; + __IM uint32_t RESERVED225; + + union + { + __IM uint32_t FWPMRDCN14; /*!< (@ 0x000068E8) PSFP Meter Red Descriptor Counter Register 14 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN14_b; + }; + __IM uint32_t RESERVED226; + + union + { + __IM uint32_t FWPMGDCN15; /*!< (@ 0x000068F0) PSFP Meter Green Descriptor Counter Register + * 15 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN15_b; + }; + __IM uint32_t RESERVED227; + + union + { + __IM uint32_t FWPMRDCN15; /*!< (@ 0x000068F8) PSFP Meter Red Descriptor Counter Register 15 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN15_b; + }; + __IM uint32_t RESERVED228; + + union + { + __IM uint32_t FWPMGDCN16; /*!< (@ 0x00006900) PSFP Meter Green Descriptor Counter Register + * 16 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN16_b; + }; + __IM uint32_t RESERVED229; + + union + { + __IM uint32_t FWPMRDCN16; /*!< (@ 0x00006908) PSFP Meter Red Descriptor Counter Register 16 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN16_b; + }; + __IM uint32_t RESERVED230; + + union + { + __IM uint32_t FWPMGDCN17; /*!< (@ 0x00006910) PSFP Meter Green Descriptor Counter Register + * 17 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN17_b; + }; + __IM uint32_t RESERVED231; + + union + { + __IM uint32_t FWPMRDCN17; /*!< (@ 0x00006918) PSFP Meter Red Descriptor Counter Register 17 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN17_b; + }; + __IM uint32_t RESERVED232; + + union + { + __IM uint32_t FWPMGDCN18; /*!< (@ 0x00006920) PSFP Meter Green Descriptor Counter Register + * 18 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN18_b; + }; + __IM uint32_t RESERVED233; + + union + { + __IM uint32_t FWPMRDCN18; /*!< (@ 0x00006928) PSFP Meter Red Descriptor Counter Register 18 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN18_b; + }; + __IM uint32_t RESERVED234; + + union + { + __IM uint32_t FWPMGDCN19; /*!< (@ 0x00006930) PSFP Meter Green Descriptor Counter Register + * 19 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN19_b; + }; + __IM uint32_t RESERVED235; + + union + { + __IM uint32_t FWPMRDCN19; /*!< (@ 0x00006938) PSFP Meter Red Descriptor Counter Register 19 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN19_b; + }; + __IM uint32_t RESERVED236; + + union + { + __IM uint32_t FWPMGDCN20; /*!< (@ 0x00006940) PSFP Meter Green Descriptor Counter Register + * 20 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN20_b; + }; + __IM uint32_t RESERVED237; + + union + { + __IM uint32_t FWPMRDCN20; /*!< (@ 0x00006948) PSFP Meter Red Descriptor Counter Register 20 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN20_b; + }; + __IM uint32_t RESERVED238; + + union + { + __IM uint32_t FWPMGDCN21; /*!< (@ 0x00006950) PSFP Meter Green Descriptor Counter Register + * 21 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN21_b; + }; + __IM uint32_t RESERVED239; + + union + { + __IM uint32_t FWPMRDCN21; /*!< (@ 0x00006958) PSFP Meter Red Descriptor Counter Register 21 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN21_b; + }; + __IM uint32_t RESERVED240; + + union + { + __IM uint32_t FWPMGDCN22; /*!< (@ 0x00006960) PSFP Meter Green Descriptor Counter Register + * 22 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN22_b; + }; + __IM uint32_t RESERVED241; + + union + { + __IM uint32_t FWPMRDCN22; /*!< (@ 0x00006968) PSFP Meter Red Descriptor Counter Register 22 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN22_b; + }; + __IM uint32_t RESERVED242; + + union + { + __IM uint32_t FWPMGDCN23; /*!< (@ 0x00006970) PSFP Meter Green Descriptor Counter Register + * 23 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN23_b; + }; + __IM uint32_t RESERVED243; + + union + { + __IM uint32_t FWPMRDCN23; /*!< (@ 0x00006978) PSFP Meter Red Descriptor Counter Register 23 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN23_b; + }; + __IM uint32_t RESERVED244; + + union + { + __IM uint32_t FWPMGDCN24; /*!< (@ 0x00006980) PSFP Meter Green Descriptor Counter Register + * 24 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN24_b; + }; + __IM uint32_t RESERVED245; + + union + { + __IM uint32_t FWPMRDCN24; /*!< (@ 0x00006988) PSFP Meter Red Descriptor Counter Register 24 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN24_b; + }; + __IM uint32_t RESERVED246; + + union + { + __IM uint32_t FWPMGDCN25; /*!< (@ 0x00006990) PSFP Meter Green Descriptor Counter Register + * 25 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN25_b; + }; + __IM uint32_t RESERVED247; + + union + { + __IM uint32_t FWPMRDCN25; /*!< (@ 0x00006998) PSFP Meter Red Descriptor Counter Register 25 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN25_b; + }; + __IM uint32_t RESERVED248; + + union + { + __IM uint32_t FWPMGDCN26; /*!< (@ 0x000069A0) PSFP Meter Green Descriptor Counter Register + * 26 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN26_b; + }; + __IM uint32_t RESERVED249; + + union + { + __IM uint32_t FWPMRDCN26; /*!< (@ 0x000069A8) PSFP Meter Red Descriptor Counter Register 26 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN26_b; + }; + __IM uint32_t RESERVED250; + + union + { + __IM uint32_t FWPMGDCN27; /*!< (@ 0x000069B0) PSFP Meter Green Descriptor Counter Register + * 27 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN27_b; + }; + __IM uint32_t RESERVED251; + + union + { + __IM uint32_t FWPMRDCN27; /*!< (@ 0x000069B8) PSFP Meter Red Descriptor Counter Register 27 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN27_b; + }; + __IM uint32_t RESERVED252; + + union + { + __IM uint32_t FWPMGDCN28; /*!< (@ 0x000069C0) PSFP Meter Green Descriptor Counter Register + * 28 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN28_b; + }; + __IM uint32_t RESERVED253; + + union + { + __IM uint32_t FWPMRDCN28; /*!< (@ 0x000069C8) PSFP Meter Red Descriptor Counter Register 28 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN28_b; + }; + __IM uint32_t RESERVED254; + + union + { + __IM uint32_t FWPMGDCN29; /*!< (@ 0x000069D0) PSFP Meter Green Descriptor Counter Register + * 29 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN29_b; + }; + __IM uint32_t RESERVED255; + + union + { + __IM uint32_t FWPMRDCN29; /*!< (@ 0x000069D8) PSFP Meter Red Descriptor Counter Register 29 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN29_b; + }; + __IM uint32_t RESERVED256; + + union + { + __IM uint32_t FWPMGDCN30; /*!< (@ 0x000069E0) PSFP Meter Green Descriptor Counter Register + * 30 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN30_b; + }; + __IM uint32_t RESERVED257; + + union + { + __IM uint32_t FWPMRDCN30; /*!< (@ 0x000069E8) PSFP Meter Red Descriptor Counter Register 30 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN30_b; + }; + __IM uint32_t RESERVED258; + + union + { + __IM uint32_t FWPMGDCN31; /*!< (@ 0x000069F0) PSFP Meter Green Descriptor Counter Register + * 31 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN31_b; + }; + __IM uint32_t RESERVED259; + + union + { + __IM uint32_t FWPMRDCN31; /*!< (@ 0x000069F8) PSFP Meter Red Descriptor Counter Register 31 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN31_b; + }; + __IM uint32_t RESERVED260; + + union + { + __IM uint32_t FWFRPPCN0; /*!< (@ 0x00006A00) FRER Passed Packet Counter Register 0 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN0_b; + }; + + union + { + __IM uint32_t FWFRDPCN0; /*!< (@ 0x00006A04) FRER Discarded Packet Counter Register 0 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN0_b; + }; + + union + { + __IM uint32_t FWFRPPCN1; /*!< (@ 0x00006A08) FRER Passed Packet Counter Register 1 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN1_b; + }; + + union + { + __IM uint32_t FWFRDPCN1; /*!< (@ 0x00006A0C) FRER Discarded Packet Counter Register 1 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN1_b; + }; + + union + { + __IM uint32_t FWFRPPCN2; /*!< (@ 0x00006A10) FRER Passed Packet Counter Register 2 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN2_b; + }; + + union + { + __IM uint32_t FWFRDPCN2; /*!< (@ 0x00006A14) FRER Discarded Packet Counter Register 2 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN2_b; + }; + + union + { + __IM uint32_t FWFRPPCN3; /*!< (@ 0x00006A18) FRER Passed Packet Counter Register 3 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN3_b; + }; + + union + { + __IM uint32_t FWFRDPCN3; /*!< (@ 0x00006A1C) FRER Discarded Packet Counter Register 3 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN3_b; + }; + + union + { + __IM uint32_t FWFRPPCN4; /*!< (@ 0x00006A20) FRER Passed Packet Counter Register 4 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN4_b; + }; + + union + { + __IM uint32_t FWFRDPCN4; /*!< (@ 0x00006A24) FRER Discarded Packet Counter Register 4 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN4_b; + }; + + union + { + __IM uint32_t FWFRPPCN5; /*!< (@ 0x00006A28) FRER Passed Packet Counter Register 5 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN5_b; + }; + + union + { + __IM uint32_t FWFRDPCN5; /*!< (@ 0x00006A2C) FRER Discarded Packet Counter Register 5 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN5_b; + }; + + union + { + __IM uint32_t FWFRPPCN6; /*!< (@ 0x00006A30) FRER Passed Packet Counter Register 6 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN6_b; + }; + + union + { + __IM uint32_t FWFRDPCN6; /*!< (@ 0x00006A34) FRER Discarded Packet Counter Register 6 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN6_b; + }; + + union + { + __IM uint32_t FWFRPPCN7; /*!< (@ 0x00006A38) FRER Passed Packet Counter Register 7 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN7_b; + }; + + union + { + __IM uint32_t FWFRDPCN7; /*!< (@ 0x00006A3C) FRER Discarded Packet Counter Register 7 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN7_b; + }; + + union + { + __IM uint32_t FWFRPPCN8; /*!< (@ 0x00006A40) FRER Passed Packet Counter Register 8 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN8_b; + }; + + union + { + __IM uint32_t FWFRDPCN8; /*!< (@ 0x00006A44) FRER Discarded Packet Counter Register 8 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN8_b; + }; + + union + { + __IM uint32_t FWFRPPCN9; /*!< (@ 0x00006A48) FRER Passed Packet Counter Register 9 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN9_b; + }; + + union + { + __IM uint32_t FWFRDPCN9; /*!< (@ 0x00006A4C) FRER Discarded Packet Counter Register 9 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN9_b; + }; + + union + { + __IM uint32_t FWFRPPCN10; /*!< (@ 0x00006A50) FRER Passed Packet Counter Register 10 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN10_b; + }; + + union + { + __IM uint32_t FWFRDPCN10; /*!< (@ 0x00006A54) FRER Discarded Packet Counter Register 10 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN10_b; + }; + + union + { + __IM uint32_t FWFRPPCN11; /*!< (@ 0x00006A58) FRER Passed Packet Counter Register 11 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN11_b; + }; + + union + { + __IM uint32_t FWFRDPCN11; /*!< (@ 0x00006A5C) FRER Discarded Packet Counter Register 11 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN11_b; + }; + + union + { + __IM uint32_t FWFRPPCN12; /*!< (@ 0x00006A60) FRER Passed Packet Counter Register 12 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN12_b; + }; + + union + { + __IM uint32_t FWFRDPCN12; /*!< (@ 0x00006A64) FRER Discarded Packet Counter Register 12 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN12_b; + }; + + union + { + __IM uint32_t FWFRPPCN13; /*!< (@ 0x00006A68) FRER Passed Packet Counter Register 13 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN13_b; + }; + + union + { + __IM uint32_t FWFRDPCN13; /*!< (@ 0x00006A6C) FRER Discarded Packet Counter Register 13 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN13_b; + }; + + union + { + __IM uint32_t FWFRPPCN14; /*!< (@ 0x00006A70) FRER Passed Packet Counter Register 14 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN14_b; + }; + + union + { + __IM uint32_t FWFRDPCN14; /*!< (@ 0x00006A74) FRER Discarded Packet Counter Register 14 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN14_b; + }; + + union + { + __IM uint32_t FWFRPPCN15; /*!< (@ 0x00006A78) FRER Passed Packet Counter Register 15 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN15_b; + }; + + union + { + __IM uint32_t FWFRDPCN15; /*!< (@ 0x00006A7C) FRER Discarded Packet Counter Register 15 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN15_b; + }; + + union + { + __IM uint32_t FWFRPPCN16; /*!< (@ 0x00006A80) FRER Passed Packet Counter Register 16 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN16_b; + }; + + union + { + __IM uint32_t FWFRDPCN16; /*!< (@ 0x00006A84) FRER Discarded Packet Counter Register 16 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN16_b; + }; + + union + { + __IM uint32_t FWFRPPCN17; /*!< (@ 0x00006A88) FRER Passed Packet Counter Register 17 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN17_b; + }; + + union + { + __IM uint32_t FWFRDPCN17; /*!< (@ 0x00006A8C) FRER Discarded Packet Counter Register 17 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN17_b; + }; + + union + { + __IM uint32_t FWFRPPCN18; /*!< (@ 0x00006A90) FRER Passed Packet Counter Register 18 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN18_b; + }; + + union + { + __IM uint32_t FWFRDPCN18; /*!< (@ 0x00006A94) FRER Discarded Packet Counter Register 18 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN18_b; + }; + + union + { + __IM uint32_t FWFRPPCN19; /*!< (@ 0x00006A98) FRER Passed Packet Counter Register 19 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN19_b; + }; + + union + { + __IM uint32_t FWFRDPCN19; /*!< (@ 0x00006A9C) FRER Discarded Packet Counter Register 19 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN19_b; + }; + + union + { + __IM uint32_t FWFRPPCN20; /*!< (@ 0x00006AA0) FRER Passed Packet Counter Register 20 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN20_b; + }; + + union + { + __IM uint32_t FWFRDPCN20; /*!< (@ 0x00006AA4) FRER Discarded Packet Counter Register 20 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN20_b; + }; + + union + { + __IM uint32_t FWFRPPCN21; /*!< (@ 0x00006AA8) FRER Passed Packet Counter Register 21 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN21_b; + }; + + union + { + __IM uint32_t FWFRDPCN21; /*!< (@ 0x00006AAC) FRER Discarded Packet Counter Register 21 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN21_b; + }; + + union + { + __IM uint32_t FWFRPPCN22; /*!< (@ 0x00006AB0) FRER Passed Packet Counter Register 22 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN22_b; + }; + + union + { + __IM uint32_t FWFRDPCN22; /*!< (@ 0x00006AB4) FRER Discarded Packet Counter Register 22 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN22_b; + }; + + union + { + __IM uint32_t FWFRPPCN23; /*!< (@ 0x00006AB8) FRER Passed Packet Counter Register 23 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN23_b; + }; + + union + { + __IM uint32_t FWFRDPCN23; /*!< (@ 0x00006ABC) FRER Discarded Packet Counter Register 23 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN23_b; + }; + + union + { + __IM uint32_t FWFRPPCN24; /*!< (@ 0x00006AC0) FRER Passed Packet Counter Register 24 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN24_b; + }; + + union + { + __IM uint32_t FWFRDPCN24; /*!< (@ 0x00006AC4) FRER Discarded Packet Counter Register 24 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN24_b; + }; + + union + { + __IM uint32_t FWFRPPCN25; /*!< (@ 0x00006AC8) FRER Passed Packet Counter Register 25 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN25_b; + }; + + union + { + __IM uint32_t FWFRDPCN25; /*!< (@ 0x00006ACC) FRER Discarded Packet Counter Register 25 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN25_b; + }; + + union + { + __IM uint32_t FWFRPPCN26; /*!< (@ 0x00006AD0) FRER Passed Packet Counter Register 26 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN26_b; + }; + + union + { + __IM uint32_t FWFRDPCN26; /*!< (@ 0x00006AD4) FRER Discarded Packet Counter Register 26 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN26_b; + }; + + union + { + __IM uint32_t FWFRPPCN27; /*!< (@ 0x00006AD8) FRER Passed Packet Counter Register 27 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN27_b; + }; + + union + { + __IM uint32_t FWFRDPCN27; /*!< (@ 0x00006ADC) FRER Discarded Packet Counter Register 27 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN27_b; + }; + + union + { + __IM uint32_t FWFRPPCN28; /*!< (@ 0x00006AE0) FRER Passed Packet Counter Register 28 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN28_b; + }; + + union + { + __IM uint32_t FWFRDPCN28; /*!< (@ 0x00006AE4) FRER Discarded Packet Counter Register 28 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN28_b; + }; + + union + { + __IM uint32_t FWFRPPCN29; /*!< (@ 0x00006AE8) FRER Passed Packet Counter Register 29 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN29_b; + }; + + union + { + __IM uint32_t FWFRDPCN29; /*!< (@ 0x00006AEC) FRER Discarded Packet Counter Register 29 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN29_b; + }; + + union + { + __IM uint32_t FWFRPPCN30; /*!< (@ 0x00006AF0) FRER Passed Packet Counter Register 30 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN30_b; + }; + + union + { + __IM uint32_t FWFRDPCN30; /*!< (@ 0x00006AF4) FRER Discarded Packet Counter Register 30 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN30_b; + }; + + union + { + __IM uint32_t FWFRPPCN31; /*!< (@ 0x00006AF8) FRER Passed Packet Counter Register 31 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN31_b; + }; + + union + { + __IM uint32_t FWFRDPCN31; /*!< (@ 0x00006AFC) FRER Discarded Packet Counter Register 31 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN31_b; + }; + + union + { + __IM uint32_t FWFRPPCN32; /*!< (@ 0x00006B00) FRER Passed Packet Counter Register 32 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN32_b; + }; + + union + { + __IM uint32_t FWFRDPCN32; /*!< (@ 0x00006B04) FRER Discarded Packet Counter Register 32 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN32_b; + }; + + union + { + __IM uint32_t FWFRPPCN33; /*!< (@ 0x00006B08) FRER Passed Packet Counter Register 33 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN33_b; + }; + + union + { + __IM uint32_t FWFRDPCN33; /*!< (@ 0x00006B0C) FRER Discarded Packet Counter Register 33 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN33_b; + }; + + union + { + __IM uint32_t FWFRPPCN34; /*!< (@ 0x00006B10) FRER Passed Packet Counter Register 34 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN34_b; + }; + + union + { + __IM uint32_t FWFRDPCN34; /*!< (@ 0x00006B14) FRER Discarded Packet Counter Register 34 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN34_b; + }; + + union + { + __IM uint32_t FWFRPPCN35; /*!< (@ 0x00006B18) FRER Passed Packet Counter Register 35 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN35_b; + }; + + union + { + __IM uint32_t FWFRDPCN35; /*!< (@ 0x00006B1C) FRER Discarded Packet Counter Register 35 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN35_b; + }; + + union + { + __IM uint32_t FWFRPPCN36; /*!< (@ 0x00006B20) FRER Passed Packet Counter Register 36 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN36_b; + }; + + union + { + __IM uint32_t FWFRDPCN36; /*!< (@ 0x00006B24) FRER Discarded Packet Counter Register 36 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN36_b; + }; + + union + { + __IM uint32_t FWFRPPCN37; /*!< (@ 0x00006B28) FRER Passed Packet Counter Register 37 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN37_b; + }; + + union + { + __IM uint32_t FWFRDPCN37; /*!< (@ 0x00006B2C) FRER Discarded Packet Counter Register 37 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN37_b; + }; + + union + { + __IM uint32_t FWFRPPCN38; /*!< (@ 0x00006B30) FRER Passed Packet Counter Register 38 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN38_b; + }; + + union + { + __IM uint32_t FWFRDPCN38; /*!< (@ 0x00006B34) FRER Discarded Packet Counter Register 38 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN38_b; + }; + + union + { + __IM uint32_t FWFRPPCN39; /*!< (@ 0x00006B38) FRER Passed Packet Counter Register 39 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN39_b; + }; + + union + { + __IM uint32_t FWFRDPCN39; /*!< (@ 0x00006B3C) FRER Discarded Packet Counter Register 39 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN39_b; + }; + + union + { + __IM uint32_t FWFRPPCN40; /*!< (@ 0x00006B40) FRER Passed Packet Counter Register 40 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN40_b; + }; + + union + { + __IM uint32_t FWFRDPCN40; /*!< (@ 0x00006B44) FRER Discarded Packet Counter Register 40 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN40_b; + }; + + union + { + __IM uint32_t FWFRPPCN41; /*!< (@ 0x00006B48) FRER Passed Packet Counter Register 41 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN41_b; + }; + + union + { + __IM uint32_t FWFRDPCN41; /*!< (@ 0x00006B4C) FRER Discarded Packet Counter Register 41 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN41_b; + }; + + union + { + __IM uint32_t FWFRPPCN42; /*!< (@ 0x00006B50) FRER Passed Packet Counter Register 42 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN42_b; + }; + + union + { + __IM uint32_t FWFRDPCN42; /*!< (@ 0x00006B54) FRER Discarded Packet Counter Register 42 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN42_b; + }; + + union + { + __IM uint32_t FWFRPPCN43; /*!< (@ 0x00006B58) FRER Passed Packet Counter Register 43 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN43_b; + }; + + union + { + __IM uint32_t FWFRDPCN43; /*!< (@ 0x00006B5C) FRER Discarded Packet Counter Register 43 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN43_b; + }; + + union + { + __IM uint32_t FWFRPPCN44; /*!< (@ 0x00006B60) FRER Passed Packet Counter Register 44 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN44_b; + }; + + union + { + __IM uint32_t FWFRDPCN44; /*!< (@ 0x00006B64) FRER Discarded Packet Counter Register 44 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN44_b; + }; + + union + { + __IM uint32_t FWFRPPCN45; /*!< (@ 0x00006B68) FRER Passed Packet Counter Register 45 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN45_b; + }; + + union + { + __IM uint32_t FWFRDPCN45; /*!< (@ 0x00006B6C) FRER Discarded Packet Counter Register 45 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN45_b; + }; + + union + { + __IM uint32_t FWFRPPCN46; /*!< (@ 0x00006B70) FRER Passed Packet Counter Register 46 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN46_b; + }; + + union + { + __IM uint32_t FWFRDPCN46; /*!< (@ 0x00006B74) FRER Discarded Packet Counter Register 46 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN46_b; + }; + + union + { + __IM uint32_t FWFRPPCN47; /*!< (@ 0x00006B78) FRER Passed Packet Counter Register 47 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN47_b; + }; + + union + { + __IM uint32_t FWFRDPCN47; /*!< (@ 0x00006B7C) FRER Discarded Packet Counter Register 47 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN47_b; + }; + + union + { + __IM uint32_t FWFRPPCN48; /*!< (@ 0x00006B80) FRER Passed Packet Counter Register 48 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN48_b; + }; + + union + { + __IM uint32_t FWFRDPCN48; /*!< (@ 0x00006B84) FRER Discarded Packet Counter Register 48 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN48_b; + }; + + union + { + __IM uint32_t FWFRPPCN49; /*!< (@ 0x00006B88) FRER Passed Packet Counter Register 49 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN49_b; + }; + + union + { + __IM uint32_t FWFRDPCN49; /*!< (@ 0x00006B8C) FRER Discarded Packet Counter Register 49 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN49_b; + }; + + union + { + __IM uint32_t FWFRPPCN50; /*!< (@ 0x00006B90) FRER Passed Packet Counter Register 50 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN50_b; + }; + + union + { + __IM uint32_t FWFRDPCN50; /*!< (@ 0x00006B94) FRER Discarded Packet Counter Register 50 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN50_b; + }; + + union + { + __IM uint32_t FWFRPPCN51; /*!< (@ 0x00006B98) FRER Passed Packet Counter Register 51 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN51_b; + }; + + union + { + __IM uint32_t FWFRDPCN51; /*!< (@ 0x00006B9C) FRER Discarded Packet Counter Register 51 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN51_b; + }; + + union + { + __IM uint32_t FWFRPPCN52; /*!< (@ 0x00006BA0) FRER Passed Packet Counter Register 52 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN52_b; + }; + + union + { + __IM uint32_t FWFRDPCN52; /*!< (@ 0x00006BA4) FRER Discarded Packet Counter Register 52 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN52_b; + }; + + union + { + __IM uint32_t FWFRPPCN53; /*!< (@ 0x00006BA8) FRER Passed Packet Counter Register 53 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN53_b; + }; + + union + { + __IM uint32_t FWFRDPCN53; /*!< (@ 0x00006BAC) FRER Discarded Packet Counter Register 53 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN53_b; + }; + + union + { + __IM uint32_t FWFRPPCN54; /*!< (@ 0x00006BB0) FRER Passed Packet Counter Register 54 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN54_b; + }; + + union + { + __IM uint32_t FWFRDPCN54; /*!< (@ 0x00006BB4) FRER Discarded Packet Counter Register 54 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN54_b; + }; + + union + { + __IM uint32_t FWFRPPCN55; /*!< (@ 0x00006BB8) FRER Passed Packet Counter Register 55 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN55_b; + }; + + union + { + __IM uint32_t FWFRDPCN55; /*!< (@ 0x00006BBC) FRER Discarded Packet Counter Register 55 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN55_b; + }; + + union + { + __IM uint32_t FWFRPPCN56; /*!< (@ 0x00006BC0) FRER Passed Packet Counter Register 56 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN56_b; + }; + + union + { + __IM uint32_t FWFRDPCN56; /*!< (@ 0x00006BC4) FRER Discarded Packet Counter Register 56 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN56_b; + }; + + union + { + __IM uint32_t FWFRPPCN57; /*!< (@ 0x00006BC8) FRER Passed Packet Counter Register 57 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN57_b; + }; + + union + { + __IM uint32_t FWFRDPCN57; /*!< (@ 0x00006BCC) FRER Discarded Packet Counter Register 57 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN57_b; + }; + + union + { + __IM uint32_t FWFRPPCN58; /*!< (@ 0x00006BD0) FRER Passed Packet Counter Register 58 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN58_b; + }; + + union + { + __IM uint32_t FWFRDPCN58; /*!< (@ 0x00006BD4) FRER Discarded Packet Counter Register 58 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN58_b; + }; + + union + { + __IM uint32_t FWFRPPCN59; /*!< (@ 0x00006BD8) FRER Passed Packet Counter Register 59 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN59_b; + }; + + union + { + __IM uint32_t FWFRDPCN59; /*!< (@ 0x00006BDC) FRER Discarded Packet Counter Register 59 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN59_b; + }; + + union + { + __IM uint32_t FWFRPPCN60; /*!< (@ 0x00006BE0) FRER Passed Packet Counter Register 60 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN60_b; + }; + + union + { + __IM uint32_t FWFRDPCN60; /*!< (@ 0x00006BE4) FRER Discarded Packet Counter Register 60 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN60_b; + }; + + union + { + __IM uint32_t FWFRPPCN61; /*!< (@ 0x00006BE8) FRER Passed Packet Counter Register 61 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN61_b; + }; + + union + { + __IM uint32_t FWFRDPCN61; /*!< (@ 0x00006BEC) FRER Discarded Packet Counter Register 61 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN61_b; + }; + + union + { + __IM uint32_t FWFRPPCN62; /*!< (@ 0x00006BF0) FRER Passed Packet Counter Register 62 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN62_b; + }; + + union + { + __IM uint32_t FWFRDPCN62; /*!< (@ 0x00006BF4) FRER Discarded Packet Counter Register 62 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN62_b; + }; + + union + { + __IM uint32_t FWFRPPCN63; /*!< (@ 0x00006BF8) FRER Passed Packet Counter Register 63 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN63_b; + }; + + union + { + __IM uint32_t FWFRDPCN63; /*!< (@ 0x00006BFC) FRER Discarded Packet Counter Register 63 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN63_b; + }; + + union + { + __IM uint32_t FWFRPPCN64; /*!< (@ 0x00006C00) FRER Passed Packet Counter Register 64 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN64_b; + }; + + union + { + __IM uint32_t FWFRDPCN64; /*!< (@ 0x00006C04) FRER Discarded Packet Counter Register 64 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN64_b; + }; + + union + { + __IM uint32_t FWFRPPCN65; /*!< (@ 0x00006C08) FRER Passed Packet Counter Register 65 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN65_b; + }; + + union + { + __IM uint32_t FWFRDPCN65; /*!< (@ 0x00006C0C) FRER Discarded Packet Counter Register 65 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN65_b; + }; + + union + { + __IM uint32_t FWFRPPCN66; /*!< (@ 0x00006C10) FRER Passed Packet Counter Register 66 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN66_b; + }; + + union + { + __IM uint32_t FWFRDPCN66; /*!< (@ 0x00006C14) FRER Discarded Packet Counter Register 66 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN66_b; + }; + + union + { + __IM uint32_t FWFRPPCN67; /*!< (@ 0x00006C18) FRER Passed Packet Counter Register 67 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN67_b; + }; + + union + { + __IM uint32_t FWFRDPCN67; /*!< (@ 0x00006C1C) FRER Discarded Packet Counter Register 67 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN67_b; + }; + + union + { + __IM uint32_t FWFRPPCN68; /*!< (@ 0x00006C20) FRER Passed Packet Counter Register 68 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN68_b; + }; + + union + { + __IM uint32_t FWFRDPCN68; /*!< (@ 0x00006C24) FRER Discarded Packet Counter Register 68 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN68_b; + }; + + union + { + __IM uint32_t FWFRPPCN69; /*!< (@ 0x00006C28) FRER Passed Packet Counter Register 69 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN69_b; + }; + + union + { + __IM uint32_t FWFRDPCN69; /*!< (@ 0x00006C2C) FRER Discarded Packet Counter Register 69 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN69_b; + }; + + union + { + __IM uint32_t FWFRPPCN70; /*!< (@ 0x00006C30) FRER Passed Packet Counter Register 70 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN70_b; + }; + + union + { + __IM uint32_t FWFRDPCN70; /*!< (@ 0x00006C34) FRER Discarded Packet Counter Register 70 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN70_b; + }; + + union + { + __IM uint32_t FWFRPPCN71; /*!< (@ 0x00006C38) FRER Passed Packet Counter Register 71 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN71_b; + }; + + union + { + __IM uint32_t FWFRDPCN71; /*!< (@ 0x00006C3C) FRER Discarded Packet Counter Register 71 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN71_b; + }; + + union + { + __IM uint32_t FWFRPPCN72; /*!< (@ 0x00006C40) FRER Passed Packet Counter Register 72 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN72_b; + }; + + union + { + __IM uint32_t FWFRDPCN72; /*!< (@ 0x00006C44) FRER Discarded Packet Counter Register 72 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN72_b; + }; + + union + { + __IM uint32_t FWFRPPCN73; /*!< (@ 0x00006C48) FRER Passed Packet Counter Register 73 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN73_b; + }; + + union + { + __IM uint32_t FWFRDPCN73; /*!< (@ 0x00006C4C) FRER Discarded Packet Counter Register 73 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN73_b; + }; + + union + { + __IM uint32_t FWFRPPCN74; /*!< (@ 0x00006C50) FRER Passed Packet Counter Register 74 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN74_b; + }; + + union + { + __IM uint32_t FWFRDPCN74; /*!< (@ 0x00006C54) FRER Discarded Packet Counter Register 74 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN74_b; + }; + + union + { + __IM uint32_t FWFRPPCN75; /*!< (@ 0x00006C58) FRER Passed Packet Counter Register 75 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN75_b; + }; + + union + { + __IM uint32_t FWFRDPCN75; /*!< (@ 0x00006C5C) FRER Discarded Packet Counter Register 75 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN75_b; + }; + + union + { + __IM uint32_t FWFRPPCN76; /*!< (@ 0x00006C60) FRER Passed Packet Counter Register 76 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN76_b; + }; + + union + { + __IM uint32_t FWFRDPCN76; /*!< (@ 0x00006C64) FRER Discarded Packet Counter Register 76 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN76_b; + }; + + union + { + __IM uint32_t FWFRPPCN77; /*!< (@ 0x00006C68) FRER Passed Packet Counter Register 77 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN77_b; + }; + + union + { + __IM uint32_t FWFRDPCN77; /*!< (@ 0x00006C6C) FRER Discarded Packet Counter Register 77 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN77_b; + }; + + union + { + __IM uint32_t FWFRPPCN78; /*!< (@ 0x00006C70) FRER Passed Packet Counter Register 78 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN78_b; + }; + + union + { + __IM uint32_t FWFRDPCN78; /*!< (@ 0x00006C74) FRER Discarded Packet Counter Register 78 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN78_b; + }; + + union + { + __IM uint32_t FWFRPPCN79; /*!< (@ 0x00006C78) FRER Passed Packet Counter Register 79 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN79_b; + }; + + union + { + __IM uint32_t FWFRDPCN79; /*!< (@ 0x00006C7C) FRER Discarded Packet Counter Register 79 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN79_b; + }; + + union + { + __IM uint32_t FWFRPPCN80; /*!< (@ 0x00006C80) FRER Passed Packet Counter Register 80 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN80_b; + }; + + union + { + __IM uint32_t FWFRDPCN80; /*!< (@ 0x00006C84) FRER Discarded Packet Counter Register 80 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN80_b; + }; + + union + { + __IM uint32_t FWFRPPCN81; /*!< (@ 0x00006C88) FRER Passed Packet Counter Register 81 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN81_b; + }; + + union + { + __IM uint32_t FWFRDPCN81; /*!< (@ 0x00006C8C) FRER Discarded Packet Counter Register 81 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN81_b; + }; + + union + { + __IM uint32_t FWFRPPCN82; /*!< (@ 0x00006C90) FRER Passed Packet Counter Register 82 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN82_b; + }; + + union + { + __IM uint32_t FWFRDPCN82; /*!< (@ 0x00006C94) FRER Discarded Packet Counter Register 82 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN82_b; + }; + + union + { + __IM uint32_t FWFRPPCN83; /*!< (@ 0x00006C98) FRER Passed Packet Counter Register 83 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN83_b; + }; + + union + { + __IM uint32_t FWFRDPCN83; /*!< (@ 0x00006C9C) FRER Discarded Packet Counter Register 83 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN83_b; + }; + + union + { + __IM uint32_t FWFRPPCN84; /*!< (@ 0x00006CA0) FRER Passed Packet Counter Register 84 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN84_b; + }; + + union + { + __IM uint32_t FWFRDPCN84; /*!< (@ 0x00006CA4) FRER Discarded Packet Counter Register 84 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN84_b; + }; + + union + { + __IM uint32_t FWFRPPCN85; /*!< (@ 0x00006CA8) FRER Passed Packet Counter Register 85 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN85_b; + }; + + union + { + __IM uint32_t FWFRDPCN85; /*!< (@ 0x00006CAC) FRER Discarded Packet Counter Register 85 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN85_b; + }; + + union + { + __IM uint32_t FWFRPPCN86; /*!< (@ 0x00006CB0) FRER Passed Packet Counter Register 86 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN86_b; + }; + + union + { + __IM uint32_t FWFRDPCN86; /*!< (@ 0x00006CB4) FRER Discarded Packet Counter Register 86 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN86_b; + }; + + union + { + __IM uint32_t FWFRPPCN87; /*!< (@ 0x00006CB8) FRER Passed Packet Counter Register 87 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN87_b; + }; + + union + { + __IM uint32_t FWFRDPCN87; /*!< (@ 0x00006CBC) FRER Discarded Packet Counter Register 87 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN87_b; + }; + + union + { + __IM uint32_t FWFRPPCN88; /*!< (@ 0x00006CC0) FRER Passed Packet Counter Register 88 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN88_b; + }; + + union + { + __IM uint32_t FWFRDPCN88; /*!< (@ 0x00006CC4) FRER Discarded Packet Counter Register 88 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN88_b; + }; + + union + { + __IM uint32_t FWFRPPCN89; /*!< (@ 0x00006CC8) FRER Passed Packet Counter Register 89 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN89_b; + }; + + union + { + __IM uint32_t FWFRDPCN89; /*!< (@ 0x00006CCC) FRER Discarded Packet Counter Register 89 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN89_b; + }; + + union + { + __IM uint32_t FWFRPPCN90; /*!< (@ 0x00006CD0) FRER Passed Packet Counter Register 90 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN90_b; + }; + + union + { + __IM uint32_t FWFRDPCN90; /*!< (@ 0x00006CD4) FRER Discarded Packet Counter Register 90 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN90_b; + }; + + union + { + __IM uint32_t FWFRPPCN91; /*!< (@ 0x00006CD8) FRER Passed Packet Counter Register 91 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN91_b; + }; + + union + { + __IM uint32_t FWFRDPCN91; /*!< (@ 0x00006CDC) FRER Discarded Packet Counter Register 91 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN91_b; + }; + + union + { + __IM uint32_t FWFRPPCN92; /*!< (@ 0x00006CE0) FRER Passed Packet Counter Register 92 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN92_b; + }; + + union + { + __IM uint32_t FWFRDPCN92; /*!< (@ 0x00006CE4) FRER Discarded Packet Counter Register 92 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN92_b; + }; + + union + { + __IM uint32_t FWFRPPCN93; /*!< (@ 0x00006CE8) FRER Passed Packet Counter Register 93 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN93_b; + }; + + union + { + __IM uint32_t FWFRDPCN93; /*!< (@ 0x00006CEC) FRER Discarded Packet Counter Register 93 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN93_b; + }; + + union + { + __IM uint32_t FWFRPPCN94; /*!< (@ 0x00006CF0) FRER Passed Packet Counter Register 94 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN94_b; + }; + + union + { + __IM uint32_t FWFRDPCN94; /*!< (@ 0x00006CF4) FRER Discarded Packet Counter Register 94 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN94_b; + }; + + union + { + __IM uint32_t FWFRPPCN95; /*!< (@ 0x00006CF8) FRER Passed Packet Counter Register 95 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN95_b; + }; + + union + { + __IM uint32_t FWFRDPCN95; /*!< (@ 0x00006CFC) FRER Discarded Packet Counter Register 95 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN95_b; + }; + + union + { + __IM uint32_t FWFRPPCN96; /*!< (@ 0x00006D00) FRER Passed Packet Counter Register 96 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN96_b; + }; + + union + { + __IM uint32_t FWFRDPCN96; /*!< (@ 0x00006D04) FRER Discarded Packet Counter Register 96 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN96_b; + }; + + union + { + __IM uint32_t FWFRPPCN97; /*!< (@ 0x00006D08) FRER Passed Packet Counter Register 97 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN97_b; + }; + + union + { + __IM uint32_t FWFRDPCN97; /*!< (@ 0x00006D0C) FRER Discarded Packet Counter Register 97 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN97_b; + }; + + union + { + __IM uint32_t FWFRPPCN98; /*!< (@ 0x00006D10) FRER Passed Packet Counter Register 98 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN98_b; + }; + + union + { + __IM uint32_t FWFRDPCN98; /*!< (@ 0x00006D14) FRER Discarded Packet Counter Register 98 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN98_b; + }; + + union + { + __IM uint32_t FWFRPPCN99; /*!< (@ 0x00006D18) FRER Passed Packet Counter Register 99 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN99_b; + }; + + union + { + __IM uint32_t FWFRDPCN99; /*!< (@ 0x00006D1C) FRER Discarded Packet Counter Register 99 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN99_b; + }; + + union + { + __IM uint32_t FWFRPPCN100; /*!< (@ 0x00006D20) FRER Passed Packet Counter Register 100 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN100_b; + }; + + union + { + __IM uint32_t FWFRDPCN100; /*!< (@ 0x00006D24) FRER Discarded Packet Counter Register 100 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN100_b; + }; + + union + { + __IM uint32_t FWFRPPCN101; /*!< (@ 0x00006D28) FRER Passed Packet Counter Register 101 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN101_b; + }; + + union + { + __IM uint32_t FWFRDPCN101; /*!< (@ 0x00006D2C) FRER Discarded Packet Counter Register 101 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN101_b; + }; + + union + { + __IM uint32_t FWFRPPCN102; /*!< (@ 0x00006D30) FRER Passed Packet Counter Register 102 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN102_b; + }; + + union + { + __IM uint32_t FWFRDPCN102; /*!< (@ 0x00006D34) FRER Discarded Packet Counter Register 102 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN102_b; + }; + + union + { + __IM uint32_t FWFRPPCN103; /*!< (@ 0x00006D38) FRER Passed Packet Counter Register 103 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN103_b; + }; + + union + { + __IM uint32_t FWFRDPCN103; /*!< (@ 0x00006D3C) FRER Discarded Packet Counter Register 103 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN103_b; + }; + + union + { + __IM uint32_t FWFRPPCN104; /*!< (@ 0x00006D40) FRER Passed Packet Counter Register 104 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN104_b; + }; + + union + { + __IM uint32_t FWFRDPCN104; /*!< (@ 0x00006D44) FRER Discarded Packet Counter Register 104 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN104_b; + }; + + union + { + __IM uint32_t FWFRPPCN105; /*!< (@ 0x00006D48) FRER Passed Packet Counter Register 105 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN105_b; + }; + + union + { + __IM uint32_t FWFRDPCN105; /*!< (@ 0x00006D4C) FRER Discarded Packet Counter Register 105 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN105_b; + }; + + union + { + __IM uint32_t FWFRPPCN106; /*!< (@ 0x00006D50) FRER Passed Packet Counter Register 106 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN106_b; + }; + + union + { + __IM uint32_t FWFRDPCN106; /*!< (@ 0x00006D54) FRER Discarded Packet Counter Register 106 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN106_b; + }; + + union + { + __IM uint32_t FWFRPPCN107; /*!< (@ 0x00006D58) FRER Passed Packet Counter Register 107 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN107_b; + }; + + union + { + __IM uint32_t FWFRDPCN107; /*!< (@ 0x00006D5C) FRER Discarded Packet Counter Register 107 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN107_b; + }; + + union + { + __IM uint32_t FWFRPPCN108; /*!< (@ 0x00006D60) FRER Passed Packet Counter Register 108 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN108_b; + }; + + union + { + __IM uint32_t FWFRDPCN108; /*!< (@ 0x00006D64) FRER Discarded Packet Counter Register 108 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN108_b; + }; + + union + { + __IM uint32_t FWFRPPCN109; /*!< (@ 0x00006D68) FRER Passed Packet Counter Register 109 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN109_b; + }; + + union + { + __IM uint32_t FWFRDPCN109; /*!< (@ 0x00006D6C) FRER Discarded Packet Counter Register 109 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN109_b; + }; + + union + { + __IM uint32_t FWFRPPCN110; /*!< (@ 0x00006D70) FRER Passed Packet Counter Register 110 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN110_b; + }; + + union + { + __IM uint32_t FWFRDPCN110; /*!< (@ 0x00006D74) FRER Discarded Packet Counter Register 110 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN110_b; + }; + + union + { + __IM uint32_t FWFRPPCN111; /*!< (@ 0x00006D78) FRER Passed Packet Counter Register 111 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN111_b; + }; + + union + { + __IM uint32_t FWFRDPCN111; /*!< (@ 0x00006D7C) FRER Discarded Packet Counter Register 111 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN111_b; + }; + + union + { + __IM uint32_t FWFRPPCN112; /*!< (@ 0x00006D80) FRER Passed Packet Counter Register 112 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN112_b; + }; + + union + { + __IM uint32_t FWFRDPCN112; /*!< (@ 0x00006D84) FRER Discarded Packet Counter Register 112 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN112_b; + }; + + union + { + __IM uint32_t FWFRPPCN113; /*!< (@ 0x00006D88) FRER Passed Packet Counter Register 113 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN113_b; + }; + + union + { + __IM uint32_t FWFRDPCN113; /*!< (@ 0x00006D8C) FRER Discarded Packet Counter Register 113 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN113_b; + }; + + union + { + __IM uint32_t FWFRPPCN114; /*!< (@ 0x00006D90) FRER Passed Packet Counter Register 114 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN114_b; + }; + + union + { + __IM uint32_t FWFRDPCN114; /*!< (@ 0x00006D94) FRER Discarded Packet Counter Register 114 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN114_b; + }; + + union + { + __IM uint32_t FWFRPPCN115; /*!< (@ 0x00006D98) FRER Passed Packet Counter Register 115 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN115_b; + }; + + union + { + __IM uint32_t FWFRDPCN115; /*!< (@ 0x00006D9C) FRER Discarded Packet Counter Register 115 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN115_b; + }; + + union + { + __IM uint32_t FWFRPPCN116; /*!< (@ 0x00006DA0) FRER Passed Packet Counter Register 116 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN116_b; + }; + + union + { + __IM uint32_t FWFRDPCN116; /*!< (@ 0x00006DA4) FRER Discarded Packet Counter Register 116 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN116_b; + }; + + union + { + __IM uint32_t FWFRPPCN117; /*!< (@ 0x00006DA8) FRER Passed Packet Counter Register 117 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN117_b; + }; + + union + { + __IM uint32_t FWFRDPCN117; /*!< (@ 0x00006DAC) FRER Discarded Packet Counter Register 117 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN117_b; + }; + + union + { + __IM uint32_t FWFRPPCN118; /*!< (@ 0x00006DB0) FRER Passed Packet Counter Register 118 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN118_b; + }; + + union + { + __IM uint32_t FWFRDPCN118; /*!< (@ 0x00006DB4) FRER Discarded Packet Counter Register 118 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN118_b; + }; + + union + { + __IM uint32_t FWFRPPCN119; /*!< (@ 0x00006DB8) FRER Passed Packet Counter Register 119 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN119_b; + }; + + union + { + __IM uint32_t FWFRDPCN119; /*!< (@ 0x00006DBC) FRER Discarded Packet Counter Register 119 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN119_b; + }; + + union + { + __IM uint32_t FWFRPPCN120; /*!< (@ 0x00006DC0) FRER Passed Packet Counter Register 120 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN120_b; + }; + + union + { + __IM uint32_t FWFRDPCN120; /*!< (@ 0x00006DC4) FRER Discarded Packet Counter Register 120 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN120_b; + }; + + union + { + __IM uint32_t FWFRPPCN121; /*!< (@ 0x00006DC8) FRER Passed Packet Counter Register 121 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN121_b; + }; + + union + { + __IM uint32_t FWFRDPCN121; /*!< (@ 0x00006DCC) FRER Discarded Packet Counter Register 121 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN121_b; + }; + + union + { + __IM uint32_t FWFRPPCN122; /*!< (@ 0x00006DD0) FRER Passed Packet Counter Register 122 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN122_b; + }; + + union + { + __IM uint32_t FWFRDPCN122; /*!< (@ 0x00006DD4) FRER Discarded Packet Counter Register 122 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN122_b; + }; + + union + { + __IM uint32_t FWFRPPCN123; /*!< (@ 0x00006DD8) FRER Passed Packet Counter Register 123 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN123_b; + }; + + union + { + __IM uint32_t FWFRDPCN123; /*!< (@ 0x00006DDC) FRER Discarded Packet Counter Register 123 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN123_b; + }; + + union + { + __IM uint32_t FWFRPPCN124; /*!< (@ 0x00006DE0) FRER Passed Packet Counter Register 124 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN124_b; + }; + + union + { + __IM uint32_t FWFRDPCN124; /*!< (@ 0x00006DE4) FRER Discarded Packet Counter Register 124 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN124_b; + }; + + union + { + __IM uint32_t FWFRPPCN125; /*!< (@ 0x00006DE8) FRER Passed Packet Counter Register 125 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN125_b; + }; + + union + { + __IM uint32_t FWFRDPCN125; /*!< (@ 0x00006DEC) FRER Discarded Packet Counter Register 125 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN125_b; + }; + + union + { + __IM uint32_t FWFRPPCN126; /*!< (@ 0x00006DF0) FRER Passed Packet Counter Register 126 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN126_b; + }; + + union + { + __IM uint32_t FWFRDPCN126; /*!< (@ 0x00006DF4) FRER Discarded Packet Counter Register 126 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN126_b; + }; + + union + { + __IM uint32_t FWFRPPCN127; /*!< (@ 0x00006DF8) FRER Passed Packet Counter Register 127 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN127_b; + }; + + union + { + __IM uint32_t FWFRDPCN127; /*!< (@ 0x00006DFC) FRER Discarded Packet Counter Register 127 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN127_b; + }; + __IM uint32_t RESERVED261[704]; + + union + { + __IOM uint32_t FWEIS00; /*!< (@ 0x00007900) Error Interrupt Status Register 00 */ + + struct + { + __IOM uint32_t LTHSPFS : 1; /*!< [0..0] Layer 3 Source Port Filtering Status */ + uint32_t : 1; + __IOM uint32_t LTHNTFS : 1; /*!< [2..2] Layer 3 No Target Filtering Status */ + __IOM uint32_t LTHUFS : 1; /*!< [3..3] Layer 3 Unknown Filtering Status */ + uint32_t : 6; + __IOM uint32_t LTWDSPFS : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Status */ + __IOM uint32_t LTWSSPFS : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Status */ + __IOM uint32_t LTWVSPFS : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Status */ + __IOM uint32_t LTWNTFS : 1; /*!< [13..13] Layer 2 No Target Filtering Status */ + __IOM uint32_t LTWSUFS : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Status */ + __IOM uint32_t LTWDUFS : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Status */ + __IOM uint32_t LTWVUFS : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Status */ + __IOM uint32_t PBNTFS : 1; /*!< [17..17] Port Based No Target Filtering Status */ + __IOM uint32_t SMHLFS : 1; /*!< [18..18] Source MAC Hardware Learning Fail Status */ + __IOM uint32_t SMHMFS : 1; /*!< [19..19] Source MAC Hardware Migration Fail Status */ + uint32_t : 2; + __IOM uint32_t WMCFS : 1; /*!< [22..22] Watermark Critical Filtering Status */ + __IOM uint32_t WMFFS : 1; /*!< [23..23] Watermark Flush Filtering Status */ + __IOM uint32_t WMISFS : 1; /*!< [24..24] Watermark IPV Secure Filtering Status */ + __IOM uint32_t WMIUFS : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Status */ + __IOM uint32_t DDES : 1; /*!< [26..26] Direct Descriptor Error Status i */ + uint32_t : 1; + __IOM uint32_t DDSES : 1; /*!< [28..28] Direct Descriptor Security Error Status */ + __IOM uint32_t DDNTFS : 1; /*!< [29..29] Direct Descriptor No Target Filtering Status */ + uint32_t : 2; + } FWEIS00_b; + }; + + union + { + __IOM uint32_t FWEIE00; /*!< (@ 0x00007904) Error Interrupt Enable Register 00 */ + + struct + { + __IOM uint32_t LTHSPFE : 1; /*!< [0..0] Layer 3 Source Port Filtering Enable */ + uint32_t : 1; + __IOM uint32_t LTHNTFE : 1; /*!< [2..2] Layer 3 No Target Filtering Enable */ + __IOM uint32_t LTHUFE : 1; /*!< [3..3] Layer 3 Unknown Filtering Enable */ + uint32_t : 6; + __IOM uint32_t LTWDSPFE : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Enable */ + __IOM uint32_t LTWSSPFE : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Enable */ + __IOM uint32_t LTWVSPFE : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Enable */ + __IOM uint32_t LTWNTFE : 1; /*!< [13..13] Layer 2 No Target Filtering Enable */ + __IOM uint32_t LTWSUFE : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Enable */ + __IOM uint32_t LTWDUFE : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Enable */ + __IOM uint32_t LTWVUFE : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Enable */ + __IOM uint32_t PBNTFE : 1; /*!< [17..17] Port Based No Target Filtering Enable */ + __IOM uint32_t SMHLFE : 1; /*!< [18..18] Source MAC Hardware Learning Fail Enable */ + __IOM uint32_t SMHMFE : 1; /*!< [19..19] Source MAC Hardware Migration Fail Enable */ + uint32_t : 2; + __IOM uint32_t WMCFE : 1; /*!< [22..22] Watermark Critical Filtering Enable */ + __IOM uint32_t WMFFE : 1; /*!< [23..23] Watermark Flush Filtering Enable */ + __IOM uint32_t WMISFE : 1; /*!< [24..24] Watermark IPV Secure Filtering Enable */ + __IOM uint32_t WMIUFE : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Enable */ + __IOM uint32_t DDEE : 1; /*!< [26..26] Direct Descriptor Error Enable */ + __IOM uint32_t DDFEE : 1; /*!< [27..27] Direct Descriptor Format Error Enable */ + __IOM uint32_t DDSEE : 1; /*!< [28..28] Direct Descriptor Security Error Enable */ + __IOM uint32_t DDNTFE : 1; /*!< [29..29] Direct Descriptor No Target Filtering Enable */ + uint32_t : 2; + } FWEIE00_b; + }; + + union + { + __IOM uint32_t FWEID00; /*!< (@ 0x00007908) Error Interrupt Disable Register 00 */ + + struct + { + __IOM uint32_t LTHSPFD : 1; /*!< [0..0] Layer 3 Source Port Filtering Disable */ + uint32_t : 1; + __IOM uint32_t LTHNTFD : 1; /*!< [2..2] Layer 3 No Target Filtering Disable */ + __IOM uint32_t LTHUFD : 1; /*!< [3..3] Layer 3 Unknown Filtering Disable */ + uint32_t : 6; + __IOM uint32_t LTWDSPFD : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Disable */ + __IOM uint32_t LTWSSPFD : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Disable */ + __IOM uint32_t LTWVSPFD : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Disable */ + __IOM uint32_t LTWNTFD : 1; /*!< [13..13] Layer 2 No Target Filtering Disable */ + __IOM uint32_t LTWSUFD : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Disable */ + __IOM uint32_t LTWDUFD : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Disable */ + __IOM uint32_t LTWVUFD : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Disable */ + __IOM uint32_t PBNTFD : 1; /*!< [17..17] Port Based No Target Filtering Disable */ + __IOM uint32_t SMHLFD : 1; /*!< [18..18] Source MAC Hardware Learning Fail Disable */ + __IOM uint32_t SMHMFD : 1; /*!< [19..19] Source MAC Hardware Migration Fail Disable */ + uint32_t : 2; + __IOM uint32_t WMCFD : 1; /*!< [22..22] Watermark Critical Filtering Disable */ + __IOM uint32_t WMFFD : 1; /*!< [23..23] Watermark Flush Filtering Disable */ + __IOM uint32_t WMISFD : 1; /*!< [24..24] Watermark IPV Secure Filtering Disable */ + __IOM uint32_t WMIUFD : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Disable */ + __IOM uint32_t DDED : 1; /*!< [26..26] Direct Descriptor Error Disable */ + __IOM uint32_t DDFED : 1; /*!< [27..27] Direct Descriptor Format Error Disable */ + __IOM uint32_t DDSED : 1; /*!< [28..28] Direct Descriptor Security Error Disable */ + __IOM uint32_t DDNTFD : 1; /*!< [29..29] Direct Descriptor No Target Filtering Disable */ + uint32_t : 2; + } FWEID00_b; + }; + __IM uint32_t RESERVED262; + + union + { + __IOM uint32_t FWEIS01; /*!< (@ 0x00007910) Error Interrupt Status Register 01 */ + + struct + { + __IOM uint32_t LTHSPFS : 1; /*!< [0..0] Layer 3 Source Port Filtering Status */ + uint32_t : 1; + __IOM uint32_t LTHNTFS : 1; /*!< [2..2] Layer 3 No Target Filtering Status */ + __IOM uint32_t LTHUFS : 1; /*!< [3..3] Layer 3 Unknown Filtering Status */ + uint32_t : 6; + __IOM uint32_t LTWDSPFS : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Status */ + __IOM uint32_t LTWSSPFS : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Status */ + __IOM uint32_t LTWVSPFS : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Status */ + __IOM uint32_t LTWNTFS : 1; /*!< [13..13] Layer 2 No Target Filtering Status */ + __IOM uint32_t LTWSUFS : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Status */ + __IOM uint32_t LTWDUFS : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Status */ + __IOM uint32_t LTWVUFS : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Status */ + __IOM uint32_t PBNTFS : 1; /*!< [17..17] Port Based No Target Filtering Status */ + __IOM uint32_t SMHLFS : 1; /*!< [18..18] Source MAC Hardware Learning Fail Status */ + __IOM uint32_t SMHMFS : 1; /*!< [19..19] Source MAC Hardware Migration Fail Status */ + uint32_t : 2; + __IOM uint32_t WMCFS : 1; /*!< [22..22] Watermark Critical Filtering Status */ + __IOM uint32_t WMFFS : 1; /*!< [23..23] Watermark Flush Filtering Status */ + __IOM uint32_t WMISFS : 1; /*!< [24..24] Watermark IPV Secure Filtering Status */ + __IOM uint32_t WMIUFS : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Status */ + __IOM uint32_t DDES : 1; /*!< [26..26] Direct Descriptor Error Status i */ + uint32_t : 1; + __IOM uint32_t DDSES : 1; /*!< [28..28] Direct Descriptor Security Error Status */ + __IOM uint32_t DDNTFS : 1; /*!< [29..29] Direct Descriptor No Target Filtering Status */ + uint32_t : 2; + } FWEIS01_b; + }; + + union + { + __IOM uint32_t FWEIE01; /*!< (@ 0x00007914) Error Interrupt Enable Register 01 */ + + struct + { + __IOM uint32_t LTHSPFE : 1; /*!< [0..0] Layer 3 Source Port Filtering Enable */ + uint32_t : 1; + __IOM uint32_t LTHNTFE : 1; /*!< [2..2] Layer 3 No Target Filtering Enable */ + __IOM uint32_t LTHUFE : 1; /*!< [3..3] Layer 3 Unknown Filtering Enable */ + uint32_t : 6; + __IOM uint32_t LTWDSPFE : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Enable */ + __IOM uint32_t LTWSSPFE : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Enable */ + __IOM uint32_t LTWVSPFE : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Enable */ + __IOM uint32_t LTWNTFE : 1; /*!< [13..13] Layer 2 No Target Filtering Enable */ + __IOM uint32_t LTWSUFE : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Enable */ + __IOM uint32_t LTWDUFE : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Enable */ + __IOM uint32_t LTWVUFE : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Enable */ + __IOM uint32_t PBNTFE : 1; /*!< [17..17] Port Based No Target Filtering Enable */ + __IOM uint32_t SMHLFE : 1; /*!< [18..18] Source MAC Hardware Learning Fail Enable */ + __IOM uint32_t SMHMFE : 1; /*!< [19..19] Source MAC Hardware Migration Fail Enable */ + uint32_t : 2; + __IOM uint32_t WMCFE : 1; /*!< [22..22] Watermark Critical Filtering Enable */ + __IOM uint32_t WMFFE : 1; /*!< [23..23] Watermark Flush Filtering Enable */ + __IOM uint32_t WMISFE : 1; /*!< [24..24] Watermark IPV Secure Filtering Enable */ + __IOM uint32_t WMIUFE : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Enable */ + __IOM uint32_t DDEE : 1; /*!< [26..26] Direct Descriptor Error Enable */ + __IOM uint32_t DDFEE : 1; /*!< [27..27] Direct Descriptor Format Error Enable */ + __IOM uint32_t DDSEE : 1; /*!< [28..28] Direct Descriptor Security Error Enable */ + __IOM uint32_t DDNTFE : 1; /*!< [29..29] Direct Descriptor No Target Filtering Enable */ + uint32_t : 2; + } FWEIE01_b; + }; + + union + { + __IOM uint32_t FWEID01; /*!< (@ 0x00007918) Error Interrupt Disable Register 01 */ + + struct + { + __IOM uint32_t LTHSPFD : 1; /*!< [0..0] Layer 3 Source Port Filtering Disable */ + uint32_t : 1; + __IOM uint32_t LTHNTFD : 1; /*!< [2..2] Layer 3 No Target Filtering Disable */ + __IOM uint32_t LTHUFD : 1; /*!< [3..3] Layer 3 Unknown Filtering Disable */ + uint32_t : 6; + __IOM uint32_t LTWDSPFD : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Disable */ + __IOM uint32_t LTWSSPFD : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Disable */ + __IOM uint32_t LTWVSPFD : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Disable */ + __IOM uint32_t LTWNTFD : 1; /*!< [13..13] Layer 2 No Target Filtering Disable */ + __IOM uint32_t LTWSUFD : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Disable */ + __IOM uint32_t LTWDUFD : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Disable */ + __IOM uint32_t LTWVUFD : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Disable */ + __IOM uint32_t PBNTFD : 1; /*!< [17..17] Port Based No Target Filtering Disable */ + __IOM uint32_t SMHLFD : 1; /*!< [18..18] Source MAC Hardware Learning Fail Disable */ + __IOM uint32_t SMHMFD : 1; /*!< [19..19] Source MAC Hardware Migration Fail Disable */ + uint32_t : 2; + __IOM uint32_t WMCFD : 1; /*!< [22..22] Watermark Critical Filtering Disable */ + __IOM uint32_t WMFFD : 1; /*!< [23..23] Watermark Flush Filtering Disable */ + __IOM uint32_t WMISFD : 1; /*!< [24..24] Watermark IPV Secure Filtering Disable */ + __IOM uint32_t WMIUFD : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Disable */ + __IOM uint32_t DDED : 1; /*!< [26..26] Direct Descriptor Error Disable */ + __IOM uint32_t DDFED : 1; /*!< [27..27] Direct Descriptor Format Error Disable */ + __IOM uint32_t DDSED : 1; /*!< [28..28] Direct Descriptor Security Error Disable */ + __IOM uint32_t DDNTFD : 1; /*!< [29..29] Direct Descriptor No Target Filtering Disable */ + uint32_t : 2; + } FWEID01_b; + }; + __IM uint32_t RESERVED263; + + union + { + __IOM uint32_t FWEIS02; /*!< (@ 0x00007920) Error Interrupt Status Register 02 */ + + struct + { + __IOM uint32_t LTHSPFS : 1; /*!< [0..0] Layer 3 Source Port Filtering Status */ + uint32_t : 1; + __IOM uint32_t LTHNTFS : 1; /*!< [2..2] Layer 3 No Target Filtering Status */ + __IOM uint32_t LTHUFS : 1; /*!< [3..3] Layer 3 Unknown Filtering Status */ + uint32_t : 6; + __IOM uint32_t LTWDSPFS : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Status */ + __IOM uint32_t LTWSSPFS : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Status */ + __IOM uint32_t LTWVSPFS : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Status */ + __IOM uint32_t LTWNTFS : 1; /*!< [13..13] Layer 2 No Target Filtering Status */ + __IOM uint32_t LTWSUFS : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Status */ + __IOM uint32_t LTWDUFS : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Status */ + __IOM uint32_t LTWVUFS : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Status */ + __IOM uint32_t PBNTFS : 1; /*!< [17..17] Port Based No Target Filtering Status */ + __IOM uint32_t SMHLFS : 1; /*!< [18..18] Source MAC Hardware Learning Fail Status */ + __IOM uint32_t SMHMFS : 1; /*!< [19..19] Source MAC Hardware Migration Fail Status */ + uint32_t : 2; + __IOM uint32_t WMCFS : 1; /*!< [22..22] Watermark Critical Filtering Status */ + __IOM uint32_t WMFFS : 1; /*!< [23..23] Watermark Flush Filtering Status */ + __IOM uint32_t WMISFS : 1; /*!< [24..24] Watermark IPV Secure Filtering Status */ + __IOM uint32_t WMIUFS : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Status */ + __IOM uint32_t DDES : 1; /*!< [26..26] Direct Descriptor Error Status i */ + uint32_t : 1; + __IOM uint32_t DDSES : 1; /*!< [28..28] Direct Descriptor Security Error Status */ + __IOM uint32_t DDNTFS : 1; /*!< [29..29] Direct Descriptor No Target Filtering Status */ + uint32_t : 2; + } FWEIS02_b; + }; + + union + { + __IOM uint32_t FWEIE02; /*!< (@ 0x00007924) Error Interrupt Enable Register 02 */ + + struct + { + __IOM uint32_t LTHSPFE : 1; /*!< [0..0] Layer 3 Source Port Filtering Enable */ + uint32_t : 1; + __IOM uint32_t LTHNTFE : 1; /*!< [2..2] Layer 3 No Target Filtering Enable */ + __IOM uint32_t LTHUFE : 1; /*!< [3..3] Layer 3 Unknown Filtering Enable */ + uint32_t : 6; + __IOM uint32_t LTWDSPFE : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Enable */ + __IOM uint32_t LTWSSPFE : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Enable */ + __IOM uint32_t LTWVSPFE : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Enable */ + __IOM uint32_t LTWNTFE : 1; /*!< [13..13] Layer 2 No Target Filtering Enable */ + __IOM uint32_t LTWSUFE : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Enable */ + __IOM uint32_t LTWDUFE : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Enable */ + __IOM uint32_t LTWVUFE : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Enable */ + __IOM uint32_t PBNTFE : 1; /*!< [17..17] Port Based No Target Filtering Enable */ + __IOM uint32_t SMHLFE : 1; /*!< [18..18] Source MAC Hardware Learning Fail Enable */ + __IOM uint32_t SMHMFE : 1; /*!< [19..19] Source MAC Hardware Migration Fail Enable */ + uint32_t : 2; + __IOM uint32_t WMCFE : 1; /*!< [22..22] Watermark Critical Filtering Enable */ + __IOM uint32_t WMFFE : 1; /*!< [23..23] Watermark Flush Filtering Enable */ + __IOM uint32_t WMISFE : 1; /*!< [24..24] Watermark IPV Secure Filtering Enable */ + __IOM uint32_t WMIUFE : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Enable */ + __IOM uint32_t DDEE : 1; /*!< [26..26] Direct Descriptor Error Enable */ + __IOM uint32_t DDFEE : 1; /*!< [27..27] Direct Descriptor Format Error Enable */ + __IOM uint32_t DDSEE : 1; /*!< [28..28] Direct Descriptor Security Error Enable */ + __IOM uint32_t DDNTFE : 1; /*!< [29..29] Direct Descriptor No Target Filtering Enable */ + uint32_t : 2; + } FWEIE02_b; + }; + + union + { + __IOM uint32_t FWEID02; /*!< (@ 0x00007928) Error Interrupt Disable Register 02 */ + + struct + { + __IOM uint32_t LTHSPFD : 1; /*!< [0..0] Layer 3 Source Port Filtering Disable */ + uint32_t : 1; + __IOM uint32_t LTHNTFD : 1; /*!< [2..2] Layer 3 No Target Filtering Disable */ + __IOM uint32_t LTHUFD : 1; /*!< [3..3] Layer 3 Unknown Filtering Disable */ + uint32_t : 6; + __IOM uint32_t LTWDSPFD : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Disable */ + __IOM uint32_t LTWSSPFD : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Disable */ + __IOM uint32_t LTWVSPFD : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Disable */ + __IOM uint32_t LTWNTFD : 1; /*!< [13..13] Layer 2 No Target Filtering Disable */ + __IOM uint32_t LTWSUFD : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Disable */ + __IOM uint32_t LTWDUFD : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Disable */ + __IOM uint32_t LTWVUFD : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Disable */ + __IOM uint32_t PBNTFD : 1; /*!< [17..17] Port Based No Target Filtering Disable */ + __IOM uint32_t SMHLFD : 1; /*!< [18..18] Source MAC Hardware Learning Fail Disable */ + __IOM uint32_t SMHMFD : 1; /*!< [19..19] Source MAC Hardware Migration Fail Disable */ + uint32_t : 2; + __IOM uint32_t WMCFD : 1; /*!< [22..22] Watermark Critical Filtering Disable */ + __IOM uint32_t WMFFD : 1; /*!< [23..23] Watermark Flush Filtering Disable */ + __IOM uint32_t WMISFD : 1; /*!< [24..24] Watermark IPV Secure Filtering Disable */ + __IOM uint32_t WMIUFD : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Disable */ + __IOM uint32_t DDED : 1; /*!< [26..26] Direct Descriptor Error Disable */ + __IOM uint32_t DDFED : 1; /*!< [27..27] Direct Descriptor Format Error Disable */ + __IOM uint32_t DDSED : 1; /*!< [28..28] Direct Descriptor Security Error Disable */ + __IOM uint32_t DDNTFD : 1; /*!< [29..29] Direct Descriptor No Target Filtering Disable */ + uint32_t : 2; + } FWEID02_b; + }; + __IM uint32_t RESERVED264[53]; + + union + { + __IOM uint32_t FWEIS1; /*!< (@ 0x00007A00) Error Interrupt Status Register 1 */ + + struct + { + __IOM uint32_t LTHTEES : 1; /*!< [0..0] L3 Table ECC Error Status */ + __IOM uint32_t LTHTSES : 1; /*!< [1..1] L3 Table Security Error Status */ + uint32_t : 2; + __IOM uint32_t MACTEES : 1; /*!< [4..4] MAC Table ECC Error Status */ + __IOM uint32_t MACTSES : 1; /*!< [5..5] MAC Table Security Error Status */ + __IOM uint32_t VLANTEES : 1; /*!< [6..6] VLAN Table ECC Error Status */ + __IOM uint32_t VLANTSES : 1; /*!< [7..7] VLAN Table Security Error Status */ + __IOM uint32_t L23UEES : 1; /*!< [8..8] Layer 2/Layer 3 Update ECC Error Status */ + uint32_t : 7; + __IOM uint32_t AREES : 1; /*!< [16..16] ATS RAM ECC Error Status */ + uint32_t : 15; + } FWEIS1_b; + }; + + union + { + __IOM uint32_t FWEIE1; /*!< (@ 0x00007A04) Error Interrupt Enable Register 1 */ + + struct + { + __IOM uint32_t LTHTEEE : 1; /*!< [0..0] L3 Table ECC Error Enable */ + __IOM uint32_t LTHTSEE : 1; /*!< [1..1] L3 Table Security Error Enable */ + uint32_t : 2; + __IOM uint32_t MACTEEE : 1; /*!< [4..4] MAC Table ECC Error Enable */ + __IOM uint32_t MACTSEE : 1; /*!< [5..5] MAC Table Security Error Enable */ + __IOM uint32_t VLANTEEE : 1; /*!< [6..6] VLAN Table ECC Error Enable */ + __IOM uint32_t VLANTSEE : 1; /*!< [7..7] VLAN Table Security Error Enable */ + __IOM uint32_t L23UEEE : 1; /*!< [8..8] Layer 2/Layer 3 Update ECC Error Enable */ + uint32_t : 7; + __IOM uint32_t AREEE : 1; /*!< [16..16] ATS RAM ECC Error Enable */ + uint32_t : 15; + } FWEIE1_b; + }; + + union + { + __IOM uint32_t FWEID1; /*!< (@ 0x00007A08) Error Interrupt Disable Register 1 */ + + struct + { + __IOM uint32_t LTHTEED : 1; /*!< [0..0] L3 Table ECC Error Disable */ + __IOM uint32_t LTHTSED : 1; /*!< [1..1] L3 Table Security Error Disable */ + uint32_t : 2; + __IOM uint32_t MACTEED : 1; /*!< [4..4] MAC Table ECC Error Disable */ + __IOM uint32_t MACTSED : 1; /*!< [5..5] MAC Table Security Error Disable */ + __IOM uint32_t VLANTEED : 1; /*!< [6..6] VLAN Table ECC Error Disable */ + __IOM uint32_t VLANTSED : 1; /*!< [7..7] VLAN Table Security Error Disable */ + __IOM uint32_t L23UEED : 1; /*!< [8..8] Layer 2/Layer 3 Update ECC Error Disable */ + uint32_t : 7; + __IOM uint32_t AREED : 1; /*!< [16..16] ATS RAM ECC Error Disable */ + uint32_t : 15; + } FWEID1_b; + }; + __IM uint32_t RESERVED265; + + union + { + __IOM uint32_t FWEIS2; /*!< (@ 0x00007A10) Error Interrupt Status Register 2 */ + + struct + { + __IOM uint32_t PMFS : 16; /*!< [15..0] PSFP MSDU Filtering Status */ + uint32_t : 16; + } FWEIS2_b; + }; + + union + { + __IOM uint32_t FWEIE2; /*!< (@ 0x00007A14) Error Interrupt Enable Register 2 */ + + struct + { + __IOM uint32_t PMFE : 16; /*!< [15..0] PSFP MSDU Filtering Enable */ + uint32_t : 16; + } FWEIE2_b; + }; + + union + { + __IOM uint32_t FWEID2; /*!< (@ 0x00007A18) Error Interrupt Disable Register 2 */ + + struct + { + __IOM uint32_t PMFD : 16; /*!< [15..0] PSFP MSDU Filtering Disable */ + uint32_t : 16; + } FWEID2_b; + }; + __IM uint32_t RESERVED266[9]; + + union + { + __IOM uint32_t FWEIS5; /*!< (@ 0x00007A40) Error Interrupt Status Register 5 */ + + struct + { + __IOM uint32_t PMRFS : 32; /*!< [31..0] PSFP Meter Filtering Status */ + } FWEIS5_b; + }; + + union + { + __IOM uint32_t FWEIE5; /*!< (@ 0x00007A44) Error Interrupt Enable Register 5 */ + + struct + { + __IOM uint32_t PMRFE : 32; /*!< [31..0] PSFP Meter Filtering Enable */ + } FWEIE5_b; + }; + + union + { + __IOM uint32_t FWEID5; /*!< (@ 0x00007A48) Error Interrupt Disable Register 5 */ + + struct + { + __IOM uint32_t PMRFD : 32; /*!< [31..0] PSFP Meter Filtering Disable */ + } FWEID5_b; + }; + __IM uint32_t RESERVED267; + + union + { + __IOM uint32_t FWEIS60; /*!< (@ 0x00007A50) Error Interrupt Status Register 60 */ + + struct + { + __IOM uint32_t FFS : 32; /*!< [31..0] FRER Filtering Status */ + } FWEIS60_b; + }; + + union + { + __IOM uint32_t FWEIE60; /*!< (@ 0x00007A54) Error Interrupt Enable Register 60 */ + + struct + { + __IOM uint32_t FFE : 32; /*!< [31..0] FRER Filtering Enable */ + } FWEIE60_b; + }; + + union + { + __IOM uint32_t FWEID60; /*!< (@ 0x00007A58) Error Interrupt Disable Register 60 */ + + struct + { + __IOM uint32_t FFD : 32; /*!< [31..0] FRER Filtering Disable */ + } FWEID60_b; + }; + __IM uint32_t RESERVED268; + + union + { + __IOM uint32_t FWEIS61; /*!< (@ 0x00007A60) Error Interrupt Status Register 61 */ + + struct + { + __IOM uint32_t FFS : 32; /*!< [31..0] FRER Filtering Status */ + } FWEIS61_b; + }; + + union + { + __IOM uint32_t FWEIE61; /*!< (@ 0x00007A64) Error Interrupt Enable Register 61 */ + + struct + { + __IOM uint32_t FFE : 32; /*!< [31..0] FRER Filtering Enable */ + } FWEIE61_b; + }; + + union + { + __IOM uint32_t FWEID61; /*!< (@ 0x00007A68) Error Interrupt Disable Register 61 */ + + struct + { + __IOM uint32_t FFD : 32; /*!< [31..0] FRER Filtering Disable */ + } FWEID61_b; + }; + __IM uint32_t RESERVED269; + + union + { + __IOM uint32_t FWEIS62; /*!< (@ 0x00007A70) Error Interrupt Status Register 62 */ + + struct + { + __IOM uint32_t FFS : 32; /*!< [31..0] FRER Filtering Status */ + } FWEIS62_b; + }; + + union + { + __IOM uint32_t FWEIE62; /*!< (@ 0x00007A74) Error Interrupt Enable Register 62 */ + + struct + { + __IOM uint32_t FFE : 32; /*!< [31..0] FRER Filtering Enable */ + } FWEIE62_b; + }; + + union + { + __IOM uint32_t FWEID62; /*!< (@ 0x00007A78) Error Interrupt Disable Register 62 */ + + struct + { + __IOM uint32_t FFD : 32; /*!< [31..0] FRER Filtering Disable */ + } FWEID62_b; + }; + __IM uint32_t RESERVED270; + + union + { + __IOM uint32_t FWEIS63; /*!< (@ 0x00007A80) Error Interrupt Status Register 63 */ + + struct + { + __IOM uint32_t FFS : 32; /*!< [31..0] FRER Filtering Status */ + } FWEIS63_b; + }; + + union + { + __IOM uint32_t FWEIE63; /*!< (@ 0x00007A84) Error Interrupt Enable Register 63 */ + + struct + { + __IOM uint32_t FFE : 32; /*!< [31..0] FRER Filtering Enable */ + } FWEIE63_b; + }; + + union + { + __IOM uint32_t FWEID63; /*!< (@ 0x00007A88) Error Interrupt Disable Register 63 */ + + struct + { + __IOM uint32_t FFD : 32; /*!< [31..0] FRER Filtering Disable */ + } FWEID63_b; + }; + __IM uint32_t RESERVED271; + + union + { + __IOM uint32_t FWEIS70; /*!< (@ 0x00007A90) Error Interrupt Status Register 70 */ + + struct + { + __IOM uint32_t FOORS : 32; /*!< [31..0] FRER Out Of Range Status */ + } FWEIS70_b; + }; + + union + { + __IOM uint32_t FWEIE70; /*!< (@ 0x00007A94) Error Interrupt Enable Register 70 */ + + struct + { + __IOM uint32_t FOORE : 32; /*!< [31..0] FRER Out Of Range Enable */ + } FWEIE70_b; + }; + + union + { + __IOM uint32_t FWEID70; /*!< (@ 0x00007A98) Error Interrupt Disable Register 70 */ + + struct + { + __IOM uint32_t FOORD : 32; /*!< [31..0] FRER Out Of Range Disable */ + } FWEID70_b; + }; + __IM uint32_t RESERVED272; + + union + { + __IOM uint32_t FWEIS71; /*!< (@ 0x00007AA0) Error Interrupt Status Register 71 */ + + struct + { + __IOM uint32_t FOORS : 32; /*!< [31..0] FRER Out Of Range Status */ + } FWEIS71_b; + }; + + union + { + __IOM uint32_t FWEIE71; /*!< (@ 0x00007AA4) Error Interrupt Enable Register 71 */ + + struct + { + __IOM uint32_t FOORE : 32; /*!< [31..0] FRER Out Of Range Enable */ + } FWEIE71_b; + }; + + union + { + __IOM uint32_t FWEID71; /*!< (@ 0x00007AA8) Error Interrupt Disable Register 71 */ + + struct + { + __IOM uint32_t FOORD : 32; /*!< [31..0] FRER Out Of Range Disable */ + } FWEID71_b; + }; + __IM uint32_t RESERVED273; + + union + { + __IOM uint32_t FWEIS72; /*!< (@ 0x00007AB0) Error Interrupt Status Register 72 */ + + struct + { + __IOM uint32_t FOORS : 32; /*!< [31..0] FRER Out Of Range Status */ + } FWEIS72_b; + }; + + union + { + __IOM uint32_t FWEIE72; /*!< (@ 0x00007AB4) Error Interrupt Enable Register 72 */ + + struct + { + __IOM uint32_t FOORE : 32; /*!< [31..0] FRER Out Of Range Enable */ + } FWEIE72_b; + }; + + union + { + __IOM uint32_t FWEID72; /*!< (@ 0x00007AB8) Error Interrupt Disable Register 72 */ + + struct + { + __IOM uint32_t FOORD : 32; /*!< [31..0] FRER Out Of Range Disable */ + } FWEID72_b; + }; + __IM uint32_t RESERVED274; + + union + { + __IOM uint32_t FWEIS73; /*!< (@ 0x00007AC0) Error Interrupt Status Register 73 */ + + struct + { + __IOM uint32_t FOORS : 32; /*!< [31..0] FRER Out Of Range Status */ + } FWEIS73_b; + }; + + union + { + __IOM uint32_t FWEIE73; /*!< (@ 0x00007AC4) Error Interrupt Enable Register 73 */ + + struct + { + __IOM uint32_t FOORE : 32; /*!< [31..0] FRER Out Of Range Enable */ + } FWEIE73_b; + }; + + union + { + __IOM uint32_t FWEID73; /*!< (@ 0x00007AC8) Error Interrupt Disable Register 73 */ + + struct + { + __IOM uint32_t FOORD : 32; /*!< [31..0] FRER Out Of Range Disable */ + } FWEID73_b; + }; + __IM uint32_t RESERVED275; + + union + { + __IOM uint32_t FWEIS80; /*!< (@ 0x00007AD0) Error Interrupt Status Register 80 */ + + struct + { + __IOM uint32_t TOS : 32; /*!< [31..0] Timeout Status */ + } FWEIS80_b; + }; + + union + { + __IOM uint32_t FWEIE80; /*!< (@ 0x00007AD4) Error Interrupt Enable Register 80 */ + + struct + { + __IOM uint32_t TOE : 32; /*!< [31..0] Timeout Enable */ + } FWEIE80_b; + }; + + union + { + __IOM uint32_t FWEID80; /*!< (@ 0x00007AD8) Error Interrupt Disable Register 80 */ + + struct + { + __IOM uint32_t TOD : 32; /*!< [31..0] Timeout Disable */ + } FWEID80_b; + }; + __IM uint32_t RESERVED276; + + union + { + __IOM uint32_t FWEIS81; /*!< (@ 0x00007AE0) Error Interrupt Status Register 81 */ + + struct + { + __IOM uint32_t TOS : 32; /*!< [31..0] Timeout Status */ + } FWEIS81_b; + }; + + union + { + __IOM uint32_t FWEIE81; /*!< (@ 0x00007AE4) Error Interrupt Enable Register 81 */ + + struct + { + __IOM uint32_t TOE : 32; /*!< [31..0] Timeout Enable */ + } FWEIE81_b; + }; + + union + { + __IOM uint32_t FWEID81; /*!< (@ 0x00007AE8) Error Interrupt Disable Register 81 */ + + struct + { + __IOM uint32_t TOD : 32; /*!< [31..0] Timeout Disable */ + } FWEID81_b; + }; + __IM uint32_t RESERVED277; + + union + { + __IOM uint32_t FWEIS82; /*!< (@ 0x00007AF0) Error Interrupt Status Register 82 */ + + struct + { + __IOM uint32_t TOS : 32; /*!< [31..0] Timeout Status */ + } FWEIS82_b; + }; + + union + { + __IOM uint32_t FWEIE82; /*!< (@ 0x00007AF4) Error Interrupt Enable Register 82 */ + + struct + { + __IOM uint32_t TOE : 32; /*!< [31..0] Timeout Enable */ + } FWEIE82_b; + }; + + union + { + __IOM uint32_t FWEID82; /*!< (@ 0x00007AF8) Error Interrupt Disable Register 82 */ + + struct + { + __IOM uint32_t TOD : 32; /*!< [31..0] Timeout Disable */ + } FWEID82_b; + }; + __IM uint32_t RESERVED278; + + union + { + __IOM uint32_t FWEIS83; /*!< (@ 0x00007B00) Error Interrupt Status Register 83 */ + + struct + { + __IOM uint32_t TOS : 32; /*!< [31..0] Timeout Status */ + } FWEIS83_b; + }; + + union + { + __IOM uint32_t FWEIE83; /*!< (@ 0x00007B04) Error Interrupt Enable Register 83 */ + + struct + { + __IOM uint32_t TOE : 32; /*!< [31..0] Timeout Enable */ + } FWEIE83_b; + }; + + union + { + __IOM uint32_t FWEID83; /*!< (@ 0x00007B08) Error Interrupt Disable Register 83 */ + + struct + { + __IOM uint32_t TOD : 32; /*!< [31..0] Timeout Disable */ + } FWEID83_b; + }; + __IM uint32_t RESERVED279[61]; + + union + { + __IOM uint32_t FWMIS0; /*!< (@ 0x00007C00) Monitoring Interrupt Status Register 0 */ + + struct + { + __IOM uint32_t LTHTFS : 1; /*!< [0..0] L3 Table Full Status */ + uint32_t : 1; + __IOM uint32_t MACTFS : 1; /*!< [2..2] MAC Table Full Status */ + __IOM uint32_t VLANTFS : 1; /*!< [3..3] VLAN Table Full Status */ + uint32_t : 13; + __IOM uint32_t MACADAS : 1; /*!< [17..17] MAC Address Deleted Aging Status */ + uint32_t : 14; + } FWMIS0_b; + }; + + union + { + __IOM uint32_t FWMIE0; /*!< (@ 0x00007C04) Monitoring Interrupt Enable Register 0 */ + + struct + { + __IOM uint32_t LTHTFE : 1; /*!< [0..0] L3 Table Full Enable */ + uint32_t : 1; + __IOM uint32_t MACTFE : 1; /*!< [2..2] MAC Table Full Enable */ + __IOM uint32_t VLANTFE : 1; /*!< [3..3] VLAN Table Full Enable */ + uint32_t : 13; + __IOM uint32_t MACADAE : 1; /*!< [17..17] MAC Address Deleted Aging Enable */ + uint32_t : 14; + } FWMIE0_b; + }; + + union + { + __IOM uint32_t FWMID0; /*!< (@ 0x00007C08) Monitoring Interrupt Disable Register 0 */ + + struct + { + __IOM uint32_t LTHTFD : 1; /*!< [0..0] L3 Table Full Disable */ + uint32_t : 1; + __IOM uint32_t MACTFD : 1; /*!< [2..2] MAC Table Full Disable */ + __IOM uint32_t VLANTFD : 1; /*!< [3..3] VLAN Table Full Disable */ + uint32_t : 13; + __IOM uint32_t MACADAD : 1; /*!< [17..17] MAC Address Deleted Aging Disable */ + uint32_t : 14; + } FWMID0_b; + }; +} R_MFWD_Type; /*!< Size = 31756 (0x7c0c) */ + +/* =========================================================================================================================== */ +/* ================ R_MIPI_DSI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DSI Link (R_MIPI_DSI) + */ + +typedef struct /*!< (@ 0x40346000) R_MIPI_DSI Structure */ +{ + union + { + __IM uint32_t ISR; /*!< (@ 0x00000000) Interrupt Status Register */ + + struct + { + __IM uint32_t SQ0 : 1; /*!< [0..0] Sequence Channel-0 Interrupt Flag */ + uint32_t : 3; + __IM uint32_t SQ1 : 1; /*!< [4..4] Sequence Channel-1 Interrupt Flag */ + uint32_t : 3; + __IM uint32_t VM : 1; /*!< [8..8] Video Mode Interrupt Flag */ + uint32_t : 3; + __IM uint32_t RCV : 1; /*!< [12..12] Receive Interrupt Flag */ + uint32_t : 3; + __IM uint32_t FERR : 1; /*!< [16..16] Fatal Error Interrupt Flag */ + uint32_t : 3; + __IM uint32_t PPI : 1; /*!< [20..20] PPI Interrupt Flag */ + uint32_t : 11; + } ISR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IM uint32_t LINKSR; /*!< (@ 0x00000010) Link Status Register */ + + struct + { + __IM uint32_t SQ0RUN : 1; /*!< [0..0] Sequence Channel-0 Running Flag */ + uint32_t : 3; + __IM uint32_t SQ1RUN : 1; /*!< [4..4] Sequence Channel-1 Running Flag */ + uint32_t : 3; + __IM uint32_t VRUN : 1; /*!< [8..8] Video Mode Operation Running Flag */ + uint32_t : 3; + __IM uint32_t HSBUSY : 1; /*!< [12..12] HS Operation Busy Flag */ + __IM uint32_t LPBUSY : 1; /*!< [13..13] LP Operation Busy Flag */ + uint32_t : 18; + } LINKSR_b; + }; + __IM uint32_t RESERVED1[59]; + + union + { + __IOM uint32_t TXSETR; /*!< (@ 0x00000100) Transmit Set Register */ + + struct + { + __IOM uint32_t NUMLANE : 2; /*!< [1..0] Number of Lane */ + uint32_t : 6; + __IOM uint32_t CLEN : 1; /*!< [8..8] Clock Lane Enable */ + __IOM uint32_t DLEN : 1; /*!< [9..9] Data Lane Enable */ + uint32_t : 22; + } TXSETR_b; + }; + + union + { + __IOM uint32_t HSCLKSETR; /*!< (@ 0x00000104) HS Clock Set Register */ + + struct + { + __IOM uint32_t HSCLST : 1; /*!< [0..0] HS Clock Start */ + __IOM uint32_t HSCLMD : 1; /*!< [1..1] HS Clock Running Mode */ + uint32_t : 30; + } HSCLKSETR_b; + }; + + union + { + __IOM uint32_t ULPSSETR; /*!< (@ 0x00000108) ULPS Set Register */ + + struct + { + __IOM uint32_t WKUP : 8; /*!< [7..0] ULPS Wakeup Period */ + uint32_t : 24; + } ULPSSETR_b; + }; + + union + { + __OM uint32_t ULPSCR; /*!< (@ 0x0000010C) ULPS Control Register */ + + struct + { + uint32_t : 24; + __OM uint32_t CLENT : 1; /*!< [24..24] CL ULPS Enter */ + __OM uint32_t CLEXIT : 1; /*!< [25..25] CL ULPS Exit */ + uint32_t : 2; + __OM uint32_t DLENT : 1; /*!< [28..28] DL ULPS Enter */ + __OM uint32_t DLEXIT : 1; /*!< [29..29] DL ULPS Exit */ + uint32_t : 2; + } ULPSCR_b; + }; + + union + { + __IOM uint32_t RSTCR; /*!< (@ 0x00000110) Reset Control Register */ + + struct + { + __IOM uint32_t SWRST : 1; /*!< [0..0] Software Reset */ + uint32_t : 15; + __IOM uint32_t FTXSTP : 1; /*!< [16..16] Force Tx Stop Mode */ + uint32_t : 15; + } RSTCR_b; + }; + + union + { + __IM uint32_t RSTSR; /*!< (@ 0x00000114) Reset Status Register */ + + struct + { + __IM uint32_t RSTHS : 1; /*!< [0..0] HS Software Reset Status */ + __IM uint32_t RSTLP : 1; /*!< [1..1] LP Software Reset Status */ + __IM uint32_t RSTAPB : 1; /*!< [2..2] APB Software Reset Status */ + __IM uint32_t RSTAXI : 1; /*!< [3..3] AXI Software Reset Status */ + __IM uint32_t RSTV : 1; /*!< [4..4] Video Software Reset Status */ + uint32_t : 3; + __IM uint32_t DL0STP : 1; /*!< [8..8] Data Lane-0 Stop Status */ + __IM uint32_t DL1STP : 1; /*!< [9..9] Data Lane-1 Stop Status */ + uint32_t : 5; + __IM uint32_t DL0DIR : 1; /*!< [15..15] Data Lane-0 Direction */ + uint32_t : 16; + } RSTSR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t DSISETR; /*!< (@ 0x00000120) DSI Set Register */ + + struct + { + __IOM uint32_t MRPSZ : 16; /*!< [15..0] Maximum Return Packet Size */ + __IOM uint32_t ECCEN : 1; /*!< [16..16] ECC Check Enable */ + uint32_t : 3; + __IOM uint32_t VC0CRCEN : 1; /*!< [20..20] VC-0 CRC Check Enable */ + __IOM uint32_t VC1CRCEN : 1; /*!< [21..21] VC-1 CRC Check Enable */ + __IOM uint32_t VC2CRCEN : 1; /*!< [22..22] VC-2 CRC Check Enable */ + __IOM uint32_t VC3CRCEN : 1; /*!< [23..23] VC-3 CRC Check Enable */ + uint32_t : 5; + __IOM uint32_t SCREN : 1; /*!< [29..29] Data Scramble Enable */ + __IOM uint32_t EXTEMD : 1; /*!< [30..30] External Tearing Effect Detection Sense Select */ + __IOM uint32_t EOTPEN : 1; /*!< [31..31] HS Transfer EoTp Enable */ + } DSISETR_b; + }; + __IM uint32_t RESERVED3[15]; + + union + { + __IOM uint32_t TXPPD0R; /*!< (@ 0x00000160) Transmit Packet Payload Data 0 Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Payload Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Payload Data 1 */ + __IOM uint32_t DATA2 : 8; /*!< [23..16] Payload Data 2 */ + __IOM uint32_t DATA3 : 8; /*!< [31..24] Payload Data 3 */ + } TXPPD0R_b; + }; + + union + { + __IOM uint32_t TXPPD1R; /*!< (@ 0x00000164) Transmit Packet Payload Data 1 Register */ + + struct + { + __IOM uint32_t DATA4 : 8; /*!< [7..0] Payload Data 4 */ + __IOM uint32_t DATA5 : 8; /*!< [15..8] Payload Data 5 */ + __IOM uint32_t DATA6 : 8; /*!< [23..16] Payload Data 6 */ + __IOM uint32_t DATA7 : 8; /*!< [31..24] Payload Data 7 */ + } TXPPD1R_b; + }; + + union + { + __IOM uint32_t TXPPD2R; /*!< (@ 0x00000168) Transmit Packet Payload Data 2 Register */ + + struct + { + __IOM uint32_t DATA8 : 8; /*!< [7..0] Payload Data 8 */ + __IOM uint32_t DATA9 : 8; /*!< [15..8] Payload Data 9 */ + __IOM uint32_t DATA10 : 8; /*!< [23..16] Payload Data 10 */ + __IOM uint32_t DATA11 : 8; /*!< [31..24] Payload Data 11 */ + } TXPPD2R_b; + }; + + union + { + __IOM uint32_t TXPPD3R; /*!< (@ 0x0000016C) Transmit Packet Payload Data 3 Register */ + + struct + { + __IOM uint32_t DATA12 : 8; /*!< [7..0] Payload Data 12 */ + __IOM uint32_t DATA13 : 8; /*!< [15..8] Payload Data 13 */ + __IOM uint32_t DATA14 : 8; /*!< [23..16] Payload Data 14 */ + __IOM uint32_t DATA15 : 8; /*!< [31..24] Payload Data 15 */ + } TXPPD3R_b; + }; + __IM uint32_t RESERVED4[36]; + + union + { + __IM uint32_t RXSR; /*!< (@ 0x00000200) Receive Status Register */ + + struct + { + __IM uint32_t BTAREND : 1; /*!< [0..0] BTA Request End Interrupt Flag */ + __IM uint32_t LRXHTO : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Flag */ + __IM uint32_t TATO : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Flag */ + uint32_t : 5; + __IM uint32_t RXRESP : 1; /*!< [8..8] Response Packet Receive Interrupt Flag */ + uint32_t : 1; + __IM uint32_t RXEOTP : 1; /*!< [10..10] EoTp Receive Interrupt Flag */ + uint32_t : 2; + __IM uint32_t RXTE : 1; /*!< [13..13] Tearing Effect Trigger Receive Interrupt Flag */ + __IM uint32_t RXACK : 1; /*!< [14..14] ACK Trigger Receive Interrupt Flag */ + __IM uint32_t EXTEDET : 1; /*!< [15..15] External Tearing Effect Detect Interrupt Flag */ + __IM uint32_t MLFERR : 1; /*!< [16..16] Malform Error Interrupt Flag */ + __IM uint32_t ECCERRM : 1; /*!< [17..17] Multi Bit ECC Error Interrupt Flag */ + __IM uint32_t UNEXERR : 1; /*!< [18..18] Unexpected Packet Error Interrupt Flag */ + uint32_t : 1; + __IM uint32_t WCERR : 1; /*!< [20..20] Word Count Error Interrupt Flag */ + __IM uint32_t CRCERR : 1; /*!< [21..21] CRC Error Interrupt Flag */ + __IM uint32_t IBERR : 1; /*!< [22..22] Internal Bus Error Interrupt Flag */ + __IM uint32_t RXOVFERR : 1; /*!< [23..23] Receive Buffer Overflow Error Interrupt Flag */ + __IM uint32_t PRTOERR : 1; /*!< [24..24] Peripheral Response Timeout Error Interrupt Flag */ + __IM uint32_t NORESERR : 1; /*!< [25..25] No Response Error Interrupt Flag */ + __IM uint32_t RSIZEERR : 1; /*!< [26..26] Return Packet Size Error Interrupt Flag */ + uint32_t : 1; + __IM uint32_t ECCERRS : 1; /*!< [28..28] Single Bit ECC Error Interrupt Flag */ + uint32_t : 1; + __IM uint32_t RXAKE : 1; /*!< [30..30] Acknowledge and Error Report Receive Interrupt Flag */ + uint32_t : 1; + } RXSR_b; + }; + + union + { + __IOM uint32_t RXSCR; /*!< (@ 0x00000204) Receive Status Clear Register */ + + struct + { + __IOM uint32_t BTAREND : 1; /*!< [0..0] BTA Request End Interrupt Flag Clear */ + __IOM uint32_t LRXHTO : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Flag Clear */ + __IOM uint32_t TATO : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Flag Clear */ + uint32_t : 5; + __IOM uint32_t RXRESP : 1; /*!< [8..8] Response Packet Receive Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t RXEOTP : 1; /*!< [10..10] EoTp Receive Interrupt Flag Clear */ + uint32_t : 2; + __IOM uint32_t RXTE : 1; /*!< [13..13] Tearing Effect Trigger Receive Interrupt Flag Clear */ + __IOM uint32_t RXACK : 1; /*!< [14..14] ACK Trigger Receive Interrupt Flag Clear */ + __IOM uint32_t EXTEDET : 1; /*!< [15..15] External Tearing Effect Detect Interrupt Flag Clear */ + __IOM uint32_t MLFERR : 1; /*!< [16..16] Malform Error Interrupt Flag Clear */ + __IOM uint32_t ECCERRM : 1; /*!< [17..17] Multi Bit ECC Error Interrupt Flag Clear */ + __IOM uint32_t UNEXERR : 1; /*!< [18..18] Unexpected Packet Error Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t WCERR : 1; /*!< [20..20] Word Count Error Interrupt Flag Clear */ + __IOM uint32_t CRCERR : 1; /*!< [21..21] CRC Error Interrupt Flag Clear */ + __IOM uint32_t IBERR : 1; /*!< [22..22] Internal Bus Error Interrupt Flag Clear */ + __IOM uint32_t RXOVFERR : 1; /*!< [23..23] Receive Buffer Overflow Error Interrupt Flag Clear */ + __IOM uint32_t PRTOERR : 1; /*!< [24..24] Peripheral Response Timeout Error Interrupt Flag Clear */ + __IOM uint32_t NORESERR : 1; /*!< [25..25] No Response Error Interrupt Flag Clear */ + __IOM uint32_t RSIZEERR : 1; /*!< [26..26] Return Packet Size Error Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t ECCERRS : 1; /*!< [28..28] Single Bit ECC Error Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t RXAKE : 1; /*!< [30..30] Acknowledge and Error Report Receive Interrupt Flag + * Clear */ + uint32_t : 1; + } RXSCR_b; + }; + + union + { + __IOM uint32_t RXIER; /*!< (@ 0x00000208) Receive Interrupt Enable Register */ + + struct + { + __IOM uint32_t BTAREND : 1; /*!< [0..0] BTA Request End Interrupt Enable */ + __IOM uint32_t LRXHTO : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Enable */ + __IOM uint32_t TATO : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Enable */ + uint32_t : 5; + __IOM uint32_t RXRESP : 1; /*!< [8..8] Response Packet Receive Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t RXEOTP : 1; /*!< [10..10] EoTp Receive Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t RXTE : 1; /*!< [13..13] Tearing Effect Trigger Receive Interrupt Enable */ + __IOM uint32_t RXACK : 1; /*!< [14..14] ACK Trigger Receive Interrupt Enable */ + __IOM uint32_t EXTEDET : 1; /*!< [15..15] External Tearing Effect Detect Interrupt Enable */ + __IOM uint32_t MLFERR : 1; /*!< [16..16] Malform Error Interrupt Enable */ + __IOM uint32_t ECCERRM : 1; /*!< [17..17] Multi Bit ECC Error Interrupt Enable */ + __IOM uint32_t UNEXERR : 1; /*!< [18..18] Unexpected Packet Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t WCERR : 1; /*!< [20..20] Word Count Error Interrupt Enable */ + __IOM uint32_t CRCERR : 1; /*!< [21..21] CRC Error Interrupt Enable */ + __IOM uint32_t IBERR : 1; /*!< [22..22] Internal Bus Error Interrupt Enable */ + __IOM uint32_t RXOVFERR : 1; /*!< [23..23] Receive Buffer Overflow Error Interrupt Enable */ + __IOM uint32_t PRTOERR : 1; /*!< [24..24] Peripheral Response Timeout Error Interrupt Enable */ + __IOM uint32_t NORESERR : 1; /*!< [25..25] No Response Error Interrupt Enable */ + __IOM uint32_t RSIZEERR : 1; /*!< [26..26] Return Packet Size Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t ECCERRS : 1; /*!< [28..28] Single Bit ECC Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t RXAKE : 1; /*!< [30..30] Acknowledge and Error Report Receive Interrupt Enable */ + uint32_t : 1; + } RXIER_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t PRESPTOBTASETR; /*!< (@ 0x00000210) Peripheral Response Timeout BTA Set Register */ + + struct + { + __IOM uint32_t PRTBTA : 32; /*!< [31..0] Peripheral Response Timeout Count */ + } PRESPTOBTASETR_b; + }; + + union + { + __IOM uint32_t PRESPTOLPSETR; /*!< (@ 0x00000214) Peripheral Response Timeout LP Set Register */ + + struct + { + __IOM uint32_t LPWTO : 16; /*!< [15..0] LPDT WRITE Request Timeout */ + __IOM uint32_t LPRTO : 16; /*!< [31..16] LPDT READ Request Timeout */ + } PRESPTOLPSETR_b; + }; + + union + { + __IOM uint32_t PRESPTOHSSETR; /*!< (@ 0x00000218) Peripheral Response Timeout HS Set Register */ + + struct + { + __IOM uint32_t HSWTO : 16; /*!< [15..0] HS WRITE Request Timeout */ + __IOM uint32_t HSRTO : 16; /*!< [31..16] HS READ Request Timeout */ + } PRESPTOHSSETR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IM uint32_t AKEPLATIR; /*!< (@ 0x00000220) Acknowledge and Error Report Packet Parameter + * Latest Info Register */ + + struct + { + __IM uint32_t EREP : 16; /*!< [15..0] Error Report */ + __IM uint32_t VC : 4; /*!< [19..16] Virtual Channel ID */ + uint32_t : 12; + } AKEPLATIR_b; + }; + + union + { + __IM uint32_t AKEPACMSR; /*!< (@ 0x00000224) Acknowledge and Error Report Packet Parameter + * Accumulate Status Register */ + + struct + { + __IM uint32_t AEREP : 16; /*!< [15..0] Accumulated Error Report */ + __IM uint32_t AVC : 4; /*!< [19..16] Virtual Channel ID */ + uint32_t : 12; + } AKEPACMSR_b; + }; + + union + { + __IOM uint32_t AKEPSCR; /*!< (@ 0x00000228) Acknowledge and Error Report Packet Parameter + * Status Clear Register */ + + struct + { + __IOM uint32_t AEREP : 16; /*!< [15..0] Accumulated Error Report Clear */ + __IM uint32_t AVC : 4; /*!< [19..16] Virtual Channel ID */ + uint32_t : 12; + } AKEPSCR_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IM uint32_t RXRSSR; /*!< (@ 0x00000230) Receive Result Saved Status Register */ + + struct + { + __IM uint32_t SLT0VLD : 1; /*!< [0..0] Slot-0 Valid Flag */ + __IM uint32_t SLT1VLD : 1; /*!< [1..1] Slot-1 Valid Flag */ + __IM uint32_t SLT2VLD : 1; /*!< [2..2] Slot-2 Valid Flag */ + __IM uint32_t SLT3VLD : 1; /*!< [3..3] Slot-3 Valid Flag */ + uint32_t : 28; + } RXRSSR_b; + }; + + union + { + __IOM uint32_t RXRSSCR; /*!< (@ 0x00000234) Receive Result Saved Status Clear Register */ + + struct + { + __IOM uint32_t SLT0VLD : 1; /*!< [0..0] Slot-0 Valid Flag Clear */ + __IOM uint32_t SLT1VLD : 1; /*!< [1..1] Slot-1 Valid Flag Clear */ + __IOM uint32_t SLT2VLD : 1; /*!< [2..2] Slot-2 Valid Flag Clear */ + __IOM uint32_t SLT3VLD : 1; /*!< [3..3] Slot-3 Valid Flag Clear */ + uint32_t : 28; + } RXRSSCR_b; + }; + + union + { + __IM uint32_t RXRINFOOWSR; /*!< (@ 0x00000238) Receive Result Info Overwrite Status Register */ + + struct + { + __IM uint32_t SL0OW : 1; /*!< [0..0] Slot-0 Information Overwrite Flag */ + __IM uint32_t SL1OW : 1; /*!< [1..1] Slot-1 Information Overwrite Flag */ + __IM uint32_t SL2OW : 1; /*!< [2..2] Slot-2 Information Overwrite Flag */ + __IM uint32_t SL3OW : 1; /*!< [3..3] Slot-3 Information Overwrite Flag */ + uint32_t : 28; + } RXRINFOOWSR_b; + }; + + union + { + __IOM uint32_t RXRINFOOWSCR; /*!< (@ 0x0000023C) Receive Result Info Overwrite Status Clear Register */ + + struct + { + __IOM uint32_t SL0OW : 1; /*!< [0..0] Slot-0 Information Overwrite Flag Clear */ + __IOM uint32_t SL1OW : 1; /*!< [1..1] Slot-1 Information Overwrite Flag Clear */ + __IOM uint32_t SL2OW : 1; /*!< [2..2] Slot-2 Information Overwrite Flag Clear */ + __IOM uint32_t SL3OW : 1; /*!< [3..3] Slot-3 Information Overwrite Flag Clear */ + uint32_t : 28; + } RXRINFOOWSCR_b; + }; + + union + { + union + { + __IM uint32_t RXRSS0R; /*!< (@ 0x00000240) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IM uint32_t FMT : 1; /*!< [24..24] Packet Format */ + __IM uint32_t RXSUC : 1; /*!< [25..25] Receive Success */ + __IM uint32_t RXFERR : 1; /*!< [26..26] Fatal Error */ + __IM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail */ + __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail */ + __IM uint32_t RXCERR : 1; /*!< [29..29] Receive Correctable Error */ + __IM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet */ + __IM uint32_t INFOOW : 1; /*!< [31..31] Information Overwrite */ + } RXRSS0R_b; + }; + + struct + { + union + { + union + { + __IM uint16_t RXRSS0R_L; /*!< (@ 0x00000240) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } RXRSS0R_L_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS0R_LL; /*!< (@ 0x00000240) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } RXRSS0R_LL_b; + }; + + union + { + __IM uint8_t RXRSS0R_LH; /*!< (@ 0x00000241) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } RXRSS0R_LH_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RXRSS0R_H; /*!< (@ 0x00000242) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IM uint16_t FMT : 1; /*!< [8..8] Packet Format */ + __IM uint16_t RXSUC : 1; /*!< [9..9] Receive Success */ + __IM uint16_t RXFERR : 1; /*!< [10..10] Fatal Error */ + __IM uint16_t RXFAIL : 1; /*!< [11..11] Receive Fail */ + __IM uint16_t RXPFAIL : 1; /*!< [12..12] Receive Packet Data Fail */ + __IM uint16_t RXCERR : 1; /*!< [13..13] Receive Correctable Error */ + __IM uint16_t RXAKE : 1; /*!< [14..14] Receive Acknowledge and Error Report Packet */ + __IM uint16_t INFOOW : 1; /*!< [15..15] Information Overwrite */ + } RXRSS0R_H_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS0R_HL; /*!< (@ 0x00000242) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } RXRSS0R_HL_b; + }; + + union + { + __IM uint8_t RXRSS0R_HH; /*!< (@ 0x00000243) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint8_t FMT : 1; /*!< [0..0] Packet Format */ + __IM uint8_t RXSUC : 1; /*!< [1..1] Receive Success */ + __IM uint8_t RXFERR : 1; /*!< [2..2] Fatal Error */ + __IM uint8_t RXFAIL : 1; /*!< [3..3] Receive Fail */ + __IM uint8_t RXPFAIL : 1; /*!< [4..4] Receive Packet Data Fail */ + __IM uint8_t RXCERR : 1; /*!< [5..5] Receive Correctable Error */ + __IM uint8_t RXAKE : 1; /*!< [6..6] Receive Acknowledge and Error Report Packet */ + __IM uint8_t INFOOW : 1; /*!< [7..7] Information Overwrite */ + } RXRSS0R_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IM uint32_t RXRSS1R; /*!< (@ 0x00000244) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IM uint32_t FMT : 1; /*!< [24..24] Packet Format */ + __IM uint32_t RXSUC : 1; /*!< [25..25] Receive Success */ + __IM uint32_t RXFERR : 1; /*!< [26..26] Fatal Error */ + __IM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail */ + __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail */ + __IM uint32_t RXCERR : 1; /*!< [29..29] Receive Correctable Error */ + __IM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet */ + __IM uint32_t INFOOW : 1; /*!< [31..31] Information Overwrite */ + } RXRSS1R_b; + }; + + struct + { + union + { + union + { + __IM uint16_t RXRSS1R_L; /*!< (@ 0x00000244) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } RXRSS1R_L_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS1R_LL; /*!< (@ 0x00000244) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } RXRSS1R_LL_b; + }; + + union + { + __IM uint8_t RXRSS1R_LH; /*!< (@ 0x00000245) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } RXRSS1R_LH_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RXRSS1R_H; /*!< (@ 0x00000246) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IM uint16_t FMT : 1; /*!< [8..8] Packet Format */ + __IM uint16_t RXSUC : 1; /*!< [9..9] Receive Success */ + __IM uint16_t RXFERR : 1; /*!< [10..10] Fatal Error */ + __IM uint16_t RXFAIL : 1; /*!< [11..11] Receive Fail */ + __IM uint16_t RXPFAIL : 1; /*!< [12..12] Receive Packet Data Fail */ + __IM uint16_t RXCERR : 1; /*!< [13..13] Receive Correctable Error */ + __IM uint16_t RXAKE : 1; /*!< [14..14] Receive Acknowledge and Error Report Packet */ + __IM uint16_t INFOOW : 1; /*!< [15..15] Information Overwrite */ + } RXRSS1R_H_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS1R_HL; /*!< (@ 0x00000246) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } RXRSS1R_HL_b; + }; + + union + { + __IM uint8_t RXRSS1R_HH; /*!< (@ 0x00000247) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint8_t FMT : 1; /*!< [0..0] Packet Format */ + __IM uint8_t RXSUC : 1; /*!< [1..1] Receive Success */ + __IM uint8_t RXFERR : 1; /*!< [2..2] Fatal Error */ + __IM uint8_t RXFAIL : 1; /*!< [3..3] Receive Fail */ + __IM uint8_t RXPFAIL : 1; /*!< [4..4] Receive Packet Data Fail */ + __IM uint8_t RXCERR : 1; /*!< [5..5] Receive Correctable Error */ + __IM uint8_t RXAKE : 1; /*!< [6..6] Receive Acknowledge and Error Report Packet */ + __IM uint8_t INFOOW : 1; /*!< [7..7] Information Overwrite */ + } RXRSS1R_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IM uint32_t RXRSS2R; /*!< (@ 0x00000248) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IM uint32_t FMT : 1; /*!< [24..24] Packet Format */ + __IM uint32_t RXSUC : 1; /*!< [25..25] Receive Success */ + __IM uint32_t RXFERR : 1; /*!< [26..26] Fatal Error */ + __IM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail */ + __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail */ + __IM uint32_t RXCERR : 1; /*!< [29..29] Receive Correctable Error */ + __IM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet */ + __IM uint32_t INFOOW : 1; /*!< [31..31] Information Overwrite */ + } RXRSS2R_b; + }; + + struct + { + union + { + union + { + __IM uint16_t RXRSS2R_L; /*!< (@ 0x00000248) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } RXRSS2R_L_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS2R_LL; /*!< (@ 0x00000248) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } RXRSS2R_LL_b; + }; + + union + { + __IM uint8_t RXRSS2R_LH; /*!< (@ 0x00000249) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } RXRSS2R_LH_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RXRSS2R_H; /*!< (@ 0x0000024A) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IM uint16_t FMT : 1; /*!< [8..8] Packet Format */ + __IM uint16_t RXSUC : 1; /*!< [9..9] Receive Success */ + __IM uint16_t RXFERR : 1; /*!< [10..10] Fatal Error */ + __IM uint16_t RXFAIL : 1; /*!< [11..11] Receive Fail */ + __IM uint16_t RXPFAIL : 1; /*!< [12..12] Receive Packet Data Fail */ + __IM uint16_t RXCERR : 1; /*!< [13..13] Receive Correctable Error */ + __IM uint16_t RXAKE : 1; /*!< [14..14] Receive Acknowledge and Error Report Packet */ + __IM uint16_t INFOOW : 1; /*!< [15..15] Information Overwrite */ + } RXRSS2R_H_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS2R_HL; /*!< (@ 0x0000024A) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } RXRSS2R_HL_b; + }; + + union + { + __IM uint8_t RXRSS2R_HH; /*!< (@ 0x0000024B) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint8_t FMT : 1; /*!< [0..0] Packet Format */ + __IM uint8_t RXSUC : 1; /*!< [1..1] Receive Success */ + __IM uint8_t RXFERR : 1; /*!< [2..2] Fatal Error */ + __IM uint8_t RXFAIL : 1; /*!< [3..3] Receive Fail */ + __IM uint8_t RXPFAIL : 1; /*!< [4..4] Receive Packet Data Fail */ + __IM uint8_t RXCERR : 1; /*!< [5..5] Receive Correctable Error */ + __IM uint8_t RXAKE : 1; /*!< [6..6] Receive Acknowledge and Error Report Packet */ + __IM uint8_t INFOOW : 1; /*!< [7..7] Information Overwrite */ + } RXRSS2R_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IM uint32_t RXRSS3R; /*!< (@ 0x0000024C) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IM uint32_t FMT : 1; /*!< [24..24] Packet Format */ + __IM uint32_t RXSUC : 1; /*!< [25..25] Receive Success */ + __IM uint32_t RXFERR : 1; /*!< [26..26] Fatal Error */ + __IM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail */ + __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail */ + __IM uint32_t RXCERR : 1; /*!< [29..29] Receive Correctable Error */ + __IM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet */ + __IM uint32_t INFOOW : 1; /*!< [31..31] Information Overwrite */ + } RXRSS3R_b; + }; + + struct + { + union + { + union + { + __IM uint16_t RXRSS3R_L; /*!< (@ 0x0000024C) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } RXRSS3R_L_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS3R_LL; /*!< (@ 0x0000024C) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } RXRSS3R_LL_b; + }; + + union + { + __IM uint8_t RXRSS3R_LH; /*!< (@ 0x0000024D) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } RXRSS3R_LH_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RXRSS3R_H; /*!< (@ 0x0000024E) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IM uint16_t FMT : 1; /*!< [8..8] Packet Format */ + __IM uint16_t RXSUC : 1; /*!< [9..9] Receive Success */ + __IM uint16_t RXFERR : 1; /*!< [10..10] Fatal Error */ + __IM uint16_t RXFAIL : 1; /*!< [11..11] Receive Fail */ + __IM uint16_t RXPFAIL : 1; /*!< [12..12] Receive Packet Data Fail */ + __IM uint16_t RXCERR : 1; /*!< [13..13] Receive Correctable Error */ + __IM uint16_t RXAKE : 1; /*!< [14..14] Receive Acknowledge and Error Report Packet */ + __IM uint16_t INFOOW : 1; /*!< [15..15] Information Overwrite */ + } RXRSS3R_H_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS3R_HL; /*!< (@ 0x0000024E) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } RXRSS3R_HL_b; + }; + + union + { + __IM uint8_t RXRSS3R_HH; /*!< (@ 0x0000024F) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint8_t FMT : 1; /*!< [0..0] Packet Format */ + __IM uint8_t RXSUC : 1; /*!< [1..1] Receive Success */ + __IM uint8_t RXFERR : 1; /*!< [2..2] Fatal Error */ + __IM uint8_t RXFAIL : 1; /*!< [3..3] Receive Fail */ + __IM uint8_t RXPFAIL : 1; /*!< [4..4] Receive Packet Data Fail */ + __IM uint8_t RXCERR : 1; /*!< [5..5] Receive Correctable Error */ + __IM uint8_t RXAKE : 1; /*!< [6..6] Receive Acknowledge and Error Report Packet */ + __IM uint8_t INFOOW : 1; /*!< [7..7] Information Overwrite */ + } RXRSS3R_HH_b; + }; + }; + }; + }; + }; + __IM uint32_t RESERVED8[28]; + + union + { + __IM uint32_t RXPPD0R; /*!< (@ 0x000002C0) Receive Packet Payload Data 0 Register */ + + struct + { + __IM uint32_t DATA0 : 8; /*!< [7..0] Payload Data 0 */ + __IM uint32_t DATA1 : 8; /*!< [15..8] Payload Data 1 */ + __IM uint32_t DATA2 : 8; /*!< [23..16] Payload Data 2 */ + __IM uint32_t DATA3 : 8; /*!< [31..24] Payload Data 3 */ + } RXPPD0R_b; + }; + + union + { + __IM uint32_t RXPPD1R; /*!< (@ 0x000002C4) Receive Packet Payload Data 1 Register */ + + struct + { + __IM uint32_t DATA4 : 8; /*!< [7..0] Payload Data 0 */ + __IM uint32_t DATA5 : 8; /*!< [15..8] Payload Data 1 */ + __IM uint32_t DATA6 : 8; /*!< [23..16] Payload Data 2 */ + __IM uint32_t DATA7 : 8; /*!< [31..24] Payload Data 3 */ + } RXPPD1R_b; + }; + + union + { + __IM uint32_t RXPPD2R; /*!< (@ 0x000002C8) Receive Packet Payload Data 2 Register */ + + struct + { + __IM uint32_t DATA8 : 8; /*!< [7..0] Payload Data 8 */ + __IM uint32_t DATA9 : 8; /*!< [15..8] Payload Data 9 */ + __IM uint32_t DATA10 : 8; /*!< [23..16] Payload Data 10 */ + __IM uint32_t DATA11 : 8; /*!< [31..24] Payload Data 11 */ + } RXPPD2R_b; + }; + + union + { + __IM uint32_t RXPPD3R; /*!< (@ 0x000002CC) Receive Packet Payload Data 3 Register */ + + struct + { + __IM uint32_t DATA12 : 8; /*!< [7..0] Payload Data 12 */ + __IM uint32_t DATA13 : 8; /*!< [15..8] Payload Data 13 */ + __IM uint32_t DATA14 : 8; /*!< [23..16] Payload Data 14 */ + __IM uint32_t DATA15 : 8; /*!< [31..24] Payload Data 15 */ + } RXPPD3R_b; + }; + __IM uint32_t RESERVED9[4]; + + union + { + __IOM uint32_t HSTXTOSETR; /*!< (@ 0x000002E0) HS TX Timeout Set Register */ + + struct + { + __IOM uint32_t HTXTO : 32; /*!< [31..0] HS TX Timeout Count */ + } HSTXTOSETR_b; + }; + + union + { + __IOM uint32_t LRXHTOSETR; /*!< (@ 0x000002E4) LRX-H Timeout Set Register */ + + struct + { + __IOM uint32_t LRXHTO : 32; /*!< [31..0] LP-RX Host Processor Timeout */ + } LRXHTOSETR_b; + }; + + union + { + __IOM uint32_t TATOSETR; /*!< (@ 0x000002E8) TA Timeout Set Register */ + + struct + { + __IOM uint32_t TATO : 32; /*!< [31..0] Turnaround Acknowledge Timeout */ + } TATOSETR_b; + }; + __IM uint32_t RESERVED10[5]; + + union + { + __IM uint32_t FERRSR; /*!< (@ 0x00000300) Fatal Error Status Register */ + + struct + { + __IM uint32_t HTXTO : 1; /*!< [0..0] HS TX Timeout Interrupt Flag */ + __IM uint32_t LRXHTO : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Flag */ + __IM uint32_t TATO : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Flag */ + uint32_t : 13; + __IM uint32_t ESCENT : 1; /*!< [16..16] Escape mode Entry Error Interrupt Flag */ + __IM uint32_t SYNCESC : 1; /*!< [17..17] LPDT Sync Error Interrupt Flag */ + __IM uint32_t CTRL : 1; /*!< [18..18] Control Error Interrupt Flag */ + __IM uint32_t CLP0 : 1; /*!< [19..19] LP0 Contention Error Interrupt Flag */ + __IM uint32_t CLP1 : 1; /*!< [20..20] LP1 Contention Error Interrupt Flag */ + uint32_t : 6; + __IM uint32_t CLP0S : 1; /*!< [27..27] LP0 Contention Error Status */ + __IM uint32_t CLP1S : 1; /*!< [28..28] LP1 Contention Error Status */ + uint32_t : 3; + } FERRSR_b; + }; + + union + { + __IOM uint32_t FERRSCR; /*!< (@ 0x00000304) Fatal Error Status Clear Register */ + + struct + { + __IOM uint32_t HTXTO : 1; /*!< [0..0] HS TX Timeout Interrupt Flag Clear */ + __IOM uint32_t LRXHTO : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Flag Clear */ + __IOM uint32_t TATO : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Flag Clear */ + uint32_t : 13; + __IOM uint32_t ESCENT : 1; /*!< [16..16] Escape mode Entry Error Interrupt Flag Clear */ + __IOM uint32_t SYNCESC : 1; /*!< [17..17] LPDT Sync Error Interrupt Flag Clear */ + __IOM uint32_t CTRL : 1; /*!< [18..18] Control Error Interrupt Flag Clear */ + __IOM uint32_t CLP0 : 1; /*!< [19..19] LP0 Contention Error Interrupt Flag Clear */ + __IOM uint32_t CLP1 : 1; /*!< [20..20] LP1 Contention Error Interrupt Flag Clear */ + uint32_t : 11; + } FERRSCR_b; + }; + + union + { + __IOM uint32_t FERRIER; /*!< (@ 0x00000308) Fatal Error Interrupt Enable Register */ + + struct + { + __IOM uint32_t HTXTO : 1; /*!< [0..0] HS TX Timeout Interrupt Enable */ + __IOM uint32_t LRXHTO : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Enable */ + __IOM uint32_t TATO : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Enable */ + uint32_t : 13; + __IOM uint32_t ESCENT : 1; /*!< [16..16] Escape mode Entry Error Interrupt Enable */ + __IOM uint32_t SYNCESC : 1; /*!< [17..17] LPDT Sync Error Interrupt Enable */ + __IOM uint32_t CTRL : 1; /*!< [18..18] Control Error Interrupt Enable */ + __IOM uint32_t CLP0 : 1; /*!< [19..19] LP0 Contention Error Interrupt Enable */ + __IOM uint32_t CLP1 : 1; /*!< [20..20] LP1 Contention Error Interrupt Enable */ + uint32_t : 11; + } FERRIER_b; + }; + __IM uint32_t RESERVED11[2]; + + union + { + __IOM uint32_t CLSTPTSETR; /*!< (@ 0x00000314) Clock Lane Stop Time Set Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t CLKSTPT : 10; /*!< [11..2] Clock Stop Time */ + uint32_t : 4; + __IOM uint32_t CLKBFHT : 8; /*!< [23..16] Clock Beforehand Time */ + __IOM uint32_t CLKKPT : 8; /*!< [31..24] Clock Keep Time */ + } CLSTPTSETR_b; + }; + + union + { + __IOM uint32_t LPTRNSTSETR; /*!< (@ 0x00000318) LP Transition Time Set Register */ + + struct + { + __IOM uint32_t GOLPBKT : 10; /*!< [9..0] Go LP and Back Time */ + uint32_t : 22; + } LPTRNSTSETR_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IM uint32_t PLSR; /*!< (@ 0x00000320) Physical Lane Status Register */ + + struct + { + __IM uint32_t CLUAN : 1; /*!< [0..0] Clock Lane UlpsActiveNot Status */ + __IM uint32_t CLSTP : 1; /*!< [1..1] Clock Lane Stop Status */ + __IM uint32_t DL0RLE : 1; /*!< [2..2] Data Lane-0 RxLpdtEsc Status */ + __IM uint32_t DL0RUE : 1; /*!< [3..3] Data Lane-0 RxUlpsEsc Status */ + __IM uint32_t DL0UAN : 1; /*!< [4..4] Data Lane-0 UlpsActiveNot Status */ + __IM uint32_t DL1UAN : 1; /*!< [5..5] Data Lane-1 UlpsActiveNot Status */ + uint32_t : 2; + __IM uint32_t DL0STP : 1; /*!< [8..8] Data Lane-0 Stop Status */ + __IM uint32_t DL1STP : 1; /*!< [9..9] Data Lane-1 Stop Status */ + uint32_t : 2; + __IM uint32_t DL0RX2TX : 1; /*!< [12..12] Data Lane-0 RX to TX Transition Interrupt Flag */ + __IM uint32_t DL0TX2RX : 1; /*!< [13..13] Data Lane-0 TX to RX Transition Interrupt Flag */ + uint32_t : 1; + __IM uint32_t DL0DIR : 1; /*!< [15..15] Data Lane-0 Direction */ + uint32_t : 8; + __IM uint32_t CLULPENT : 1; /*!< [24..24] Clock Lane ULPS Enter Interrupt Flag */ + __IM uint32_t CLULPEXT : 1; /*!< [25..25] Clock Lane ULPS Exit Interrupt Flag */ + __IM uint32_t CLLP2HS : 1; /*!< [26..26] Clock Lane LP to HS Transition Interrupt Flag */ + __IM uint32_t CLHS2LP : 1; /*!< [27..27] Clock Lane HS to LP Transition Interrupt Flag */ + __IM uint32_t DLULPENT : 1; /*!< [28..28] Data Lane ULPS Enter Interrupt Flag */ + __IM uint32_t DLULPEXT : 1; /*!< [29..29] Data Lane ULPS Exit Interrupt Flag */ + uint32_t : 2; + } PLSR_b; + }; + + union + { + __IOM uint32_t PLSCR; /*!< (@ 0x00000324) Physical Lane Status Clear Register */ + + struct + { + uint32_t : 12; + __IOM uint32_t DL0RX2TX : 1; /*!< [12..12] Data Lane-0 RX to TX Transition Interrupt Flag Clear */ + __IOM uint32_t DL0TX2RX : 1; /*!< [13..13] Data Lane-0 TX to RX Transition Interrupt Flag Clear */ + uint32_t : 10; + __IOM uint32_t CLULPENT : 1; /*!< [24..24] Clock Lane ULPS Enter Interrupt Flag Clear */ + __IOM uint32_t CLULPEXT : 1; /*!< [25..25] Clock Lane ULPS Exit Interrupt Flag Clear */ + __IOM uint32_t CLLP2HS : 1; /*!< [26..26] Clock Lane LP to HS Transition Interrupt Flag Clear */ + __IOM uint32_t CLHS2LP : 1; /*!< [27..27] Clock Lane HS to LP Transition Interrupt Flag Clear */ + __IOM uint32_t DLULPENT : 1; /*!< [28..28] Data Lane ULPS Enter Interrupt Flag Clear */ + __IOM uint32_t DLULPEXT : 1; /*!< [29..29] Data Lane ULPS Exit Interrupt Flag Clear */ + uint32_t : 2; + } PLSCR_b; + }; + + union + { + __IOM uint32_t PLIER; /*!< (@ 0x00000328) Physical Lane Interrupt Enable Register */ + + struct + { + uint32_t : 12; + __IOM uint32_t DL0RX2TX : 1; /*!< [12..12] Data Lane-0 RX to TX Transition Interrupt Enable */ + __IOM uint32_t DL0TX2RX : 1; /*!< [13..13] Data Lane-0 TX to RX Transition Interrupt Enable */ + uint32_t : 10; + __IOM uint32_t CLULPENT : 1; /*!< [24..24] Clock Lane ULPS Enter Interrupt Enable */ + __IOM uint32_t CLULPEXT : 1; /*!< [25..25] Clock Lane ULPS Exit Interrupt Enable */ + __IOM uint32_t CLLP2HS : 1; /*!< [26..26] Clock Lane LP to HS Transition Interrupt Enable */ + __IOM uint32_t CLHS2LP : 1; /*!< [27..27] Clock Lane HS to LP Transition Interrupt Enable */ + __IOM uint32_t DLULPENT : 1; /*!< [28..28] Data Lane ULPS Enter Interrupt Enable */ + __IOM uint32_t DLULPEXT : 1; /*!< [29..29] Data Lane ULPS Exit Interrupt Enable */ + uint32_t : 2; + } PLIER_b; + }; + __IM uint32_t RESERVED13[53]; + + union + { + __IOM uint32_t VMSET0R; /*!< (@ 0x00000400) Video Mode Set 0 Register */ + + struct + { + __OM uint32_t VSTART : 1; /*!< [0..0] Video Mode Operation Start */ + __OM uint32_t VSTOP : 1; /*!< [1..1] Video Mode Operation Stop */ + uint32_t : 6; + __IOM uint32_t HSANOLP : 1; /*!< [8..8] HSA period No LP */ + __IOM uint32_t HBPNOLP : 1; /*!< [9..9] HBP period No LP */ + __IOM uint32_t HFPNOLP : 1; /*!< [10..10] HFP period No LP */ + uint32_t : 21; + } VMSET0R_b; + }; + + union + { + __IOM uint32_t VMSET1R; /*!< (@ 0x00000404) Video Mode Set 1 Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t DLY : 12; /*!< [13..2] Delay Value */ + uint32_t : 18; + } VMSET1R_b; + }; + __IM uint32_t RESERVED14[2]; + + union + { + __IM uint32_t VMSR; /*!< (@ 0x00000410) Video Mode Status Register */ + + struct + { + __IM uint32_t START : 1; /*!< [0..0] Video Mode Operation Start Interrupt Flag */ + __IM uint32_t STOP : 1; /*!< [1..1] Video Mode Operation Stop Interrupt Flag */ + __IM uint32_t RUNNING : 1; /*!< [2..2] Video Mode Operation Running Status */ + __IM uint32_t VIRDY : 1; /*!< [3..3] Video Mode Operation Ready Interrupt Flag */ + uint32_t : 16; + __IM uint32_t TIMERR : 1; /*!< [20..20] Timing Error Interrupt Flag */ + uint32_t : 1; + __IM uint32_t VBUFUDF : 1; /*!< [22..22] Video Buffer Underflow Error Interrupt Flag */ + __IM uint32_t VBUFOVF : 1; /*!< [23..23] Video Buffer Overflow Error Interrupt Flag */ + uint32_t : 8; + } VMSR_b; + }; + + union + { + __IOM uint32_t VMSCR; /*!< (@ 0x00000414) Video Mode Status Clear Register */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] Video Mode Operation Start Interrupt Flag Clear */ + __IOM uint32_t STOP : 1; /*!< [1..1] Video Mode Operation Stop Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t VIRDY : 1; /*!< [3..3] Video Mode Operation Ready Interrupt Flag Clear */ + uint32_t : 16; + __IOM uint32_t TIMERR : 1; /*!< [20..20] Timing Error Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t VBUFUDF : 1; /*!< [22..22] Video Buffer Underflow Error Interrupt Flag Clear */ + __IOM uint32_t VBUFOVF : 1; /*!< [23..23] Video Buffer Overflow Error Interrupt Flag Clear */ + uint32_t : 8; + } VMSCR_b; + }; + + union + { + __IOM uint32_t VMIER; /*!< (@ 0x00000418) Video Mode Interrupt Enable Register */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] Video Mode Operation Start Interrupt Enable */ + __IOM uint32_t STOP : 1; /*!< [1..1] Video Mode Operation Stop Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t VIRDY : 1; /*!< [3..3] Video Mode Operation Ready Interrupt Enable */ + uint32_t : 16; + __IOM uint32_t TIMERR : 1; /*!< [20..20] Timing Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t VBUFUDF : 1; /*!< [22..22] Video Buffer Underflow Error Interrupt Enable */ + __IOM uint32_t VBUFOVF : 1; /*!< [23..23] Video Buffer Overflow Error Interrupt Enable */ + uint32_t : 8; + } VMIER_b; + }; + __IM uint32_t RESERVED15; + + union + { + __IOM uint32_t VMPPSETR; /*!< (@ 0x00000420) Video Mode Pixel Packet Set Register */ + + struct + { + uint32_t : 15; + __IOM uint32_t TXESYNC : 1; /*!< [15..15] Transmit End of Sync Pulse */ + __IOM uint32_t DT : 6; /*!< [21..16] Video Mode Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Video Mode Virtual Channel */ + uint32_t : 8; + } VMPPSETR_b; + }; + __IM uint32_t RESERVED16; + + union + { + __IOM uint32_t VMVSSETR; /*!< (@ 0x00000428) Video Mode Vertical Size Set Register */ + + struct + { + __IOM uint32_t VSA : 12; /*!< [11..0] VSA Lines */ + uint32_t : 3; + __IOM uint32_t VSPOL : 1; /*!< [15..15] VSYNC Polarity */ + __IOM uint32_t VACT : 15; /*!< [30..16] Vertical Active Lines */ + uint32_t : 1; + } VMVSSETR_b; + }; + + union + { + __IOM uint32_t VMVPSETR; /*!< (@ 0x0000042C) Video Mode Vertical Porch Set Register */ + + struct + { + __IOM uint32_t VBP : 13; /*!< [12..0] VBP Lines */ + uint32_t : 3; + __IOM uint32_t VFP : 13; /*!< [28..16] VFP Lines */ + uint32_t : 3; + } VMVPSETR_b; + }; + + union + { + __IOM uint32_t VMHSSETR; /*!< (@ 0x00000430) Video Mode Horizontal Size Set Register */ + + struct + { + __IOM uint32_t HSA : 12; /*!< [11..0] HSA Pixels */ + uint32_t : 3; + __IOM uint32_t HSPOL : 1; /*!< [15..15] HSYNC Polarity */ + __IOM uint32_t HACT : 15; /*!< [30..16] HACT Pixels */ + uint32_t : 1; + } VMHSSETR_b; + }; + + union + { + __IOM uint32_t VMHPSETR; /*!< (@ 0x00000434) Video Mode Horizontal Porch Set Register */ + + struct + { + __IOM uint32_t HBP : 13; /*!< [12..0] HBP Pixels */ + uint32_t : 3; + __IOM uint32_t HFP : 13; /*!< [28..16] HFP Pixels */ + uint32_t : 3; + } VMHPSETR_b; + }; + __IM uint32_t RESERVED17[98]; + + union + { + __IOM uint32_t SQCH0SET0R; /*!< (@ 0x000005C0) Sequence Channel 0 Set 0 Register */ + + struct + { + __OM uint32_t START : 1; /*!< [0..0] Sequence Operation Start */ + uint32_t : 31; + } SQCH0SET0R_b; + }; + __IM uint32_t RESERVED18[3]; + + union + { + __IM uint32_t SQCH0SR; /*!< (@ 0x000005D0) Sequence Channel 0 Status Register */ + + struct + { + uint32_t : 2; + __IM uint32_t RUNNING : 1; /*!< [2..2] Sequence Operation Running Status */ + uint32_t : 1; + __IM uint32_t AACTFIN : 1; /*!< [4..4] All Actions Finish Interrupt Flag */ + uint32_t : 3; + __IM uint32_t ADESFIN : 1; /*!< [8..8] All-Descriptors Finish Interrupt Flag */ + uint32_t : 7; + __IM uint32_t DABORT : 1; /*!< [16..16] Descriptor Abort Interrupt Flag */ + uint32_t : 2; + __IM uint32_t SIZEERR : 1; /*!< [19..19] Packet Size Error Interrupt Flag */ + uint32_t : 4; + __IM uint32_t TXIBERR : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Flag */ + uint32_t : 1; + __IM uint32_t RXFERR : 1; /*!< [26..26] Receive Fatal Error Interrupt Flag */ + __IM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail Interrupt Flag */ + __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Flag */ + __IM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Flag */ + __IM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt + * Flag */ + uint32_t : 1; + } SQCH0SR_b; + }; + + union + { + __IOM uint32_t SQCH0SCR; /*!< (@ 0x000005D4) Sequence Channel 0 Status Clear Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t AACTFIN : 1; /*!< [4..4] All Actions Finish Interrupt Flag Clear */ + uint32_t : 3; + __IOM uint32_t ADESFIN : 1; /*!< [8..8] All-Descriptors Finish Interrupt Flag Clear */ + uint32_t : 7; + __IOM uint32_t DABORT : 1; /*!< [16..16] Descriptor Abort Interrupt Flag Clear */ + uint32_t : 2; + __IOM uint32_t SIZEERR : 1; /*!< [19..19] Packet Size Error Interrupt Flag Clear */ + uint32_t : 4; + __IOM uint32_t TXIBERR : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t RXFERR : 1; /*!< [26..26] Receive Fatal Error Interrupt Flag Clear */ + __IOM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail Interrupt Flag Clear */ + __IOM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Flag Clear */ + __IOM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Flag Clear */ + __IOM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt + * Flag Clear */ + uint32_t : 1; + } SQCH0SCR_b; + }; + + union + { + __IOM uint32_t SQCH0IER; /*!< (@ 0x000005D8) Sequence Channel 0 Interrupt Enable Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t AACTFIN : 1; /*!< [4..4] All Actions Finish Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t ADESFIN : 1; /*!< [8..8] All-Descriptors Finish Interrupt Enable */ + uint32_t : 7; + __IOM uint32_t DABORT : 1; /*!< [16..16] Descriptor Abort Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SIZEERR : 1; /*!< [19..19] Packet Size Error Interrupt Enable */ + uint32_t : 4; + __IOM uint32_t TXIBERR : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t RXFERR : 1; /*!< [26..26] Receive Fatal Error Interrupt Enable */ + __IOM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail Interrupt Enable */ + __IOM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Enable */ + __IOM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Enable */ + __IOM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt + * Enable */ + uint32_t : 1; + } SQCH0IER_b; + }; + __IM uint32_t RESERVED19[9]; + + union + { + __IOM uint32_t SQCH1SET0R; /*!< (@ 0x00000600) Sequence Channel 1 Set 0 Register */ + + struct + { + __OM uint32_t START : 1; /*!< [0..0] Sequence Operation Start */ + uint32_t : 31; + } SQCH1SET0R_b; + }; + __IM uint32_t RESERVED20[3]; + + union + { + __IM uint32_t SQCH1SR; /*!< (@ 0x00000610) Sequence Channel 1 Status Register */ + + struct + { + uint32_t : 2; + __IM uint32_t RUNNING : 1; /*!< [2..2] Sequence Operation Running Status */ + uint32_t : 1; + __IM uint32_t AACTFIN : 1; /*!< [4..4] All Actions Finish Interrupt Flag */ + uint32_t : 3; + __IM uint32_t ADESFIN : 1; /*!< [8..8] All-Descriptors Finish Interrupt Flag */ + uint32_t : 7; + __IM uint32_t DABORT : 1; /*!< [16..16] Descriptor Abort Interrupt Flag */ + uint32_t : 2; + __IM uint32_t SIZEERR : 1; /*!< [19..19] Packet Size Error Interrupt Flag */ + uint32_t : 4; + __IM uint32_t TXIBERR : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Flag */ + uint32_t : 1; + __IM uint32_t RXFERR : 1; /*!< [26..26] Receive Fatal Error Interrupt Flag */ + __IM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail Interrupt Flag */ + __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Flag */ + __IM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Flag */ + __IM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt + * Flag */ + uint32_t : 1; + } SQCH1SR_b; + }; + + union + { + __IOM uint32_t SQCH1SCR; /*!< (@ 0x00000614) Sequence Channel 1 Status Clear Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t AACTFIN : 1; /*!< [4..4] All Actions Finish Interrupt Flag Clear */ + uint32_t : 3; + __IOM uint32_t ADESFIN : 1; /*!< [8..8] All-Descriptors Finish Interrupt Flag Clear */ + uint32_t : 7; + __IOM uint32_t DABORT : 1; /*!< [16..16] Descriptor Abort Interrupt Flag Clear */ + uint32_t : 2; + __IOM uint32_t SIZEERR : 1; /*!< [19..19] Packet Size Error Interrupt Flag Clear */ + uint32_t : 4; + __IOM uint32_t TXIBERR : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t RXFERR : 1; /*!< [26..26] Receive Fatal Error Interrupt Flag Clear */ + __IOM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail Interrupt Flag Clear */ + __IOM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Flag Clear */ + __IOM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Flag Clear */ + __IOM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt + * Flag Clear */ + uint32_t : 1; + } SQCH1SCR_b; + }; + + union + { + __IOM uint32_t SQCH1IER; /*!< (@ 0x00000618) Sequence Channel 1 Interrupt Enable Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t AACTFIN : 1; /*!< [4..4] All Actions Finish Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t ADESFIN : 1; /*!< [8..8] All-Descriptors Finish Interrupt Enable */ + uint32_t : 7; + __IOM uint32_t DABORT : 1; /*!< [16..16] Descriptor Abort Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SIZEERR : 1; /*!< [19..19] Packet Size Error Interrupt Enable */ + uint32_t : 4; + __IOM uint32_t TXIBERR : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t RXFERR : 1; /*!< [26..26] Receive Fatal Error Interrupt Enable */ + __IOM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail Interrupt Enable */ + __IOM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Enable */ + __IOM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Enable */ + __IOM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt + * Enable */ + uint32_t : 1; + } SQCH1IER_b; + }; + __IM uint32_t RESERVED21[89]; + + union + { + union + { + __IOM uint32_t SQCH0DSC0AR; /*!< (@ 0x00000780) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC0AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC0AR_L; /*!< (@ 0x00000780) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC0AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC0AR_LL; /*!< (@ 0x00000780) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC0AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC0AR_LH; /*!< (@ 0x00000781) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC0AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC0AR_H; /*!< (@ 0x00000782) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC0AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC0AR_HL; /*!< (@ 0x00000782) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC0AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC0AR_HH; /*!< (@ 0x00000783) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC0AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC0BR; /*!< (@ 0x00000784) Sequence Channel 0 Descriptor-0 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC0BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC0CR; /*!< (@ 0x00000788) Sequence Channel 0 Descriptor-0 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC0CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC0CR_L; /*!< (@ 0x00000788) Sequence Channel 0 Descriptor-0 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC0CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC0CR_LL; /*!< (@ 0x00000788) Sequence Channel 0 Descriptor-0 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC0CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC0CR_H; /*!< (@ 0x0000078A) Sequence Channel 0 Descriptor-0 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC0CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC0CR_HL; /*!< (@ 0x0000078A) Sequence Channel 0 Descriptor-0 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC0CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC0CR_HH; /*!< (@ 0x0000078B) Sequence Channel 0 Descriptor-0 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC0CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC0DR; /*!< (@ 0x0000078C) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC0DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC0DR_L; /*!< (@ 0x0000078C) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC0DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC0DR_LL; /*!< (@ 0x0000078C) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC0DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC0DR_LH; /*!< (@ 0x0000078D) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC0DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC0DR_H; /*!< (@ 0x0000078E) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC0DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC0DR_HL; /*!< (@ 0x0000078E) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC0DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC0DR_HH; /*!< (@ 0x0000078F) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC0DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC1AR; /*!< (@ 0x00000790) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC1AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC1AR_L; /*!< (@ 0x00000790) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC1AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC1AR_LL; /*!< (@ 0x00000790) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC1AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC1AR_LH; /*!< (@ 0x00000791) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC1AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC1AR_H; /*!< (@ 0x00000792) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC1AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC1AR_HL; /*!< (@ 0x00000792) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC1AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC1AR_HH; /*!< (@ 0x00000793) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC1AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC1BR; /*!< (@ 0x00000794) Sequence Channel 0 Descriptor-1 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC1BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC1CR; /*!< (@ 0x00000798) Sequence Channel 0 Descriptor-1 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC1CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC1CR_L; /*!< (@ 0x00000798) Sequence Channel 0 Descriptor-1 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC1CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC1CR_LL; /*!< (@ 0x00000798) Sequence Channel 0 Descriptor-1 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC1CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC1CR_H; /*!< (@ 0x0000079A) Sequence Channel 0 Descriptor-1 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC1CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC1CR_HL; /*!< (@ 0x0000079A) Sequence Channel 0 Descriptor-1 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC1CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC1CR_HH; /*!< (@ 0x0000079B) Sequence Channel 0 Descriptor-1 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC1CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC1DR; /*!< (@ 0x0000079C) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC1DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC1DR_L; /*!< (@ 0x0000079C) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC1DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC1DR_LL; /*!< (@ 0x0000079C) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC1DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC1DR_LH; /*!< (@ 0x0000079D) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC1DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC1DR_H; /*!< (@ 0x0000079E) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC1DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC1DR_HL; /*!< (@ 0x0000079E) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC1DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC1DR_HH; /*!< (@ 0x0000079F) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC1DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC2AR; /*!< (@ 0x000007A0) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC2AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC2AR_L; /*!< (@ 0x000007A0) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC2AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC2AR_LL; /*!< (@ 0x000007A0) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC2AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC2AR_LH; /*!< (@ 0x000007A1) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC2AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC2AR_H; /*!< (@ 0x000007A2) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC2AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC2AR_HL; /*!< (@ 0x000007A2) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC2AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC2AR_HH; /*!< (@ 0x000007A3) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC2AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC2BR; /*!< (@ 0x000007A4) Sequence Channel 0 Descriptor-2 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC2BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC2CR; /*!< (@ 0x000007A8) Sequence Channel 0 Descriptor-2 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC2CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC2CR_L; /*!< (@ 0x000007A8) Sequence Channel 0 Descriptor-2 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC2CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC2CR_LL; /*!< (@ 0x000007A8) Sequence Channel 0 Descriptor-2 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC2CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC2CR_H; /*!< (@ 0x000007AA) Sequence Channel 0 Descriptor-2 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC2CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC2CR_HL; /*!< (@ 0x000007AA) Sequence Channel 0 Descriptor-2 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC2CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC2CR_HH; /*!< (@ 0x000007AB) Sequence Channel 0 Descriptor-2 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC2CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC2DR; /*!< (@ 0x000007AC) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC2DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC2DR_L; /*!< (@ 0x000007AC) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC2DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC2DR_LL; /*!< (@ 0x000007AC) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC2DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC2DR_LH; /*!< (@ 0x000007AD) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC2DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC2DR_H; /*!< (@ 0x000007AE) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC2DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC2DR_HL; /*!< (@ 0x000007AE) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC2DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC2DR_HH; /*!< (@ 0x000007AF) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC2DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC3AR; /*!< (@ 0x000007B0) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC3AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC3AR_L; /*!< (@ 0x000007B0) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC3AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC3AR_LL; /*!< (@ 0x000007B0) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC3AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC3AR_LH; /*!< (@ 0x000007B1) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC3AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC3AR_H; /*!< (@ 0x000007B2) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC3AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC3AR_HL; /*!< (@ 0x000007B2) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC3AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC3AR_HH; /*!< (@ 0x000007B3) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC3AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC3BR; /*!< (@ 0x000007B4) Sequence Channel 0 Descriptor-3 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC3BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC3CR; /*!< (@ 0x000007B8) Sequence Channel 0 Descriptor-3 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC3CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC3CR_L; /*!< (@ 0x000007B8) Sequence Channel 0 Descriptor-3 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC3CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC3CR_LL; /*!< (@ 0x000007B8) Sequence Channel 0 Descriptor-3 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC3CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC3CR_H; /*!< (@ 0x000007BA) Sequence Channel 0 Descriptor-3 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC3CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC3CR_HL; /*!< (@ 0x000007BA) Sequence Channel 0 Descriptor-3 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC3CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC3CR_HH; /*!< (@ 0x000007BB) Sequence Channel 0 Descriptor-3 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC3CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC3DR; /*!< (@ 0x000007BC) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC3DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC3DR_L; /*!< (@ 0x000007BC) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC3DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC3DR_LL; /*!< (@ 0x000007BC) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC3DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC3DR_LH; /*!< (@ 0x000007BD) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC3DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC3DR_H; /*!< (@ 0x000007BE) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC3DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC3DR_HL; /*!< (@ 0x000007BE) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC3DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC3DR_HH; /*!< (@ 0x000007BF) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC3DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC4AR; /*!< (@ 0x000007C0) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC4AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC4AR_L; /*!< (@ 0x000007C0) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC4AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC4AR_LL; /*!< (@ 0x000007C0) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC4AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC4AR_LH; /*!< (@ 0x000007C1) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC4AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC4AR_H; /*!< (@ 0x000007C2) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC4AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC4AR_HL; /*!< (@ 0x000007C2) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC4AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC4AR_HH; /*!< (@ 0x000007C3) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC4AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC4BR; /*!< (@ 0x000007C4) Sequence Channel 0 Descriptor-4 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC4BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC4CR; /*!< (@ 0x000007C8) Sequence Channel 0 Descriptor-4 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC4CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC4CR_L; /*!< (@ 0x000007C8) Sequence Channel 0 Descriptor-4 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC4CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC4CR_LL; /*!< (@ 0x000007C8) Sequence Channel 0 Descriptor-4 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC4CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC4CR_H; /*!< (@ 0x000007CA) Sequence Channel 0 Descriptor-4 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC4CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC4CR_HL; /*!< (@ 0x000007CA) Sequence Channel 0 Descriptor-4 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC4CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC4CR_HH; /*!< (@ 0x000007CB) Sequence Channel 0 Descriptor-4 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC4CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC4DR; /*!< (@ 0x000007CC) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC4DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC4DR_L; /*!< (@ 0x000007CC) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC4DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC4DR_LL; /*!< (@ 0x000007CC) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC4DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC4DR_LH; /*!< (@ 0x000007CD) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC4DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC4DR_H; /*!< (@ 0x000007CE) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC4DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC4DR_HL; /*!< (@ 0x000007CE) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC4DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC4DR_HH; /*!< (@ 0x000007CF) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC4DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC5AR; /*!< (@ 0x000007D0) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC5AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC5AR_L; /*!< (@ 0x000007D0) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC5AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC5AR_LL; /*!< (@ 0x000007D0) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC5AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC5AR_LH; /*!< (@ 0x000007D1) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC5AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC5AR_H; /*!< (@ 0x000007D2) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC5AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC5AR_HL; /*!< (@ 0x000007D2) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC5AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC5AR_HH; /*!< (@ 0x000007D3) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC5AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC5BR; /*!< (@ 0x000007D4) Sequence Channel 0 Descriptor-5 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC5BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC5CR; /*!< (@ 0x000007D8) Sequence Channel 0 Descriptor-5 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC5CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC5CR_L; /*!< (@ 0x000007D8) Sequence Channel 0 Descriptor-5 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC5CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC5CR_LL; /*!< (@ 0x000007D8) Sequence Channel 0 Descriptor-5 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC5CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC5CR_H; /*!< (@ 0x000007DA) Sequence Channel 0 Descriptor-5 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC5CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC5CR_HL; /*!< (@ 0x000007DA) Sequence Channel 0 Descriptor-5 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC5CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC5CR_HH; /*!< (@ 0x000007DB) Sequence Channel 0 Descriptor-5 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC5CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC5DR; /*!< (@ 0x000007DC) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC5DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC5DR_L; /*!< (@ 0x000007DC) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC5DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC5DR_LL; /*!< (@ 0x000007DC) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC5DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC5DR_LH; /*!< (@ 0x000007DD) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC5DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC5DR_H; /*!< (@ 0x000007DE) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC5DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC5DR_HL; /*!< (@ 0x000007DE) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC5DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC5DR_HH; /*!< (@ 0x000007DF) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC5DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC6AR; /*!< (@ 0x000007E0) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC6AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC6AR_L; /*!< (@ 0x000007E0) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC6AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC6AR_LL; /*!< (@ 0x000007E0) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC6AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC6AR_LH; /*!< (@ 0x000007E1) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC6AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC6AR_H; /*!< (@ 0x000007E2) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC6AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC6AR_HL; /*!< (@ 0x000007E2) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC6AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC6AR_HH; /*!< (@ 0x000007E3) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC6AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC6BR; /*!< (@ 0x000007E4) Sequence Channel 0 Descriptor-6 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC6BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC6CR; /*!< (@ 0x000007E8) Sequence Channel 0 Descriptor-6 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC6CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC6CR_L; /*!< (@ 0x000007E8) Sequence Channel 0 Descriptor-6 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC6CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC6CR_LL; /*!< (@ 0x000007E8) Sequence Channel 0 Descriptor-6 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC6CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC6CR_H; /*!< (@ 0x000007EA) Sequence Channel 0 Descriptor-6 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC6CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC6CR_HL; /*!< (@ 0x000007EA) Sequence Channel 0 Descriptor-6 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC6CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC6CR_HH; /*!< (@ 0x000007EB) Sequence Channel 0 Descriptor-6 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC6CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC6DR; /*!< (@ 0x000007EC) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC6DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC6DR_L; /*!< (@ 0x000007EC) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC6DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC6DR_LL; /*!< (@ 0x000007EC) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC6DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC6DR_LH; /*!< (@ 0x000007ED) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC6DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC6DR_H; /*!< (@ 0x000007EE) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC6DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC6DR_HL; /*!< (@ 0x000007EE) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC6DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC6DR_HH; /*!< (@ 0x000007EF) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC6DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC7AR; /*!< (@ 0x000007F0) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC7AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC7AR_L; /*!< (@ 0x000007F0) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC7AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC7AR_LL; /*!< (@ 0x000007F0) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC7AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC7AR_LH; /*!< (@ 0x000007F1) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC7AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC7AR_H; /*!< (@ 0x000007F2) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC7AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC7AR_HL; /*!< (@ 0x000007F2) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC7AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC7AR_HH; /*!< (@ 0x000007F3) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC7AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC7BR; /*!< (@ 0x000007F4) Sequence Channel 0 Descriptor-7 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC7BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC7CR; /*!< (@ 0x000007F8) Sequence Channel 0 Descriptor-7 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC7CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC7CR_L; /*!< (@ 0x000007F8) Sequence Channel 0 Descriptor-7 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC7CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC7CR_LL; /*!< (@ 0x000007F8) Sequence Channel 0 Descriptor-7 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC7CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC7CR_H; /*!< (@ 0x000007FA) Sequence Channel 0 Descriptor-7 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC7CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC7CR_HL; /*!< (@ 0x000007FA) Sequence Channel 0 Descriptor-7 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC7CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC7CR_HH; /*!< (@ 0x000007FB) Sequence Channel 0 Descriptor-7 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC7CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC7DR; /*!< (@ 0x000007FC) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC7DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC7DR_L; /*!< (@ 0x000007FC) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC7DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC7DR_LL; /*!< (@ 0x000007FC) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC7DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC7DR_LH; /*!< (@ 0x000007FD) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC7DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC7DR_H; /*!< (@ 0x000007FE) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC7DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC7DR_HL; /*!< (@ 0x000007FE) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC7DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC7DR_HH; /*!< (@ 0x000007FF) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC7DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC0AR; /*!< (@ 0x00000800) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC0AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC0AR_L; /*!< (@ 0x00000800) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC0AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC0AR_LL; /*!< (@ 0x00000800) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC0AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC0AR_LH; /*!< (@ 0x00000801) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC0AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC0AR_H; /*!< (@ 0x00000802) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC0AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC0AR_HL; /*!< (@ 0x00000802) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC0AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC0AR_HH; /*!< (@ 0x00000803) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC0AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC0BR; /*!< (@ 0x00000804) Sequence Channel 1 Descriptor-0 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC0BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC0CR; /*!< (@ 0x00000808) Sequence Channel 1 Descriptor-0 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC0CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC0CR_L; /*!< (@ 0x00000808) Sequence Channel 1 Descriptor-0 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC0CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC0CR_LL; /*!< (@ 0x00000808) Sequence Channel 1 Descriptor-0 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC0CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC0CR_H; /*!< (@ 0x0000080A) Sequence Channel 1 Descriptor-0 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC0CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC0CR_HL; /*!< (@ 0x0000080A) Sequence Channel 1 Descriptor-0 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC0CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC0CR_HH; /*!< (@ 0x0000080B) Sequence Channel 1 Descriptor-0 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC0CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC0DR; /*!< (@ 0x0000080C) Sequence Channel 1 Descriptor-0 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC0DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC0DR_L; /*!< (@ 0x0000080C) Sequence Channel 1 Descriptor-0 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC0DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC0DR_LL; /*!< (@ 0x0000080C) Sequence Channel 1 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC0DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC0DR_LH; /*!< (@ 0x0000080D) Sequence Channel 1 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC0DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC0DR_HL; /*!< (@ 0x0000080E) Sequence Channel 1 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC0DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC0DR_HH; /*!< (@ 0x0000080F) Sequence Channel 1 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC0DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC1AR; /*!< (@ 0x00000810) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC1AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC1AR_L; /*!< (@ 0x00000810) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC1AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC1AR_LL; /*!< (@ 0x00000810) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC1AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC1AR_LH; /*!< (@ 0x00000811) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC1AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC1AR_H; /*!< (@ 0x00000812) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC1AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC1AR_HL; /*!< (@ 0x00000812) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC1AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC1AR_HH; /*!< (@ 0x00000813) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC1AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC1BR; /*!< (@ 0x00000814) Sequence Channel 1 Descriptor-1 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC1BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC1CR; /*!< (@ 0x00000818) Sequence Channel 1 Descriptor-1 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC1CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC1CR_L; /*!< (@ 0x00000818) Sequence Channel 1 Descriptor-1 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC1CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC1CR_LL; /*!< (@ 0x00000818) Sequence Channel 1 Descriptor-1 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC1CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC1CR_H; /*!< (@ 0x0000081A) Sequence Channel 1 Descriptor-1 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC1CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC1CR_HL; /*!< (@ 0x0000081A) Sequence Channel 1 Descriptor-1 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC1CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC1CR_HH; /*!< (@ 0x0000081B) Sequence Channel 1 Descriptor-1 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC1CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC1DR; /*!< (@ 0x0000081C) Sequence Channel 1 Descriptor-1 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC1DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC1DR_L; /*!< (@ 0x0000081C) Sequence Channel 1 Descriptor-1 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC1DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC1DR_LL; /*!< (@ 0x0000081C) Sequence Channel 1 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC1DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC1DR_LH; /*!< (@ 0x0000081D) Sequence Channel 1 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC1DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC1DR_HL; /*!< (@ 0x0000081E) Sequence Channel 1 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC1DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC1DR_HH; /*!< (@ 0x0000081F) Sequence Channel 1 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC1DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC2AR; /*!< (@ 0x00000820) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC2AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC2AR_L; /*!< (@ 0x00000820) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC2AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC2AR_LL; /*!< (@ 0x00000820) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC2AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC2AR_LH; /*!< (@ 0x00000821) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC2AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC2AR_H; /*!< (@ 0x00000822) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC2AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC2AR_HL; /*!< (@ 0x00000822) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC2AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC2AR_HH; /*!< (@ 0x00000823) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC2AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC2BR; /*!< (@ 0x00000824) Sequence Channel 1 Descriptor-2 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC2BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC2CR; /*!< (@ 0x00000828) Sequence Channel 1 Descriptor-2 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC2CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC2CR_L; /*!< (@ 0x00000828) Sequence Channel 1 Descriptor-2 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC2CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC2CR_LL; /*!< (@ 0x00000828) Sequence Channel 1 Descriptor-2 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC2CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC2CR_H; /*!< (@ 0x0000082A) Sequence Channel 1 Descriptor-2 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC2CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC2CR_HL; /*!< (@ 0x0000082A) Sequence Channel 1 Descriptor-2 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC2CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC2CR_HH; /*!< (@ 0x0000082B) Sequence Channel 1 Descriptor-2 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC2CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC2DR; /*!< (@ 0x0000082C) Sequence Channel 1 Descriptor-2 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC2DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC2DR_L; /*!< (@ 0x0000082C) Sequence Channel 1 Descriptor-2 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC2DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC2DR_LL; /*!< (@ 0x0000082C) Sequence Channel 1 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC2DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC2DR_LH; /*!< (@ 0x0000082D) Sequence Channel 1 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC2DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC2DR_HL; /*!< (@ 0x0000082E) Sequence Channel 1 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC2DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC2DR_HH; /*!< (@ 0x0000082F) Sequence Channel 1 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC2DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC3AR; /*!< (@ 0x00000830) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC3AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC3AR_L; /*!< (@ 0x00000830) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC3AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC3AR_LL; /*!< (@ 0x00000830) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC3AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC3AR_LH; /*!< (@ 0x00000831) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC3AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC3AR_H; /*!< (@ 0x00000832) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC3AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC3AR_HL; /*!< (@ 0x00000832) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC3AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC3AR_HH; /*!< (@ 0x00000833) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC3AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC3BR; /*!< (@ 0x00000834) Sequence Channel 1 Descriptor-3 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC3BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC3CR; /*!< (@ 0x00000838) Sequence Channel 1 Descriptor-3 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC3CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC3CR_L; /*!< (@ 0x00000838) Sequence Channel 1 Descriptor-3 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC3CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC3CR_LL; /*!< (@ 0x00000838) Sequence Channel 1 Descriptor-3 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC3CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC3CR_H; /*!< (@ 0x0000083A) Sequence Channel 1 Descriptor-3 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC3CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC3CR_HL; /*!< (@ 0x0000083A) Sequence Channel 1 Descriptor-3 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC3CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC3CR_HH; /*!< (@ 0x0000083B) Sequence Channel 1 Descriptor-3 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC3CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC3DR; /*!< (@ 0x0000083C) Sequence Channel 1 Descriptor-3 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC3DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC3DR_L; /*!< (@ 0x0000083C) Sequence Channel 1 Descriptor-3 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC3DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC3DR_LL; /*!< (@ 0x0000083C) Sequence Channel 1 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC3DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC3DR_LH; /*!< (@ 0x0000083D) Sequence Channel 1 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC3DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC3DR_HL; /*!< (@ 0x0000083E) Sequence Channel 1 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC3DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC3DR_HH; /*!< (@ 0x0000083F) Sequence Channel 1 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC3DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC4AR; /*!< (@ 0x00000840) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC4AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC4AR_L; /*!< (@ 0x00000840) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC4AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC4AR_LL; /*!< (@ 0x00000840) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC4AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC4AR_LH; /*!< (@ 0x00000841) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC4AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC4AR_H; /*!< (@ 0x00000842) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC4AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC4AR_HL; /*!< (@ 0x00000842) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC4AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC4AR_HH; /*!< (@ 0x00000843) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC4AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC4BR; /*!< (@ 0x00000844) Sequence Channel 1 Descriptor-4 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC4BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC4CR; /*!< (@ 0x00000848) Sequence Channel 1 Descriptor-4 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC4CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC4CR_L; /*!< (@ 0x00000848) Sequence Channel 1 Descriptor-4 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC4CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC4CR_LL; /*!< (@ 0x00000848) Sequence Channel 1 Descriptor-4 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC4CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC4CR_H; /*!< (@ 0x0000084A) Sequence Channel 1 Descriptor-4 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC4CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC4CR_HL; /*!< (@ 0x0000084A) Sequence Channel 1 Descriptor-4 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC4CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC4CR_HH; /*!< (@ 0x0000084B) Sequence Channel 1 Descriptor-4 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC4CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC4DR; /*!< (@ 0x0000084C) Sequence Channel 1 Descriptor-4 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC4DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC4DR_L; /*!< (@ 0x0000084C) Sequence Channel 1 Descriptor-4 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC4DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC4DR_LL; /*!< (@ 0x0000084C) Sequence Channel 1 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC4DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC4DR_LH; /*!< (@ 0x0000084D) Sequence Channel 1 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC4DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC4DR_HL; /*!< (@ 0x0000084E) Sequence Channel 1 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC4DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC4DR_HH; /*!< (@ 0x0000084F) Sequence Channel 1 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC4DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC5AR; /*!< (@ 0x00000850) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC5AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC5AR_L; /*!< (@ 0x00000850) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC5AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC5AR_LL; /*!< (@ 0x00000850) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC5AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC5AR_LH; /*!< (@ 0x00000851) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC5AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC5AR_H; /*!< (@ 0x00000852) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC5AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC5AR_HL; /*!< (@ 0x00000852) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC5AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC5AR_HH; /*!< (@ 0x00000853) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC5AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC5BR; /*!< (@ 0x00000854) Sequence Channel 1 Descriptor-5 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC5BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC5CR; /*!< (@ 0x00000858) Sequence Channel 1 Descriptor-5 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC5CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC5CR_L; /*!< (@ 0x00000858) Sequence Channel 1 Descriptor-5 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC5CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC5CR_LL; /*!< (@ 0x00000858) Sequence Channel 1 Descriptor-5 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC5CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC5CR_H; /*!< (@ 0x0000085A) Sequence Channel 1 Descriptor-5 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC5CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC5CR_HL; /*!< (@ 0x0000085A) Sequence Channel 1 Descriptor-5 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC5CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC5CR_HH; /*!< (@ 0x0000085B) Sequence Channel 1 Descriptor-5 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC5CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC5DR; /*!< (@ 0x0000085C) Sequence Channel 1 Descriptor-5 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC5DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC5DR_L; /*!< (@ 0x0000085C) Sequence Channel 1 Descriptor-5 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC5DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC5DR_LL; /*!< (@ 0x0000085C) Sequence Channel 1 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC5DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC5DR_LH; /*!< (@ 0x0000085D) Sequence Channel 1 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC5DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC5DR_HL; /*!< (@ 0x0000085E) Sequence Channel 1 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC5DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC5DR_HH; /*!< (@ 0x0000085F) Sequence Channel 1 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC5DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC6AR; /*!< (@ 0x00000860) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC6AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC6AR_L; /*!< (@ 0x00000860) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC6AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC6AR_LL; /*!< (@ 0x00000860) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC6AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC6AR_LH; /*!< (@ 0x00000861) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC6AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC6AR_H; /*!< (@ 0x00000862) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC6AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC6AR_HL; /*!< (@ 0x00000862) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC6AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC6AR_HH; /*!< (@ 0x00000863) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC6AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC6BR; /*!< (@ 0x00000864) Sequence Channel 1 Descriptor-6 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC6BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC6CR; /*!< (@ 0x00000868) Sequence Channel 1 Descriptor-6 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC6CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC6CR_L; /*!< (@ 0x00000868) Sequence Channel 1 Descriptor-6 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC6CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC6CR_LL; /*!< (@ 0x00000868) Sequence Channel 1 Descriptor-6 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC6CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC6CR_H; /*!< (@ 0x0000086A) Sequence Channel 1 Descriptor-6 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC6CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC6CR_HL; /*!< (@ 0x0000086A) Sequence Channel 1 Descriptor-6 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC6CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC6CR_HH; /*!< (@ 0x0000086B) Sequence Channel 1 Descriptor-6 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC6CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC6DR; /*!< (@ 0x0000086C) Sequence Channel 1 Descriptor-6 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC6DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC6DR_L; /*!< (@ 0x0000086C) Sequence Channel 1 Descriptor-6 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC6DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC6DR_LL; /*!< (@ 0x0000086C) Sequence Channel 1 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC6DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC6DR_LH; /*!< (@ 0x0000086D) Sequence Channel 1 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC6DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC6DR_HL; /*!< (@ 0x0000086E) Sequence Channel 1 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC6DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC6DR_HH; /*!< (@ 0x0000086F) Sequence Channel 1 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC6DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC7AR; /*!< (@ 0x00000870) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC7AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC7AR_L; /*!< (@ 0x00000870) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC7AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC7AR_LL; /*!< (@ 0x00000870) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC7AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC7AR_LH; /*!< (@ 0x00000871) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC7AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC7AR_H; /*!< (@ 0x00000872) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC7AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC7AR_HL; /*!< (@ 0x00000872) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC7AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC7AR_HH; /*!< (@ 0x00000873) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC7AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC7BR; /*!< (@ 0x00000874) Sequence Channel 1 Descriptor-7 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC7BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC7CR; /*!< (@ 0x00000878) Sequence Channel 1 Descriptor-7 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC7CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC7CR_L; /*!< (@ 0x00000878) Sequence Channel 1 Descriptor-7 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC7CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC7CR_LL; /*!< (@ 0x00000878) Sequence Channel 1 Descriptor-7 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC7CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC7CR_H; /*!< (@ 0x0000087A) Sequence Channel 1 Descriptor-7 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC7CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC7CR_HL; /*!< (@ 0x0000087A) Sequence Channel 1 Descriptor-7 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC7CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC7CR_HH; /*!< (@ 0x0000087B) Sequence Channel 1 Descriptor-7 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC7CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC7DR; /*!< (@ 0x0000087C) Sequence Channel 1 Descriptor-7 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC7DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC7DR_L; /*!< (@ 0x0000087C) Sequence Channel 1 Descriptor-7 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC7DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC7DR_LL; /*!< (@ 0x0000087C) Sequence Channel 1 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC7DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC7DR_LH; /*!< (@ 0x0000087D) Sequence Channel 1 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC7DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC7DR_HL; /*!< (@ 0x0000087E) Sequence Channel 1 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC7DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC7DR_HH; /*!< (@ 0x0000087F) Sequence Channel 1 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC7DR_HH_b; + }; + }; + }; +} R_MIPI_DSI_Type; /*!< Size = 2176 (0x880) */ + +/* =========================================================================================================================== */ +/* ================ R_MRMS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief MRAM Control (R_MRMS) + */ + +typedef struct /*!< (@ 0x4013C000) R_MRMS Structure */ +{ + union + { + __IOM uint8_t MRCPFB; /*!< (@ 0x00000000) Code MRAM Pre-Fetch Buffer Enable Register */ + + struct + { + __IOM uint8_t MPFBEN : 1; /*!< [0..0] MRAM Pre-Fetch Buffer enable. */ + uint8_t : 7; + } MRCPFB_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t MRCFREQ; /*!< (@ 0x00000004) Code MRAM Frequency Notifications Register */ + + struct + { + __IOM uint32_t MRCMHZ : 10; /*!< [9..0] Setting the operating frequency in the order of MHz */ + uint32_t : 14; + __IOM uint32_t KEY : 8; /*!< [31..24] Key Code */ + } MRCFREQ_b; + }; + + union + { + __IOM uint32_t MREFREQ; /*!< (@ 0x00000008) Extra MRAM Frequency Notifications Register */ + + struct + { + __IOM uint32_t MREMHZ : 8; /*!< [7..0] Setting the operating frequency in the order of MHz */ + uint32_t : 16; + __IOM uint32_t KEY : 8; /*!< [31..24] Key Code */ + } MREFREQ_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint16_t MRCDECC; /*!< (@ 0x00000010) Code MRAM ECC Decoder Control Register */ + + struct + { + __IOM uint16_t DECDISC : 1; /*!< [0..0] MRC ECC Decoder disable */ + __IOM uint16_t ECCSELC : 1; /*!< [1..1] MRC ECC Data select */ + uint16_t : 6; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MRCDECC_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t MRCRAEINT; /*!< (@ 0x00000014) Code MRAM Read Access Error Interrupt Enable + * Register */ + + struct + { + __IOM uint8_t INTENBDC : 1; /*!< [0..0] MRC DEC error interrupt enable. */ + __IOM uint8_t INTENBTC : 1; /*!< [1..1] MRC TED error interrupt enable. */ + uint8_t : 6; + } MRCRAEINT_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + + union + { + __IOM uint8_t MRCRAES; /*!< (@ 0x00000018) Code MRAM Read Access Error Status Register */ + + struct + { + __IOM uint8_t DECERRC : 1; /*!< [0..0] MRC DEC error detected. */ + __IOM uint8_t TEDERRC : 1; /*!< [1..1] MRC TED error detected. */ + uint8_t : 6; + } MRCRAES_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IM uint32_t MRCRTEA; /*!< (@ 0x0000001C) Code MRAM TED Error Address Register */ + + struct + { + uint32_t : 5; + __IM uint32_t MRCRTEA : 27; /*!< [31..5] MRC read access TED error Address. */ + } MRCRTEA_b; + }; + + union + { + __IM uint32_t MRCRDEA; /*!< (@ 0x00000020) Code MRAM DEC Error Address Register */ + + struct + { + uint32_t : 5; + __IM uint32_t MRCRDEA : 27; /*!< [31..5] MRC read access DEC error Address. */ + } MRCRDEA_b; + }; + __IM uint32_t RESERVED8[4]; + + union + { + __IOM uint8_t MRERAINT; /*!< (@ 0x00000034) Extra MRAM Read Access Error Interrupt Enable + * Register */ + + struct + { + __IOM uint8_t INTENBDE : 1; /*!< [0..0] MRE DEC error interrupt enable. */ + __IOM uint8_t INTENBTE : 1; /*!< [1..1] MRE TED error interrupt enable. */ + uint8_t : 6; + } MRERAINT_b; + }; + __IM uint8_t RESERVED9; + __IM uint16_t RESERVED10; + + union + { + __IOM uint8_t MRERAES; /*!< (@ 0x00000038) Extra MRAM Read Access Error Status Register */ + + struct + { + __IOM uint8_t DECERRE : 1; /*!< [0..0] MRE DEC error detected. */ + __IOM uint8_t TEDERRE : 1; /*!< [1..1] MRE TED error detected. */ + uint8_t : 6; + } MRERAES_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IM uint32_t MRERTEA; /*!< (@ 0x0000003C) Extra MRAM TED Error Address Register */ + + struct + { + uint32_t : 4; + __IM uint32_t MRERTEA : 28; /*!< [31..4] MRE read access TED error Address. */ + } MRERTEA_b; + }; + + union + { + __IM uint32_t MRERDEA; /*!< (@ 0x00000040) Extra MRAM DEC Error Address Register */ + + struct + { + uint32_t : 4; + __IM uint32_t MRERDEA : 28; /*!< [31..4] MRE read access DEC error Address. */ + } MRERDEA_b; + }; + __IM uint32_t RESERVED13[47]; + + union + { + __IOM uint16_t MSAR; /*!< (@ 0x00000100) MRAM Security Attribution Register */ + + struct + { + __IOM uint16_t MREECCSA : 1; /*!< [0..0] Extra MRAM ECC Register Security Attribution */ + __IOM uint16_t MREFREQSA : 1; /*!< [1..1] MREFREQ register Security Attribution */ + __IOM uint16_t MRCECCSA : 1; /*!< [2..2] Code MRAM ECC Register Security Attribution */ + __IOM uint16_t MRCFREQSA : 1; /*!< [3..3] MRCFREQ register Security Attribution */ + __IOM uint16_t MPFBENSA : 1; /*!< [4..4] MRCPFB register Security Attribution */ + uint16_t : 4; + __IOM uint16_t MACICMISA : 1; /*!< [9..9] MACI Command Issuing Security Attribution */ + __IOM uint16_t MACICMRSA : 1; /*!< [10..10] MACI Command Registers Security Attribution */ + __IOM uint16_t MACITRSA : 1; /*!< [11..11] MACI Transfer Security Attribution */ + uint16_t : 1; + __IOM uint16_t MRCPSA : 1; /*!< [13..13] Code MRAM Program Register Security Attribution */ + __IOM uint16_t MREPSEQSA : 1; /*!< [14..14] EPSEQ Area Register Security Attribution */ + __IOM uint16_t MRCPSEQSA : 1; /*!< [15..15] CPSEQ Area Register Security Attribution */ + } MSAR_b; + }; + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[191]; + + union + { + __IM uint8_t MREZS; /*!< (@ 0x00000400) Extra MRAM Zeroization Status Register */ + + struct + { + __IM uint8_t WHUKZF : 1; /*!< [0..0] W-HUK Zero Flag Status. */ + __IM uint8_t WHUKEXE : 1; /*!< [1..1] W-HUK Zeroization Executing Status */ + uint8_t : 6; + } MREZS_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint16_t MREZC; /*!< (@ 0x00000404) Extra MRAM Zeroization Control Register */ + + struct + { + __IOM uint16_t WHUKZE : 3; /*!< [2..0] W-KUK zeroization execute. */ + uint16_t : 5; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MREZC_b; + }; + __IM uint16_t RESERVED18; + __IM uint32_t RESERVED19[1794]; + + union + { + __IOM uint8_t MASTAT; /*!< (@ 0x00002010) Extra MRAM Access Status Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t MREAE : 1; /*!< [3..3] Extra MRAM Access Error */ + __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ + uint8_t : 3; + } MASTAT_b; + }; + __IM uint8_t RESERVED20; + __IM uint16_t RESERVED21; + + union + { + __IOM uint8_t MPAEINT; /*!< (@ 0x00002014) Extra MRAM Access Error Interrupt Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t MREAEIE : 1; /*!< [3..3] MRE Access Error Interrupt Enable */ + __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ + uint8_t : 3; + } MPAEINT_b; + }; + __IM uint8_t RESERVED22; + __IM uint16_t RESERVED23; + + union + { + __IOM uint8_t MRDYIE; /*!< (@ 0x00002018) Extra MRAM Ready Interrupt Enable Register */ + + struct + { + __IOM uint8_t MRDYIE : 1; /*!< [0..0] MRDY Interrupt Enable */ + uint8_t : 7; + } MRDYIE_b; + }; + __IM uint8_t RESERVED24; + __IM uint16_t RESERVED25; + __IM uint32_t RESERVED26[5]; + + union + { + __IOM uint32_t MSADDR; /*!< (@ 0x00002030) MACI Command Start Address Register */ + + struct + { + __IOM uint32_t MSADDR : 32; /*!< [31..0] Start Address for MACI Command Processing */ + } MSADDR_b; + }; + __IM uint32_t RESERVED27[5]; + + union + { + __IOM uint8_t MCNTSELR; /*!< (@ 0x00002048) MRAM Counter Select Register */ + + struct + { + __IOM uint8_t CNTSEL : 3; /*!< [2..0] Counter Select */ + uint8_t : 5; + } MCNTSELR_b; + }; + __IM uint8_t RESERVED28; + __IM uint16_t RESERVED29; + + union + { + __IM uint32_t MCNTDTR0; /*!< (@ 0x0000204C) MRAM Counter Data Register 0 */ + + struct + { + __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data */ + } MCNTDTR0_b; + }; + + union + { + __IM uint32_t MCNTDTR1; /*!< (@ 0x00002050) MRAM Counter Data Register 1 */ + + struct + { + __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data */ + } MCNTDTR1_b; + }; + __IM uint32_t RESERVED30[3]; + + union + { + __IOM uint16_t MCTRCNTR; /*!< (@ 0x00002060) MRAM Configuration Update Transfer Control Register */ + + struct + { + __IOM uint16_t TRTRG : 1; /*!< [0..0] Transfer Start Trigger */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MCTRCNTR_b; + }; + __IM uint16_t RESERVED31; + + union + { + __IOM uint8_t MCTRLSR; /*!< (@ 0x00002064) MRAM Configuration Update Transfer List Select + * Register */ + + struct + { + __IOM uint8_t TRLIST : 3; /*!< [2..0] Configuration Update Transfer List */ + uint8_t : 5; + } MCTRLSR_b; + }; + __IM uint8_t RESERVED32; + __IM uint16_t RESERVED33; + __IM uint32_t RESERVED34; + + union + { + __IM uint8_t MCTRSTATR; /*!< (@ 0x0000206C) MRAM Configuration Update Transfer Status Register */ + + struct + { + __IM uint8_t TRBUSY : 1; /*!< [0..0] Transfer Busy Status */ + uint8_t : 1; + __IM uint8_t TRMD : 1; /*!< [2..2] Transfer Mode Setting Status */ + uint8_t : 5; + } MCTRSTATR_b; + }; + __IM uint8_t RESERVED35; + __IM uint16_t RESERVED36; + __IM uint32_t RESERVED37[4]; + + union + { + __IM uint32_t MSTATR; /*!< (@ 0x00002080) Extra MRAM Status Register */ + + struct + { + uint32_t : 5; + __IM uint32_t CFGSETERR : 1; /*!< [5..5] Configuration Set Error Flag */ + uint32_t : 6; + __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ + uint32_t : 1; + __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Error */ + __IM uint32_t MRDY : 1; /*!< [15..15] MRE Ready */ + uint32_t : 3; + __IM uint32_t TZFERR : 1; /*!< [19..19] TrustZone Filter Error */ + __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ + __IM uint32_t SECERR : 1; /*!< [21..21] Security Error */ + uint32_t : 1; + __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ + uint32_t : 8; + } MSTATR_b; + }; + + union + { + __IOM uint16_t MENTRYR; /*!< (@ 0x00002084) Extra MRAM Program Mode Entry Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t MENTRY : 1; /*!< [7..7] Extra MRAM Mode Entry */ + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MENTRYR_b; + }; + __IM uint16_t RESERVED38; + __IM uint32_t RESERVED39; + + union + { + __IOM uint16_t MSUINITR; /*!< (@ 0x0000208C) Extra MRAM Sequencer Set-Up Initialization Register */ + + struct + { + __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MSUINITR_b; + }; + __IM uint16_t RESERVED40; + __IM uint32_t RESERVED41[4]; + + union + { + __IM uint16_t MCMDR; /*!< (@ 0x000020A0) MACI Command Register */ + + struct + { + __IM uint16_t PCMDR : 8; /*!< [7..0] Pre-command Flag */ + __IM uint16_t CMDR : 8; /*!< [15..8] Command Flag */ + } MCMDR_b; + }; + __IM uint16_t RESERVED42; + __IM uint32_t RESERVED43[14]; + + union + { + __IM uint32_t MSUASMON; /*!< (@ 0x000020DC) MRAM Start-Up Area Select Monitor Register */ + + struct + { + uint32_t : 15; + __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programing to set the Start-Up Area + * Select setting */ + uint32_t : 13; + __IM uint32_t BTSIZE : 2; /*!< [30..29] Size of Start-Up area select for Boot Swap */ + __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ + } MSUASMON_b; + }; + __IM uint32_t RESERVED44[2]; + + union + { + __IOM uint16_t MSUACR; /*!< (@ 0x000020E8) MRAM Start-Up Area Control Register */ + + struct + { + __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select */ + uint16_t : 6; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MSUACR_b; + }; + __IM uint16_t RESERVED45; + __IM uint32_t RESERVED46[453]; + + union + { + __IOM uint8_t MRPSC; /*!< (@ 0x00002800) MRAM Program Speed Control Register */ + + struct + { + __IOM uint8_t MHSPEN : 1; /*!< [0..0] MRAM high speed program mode enable. */ + uint8_t : 7; + } MRPSC_b; + }; + __IM uint8_t RESERVED47; + __IM uint16_t RESERVED48; + __IM uint32_t RESERVED49[511]; + + union + { + __IOM uint16_t MRCPC0; /*!< (@ 0x00003000) Code MRAM Program Control Register */ + + struct + { + __IOM uint16_t MRCPNEN : 1; /*!< [0..0] Code MRAM Program Enable for Non-secure */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MRCPC0_b; + }; + __IM uint16_t RESERVED50; + + union + { + __IOM uint16_t MRCPC1; /*!< (@ 0x00003004) Code MRAM Program Control for Secure Register */ + + struct + { + __IOM uint16_t MRCPSEN : 1; /*!< [0..0] Code MRAM Program Enable for Secure */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MRCPC1_b; + }; + __IM uint16_t RESERVED51; + + union + { + __IOM uint16_t MRCBPROT0; /*!< (@ 0x00003008) Code MRAM Block Protection Register */ + + struct + { + __IOM uint16_t BPCN0 : 1; /*!< [0..0] Code MRAM Block Protection Cancel for Non-secure */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MRCBPROT0_b; + }; + __IM uint16_t RESERVED52; + + union + { + __IOM uint16_t MRCBPROT1; /*!< (@ 0x0000300C) Code MRAM Block Protection for Secure Register */ + + struct + { + __IOM uint16_t BPCN1 : 1; /*!< [0..0] Code MRAM Block Protection Cancel for Secure */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MRCBPROT1_b; + }; + __IM uint16_t RESERVED53; + + union + { + __IOM uint8_t MRCPS; /*!< (@ 0x00003010) Code MRAM Program Status Register */ + + struct + { + __IOM uint8_t PRGERRC : 1; /*!< [0..0] Programming Error */ + __IOM uint8_t ECCERRC : 1; /*!< [1..1] ECC Error */ + uint8_t : 3; + __IM uint8_t ABUFEMP : 1; /*!< [5..5] Address Buffer Empty */ + __IM uint8_t ABUFFULL : 1; /*!< [6..6] Address Buffer Full */ + __IM uint8_t PRGBSYC : 1; /*!< [7..7] Code MRAM Program Busy */ + } MRCPS_b; + }; + __IM uint8_t RESERVED54; + __IM uint16_t RESERVED55; + + union + { + __IOM uint8_t MRCPAEINT; /*!< (@ 0x00003014) Code MRAM Program Access Error Interrupt Enable + * Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t MRCAEIE : 1; /*!< [7..7] Code MRAM Program Access Error Interrupt Enable */ + } MRCPAEINT_b; + }; + __IM uint8_t RESERVED56; + __IM uint16_t RESERVED57; + + union + { + __IM uint32_t MRCPEA; /*!< (@ 0x00003018) Code MRAM Program Error Address Register */ + + struct + { + uint32_t : 5; + __IM uint32_t MCPEA : 27; /*!< [31..5] Code MRAM Program Error Address */ + } MRCPEA_b; + }; + __IM uint32_t RESERVED58[5]; + + union + { + __IOM uint16_t MRCFLR; /*!< (@ 0x00003030) Code MRAM Flush Register */ + + struct + { + __IOM uint16_t MRCFL : 1; /*!< [0..0] Flush Write Data Buffer for code MRAM */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MRCFLR_b; + }; + __IM uint16_t RESERVED59; + __IM uint32_t RESERVED60[500]; + + union + { + __IOM uint16_t MRCEECC; /*!< (@ 0x00003804) Code MRAM ECC Encoder Control Register */ + + struct + { + __IOM uint16_t ECCBYPC : 1; /*!< [0..0] Code MRAM ECC encoder outputs bypass enable */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MRCEECC_b; + }; + __IM uint16_t RESERVED61; +} R_MRMS_Type; /*!< Size = 14344 (0x3808) */ + +/* =========================================================================================================================== */ +/* ================ R_NPU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Neural Processing Unit (R_NPU) + */ + +typedef struct /*!< (@ 0x40140000) R_NPU Structure */ +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) ID register */ + + struct + { + __IM uint32_t version_status : 4; /*!< [3..0] This is the version of the product */ + __IM uint32_t version_minor : 4; /*!< [7..4] This is the n for the P-part of an RnPn release number */ + __IM uint32_t version_major : 4; /*!< [11..8] This is the n for the R-part of an RnPn release number */ + __IM uint32_t product_major : 4; /*!< [15..12] This is the X-part of the ML00X product number */ + __IM uint32_t arch_patch_rev : 4; /*!< [19..16] This is the patch number of the architecture version + * a.b */ + __IM uint32_t arch_minor_rev : 8; /*!< [27..20] This is the minor architecture version number, b in + * the architecture version a.b */ + __IM uint32_t arch_major_rev : 4; /*!< [31..28] This is the major architecture version number, a in + * the architecture version a.b */ + } ID_b; + }; + + union + { + __IM uint32_t STATUS; /*!< (@ 0x00000004) Register describes the current operating status + * of the NPU */ + + struct + { + __IM uint32_t state : 1; /*!< [0..0] NPU state; 0 = Stopped, 1 = Running */ + __IM uint32_t irq_raised : 1; /*!< [1..1] Raw IRQ status: 0 = IRQ not raised, 1 = IRQ raised. IRQ + * is cleared using command register bit 1. */ + __IM uint32_t bus_status : 1; /*!< [2..2] 0=OK, 1=Bus abort detected and processing halted (the + * NPU has reached IDLE state and does not start to process + * any more commands/AXI transactions). Can only be cleared + * by a reset. */ + __IM uint32_t reset_status : 1; /*!< [3..3] Reset is ongoing and only this register can be read (other + * registers read as 0 and writes are ignored). A value of + * 0 means the NPU is not being reset and can be accessed + * as normal. */ + __IM uint32_t cmd_parse_error : 1; /*!< [4..4] 0=No error, 1=Command-stream parsing error detected. + * Can only be cleared by a reset. */ + __IM uint32_t cmd_end_reached : 1; /*!< [5..5] 0=Not reached, 1=Reached. Cleared by writing QBASE or + * QSIZE when the NPU is in stopped state. */ + __IM uint32_t pmu_irq_raised : 1; /*!< [6..6] 0=No PMU IRQ, 1=PMU IRQ raised. Cleared by using command + * register bit 1 */ + uint32_t : 1; + __IM uint32_t ecc_fault : 1; /*!< [8..8] ECC state for internal RAMs: 0=no fault, 1=ECC fault + * signalled. Can only be cleared by reset. */ + uint32_t : 2; + __IM uint32_t faulting_interface : 1; /*!< [11..11] Faulting interface on bus abort. 0=AXI-M0, 1=AXI-M1 */ + __IM uint32_t faulting_channel : 4; /*!< [15..12] Faulting channel on a bus abort. Read: 0=Cmd, 1=IFM, + * 2=Weights, 3=Scale+Bias, 4=Mem2Mem; Write: 8=OFM, 9=Mem2Mem */ + __IM uint32_t irq_history_mask : 16; /*!< [31..16] IRQ History mask */ + } STATUS_b; + }; + + union + { + __IOM uint32_t CMD; /*!< (@ 0x00000008) Command register, reads as last written command */ + + struct + { + __IOM uint32_t transition_to_running_state : 1; /*!< [0..0] Write 1 to transition the NPU to running state. Writing + * 0 has no effect */ + __IOM uint32_t clear_irq : 1; /*!< [1..1] Write 1 to clear the IRQ status in the STATUS register. + * Writing 0 has no effect */ + __IOM uint32_t clock_q_enable : 1; /*!< [2..2] Write 1 to this bit to enable clock off using the Clock + * Q-interface and enable the main clock gate */ + __IOM uint32_t power_q_enable : 1; /*!< [3..3] Write 1 to this bit to enable power off using the Power + * Q-interface */ + uint32_t : 12; + __IOM uint32_t clear_irq_history : 16; /*!< [31..16] Clears the IRQ history mask */ + } CMD_b; + }; + + union + { + __IOM uint32_t RESET; /*!< (@ 0x0000000C) Request Reset and new security mode */ + + struct + { + __IOM uint32_t pending_CPL : 1; /*!< [0..0] Current privilege level: 0=User, 1=Privileged */ + __IOM uint32_t pending_CSL : 1; /*!< [1..1] Current security level: 0=Secure, 1=Non secure */ + uint32_t : 30; + } RESET_b; + }; + + union + { + __IOM uint32_t QBASE0; /*!< (@ 0x00000010) Base address of Command-queue bits[31:0]. The + * address is 4-byte-aligned */ + + struct + { + __IOM uint32_t QBASE0 : 32; /*!< [31..0] The 4-byte-aligned lower bytes of the base address value + * for the command stream */ + } QBASE0_b; + }; + + union + { + __IOM uint32_t QBASE1; /*!< (@ 0x00000014) Address extension bits[47:32] for queue base */ + + struct + { + __IOM uint32_t QBASE1 : 32; /*!< [31..0] The 4-byte-aligned upper bytes of the base address value + * for the command stream */ + } QBASE1_b; + }; + + union + { + __IM uint32_t QREAD; /*!< (@ 0x00000018) Read offset in the command stream in bytes. Multiples + * of 4 in the range 0-16 MB */ + + struct + { + __IM uint32_t QREAD : 32; /*!< [31..0] The read offset of the current command under execution */ + } QREAD_b; + }; + + union + { + __IOM uint32_t QCONFIG; /*!< (@ 0x0000001C) AXI configuration for the command stream in the + * range 0-3. Same encoding as for REGIONCFG */ + + struct + { + __IOM uint32_t QCONFIG : 32; /*!< [31..0] AXI configuration for the command stream in the range + * 0-3 */ + } QCONFIG_b; + }; + + union + { + __IOM uint32_t QSIZE; /*!< (@ 0x00000020) Size of the command stream in bytes. Multiples + * of 4 in the range 0-16 MB */ + + struct + { + __IOM uint32_t QSIZE : 32; /*!< [31..0] Size of the next command stream to be executed by the + * NPU */ + } QSIZE_b; + }; + + union + { + __IM uint32_t PROT; /*!< (@ 0x00000024) Protection level configured for the NPU when + * acting as an AXI master */ + + struct + { + __IM uint32_t active_CPL : 1; /*!< [0..0] Current privilege level: 0=User, 1=Privileged */ + __IM uint32_t active_CSL : 1; /*!< [1..1] Current security level: 0=Secure, 1=Non-secure */ + uint32_t : 30; + } PROT_b; + }; + + union + { + __IM uint32_t CONFIG; /*!< (@ 0x00000028) RTL configuration */ + + struct + { + __IM uint32_t macs_per_cc : 4; /*!< [3..0] The log2(macs/clock cycle). Valid encoding range is 5-8 + * for 32-256 MACs/clock cycle. */ + __IM uint32_t cmd_stream_version : 4; /*!< [7..4] Command-stream version accepted by this NPU. */ + __IM uint32_t shram_size : 8; /*!< [15..8] Size in KB of SHRAM in the range 8-48. */ + uint32_t : 11; + __IM uint32_t custom_dma : 1; /*!< [27..27] Custom DMA configuration */ + __IM uint32_t product : 4; /*!< [31..28] Product configuration */ + } CONFIG_b; + }; + + union + { + __IOM uint32_t LOCK; /*!< (@ 0x0000002C) Lock register. This register is designed for + * driver use and does not affect NPU functionality */ + + struct + { + __IOM uint32_t LOCK : 32; /*!< [31..0] 32-bit value for the LOCK configuration */ + } LOCK_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t REGIONCFG; /*!< (@ 0x0000003C) Base pointer configuration. Bits[2*k+1:2*k] give + * the memory type for REGION[k] */ + + struct + { + __IOM uint32_t region0 : 2; /*!< [1..0] Bits for the Region0 configuration */ + __IOM uint32_t region1 : 2; /*!< [3..2] Bits for the Region1 configuration */ + __IOM uint32_t region2 : 2; /*!< [5..4] Bits for the Region2 configuration */ + __IOM uint32_t region3 : 2; /*!< [7..6] Bits for the Region3 configuration */ + __IOM uint32_t region4 : 2; /*!< [9..8] Bits for the Region4 configuration */ + __IOM uint32_t region5 : 2; /*!< [11..10] Bits for the Region5 configuration */ + __IOM uint32_t region6 : 2; /*!< [13..12] Bits for the Region6 configuration */ + __IOM uint32_t region7 : 2; /*!< [15..14] Bits for the Region7 configuration */ + uint32_t : 16; + } REGIONCFG_b; + }; + + union + { + __IOM uint32_t AXI_LIMIT0; /*!< (@ 0x00000040) AXI limits for port 0 counter 0 */ + + struct + { + __IOM uint32_t max_beats : 2; /*!< [1..0] Burst-split alignment: 0=64 bytes, 1=128 bytes, 2=256 + * bytes, 3=reserved */ + uint32_t : 2; + __IOM uint32_t memtype : 4; /*!< [7..4] Memtype */ + uint32_t : 8; + __IOM uint32_t max_outstanding_read_m1 : 8; /*!< [23..16] Maximum number of outstanding AXI read transactions + * - 1 in range 0-31 */ + __IOM uint32_t max_outstanding_write_m1 : 8; /*!< [31..24] Maximum number of outstanding AXI write transactions + * - 1 in range 0-15 */ + } AXI_LIMIT0_b; + }; + + union + { + __IOM uint32_t AXI_LIMIT1; /*!< (@ 0x00000044) AXI limits for port 0 counter 1 */ + + struct + { + __IOM uint32_t max_beats : 2; /*!< [1..0] Burst-split alignment: 0=64 bytes, 1=128 bytes, 2=256 + * bytes, 3=reserved */ + uint32_t : 2; + __IOM uint32_t memtype : 4; /*!< [7..4] Memtype */ + uint32_t : 8; + __IOM uint32_t max_outstanding_read_m1 : 8; /*!< [23..16] Maximum number of outstanding AXI read transactions + * - 1 in range 0-31 */ + __IOM uint32_t max_outstanding_write_m1 : 8; /*!< [31..24] Maximum number of outstanding AXI write transactions + * - 1 in range 0-15 */ + } AXI_LIMIT1_b; + }; + + union + { + __IOM uint32_t AXI_LIMIT2; /*!< (@ 0x00000048) AXI limits for port 1 counter 2 */ + + struct + { + __IOM uint32_t max_beats : 2; /*!< [1..0] Burst-split alignment: 0=64 bytes, 1=128 bytes, 2=256 + * bytes, 3=reserved */ + uint32_t : 2; + __IOM uint32_t memtype : 4; /*!< [7..4] Memtype */ + uint32_t : 8; + __IOM uint32_t max_outstanding_read_m1 : 8; /*!< [23..16] Maximum number of outstanding AXI read transactions + * - 1 in range 0-31 */ + __IOM uint32_t max_outstanding_write_m1 : 8; /*!< [31..24] Maximum number of outstanding AXI write transactions + * - 1 in range 0-15 */ + } AXI_LIMIT2_b; + }; + + union + { + __IOM uint32_t AXI_LIMIT3; /*!< (@ 0x0000004C) AXI limits for port 1 counter 3 */ + + struct + { + __IOM uint32_t max_beats : 2; /*!< [1..0] Burst-split alignment: 0=64 bytes, 1=128 bytes, 2=256 + * bytes, 3=reserved */ + uint32_t : 2; + __IOM uint32_t memtype : 4; /*!< [7..4] Memtype */ + uint32_t : 8; + __IOM uint32_t max_outstanding_read_m1 : 8; /*!< [23..16] Maximum number of outstanding AXI read transactions + * - 1 in range 0-31 */ + __IOM uint32_t max_outstanding_write_m1 : 8; /*!< [31..24] Maximum number of outstanding AXI write transactions + * - 1 in range 0-15 */ + } AXI_LIMIT3_b; + }; + __IM uint32_t RESERVED1[12]; + + union + { + __IOM uint32_t BASEP0; /*!< (@ 0x00000080) Lower 32 bits of the Base pointer for region + * index 0 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP0_b; + }; + + union + { + __IOM uint32_t BASEP1; /*!< (@ 0x00000084) Upper 32 bits of the Base pointer for region + * index 0 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP1_b; + }; + + union + { + __IOM uint32_t BASEP2; /*!< (@ 0x00000088) Lower 32 bits of the Base pointer for region + * index 1 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP2_b; + }; + + union + { + __IOM uint32_t BASEP3; /*!< (@ 0x0000008C) Upper 32 bits of the Base pointer for region + * index 1 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP3_b; + }; + + union + { + __IOM uint32_t BASEP4; /*!< (@ 0x00000090) Lower 32 bits of the Base pointer for region + * index 2 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP4_b; + }; + + union + { + __IOM uint32_t BASEP5; /*!< (@ 0x00000094) Upper 32 bits of the Base pointer for region + * index 2 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP5_b; + }; + + union + { + __IOM uint32_t BASEP6; /*!< (@ 0x00000098) Lower 32 bits of the Base pointer for region + * index 3 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP6_b; + }; + + union + { + __IOM uint32_t BASEP7; /*!< (@ 0x0000009C) Upper 32 bits of the Base pointer for region + * index 3 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP7_b; + }; + + union + { + __IOM uint32_t BASEP8; /*!< (@ 0x000000A0) Lower 32 bits of the Base pointer for region + * index 4 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP8_b; + }; + + union + { + __IOM uint32_t BASEP9; /*!< (@ 0x000000A4) Upper 32 bits of the Base pointer for region + * index 4 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP9_b; + }; + + union + { + __IOM uint32_t BASEP10; /*!< (@ 0x000000A8) Lower 32 bits of the Base pointer for region + * index 5 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP10_b; + }; + + union + { + __IOM uint32_t BASEP11; /*!< (@ 0x000000AC) Upper 32 bits of the Base pointer for region + * index 5 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP11_b; + }; + + union + { + __IOM uint32_t BASEP12; /*!< (@ 0x000000B0) Lower 32 bits of the Base pointer for region + * index 6 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP12_b; + }; + + union + { + __IOM uint32_t BASEP13; /*!< (@ 0x000000B4) Upper 32 bits of the Base pointer for region + * index 6 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP13_b; + }; + + union + { + __IOM uint32_t BASEP14; /*!< (@ 0x000000B8) Lower 32 bits of the Base pointer for region + * index 7 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP14_b; + }; + + union + { + __IOM uint32_t BASEP15; /*!< (@ 0x000000BC) Upper 32 bits of the Base pointer for region + * index 7 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP15_b; + }; + __IM uint32_t RESERVED2[48]; + + union + { + __IOM uint32_t PMCR; /*!< (@ 0x00000180) PMU master control register */ + + struct + { + __IOM uint32_t cnt_en : 1; /*!< [0..0] Enable counter */ + __IOM uint32_t event_cnt_rst : 1; /*!< [1..1] Reset event counter */ + __IOM uint32_t cycle_cnt_rst : 1; /*!< [2..2] Reset cycle counter */ + __IOM uint32_t mask_en : 1; /*!< [3..3] PMU can be enabled/disabled by command stream operationNPU_OP_PMU_MASK */ + uint32_t : 7; + __IOM uint32_t num_event_cnt : 5; /*!< [15..11] Number of event counters available for performance + * measurement */ + uint32_t : 16; + } PMCR_b; + }; + + union + { + __IOM uint32_t PMCNTENSET; /*!< (@ 0x00000184) Count-enable set register */ + + struct + { + __IOM uint32_t EVENT_CNT_0 : 1; /*!< [0..0] Event-counter enable bit for PMU_EVCNTR0 */ + __IOM uint32_t EVENT_CNT_1 : 1; /*!< [1..1] Event-counter enable bit for PMU_EVCNTR1 */ + __IOM uint32_t EVENT_CNT_2 : 1; /*!< [2..2] Event-counter enable bit for PMU_EVCNTR2 */ + __IOM uint32_t EVENT_CNT_3 : 1; /*!< [3..3] Event-counter enable bit for PMU_EVCNTR3 */ + uint32_t : 27; + __IOM uint32_t CYCLE_CNT : 1; /*!< [31..31] PMCCNTR enable bit */ + } PMCNTENSET_b; + }; + + union + { + __IOM uint32_t PMCNTENCLR; /*!< (@ 0x00000188) Count-enable clear register */ + + struct + { + __IOM uint32_t EVENT_CNT_0 : 1; /*!< [0..0] Event-counter disable bit for PMU_EVCNTR0 */ + __IOM uint32_t EVENT_CNT_1 : 1; /*!< [1..1] Event-counter disable bit for PMU_EVCNTR1 */ + __IOM uint32_t EVENT_CNT_2 : 1; /*!< [2..2] Event-counter disable bit for PMU_EVCNTR2 */ + __IOM uint32_t EVENT_CNT_3 : 1; /*!< [3..3] Event-counter disable bit for PMU_EVCNTR3 */ + uint32_t : 27; + __IOM uint32_t CYCLE_CNT : 1; /*!< [31..31] PMCCNTR disable bit */ + } PMCNTENCLR_b; + }; + + union + { + __IOM uint32_t PMOVSSET; /*!< (@ 0x0000018C) Overflow-flag status set register */ + + struct + { + __IOM uint32_t EVENT_CNT_0_OVF : 1; /*!< [0..0] Event-counter overflow set bit for PMU_EVCNTR0 */ + __IOM uint32_t EVENT_CNT_1_OVF : 1; /*!< [1..1] Event-counter overflow set bit for PMU_EVCNTR1 */ + __IOM uint32_t EVENT_CNT_2_OVF : 1; /*!< [2..2] Event-counter overflow set bit for PMU_EVCNTR2 */ + __IOM uint32_t EVENT_CNT_3_OVF : 1; /*!< [3..3] Event-counter overflow set bit for PMU_EVCNTR3 */ + uint32_t : 27; + __IOM uint32_t CYCLE_CNT_OVF : 1; /*!< [31..31] PMCCNTR overflow set bit */ + } PMOVSSET_b; + }; + + union + { + __IOM uint32_t PMOVSCLR; /*!< (@ 0x00000190) Overflow-flag status clear register */ + + struct + { + __IOM uint32_t EVENT_CNT_0_OVF : 1; /*!< [0..0] Event-counter overflow clear bit for PMU_EVCNTR0 */ + __IOM uint32_t EVENT_CNT_1_OVF : 1; /*!< [1..1] Event-counter overflow clear bit for PMU_EVCNTR1 */ + __IOM uint32_t EVENT_CNT_2_OVF : 1; /*!< [2..2] Event-counter overflow clear bit for PMU_EVCNTR2 */ + __IOM uint32_t EVENT_CNT_3_OVF : 1; /*!< [3..3] Event-counter overflow clear bit for PMU_EVCNTR3 */ + uint32_t : 27; + __IOM uint32_t CYCLE_CNT_OVF : 1; /*!< [31..31] PMCCNTR overflow clear bit */ + } PMOVSCLR_b; + }; + + union + { + __IOM uint32_t PMINTSET; /*!< (@ 0x00000194) Interrupt-enable set register */ + + struct + { + __IOM uint32_t EVENT_CNT_0_INT : 1; /*!< [0..0] Event-counter overflow interrupt-request enable bit for + * PMU_EVCNTR0 */ + __IOM uint32_t EVENT_CNT_1_INT : 1; /*!< [1..1] Event-counter overflow interrupt-request enable bit for + * PMU_EVCNTR1 */ + __IOM uint32_t EVENT_CNT_2_INT : 1; /*!< [2..2] Event-counter overflow interrupt-request enable bit for + * PMU_EVCNTR2 */ + __IOM uint32_t EVENT_CNT_3_INT : 1; /*!< [3..3] Event-counter overflow interrupt-request enable bit for + * PMU_EVCNTR3 */ + uint32_t : 27; + __IOM uint32_t CYCLE_CNT_INT : 1; /*!< [31..31] PMCCNTR overflow interrupt-request enable bit */ + } PMINTSET_b; + }; + + union + { + __IOM uint32_t PMINTCLR; /*!< (@ 0x00000198) Interrupt-enable clear register */ + + struct + { + __IOM uint32_t EVENT_CNT_0_INT : 1; /*!< [0..0] Event-counter overflow interrupt-request disable bit + * for PMU_EVCNTR0 */ + __IOM uint32_t EVENT_CNT_1_INT : 1; /*!< [1..1] Event-counter overflow interrupt-request disable bit + * for PMU_EVCNTR1 */ + __IOM uint32_t EVENT_CNT_2_INT : 1; /*!< [2..2] Event-counter overflow interrupt-request disable bit + * for PMU_EVCNTR2 */ + __IOM uint32_t EVENT_CNT_3_INT : 1; /*!< [3..3] Event-counter overflow interrupt-request disable bit + * for PMU_EVCNTR3 */ + uint32_t : 27; + __IOM uint32_t CYCLE_CNT_INT : 1; /*!< [31..31] PMCCNTR overflow interrupt-request disable bit */ + } PMINTCLR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t PMCCNTR_LO; /*!< (@ 0x000001A0) Performance-monitor cycle count low register */ + + struct + { + __IOM uint32_t CYCLE_CNT_LO : 32; /*!< [31..0] Cycle count low */ + } PMCCNTR_LO_b; + }; + + union + { + __IOM uint32_t PMCCNTR_HI; /*!< (@ 0x000001A4) Performance-monitor cycle count high register */ + + struct + { + __IOM uint32_t CYCLE_CNT_HI : 32; /*!< [31..0] Cycle count high */ + } PMCCNTR_HI_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t PMCAXI_CHAN; /*!< (@ 0x000001AC) Set which AXI channel monitor */ + + struct + { + __IOM uint32_t CH_SEL : 4; /*!< [3..0] Specify the type of traffic for bandwidth or latency + * measurements (Read: 0=command traffic, 1=IFM traffic, 2=Weight + * traffic, 3=Scale+Bias, 4=Mem2Mem traffic - read direction; + * Write: 8=OFM traffic, 9=Mem2Mem traffic - write direction) */ + uint32_t : 4; + __IOM uint32_t AXI_CNT_SEL : 2; /*!< [9..8] Select AXI counter to monitor for latency measurements + * (0=AXI0 counter0, 1=AXI0 counter1, 2=AXI1 counter 2, 3=AXI1 + * counter3) */ + __IOM uint32_t BW_CH_SEL_EN : 1; /*!< [10..10] Enable bandwidth channel selector: 0=AXI bw events + * measured for all channels, 1=AXI bw events measured for + * channel specified by CH_SEL */ + uint32_t : 21; + } PMCAXI_CHAN_b; + }; + __IM uint32_t RESERVED5[84]; + + union + { + __IOM uint32_t PMU_EVCNTR0; /*!< (@ 0x00000300) Performance-monitor event counters 0 */ + + struct + { + __IOM uint32_t PMEVCNTR : 32; /*!< [31..0] Performance-monitor event counters. */ + } PMU_EVCNTR0_b; + }; + + union + { + __IOM uint32_t PMU_EVCNTR1; /*!< (@ 0x00000304) Performance-monitor event counters 1 */ + + struct + { + __IOM uint32_t PMEVCNTR : 32; /*!< [31..0] Performance-monitor event counters. */ + } PMU_EVCNTR1_b; + }; + + union + { + __IOM uint32_t PMU_EVCNTR2; /*!< (@ 0x00000308) Performance-monitor event counters 2 */ + + struct + { + __IOM uint32_t PMEVCNTR : 32; /*!< [31..0] Performance-monitor event counters. */ + } PMU_EVCNTR2_b; + }; + + union + { + __IOM uint32_t PMU_EVCNTR3; /*!< (@ 0x0000030C) Performance-monitor event counters 3 */ + + struct + { + __IOM uint32_t PMEVCNTR : 32; /*!< [31..0] Performance-monitor event counters. */ + } PMU_EVCNTR3_b; + }; + __IM uint32_t RESERVED6[28]; + + union + { + __IOM uint32_t PMU_EVTYPER0; /*!< (@ 0x00000380) Performance-monitor event-type control counters + * 0 */ + + struct + { + __IOM uint32_t EV_TYPE : 32; /*!< [31..0] Event type. */ + } PMU_EVTYPER0_b; + }; + + union + { + __IOM uint32_t PMU_EVTYPER1; /*!< (@ 0x00000384) Performance-monitor event-type control counters + * 1 */ + + struct + { + __IOM uint32_t EV_TYPE : 32; /*!< [31..0] Event type. */ + } PMU_EVTYPER1_b; + }; + + union + { + __IOM uint32_t PMU_EVTYPER2; /*!< (@ 0x00000388) Performance-monitor event-type control counters + * 2 */ + + struct + { + __IOM uint32_t EV_TYPE : 32; /*!< [31..0] Event type. */ + } PMU_EVTYPER2_b; + }; + + union + { + __IOM uint32_t PMU_EVTYPER3; /*!< (@ 0x0000038C) Performance-monitor event-type control counters + * 3 */ + + struct + { + __IOM uint32_t EV_TYPE : 32; /*!< [31..0] Event type. */ + } PMU_EVTYPER3_b; + }; + __IM uint32_t RESERVED7[784]; + + union + { + __IM uint32_t PID4; /*!< (@ 0x00000FD0) Peripheral ID byte 4 (Arm=code 4) */ + + struct + { + __IM uint32_t PID4 : 32; /*!< [31..0] Byte 4 of the Peripheral ID (Lower 8 bits valid) */ + } PID4_b; + }; + + union + { + __IM uint32_t PID5; /*!< (@ 0x00000FD4) Peripheral ID byte 5 (reserved) */ + + struct + { + __IM uint32_t PID5 : 32; /*!< [31..0] Byte 5 of the Peripheral ID (Lower 8 bits valid) */ + } PID5_b; + }; + + union + { + __IM uint32_t PID6; /*!< (@ 0x00000FD8) Peripheral ID byte 6 (reserved) */ + + struct + { + __IM uint32_t PID6 : 32; /*!< [31..0] Byte 6 of the Peripheral ID (Lower 8 bits valid) */ + } PID6_b; + }; + + union + { + __IM uint32_t PID7; /*!< (@ 0x00000FDC) Peripheral ID byte 7 (reserved) */ + + struct + { + __IM uint32_t PID7 : 32; /*!< [31..0] Byte 7 of the Peripheral ID (Lower 8 bits valid) */ + } PID7_b; + }; + + union + { + __IM uint32_t PID0; /*!< (@ 0x00000FE0) Peripheral ID byte 0. This is bits[7:0] of the + * part number. */ + + struct + { + __IM uint32_t PID0 : 32; /*!< [31..0] Byte 0 of the Peripheral ID (Lower 8 bits valid) */ + } PID0_b; + }; + + union + { + __IM uint32_t PID1; /*!< (@ 0x00000FE4) Peripheral ID byte 1. This is bits[11:8] of the + * part number in bits[3:0], and bits[3:0] + * of the Arm ID in bits[7:4]. */ + + struct + { + __IM uint32_t PID1 : 32; /*!< [31..0] Byte 1 of the Peripheral ID (Lower 8 bits valid) */ + } PID1_b; + }; + + union + { + __IM uint32_t PID2; /*!< (@ 0x00000FE8) Peripheral ID byte 2. This is bits[6:4] of the + * Arm ID in bits[2:0], and bit 3 indicates + * format B. */ + + struct + { + __IM uint32_t PID2 : 32; /*!< [31..0] Byte 2 of the Peripheral ID (Lower 8 bits valid) */ + } PID2_b; + }; + + union + { + __IM uint32_t PID3; /*!< (@ 0x00000FEC) Peripheral ID byte 3. */ + + struct + { + __IM uint32_t PID3 : 32; /*!< [31..0] Byte 3 of the Peripheral ID (Lower 8 bits valid) */ + } PID3_b; + }; + + union + { + __IM uint32_t CID0; /*!< (@ 0x00000FF0) Component ID byte 0. */ + + struct + { + __IM uint32_t CID0 : 32; /*!< [31..0] Byte 0 of the Component ID (Lower 8 bits valid) */ + } CID0_b; + }; + + union + { + __IM uint32_t CID1; /*!< (@ 0x00000FF4) Component ID byte 1. */ + + struct + { + __IM uint32_t CID1 : 32; /*!< [31..0] Byte 1 of the Component ID (Lower 8 bits valid) */ + } CID1_b; + }; + + union + { + __IM uint32_t CID2; /*!< (@ 0x00000FF8) Component ID byte 2. */ + + struct + { + __IM uint32_t CID2 : 32; /*!< [31..0] Byte 2 of the Component ID (Lower 8 bits valid) */ + } CID2_b; + }; + + union + { + __IM uint32_t CID3; /*!< (@ 0x00000FFC) Component ID byte 3. */ + + struct + { + __IM uint32_t CID3 : 32; /*!< [31..0] Byte 3 of the Component ID (Lower 8 bits valid) */ + } CID3_b; + }; +} R_NPU_Type; /*!< Size = 4096 (0x1000) */ + +/* =========================================================================================================================== */ +/* ================ R_PDM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Pulse Density Modulator Interface (R_PDM) + */ + +typedef struct /*!< (@ 0x40256000) R_PDM Structure */ +{ + union + { + __OM uint32_t PDCSTRTR; /*!< (@ 0x00000000) Channel Software Start Trigger Register */ + + struct + { + __OM uint32_t STRTRG0 : 1; /*!< [0..0] Channel 0 start trigger */ + __OM uint32_t STRTRG1 : 1; /*!< [1..1] Channel 1 start trigger */ + __OM uint32_t STRTRG2 : 1; /*!< [2..2] Channel 2 start trigger */ + uint32_t : 29; + } PDCSTRTR_b; + }; + + union + { + __OM uint32_t PDCSTPTR; /*!< (@ 0x00000004) Channel Software Stop Trigger Register */ + + struct + { + __OM uint32_t STPTRG0 : 1; /*!< [0..0] Channel 0 stop trigger */ + __OM uint32_t STPTRG1 : 1; /*!< [1..1] Channel 1 stop trigger */ + __OM uint32_t STPTRG2 : 1; /*!< [2..2] Channel 2 stop trigger */ + uint32_t : 29; + } PDCSTPTR_b; + }; + + union + { + __OM uint32_t PDCCHGTR; /*!< (@ 0x00000008) Channel Software Change Trigger Register */ + + struct + { + __OM uint32_t CHGTRG0 : 1; /*!< [0..0] Channel 0 change trigger */ + __OM uint32_t CHGTRG1 : 1; /*!< [1..1] Channel 1 change trigger */ + __OM uint32_t CHGTRG2 : 1; /*!< [2..2] Channel 2 change trigger */ + uint32_t : 29; + } PDCCHGTR_b; + }; + + union + { + __IOM uint32_t PDCICR; /*!< (@ 0x0000000C) Channel Interrupt Control Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t ISDE0 : 1; /*!< [8..8] Channel 0 sound detection interrupt enable bit */ + __IOM uint32_t ISDE1 : 1; /*!< [9..9] Channel 1 sound detection interrupt enable bit */ + __IOM uint32_t ISDE2 : 1; /*!< [10..10] Channel 2 sound detection interrupt enable bit */ + uint32_t : 5; + __IOM uint32_t IDRE0 : 1; /*!< [16..16] Channel 0 data reception interrupt enable bit */ + __IOM uint32_t IDRE1 : 1; /*!< [17..17] Channel 1 data reception interrupt enable bit */ + __IOM uint32_t IDRE2 : 1; /*!< [18..18] Channel 2 data reception interrupt enable bit */ + uint32_t : 5; + __IOM uint32_t IEDE0 : 1; /*!< [24..24] Channel 0 error detection interrupt enable bit */ + __IOM uint32_t IEDE1 : 1; /*!< [25..25] Channel 1 error detection interrupt enable bit */ + __IOM uint32_t IEDE2 : 1; /*!< [26..26] Channel 2 error detection interrupt enable bit */ + uint32_t : 5; + } PDCICR_b; + }; + + union + { + __IM uint32_t PDCSR; /*!< (@ 0x00000010) Channel Status Register */ + + struct + { + __IM uint32_t STATE0 : 1; /*!< [0..0] Channel 0 state */ + __IM uint32_t STATE1 : 1; /*!< [1..1] Channel 1 state */ + __IM uint32_t STATE2 : 1; /*!< [2..2] Channel 2 state */ + uint32_t : 5; + __IM uint32_t SDF0 : 1; /*!< [8..8] Channel 0 sound detection flag */ + __IM uint32_t SDF1 : 1; /*!< [9..9] Channel 1 sound detection flag */ + __IM uint32_t SDF2 : 1; /*!< [10..10] Channel 2 sound detection flag */ + uint32_t : 5; + __IM uint32_t DRF0 : 1; /*!< [16..16] Channel 0 data reception flag */ + __IM uint32_t DRF1 : 1; /*!< [17..17] Channel 1 data reception flag */ + __IM uint32_t DRF2 : 1; /*!< [18..18] Channel 2 data reception flag */ + uint32_t : 5; + __IM uint32_t EDF0 : 1; /*!< [24..24] Channel 0 error detection flag */ + __IM uint32_t EDF1 : 1; /*!< [25..25] Channel 1 error detection flag */ + __IM uint32_t EDF2 : 1; /*!< [26..26] Channel 2 error detection flag */ + uint32_t : 5; + } PDCSR_b; + }; + + union + { + __OM uint32_t PDCSCR; /*!< (@ 0x00000014) Channel Status Clear Register */ + + struct + { + uint32_t : 8; + __OM uint32_t SDFC0 : 1; /*!< [8..8] Channel 0 sound detection flag clear */ + __OM uint32_t SDFC1 : 1; /*!< [9..9] Channel 1 sound detection flag clear */ + __OM uint32_t SDFC2 : 1; /*!< [10..10] Channel 2 sound detection flag clear */ + uint32_t : 21; + } PDCSCR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t PDCSDCR; /*!< (@ 0x00000020) Channel Sound Detection Control Register */ + + struct + { + __IOM uint32_t SDE0 : 1; /*!< [0..0] Channel 0 sound detection enable bit */ + __IOM uint32_t SDE1 : 1; /*!< [1..1] Channel 1 sound detection enable bit */ + __IOM uint32_t SDE2 : 1; /*!< [2..2] Channel 2 sound detection enable bit */ + uint32_t : 29; + } PDCSDCR_b; + }; + + union + { + __IOM uint32_t PDCDRCR; /*!< (@ 0x00000024) Channel Data Read Control Register */ + + struct + { + __IOM uint32_t DATRE0 : 1; /*!< [0..0] Channel 0 data read enable bit */ + __IOM uint32_t DATRE1 : 1; /*!< [1..1] Channel 1 data read enable bit */ + __IOM uint32_t DATRE2 : 1; /*!< [2..2] Channel 2 data read enable bit */ + uint32_t : 29; + } PDCDRCR_b; + }; + + union + { + __OM uint32_t PDCDCR; /*!< (@ 0x00000028) Channel Data Clear Register */ + + struct + { + __OM uint32_t DATC0 : 1; /*!< [0..0] Channel 0 data clear */ + __OM uint32_t DATC1 : 1; /*!< [1..1] Channel 1 data clear */ + __OM uint32_t DATC2 : 1; /*!< [2..2] Channel 2 data clear */ + uint32_t : 29; + } PDCDCR_b; + }; + __IM uint32_t RESERVED1[21]; + + union + { + __IM uint32_t PDVR; /*!< (@ 0x00000080) Version Register */ + + struct + { + __IM uint32_t VER : 12; /*!< [11..0] Version */ + uint32_t : 20; + } PDVR_b; + }; + __IM uint32_t RESERVED2[31]; + __IOM R_PDM_CH_Type CH[3]; /*!< (@ 0x00000100) PDM Channel-Specific Registers */ +} R_PDM_Type; /*!< Size = 1024 (0x400) */ + +/* =========================================================================================================================== */ +/* ================ R_RMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet MAC (R_RMAC0) + */ + +typedef struct /*!< (@ 0x403CB000) R_RMAC0 Structure */ +{ + union + { + __IOM uint32_t MPSM; /*!< (@ 0x00000000) MAC PHY Station Management Register (MPSM) */ + + struct + { + __IOM uint32_t PSME : 1; /*!< [0..0] PSME */ + uint32_t : 1; + __IOM uint32_t MFF : 1; /*!< [2..2] MFF */ + __IOM uint32_t PDA : 5; /*!< [7..3] PDA */ + __IOM uint32_t PRA : 5; /*!< [12..8] PRA */ + __IOM uint32_t POP : 2; /*!< [14..13] POP */ + uint32_t : 1; + __IOM uint32_t PRD : 16; /*!< [31..16] PRD */ + } MPSM_b; + }; + + union + { + __IOM uint32_t MPIC; /*!< (@ 0x00000004) MAC PHY Interfaces Configuration Register (MPIC) */ + + struct + { + __IOM uint32_t PIS : 3; /*!< [2..0] PIS */ + __IOM uint32_t LSC : 3; /*!< [5..3] LSC */ + uint32_t : 2; + __IOM uint32_t PIP : 1; /*!< [8..8] PIP */ + __IOM uint32_t PIPP : 1; /*!< [9..9] PIPP */ + __IOM uint32_t PLSPP : 1; /*!< [10..10] PLSPP */ + uint32_t : 5; + __IOM uint32_t PSMCS : 7; /*!< [22..16] PSMCS */ + __IOM uint32_t PSMDP : 1; /*!< [23..23] PSMDP */ + __IOM uint32_t PSMHT : 3; /*!< [26..24] PSMHT */ + uint32_t : 1; + __IOM uint32_t PSMCT : 3; /*!< [30..28] PSMCT */ + uint32_t : 1; + } MPIC_b; + }; + + union + { + __IOM uint32_t MPIM; /*!< (@ 0x00000008) MAC PHY Interfaces Monitoring Register (MPIM) */ + + struct + { + __IOM uint32_t PLS : 1; /*!< [0..0] PLS */ + __IOM uint32_t LPIA : 1; /*!< [1..1] LPIA */ + uint32_t : 30; + } MPIM_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t MIOC; /*!< (@ 0x00000010) RMAC IO Configuration Registers Register (MIOC) */ + + struct + { + __IOM uint32_t MIOC : 32; /*!< [31..0] MIOC */ + } MIOC_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t MTFFC; /*!< (@ 0x00000020) MAC Transmission Frame Format Configuration Register + * (MTFFC) */ + + struct + { + __IOM uint32_t DPAD : 1; /*!< [0..0] DPAD */ + __IOM uint32_t FCM : 1; /*!< [1..1] FCM */ + uint32_t : 30; + } MTFFC_b; + }; + + union + { + __IOM uint32_t MTPFC; /*!< (@ 0x00000024) MAC Transmission Pause or PFC Frame Configuration + * Register (MTPFC) */ + + struct + { + __IOM uint32_t PT : 16; /*!< [15..0] PT */ + __IOM uint32_t PFRT : 8; /*!< [23..16] PFRT */ + uint32_t : 2; + __IOM uint32_t PFM : 1; /*!< [26..26] PFM */ + __IOM uint32_t PFRLV : 5; /*!< [31..27] PFRLV */ + } MTPFC_b; + }; + + union + { + __IOM uint32_t MTPFC2; /*!< (@ 0x00000028) MAC Transmission Pause or PFC Frame configuration2 + * Register (MTPFC2) */ + + struct + { + __IOM uint32_t PFCTTZ : 2; /*!< [1..0] PFCTTZ */ + uint32_t : 6; + __IOM uint32_t MPFCFR0 : 1; /*!< [8..8] MPFCFR0 */ + __IOM uint32_t MPFCFR1 : 1; /*!< [9..9] MPFCFR1 */ + uint32_t : 6; + __IOM uint32_t PFTTZ : 1; /*!< [16..16] PFTTZ */ + __IOM uint32_t MPFR : 1; /*!< [17..17] MPFR */ + uint32_t : 14; + } MTPFC2_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t MTPFC30; /*!< (@ 0x00000030) MAC Transmission Pause or PFC Frame Configuration + * Register 3 (MTPFC3t) (t = 0, 1) */ + + struct + { + __IOM uint32_t PFCPG : 8; /*!< [7..0] PFCPG */ + uint32_t : 24; + } MTPFC30_b; + }; + + union + { + __IOM uint32_t MTPFC31; /*!< (@ 0x00000034) MAC Transmission Pause or PFC Frame Configuration + * Register 3 (MTPFC3t) (t = 0, 1) */ + + struct + { + __IOM uint32_t PFCPG : 8; /*!< [7..0] PFCPG */ + uint32_t : 24; + } MTPFC31_b; + }; + __IM uint32_t RESERVED3[6]; + + union + { + __IOM uint32_t MTATC0; /*!< (@ 0x00000050) MAC Transmission Automatic Timestamp Configuration + * Register (MTATCt) (t = 0, 1) */ + + struct + { + __IOM uint32_t TRTP : 8; /*!< [7..0] TRTP */ + __IOM uint32_t TRTL : 3; /*!< [10..8] TRTL */ + uint32_t : 21; + } MTATC0_b; + }; + + union + { + __IOM uint32_t MTATC1; /*!< (@ 0x00000054) MAC Transmission Automatic Timestamp Configuration + * Register (MTATCt) (t = 0, 1) */ + + struct + { + __IOM uint32_t TRTP : 8; /*!< [7..0] TRTP */ + __IOM uint32_t TRTL : 3; /*!< [10..8] TRTL */ + uint32_t : 21; + } MTATC1_b; + }; + __IM uint32_t RESERVED4[2]; + + union + { + __IOM uint32_t MTIM; /*!< (@ 0x00000060) MAC Transmission Interfaces Monitoring Register + * (MTIM) */ + + struct + { + __IOM uint32_t TS : 1; /*!< [0..0] TS */ + uint32_t : 31; + } MTIM_b; + }; + __IM uint32_t RESERVED5[7]; + + union + { + __IOM uint32_t MRGC; /*!< (@ 0x00000080) MAC Reception General Configuration Register + * (MRGC) */ + + struct + { + __IOM uint32_t RCPT : 1; /*!< [0..0] RCPT */ + __IOM uint32_t PFRC : 1; /*!< [1..1] PFRC */ + __IOM uint32_t PFRTZ : 1; /*!< [2..2] PFRTZ */ + __IOM uint32_t MPDE : 1; /*!< [3..3] MPDE */ + __IOM uint32_t RFCFE : 1; /*!< [4..4] RFCFE */ + uint32_t : 11; + __IOM uint32_t PFCRC : 8; /*!< [23..16] PFCRC */ + uint32_t : 8; + } MRGC_b; + }; + + union + { + __IOM uint32_t MRMAC0; /*!< (@ 0x00000084) MAC Reception MAC Address Configuration Register + * 0 (MRMAC0) */ + + struct + { + __IOM uint32_t MAU : 16; /*!< [15..0] MAU */ + uint32_t : 16; + } MRMAC0_b; + }; + + union + { + __IOM uint32_t MRMAC1; /*!< (@ 0x00000088) MAC Reception MAC Address Configuration Register + * 1 (MRMAC1) */ + + struct + { + __IOM uint32_t MAL : 32; /*!< [31..0] MAL */ + } MRMAC1_b; + }; + + union + { + __IOM uint32_t MRAFC; /*!< (@ 0x0000008C) MAC Reception Address Filter Configuration Register + * (MRAFC) */ + + struct + { + __IOM uint32_t UCENE : 1; /*!< [0..0] UCENE */ + __IOM uint32_t MCENE : 1; /*!< [1..1] MCENE */ + __IOM uint32_t BCENE : 1; /*!< [2..2] BCENE */ + __IOM uint32_t MSTENE : 1; /*!< [3..3] MSTENE */ + __IOM uint32_t BSTENE : 1; /*!< [4..4] BSTENE */ + __IOM uint32_t MCACE : 1; /*!< [5..5] MCACE */ + __IOM uint32_t BCACE : 1; /*!< [6..6] BCACE */ + __IOM uint32_t NDAREE : 1; /*!< [7..7] NDAREE */ + __IOM uint32_t SDSFREE : 1; /*!< [8..8] SDSFREE */ + __IOM uint32_t NSAREE : 1; /*!< [9..9] NSAREE */ + __IOM uint32_t MSAREE : 1; /*!< [10..10] MSAREE */ + uint32_t : 5; + __IOM uint32_t UCENP : 1; /*!< [16..16] UCENP */ + __IOM uint32_t MCENP : 1; /*!< [17..17] MCENP */ + __IOM uint32_t BCENP : 1; /*!< [18..18] BCENP */ + __IOM uint32_t MSTENP : 1; /*!< [19..19] MSTENP */ + __IOM uint32_t BSTENP : 1; /*!< [20..20] BSTENP */ + __IOM uint32_t MCACP : 1; /*!< [21..21] MCACP */ + __IOM uint32_t BCACP : 1; /*!< [22..22] BCACP */ + __IOM uint32_t NDAREP : 1; /*!< [23..23] NDAREP */ + __IOM uint32_t SDSFREP : 1; /*!< [24..24] SDSFREP */ + __IOM uint32_t NSAREP : 1; /*!< [25..25] NSAREP */ + __IOM uint32_t MSAREP : 1; /*!< [26..26] MSAREP */ + uint32_t : 5; + } MRAFC_b; + }; + + union + { + __IOM uint32_t MRSCE; /*!< (@ 0x00000090) MAC Reception Storm Configuration for e-Frames + * Register (MRSCE) */ + + struct + { + __IOM uint32_t CMFE : 16; /*!< [15..0] CMFE */ + __IOM uint32_t CBFE : 16; /*!< [31..16] CBFE */ + } MRSCE_b; + }; + + union + { + __IOM uint32_t MRSCP; /*!< (@ 0x00000094) MAC Reception Storm Configuration for p-Frames + * Register (MRSCP) */ + + struct + { + __IOM uint32_t CMFP : 16; /*!< [15..0] CMFP */ + __IOM uint32_t CBFP : 16; /*!< [31..16] CBFP */ + } MRSCP_b; + }; + + union + { + __IOM uint32_t MRSCC; /*!< (@ 0x00000098) MAC Reception Storm Counter Configuration Register + * (MRSCC) */ + + struct + { + __IOM uint32_t MSCCE : 1; /*!< [0..0] MSCCE */ + __IOM uint32_t BSCCE : 1; /*!< [1..1] BSCCE */ + uint32_t : 14; + __IOM uint32_t MSCCP : 1; /*!< [16..16] MSCCP */ + __IOM uint32_t BSCCP : 1; /*!< [17..17] BSCCP */ + uint32_t : 14; + } MRSCC_b; + }; + + union + { + __IOM uint32_t MRFSCE; /*!< (@ 0x0000009C) MAC Reception Frame Size Configuration for e-Frames + * Register (MRFSCE) */ + + struct + { + __IOM uint32_t EMXS : 16; /*!< [15..0] EMXS */ + __IOM uint32_t EMNS : 16; /*!< [31..16] EMNS */ + } MRFSCE_b; + }; + + union + { + __IOM uint32_t MRFSCP; /*!< (@ 0x000000A0) MAC Reception Frame Size Configuration for p-Frames + * Register (MRFSCP) */ + + struct + { + __IOM uint32_t PMXS : 16; /*!< [15..0] PMXS */ + __IOM uint32_t PMNS : 16; /*!< [31..16] PMNS */ + } MRFSCP_b; + }; + + union + { + __IOM uint32_t MTRC; /*!< (@ 0x000000A4) MAC Timestamp Reception Configuration Register + * (MTRC) */ + + struct + { + __IOM uint32_t TRHFME0 : 1; /*!< [0..0] TRHFME0 */ + __IOM uint32_t TRHFME1 : 1; /*!< [1..1] TRHFME1 */ + uint32_t : 22; + __IOM uint32_t TRDDE : 1; /*!< [24..24] TRDDE */ + __IOM uint32_t TRDDP : 1; /*!< [25..25] TRDDP */ + __IOM uint32_t TCTSE : 1; /*!< [26..26] TCTSE */ + __IOM uint32_t TCTSP : 1; /*!< [27..27] TCTSP */ + __IOM uint32_t DTN : 1; /*!< [28..28] DTN */ + uint32_t : 3; + } MTRC_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t MRPFM; /*!< (@ 0x000000AC) MAC Reception Pause or PFC Frame Monitoring Register + * (MRPFM) */ + + struct + { + __IOM uint32_t PTCA : 1; /*!< [0..0] PTCA */ + uint32_t : 15; + __IOM uint32_t PFCTCA : 8; /*!< [23..16] PFCTCA */ + uint32_t : 8; + } MRPFM_b; + }; + __IM uint32_t RESERVED7[20]; + + union + { + __IOM uint32_t MPFC0; /*!< (@ 0x00000100) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC0_b; + }; + + union + { + __IOM uint32_t MPFC1; /*!< (@ 0x00000104) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC1_b; + }; + + union + { + __IOM uint32_t MPFC2; /*!< (@ 0x00000108) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC2_b; + }; + + union + { + __IOM uint32_t MPFC3; /*!< (@ 0x0000010C) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC3_b; + }; + + union + { + __IOM uint32_t MPFC4; /*!< (@ 0x00000110) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC4_b; + }; + + union + { + __IOM uint32_t MPFC5; /*!< (@ 0x00000114) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC5_b; + }; + + union + { + __IOM uint32_t MPFC6; /*!< (@ 0x00000118) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC6_b; + }; + + union + { + __IOM uint32_t MPFC7; /*!< (@ 0x0000011C) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC7_b; + }; + + union + { + __IOM uint32_t MPFC8; /*!< (@ 0x00000120) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC8_b; + }; + + union + { + __IOM uint32_t MPFC9; /*!< (@ 0x00000124) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC9_b; + }; + + union + { + __IOM uint32_t MPFC10; /*!< (@ 0x00000128) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC10_b; + }; + + union + { + __IOM uint32_t MPFC11; /*!< (@ 0x0000012C) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC11_b; + }; + + union + { + __IOM uint32_t MPFC12; /*!< (@ 0x00000130) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC12_b; + }; + + union + { + __IOM uint32_t MPFC13; /*!< (@ 0x00000134) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC13_b; + }; + + union + { + __IOM uint32_t MPFC14; /*!< (@ 0x00000138) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC14_b; + }; + + union + { + __IOM uint32_t MPFC15; /*!< (@ 0x0000013C) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC15_b; + }; + __IM uint32_t RESERVED8[16]; + + union + { + __IOM uint32_t MLVC; /*!< (@ 0x00000180) MAC Link Verification Configuration Register + * (MLVC) */ + + struct + { + __IOM uint32_t LVT : 7; /*!< [6..0] LVT */ + uint32_t : 1; + __IOM uint32_t PASE : 1; /*!< [8..8] PASE */ + uint32_t : 7; + __IOM uint32_t PLV : 1; /*!< [16..16] PLV */ + uint32_t : 15; + } MLVC_b; + }; + + union + { + __IOM uint32_t MEEEC; /*!< (@ 0x00000184) MAC Energy Efficient Ethernet Configuration Register + * (MEEEC) */ + + struct + { + __IOM uint32_t LPITR : 1; /*!< [0..0] LPITR */ + uint32_t : 31; + } MEEEC_b; + }; + + union + { + __IOM uint32_t MLBC; /*!< (@ 0x00000188) MAC Loopback Configuration Register (MLBC) */ + + struct + { + __IOM uint32_t LBME : 1; /*!< [0..0] LBME */ + uint32_t : 31; + } MLBC_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t MXGMIIC; /*!< (@ 0x00000190) XGMII Configuration Register (MXGMIIC) */ + + struct + { + __IOM uint32_t LFS_TXRFS : 1; /*!< [0..0] LFS_TXRFS */ + __IOM uint32_t LFS_TXIDLE : 1; /*!< [1..1] LFS_TXIDLE */ + uint32_t : 30; + } MXGMIIC_b; + }; + + union + { + __IOM uint32_t MPCH; /*!< (@ 0x00000194) XGMII PCH Configuration Register (MPCH) */ + + struct + { + __IOM uint32_t TXPCH_M : 1; /*!< [0..0] TXPCH_M */ + uint32_t : 1; + __IOM uint32_t TXPCH_ETYPE : 2; /*!< [3..2] TXPCH_ETYPE */ + __IOM uint32_t TXPCH_PID : 4; /*!< [7..4] TXPCH_PID */ + __IOM uint32_t IETPTE : 1; /*!< [8..8] IETPTE */ + __IOM uint32_t CTPTE : 1; /*!< [9..9] CTPTE */ + __IOM uint32_t IETRIOD : 1; /*!< [10..10] IETRIOD */ + __IOM uint32_t CTRIOD : 1; /*!< [11..11] CTRIOD */ + uint32_t : 4; + __IOM uint32_t RXPCH_TSM : 1; /*!< [16..16] RXPCH_TSM */ + __IOM uint32_t RPHCRCD : 1; /*!< [17..17] RPHCRCD */ + uint32_t : 14; + } MPCH_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t MANM; /*!< (@ 0x0000019C) Auto-Negotiation Message Register (MANM) */ + + struct + { + __IOM uint32_t RX_AN_MES : 16; /*!< [15..0] RX_AN_MES */ + uint32_t : 16; + } MANM_b; + }; + __IM uint32_t RESERVED11[24]; + + union + { + __IOM uint32_t MEIS; /*!< (@ 0x00000200) MAC Error Interrupt Status Register (MEIS) */ + + struct + { + __IOM uint32_t TSLS : 1; /*!< [0..0] TSLS */ + __IOM uint32_t TIES : 1; /*!< [1..1] TIES */ + __IOM uint32_t PRES : 1; /*!< [2..2] PRES */ + __IOM uint32_t PFRROS : 1; /*!< [3..3] PFRROS */ + __IOM uint32_t FCDS : 1; /*!< [4..4] FCDS */ + __IOM uint32_t TCES : 1; /*!< [5..5] TCES */ + __IOM uint32_t TBCIS : 1; /*!< [6..6] TBCIS */ + __IOM uint32_t BFES : 1; /*!< [7..7] BFES */ + __IOM uint32_t FCES : 1; /*!< [8..8] FCES */ + __IOM uint32_t REOES : 1; /*!< [9..9] REOES */ + __IOM uint32_t RPOES : 1; /*!< [10..10] RPOES */ + __IOM uint32_t RPCRES : 1; /*!< [11..11] RPCRES */ + __IOM uint32_t CTLES0 : 1; /*!< [12..12] CTLES0 */ + __IOM uint32_t CTLES1 : 1; /*!< [13..13] CTLES1 */ + uint32_t : 6; + __IOM uint32_t PDES : 1; /*!< [20..20] PDES */ + __IOM uint32_t PNAES : 1; /*!< [21..21] PNAES */ + __IOM uint32_t FCMCES : 1; /*!< [22..22] FCMCES */ + __IOM uint32_t FFMES : 1; /*!< [23..23] FFMES */ + __IOM uint32_t CFCES : 1; /*!< [24..24] CFCES */ + __IOM uint32_t FRCES : 1; /*!< [25..25] FRCES */ + __IOM uint32_t RPOOMS : 1; /*!< [26..26] RPOOMS */ + __IOM uint32_t FFS : 1; /*!< [27..27] FFS */ + __IOM uint32_t FUES : 1; /*!< [28..28] FUES */ + __IOM uint32_t FOES : 1; /*!< [29..29] FOES */ + uint32_t : 2; + } MEIS_b; + }; + + union + { + __IOM uint32_t MEIE; /*!< (@ 0x00000204) MAC Error Interrupt Enable Register (MEIE) */ + + struct + { + __IOM uint32_t TSLE : 1; /*!< [0..0] TSLE */ + __IOM uint32_t TIEE : 1; /*!< [1..1] TIEE */ + __IOM uint32_t PMSEE : 1; /*!< [2..2] PMSEE */ + __IOM uint32_t PFRROE : 1; /*!< [3..3] PFRROE */ + __IOM uint32_t FCDE : 1; /*!< [4..4] FCDE */ + __IOM uint32_t TCEE : 1; /*!< [5..5] TCEE */ + __IOM uint32_t TBCIE : 1; /*!< [6..6] TBCIE */ + __IOM uint32_t BFEE : 1; /*!< [7..7] BFEE */ + __IOM uint32_t FCEE : 1; /*!< [8..8] FCEE */ + __IOM uint32_t REOEE : 1; /*!< [9..9] REOEE */ + __IOM uint32_t RPOEE : 1; /*!< [10..10] RPOEE */ + __IOM uint32_t RPCREE : 1; /*!< [11..11] RPCREE */ + __IOM uint32_t CTLEE0 : 1; /*!< [12..12] CTLEE0 */ + __IOM uint32_t CTLEE1 : 1; /*!< [13..13] CTLEE1 */ + uint32_t : 6; + __IOM uint32_t PDEE : 1; /*!< [20..20] PDEE */ + __IOM uint32_t PNAEE : 1; /*!< [21..21] PNAEE */ + __IOM uint32_t FCMCEE : 1; /*!< [22..22] FCMCEE */ + __IOM uint32_t FFMEE : 1; /*!< [23..23] FFMEE */ + __IOM uint32_t CFCEE : 1; /*!< [24..24] CFCEE */ + __IOM uint32_t FRCEE : 1; /*!< [25..25] FRCEE */ + __IOM uint32_t RPOOME : 1; /*!< [26..26] RPOOME */ + __IOM uint32_t FFE : 1; /*!< [27..27] FFE */ + __IOM uint32_t FUEE : 1; /*!< [28..28] FUEE */ + __IOM uint32_t FOEE : 1; /*!< [29..29] FOEE */ + uint32_t : 2; + } MEIE_b; + }; + + union + { + __IOM uint32_t MEID; /*!< (@ 0x00000208) MAC Error Interrupt Disable Register (MEID) */ + + struct + { + __IOM uint32_t TSLD : 1; /*!< [0..0] TSLD */ + __IOM uint32_t TIED : 1; /*!< [1..1] TIED */ + __IOM uint32_t PRED : 1; /*!< [2..2] PRED */ + __IOM uint32_t PFRROD : 1; /*!< [3..3] PFRROD */ + __IOM uint32_t FCDD : 1; /*!< [4..4] FCDD */ + __IOM uint32_t TCED : 1; /*!< [5..5] TCED */ + __IOM uint32_t TBCID : 1; /*!< [6..6] TBCID */ + __IOM uint32_t BFED : 1; /*!< [7..7] BFED */ + __IOM uint32_t FCED : 1; /*!< [8..8] FCED */ + __IOM uint32_t REOED : 1; /*!< [9..9] REOED */ + __IOM uint32_t RPOED : 1; /*!< [10..10] RPOED */ + __IOM uint32_t RPCRED : 1; /*!< [11..11] RPCRED */ + __IOM uint32_t CTLED0 : 1; /*!< [12..12] CTLED0 */ + __IOM uint32_t CTLED1 : 1; /*!< [13..13] CTLED1 */ + uint32_t : 6; + __IOM uint32_t PDED : 1; /*!< [20..20] PDED */ + __IOM uint32_t PNAED : 1; /*!< [21..21] PNAED */ + __IOM uint32_t FCMCED : 1; /*!< [22..22] FCMCED */ + __IOM uint32_t FFMED : 1; /*!< [23..23] FFMED */ + __IOM uint32_t CFCED : 1; /*!< [24..24] CFCED */ + __IOM uint32_t FRCED : 1; /*!< [25..25] FRCED */ + __IOM uint32_t RPOOMD : 1; /*!< [26..26] RPOOMD */ + __IOM uint32_t FFD : 1; /*!< [27..27] FFD */ + __IOM uint32_t FUED : 1; /*!< [28..28] FUED */ + __IOM uint32_t FOED : 1; /*!< [29..29] FOED */ + uint32_t : 2; + } MEID_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t MMIS0; /*!< (@ 0x00000210) MAC Monitoring Interrupt Status Register 0 (MMIS0) */ + + struct + { + __IOM uint32_t PLSCS : 1; /*!< [0..0] PLSCS */ + __IOM uint32_t PIDS : 1; /*!< [1..1] PIDS */ + __IOM uint32_t LVSS : 1; /*!< [2..2] LVSS */ + __IOM uint32_t LVFS : 1; /*!< [3..3] LVFS */ + __IOM uint32_t VFRS : 1; /*!< [4..4] VFRS */ + uint32_t : 1; + __IOM uint32_t ANDETS : 1; /*!< [6..6] ANDETS */ + uint32_t : 1; + __IOM uint32_t XLFDS : 1; /*!< [8..8] XLFDS */ + __IOM uint32_t XLFES : 1; /*!< [9..9] XLFES */ + __IOM uint32_t XLFSDS : 1; /*!< [10..10] XLFSDS */ + __IOM uint32_t XRFSDS : 1; /*!< [11..11] XRFSDS */ + __IOM uint32_t XLISDS : 1; /*!< [12..12] XLISDS */ + uint32_t : 19; + } MMIS0_b; + }; + + union + { + __IOM uint32_t MMIE0; /*!< (@ 0x00000214) MAC Monitoring Interrupt Enable Register 0 (MMIE0) */ + + struct + { + __IOM uint32_t PLSCE : 1; /*!< [0..0] PLSCE */ + __IOM uint32_t PIDE : 1; /*!< [1..1] PIDE */ + __IOM uint32_t LVSE : 1; /*!< [2..2] LVSE */ + __IOM uint32_t LVFE : 1; /*!< [3..3] LVFE */ + __IOM uint32_t VFRE : 1; /*!< [4..4] VFRE */ + uint32_t : 1; + __IOM uint32_t ANDETE : 1; /*!< [6..6] ANDETE */ + uint32_t : 1; + __IOM uint32_t XLFDE : 1; /*!< [8..8] XLFDE */ + __IOM uint32_t XLFEE : 1; /*!< [9..9] XLFEE */ + __IOM uint32_t XLFSDE : 1; /*!< [10..10] XLFSDE */ + __IOM uint32_t XRFSDE : 1; /*!< [11..11] XRFSDE */ + __IOM uint32_t XLISDE : 1; /*!< [12..12] XLISDE */ + uint32_t : 19; + } MMIE0_b; + }; + + union + { + __IOM uint32_t MMID0; /*!< (@ 0x00000218) MAC Monitoring Interrupt Disable Register 0 (MMID0) */ + + struct + { + __IOM uint32_t PLSCD : 1; /*!< [0..0] PLSCD */ + __IOM uint32_t PIDD : 1; /*!< [1..1] PIDD */ + __IOM uint32_t LVSD : 1; /*!< [2..2] LVSD */ + __IOM uint32_t LVFD : 1; /*!< [3..3] LVFD */ + __IOM uint32_t VFRD : 1; /*!< [4..4] VFRD */ + uint32_t : 1; + __IOM uint32_t ANDETD : 1; /*!< [6..6] ANDETD */ + uint32_t : 1; + __IOM uint32_t XLFDD : 1; /*!< [8..8] XLFDD */ + __IOM uint32_t XLFED : 1; /*!< [9..9] XLFED */ + __IOM uint32_t XLFSDD : 1; /*!< [10..10] XLFSDD */ + __IOM uint32_t XRFSDD : 1; /*!< [11..11] XRFSDD */ + __IOM uint32_t XLISDD : 1; /*!< [12..12] XLISDD */ + uint32_t : 19; + } MMID0_b; + }; + __IM uint32_t RESERVED13; + + union + { + __IOM uint32_t MMIS1; /*!< (@ 0x00000220) MAC Monitoring Interrupt Status Register 1 (MMIS1) */ + + struct + { + __IOM uint32_t PRACS : 1; /*!< [0..0] PRACS */ + __IOM uint32_t PWACS : 1; /*!< [1..1] PWACS */ + __IOM uint32_t PAACS : 1; /*!< [2..2] PAACS */ + __IOM uint32_t PPRACS : 1; /*!< [3..3] PPRACS */ + uint32_t : 28; + } MMIS1_b; + }; + + union + { + __IOM uint32_t MMIE1; /*!< (@ 0x00000224) MAC Monitoring Interrupt Enable Register 1 (MMIE1) */ + + struct + { + __IOM uint32_t PRACE : 1; /*!< [0..0] PRACE */ + __IOM uint32_t PWACE : 1; /*!< [1..1] PWACE */ + __IOM uint32_t PAACE : 1; /*!< [2..2] PAACE */ + __IOM uint32_t PPRACE : 1; /*!< [3..3] PPRACE */ + uint32_t : 28; + } MMIE1_b; + }; + + union + { + __IOM uint32_t MMID1; /*!< (@ 0x00000228) MAC Monitoring Interrupt Disable Register 1 (MMID1) */ + + struct + { + __IOM uint32_t PRACD : 1; /*!< [0..0] PRACD */ + __IOM uint32_t PWACD : 1; /*!< [1..1] PWACD */ + __IOM uint32_t PAACD : 1; /*!< [2..2] PAACD */ + __IOM uint32_t PPRACD : 1; /*!< [3..3] PPRACD */ + uint32_t : 28; + } MMID1_b; + }; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t MMIS2; /*!< (@ 0x00000230) MAC Monitoring Interrupt Status Register 2 (MMIS2) */ + + struct + { + __IOM uint32_t MPDIS : 1; /*!< [0..0] MPDIS */ + __IOM uint32_t LPIAIS : 1; /*!< [1..1] LPIAIS */ + __IOM uint32_t LPIDIS : 1; /*!< [2..2] LPIDIS */ + uint32_t : 29; + } MMIS2_b; + }; + + union + { + __IOM uint32_t MMIE2; /*!< (@ 0x00000234) MAC Monitoring Interrupt Enable Register 2 (MMIE2) */ + + struct + { + __IOM uint32_t MPDIE : 1; /*!< [0..0] MPDIE */ + __IOM uint32_t LPIAIE : 1; /*!< [1..1] LPIAIE */ + __IOM uint32_t LPIDIE : 1; /*!< [2..2] LPIDIE */ + uint32_t : 29; + } MMIE2_b; + }; + + union + { + __IOM uint32_t MMID2; /*!< (@ 0x00000238) MAC Monitoring Interrupt Disable Register 2 (MMID2) */ + + struct + { + __IOM uint32_t MPDID : 1; /*!< [0..0] MPDID */ + __IOM uint32_t LPIAID : 1; /*!< [1..1] LPIAID */ + __IOM uint32_t LPIDID : 1; /*!< [2..2] LPIDID */ + uint32_t : 29; + } MMID2_b; + }; + __IM uint32_t RESERVED15[49]; + + union + { + __IOM uint32_t MMPFTCT; /*!< (@ 0x00000300) MAC Manual Pause Frame Transmit Counter Register + * (MMPFTCT) */ + + struct + { + __IOM uint32_t MPFTC : 16; /*!< [15..0] MPFTC */ + uint32_t : 16; + } MMPFTCT_b; + }; + + union + { + __IOM uint32_t MAPFTCT; /*!< (@ 0x00000304) MAC Automatic Pause Frame Transmit Counter Register + * (MAPFTCT) */ + + struct + { + __IOM uint32_t APFTC : 16; /*!< [15..0] APFTC */ + uint32_t : 16; + } MAPFTCT_b; + }; + + union + { + __IOM uint32_t MPFRCT; /*!< (@ 0x00000308) MAC Pause Frame Receive Counter Register (MPFRCT) */ + + struct + { + __IOM uint32_t PFRC : 16; /*!< [15..0] PFRC */ + uint32_t : 16; + } MPFRCT_b; + }; + + union + { + __IOM uint32_t MFCICT; /*!< (@ 0x0000030C) MAC False Carrier Indication Counter Register + * (MFCICT) */ + + struct + { + __IOM uint32_t FCIC : 16; /*!< [15..0] FCIC */ + uint32_t : 16; + } MFCICT_b; + }; + + union + { + __IOM uint32_t MEEECT; /*!< (@ 0x00000310) MAC Energy Efficient Ethernet Counter Register + * (MEEECT) */ + + struct + { + __IOM uint32_t EEERC : 16; /*!< [15..0] EEERC */ + uint32_t : 16; + } MEEECT_b; + }; + __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint32_t MMPCFTCT0; /*!< (@ 0x00000320) MAC Manual PFC Frame Transmit Counter Register + * (MMPCFTCTt) (t = 0, 1) */ + + struct + { + __IOM uint32_t MPCFCTC : 16; /*!< [15..0] MPCFCTC */ + uint32_t : 16; + } MMPCFTCT0_b; + }; + + union + { + __IOM uint32_t MMPCFTCT1; /*!< (@ 0x00000324) MAC Manual PFC Frame Transmit Counter Register + * (MMPCFTCTt) (t = 0, 1) */ + + struct + { + __IOM uint32_t MPCFCTC : 16; /*!< [15..0] MPCFCTC */ + uint32_t : 16; + } MMPCFTCT1_b; + }; + __IM uint32_t RESERVED17[2]; + + union + { + __IOM uint32_t MAPCFTCT0; /*!< (@ 0x00000330) MAC Automatic PFC Frame Transmit Counter Register + * (MAPCFTCTt) (t = 0, 1) */ + + struct + { + __IOM uint32_t APCFCTC : 16; /*!< [15..0] APCFCTC */ + uint32_t : 16; + } MAPCFTCT0_b; + }; + + union + { + __IOM uint32_t MAPCFTCT1; /*!< (@ 0x00000334) MAC Automatic PFC Frame Transmit Counter Register + * (MAPCFTCTt) (t = 0, 1) */ + + struct + { + __IOM uint32_t APCFCTC : 16; /*!< [15..0] APCFCTC */ + uint32_t : 16; + } MAPCFTCT1_b; + }; + __IM uint32_t RESERVED18[2]; + + union + { + __IOM uint32_t MPCFRCT0; /*!< (@ 0x00000340) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT0_b; + }; + + union + { + __IOM uint32_t MPCFRCT1; /*!< (@ 0x00000344) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT1_b; + }; + + union + { + __IOM uint32_t MPCFRCT2; /*!< (@ 0x00000348) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT2_b; + }; + + union + { + __IOM uint32_t MPCFRCT3; /*!< (@ 0x0000034C) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT3_b; + }; + + union + { + __IOM uint32_t MPCFRCT4; /*!< (@ 0x00000350) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT4_b; + }; + + union + { + __IOM uint32_t MPCFRCT5; /*!< (@ 0x00000354) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT5_b; + }; + + union + { + __IOM uint32_t MPCFRCT6; /*!< (@ 0x00000358) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT6_b; + }; + + union + { + __IOM uint32_t MPCFRCT7; /*!< (@ 0x0000035C) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT7_b; + }; + + union + { + __IOM uint32_t MROVFC; /*!< (@ 0x00000360) Receive Overflow Counter Register (MROVFC) */ + + struct + { + __IOM uint32_t ROVFC : 32; /*!< [31..0] ROVFC */ + } MROVFC_b; + }; + + union + { + __IOM uint32_t MRHCRCEC; /*!< (@ 0x00000364) Reception Header-CRC(PCH CRC) Error Counter Register + * (MRHCRCEC) */ + + struct + { + __IOM uint32_t RHCRCEC : 16; /*!< [15..0] RHCRCEC */ + uint32_t : 16; + } MRHCRCEC_b; + }; + __IM uint32_t RESERVED19[40]; + + union + { + __IOM uint32_t MRGFCE; /*!< (@ 0x00000408) RMAC Received Good Frame Counter E-Frames Register + * (MRGFCE) */ + + struct + { + __IOM uint32_t RGFNE : 32; /*!< [31..0] RGFNE */ + } MRGFCE_b; + }; + + union + { + __IOM uint32_t MRGFCP; /*!< (@ 0x0000040C) RMAC Received Good Frame Counter P-Frames Register + * (MRGFCP) */ + + struct + { + __IOM uint32_t RGFNP : 32; /*!< [31..0] RGFNP */ + } MRGFCP_b; + }; + + union + { + __IOM uint32_t MRBFC; /*!< (@ 0x00000410) Register (MRBFC) */ + + struct + { + __IOM uint32_t RBFN : 32; /*!< [31..0] RBFN */ + } MRBFC_b; + }; + + union + { + __IOM uint32_t MRMFC; /*!< (@ 0x00000414) RMAC Received Good Multicast Frame Counter Register + * (MRMFC) */ + + struct + { + __IOM uint32_t RMFN : 32; /*!< [31..0] RMFN */ + } MRMFC_b; + }; + + union + { + __IOM uint32_t MRUFC; /*!< (@ 0x00000418) RMAC Received Good Unicast Frame Counter Register + * (MRUFC) */ + + struct + { + __IOM uint32_t RUFN : 32; /*!< [31..0] RUFN */ + } MRUFC_b; + }; + + union + { + __IOM uint32_t MRPEFC; /*!< (@ 0x0000041C) Register (MRPEFC) */ + + struct + { + __IOM uint32_t RPEFN : 16; /*!< [15..0] RPEFN */ + uint32_t : 16; + } MRPEFC_b; + }; + + union + { + __IOM uint32_t MRNEFC; /*!< (@ 0x00000420) Register (MRNEFC) */ + + struct + { + __IOM uint32_t RNEFN : 16; /*!< [15..0] RNEFN */ + uint32_t : 16; + } MRNEFC_b; + }; + + union + { + __IOM uint32_t MRFMEFC; /*!< (@ 0x00000424) Register (MRFMEFC) */ + + struct + { + __IOM uint32_t RFMEFN : 32; /*!< [31..0] RFMEFN */ + } MRFMEFC_b; + }; + + union + { + __IOM uint32_t MRFFMEFC; /*!< (@ 0x00000428) Register (MRFFMEFC) */ + + struct + { + __IOM uint32_t RFFMEFN : 16; /*!< [15..0] RFFMEFN */ + uint32_t : 16; + } MRFFMEFC_b; + }; + + union + { + __IOM uint32_t MRCFCEFC; /*!< (@ 0x0000042C) Register (MRCFCEFC) */ + + struct + { + __IOM uint32_t RCFCEFN : 16; /*!< [15..0] RCFCEFN */ + uint32_t : 16; + } MRCFCEFC_b; + }; + + union + { + __IOM uint32_t MRFCEFC; /*!< (@ 0x00000430) Register (MRFCEFC) */ + + struct + { + __IOM uint32_t RFCEFN : 16; /*!< [15..0] RFCEFN */ + uint32_t : 16; + } MRFCEFC_b; + }; + + union + { + __IOM uint32_t MRRCFEFC; /*!< (@ 0x00000434) Register (MRRCFEFC) */ + + struct + { + __IOM uint32_t RRCFEFN : 16; /*!< [15..0] RRCFEFN */ + uint32_t : 16; + } MRRCFEFC_b; + }; + + union + { + __IOM uint32_t MRFC; /*!< (@ 0x00000438) Register (MRFC) */ + + struct + { + __IOM uint32_t RFN : 32; /*!< [31..0] RFN */ + } MRFC_b; + }; + + union + { + __IOM uint32_t MRGUEFC; /*!< (@ 0x0000043C) RMAC Received Good Undersize Error Frame Count + * Register (MRGUEFC) */ + + struct + { + __IOM uint32_t RUEFN : 32; /*!< [31..0] RUEFN */ + } MRGUEFC_b; + }; + + union + { + __IOM uint32_t MRBUEFC; /*!< (@ 0x00000440) RMAC Received bad Undersize Error Frame Count + * Register (MRBUEFC) */ + + struct + { + __IOM uint32_t RUEFN : 32; /*!< [31..0] RUEFN */ + } MRBUEFC_b; + }; + + union + { + __IOM uint32_t MRGOEFC; /*!< (@ 0x00000444) Register (MRGOEFC) */ + + struct + { + __IOM uint32_t RGOEFN : 32; /*!< [31..0] RGOEFN */ + } MRGOEFC_b; + }; + + union + { + __IOM uint32_t MRBOEFC; /*!< (@ 0x00000448) Register (MRBOEFC) */ + + struct + { + __IOM uint32_t RBOEFN : 32; /*!< [31..0] RBOEFN */ + } MRBOEFC_b; + }; + + union + { + __IOM uint32_t MRXBCEU; /*!< (@ 0x0000044C) Register (MRXBCEU) */ + + struct + { + __IOM uint32_t RBNEU : 32; /*!< [31..0] RBNEU */ + } MRXBCEU_b; + }; + + union + { + __IOM uint32_t MRXBCEL; /*!< (@ 0x00000450) Register (MRXBCEL) */ + + struct + { + __IOM uint32_t RBNEL : 32; /*!< [31..0] RBNEL */ + } MRXBCEL_b; + }; + + union + { + __IOM uint32_t MRXBCPU; /*!< (@ 0x00000454) Register (MRXBCPU) */ + + struct + { + __IOM uint32_t RBNPU : 32; /*!< [31..0] RBNPU */ + } MRXBCPU_b; + }; + + union + { + __IOM uint32_t MRXBCPL; /*!< (@ 0x00000458) Register (MRXBCPL) */ + + struct + { + __IOM uint32_t RBNPL : 32; /*!< [31..0] RBNPL */ + } MRXBCPL_b; + }; + __IM uint32_t RESERVED20[43]; + + union + { + __IOM uint32_t MTGFCE; /*!< (@ 0x00000508) RMAC Transmitted Good Frame Counter E-Frames + * Register (MTGFCE) */ + + struct + { + __IOM uint32_t TGFNE : 32; /*!< [31..0] TGFNE */ + } MTGFCE_b; + }; + + union + { + __IOM uint32_t MTGFCP; /*!< (@ 0x0000050C) RMAC Transmitted Good Frame Counter P-Frames + * Register (MTGFCP) */ + + struct + { + __IOM uint32_t TGFNP : 32; /*!< [31..0] TGFNP */ + } MTGFCP_b; + }; + + union + { + __IOM uint32_t MTBFC; /*!< (@ 0x00000510) Register (MTBFC) */ + + struct + { + __IOM uint32_t TBFN : 32; /*!< [31..0] TBFN */ + } MTBFC_b; + }; + + union + { + __IOM uint32_t MTMFC; /*!< (@ 0x00000514) RMAC Transmitted Multicast Frame Counter Register + * (MTMFC) */ + + struct + { + __IOM uint32_t TMFN : 32; /*!< [31..0] TMFN */ + } MTMFC_b; + }; + + union + { + __IOM uint32_t MTUFC; /*!< (@ 0x00000518) Register (MTUFC) */ + + struct + { + __IOM uint32_t TUFN : 32; /*!< [31..0] TUFN */ + } MTUFC_b; + }; + + union + { + __IOM uint32_t MTEFC; /*!< (@ 0x0000051C) Register (MTEFC) */ + + struct + { + __IOM uint32_t TEFN : 16; /*!< [15..0] TEFN */ + uint32_t : 16; + } MTEFC_b; + }; + + union + { + __IOM uint32_t MTXBCEU; /*!< (@ 0x00000520) Register (MTXBCEU) */ + + struct + { + __IOM uint32_t TBNEU : 32; /*!< [31..0] TBNEU */ + } MTXBCEU_b; + }; + + union + { + __IOM uint32_t MTXBCEL; /*!< (@ 0x00000524) Register (MTXBCEL) */ + + struct + { + __IOM uint32_t TBNEL : 32; /*!< [31..0] TBNEL */ + } MTXBCEL_b; + }; + + union + { + __IOM uint32_t MTXBCPU; /*!< (@ 0x00000528) RMAC Transmitted Byte Counter P-Frames Upper + * Side Register (MTXBCPU) */ + + struct + { + __IOM uint32_t TBNPU : 32; /*!< [31..0] TBNPU */ + } MTXBCPU_b; + }; + + union + { + __IOM uint32_t MTXBCPL; /*!< (@ 0x0000052C) RMAC Transmitted Byte Counter P-Frames Lower + * Side Register (MTXBCPL) */ + + struct + { + __IOM uint32_t TBNPL : 32; /*!< [31..0] TBNPL */ + } MTXBCPL_b; + }; +} R_RMAC0_Type; /*!< Size = 1328 (0x530) */ + +/* =========================================================================================================================== */ +/* ================ R_TCM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Tightly Coupled Memory (R_TCM) + */ + +typedef struct /*!< (@ 0x4001C800) R_TCM Structure */ +{ + union + { + __IOM uint16_t TCMPRCR_S; /*!< (@ 0x00000000) TCM Protection Control Register for Secure */ + + struct + { + __IOM uint16_t PR : 1; /*!< [0..0] Register Write Control */ + uint16_t : 7; + __IOM uint16_t KW : 8; /*!< [15..8] Write Key Code */ + } TCMPRCR_S_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TCMPRCR_NS; /*!< (@ 0x00000004) TCM Protection Control Register for Non-Secure */ + + struct + { + __IOM uint16_t PR : 1; /*!< [0..0] Register Write Control */ + uint16_t : 7; + __IOM uint16_t KW : 8; /*!< [15..8] Write Key Code */ + } TCMPRCR_NS_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint8_t TCMCRC; /*!< (@ 0x00000010) TCM Control Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after ECC error detection */ + uint8_t : 1; + __IOM uint8_t ECCMOD : 2; /*!< [3..2] ECC Operating Mode Select */ + __IOM uint8_t E1STSEN : 1; /*!< [4..4] ECC 1-Bit Error Information Update Enable */ + uint8_t : 2; + __IOM uint8_t TSTBYP : 1; /*!< [7..7] ECC Test Enable / ECC Bypass Select */ + } TCMCRC_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t TCMCRS; /*!< (@ 0x00000014) TCM Control Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after ECC error detection */ + uint8_t : 1; + __IOM uint8_t ECCMOD : 2; /*!< [3..2] ECC Operating Mode Select */ + __IOM uint8_t E1STSEN : 1; /*!< [4..4] ECC 1-Bit Error Information Update Enable */ + uint8_t : 2; + __IOM uint8_t TSTBYP : 1; /*!< [7..7] ECC Test Enable / ECC Bypass Select */ + } TCMCRS_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[10]; + + union + { + __IOM uint16_t TCMESR; /*!< (@ 0x00000040) TCM Error Status Register */ + + struct + { + __IOM uint16_t ERRC0 : 1; /*!< [0..0] C-TCM 1-bit ECC Error Status */ + __IOM uint16_t ERRC1 : 1; /*!< [1..1] C-TCM 2-bit ECC Error Status */ + __IOM uint16_t ERRS0 : 1; /*!< [2..2] S-TCM 1-bit ECC Error Status */ + __IOM uint16_t ERRS1 : 1; /*!< [3..3] S-TCM 2-bit ECC Error Status */ + uint16_t : 12; + } TCMESR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9; + + union + { + __IOM uint16_t TCMESCLR; /*!< (@ 0x00000048) TCM Error Status Clear Register */ + + struct + { + __IOM uint16_t CLRC0 : 1; /*!< [0..0] TCM 1-bit ECC Error Status Clear */ + __IOM uint16_t CLRC1 : 1; /*!< [1..1] TCM 2-bit ECC Error Status Clear */ + __IOM uint16_t CLRS0 : 1; /*!< [2..2] S-TCM 1-bit ECC Error Status Clear */ + __IOM uint16_t CLRS1 : 1; /*!< [3..3] S-TCM 2-bit ECC Error Status Clear */ + uint16_t : 12; + } TCMESCLR_b; + }; + __IM uint16_t RESERVED10; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t TCMEARC0; /*!< (@ 0x00000050) TCM Error Address Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t EAR : 16; /*!< [17..2] When an SRAM error occurs, it stores an error address */ + uint32_t : 14; + } TCMEARC0_b; + }; + + union + { + __IOM uint32_t TCMEARC1; /*!< (@ 0x00000054) TCM Error Address Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t EAR : 16; /*!< [17..2] When an SRAM error occurs, it stores an error address */ + uint32_t : 14; + } TCMEARC1_b; + }; + + union + { + __IOM uint32_t TCMEARS0; /*!< (@ 0x00000058) TCM Error Address Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t EAR : 16; /*!< [17..2] When an SRAM error occurs, it stores an error address */ + uint32_t : 14; + } TCMEARS0_b; + }; + + union + { + __IOM uint32_t TCMEARS1; /*!< (@ 0x0000005C) TCM Error Address Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t EAR : 16; /*!< [17..2] When an SRAM error occurs, it stores an error address */ + uint32_t : 14; + } TCMEARS1_b; + }; +} R_TCM_Type; /*!< Size = 96 (0x60) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #if defined(_RA_TZ_NONSECURE) + #define BASE_NS_OFFSET (BSP_FEATURE_TZ_NS_OFFSET) + #else + #define BASE_NS_OFFSET 0U + #endif + + #define R_ACMPHS0_BASE (0x40236000UL + BASE_NS_OFFSET) + #define R_ACMPHS1_BASE (0x40236100UL + BASE_NS_OFFSET) + #define R_ACMPHS2_BASE (0x40236200UL + BASE_NS_OFFSET) + #define R_ACMPHS3_BASE (0x40236300UL + BASE_NS_OFFSET) + #define R_ACMPHS4_BASE (0x40236400UL + BASE_NS_OFFSET) + #define R_ACMPHS5_BASE (0x40236500UL + BASE_NS_OFFSET) + #define R_PSCU_BASE (0x40204000UL + BASE_NS_OFFSET) + #define R_BUS_BASE (0x40003000UL + BASE_NS_OFFSET) + #define R_CAC_BASE (0x40202400UL + BASE_NS_OFFSET) + #define R_CANFD_BASE (0x40380000UL + BASE_NS_OFFSET) + #define R_CANFD1_BASE (0x40382000UL + BASE_NS_OFFSET) + #define R_CRC_BASE (0x40310000UL + BASE_NS_OFFSET) + #define R_DAC_B0_BASE (0x40233000UL + BASE_NS_OFFSET) + #define R_DAC_B1_BASE (0x40233100UL + BASE_NS_OFFSET) + #define R_DEBUG_BASE (0x4001B000UL + BASE_NS_OFFSET) + #define R_DMA_BASE (0x4000A800UL + BASE_NS_OFFSET) + #define R_DMAC0_BASE (0x4000A000UL + BASE_NS_OFFSET) + #define R_DMAC1_BASE (0x4000A040UL + BASE_NS_OFFSET) + #define R_DMAC2_BASE (0x4000A080UL + BASE_NS_OFFSET) + #define R_DMAC3_BASE (0x4000A0C0UL + BASE_NS_OFFSET) + #define R_DMAC4_BASE (0x4000A100UL + BASE_NS_OFFSET) + #define R_DMAC5_BASE (0x4000A140UL + BASE_NS_OFFSET) + #define R_DMAC6_BASE (0x4000A180UL + BASE_NS_OFFSET) + #define R_DMAC7_BASE (0x4000A1C0UL + BASE_NS_OFFSET) + #define R_DOC_BASE (0x40311000UL + BASE_NS_OFFSET) + #define R_DRW_BASE (0x40444000UL + BASE_NS_OFFSET) + #define R_DTC_BASE (0x4000AC00UL + BASE_NS_OFFSET) + #define R_ELC_BASE (0x40201000UL + BASE_NS_OFFSET) + #define R_ETHERC_EDMAC_BASE (0x40354000UL + BASE_NS_OFFSET) + #define R_GLCDC_BASE (0x40342000UL + BASE_NS_OFFSET) + #define R_GPT0_BASE (0x40322000UL + BASE_NS_OFFSET) + #define R_GPT1_BASE (0x40322100UL + BASE_NS_OFFSET) + #define R_GPT2_BASE (0x40322200UL + BASE_NS_OFFSET) + #define R_GPT3_BASE (0x40322300UL + BASE_NS_OFFSET) + #define R_GPT4_BASE (0x40322400UL + BASE_NS_OFFSET) + #define R_GPT5_BASE (0x40322500UL + BASE_NS_OFFSET) + #define R_GPT6_BASE (0x40322600UL + BASE_NS_OFFSET) + #define R_GPT7_BASE (0x40322700UL + BASE_NS_OFFSET) + #define R_GPT8_BASE (0x40322800UL + BASE_NS_OFFSET) + #define R_GPT9_BASE (0x40322900UL + BASE_NS_OFFSET) + #define R_GPT10_BASE (0x40322A00UL + BASE_NS_OFFSET) + #define R_GPT11_BASE (0x40322B00UL + BASE_NS_OFFSET) + #define R_GPT12_BASE (0x40322C00UL + BASE_NS_OFFSET) + #define R_GPT13_BASE (0x40322D00UL + BASE_NS_OFFSET) + #define R_GPT_GTCLK_BASE (0x40323F10UL + BASE_NS_OFFSET) + #define R_GPT_ODC_BASE (0x40324000UL + BASE_NS_OFFSET) + #define R_GPT_OPS_BASE (0x40323F00UL + BASE_NS_OFFSET) + #define R_GPT_POEG0_BASE (0x40212000UL + BASE_NS_OFFSET) + #define R_GPT_POEG1_BASE (0x40212100UL + BASE_NS_OFFSET) + #define R_GPT_POEG2_BASE (0x40212200UL + BASE_NS_OFFSET) + #define R_GPT_POEG3_BASE (0x40212300UL + BASE_NS_OFFSET) + #define R_ICU_BASE (0x40006000UL + BASE_NS_OFFSET) + #define R_IIC0_BASE (0x4025E000UL + BASE_NS_OFFSET) + #define R_IIC1_BASE (0x4025E100UL + BASE_NS_OFFSET) + #define R_IIC2_BASE (0x4025E200UL + BASE_NS_OFFSET) + #define R_IWDT_BASE (0x40202200UL + BASE_NS_OFFSET) + #define R_I3C0_BASE (0x4035F000UL + BASE_NS_OFFSET) + #define R_I3C1_BASE (0x4035F100UL + BASE_NS_OFFSET) + #define R_MPU_MMPU_BASE (0x40000000UL + BASE_NS_OFFSET) + #define R_MPU_SPMON_BASE (0x40000D00UL + BASE_NS_OFFSET) + #define R_MSTP_BASE (0x40203000UL + BASE_NS_OFFSET) + #define R_PORT0_BASE (0x40400000UL + BASE_NS_OFFSET) + #define R_PORT1_BASE (0x40400020UL + BASE_NS_OFFSET) + #define R_PORT2_BASE (0x40400040UL + BASE_NS_OFFSET) + #define R_PORT3_BASE (0x40400060UL + BASE_NS_OFFSET) + #define R_PORT4_BASE (0x40400080UL + BASE_NS_OFFSET) + #define R_PORT5_BASE (0x404000A0UL + BASE_NS_OFFSET) + #define R_PORT6_BASE (0x404000C0UL + BASE_NS_OFFSET) + #define R_PORT7_BASE (0x404000E0UL + BASE_NS_OFFSET) + #define R_PORT8_BASE (0x40400100UL + BASE_NS_OFFSET) + #define R_PORT9_BASE (0x40400120UL + BASE_NS_OFFSET) + #define R_PORT10_BASE (0x40400140UL + BASE_NS_OFFSET) + #define R_PORT11_BASE (0x40400160UL + BASE_NS_OFFSET) + #define R_PORT12_BASE (0x40400180UL + BASE_NS_OFFSET) + #define R_PORT13_BASE (0x404001A0UL + BASE_NS_OFFSET) + #define R_PORT14_BASE (0x404001C0UL + BASE_NS_OFFSET) + #define R_PFS_BASE (0x40400800UL + BASE_NS_OFFSET) + #define R_PMISC_BASE (0x40400D00UL + BASE_NS_OFFSET) + #define R_RTC_BASE (0x40202000UL + BASE_NS_OFFSET) + #define R_SCI0_BASE (0x40358000UL + BASE_NS_OFFSET) + #define R_SCI1_BASE (0x40358100UL + BASE_NS_OFFSET) + #define R_SCI2_BASE (0x40358200UL + BASE_NS_OFFSET) + #define R_SCI3_BASE (0x40358300UL + BASE_NS_OFFSET) + #define R_SCI4_BASE (0x40358400UL + BASE_NS_OFFSET) + #define R_SCI5_BASE (0x40358500UL + BASE_NS_OFFSET) + #define R_SCI6_BASE (0x40358600UL + BASE_NS_OFFSET) + #define R_SCI7_BASE (0x40358700UL + BASE_NS_OFFSET) + #define R_SCI8_BASE (0x40358800UL + BASE_NS_OFFSET) + #define R_SCI9_BASE (0x40358900UL + BASE_NS_OFFSET) + #define R_SDHI0_BASE (0x40252000UL + BASE_NS_OFFSET) + #define R_SDHI1_BASE (0x40252400UL + BASE_NS_OFFSET) + #define R_SPI0_BASE (0x4035C000UL + BASE_NS_OFFSET) + #define R_SPI1_BASE (0x4035C100UL + BASE_NS_OFFSET) + #define R_SPI2_BASE (0x40072200UL + BASE_NS_OFFSET) + #define R_SRAM_BASE (0x40002000UL + BASE_NS_OFFSET) + #define R_SSI0_BASE (0x4025D000UL + BASE_NS_OFFSET) + #define R_SSI1_BASE (0x4025D100UL + BASE_NS_OFFSET) + #define R_SYSTEM_BASE (0x4001E000UL + BASE_NS_OFFSET) + #define R_TSN_CAL_BASE (0x02C1EDA0UL + BASE_NS_OFFSET) + #define R_TSN_CTRL_BASE (0x40235000UL + BASE_NS_OFFSET) + #define R_USB_FS0_BASE (0x40250000UL + BASE_NS_OFFSET) + #define R_VIN_BASE (0x40347400UL + BASE_NS_OFFSET) + #define R_WDT_BASE (0x40202600UL + BASE_NS_OFFSET) + #define R_CPSCU_BASE (0x40008000UL + BASE_NS_OFFSET) + #define R_ADC_B0_BASE (0x40338000UL + BASE_NS_OFFSET) + #define R_DOC_B_BASE (0x40311000UL + BASE_NS_OFFSET) + #define R_SCI_B0_BASE (0x40358000UL + BASE_NS_OFFSET) + #define R_SCI_B1_BASE (0x40358100UL + BASE_NS_OFFSET) + #define R_SCI_B2_BASE (0x40358200UL + BASE_NS_OFFSET) + #define R_SCI_B3_BASE (0x40358300UL + BASE_NS_OFFSET) + #define R_SCI_B4_BASE (0x40358400UL + BASE_NS_OFFSET) + #define R_SCI_B9_BASE (0x40358900UL + BASE_NS_OFFSET) + #define R_SPI_B0_BASE (0x4035C000UL + BASE_NS_OFFSET) + #define R_SPI_B1_BASE (0x4035C100UL + BASE_NS_OFFSET) + #define R_USB_HS0_BASE (0x40351000UL + BASE_NS_OFFSET) + #define R_XSPI0_BASE (0x40268000UL + BASE_NS_OFFSET) + #define R_XSPI1_BASE (0x40268400UL + BASE_NS_OFFSET) + #define R_MIPI_PHY_BASE (0x40346C00UL + BASE_NS_OFFSET) + #define R_MIPI_CSI_BASE (0x40347000UL + BASE_NS_OFFSET) + #define R_CEU_BASE (0x40348000UL + BASE_NS_OFFSET) + #define R_ULPT0_BASE (0x40220000UL + BASE_NS_OFFSET) + #define R_ULPT1_BASE (0x40220100UL + BASE_NS_OFFSET) + #define R_DEBUG_OCD_BASE (0x40011000UL + BASE_NS_OFFSET) + #define R_DOTF_BASE (0x40268800UL + BASE_NS_OFFSET) + #define R_AGTX0_BASE (0x40221000UL + BASE_NS_OFFSET) + #define R_AGTX1_BASE (0x40221100UL + BASE_NS_OFFSET) + #define R_AGTX2_BASE (0x40221200UL + BASE_NS_OFFSET) + #define R_AGTX3_BASE (0x40221300UL + BASE_NS_OFFSET) + #define R_AGTX4_BASE (0x40221400UL + BASE_NS_OFFSET) + #define R_AGTX5_BASE (0x40221500UL + BASE_NS_OFFSET) + #define R_AGTX6_BASE (0x40221600UL + BASE_NS_OFFSET) + #define R_AGTX7_BASE (0x40221700UL + BASE_NS_OFFSET) + #define R_AGTX8_BASE (0x40221800UL + BASE_NS_OFFSET) + #define R_AGTX9_BASE (0x40221900UL + BASE_NS_OFFSET) + #define R_COMA_BASE (0x403C9000UL + BASE_NS_OFFSET) + #define R_CPU_CTRL_BASE (0x4000F000UL + BASE_NS_OFFSET) + #define R_DOTF1_BASE (0x40268900UL + BASE_NS_OFFSET) + #define R_ECCMB0_BASE (0x4036F200UL + BASE_NS_OFFSET) + #define R_ECCMB1_BASE (0x4036F300UL + BASE_NS_OFFSET) + #define R_ESWM_BASE (0x403C8000UL + BASE_NS_OFFSET) + #define R_ETHA0_BASE (0x403CA000UL + BASE_NS_OFFSET) + #define R_ETHA1_BASE (0x403CC000UL + BASE_NS_OFFSET) + #define R_GPTP_BASE (0x403E0000UL + BASE_NS_OFFSET) + #define R_GWCA0_BASE (0x403CE000UL + BASE_NS_OFFSET) + #define R_IPC_BASE (0x40020000UL + BASE_NS_OFFSET) + #define R_MFWD_BASE (0x403C0000UL + BASE_NS_OFFSET) + #define R_MIPI_DSI_BASE (0x40346000UL + BASE_NS_OFFSET) + #define R_MRMS_BASE (0x4013C000UL + BASE_NS_OFFSET) + #define R_NPU_BASE (0x40140000UL + BASE_NS_OFFSET) + #define R_PDM_BASE (0x40256000UL + BASE_NS_OFFSET) + #define R_RMAC0_BASE (0x403CB000UL + BASE_NS_OFFSET) + #define R_RMAC1_BASE (0x403CD000UL + BASE_NS_OFFSET) + #define R_SCI_B5_BASE (0x40358500UL + BASE_NS_OFFSET) + #define R_SCI_B6_BASE (0x40358600UL + BASE_NS_OFFSET) + #define R_SCI_B7_BASE (0x40358700UL + BASE_NS_OFFSET) + #define R_SCI_B8_BASE (0x40358800UL + BASE_NS_OFFSET) + #define R_TCM_BASE (0x4001C800UL + BASE_NS_OFFSET) + #define R_WDT1_BASE (0x40202700UL + BASE_NS_OFFSET) + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_ACMPHS0 ((R_ACMPHS0_Type *) R_ACMPHS0_BASE) + #define R_ACMPHS1 ((R_ACMPHS0_Type *) R_ACMPHS1_BASE) + #define R_ACMPHS2 ((R_ACMPHS0_Type *) R_ACMPHS2_BASE) + #define R_ACMPHS3 ((R_ACMPHS0_Type *) R_ACMPHS3_BASE) + #define R_ACMPHS4 ((R_ACMPHS0_Type *) R_ACMPHS4_BASE) + #define R_ACMPHS5 ((R_ACMPHS0_Type *) R_ACMPHS5_BASE) + #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE) + #define R_CANFD0 ((R_CANFD_Type *) R_CANFD_BASE) + #define R_CANFD1 ((R_CANFD_Type *) R_CANFD1_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #define R_DAC_B0 ((R_DAC_B0_Type *) R_DAC_B0_BASE) + #define R_DAC_B1 ((R_DAC_B0_Type *) R_DAC_B1_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DMA ((R_DMA_Type *) R_DMA_BASE) + #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) + #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) + #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) + #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) + #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) + #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) + #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) + #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_DRW ((R_DRW_Type *) R_DRW_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE) + #define R_GLCDC ((R_GLCDC_Type *) R_GLCDC_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_GPT_GTCLK ((R_GPT_GTCLK_Type *) R_GPT_GTCLK_BASE) + #define R_GPT_ODC ((R_GPT_ODC_Type *) R_GPT_ODC_BASE) + #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE) + #define R_I3C1 ((R_I3C0_Type *) R_I3C1_BASE) + #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) + #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) + #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) + #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) + #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE) + #define R_SDHI1 ((R_SDHI0_Type *) R_SDHI1_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SPI2 ((R_SPI0_Type *) R_SPI2_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) + #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) + #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) + #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) + #define R_VIN ((R_VIN_Type *) R_VIN_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + #define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE) + #define R_ADC_B ((R_ADC_B0_Type *) R_ADC_B0_BASE) + #define R_DOC_B ((R_DOC_B_Type *) R_DOC_B_BASE) + #define R_SCI_B0 ((R_SCI_B0_Type *) R_SCI_B0_BASE) + #define R_SCI_B1 ((R_SCI_B0_Type *) R_SCI_B1_BASE) + #define R_SCI_B2 ((R_SCI_B0_Type *) R_SCI_B2_BASE) + #define R_SCI_B3 ((R_SCI_B0_Type *) R_SCI_B3_BASE) + #define R_SCI_B4 ((R_SCI_B0_Type *) R_SCI_B4_BASE) + #define R_SCI_B9 ((R_SCI_B0_Type *) R_SCI_B9_BASE) + #define R_SPI_B0 ((R_SPI_B0_Type *) R_SPI_B0_BASE) + #define R_SPI_B1 ((R_SPI_B0_Type *) R_SPI_B1_BASE) + #define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE) + #define R_XSPI0 ((R_XSPI0_Type *) R_XSPI0_BASE) + #define R_XSPI1 ((R_XSPI0_Type *) R_XSPI1_BASE) + #define R_MIPI_PHY ((R_MIPI_PHY_Type *) R_MIPI_PHY_BASE) + #define R_MIPI_CSI ((R_MIPI_CSI_Type *) R_MIPI_CSI_BASE) + #define R_CEU ((R_CEU_Type *) R_CEU_BASE) + #define R_ULPT0 ((R_ULPT0_Type *) R_ULPT0_BASE) + #define R_ULPT1 ((R_ULPT0_Type *) R_ULPT1_BASE) + #define R_DEBUG_OCD ((R_DEBUG_OCD_Type *) R_DEBUG_OCD_BASE) + #define R_DOTF ((R_DOTF_Type *) R_DOTF_BASE) + #define R_AGT0 ((R_AGTX0_Type *) R_AGTX0_BASE) + #define R_AGT1 ((R_AGTX0_Type *) R_AGTX1_BASE) + #define R_AGT2 ((R_AGTX0_Type *) R_AGTX2_BASE) + #define R_AGT3 ((R_AGTX0_Type *) R_AGTX3_BASE) + #define R_AGT4 ((R_AGTX0_Type *) R_AGTX4_BASE) + #define R_AGT5 ((R_AGTX0_Type *) R_AGTX5_BASE) + #define R_AGT6 ((R_AGTX0_Type *) R_AGTX6_BASE) + #define R_AGT7 ((R_AGTX0_Type *) R_AGTX7_BASE) + #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) + #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) + #define R_COMA ((R_COMA_Type *) R_COMA_BASE) + #define R_CPU_CTRL ((R_CPU_CTRL_Type *) R_CPU_CTRL_BASE) + #define R_DOTF1 ((R_DOTF_Type *) R_DOTF1_BASE) + #define R_ECCMB0 ((R_ECCMB0_Type *) R_ECCMB0_BASE) + #define R_ECCMB1 ((R_ECCMB0_Type *) R_ECCMB1_BASE) + #define R_ESWM ((R_ESWM_Type *) R_ESWM_BASE) + #define R_ETHA0 ((R_ETHA0_Type *) R_ETHA0_BASE) + #define R_ETHA1 ((R_ETHA0_Type *) R_ETHA1_BASE) + #define R_GPTP ((R_GPTP_Type *) R_GPTP_BASE) + #define R_GWCA0 ((R_GWCA0_Type *) R_GWCA0_BASE) + #define R_IPC ((R_IPC_Type *) R_IPC_BASE) + #define R_MFWD ((R_MFWD_Type *) R_MFWD_BASE) + #define R_MIPI_DSI ((R_MIPI_DSI_Type *) R_MIPI_DSI_BASE) + #define R_MRMS ((R_MRMS_Type *) R_MRMS_BASE) + #define R_NPU ((R_NPU_Type *) R_NPU_BASE) + #define R_PDM ((R_PDM_Type *) R_PDM_BASE) + #define R_RMAC0 ((R_RMAC0_Type *) R_RMAC0_BASE) + #define R_RMAC1 ((R_RMAC0_Type *) R_RMAC1_BASE) + #define R_SCI_B5 ((R_SCI_B0_Type *) R_SCI_B5_BASE) + #define R_SCI_B6 ((R_SCI_B0_Type *) R_SCI_B6_BASE) + #define R_SCI_B7 ((R_SCI_B0_Type *) R_SCI_B7_BASE) + #define R_SCI_B8 ((R_SCI_B0_Type *) R_SCI_B8_BASE) + #define R_TCM ((R_TCM_Type *) R_TCM_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ SDRAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SDCCR ========================================================= */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCMOD ========================================================= */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDAMOD ========================================================= */ + #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDSELF ========================================================= */ + #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ + #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDRFCR ========================================================= */ + #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ + #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ +/* ======================================================== SDRFEN ========================================================= */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SDICR ========================================================= */ + #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ + #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SDIR ========================================================== */ + #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ + #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ + #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ + #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ +/* ========================================================= SDADR ========================================================= */ + #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ + #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ +/* ========================================================= SDTR ========================================================== */ + #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ + #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ + #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ + #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ + #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ + #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ +/* ========================================================= SDMOD ========================================================= */ + #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ + #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ +/* ========================================================= SDSR ========================================================== */ + #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ + #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ + #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ + #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU1TCMBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ + #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ + #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CFDC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= NCFG ========================================================== */ + #define R_CANFD_CFDC_NCFG_NBRP_Pos (0UL) /*!< NBRP (Bit 0) */ + #define R_CANFD_CFDC_NCFG_NBRP_Msk (0x3ffUL) /*!< NBRP (Bitfield-Mask: 0x3ff) */ + #define R_CANFD_CFDC_NCFG_NSJW_Pos (10UL) /*!< NSJW (Bit 10) */ + #define R_CANFD_CFDC_NCFG_NSJW_Msk (0x1fc00UL) /*!< NSJW (Bitfield-Mask: 0x7f) */ + #define R_CANFD_CFDC_NCFG_NTSEG1_Pos (17UL) /*!< NTSEG1 (Bit 17) */ + #define R_CANFD_CFDC_NCFG_NTSEG1_Msk (0x1fe0000UL) /*!< NTSEG1 (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC_NCFG_NTSEG2_Pos (25UL) /*!< NTSEG2 (Bit 25) */ + #define R_CANFD_CFDC_NCFG_NTSEG2_Msk (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f) */ +/* ========================================================== CTR ========================================================== */ + #define R_CANFD_CFDC_CTR_CHMDC_Pos (0UL) /*!< CHMDC (Bit 0) */ + #define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_CSLPR_Pos (2UL) /*!< CSLPR (Bit 2) */ + #define R_CANFD_CFDC_CTR_CSLPR_Msk (0x4UL) /*!< CSLPR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_RTBO_Pos (3UL) /*!< RTBO (Bit 3) */ + #define R_CANFD_CFDC_CTR_RTBO_Msk (0x8UL) /*!< RTBO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BEIE_Pos (8UL) /*!< BEIE (Bit 8) */ + #define R_CANFD_CFDC_CTR_BEIE_Msk (0x100UL) /*!< BEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EWIE_Pos (9UL) /*!< EWIE (Bit 9) */ + #define R_CANFD_CFDC_CTR_EWIE_Msk (0x200UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EPIE_Pos (10UL) /*!< EPIE (Bit 10) */ + #define R_CANFD_CFDC_CTR_EPIE_Msk (0x400UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BOEIE_Pos (11UL) /*!< BOEIE (Bit 11) */ + #define R_CANFD_CFDC_CTR_BOEIE_Msk (0x800UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BORIE_Pos (12UL) /*!< BORIE (Bit 12) */ + #define R_CANFD_CFDC_CTR_BORIE_Msk (0x1000UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_OLIE_Pos (13UL) /*!< OLIE (Bit 13) */ + #define R_CANFD_CFDC_CTR_OLIE_Msk (0x2000UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BLIE_Pos (14UL) /*!< BLIE (Bit 14) */ + #define R_CANFD_CFDC_CTR_BLIE_Msk (0x4000UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_ALIE_Pos (15UL) /*!< ALIE (Bit 15) */ + #define R_CANFD_CFDC_CTR_ALIE_Msk (0x8000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TAIE_Pos (16UL) /*!< TAIE (Bit 16) */ + #define R_CANFD_CFDC_CTR_TAIE_Msk (0x10000UL) /*!< TAIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EOCOIE_Pos (17UL) /*!< EOCOIE (Bit 17) */ + #define R_CANFD_CFDC_CTR_EOCOIE_Msk (0x20000UL) /*!< EOCOIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_SOCOIE_Pos (18UL) /*!< SOCOIE (Bit 18) */ + #define R_CANFD_CFDC_CTR_SOCOIE_Msk (0x40000UL) /*!< SOCOIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TDCVFIE_Pos (19UL) /*!< TDCVFIE (Bit 19) */ + #define R_CANFD_CFDC_CTR_TDCVFIE_Msk (0x80000UL) /*!< TDCVFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BOM_Pos (21UL) /*!< BOM (Bit 21) */ + #define R_CANFD_CFDC_CTR_BOM_Msk (0x600000UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_ERRD_Pos (23UL) /*!< ERRD (Bit 23) */ + #define R_CANFD_CFDC_CTR_ERRD_Msk (0x800000UL) /*!< ERRD (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_CTME_Pos (24UL) /*!< CTME (Bit 24) */ + #define R_CANFD_CFDC_CTR_CTME_Msk (0x1000000UL) /*!< CTME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_CTMS_Pos (25UL) /*!< CTMS (Bit 25) */ + #define R_CANFD_CFDC_CTR_CTMS_Msk (0x6000000UL) /*!< CTMS (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_CRCT_Pos (30UL) /*!< CRCT (Bit 30) */ + #define R_CANFD_CFDC_CTR_CRCT_Msk (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_ROM_Pos (31UL) /*!< ROM (Bit 31) */ + #define R_CANFD_CFDC_CTR_ROM_Msk (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01) */ +/* ========================================================== STS ========================================================== */ + #define R_CANFD_CFDC_STS_CRSTSTS_Pos (0UL) /*!< CRSTSTS (Bit 0) */ + #define R_CANFD_CFDC_STS_CRSTSTS_Msk (0x1UL) /*!< CRSTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_CHLTSTS_Pos (1UL) /*!< CHLTSTS (Bit 1) */ + #define R_CANFD_CFDC_STS_CHLTSTS_Msk (0x2UL) /*!< CHLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_CSLPSTS_Pos (2UL) /*!< CSLPSTS (Bit 2) */ + #define R_CANFD_CFDC_STS_CSLPSTS_Msk (0x4UL) /*!< CSLPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_EPSTS_Pos (3UL) /*!< EPSTS (Bit 3) */ + #define R_CANFD_CFDC_STS_EPSTS_Msk (0x8UL) /*!< EPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_BOSTS_Pos (4UL) /*!< BOSTS (Bit 4) */ + #define R_CANFD_CFDC_STS_BOSTS_Msk (0x10UL) /*!< BOSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_TRMSTS_Pos (5UL) /*!< TRMSTS (Bit 5) */ + #define R_CANFD_CFDC_STS_TRMSTS_Msk (0x20UL) /*!< TRMSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_RECSTS_Pos (6UL) /*!< RECSTS (Bit 6) */ + #define R_CANFD_CFDC_STS_RECSTS_Msk (0x40UL) /*!< RECSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_COMSTS_Pos (7UL) /*!< COMSTS (Bit 7) */ + #define R_CANFD_CFDC_STS_COMSTS_Msk (0x80UL) /*!< COMSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_ESIF_Pos (8UL) /*!< ESIF (Bit 8) */ + #define R_CANFD_CFDC_STS_ESIF_Msk (0x100UL) /*!< ESIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_REC_Pos (16UL) /*!< REC (Bit 16) */ + #define R_CANFD_CFDC_STS_REC_Msk (0xff0000UL) /*!< REC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC_STS_TEC_Pos (24UL) /*!< TEC (Bit 24) */ + #define R_CANFD_CFDC_STS_TEC_Msk (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff) */ +/* ========================================================= ERFL ========================================================== */ + #define R_CANFD_CFDC_ERFL_BEF_Pos (0UL) /*!< BEF (Bit 0) */ + #define R_CANFD_CFDC_ERFL_BEF_Msk (0x1UL) /*!< BEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_EWF_Pos (1UL) /*!< EWF (Bit 1) */ + #define R_CANFD_CFDC_ERFL_EWF_Msk (0x2UL) /*!< EWF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_EPF_Pos (2UL) /*!< EPF (Bit 2) */ + #define R_CANFD_CFDC_ERFL_EPF_Msk (0x4UL) /*!< EPF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BOEF_Pos (3UL) /*!< BOEF (Bit 3) */ + #define R_CANFD_CFDC_ERFL_BOEF_Msk (0x8UL) /*!< BOEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BORF_Pos (4UL) /*!< BORF (Bit 4) */ + #define R_CANFD_CFDC_ERFL_BORF_Msk (0x10UL) /*!< BORF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_OVLF_Pos (5UL) /*!< OVLF (Bit 5) */ + #define R_CANFD_CFDC_ERFL_OVLF_Msk (0x20UL) /*!< OVLF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BLF_Pos (6UL) /*!< BLF (Bit 6) */ + #define R_CANFD_CFDC_ERFL_BLF_Msk (0x40UL) /*!< BLF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_ALF_Pos (7UL) /*!< ALF (Bit 7) */ + #define R_CANFD_CFDC_ERFL_ALF_Msk (0x80UL) /*!< ALF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_SERR_Pos (8UL) /*!< SERR (Bit 8) */ + #define R_CANFD_CFDC_ERFL_SERR_Msk (0x100UL) /*!< SERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_FERR_Pos (9UL) /*!< FERR (Bit 9) */ + #define R_CANFD_CFDC_ERFL_FERR_Msk (0x200UL) /*!< FERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_AERR_Pos (10UL) /*!< AERR (Bit 10) */ + #define R_CANFD_CFDC_ERFL_AERR_Msk (0x400UL) /*!< AERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_CERR_Pos (11UL) /*!< CERR (Bit 11) */ + #define R_CANFD_CFDC_ERFL_CERR_Msk (0x800UL) /*!< CERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_B1ERR_Pos (12UL) /*!< B1ERR (Bit 12) */ + #define R_CANFD_CFDC_ERFL_B1ERR_Msk (0x1000UL) /*!< B1ERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_B0ERR_Pos (13UL) /*!< B0ERR (Bit 13) */ + #define R_CANFD_CFDC_ERFL_B0ERR_Msk (0x2000UL) /*!< B0ERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_ADERR_Pos (14UL) /*!< ADERR (Bit 14) */ + #define R_CANFD_CFDC_ERFL_ADERR_Msk (0x4000UL) /*!< ADERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_CRCREG_Pos (16UL) /*!< CRCREG (Bit 16) */ + #define R_CANFD_CFDC_ERFL_CRCREG_Msk (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff) */ + +/* =========================================================================================================================== */ +/* ================ CFDC2 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DCFG ========================================================== */ + #define R_CANFD_CFDC2_DCFG_DBRP_Pos (0UL) /*!< DBRP (Bit 0) */ + #define R_CANFD_CFDC2_DCFG_DBRP_Msk (0xffUL) /*!< DBRP (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos (8UL) /*!< DTSEG1 (Bit 8) */ + #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk (0x1f00UL) /*!< DTSEG1 (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos (16UL) /*!< DTSEG2 (Bit 16) */ + #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk (0xf0000UL) /*!< DTSEG2 (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDC2_DCFG_DSJW_Pos (24UL) /*!< DSJW (Bit 24) */ + #define R_CANFD_CFDC2_DCFG_DSJW_Msk (0xf000000UL) /*!< DSJW (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCFG ========================================================= */ + #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos (0UL) /*!< EOCCFG (Bit 0) */ + #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk (0x7UL) /*!< EOCCFG (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos (8UL) /*!< TDCOC (Bit 8) */ + #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk (0x100UL) /*!< TDCOC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_TDCE_Pos (9UL) /*!< TDCE (Bit 9) */ + #define R_CANFD_CFDC2_FDCFG_TDCE_Msk (0x200UL) /*!< TDCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_ESIC_Pos (10UL) /*!< ESIC (Bit 10) */ + #define R_CANFD_CFDC2_FDCFG_ESIC_Msk (0x400UL) /*!< ESIC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_TDCO_Pos (16UL) /*!< TDCO (Bit 16) */ + #define R_CANFD_CFDC2_FDCFG_TDCO_Msk (0xff0000UL) /*!< TDCO (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDCFG_FDOE_Pos (28UL) /*!< FDOE (Bit 28) */ + #define R_CANFD_CFDC2_FDCFG_FDOE_Msk (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_REFE_Pos (29UL) /*!< REFE (Bit 29) */ + #define R_CANFD_CFDC2_FDCFG_REFE_Msk (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_CLOE_Pos (30UL) /*!< CLOE (Bit 30) */ + #define R_CANFD_CFDC2_FDCFG_CLOE_Msk (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01) */ +/* ========================================================= FDCTR ========================================================= */ + #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos (0UL) /*!< EOCCLR (Bit 0) */ + #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk (0x1UL) /*!< EOCCLR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos (1UL) /*!< SOCCLR (Bit 1) */ + #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk (0x2UL) /*!< SOCCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDC2_FDSTS_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ + #define R_CANFD_CFDC2_FDSTS_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDSTS_EOCO_Pos (8UL) /*!< EOCO (Bit 8) */ + #define R_CANFD_CFDC2_FDSTS_EOCO_Msk (0x100UL) /*!< EOCO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_SOCO_Pos (9UL) /*!< SOCO (Bit 9) */ + #define R_CANFD_CFDC2_FDSTS_SOCO_Msk (0x200UL) /*!< SOCO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos (15UL) /*!< TDCVF (Bit 15) */ + #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk (0x8000UL) /*!< TDCVF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_EOC_Pos (16UL) /*!< EOC (Bit 16) */ + #define R_CANFD_CFDC2_FDSTS_EOC_Msk (0xff0000UL) /*!< EOC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDSTS_SOC_Pos (24UL) /*!< SOC (Bit 24) */ + #define R_CANFD_CFDC2_FDSTS_SOC_Msk (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff) */ +/* ========================================================= FDCRC ========================================================= */ + #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos (0UL) /*!< CRCREG (Bit 0) */ + #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk (0x1fffffUL) /*!< CRCREG (Bitfield-Mask: 0x1fffff) */ + #define R_CANFD_CFDC2_FDCRC_SCNT_Pos (24UL) /*!< SCNT (Bit 24) */ + #define R_CANFD_CFDC2_FDCRC_SCNT_Msk (0xf000000UL) /*!< SCNT (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ CFDGAFL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDGAFL_ID_GAFLID_Pos (0UL) /*!< GAFLID (Bit 0) */ + #define R_CANFD_CFDGAFL_ID_GAFLID_Msk (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos (29UL) /*!< GAFLLB (Bit 29) */ + #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos (30UL) /*!< GAFLRTR (Bit 30) */ + #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos (31UL) /*!< GAFLIDE (Bit 31) */ + #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01) */ +/* =========================================================== M =========================================================== */ + #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos (0UL) /*!< GAFLIDM (Bit 0) */ + #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos (29UL) /*!< GAFLIFL1 (Bit 29) */ + #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos (30UL) /*!< GAFLRTRM (Bit 30) */ + #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos (31UL) /*!< GAFLIDEM (Bit 31) */ + #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01) */ +/* ========================================================== P0 =========================================================== */ + #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos (0UL) /*!< GAFLDLC (Bit 0) */ + #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk (0xfUL) /*!< GAFLDLC (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos (7UL) /*!< GAFLIFL0 (Bit 7) */ + #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk (0x80UL) /*!< GAFLIFL0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos (8UL) /*!< GAFLRMDP (Bit 8) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk (0x1f00UL) /*!< GAFLRMDP (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos (15UL) /*!< GAFLRMV (Bit 15) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk (0x8000UL) /*!< GAFLRMV (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos (16UL) /*!< GAFLPTR (Bit 16) */ + #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== P1 =========================================================== */ + #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos (0UL) /*!< GAFLFDP (Bit 0) */ + #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk (0x1ffUL) /*!< GAFLFDP (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ CFDTHL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ACC0 ========================================================== */ + #define R_CANFD_CFDTHL_ACC0_BT_Pos (0UL) /*!< BT (Bit 0) */ + #define R_CANFD_CFDTHL_ACC0_BT_Msk (0x7UL) /*!< BT (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTHL_ACC0_BN_Pos (3UL) /*!< BN (Bit 3) */ + #define R_CANFD_CFDTHL_ACC0_BN_Msk (0x3f8UL) /*!< BN (Bitfield-Mask: 0x7f) */ + #define R_CANFD_CFDTHL_ACC0_TMTS_Pos (16UL) /*!< TMTS (Bit 16) */ + #define R_CANFD_CFDTHL_ACC0_TMTS_Msk (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff) */ +/* ========================================================= ACC1 ========================================================== */ + #define R_CANFD_CFDTHL_ACC1_TID_Pos (0UL) /*!< TID (Bit 0) */ + #define R_CANFD_CFDTHL_ACC1_TID_Msk (0xffffUL) /*!< TID (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDTHL_ACC1_TIFL_Pos (16UL) /*!< TIFL (Bit 16) */ + #define R_CANFD_CFDTHL_ACC1_TIFL_Msk (0x30000UL) /*!< TIFL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CFDRF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDRF_ID_RFID_Pos (0UL) /*!< RFID (Bit 0) */ + #define R_CANFD_CFDRF_ID_RFID_Msk (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDRF_ID_RFRTR_Pos (30UL) /*!< RFRTR (Bit 30) */ + #define R_CANFD_CFDRF_ID_RFRTR_Msk (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_ID_RFIDE_Pos (31UL) /*!< RFIDE (Bit 31) */ + #define R_CANFD_CFDRF_ID_RFIDE_Msk (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDRF_PTR_RFTS_Pos (0UL) /*!< RFTS (Bit 0) */ + #define R_CANFD_CFDRF_PTR_RFTS_Msk (0xffffUL) /*!< RFTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDRF_PTR_RFDLC_Pos (28UL) /*!< RFDLC (Bit 28) */ + #define R_CANFD_CFDRF_PTR_RFDLC_Msk (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDRF_FDSTS_RFESI_Pos (0UL) /*!< RFESI (Bit 0) */ + #define R_CANFD_CFDRF_FDSTS_RFESI_Msk (0x1UL) /*!< RFESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos (1UL) /*!< RFBRS (Bit 1) */ + #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk (0x2UL) /*!< RFBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos (2UL) /*!< RFFDF (Bit 2) */ + #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk (0x4UL) /*!< RFFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos (8UL) /*!< RFIFL (Bit 8) */ + #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk (0x300UL) /*!< RFIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDRF_FDSTS_RFPTR_Pos (16UL) /*!< RFPTR (Bit 16) */ + #define R_CANFD_CFDRF_FDSTS_RFPTR_Msk (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDRF_DF_RFDB_Pos (0UL) /*!< RFDB (Bit 0) */ + #define R_CANFD_CFDRF_DF_RFDB_Msk (0xffUL) /*!< RFDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDCF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */ + #define R_CANFD_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDCF_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDCF_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */ + #define R_CANFD_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */ + #define R_CANFD_CFDCF_ID_CFIDE_Msk (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDCF_PTR_CFTS_Pos (0UL) /*!< CFTS (Bit 0) */ + #define R_CANFD_CFDCF_PTR_CFTS_Msk (0xffffUL) /*!< CFTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDCF_PTR_CFDLC_Pos (28UL) /*!< CFDLC (Bit 28) */ + #define R_CANFD_CFDCF_PTR_CFDLC_Msk (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDCF_FDSTS_CFESI_Pos (0UL) /*!< CFESI (Bit 0) */ + #define R_CANFD_CFDCF_FDSTS_CFESI_Msk (0x1UL) /*!< CFESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFBRS_Pos (1UL) /*!< CFBRS (Bit 1) */ + #define R_CANFD_CFDCF_FDSTS_CFBRS_Msk (0x2UL) /*!< CFBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFFDF_Pos (2UL) /*!< CFFDF (Bit 2) */ + #define R_CANFD_CFDCF_FDSTS_CFFDF_Msk (0x4UL) /*!< CFFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFIFL_Pos (8UL) /*!< CFIFL (Bit 8) */ + #define R_CANFD_CFDCF_FDSTS_CFIFL_Msk (0x300UL) /*!< CFIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDCF_FDSTS_CFPTR_Pos (16UL) /*!< CFPTR (Bit 16) */ + #define R_CANFD_CFDCF_FDSTS_CFPTR_Msk (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDCF_DF_CFDB_Pos (0UL) /*!< CFDB (Bit 0) */ + #define R_CANFD_CFDCF_DF_CFDB_Msk (0xffUL) /*!< CFDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDTM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */ + #define R_CANFD_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDTM_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDTM_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */ + #define R_CANFD_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */ + #define R_CANFD_CFDTM_ID_TMIDE_Msk (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDTM_PTR_TMTS_Pos (0UL) /*!< TMTS (Bit 0) */ + #define R_CANFD_CFDTM_PTR_TMTS_Msk (0xffffUL) /*!< TMTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDTM_PTR_TMDLC_Pos (28UL) /*!< TMDLC (Bit 28) */ + #define R_CANFD_CFDTM_PTR_TMDLC_Msk (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCTR ========================================================= */ + #define R_CANFD_CFDTM_FDCTR_TMESI_Pos (0UL) /*!< TMESI (Bit 0) */ + #define R_CANFD_CFDTM_FDCTR_TMESI_Msk (0x1UL) /*!< TMESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos (1UL) /*!< TMBRS (Bit 1) */ + #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk (0x2UL) /*!< TMBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos (2UL) /*!< TMFDF (Bit 2) */ + #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk (0x4UL) /*!< TMFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos (8UL) /*!< TMIFL (Bit 8) */ + #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk (0x300UL) /*!< TMIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos (16UL) /*!< TMPTR (Bit 16) */ + #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDTM_DF_TMDB_Pos (0UL) /*!< TMDB (Bit 0) */ + #define R_CANFD_CFDTM_DF_TMDB_Msk (0xffUL) /*!< TMDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ RM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDRM_RM_ID_RMID_Pos (0UL) /*!< RMID (Bit 0) */ + #define R_CANFD_CFDRM_RM_ID_RMID_Msk (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDRM_RM_ID_RMRTR_Pos (30UL) /*!< RMRTR (Bit 30) */ + #define R_CANFD_CFDRM_RM_ID_RMRTR_Msk (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_ID_RMIDE_Pos (31UL) /*!< RMIDE (Bit 31) */ + #define R_CANFD_CFDRM_RM_ID_RMIDE_Msk (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDRM_RM_PTR_RMTS_Pos (0UL) /*!< RMTS (Bit 0) */ + #define R_CANFD_CFDRM_RM_PTR_RMTS_Msk (0xffffUL) /*!< RMTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDRM_RM_PTR_RMDLC_Pos (28UL) /*!< RMDLC (Bit 28) */ + #define R_CANFD_CFDRM_RM_PTR_RMDLC_Msk (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Pos (0UL) /*!< RMESI (Bit 0) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Msk (0x1UL) /*!< RMESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Pos (1UL) /*!< RMBRS (Bit 1) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Msk (0x2UL) /*!< RMBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Pos (2UL) /*!< RMFDF (Bit 2) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Msk (0x4UL) /*!< RMFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Pos (8UL) /*!< RMIFL (Bit 8) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Msk (0x300UL) /*!< RMIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Pos (16UL) /*!< RMPTR (Bit 16) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Msk (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDRM_RM_DF_RMDB_Pos (0UL) /*!< RMDB (Bit 0) */ + #define R_CANFD_CFDRM_RM_DF_RMDB_Msk (0xffUL) /*!< RMDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDRM ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ ELSEGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ + #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ + #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ + #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELSR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== HA =========================================================== */ + #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ + #define R_ELC_ELSR_HA_ELS_Msk (0x3ffUL) /*!< ELS (Bitfield-Mask: 0x3ff) */ + +/* =========================================================================================================================== */ +/* ================ BG ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EN =========================================================== */ + #define R_GLCDC_BG_EN_SWRST_Pos (16UL) /*!< SWRST (Bit 16) */ + #define R_GLCDC_BG_EN_SWRST_Msk (0x10000UL) /*!< SWRST (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_EN_VEN_Pos (8UL) /*!< VEN (Bit 8) */ + #define R_GLCDC_BG_EN_VEN_Msk (0x100UL) /*!< VEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_EN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_GLCDC_BG_EN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= PERI ========================================================== */ + #define R_GLCDC_BG_PERI_FV_Pos (16UL) /*!< FV (Bit 16) */ + #define R_GLCDC_BG_PERI_FV_Msk (0x7ff0000UL) /*!< FV (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_BG_PERI_FH_Pos (0UL) /*!< FH (Bit 0) */ + #define R_GLCDC_BG_PERI_FH_Msk (0x7ffUL) /*!< FH (Bitfield-Mask: 0x7ff) */ +/* ========================================================= SYNC ========================================================== */ + #define R_GLCDC_BG_SYNC_VP_Pos (16UL) /*!< VP (Bit 16) */ + #define R_GLCDC_BG_SYNC_VP_Msk (0xf0000UL) /*!< VP (Bitfield-Mask: 0x0f) */ + #define R_GLCDC_BG_SYNC_HP_Pos (0UL) /*!< HP (Bit 0) */ + #define R_GLCDC_BG_SYNC_HP_Msk (0xfUL) /*!< HP (Bitfield-Mask: 0x0f) */ +/* ========================================================= VSIZE ========================================================= */ + #define R_GLCDC_BG_VSIZE_VP_Pos (16UL) /*!< VP (Bit 16) */ + #define R_GLCDC_BG_VSIZE_VP_Msk (0x7ff0000UL) /*!< VP (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_BG_VSIZE_VW_Pos (0UL) /*!< VW (Bit 0) */ + #define R_GLCDC_BG_VSIZE_VW_Msk (0x7ffUL) /*!< VW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= HSIZE ========================================================= */ + #define R_GLCDC_BG_HSIZE_HP_Pos (16UL) /*!< HP (Bit 16) */ + #define R_GLCDC_BG_HSIZE_HP_Msk (0x7ff0000UL) /*!< HP (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_BG_HSIZE_HW_Pos (0UL) /*!< HW (Bit 0) */ + #define R_GLCDC_BG_HSIZE_HW_Msk (0x7ffUL) /*!< HW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== BGC ========================================================== */ + #define R_GLCDC_BG_BGC_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_BG_BGC_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_BG_BGC_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_BG_BGC_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_BG_BGC_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_BG_BGC_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ========================================================== MON ========================================================== */ + #define R_GLCDC_BG_MON_SWRST_Pos (16UL) /*!< SWRST (Bit 16) */ + #define R_GLCDC_BG_MON_SWRST_Msk (0x10000UL) /*!< SWRST (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_MON_VEN_Pos (8UL) /*!< VEN (Bit 8) */ + #define R_GLCDC_BG_MON_VEN_Msk (0x100UL) /*!< VEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_MON_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_GLCDC_BG_MON_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ GR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== VEN ========================================================== */ + #define R_GLCDC_GR_VEN_PVEN_Pos (0UL) /*!< PVEN (Bit 0) */ + #define R_GLCDC_GR_VEN_PVEN_Msk (0x1UL) /*!< PVEN (Bitfield-Mask: 0x01) */ +/* ========================================================= FLMRD ========================================================= */ + #define R_GLCDC_GR_FLMRD_RENB_Pos (0UL) /*!< RENB (Bit 0) */ + #define R_GLCDC_GR_FLMRD_RENB_Msk (0x1UL) /*!< RENB (Bitfield-Mask: 0x01) */ +/* ========================================================= FLM1 ========================================================== */ + #define R_GLCDC_GR_FLM1_BSTMD_Pos (0UL) /*!< BSTMD (Bit 0) */ + #define R_GLCDC_GR_FLM1_BSTMD_Msk (0x3UL) /*!< BSTMD (Bitfield-Mask: 0x03) */ +/* ========================================================= FLM2 ========================================================== */ + #define R_GLCDC_GR_FLM2_BASE_Pos (0UL) /*!< BASE (Bit 0) */ + #define R_GLCDC_GR_FLM2_BASE_Msk (0xffffffffUL) /*!< BASE (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= FLM3 ========================================================== */ + #define R_GLCDC_GR_FLM3_LNOFF_Pos (16UL) /*!< LNOFF (Bit 16) */ + #define R_GLCDC_GR_FLM3_LNOFF_Msk (0xffff0000UL) /*!< LNOFF (Bitfield-Mask: 0xffff) */ +/* ========================================================= FLM5 ========================================================== */ + #define R_GLCDC_GR_FLM5_LNNUM_Pos (16UL) /*!< LNNUM (Bit 16) */ + #define R_GLCDC_GR_FLM5_LNNUM_Msk (0x7ff0000UL) /*!< LNNUM (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_FLM5_DATANUM_Pos (0UL) /*!< DATANUM (Bit 0) */ + #define R_GLCDC_GR_FLM5_DATANUM_Msk (0xffffUL) /*!< DATANUM (Bitfield-Mask: 0xffff) */ +/* ========================================================= FLM6 ========================================================== */ + #define R_GLCDC_GR_FLM6_FORMAT_Pos (28UL) /*!< FORMAT (Bit 28) */ + #define R_GLCDC_GR_FLM6_FORMAT_Msk (0x70000000UL) /*!< FORMAT (Bitfield-Mask: 0x07) */ +/* ========================================================== AB1 ========================================================== */ + #define R_GLCDC_GR_AB1_ARCON_Pos (12UL) /*!< ARCON (Bit 12) */ + #define R_GLCDC_GR_AB1_ARCON_Msk (0x1000UL) /*!< ARCON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_AB1_ARCDISPON_Pos (8UL) /*!< ARCDISPON (Bit 8) */ + #define R_GLCDC_GR_AB1_ARCDISPON_Msk (0x100UL) /*!< ARCDISPON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_AB1_GRCDISPON_Pos (4UL) /*!< GRCDISPON (Bit 4) */ + #define R_GLCDC_GR_AB1_GRCDISPON_Msk (0x10UL) /*!< GRCDISPON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_AB1_DISPSEL_Pos (0UL) /*!< DISPSEL (Bit 0) */ + #define R_GLCDC_GR_AB1_DISPSEL_Msk (0x3UL) /*!< DISPSEL (Bitfield-Mask: 0x03) */ +/* ========================================================== AB2 ========================================================== */ + #define R_GLCDC_GR_AB2_GRCVS_Pos (16UL) /*!< GRCVS (Bit 16) */ + #define R_GLCDC_GR_AB2_GRCVS_Msk (0x7ff0000UL) /*!< GRCVS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB2_GRCVW_Pos (0UL) /*!< GRCVW (Bit 0) */ + #define R_GLCDC_GR_AB2_GRCVW_Msk (0x7ffUL) /*!< GRCVW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB3 ========================================================== */ + #define R_GLCDC_GR_AB3_GRCHS_Pos (16UL) /*!< GRCHS (Bit 16) */ + #define R_GLCDC_GR_AB3_GRCHS_Msk (0x7ff0000UL) /*!< GRCHS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB3_GRCHW_Pos (0UL) /*!< GRCHW (Bit 0) */ + #define R_GLCDC_GR_AB3_GRCHW_Msk (0x7ffUL) /*!< GRCHW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB4 ========================================================== */ + #define R_GLCDC_GR_AB4_ARCVS_Pos (16UL) /*!< ARCVS (Bit 16) */ + #define R_GLCDC_GR_AB4_ARCVS_Msk (0x7ff0000UL) /*!< ARCVS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB4_ARCVW_Pos (0UL) /*!< ARCVW (Bit 0) */ + #define R_GLCDC_GR_AB4_ARCVW_Msk (0x7ffUL) /*!< ARCVW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB5 ========================================================== */ + #define R_GLCDC_GR_AB5_ARCHS_Pos (16UL) /*!< ARCHS (Bit 16) */ + #define R_GLCDC_GR_AB5_ARCHS_Msk (0x7ff0000UL) /*!< ARCHS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB5_ARCHW_Pos (0UL) /*!< ARCHW (Bit 0) */ + #define R_GLCDC_GR_AB5_ARCHW_Msk (0x7ffUL) /*!< ARCHW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB6 ========================================================== */ + #define R_GLCDC_GR_AB6_ARCCOEF_Pos (16UL) /*!< ARCCOEF (Bit 16) */ + #define R_GLCDC_GR_AB6_ARCCOEF_Msk (0x1ff0000UL) /*!< ARCCOEF (Bitfield-Mask: 0x1ff) */ + #define R_GLCDC_GR_AB6_ARCRATE_Pos (0UL) /*!< ARCRATE (Bit 0) */ + #define R_GLCDC_GR_AB6_ARCRATE_Msk (0xffUL) /*!< ARCRATE (Bitfield-Mask: 0xff) */ +/* ========================================================== AB7 ========================================================== */ + #define R_GLCDC_GR_AB7_ARCDEF_Pos (16UL) /*!< ARCDEF (Bit 16) */ + #define R_GLCDC_GR_AB7_ARCDEF_Msk (0xff0000UL) /*!< ARCDEF (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB7_CKON_Pos (0UL) /*!< CKON (Bit 0) */ + #define R_GLCDC_GR_AB7_CKON_Msk (0x1UL) /*!< CKON (Bitfield-Mask: 0x01) */ +/* ========================================================== AB8 ========================================================== */ + #define R_GLCDC_GR_AB8_CKKG_Pos (16UL) /*!< CKKG (Bit 16) */ + #define R_GLCDC_GR_AB8_CKKG_Msk (0xff0000UL) /*!< CKKG (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB8_CKKB_Pos (8UL) /*!< CKKB (Bit 8) */ + #define R_GLCDC_GR_AB8_CKKB_Msk (0xff00UL) /*!< CKKB (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB8_CKKR_Pos (0UL) /*!< CKKR (Bit 0) */ + #define R_GLCDC_GR_AB8_CKKR_Msk (0xffUL) /*!< CKKR (Bitfield-Mask: 0xff) */ +/* ========================================================== AB9 ========================================================== */ + #define R_GLCDC_GR_AB9_CKA_Pos (24UL) /*!< CKA (Bit 24) */ + #define R_GLCDC_GR_AB9_CKA_Msk (0xff000000UL) /*!< CKA (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB9_CKG_Pos (16UL) /*!< CKG (Bit 16) */ + #define R_GLCDC_GR_AB9_CKG_Msk (0xff0000UL) /*!< CKG (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB9_CKB_Pos (8UL) /*!< CKB (Bit 8) */ + #define R_GLCDC_GR_AB9_CKB_Msk (0xff00UL) /*!< CKB (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB9_CKR_Pos (0UL) /*!< CKR (Bit 0) */ + #define R_GLCDC_GR_AB9_CKR_Msk (0xffUL) /*!< CKR (Bitfield-Mask: 0xff) */ +/* ========================================================= BASE ========================================================== */ + #define R_GLCDC_GR_BASE_G_Pos (16UL) /*!< G (Bit 16) */ + #define R_GLCDC_GR_BASE_G_Msk (0xff0000UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_BASE_B_Pos (8UL) /*!< B (Bit 8) */ + #define R_GLCDC_GR_BASE_B_Msk (0xff00UL) /*!< B (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_BASE_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_GLCDC_GR_BASE_R_Msk (0xffUL) /*!< R (Bitfield-Mask: 0xff) */ +/* ======================================================== CLUTINT ======================================================== */ + #define R_GLCDC_GR_CLUTINT_SEL_Pos (16UL) /*!< SEL (Bit 16) */ + #define R_GLCDC_GR_CLUTINT_SEL_Msk (0x10000UL) /*!< SEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_CLUTINT_LINE_Pos (0UL) /*!< LINE (Bit 0) */ + #define R_GLCDC_GR_CLUTINT_LINE_Msk (0x7ffUL) /*!< LINE (Bitfield-Mask: 0x7ff) */ +/* ========================================================== MON ========================================================== */ + #define R_GLCDC_GR_MON_UNDFLST_Pos (16UL) /*!< UNDFLST (Bit 16) */ + #define R_GLCDC_GR_MON_UNDFLST_Msk (0x10000UL) /*!< UNDFLST (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_MON_ARCST_Pos (0UL) /*!< ARCST (Bit 0) */ + #define R_GLCDC_GR_MON_ARCST_Msk (0x1UL) /*!< ARCST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ GAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= LATCH ========================================================= */ + #define R_GLCDC_GAM_LATCH_VEN_Pos (0UL) /*!< VEN (Bit 0) */ + #define R_GLCDC_GAM_LATCH_VEN_Msk (0x1UL) /*!< VEN (Bitfield-Mask: 0x01) */ +/* ======================================================== GAM_SW ========================================================= */ + #define R_GLCDC_GAM_GAM_SW_GAMON_Pos (0UL) /*!< GAMON (Bit 0) */ + #define R_GLCDC_GAM_GAM_SW_GAMON_Msk (0x1UL) /*!< GAMON (Bitfield-Mask: 0x01) */ +/* ========================================================== LUT ========================================================== */ + #define R_GLCDC_GAM_LUT___Pos (0UL) /*!< _ (Bit 0) */ + #define R_GLCDC_GAM_LUT___Msk (0x7ffUL) /*!< _ (Bitfield-Mask: 0x7ff) */ +/* ========================================================= AREA ========================================================== */ + #define R_GLCDC_GAM_AREA___Pos (0UL) /*!< _ (Bit 0) */ + #define R_GLCDC_GAM_AREA___Msk (0x3ffUL) /*!< _ (Bitfield-Mask: 0x3ff) */ + +/* =========================================================================================================================== */ +/* ================ OUT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== VLATCH ========================================================= */ + #define R_GLCDC_OUT_VLATCH_VEN_Pos (0UL) /*!< VEN (Bit 0) */ + #define R_GLCDC_OUT_VLATCH_VEN_Msk (0x1UL) /*!< VEN (Bitfield-Mask: 0x01) */ +/* ========================================================== SET ========================================================== */ + #define R_GLCDC_OUT_SET_ENDIANON_Pos (28UL) /*!< ENDIANON (Bit 28) */ + #define R_GLCDC_OUT_SET_ENDIANON_Msk (0x10000000UL) /*!< ENDIANON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_SET_SWAPON_Pos (24UL) /*!< SWAPON (Bit 24) */ + #define R_GLCDC_OUT_SET_SWAPON_Msk (0x1000000UL) /*!< SWAPON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_SET_FORMAT_Pos (12UL) /*!< FORMAT (Bit 12) */ + #define R_GLCDC_OUT_SET_FORMAT_Msk (0x3000UL) /*!< FORMAT (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_SET_FRQSEL_Pos (8UL) /*!< FRQSEL (Bit 8) */ + #define R_GLCDC_OUT_SET_FRQSEL_Msk (0x300UL) /*!< FRQSEL (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_SET_DIRSEL_Pos (4UL) /*!< DIRSEL (Bit 4) */ + #define R_GLCDC_OUT_SET_DIRSEL_Msk (0x10UL) /*!< DIRSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_SET_PHASE_Pos (0UL) /*!< PHASE (Bit 0) */ + #define R_GLCDC_OUT_SET_PHASE_Msk (0x3UL) /*!< PHASE (Bitfield-Mask: 0x03) */ +/* ======================================================== BRIGHT1 ======================================================== */ + #define R_GLCDC_OUT_BRIGHT1_BRTG_Pos (0UL) /*!< BRTG (Bit 0) */ + #define R_GLCDC_OUT_BRIGHT1_BRTG_Msk (0x3ffUL) /*!< BRTG (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BRIGHT2 ======================================================== */ + #define R_GLCDC_OUT_BRIGHT2_BRTB_Pos (16UL) /*!< BRTB (Bit 16) */ + #define R_GLCDC_OUT_BRIGHT2_BRTB_Msk (0x3ff0000UL) /*!< BRTB (Bitfield-Mask: 0x3ff) */ + #define R_GLCDC_OUT_BRIGHT2_BRTR_Pos (0UL) /*!< BRTR (Bit 0) */ + #define R_GLCDC_OUT_BRIGHT2_BRTR_Msk (0x3ffUL) /*!< BRTR (Bitfield-Mask: 0x3ff) */ +/* ======================================================= CONTRAST ======================================================== */ + #define R_GLCDC_OUT_CONTRAST_CONTG_Pos (16UL) /*!< CONTG (Bit 16) */ + #define R_GLCDC_OUT_CONTRAST_CONTG_Msk (0xff0000UL) /*!< CONTG (Bitfield-Mask: 0xff) */ + #define R_GLCDC_OUT_CONTRAST_CONTB_Pos (8UL) /*!< CONTB (Bit 8) */ + #define R_GLCDC_OUT_CONTRAST_CONTB_Msk (0xff00UL) /*!< CONTB (Bitfield-Mask: 0xff) */ + #define R_GLCDC_OUT_CONTRAST_CONTR_Pos (0UL) /*!< CONTR (Bit 0) */ + #define R_GLCDC_OUT_CONTRAST_CONTR_Msk (0xffUL) /*!< CONTR (Bitfield-Mask: 0xff) */ +/* ========================================================= PDTHA ========================================================= */ + #define R_GLCDC_OUT_PDTHA_SEL_Pos (20UL) /*!< SEL (Bit 20) */ + #define R_GLCDC_OUT_PDTHA_SEL_Msk (0x300000UL) /*!< SEL (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_FORM_Pos (16UL) /*!< FORM (Bit 16) */ + #define R_GLCDC_OUT_PDTHA_FORM_Msk (0x30000UL) /*!< FORM (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PA_Pos (12UL) /*!< PA (Bit 12) */ + #define R_GLCDC_OUT_PDTHA_PA_Msk (0x3000UL) /*!< PA (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PB_Pos (8UL) /*!< PB (Bit 8) */ + #define R_GLCDC_OUT_PDTHA_PB_Msk (0x300UL) /*!< PB (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PC_Pos (4UL) /*!< PC (Bit 4) */ + #define R_GLCDC_OUT_PDTHA_PC_Msk (0x30UL) /*!< PC (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PD_Pos (0UL) /*!< PD (Bit 0) */ + #define R_GLCDC_OUT_PDTHA_PD_Msk (0x3UL) /*!< PD (Bitfield-Mask: 0x03) */ +/* ======================================================= CLKPHASE ======================================================== */ + #define R_GLCDC_OUT_CLKPHASE_FRONTGAM_Pos (12UL) /*!< FRONTGAM (Bit 12) */ + #define R_GLCDC_OUT_CLKPHASE_FRONTGAM_Msk (0x1000UL) /*!< FRONTGAM (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_LCDEDGE_Pos (8UL) /*!< LCDEDGE (Bit 8) */ + #define R_GLCDC_OUT_CLKPHASE_LCDEDGE_Msk (0x100UL) /*!< LCDEDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON0EDGE_Pos (6UL) /*!< TCON0EDGE (Bit 6) */ + #define R_GLCDC_OUT_CLKPHASE_TCON0EDGE_Msk (0x40UL) /*!< TCON0EDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON1EDGE_Pos (5UL) /*!< TCON1EDGE (Bit 5) */ + #define R_GLCDC_OUT_CLKPHASE_TCON1EDGE_Msk (0x20UL) /*!< TCON1EDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON2EDGE_Pos (4UL) /*!< TCON2EDGE (Bit 4) */ + #define R_GLCDC_OUT_CLKPHASE_TCON2EDGE_Msk (0x10UL) /*!< TCON2EDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON3EDGE_Pos (3UL) /*!< TCON3EDGE (Bit 3) */ + #define R_GLCDC_OUT_CLKPHASE_TCON3EDGE_Msk (0x8UL) /*!< TCON3EDGE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ TCON ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TIM ========================================================== */ + #define R_GLCDC_TCON_TIM_HALF_Pos (16UL) /*!< HALF (Bit 16) */ + #define R_GLCDC_TCON_TIM_HALF_Msk (0x7ff0000UL) /*!< HALF (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_TIM_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */ + #define R_GLCDC_TCON_TIM_OFFSET_Msk (0x7ffUL) /*!< OFFSET (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STVA1 ========================================================= */ + #define R_GLCDC_TCON_STVA1_VS_Pos (16UL) /*!< VS (Bit 16) */ + #define R_GLCDC_TCON_STVA1_VS_Msk (0x7ff0000UL) /*!< VS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STVA1_VW_Pos (0UL) /*!< VW (Bit 0) */ + #define R_GLCDC_TCON_STVA1_VW_Msk (0x7ffUL) /*!< VW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STVB1 ========================================================= */ + #define R_GLCDC_TCON_STVB1_VS_Pos (16UL) /*!< VS (Bit 16) */ + #define R_GLCDC_TCON_STVB1_VS_Msk (0x7ff0000UL) /*!< VS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STVB1_VW_Pos (0UL) /*!< VW (Bit 0) */ + #define R_GLCDC_TCON_STVB1_VW_Msk (0x7ffUL) /*!< VW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STVA2 ========================================================= */ + #define R_GLCDC_TCON_STVA2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STVA2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STVA2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STVA2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================= STVB2 ========================================================= */ + #define R_GLCDC_TCON_STVB2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STVB2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STVB2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STVB2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================= STHA1 ========================================================= */ + #define R_GLCDC_TCON_STHA1_HS_Pos (16UL) /*!< HS (Bit 16) */ + #define R_GLCDC_TCON_STHA1_HS_Msk (0x7ff0000UL) /*!< HS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STHA1_HW_Pos (0UL) /*!< HW (Bit 0) */ + #define R_GLCDC_TCON_STHA1_HW_Msk (0x7ffUL) /*!< HW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STHB1 ========================================================= */ + #define R_GLCDC_TCON_STHB1_HS_Pos (16UL) /*!< HS (Bit 16) */ + #define R_GLCDC_TCON_STHB1_HS_Msk (0x7ff0000UL) /*!< HS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STHB1_HW_Pos (0UL) /*!< HW (Bit 0) */ + #define R_GLCDC_TCON_STHB1_HW_Msk (0x7ffUL) /*!< HW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STHA2 ========================================================= */ + #define R_GLCDC_TCON_STHA2_HSSEL_Pos (8UL) /*!< HSSEL (Bit 8) */ + #define R_GLCDC_TCON_STHA2_HSSEL_Msk (0x100UL) /*!< HSSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHA2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STHA2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHA2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STHA2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================= STHB2 ========================================================= */ + #define R_GLCDC_TCON_STHB2_HSSEL_Pos (8UL) /*!< HSSEL (Bit 8) */ + #define R_GLCDC_TCON_STHB2_HSSEL_Msk (0x100UL) /*!< HSSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHB2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STHB2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHB2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STHB2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================== DE =========================================================== */ + #define R_GLCDC_TCON_DE_INV_Pos (0UL) /*!< INV (Bit 0) */ + #define R_GLCDC_TCON_DE_INV_Msk (0x1UL) /*!< INV (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SYSCNT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DTCTEN ========================================================= */ + #define R_GLCDC_SYSCNT_DTCTEN_L2UNDFDTC_Pos (2UL) /*!< L2UNDFDTC (Bit 2) */ + #define R_GLCDC_SYSCNT_DTCTEN_L2UNDFDTC_Msk (0x4UL) /*!< L2UNDFDTC (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_DTCTEN_L1UNDFDTC_Pos (1UL) /*!< L1UNDFDTC (Bit 1) */ + #define R_GLCDC_SYSCNT_DTCTEN_L1UNDFDTC_Msk (0x2UL) /*!< L1UNDFDTC (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_DTCTEN_VPOSDTC_Pos (0UL) /*!< VPOSDTC (Bit 0) */ + #define R_GLCDC_SYSCNT_DTCTEN_VPOSDTC_Msk (0x1UL) /*!< VPOSDTC (Bitfield-Mask: 0x01) */ +/* ========================================================= INTEN ========================================================= */ + #define R_GLCDC_SYSCNT_INTEN_L2UNDFINTEN_Pos (2UL) /*!< L2UNDFINTEN (Bit 2) */ + #define R_GLCDC_SYSCNT_INTEN_L2UNDFINTEN_Msk (0x4UL) /*!< L2UNDFINTEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_INTEN_L1UNDFINTEN_Pos (1UL) /*!< L1UNDFINTEN (Bit 1) */ + #define R_GLCDC_SYSCNT_INTEN_L1UNDFINTEN_Msk (0x2UL) /*!< L1UNDFINTEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_INTEN_VPOSINTEN_Pos (0UL) /*!< VPOSINTEN (Bit 0) */ + #define R_GLCDC_SYSCNT_INTEN_VPOSINTEN_Msk (0x1UL) /*!< VPOSINTEN (Bitfield-Mask: 0x01) */ +/* ========================================================= STCLR ========================================================= */ + #define R_GLCDC_SYSCNT_STCLR_L2UNDFCLR_Pos (2UL) /*!< L2UNDFCLR (Bit 2) */ + #define R_GLCDC_SYSCNT_STCLR_L2UNDFCLR_Msk (0x4UL) /*!< L2UNDFCLR (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STCLR_L1UNDFCLR_Pos (1UL) /*!< L1UNDFCLR (Bit 1) */ + #define R_GLCDC_SYSCNT_STCLR_L1UNDFCLR_Msk (0x2UL) /*!< L1UNDFCLR (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STCLR_VPOSCLR_Pos (0UL) /*!< VPOSCLR (Bit 0) */ + #define R_GLCDC_SYSCNT_STCLR_VPOSCLR_Msk (0x1UL) /*!< VPOSCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= STMON ========================================================= */ + #define R_GLCDC_SYSCNT_STMON_L2UNDF_Pos (2UL) /*!< L2UNDF (Bit 2) */ + #define R_GLCDC_SYSCNT_STMON_L2UNDF_Msk (0x4UL) /*!< L2UNDF (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STMON_L1UNDF_Pos (1UL) /*!< L1UNDF (Bit 1) */ + #define R_GLCDC_SYSCNT_STMON_L1UNDF_Msk (0x2UL) /*!< L1UNDF (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STMON_VPOS_Pos (0UL) /*!< VPOS (Bit 0) */ + #define R_GLCDC_SYSCNT_STMON_VPOS_Msk (0x1UL) /*!< VPOS (Bitfield-Mask: 0x01) */ +/* ======================================================= PANEL_CLK ======================================================= */ + #define R_GLCDC_SYSCNT_PANEL_CLK_VER_Pos (16UL) /*!< VER (Bit 16) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_VER_Msk (0xffff0000UL) /*!< VER (Bitfield-Mask: 0xffff) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_PIXSEL_Pos (12UL) /*!< PIXSEL (Bit 12) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_PIXSEL_Msk (0x1000UL) /*!< PIXSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKSEL_Pos (8UL) /*!< CLKSEL (Bit 8) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKSEL_Msk (0x100UL) /*!< CLKSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKEN_Pos (6UL) /*!< CLKEN (Bit 6) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKEN_Msk (0x40UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_DCDR_Pos (0UL) /*!< DCDR (Bit 0) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_DCDR_Msk (0x3fUL) /*!< DCDR (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ GTDLYR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== A =========================================================== */ + #define R_GPT_ODC_GTDLYR_A_DLY_Pos (0UL) /*!< DLY (Bit 0) */ + #define R_GPT_ODC_GTDLYR_A_DLY_Msk (0x7fUL) /*!< DLY (Bitfield-Mask: 0x7f) */ +/* =========================================================== B =========================================================== */ + #define R_GPT_ODC_GTDLYR_B_DLY_Pos (0UL) /*!< DLY (Bit 0) */ + #define R_GPT_ODC_GTDLYR_B_DLY_Msk (0x7fUL) /*!< DLY (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ + #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ + #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ + #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ REGION ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos (3UL) /*!< PP (Bit 3) */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk (0x8UL) /*!< PP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* =========================================================== S =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ +/* =========================================================== E =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ GROUP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EN =========================================================== */ + #define R_MPU_MMPU_GROUP_EN_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_EN_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================= ENPT ========================================================== */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== RPT ========================================================== */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== RPT_SEC ======================================================== */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== CTL ========================================================== */ + #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ + #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== SA =========================================================== */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== EA =========================================================== */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ PIN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PmnPFS_BY ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ +/* ======================================================= PmnPFS_HA ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ +/* ======================================================== PmnPFS ========================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ PMSAR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PMSAR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ RTCCR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RTCCR ========================================================= */ + #define R_RTC_RTCCR_RTCCR_TCEN_Pos (7UL) /*!< TCEN (Bit 7) */ + #define R_RTC_RTCCR_RTCCR_TCEN_Msk (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ + #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ + #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RSEC ========================================================== */ + #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ + #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMIN ========================================================== */ + #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ + #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ +/* ========================================================== RHR ========================================================== */ + #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ + #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RDAY ========================================================== */ + #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ + #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMON ========================================================== */ + #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_HS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_HS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_HS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_HS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_HS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ CMCFGCS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CMCFG0 ========================================================= */ + #define R_XSPI0_CMCFGCS_CMCFG0_FFMT_Pos (0UL) /*!< FFMT (Bit 0) */ + #define R_XSPI0_CMCFGCS_CMCFG0_FFMT_Msk (0x3UL) /*!< FFMT (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDSIZE_Pos (2UL) /*!< ADDSIZE (Bit 2) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDSIZE_Msk (0xcUL) /*!< ADDSIZE (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CMCFGCS_CMCFG0_WPBSTMD_Pos (4UL) /*!< WPBSTMD (Bit 4) */ + #define R_XSPI0_CMCFGCS_CMCFG0_WPBSTMD_Msk (0x10UL) /*!< WPBSTMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ARYAMD_Pos (5UL) /*!< ARYAMD (Bit 5) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ARYAMD_Msk (0x20UL) /*!< ARYAMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDRPEN_Pos (16UL) /*!< ADDRPEN (Bit 16) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDRPEN_Msk (0xff0000UL) /*!< ADDRPEN (Bitfield-Mask: 0xff) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDRPCD_Pos (24UL) /*!< ADDRPCD (Bit 24) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDRPCD_Msk (0xff000000UL) /*!< ADDRPCD (Bitfield-Mask: 0xff) */ +/* ======================================================== CMCFG1 ========================================================= */ + #define R_XSPI0_CMCFGCS_CMCFG1_RDCMD_Pos (0UL) /*!< RDCMD (Bit 0) */ + #define R_XSPI0_CMCFGCS_CMCFG1_RDCMD_Msk (0xffffUL) /*!< RDCMD (Bitfield-Mask: 0xffff) */ + #define R_XSPI0_CMCFGCS_CMCFG1_RDLATE_Pos (16UL) /*!< RDLATE (Bit 16) */ + #define R_XSPI0_CMCFGCS_CMCFG1_RDLATE_Msk (0x1f0000UL) /*!< RDLATE (Bitfield-Mask: 0x1f) */ +/* ======================================================== CMCFG2 ========================================================= */ + #define R_XSPI0_CMCFGCS_CMCFG2_WRCMD_Pos (0UL) /*!< WRCMD (Bit 0) */ + #define R_XSPI0_CMCFGCS_CMCFG2_WRCMD_Msk (0xffffUL) /*!< WRCMD (Bitfield-Mask: 0xffff) */ + #define R_XSPI0_CMCFGCS_CMCFG2_WRLATE_Pos (16UL) /*!< WRLATE (Bit 16) */ + #define R_XSPI0_CMCFGCS_CMCFG2_WRLATE_Msk (0x1f0000UL) /*!< WRLATE (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ CDBUF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CDT ========================================================== */ + #define R_XSPI0_CDBUF_CDT_CMDSIZE_Pos (0UL) /*!< CMDSIZE (Bit 0) */ + #define R_XSPI0_CDBUF_CDT_CMDSIZE_Msk (0x3UL) /*!< CMDSIZE (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CDBUF_CDT_ADDSIZE_Pos (2UL) /*!< ADDSIZE (Bit 2) */ + #define R_XSPI0_CDBUF_CDT_ADDSIZE_Msk (0x1cUL) /*!< ADDSIZE (Bitfield-Mask: 0x07) */ + #define R_XSPI0_CDBUF_CDT_DATASIZE_Pos (5UL) /*!< DATASIZE (Bit 5) */ + #define R_XSPI0_CDBUF_CDT_DATASIZE_Msk (0x1e0UL) /*!< DATASIZE (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_CDBUF_CDT_LATE_Pos (9UL) /*!< LATE (Bit 9) */ + #define R_XSPI0_CDBUF_CDT_LATE_Msk (0x3e00UL) /*!< LATE (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CDBUF_CDT_TRTYPE_Pos (15UL) /*!< TRTYPE (Bit 15) */ + #define R_XSPI0_CDBUF_CDT_TRTYPE_Msk (0x8000UL) /*!< TRTYPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDBUF_CDT_CMD_Pos (16UL) /*!< CMD (Bit 16) */ + #define R_XSPI0_CDBUF_CDT_CMD_Msk (0xffff0000UL) /*!< CMD (Bitfield-Mask: 0xffff) */ +/* ========================================================== CDA ========================================================== */ + #define R_XSPI0_CDBUF_CDA_ADD_Pos (0UL) /*!< ADD (Bit 0) */ + #define R_XSPI0_CDBUF_CDA_ADD_Msk (0xffffffffUL) /*!< ADD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDD0 ========================================================== */ + #define R_XSPI0_CDBUF_CDD0_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_XSPI0_CDBUF_CDD0_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDD1 ========================================================== */ + #define R_XSPI0_CDBUF_CDD1_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_XSPI0_CDBUF_CDD1_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CCCTLCS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CCCTL0 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL0_CAEN_Pos (0UL) /*!< CAEN (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CAEN_Msk (0x1UL) /*!< CAEN (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CANOWR_Pos (1UL) /*!< CANOWR (Bit 1) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CANOWR_Msk (0x2UL) /*!< CANOWR (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CAITV_Pos (8UL) /*!< CAITV (Bit 8) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CAITV_Msk (0x1f00UL) /*!< CAITV (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CASFTSTA_Pos (16UL) /*!< CASFTSTA (Bit 16) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CASFTSTA_Msk (0x1f0000UL) /*!< CASFTSTA (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CASFTEND_Pos (24UL) /*!< CASFTEND (Bit 24) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CASFTEND_Msk (0x1f000000UL) /*!< CASFTEND (Bitfield-Mask: 0x1f) */ +/* ======================================================== CCCTL1 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL1_CACMDSIZE_Pos (0UL) /*!< CACMDSIZE (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CACMDSIZE_Msk (0x3UL) /*!< CACMDSIZE (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CAADDSIZE_Pos (2UL) /*!< CAADDSIZE (Bit 2) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CAADDSIZE_Msk (0x1cUL) /*!< CAADDSIZE (Bitfield-Mask: 0x07) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CADATASIZE_Pos (5UL) /*!< CADATASIZE (Bit 5) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CADATASIZE_Msk (0x1e0UL) /*!< CADATASIZE (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CAWRLATE_Pos (16UL) /*!< CAWRLATE (Bit 16) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CAWRLATE_Msk (0x1f0000UL) /*!< CAWRLATE (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CARDLATE_Pos (24UL) /*!< CARDLATE (Bit 24) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CARDLATE_Msk (0x1f000000UL) /*!< CARDLATE (Bitfield-Mask: 0x1f) */ +/* ======================================================== CCCTL2 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL2_CAWRCMD_Pos (0UL) /*!< CAWRCMD (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL2_CAWRCMD_Msk (0xffffUL) /*!< CAWRCMD (Bitfield-Mask: 0xffff) */ + #define R_XSPI0_CCCTLCS_CCCTL2_CARDCMD_Pos (16UL) /*!< CARDCMD (Bit 16) */ + #define R_XSPI0_CCCTLCS_CCCTL2_CARDCMD_Msk (0xffff0000UL) /*!< CARDCMD (Bitfield-Mask: 0xffff) */ +/* ======================================================== CCCTL3 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL3_CAADD_Pos (0UL) /*!< CAADD (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL3_CAADD_Msk (0xffffffffUL) /*!< CAADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL4 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL4_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL4_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL5 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL5_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL5_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL6 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL6_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL6_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL7 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL7_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL7_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= AGTCR ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTMR1 ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTMR2 ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ +/* ===================================================== AGTIOSEL_ALT ====================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ +/* ======================================================== AGTIOC ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTISR ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTCMSR ======================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ +/* ======================================================= AGTIOSEL ======================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ AGT16 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGTX0_AGT16_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGTX0_AGT16_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ AGT32 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGTX0_AGT32_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGTX0_AGT32_AGT_AGT_Msk (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CABPPPFLC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== LEVEL0 ========================================================= */ + #define R_COMA_CABPPPFLC_LEVEL0_PPDL_Pos (0UL) /*!< PPDL (Bit 0) */ + #define R_COMA_CABPPPFLC_LEVEL0_PPDL_Msk (0x3ffUL) /*!< PPDL (Bitfield-Mask: 0x3ff) */ + #define R_COMA_CABPPPFLC_LEVEL0_PPAL_Pos (16UL) /*!< PPAL (Bit 16) */ + #define R_COMA_CABPPPFLC_LEVEL0_PPAL_Msk (0x3ff0000UL) /*!< PPAL (Bitfield-Mask: 0x3ff) */ +/* ======================================================== LEVEL1 ========================================================= */ + #define R_COMA_CABPPPFLC_LEVEL1_PPDL_Pos (0UL) /*!< PPDL (Bit 0) */ + #define R_COMA_CABPPPFLC_LEVEL1_PPDL_Msk (0x3ffUL) /*!< PPDL (Bitfield-Mask: 0x3ff) */ + #define R_COMA_CABPPPFLC_LEVEL1_PPAL_Pos (16UL) /*!< PPAL (Bit 16) */ + #define R_COMA_CABPPPFLC_LEVEL1_PPAL_Msk (0x3ff0000UL) /*!< PPAL (Bitfield-Mask: 0x3ff) */ + +/* =========================================================================================================================== */ +/* ================ IPCNMI ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== STA ========================================================== */ + #define R_IPC_IPCNMI_STA_NMI_Pos (0UL) /*!< NMI (Bit 0) */ + #define R_IPC_IPCNMI_STA_NMI_Msk (0x1UL) /*!< NMI (Bitfield-Mask: 0x01) */ +/* ========================================================== SET ========================================================== */ + #define R_IPC_IPCNMI_SET_SET_Pos (0UL) /*!< SET (Bit 0) */ + #define R_IPC_IPCNMI_SET_SET_Msk (0x1UL) /*!< SET (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_IPC_IPCNMI_CLR_CLR_Pos (0UL) /*!< CLR (Bit 0) */ + #define R_IPC_IPCNMI_CLR_CLR_Msk (0x1UL) /*!< CLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ CH ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== STA ========================================================== */ + #define R_IPC_IPC_CH_STA_IRQ_Pos (0UL) /*!< IRQ (Bit 0) */ + #define R_IPC_IPC_CH_STA_IRQ_Msk (0x1UL) /*!< IRQ (Bitfield-Mask: 0x01) */ + #define R_IPC_IPC_CH_STA_RDY_Pos (16UL) /*!< RDY (Bit 16) */ + #define R_IPC_IPC_CH_STA_RDY_Msk (0x10000UL) /*!< RDY (Bitfield-Mask: 0x01) */ + #define R_IPC_IPC_CH_STA_FULL_Pos (17UL) /*!< FULL (Bit 17) */ + #define R_IPC_IPC_CH_STA_FULL_Msk (0x20000UL) /*!< FULL (Bitfield-Mask: 0x01) */ + #define R_IPC_IPC_CH_STA_RERR_Pos (24UL) /*!< RERR (Bit 24) */ + #define R_IPC_IPC_CH_STA_RERR_Msk (0x1000000UL) /*!< RERR (Bitfield-Mask: 0x01) */ + #define R_IPC_IPC_CH_STA_FERR_Pos (25UL) /*!< FERR (Bit 25) */ + #define R_IPC_IPC_CH_STA_FERR_Msk (0x2000000UL) /*!< FERR (Bitfield-Mask: 0x01) */ +/* ========================================================== SET ========================================================== */ + #define R_IPC_IPC_CH_SET_SET_Pos (0UL) /*!< SET (Bit 0) */ + #define R_IPC_IPC_CH_SET_SET_Msk (0x1UL) /*!< SET (Bitfield-Mask: 0x01) */ +/* ========================================================== TXD ========================================================== */ + #define R_IPC_IPC_CH_TXD_TXD_Pos (0UL) /*!< TXD (Bit 0) */ + #define R_IPC_IPC_CH_TXD_TXD_Msk (0xffffffffUL) /*!< TXD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RXD ========================================================== */ + #define R_IPC_IPC_CH_RXD_RXD_Pos (0UL) /*!< RXD (Bit 0) */ + #define R_IPC_IPC_CH_RXD_RXD_Msk (0xffffffffUL) /*!< RXD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== CLR ========================================================== */ + #define R_IPC_IPC_CH_CLR_CLR_Pos (0UL) /*!< CLR (Bit 0) */ + #define R_IPC_IPC_CH_CLR_CLR_Msk (0x1UL) /*!< CLR (Bitfield-Mask: 0x01) */ + #define R_IPC_IPC_CH_CLR_RST_Pos (16UL) /*!< RST (Bit 16) */ + #define R_IPC_IPC_CH_CLR_RST_Msk (0x10000UL) /*!< RST (Bitfield-Mask: 0x01) */ + #define R_IPC_IPC_CH_CLR_RCLR_Pos (24UL) /*!< RCLR (Bit 24) */ + #define R_IPC_IPC_CH_CLR_RCLR_Msk (0x1000000UL) /*!< RCLR (Bitfield-Mask: 0x01) */ + #define R_IPC_IPC_CH_CLR_FCLR_Pos (25UL) /*!< FCLR (Bit 25) */ + #define R_IPC_IPC_CH_CLR_FCLR_Msk (0x2000000UL) /*!< FCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ IPC ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ CH ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PDSTRTR ======================================================== */ + #define R_PDM_CH_PDSTRTR_STRTRG_Pos (0UL) /*!< STRTRG (Bit 0) */ + #define R_PDM_CH_PDSTRTR_STRTRG_Msk (0x1UL) /*!< STRTRG (Bitfield-Mask: 0x01) */ +/* ======================================================== PDSTPTR ======================================================== */ + #define R_PDM_CH_PDSTPTR_STPTRG_Pos (0UL) /*!< STPTRG (Bit 0) */ + #define R_PDM_CH_PDSTPTR_STPTRG_Msk (0x1UL) /*!< STPTRG (Bitfield-Mask: 0x01) */ +/* ======================================================== PDCHGTR ======================================================== */ + #define R_PDM_CH_PDCHGTR_CHGTRG_Pos (0UL) /*!< CHGTRG (Bit 0) */ + #define R_PDM_CH_PDCHGTR_CHGTRG_Msk (0x1UL) /*!< CHGTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= PDICR ========================================================= */ + #define R_PDM_CH_PDICR_ISDE_Pos (1UL) /*!< ISDE (Bit 1) */ + #define R_PDM_CH_PDICR_ISDE_Msk (0x2UL) /*!< ISDE (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDICR_IDRE_Pos (2UL) /*!< IDRE (Bit 2) */ + #define R_PDM_CH_PDICR_IDRE_Msk (0x4UL) /*!< IDRE (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDICR_IEDE_Pos (16UL) /*!< IEDE (Bit 16) */ + #define R_PDM_CH_PDICR_IEDE_Msk (0x10000UL) /*!< IEDE (Bitfield-Mask: 0x01) */ +/* ======================================================== PDSDCR ========================================================= */ + #define R_PDM_CH_PDSDCR_SDE_Pos (1UL) /*!< SDE (Bit 1) */ + #define R_PDM_CH_PDSDCR_SDE_Msk (0x2UL) /*!< SDE (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSDCR_SCDE_Pos (16UL) /*!< SCDE (Bit 16) */ + #define R_PDM_CH_PDSDCR_SCDE_Msk (0x10000UL) /*!< SCDE (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSDCR_OVLDE_Pos (17UL) /*!< OVLDE (Bit 17) */ + #define R_PDM_CH_PDSDCR_OVLDE_Msk (0x20000UL) /*!< OVLDE (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSDCR_OVUDE_Pos (18UL) /*!< OVUDE (Bit 18) */ + #define R_PDM_CH_PDSDCR_OVUDE_Msk (0x40000UL) /*!< OVUDE (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSDCR_BFOWDE_Pos (27UL) /*!< BFOWDE (Bit 27) */ + #define R_PDM_CH_PDSDCR_BFOWDE_Msk (0x8000000UL) /*!< BFOWDE (Bitfield-Mask: 0x01) */ +/* ========================================================= PDSR ========================================================== */ + #define R_PDM_CH_PDSR_STATE_Pos (0UL) /*!< STATE (Bit 0) */ + #define R_PDM_CH_PDSR_STATE_Msk (0x1UL) /*!< STATE (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSR_SDF_Pos (1UL) /*!< SDF (Bit 1) */ + #define R_PDM_CH_PDSR_SDF_Msk (0x2UL) /*!< SDF (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSR_DRF_Pos (2UL) /*!< DRF (Bit 2) */ + #define R_PDM_CH_PDSR_DRF_Msk (0x4UL) /*!< DRF (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSR_SCDF_Pos (16UL) /*!< SCDF (Bit 16) */ + #define R_PDM_CH_PDSR_SCDF_Msk (0x10000UL) /*!< SCDF (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSR_OVLDF_Pos (17UL) /*!< OVLDF (Bit 17) */ + #define R_PDM_CH_PDSR_OVLDF_Msk (0x20000UL) /*!< OVLDF (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSR_OVUDF_Pos (18UL) /*!< OVUDF (Bit 18) */ + #define R_PDM_CH_PDSR_OVUDF_Msk (0x40000UL) /*!< OVUDF (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSR_BFOWDF_Pos (27UL) /*!< BFOWDF (Bit 27) */ + #define R_PDM_CH_PDSR_BFOWDF_Msk (0x8000000UL) /*!< BFOWDF (Bitfield-Mask: 0x01) */ +/* ========================================================= PDSCR ========================================================= */ + #define R_PDM_CH_PDSCR_SDFC_Pos (1UL) /*!< SDFC (Bit 1) */ + #define R_PDM_CH_PDSCR_SDFC_Msk (0x2UL) /*!< SDFC (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSCR_SCDFC_Pos (16UL) /*!< SCDFC (Bit 16) */ + #define R_PDM_CH_PDSCR_SCDFC_Msk (0x10000UL) /*!< SCDFC (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSCR_OVLDFC_Pos (17UL) /*!< OVLDFC (Bit 17) */ + #define R_PDM_CH_PDSCR_OVLDFC_Msk (0x20000UL) /*!< OVLDFC (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSCR_OVUDFC_Pos (18UL) /*!< OVUDFC (Bit 18) */ + #define R_PDM_CH_PDSCR_OVUDFC_Msk (0x40000UL) /*!< OVUDFC (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSCR_BFOWDFC_Pos (27UL) /*!< BFOWDFC (Bit 27) */ + #define R_PDM_CH_PDSCR_BFOWDFC_Msk (0x8000000UL) /*!< BFOWDFC (Bitfield-Mask: 0x01) */ +/* ======================================================== PDMDSR ========================================================= */ + #define R_PDM_CH_PDMDSR_INPSEL_Pos (0UL) /*!< INPSEL (Bit 0) */ + #define R_PDM_CH_PDMDSR_INPSEL_Msk (0x1UL) /*!< INPSEL (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDMDSR_SFMD_Pos (4UL) /*!< SFMD (Bit 4) */ + #define R_PDM_CH_PDMDSR_SFMD_Msk (0x70UL) /*!< SFMD (Bitfield-Mask: 0x07) */ + #define R_PDM_CH_PDMDSR_HFIS_Pos (8UL) /*!< HFIS (Bit 8) */ + #define R_PDM_CH_PDMDSR_HFIS_Msk (0x300UL) /*!< HFIS (Bitfield-Mask: 0x03) */ + #define R_PDM_CH_PDMDSR_CFIS_Pos (12UL) /*!< CFIS (Bit 12) */ + #define R_PDM_CH_PDMDSR_CFIS_Msk (0x3000UL) /*!< CFIS (Bitfield-Mask: 0x03) */ + #define R_PDM_CH_PDMDSR_LFIS_Pos (16UL) /*!< LFIS (Bit 16) */ + #define R_PDM_CH_PDMDSR_LFIS_Msk (0x30000UL) /*!< LFIS (Bitfield-Mask: 0x03) */ + #define R_PDM_CH_PDMDSR_SDMAMD_Pos (24UL) /*!< SDMAMD (Bit 24) */ + #define R_PDM_CH_PDMDSR_SDMAMD_Msk (0x3000000UL) /*!< SDMAMD (Bitfield-Mask: 0x03) */ + #define R_PDM_CH_PDMDSR_DBIS_Pos (28UL) /*!< DBIS (Bit 28) */ + #define R_PDM_CH_PDMDSR_DBIS_Msk (0xf0000000UL) /*!< DBIS (Bitfield-Mask: 0x0f) */ +/* ======================================================== PDSFCR ========================================================= */ + #define R_PDM_CH_PDSFCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_PDM_CH_PDSFCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ + #define R_PDM_CH_PDSFCR_SINCDEC_Pos (16UL) /*!< SINCDEC (Bit 16) */ + #define R_PDM_CH_PDSFCR_SINCDEC_Msk (0xff0000UL) /*!< SINCDEC (Bitfield-Mask: 0xff) */ + #define R_PDM_CH_PDSFCR_SINCRNG_Pos (24UL) /*!< SINCRNG (Bit 24) */ + #define R_PDM_CH_PDSFCR_SINCRNG_Msk (0x1f000000UL) /*!< SINCRNG (Bitfield-Mask: 0x1f) */ +/* ======================================================= PDHFCS0R ======================================================== */ + #define R_PDM_CH_PDHFCS0R_HFS0_Pos (0UL) /*!< HFS0 (Bit 0) */ + #define R_PDM_CH_PDHFCS0R_HFS0_Msk (0xffffUL) /*!< HFS0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= PDHFCK1R ======================================================== */ + #define R_PDM_CH_PDHFCK1R_HFK1_Pos (0UL) /*!< HFK1 (Bit 0) */ + #define R_PDM_CH_PDHFCK1R_HFK1_Msk (0xffffUL) /*!< HFK1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== PDHFCHR ======================================================== */ + #define R_PDM_CH_PDHFCHR_HFHn_Pos (0UL) /*!< HFHn (Bit 0) */ + #define R_PDM_CH_PDHFCHR_HFHn_Msk (0xffffUL) /*!< HFHn (Bitfield-Mask: 0xffff) */ +/* ======================================================== PDCFCHR ======================================================== */ + #define R_PDM_CH_PDCFCHR_CFHn_Pos (0UL) /*!< CFHn (Bit 0) */ + #define R_PDM_CH_PDCFCHR_CFHn_Msk (0x1fffUL) /*!< CFHn (Bitfield-Mask: 0x1fff) */ +/* ====================================================== PDLFCH010R ======================================================= */ + #define R_PDM_CH_PDLFCH010R_LFH010_Pos (0UL) /*!< LFH010 (Bit 0) */ + #define R_PDM_CH_PDLFCH010R_LFH010_Msk (0x1fffUL) /*!< LFH010 (Bitfield-Mask: 0x1fff) */ +/* ======================================================= PDLFCH1R ======================================================== */ + #define R_PDM_CH_PDLFCH1R_LFH1n_Pos (0UL) /*!< LFH1n (Bit 0) */ + #define R_PDM_CH_PDLFCH1R_LFH1n_Msk (0x1fffUL) /*!< LFH1n (Bitfield-Mask: 0x1fff) */ +/* ======================================================== PDSDLTR ======================================================== */ + #define R_PDM_CH_PDSDLTR_SDETL_Pos (0UL) /*!< SDETL (Bit 0) */ + #define R_PDM_CH_PDSDLTR_SDETL_Msk (0xfffffUL) /*!< SDETL (Bitfield-Mask: 0xfffff) */ +/* ======================================================== PDSDUTR ======================================================== */ + #define R_PDM_CH_PDSDUTR_SDETU_Pos (0UL) /*!< SDETU (Bit 0) */ + #define R_PDM_CH_PDSDUTR_SDETU_Msk (0xfffffUL) /*!< SDETU (Bitfield-Mask: 0xfffff) */ +/* ======================================================== PDDBCR ========================================================= */ + #define R_PDM_CH_PDDBCR_DATRITHR_Pos (0UL) /*!< DATRITHR (Bit 0) */ + #define R_PDM_CH_PDDBCR_DATRITHR_Msk (0x7UL) /*!< DATRITHR (Bitfield-Mask: 0x07) */ +/* ======================================================== PDSCTSR ======================================================== */ + #define R_PDM_CH_PDSCTSR_SCDL_Pos (0UL) /*!< SCDL (Bit 0) */ + #define R_PDM_CH_PDSCTSR_SCDL_Msk (0x1fffUL) /*!< SCDL (Bitfield-Mask: 0x1fff) */ + #define R_PDM_CH_PDSCTSR_SCDH_Pos (16UL) /*!< SCDH (Bit 16) */ + #define R_PDM_CH_PDSCTSR_SCDH_Msk (0x1fff0000UL) /*!< SCDH (Bitfield-Mask: 0x1fff) */ +/* ======================================================== PDOVLTR ======================================================== */ + #define R_PDM_CH_PDOVLTR_OVDL_Pos (0UL) /*!< OVDL (Bit 0) */ + #define R_PDM_CH_PDOVLTR_OVDL_Msk (0xfffffUL) /*!< OVDL (Bitfield-Mask: 0xfffff) */ +/* ======================================================== PDOVUTR ======================================================== */ + #define R_PDM_CH_PDOVUTR_OVDU_Pos (0UL) /*!< OVDU (Bit 0) */ + #define R_PDM_CH_PDOVUTR_OVDU_Msk (0xfffffUL) /*!< OVDU (Bitfield-Mask: 0xfffff) */ +/* ======================================================== PDDRCR ========================================================= */ + #define R_PDM_CH_PDDRCR_DATRE_Pos (0UL) /*!< DATRE (Bit 0) */ + #define R_PDM_CH_PDDRCR_DATRE_Msk (0x1UL) /*!< DATRE (Bitfield-Mask: 0x01) */ +/* ========================================================= PDDCR ========================================================= */ + #define R_PDM_CH_PDDCR_DATC_Pos (0UL) /*!< DATC (Bit 0) */ + #define R_PDM_CH_PDDCR_DATC_Msk (0x1UL) /*!< DATC (Bitfield-Mask: 0x01) */ +/* ========================================================= PDDRR ========================================================= */ + #define R_PDM_CH_PDDRR_DAT_Pos (0UL) /*!< DAT (Bit 0) */ + #define R_PDM_CH_PDDRR_DAT_Msk (0xfffffUL) /*!< DAT (Bitfield-Mask: 0xfffff) */ +/* ========================================================= PDDSR ========================================================= */ + #define R_PDM_CH_PDDSR_DATNUM_Pos (0UL) /*!< DATNUM (Bit 0) */ + #define R_PDM_CH_PDDSR_DATNUM_Msk (0xffUL) /*!< DATNUM (Bitfield-Mask: 0xff) */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CMPCTL ========================================================= */ + #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ + #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ + #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ + #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ + #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ +/* ======================================================== CMPSEL0 ======================================================== */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== CMPSEL1 ======================================================== */ + #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ +/* ======================================================== CMPMON ========================================================= */ + #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ + #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ +/* ========================================================= CPIOC ========================================================= */ + #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ + #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ + #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPINTCTL ======================================================== */ + #define R_ACMPHS0_CPINTCTL_MSKE_Pos (0UL) /*!< MSKE (Bit 0) */ + #define R_ACMPHS0_CPINTCTL_MSKE_Msk (0x1UL) /*!< MSKE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPMSKCTL ======================================================== */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Pos (0UL) /*!< MSKSEL (Bit 0) */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Msk (0x7UL) /*!< MSKSEL (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PSARB ========================================================= */ + #define R_PSCU_PSARB_PSARB_Pos (0UL) /*!< PSARB (Bit 0) */ + #define R_PSCU_PSARB_PSARB_Msk (0x1UL) /*!< PSARB (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARC ========================================================= */ + #define R_PSCU_PSARC_PSARC_Pos (0UL) /*!< PSARC (Bit 0) */ + #define R_PSCU_PSARC_PSARC_Msk (0x1UL) /*!< PSARC (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARD ========================================================= */ + #define R_PSCU_PSARD_PSARD_Pos (0UL) /*!< PSARD (Bit 0) */ + #define R_PSCU_PSARD_PSARD_Msk (0x1UL) /*!< PSARD (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARE ========================================================= */ + #define R_PSCU_PSARE_PSARE_Pos (0UL) /*!< PSARE (Bit 0) */ + #define R_PSCU_PSARE_PSARE_Msk (0x1UL) /*!< PSARE (Bitfield-Mask: 0x01) */ +/* ========================================================= MSSAR ========================================================= */ + #define R_PSCU_MSSAR_MSSAR_Pos (0UL) /*!< MSSAR (Bit 0) */ + #define R_PSCU_MSSAR_MSSAR_Msk (0x1UL) /*!< MSSAR (Bitfield-Mask: 0x01) */ +/* ========================================================= PPARB ========================================================= */ + #define R_PSCU_PPARB_PPARB_Pos (0UL) /*!< PPARB (Bit 0) */ + #define R_PSCU_PPARB_PPARB_Msk (0x1UL) /*!< PPARB (Bitfield-Mask: 0x01) */ +/* ========================================================= PPARC ========================================================= */ + #define R_PSCU_PPARC_PPARC_Pos (0UL) /*!< PPARC (Bit 0) */ + #define R_PSCU_PPARC_PPARC_Msk (0x1UL) /*!< PPARC (Bitfield-Mask: 0x01) */ +/* ========================================================= PPARD ========================================================= */ + #define R_PSCU_PPARD_PPARD_Pos (0UL) /*!< PPARD (Bit 0) */ + #define R_PSCU_PPARD_PPARD_Msk (0x1UL) /*!< PPARD (Bitfield-Mask: 0x01) */ +/* ========================================================= PPARE ========================================================= */ + #define R_PSCU_PPARE_PPARE_Pos (0UL) /*!< PPARE (Bit 0) */ + #define R_PSCU_PPARE_PPARE_Msk (0x1UL) /*!< PPARE (Bitfield-Mask: 0x01) */ +/* ========================================================= MSPAR ========================================================= */ + #define R_PSCU_MSPAR_MSPAR_Pos (0UL) /*!< MSPAR (Bit 0) */ + #define R_PSCU_MSPAR_MSPAR_Msk (0x1UL) /*!< MSPAR (Bitfield-Mask: 0x01) */ +/* ======================================================= CFSAMONA ======================================================== */ + #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ + #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ +/* ======================================================== DLMMON ========================================================= */ + #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */ + #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFSAMON ======================================================== */ + #define R_PSCU_SFSAMON_SFS_Pos (15UL) /*!< SFS (Bit 15) */ + #define R_PSCU_SFSAMON_SFS_Msk (0xff8000UL) /*!< SFS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CACR0 ========================================================= */ + #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ + #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR1 ========================================================= */ + #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ + #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ + #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ + #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR2 ========================================================= */ + #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ + #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ + #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ + #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ + #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ +/* ========================================================= CAICR ========================================================= */ + #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ + #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ + #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ + #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ + #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ + #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ + #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CASTR ========================================================= */ + #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ + #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ + #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ + #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ +/* ======================================================== CAULVR ========================================================= */ + #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ + #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CALLVR ========================================================= */ + #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ + #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CACNTBR ======================================================== */ + #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ + #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CANFD0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CFDGCFG ======================================================== */ + #define R_CANFD_CFDGCFG_TPRI_Pos (0UL) /*!< TPRI (Bit 0) */ + #define R_CANFD_CFDGCFG_TPRI_Msk (0x1UL) /*!< TPRI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DCE_Pos (1UL) /*!< DCE (Bit 1) */ + #define R_CANFD_CFDGCFG_DCE_Msk (0x2UL) /*!< DCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DRE_Pos (2UL) /*!< DRE (Bit 2) */ + #define R_CANFD_CFDGCFG_DRE_Msk (0x4UL) /*!< DRE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_MME_Pos (3UL) /*!< MME (Bit 3) */ + #define R_CANFD_CFDGCFG_MME_Msk (0x8UL) /*!< MME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DCS_Pos (4UL) /*!< DCS (Bit 4) */ + #define R_CANFD_CFDGCFG_DCS_Msk (0x10UL) /*!< DCS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_CMPOC_Pos (5UL) /*!< CMPOC (Bit 5) */ + #define R_CANFD_CFDGCFG_CMPOC_Msk (0x20UL) /*!< CMPOC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_TSP_Pos (8UL) /*!< TSP (Bit 8) */ + #define R_CANFD_CFDGCFG_TSP_Msk (0xf00UL) /*!< TSP (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGCFG_TSSS_Pos (12UL) /*!< TSSS (Bit 12) */ + #define R_CANFD_CFDGCFG_TSSS_Msk (0x1000UL) /*!< TSSS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_ITRCP_Pos (16UL) /*!< ITRCP (Bit 16) */ + #define R_CANFD_CFDGCFG_ITRCP_Msk (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff) */ +/* ======================================================== CFDGCTR ======================================================== */ + #define R_CANFD_CFDGCTR_GMDC_Pos (0UL) /*!< GMDC (Bit 0) */ + #define R_CANFD_CFDGCTR_GMDC_Msk (0x3UL) /*!< GMDC (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDGCTR_GSLPR_Pos (2UL) /*!< GSLPR (Bit 2) */ + #define R_CANFD_CFDGCTR_GSLPR_Msk (0x4UL) /*!< GSLPR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_DEIE_Pos (8UL) /*!< DEIE (Bit 8) */ + #define R_CANFD_CFDGCTR_DEIE_Msk (0x100UL) /*!< DEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_MEIE_Pos (9UL) /*!< MEIE (Bit 9) */ + #define R_CANFD_CFDGCTR_MEIE_Msk (0x200UL) /*!< MEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_THLEIE_Pos (10UL) /*!< THLEIE (Bit 10) */ + #define R_CANFD_CFDGCTR_THLEIE_Msk (0x400UL) /*!< THLEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_CMPOFIE_Pos (11UL) /*!< CMPOFIE (Bit 11) */ + #define R_CANFD_CFDGCTR_CMPOFIE_Msk (0x800UL) /*!< CMPOFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_TSRST_Pos (16UL) /*!< TSRST (Bit 16) */ + #define R_CANFD_CFDGCTR_TSRST_Msk (0x10000UL) /*!< TSRST (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGSTS ======================================================== */ + #define R_CANFD_CFDGSTS_GRSTSTS_Pos (0UL) /*!< GRSTSTS (Bit 0) */ + #define R_CANFD_CFDGSTS_GRSTSTS_Msk (0x1UL) /*!< GRSTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GHLTSTS_Pos (1UL) /*!< GHLTSTS (Bit 1) */ + #define R_CANFD_CFDGSTS_GHLTSTS_Msk (0x2UL) /*!< GHLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GSLPSTS_Pos (2UL) /*!< GSLPSTS (Bit 2) */ + #define R_CANFD_CFDGSTS_GSLPSTS_Msk (0x4UL) /*!< GSLPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GRAMINIT_Pos (3UL) /*!< GRAMINIT (Bit 3) */ + #define R_CANFD_CFDGSTS_GRAMINIT_Msk (0x8UL) /*!< GRAMINIT (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGERFL ======================================================== */ + #define R_CANFD_CFDGERFL_DEF_Pos (0UL) /*!< DEF (Bit 0) */ + #define R_CANFD_CFDGERFL_DEF_Msk (0x1UL) /*!< DEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_MES_Pos (1UL) /*!< MES (Bit 1) */ + #define R_CANFD_CFDGERFL_MES_Msk (0x2UL) /*!< MES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_THLES_Pos (2UL) /*!< THLES (Bit 2) */ + #define R_CANFD_CFDGERFL_THLES_Msk (0x4UL) /*!< THLES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_CMPOF_Pos (3UL) /*!< CMPOF (Bit 3) */ + #define R_CANFD_CFDGERFL_CMPOF_Msk (0x8UL) /*!< CMPOF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_EEF0_Pos (16UL) /*!< EEF0 (Bit 16) */ + #define R_CANFD_CFDGERFL_EEF0_Msk (0x10000UL) /*!< EEF0 (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGTSC ======================================================== */ + #define R_CANFD_CFDGTSC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CANFD_CFDGTSC_TS_Msk (0xffffUL) /*!< TS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CFDGAFLECTR ====================================================== */ + #define R_CANFD_CFDGAFLECTR_AFLPN_Pos (0UL) /*!< AFLPN (Bit 0) */ + #define R_CANFD_CFDGAFLECTR_AFLPN_Msk (0xfUL) /*!< AFLPN (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos (8UL) /*!< AFLDAE (Bit 8) */ + #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk (0x100UL) /*!< AFLDAE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGAFLCFG0 ====================================================== */ + #define R_CANFD_CFDGAFLCFG0_RNC1_Pos (0UL) /*!< RNC1 (Bit 0) */ + #define R_CANFD_CFDGAFLCFG0_RNC1_Msk (0x1ffUL) /*!< RNC1 (Bitfield-Mask: 0x1ff) */ + #define R_CANFD_CFDGAFLCFG0_RNC0_Pos (16UL) /*!< RNC0 (Bit 16) */ + #define R_CANFD_CFDGAFLCFG0_RNC0_Msk (0x1ff0000UL) /*!< RNC0 (Bitfield-Mask: 0x1ff) */ +/* ======================================================== CFDRMNB ======================================================== */ + #define R_CANFD_CFDRMNB_NRXMB_Pos (0UL) /*!< NRXMB (Bit 0) */ + #define R_CANFD_CFDRMNB_NRXMB_Msk (0xffUL) /*!< NRXMB (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRMNB_RMPLS_Pos (8UL) /*!< RMPLS (Bit 8) */ + #define R_CANFD_CFDRMNB_RMPLS_Msk (0x700UL) /*!< RMPLS (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDRMND0 ======================================================== */ + #define R_CANFD_CFDRMND0_RMNSu_Pos (0UL) /*!< RMNSu (Bit 0) */ + #define R_CANFD_CFDRMND0_RMNSu_Msk (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CFDRMIEC ======================================================== */ + #define R_CANFD_CFDRMIEC_RMIE_Pos (0UL) /*!< RMIE (Bit 0) */ + #define R_CANFD_CFDRMIEC_RMIE_Msk (0xffffffffUL) /*!< RMIE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CFDRFCC ======================================================== */ + #define R_CANFD_CFDRFCC_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CANFD_CFDRFCC_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFIE_Pos (1UL) /*!< RFIE (Bit 1) */ + #define R_CANFD_CFDRFCC_RFIE_Msk (0x2UL) /*!< RFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFPLS_Pos (4UL) /*!< RFPLS (Bit 4) */ + #define R_CANFD_CFDRFCC_RFPLS_Msk (0x70UL) /*!< RFPLS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFDC_Pos (8UL) /*!< RFDC (Bit 8) */ + #define R_CANFD_CFDRFCC_RFDC_Msk (0x700UL) /*!< RFDC (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFIM_Pos (12UL) /*!< RFIM (Bit 12) */ + #define R_CANFD_CFDRFCC_RFIM_Msk (0x1000UL) /*!< RFIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFIGCV_Pos (13UL) /*!< RFIGCV (Bit 13) */ + #define R_CANFD_CFDRFCC_RFIGCV_Msk (0xe000UL) /*!< RFIGCV (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDRFSTS ======================================================== */ + #define R_CANFD_CFDRFSTS_RFEMP_Pos (0UL) /*!< RFEMP (Bit 0) */ + #define R_CANFD_CFDRFSTS_RFEMP_Msk (0x1UL) /*!< RFEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFFLL_Pos (1UL) /*!< RFFLL (Bit 1) */ + #define R_CANFD_CFDRFSTS_RFFLL_Msk (0x2UL) /*!< RFFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFMLT_Pos (2UL) /*!< RFMLT (Bit 2) */ + #define R_CANFD_CFDRFSTS_RFMLT_Msk (0x4UL) /*!< RFMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFIF_Pos (3UL) /*!< RFIF (Bit 3) */ + #define R_CANFD_CFDRFSTS_RFIF_Msk (0x8UL) /*!< RFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFMC_Pos (8UL) /*!< RFMC (Bit 8) */ + #define R_CANFD_CFDRFSTS_RFMC_Msk (0xff00UL) /*!< RFMC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDRFPCTR ======================================================= */ + #define R_CANFD_CFDRFPCTR_RFPC_Pos (0UL) /*!< RFPC (Bit 0) */ + #define R_CANFD_CFDRFPCTR_RFPC_Msk (0xffUL) /*!< RFPC (Bitfield-Mask: 0xff) */ +/* ======================================================== CFDCFCC ======================================================== */ + #define R_CANFD_CFDCFCC_CFE_Pos (0UL) /*!< CFE (Bit 0) */ + #define R_CANFD_CFDCFCC_CFE_Msk (0x1UL) /*!< CFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFRXIE_Pos (1UL) /*!< CFRXIE (Bit 1) */ + #define R_CANFD_CFDCFCC_CFRXIE_Msk (0x2UL) /*!< CFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFTXIE_Pos (2UL) /*!< CFTXIE (Bit 2) */ + #define R_CANFD_CFDCFCC_CFTXIE_Msk (0x4UL) /*!< CFTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFPLS_Pos (4UL) /*!< CFPLS (Bit 4) */ + #define R_CANFD_CFDCFCC_CFPLS_Msk (0x70UL) /*!< CFPLS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFM_Pos (8UL) /*!< CFM (Bit 8) */ + #define R_CANFD_CFDCFCC_CFM_Msk (0x300UL) /*!< CFM (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDCFCC_CFITSS_Pos (10UL) /*!< CFITSS (Bit 10) */ + #define R_CANFD_CFDCFCC_CFITSS_Msk (0x400UL) /*!< CFITSS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFITR_Pos (11UL) /*!< CFITR (Bit 11) */ + #define R_CANFD_CFDCFCC_CFITR_Msk (0x800UL) /*!< CFITR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFIM_Pos (12UL) /*!< CFIM (Bit 12) */ + #define R_CANFD_CFDCFCC_CFIM_Msk (0x1000UL) /*!< CFIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFIGCV_Pos (13UL) /*!< CFIGCV (Bit 13) */ + #define R_CANFD_CFDCFCC_CFIGCV_Msk (0xe000UL) /*!< CFIGCV (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFTML_Pos (16UL) /*!< CFTML (Bit 16) */ + #define R_CANFD_CFDCFCC_CFTML_Msk (0x1f0000UL) /*!< CFTML (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDCFCC_CFDC_Pos (21UL) /*!< CFDC (Bit 21) */ + #define R_CANFD_CFDCFCC_CFDC_Msk (0xe00000UL) /*!< CFDC (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFITT_Pos (24UL) /*!< CFITT (Bit 24) */ + #define R_CANFD_CFDCFCC_CFITT_Msk (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCFSTS ======================================================== */ + #define R_CANFD_CFDCFSTS_CFEMP_Pos (0UL) /*!< CFEMP (Bit 0) */ + #define R_CANFD_CFDCFSTS_CFEMP_Msk (0x1UL) /*!< CFEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFFLL_Pos (1UL) /*!< CFFLL (Bit 1) */ + #define R_CANFD_CFDCFSTS_CFFLL_Msk (0x2UL) /*!< CFFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMLT_Pos (2UL) /*!< CFMLT (Bit 2) */ + #define R_CANFD_CFDCFSTS_CFMLT_Msk (0x4UL) /*!< CFMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFRXIF_Pos (3UL) /*!< CFRXIF (Bit 3) */ + #define R_CANFD_CFDCFSTS_CFRXIF_Msk (0x8UL) /*!< CFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFTXIF_Pos (4UL) /*!< CFTXIF (Bit 4) */ + #define R_CANFD_CFDCFSTS_CFTXIF_Msk (0x10UL) /*!< CFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMC_Pos (8UL) /*!< CFMC (Bit 8) */ + #define R_CANFD_CFDCFSTS_CFMC_Msk (0xff00UL) /*!< CFMC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCFPCTR ======================================================= */ + #define R_CANFD_CFDCFPCTR_CFPC_Pos (0UL) /*!< CFPC (Bit 0) */ + #define R_CANFD_CFDCFPCTR_CFPC_Msk (0xffUL) /*!< CFPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDFESTS ======================================================== */ + #define R_CANFD_CFDFESTS_RFXEMP_Pos (0UL) /*!< RFXEMP (Bit 0) */ + #define R_CANFD_CFDFESTS_RFXEMP_Msk (0x3UL) /*!< RFXEMP (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDFESTS_CFXEMP_Pos (8UL) /*!< CFXEMP (Bit 8) */ + #define R_CANFD_CFDFESTS_CFXEMP_Msk (0x100UL) /*!< CFXEMP (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDFFSTS ======================================================== */ + #define R_CANFD_CFDFFSTS_RFXFLL_Pos (0UL) /*!< RFXFLL (Bit 0) */ + #define R_CANFD_CFDFFSTS_RFXFLL_Msk (0x3UL) /*!< RFXFLL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDFFSTS_CFXFLL_Pos (8UL) /*!< CFXFLL (Bit 8) */ + #define R_CANFD_CFDFFSTS_CFXFLL_Msk (0x100UL) /*!< CFXFLL (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDFMSTS ======================================================== */ + #define R_CANFD_CFDFMSTS_RFXMLT_Pos (0UL) /*!< RFXMLT (Bit 0) */ + #define R_CANFD_CFDFMSTS_RFXMLT_Msk (0x3UL) /*!< RFXMLT (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDFMSTS_CFXMLT_Pos (8UL) /*!< CFXMLT (Bit 8) */ + #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x100UL) /*!< CFXMLT (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDRFISTS ======================================================= */ + #define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */ + #define R_CANFD_CFDRFISTS_RFXIF_Msk (0x3UL) /*!< RFXIF (Bitfield-Mask: 0x03) */ +/* ======================================================== CFDTMC ========================================================= */ + #define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */ + #define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMC_TMTAR_Pos (1UL) /*!< TMTAR (Bit 1) */ + #define R_CANFD_CFDTMC_TMTAR_Msk (0x2UL) /*!< TMTAR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMC_TMOM_Pos (2UL) /*!< TMOM (Bit 2) */ + #define R_CANFD_CFDTMC_TMOM_Msk (0x4UL) /*!< TMOM (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTMSTS ======================================================== */ + #define R_CANFD_CFDTMSTS_TMTSTS_Pos (0UL) /*!< TMTSTS (Bit 0) */ + #define R_CANFD_CFDTMSTS_TMTSTS_Msk (0x1UL) /*!< TMTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMSTS_TMTRF_Pos (1UL) /*!< TMTRF (Bit 1) */ + #define R_CANFD_CFDTMSTS_TMTRF_Msk (0x6UL) /*!< TMTRF (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDTMSTS_TMTRM_Pos (3UL) /*!< TMTRM (Bit 3) */ + #define R_CANFD_CFDTMSTS_TMTRM_Msk (0x8UL) /*!< TMTRM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMSTS_TMTARM_Pos (4UL) /*!< TMTARM (Bit 4) */ + #define R_CANFD_CFDTMSTS_TMTARM_Msk (0x10UL) /*!< TMTARM (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTMTRSTS ======================================================= */ + #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Pos (0UL) /*!< CFDTMTRSTSg (Bit 0) */ + #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Msk (0xfUL) /*!< CFDTMTRSTSg (Bitfield-Mask: 0x0f) */ +/* ====================================================== CFDTMTARSTS ====================================================== */ + #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Pos (0UL) /*!< CFDTMTARSTSg (Bit 0) */ + #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Msk (0xfUL) /*!< CFDTMTARSTSg (Bitfield-Mask: 0x0f) */ +/* ====================================================== CFDTMTCSTS ======================================================= */ + #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Pos (0UL) /*!< CFDTMTCSTSg (Bit 0) */ + #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Msk (0xfUL) /*!< CFDTMTCSTSg (Bitfield-Mask: 0x0f) */ +/* ====================================================== CFDTMTASTS ======================================================= */ + #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Pos (0UL) /*!< CFDTMTASTSg (Bit 0) */ + #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Msk (0xfUL) /*!< CFDTMTASTSg (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFDTMIEC ======================================================== */ + #define R_CANFD_CFDTMIEC_TMIEg_Pos (0UL) /*!< TMIEg (Bit 0) */ + #define R_CANFD_CFDTMIEC_TMIEg_Msk (0xfUL) /*!< TMIEg (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFDTXQCC0 ======================================================= */ + #define R_CANFD_CFDTXQCC0_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC0_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC0_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC0_TXQDC_Msk (0x300UL) /*!< TXQDC (Bitfield-Mask: 0x03) */ +/* ====================================================== CFDTXQSTS0 ======================================================= */ + #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS0_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDTXQPCTR0 ====================================================== */ + #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTHLCC ======================================================== */ + #define R_CANFD_CFDTHLCC_THLE_Pos (0UL) /*!< THLE (Bit 0) */ + #define R_CANFD_CFDTHLCC_THLE_Msk (0x1UL) /*!< THLE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLIE_Pos (8UL) /*!< THLIE (Bit 8) */ + #define R_CANFD_CFDTHLCC_THLIE_Msk (0x100UL) /*!< THLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLIM_Pos (9UL) /*!< THLIM (Bit 9) */ + #define R_CANFD_CFDTHLCC_THLIM_Msk (0x200UL) /*!< THLIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLDTE_Pos (10UL) /*!< THLDTE (Bit 10) */ + #define R_CANFD_CFDTHLCC_THLDTE_Msk (0x400UL) /*!< THLDTE (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTHLSTS ======================================================= */ + #define R_CANFD_CFDTHLSTS_THLEMP_Pos (0UL) /*!< THLEMP (Bit 0) */ + #define R_CANFD_CFDTHLSTS_THLEMP_Msk (0x1UL) /*!< THLEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLFLL_Pos (1UL) /*!< THLFLL (Bit 1) */ + #define R_CANFD_CFDTHLSTS_THLFLL_Msk (0x2UL) /*!< THLFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLELT_Pos (2UL) /*!< THLELT (Bit 2) */ + #define R_CANFD_CFDTHLSTS_THLELT_Msk (0x4UL) /*!< THLELT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLIF_Pos (3UL) /*!< THLIF (Bit 3) */ + #define R_CANFD_CFDTHLSTS_THLIF_Msk (0x8UL) /*!< THLIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLMC_Pos (8UL) /*!< THLMC (Bit 8) */ + #define R_CANFD_CFDTHLSTS_THLMC_Msk (0x3f00UL) /*!< THLMC (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDTHLPCTR ======================================================= */ + #define R_CANFD_CFDTHLPCTR_THLPC_Pos (0UL) /*!< THLPC (Bit 0) */ + #define R_CANFD_CFDTHLPCTR_THLPC_Msk (0xffUL) /*!< THLPC (Bitfield-Mask: 0xff) */ +/* ===================================================== CFDGTINTSTS0 ====================================================== */ + #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos (0UL) /*!< TSIF0 (Bit 0) */ + #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk (0x1UL) /*!< TSIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos (1UL) /*!< TAIF0 (Bit 1) */ + #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk (0x2UL) /*!< TAIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos (2UL) /*!< TQIF0 (Bit 2) */ + #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk (0x4UL) /*!< TQIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos (3UL) /*!< CFTIF0 (Bit 3) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk (0x8UL) /*!< CFTIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_THIF0_Pos (4UL) /*!< THIF0 (Bit 4) */ + #define R_CANFD_CFDGTINTSTS0_THIF0_Msk (0x10UL) /*!< THIF0 (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGTSTCFG ======================================================= */ + #define R_CANFD_CFDGTSTCFG_RTMPS_Pos (16UL) /*!< RTMPS (Bit 16) */ + #define R_CANFD_CFDGTSTCFG_RTMPS_Msk (0x3ff0000UL) /*!< RTMPS (Bitfield-Mask: 0x3ff) */ +/* ====================================================== CFDGTSTCTR ======================================================= */ + #define R_CANFD_CFDGTSTCTR_RTME_Pos (2UL) /*!< RTME (Bit 2) */ + #define R_CANFD_CFDGTSTCTR_RTME_Msk (0x4UL) /*!< RTME (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGFDCFG ======================================================= */ + #define R_CANFD_CFDGFDCFG_RPED_Pos (0UL) /*!< RPED (Bit 0) */ + #define R_CANFD_CFDGFDCFG_RPED_Msk (0x1UL) /*!< RPED (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGFDCFG_TSCCFG_Pos (8UL) /*!< TSCCFG (Bit 8) */ + #define R_CANFD_CFDGFDCFG_TSCCFG_Msk (0x300UL) /*!< TSCCFG (Bitfield-Mask: 0x03) */ +/* ======================================================= CFDGLOCKK ======================================================= */ + #define R_CANFD_CFDGLOCKK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ + #define R_CANFD_CFDGLOCKK_LOCK_Msk (0xffffUL) /*!< LOCK (Bitfield-Mask: 0xffff) */ +/* ===================================================== CFDGAFLIGNENT ===================================================== */ + #define R_CANFD_CFDGAFLIGNENT_IRN_Pos (0UL) /*!< IRN (Bit 0) */ + #define R_CANFD_CFDGAFLIGNENT_IRN_Msk (0x1fUL) /*!< IRN (Bitfield-Mask: 0x1f) */ +/* ===================================================== CFDGAFLIGNCTR ===================================================== */ + #define R_CANFD_CFDGAFLIGNCTR_IREN_Pos (0UL) /*!< IREN (Bit 0) */ + #define R_CANFD_CFDGAFLIGNCTR_IREN_Msk (0x1UL) /*!< IREN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFLIGNCTR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CANFD_CFDGAFLIGNCTR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCDTCT ======================================================== */ + #define R_CANFD_CFDCDTCT_RFDMAE0_Pos (0UL) /*!< RFDMAE0 (Bit 0) */ + #define R_CANFD_CFDCDTCT_RFDMAE0_Msk (0x1UL) /*!< RFDMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE1_Pos (1UL) /*!< RFDMAE1 (Bit 1) */ + #define R_CANFD_CFDCDTCT_RFDMAE1_Msk (0x2UL) /*!< RFDMAE1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_CFDMAE0_Pos (8UL) /*!< CFDMAE0 (Bit 8) */ + #define R_CANFD_CFDCDTCT_CFDMAE0_Msk (0x100UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCDTSTS ======================================================= */ + #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos (0UL) /*!< RFDMASTS0 (Bit 0) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk (0x1UL) /*!< RFDMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos (1UL) /*!< RFDMASTS1 (Bit 1) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk (0x2UL) /*!< RFDMASTS1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos (8UL) /*!< CFDMASTS0 (Bit 8) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk (0x100UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGRSTC ======================================================== */ + #define R_CANFD_CFDGRSTC_SRST_Pos (0UL) /*!< SRST (Bit 0) */ + #define R_CANFD_CFDGRSTC_SRST_Msk (0x1UL) /*!< SRST (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGRSTC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CANFD_CFDGRSTC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDRPGACC ======================================================= */ + #define R_CANFD_CFDRPGACC_RDTA_Pos (0UL) /*!< RDTA (Bit 0) */ + #define R_CANFD_CFDRPGACC_RDTA_Msk (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ + #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ + #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ + #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ + #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDIR_BY ======================================================= */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCDOR ========================================================= */ + #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ + #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDOR_HA ======================================================= */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ +/* ======================================================= CRCDOR_BY ======================================================= */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCSAR ========================================================= */ + #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ + #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC_B0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DADR ========================================================== */ + #define R_DAC_B0_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ + #define R_DAC_B0_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DACR0 ========================================================= */ + #define R_DAC_B0_DACR0_DACEN_Pos (0UL) /*!< DACEN (Bit 0) */ + #define R_DAC_B0_DACR0_DACEN_Msk (0x1UL) /*!< DACEN (Bitfield-Mask: 0x01) */ + #define R_DAC_B0_DACR0_DAE_Pos (15UL) /*!< DAE (Bit 15) */ + #define R_DAC_B0_DACR0_DAE_Msk (0x8000UL) /*!< DAE (Bitfield-Mask: 0x01) */ + #define R_DAC_B0_DACR0_DAOUTDIS_Pos (31UL) /*!< DAOUTDIS (Bit 31) */ + #define R_DAC_B0_DACR0_DAOUTDIS_Msk (0x80000000UL) /*!< DAOUTDIS (Bitfield-Mask: 0x01) */ +/* ========================================================= DACR1 ========================================================= */ + #define R_DAC_B0_DACR1_DPSEL_Pos (16UL) /*!< DPSEL (Bit 16) */ + #define R_DAC_B0_DACR1_DPSEL_Msk (0x10000UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= DACR2 ========================================================= */ + #define R_DAC_B0_DACR2_OFSSEL_Pos (8UL) /*!< OFSSEL (Bit 8) */ + #define R_DAC_B0_DACR2_OFSSEL_Msk (0x100UL) /*!< OFSSEL (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DBGSTR ========================================================= */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGSTOPCR ======================================================= */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Pos (14UL) /*!< DBGSTOP_TIM (Bit 14) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Msk (0x4000UL) /*!< DBGSTOP_TIM (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Pos (15UL) /*!< DBGSTOP_SIR (Bit 15) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Msk (0x8000UL) /*!< DBGSTOP_SIR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT1_Pos (2UL) /*!< DBGSTOP_WDT1 (Bit 2) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT1_Msk (0x4UL) /*!< DBGSTOP_WDT1 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_NVMERR_Pos (26UL) /*!< DBGSTOP_NVMERR (Bit 26) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_NVMERR_Msk (0x4000000UL) /*!< DBGSTOP_NVMERR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CTERR0_Pos (28UL) /*!< DBGSTOP_CTERR0 (Bit 28) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CTERR0_Msk (0x10000000UL) /*!< DBGSTOP_CTERR0 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CTERR1_Pos (29UL) /*!< DBGSTOP_CTERR1 (Bit 29) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CTERR1_Msk (0x20000000UL) /*!< DBGSTOP_CTERR1 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGAUTH0 ======================================================== */ + #define R_DEBUG_DBGAUTH0_DBGEN0_Pos (0UL) /*!< DBGEN0 (Bit 0) */ + #define R_DEBUG_DBGAUTH0_DBGEN0_Msk (0x1UL) /*!< DBGEN0 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGAUTH0_DBGEN1_Pos (1UL) /*!< DBGEN1 (Bit 1) */ + #define R_DEBUG_DBGAUTH0_DBGEN1_Msk (0x2UL) /*!< DBGEN1 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGAUTH0_NIDEN0_Pos (4UL) /*!< NIDEN0 (Bit 4) */ + #define R_DEBUG_DBGAUTH0_NIDEN0_Msk (0x10UL) /*!< NIDEN0 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGAUTH0_NIDEN1_Pos (5UL) /*!< NIDEN1 (Bit 5) */ + #define R_DEBUG_DBGAUTH0_NIDEN1_Msk (0x20UL) /*!< NIDEN1 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGAUTH0_DEVICEEN_Pos (16UL) /*!< DEVICEEN (Bit 16) */ + #define R_DEBUG_DBGAUTH0_DEVICEEN_Msk (0x10000UL) /*!< DEVICEEN (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGAUTH0_SWDBG_Pos (31UL) /*!< SWDBG (Bit 31) */ + #define R_DEBUG_DBGAUTH0_SWDBG_Msk (0x80000000UL) /*!< SWDBG (Bitfield-Mask: 0x01) */ +/* ====================================================== CACHEDBGCR ======================================================= */ + #define R_DEBUG_CACHEDBGCR_L1RSTDIS_Pos (0UL) /*!< L1RSTDIS (Bit 0) */ + #define R_DEBUG_CACHEDBGCR_L1RSTDIS_Msk (0x1UL) /*!< L1RSTDIS (Bitfield-Mask: 0x01) */ +/* ======================================================= TRPORTCR ======================================================== */ + #define R_DEBUG_TRPORTCR_OE_Pos (0UL) /*!< OE (Bit 0) */ + #define R_DEBUG_TRPORTCR_OE_Msk (0x1UL) /*!< OE (Bitfield-Mask: 0x01) */ + #define R_DEBUG_TRPORTCR_DRV_Pos (2UL) /*!< DRV (Bit 2) */ + #define R_DEBUG_TRPORTCR_DRV_Msk (0xcUL) /*!< DRV (Bitfield-Mask: 0x03) */ + #define R_DEBUG_TRPORTCR_PORTSEL_Pos (8UL) /*!< PORTSEL (Bit 8) */ + #define R_DEBUG_TRPORTCR_PORTSEL_Msk (0x300UL) /*!< PORTSEL (Bitfield-Mask: 0x03) */ + #define R_DEBUG_TRPORTCR_SWOSEL_Pos (16UL) /*!< SWOSEL (Bit 16) */ + #define R_DEBUG_TRPORTCR_SWOSEL_Msk (0x10000UL) /*!< SWOSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== ALCTRL ========================================================= */ + #define R_DEBUG_ALCTRL_AL_Pos (0UL) /*!< AL (Bit 0) */ + #define R_DEBUG_ALCTRL_AL_Msk (0xffUL) /*!< AL (Bitfield-Mask: 0xff) */ + #define R_DEBUG_ALCTRL_FAILCNT_Pos (30UL) /*!< FAILCNT (Bit 30) */ + #define R_DEBUG_ALCTRL_FAILCNT_Msk (0xc0000000UL) /*!< FAILCNT (Bitfield-Mask: 0x03) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ +/* ======================================================= TRPORTSZ ======================================================== */ + #define R_DEBUG_TRPORTSZ_PORTSIZE_Pos (0UL) /*!< PORTSIZE (Bit 0) */ + #define R_DEBUG_TRPORTSZ_PORTSIZE_Msk (0xffffffffUL) /*!< PORTSIZE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DBGNVMCR ======================================================== */ + #define R_DEBUG_DBGNVMCR_NVMWE_Pos (0UL) /*!< NVMWE (Bit 0) */ + #define R_DEBUG_DBGNVMCR_NVMWE_Msk (0x1UL) /*!< NVMWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMAST ========================================================= */ + #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ + #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ +/* ======================================================== DMECHR ========================================================= */ + #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ + #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ + #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ + #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ + #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ + #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */ +/* ========================================================= DELSR ========================================================= */ + #define R_DMA_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMSAR ========================================================= */ + #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */ + #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMDAR ========================================================= */ + #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */ + #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCRA ========================================================= */ + #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */ + #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */ + #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */ + #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMCRB ========================================================= */ + #define R_DMAC0_DMCRB_DMCRBL_Pos (0UL) /*!< DMCRBL (Bit 0) */ + #define R_DMAC0_DMCRB_DMCRBL_Msk (0xffffUL) /*!< DMCRBL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMCRB_DMCRBH_Pos (16UL) /*!< DMCRBH (Bit 16) */ + #define R_DMAC0_DMCRB_DMCRBH_Msk (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMTMD ========================================================= */ + #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */ + #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */ + #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */ + #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */ + #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */ + #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */ +/* ========================================================= DMINT ========================================================= */ + #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */ + #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */ + #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */ + #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */ + #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */ + #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMAMD ========================================================= */ + #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */ + #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */ + #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */ + #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */ + #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */ + #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */ + #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */ +/* ========================================================= DMOFR ========================================================= */ + #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */ + #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCNT ========================================================= */ + #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */ + #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMREQ ========================================================= */ + #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */ + #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */ + #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSTS ========================================================= */ + #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */ + #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */ + #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSRR ========================================================= */ +/* ========================================================= DMDRR ========================================================= */ +/* ========================================================= DMSBS ========================================================= */ + #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */ + #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */ + #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMDBS ========================================================= */ + #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */ + #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */ + #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMBWR ========================================================= */ + #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */ + #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ +/* ========================================================= DODIR ========================================================= */ + #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ + #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DODSR ========================================================= */ + #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ + #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_DRW ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CONTROL ======================================================== */ + #define R_DRW_CONTROL_SPANSTORE_Pos (23UL) /*!< SPANSTORE (Bit 23) */ + #define R_DRW_CONTROL_SPANSTORE_Msk (0x800000UL) /*!< SPANSTORE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_SPANABORT_Pos (22UL) /*!< SPANABORT (Bit 22) */ + #define R_DRW_CONTROL_SPANABORT_Msk (0x400000UL) /*!< SPANABORT (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNIONCD_Pos (21UL) /*!< UNIONCD (Bit 21) */ + #define R_DRW_CONTROL_UNIONCD_Msk (0x200000UL) /*!< UNIONCD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNIONAB_Pos (20UL) /*!< UNIONAB (Bit 20) */ + #define R_DRW_CONTROL_UNIONAB_Msk (0x100000UL) /*!< UNIONAB (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNION56_Pos (19UL) /*!< UNION56 (Bit 19) */ + #define R_DRW_CONTROL_UNION56_Msk (0x80000UL) /*!< UNION56 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNION34_Pos (18UL) /*!< UNION34 (Bit 18) */ + #define R_DRW_CONTROL_UNION34_Msk (0x40000UL) /*!< UNION34 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNION12_Pos (17UL) /*!< UNION12 (Bit 17) */ + #define R_DRW_CONTROL_UNION12_Msk (0x20000UL) /*!< UNION12 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_BAND2ENABLE_Pos (16UL) /*!< BAND2ENABLE (Bit 16) */ + #define R_DRW_CONTROL_BAND2ENABLE_Msk (0x10000UL) /*!< BAND2ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_BAND1ENABLE_Pos (15UL) /*!< BAND1ENABLE (Bit 15) */ + #define R_DRW_CONTROL_BAND1ENABLE_Msk (0x8000UL) /*!< BAND1ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM6THRESHOLD_Pos (14UL) /*!< LIM6THRESHOLD (Bit 14) */ + #define R_DRW_CONTROL_LIM6THRESHOLD_Msk (0x4000UL) /*!< LIM6THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM5THRESHOLD_Pos (13UL) /*!< LIM5THRESHOLD (Bit 13) */ + #define R_DRW_CONTROL_LIM5THRESHOLD_Msk (0x2000UL) /*!< LIM5THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM4THRESHOLD_Pos (12UL) /*!< LIM4THRESHOLD (Bit 12) */ + #define R_DRW_CONTROL_LIM4THRESHOLD_Msk (0x1000UL) /*!< LIM4THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM3THRESHOLD_Pos (11UL) /*!< LIM3THRESHOLD (Bit 11) */ + #define R_DRW_CONTROL_LIM3THRESHOLD_Msk (0x800UL) /*!< LIM3THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM2THRESHOLD_Pos (10UL) /*!< LIM2THRESHOLD (Bit 10) */ + #define R_DRW_CONTROL_LIM2THRESHOLD_Msk (0x400UL) /*!< LIM2THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM1THRESHOLD_Pos (9UL) /*!< LIM1THRESHOLD (Bit 9) */ + #define R_DRW_CONTROL_LIM1THRESHOLD_Msk (0x200UL) /*!< LIM1THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_QUAD3ENABLE_Pos (8UL) /*!< QUAD3ENABLE (Bit 8) */ + #define R_DRW_CONTROL_QUAD3ENABLE_Msk (0x100UL) /*!< QUAD3ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_QUAD2ENABLE_Pos (7UL) /*!< QUAD2ENABLE (Bit 7) */ + #define R_DRW_CONTROL_QUAD2ENABLE_Msk (0x80UL) /*!< QUAD2ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_QUAD1ENABLE_Pos (6UL) /*!< QUAD1ENABLE (Bit 6) */ + #define R_DRW_CONTROL_QUAD1ENABLE_Msk (0x40UL) /*!< QUAD1ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM6ENABLE_Pos (5UL) /*!< LIM6ENABLE (Bit 5) */ + #define R_DRW_CONTROL_LIM6ENABLE_Msk (0x20UL) /*!< LIM6ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM5ENABLE_Pos (4UL) /*!< LIM5ENABLE (Bit 4) */ + #define R_DRW_CONTROL_LIM5ENABLE_Msk (0x10UL) /*!< LIM5ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM4ENABLE_Pos (3UL) /*!< LIM4ENABLE (Bit 3) */ + #define R_DRW_CONTROL_LIM4ENABLE_Msk (0x8UL) /*!< LIM4ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM3ENABLE_Pos (2UL) /*!< LIM3ENABLE (Bit 2) */ + #define R_DRW_CONTROL_LIM3ENABLE_Msk (0x4UL) /*!< LIM3ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM2ENABLE_Pos (1UL) /*!< LIM2ENABLE (Bit 1) */ + #define R_DRW_CONTROL_LIM2ENABLE_Msk (0x2UL) /*!< LIM2ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM1ENABLE_Pos (0UL) /*!< LIM1ENABLE (Bit 0) */ + #define R_DRW_CONTROL_LIM1ENABLE_Msk (0x1UL) /*!< LIM1ENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================= CONTROL2 ======================================================== */ + #define R_DRW_CONTROL2_RLEPIXELWIDTH_Pos (30UL) /*!< RLEPIXELWIDTH (Bit 30) */ + #define R_DRW_CONTROL2_RLEPIXELWIDTH_Msk (0xc0000000UL) /*!< RLEPIXELWIDTH (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_BDIA_Pos (29UL) /*!< BDIA (Bit 29) */ + #define R_DRW_CONTROL2_BDIA_Msk (0x20000000UL) /*!< BDIA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSIA_Pos (28UL) /*!< BSIA (Bit 28) */ + #define R_DRW_CONTROL2_BSIA_Msk (0x10000000UL) /*!< BSIA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_CLUTFORMAT_Pos (27UL) /*!< CLUTFORMAT (Bit 27) */ + #define R_DRW_CONTROL2_CLUTFORMAT_Msk (0x8000000UL) /*!< CLUTFORMAT (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_COLKEYENABLE_Pos (26UL) /*!< COLKEYENABLE (Bit 26) */ + #define R_DRW_CONTROL2_COLKEYENABLE_Msk (0x4000000UL) /*!< COLKEYENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_CLUTENABLE_Pos (25UL) /*!< CLUTENABLE (Bit 25) */ + #define R_DRW_CONTROL2_CLUTENABLE_Msk (0x2000000UL) /*!< CLUTENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_RLEENABLE_Pos (24UL) /*!< RLEENABLE (Bit 24) */ + #define R_DRW_CONTROL2_RLEENABLE_Msk (0x1000000UL) /*!< RLEENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_WRITEALPHA_Pos (22UL) /*!< WRITEALPHA (Bit 22) */ + #define R_DRW_CONTROL2_WRITEALPHA_Msk (0xc00000UL) /*!< WRITEALPHA (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_WRITEFORMAT10_Pos (20UL) /*!< WRITEFORMAT10 (Bit 20) */ + #define R_DRW_CONTROL2_WRITEFORMAT10_Msk (0x300000UL) /*!< WRITEFORMAT10 (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_READFORMAT10_Pos (18UL) /*!< READFORMAT10 (Bit 18) */ + #define R_DRW_CONTROL2_READFORMAT10_Msk (0xc0000UL) /*!< READFORMAT10 (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_TEXTUREFILTERY_Pos (17UL) /*!< TEXTUREFILTERY (Bit 17) */ + #define R_DRW_CONTROL2_TEXTUREFILTERY_Msk (0x20000UL) /*!< TEXTUREFILTERY (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTUREFILTERX_Pos (16UL) /*!< TEXTUREFILTERX (Bit 16) */ + #define R_DRW_CONTROL2_TEXTUREFILTERX_Msk (0x10000UL) /*!< TEXTUREFILTERX (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTURECLAMPY_Pos (15UL) /*!< TEXTURECLAMPY (Bit 15) */ + #define R_DRW_CONTROL2_TEXTURECLAMPY_Msk (0x8000UL) /*!< TEXTURECLAMPY (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTURECLAMPX_Pos (14UL) /*!< TEXTURECLAMPX (Bit 14) */ + #define R_DRW_CONTROL2_TEXTURECLAMPX_Msk (0x4000UL) /*!< TEXTURECLAMPX (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BC2_Pos (13UL) /*!< BC2 (Bit 13) */ + #define R_DRW_CONTROL2_BC2_Msk (0x2000UL) /*!< BC2 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BDI_Pos (12UL) /*!< BDI (Bit 12) */ + #define R_DRW_CONTROL2_BDI_Msk (0x1000UL) /*!< BDI (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSI_Pos (11UL) /*!< BSI (Bit 11) */ + #define R_DRW_CONTROL2_BSI_Msk (0x800UL) /*!< BSI (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BDF_Pos (10UL) /*!< BDF (Bit 10) */ + #define R_DRW_CONTROL2_BDF_Msk (0x400UL) /*!< BDF (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSF_Pos (9UL) /*!< BSF (Bit 9) */ + #define R_DRW_CONTROL2_BSF_Msk (0x200UL) /*!< BSF (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_WRITEFORMAT2_Pos (8UL) /*!< WRITEFORMAT2 (Bit 8) */ + #define R_DRW_CONTROL2_WRITEFORMAT2_Msk (0x100UL) /*!< WRITEFORMAT2 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BDFA_Pos (7UL) /*!< BDFA (Bit 7) */ + #define R_DRW_CONTROL2_BDFA_Msk (0x80UL) /*!< BDFA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSFA_Pos (6UL) /*!< BSFA (Bit 6) */ + #define R_DRW_CONTROL2_BSFA_Msk (0x40UL) /*!< BSFA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_READFORMAT32_Pos (4UL) /*!< READFORMAT32 (Bit 4) */ + #define R_DRW_CONTROL2_READFORMAT32_Msk (0x30UL) /*!< READFORMAT32 (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_USEACB_Pos (3UL) /*!< USEACB (Bit 3) */ + #define R_DRW_CONTROL2_USEACB_Msk (0x8UL) /*!< USEACB (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_PATTERNSOURCEL5_Pos (2UL) /*!< PATTERNSOURCEL5 (Bit 2) */ + #define R_DRW_CONTROL2_PATTERNSOURCEL5_Msk (0x4UL) /*!< PATTERNSOURCEL5 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTUREENABLE_Pos (1UL) /*!< TEXTUREENABLE (Bit 1) */ + #define R_DRW_CONTROL2_TEXTUREENABLE_Msk (0x2UL) /*!< TEXTUREENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_PATTERNENABLE_Pos (0UL) /*!< PATTERNENABLE (Bit 0) */ + #define R_DRW_CONTROL2_PATTERNENABLE_Msk (0x1UL) /*!< PATTERNENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================== IRQCTL ========================================================= */ + #define R_DRW_IRQCTL_BUSIRQCLR_Pos (5UL) /*!< BUSIRQCLR (Bit 5) */ + #define R_DRW_IRQCTL_BUSIRQCLR_Msk (0x20UL) /*!< BUSIRQCLR (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_BUSIRQEN_Pos (4UL) /*!< BUSIRQEN (Bit 4) */ + #define R_DRW_IRQCTL_BUSIRQEN_Msk (0x10UL) /*!< BUSIRQEN (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_DLISTIRQCLR_Pos (3UL) /*!< DLISTIRQCLR (Bit 3) */ + #define R_DRW_IRQCTL_DLISTIRQCLR_Msk (0x8UL) /*!< DLISTIRQCLR (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_ENUMIRQCLR_Pos (2UL) /*!< ENUMIRQCLR (Bit 2) */ + #define R_DRW_IRQCTL_ENUMIRQCLR_Msk (0x4UL) /*!< ENUMIRQCLR (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_DLISTIRQEN_Pos (1UL) /*!< DLISTIRQEN (Bit 1) */ + #define R_DRW_IRQCTL_DLISTIRQEN_Msk (0x2UL) /*!< DLISTIRQEN (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_ENUMIRQEN_Pos (0UL) /*!< ENUMIRQEN (Bit 0) */ + #define R_DRW_IRQCTL_ENUMIRQEN_Msk (0x1UL) /*!< ENUMIRQEN (Bitfield-Mask: 0x01) */ +/* ======================================================= CACHECTL ======================================================== */ + #define R_DRW_CACHECTL_CFLUSHTX_Pos (3UL) /*!< CFLUSHTX (Bit 3) */ + #define R_DRW_CACHECTL_CFLUSHTX_Msk (0x8UL) /*!< CFLUSHTX (Bitfield-Mask: 0x01) */ + #define R_DRW_CACHECTL_CENABLETX_Pos (2UL) /*!< CENABLETX (Bit 2) */ + #define R_DRW_CACHECTL_CENABLETX_Msk (0x4UL) /*!< CENABLETX (Bitfield-Mask: 0x01) */ + #define R_DRW_CACHECTL_CFLUSHFX_Pos (1UL) /*!< CFLUSHFX (Bit 1) */ + #define R_DRW_CACHECTL_CFLUSHFX_Msk (0x2UL) /*!< CFLUSHFX (Bitfield-Mask: 0x01) */ + #define R_DRW_CACHECTL_CENABLEFX_Pos (0UL) /*!< CENABLEFX (Bit 0) */ + #define R_DRW_CACHECTL_CENABLEFX_Msk (0x1UL) /*!< CENABLEFX (Bitfield-Mask: 0x01) */ +/* ======================================================== STATUS ========================================================= */ + #define R_DRW_STATUS_BUSERRMDL_Pos (10UL) /*!< BUSERRMDL (Bit 10) */ + #define R_DRW_STATUS_BUSERRMDL_Msk (0x400UL) /*!< BUSERRMDL (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSERRMTXMRL_Pos (9UL) /*!< BUSERRMTXMRL (Bit 9) */ + #define R_DRW_STATUS_BUSERRMTXMRL_Msk (0x200UL) /*!< BUSERRMTXMRL (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSERRMFB_Pos (8UL) /*!< BUSERRMFB (Bit 8) */ + #define R_DRW_STATUS_BUSERRMFB_Msk (0x100UL) /*!< BUSERRMFB (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSIRQ_Pos (6UL) /*!< BUSIRQ (Bit 6) */ + #define R_DRW_STATUS_BUSIRQ_Msk (0x40UL) /*!< BUSIRQ (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_DLISTIRQ_Pos (5UL) /*!< DLISTIRQ (Bit 5) */ + #define R_DRW_STATUS_DLISTIRQ_Msk (0x20UL) /*!< DLISTIRQ (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_ENUMIRQ_Pos (4UL) /*!< ENUMIRQ (Bit 4) */ + #define R_DRW_STATUS_ENUMIRQ_Msk (0x10UL) /*!< ENUMIRQ (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_DLISTACTIVE_Pos (3UL) /*!< DLISTACTIVE (Bit 3) */ + #define R_DRW_STATUS_DLISTACTIVE_Msk (0x8UL) /*!< DLISTACTIVE (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_CACHEDIRTY_Pos (2UL) /*!< CACHEDIRTY (Bit 2) */ + #define R_DRW_STATUS_CACHEDIRTY_Msk (0x4UL) /*!< CACHEDIRTY (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSYWRITE_Pos (1UL) /*!< BUSYWRITE (Bit 1) */ + #define R_DRW_STATUS_BUSYWRITE_Msk (0x2UL) /*!< BUSYWRITE (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSYENUM_Pos (0UL) /*!< BUSYENUM (Bit 0) */ + #define R_DRW_STATUS_BUSYENUM_Msk (0x1UL) /*!< BUSYENUM (Bitfield-Mask: 0x01) */ +/* ====================================================== HWREVISION ======================================================= */ + #define R_DRW_HWREVISION_ACBLEND_Pos (27UL) /*!< ACBLEND (Bit 27) */ + #define R_DRW_HWREVISION_ACBLEND_Msk (0x8000000UL) /*!< ACBLEND (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_COLORKEY_Pos (25UL) /*!< COLORKEY (Bit 25) */ + #define R_DRW_HWREVISION_COLORKEY_Msk (0x2000000UL) /*!< COLORKEY (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_TEXCLUT256_Pos (24UL) /*!< TEXCLUT256 (Bit 24) */ + #define R_DRW_HWREVISION_TEXCLUT256_Msk (0x1000000UL) /*!< TEXCLUT256 (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_RLEUNIT_Pos (23UL) /*!< RLEUNIT (Bit 23) */ + #define R_DRW_HWREVISION_RLEUNIT_Msk (0x800000UL) /*!< RLEUNIT (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_TEXCLU_Pos (21UL) /*!< TEXCLU (Bit 21) */ + #define R_DRW_HWREVISION_TEXCLU_Msk (0x200000UL) /*!< TEXCLU (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_PERFCOUNT_Pos (20UL) /*!< PERFCOUNT (Bit 20) */ + #define R_DRW_HWREVISION_PERFCOUNT_Msk (0x100000UL) /*!< PERFCOUNT (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_TXCACHE_Pos (19UL) /*!< TXCACHE (Bit 19) */ + #define R_DRW_HWREVISION_TXCACHE_Msk (0x80000UL) /*!< TXCACHE (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_FBCACHE_Pos (18UL) /*!< FBCACHE (Bit 18) */ + #define R_DRW_HWREVISION_FBCACHE_Msk (0x40000UL) /*!< FBCACHE (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_DLR_Pos (17UL) /*!< DLR (Bit 17) */ + #define R_DRW_HWREVISION_DLR_Msk (0x20000UL) /*!< DLR (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_REV_Pos (0UL) /*!< REV (Bit 0) */ + #define R_DRW_HWREVISION_REV_Msk (0xfffUL) /*!< REV (Bitfield-Mask: 0xfff) */ +/* ======================================================== COLOR1 ========================================================= */ + #define R_DRW_COLOR1_COLOR1A_Pos (24UL) /*!< COLOR1A (Bit 24) */ + #define R_DRW_COLOR1_COLOR1A_Msk (0xff000000UL) /*!< COLOR1A (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR1_COLOR1R_Pos (16UL) /*!< COLOR1R (Bit 16) */ + #define R_DRW_COLOR1_COLOR1R_Msk (0xff0000UL) /*!< COLOR1R (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR1_COLOR1G_Pos (8UL) /*!< COLOR1G (Bit 8) */ + #define R_DRW_COLOR1_COLOR1G_Msk (0xff00UL) /*!< COLOR1G (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR1_COLOR1B_Pos (0UL) /*!< COLOR1B (Bit 0) */ + #define R_DRW_COLOR1_COLOR1B_Msk (0xffUL) /*!< COLOR1B (Bitfield-Mask: 0xff) */ +/* ======================================================== COLOR2 ========================================================= */ + #define R_DRW_COLOR2_COLOR2A_Pos (24UL) /*!< COLOR2A (Bit 24) */ + #define R_DRW_COLOR2_COLOR2A_Msk (0xff000000UL) /*!< COLOR2A (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR2_COLOR2R_Pos (16UL) /*!< COLOR2R (Bit 16) */ + #define R_DRW_COLOR2_COLOR2R_Msk (0xff0000UL) /*!< COLOR2R (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR2_COLOR2G_Pos (8UL) /*!< COLOR2G (Bit 8) */ + #define R_DRW_COLOR2_COLOR2G_Msk (0xff00UL) /*!< COLOR2G (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR2_COLOR2B_Pos (0UL) /*!< COLOR2B (Bit 0) */ + #define R_DRW_COLOR2_COLOR2B_Msk (0xffUL) /*!< COLOR2B (Bitfield-Mask: 0xff) */ +/* ======================================================== PATTERN ======================================================== */ + #define R_DRW_PATTERN_PATTERN_Pos (0UL) /*!< PATTERN (Bit 0) */ + #define R_DRW_PATTERN_PATTERN_Msk (0xffUL) /*!< PATTERN (Bitfield-Mask: 0xff) */ +/* ======================================================== L1START ======================================================== */ + #define R_DRW_L1START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L1START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2START ======================================================== */ + #define R_DRW_L2START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L2START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L3START ======================================================== */ + #define R_DRW_L3START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L3START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L4START ======================================================== */ + #define R_DRW_L4START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L4START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L5START ======================================================== */ + #define R_DRW_L5START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L5START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L6START ======================================================== */ + #define R_DRW_L6START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L6START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L1XADD ========================================================= */ + #define R_DRW_L1XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L1XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2XADD ========================================================= */ + #define R_DRW_L2XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L2XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L3XADD ========================================================= */ + #define R_DRW_L3XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L3XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L4XADD ========================================================= */ + #define R_DRW_L4XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L4XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L5XADD ========================================================= */ + #define R_DRW_L5XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L5XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L6XADD ========================================================= */ + #define R_DRW_L6XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L6XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L1YADD ========================================================= */ + #define R_DRW_L1YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L1YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2YADD ========================================================= */ + #define R_DRW_L2YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L2YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L3YADD ========================================================= */ + #define R_DRW_L3YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L3YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L4YADD ========================================================= */ + #define R_DRW_L4YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L4YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L5YADD ========================================================= */ + #define R_DRW_L5YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L5YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L6YADD ========================================================= */ + #define R_DRW_L6YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L6YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L1BAND ========================================================= */ + #define R_DRW_L1BAND_LBAND_Pos (0UL) /*!< LBAND (Bit 0) */ + #define R_DRW_L1BAND_LBAND_Msk (0xffffffffUL) /*!< LBAND (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2BAND ========================================================= */ + #define R_DRW_L2BAND_LBAND_Pos (0UL) /*!< LBAND (Bit 0) */ + #define R_DRW_L2BAND_LBAND_Msk (0xffffffffUL) /*!< LBAND (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TEXORIGIN ======================================================= */ + #define R_DRW_TEXORIGIN_TEXORIGIN_Pos (0UL) /*!< TEXORIGIN (Bit 0) */ + #define R_DRW_TEXORIGIN_TEXORIGIN_Msk (0xffffffffUL) /*!< TEXORIGIN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TEXPITCH ======================================================== */ + #define R_DRW_TEXPITCH_TEXPITCH_Pos (0UL) /*!< TEXPITCH (Bit 0) */ + #define R_DRW_TEXPITCH_TEXPITCH_Msk (0xffffffffUL) /*!< TEXPITCH (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TEXMASK ======================================================== */ + #define R_DRW_TEXMASK_TEXVMASK_Pos (11UL) /*!< TEXVMASK (Bit 11) */ + #define R_DRW_TEXMASK_TEXVMASK_Msk (0xfffff800UL) /*!< TEXVMASK (Bitfield-Mask: 0x1fffff) */ + #define R_DRW_TEXMASK_TEXUMASK_Pos (0UL) /*!< TEXUMASK (Bit 0) */ + #define R_DRW_TEXMASK_TEXUMASK_Msk (0x7ffUL) /*!< TEXUMASK (Bitfield-Mask: 0x7ff) */ +/* ======================================================== LUSTART ======================================================== */ + #define R_DRW_LUSTART_LUSTART_Pos (0UL) /*!< LUSTART (Bit 0) */ + #define R_DRW_LUSTART_LUSTART_Msk (0xffffffffUL) /*!< LUSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LUXADD ========================================================= */ + #define R_DRW_LUXADD_LUXADD_Pos (0UL) /*!< LUXADD (Bit 0) */ + #define R_DRW_LUXADD_LUXADD_Msk (0xffffffffUL) /*!< LUXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LUYADD ========================================================= */ + #define R_DRW_LUYADD_LUYADD_Pos (0UL) /*!< LUYADD (Bit 0) */ + #define R_DRW_LUYADD_LUYADD_Msk (0xffffffffUL) /*!< LUYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= LVSTARTI ======================================================== */ + #define R_DRW_LVSTARTI_LVSTARTI_Pos (0UL) /*!< LVSTARTI (Bit 0) */ + #define R_DRW_LVSTARTI_LVSTARTI_Msk (0xffffffffUL) /*!< LVSTARTI (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= LVSTARTF ======================================================== */ + #define R_DRW_LVSTARTF_LVSTARTF_Pos (0UL) /*!< LVSTARTF (Bit 0) */ + #define R_DRW_LVSTARTF_LVSTARTF_Msk (0xffffUL) /*!< LVSTARTF (Bitfield-Mask: 0xffff) */ +/* ======================================================== LVXADDI ======================================================== */ + #define R_DRW_LVXADDI_LVXADDI_Pos (0UL) /*!< LVXADDI (Bit 0) */ + #define R_DRW_LVXADDI_LVXADDI_Msk (0xffffffffUL) /*!< LVXADDI (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LVYADDI ======================================================== */ + #define R_DRW_LVYADDI_LVYADDI_Pos (0UL) /*!< LVYADDI (Bit 0) */ + #define R_DRW_LVYADDI_LVYADDI_Msk (0xffffffffUL) /*!< LVYADDI (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= LVYXADDF ======================================================== */ + #define R_DRW_LVYXADDF_LVYADDF_Pos (16UL) /*!< LVYADDF (Bit 16) */ + #define R_DRW_LVYXADDF_LVYADDF_Msk (0xffff0000UL) /*!< LVYADDF (Bitfield-Mask: 0xffff) */ + #define R_DRW_LVYXADDF_LVXADDF_Pos (0UL) /*!< LVXADDF (Bit 0) */ + #define R_DRW_LVYXADDF_LVXADDF_Msk (0xffffUL) /*!< LVXADDF (Bitfield-Mask: 0xffff) */ +/* ======================================================= TEXCLADDR ======================================================= */ + #define R_DRW_TEXCLADDR_CLADDR_Pos (0UL) /*!< CLADDR (Bit 0) */ + #define R_DRW_TEXCLADDR_CLADDR_Msk (0xffUL) /*!< CLADDR (Bitfield-Mask: 0xff) */ +/* ======================================================= TEXCLDATA ======================================================= */ + #define R_DRW_TEXCLDATA_CLDATA_Pos (0UL) /*!< CLDATA (Bit 0) */ + #define R_DRW_TEXCLDATA_CLDATA_Msk (0xffffffffUL) /*!< CLDATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== TEXCLOFFSET ====================================================== */ + #define R_DRW_TEXCLOFFSET_CLOFFSET_Pos (0UL) /*!< CLOFFSET (Bit 0) */ + #define R_DRW_TEXCLOFFSET_CLOFFSET_Msk (0xffUL) /*!< CLOFFSET (Bitfield-Mask: 0xff) */ +/* ======================================================== COLKEY ========================================================= */ + #define R_DRW_COLKEY_COLKEYR_Pos (16UL) /*!< COLKEYR (Bit 16) */ + #define R_DRW_COLKEY_COLKEYR_Msk (0xff0000UL) /*!< COLKEYR (Bitfield-Mask: 0xff) */ + #define R_DRW_COLKEY_COLKEYG_Pos (8UL) /*!< COLKEYG (Bit 8) */ + #define R_DRW_COLKEY_COLKEYG_Msk (0xff00UL) /*!< COLKEYG (Bitfield-Mask: 0xff) */ + #define R_DRW_COLKEY_COLKEYB_Pos (0UL) /*!< COLKEYB (Bit 0) */ + #define R_DRW_COLKEY_COLKEYB_Msk (0xffUL) /*!< COLKEYB (Bitfield-Mask: 0xff) */ +/* ========================================================= SIZE ========================================================== */ + #define R_DRW_SIZE_SIZEY_Pos (16UL) /*!< SIZEY (Bit 16) */ + #define R_DRW_SIZE_SIZEY_Msk (0xffff0000UL) /*!< SIZEY (Bitfield-Mask: 0xffff) */ + #define R_DRW_SIZE_SIZEX_Pos (0UL) /*!< SIZEX (Bit 0) */ + #define R_DRW_SIZE_SIZEX_Msk (0xffffUL) /*!< SIZEX (Bitfield-Mask: 0xffff) */ +/* ========================================================= PITCH ========================================================= */ + #define R_DRW_PITCH_SSD_Pos (16UL) /*!< SSD (Bit 16) */ + #define R_DRW_PITCH_SSD_Msk (0xffff0000UL) /*!< SSD (Bitfield-Mask: 0xffff) */ + #define R_DRW_PITCH_PITCH_Pos (0UL) /*!< PITCH (Bit 0) */ + #define R_DRW_PITCH_PITCH_Msk (0xffffUL) /*!< PITCH (Bitfield-Mask: 0xffff) */ +/* ======================================================== ORIGIN ========================================================= */ + #define R_DRW_ORIGIN_ORIGIN_Pos (0UL) /*!< ORIGIN (Bit 0) */ + #define R_DRW_ORIGIN_ORIGIN_Msk (0xffffffffUL) /*!< ORIGIN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== DLISTSTART ======================================================= */ + #define R_DRW_DLISTSTART_DLISTSTART_Pos (0UL) /*!< DLISTSTART (Bit 0) */ + #define R_DRW_DLISTSTART_DLISTSTART_Msk (0xffffffffUL) /*!< DLISTSTART (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PERFTRIGGER ====================================================== */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER2_Pos (16UL) /*!< PERFTRIGGER2 (Bit 16) */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER2_Msk (0xffff0000UL) /*!< PERFTRIGGER2 (Bitfield-Mask: 0xffff) */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER1_Pos (0UL) /*!< PERFTRIGGER1 (Bit 0) */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER1_Msk (0xffffUL) /*!< PERFTRIGGER1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== PERFCOUNT1 ======================================================= */ + #define R_DRW_PERFCOUNT1_PERFCOUNT_Pos (0UL) /*!< PERFCOUNT (Bit 0) */ + #define R_DRW_PERFCOUNT1_PERFCOUNT_Msk (0xffffffffUL) /*!< PERFCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PERFCOUNT2 ======================================================= */ + #define R_DRW_PERFCOUNT2_PERFCOUNT_Pos (0UL) /*!< PERFCOUNT (Bit 0) */ + #define R_DRW_PERFCOUNT2_PERFCOUNT_Msk (0xffffffffUL) /*!< PERFCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DBWER ========================================================= */ + #define R_DRW_DBWER_BWE_Pos (2UL) /*!< BWE (Bit 2) */ + #define R_DRW_DBWER_BWE_Msk (0x4UL) /*!< BWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DTCCR ========================================================= */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCVBR ========================================================= */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ +/* ========================================================= DTCST ========================================================= */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSTS ========================================================= */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ +/* ======================================================= DTCCR_SEC ======================================================= */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTEVR ========================================================= */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELCR ========================================================== */ + #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ + #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARA ======================================================== */ + #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR_Pos (1UL) /*!< ELSEGR (Bit 1) */ + #define R_ELC_ELCSARA_ELSEGR_Msk (0x2UL) /*!< ELSEGR (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARB ======================================================== */ + #define R_ELC_ELCSARB_ELSR_Pos (0UL) /*!< ELSR (Bit 0) */ + #define R_ELC_ELCSARB_ELSR_Msk (0x1UL) /*!< ELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARC ======================================================== */ + #define R_ELC_ELCSARC_ELSR_Pos (0UL) /*!< ELSR (Bit 0) */ + #define R_ELC_ELCSARC_ELSR_Msk (0x1UL) /*!< ELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCPARA ======================================================== */ + #define R_ELC_ELCPARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCPARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCPARA_ELSEGR_Pos (1UL) /*!< ELSEGR (Bit 1) */ + #define R_ELC_ELCPARA_ELSEGR_Msk (0x2UL) /*!< ELSEGR (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCPARB ======================================================== */ + #define R_ELC_ELCPARB_ELSR_Pos (0UL) /*!< ELSR (Bit 0) */ + #define R_ELC_ELCPARB_ELSR_Msk (0x1UL) /*!< ELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCPARC ======================================================== */ + #define R_ELC_ELCPARC_ELSR_Pos (0UL) /*!< ELSR (Bit 0) */ + #define R_ELC_ELCPARC_ELSR_Msk (0x1UL) /*!< ELSR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EDMAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= EDMR ========================================================== */ + #define R_ETHERC_EDMAC_EDMR_DE_Pos (6UL) /*!< DE (Bit 6) */ + #define R_ETHERC_EDMAC_EDMR_DE_Msk (0x40UL) /*!< DE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EDMR_DL_Pos (4UL) /*!< DL (Bit 4) */ + #define R_ETHERC_EDMAC_EDMR_DL_Msk (0x30UL) /*!< DL (Bitfield-Mask: 0x03) */ + #define R_ETHERC_EDMAC_EDMR_SWR_Pos (0UL) /*!< SWR (Bit 0) */ + #define R_ETHERC_EDMAC_EDMR_SWR_Msk (0x1UL) /*!< SWR (Bitfield-Mask: 0x01) */ +/* ========================================================= EDTRR ========================================================= */ + #define R_ETHERC_EDMAC_EDTRR_TR_Pos (0UL) /*!< TR (Bit 0) */ + #define R_ETHERC_EDMAC_EDTRR_TR_Msk (0x1UL) /*!< TR (Bitfield-Mask: 0x01) */ +/* ========================================================= EDRRR ========================================================= */ + #define R_ETHERC_EDMAC_EDRRR_RR_Pos (0UL) /*!< RR (Bit 0) */ + #define R_ETHERC_EDMAC_EDRRR_RR_Msk (0x1UL) /*!< RR (Bitfield-Mask: 0x01) */ +/* ========================================================= TDLAR ========================================================= */ + #define R_ETHERC_EDMAC_TDLAR_TDLAR_Pos (0UL) /*!< TDLAR (Bit 0) */ + #define R_ETHERC_EDMAC_TDLAR_TDLAR_Msk (0xffffffffUL) /*!< TDLAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RDLAR ========================================================= */ + #define R_ETHERC_EDMAC_RDLAR_RDLAR_Pos (0UL) /*!< RDLAR (Bit 0) */ + #define R_ETHERC_EDMAC_RDLAR_RDLAR_Msk (0xffffffffUL) /*!< RDLAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= EESR ========================================================== */ + #define R_ETHERC_EDMAC_EESR_TWB_Pos (30UL) /*!< TWB (Bit 30) */ + #define R_ETHERC_EDMAC_EESR_TWB_Msk (0x40000000UL) /*!< TWB (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TABT_Pos (26UL) /*!< TABT (Bit 26) */ + #define R_ETHERC_EDMAC_EESR_TABT_Msk (0x4000000UL) /*!< TABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RABT_Pos (25UL) /*!< RABT (Bit 25) */ + #define R_ETHERC_EDMAC_EESR_RABT_Msk (0x2000000UL) /*!< RABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RFCOF_Pos (24UL) /*!< RFCOF (Bit 24) */ + #define R_ETHERC_EDMAC_EESR_RFCOF_Msk (0x1000000UL) /*!< RFCOF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_ADE_Pos (23UL) /*!< ADE (Bit 23) */ + #define R_ETHERC_EDMAC_EESR_ADE_Msk (0x800000UL) /*!< ADE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_ECI_Pos (22UL) /*!< ECI (Bit 22) */ + #define R_ETHERC_EDMAC_EESR_ECI_Msk (0x400000UL) /*!< ECI (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TC_Pos (21UL) /*!< TC (Bit 21) */ + #define R_ETHERC_EDMAC_EESR_TC_Msk (0x200000UL) /*!< TC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TDE_Pos (20UL) /*!< TDE (Bit 20) */ + #define R_ETHERC_EDMAC_EESR_TDE_Msk (0x100000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TFUF_Pos (19UL) /*!< TFUF (Bit 19) */ + #define R_ETHERC_EDMAC_EESR_TFUF_Msk (0x80000UL) /*!< TFUF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_FR_Pos (18UL) /*!< FR (Bit 18) */ + #define R_ETHERC_EDMAC_EESR_FR_Msk (0x40000UL) /*!< FR (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RDE_Pos (17UL) /*!< RDE (Bit 17) */ + #define R_ETHERC_EDMAC_EESR_RDE_Msk (0x20000UL) /*!< RDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RFOF_Pos (16UL) /*!< RFOF (Bit 16) */ + #define R_ETHERC_EDMAC_EESR_RFOF_Msk (0x10000UL) /*!< RFOF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CND_Pos (11UL) /*!< CND (Bit 11) */ + #define R_ETHERC_EDMAC_EESR_CND_Msk (0x800UL) /*!< CND (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_DLC_Pos (10UL) /*!< DLC (Bit 10) */ + #define R_ETHERC_EDMAC_EESR_DLC_Msk (0x400UL) /*!< DLC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CD_Pos (9UL) /*!< CD (Bit 9) */ + #define R_ETHERC_EDMAC_EESR_CD_Msk (0x200UL) /*!< CD (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TRO_Pos (8UL) /*!< TRO (Bit 8) */ + #define R_ETHERC_EDMAC_EESR_TRO_Msk (0x100UL) /*!< TRO (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RMAF_Pos (7UL) /*!< RMAF (Bit 7) */ + #define R_ETHERC_EDMAC_EESR_RMAF_Msk (0x80UL) /*!< RMAF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RRF_Pos (4UL) /*!< RRF (Bit 4) */ + #define R_ETHERC_EDMAC_EESR_RRF_Msk (0x10UL) /*!< RRF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RTLF_Pos (3UL) /*!< RTLF (Bit 3) */ + #define R_ETHERC_EDMAC_EESR_RTLF_Msk (0x8UL) /*!< RTLF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RTSF_Pos (2UL) /*!< RTSF (Bit 2) */ + #define R_ETHERC_EDMAC_EESR_RTSF_Msk (0x4UL) /*!< RTSF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_PRE_Pos (1UL) /*!< PRE (Bit 1) */ + #define R_ETHERC_EDMAC_EESR_PRE_Msk (0x2UL) /*!< PRE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CERF_Pos (0UL) /*!< CERF (Bit 0) */ + #define R_ETHERC_EDMAC_EESR_CERF_Msk (0x1UL) /*!< CERF (Bitfield-Mask: 0x01) */ +/* ======================================================== EESIPR ========================================================= */ + #define R_ETHERC_EDMAC_EESIPR_TWBIP_Pos (30UL) /*!< TWBIP (Bit 30) */ + #define R_ETHERC_EDMAC_EESIPR_TWBIP_Msk (0x40000000UL) /*!< TWBIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TABTIP_Pos (26UL) /*!< TABTIP (Bit 26) */ + #define R_ETHERC_EDMAC_EESIPR_TABTIP_Msk (0x4000000UL) /*!< TABTIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RABTIP_Pos (25UL) /*!< RABTIP (Bit 25) */ + #define R_ETHERC_EDMAC_EESIPR_RABTIP_Msk (0x2000000UL) /*!< RABTIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Pos (24UL) /*!< RFCOFIP (Bit 24) */ + #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Msk (0x1000000UL) /*!< RFCOFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_ADEIP_Pos (23UL) /*!< ADEIP (Bit 23) */ + #define R_ETHERC_EDMAC_EESIPR_ADEIP_Msk (0x800000UL) /*!< ADEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_ECIIP_Pos (22UL) /*!< ECIIP (Bit 22) */ + #define R_ETHERC_EDMAC_EESIPR_ECIIP_Msk (0x400000UL) /*!< ECIIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TCIP_Pos (21UL) /*!< TCIP (Bit 21) */ + #define R_ETHERC_EDMAC_EESIPR_TCIP_Msk (0x200000UL) /*!< TCIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TDEIP_Pos (20UL) /*!< TDEIP (Bit 20) */ + #define R_ETHERC_EDMAC_EESIPR_TDEIP_Msk (0x100000UL) /*!< TDEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Pos (19UL) /*!< TFUFIP (Bit 19) */ + #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Msk (0x80000UL) /*!< TFUFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_FRIP_Pos (18UL) /*!< FRIP (Bit 18) */ + #define R_ETHERC_EDMAC_EESIPR_FRIP_Msk (0x40000UL) /*!< FRIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RDEIP_Pos (17UL) /*!< RDEIP (Bit 17) */ + #define R_ETHERC_EDMAC_EESIPR_RDEIP_Msk (0x20000UL) /*!< RDEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Pos (16UL) /*!< RFOFIP (Bit 16) */ + #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Msk (0x10000UL) /*!< RFOFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CNDIP_Pos (11UL) /*!< CNDIP (Bit 11) */ + #define R_ETHERC_EDMAC_EESIPR_CNDIP_Msk (0x800UL) /*!< CNDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_DLCIP_Pos (10UL) /*!< DLCIP (Bit 10) */ + #define R_ETHERC_EDMAC_EESIPR_DLCIP_Msk (0x400UL) /*!< DLCIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CDIP_Pos (9UL) /*!< CDIP (Bit 9) */ + #define R_ETHERC_EDMAC_EESIPR_CDIP_Msk (0x200UL) /*!< CDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TROIP_Pos (8UL) /*!< TROIP (Bit 8) */ + #define R_ETHERC_EDMAC_EESIPR_TROIP_Msk (0x100UL) /*!< TROIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Pos (7UL) /*!< RMAFIP (Bit 7) */ + #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Msk (0x80UL) /*!< RMAFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RRFIP_Pos (4UL) /*!< RRFIP (Bit 4) */ + #define R_ETHERC_EDMAC_EESIPR_RRFIP_Msk (0x10UL) /*!< RRFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Pos (3UL) /*!< RTLFIP (Bit 3) */ + #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Msk (0x8UL) /*!< RTLFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Pos (2UL) /*!< RTSFIP (Bit 2) */ + #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Msk (0x4UL) /*!< RTSFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_PREIP_Pos (1UL) /*!< PREIP (Bit 1) */ + #define R_ETHERC_EDMAC_EESIPR_PREIP_Msk (0x2UL) /*!< PREIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CERFIP_Pos (0UL) /*!< CERFIP (Bit 0) */ + #define R_ETHERC_EDMAC_EESIPR_CERFIP_Msk (0x1UL) /*!< CERFIP (Bitfield-Mask: 0x01) */ +/* ======================================================== TRSCER ========================================================= */ + #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Pos (7UL) /*!< RMAFCE (Bit 7) */ + #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Msk (0x80UL) /*!< RMAFCE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_TRSCER_RRFCE_Pos (4UL) /*!< RRFCE (Bit 4) */ + #define R_ETHERC_EDMAC_TRSCER_RRFCE_Msk (0x10UL) /*!< RRFCE (Bitfield-Mask: 0x01) */ +/* ========================================================= RMFCR ========================================================= */ + #define R_ETHERC_EDMAC_RMFCR_MFC_Pos (0UL) /*!< MFC (Bit 0) */ + #define R_ETHERC_EDMAC_RMFCR_MFC_Msk (0xffffUL) /*!< MFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= TFTR ========================================================== */ + #define R_ETHERC_EDMAC_TFTR_TFT_Pos (0UL) /*!< TFT (Bit 0) */ + #define R_ETHERC_EDMAC_TFTR_TFT_Msk (0x7ffUL) /*!< TFT (Bitfield-Mask: 0x7ff) */ +/* ========================================================== FDR ========================================================== */ + #define R_ETHERC_EDMAC_FDR_TFD_Pos (8UL) /*!< TFD (Bit 8) */ + #define R_ETHERC_EDMAC_FDR_TFD_Msk (0x1f00UL) /*!< TFD (Bitfield-Mask: 0x1f) */ + #define R_ETHERC_EDMAC_FDR_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHERC_EDMAC_FDR_RFD_Msk (0x1fUL) /*!< RFD (Bitfield-Mask: 0x1f) */ +/* ========================================================= RMCR ========================================================== */ + #define R_ETHERC_EDMAC_RMCR_RNR_Pos (0UL) /*!< RNR (Bit 0) */ + #define R_ETHERC_EDMAC_RMCR_RNR_Msk (0x1UL) /*!< RNR (Bitfield-Mask: 0x01) */ +/* ========================================================= TFUCR ========================================================= */ + #define R_ETHERC_EDMAC_TFUCR_UNDER_Pos (0UL) /*!< UNDER (Bit 0) */ + #define R_ETHERC_EDMAC_TFUCR_UNDER_Msk (0xffffUL) /*!< UNDER (Bitfield-Mask: 0xffff) */ +/* ========================================================= RFOCR ========================================================= */ + #define R_ETHERC_EDMAC_RFOCR_OVER_Pos (0UL) /*!< OVER (Bit 0) */ + #define R_ETHERC_EDMAC_RFOCR_OVER_Msk (0xffffUL) /*!< OVER (Bitfield-Mask: 0xffff) */ +/* ========================================================= IOSR ========================================================== */ + #define R_ETHERC_EDMAC_IOSR_ELB_Pos (0UL) /*!< ELB (Bit 0) */ + #define R_ETHERC_EDMAC_IOSR_ELB_Msk (0x1UL) /*!< ELB (Bitfield-Mask: 0x01) */ +/* ========================================================= FCFTR ========================================================= */ + #define R_ETHERC_EDMAC_FCFTR_RFFO_Pos (16UL) /*!< RFFO (Bit 16) */ + #define R_ETHERC_EDMAC_FCFTR_RFFO_Msk (0x70000UL) /*!< RFFO (Bitfield-Mask: 0x07) */ + #define R_ETHERC_EDMAC_FCFTR_RFDO_Pos (0UL) /*!< RFDO (Bit 0) */ + #define R_ETHERC_EDMAC_FCFTR_RFDO_Msk (0x7UL) /*!< RFDO (Bitfield-Mask: 0x07) */ +/* ======================================================== RPADIR ========================================================= */ + #define R_ETHERC_EDMAC_RPADIR_PADS_Pos (16UL) /*!< PADS (Bit 16) */ + #define R_ETHERC_EDMAC_RPADIR_PADS_Msk (0x30000UL) /*!< PADS (Bitfield-Mask: 0x03) */ + #define R_ETHERC_EDMAC_RPADIR_PADR_Pos (0UL) /*!< PADR (Bit 0) */ + #define R_ETHERC_EDMAC_RPADIR_PADR_Msk (0x3fUL) /*!< PADR (Bitfield-Mask: 0x3f) */ +/* ========================================================= TRIMD ========================================================= */ + #define R_ETHERC_EDMAC_TRIMD_TIM_Pos (4UL) /*!< TIM (Bit 4) */ + #define R_ETHERC_EDMAC_TRIMD_TIM_Msk (0x10UL) /*!< TIM (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_TRIMD_TIS_Pos (0UL) /*!< TIS (Bit 0) */ + #define R_ETHERC_EDMAC_TRIMD_TIS_Msk (0x1UL) /*!< TIS (Bitfield-Mask: 0x01) */ +/* ========================================================= RBWAR ========================================================= */ + #define R_ETHERC_EDMAC_RBWAR_RBWAR_Pos (0UL) /*!< RBWAR (Bit 0) */ + #define R_ETHERC_EDMAC_RBWAR_RBWAR_Msk (0xffffffffUL) /*!< RBWAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RDFAR ========================================================= */ + #define R_ETHERC_EDMAC_RDFAR_RDFAR_Pos (0UL) /*!< RDFAR (Bit 0) */ + #define R_ETHERC_EDMAC_RDFAR_RDFAR_Msk (0xffffffffUL) /*!< RDFAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TBRAR ========================================================= */ + #define R_ETHERC_EDMAC_TBRAR_TBRAR_Pos (0UL) /*!< TBRAR (Bit 0) */ + #define R_ETHERC_EDMAC_TBRAR_TBRAR_Msk (0xffffffffUL) /*!< TBRAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TDFAR ========================================================= */ + #define R_ETHERC_EDMAC_TDFAR_TDFAR_Pos (0UL) /*!< TDFAR (Bit 0) */ + #define R_ETHERC_EDMAC_TDFAR_TDFAR_Msk (0xffffffffUL) /*!< TDFAR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_GLCDC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= GR1_CLUT0 ======================================================= */ + #define R_GLCDC_GR1_CLUT0_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR1_CLUT0_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT0_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR1_CLUT0_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT0_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR1_CLUT0_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT0_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR1_CLUT0_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ======================================================= GR1_CLUT1 ======================================================= */ + #define R_GLCDC_GR1_CLUT1_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR1_CLUT1_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT1_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR1_CLUT1_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT1_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR1_CLUT1_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT1_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR1_CLUT1_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ======================================================= GR2_CLUT0 ======================================================= */ + #define R_GLCDC_GR2_CLUT0_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR2_CLUT0_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT0_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR2_CLUT0_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT0_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR2_CLUT0_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT0_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR2_CLUT0_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ======================================================= GR2_CLUT1 ======================================================= */ + #define R_GLCDC_GR2_CLUT1_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR2_CLUT1_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT1_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR2_CLUT1_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT1_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR2_CLUT1_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT1_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR2_CLUT1_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ + #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ + #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ + #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ + #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ + #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ + #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ + #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ + #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ + #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ + #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ + #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ + #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ + #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ + #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ + #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ + #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ + #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ + #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ + #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ + #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ + #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ + #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ + #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ + #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ + #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ + #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ + #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ + #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ + #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ + #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ + #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ + #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ + #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ + #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ + #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ + #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ + #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ + #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ + #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ + #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ + #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ + #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ + #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ + #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ + #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ + #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ + #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ + #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ + #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ + #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ + #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ + #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ + #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ + #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ + #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ + #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ + #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ + #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ + #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ + #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ + #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ + #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ + #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ + #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ + #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ + #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ + #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ + #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ + #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ + #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ + #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ + #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ + #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ + #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ + #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ + #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ + #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ + #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ + #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ + #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ + #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ + #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ + #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ + #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT0_GTCR_CKEG_Pos (27UL) /*!< CKEG (Bit 27) */ + #define R_GPT0_GTCR_CKEG_Msk (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ + #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT0_GTCR_MD_Msk (0xf0000UL) /*!< MD (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_SSCEN_Pos (15UL) /*!< SSCEN (Bit 15) */ + #define R_GPT0_GTCR_SSCEN_Msk (0x8000UL) /*!< SSCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_CPSCD_Pos (12UL) /*!< CPSCD (Bit 12) */ + #define R_GPT0_GTCR_CPSCD_Msk (0x1000UL) /*!< CPSCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_SSCGRP_Pos (10UL) /*!< SSCGRP (Bit 10) */ + #define R_GPT0_GTCR_SSCGRP_Msk (0xc00UL) /*!< SSCGRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTCR_SCGTIOC_Pos (9UL) /*!< SCGTIOC (Bit 9) */ + #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ + #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ + #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ + #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ + #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ + #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ + #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_ADTRDEN_Pos (17UL) /*!< ADTRDEN (Bit 17) */ + #define R_GPT0_GTINTAD_ADTRDEN_Msk (0x20000UL) /*!< ADTRDEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_ADTRUEN_Pos (16UL) /*!< ADTRUEN (Bit 16) */ + #define R_GPT0_GTINTAD_ADTRUEN_Msk (0x10000UL) /*!< ADTRUEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCFPU_Pos (15UL) /*!< SCFPU (Bit 15) */ + #define R_GPT0_GTINTAD_SCFPU_Msk (0x8000UL) /*!< SCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCFPO_Pos (14UL) /*!< SCFPO (Bit 14) */ + #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ + #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ + #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ + #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ + #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ + #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ + #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ + #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ + #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ + #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_DBRTEC_Pos (8UL) /*!< DBRTEC (Bit 8) */ + #define R_GPT0_GTBER_DBRTEC_Msk (0x100UL) /*!< DBRTEC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ + #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ + #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTCCR ========================================================= */ + #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ + #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPR ========================================================== */ + #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ + #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPBR ========================================================= */ + #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ + #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTPDBR ========================================================= */ + #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ + #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRA ======================================================== */ + #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ + #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRB ======================================================== */ + #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ + #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRA ======================================================== */ + #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ + #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRB ======================================================== */ + #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ + #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRA ======================================================= */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRB ======================================================= */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ + #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDVD ========================================================= */ + #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ + #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBU ========================================================= */ + #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBD ========================================================= */ + #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ + #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTADSMR ======================================================== */ + #define R_GPT0_GTADSMR_ADSMS0_Pos (0UL) /*!< ADSMS0 (Bit 0) */ + #define R_GPT0_GTADSMR_ADSMS0_Msk (0x3UL) /*!< ADSMS0 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTADSMR_ADSMEN0_Pos (8UL) /*!< ADSMEN0 (Bit 8) */ + #define R_GPT0_GTADSMR_ADSMEN0_Msk (0x100UL) /*!< ADSMEN0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTADSMR_ADSMS1_Pos (16UL) /*!< ADSMS1 (Bit 16) */ + #define R_GPT0_GTADSMR_ADSMS1_Msk (0x30000UL) /*!< ADSMS1 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTADSMR_ADSMEN1_Pos (24UL) /*!< ADSMEN1 (Bit 24) */ + #define R_GPT0_GTADSMR_ADSMEN1_Msk (0x1000000UL) /*!< ADSMEN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTEITC ========================================================= */ + #define R_GPT0_GTEITC_EIVTC1_Pos (0UL) /*!< EIVTC1 (Bit 0) */ + #define R_GPT0_GTEITC_EIVTC1_Msk (0x3UL) /*!< EIVTC1 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTEITC_EIVTT1_Pos (4UL) /*!< EIVTT1 (Bit 4) */ + #define R_GPT0_GTEITC_EIVTT1_Msk (0xf0UL) /*!< EIVTT1 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT1_Pos (12UL) /*!< EITCNT1 (Bit 12) */ + #define R_GPT0_GTEITC_EITCNT1_Msk (0xf000UL) /*!< EITCNT1 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EIVTC2_Pos (16UL) /*!< EIVTC2 (Bit 16) */ + #define R_GPT0_GTEITC_EIVTC2_Msk (0x30000UL) /*!< EIVTC2 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTEITC_EIVTT2_Pos (20UL) /*!< EIVTT2 (Bit 20) */ + #define R_GPT0_GTEITC_EIVTT2_Msk (0xf00000UL) /*!< EIVTT2 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT2IV_Pos (24UL) /*!< EITCNT2IV (Bit 24) */ + #define R_GPT0_GTEITC_EITCNT2IV_Msk (0xf000000UL) /*!< EITCNT2IV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT2_Pos (28UL) /*!< EITCNT2 (Bit 28) */ + #define R_GPT0_GTEITC_EITCNT2_Msk (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f) */ +/* ======================================================= GTEITLI1 ======================================================== */ + #define R_GPT0_GTEITLI1_EITLA_Pos (0UL) /*!< EITLA (Bit 0) */ + #define R_GPT0_GTEITLI1_EITLA_Msk (0x7UL) /*!< EITLA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLB_Pos (4UL) /*!< EITLB (Bit 4) */ + #define R_GPT0_GTEITLI1_EITLB_Msk (0x70UL) /*!< EITLB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLC_Pos (8UL) /*!< EITLC (Bit 8) */ + #define R_GPT0_GTEITLI1_EITLC_Msk (0x700UL) /*!< EITLC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLD_Pos (12UL) /*!< EITLD (Bit 12) */ + #define R_GPT0_GTEITLI1_EITLD_Msk (0x7000UL) /*!< EITLD (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLE_Pos (16UL) /*!< EITLE (Bit 16) */ + #define R_GPT0_GTEITLI1_EITLE_Msk (0x70000UL) /*!< EITLE (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLF_Pos (20UL) /*!< EITLF (Bit 20) */ + #define R_GPT0_GTEITLI1_EITLF_Msk (0x700000UL) /*!< EITLF (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLV_Pos (24UL) /*!< EITLV (Bit 24) */ + #define R_GPT0_GTEITLI1_EITLV_Msk (0x7000000UL) /*!< EITLV (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLU_Pos (28UL) /*!< EITLU (Bit 28) */ + #define R_GPT0_GTEITLI1_EITLU_Msk (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07) */ +/* ======================================================= GTEITLI2 ======================================================== */ + #define R_GPT0_GTEITLI2_EADTAL_Pos (0UL) /*!< EADTAL (Bit 0) */ + #define R_GPT0_GTEITLI2_EADTAL_Msk (0x7UL) /*!< EADTAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI2_EADTBL_Pos (4UL) /*!< EADTBL (Bit 4) */ + #define R_GPT0_GTEITLI2_EADTBL_Msk (0x70UL) /*!< EADTBL (Bitfield-Mask: 0x07) */ +/* ======================================================== GTEITLB ======================================================== */ + #define R_GPT0_GTEITLB_EBTLCA_Pos (0UL) /*!< EBTLCA (Bit 0) */ + #define R_GPT0_GTEITLB_EBTLCA_Msk (0x7UL) /*!< EBTLCA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLCB_Pos (4UL) /*!< EBTLCB (Bit 4) */ + #define R_GPT0_GTEITLB_EBTLCB_Msk (0x70UL) /*!< EBTLCB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLPR_Pos (8UL) /*!< EBTLPR (Bit 8) */ + #define R_GPT0_GTEITLB_EBTLPR_Msk (0x700UL) /*!< EBTLPR (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLADA_Pos (16UL) /*!< EBTLADA (Bit 16) */ + #define R_GPT0_GTEITLB_EBTLADA_Msk (0x70000UL) /*!< EBTLADA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLADB_Pos (20UL) /*!< EBTLADB (Bit 20) */ + #define R_GPT0_GTEITLB_EBTLADB_Msk (0x700000UL) /*!< EBTLADB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLDVU_Pos (24UL) /*!< EBTLDVU (Bit 24) */ + #define R_GPT0_GTEITLB_EBTLDVU_Msk (0x7000000UL) /*!< EBTLDVU (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLDVD_Pos (28UL) /*!< EBTLDVD (Bit 28) */ + #define R_GPT0_GTEITLB_EBTLDVD_Msk (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07) */ +/* ======================================================== GTICLF ========================================================= */ + #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ + #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ + #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ + #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ + #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ + #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ +/* ========================================================= GTPC ========================================================== */ + #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ + #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ + #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ + #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ + #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ + #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ + #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDAE_Pos (2UL) /*!< SBDAE (Bit 2) */ + #define R_GPT0_GTSECR_SBDAE_Msk (0x4UL) /*!< SBDAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDDE_Pos (3UL) /*!< SBDDE (Bit 3) */ + #define R_GPT0_GTSECR_SBDDE_Msk (0x8UL) /*!< SBDDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDAD_Pos (10UL) /*!< SBDAD (Bit 10) */ + #define R_GPT0_GTSECR_SBDAD_Msk (0x400UL) /*!< SBDAD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDDD_Pos (11UL) /*!< SBDDD (Bit 11) */ + #define R_GPT0_GTSECR_SBDDD_Msk (0x800UL) /*!< SBDDD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ + #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SSCE_Pos (17UL) /*!< SSCE (Bit 17) */ + #define R_GPT0_GTSECR_SSCE_Msk (0x20000UL) /*!< SSCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ + #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SSCD_Pos (25UL) /*!< SSCD (Bit 25) */ + #define R_GPT0_GTSECR_SSCD_Msk (0x2000000UL) /*!< SSCD (Bitfield-Mask: 0x01) */ +/* ======================================================== GTBER2 ========================================================= */ + #define R_GPT0_GTBER2_CCTCA_Pos (0UL) /*!< CCTCA (Bit 0) */ + #define R_GPT0_GTBER2_CCTCA_Msk (0x1UL) /*!< CCTCA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTCB_Pos (1UL) /*!< CCTCB (Bit 1) */ + #define R_GPT0_GTBER2_CCTCB_Msk (0x2UL) /*!< CCTCB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTPR_Pos (2UL) /*!< CCTPR (Bit 2) */ + #define R_GPT0_GTBER2_CCTPR_Msk (0x4UL) /*!< CCTPR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTADA_Pos (3UL) /*!< CCTADA (Bit 3) */ + #define R_GPT0_GTBER2_CCTADA_Msk (0x8UL) /*!< CCTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTADB_Pos (4UL) /*!< CCTADB (Bit 4) */ + #define R_GPT0_GTBER2_CCTADB_Msk (0x10UL) /*!< CCTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTDV_Pos (5UL) /*!< CCTDV (Bit 5) */ + #define R_GPT0_GTBER2_CCTDV_Msk (0x20UL) /*!< CCTDV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CMTCA_Pos (8UL) /*!< CMTCA (Bit 8) */ + #define R_GPT0_GTBER2_CMTCA_Msk (0x300UL) /*!< CMTCA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_CMTCB_Pos (10UL) /*!< CMTCB (Bit 10) */ + #define R_GPT0_GTBER2_CMTCB_Msk (0xc00UL) /*!< CMTCB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_CMTADA_Pos (13UL) /*!< CMTADA (Bit 13) */ + #define R_GPT0_GTBER2_CMTADA_Msk (0x2000UL) /*!< CMTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CMTADB_Pos (14UL) /*!< CMTADB (Bit 14) */ + #define R_GPT0_GTBER2_CMTADB_Msk (0x4000UL) /*!< CMTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTCA_Pos (16UL) /*!< CPTCA (Bit 16) */ + #define R_GPT0_GTBER2_CPTCA_Msk (0x10000UL) /*!< CPTCA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTCB_Pos (17UL) /*!< CPTCB (Bit 17) */ + #define R_GPT0_GTBER2_CPTCB_Msk (0x20000UL) /*!< CPTCB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTPR_Pos (18UL) /*!< CPTPR (Bit 18) */ + #define R_GPT0_GTBER2_CPTPR_Msk (0x40000UL) /*!< CPTPR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTADA_Pos (19UL) /*!< CPTADA (Bit 19) */ + #define R_GPT0_GTBER2_CPTADA_Msk (0x80000UL) /*!< CPTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTADB_Pos (20UL) /*!< CPTADB (Bit 20) */ + #define R_GPT0_GTBER2_CPTADB_Msk (0x100000UL) /*!< CPTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTDV_Pos (21UL) /*!< CPTDV (Bit 21) */ + #define R_GPT0_GTBER2_CPTDV_Msk (0x200000UL) /*!< CPTDV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CP3DB_Pos (24UL) /*!< CP3DB (Bit 24) */ + #define R_GPT0_GTBER2_CP3DB_Msk (0x1000000UL) /*!< CP3DB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPBTD_Pos (25UL) /*!< CPBTD (Bit 25) */ + #define R_GPT0_GTBER2_CPBTD_Msk (0x2000000UL) /*!< CPBTD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_OLTTA_Pos (26UL) /*!< OLTTA (Bit 26) */ + #define R_GPT0_GTBER2_OLTTA_Msk (0xc000000UL) /*!< OLTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_OLTTB_Pos (28UL) /*!< OLTTB (Bit 28) */ + #define R_GPT0_GTBER2_OLTTB_Msk (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03) */ +/* ======================================================== GTOLBR ========================================================= */ + #define R_GPT0_GTOLBR_GTIOAB_Pos (0UL) /*!< GTIOAB (Bit 0) */ + #define R_GPT0_GTOLBR_GTIOAB_Msk (0x1fUL) /*!< GTIOAB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTOLBR_GTIOBB_Pos (16UL) /*!< GTIOBB (Bit 16) */ + #define R_GPT0_GTOLBR_GTIOBB_Msk (0x1f0000UL) /*!< GTIOBB (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTICCR ========================================================= */ + #define R_GPT0_GTICCR_ICAFA_Pos (0UL) /*!< ICAFA (Bit 0) */ + #define R_GPT0_GTICCR_ICAFA_Msk (0x1UL) /*!< ICAFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFB_Pos (1UL) /*!< ICAFB (Bit 1) */ + #define R_GPT0_GTICCR_ICAFB_Msk (0x2UL) /*!< ICAFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFC_Pos (2UL) /*!< ICAFC (Bit 2) */ + #define R_GPT0_GTICCR_ICAFC_Msk (0x4UL) /*!< ICAFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFD_Pos (3UL) /*!< ICAFD (Bit 3) */ + #define R_GPT0_GTICCR_ICAFD_Msk (0x8UL) /*!< ICAFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFE_Pos (4UL) /*!< ICAFE (Bit 4) */ + #define R_GPT0_GTICCR_ICAFE_Msk (0x10UL) /*!< ICAFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFF_Pos (5UL) /*!< ICAFF (Bit 5) */ + #define R_GPT0_GTICCR_ICAFF_Msk (0x20UL) /*!< ICAFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFPO_Pos (6UL) /*!< ICAFPO (Bit 6) */ + #define R_GPT0_GTICCR_ICAFPO_Msk (0x40UL) /*!< ICAFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFPU_Pos (7UL) /*!< ICAFPU (Bit 7) */ + #define R_GPT0_GTICCR_ICAFPU_Msk (0x80UL) /*!< ICAFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICACLK_Pos (8UL) /*!< ICACLK (Bit 8) */ + #define R_GPT0_GTICCR_ICACLK_Msk (0x100UL) /*!< ICACLK (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAGRP_Pos (14UL) /*!< ICAGRP (Bit 14) */ + #define R_GPT0_GTICCR_ICAGRP_Msk (0xc000UL) /*!< ICAGRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTICCR_ICBFA_Pos (16UL) /*!< ICBFA (Bit 16) */ + #define R_GPT0_GTICCR_ICBFA_Msk (0x10000UL) /*!< ICBFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFB_Pos (17UL) /*!< ICBFB (Bit 17) */ + #define R_GPT0_GTICCR_ICBFB_Msk (0x20000UL) /*!< ICBFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFC_Pos (18UL) /*!< ICBFC (Bit 18) */ + #define R_GPT0_GTICCR_ICBFC_Msk (0x40000UL) /*!< ICBFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFD_Pos (19UL) /*!< ICBFD (Bit 19) */ + #define R_GPT0_GTICCR_ICBFD_Msk (0x80000UL) /*!< ICBFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFE_Pos (20UL) /*!< ICBFE (Bit 20) */ + #define R_GPT0_GTICCR_ICBFE_Msk (0x100000UL) /*!< ICBFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFF_Pos (21UL) /*!< ICBFF (Bit 21) */ + #define R_GPT0_GTICCR_ICBFF_Msk (0x200000UL) /*!< ICBFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFPO_Pos (22UL) /*!< ICBFPO (Bit 22) */ + #define R_GPT0_GTICCR_ICBFPO_Msk (0x400000UL) /*!< ICBFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFPU_Pos (23UL) /*!< ICBFPU (Bit 23) */ + #define R_GPT0_GTICCR_ICBFPU_Msk (0x800000UL) /*!< ICBFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBCLK_Pos (24UL) /*!< ICBCLK (Bit 24) */ + #define R_GPT0_GTICCR_ICBCLK_Msk (0x1000000UL) /*!< ICBCLK (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBGRP_Pos (30UL) /*!< ICBGRP (Bit 30) */ + #define R_GPT0_GTICCR_ICBGRP_Msk (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_GTCLK ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== GTCLKCR ======================================================== */ + #define R_GPT_GTCLK_GTCLKCR_BPEN_Pos (0UL) /*!< BPEN (Bit 0) */ + #define R_GPT_GTCLK_GTCLKCR_BPEN_Msk (0x1UL) /*!< BPEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_ODC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= GTDLYCR1 ======================================================== */ + #define R_GPT_ODC_GTDLYCR1_FRANGE_Pos (8UL) /*!< FRANGE (Bit 8) */ + #define R_GPT_ODC_GTDLYCR1_FRANGE_Msk (0x300UL) /*!< FRANGE (Bitfield-Mask: 0x03) */ + #define R_GPT_ODC_GTDLYCR1_DLYRST_Pos (1UL) /*!< DLYRST (Bit 1) */ + #define R_GPT_ODC_GTDLYCR1_DLYRST_Msk (0x2UL) /*!< DLYRST (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR1_DLLEN_Pos (0UL) /*!< DLLEN (Bit 0) */ + #define R_GPT_ODC_GTDLYCR1_DLLEN_Msk (0x1UL) /*!< DLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================= GTDLYCR2 ======================================================== */ + #define R_GPT_ODC_GTDLYCR2_DLYDENB_Pos (12UL) /*!< DLYDENB (Bit 12) */ + #define R_GPT_ODC_GTDLYCR2_DLYDENB_Msk (0x1000UL) /*!< DLYDENB (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR2_DLYEN_Pos (8UL) /*!< DLYEN (Bit 8) */ + #define R_GPT_ODC_GTDLYCR2_DLYEN_Msk (0x100UL) /*!< DLYEN (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR2_DLYBS_Pos (0UL) /*!< DLYBS (Bit 0) */ + #define R_GPT_ODC_GTDLYCR2_DLYBS_Msk (0x1UL) /*!< DLYBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= OPSCR ========================================================= */ + #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */ + #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */ + #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */ + #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */ + #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */ + #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */ + #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */ + #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */ + #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */ + #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */ + #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */ + #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */ + #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */ + #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */ + #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= POEGG ========================================================= */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IRQCRa ========================================================= */ + #define R_ICU_IRQCRa_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCRa_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCRa_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCRa_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCRa_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCRa_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ +/* ========================================================= NMICR ========================================================= */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ +/* ======================================================== IRQCRb ========================================================= */ + #define R_ICU_IRQCRb_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCRb_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCRb_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCRb_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCRb_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCRb_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSELR ======================================================== */ + #define R_ICU_INTSELR_IS_Pos (0UL) /*!< IS (Bit 0) */ + #define R_ICU_INTSELR_IS_Msk (0x1UL) /*!< IS (Bitfield-Mask: 0x01) */ +/* ========================================================= NMIER ========================================================= */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_PVD1EN_Pos (2UL) /*!< PVD1EN (Bit 2) */ + #define R_ICU_NMIER_PVD1EN_Msk (0x4UL) /*!< PVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_PVD2EN_Pos (3UL) /*!< PVD2EN (Bit 3) */ + #define R_ICU_NMIER_PVD2EN_Msk (0x8UL) /*!< PVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_SOSTEN_Pos (5UL) /*!< SOSTEN (Bit 5) */ + #define R_ICU_NMIER_SOSTEN_Msk (0x20UL) /*!< SOSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSEN_Pos (12UL) /*!< BUSEN (Bit 12) */ + #define R_ICU_NMIER_BUSEN_Msk (0x1000UL) /*!< BUSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CMEN_Pos (13UL) /*!< CMEN (Bit 13) */ + #define R_ICU_NMIER_CMEN_Msk (0x2000UL) /*!< CMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LMEN_Pos (14UL) /*!< LMEN (Bit 14) */ + #define R_ICU_NMIER_LMEN_Msk (0x4000UL) /*!< LMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LUEN_Pos (15UL) /*!< LUEN (Bit 15) */ + #define R_ICU_NMIER_LUEN_Msk (0x8000UL) /*!< LUEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_FPUFLTEN_Pos (16UL) /*!< FPUFLTEN (Bit 16) */ + #define R_ICU_NMIER_FPUFLTEN_Msk (0x10000UL) /*!< FPUFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_MRCRDEN_Pos (17UL) /*!< MRCRDEN (Bit 17) */ + #define R_ICU_NMIER_MRCRDEN_Msk (0x20000UL) /*!< MRCRDEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_MRERDEN_Pos (18UL) /*!< MRERDEN (Bit 18) */ + #define R_ICU_NMIER_MRERDEN_Msk (0x40000UL) /*!< MRERDEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IPCEN_Pos (20UL) /*!< IPCEN (Bit 20) */ + #define R_ICU_NMIER_IPCEN_Msk (0x100000UL) /*!< IPCEN (Bitfield-Mask: 0x01) */ +/* ======================================================== NMICLR ========================================================= */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_PVD1CLR_Pos (2UL) /*!< PVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_PVD1CLR_Msk (0x4UL) /*!< PVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_PVD2CLR_Pos (3UL) /*!< PVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_PVD2CLR_Msk (0x8UL) /*!< PVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_SOSTCLR_Pos (5UL) /*!< SOSTCLR (Bit 5) */ + #define R_ICU_NMICLR_SOSTCLR_Msk (0x20UL) /*!< SOSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSCLR_Pos (12UL) /*!< BUSCLR (Bit 12) */ + #define R_ICU_NMICLR_BUSCLR_Msk (0x1000UL) /*!< BUSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CMCLR_Pos (13UL) /*!< CMCLR (Bit 13) */ + #define R_ICU_NMICLR_CMCLR_Msk (0x2000UL) /*!< CMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LMCLR_Pos (14UL) /*!< LMCLR (Bit 14) */ + #define R_ICU_NMICLR_LMCLR_Msk (0x4000UL) /*!< LMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LUCLR_Pos (15UL) /*!< LUCLR (Bit 15) */ + #define R_ICU_NMICLR_LUCLR_Msk (0x8000UL) /*!< LUCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_FPUFLTCLR_Pos (16UL) /*!< FPUFLTCLR (Bit 16) */ + #define R_ICU_NMICLR_FPUFLTCLR_Msk (0x10000UL) /*!< FPUFLTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_MRCRDCLR_Pos (17UL) /*!< MRCRDCLR (Bit 17) */ + #define R_ICU_NMICLR_MRCRDCLR_Msk (0x20000UL) /*!< MRCRDCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_MRERDCLR_Pos (18UL) /*!< MRERDCLR (Bit 18) */ + #define R_ICU_NMICLR_MRERDCLR_Msk (0x40000UL) /*!< MRERDCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IPCCLR_Pos (20UL) /*!< IPCCLR (Bit 20) */ + #define R_ICU_NMICLR_IPCCLR_Msk (0x100000UL) /*!< IPCCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= NMISR ========================================================= */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_PVD1ST_Pos (2UL) /*!< PVD1ST (Bit 2) */ + #define R_ICU_NMISR_PVD1ST_Msk (0x4UL) /*!< PVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_PVD2ST_Pos (3UL) /*!< PVD2ST (Bit 3) */ + #define R_ICU_NMISR_PVD2ST_Msk (0x8UL) /*!< PVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_SOSTST_Pos (5UL) /*!< SOSTST (Bit 5) */ + #define R_ICU_NMISR_SOSTST_Msk (0x20UL) /*!< SOSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSST_Pos (12UL) /*!< BUSST (Bit 12) */ + #define R_ICU_NMISR_BUSST_Msk (0x1000UL) /*!< BUSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CMST_Pos (13UL) /*!< CMST (Bit 13) */ + #define R_ICU_NMISR_CMST_Msk (0x2000UL) /*!< CMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LMST_Pos (14UL) /*!< LMST (Bit 14) */ + #define R_ICU_NMISR_LMST_Msk (0x4000UL) /*!< LMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LUST_Pos (15UL) /*!< LUST (Bit 15) */ + #define R_ICU_NMISR_LUST_Msk (0x8000UL) /*!< LUST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_FPUFLTST_Pos (16UL) /*!< FPUFLTST (Bit 16) */ + #define R_ICU_NMISR_FPUFLTST_Msk (0x10000UL) /*!< FPUFLTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_MRCRDST_Pos (17UL) /*!< MRCRDST (Bit 17) */ + #define R_ICU_NMISR_MRCRDST_Msk (0x20000UL) /*!< MRCRDST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_MRERDST_Pos (18UL) /*!< MRERDST (Bit 18) */ + #define R_ICU_NMISR_MRERDST_Msk (0x40000UL) /*!< MRERDST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IPCST_Pos (20UL) /*!< IPCST (Bit 20) */ + #define R_ICU_NMISR_IPCST_Msk (0x100000UL) /*!< IPCST (Bitfield-Mask: 0x01) */ +/* ========================================================= WUPEN ========================================================= */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_WUPEN_Pos (16UL) /*!< WUPEN (Bit 16) */ + #define R_ICU_WUPEN_WUPEN_Msk (0x10000UL) /*!< WUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN1 ========================================================= */ + #define R_ICU_WUPEN1_WUPEN_Pos (0UL) /*!< WUPEN (Bit 0) */ + #define R_ICU_WUPEN1_WUPEN_Msk (0x1UL) /*!< WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_IRQWUPEN_Pos (16UL) /*!< IRQWUPEN (Bit 16) */ + #define R_ICU_WUPEN1_IRQWUPEN_Msk (0x10000UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ +/* ===================================================== DSLPWUPIRQEN ====================================================== */ + #define R_ICU_DSLPWUPIRQEN_IRQ_Pos (0UL) /*!< IRQ (Bit 0) */ + #define R_ICU_DSLPWUPIRQEN_IRQ_Msk (0x1UL) /*!< IRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= DELSR ========================================================= */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x3ffUL) /*!< DELS (Bitfield-Mask: 0x3ff) */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ +/* ========================================================= IELSR ========================================================= */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x3ffUL) /*!< IELS (Bitfield-Mask: 0x3ff) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ + #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ + #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ + #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ +/* ========================================================= ICDRR ========================================================= */ + #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ + #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ +/* ========================================================= ICWUR ========================================================= */ + #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ + #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ + #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ + #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ + #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ + #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICWUR2 ========================================================= */ + #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ + #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ + #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ + #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IWDTRR ========================================================= */ + #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ + #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ +/* ======================================================== IWDTCR ========================================================= */ + #define R_IWDT_IWDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_IWDT_IWDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_IWDT_IWDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_IWDT_IWDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_IWDT_IWDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IWDT_IWDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_IWDT_IWDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_IWDT_IWDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ======================================================== IWDTSR ========================================================= */ + #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== IWDTRCR ======================================================== */ + #define R_IWDT_IWDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_IWDT_IWDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= IWDTCSTPR ======================================================= */ + #define R_IWDT_IWDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_IWDT_IWDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_I3C0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PRTS ========================================================== */ + #define R_I3C0_PRTS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */ + #define R_I3C0_PRTS_PRTMD_Msk (0x1UL) /*!< PRTMD (Bitfield-Mask: 0x01) */ +/* ========================================================= CECTL ========================================================= */ + #define R_I3C0_CECTL_CLKE_Pos (0UL) /*!< CLKE (Bit 0) */ + #define R_I3C0_CECTL_CLKE_Msk (0x1UL) /*!< CLKE (Bitfield-Mask: 0x01) */ +/* ========================================================= BCTL ========================================================== */ + #define R_I3C0_BCTL_INCBA_Pos (0UL) /*!< INCBA (Bit 0) */ + #define R_I3C0_BCTL_INCBA_Msk (0x1UL) /*!< INCBA (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_BMDS_Pos (7UL) /*!< BMDS (Bit 7) */ + #define R_I3C0_BCTL_BMDS_Msk (0x80UL) /*!< BMDS (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_HJACKCTL_Pos (8UL) /*!< HJACKCTL (Bit 8) */ + #define R_I3C0_BCTL_HJACKCTL_Msk (0x100UL) /*!< HJACKCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_ABT_Pos (29UL) /*!< ABT (Bit 29) */ + #define R_I3C0_BCTL_ABT_Msk (0x20000000UL) /*!< ABT (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_RSM_Pos (30UL) /*!< RSM (Bit 30) */ + #define R_I3C0_BCTL_RSM_Msk (0x40000000UL) /*!< RSM (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_BUSE_Pos (31UL) /*!< BUSE (Bit 31) */ + #define R_I3C0_BCTL_BUSE_Msk (0x80000000UL) /*!< BUSE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSDVAD ========================================================= */ + #define R_I3C0_MSDVAD_MDYAD_Pos (16UL) /*!< MDYAD (Bit 16) */ + #define R_I3C0_MSDVAD_MDYAD_Msk (0x7f0000UL) /*!< MDYAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_MSDVAD_MDYADV_Pos (31UL) /*!< MDYADV (Bit 31) */ + #define R_I3C0_MSDVAD_MDYADV_Msk (0x80000000UL) /*!< MDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTCTL ========================================================= */ + #define R_I3C0_RSTCTL_RI3CRST_Pos (0UL) /*!< RI3CRST (Bit 0) */ + #define R_I3C0_RSTCTL_RI3CRST_Msk (0x1UL) /*!< RI3CRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_CMDQRST_Pos (1UL) /*!< CMDQRST (Bit 1) */ + #define R_I3C0_RSTCTL_CMDQRST_Msk (0x2UL) /*!< CMDQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RSPQRST_Pos (2UL) /*!< RSPQRST (Bit 2) */ + #define R_I3C0_RSTCTL_RSPQRST_Msk (0x4UL) /*!< RSPQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_TDBRST_Pos (3UL) /*!< TDBRST (Bit 3) */ + #define R_I3C0_RSTCTL_TDBRST_Msk (0x8UL) /*!< TDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RDBRST_Pos (4UL) /*!< RDBRST (Bit 4) */ + #define R_I3C0_RSTCTL_RDBRST_Msk (0x10UL) /*!< RDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_IBIQRST_Pos (5UL) /*!< IBIQRST (Bit 5) */ + #define R_I3C0_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */ + #define R_I3C0_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HCMDQRST_Pos (9UL) /*!< HCMDQRST (Bit 9) */ + #define R_I3C0_RSTCTL_HCMDQRST_Msk (0x200UL) /*!< HCMDQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRSPQRST_Pos (10UL) /*!< HRSPQRST (Bit 10) */ + #define R_I3C0_RSTCTL_HRSPQRST_Msk (0x400UL) /*!< HRSPQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HTDBRST_Pos (11UL) /*!< HTDBRST (Bit 11) */ + #define R_I3C0_RSTCTL_HTDBRST_Msk (0x800UL) /*!< HTDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRDBRST_Pos (12UL) /*!< HRDBRST (Bit 12) */ + #define R_I3C0_RSTCTL_HRDBRST_Msk (0x1000UL) /*!< HRDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */ + #define R_I3C0_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */ +/* ========================================================= PRSST ========================================================= */ + #define R_I3C0_PRSST_CRMS_Pos (2UL) /*!< CRMS (Bit 2) */ + #define R_I3C0_PRSST_CRMS_Msk (0x4UL) /*!< CRMS (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSST_TRMD_Pos (4UL) /*!< TRMD (Bit 4) */ + #define R_I3C0_PRSST_TRMD_Msk (0x10UL) /*!< TRMD (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSST_PRSSTWP_Pos (7UL) /*!< PRSSTWP (Bit 7) */ + #define R_I3C0_PRSST_PRSSTWP_Msk (0x80UL) /*!< PRSSTWP (Bitfield-Mask: 0x01) */ +/* ========================================================= INST ========================================================== */ + #define R_I3C0_INST_INEF_Pos (10UL) /*!< INEF (Bit 10) */ + #define R_I3C0_INST_INEF_Msk (0x400UL) /*!< INEF (Bitfield-Mask: 0x01) */ +/* ========================================================= INSTE ========================================================= */ + #define R_I3C0_INSTE_INEE_Pos (10UL) /*!< INEE (Bit 10) */ + #define R_I3C0_INSTE_INEE_Msk (0x400UL) /*!< INEE (Bitfield-Mask: 0x01) */ +/* ========================================================= INIE ========================================================== */ + #define R_I3C0_INIE_INEIE_Pos (10UL) /*!< INEIE (Bit 10) */ + #define R_I3C0_INIE_INEIE_Msk (0x400UL) /*!< INEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== INSTFC ========================================================= */ + #define R_I3C0_INSTFC_INEFC_Pos (10UL) /*!< INEFC (Bit 10) */ + #define R_I3C0_INSTFC_INEFC_Msk (0x400UL) /*!< INEFC (Bitfield-Mask: 0x01) */ +/* ========================================================= DVCT ========================================================== */ + #define R_I3C0_DVCT_IDX_Pos (19UL) /*!< IDX (Bit 19) */ + #define R_I3C0_DVCT_IDX_Msk (0xf80000UL) /*!< IDX (Bitfield-Mask: 0x1f) */ +/* ======================================================== IBINCTL ======================================================== */ + #define R_I3C0_IBINCTL_NRHJCTL_Pos (0UL) /*!< NRHJCTL (Bit 0) */ + #define R_I3C0_IBINCTL_NRHJCTL_Msk (0x1UL) /*!< NRHJCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_IBINCTL_NRMRCTL_Pos (1UL) /*!< NRMRCTL (Bit 1) */ + #define R_I3C0_IBINCTL_NRMRCTL_Msk (0x2UL) /*!< NRMRCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_IBINCTL_NRSIRCTL_Pos (3UL) /*!< NRSIRCTL (Bit 3) */ + #define R_I3C0_IBINCTL_NRSIRCTL_Msk (0x8UL) /*!< NRSIRCTL (Bitfield-Mask: 0x01) */ +/* ========================================================= BFCTL ========================================================= */ + #define R_I3C0_BFCTL_MALE_Pos (0UL) /*!< MALE (Bit 0) */ + #define R_I3C0_BFCTL_MALE_Msk (0x1UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_NALE_Pos (1UL) /*!< NALE (Bit 1) */ + #define R_I3C0_BFCTL_NALE_Msk (0x2UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SALE_Pos (2UL) /*!< SALE (Bit 2) */ + #define R_I3C0_BFCTL_SALE_Msk (0x4UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SCSYNE_Pos (8UL) /*!< SCSYNE (Bit 8) */ + #define R_I3C0_BFCTL_SCSYNE_Msk (0x100UL) /*!< SCSYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SMBS_Pos (12UL) /*!< SMBS (Bit 12) */ + #define R_I3C0_BFCTL_SMBS_Msk (0x1000UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_FMPE_Pos (14UL) /*!< FMPE (Bit 14) */ + #define R_I3C0_BFCTL_FMPE_Msk (0x4000UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_HSME_Pos (15UL) /*!< HSME (Bit 15) */ + #define R_I3C0_BFCTL_HSME_Msk (0x8000UL) /*!< HSME (Bitfield-Mask: 0x01) */ +/* ========================================================= SVCTL ========================================================= */ + #define R_I3C0_SVCTL_GCAE_Pos (0UL) /*!< GCAE (Bit 0) */ + #define R_I3C0_SVCTL_GCAE_Msk (0x1UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_HSMCE_Pos (5UL) /*!< HSMCE (Bit 5) */ + #define R_I3C0_SVCTL_HSMCE_Msk (0x20UL) /*!< HSMCE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_DVIDE_Pos (6UL) /*!< DVIDE (Bit 6) */ + #define R_I3C0_SVCTL_DVIDE_Msk (0x40UL) /*!< DVIDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */ + #define R_I3C0_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */ + #define R_I3C0_SVCTL_SVAEn_Msk (0x70000UL) /*!< SVAEn (Bitfield-Mask: 0x07) */ +/* ======================================================= REFCKCTL ======================================================== */ + #define R_I3C0_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */ + #define R_I3C0_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */ +/* ========================================================= STDBR ========================================================= */ + #define R_I3C0_STDBR_SBRLO_Pos (0UL) /*!< SBRLO (Bit 0) */ + #define R_I3C0_STDBR_SBRLO_Msk (0xffUL) /*!< SBRLO (Bitfield-Mask: 0xff) */ + #define R_I3C0_STDBR_SBRHO_Pos (8UL) /*!< SBRHO (Bit 8) */ + #define R_I3C0_STDBR_SBRHO_Msk (0xff00UL) /*!< SBRHO (Bitfield-Mask: 0xff) */ + #define R_I3C0_STDBR_SBRLP_Pos (16UL) /*!< SBRLP (Bit 16) */ + #define R_I3C0_STDBR_SBRLP_Msk (0x3f0000UL) /*!< SBRLP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_STDBR_SBRHP_Pos (24UL) /*!< SBRHP (Bit 24) */ + #define R_I3C0_STDBR_SBRHP_Msk (0x3f000000UL) /*!< SBRHP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_STDBR_DSBRPO_Pos (31UL) /*!< DSBRPO (Bit 31) */ + #define R_I3C0_STDBR_DSBRPO_Msk (0x80000000UL) /*!< DSBRPO (Bitfield-Mask: 0x01) */ +/* ========================================================= EXTBR ========================================================= */ + #define R_I3C0_EXTBR_EBRLO_Pos (0UL) /*!< EBRLO (Bit 0) */ + #define R_I3C0_EXTBR_EBRLO_Msk (0xffUL) /*!< EBRLO (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXTBR_EBRHO_Pos (8UL) /*!< EBRHO (Bit 8) */ + #define R_I3C0_EXTBR_EBRHO_Msk (0xff00UL) /*!< EBRHO (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXTBR_EBRLP_Pos (16UL) /*!< EBRLP (Bit 16) */ + #define R_I3C0_EXTBR_EBRLP_Msk (0x3f0000UL) /*!< EBRLP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_EXTBR_EBRHP_Pos (24UL) /*!< EBRHP (Bit 24) */ + #define R_I3C0_EXTBR_EBRHP_Msk (0x3f000000UL) /*!< EBRHP (Bitfield-Mask: 0x3f) */ +/* ======================================================== BFRECDT ======================================================== */ + #define R_I3C0_BFRECDT_FRECYC_Pos (0UL) /*!< FRECYC (Bit 0) */ + #define R_I3C0_BFRECDT_FRECYC_Msk (0x1ffUL) /*!< FRECYC (Bitfield-Mask: 0x1ff) */ +/* ======================================================== BAVLCDT ======================================================== */ + #define R_I3C0_BAVLCDT_AVLCYC_Pos (0UL) /*!< AVLCYC (Bit 0) */ + #define R_I3C0_BAVLCDT_AVLCYC_Msk (0x1ffUL) /*!< AVLCYC (Bitfield-Mask: 0x1ff) */ +/* ======================================================== BIDLCDT ======================================================== */ + #define R_I3C0_BIDLCDT_IDLCYC_Pos (0UL) /*!< IDLCYC (Bit 0) */ + #define R_I3C0_BIDLCDT_IDLCYC_Msk (0x3ffffUL) /*!< IDLCYC (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== OUTCTL ========================================================= */ + #define R_I3C0_OUTCTL_SDOC_Pos (0UL) /*!< SDOC (Bit 0) */ + #define R_I3C0_OUTCTL_SDOC_Msk (0x1UL) /*!< SDOC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SCOC_Pos (1UL) /*!< SCOC (Bit 1) */ + #define R_I3C0_OUTCTL_SCOC_Msk (0x2UL) /*!< SCOC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SOCWP_Pos (2UL) /*!< SOCWP (Bit 2) */ + #define R_I3C0_OUTCTL_SOCWP_Msk (0x4UL) /*!< SOCWP (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_EXCYC_Pos (4UL) /*!< EXCYC (Bit 4) */ + #define R_I3C0_OUTCTL_EXCYC_Msk (0x10UL) /*!< EXCYC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SDOD_Pos (8UL) /*!< SDOD (Bit 8) */ + #define R_I3C0_OUTCTL_SDOD_Msk (0x700UL) /*!< SDOD (Bitfield-Mask: 0x07) */ + #define R_I3C0_OUTCTL_SDODCS_Pos (15UL) /*!< SDODCS (Bit 15) */ + #define R_I3C0_OUTCTL_SDODCS_Msk (0x8000UL) /*!< SDODCS (Bitfield-Mask: 0x01) */ +/* ========================================================= INCTL ========================================================= */ + #define R_I3C0_INCTL_DNFS_Pos (0UL) /*!< DNFS (Bit 0) */ + #define R_I3C0_INCTL_DNFS_Msk (0xfUL) /*!< DNFS (Bitfield-Mask: 0x0f) */ + #define R_I3C0_INCTL_DNFE_Pos (4UL) /*!< DNFE (Bit 4) */ + #define R_I3C0_INCTL_DNFE_Msk (0x10UL) /*!< DNFE (Bitfield-Mask: 0x01) */ +/* ======================================================== TMOCTL ========================================================= */ + #define R_I3C0_TMOCTL_TODTS_Pos (0UL) /*!< TODTS (Bit 0) */ + #define R_I3C0_TMOCTL_TODTS_Msk (0x3UL) /*!< TODTS (Bitfield-Mask: 0x03) */ + #define R_I3C0_TMOCTL_TOLCTL_Pos (4UL) /*!< TOLCTL (Bit 4) */ + #define R_I3C0_TMOCTL_TOLCTL_Msk (0x10UL) /*!< TOLCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_TMOCTL_TOHCTL_Pos (5UL) /*!< TOHCTL (Bit 5) */ + #define R_I3C0_TMOCTL_TOHCTL_Msk (0x20UL) /*!< TOHCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_TMOCTL_TOMDS_Pos (6UL) /*!< TOMDS (Bit 6) */ + #define R_I3C0_TMOCTL_TOMDS_Msk (0xc0UL) /*!< TOMDS (Bitfield-Mask: 0x03) */ +/* ========================================================= WUCTL ========================================================= */ + #define R_I3C0_WUCTL_WUACKS_Pos (0UL) /*!< WUACKS (Bit 0) */ + #define R_I3C0_WUCTL_WUACKS_Msk (0x1UL) /*!< WUACKS (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUANFS_Pos (4UL) /*!< WUANFS (Bit 4) */ + #define R_I3C0_WUCTL_WUANFS_Msk (0x10UL) /*!< WUANFS (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUFSYNE_Pos (6UL) /*!< WUFSYNE (Bit 6) */ + #define R_I3C0_WUCTL_WUFSYNE_Msk (0x40UL) /*!< WUFSYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUFE_Pos (7UL) /*!< WUFE (Bit 7) */ + #define R_I3C0_WUCTL_WUFE_Msk (0x80UL) /*!< WUFE (Bitfield-Mask: 0x01) */ +/* ======================================================== ACKCTL ========================================================= */ + #define R_I3C0_ACKCTL_ACKR_Pos (0UL) /*!< ACKR (Bit 0) */ + #define R_I3C0_ACKCTL_ACKR_Msk (0x1UL) /*!< ACKR (Bitfield-Mask: 0x01) */ + #define R_I3C0_ACKCTL_ACKT_Pos (1UL) /*!< ACKT (Bit 1) */ + #define R_I3C0_ACKCTL_ACKT_Msk (0x2UL) /*!< ACKT (Bitfield-Mask: 0x01) */ + #define R_I3C0_ACKCTL_ACKTWP_Pos (2UL) /*!< ACKTWP (Bit 2) */ + #define R_I3C0_ACKCTL_ACKTWP_Msk (0x4UL) /*!< ACKTWP (Bitfield-Mask: 0x01) */ +/* ======================================================= SCSTRCTL ======================================================== */ + #define R_I3C0_SCSTRCTL_ACKTWE_Pos (0UL) /*!< ACKTWE (Bit 0) */ + #define R_I3C0_SCSTRCTL_ACKTWE_Msk (0x1UL) /*!< ACKTWE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTRCTL_RWE_Pos (1UL) /*!< RWE (Bit 1) */ + #define R_I3C0_SCSTRCTL_RWE_Msk (0x2UL) /*!< RWE (Bitfield-Mask: 0x01) */ +/* ======================================================= SCSTLCTL ======================================================== */ + #define R_I3C0_SCSTLCTL_STLCYC_Pos (0UL) /*!< STLCYC (Bit 0) */ + #define R_I3C0_SCSTLCTL_STLCYC_Msk (0xffffUL) /*!< STLCYC (Bitfield-Mask: 0xffff) */ + #define R_I3C0_SCSTLCTL_AAPE_Pos (28UL) /*!< AAPE (Bit 28) */ + #define R_I3C0_SCSTLCTL_AAPE_Msk (0x10000000UL) /*!< AAPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_TRAPE_Pos (29UL) /*!< TRAPE (Bit 29) */ + #define R_I3C0_SCSTLCTL_TRAPE_Msk (0x20000000UL) /*!< TRAPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_PARPE_Pos (30UL) /*!< PARPE (Bit 30) */ + #define R_I3C0_SCSTLCTL_PARPE_Msk (0x40000000UL) /*!< PARPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_ACKPE_Pos (31UL) /*!< ACKPE (Bit 31) */ + #define R_I3C0_SCSTLCTL_ACKPE_Msk (0x80000000UL) /*!< ACKPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SVTDLG0 ======================================================== */ + #define R_I3C0_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */ + #define R_I3C0_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */ +/* ========================================================= STCTL ========================================================= */ + #define R_I3C0_STCTL_STOE_Pos (0UL) /*!< STOE (Bit 0) */ + #define R_I3C0_STCTL_STOE_Msk (0x1UL) /*!< STOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ATCTL ========================================================= */ + #define R_I3C0_ATCTL_ATTRGS_Pos (0UL) /*!< ATTRGS (Bit 0) */ + #define R_I3C0_ATCTL_ATTRGS_Msk (0x1UL) /*!< ATTRGS (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_MREFOE_Pos (1UL) /*!< MREFOE (Bit 1) */ + #define R_I3C0_ATCTL_MREFOE_Msk (0x2UL) /*!< MREFOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_AMEOE_Pos (2UL) /*!< AMEOE (Bit 2) */ + #define R_I3C0_ATCTL_AMEOE_Msk (0x4UL) /*!< AMEOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_CDIV_Pos (8UL) /*!< CDIV (Bit 8) */ + #define R_I3C0_ATCTL_CDIV_Msk (0xff00UL) /*!< CDIV (Bitfield-Mask: 0xff) */ +/* ========================================================= ATTRG ========================================================= */ + #define R_I3C0_ATTRG_ATSTRG_Pos (0UL) /*!< ATSTRG (Bit 0) */ + #define R_I3C0_ATTRG_ATSTRG_Msk (0x1UL) /*!< ATSTRG (Bitfield-Mask: 0x01) */ +/* ======================================================== ATCCNTE ======================================================== */ + #define R_I3C0_ATCCNTE_ATCE_Pos (0UL) /*!< ATCE (Bit 0) */ + #define R_I3C0_ATCCNTE_ATCE_Msk (0x1UL) /*!< ATCE (Bitfield-Mask: 0x01) */ +/* ======================================================== CNDCTL ========================================================= */ + #define R_I3C0_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */ + #define R_I3C0_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */ + #define R_I3C0_CNDCTL_SRCND_Pos (1UL) /*!< SRCND (Bit 1) */ + #define R_I3C0_CNDCTL_SRCND_Msk (0x2UL) /*!< SRCND (Bitfield-Mask: 0x01) */ + #define R_I3C0_CNDCTL_SPCND_Pos (2UL) /*!< SPCND (Bit 2) */ + #define R_I3C0_CNDCTL_SPCND_Msk (0x4UL) /*!< SPCND (Bitfield-Mask: 0x01) */ +/* ======================================================== NCMDQP ========================================================= */ +/* ======================================================== NRSPQP ========================================================= */ +/* ======================================================== NTDTBP0 ======================================================== */ +/* ======================================================== NIBIQP ========================================================= */ +/* ========================================================= NRSQP ========================================================= */ +/* ======================================================== HCMDQP ========================================================= */ + #define R_I3C0_HCMDQP_HCMDQP_Pos (0UL) /*!< HCMDQP (Bit 0) */ + #define R_I3C0_HCMDQP_HCMDQP_Msk (0xffffffffUL) /*!< HCMDQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HRSPQP ========================================================= */ + #define R_I3C0_HRSPQP_HRSPQP_Pos (0UL) /*!< HRSPQP (Bit 0) */ + #define R_I3C0_HRSPQP_HRSPQP_Msk (0xffffffffUL) /*!< HRSPQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HTDTBP ========================================================= */ + #define R_I3C0_HTDTBP_HTDTBP_Pos (0UL) /*!< HTDTBP (Bit 0) */ + #define R_I3C0_HTDTBP_HTDTBP_Msk (0xffffffffUL) /*!< HTDTBP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== NQTHCTL ======================================================== */ + #define R_I3C0_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ + #define R_I3C0_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ + #define R_I3C0_NQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_IBIDSSZ_Pos (16UL) /*!< IBIDSSZ (Bit 16) */ + #define R_I3C0_NQTHCTL_IBIDSSZ_Msk (0xff0000UL) /*!< IBIDSSZ (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_IBIQTH_Pos (24UL) /*!< IBIQTH (Bit 24) */ + #define R_I3C0_NQTHCTL_IBIQTH_Msk (0xff000000UL) /*!< IBIQTH (Bitfield-Mask: 0xff) */ +/* ======================================================= NTBTHCTL0 ======================================================= */ + #define R_I3C0_NTBTHCTL0_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ + #define R_I3C0_NTBTHCTL0_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ + #define R_I3C0_NTBTHCTL0_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ + #define R_I3C0_NTBTHCTL0_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ + #define R_I3C0_NTBTHCTL0_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ +/* ======================================================= NRQTHCTL ======================================================== */ + #define R_I3C0_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */ + #define R_I3C0_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */ +/* ======================================================== HQTHCTL ======================================================== */ + #define R_I3C0_HQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ + #define R_I3C0_HQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ + #define R_I3C0_HQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ +/* ======================================================= HTBTHCTL ======================================================== */ + #define R_I3C0_HTBTHCTL_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ + #define R_I3C0_HTBTHCTL_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ +/* ========================================================== BST ========================================================== */ + #define R_I3C0_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */ + #define R_I3C0_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_SPCNDDF_Pos (1UL) /*!< SPCNDDF (Bit 1) */ + #define R_I3C0_BST_SPCNDDF_Msk (0x2UL) /*!< SPCNDDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_HDREXDF_Pos (2UL) /*!< HDREXDF (Bit 2) */ + #define R_I3C0_BST_HDREXDF_Msk (0x4UL) /*!< HDREXDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_NACKDF_Pos (4UL) /*!< NACKDF (Bit 4) */ + #define R_I3C0_BST_NACKDF_Msk (0x10UL) /*!< NACKDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_TENDF_Pos (8UL) /*!< TENDF (Bit 8) */ + #define R_I3C0_BST_TENDF_Msk (0x100UL) /*!< TENDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_ALF_Pos (16UL) /*!< ALF (Bit 16) */ + #define R_I3C0_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */ + #define R_I3C0_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_WUCNDDF_Pos (24UL) /*!< WUCNDDF (Bit 24) */ + #define R_I3C0_BST_WUCNDDF_Msk (0x1000000UL) /*!< WUCNDDF (Bitfield-Mask: 0x01) */ +/* ========================================================= BSTE ========================================================== */ + #define R_I3C0_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */ + #define R_I3C0_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_SPCNDDE_Pos (1UL) /*!< SPCNDDE (Bit 1) */ + #define R_I3C0_BSTE_SPCNDDE_Msk (0x2UL) /*!< SPCNDDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_HDREXDE_Pos (2UL) /*!< HDREXDE (Bit 2) */ + #define R_I3C0_BSTE_HDREXDE_Msk (0x4UL) /*!< HDREXDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_NACKDE_Pos (4UL) /*!< NACKDE (Bit 4) */ + #define R_I3C0_BSTE_NACKDE_Msk (0x10UL) /*!< NACKDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_TENDE_Pos (8UL) /*!< TENDE (Bit 8) */ + #define R_I3C0_BSTE_TENDE_Msk (0x100UL) /*!< TENDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_ALE_Pos (16UL) /*!< ALE (Bit 16) */ + #define R_I3C0_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */ + #define R_I3C0_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_WUCNDDE_Pos (24UL) /*!< WUCNDDE (Bit 24) */ + #define R_I3C0_BSTE_WUCNDDE_Msk (0x1000000UL) /*!< WUCNDDE (Bitfield-Mask: 0x01) */ +/* ========================================================== BIE ========================================================== */ + #define R_I3C0_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */ + #define R_I3C0_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_SPCNDDIE_Pos (1UL) /*!< SPCNDDIE (Bit 1) */ + #define R_I3C0_BIE_SPCNDDIE_Msk (0x2UL) /*!< SPCNDDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_HDREXDIE_Pos (2UL) /*!< HDREXDIE (Bit 2) */ + #define R_I3C0_BIE_HDREXDIE_Msk (0x4UL) /*!< HDREXDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_NACKDIE_Pos (4UL) /*!< NACKDIE (Bit 4) */ + #define R_I3C0_BIE_NACKDIE_Msk (0x10UL) /*!< NACKDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_TENDIE_Pos (8UL) /*!< TENDIE (Bit 8) */ + #define R_I3C0_BIE_TENDIE_Msk (0x100UL) /*!< TENDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_ALIE_Pos (16UL) /*!< ALIE (Bit 16) */ + #define R_I3C0_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */ + #define R_I3C0_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_WUCNDDIE_Pos (24UL) /*!< WUCNDDIE (Bit 24) */ + #define R_I3C0_BIE_WUCNDDIE_Msk (0x1000000UL) /*!< WUCNDDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= BSTFC ========================================================= */ + #define R_I3C0_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */ + #define R_I3C0_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_SPCNDDFC_Pos (1UL) /*!< SPCNDDFC (Bit 1) */ + #define R_I3C0_BSTFC_SPCNDDFC_Msk (0x2UL) /*!< SPCNDDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_HDREXDFC_Pos (2UL) /*!< HDREXDFC (Bit 2) */ + #define R_I3C0_BSTFC_HDREXDFC_Msk (0x4UL) /*!< HDREXDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_NACKDFC_Pos (4UL) /*!< NACKDFC (Bit 4) */ + #define R_I3C0_BSTFC_NACKDFC_Msk (0x10UL) /*!< NACKDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_TENDFC_Pos (8UL) /*!< TENDFC (Bit 8) */ + #define R_I3C0_BSTFC_TENDFC_Msk (0x100UL) /*!< TENDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_ALFC_Pos (16UL) /*!< ALFC (Bit 16) */ + #define R_I3C0_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */ + #define R_I3C0_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_WUCNDDFC_Pos (24UL) /*!< WUCNDDFC (Bit 24) */ + #define R_I3C0_BSTFC_WUCNDDFC_Msk (0x1000000UL) /*!< WUCNDDFC (Bitfield-Mask: 0x01) */ +/* ========================================================= NTST ========================================================== */ + #define R_I3C0_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */ + #define R_I3C0_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RDBFF0_Pos (1UL) /*!< RDBFF0 (Bit 1) */ + #define R_I3C0_NTST_RDBFF0_Msk (0x2UL) /*!< RDBFF0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_IBIQEFF_Pos (2UL) /*!< IBIQEFF (Bit 2) */ + #define R_I3C0_NTST_IBIQEFF_Msk (0x4UL) /*!< IBIQEFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ + #define R_I3C0_NTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ + #define R_I3C0_NTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ + #define R_I3C0_NTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ + #define R_I3C0_NTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RSQFF_Pos (20UL) /*!< RSQFF (Bit 20) */ + #define R_I3C0_NTST_RSQFF_Msk (0x100000UL) /*!< RSQFF (Bitfield-Mask: 0x01) */ +/* ========================================================= NTSTE ========================================================= */ + #define R_I3C0_NTSTE_TDBEE0_Pos (0UL) /*!< TDBEE0 (Bit 0) */ + #define R_I3C0_NTSTE_TDBEE0_Msk (0x1UL) /*!< TDBEE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RDBFE0_Pos (1UL) /*!< RDBFE0 (Bit 1) */ + #define R_I3C0_NTSTE_RDBFE0_Msk (0x2UL) /*!< RDBFE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_IBIQEFE_Pos (2UL) /*!< IBIQEFE (Bit 2) */ + #define R_I3C0_NTSTE_IBIQEFE_Msk (0x4UL) /*!< IBIQEFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ + #define R_I3C0_NTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ + #define R_I3C0_NTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ + #define R_I3C0_NTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ + #define R_I3C0_NTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RSQFE_Pos (20UL) /*!< RSQFE (Bit 20) */ + #define R_I3C0_NTSTE_RSQFE_Msk (0x100000UL) /*!< RSQFE (Bitfield-Mask: 0x01) */ +/* ========================================================= NTIE ========================================================== */ + #define R_I3C0_NTIE_TDBEIE0_Pos (0UL) /*!< TDBEIE0 (Bit 0) */ + #define R_I3C0_NTIE_TDBEIE0_Msk (0x1UL) /*!< TDBEIE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RDBFIE0_Pos (1UL) /*!< RDBFIE0 (Bit 1) */ + #define R_I3C0_NTIE_RDBFIE0_Msk (0x2UL) /*!< RDBFIE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_IBIQEFIE_Pos (2UL) /*!< IBIQEFIE (Bit 2) */ + #define R_I3C0_NTIE_IBIQEFIE_Msk (0x4UL) /*!< IBIQEFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ + #define R_I3C0_NTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ + #define R_I3C0_NTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ + #define R_I3C0_NTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ + #define R_I3C0_NTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RSQFIE_Pos (20UL) /*!< RSQFIE (Bit 20) */ + #define R_I3C0_NTIE_RSQFIE_Msk (0x100000UL) /*!< RSQFIE (Bitfield-Mask: 0x01) */ +/* ======================================================== NTSTFC ========================================================= */ + #define R_I3C0_NTSTFC_TDBEFC0_Pos (0UL) /*!< TDBEFC0 (Bit 0) */ + #define R_I3C0_NTSTFC_TDBEFC0_Msk (0x1UL) /*!< TDBEFC0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RDBFFC0_Pos (1UL) /*!< RDBFFC0 (Bit 1) */ + #define R_I3C0_NTSTFC_RDBFFC0_Msk (0x2UL) /*!< RDBFFC0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_IBIQEFFC_Pos (2UL) /*!< IBIQEFFC (Bit 2) */ + #define R_I3C0_NTSTFC_IBIQEFFC_Msk (0x4UL) /*!< IBIQEFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ + #define R_I3C0_NTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ + #define R_I3C0_NTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ + #define R_I3C0_NTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ + #define R_I3C0_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */ + #define R_I3C0_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */ +/* ========================================================= HTST ========================================================== */ + #define R_I3C0_HTST_TDBEF_Pos (0UL) /*!< TDBEF (Bit 0) */ + #define R_I3C0_HTST_TDBEF_Msk (0x1UL) /*!< TDBEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RDBFF_Pos (1UL) /*!< RDBFF (Bit 1) */ + #define R_I3C0_HTST_RDBFF_Msk (0x2UL) /*!< RDBFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ + #define R_I3C0_HTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ + #define R_I3C0_HTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ + #define R_I3C0_HTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ + #define R_I3C0_HTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ +/* ========================================================= HTSTE ========================================================= */ + #define R_I3C0_HTSTE_TDBEE_Pos (0UL) /*!< TDBEE (Bit 0) */ + #define R_I3C0_HTSTE_TDBEE_Msk (0x1UL) /*!< TDBEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RDBFE_Pos (1UL) /*!< RDBFE (Bit 1) */ + #define R_I3C0_HTSTE_RDBFE_Msk (0x2UL) /*!< RDBFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ + #define R_I3C0_HTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ + #define R_I3C0_HTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ + #define R_I3C0_HTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ + #define R_I3C0_HTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ +/* ========================================================= HTIE ========================================================== */ + #define R_I3C0_HTIE_TDBEIE_Pos (0UL) /*!< TDBEIE (Bit 0) */ + #define R_I3C0_HTIE_TDBEIE_Msk (0x1UL) /*!< TDBEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RDBFIE_Pos (1UL) /*!< RDBFIE (Bit 1) */ + #define R_I3C0_HTIE_RDBFIE_Msk (0x2UL) /*!< RDBFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ + #define R_I3C0_HTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ + #define R_I3C0_HTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ + #define R_I3C0_HTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ + #define R_I3C0_HTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== HTSTFC ========================================================= */ + #define R_I3C0_HTSTFC_TDBEFC_Pos (0UL) /*!< TDBEFC (Bit 0) */ + #define R_I3C0_HTSTFC_TDBEFC_Msk (0x1UL) /*!< TDBEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RDBFFC_Pos (1UL) /*!< RDBFFC (Bit 1) */ + #define R_I3C0_HTSTFC_RDBFFC_Msk (0x2UL) /*!< RDBFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ + #define R_I3C0_HTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ + #define R_I3C0_HTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ + #define R_I3C0_HTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ + #define R_I3C0_HTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ +/* ========================================================= BCST ========================================================== */ + #define R_I3C0_BCST_BFREF_Pos (0UL) /*!< BFREF (Bit 0) */ + #define R_I3C0_BCST_BFREF_Msk (0x1UL) /*!< BFREF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCST_BAVLF_Pos (1UL) /*!< BAVLF (Bit 1) */ + #define R_I3C0_BCST_BAVLF_Msk (0x2UL) /*!< BAVLF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCST_BIDLF_Pos (2UL) /*!< BIDLF (Bit 2) */ + #define R_I3C0_BCST_BIDLF_Msk (0x4UL) /*!< BIDLF (Bitfield-Mask: 0x01) */ +/* ========================================================= SVST ========================================================== */ + #define R_I3C0_SVST_GCAF_Pos (0UL) /*!< GCAF (Bit 0) */ + #define R_I3C0_SVST_GCAF_Msk (0x1UL) /*!< GCAF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_HSMCF_Pos (5UL) /*!< HSMCF (Bit 5) */ + #define R_I3C0_SVST_HSMCF_Msk (0x20UL) /*!< HSMCF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_DVIDF_Pos (6UL) /*!< DVIDF (Bit 6) */ + #define R_I3C0_SVST_DVIDF_Msk (0x40UL) /*!< DVIDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */ + #define R_I3C0_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */ + #define R_I3C0_SVST_SVAFn_Msk (0x70000UL) /*!< SVAFn (Bitfield-Mask: 0x07) */ +/* ========================================================= WUST ========================================================== */ + #define R_I3C0_WUST_WUASYNF_Pos (0UL) /*!< WUASYNF (Bit 0) */ + #define R_I3C0_WUST_WUASYNF_Msk (0x1UL) /*!< WUASYNF (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCCPT ========================================================= */ + #define R_I3C0_MRCCPT_MRCCPT_Pos (0UL) /*!< MRCCPT (Bit 0) */ + #define R_I3C0_MRCCPT_MRCCPT_Msk (0xffffffffUL) /*!< MRCCPT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DATBAS0 ======================================================== */ + #define R_I3C0_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS0_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS0_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS0_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS0_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS0_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS0_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS0_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS0_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS0_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS0_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS1 ======================================================== */ + #define R_I3C0_DATBAS1_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS1_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS1_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS1_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS1_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS1_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS1_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS1_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS1_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS1_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS1_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS1_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS2 ======================================================== */ + #define R_I3C0_DATBAS2_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS2_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS2_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS2_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS2_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS2_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS2_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS2_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS2_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS2_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS2_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS2_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS3 ======================================================== */ + #define R_I3C0_DATBAS3_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS3_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS3_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS3_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS3_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS3_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS3_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS3_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS3_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS4 ======================================================== */ + #define R_I3C0_DATBAS4_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS4_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS4_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS4_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS4_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS4_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS4_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS4_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS4_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS4_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS4_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS5 ======================================================== */ + #define R_I3C0_DATBAS5_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS5_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS5_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS5_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS5_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS5_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS5_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS5_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS5_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS5_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS5_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS6 ======================================================== */ + #define R_I3C0_DATBAS6_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS6_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS6_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS6_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS6_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS6_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS6_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS6_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS6_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS6_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS6_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS7 ======================================================== */ + #define R_I3C0_DATBAS7_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS7_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS7_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS7_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS7_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS7_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS7_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS7_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS7_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS7_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS7_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================= EXDATBAS ======================================================== */ + #define R_I3C0_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */ + #define R_I3C0_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_EXDATBAS_EDDYAD_Pos (16UL) /*!< EDDYAD (Bit 16) */ + #define R_I3C0_EXDATBAS_EDDYAD_Msk (0xff0000UL) /*!< EDDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXDATBAS_EDNACK_Pos (29UL) /*!< EDNACK (Bit 29) */ + #define R_I3C0_EXDATBAS_EDNACK_Msk (0x60000000UL) /*!< EDNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_EXDATBAS_EDTYP_Pos (31UL) /*!< EDTYP (Bit 31) */ + #define R_I3C0_EXDATBAS_EDTYP_Msk (0x80000000UL) /*!< EDTYP (Bitfield-Mask: 0x01) */ +/* ======================================================= SDATBAS0 ======================================================== */ + #define R_I3C0_SDATBAS0_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS0_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS0_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS0_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS0_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS0_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS0_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS0_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================= SDATBAS1 ======================================================== */ + #define R_I3C0_SDATBAS1_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS1_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS1_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS1_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS1_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS1_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS1_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS1_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================= SDATBAS2 ======================================================== */ + #define R_I3C0_SDATBAS2_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS2_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS2_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS2_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS2_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS2_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS2_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS2_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================== MSDCT0 ========================================================= */ + #define R_I3C0_MSDCT0_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT0_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT0_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT0_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT0_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT1 ========================================================= */ + #define R_I3C0_MSDCT1_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT1_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT1_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT1_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT1_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT2 ========================================================= */ + #define R_I3C0_MSDCT2_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT2_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT2_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT2_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT2_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT3 ========================================================= */ + #define R_I3C0_MSDCT3_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT3_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT3_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT3_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT4 ========================================================= */ + #define R_I3C0_MSDCT4_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT4_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT4_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT4_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT4_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT4_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT4_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT4_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT5 ========================================================= */ + #define R_I3C0_MSDCT5_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT5_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT5_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT5_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT5_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT5_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT5_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT5_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT6 ========================================================= */ + #define R_I3C0_MSDCT6_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT6_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT6_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT6_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT6_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT6_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT6_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT6_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT7 ========================================================= */ + #define R_I3C0_MSDCT7_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT7_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT7_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT7_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT7_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT7_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT7_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT7_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ========================================================= SVDCT ========================================================= */ + #define R_I3C0_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ + #define R_I3C0_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ + #define R_I3C0_SVDCT_TBCR0_Pos (8UL) /*!< TBCR0 (Bit 8) */ + #define R_I3C0_SVDCT_TBCR0_Msk (0x100UL) /*!< TBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR1_Pos (9UL) /*!< TBCR1 (Bit 9) */ + #define R_I3C0_SVDCT_TBCR1_Msk (0x200UL) /*!< TBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR2_Pos (10UL) /*!< TBCR2 (Bit 10) */ + #define R_I3C0_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */ + #define R_I3C0_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR4_Pos (12UL) /*!< TBCR4 (Bit 12) */ + #define R_I3C0_SVDCT_TBCR4_Msk (0x1000UL) /*!< TBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR5_Pos (13UL) /*!< TBCR5 (Bit 13) */ + #define R_I3C0_SVDCT_TBCR5_Msk (0x2000UL) /*!< TBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */ + #define R_I3C0_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================= SDCTPIDL ======================================================== */ +/* ======================================================= SDCTPIDH ======================================================== */ +/* ======================================================== SVDVAD0 ======================================================== */ + #define R_I3C0_SVDVAD0_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD0_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD0_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD0_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD0_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD1 ======================================================== */ + #define R_I3C0_SVDVAD1_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD1_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD1_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD1_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD1_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD1_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD2 ======================================================== */ + #define R_I3C0_SVDVAD2_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD2_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD2_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD2_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD2_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD2_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== CSECMD ========================================================= */ + #define R_I3C0_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */ + #define R_I3C0_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CSECMD_MSRQE_Pos (1UL) /*!< MSRQE (Bit 1) */ + #define R_I3C0_CSECMD_MSRQE_Msk (0x2UL) /*!< MSRQE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CSECMD_HJEVE_Pos (3UL) /*!< HJEVE (Bit 3) */ + #define R_I3C0_CSECMD_HJEVE_Msk (0x8UL) /*!< HJEVE (Bitfield-Mask: 0x01) */ +/* ======================================================== CEACTST ======================================================== */ + #define R_I3C0_CEACTST_ACTST_Pos (0UL) /*!< ACTST (Bit 0) */ + #define R_I3C0_CEACTST_ACTST_Msk (0xfUL) /*!< ACTST (Bitfield-Mask: 0x0f) */ +/* ========================================================= CMWLG ========================================================= */ + #define R_I3C0_CMWLG_MWLG_Pos (0UL) /*!< MWLG (Bit 0) */ + #define R_I3C0_CMWLG_MWLG_Msk (0xffffUL) /*!< MWLG (Bitfield-Mask: 0xffff) */ +/* ========================================================= CMRLG ========================================================= */ + #define R_I3C0_CMRLG_MRLG_Pos (0UL) /*!< MRLG (Bit 0) */ + #define R_I3C0_CMRLG_MRLG_Msk (0xffffUL) /*!< MRLG (Bitfield-Mask: 0xffff) */ + #define R_I3C0_CMRLG_IBIPSZ_Pos (16UL) /*!< IBIPSZ (Bit 16) */ + #define R_I3C0_CMRLG_IBIPSZ_Msk (0xff0000UL) /*!< IBIPSZ (Bitfield-Mask: 0xff) */ +/* ======================================================== CETSTMD ======================================================== */ + #define R_I3C0_CETSTMD_TSTMD_Pos (0UL) /*!< TSTMD (Bit 0) */ + #define R_I3C0_CETSTMD_TSTMD_Msk (0xffUL) /*!< TSTMD (Bitfield-Mask: 0xff) */ +/* ======================================================== CGDVST ========================================================= */ + #define R_I3C0_CGDVST_PNDINT_Pos (0UL) /*!< PNDINT (Bit 0) */ + #define R_I3C0_CGDVST_PNDINT_Msk (0xfUL) /*!< PNDINT (Bitfield-Mask: 0x0f) */ + #define R_I3C0_CGDVST_PRTE_Pos (5UL) /*!< PRTE (Bit 5) */ + #define R_I3C0_CGDVST_PRTE_Msk (0x20UL) /*!< PRTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGDVST_ACTMD_Pos (6UL) /*!< ACTMD (Bit 6) */ + #define R_I3C0_CGDVST_ACTMD_Msk (0xc0UL) /*!< ACTMD (Bitfield-Mask: 0x03) */ + #define R_I3C0_CGDVST_VDRSV_Pos (8UL) /*!< VDRSV (Bit 8) */ + #define R_I3C0_CGDVST_VDRSV_Msk (0xff00UL) /*!< VDRSV (Bitfield-Mask: 0xff) */ +/* ======================================================== CMDSPW ========================================================= */ + #define R_I3C0_CMDSPW_MSWDR_Pos (0UL) /*!< MSWDR (Bit 0) */ + #define R_I3C0_CMDSPW_MSWDR_Msk (0x7UL) /*!< MSWDR (Bitfield-Mask: 0x07) */ +/* ======================================================== CMDSPR ========================================================= */ + #define R_I3C0_CMDSPR_MSRDR_Pos (0UL) /*!< MSRDR (Bit 0) */ + #define R_I3C0_CMDSPR_MSRDR_Msk (0x7UL) /*!< MSRDR (Bitfield-Mask: 0x07) */ + #define R_I3C0_CMDSPR_CDTTIM_Pos (3UL) /*!< CDTTIM (Bit 3) */ + #define R_I3C0_CMDSPR_CDTTIM_Msk (0x38UL) /*!< CDTTIM (Bitfield-Mask: 0x07) */ +/* ======================================================== CMDSPT ========================================================= */ + #define R_I3C0_CMDSPT_MRTTIM_Pos (0UL) /*!< MRTTIM (Bit 0) */ + #define R_I3C0_CMDSPT_MRTTIM_Msk (0xffffffUL) /*!< MRTTIM (Bitfield-Mask: 0xffffff) */ + #define R_I3C0_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */ + #define R_I3C0_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */ +/* ========================================================= CETSM ========================================================= */ + #define R_I3C0_CETSM_SPTSYN_Pos (0UL) /*!< SPTSYN (Bit 0) */ + #define R_I3C0_CETSM_SPTSYN_Msk (0x1UL) /*!< SPTSYN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN0_Pos (1UL) /*!< SPTASYN0 (Bit 1) */ + #define R_I3C0_CETSM_SPTASYN0_Msk (0x2UL) /*!< SPTASYN0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN1_Pos (2UL) /*!< SPTASYN1 (Bit 2) */ + #define R_I3C0_CETSM_SPTASYN1_Msk (0x4UL) /*!< SPTASYN1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */ + #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ + #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ + #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ========================================================= CETSS ========================================================= */ + #define R_I3C0_CETSS_SYNE_Pos (0UL) /*!< SYNE (Bit 0) */ + #define R_I3C0_CETSS_SYNE_Msk (0x1UL) /*!< SYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSS_ASYNE_Pos (1UL) /*!< ASYNE (Bit 1) */ + #define R_I3C0_CETSS_ASYNE_Msk (0x6UL) /*!< ASYNE (Bitfield-Mask: 0x03) */ + #define R_I3C0_CETSS_ICOVF_Pos (7UL) /*!< ICOVF (Bit 7) */ + #define R_I3C0_CETSS_ICOVF_Msk (0x80UL) /*!< ICOVF (Bitfield-Mask: 0x01) */ +/* ======================================================= CGHDRCAP ======================================================== */ + #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ + #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSPEN_Pos (1UL) /*!< TSPEN (Bit 1) */ + #define R_I3C0_CGHDRCAP_TSPEN_Msk (0x2UL) /*!< TSPEN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSLEN_Pos (2UL) /*!< TSLEN (Bit 2) */ + #define R_I3C0_CGHDRCAP_TSLEN_Msk (0x4UL) /*!< TSLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BITCNT ========================================================= */ + #define R_I3C0_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */ + #define R_I3C0_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */ + #define R_I3C0_BITCNT_BCNTWP_Pos (7UL) /*!< BCNTWP (Bit 7) */ + #define R_I3C0_BITCNT_BCNTWP_Msk (0x80UL) /*!< BCNTWP (Bitfield-Mask: 0x01) */ +/* ======================================================== NQSTLV ========================================================= */ + #define R_I3C0_NQSTLV_CMDQFLV_Pos (0UL) /*!< CMDQFLV (Bit 0) */ + #define R_I3C0_NQSTLV_CMDQFLV_Msk (0xffUL) /*!< CMDQFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ + #define R_I3C0_NQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_IBIQLV_Pos (16UL) /*!< IBIQLV (Bit 16) */ + #define R_I3C0_NQSTLV_IBIQLV_Msk (0xff0000UL) /*!< IBIQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_IBISCNT_Pos (24UL) /*!< IBISCNT (Bit 24) */ + #define R_I3C0_NQSTLV_IBISCNT_Msk (0x1f000000UL) /*!< IBISCNT (Bitfield-Mask: 0x1f) */ +/* ======================================================= NDBSTLV0 ======================================================== */ + #define R_I3C0_NDBSTLV0_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ + #define R_I3C0_NDBSTLV0_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NDBSTLV0_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ + #define R_I3C0_NDBSTLV0_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ +/* ======================================================= NRSQSTLV ======================================================== */ + #define R_I3C0_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */ + #define R_I3C0_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HQSTLV ========================================================= */ + #define R_I3C0_HQSTLV_CMDQLV_Pos (0UL) /*!< CMDQLV (Bit 0) */ + #define R_I3C0_HQSTLV_CMDQLV_Msk (0xffUL) /*!< CMDQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ + #define R_I3C0_HQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HDBSTLV ======================================================== */ + #define R_I3C0_HDBSTLV_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ + #define R_I3C0_HDBSTLV_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HDBSTLV_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ + #define R_I3C0_HDBSTLV_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ +/* ======================================================== PRSTDBG ======================================================== */ + #define R_I3C0_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */ + #define R_I3C0_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SDILV_Pos (1UL) /*!< SDILV (Bit 1) */ + #define R_I3C0_PRSTDBG_SDILV_Msk (0x2UL) /*!< SDILV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SCOLV_Pos (2UL) /*!< SCOLV (Bit 2) */ + #define R_I3C0_PRSTDBG_SCOLV_Msk (0x4UL) /*!< SCOLV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SDOLV_Pos (3UL) /*!< SDOLV (Bit 3) */ + #define R_I3C0_PRSTDBG_SDOLV_Msk (0x8UL) /*!< SDOLV (Bitfield-Mask: 0x01) */ +/* ======================================================= MSERRCNT ======================================================== */ + #define R_I3C0_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */ + #define R_I3C0_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */ +/* ======================================================== SC1CPT ========================================================= */ + #define R_I3C0_SC1CPT_SC1C_Pos (0UL) /*!< SC1C (Bit 0) */ + #define R_I3C0_SC1CPT_SC1C_Msk (0xffffUL) /*!< SC1C (Bitfield-Mask: 0xffff) */ +/* ======================================================== SC2CPT ========================================================= */ + #define R_I3C0_SC2CPT_SC2C_Pos (0UL) /*!< SC2C (Bit 0) */ + #define R_I3C0_SC2CPT_SC2C_Msk (0xffffUL) /*!< SC2C (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_MMPU_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_MMPU_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= OADPT ========================================================= */ + #define R_MPU_MMPU_OADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_OADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MSTPCRA ======================================================== */ + #define R_MSTP_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */ + #define R_MSTP_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_MSTP_MSTPCRB_MSTPB_Pos (0UL) /*!< MSTPB (Bit 0) */ + #define R_MSTP_MSTPCRB_MSTPB_Msk (0x1UL) /*!< MSTPB (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_MSTP_MSTPCRC_MSTPC_Pos (0UL) /*!< MSTPC (Bit 0) */ + #define R_MSTP_MSTPCRC_MSTPC_Msk (0x1UL) /*!< MSTPC (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_MSTP_MSTPCRD_MSTPD_Pos (0UL) /*!< MSTPD (Bit 0) */ + #define R_MSTP_MSTPCRD_MSTPD_Msk (0x1UL) /*!< MSTPD (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_MSTP_MSTPCRE_MSTPE_Pos (0UL) /*!< MSTPE (Bit 0) */ + #define R_MSTP_MSTPCRE_MSTPE_Msk (0x1UL) /*!< MSTPE (Bitfield-Mask: 0x01) */ +/* ======================================================= LSMRWDIS ======================================================== */ + #define R_MSTP_LSMRWDIS_RTCRWDIS_Pos (0UL) /*!< RTCRWDIS (Bit 0) */ + #define R_MSTP_LSMRWDIS_RTCRWDIS_Msk (0x1UL) /*!< RTCRWDIS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_WDTDIS_Pos (1UL) /*!< WDTDIS (Bit 1) */ + #define R_MSTP_LSMRWDIS_WDTDIS_Msk (0x2UL) /*!< WDTDIS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_IWDTIDS_Pos (2UL) /*!< IWDTIDS (Bit 2) */ + #define R_MSTP_LSMRWDIS_IWDTIDS_Msk (0x4UL) /*!< IWDTIDS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_WREN_Pos (7UL) /*!< WREN (Bit 7) */ + #define R_MSTP_LSMRWDIS_WREN_Msk (0x80UL) /*!< WREN (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_MSTP_LSMRWDIS_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PCNTR1 ========================================================= */ + #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ +/* ========================================================== PDR ========================================================== */ + #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ +/* ========================================================= PODR ========================================================== */ + #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR2 ========================================================= */ + #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PIDR ========================================================== */ + #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ +/* ========================================================= EIDR ========================================================== */ + #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ + #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR3 ========================================================= */ + #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ +/* ========================================================= POSR ========================================================== */ + #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ +/* ========================================================= PORR ========================================================== */ + #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ + #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR4 ========================================================= */ + #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EOSR ========================================================== */ + #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ +/* ========================================================= EORR ========================================================== */ + #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ + #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PFENET ========================================================= */ + #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ + #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPR ========================================================== */ + #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPRS ========================================================= */ + #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== R64CNT ========================================================= */ + #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ + #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ + #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ + #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ +/* ======================================================== RSECCNT ======================================================== */ + #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ + #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINCNT ======================================================== */ + #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ + #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ +/* ======================================================== RHRCNT ========================================================= */ + #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ + #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RWKCNT ========================================================= */ + #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================== RDAYCNT ======================================================== */ + #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RMONCNT ======================================================== */ + #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RYRCNT ========================================================= */ + #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT0AR ======================================================== */ + #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ + #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RSECAR ========================================================= */ + #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT1AR ======================================================== */ + #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ + #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINAR ========================================================= */ + #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT2AR ======================================================== */ + #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ + #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RHRAR ========================================================= */ + #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT3AR ======================================================== */ + #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ + #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RWKAR ========================================================= */ + #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================= BCNT0AER ======================================================== */ + #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYAR ========================================================= */ + #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT1AER ======================================================== */ + #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RMONAR ========================================================= */ + #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT2AER ======================================================== */ + #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RYRAR ========================================================= */ + #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT3AER ======================================================== */ + #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RYRAREN ======================================================== */ + #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR1 ========================================================== */ + #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ + #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ + #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ + #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ + #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ + #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ + #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR2 ========================================================== */ + #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ + #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ + #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ + #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ + #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ + #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ + #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ + #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR4 ========================================================== */ + #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ + #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ + #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRH ========================================================== */ + #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ + #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRL ========================================================== */ + #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= RADJ ========================================================== */ + #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ + #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ + #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ + #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ +/* ========================================================= RADJ2 ========================================================= */ + #define R_RTC_RADJ2_FADJ_Pos (5UL) /*!< FADJ (Bit 5) */ + #define R_RTC_RADJ2_FADJ_Msk (0xffe0UL) /*!< FADJ (Bitfield-Mask: 0x7ff) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SMR ========================================================== */ + #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ + #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ + #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ + #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ======================================================= SMR_SMCI ======================================================== */ + #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ + #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ + #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ + #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ + #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ========================================================== BRR ========================================================== */ + #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ + #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== SCR ========================================================== */ + #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ======================================================= SCR_SMCI ======================================================== */ + #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ + #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ +/* ========================================================== SSR ========================================================== */ + #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_FIFO ======================================================== */ + #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ + #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_MANC ======================================================== */ + #define R_SCI0_SSR_MANC_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_MANC_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_MANC_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_MANC_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_MANC_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_MANC_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_MANC_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MANC_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_MER_Pos (0UL) /*!< MER (Bit 0) */ + #define R_SCI0_SSR_MANC_MER_Msk (0x1UL) /*!< MER (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_SMCI ======================================================== */ + #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ + #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ +/* ========================================================= SCMR ========================================================== */ + #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ + #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ + #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ + #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ + #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ + #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SEMR ========================================================== */ + #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ + #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ + #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ + #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ + #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ + #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ + #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ + #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ + #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SNFR ========================================================== */ + #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ + #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ +/* ========================================================= SIMR1 ========================================================= */ + #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ + #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ + #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR2 ========================================================= */ + #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ + #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ + #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ + #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR3 ========================================================= */ + #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ + #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ + #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ + #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ + #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ + #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ +/* ========================================================= SPMR ========================================================== */ + #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ + #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ + #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ + #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ + #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ + #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ + #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ + #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TDRHL ========================================================= */ + #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ + #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FTDRHL ========================================================= */ + #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FTDRH ========================================================= */ + #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ + #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ + #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FTDRL ========================================================= */ + #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ + #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= RDRHL ========================================================= */ + #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ + #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRDRHL ========================================================= */ + #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ + #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ + #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ + #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ + #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ +/* ======================================================= TDRHL_MAN ======================================================= */ + #define R_SCI0_TDRHL_MAN_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_TDRHL_MAN_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI0_TDRHL_MAN_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_TDRHL_MAN_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_TDRHL_MAN_TSYNC_Pos (12UL) /*!< TSYNC (Bit 12) */ + #define R_SCI0_TDRHL_MAN_TSYNC_Msk (0x1000UL) /*!< TSYNC (Bitfield-Mask: 0x01) */ +/* ======================================================= RDRHL_MAN ======================================================= */ + #define R_SCI0_RDRHL_MAN_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_RDRHL_MAN_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI0_RDRHL_MAN_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_RDRHL_MAN_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_RDRHL_MAN_RSYNC_Pos (12UL) /*!< RSYNC (Bit 12) */ + #define R_SCI0_RDRHL_MAN_RSYNC_Msk (0x1000UL) /*!< RSYNC (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRH ========================================================= */ + #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ + #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ + #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRL ========================================================= */ + #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ + #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= MDDR ========================================================== */ + #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ + #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= DCCR ========================================================== */ + #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ + #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ + #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ + #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ + #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ + #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ + #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ + #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ + #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ + #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ + #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ + #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ + #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ + #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ + #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ +/* ========================================================== LSR ========================================================== */ + #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ + #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ + #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ +/* ========================================================== CDR ========================================================== */ + #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ +/* ========================================================= SPTR ========================================================== */ + #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ + #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ + #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ + #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ + #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ + #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ + #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ + #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ACTR ========================================================== */ + #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ + #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ + #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ + #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ + #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= ESMER ========================================================= */ + #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ + #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ + #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ + #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ + #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ + #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ + #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ + #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ + #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ + #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ + #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ + #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ +/* ========================================================== CR2 ========================================================== */ + #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ + #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ + #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ + #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ +/* ========================================================== CR3 ========================================================== */ + #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ + #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ +/* ========================================================== PCR ========================================================== */ + #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ + #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ + #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ + #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ + #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ + #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ + #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ + #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ + #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ + #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ + #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ + #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ + #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ + #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ + #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ + #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ +/* ========================================================= STCR ========================================================== */ + #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ + #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ + #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ + #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ + #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ + #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ + #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0DR ========================================================= */ +/* ========================================================= CF0CR ========================================================= */ + #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ + #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ + #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ + #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ + #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ + #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ + #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ + #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ + #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0RR ========================================================= */ +/* ======================================================== PCF1DR ========================================================= */ +/* ======================================================== SCF1DR ========================================================= */ +/* ========================================================= CF1CR ========================================================= */ + #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ + #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ + #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ + #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ + #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ + #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ + #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ + #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ + #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF1RR ========================================================= */ +/* ========================================================== TCR ========================================================== */ + #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ +/* ========================================================== TMR ========================================================== */ + #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ + #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ + #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ + #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ + #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ +/* ========================================================= TPRE ========================================================== */ +/* ========================================================= TCNT ========================================================== */ +/* ======================================================= SCIMSKEN ======================================================== */ + #define R_SCI0_SCIMSKEN_MSKEN_Pos (0UL) /*!< MSKEN (Bit 0) */ + #define R_SCI0_SCIMSKEN_MSKEN_Msk (0x1UL) /*!< MSKEN (Bitfield-Mask: 0x01) */ +/* ========================================================== MMR ========================================================== */ + #define R_SCI0_MMR_MANEN_Pos (7UL) /*!< MANEN (Bit 7) */ + #define R_SCI0_MMR_MANEN_Msk (0x80UL) /*!< MANEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_SBSEL_Pos (6UL) /*!< SBSEL (Bit 6) */ + #define R_SCI0_MMR_SBSEL_Msk (0x40UL) /*!< SBSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_SYNSEL_Pos (5UL) /*!< SYNSEL (Bit 5) */ + #define R_SCI0_MMR_SYNSEL_Msk (0x20UL) /*!< SYNSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_SYNVAL_Pos (4UL) /*!< SYNVAL (Bit 4) */ + #define R_SCI0_MMR_SYNVAL_Msk (0x10UL) /*!< SYNVAL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_ERTEN_Pos (2UL) /*!< ERTEN (Bit 2) */ + #define R_SCI0_MMR_ERTEN_Msk (0x4UL) /*!< ERTEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_TMPOL_Pos (1UL) /*!< TMPOL (Bit 1) */ + #define R_SCI0_MMR_TMPOL_Msk (0x2UL) /*!< TMPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_RMPOL_Pos (0UL) /*!< RMPOL (Bit 0) */ + #define R_SCI0_MMR_RMPOL_Msk (0x1UL) /*!< RMPOL (Bitfield-Mask: 0x01) */ +/* ========================================================= TMPR ========================================================== */ + #define R_SCI0_TMPR_TPLEN_Pos (0UL) /*!< TPLEN (Bit 0) */ + #define R_SCI0_TMPR_TPLEN_Msk (0xfUL) /*!< TPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI0_TMPR_TPPAT_Pos (4UL) /*!< TPPAT (Bit 4) */ + #define R_SCI0_TMPR_TPPAT_Msk (0x30UL) /*!< TPPAT (Bitfield-Mask: 0x03) */ +/* ========================================================= RMPR ========================================================== */ + #define R_SCI0_RMPR_RPLEN_Pos (0UL) /*!< RPLEN (Bit 0) */ + #define R_SCI0_RMPR_RPLEN_Msk (0xfUL) /*!< RPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI0_RMPR_RPPAT_Pos (4UL) /*!< RPPAT (Bit 4) */ + #define R_SCI0_RMPR_RPPAT_Msk (0x30UL) /*!< RPPAT (Bitfield-Mask: 0x03) */ +/* ========================================================= MESR ========================================================== */ + #define R_SCI0_MESR_PFER_Pos (0UL) /*!< PFER (Bit 0) */ + #define R_SCI0_MESR_PFER_Msk (0x1UL) /*!< PFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_MESR_SYER_Pos (1UL) /*!< SYER (Bit 1) */ + #define R_SCI0_MESR_SYER_Msk (0x2UL) /*!< SYER (Bitfield-Mask: 0x01) */ + #define R_SCI0_MESR_SBER_Pos (2UL) /*!< SBER (Bit 2) */ + #define R_SCI0_MESR_SBER_Msk (0x4UL) /*!< SBER (Bitfield-Mask: 0x01) */ +/* ========================================================= MECR ========================================================== */ + #define R_SCI0_MECR_PFEREN_Pos (0UL) /*!< PFEREN (Bit 0) */ + #define R_SCI0_MECR_PFEREN_Msk (0x1UL) /*!< PFEREN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MECR_SYEREN_Pos (1UL) /*!< SYEREN (Bit 1) */ + #define R_SCI0_MECR_SYEREN_Msk (0x2UL) /*!< SYEREN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MECR_SBEREN_Pos (2UL) /*!< SBEREN (Bit 2) */ + #define R_SCI0_MECR_SBEREN_Msk (0x4UL) /*!< SBEREN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SD_CMD ========================================================= */ + #define R_SDHI0_SD_CMD_CMD12AT_Pos (14UL) /*!< CMD12AT (Bit 14) */ + #define R_SDHI0_SD_CMD_CMD12AT_Msk (0xc000UL) /*!< CMD12AT (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_TRSTP_Pos (13UL) /*!< TRSTP (Bit 13) */ + #define R_SDHI0_SD_CMD_TRSTP_Msk (0x2000UL) /*!< TRSTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDRW_Pos (12UL) /*!< CMDRW (Bit 12) */ + #define R_SDHI0_SD_CMD_CMDRW_Msk (0x1000UL) /*!< CMDRW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDTP_Pos (11UL) /*!< CMDTP (Bit 11) */ + #define R_SDHI0_SD_CMD_CMDTP_Msk (0x800UL) /*!< CMDTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_RSPTP_Pos (8UL) /*!< RSPTP (Bit 8) */ + #define R_SDHI0_SD_CMD_RSPTP_Msk (0x700UL) /*!< RSPTP (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_CMD_ACMD_Pos (6UL) /*!< ACMD (Bit 6) */ + #define R_SDHI0_SD_CMD_ACMD_Msk (0xc0UL) /*!< ACMD (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_CMDIDX_Pos (0UL) /*!< CMDIDX (Bit 0) */ + #define R_SDHI0_SD_CMD_CMDIDX_Msk (0x3fUL) /*!< CMDIDX (Bitfield-Mask: 0x3f) */ +/* ======================================================== SD_ARG ========================================================= */ + #define R_SDHI0_SD_ARG_SD_ARG_Pos (0UL) /*!< SD_ARG (Bit 0) */ + #define R_SDHI0_SD_ARG_SD_ARG_Msk (0xffffffffUL) /*!< SD_ARG (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_ARG1 ======================================================== */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Pos (0UL) /*!< SD_ARG1 (Bit 0) */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Msk (0xffffUL) /*!< SD_ARG1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== SD_STOP ======================================================== */ + #define R_SDHI0_SD_STOP_SEC_Pos (8UL) /*!< SEC (Bit 8) */ + #define R_SDHI0_SD_STOP_SEC_Msk (0x100UL) /*!< SEC (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_STOP_STP_Pos (0UL) /*!< STP (Bit 0) */ + #define R_SDHI0_SD_STOP_STP_Msk (0x1UL) /*!< STP (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_SECCNT ======================================================= */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Pos (0UL) /*!< SD_SECCNT (Bit 0) */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Msk (0xffffffffUL) /*!< SD_SECCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SD_RSP10 ======================================================== */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Pos (0UL) /*!< SD_RSP10 (Bit 0) */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Msk (0xffffffffUL) /*!< SD_RSP10 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP1 ======================================================== */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Pos (0UL) /*!< SD_RSP1 (Bit 0) */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Msk (0xffffUL) /*!< SD_RSP1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP32 ======================================================== */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Pos (0UL) /*!< SD_RSP32 (Bit 0) */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Msk (0xffffffffUL) /*!< SD_RSP32 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP3 ======================================================== */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Pos (0UL) /*!< SD_RSP3 (Bit 0) */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Msk (0xffffUL) /*!< SD_RSP3 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP54 ======================================================== */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Pos (0UL) /*!< SD_RSP54 (Bit 0) */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Msk (0xffffffffUL) /*!< SD_RSP54 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP5 ======================================================== */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Pos (0UL) /*!< SD_RSP5 (Bit 0) */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Msk (0xffffUL) /*!< SD_RSP5 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP76 ======================================================== */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Pos (0UL) /*!< SD_RSP76 (Bit 0) */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Msk (0xffffffUL) /*!< SD_RSP76 (Bitfield-Mask: 0xffffff) */ +/* ======================================================== SD_RSP7 ======================================================== */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Pos (0UL) /*!< SD_RSP7 (Bit 0) */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Msk (0xffUL) /*!< SD_RSP7 (Bitfield-Mask: 0xff) */ +/* ======================================================= SD_INFO1 ======================================================== */ + #define R_SDHI0_SD_INFO1_SDD3MON_Pos (10UL) /*!< SDD3MON (Bit 10) */ + #define R_SDHI0_SD_INFO1_SDD3MON_Msk (0x400UL) /*!< SDD3MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Pos (9UL) /*!< SDD3IN (Bit 9) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Msk (0x200UL) /*!< SDD3IN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Pos (8UL) /*!< SDD3RM (Bit 8) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Msk (0x100UL) /*!< SDD3RM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Pos (7UL) /*!< SDWPMON (Bit 7) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Msk (0x80UL) /*!< SDWPMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Pos (5UL) /*!< SDCDMON (Bit 5) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Msk (0x20UL) /*!< SDCDMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Pos (4UL) /*!< SDCDIN (Bit 4) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Msk (0x10UL) /*!< SDCDIN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Pos (3UL) /*!< SDCDRM (Bit 3) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Msk (0x8UL) /*!< SDCDRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_ACEND_Pos (2UL) /*!< ACEND (Bit 2) */ + #define R_SDHI0_SD_INFO1_ACEND_Msk (0x4UL) /*!< ACEND (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_RSPEND_Pos (0UL) /*!< RSPEND (Bit 0) */ + #define R_SDHI0_SD_INFO1_RSPEND_Msk (0x1UL) /*!< RSPEND (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_INFO2 ======================================================== */ + #define R_SDHI0_SD_INFO2_ILA_Pos (15UL) /*!< ILA (Bit 15) */ + #define R_SDHI0_SD_INFO2_ILA_Msk (0x8000UL) /*!< ILA (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CBSY_Pos (14UL) /*!< CBSY (Bit 14) */ + #define R_SDHI0_SD_INFO2_CBSY_Msk (0x4000UL) /*!< CBSY (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Pos (13UL) /*!< SD_CLK_CTRLEN (Bit 13) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Msk (0x2000UL) /*!< SD_CLK_CTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BWE_Pos (9UL) /*!< BWE (Bit 9) */ + #define R_SDHI0_SD_INFO2_BWE_Msk (0x200UL) /*!< BWE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BRE_Pos (8UL) /*!< BRE (Bit 8) */ + #define R_SDHI0_SD_INFO2_BRE_Msk (0x100UL) /*!< BRE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Pos (7UL) /*!< SDD0MON (Bit 7) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Msk (0x80UL) /*!< SDD0MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_RSPTO_Pos (6UL) /*!< RSPTO (Bit 6) */ + #define R_SDHI0_SD_INFO2_RSPTO_Msk (0x40UL) /*!< RSPTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILR_Pos (5UL) /*!< ILR (Bit 5) */ + #define R_SDHI0_SD_INFO2_ILR_Msk (0x20UL) /*!< ILR (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILW_Pos (4UL) /*!< ILW (Bit 4) */ + #define R_SDHI0_SD_INFO2_ILW_Msk (0x10UL) /*!< ILW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_DTO_Pos (3UL) /*!< DTO (Bit 3) */ + #define R_SDHI0_SD_INFO2_DTO_Msk (0x8UL) /*!< DTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ENDE_Pos (2UL) /*!< ENDE (Bit 2) */ + #define R_SDHI0_SD_INFO2_ENDE_Msk (0x4UL) /*!< ENDE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CRCE_Pos (1UL) /*!< CRCE (Bit 1) */ + #define R_SDHI0_SD_INFO2_CRCE_Msk (0x2UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CMDE_Pos (0UL) /*!< CMDE (Bit 0) */ + #define R_SDHI0_SD_INFO2_CMDE_Msk (0x1UL) /*!< CMDE (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO1_MASK ===================================================== */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Pos (9UL) /*!< SDD3INM (Bit 9) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Msk (0x200UL) /*!< SDD3INM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Pos (8UL) /*!< SDD3RMM (Bit 8) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Msk (0x100UL) /*!< SDD3RMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Pos (4UL) /*!< SDCDINM (Bit 4) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Msk (0x10UL) /*!< SDCDINM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Pos (3UL) /*!< SDCDRMM (Bit 3) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Msk (0x8UL) /*!< SDCDRMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Pos (2UL) /*!< ACENDM (Bit 2) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Msk (0x4UL) /*!< ACENDM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Pos (0UL) /*!< RSPENDM (Bit 0) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Msk (0x1UL) /*!< RSPENDM (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO2_MASK ===================================================== */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Pos (15UL) /*!< ILAM (Bit 15) */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Msk (0x8000UL) /*!< ILAM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Pos (9UL) /*!< BWEM (Bit 9) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Msk (0x200UL) /*!< BWEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Pos (8UL) /*!< BREM (Bit 8) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Msk (0x100UL) /*!< BREM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Pos (6UL) /*!< RSPTOM (Bit 6) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Msk (0x40UL) /*!< RSPTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Pos (5UL) /*!< ILRM (Bit 5) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Msk (0x20UL) /*!< ILRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Pos (4UL) /*!< ILWM (Bit 4) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Msk (0x10UL) /*!< ILWM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Pos (3UL) /*!< DTOM (Bit 3) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Msk (0x8UL) /*!< DTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Pos (2UL) /*!< ENDEM (Bit 2) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Msk (0x4UL) /*!< ENDEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Pos (1UL) /*!< CRCEM (Bit 1) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Msk (0x2UL) /*!< CRCEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Pos (0UL) /*!< CMDEM (Bit 0) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Msk (0x1UL) /*!< CMDEM (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_CLK_CTRL ====================================================== */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Pos (9UL) /*!< CLKCTRLEN (Bit 9) */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Msk (0x200UL) /*!< CLKCTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Pos (8UL) /*!< CLKEN (Bit 8) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Msk (0x100UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Msk (0xffUL) /*!< CLKSEL (Bitfield-Mask: 0xff) */ +/* ======================================================== SD_SIZE ======================================================== */ + #define R_SDHI0_SD_SIZE_LEN_Pos (0UL) /*!< LEN (Bit 0) */ + #define R_SDHI0_SD_SIZE_LEN_Msk (0x3ffUL) /*!< LEN (Bitfield-Mask: 0x3ff) */ +/* ======================================================= SD_OPTION ======================================================= */ + #define R_SDHI0_SD_OPTION_WIDTH_Pos (15UL) /*!< WIDTH (Bit 15) */ + #define R_SDHI0_SD_OPTION_WIDTH_Msk (0x8000UL) /*!< WIDTH (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Pos (13UL) /*!< WIDTH8 (Bit 13) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Msk (0x2000UL) /*!< WIDTH8 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Pos (8UL) /*!< TOUTMASK (Bit 8) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Msk (0x100UL) /*!< TOUTMASK (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOP_Pos (4UL) /*!< TOP (Bit 4) */ + #define R_SDHI0_SD_OPTION_TOP_Msk (0xf0UL) /*!< TOP (Bitfield-Mask: 0x0f) */ + #define R_SDHI0_SD_OPTION_CTOP_Pos (0UL) /*!< CTOP (Bit 0) */ + #define R_SDHI0_SD_OPTION_CTOP_Msk (0xfUL) /*!< CTOP (Bitfield-Mask: 0x0f) */ +/* ====================================================== SD_ERR_STS1 ====================================================== */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Pos (12UL) /*!< CRCTK (Bit 12) */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Msk (0x7000UL) /*!< CRCTK (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Pos (11UL) /*!< CRCTKE (Bit 11) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Msk (0x800UL) /*!< CRCTKE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Pos (10UL) /*!< RDCRCE (Bit 10) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Msk (0x400UL) /*!< RDCRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Pos (9UL) /*!< RSPCRCE1 (Bit 9) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Msk (0x200UL) /*!< RSPCRCE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Pos (8UL) /*!< RSPCRCE0 (Bit 8) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Msk (0x100UL) /*!< RSPCRCE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Pos (5UL) /*!< CRCLENE (Bit 5) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Msk (0x20UL) /*!< CRCLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Pos (4UL) /*!< RDLENE (Bit 4) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Msk (0x10UL) /*!< RDLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Pos (3UL) /*!< RSPLENE1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Msk (0x8UL) /*!< RSPLENE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Pos (2UL) /*!< RSPLENE0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Msk (0x4UL) /*!< RSPLENE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Pos (1UL) /*!< CMDE1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Msk (0x2UL) /*!< CMDE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Pos (0UL) /*!< CMDE0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Msk (0x1UL) /*!< CMDE0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_ERR_STS2 ====================================================== */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Pos (6UL) /*!< CRCBSYTO (Bit 6) */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Msk (0x40UL) /*!< CRCBSYTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Pos (5UL) /*!< CRCTO (Bit 5) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Msk (0x20UL) /*!< CRCTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Pos (4UL) /*!< RDTO (Bit 4) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Msk (0x10UL) /*!< RDTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Pos (3UL) /*!< BSYTO1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Msk (0x8UL) /*!< BSYTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Pos (2UL) /*!< BSYTO0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Msk (0x4UL) /*!< BSYTO0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Pos (1UL) /*!< RSPTO1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Msk (0x2UL) /*!< RSPTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Pos (0UL) /*!< RSPTO0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Msk (0x1UL) /*!< RSPTO0 (Bitfield-Mask: 0x01) */ +/* ======================================================== SD_BUF0 ======================================================== */ + #define R_SDHI0_SD_BUF0_SD_BUF_Pos (0UL) /*!< SD_BUF (Bit 0) */ + #define R_SDHI0_SD_BUF0_SD_BUF_Msk (0xffffffffUL) /*!< SD_BUF (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SDIO_MODE ======================================================= */ + #define R_SDHI0_SDIO_MODE_C52PUB_Pos (9UL) /*!< C52PUB (Bit 9) */ + #define R_SDHI0_SDIO_MODE_C52PUB_Msk (0x200UL) /*!< C52PUB (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_IOABT_Pos (8UL) /*!< IOABT (Bit 8) */ + #define R_SDHI0_SDIO_MODE_IOABT_Msk (0x100UL) /*!< IOABT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Pos (2UL) /*!< RWREQ (Bit 2) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Msk (0x4UL) /*!< RWREQ (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_INTEN_Pos (0UL) /*!< INTEN (Bit 0) */ + #define R_SDHI0_SDIO_MODE_INTEN_Msk (0x1UL) /*!< INTEN (Bitfield-Mask: 0x01) */ +/* ====================================================== SDIO_INFO1 ======================================================= */ + #define R_SDHI0_SDIO_INFO1_EXWT_Pos (15UL) /*!< EXWT (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_EXWT_Msk (0x8000UL) /*!< EXWT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos (14UL) /*!< EXPUB52 (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk (0x4000UL) /*!< EXPUB52 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos (0UL) /*!< IOIRQ (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk (0x1UL) /*!< IOIRQ (Bitfield-Mask: 0x01) */ +/* ==================================================== SDIO_INFO1_MASK ==================================================== */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Pos (15UL) /*!< EXWTM (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Msk (0x8000UL) /*!< EXWTM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Pos (14UL) /*!< EXPUB52M (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Msk (0x4000UL) /*!< EXPUB52M (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Pos (0UL) /*!< IOIRQM (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Msk (0x1UL) /*!< IOIRQM (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_DMAEN ======================================================== */ + #define R_SDHI0_SD_DMAEN_DMAEN_Pos (1UL) /*!< DMAEN (Bit 1) */ + #define R_SDHI0_SD_DMAEN_DMAEN_Msk (0x2UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ +/* ======================================================= SOFT_RST ======================================================== */ + #define R_SDHI0_SOFT_RST_SDRST_Pos (0UL) /*!< SDRST (Bit 0) */ + #define R_SDHI0_SOFT_RST_SDRST_Msk (0x1UL) /*!< SDRST (Bitfield-Mask: 0x01) */ +/* ======================================================= SDIF_MODE ======================================================= */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos (8UL) /*!< NOCHKCR (Bit 8) */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk (0x100UL) /*!< NOCHKCR (Bitfield-Mask: 0x01) */ +/* ======================================================= EXT_SWAP ======================================================== */ + #define R_SDHI0_EXT_SWAP_BRSWP_Pos (7UL) /*!< BRSWP (Bit 7) */ + #define R_SDHI0_EXT_SWAP_BRSWP_Msk (0x80UL) /*!< BRSWP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Pos (6UL) /*!< BWSWP (Bit 6) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Msk (0x40UL) /*!< BWSWP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ + #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ + #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ + #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ + #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ + #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ + #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ + #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ + #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ + #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ + #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ + #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ + #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ + #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ + #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ + #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ + #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ + #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ + #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ + #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ + #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ + #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ + #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ + #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ + #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ + #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPR ========================================================== */ + #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ + #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ + #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ + #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= SRAMPRCR ======================================================== */ + #define R_SRAM_SRAMPRCR_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_SRAM_SRAMPRCR_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR_KW_Pos (8UL) /*!< KW (Bit 8) */ + #define R_SRAM_SRAMPRCR_KW_Msk (0xff00UL) /*!< KW (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMPRCR_NS ====================================================== */ + #define R_SRAM_SRAMPRCR_NS_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_SRAM_SRAMPRCR_NS_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR_NS_KW_Pos (8UL) /*!< KW (Bit 8) */ + #define R_SRAM_SRAMPRCR_NS_KW_Msk (0xff00UL) /*!< KW (Bitfield-Mask: 0xff) */ +/* ======================================================= SRAMWTSC ======================================================== */ + #define R_SRAM_SRAMWTSC_WTEN_Pos (0UL) /*!< WTEN (Bit 0) */ + #define R_SRAM_SRAMWTSC_WTEN_Msk (0x1UL) /*!< WTEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMCR0 ======================================================== */ + #define R_SRAM_SRAMCR0_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_SRAMCR0_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR0_ECCMOD_Pos (2UL) /*!< ECCMOD (Bit 2) */ + #define R_SRAM_SRAMCR0_ECCMOD_Msk (0xcUL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ + #define R_SRAM_SRAMCR0_E1STSEN_Pos (4UL) /*!< E1STSEN (Bit 4) */ + #define R_SRAM_SRAMCR0_E1STSEN_Msk (0x10UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR0_TSTBYP_Pos (7UL) /*!< TSTBYP (Bit 7) */ + #define R_SRAM_SRAMCR0_TSTBYP_Msk (0x80UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMCR1 ======================================================== */ + #define R_SRAM_SRAMCR1_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_SRAMCR1_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR1_ECCMOD_Pos (2UL) /*!< ECCMOD (Bit 2) */ + #define R_SRAM_SRAMCR1_ECCMOD_Msk (0xcUL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ + #define R_SRAM_SRAMCR1_E1STSEN_Pos (4UL) /*!< E1STSEN (Bit 4) */ + #define R_SRAM_SRAMCR1_E1STSEN_Msk (0x10UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR1_TSTBYP_Pos (7UL) /*!< TSTBYP (Bit 7) */ + #define R_SRAM_SRAMCR1_TSTBYP_Msk (0x80UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMCR2 ======================================================== */ + #define R_SRAM_SRAMCR2_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_SRAMCR2_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR2_ECCMOD_Pos (2UL) /*!< ECCMOD (Bit 2) */ + #define R_SRAM_SRAMCR2_ECCMOD_Msk (0xcUL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ + #define R_SRAM_SRAMCR2_E1STSEN_Pos (4UL) /*!< E1STSEN (Bit 4) */ + #define R_SRAM_SRAMCR2_E1STSEN_Msk (0x10UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR2_TSTBYP_Pos (7UL) /*!< TSTBYP (Bit 7) */ + #define R_SRAM_SRAMCR2_TSTBYP_Msk (0x80UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMCR3 ======================================================== */ + #define R_SRAM_SRAMCR3_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_SRAMCR3_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR3_ECCMOD_Pos (2UL) /*!< ECCMOD (Bit 2) */ + #define R_SRAM_SRAMCR3_ECCMOD_Msk (0xcUL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ + #define R_SRAM_SRAMCR3_E1STSEN_Pos (4UL) /*!< E1STSEN (Bit 4) */ + #define R_SRAM_SRAMCR3_E1STSEN_Msk (0x10UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR3_TSTBYP_Pos (7UL) /*!< TSTBYP (Bit 7) */ + #define R_SRAM_SRAMCR3_TSTBYP_Msk (0x80UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ====================================================== SRAMECCRGN0 ====================================================== */ + #define R_SRAM_SRAMECCRGN0_ECCRGN_Pos (0UL) /*!< ECCRGN (Bit 0) */ + #define R_SRAM_SRAMECCRGN0_ECCRGN_Msk (0x7UL) /*!< ECCRGN (Bitfield-Mask: 0x07) */ +/* ====================================================== SRAMECCRGN1 ====================================================== */ + #define R_SRAM_SRAMECCRGN1_ECCRGN_Pos (0UL) /*!< ECCRGN (Bit 0) */ + #define R_SRAM_SRAMECCRGN1_ECCRGN_Msk (0x7UL) /*!< ECCRGN (Bitfield-Mask: 0x07) */ +/* ====================================================== SRAMECCRGN2 ====================================================== */ + #define R_SRAM_SRAMECCRGN2_ECCRGN_Pos (0UL) /*!< ECCRGN (Bit 0) */ + #define R_SRAM_SRAMECCRGN2_ECCRGN_Msk (0x7UL) /*!< ECCRGN (Bitfield-Mask: 0x07) */ +/* ====================================================== SRAMECCRGN3 ====================================================== */ + #define R_SRAM_SRAMECCRGN3_ECCRGN_Pos (0UL) /*!< ECCRGN (Bit 0) */ + #define R_SRAM_SRAMECCRGN3_ECCRGN_Msk (0x7UL) /*!< ECCRGN (Bitfield-Mask: 0x07) */ +/* ======================================================== SRAMESR ======================================================== */ + #define R_SRAM_SRAMESR_ERR0_Pos (0UL) /*!< ERR0 (Bit 0) */ + #define R_SRAM_SRAMESR_ERR0_Msk (0x1UL) /*!< ERR0 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMESR_ERR1_Pos (1UL) /*!< ERR1 (Bit 1) */ + #define R_SRAM_SRAMESR_ERR1_Msk (0x2UL) /*!< ERR1 (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMESCLR ======================================================= */ + #define R_SRAM_SRAMESCLR_CLR0_Pos (0UL) /*!< CLR0 (Bit 0) */ + #define R_SRAM_SRAMESCLR_CLR0_Msk (0x1UL) /*!< CLR0 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMESCLR_CLR1_Pos (1UL) /*!< CLR1 (Bit 1) */ + #define R_SRAM_SRAMESCLR_CLR1_Msk (0x2UL) /*!< CLR1 (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMEAR00 ======================================================= */ + #define R_SRAM_SRAMEAR00_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR00_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRAMEAR10 ======================================================= */ + #define R_SRAM_SRAMEAR10_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR10_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRAMEAR20 ======================================================= */ + #define R_SRAM_SRAMEAR20_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR20_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRAMEAR30 ======================================================= */ + #define R_SRAM_SRAMEAR30_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR30_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRAMEAR01 ======================================================= */ + #define R_SRAM_SRAMEAR01_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR01_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRAMEAR11 ======================================================= */ + #define R_SRAM_SRAMEAR11_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR11_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRAMEAR21 ======================================================= */ + #define R_SRAM_SRAMEAR21_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR21_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRAMEAR31 ======================================================= */ + #define R_SRAM_SRAMEAR31_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR31_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SSICR ========================================================= */ + #define R_SSI0_SSICR_CKS_Pos (30UL) /*!< CKS (Bit 30) */ + #define R_SSI0_SSICR_CKS_Msk (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TUIEN_Pos (29UL) /*!< TUIEN (Bit 29) */ + #define R_SSI0_SSICR_TUIEN_Msk (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TOIEN_Pos (28UL) /*!< TOIEN (Bit 28) */ + #define R_SSI0_SSICR_TOIEN_Msk (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_RUIEN_Pos (27UL) /*!< RUIEN (Bit 27) */ + #define R_SSI0_SSICR_RUIEN_Msk (0x8000000UL) /*!< RUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_ROIEN_Pos (26UL) /*!< ROIEN (Bit 26) */ + #define R_SSI0_SSICR_ROIEN_Msk (0x4000000UL) /*!< ROIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_IIEN_Pos (25UL) /*!< IIEN (Bit 25) */ + #define R_SSI0_SSICR_IIEN_Msk (0x2000000UL) /*!< IIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_FRM_Pos (22UL) /*!< FRM (Bit 22) */ + #define R_SSI0_SSICR_FRM_Msk (0xc00000UL) /*!< FRM (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSICR_DWL_Pos (19UL) /*!< DWL (Bit 19) */ + #define R_SSI0_SSICR_DWL_Msk (0x380000UL) /*!< DWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_SWL_Pos (16UL) /*!< SWL (Bit 16) */ + #define R_SSI0_SSICR_SWL_Msk (0x70000UL) /*!< SWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_MST_Pos (14UL) /*!< MST (Bit 14) */ + #define R_SSI0_SSICR_MST_Msk (0x4000UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_BCKP_Pos (13UL) /*!< BCKP (Bit 13) */ + #define R_SSI0_SSICR_BCKP_Msk (0x2000UL) /*!< BCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_LRCKP_Pos (12UL) /*!< LRCKP (Bit 12) */ + #define R_SSI0_SSICR_LRCKP_Msk (0x1000UL) /*!< LRCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SPDP_Pos (11UL) /*!< SPDP (Bit 11) */ + #define R_SSI0_SSICR_SPDP_Msk (0x800UL) /*!< SPDP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SDTA_Pos (10UL) /*!< SDTA (Bit 10) */ + #define R_SSI0_SSICR_SDTA_Msk (0x400UL) /*!< SDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_PDTA_Pos (9UL) /*!< PDTA (Bit 9) */ + #define R_SSI0_SSICR_PDTA_Msk (0x200UL) /*!< PDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_DEL_Pos (8UL) /*!< DEL (Bit 8) */ + #define R_SSI0_SSICR_DEL_Msk (0x100UL) /*!< DEL (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_CKDV_Pos (4UL) /*!< CKDV (Bit 4) */ + #define R_SSI0_SSICR_CKDV_Msk (0xf0UL) /*!< CKDV (Bitfield-Mask: 0x0f) */ + #define R_SSI0_SSICR_MUEN_Pos (3UL) /*!< MUEN (Bit 3) */ + #define R_SSI0_SSICR_MUEN_Msk (0x8UL) /*!< MUEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TEN_Pos (1UL) /*!< TEN (Bit 1) */ + #define R_SSI0_SSICR_TEN_Msk (0x2UL) /*!< TEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_REN_Pos (0UL) /*!< REN (Bit 0) */ + #define R_SSI0_SSICR_REN_Msk (0x1UL) /*!< REN (Bitfield-Mask: 0x01) */ +/* ========================================================= SSISR ========================================================= */ + #define R_SSI0_SSISR_TUIRQ_Pos (29UL) /*!< TUIRQ (Bit 29) */ + #define R_SSI0_SSISR_TUIRQ_Msk (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TOIRQ_Pos (28UL) /*!< TOIRQ (Bit 28) */ + #define R_SSI0_SSISR_TOIRQ_Msk (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RUIRQ_Pos (27UL) /*!< RUIRQ (Bit 27) */ + #define R_SSI0_SSISR_RUIRQ_Msk (0x8000000UL) /*!< RUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_ROIRQ_Pos (26UL) /*!< ROIRQ (Bit 26) */ + #define R_SSI0_SSISR_ROIRQ_Msk (0x4000000UL) /*!< ROIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IIRQ_Pos (25UL) /*!< IIRQ (Bit 25) */ + #define R_SSI0_SSISR_IIRQ_Msk (0x2000000UL) /*!< IIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TCHNO_Pos (5UL) /*!< TCHNO (Bit 5) */ + #define R_SSI0_SSISR_TCHNO_Msk (0x60UL) /*!< TCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_TSWNO_Pos (4UL) /*!< TSWNO (Bit 4) */ + #define R_SSI0_SSISR_TSWNO_Msk (0x10UL) /*!< TSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RCHNO_Pos (2UL) /*!< RCHNO (Bit 2) */ + #define R_SSI0_SSISR_RCHNO_Msk (0xcUL) /*!< RCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_RSWNO_Pos (1UL) /*!< RSWNO (Bit 1) */ + #define R_SSI0_SSISR_RSWNO_Msk (0x2UL) /*!< RSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IDST_Pos (0UL) /*!< IDST (Bit 0) */ + #define R_SSI0_SSISR_IDST_Msk (0x1UL) /*!< IDST (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFCR ========================================================= */ + #define R_SSI0_SSIFCR_AUCKE_Pos (31UL) /*!< AUCKE (Bit 31) */ + #define R_SSI0_SSIFCR_AUCKE_Msk (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_SSIRST_Pos (16UL) /*!< SSIRST (Bit 16) */ + #define R_SSI0_SSIFCR_SSIRST_Msk (0x10000UL) /*!< SSIRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TTRG_Pos (6UL) /*!< TTRG (Bit 6) */ + #define R_SSI0_SSIFCR_TTRG_Msk (0xc0UL) /*!< TTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_RTRG_Pos (4UL) /*!< RTRG (Bit 4) */ + #define R_SSI0_SSIFCR_RTRG_Msk (0x30UL) /*!< RTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_TIE_Pos (3UL) /*!< TIE (Bit 3) */ + #define R_SSI0_SSIFCR_TIE_Msk (0x8UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RIE_Pos (2UL) /*!< RIE (Bit 2) */ + #define R_SSI0_SSIFCR_RIE_Msk (0x4UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TFRST_Pos (1UL) /*!< TFRST (Bit 1) */ + #define R_SSI0_SSIFCR_TFRST_Msk (0x2UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RFRST_Pos (0UL) /*!< RFRST (Bit 0) */ + #define R_SSI0_SSIFCR_RFRST_Msk (0x1UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_BSW_Pos (11UL) /*!< BSW (Bit 11) */ + #define R_SSI0_SSIFCR_BSW_Msk (0x800UL) /*!< BSW (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFSR ========================================================= */ + #define R_SSI0_SSIFSR_TDC_Pos (24UL) /*!< TDC (Bit 24) */ + #define R_SSI0_SSIFSR_TDC_Msk (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_TDE_Pos (16UL) /*!< TDE (Bit 16) */ + #define R_SSI0_SSIFSR_TDE_Msk (0x10000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFSR_RDC_Pos (8UL) /*!< RDC (Bit 8) */ + #define R_SSI0_SSIFSR_RDC_Msk (0x3f00UL) /*!< RDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_RDF_Pos (0UL) /*!< RDF (Bit 0) */ + #define R_SSI0_SSIFSR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFTDR ======================================================== */ + #define R_SSI0_SSIFTDR_SSIFTDR_Pos (0UL) /*!< SSIFTDR (Bit 0) */ + #define R_SSI0_SSIFTDR_SSIFTDR_Msk (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFTDR16 ======================================================= */ +/* ======================================================= SSIFTDR8 ======================================================== */ +/* ======================================================== SSIFRDR ======================================================== */ + #define R_SSI0_SSIFRDR_SSIFRDR_Pos (0UL) /*!< SSIFRDR (Bit 0) */ + #define R_SSI0_SSIFRDR_SSIFRDR_Msk (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFRDR16 ======================================================= */ +/* ======================================================= SSIFRDR8 ======================================================== */ +/* ======================================================== SSIOFR ========================================================= */ + #define R_SSI0_SSIOFR_BCKASTP_Pos (9UL) /*!< BCKASTP (Bit 9) */ + #define R_SSI0_SSIOFR_BCKASTP_Msk (0x200UL) /*!< BCKASTP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_LRCONT_Pos (8UL) /*!< LRCONT (Bit 8) */ + #define R_SSI0_SSIOFR_LRCONT_Msk (0x100UL) /*!< LRCONT (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_OMOD_Pos (0UL) /*!< OMOD (Bit 0) */ + #define R_SSI0_SSIOFR_OMOD_Msk (0x3UL) /*!< OMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== SSISCR ========================================================= */ + #define R_SSI0_SSISCR_TDES_Pos (8UL) /*!< TDES (Bit 8) */ + #define R_SSI0_SSISCR_TDES_Msk (0x1f00UL) /*!< TDES (Bitfield-Mask: 0x1f) */ + #define R_SSI0_SSISCR_RDFS_Pos (0UL) /*!< RDFS (Bit 0) */ + #define R_SSI0_SSISCR_RDFS_Msk (0x1fUL) /*!< RDFS (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SBYCR ========================================================= */ + #define R_SYSTEM_SBYCR_OPE_Pos (6UL) /*!< OPE (Bit 6) */ + #define R_SYSTEM_SBYCR_OPE_Msk (0x40UL) /*!< OPE (Bitfield-Mask: 0x01) */ +/* ========================================================= SSCR2 ========================================================= */ + #define R_SYSTEM_SSCR2_SS2FSR_Pos (0UL) /*!< SS2FSR (Bit 0) */ + #define R_SYSTEM_SSCR2_SS2FSR_Msk (0x1UL) /*!< SS2FSR (Bitfield-Mask: 0x01) */ +/* ========================================================= MRSCR ========================================================= */ + #define R_SYSTEM_MRSCR_MRSWCF_Pos (0UL) /*!< MRSWCF (Bit 0) */ + #define R_SYSTEM_MRSCR_MRSWCF_Msk (0x1UL) /*!< MRSWCF (Bitfield-Mask: 0x01) */ +/* ========================================================= VSCR ========================================================== */ + #define R_SYSTEM_VSCR_VSCM_Pos (0UL) /*!< VSCM (Bit 0) */ + #define R_SYSTEM_VSCR_VSCM_Msk (0x7UL) /*!< VSCM (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_VSCR_VSCMTSF_Pos (4UL) /*!< VSCMTSF (Bit 4) */ + #define R_SYSTEM_VSCR_VSCMTSF_Msk (0x10UL) /*!< VSCMTSF (Bitfield-Mask: 0x01) */ +/* ======================================================== SRMONR ========================================================= */ + #define R_SYSTEM_SRMONR_MON_Pos (0UL) /*!< MON (Bit 0) */ + #define R_SYSTEM_SRMONR_MON_Msk (0x3UL) /*!< MON (Bitfield-Mask: 0x03) */ +/* ======================================================= SCKDIVCR ======================================================== */ + #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0xfUL) /*!< PCKD (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0xf0UL) /*!< PCKC (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0xf00UL) /*!< PCKB (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0xf000UL) /*!< PCKA (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ + #define R_SYSTEM_SCKDIVCR_BCK_Msk (0xf0000UL) /*!< BCK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_PCKE_Pos (20UL) /*!< PCKE (Bit 20) */ + #define R_SYSTEM_SCKDIVCR_PCKE_Msk (0xf00000UL) /*!< PCKE (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ + #define R_SYSTEM_SCKDIVCR_ICK_Msk (0xf000000UL) /*!< ICK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ + #define R_SYSTEM_SCKDIVCR_FCK_Msk (0xf0000000UL) /*!< FCK (Bitfield-Mask: 0x0f) */ +/* ======================================================= SCKDIVCR2 ======================================================= */ + #define R_SYSTEM_SCKDIVCR2_CPUCK_Pos (0UL) /*!< CPUCK (Bit 0) */ + #define R_SYSTEM_SCKDIVCR2_CPUCK_Msk (0xfUL) /*!< CPUCK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR2_CPUCK1_Pos (4UL) /*!< CPUCK1 (Bit 4) */ + #define R_SYSTEM_SCKDIVCR2_CPUCK1_Msk (0xf0UL) /*!< CPUCK1 (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR2_NPUCK_Pos (8UL) /*!< NPUCK (Bit 8) */ + #define R_SYSTEM_SCKDIVCR2_NPUCK_Msk (0xf00UL) /*!< NPUCK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR2_MRICK_Pos (12UL) /*!< MRICK (Bit 12) */ + #define R_SYSTEM_SCKDIVCR2_MRICK_Msk (0xf000UL) /*!< MRICK (Bitfield-Mask: 0x0f) */ +/* ======================================================== SCKSCR ========================================================= */ + #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ +/* ========================================================= PLLCR ========================================================= */ + #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= BCKCR ========================================================= */ + #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BCKCR_EBCKASEL_Pos (7UL) /*!< EBCKASEL (Bit 7) */ + #define R_SYSTEM_BCKCR_EBCKASEL_Msk (0x80UL) /*!< EBCKASEL (Bitfield-Mask: 0x01) */ +/* ======================================================== MEMWAIT ======================================================== */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCCR ========================================================= */ + #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ + #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR ========================================================= */ + #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ + #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOCOCR ========================================================= */ + #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ + #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR1 ========================================================= */ + #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ + #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR2 ========================================================= */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ +/* ========================================================= OSCSF ========================================================= */ + #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ + #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ + #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ + #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ + #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ +/* ========================================================= CKOCR ========================================================= */ + #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ + #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ + #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ + #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== TRCKCR ========================================================= */ + #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ + #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_TRCKCR_TRCKSEL_Pos (4UL) /*!< TRCKSEL (Bit 4) */ + #define R_SYSTEM_TRCKCR_TRCKSEL_Msk (0x10UL) /*!< TRCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDCR ========================================================= */ + #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ + #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDSR ========================================================= */ + #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ + #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ +/* ======================================================== OSCMONR ======================================================== */ + #define R_SYSTEM_OSCMONR_MOCOMON_Pos (1UL) /*!< MOCOMON (Bit 1) */ + #define R_SYSTEM_OSCMONR_MOCOMON_Msk (0x2UL) /*!< MOCOMON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCMONR_LOCOMON_Pos (2UL) /*!< LOCOMON (Bit 2) */ + #define R_SYSTEM_OSCMONR_LOCOMON_Msk (0x4UL) /*!< LOCOMON (Bitfield-Mask: 0x01) */ +/* ======================================================== PLL2CR ========================================================= */ + #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR2 ======================================================== */ + #define R_SYSTEM_PLLCCR2_PLODIVP_Pos (0UL) /*!< PLODIVP (Bit 0) */ + #define R_SYSTEM_PLLCCR2_PLODIVP_Msk (0xfUL) /*!< PLODIVP (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_PLLCCR2_PLODIVQ_Pos (4UL) /*!< PLODIVQ (Bit 4) */ + #define R_SYSTEM_PLLCCR2_PLODIVQ_Msk (0xf0UL) /*!< PLODIVQ (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_PLLCCR2_PLODIVR_Pos (8UL) /*!< PLODIVR (Bit 8) */ + #define R_SYSTEM_PLLCCR2_PLODIVR_Msk (0xf00UL) /*!< PLODIVR (Bitfield-Mask: 0x0f) */ +/* ========================================================= LPOPT ========================================================= */ + #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */ + #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */ + #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PLL2CCR2 ======================================================== */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos (0UL) /*!< PL2ODIVP (Bit 0) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk (0xfUL) /*!< PL2ODIVP (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos (4UL) /*!< PL2ODIVQ (Bit 4) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk (0xf0UL) /*!< PL2ODIVQ (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos (8UL) /*!< PL2ODIVR (Bit 8) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk (0xf00UL) /*!< PL2ODIVR (Bitfield-Mask: 0x0f) */ +/* ======================================================= SLCDSCKCR ======================================================= */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== EBCKOCR ======================================================== */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCKOCR ======================================================== */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ +/* ====================================================== SCICKDIVCR ======================================================= */ + #define R_SYSTEM_SCICKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_SCICKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== SCICKCR ======================================================== */ + #define R_SYSTEM_SCICKCR_SCICKSEL_Pos (0UL) /*!< SCICKSEL (Bit 0) */ + #define R_SYSTEM_SCICKCR_SCICKSEL_Msk (0xfUL) /*!< SCICKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCICKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_SCICKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SCICKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_SCICKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== SPICKDIVCR ======================================================= */ + #define R_SYSTEM_SPICKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_SPICKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== SPICKCR ======================================================== */ + #define R_SYSTEM_SPICKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SPICKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SPICKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_SPICKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SPICKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_SPICKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCCKDIVCR ======================================================= */ + #define R_SYSTEM_ADCCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_ADCCKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCCKCR ======================================================== */ + #define R_SYSTEM_ADCCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_ADCCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_ADCCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_ADCCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_ADCCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_ADCCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== GPTCKDIVCR ======================================================= */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0xfUL) /*!< GPTCKDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== GPTCKCR ======================================================== */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0xfUL) /*!< GPTCKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== LCDCKDIVCR ======================================================= */ + #define R_SYSTEM_LCDCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_LCDCKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== LCDCKCR ======================================================== */ + #define R_SYSTEM_LCDCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_LCDCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_LCDCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_LCDCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LCDCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_LCDCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= MOCOUTCR ======================================================== */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================= HOCOUTCR ======================================================== */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ +/* ====================================================== USBCKDIVCR ======================================================= */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0xfUL) /*!< USBCKDIV (Bitfield-Mask: 0x0f) */ +/* ====================================================== OCTACKDIVCR ====================================================== */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0xfUL) /*!< OCTACKDIV (Bitfield-Mask: 0x0f) */ +/* ===================================================== CANFDCKDIVCR ====================================================== */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0xfUL) /*!< CANFDCKDIV (Bitfield-Mask: 0x0f) */ +/* ===================================================== USB60CKDIVCR ====================================================== */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0xfUL) /*!< USB60CKDIV (Bitfield-Mask: 0x0f) */ +/* ====================================================== I3CCKDIVCR ======================================================= */ + #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos (0UL) /*!< I3CCKDIV (Bit 0) */ + #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk (0xfUL) /*!< I3CCKDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== USBCKCR ======================================================== */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0xfUL) /*!< USBCKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= OCTACKCR ======================================================== */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0xfUL) /*!< OCTACKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= CANFDCKCR ======================================================= */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0xfUL) /*!< CANFDCKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= USB60CKCR ======================================================= */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== I3CCKCR ======================================================== */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0xfUL) /*!< I3CCKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCSCR ======================================================== */ + #define R_SYSTEM_MOSCSCR_MOSCSOKP_Pos (0UL) /*!< MOSCSOKP (Bit 0) */ + #define R_SYSTEM_MOSCSCR_MOSCSOKP_Msk (0x1UL) /*!< MOSCSOKP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOSCR ======================================================== */ + #define R_SYSTEM_HOCOSCR_HOSCSOKP_Pos (0UL) /*!< HOSCSOKP (Bit 0) */ + #define R_SYSTEM_HOCOSCR_HOSCSOKP_Msk (0x1UL) /*!< HOSCSOKP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOCOSCR ======================================================== */ + #define R_SYSTEM_MOCOSCR_MOCOSOKP_Pos (0UL) /*!< MOCOSOKP (Bit 0) */ + #define R_SYSTEM_MOCOSCR_MOCOSOKP_Msk (0x1UL) /*!< MOCOSOKP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLSTOP ========================================================= */ + #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ +/* ========================================================= PSMCR ========================================================= */ + #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ + #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ +/* ========================================================= OPCCR ========================================================= */ + #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ + #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ +/* ======================================================= MOSCWTCR ======================================================== */ + #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ +/* ======================================================= HOCOWTCR ======================================================== */ + #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ +/* ======================================================== SOPCCR ========================================================= */ + #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ + #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR ========================================================= */ + #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCCR_PLLMULNF_Pos (6UL) /*!< PLLMULNF (Bit 6) */ + #define R_SYSTEM_PLLCCR_PLLMULNF_Msk (0xc0UL) /*!< PLLMULNF (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x1ff00UL) /*!< PLLMUL (Bitfield-Mask: 0x1ff) */ +/* ======================================================== RSTSR1 ========================================================= */ + #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ + #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ + #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CLURF_Pos (4UL) /*!< CLURF (Bit 4) */ + #define R_SYSTEM_RSTSR1_CLURF_Msk (0x10UL) /*!< CLURF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_LM0RF_Pos (5UL) /*!< LM0RF (Bit 5) */ + #define R_SYSTEM_RSTSR1_LM0RF_Msk (0x20UL) /*!< LM0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CMRF_Pos (14UL) /*!< CMRF (Bit 14) */ + #define R_SYSTEM_RSTSR1_CMRF_Msk (0x4000UL) /*!< CMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDT1RF_Pos (17UL) /*!< WDT1RF (Bit 17) */ + #define R_SYSTEM_RSTSR1_WDT1RF_Msk (0x20000UL) /*!< WDT1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CLU1RF_Pos (20UL) /*!< CLU1RF (Bit 20) */ + #define R_SYSTEM_RSTSR1_CLU1RF_Msk (0x100000UL) /*!< CLU1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_LM1RF_Pos (21UL) /*!< LM1RF (Bit 21) */ + #define R_SYSTEM_RSTSR1_LM1RF_Msk (0x200000UL) /*!< LM1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_NWRF_Pos (22UL) /*!< NWRF (Bit 22) */ + #define R_SYSTEM_RSTSR1_NWRF_Msk (0x400000UL) /*!< NWRF (Bitfield-Mask: 0x01) */ +/* ======================================================== PLL2CCR ======================================================== */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CCR_PLL2MULNF_Pos (6UL) /*!< PLL2MULNF (Bit 6) */ + #define R_SYSTEM_PLL2CCR_PLL2MULNF_Msk (0xc0UL) /*!< PLL2MULNF (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x1ff00UL) /*!< PLL2MUL (Bitfield-Mask: 0x1ff) */ +/* ======================================================== SYRACCR ======================================================== */ + #define R_SYSTEM_SYRACCR_BUSY_Pos (0UL) /*!< BUSY (Bit 0) */ + #define R_SYSTEM_SYRACCR_BUSY_Msk (0x1UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +/* ====================================================== USBCKCR_ALT ====================================================== */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= SDADCCKCR ======================================================= */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================= BCKADIVCR ======================================================= */ + #define R_SYSTEM_BCKADIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_BCKADIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ====================================================== ESWCKDIVCR ======================================================= */ + #define R_SYSTEM_ESWCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_ESWCKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ====================================================== ESWPCKDIVCR ====================================================== */ + #define R_SYSTEM_ESWPCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_ESWPCKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ====================================================== ESCCKDIVCR ======================================================= */ + #define R_SYSTEM_ESCCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_ESCCKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ====================================================== ETHPCKDIVCR ====================================================== */ + #define R_SYSTEM_ETHPCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_ETHPCKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCKACR ========================================================= */ + #define R_SYSTEM_BCKACR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_BCKACR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_BCKACR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_BCKACR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BCKACR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_BCKACR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== ESWCKCR ======================================================== */ + #define R_SYSTEM_ESWCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_ESWCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_ESWCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_ESWCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_ESWCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_ESWCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= ESWPCKCR ======================================================== */ + #define R_SYSTEM_ESWPCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_ESWPCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_ESWPCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_ESWPCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_ESWPCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_ESWPCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== ESCCKCR ======================================================== */ + #define R_SYSTEM_ESCCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_ESCCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_ESCCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_ESCCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_ESCCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_ESCCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= ETHPCKCR ======================================================== */ + #define R_SYSTEM_ETHPCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_ETHPCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_ETHPCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_ETHPCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_ETHPCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_ETHPCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR1 ======================================================== */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR1 ======================================================== */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD3CR1 ======================================================== */ + #define R_SYSTEM_LVD3CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD3CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD3CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD3CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD4CR1 ======================================================== */ + #define R_SYSTEM_LVD4CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD4CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD4CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD4CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD5CR1 ======================================================== */ + #define R_SYSTEM_LVD5CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD5CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD5CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD5CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1SR ========================================================= */ + #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2SR ========================================================= */ + #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD3SR ========================================================= */ + #define R_SYSTEM_LVD3SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD3SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD3SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD3SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ +/* ======================================================= CRVSYSCR ======================================================== */ + #define R_SYSTEM_CRVSYSCR_CRVEN_Pos (0UL) /*!< CRVEN (Bit 0) */ + #define R_SYSTEM_CRVSYSCR_CRVEN_Msk (0x1UL) /*!< CRVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== CPUDSCR ======================================================== */ + #define R_SYSTEM_CPUDSCR_PGD_Pos (0UL) /*!< PGD (Bit 0) */ + #define R_SYSTEM_CPUDSCR_PGD_Msk (0x1UL) /*!< PGD (Bitfield-Mask: 0x01) */ +/* ======================================================== PDCTRGD ======================================================== */ + #define R_SYSTEM_PDCTRGD_PDDE_Pos (0UL) /*!< PDDE (Bit 0) */ + #define R_SYSTEM_PDCTRGD_PDDE_Msk (0x1UL) /*!< PDDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PDCTRGD_PDCSF_Pos (6UL) /*!< PDCSF (Bit 6) */ + #define R_SYSTEM_PDCTRGD_PDCSF_Msk (0x40UL) /*!< PDCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PDCTRGD_PDPGSF_Pos (7UL) /*!< PDPGSF (Bit 7) */ + #define R_SYSTEM_PDCTRGD_PDPGSF_Msk (0x80UL) /*!< PDPGSF (Bitfield-Mask: 0x01) */ +/* ======================================================= PDCTRNPU ======================================================== */ + #define R_SYSTEM_PDCTRNPU_PDDE_Pos (0UL) /*!< PDDE (Bit 0) */ + #define R_SYSTEM_PDCTRNPU_PDDE_Msk (0x1UL) /*!< PDDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PDCTRNPU_PDCSF_Pos (6UL) /*!< PDCSF (Bit 6) */ + #define R_SYSTEM_PDCTRNPU_PDCSF_Msk (0x40UL) /*!< PDCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PDCTRNPU_PDPGSF_Pos (7UL) /*!< PDPGSF (Bit 7) */ + #define R_SYSTEM_PDCTRNPU_PDPGSF_Msk (0x80UL) /*!< PDPGSF (Bitfield-Mask: 0x01) */ +/* ======================================================= PDCTRESWM ======================================================= */ + #define R_SYSTEM_PDCTRESWM_PDDE_Pos (0UL) /*!< PDDE (Bit 0) */ + #define R_SYSTEM_PDCTRESWM_PDDE_Msk (0x1UL) /*!< PDDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PDCTRESWM_PDCSF_Pos (6UL) /*!< PDCSF (Bit 6) */ + #define R_SYSTEM_PDCTRESWM_PDCSF_Msk (0x40UL) /*!< PDCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PDCTRESWM_PDPGSF_Pos (7UL) /*!< PDPGSF (Bit 7) */ + #define R_SYSTEM_PDCTRESWM_PDPGSF_Msk (0x80UL) /*!< PDPGSF (Bitfield-Mask: 0x01) */ +/* ======================================================= PDRAMSCR0 ======================================================= */ + #define R_SYSTEM_PDRAMSCR0_RKEEP_Pos (0UL) /*!< RKEEP (Bit 0) */ + #define R_SYSTEM_PDRAMSCR0_RKEEP_Msk (0x1UL) /*!< RKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================= PDRAMSCR1 ======================================================= */ + #define R_SYSTEM_PDRAMSCR1_RKEEP_Pos (0UL) /*!< RKEEP (Bit 0) */ + #define R_SYSTEM_PDRAMSCR1_RKEEP_Msk (0x1UL) /*!< RKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================= VBRSABAR ======================================================== */ + #define R_SYSTEM_VBRSABAR_SABA_Pos (0UL) /*!< SABA (Bit 0) */ + #define R_SYSTEM_VBRSABAR_SABA_Msk (0xffffUL) /*!< SABA (Bitfield-Mask: 0xffff) */ +/* ======================================================= VBRPABARS ======================================================= */ + #define R_SYSTEM_VBRPABARS_PABAS_Pos (0UL) /*!< PABAS (Bit 0) */ + #define R_SYSTEM_VBRPABARS_PABAS_Msk (0xffffUL) /*!< PABAS (Bitfield-Mask: 0xffff) */ +/* ====================================================== VBRPABARNS ======================================================= */ + #define R_SYSTEM_VBRPABARNS_PABANS_Pos (0UL) /*!< PABANS (Bit 0) */ + #define R_SYSTEM_VBRPABARNS_PABANS_Msk (0xffffUL) /*!< PABANS (Bitfield-Mask: 0xffff) */ +/* ======================================================== CGFSAR ========================================================= */ + #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ + #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSAR ========================================================= */ + #define R_SYSTEM_RSTSAR_NONSEC_Pos (0UL) /*!< NONSEC (Bit 0) */ + #define R_SYSTEM_RSTSAR_NONSEC_Msk (0x1UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ +/* ======================================================== LPMSAR ========================================================= */ + #define R_SYSTEM_LPMSAR_NONSEC_Pos (0UL) /*!< NONSEC (Bit 0) */ + #define R_SYSTEM_LPMSAR_NONSEC_Msk (0x1UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDSAR ========================================================= */ + #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== BBFSAR ========================================================= */ + #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC3_Pos (3UL) /*!< NONSEC3 (Bit 3) */ + #define R_SYSTEM_BBFSAR_NONSEC3_Msk (0x8UL) /*!< NONSEC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ + #define R_SYSTEM_BBFSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC5_Pos (5UL) /*!< NONSEC5 (Bit 5) */ + #define R_SYSTEM_BBFSAR_NONSEC5_Msk (0x20UL) /*!< NONSEC5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC6_Pos (6UL) /*!< NONSEC6 (Bit 6) */ + #define R_SYSTEM_BBFSAR_NONSEC6_Msk (0x40UL) /*!< NONSEC6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC7_Pos (7UL) /*!< NONSEC7 (Bit 7) */ + #define R_SYSTEM_BBFSAR_NONSEC7_Msk (0x80UL) /*!< NONSEC7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ + #define R_SYSTEM_BBFSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ +/* ======================================================== PGCSAR ========================================================= */ + #define R_SYSTEM_PGCSAR_NONSEC_Pos (0UL) /*!< NONSEC (Bit 0) */ + #define R_SYSTEM_PGCSAR_NONSEC_Msk (0x1UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR ========================================================= */ + #define R_SYSTEM_DPFSAR_DPFSA_Pos (0UL) /*!< DPFSA (Bit 0) */ + #define R_SYSTEM_DPFSAR_DPFSA_Msk (0x1UL) /*!< DPFSA (Bitfield-Mask: 0x01) */ +/* ======================================================== RSCSAR ========================================================= */ + #define R_SYSTEM_RSCSAR_RSCSA_Pos (0UL) /*!< RSCSA (Bit 0) */ + #define R_SYSTEM_RSCSAR_RSCSA_Msk (0x1UL) /*!< RSCSA (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR1 ======================================================== */ + #define R_SYSTEM_DPFSAR1_DPFSA_Pos (0UL) /*!< DPFSA (Bit 0) */ + #define R_SYSTEM_DPFSAR1_DPFSA_Msk (0x1UL) /*!< DPFSA (Bitfield-Mask: 0x01) */ +/* ========================================================= PRCR ========================================================== */ + #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC5_Pos (5UL) /*!< PRC5 (Bit 5) */ + #define R_SYSTEM_PRCR_PRC5_Msk (0x20UL) /*!< PRC5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== PRCR_NS ======================================================== */ + #define R_SYSTEM_PRCR_NS_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_NS_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_NS_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_NS_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_NS_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_NS_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_NS_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_NS_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_NS_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_NS_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= LOCOUTCR ======================================================== */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================== STCONR ========================================================= */ + #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ + #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ +/* ======================================================== FWEPROR ======================================================== */ + #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ + #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ +/* ======================================================= VBATTMONR ======================================================= */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTCR1 ========================================================= */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== DCDCCTL ======================================================== */ + #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ + #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ + #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ +/* ======================================================== VCCSEL ========================================================= */ + #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ + #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SOMRG ========================================================= */ + #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ + #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ +/* ======================================================== VBTCR2 ========================================================= */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ +/* ========================================================= VBTSR ========================================================= */ + #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ + #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTCMPCR ======================================================== */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTLVDICR ======================================================= */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTWCTLR ======================================================== */ + #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ + #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH0OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH1OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH2OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTOCTLR ======================================================== */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWTER ======================================================== */ + #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ + #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ + #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ + #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWEGR ======================================================== */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWFR ========================================================= */ + #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ + #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ + #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ + #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSBYCR ======================================================== */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_DPSBYCR_DCSSMODE_Pos (2UL) /*!< DCSSMODE (Bit 2) */ + #define R_SYSTEM_DPSBYCR_DCSSMODE_Msk (0xcUL) /*!< DCSSMODE (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER0 ======================================================== */ + #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER1 ======================================================== */ + #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER2 ======================================================== */ + #define R_SYSTEM_DPSIER2_DPVD1IE_Pos (0UL) /*!< DPVD1IE (Bit 0) */ + #define R_SYSTEM_DPSIER2_DPVD1IE_Msk (0x1UL) /*!< DPVD1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DPVD2IE_Pos (1UL) /*!< DPVD2IE (Bit 1) */ + #define R_SYSTEM_DPSIER2_DPVD2IE_Msk (0x2UL) /*!< DPVD2IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCIIE_Pos (2UL) /*!< DRTCIIE (Bit 2) */ + #define R_SYSTEM_DPSIER2_DRTCIIE_Msk (0x4UL) /*!< DRTCIIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ + #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DPVD3IE_Pos (5UL) /*!< DPVD3IE (Bit 5) */ + #define R_SYSTEM_DPSIER2_DPVD3IE_Msk (0x20UL) /*!< DPVD3IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER3 ======================================================== */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DULPT0IE_Pos (2UL) /*!< DULPT0IE (Bit 2) */ + #define R_SYSTEM_DPSIER3_DULPT0IE_Msk (0x4UL) /*!< DULPT0IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DULPT1IE_Pos (3UL) /*!< DULPT1IE (Bit 3) */ + #define R_SYSTEM_DPSIER3_DULPT1IE_Msk (0x8UL) /*!< DULPT1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DIWDTIE_Pos (5UL) /*!< DIWDTIE (Bit 5) */ + #define R_SYSTEM_DPSIER3_DIWDTIE_Msk (0x20UL) /*!< DIWDTIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DSOSTDIE_Pos (6UL) /*!< DSOSTDIE (Bit 6) */ + #define R_SYSTEM_DPSIER3_DSOSTDIE_Msk (0x40UL) /*!< DSOSTDIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DVBATTADIE_Pos (7UL) /*!< DVBATTADIE (Bit 7) */ + #define R_SYSTEM_DPSIER3_DVBATTADIE_Msk (0x80UL) /*!< DVBATTADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR0 ======================================================== */ + #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR1 ======================================================== */ + #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR2 ======================================================== */ + #define R_SYSTEM_DPSIFR2_DPVD1IF_Pos (0UL) /*!< DPVD1IF (Bit 0) */ + #define R_SYSTEM_DPSIFR2_DPVD1IF_Msk (0x1UL) /*!< DPVD1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DPVD2IF_Pos (1UL) /*!< DPVD2IF (Bit 1) */ + #define R_SYSTEM_DPSIFR2_DPVD2IF_Msk (0x2UL) /*!< DPVD2IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCIIF_Pos (2UL) /*!< DRTCIIF (Bit 2) */ + #define R_SYSTEM_DPSIFR2_DRTCIIF_Msk (0x4UL) /*!< DRTCIIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DPVD3IF_Pos (5UL) /*!< DPVD3IF (Bit 5) */ + #define R_SYSTEM_DPSIFR2_DPVD3IF_Msk (0x20UL) /*!< DPVD3IF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR3 ======================================================== */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DULPT0IF_Pos (2UL) /*!< DULPT0IF (Bit 2) */ + #define R_SYSTEM_DPSIFR3_DULPT0IF_Msk (0x4UL) /*!< DULPT0IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DULPT1IF_Pos (3UL) /*!< DULPT1IF (Bit 3) */ + #define R_SYSTEM_DPSIFR3_DULPT1IF_Msk (0x8UL) /*!< DULPT1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DIWDTIF_Pos (5UL) /*!< DIWDTIF (Bit 5) */ + #define R_SYSTEM_DPSIFR3_DIWDTIF_Msk (0x20UL) /*!< DIWDTIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DSOSTDIF_Pos (6UL) /*!< DSOSTDIF (Bit 6) */ + #define R_SYSTEM_DPSIFR3_DSOSTDIF_Msk (0x40UL) /*!< DSOSTDIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DVBATTADIF_Pos (7UL) /*!< DVBATTADIF (Bit 7) */ + #define R_SYSTEM_DPSIFR3_DVBATTADIF_Msk (0x80UL) /*!< DVBATTADIF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR0 ======================================================== */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR1 ======================================================== */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR2 ======================================================== */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD3IEG_Pos (5UL) /*!< DLVD3IEG (Bit 5) */ + #define R_SYSTEM_DPSIEGR2_DLVD3IEG_Msk (0x20UL) /*!< DLVD3IEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR3 ======================================================== */ + #define R_SYSTEM_DPSIEGR3_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR3_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================== SYOCDCR ======================================================== */ + #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ + #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD4RF_Pos (5UL) /*!< LVD4RF (Bit 5) */ + #define R_SYSTEM_RSTSR0_LVD4RF_Msk (0x20UL) /*!< LVD4RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD5RF_Pos (6UL) /*!< LVD5RF (Bit 6) */ + #define R_SYSTEM_RSTSR0_LVD5RF_Msk (0x40UL) /*!< LVD5RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR2 ========================================================= */ + #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ + #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR3 ========================================================= */ + #define R_SYSTEM_RSTSR3_CVMRF_Pos (0UL) /*!< CVMRF (Bit 0) */ + #define R_SYSTEM_RSTSR3_CVMRF_Msk (0x1UL) /*!< CVMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR3_OCPRF_Pos (4UL) /*!< OCPRF (Bit 4) */ + #define R_SYSTEM_RSTSR3_OCPRF_Msk (0x10UL) /*!< OCPRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR3_TEMPRF_Pos (7UL) /*!< TEMPRF (Bit 7) */ + #define R_SYSTEM_RSTSR3_TEMPRF_Msk (0x80UL) /*!< TEMPRF (Bitfield-Mask: 0x01) */ +/* ========================================================= MOMCR ========================================================= */ + #define R_SYSTEM_MOMCR_MODRV0_Pos (1UL) /*!< MODRV0 (Bit 1) */ + #define R_SYSTEM_MOMCR_MODRV0_Msk (0xeUL) /*!< MODRV0 (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ + #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD1CMPCR ======================================================= */ + #define R_SYSTEM_LVD1CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD1CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD1CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD1CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD2CMPCR ======================================================= */ + #define R_SYSTEM_LVD2CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD2CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD2CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD2CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD3CMPCR ======================================================= */ + #define R_SYSTEM_LVD3CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD3CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD3CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD3CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD4CMPCR ======================================================= */ + #define R_SYSTEM_LVD4CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD4CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD4CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD4CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD5CMPCR ======================================================= */ + #define R_SYSTEM_LVD5CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD5CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD5CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD5CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR0 ======================================================== */ + #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR0 ======================================================== */ + #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD3CR0 ======================================================== */ + #define R_SYSTEM_LVD3CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD3CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD3CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD3CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD3CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD3CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD3CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD3CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD3CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD3CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD3CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD3CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD4CR0 ======================================================== */ + #define R_SYSTEM_LVD4CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD4CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD4CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD4CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD4CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD4CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD4CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD4CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD4CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD4CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD4CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD4CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD5CR0 ======================================================== */ + #define R_SYSTEM_LVD5CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD5CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD5CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD5CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD5CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD5CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD5CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD5CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD5CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD5CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD5CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD5CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBATTMNSELR ====================================================== */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTBPCR1 ======================================================== */ + #define R_SYSTEM_VBTBPCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTBPCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSCR ========================================================= */ + #define R_SYSTEM_LPSCR_LPMD_Pos (0UL) /*!< LPMD (Bit 0) */ + #define R_SYSTEM_LPSCR_LPMD_Msk (0xfUL) /*!< LPMD (Bitfield-Mask: 0x0f) */ +/* ========================================================= SSCR1 ========================================================= */ + #define R_SYSTEM_SSCR1_SS2FR_Pos (0UL) /*!< SS2FR (Bit 0) */ + #define R_SYSTEM_SSCR1_SS2FR_Msk (0x1UL) /*!< SS2FR (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SSCR1_SS2LP_Pos (2UL) /*!< SS2LP (Bit 2) */ + #define R_SYSTEM_SSCR1_SS2LP_Msk (0xcUL) /*!< SS2LP (Bitfield-Mask: 0x03) */ +/* ========================================================= SVSCR ========================================================= */ + #define R_SYSTEM_SVSCR_SVSCM_Pos (0UL) /*!< SVSCM (Bit 0) */ + #define R_SYSTEM_SVSCR_SVSCM_Msk (0x7UL) /*!< SVSCM (Bitfield-Mask: 0x07) */ +/* ========================================================= LVOCR ========================================================= */ + #define R_SYSTEM_LVOCR_LVO0E_Pos (0UL) /*!< LVO0E (Bit 0) */ + #define R_SYSTEM_LVOCR_LVO0E_Msk (0x1UL) /*!< LVO0E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVOCR_LVO1E_Pos (1UL) /*!< LVO1E (Bit 1) */ + #define R_SYSTEM_LVOCR_LVO1E_Msk (0x2UL) /*!< LVO1E (Bitfield-Mask: 0x01) */ +/* ========================================================= MWMCR ========================================================= */ + #define R_SYSTEM_MWMCR_MWM_Pos (0UL) /*!< MWM (Bit 0) */ + #define R_SYSTEM_MWMCR_MWM_Msk (0x3UL) /*!< MWM (Bitfield-Mask: 0x03) */ +/* ======================================================= SYRSTMSK0 ======================================================= */ + #define R_SYSTEM_SYRSTMSK0_IWDTMASK_Pos (0UL) /*!< IWDTMASK (Bit 0) */ + #define R_SYSTEM_SYRSTMSK0_IWDTMASK_Msk (0x1UL) /*!< IWDTMASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_WDT0MASK_Pos (1UL) /*!< WDT0MASK (Bit 1) */ + #define R_SYSTEM_SYRSTMSK0_WDT0MASK_Msk (0x2UL) /*!< WDT0MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_SWMASK_Pos (2UL) /*!< SWMASK (Bit 2) */ + #define R_SYSTEM_SYRSTMSK0_SWMASK_Msk (0x4UL) /*!< SWMASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_CLU0MASK_Pos (4UL) /*!< CLU0MASK (Bit 4) */ + #define R_SYSTEM_SYRSTMSK0_CLU0MASK_Msk (0x10UL) /*!< CLU0MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_LM0MASK_Pos (5UL) /*!< LM0MASK (Bit 5) */ + #define R_SYSTEM_SYRSTMSK0_LM0MASK_Msk (0x20UL) /*!< LM0MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_CMMASK_Pos (6UL) /*!< CMMASK (Bit 6) */ + #define R_SYSTEM_SYRSTMSK0_CMMASK_Msk (0x40UL) /*!< CMMASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_BUSMASK_Pos (7UL) /*!< BUSMASK (Bit 7) */ + #define R_SYSTEM_SYRSTMSK0_BUSMASK_Msk (0x80UL) /*!< BUSMASK (Bitfield-Mask: 0x01) */ +/* ======================================================= SYRSTMSK1 ======================================================= */ + #define R_SYSTEM_SYRSTMSK1_WDT1MASK_Pos (1UL) /*!< WDT1MASK (Bit 1) */ + #define R_SYSTEM_SYRSTMSK1_WDT1MASK_Msk (0x2UL) /*!< WDT1MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK1_CLU1MASK_Pos (4UL) /*!< CLU1MASK (Bit 4) */ + #define R_SYSTEM_SYRSTMSK1_CLU1MASK_Msk (0x10UL) /*!< CLU1MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK1_LM1MASK_Pos (5UL) /*!< LM1MASK (Bit 5) */ + #define R_SYSTEM_SYRSTMSK1_LM1MASK_Msk (0x20UL) /*!< LM1MASK (Bitfield-Mask: 0x01) */ +/* ======================================================= SYRSTMSK2 ======================================================= */ + #define R_SYSTEM_SYRSTMSK2_PVD1MASK_Pos (0UL) /*!< PVD1MASK (Bit 0) */ + #define R_SYSTEM_SYRSTMSK2_PVD1MASK_Msk (0x1UL) /*!< PVD1MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK2_PVD2MASK_Pos (1UL) /*!< PVD2MASK (Bit 1) */ + #define R_SYSTEM_SYRSTMSK2_PVD2MASK_Msk (0x2UL) /*!< PVD2MASK (Bitfield-Mask: 0x01) */ +/* ======================================================== TEMPRCR ======================================================== */ + #define R_SYSTEM_TEMPRCR_TEMPREN_Pos (0UL) /*!< TEMPREN (Bit 0) */ + #define R_SYSTEM_TEMPRCR_TEMPREN_Msk (0x1UL) /*!< TEMPREN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TEMPRCR_TSNEN_Pos (1UL) /*!< TSNEN (Bit 1) */ + #define R_SYSTEM_TEMPRCR_TSNEN_Msk (0x2UL) /*!< TSNEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TEMPRCR_CMPEN_Pos (2UL) /*!< CMPEN (Bit 2) */ + #define R_SYSTEM_TEMPRCR_CMPEN_Msk (0x4UL) /*!< CMPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TEMPRCR_TSNKEEP_Pos (3UL) /*!< TSNKEEP (Bit 3) */ + #define R_SYSTEM_TEMPRCR_TSNKEEP_Msk (0x8UL) /*!< TSNKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================== TEMPRLR ======================================================== */ + #define R_SYSTEM_TEMPRLR_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ + #define R_SYSTEM_TEMPRLR_LOCK_Msk (0x1UL) /*!< LOCK (Bitfield-Mask: 0x01) */ +/* ======================================================== LDOSCR ========================================================= */ + #define R_SYSTEM_LDOSCR_LDOSTP_Pos (0UL) /*!< LDOSTP (Bit 0) */ + #define R_SYSTEM_LDOSCR_LDOSTP_Msk (0x1UL) /*!< LDOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= PLL1LDOCR ======================================================= */ + #define R_SYSTEM_PLL1LDOCR_LDOSTP_Pos (0UL) /*!< LDOSTP (Bit 0) */ + #define R_SYSTEM_PLL1LDOCR_LDOSTP_Msk (0x1UL) /*!< LDOSTP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL1LDOCR_SKEEP_Pos (1UL) /*!< SKEEP (Bit 1) */ + #define R_SYSTEM_PLL1LDOCR_SKEEP_Msk (0x2UL) /*!< SKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================= PLL2LDOCR ======================================================= */ + #define R_SYSTEM_PLL2LDOCR_LDOSTP_Pos (0UL) /*!< LDOSTP (Bit 0) */ + #define R_SYSTEM_PLL2LDOCR_LDOSTP_Msk (0x1UL) /*!< LDOSTP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2LDOCR_SKEEP_Pos (1UL) /*!< SKEEP (Bit 1) */ + #define R_SYSTEM_PLL2LDOCR_SKEEP_Msk (0x2UL) /*!< SKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================= HOCOLDOCR ======================================================= */ + #define R_SYSTEM_HOCOLDOCR_LDOSTP_Pos (0UL) /*!< LDOSTP (Bit 0) */ + #define R_SYSTEM_HOCOLDOCR_LDOSTP_Msk (0x1UL) /*!< LDOSTP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_HOCOLDOCR_SKEEP_Pos (1UL) /*!< SKEEP (Bit 1) */ + #define R_SYSTEM_HOCOLDOCR_SKEEP_Msk (0x2UL) /*!< SKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOMCR2 ========================================================= */ + #define R_SYSTEM_MOMCR2_MOMODE_Pos (0UL) /*!< MOMODE (Bit 0) */ + #define R_SYSTEM_MOMCR2_MOMODE_Msk (0x1UL) /*!< MOMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1FCR ======================================================== */ + #define R_SYSTEM_LVD1FCR_RHSEL_Pos (0UL) /*!< RHSEL (Bit 0) */ + #define R_SYSTEM_LVD1FCR_RHSEL_Msk (0x1UL) /*!< RHSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2FCR ======================================================== */ + #define R_SYSTEM_LVD2FCR_RHSEL_Pos (0UL) /*!< RHSEL (Bit 0) */ + #define R_SYSTEM_LVD2FCR_RHSEL_Msk (0x1UL) /*!< RHSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD3FCR ======================================================== */ + #define R_SYSTEM_LVD3FCR_RHSEL_Pos (0UL) /*!< RHSEL (Bit 0) */ + #define R_SYSTEM_LVD3FCR_RHSEL_Msk (0x1UL) /*!< RHSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD4FCR ======================================================== */ + #define R_SYSTEM_LVD4FCR_RHSEL_Pos (0UL) /*!< RHSEL (Bit 0) */ + #define R_SYSTEM_LVD4FCR_RHSEL_Msk (0x1UL) /*!< RHSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD5FCR ======================================================== */ + #define R_SYSTEM_LVD5FCR_RHSEL_Pos (0UL) /*!< RHSEL (Bit 0) */ + #define R_SYSTEM_LVD5FCR_RHSEL_Msk (0x1UL) /*!< RHSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= PVDLR ========================================================= */ + #define R_SYSTEM_PVDLR_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ + #define R_SYSTEM_PVDLR_LOCK_Msk (0x1UL) /*!< LOCK (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER4 ======================================================== */ + #define R_SYSTEM_DPSIER4_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER4_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER5 ======================================================== */ + #define R_SYSTEM_DPSIER5_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER5_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR4 ======================================================== */ + #define R_SYSTEM_DPSIFR4_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR4_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR5 ======================================================== */ + #define R_SYSTEM_DPSIFR5_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR5_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR4 ======================================================== */ + #define R_SYSTEM_DPSIEGR4_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR4_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTSWMON ======================================================== */ + #define R_SYSTEM_VBTSWMON_VLVLMON_Pos (0UL) /*!< VLVLMON (Bit 0) */ + #define R_SYSTEM_VBTSWMON_VLVLMON_Msk (0x7UL) /*!< VLVLMON (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_VBTSWMON_VDETEMON_Pos (4UL) /*!< VDETEMON (Bit 4) */ + #define R_SYSTEM_VBTSWMON_VDETEMON_Msk (0x10UL) /*!< VDETEMON (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTSWSCR ======================================================== */ + #define R_SYSTEM_VBTSWSCR_VBTSWE_Pos (0UL) /*!< VBTSWE (Bit 0) */ + #define R_SYSTEM_VBTSWSCR_VBTSWE_Msk (0x1UL) /*!< VBTSWE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSCCR ========================================================= */ + #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ + #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= SOMCR ========================================================= */ + #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ + #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_SOMCR_SOSEL_Pos (6UL) /*!< SOSEL (Bit 6) */ + #define R_SYSTEM_SOMCR_SOSEL_Msk (0x40UL) /*!< SOSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSTDCR ======================================================== */ + #define R_SYSTEM_SOSTDCR_SOSTDIE_Pos (0UL) /*!< SOSTDIE (Bit 0) */ + #define R_SYSTEM_SOSTDCR_SOSTDIE_Msk (0x1UL) /*!< SOSTDIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOSTDCR_SOSTDE_Pos (7UL) /*!< SOSTDE (Bit 7) */ + #define R_SYSTEM_SOSTDCR_SOSTDE_Msk (0x80UL) /*!< SOSTDE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSTDSR ======================================================== */ + #define R_SYSTEM_SOSTDSR_SOSTDF_Pos (0UL) /*!< SOSTDF (Bit 0) */ + #define R_SYSTEM_SOSTDSR_SOSTDF_Msk (0x1UL) /*!< SOSTDF (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBER ========================================================= */ + #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ + #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTBPCR2 ======================================================== */ + #define R_SYSTEM_VBTBPCR2_VDETLVL_Pos (0UL) /*!< VDETLVL (Bit 0) */ + #define R_SYSTEM_VBTBPCR2_VDETLVL_Msk (0x7UL) /*!< VDETLVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_VBTBPCR2_VDETE_Pos (4UL) /*!< VDETE (Bit 4) */ + #define R_SYSTEM_VBTBPCR2_VDETE_Msk (0x10UL) /*!< VDETE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBPSR ======================================================== */ + #define R_SYSTEM_VBTBPSR_VBPORF_Pos (0UL) /*!< VBPORF (Bit 0) */ + #define R_SYSTEM_VBTBPSR_VBPORF_Msk (0x1UL) /*!< VBPORF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTBPSR_VBPORM_Pos (4UL) /*!< VBPORM (Bit 4) */ + #define R_SYSTEM_VBTBPSR_VBPORM_Msk (0x10UL) /*!< VBPORM (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTBPSR_BPWSWM_Pos (5UL) /*!< BPWSWM (Bit 5) */ + #define R_SYSTEM_VBTBPSR_BPWSWM_Msk (0x20UL) /*!< BPWSWM (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTADSR ======================================================== */ + #define R_SYSTEM_VBTADSR_VBTADF0_Pos (0UL) /*!< VBTADF0 (Bit 0) */ + #define R_SYSTEM_VBTADSR_VBTADF0_Msk (0x1UL) /*!< VBTADF0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADSR_VBTADF1_Pos (1UL) /*!< VBTADF1 (Bit 1) */ + #define R_SYSTEM_VBTADSR_VBTADF1_Msk (0x2UL) /*!< VBTADF1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADSR_VBTADF2_Pos (2UL) /*!< VBTADF2 (Bit 2) */ + #define R_SYSTEM_VBTADSR_VBTADF2_Msk (0x4UL) /*!< VBTADF2 (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTADCR1 ======================================================== */ + #define R_SYSTEM_VBTADCR1_VBTADIE0_Pos (0UL) /*!< VBTADIE0 (Bit 0) */ + #define R_SYSTEM_VBTADCR1_VBTADIE0_Msk (0x1UL) /*!< VBTADIE0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADIE1_Pos (1UL) /*!< VBTADIE1 (Bit 1) */ + #define R_SYSTEM_VBTADCR1_VBTADIE1_Msk (0x2UL) /*!< VBTADIE1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADIE2_Pos (2UL) /*!< VBTADIE2 (Bit 2) */ + #define R_SYSTEM_VBTADCR1_VBTADIE2_Msk (0x4UL) /*!< VBTADIE2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE0_Pos (4UL) /*!< VBTADCLE0 (Bit 4) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE0_Msk (0x10UL) /*!< VBTADCLE0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE1_Pos (5UL) /*!< VBTADCLE1 (Bit 5) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE1_Msk (0x20UL) /*!< VBTADCLE1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE2_Pos (6UL) /*!< VBTADCLE2 (Bit 6) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE2_Msk (0x40UL) /*!< VBTADCLE2 (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTADCR2 ======================================================== */ + #define R_SYSTEM_VBTADCR2_VBRTCES0_Pos (0UL) /*!< VBRTCES0 (Bit 0) */ + #define R_SYSTEM_VBTADCR2_VBRTCES0_Msk (0x1UL) /*!< VBRTCES0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR2_VBRTCES1_Pos (1UL) /*!< VBRTCES1 (Bit 1) */ + #define R_SYSTEM_VBTADCR2_VBRTCES1_Msk (0x2UL) /*!< VBRTCES1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR2_VBRTCES2_Pos (2UL) /*!< VBRTCES2 (Bit 2) */ + #define R_SYSTEM_VBTADCR2_VBRTCES2_Msk (0x4UL) /*!< VBRTCES2 (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR ======================================================== */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR2 ======================================================= */ + #define R_SYSTEM_VBTICTLR2_VCH0NCE_Pos (0UL) /*!< VCH0NCE (Bit 0) */ + #define R_SYSTEM_VBTICTLR2_VCH0NCE_Msk (0x1UL) /*!< VCH0NCE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH1NCE_Pos (1UL) /*!< VCH1NCE (Bit 1) */ + #define R_SYSTEM_VBTICTLR2_VCH1NCE_Msk (0x2UL) /*!< VCH1NCE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH2NCE_Pos (2UL) /*!< VCH2NCE (Bit 2) */ + #define R_SYSTEM_VBTICTLR2_VCH2NCE_Msk (0x4UL) /*!< VCH2NCE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH0EG_Pos (4UL) /*!< VCH0EG (Bit 4) */ + #define R_SYSTEM_VBTICTLR2_VCH0EG_Msk (0x10UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH1EG_Pos (5UL) /*!< VCH1EG (Bit 5) */ + #define R_SYSTEM_VBTICTLR2_VCH1EG_Msk (0x20UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH2EG_Pos (6UL) /*!< VCH2EG (Bit 6) */ + #define R_SYSTEM_VBTICTLR2_VCH2EG_Msk (0x40UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTIMONR ======================================================== */ + #define R_SYSTEM_VBTIMONR_VCH0MON_Pos (0UL) /*!< VCH0MON (Bit 0) */ + #define R_SYSTEM_VBTIMONR_VCH0MON_Msk (0x1UL) /*!< VCH0MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTIMONR_VCH1MON_Pos (1UL) /*!< VCH1MON (Bit 1) */ + #define R_SYSTEM_VBTIMONR_VCH1MON_Msk (0x2UL) /*!< VCH1MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTIMONR_VCH2MON_Pos (2UL) /*!< VCH2MON (Bit 2) */ + #define R_SYSTEM_VBTIMONR_VCH2MON_Msk (0x4UL) /*!< VCH2MON (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTNCWCR ======================================================== */ + #define R_SYSTEM_VBTNCWCR_VINCW_Pos (0UL) /*!< VINCW (Bit 0) */ + #define R_SYSTEM_VBTNCWCR_VINCW_Msk (0x7UL) /*!< VINCW (Bitfield-Mask: 0x07) */ +/* ======================================================= VBTADCR3 ======================================================== */ + #define R_SYSTEM_VBTADCR3_VBTADZE0_Pos (0UL) /*!< VBTADZE0 (Bit 0) */ + #define R_SYSTEM_VBTADCR3_VBTADZE0_Msk (0x1UL) /*!< VBTADZE0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR3_VBTADZE1_Pos (1UL) /*!< VBTADZE1 (Bit 1) */ + #define R_SYSTEM_VBTADCR3_VBTADZE1_Msk (0x2UL) /*!< VBTADZE1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR3_VBTADZE2_Pos (2UL) /*!< VBTADZE2 (Bit 2) */ + #define R_SYSTEM_VBTADCR3_VBTADZE2_Msk (0x4UL) /*!< VBTADZE2 (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBKR ========================================================= */ + #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCDR ========================================================= */ + #define R_TSN_CAL_TSCDR_TSCDR_Pos (0UL) /*!< TSCDR (Bit 0) */ + #define R_TSN_CAL_TSCDR_TSCDR_Msk (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCR ========================================================== */ + #define R_TSN_CTRL_TSCR_TSEN_Pos (7UL) /*!< TSEN (Bit 7) */ + #define R_TSN_CTRL_TSCR_TSEN_Msk (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01) */ + #define R_TSN_CTRL_TSCR_TSOE_Pos (4UL) /*!< TSOE (Bit 4) */ + #define R_TSN_CTRL_TSCR_TSOE_Msk (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */ + #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */ + #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ========================================================= CFIFO ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== DVCHGR ========================================================= */ + #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ + #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ + #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ + #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ====================================================== USBBCCTRL0 ======================================================= */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */ +/* ======================================================== UCKSEL ========================================================= */ + #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */ + #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */ +/* ========================================================= USBMC ========================================================= */ + #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */ + #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */ + #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSLEW ======================================================== */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR0R_FS ======================================================= */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR1R_FS ======================================================= */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_VIN ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MC =========================================================== */ + #define R_VIN_MC_ME_Pos (0UL) /*!< ME (Bit 0) */ + #define R_VIN_MC_ME_Msk (0x1UL) /*!< ME (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_BPS_Pos (1UL) /*!< BPS (Bit 1) */ + #define R_VIN_MC_BPS_Msk (0x2UL) /*!< BPS (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_IM_Pos (3UL) /*!< IM (Bit 3) */ + #define R_VIN_MC_IM_Msk (0x18UL) /*!< IM (Bitfield-Mask: 0x03) */ + #define R_VIN_MC_EN_Pos (6UL) /*!< EN (Bit 6) */ + #define R_VIN_MC_EN_Msk (0x40UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_DC_Pos (14UL) /*!< DC (Bit 14) */ + #define R_VIN_MC_DC_Msk (0xc000UL) /*!< DC (Bitfield-Mask: 0x03) */ + #define R_VIN_MC_INF_Pos (16UL) /*!< INF (Bit 16) */ + #define R_VIN_MC_INF_Msk (0x70000UL) /*!< INF (Bitfield-Mask: 0x07) */ + #define R_VIN_MC_LUTE_Pos (20UL) /*!< LUTE (Bit 20) */ + #define R_VIN_MC_LUTE_Msk (0x100000UL) /*!< LUTE (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_ST_Pos (22UL) /*!< ST (Bit 22) */ + #define R_VIN_MC_ST_Msk (0x400000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_DC2_Pos (24UL) /*!< DC2 (Bit 24) */ + #define R_VIN_MC_DC2_Msk (0x1000000UL) /*!< DC2 (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_YUV444_Pos (25UL) /*!< YUV444 (Bit 25) */ + #define R_VIN_MC_YUV444_Msk (0x2000000UL) /*!< YUV444 (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_SCLE_Pos (26UL) /*!< SCLE (Bit 26) */ + #define R_VIN_MC_SCLE_Msk (0x4000000UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_CLP_Pos (28UL) /*!< CLP (Bit 28) */ + #define R_VIN_MC_CLP_Msk (0x30000000UL) /*!< CLP (Bitfield-Mask: 0x03) */ +/* ========================================================== MS =========================================================== */ + #define R_VIN_MS_CA_Pos (0UL) /*!< CA (Bit 0) */ + #define R_VIN_MS_CA_Msk (0x1UL) /*!< CA (Bitfield-Mask: 0x01) */ + #define R_VIN_MS_AV_Pos (1UL) /*!< AV (Bit 1) */ + #define R_VIN_MS_AV_Msk (0x2UL) /*!< AV (Bitfield-Mask: 0x01) */ + #define R_VIN_MS_FS_Pos (2UL) /*!< FS (Bit 2) */ + #define R_VIN_MS_FS_Msk (0x4UL) /*!< FS (Bitfield-Mask: 0x01) */ + #define R_VIN_MS_FBS_Pos (3UL) /*!< FBS (Bit 3) */ + #define R_VIN_MS_FBS_Msk (0x18UL) /*!< FBS (Bitfield-Mask: 0x03) */ + #define R_VIN_MS_MA_Pos (16UL) /*!< MA (Bit 16) */ + #define R_VIN_MS_MA_Msk (0x10000UL) /*!< MA (Bitfield-Mask: 0x01) */ + #define R_VIN_MS_FMS_Pos (19UL) /*!< FMS (Bit 19) */ + #define R_VIN_MS_FMS_Msk (0x180000UL) /*!< FMS (Bitfield-Mask: 0x03) */ +/* ========================================================== FC =========================================================== */ + #define R_VIN_FC_CC_Pos (1UL) /*!< CC (Bit 1) */ + #define R_VIN_FC_CC_Msk (0x2UL) /*!< CC (Bitfield-Mask: 0x01) */ +/* ========================================================= SLPRC ========================================================= */ + #define R_VIN_SLPRC_SLPRC_Pos (0UL) /*!< SLPRC (Bit 0) */ + #define R_VIN_SLPRC_SLPRC_Msk (0xfffUL) /*!< SLPRC (Bitfield-Mask: 0xfff) */ +/* ========================================================= ELPRC ========================================================= */ + #define R_VIN_ELPRC_ELPRC_Pos (0UL) /*!< ELPRC (Bit 0) */ + #define R_VIN_ELPRC_ELPRC_Msk (0xfffUL) /*!< ELPRC (Bitfield-Mask: 0xfff) */ +/* ========================================================= SPPRC ========================================================= */ + #define R_VIN_SPPRC_SPPRC_Pos (0UL) /*!< SPPRC (Bit 0) */ + #define R_VIN_SPPRC_SPPRC_Msk (0xfffUL) /*!< SPPRC (Bitfield-Mask: 0xfff) */ +/* ========================================================= EPPRC ========================================================= */ + #define R_VIN_EPPRC_EPPRC_Pos (0UL) /*!< EPPRC (Bit 0) */ + #define R_VIN_EPPRC_EPPRC_Msk (0xfffUL) /*!< EPPRC (Bitfield-Mask: 0xfff) */ +/* ======================================================= CSI_IFMD ======================================================== */ + #define R_VIN_CSI_IFMD_VC_SEL_Pos (0UL) /*!< VC_SEL (Bit 0) */ + #define R_VIN_CSI_IFMD_VC_SEL_Msk (0xfUL) /*!< VC_SEL (Bitfield-Mask: 0x0f) */ + #define R_VIN_CSI_IFMD_DT_Pos (8UL) /*!< DT (Bit 8) */ + #define R_VIN_CSI_IFMD_DT_Msk (0x3f00UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_VIN_CSI_IFMD_DES0_Pos (25UL) /*!< DES0 (Bit 25) */ + #define R_VIN_CSI_IFMD_DES0_Msk (0x2000000UL) /*!< DES0 (Bitfield-Mask: 0x01) */ +/* ======================================================== CSIFLD ========================================================= */ + #define R_VIN_CSIFLD_FLD_EN_Pos (0UL) /*!< FLD_EN (Bit 0) */ + #define R_VIN_CSIFLD_FLD_EN_Msk (0x1UL) /*!< FLD_EN (Bitfield-Mask: 0x01) */ + #define R_VIN_CSIFLD_FLD_SEL_Pos (4UL) /*!< FLD_SEL (Bit 4) */ + #define R_VIN_CSIFLD_FLD_SEL_Msk (0x30UL) /*!< FLD_SEL (Bitfield-Mask: 0x03) */ + #define R_VIN_CSIFLD_FLD_NUM_Pos (16UL) /*!< FLD_NUM (Bit 16) */ + #define R_VIN_CSIFLD_FLD_NUM_Msk (0x10000UL) /*!< FLD_NUM (Bitfield-Mask: 0x01) */ +/* ========================================================== IS =========================================================== */ + #define R_VIN_IS_IS_Pos (0UL) /*!< IS (Bit 0) */ + #define R_VIN_IS_IS_Msk (0x1fffUL) /*!< IS (Bitfield-Mask: 0x1fff) */ +/* ========================================================== MB1 ========================================================== */ + #define R_VIN_MB1_MB1_Pos (7UL) /*!< MB1 (Bit 7) */ + #define R_VIN_MB1_MB1_Msk (0xffffff80UL) /*!< MB1 (Bitfield-Mask: 0x1ffffff) */ +/* ========================================================== MB2 ========================================================== */ + #define R_VIN_MB2_MB2_Pos (7UL) /*!< MB2 (Bit 7) */ + #define R_VIN_MB2_MB2_Msk (0xffffff80UL) /*!< MB2 (Bitfield-Mask: 0x1ffffff) */ +/* ========================================================== MB3 ========================================================== */ + #define R_VIN_MB3_MB3_Pos (7UL) /*!< MB3 (Bit 7) */ + #define R_VIN_MB3_MB3_Msk (0xffffff80UL) /*!< MB3 (Bitfield-Mask: 0x1ffffff) */ +/* ========================================================== LC =========================================================== */ + #define R_VIN_LC_LC_Pos (0UL) /*!< LC (Bit 0) */ + #define R_VIN_LC_LC_Msk (0xfffUL) /*!< LC (Bitfield-Mask: 0xfff) */ +/* ========================================================== IE =========================================================== */ + #define R_VIN_IE_FOE_Pos (0UL) /*!< FOE (Bit 0) */ + #define R_VIN_IE_FOE_Msk (0x1UL) /*!< FOE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_EFE_Pos (1UL) /*!< EFE (Bit 1) */ + #define R_VIN_IE_EFE_Msk (0x2UL) /*!< EFE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_SIE_Pos (2UL) /*!< SIE (Bit 2) */ + #define R_VIN_IE_SIE_Msk (0x4UL) /*!< SIE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_FIE_Pos (4UL) /*!< FIE (Bit 4) */ + #define R_VIN_IE_FIE_Msk (0x10UL) /*!< FIE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_FME_Pos (5UL) /*!< FME (Bit 5) */ + #define R_VIN_IE_FME_Msk (0x20UL) /*!< FME (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_PRCLIPHEE_Pos (8UL) /*!< PRCLIPHEE (Bit 8) */ + #define R_VIN_IE_PRCLIPHEE_Msk (0x100UL) /*!< PRCLIPHEE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_PRCLIPVEE_Pos (9UL) /*!< PRCLIPVEE (Bit 9) */ + #define R_VIN_IE_PRCLIPVEE_Msk (0x200UL) /*!< PRCLIPVEE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_ROE_Pos (14UL) /*!< ROE (Bit 14) */ + #define R_VIN_IE_ROE_Msk (0x4000UL) /*!< ROE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_AREE_Pos (15UL) /*!< AREE (Bit 15) */ + #define R_VIN_IE_AREE_Msk (0x8000UL) /*!< AREE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_VRE_Pos (16UL) /*!< VRE (Bit 16) */ + #define R_VIN_IE_VRE_Msk (0x10000UL) /*!< VRE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_VFE_Pos (17UL) /*!< VFE (Bit 17) */ + #define R_VIN_IE_VFE_Msk (0x20000UL) /*!< VFE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_FIE2_Pos (31UL) /*!< FIE2 (Bit 31) */ + #define R_VIN_IE_FIE2_Msk (0x80000000UL) /*!< FIE2 (Bitfield-Mask: 0x01) */ +/* ========================================================= INTS ========================================================== */ + #define R_VIN_INTS_FOS_Pos (0UL) /*!< FOS (Bit 0) */ + #define R_VIN_INTS_FOS_Msk (0x1UL) /*!< FOS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_EFS_Pos (1UL) /*!< EFS (Bit 1) */ + #define R_VIN_INTS_EFS_Msk (0x2UL) /*!< EFS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_SIS_Pos (2UL) /*!< SIS (Bit 2) */ + #define R_VIN_INTS_SIS_Msk (0x4UL) /*!< SIS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_FIS_Pos (4UL) /*!< FIS (Bit 4) */ + #define R_VIN_INTS_FIS_Msk (0x10UL) /*!< FIS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_FMS_Pos (5UL) /*!< FMS (Bit 5) */ + #define R_VIN_INTS_FMS_Msk (0x20UL) /*!< FMS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_PRCLIPHES_Pos (8UL) /*!< PRCLIPHES (Bit 8) */ + #define R_VIN_INTS_PRCLIPHES_Msk (0x100UL) /*!< PRCLIPHES (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_PRCLIPVES_Pos (9UL) /*!< PRCLIPVES (Bit 9) */ + #define R_VIN_INTS_PRCLIPVES_Msk (0x200UL) /*!< PRCLIPVES (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_ROS_Pos (14UL) /*!< ROS (Bit 14) */ + #define R_VIN_INTS_ROS_Msk (0x4000UL) /*!< ROS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_ARES_Pos (15UL) /*!< ARES (Bit 15) */ + #define R_VIN_INTS_ARES_Msk (0x8000UL) /*!< ARES (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_VRS_Pos (16UL) /*!< VRS (Bit 16) */ + #define R_VIN_INTS_VRS_Msk (0x10000UL) /*!< VRS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_VFS_Pos (17UL) /*!< VFS (Bit 17) */ + #define R_VIN_INTS_VFS_Msk (0x20000UL) /*!< VFS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_FIS2_Pos (31UL) /*!< FIS2 (Bit 31) */ + #define R_VIN_INTS_FIS2_Msk (0x80000000UL) /*!< FIS2 (Bitfield-Mask: 0x01) */ +/* ========================================================== SI =========================================================== */ + #define R_VIN_SI_SI_Pos (0UL) /*!< SI (Bit 0) */ + #define R_VIN_SI_SI_Msk (0xfffUL) /*!< SI (Bitfield-Mask: 0xfff) */ +/* ======================================================== MTCSTOP ======================================================== */ + #define R_VIN_MTCSTOP_STOPREQ_Pos (0UL) /*!< STOPREQ (Bit 0) */ + #define R_VIN_MTCSTOP_STOPREQ_Msk (0x1UL) /*!< STOPREQ (Bitfield-Mask: 0x01) */ + #define R_VIN_MTCSTOP_STOPACK_Pos (1UL) /*!< STOPACK (Bit 1) */ + #define R_VIN_MTCSTOP_STOPACK_Msk (0x2UL) /*!< STOPACK (Bitfield-Mask: 0x01) */ + #define R_VIN_MTCSTOP_OUTSTAND_Pos (16UL) /*!< OUTSTAND (Bit 16) */ + #define R_VIN_MTCSTOP_OUTSTAND_Msk (0x3f0000UL) /*!< OUTSTAND (Bitfield-Mask: 0x3f) */ +/* ========================================================== DMR ========================================================== */ + #define R_VIN_DMR_DTMD_Pos (0UL) /*!< DTMD (Bit 0) */ + #define R_VIN_DMR_DTMD_Msk (0x3UL) /*!< DTMD (Bitfield-Mask: 0x03) */ + #define R_VIN_DMR_ABIT_Pos (2UL) /*!< ABIT (Bit 2) */ + #define R_VIN_DMR_ABIT_Msk (0x4UL) /*!< ABIT (Bitfield-Mask: 0x01) */ + #define R_VIN_DMR_BPSM_Pos (4UL) /*!< BPSM (Bit 4) */ + #define R_VIN_DMR_BPSM_Msk (0x10UL) /*!< BPSM (Bitfield-Mask: 0x01) */ + #define R_VIN_DMR_EXRGB_Pos (8UL) /*!< EXRGB (Bit 8) */ + #define R_VIN_DMR_EXRGB_Msk (0x100UL) /*!< EXRGB (Bitfield-Mask: 0x01) */ + #define R_VIN_DMR_YC_THR_Pos (11UL) /*!< YC_THR (Bit 11) */ + #define R_VIN_DMR_YC_THR_Msk (0x800UL) /*!< YC_THR (Bitfield-Mask: 0x01) */ + #define R_VIN_DMR_YMODE_Pos (12UL) /*!< YMODE (Bit 12) */ + #define R_VIN_DMR_YMODE_Msk (0x7000UL) /*!< YMODE (Bitfield-Mask: 0x07) */ + #define R_VIN_DMR_A8BIT_Pos (24UL) /*!< A8BIT (Bit 24) */ + #define R_VIN_DMR_A8BIT_Msk (0xff000000UL) /*!< A8BIT (Bitfield-Mask: 0xff) */ +/* ========================================================= UVAOF ========================================================= */ + #define R_VIN_UVAOF_UVAOF_Pos (7UL) /*!< UVAOF (Bit 7) */ + #define R_VIN_UVAOF_UVAOF_Msk (0xffffff80UL) /*!< UVAOF (Bitfield-Mask: 0x1ffffff) */ +/* ========================================================= CSCE1 ========================================================= */ + #define R_VIN_CSCE1_YMUL2_Pos (0UL) /*!< YMUL2 (Bit 0) */ + #define R_VIN_CSCE1_YMUL2_Msk (0x3fffUL) /*!< YMUL2 (Bitfield-Mask: 0x3fff) */ + #define R_VIN_CSCE1_ROUND_Pos (16UL) /*!< ROUND (Bit 16) */ + #define R_VIN_CSCE1_ROUND_Msk (0x10000UL) /*!< ROUND (Bitfield-Mask: 0x01) */ +/* ========================================================= CSCE2 ========================================================= */ + #define R_VIN_CSCE2_CSUB2_Pos (0UL) /*!< CSUB2 (Bit 0) */ + #define R_VIN_CSCE2_CSUB2_Msk (0xfffUL) /*!< CSUB2 (Bitfield-Mask: 0xfff) */ + #define R_VIN_CSCE2_YSUB2_Pos (16UL) /*!< YSUB2 (Bit 16) */ + #define R_VIN_CSCE2_YSUB2_Msk (0xfff0000UL) /*!< YSUB2 (Bitfield-Mask: 0xfff) */ +/* ========================================================= CSCE3 ========================================================= */ + #define R_VIN_CSCE3_GCRMUL2_Pos (0UL) /*!< GCRMUL2 (Bit 0) */ + #define R_VIN_CSCE3_GCRMUL2_Msk (0x3fffUL) /*!< GCRMUL2 (Bitfield-Mask: 0x3fff) */ + #define R_VIN_CSCE3_RCRMUL2_Pos (16UL) /*!< RCRMUL2 (Bit 16) */ + #define R_VIN_CSCE3_RCRMUL2_Msk (0x3fff0000UL) /*!< RCRMUL2 (Bitfield-Mask: 0x3fff) */ +/* ========================================================= CSCE4 ========================================================= */ + #define R_VIN_CSCE4_BCBMUL2_Pos (0UL) /*!< BCBMUL2 (Bit 0) */ + #define R_VIN_CSCE4_BCBMUL2_Msk (0x3fffUL) /*!< BCBMUL2 (Bitfield-Mask: 0x3fff) */ + #define R_VIN_CSCE4_GCBMUL2_Pos (16UL) /*!< GCBMUL2 (Bit 16) */ + #define R_VIN_CSCE4_GCBMUL2_Msk (0x3fff0000UL) /*!< GCBMUL2 (Bitfield-Mask: 0x3fff) */ +/* ======================================================= UDS_CTRL ======================================================== */ + #define R_VIN_UDS_CTRL_NE_BCB_Pos (16UL) /*!< NE_BCB (Bit 16) */ + #define R_VIN_UDS_CTRL_NE_BCB_Msk (0x10000UL) /*!< NE_BCB (Bitfield-Mask: 0x01) */ + #define R_VIN_UDS_CTRL_NE_GY_Pos (17UL) /*!< NE_GY (Bit 17) */ + #define R_VIN_UDS_CTRL_NE_GY_Msk (0x20000UL) /*!< NE_GY (Bitfield-Mask: 0x01) */ + #define R_VIN_UDS_CTRL_NE_RCR_Pos (18UL) /*!< NE_RCR (Bit 18) */ + #define R_VIN_UDS_CTRL_NE_RCR_Msk (0x40000UL) /*!< NE_RCR (Bitfield-Mask: 0x01) */ + #define R_VIN_UDS_CTRL_BC_Pos (20UL) /*!< BC (Bit 20) */ + #define R_VIN_UDS_CTRL_BC_Msk (0x100000UL) /*!< BC (Bitfield-Mask: 0x01) */ + #define R_VIN_UDS_CTRL_BLADV_Pos (28UL) /*!< BLADV (Bit 28) */ + #define R_VIN_UDS_CTRL_BLADV_Msk (0x10000000UL) /*!< BLADV (Bitfield-Mask: 0x01) */ + #define R_VIN_UDS_CTRL_AMD_Pos (30UL) /*!< AMD (Bit 30) */ + #define R_VIN_UDS_CTRL_AMD_Msk (0x40000000UL) /*!< AMD (Bitfield-Mask: 0x01) */ +/* ======================================================= UDS_SCALE ======================================================= */ + #define R_VIN_UDS_SCALE_VFRAC_Pos (0UL) /*!< VFRAC (Bit 0) */ + #define R_VIN_UDS_SCALE_VFRAC_Msk (0xfffUL) /*!< VFRAC (Bitfield-Mask: 0xfff) */ + #define R_VIN_UDS_SCALE_VMANT_Pos (12UL) /*!< VMANT (Bit 12) */ + #define R_VIN_UDS_SCALE_VMANT_Msk (0xf000UL) /*!< VMANT (Bitfield-Mask: 0x0f) */ + #define R_VIN_UDS_SCALE_HFRAC_Pos (16UL) /*!< HFRAC (Bit 16) */ + #define R_VIN_UDS_SCALE_HFRAC_Msk (0xfff0000UL) /*!< HFRAC (Bitfield-Mask: 0xfff) */ + #define R_VIN_UDS_SCALE_HMANT_Pos (28UL) /*!< HMANT (Bit 28) */ + #define R_VIN_UDS_SCALE_HMANT_Msk (0xf0000000UL) /*!< HMANT (Bitfield-Mask: 0x0f) */ +/* ==================================================== UDS_PASS_BWIDTH ==================================================== */ + #define R_VIN_UDS_PASS_BWIDTH_BWIDTH_V_Pos (0UL) /*!< BWIDTH_V (Bit 0) */ + #define R_VIN_UDS_PASS_BWIDTH_BWIDTH_V_Msk (0x7fUL) /*!< BWIDTH_V (Bitfield-Mask: 0x7f) */ + #define R_VIN_UDS_PASS_BWIDTH_BWIDTH_H_Pos (16UL) /*!< BWIDTH_H (Bit 16) */ + #define R_VIN_UDS_PASS_BWIDTH_BWIDTH_H_Msk (0x7f0000UL) /*!< BWIDTH_H (Bitfield-Mask: 0x7f) */ +/* ===================================================== UDS_CLIP_SIZE ===================================================== */ + #define R_VIN_UDS_CLIP_SIZE_CL_VSIZE_Pos (0UL) /*!< CL_VSIZE (Bit 0) */ + #define R_VIN_UDS_CLIP_SIZE_CL_VSIZE_Msk (0xfffUL) /*!< CL_VSIZE (Bitfield-Mask: 0xfff) */ + #define R_VIN_UDS_CLIP_SIZE_CL_HSIZE_Pos (16UL) /*!< CL_HSIZE (Bit 16) */ + #define R_VIN_UDS_CLIP_SIZE_CL_HSIZE_Msk (0xfff0000UL) /*!< CL_HSIZE (Bitfield-Mask: 0xfff) */ +/* ========================================================= LUTP ========================================================== */ + #define R_VIN_LUTP_LTCRPR_Pos (0UL) /*!< LTCRPR (Bit 0) */ + #define R_VIN_LUTP_LTCRPR_Msk (0x3ffUL) /*!< LTCRPR (Bitfield-Mask: 0x3ff) */ + #define R_VIN_LUTP_LTCBPR_Pos (10UL) /*!< LTCBPR (Bit 10) */ + #define R_VIN_LUTP_LTCBPR_Msk (0xffc00UL) /*!< LTCBPR (Bitfield-Mask: 0x3ff) */ + #define R_VIN_LUTP_LTYPR_Pos (20UL) /*!< LTYPR (Bit 20) */ + #define R_VIN_LUTP_LTYPR_Msk (0x3ff00000UL) /*!< LTYPR (Bitfield-Mask: 0x3ff) */ +/* ========================================================= LUTD ========================================================== */ + #define R_VIN_LUTD_LTCRDT_Pos (0UL) /*!< LTCRDT (Bit 0) */ + #define R_VIN_LUTD_LTCRDT_Msk (0xffUL) /*!< LTCRDT (Bitfield-Mask: 0xff) */ + #define R_VIN_LUTD_LTCBDT_Pos (8UL) /*!< LTCBDT (Bit 8) */ + #define R_VIN_LUTD_LTCBDT_Msk (0xff00UL) /*!< LTCBDT (Bitfield-Mask: 0xff) */ + #define R_VIN_LUTD_LTYDT_Pos (16UL) /*!< LTYDT (Bit 16) */ + #define R_VIN_LUTD_LTYDT_Msk (0xff0000UL) /*!< LTYDT (Bitfield-Mask: 0xff) */ +/* ========================================================= YCCR1 ========================================================= */ + #define R_VIN_YCCR1_YCLRP_Pos (0UL) /*!< YCLRP (Bit 0) */ + #define R_VIN_YCCR1_YCLRP_Msk (0x1fffUL) /*!< YCLRP (Bitfield-Mask: 0x1fff) */ +/* ========================================================= YCCR2 ========================================================= */ + #define R_VIN_YCCR2_YCLGP_Pos (0UL) /*!< YCLGP (Bit 0) */ + #define R_VIN_YCCR2_YCLGP_Msk (0x1fffUL) /*!< YCLGP (Bitfield-Mask: 0x1fff) */ + #define R_VIN_YCCR2_YCLBP_Pos (16UL) /*!< YCLBP (Bit 16) */ + #define R_VIN_YCCR2_YCLBP_Msk (0x1fff0000UL) /*!< YCLBP (Bitfield-Mask: 0x1fff) */ +/* ========================================================= YCCR3 ========================================================= */ + #define R_VIN_YCCR3_YCLAP_Pos (0UL) /*!< YCLAP (Bit 0) */ + #define R_VIN_YCCR3_YCLAP_Msk (0xfffUL) /*!< YCLAP (Bitfield-Mask: 0xfff) */ + #define R_VIN_YCCR3_YCLHEN_Pos (23UL) /*!< YCLHEN (Bit 23) */ + #define R_VIN_YCCR3_YCLHEN_Msk (0x800000UL) /*!< YCLHEN (Bitfield-Mask: 0x01) */ + #define R_VIN_YCCR3_YCLSFT_Pos (24UL) /*!< YCLSFT (Bit 24) */ + #define R_VIN_YCCR3_YCLSFT_Msk (0x1f000000UL) /*!< YCLSFT (Bitfield-Mask: 0x1f) */ +/* ======================================================== CBCCR1 ========================================================= */ + #define R_VIN_CBCCR1_CBCLRP_Pos (0UL) /*!< CBCLRP (Bit 0) */ + #define R_VIN_CBCCR1_CBCLRP_Msk (0x1fffUL) /*!< CBCLRP (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CBCCR2 ========================================================= */ + #define R_VIN_CBCCR2_CBCLGP_Pos (0UL) /*!< CBCLGP (Bit 0) */ + #define R_VIN_CBCCR2_CBCLGP_Msk (0x1fffUL) /*!< CBCLGP (Bitfield-Mask: 0x1fff) */ + #define R_VIN_CBCCR2_CBCLBP_Pos (16UL) /*!< CBCLBP (Bit 16) */ + #define R_VIN_CBCCR2_CBCLBP_Msk (0x1fff0000UL) /*!< CBCLBP (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CBCCR3 ========================================================= */ + #define R_VIN_CBCCR3_CBCLAP_Pos (0UL) /*!< CBCLAP (Bit 0) */ + #define R_VIN_CBCCR3_CBCLAP_Msk (0xfffUL) /*!< CBCLAP (Bitfield-Mask: 0xfff) */ + #define R_VIN_CBCCR3_CBCLHEN_Pos (23UL) /*!< CBCLHEN (Bit 23) */ + #define R_VIN_CBCCR3_CBCLHEN_Msk (0x800000UL) /*!< CBCLHEN (Bitfield-Mask: 0x01) */ + #define R_VIN_CBCCR3_CBCLSFT_Pos (24UL) /*!< CBCLSFT (Bit 24) */ + #define R_VIN_CBCCR3_CBCLSFT_Msk (0x1f000000UL) /*!< CBCLSFT (Bitfield-Mask: 0x1f) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_VIN_CRCCR1_CRCLRP_Pos (0UL) /*!< CRCLRP (Bit 0) */ + #define R_VIN_CRCCR1_CRCLRP_Msk (0x1fffUL) /*!< CRCLRP (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CRCCR2 ========================================================= */ + #define R_VIN_CRCCR2_CRCLGP_Pos (0UL) /*!< CRCLGP (Bit 0) */ + #define R_VIN_CRCCR2_CRCLGP_Msk (0x1fffUL) /*!< CRCLGP (Bitfield-Mask: 0x1fff) */ + #define R_VIN_CRCCR2_CRCLBP_Pos (16UL) /*!< CRCLBP (Bit 16) */ + #define R_VIN_CRCCR2_CRCLBP_Msk (0x1fff0000UL) /*!< CRCLBP (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CRCCR3 ========================================================= */ + #define R_VIN_CRCCR3_CRCLAP_Pos (0UL) /*!< CRCLAP (Bit 0) */ + #define R_VIN_CRCCR3_CRCLAP_Msk (0xfffUL) /*!< CRCLAP (Bitfield-Mask: 0xfff) */ + #define R_VIN_CRCCR3_CRCLHEN_Pos (23UL) /*!< CRCLHEN (Bit 23) */ + #define R_VIN_CRCCR3_CRCLHEN_Msk (0x800000UL) /*!< CRCLHEN (Bitfield-Mask: 0x01) */ + #define R_VIN_CRCCR3_CRCLSFT_Pos (24UL) /*!< CRCLSFT (Bit 24) */ + #define R_VIN_CRCCR3_CRCLSFT_Msk (0x1f000000UL) /*!< CRCLSFT (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ + #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ + #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= WDTCSTPR ======================================================== */ + #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CSAR ========================================================== */ + #define R_CPSCU_CSAR_CACHESA_Pos (0UL) /*!< CACHESA (Bit 0) */ + #define R_CPSCU_CSAR_CACHESA_Msk (0x1UL) /*!< CACHESA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHELSA_Pos (1UL) /*!< CACHELSA (Bit 1) */ + #define R_CPSCU_CSAR_CACHELSA_Msk (0x2UL) /*!< CACHELSA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHEESA_Pos (2UL) /*!< CACHEESA (Bit 2) */ + #define R_CPSCU_CSAR_CACHEESA_Msk (0x4UL) /*!< CACHEESA (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMSAR ======================================================== */ + #define R_CPSCU_SRAMSAR_SRAMSA_Pos (0UL) /*!< SRAMSA (Bit 0) */ + #define R_CPSCU_SRAMSAR_SRAMSA_Msk (0x1UL) /*!< SRAMSA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMWTSA_Pos (8UL) /*!< SRAMWTSA (Bit 8) */ + #define R_CPSCU_SRAMSAR_SRAMWTSA_Msk (0x100UL) /*!< SRAMWTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= STBRAMSAR ======================================================= */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos (0UL) /*!< NSBSTBR (Bit 0) */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk (0xfUL) /*!< NSBSTBR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DTCSAR ========================================================= */ + #define R_CPSCU_DTCSAR_DTCSTSA_Pos (0UL) /*!< DTCSTSA (Bit 0) */ + #define R_CPSCU_DTCSAR_DTCSTSA_Msk (0x1UL) /*!< DTCSTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== DMACSAR ======================================================== */ + #define R_CPSCU_DMACSAR_DMASTSA_Pos (0UL) /*!< DMASTSA (Bit 0) */ + #define R_CPSCU_DMACSAR_DMASTSA_Msk (0x1UL) /*!< DMASTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARA ======================================================== */ + #define R_CPSCU_ICUSARA_SAIRQCR_Pos (0UL) /*!< SAIRQCR (Bit 0) */ + #define R_CPSCU_ICUSARA_SAIRQCR_Msk (0x1UL) /*!< SAIRQCR (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARB ======================================================== */ + #define R_CPSCU_ICUSARB_SANMI_Pos (0UL) /*!< SANMI (Bit 0) */ + #define R_CPSCU_ICUSARB_SANMI_Msk (0x1UL) /*!< SANMI (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARC ======================================================== */ + #define R_CPSCU_ICUSARC_SADMACn_Pos (0UL) /*!< SADMACn (Bit 0) */ + #define R_CPSCU_ICUSARC_SADMACn_Msk (0xffUL) /*!< SADMACn (Bitfield-Mask: 0xff) */ +/* ======================================================== ICUSARD ======================================================== */ + #define R_CPSCU_ICUSARD_SASELSR0_Pos (0UL) /*!< SASELSR0 (Bit 0) */ + #define R_CPSCU_ICUSARD_SASELSR0_Msk (0x1UL) /*!< SASELSR0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARE ======================================================== */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos (16UL) /*!< SAIWDTWUP (Bit 16) */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk (0x10000UL) /*!< SAIWDTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Pos (18UL) /*!< SALVD1WUP (Bit 18) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Msk (0x40000UL) /*!< SALVD1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Pos (19UL) /*!< SALVD2WUP (Bit 19) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos (20UL) /*!< SAVBATTWUP (Bit 20) */ + #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk (0x100000UL) /*!< SAVBATTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk (0x2000000UL) /*!< SARTCPRDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos (27UL) /*!< SAUSBFS0WUP (Bit 27) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk (0x8000000UL) /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos (28UL) /*!< SAAGT1UDWUP (Bit 28) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos (29UL) /*!< SAAGT1CAWUP (Bit 29) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos (30UL) /*!< SAAGT1CBWUP (Bit 30) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos (31UL) /*!< SAIIC0WUP (Bit 31) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARF ======================================================== */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos (0UL) /*!< SAAGT3UDWUP (Bit 0) */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk (0x1UL) /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos (1UL) /*!< SAAGT3CAWUP (Bit 1) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk (0x2UL) /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos (2UL) /*!< SAAGT3CBWUP (Bit 2) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos (3UL) /*!< SACOMPHS0WUP (Bit 3) */ + #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk (0x8UL) /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Pos (7UL) /*!< SASOSCWUP (Bit 7) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Msk (0x80UL) /*!< SASOSCWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos (8UL) /*!< SAULP0UWUP (Bit 8) */ + #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk (0x100UL) /*!< SAULP0UWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos (9UL) /*!< SAULP0AWUP (Bit 9) */ + #define R_CPSCU_ICUSARF_SAULP0AWUP_Msk (0x200UL) /*!< SAULP0AWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP0BWUP_Pos (10UL) /*!< SAULP0BWUP (Bit 10) */ + #define R_CPSCU_ICUSARF_SAULP0BWUP_Msk (0x400UL) /*!< SAULP0BWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAI3CWUP_Pos (11UL) /*!< SAI3CWUP (Bit 11) */ + #define R_CPSCU_ICUSARF_SAI3CWUP_Msk (0x800UL) /*!< SAI3CWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP1UWUP_Pos (12UL) /*!< SAULP1UWUP (Bit 12) */ + #define R_CPSCU_ICUSARF_SAULP1UWUP_Msk (0x1000UL) /*!< SAULP1UWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP1AWUP_Pos (13UL) /*!< SAULP1AWUP (Bit 13) */ + #define R_CPSCU_ICUSARF_SAULP1AWUP_Msk (0x2000UL) /*!< SAULP1AWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP1BWUP_Pos (14UL) /*!< SAULP1BWUP (Bit 14) */ + #define R_CPSCU_ICUSARF_SAULP1BWUP_Msk (0x4000UL) /*!< SAULP1BWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAPDMWUP_Pos (15UL) /*!< SAPDMWUP (Bit 15) */ + #define R_CPSCU_ICUSARF_SAPDMWUP_Msk (0x8000UL) /*!< SAPDMWUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARG ======================================================== */ + #define R_CPSCU_ICUSARG_SAIELSR_Pos (0UL) /*!< SAIELSR (Bit 0) */ + #define R_CPSCU_ICUSARG_SAIELSR_Msk (0x1UL) /*!< SAIELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARH ======================================================== */ + #define R_CPSCU_ICUSARH_SAIELSR_Pos (0UL) /*!< SAIELSR (Bit 0) */ + #define R_CPSCU_ICUSARH_SAIELSR_Msk (0x1UL) /*!< SAIELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARI ======================================================== */ + #define R_CPSCU_ICUSARI_SAIELSR_Pos (0UL) /*!< SAIELSR (Bit 0) */ + #define R_CPSCU_ICUSARI_SAIELSR_Msk (0x1UL) /*!< SAIELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARJ ======================================================== */ + #define R_CPSCU_ICUSARJ_SAIELSR_Pos (0UL) /*!< SAIELSR (Bit 0) */ + #define R_CPSCU_ICUSARJ_SAIELSR_Msk (0x1UL) /*!< SAIELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARK ======================================================== */ + #define R_CPSCU_ICUSARK_SAIELSR_Pos (0UL) /*!< SAIELSR (Bit 0) */ + #define R_CPSCU_ICUSARK_SAIELSR_Msk (0x1UL) /*!< SAIELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARL ======================================================== */ + #define R_CPSCU_ICUSARL_SAIELSR_Pos (0UL) /*!< SAIELSR (Bit 0) */ + #define R_CPSCU_ICUSARL_SAIELSR_Msk (0x1UL) /*!< SAIELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARA ======================================================== */ + #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ + #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARB ======================================================== */ + #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ + #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARC ======================================================== */ + #define R_CPSCU_BUSSARC_BUSSC0_Pos (0UL) /*!< BUSSC0 (Bit 0) */ + #define R_CPSCU_BUSSARC_BUSSC0_Msk (0x1UL) /*!< BUSSC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSPARC ======================================================== */ + #define R_CPSCU_BUSPARC_BUSPA0_Pos (0UL) /*!< BUSPA0 (Bit 0) */ + #define R_CPSCU_BUSPARC_BUSPA0_Msk (0x1UL) /*!< BUSPA0 (Bitfield-Mask: 0x01) */ +/* ========================================================= NMISR ========================================================= */ + #define R_CPSCU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_CPSCU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_CPSCU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_PVD1ST_Pos (2UL) /*!< PVD1ST (Bit 2) */ + #define R_CPSCU_NMISR_PVD1ST_Msk (0x4UL) /*!< PVD1ST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_PVD2ST_Pos (3UL) /*!< PVD2ST (Bit 3) */ + #define R_CPSCU_NMISR_PVD2ST_Msk (0x8UL) /*!< PVD2ST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_SOSTST_Pos (5UL) /*!< SOSTST (Bit 5) */ + #define R_CPSCU_NMISR_SOSTST_Msk (0x20UL) /*!< SOSTST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_CPSCU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_CPSCU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_BUSST_Pos (12UL) /*!< BUSST (Bit 12) */ + #define R_CPSCU_NMISR_BUSST_Msk (0x1000UL) /*!< BUSST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_CMST_Pos (13UL) /*!< CMST (Bit 13) */ + #define R_CPSCU_NMISR_CMST_Msk (0x2000UL) /*!< CMST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_LMST_Pos (14UL) /*!< LMST (Bit 14) */ + #define R_CPSCU_NMISR_LMST_Msk (0x4000UL) /*!< LMST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_LUST_Pos (15UL) /*!< LUST (Bit 15) */ + #define R_CPSCU_NMISR_LUST_Msk (0x8000UL) /*!< LUST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_FPUEXCST_Pos (16UL) /*!< FPUEXCST (Bit 16) */ + #define R_CPSCU_NMISR_FPUEXCST_Msk (0x10000UL) /*!< FPUEXCST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_MRCRDST_Pos (17UL) /*!< MRCRDST (Bit 17) */ + #define R_CPSCU_NMISR_MRCRDST_Msk (0x20000UL) /*!< MRCRDST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_MRERDST_Pos (18UL) /*!< MRERDST (Bit 18) */ + #define R_CPSCU_NMISR_MRERDST_Msk (0x40000UL) /*!< MRERDST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_IPCST_Pos (20UL) /*!< IPCST (Bit 20) */ + #define R_CPSCU_NMISR_IPCST_Msk (0x100000UL) /*!< IPCST (Bitfield-Mask: 0x01) */ +/* ======================================================= MMPUSARA ======================================================== */ + #define R_CPSCU_MMPUSARA_MMPUASA_Pos (0UL) /*!< MMPUASA (Bit 0) */ + #define R_CPSCU_MMPUSARA_MMPUASA_Msk (0x1UL) /*!< MMPUASA (Bitfield-Mask: 0x01) */ +/* ======================================================= MMPUSARB ======================================================== */ + #define R_CPSCU_MMPUSARB_MMPUBSA_Pos (0UL) /*!< MMPUBSA (Bit 0) */ + #define R_CPSCU_MMPUSARB_MMPUBSA_Msk (0x1UL) /*!< MMPUBSA (Bitfield-Mask: 0x01) */ +/* ======================================================== CPUSAR ========================================================= */ + #define R_CPSCU_CPUSAR_CPUSA_Pos (0UL) /*!< CPUSA (Bit 0) */ + #define R_CPSCU_CPUSAR_CPUSA_Msk (0x1UL) /*!< CPUSA (Bitfield-Mask: 0x01) */ +/* ======================================================= DEBUGSAR ======================================================== */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Pos (0UL) /*!< DBGSA0 (Bit 0) */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Msk (0x1UL) /*!< DBGSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DMACCHSAR ======================================================= */ + #define R_CPSCU_DMACCHSAR_SADMAC0_Pos (0UL) /*!< SADMAC0 (Bit 0) */ + #define R_CPSCU_DMACCHSAR_SADMAC0_Msk (0x1UL) /*!< SADMAC0 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_DMACCHSAR_SADMAC1_Pos (16UL) /*!< SADMAC1 (Bit 16) */ + #define R_CPSCU_DMACCHSAR_SADMAC1_Msk (0x10000UL) /*!< SADMAC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== CPUDSAR ======================================================== */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DMACCHPAR ======================================================= */ + #define R_CPSCU_DMACCHPAR_PADMAC0_Pos (0UL) /*!< PADMAC0 (Bit 0) */ + #define R_CPSCU_DMACCHPAR_PADMAC0_Msk (0x1UL) /*!< PADMAC0 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_DMACCHPAR_PADMAC1_Pos (16UL) /*!< PADMAC1 (Bit 16) */ + #define R_CPSCU_DMACCHPAR_PADMAC1_Msk (0x10000UL) /*!< PADMAC1 (Bitfield-Mask: 0x01) */ +/* ====================================================== SRAMSABAR0 ======================================================= */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMSABAR1 ======================================================= */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMSABAR2 ======================================================= */ + #define R_CPSCU_SRAMSABAR2_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR2_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMSABAR3 ======================================================= */ + #define R_CPSCU_SRAMSABAR3_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR3_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ======================================================= CACHESAR ======================================================== */ + #define R_CPSCU_CACHESAR_CACHESA_Pos (0UL) /*!< CACHESA (Bit 0) */ + #define R_CPSCU_CACHESAR_CACHESA_Msk (0x1UL) /*!< CACHESA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CACHESAR_CACHEESA_Pos (2UL) /*!< CACHEESA (Bit 2) */ + #define R_CPSCU_CACHESAR_CACHEESA_Msk (0x4UL) /*!< CACHEESA (Bitfield-Mask: 0x01) */ +/* ======================================================== TCMSAR ========================================================= */ + #define R_CPSCU_TCMSAR_TCMSA_Pos (0UL) /*!< TCMSA (Bit 0) */ + #define R_CPSCU_TCMSAR_TCMSA_Msk (0x1UL) /*!< TCMSA (Bitfield-Mask: 0x01) */ +/* ======================================================= TCMSABARC ======================================================= */ + #define R_CPSCU_TCMSABARC_TCMSABA_Pos (13UL) /*!< TCMSABA (Bit 13) */ + #define R_CPSCU_TCMSABARC_TCMSABA_Msk (0x7e000UL) /*!< TCMSABA (Bitfield-Mask: 0x3f) */ +/* ======================================================= TCMSABARS ======================================================= */ + #define R_CPSCU_TCMSABARS_TCMSABA_Pos (13UL) /*!< TCMSABA (Bit 13) */ + #define R_CPSCU_TCMSABARS_TCMSABA_Msk (0x7e000UL) /*!< TCMSABA (Bitfield-Mask: 0x3f) */ +/* ======================================================= SRAMESAR ======================================================== */ + #define R_CPSCU_SRAMESAR_SRAMESA_Pos (0UL) /*!< SRAMESA (Bit 0) */ + #define R_CPSCU_SRAMESAR_SRAMESA_Msk (0x1UL) /*!< SRAMESA (Bitfield-Mask: 0x01) */ +/* ======================================================== TEVTRCR ======================================================== */ + #define R_CPSCU_TEVTRCR_TEVTE_Pos (0UL) /*!< TEVTE (Bit 0) */ + #define R_CPSCU_TEVTRCR_TEVTE_Msk (0x1UL) /*!< TEVTE (Bitfield-Mask: 0x01) */ + #define R_CPSCU_TEVTRCR_TEVTEICU_Pos (1UL) /*!< TEVTEICU (Bit 1) */ + #define R_CPSCU_TEVTRCR_TEVTEICU_Msk (0x2UL) /*!< TEVTEICU (Bitfield-Mask: 0x01) */ +/* ======================================================== IPCSAR ========================================================= */ + #define R_CPSCU_IPCSAR_SAIPCSEM_Pos (0UL) /*!< SAIPCSEM (Bit 0) */ + #define R_CPSCU_IPCSAR_SAIPCSEM_Msk (0x1UL) /*!< SAIPCSEM (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCSAR_SAIPCNMI_Pos (8UL) /*!< SAIPCNMI (Bit 8) */ + #define R_CPSCU_IPCSAR_SAIPCNMI_Msk (0x100UL) /*!< SAIPCNMI (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCSAR_SAIPCIR0_Pos (16UL) /*!< SAIPCIR0 (Bit 16) */ + #define R_CPSCU_IPCSAR_SAIPCIR0_Msk (0x10000UL) /*!< SAIPCIR0 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCSAR_SAIPCIR1_Pos (17UL) /*!< SAIPCIR1 (Bit 17) */ + #define R_CPSCU_IPCSAR_SAIPCIR1_Msk (0x20000UL) /*!< SAIPCIR1 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCSAR_SAIPCIR2_Pos (18UL) /*!< SAIPCIR2 (Bit 18) */ + #define R_CPSCU_IPCSAR_SAIPCIR2_Msk (0x40000UL) /*!< SAIPCIR2 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCSAR_SAIPCIR3_Pos (19UL) /*!< SAIPCIR3 (Bit 19) */ + #define R_CPSCU_IPCSAR_SAIPCIR3_Msk (0x80000UL) /*!< SAIPCIR3 (Bitfield-Mask: 0x01) */ +/* ======================================================== IPCPAR ========================================================= */ + #define R_CPSCU_IPCPAR_PAIPCSEM_Pos (0UL) /*!< PAIPCSEM (Bit 0) */ + #define R_CPSCU_IPCPAR_PAIPCSEM_Msk (0x1UL) /*!< PAIPCSEM (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCPAR_PAIPCNMI_Pos (8UL) /*!< PAIPCNMI (Bit 8) */ + #define R_CPSCU_IPCPAR_PAIPCNMI_Msk (0x100UL) /*!< PAIPCNMI (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCPAR_PAIPCIR0_Pos (16UL) /*!< PAIPCIR0 (Bit 16) */ + #define R_CPSCU_IPCPAR_PAIPCIR0_Msk (0x10000UL) /*!< PAIPCIR0 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCPAR_PAIPCIR1_Pos (17UL) /*!< PAIPCIR1 (Bit 17) */ + #define R_CPSCU_IPCPAR_PAIPCIR1_Msk (0x20000UL) /*!< PAIPCIR1 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCPAR_PAIPCIR2_Pos (18UL) /*!< PAIPCIR2 (Bit 18) */ + #define R_CPSCU_IPCPAR_PAIPCIR2_Msk (0x40000UL) /*!< PAIPCIR2 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCPAR_PAIPCIR3_Pos (19UL) /*!< PAIPCIR3 (Bit 19) */ + #define R_CPSCU_IPCPAR_PAIPCIR3_Msk (0x80000UL) /*!< PAIPCIR3 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC_B0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= ADCLKENR ======================================================== */ + #define R_ADC_B0_ADCLKENR_CLKEN_Pos (0UL) /*!< CLKEN (Bit 0) */ + #define R_ADC_B0_ADCLKENR_CLKEN_Msk (0x1UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCLKSR ======================================================== */ + #define R_ADC_B0_ADCLKSR_CLKSR_Pos (0UL) /*!< CLKSR (Bit 0) */ + #define R_ADC_B0_ADCLKSR_CLKSR_Msk (0x1UL) /*!< CLKSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCLKCR ======================================================== */ + #define R_ADC_B0_ADCLKCR_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ + #define R_ADC_B0_ADCLKCR_CLKSEL_Msk (0x3UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCLKCR_DIVR_Pos (16UL) /*!< DIVR (Bit 16) */ + #define R_ADC_B0_ADCLKCR_DIVR_Msk (0x70000UL) /*!< DIVR (Bitfield-Mask: 0x07) */ +/* ======================================================== ADSYCR ========================================================= */ + #define R_ADC_B0_ADSYCR_ADSYCYC_Pos (0UL) /*!< ADSYCYC (Bit 0) */ + #define R_ADC_B0_ADSYCR_ADSYCYC_Msk (0x7ffUL) /*!< ADSYCYC (Bitfield-Mask: 0x7ff) */ + #define R_ADC_B0_ADSYCR_ADSYDIS0_Pos (16UL) /*!< ADSYDIS0 (Bit 16) */ + #define R_ADC_B0_ADSYCR_ADSYDIS0_Msk (0x10000UL) /*!< ADSYDIS0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSYCR_ADSYDIS1_Pos (17UL) /*!< ADSYDIS1 (Bit 17) */ + #define R_ADC_B0_ADSYCR_ADSYDIS1_Msk (0x20000UL) /*!< ADSYDIS1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADERINTCR ======================================================= */ + #define R_ADC_B0_ADERINTCR_ADEIE0_Pos (0UL) /*!< ADEIE0 (Bit 0) */ + #define R_ADC_B0_ADERINTCR_ADEIE0_Msk (0x1UL) /*!< ADEIE0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADERINTCR_ADEIE1_Pos (1UL) /*!< ADEIE1 (Bit 1) */ + #define R_ADC_B0_ADERINTCR_ADEIE1_Msk (0x2UL) /*!< ADEIE1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADOVFINTCR ======================================================= */ + #define R_ADC_B0_ADOVFINTCR_ADOVFIE0_Pos (0UL) /*!< ADOVFIE0 (Bit 0) */ + #define R_ADC_B0_ADOVFINTCR_ADOVFIE0_Msk (0x1UL) /*!< ADOVFIE0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFINTCR_ADOVFIE1_Pos (1UL) /*!< ADOVFIE1 (Bit 1) */ + #define R_ADC_B0_ADOVFINTCR_ADOVFIE1_Msk (0x2UL) /*!< ADOVFIE1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCALINTCR ======================================================= */ + #define R_ADC_B0_ADCALINTCR_CALENDIE0_Pos (16UL) /*!< CALENDIE0 (Bit 16) */ + #define R_ADC_B0_ADCALINTCR_CALENDIE0_Msk (0x10000UL) /*!< CALENDIE0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCALINTCR_CALENDIE1_Pos (17UL) /*!< CALENDIE1 (Bit 17) */ + #define R_ADC_B0_ADCALINTCR_CALENDIE1_Msk (0x20000UL) /*!< CALENDIE1 (Bitfield-Mask: 0x01) */ +/* ========================================================= ADMDR ========================================================= */ + #define R_ADC_B0_ADMDR_ADMD0_Pos (0UL) /*!< ADMD0 (Bit 0) */ + #define R_ADC_B0_ADMDR_ADMD0_Msk (0xfUL) /*!< ADMD0 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADMDR_ADMD1_Pos (8UL) /*!< ADMD1 (Bit 8) */ + #define R_ADC_B0_ADMDR_ADMD1_Msk (0xf00UL) /*!< ADMD1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC_B0_ADGSPCR_PGS0_Pos (0UL) /*!< PGS0 (Bit 0) */ + #define R_ADC_B0_ADGSPCR_PGS0_Msk (0x1UL) /*!< PGS0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_RSCN0_Pos (1UL) /*!< RSCN0 (Bit 1) */ + #define R_ADC_B0_ADGSPCR_RSCN0_Msk (0x2UL) /*!< RSCN0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_LGRRS0_Pos (2UL) /*!< LGRRS0 (Bit 2) */ + #define R_ADC_B0_ADGSPCR_LGRRS0_Msk (0x4UL) /*!< LGRRS0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_GRP0_Pos (3UL) /*!< GRP0 (Bit 3) */ + #define R_ADC_B0_ADGSPCR_GRP0_Msk (0x8UL) /*!< GRP0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_PGS1_Pos (8UL) /*!< PGS1 (Bit 8) */ + #define R_ADC_B0_ADGSPCR_PGS1_Msk (0x100UL) /*!< PGS1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_RSCN1_Pos (9UL) /*!< RSCN1 (Bit 9) */ + #define R_ADC_B0_ADGSPCR_RSCN1_Msk (0x200UL) /*!< RSCN1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_LGRRS1_Pos (10UL) /*!< LGRRS1 (Bit 10) */ + #define R_ADC_B0_ADGSPCR_LGRRS1_Msk (0x400UL) /*!< LGRRS1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_GRP1_Pos (11UL) /*!< GRP1 (Bit 11) */ + #define R_ADC_B0_ADGSPCR_GRP1_Msk (0x800UL) /*!< GRP1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSGER ========================================================= */ + #define R_ADC_B0_ADSGER_SGREn_Pos (0UL) /*!< SGREn (Bit 0) */ + #define R_ADC_B0_ADSGER_SGREn_Msk (0x1ffUL) /*!< SGREn (Bitfield-Mask: 0x1ff) */ +/* ======================================================== ADSGCR0 ======================================================== */ + #define R_ADC_B0_ADSGCR0_SGADS0_Pos (0UL) /*!< SGADS0 (Bit 0) */ + #define R_ADC_B0_ADSGCR0_SGADS0_Msk (0x3UL) /*!< SGADS0 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADSGCR0_SGADS1_Pos (8UL) /*!< SGADS1 (Bit 8) */ + #define R_ADC_B0_ADSGCR0_SGADS1_Msk (0x300UL) /*!< SGADS1 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADSGCR0_SGADS2_Pos (16UL) /*!< SGADS2 (Bit 16) */ + #define R_ADC_B0_ADSGCR0_SGADS2_Msk (0x30000UL) /*!< SGADS2 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADSGCR0_SGADS3_Pos (24UL) /*!< SGADS3 (Bit 24) */ + #define R_ADC_B0_ADSGCR0_SGADS3_Msk (0x3000000UL) /*!< SGADS3 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADSGCR1 ======================================================== */ + #define R_ADC_B0_ADSGCR1_SGADS4_Pos (0UL) /*!< SGADS4 (Bit 0) */ + #define R_ADC_B0_ADSGCR1_SGADS4_Msk (0x3UL) /*!< SGADS4 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADSGCR1_SGADS5_Pos (8UL) /*!< SGADS5 (Bit 8) */ + #define R_ADC_B0_ADSGCR1_SGADS5_Msk (0x300UL) /*!< SGADS5 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADSGCR1_SGADS6_Pos (16UL) /*!< SGADS6 (Bit 16) */ + #define R_ADC_B0_ADSGCR1_SGADS6_Msk (0x30000UL) /*!< SGADS6 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADSGCR1_SGADS7_Pos (24UL) /*!< SGADS7 (Bit 24) */ + #define R_ADC_B0_ADSGCR1_SGADS7_Msk (0x3000000UL) /*!< SGADS7 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADSGCR2 ======================================================== */ + #define R_ADC_B0_ADSGCR2_SGADS8_Pos (0UL) /*!< SGADS8 (Bit 0) */ + #define R_ADC_B0_ADSGCR2_SGADS8_Msk (0x3UL) /*!< SGADS8 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADINTCR ======================================================== */ + #define R_ADC_B0_ADINTCR_ADIEn_Pos (0UL) /*!< ADIEn (Bit 0) */ + #define R_ADC_B0_ADINTCR_ADIEn_Msk (0x1ffUL) /*!< ADIEn (Bitfield-Mask: 0x1ff) */ +/* ======================================================= ADTRGEXT0 ======================================================= */ + #define R_ADC_B0_ADTRGEXT0_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT0_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT0_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT0_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT1 ======================================================= */ + #define R_ADC_B0_ADTRGEXT1_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT1_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT1_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT1_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT2 ======================================================= */ + #define R_ADC_B0_ADTRGEXT2_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT2_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT2_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT2_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT3 ======================================================= */ + #define R_ADC_B0_ADTRGEXT3_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT3_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT3_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT3_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT4 ======================================================= */ + #define R_ADC_B0_ADTRGEXT4_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT4_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT4_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT4_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT5 ======================================================= */ + #define R_ADC_B0_ADTRGEXT5_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT5_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT5_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT5_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT6 ======================================================= */ + #define R_ADC_B0_ADTRGEXT6_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT6_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT6_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT6_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT7 ======================================================= */ + #define R_ADC_B0_ADTRGEXT7_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT7_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT7_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT7_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT8 ======================================================= */ + #define R_ADC_B0_ADTRGEXT8_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT8_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT8_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT8_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGELC0 ======================================================= */ + #define R_ADC_B0_ADTRGELC0_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC0_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC1 ======================================================= */ + #define R_ADC_B0_ADTRGELC1_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC1_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC2 ======================================================= */ + #define R_ADC_B0_ADTRGELC2_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC2_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC3 ======================================================= */ + #define R_ADC_B0_ADTRGELC3_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC3_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC4 ======================================================= */ + #define R_ADC_B0_ADTRGELC4_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC4_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC5 ======================================================= */ + #define R_ADC_B0_ADTRGELC5_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC5_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC6 ======================================================= */ + #define R_ADC_B0_ADTRGELC6_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC6_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC7 ======================================================= */ + #define R_ADC_B0_ADTRGELC7_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC7_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC8 ======================================================= */ + #define R_ADC_B0_ADTRGELC8_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC8_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGGPT0 ======================================================= */ + #define R_ADC_B0_ADTRGGPT0_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT0_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT0_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT0_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT1 ======================================================= */ + #define R_ADC_B0_ADTRGGPT1_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT1_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT1_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT1_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT2 ======================================================= */ + #define R_ADC_B0_ADTRGGPT2_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT2_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT2_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT2_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT3 ======================================================= */ + #define R_ADC_B0_ADTRGGPT3_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT3_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT3_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT3_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT4 ======================================================= */ + #define R_ADC_B0_ADTRGGPT4_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT4_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT4_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT4_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT5 ======================================================= */ + #define R_ADC_B0_ADTRGGPT5_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT5_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT5_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT5_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT6 ======================================================= */ + #define R_ADC_B0_ADTRGGPT6_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT6_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT6_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT6_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT7 ======================================================= */ + #define R_ADC_B0_ADTRGGPT7_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT7_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT7_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT7_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT8 ======================================================= */ + #define R_ADC_B0_ADTRGGPT8_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT8_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT8_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT8_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGDLR0 ======================================================= */ + #define R_ADC_B0_ADTRGDLR0_TRGDLY0_Pos (0UL) /*!< TRGDLY0 (Bit 0) */ + #define R_ADC_B0_ADTRGDLR0_TRGDLY0_Msk (0xffUL) /*!< TRGDLY0 (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADTRGDLR0_TRGDLY1_Pos (16UL) /*!< TRGDLY1 (Bit 16) */ + #define R_ADC_B0_ADTRGDLR0_TRGDLY1_Msk (0xff0000UL) /*!< TRGDLY1 (Bitfield-Mask: 0xff) */ +/* ======================================================= ADTRGDLR1 ======================================================= */ + #define R_ADC_B0_ADTRGDLR1_TRGDLY2_Pos (0UL) /*!< TRGDLY2 (Bit 0) */ + #define R_ADC_B0_ADTRGDLR1_TRGDLY2_Msk (0xffUL) /*!< TRGDLY2 (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADTRGDLR1_TRGDLY3_Pos (16UL) /*!< TRGDLY3 (Bit 16) */ + #define R_ADC_B0_ADTRGDLR1_TRGDLY3_Msk (0xff0000UL) /*!< TRGDLY3 (Bitfield-Mask: 0xff) */ +/* ======================================================= ADTRGDLR2 ======================================================= */ + #define R_ADC_B0_ADTRGDLR2_TRGDLY4_Pos (0UL) /*!< TRGDLY4 (Bit 0) */ + #define R_ADC_B0_ADTRGDLR2_TRGDLY4_Msk (0xffUL) /*!< TRGDLY4 (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADTRGDLR2_TRGDLY5_Pos (16UL) /*!< TRGDLY5 (Bit 16) */ + #define R_ADC_B0_ADTRGDLR2_TRGDLY5_Msk (0xff0000UL) /*!< TRGDLY5 (Bitfield-Mask: 0xff) */ +/* ======================================================= ADTRGDLR3 ======================================================= */ + #define R_ADC_B0_ADTRGDLR3_TRGDLY6_Pos (0UL) /*!< TRGDLY6 (Bit 0) */ + #define R_ADC_B0_ADTRGDLR3_TRGDLY6_Msk (0xffUL) /*!< TRGDLY6 (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADTRGDLR3_TRGDLY7_Pos (16UL) /*!< TRGDLY7 (Bit 16) */ + #define R_ADC_B0_ADTRGDLR3_TRGDLY7_Msk (0xff0000UL) /*!< TRGDLY7 (Bitfield-Mask: 0xff) */ +/* ======================================================= ADTRGDLR4 ======================================================= */ + #define R_ADC_B0_ADTRGDLR4_TRGDLY8_Pos (0UL) /*!< TRGDLY8 (Bit 0) */ + #define R_ADC_B0_ADTRGDLR4_TRGDLY8_Msk (0xffUL) /*!< TRGDLY8 (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR0 ======================================================== */ + #define R_ADC_B0_ADSGDCR0_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR0_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR0_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR0_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR0_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR0_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR0_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR0_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR0_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR0_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR1 ======================================================== */ + #define R_ADC_B0_ADSGDCR1_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR1_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR1_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR1_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR1_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR1_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR1_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR1_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR1_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR1_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR2 ======================================================== */ + #define R_ADC_B0_ADSGDCR2_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR2_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR2_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR2_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR2_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR2_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR2_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR2_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR2_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR2_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR3 ======================================================== */ + #define R_ADC_B0_ADSGDCR3_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR3_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR3_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR3_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR3_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR3_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR3_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR3_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR3_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR3_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR4 ======================================================== */ + #define R_ADC_B0_ADSGDCR4_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR4_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR4_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR4_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR4_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR4_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR4_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR4_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR4_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR4_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR5 ======================================================== */ + #define R_ADC_B0_ADSGDCR5_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR5_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR5_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR5_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR5_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR5_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR5_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR5_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR5_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR5_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR6 ======================================================== */ + #define R_ADC_B0_ADSGDCR6_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR6_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR6_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR6_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR6_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR6_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR6_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR6_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR6_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR6_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR7 ======================================================== */ + #define R_ADC_B0_ADSGDCR7_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR7_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR7_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR7_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR7_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR7_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR7_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR7_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR7_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR7_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR8 ======================================================== */ + #define R_ADC_B0_ADSGDCR8_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR8_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR8_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR8_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR8_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR8_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR8_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR8_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR8_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR8_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTR0 ======================================================== */ + #define R_ADC_B0_ADSSTR0_SST0_Pos (0UL) /*!< SST0 (Bit 0) */ + #define R_ADC_B0_ADSSTR0_SST0_Msk (0x3ffUL) /*!< SST0 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR0_SST1_Pos (16UL) /*!< SST1 (Bit 16) */ + #define R_ADC_B0_ADSSTR0_SST1_Msk (0x3ff0000UL) /*!< SST1 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR1 ======================================================== */ + #define R_ADC_B0_ADSSTR1_SST2_Pos (0UL) /*!< SST2 (Bit 0) */ + #define R_ADC_B0_ADSSTR1_SST2_Msk (0x3ffUL) /*!< SST2 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR1_SST3_Pos (16UL) /*!< SST3 (Bit 16) */ + #define R_ADC_B0_ADSSTR1_SST3_Msk (0x3ff0000UL) /*!< SST3 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR2 ======================================================== */ + #define R_ADC_B0_ADSSTR2_SST4_Pos (0UL) /*!< SST4 (Bit 0) */ + #define R_ADC_B0_ADSSTR2_SST4_Msk (0x3ffUL) /*!< SST4 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR2_SST5_Pos (16UL) /*!< SST5 (Bit 16) */ + #define R_ADC_B0_ADSSTR2_SST5_Msk (0x3ff0000UL) /*!< SST5 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR3 ======================================================== */ + #define R_ADC_B0_ADSSTR3_SST6_Pos (0UL) /*!< SST6 (Bit 0) */ + #define R_ADC_B0_ADSSTR3_SST6_Msk (0x3ffUL) /*!< SST6 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR3_SST7_Pos (16UL) /*!< SST7 (Bit 16) */ + #define R_ADC_B0_ADSSTR3_SST7_Msk (0x3ff0000UL) /*!< SST7 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR4 ======================================================== */ + #define R_ADC_B0_ADSSTR4_SST8_Pos (0UL) /*!< SST8 (Bit 0) */ + #define R_ADC_B0_ADSSTR4_SST8_Msk (0x3ffUL) /*!< SST8 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR4_SST9_Pos (16UL) /*!< SST9 (Bit 16) */ + #define R_ADC_B0_ADSSTR4_SST9_Msk (0x3ff0000UL) /*!< SST9 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR5 ======================================================== */ + #define R_ADC_B0_ADSSTR5_SST10_Pos (0UL) /*!< SST10 (Bit 0) */ + #define R_ADC_B0_ADSSTR5_SST10_Msk (0x3ffUL) /*!< SST10 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR5_SST11_Pos (16UL) /*!< SST11 (Bit 16) */ + #define R_ADC_B0_ADSSTR5_SST11_Msk (0x3ff0000UL) /*!< SST11 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR6 ======================================================== */ + #define R_ADC_B0_ADSSTR6_SST12_Pos (0UL) /*!< SST12 (Bit 0) */ + #define R_ADC_B0_ADSSTR6_SST12_Msk (0x3ffUL) /*!< SST12 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR6_SST13_Pos (16UL) /*!< SST13 (Bit 16) */ + #define R_ADC_B0_ADSSTR6_SST13_Msk (0x3ff0000UL) /*!< SST13 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR7 ======================================================== */ + #define R_ADC_B0_ADSSTR7_SST14_Pos (0UL) /*!< SST14 (Bit 0) */ + #define R_ADC_B0_ADSSTR7_SST14_Msk (0x3ffUL) /*!< SST14 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR7_SST15_Pos (16UL) /*!< SST15 (Bit 16) */ + #define R_ADC_B0_ADSSTR7_SST15_Msk (0x3ff0000UL) /*!< SST15 (Bitfield-Mask: 0x3ff) */ +/* ======================================================= ADCNVSTR ======================================================== */ + #define R_ADC_B0_ADCNVSTR_CST0_Pos (0UL) /*!< CST0 (Bit 0) */ + #define R_ADC_B0_ADCNVSTR_CST0_Msk (0x3fUL) /*!< CST0 (Bitfield-Mask: 0x3f) */ + #define R_ADC_B0_ADCNVSTR_CST1_Pos (8UL) /*!< CST1 (Bit 8) */ + #define R_ADC_B0_ADCNVSTR_CST1_Msk (0x3f00UL) /*!< CST1 (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADCALSTCR ======================================================= */ + #define R_ADC_B0_ADCALSTCR_CALADSST_Pos (0UL) /*!< CALADSST (Bit 0) */ + #define R_ADC_B0_ADCALSTCR_CALADSST_Msk (0x3ffUL) /*!< CALADSST (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADCALSTCR_CALADCST_Pos (16UL) /*!< CALADCST (Bit 16) */ + #define R_ADC_B0_ADCALSTCR_CALADCST_Msk (0x3f0000UL) /*!< CALADCST (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADSHCR0 ======================================================== */ + #define R_ADC_B0_ADSHCR0_SHEN_Pos (0UL) /*!< SHEN (Bit 0) */ + #define R_ADC_B0_ADSHCR0_SHEN_Msk (0x1UL) /*!< SHEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSHCR0_SHMD_Pos (16UL) /*!< SHMD (Bit 16) */ + #define R_ADC_B0_ADSHCR0_SHMD_Msk (0x10000UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSHSTR0 ======================================================== */ + #define R_ADC_B0_ADSHSTR0_SHSST_Pos (0UL) /*!< SHSST (Bit 0) */ + #define R_ADC_B0_ADSHSTR0_SHSST_Msk (0xffUL) /*!< SHSST (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADSHSTR0_SHHST_Pos (16UL) /*!< SHHST (Bit 16) */ + #define R_ADC_B0_ADSHSTR0_SHHST_Msk (0x70000UL) /*!< SHHST (Bitfield-Mask: 0x07) */ +/* ======================================================== ADSHCR1 ======================================================== */ + #define R_ADC_B0_ADSHCR1_SHEN_Pos (0UL) /*!< SHEN (Bit 0) */ + #define R_ADC_B0_ADSHCR1_SHEN_Msk (0x1UL) /*!< SHEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSHCR1_SHMD_Pos (16UL) /*!< SHMD (Bit 16) */ + #define R_ADC_B0_ADSHCR1_SHMD_Msk (0x10000UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSHSTR1 ======================================================== */ + #define R_ADC_B0_ADSHSTR1_SHSST_Pos (0UL) /*!< SHSST (Bit 0) */ + #define R_ADC_B0_ADSHSTR1_SHSST_Msk (0xffUL) /*!< SHSST (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADSHSTR1_SHHST_Pos (16UL) /*!< SHHST (Bit 16) */ + #define R_ADC_B0_ADSHSTR1_SHHST_Msk (0x70000UL) /*!< SHHST (Bitfield-Mask: 0x07) */ +/* ======================================================= ADCALSHCR ======================================================= */ + #define R_ADC_B0_ADCALSHCR_CALSHSST_Pos (0UL) /*!< CALSHSST (Bit 0) */ + #define R_ADC_B0_ADCALSHCR_CALSHSST_Msk (0xffUL) /*!< CALSHSST (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADCALSHCR_CALSHHST_Pos (16UL) /*!< CALSHHST (Bit 16) */ + #define R_ADC_B0_ADCALSHCR_CALSHHST_Msk (0x70000UL) /*!< CALSHHST (Bitfield-Mask: 0x07) */ +/* ======================================================== ADREFCR ======================================================== */ + #define R_ADC_B0_ADREFCR_VDE_Pos (0UL) /*!< VDE (Bit 0) */ + #define R_ADC_B0_ADREFCR_VDE_Msk (0x1UL) /*!< VDE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADDFSR0 ======================================================== */ + #define R_ADC_B0_ADDFSR0_DFSEL0_Pos (0UL) /*!< DFSEL0 (Bit 0) */ + #define R_ADC_B0_ADDFSR0_DFSEL0_Msk (0x3UL) /*!< DFSEL0 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDFSR0_DFSEL1_Pos (8UL) /*!< DFSEL1 (Bit 8) */ + #define R_ADC_B0_ADDFSR0_DFSEL1_Msk (0x300UL) /*!< DFSEL1 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDFSR0_DFSEL2_Pos (16UL) /*!< DFSEL2 (Bit 16) */ + #define R_ADC_B0_ADDFSR0_DFSEL2_Msk (0x30000UL) /*!< DFSEL2 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDFSR0_DFSEL3_Pos (24UL) /*!< DFSEL3 (Bit 24) */ + #define R_ADC_B0_ADDFSR0_DFSEL3_Msk (0x3000000UL) /*!< DFSEL3 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADDFSR1 ======================================================== */ + #define R_ADC_B0_ADDFSR1_DFSEL0_Pos (0UL) /*!< DFSEL0 (Bit 0) */ + #define R_ADC_B0_ADDFSR1_DFSEL0_Msk (0x3UL) /*!< DFSEL0 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDFSR1_DFSEL1_Pos (8UL) /*!< DFSEL1 (Bit 8) */ + #define R_ADC_B0_ADDFSR1_DFSEL1_Msk (0x300UL) /*!< DFSEL1 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDFSR1_DFSEL2_Pos (16UL) /*!< DFSEL2 (Bit 16) */ + #define R_ADC_B0_ADDFSR1_DFSEL2_Msk (0x30000UL) /*!< DFSEL2 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDFSR1_DFSEL3_Pos (24UL) /*!< DFSEL3 (Bit 24) */ + #define R_ADC_B0_ADDFSR1_DFSEL3_Msk (0x3000000UL) /*!< DFSEL3 (Bitfield-Mask: 0x03) */ +/* ======================================================= ADUOFTR0 ======================================================== */ + #define R_ADC_B0_ADUOFTR0_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR0_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR1 ======================================================== */ + #define R_ADC_B0_ADUOFTR1_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR1_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR2 ======================================================== */ + #define R_ADC_B0_ADUOFTR2_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR2_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR3 ======================================================== */ + #define R_ADC_B0_ADUOFTR3_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR3_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR4 ======================================================== */ + #define R_ADC_B0_ADUOFTR4_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR4_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR5 ======================================================== */ + #define R_ADC_B0_ADUOFTR5_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR5_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR6 ======================================================== */ + #define R_ADC_B0_ADUOFTR6_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR6_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR7 ======================================================== */ + #define R_ADC_B0_ADUOFTR7_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR7_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADUGTR0 ======================================================== */ + #define R_ADC_B0_ADUGTR0_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR0_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR0_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR0_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ======================================================== ADUGTR1 ======================================================== */ + #define R_ADC_B0_ADUGTR1_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR1_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR1_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR1_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ======================================================== ADUGTR2 ======================================================== */ + #define R_ADC_B0_ADUGTR2_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR2_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR2_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR2_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ======================================================== ADUGTR3 ======================================================== */ + #define R_ADC_B0_ADUGTR3_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR3_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR3_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR3_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ======================================================== ADUGTR4 ======================================================== */ + #define R_ADC_B0_ADUGTR4_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR4_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR4_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR4_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ======================================================== ADUGTR5 ======================================================== */ + #define R_ADC_B0_ADUGTR5_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR5_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR5_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR5_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ======================================================== ADUGTR6 ======================================================== */ + #define R_ADC_B0_ADUGTR6_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR6_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR6_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR6_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ======================================================== ADUGTR7 ======================================================== */ + #define R_ADC_B0_ADUGTR7_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR7_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR7_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR7_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ====================================================== ADLIMINTCR ======================================================= */ + #define R_ADC_B0_ADLIMINTCR_LIMIEn_Pos (0UL) /*!< LIMIEn (Bit 0) */ + #define R_ADC_B0_ADLIMINTCR_LIMIEn_Msk (0x1ffUL) /*!< LIMIEn (Bitfield-Mask: 0x1ff) */ +/* ======================================================= ADLIMTR0 ======================================================== */ + #define R_ADC_B0_ADLIMTR0_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR0_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR0_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR0_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR1 ======================================================== */ + #define R_ADC_B0_ADLIMTR1_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR1_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR1_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR1_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR2 ======================================================== */ + #define R_ADC_B0_ADLIMTR2_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR2_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR2_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR2_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR3 ======================================================== */ + #define R_ADC_B0_ADLIMTR3_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR3_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR3_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR3_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR4 ======================================================== */ + #define R_ADC_B0_ADLIMTR4_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR4_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR4_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR4_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR5 ======================================================== */ + #define R_ADC_B0_ADLIMTR5_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR5_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR5_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR5_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR6 ======================================================== */ + #define R_ADC_B0_ADLIMTR6_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR6_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR6_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR6_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR7 ======================================================== */ + #define R_ADC_B0_ADLIMTR7_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR7_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR7_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR7_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPENR ======================================================== */ + #define R_ADC_B0_ADCMPENR_CMPENn_Pos (0UL) /*!< CMPENn (Bit 0) */ + #define R_ADC_B0_ADCMPENR_CMPENn_Msk (0xffUL) /*!< CMPENn (Bitfield-Mask: 0xff) */ +/* ====================================================== ADCMPINTCR ======================================================= */ + #define R_ADC_B0_ADCMPINTCR_CMPIEn_Pos (0UL) /*!< CMPIEn (Bit 0) */ + #define R_ADC_B0_ADCMPINTCR_CMPIEn_Msk (0xfUL) /*!< CMPIEn (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCCMPCR0 ======================================================= */ + #define R_ADC_B0_ADCCMPCR0_CCMPCND_Pos (0UL) /*!< CCMPCND (Bit 0) */ + #define R_ADC_B0_ADCCMPCR0_CCMPCND_Msk (0x3UL) /*!< CCMPCND (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCCMPCR0_CCMPTBLm_Pos (16UL) /*!< CCMPTBLm (Bit 16) */ + #define R_ADC_B0_ADCCMPCR0_CCMPTBLm_Msk (0xff0000UL) /*!< CCMPTBLm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADCCMPCR1 ======================================================= */ + #define R_ADC_B0_ADCCMPCR1_CCMPCND_Pos (0UL) /*!< CCMPCND (Bit 0) */ + #define R_ADC_B0_ADCCMPCR1_CCMPCND_Msk (0x3UL) /*!< CCMPCND (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCCMPCR1_CCMPTBLm_Pos (16UL) /*!< CCMPTBLm (Bit 16) */ + #define R_ADC_B0_ADCCMPCR1_CCMPTBLm_Msk (0xff0000UL) /*!< CCMPTBLm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADCMPMDR0 ======================================================= */ + #define R_ADC_B0_ADCMPMDR0_CMPMD0_Pos (0UL) /*!< CMPMD0 (Bit 0) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD0_Msk (0x3UL) /*!< CMPMD0 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD1_Pos (8UL) /*!< CMPMD1 (Bit 8) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD1_Msk (0x300UL) /*!< CMPMD1 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD2_Pos (16UL) /*!< CMPMD2 (Bit 16) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD2_Msk (0x30000UL) /*!< CMPMD2 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD3_Pos (24UL) /*!< CMPMD3 (Bit 24) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD3_Msk (0x3000000UL) /*!< CMPMD3 (Bitfield-Mask: 0x03) */ +/* ======================================================= ADCMPMDR1 ======================================================= */ + #define R_ADC_B0_ADCMPMDR1_CMPMD4_Pos (0UL) /*!< CMPMD4 (Bit 0) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD4_Msk (0x3UL) /*!< CMPMD4 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD5_Pos (8UL) /*!< CMPMD5 (Bit 8) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD5_Msk (0x300UL) /*!< CMPMD5 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD6_Pos (16UL) /*!< CMPMD6 (Bit 16) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD6_Msk (0x30000UL) /*!< CMPMD6 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD7_Pos (24UL) /*!< CMPMD7 (Bit 24) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD7_Msk (0x3000000UL) /*!< CMPMD7 (Bitfield-Mask: 0x03) */ +/* ======================================================= ADCMPTBR0 ======================================================= */ + #define R_ADC_B0_ADCMPTBR0_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR0_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR0_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR0_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR1 ======================================================= */ + #define R_ADC_B0_ADCMPTBR1_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR1_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR1_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR1_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR2 ======================================================= */ + #define R_ADC_B0_ADCMPTBR2_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR2_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR2_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR2_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR3 ======================================================= */ + #define R_ADC_B0_ADCMPTBR3_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR3_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR3_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR3_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR4 ======================================================= */ + #define R_ADC_B0_ADCMPTBR4_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR4_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR4_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR4_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR5 ======================================================= */ + #define R_ADC_B0_ADCMPTBR5_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR5_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR5_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR5_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR6 ======================================================= */ + #define R_ADC_B0_ADCMPTBR6_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR6_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR6_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR6_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR7 ======================================================= */ + #define R_ADC_B0_ADCMPTBR7_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR7_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR7_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR7_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADFIFOCR ======================================================== */ + #define R_ADC_B0_ADFIFOCR_FIFOEN0_Pos (0UL) /*!< FIFOEN0 (Bit 0) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN0_Msk (0x1UL) /*!< FIFOEN0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN1_Pos (1UL) /*!< FIFOEN1 (Bit 1) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN1_Msk (0x2UL) /*!< FIFOEN1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN2_Pos (2UL) /*!< FIFOEN2 (Bit 2) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN2_Msk (0x4UL) /*!< FIFOEN2 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN3_Pos (3UL) /*!< FIFOEN3 (Bit 3) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN3_Msk (0x8UL) /*!< FIFOEN3 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN4_Pos (4UL) /*!< FIFOEN4 (Bit 4) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN4_Msk (0x10UL) /*!< FIFOEN4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN5_Pos (5UL) /*!< FIFOEN5 (Bit 5) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN5_Msk (0x20UL) /*!< FIFOEN5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN6_Pos (6UL) /*!< FIFOEN6 (Bit 6) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN6_Msk (0x40UL) /*!< FIFOEN6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN7_Pos (7UL) /*!< FIFOEN7 (Bit 7) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN7_Msk (0x80UL) /*!< FIFOEN7 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN8_Pos (8UL) /*!< FIFOEN8 (Bit 8) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN8_Msk (0x100UL) /*!< FIFOEN8 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADFIFOINTCR ====================================================== */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE0_Pos (0UL) /*!< FIFOIE0 (Bit 0) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE0_Msk (0x1UL) /*!< FIFOIE0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE1_Pos (1UL) /*!< FIFOIE1 (Bit 1) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE1_Msk (0x2UL) /*!< FIFOIE1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE2_Pos (2UL) /*!< FIFOIE2 (Bit 2) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE2_Msk (0x4UL) /*!< FIFOIE2 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE3_Pos (3UL) /*!< FIFOIE3 (Bit 3) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE3_Msk (0x8UL) /*!< FIFOIE3 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE4_Pos (4UL) /*!< FIFOIE4 (Bit 4) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE4_Msk (0x10UL) /*!< FIFOIE4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE5_Pos (5UL) /*!< FIFOIE5 (Bit 5) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE5_Msk (0x20UL) /*!< FIFOIE5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE6_Pos (6UL) /*!< FIFOIE6 (Bit 6) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE6_Msk (0x40UL) /*!< FIFOIE6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE7_Pos (7UL) /*!< FIFOIE7 (Bit 7) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE7_Msk (0x80UL) /*!< FIFOIE7 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE8_Pos (8UL) /*!< FIFOIE8 (Bit 8) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE8_Msk (0x100UL) /*!< FIFOIE8 (Bitfield-Mask: 0x01) */ +/* ===================================================== ADFIFOINTLR0 ====================================================== */ + #define R_ADC_B0_ADFIFOINTLR0_FIFOILV0_Pos (0UL) /*!< FIFOILV0 (Bit 0) */ + #define R_ADC_B0_ADFIFOINTLR0_FIFOILV0_Msk (0xfUL) /*!< FIFOILV0 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOINTLR0_FIFOILV1_Pos (16UL) /*!< FIFOILV1 (Bit 16) */ + #define R_ADC_B0_ADFIFOINTLR0_FIFOILV1_Msk (0xf0000UL) /*!< FIFOILV1 (Bitfield-Mask: 0x0f) */ +/* ===================================================== ADFIFOINTLR1 ====================================================== */ + #define R_ADC_B0_ADFIFOINTLR1_FIFOILV2_Pos (0UL) /*!< FIFOILV2 (Bit 0) */ + #define R_ADC_B0_ADFIFOINTLR1_FIFOILV2_Msk (0xfUL) /*!< FIFOILV2 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOINTLR1_FIFOILV3_Pos (16UL) /*!< FIFOILV3 (Bit 16) */ + #define R_ADC_B0_ADFIFOINTLR1_FIFOILV3_Msk (0xf0000UL) /*!< FIFOILV3 (Bitfield-Mask: 0x0f) */ +/* ===================================================== ADFIFOINTLR2 ====================================================== */ + #define R_ADC_B0_ADFIFOINTLR2_FIFOILV4_Pos (0UL) /*!< FIFOILV4 (Bit 0) */ + #define R_ADC_B0_ADFIFOINTLR2_FIFOILV4_Msk (0xfUL) /*!< FIFOILV4 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOINTLR2_FIFOILV5_Pos (16UL) /*!< FIFOILV5 (Bit 16) */ + #define R_ADC_B0_ADFIFOINTLR2_FIFOILV5_Msk (0xf0000UL) /*!< FIFOILV5 (Bitfield-Mask: 0x0f) */ +/* ===================================================== ADFIFOINTLR3 ====================================================== */ + #define R_ADC_B0_ADFIFOINTLR3_FIFOILV6_Pos (0UL) /*!< FIFOILV6 (Bit 0) */ + #define R_ADC_B0_ADFIFOINTLR3_FIFOILV6_Msk (0xfUL) /*!< FIFOILV6 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOINTLR3_FIFOILV7_Pos (16UL) /*!< FIFOILV7 (Bit 16) */ + #define R_ADC_B0_ADFIFOINTLR3_FIFOILV7_Msk (0xf0000UL) /*!< FIFOILV7 (Bitfield-Mask: 0x0f) */ +/* ===================================================== ADFIFOINTLR4 ====================================================== */ + #define R_ADC_B0_ADFIFOINTLR4_FIFOILV8_Pos (0UL) /*!< FIFOILV8 (Bit 0) */ + #define R_ADC_B0_ADFIFOINTLR4_FIFOILV8_Msk (0xfUL) /*!< FIFOILV8 (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR0 ======================================================== */ + #define R_ADC_B0_ADCHCR0_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR0_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR0_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR0_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR0_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR0_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR0_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR0_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR1 ======================================================== */ + #define R_ADC_B0_ADCHCR1_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR1_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR1_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR1_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR1_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR1_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR1_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR1_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR2 ======================================================== */ + #define R_ADC_B0_ADCHCR2_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR2_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR2_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR2_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR2_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR2_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR2_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR2_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR3 ======================================================== */ + #define R_ADC_B0_ADCHCR3_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR3_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR3_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR3_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR3_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR3_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR3_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR3_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR4 ======================================================== */ + #define R_ADC_B0_ADCHCR4_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR4_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR4_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR4_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR4_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR4_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR4_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR4_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR5 ======================================================== */ + #define R_ADC_B0_ADCHCR5_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR5_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR5_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR5_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR5_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR5_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR5_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR5_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR6 ======================================================== */ + #define R_ADC_B0_ADCHCR6_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR6_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR6_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR6_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR6_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR6_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR6_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR6_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR7 ======================================================== */ + #define R_ADC_B0_ADCHCR7_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR7_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR7_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR7_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR7_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR7_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR7_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR7_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR8 ======================================================== */ + #define R_ADC_B0_ADCHCR8_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR8_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR8_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR8_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR8_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR8_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR8_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR8_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR9 ======================================================== */ + #define R_ADC_B0_ADCHCR9_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR9_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR9_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR9_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR9_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR9_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR9_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR9_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR10 ======================================================== */ + #define R_ADC_B0_ADCHCR10_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR10_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR10_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR10_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR10_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR10_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR10_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR10_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR11 ======================================================== */ + #define R_ADC_B0_ADCHCR11_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR11_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR11_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR11_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR11_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR11_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR11_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR11_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR12 ======================================================== */ + #define R_ADC_B0_ADCHCR12_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR12_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR12_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR12_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR12_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR12_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR12_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR12_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR13 ======================================================== */ + #define R_ADC_B0_ADCHCR13_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR13_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR13_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR13_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR13_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR13_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR13_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR13_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR14 ======================================================== */ + #define R_ADC_B0_ADCHCR14_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR14_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR14_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR14_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR14_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR14_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR14_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR14_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR15 ======================================================== */ + #define R_ADC_B0_ADCHCR15_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR15_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR15_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR15_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR15_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR15_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR15_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR15_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR16 ======================================================== */ + #define R_ADC_B0_ADCHCR16_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR16_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR16_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR16_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR16_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR16_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR16_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR16_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR17 ======================================================== */ + #define R_ADC_B0_ADCHCR17_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR17_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR17_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR17_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR17_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR17_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR17_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR17_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR18 ======================================================== */ + #define R_ADC_B0_ADCHCR18_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR18_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR18_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR18_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR18_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR18_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR18_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR18_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR19 ======================================================== */ + #define R_ADC_B0_ADCHCR19_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR19_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR19_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR19_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR19_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR19_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR19_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR19_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR20 ======================================================== */ + #define R_ADC_B0_ADCHCR20_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR20_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR20_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR20_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR20_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR20_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR20_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR20_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR21 ======================================================== */ + #define R_ADC_B0_ADCHCR21_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR21_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR21_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR21_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR21_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR21_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR21_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR21_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR22 ======================================================== */ + #define R_ADC_B0_ADCHCR22_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR22_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR22_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR22_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR22_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR22_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR22_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR22_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR23 ======================================================== */ + #define R_ADC_B0_ADCHCR23_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR23_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR23_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR23_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR23_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR23_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR23_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR23_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR24 ======================================================== */ + #define R_ADC_B0_ADCHCR24_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR24_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR24_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR24_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR24_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR24_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR24_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR24_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR25 ======================================================== */ + #define R_ADC_B0_ADCHCR25_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR25_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR25_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR25_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR25_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR25_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR25_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR25_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR26 ======================================================== */ + #define R_ADC_B0_ADCHCR26_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR26_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR26_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR26_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR26_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR26_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR26_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR26_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR27 ======================================================== */ + #define R_ADC_B0_ADCHCR27_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR27_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR27_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR27_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR27_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR27_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR27_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR27_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR28 ======================================================== */ + #define R_ADC_B0_ADCHCR28_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR28_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR28_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR28_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR28_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR28_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR28_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR28_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR29 ======================================================== */ + #define R_ADC_B0_ADCHCR29_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR29_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR29_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR29_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR29_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR29_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR29_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR29_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR30 ======================================================== */ + #define R_ADC_B0_ADCHCR30_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR30_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR30_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR30_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR30_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR30_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR30_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR30_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR31 ======================================================== */ + #define R_ADC_B0_ADCHCR31_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR31_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR31_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR31_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR31_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR31_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR31_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR31_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR32 ======================================================== */ + #define R_ADC_B0_ADCHCR32_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR32_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR32_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR32_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR32_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR32_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR32_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR32_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA0 ======================================================= */ + #define R_ADC_B0_ADDOPCRA0_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA0_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA0_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA0_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA0_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA0_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA1 ======================================================= */ + #define R_ADC_B0_ADDOPCRA1_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA1_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA1_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA1_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA1_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA1_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA2 ======================================================= */ + #define R_ADC_B0_ADDOPCRA2_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA2_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA2_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA2_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA2_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA2_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA3 ======================================================= */ + #define R_ADC_B0_ADDOPCRA3_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA3_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA3_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA3_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA3_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA3_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA4 ======================================================= */ + #define R_ADC_B0_ADDOPCRA4_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA4_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA4_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA4_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA4_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA4_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA5 ======================================================= */ + #define R_ADC_B0_ADDOPCRA5_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA5_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA5_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA5_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA5_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA5_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA6 ======================================================= */ + #define R_ADC_B0_ADDOPCRA6_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA6_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA6_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA6_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA6_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA6_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA7 ======================================================= */ + #define R_ADC_B0_ADDOPCRA7_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA7_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA7_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA7_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA7_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA7_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA8 ======================================================= */ + #define R_ADC_B0_ADDOPCRA8_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA8_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA8_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA8_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA8_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA8_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA9 ======================================================= */ + #define R_ADC_B0_ADDOPCRA9_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA9_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA9_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA9_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA9_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA9_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA10 ======================================================= */ + #define R_ADC_B0_ADDOPCRA10_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA10_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA10_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA10_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA10_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA10_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA11 ======================================================= */ + #define R_ADC_B0_ADDOPCRA11_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA11_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA11_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA11_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA11_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA11_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA12 ======================================================= */ + #define R_ADC_B0_ADDOPCRA12_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA12_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA12_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA12_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA12_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA12_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA13 ======================================================= */ + #define R_ADC_B0_ADDOPCRA13_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA13_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA13_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA13_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA13_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA13_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA14 ======================================================= */ + #define R_ADC_B0_ADDOPCRA14_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA14_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA14_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA14_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA14_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA14_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA15 ======================================================= */ + #define R_ADC_B0_ADDOPCRA15_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA15_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA15_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA15_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA15_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA15_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA16 ======================================================= */ + #define R_ADC_B0_ADDOPCRA16_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA16_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA16_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA16_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA16_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA16_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA17 ======================================================= */ + #define R_ADC_B0_ADDOPCRA17_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA17_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA17_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA17_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA17_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA17_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA18 ======================================================= */ + #define R_ADC_B0_ADDOPCRA18_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA18_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA18_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA18_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA18_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA18_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA19 ======================================================= */ + #define R_ADC_B0_ADDOPCRA19_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA19_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA19_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA19_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA19_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA19_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA20 ======================================================= */ + #define R_ADC_B0_ADDOPCRA20_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA20_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA20_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA20_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA20_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA20_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA21 ======================================================= */ + #define R_ADC_B0_ADDOPCRA21_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA21_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA21_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA21_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA21_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA21_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA22 ======================================================= */ + #define R_ADC_B0_ADDOPCRA22_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA22_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA22_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA22_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA22_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA22_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA23 ======================================================= */ + #define R_ADC_B0_ADDOPCRA23_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA23_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA23_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA23_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA23_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA23_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA24 ======================================================= */ + #define R_ADC_B0_ADDOPCRA24_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA24_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA24_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA24_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA24_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA24_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA25 ======================================================= */ + #define R_ADC_B0_ADDOPCRA25_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA25_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA25_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA25_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA25_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA25_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA26 ======================================================= */ + #define R_ADC_B0_ADDOPCRA26_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA26_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA26_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA26_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA26_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA26_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA27 ======================================================= */ + #define R_ADC_B0_ADDOPCRA27_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA27_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA27_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA27_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA27_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA27_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA28 ======================================================= */ + #define R_ADC_B0_ADDOPCRA28_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA28_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA28_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA28_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA28_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA28_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA29 ======================================================= */ + #define R_ADC_B0_ADDOPCRA29_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA29_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA29_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA29_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA29_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA29_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA30 ======================================================= */ + #define R_ADC_B0_ADDOPCRA30_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA30_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA30_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA30_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA30_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA30_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA31 ======================================================= */ + #define R_ADC_B0_ADDOPCRA31_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA31_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA31_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA31_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA31_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA31_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA32 ======================================================= */ + #define R_ADC_B0_ADDOPCRA32_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA32_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA32_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA32_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA32_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA32_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRB0 ======================================================= */ + #define R_ADC_B0_ADDOPCRB0_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB0_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB0_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB0_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB0_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB0_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB1 ======================================================= */ + #define R_ADC_B0_ADDOPCRB1_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB1_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB1_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB1_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB1_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB1_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB2 ======================================================= */ + #define R_ADC_B0_ADDOPCRB2_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB2_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB2_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB2_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB2_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB2_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB3 ======================================================= */ + #define R_ADC_B0_ADDOPCRB3_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB3_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB3_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB3_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB3_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB3_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB4 ======================================================= */ + #define R_ADC_B0_ADDOPCRB4_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB4_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB4_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB4_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB4_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB4_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB5 ======================================================= */ + #define R_ADC_B0_ADDOPCRB5_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB5_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB5_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB5_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB5_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB5_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB6 ======================================================= */ + #define R_ADC_B0_ADDOPCRB6_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB6_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB6_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB6_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB6_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB6_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB7 ======================================================= */ + #define R_ADC_B0_ADDOPCRB7_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB7_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB7_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB7_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB7_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB7_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB8 ======================================================= */ + #define R_ADC_B0_ADDOPCRB8_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB8_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB8_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB8_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB8_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB8_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB9 ======================================================= */ + #define R_ADC_B0_ADDOPCRB9_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB9_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB9_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB9_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB9_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB9_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB10 ======================================================= */ + #define R_ADC_B0_ADDOPCRB10_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB10_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB10_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB10_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB10_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB10_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB11 ======================================================= */ + #define R_ADC_B0_ADDOPCRB11_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB11_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB11_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB11_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB11_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB11_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB12 ======================================================= */ + #define R_ADC_B0_ADDOPCRB12_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB12_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB12_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB12_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB12_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB12_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB13 ======================================================= */ + #define R_ADC_B0_ADDOPCRB13_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB13_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB13_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB13_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB13_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB13_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB14 ======================================================= */ + #define R_ADC_B0_ADDOPCRB14_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB14_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB14_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB14_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB14_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB14_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB15 ======================================================= */ + #define R_ADC_B0_ADDOPCRB15_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB15_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB15_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB15_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB15_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB15_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB16 ======================================================= */ + #define R_ADC_B0_ADDOPCRB16_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB16_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB16_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB16_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB16_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB16_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB17 ======================================================= */ + #define R_ADC_B0_ADDOPCRB17_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB17_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB17_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB17_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB17_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB17_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB18 ======================================================= */ + #define R_ADC_B0_ADDOPCRB18_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB18_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB18_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB18_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB18_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB18_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB19 ======================================================= */ + #define R_ADC_B0_ADDOPCRB19_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB19_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB19_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB19_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB19_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB19_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB20 ======================================================= */ + #define R_ADC_B0_ADDOPCRB20_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB20_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB20_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB20_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB20_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB20_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB21 ======================================================= */ + #define R_ADC_B0_ADDOPCRB21_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB21_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB21_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB21_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB21_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB21_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB22 ======================================================= */ + #define R_ADC_B0_ADDOPCRB22_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB22_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB22_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB22_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB22_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB22_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB23 ======================================================= */ + #define R_ADC_B0_ADDOPCRB23_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB23_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB23_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB23_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB23_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB23_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB24 ======================================================= */ + #define R_ADC_B0_ADDOPCRB24_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB24_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB24_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB24_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB24_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB24_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB25 ======================================================= */ + #define R_ADC_B0_ADDOPCRB25_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB25_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB25_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB25_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB25_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB25_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB26 ======================================================= */ + #define R_ADC_B0_ADDOPCRB26_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB26_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB26_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB26_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB26_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB26_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB27 ======================================================= */ + #define R_ADC_B0_ADDOPCRB27_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB27_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB27_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB27_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB27_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB27_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB28 ======================================================= */ + #define R_ADC_B0_ADDOPCRB28_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB28_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB28_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB28_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB28_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB28_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB29 ======================================================= */ + #define R_ADC_B0_ADDOPCRB29_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB29_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB29_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB29_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB29_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB29_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB30 ======================================================= */ + #define R_ADC_B0_ADDOPCRB30_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB30_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB30_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB30_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB30_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB30_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB31 ======================================================= */ + #define R_ADC_B0_ADDOPCRB31_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB31_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB31_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB31_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB31_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB31_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB32 ======================================================= */ + #define R_ADC_B0_ADDOPCRB32_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB32_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB32_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB32_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB32_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB32_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRC0 ======================================================= */ + #define R_ADC_B0_ADDOPCRC0_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC0_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC0_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC0_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC0_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC0_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC1 ======================================================= */ + #define R_ADC_B0_ADDOPCRC1_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC1_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC1_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC1_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC1_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC1_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC2 ======================================================= */ + #define R_ADC_B0_ADDOPCRC2_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC2_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC2_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC2_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC2_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC2_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC3 ======================================================= */ + #define R_ADC_B0_ADDOPCRC3_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC3_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC3_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC3_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC3_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC3_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC4 ======================================================= */ + #define R_ADC_B0_ADDOPCRC4_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC4_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC4_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC4_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC4_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC4_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC5 ======================================================= */ + #define R_ADC_B0_ADDOPCRC5_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC5_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC5_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC5_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC5_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC5_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC6 ======================================================= */ + #define R_ADC_B0_ADDOPCRC6_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC6_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC6_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC6_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC6_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC6_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC7 ======================================================= */ + #define R_ADC_B0_ADDOPCRC7_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC7_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC7_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC7_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC7_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC7_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC8 ======================================================= */ + #define R_ADC_B0_ADDOPCRC8_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC8_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC8_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC8_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC8_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC8_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC9 ======================================================= */ + #define R_ADC_B0_ADDOPCRC9_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC9_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC9_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC9_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC9_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC9_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC10 ======================================================= */ + #define R_ADC_B0_ADDOPCRC10_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC10_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC10_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC10_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC10_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC10_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC11 ======================================================= */ + #define R_ADC_B0_ADDOPCRC11_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC11_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC11_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC11_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC11_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC11_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC12 ======================================================= */ + #define R_ADC_B0_ADDOPCRC12_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC12_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC12_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC12_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC12_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC12_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC13 ======================================================= */ + #define R_ADC_B0_ADDOPCRC13_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC13_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC13_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC13_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC13_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC13_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC14 ======================================================= */ + #define R_ADC_B0_ADDOPCRC14_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC14_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC14_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC14_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC14_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC14_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC15 ======================================================= */ + #define R_ADC_B0_ADDOPCRC15_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC15_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC15_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC15_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC15_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC15_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC16 ======================================================= */ + #define R_ADC_B0_ADDOPCRC16_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC16_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC16_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC16_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC16_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC16_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC17 ======================================================= */ + #define R_ADC_B0_ADDOPCRC17_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC17_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC17_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC17_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC17_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC17_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC18 ======================================================= */ + #define R_ADC_B0_ADDOPCRC18_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC18_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC18_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC18_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC18_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC18_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC19 ======================================================= */ + #define R_ADC_B0_ADDOPCRC19_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC19_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC19_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC19_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC19_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC19_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC20 ======================================================= */ + #define R_ADC_B0_ADDOPCRC20_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC20_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC20_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC20_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC20_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC20_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC21 ======================================================= */ + #define R_ADC_B0_ADDOPCRC21_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC21_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC21_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC21_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC21_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC21_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC22 ======================================================= */ + #define R_ADC_B0_ADDOPCRC22_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC22_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC22_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC22_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC22_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC22_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC23 ======================================================= */ + #define R_ADC_B0_ADDOPCRC23_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC23_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC23_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC23_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC23_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC23_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC24 ======================================================= */ + #define R_ADC_B0_ADDOPCRC24_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC24_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC24_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC24_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC24_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC24_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC25 ======================================================= */ + #define R_ADC_B0_ADDOPCRC25_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC25_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC25_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC25_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC25_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC25_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC26 ======================================================= */ + #define R_ADC_B0_ADDOPCRC26_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC26_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC26_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC26_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC26_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC26_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC27 ======================================================= */ + #define R_ADC_B0_ADDOPCRC27_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC27_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC27_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC27_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC27_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC27_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC28 ======================================================= */ + #define R_ADC_B0_ADDOPCRC28_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC28_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC28_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC28_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC28_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC28_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC29 ======================================================= */ + #define R_ADC_B0_ADDOPCRC29_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC29_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC29_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC29_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC29_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC29_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC30 ======================================================= */ + #define R_ADC_B0_ADDOPCRC30_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC30_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC30_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC30_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC30_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC30_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC31 ======================================================= */ + #define R_ADC_B0_ADDOPCRC31_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC31_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC31_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC31_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC31_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC31_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC32 ======================================================= */ + #define R_ADC_B0_ADDOPCRC32_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC32_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC32_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC32_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC32_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC32_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCALSTR ======================================================== */ + #define R_ADC_B0_ADCALSTR_ADCALST0_Pos (0UL) /*!< ADCALST0 (Bit 0) */ + #define R_ADC_B0_ADCALSTR_ADCALST0_Msk (0x7UL) /*!< ADCALST0 (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADCALSTR_ADCALST1_Pos (8UL) /*!< ADCALST1 (Bit 8) */ + #define R_ADC_B0_ADCALSTR_ADCALST1_Msk (0x700UL) /*!< ADCALST1 (Bitfield-Mask: 0x07) */ +/* ======================================================= ADTRGENR ======================================================== */ + #define R_ADC_B0_ADTRGENR_STTRGENn_Pos (0UL) /*!< STTRGENn (Bit 0) */ + #define R_ADC_B0_ADTRGENR_STTRGENn_Msk (0x1ffUL) /*!< STTRGENn (Bitfield-Mask: 0x1ff) */ +/* ======================================================== ADSYSTR ======================================================== */ + #define R_ADC_B0_ADSYSTR_ADSYSTn_Pos (0UL) /*!< ADSYSTn (Bit 0) */ + #define R_ADC_B0_ADSYSTR_ADSYSTn_Msk (0x1ffUL) /*!< ADSYSTn (Bitfield-Mask: 0x1ff) */ +/* ========================================================= ADSTR ========================================================= */ + #define R_ADC_B0_ADSTR_ADST_Pos (0UL) /*!< ADST (Bit 0) */ + #define R_ADC_B0_ADSTR_ADST_Msk (0x1UL) /*!< ADST (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTOPR ======================================================== */ + #define R_ADC_B0_ADSTOPR_ADSTOP0_Pos (0UL) /*!< ADSTOP0 (Bit 0) */ + #define R_ADC_B0_ADSTOPR_ADSTOP0_Msk (0x1UL) /*!< ADSTOP0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSTOPR_ADSTOP1_Pos (8UL) /*!< ADSTOP1 (Bit 8) */ + #define R_ADC_B0_ADSTOPR_ADSTOP1_Msk (0x100UL) /*!< ADSTOP1 (Bitfield-Mask: 0x01) */ +/* ========================================================= ADSR ========================================================== */ + #define R_ADC_B0_ADSR_ADACT0_Pos (0UL) /*!< ADACT0 (Bit 0) */ + #define R_ADC_B0_ADSR_ADACT0_Msk (0x1UL) /*!< ADACT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSR_ADACT1_Pos (1UL) /*!< ADACT1 (Bit 1) */ + #define R_ADC_B0_ADSR_ADACT1_Msk (0x2UL) /*!< ADACT1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSR_CALACT0_Pos (16UL) /*!< CALACT0 (Bit 16) */ + #define R_ADC_B0_ADSR_CALACT0_Msk (0x10000UL) /*!< CALACT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSR_CALACT1_Pos (17UL) /*!< CALACT1 (Bit 17) */ + #define R_ADC_B0_ADSR_CALACT1_Msk (0x20000UL) /*!< CALACT1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGRSR ========================================================= */ + #define R_ADC_B0_ADGRSR_ACTGRn_Pos (0UL) /*!< ACTGRn (Bit 0) */ + #define R_ADC_B0_ADGRSR_ACTGRn_Msk (0x1ffUL) /*!< ACTGRn (Bitfield-Mask: 0x1ff) */ +/* ======================================================== ADERSR ========================================================= */ + #define R_ADC_B0_ADERSR_ADERF0_Pos (0UL) /*!< ADERF0 (Bit 0) */ + #define R_ADC_B0_ADERSR_ADERF0_Msk (0x1UL) /*!< ADERF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADERSR_ADERF1_Pos (1UL) /*!< ADERF1 (Bit 1) */ + #define R_ADC_B0_ADERSR_ADERF1_Msk (0x2UL) /*!< ADERF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ADERSCR ======================================================== */ + #define R_ADC_B0_ADERSCR_ADERCLR0_Pos (0UL) /*!< ADERCLR0 (Bit 0) */ + #define R_ADC_B0_ADERSCR_ADERCLR0_Msk (0x1UL) /*!< ADERCLR0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADERSCR_ADERCLR1_Pos (1UL) /*!< ADERCLR1 (Bit 1) */ + #define R_ADC_B0_ADERSCR_ADERCLR1_Msk (0x2UL) /*!< ADERCLR1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCALENDSR ======================================================= */ + #define R_ADC_B0_ADCALENDSR_CALENDF0_Pos (0UL) /*!< CALENDF0 (Bit 0) */ + #define R_ADC_B0_ADCALENDSR_CALENDF0_Msk (0x1UL) /*!< CALENDF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCALENDSR_CALENDF1_Pos (1UL) /*!< CALENDF1 (Bit 1) */ + #define R_ADC_B0_ADCALENDSR_CALENDF1_Msk (0x2UL) /*!< CALENDF1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCALENDSCR ====================================================== */ + #define R_ADC_B0_ADCALENDSCR_CALENDC0_Pos (0UL) /*!< CALENDC0 (Bit 0) */ + #define R_ADC_B0_ADCALENDSCR_CALENDC0_Msk (0x1UL) /*!< CALENDC0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCALENDSCR_CALENDC1_Pos (1UL) /*!< CALENDC1 (Bit 1) */ + #define R_ADC_B0_ADCALENDSCR_CALENDC1_Msk (0x2UL) /*!< CALENDC1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADOVFERSR ======================================================= */ + #define R_ADC_B0_ADOVFERSR_ADOVFEF0_Pos (0UL) /*!< ADOVFEF0 (Bit 0) */ + #define R_ADC_B0_ADOVFERSR_ADOVFEF0_Msk (0x1UL) /*!< ADOVFEF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFERSR_ADOVFEF1_Pos (1UL) /*!< ADOVFEF1 (Bit 1) */ + #define R_ADC_B0_ADOVFERSR_ADOVFEF1_Msk (0x2UL) /*!< ADOVFEF1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADOVFCHSR0 ======================================================= */ + #define R_ADC_B0_ADOVFCHSR0_OVFCHFn_Pos (0UL) /*!< OVFCHFn (Bit 0) */ + #define R_ADC_B0_ADOVFCHSR0_OVFCHFn_Msk (0x7fffffUL) /*!< OVFCHFn (Bitfield-Mask: 0x7fffff) */ +/* ======================================================= ADOVFEXSR ======================================================= */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF0_Pos (0UL) /*!< OVFEXF0 (Bit 0) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF0_Msk (0x1UL) /*!< OVFEXF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF1_Pos (1UL) /*!< OVFEXF1 (Bit 1) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF1_Msk (0x2UL) /*!< OVFEXF1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF4_Pos (4UL) /*!< OVFEXF4 (Bit 4) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF4_Msk (0x10UL) /*!< OVFEXF4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF5_Pos (5UL) /*!< OVFEXF5 (Bit 5) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF5_Msk (0x20UL) /*!< OVFEXF5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF6_Pos (6UL) /*!< OVFEXF6 (Bit 6) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF6_Msk (0x40UL) /*!< OVFEXF6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF8_Pos (8UL) /*!< OVFEXF8 (Bit 8) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF8_Msk (0x100UL) /*!< OVFEXF8 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF9_Pos (9UL) /*!< OVFEXF9 (Bit 9) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF9_Msk (0x200UL) /*!< OVFEXF9 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF16_Pos (16UL) /*!< OVFEXF16 (Bit 16) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF16_Msk (0x10000UL) /*!< OVFEXF16 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF17_Pos (17UL) /*!< OVFEXF17 (Bit 17) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF17_Msk (0x20000UL) /*!< OVFEXF17 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF18_Pos (18UL) /*!< OVFEXF18 (Bit 18) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF18_Msk (0x40000UL) /*!< OVFEXF18 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF20_Pos (20UL) /*!< OVFEXF20 (Bit 20) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF20_Msk (0x100000UL) /*!< OVFEXF20 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF21_Pos (21UL) /*!< OVFEXF21 (Bit 21) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF21_Msk (0x200000UL) /*!< OVFEXF21 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF22_Pos (22UL) /*!< OVFEXF22 (Bit 22) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF22_Msk (0x400000UL) /*!< OVFEXF22 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADOVFERSCR ======================================================= */ + #define R_ADC_B0_ADOVFERSCR_ADOVFEC0_Pos (0UL) /*!< ADOVFEC0 (Bit 0) */ + #define R_ADC_B0_ADOVFERSCR_ADOVFEC0_Msk (0x1UL) /*!< ADOVFEC0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFERSCR_ADOVFEC1_Pos (1UL) /*!< ADOVFEC1 (Bit 1) */ + #define R_ADC_B0_ADOVFERSCR_ADOVFEC1_Msk (0x2UL) /*!< ADOVFEC1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADOVFCHSCR0 ====================================================== */ + #define R_ADC_B0_ADOVFCHSCR0_OVFCHCn_Pos (0UL) /*!< OVFCHCn (Bit 0) */ + #define R_ADC_B0_ADOVFCHSCR0_OVFCHCn_Msk (0x7fffffUL) /*!< OVFCHCn (Bitfield-Mask: 0x7fffff) */ +/* ====================================================== ADOVFEXSCR ======================================================= */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC0_Pos (0UL) /*!< OVFEXC0 (Bit 0) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC0_Msk (0x1UL) /*!< OVFEXC0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC1_Pos (1UL) /*!< OVFEXC1 (Bit 1) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC1_Msk (0x2UL) /*!< OVFEXC1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC4_Pos (4UL) /*!< OVFEXC4 (Bit 4) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC4_Msk (0x10UL) /*!< OVFEXC4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC5_Pos (5UL) /*!< OVFEXC5 (Bit 5) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC5_Msk (0x20UL) /*!< OVFEXC5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC6_Pos (6UL) /*!< OVFEXC6 (Bit 6) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC6_Msk (0x40UL) /*!< OVFEXC6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC8_Pos (8UL) /*!< OVFEXC8 (Bit 8) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC8_Msk (0x100UL) /*!< OVFEXC8 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC9_Pos (9UL) /*!< OVFEXC9 (Bit 9) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC9_Msk (0x200UL) /*!< OVFEXC9 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC16_Pos (16UL) /*!< OVFEXC16 (Bit 16) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC16_Msk (0x10000UL) /*!< OVFEXC16 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC17_Pos (17UL) /*!< OVFEXC17 (Bit 17) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC17_Msk (0x20000UL) /*!< OVFEXC17 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC18_Pos (18UL) /*!< OVFEXC18 (Bit 18) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC18_Msk (0x40000UL) /*!< OVFEXC18 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC20_Pos (20UL) /*!< OVFEXC20 (Bit 20) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC20_Msk (0x100000UL) /*!< OVFEXC20 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC21_Pos (21UL) /*!< OVFEXC21 (Bit 21) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC21_Msk (0x200000UL) /*!< OVFEXC21 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC22_Pos (22UL) /*!< OVFEXC22 (Bit 22) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC22_Msk (0x400000UL) /*!< OVFEXC22 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFOSR0 ======================================================= */ + #define R_ADC_B0_ADFIFOSR0_FIFOST0_Pos (0UL) /*!< FIFOST0 (Bit 0) */ + #define R_ADC_B0_ADFIFOSR0_FIFOST0_Msk (0xfUL) /*!< FIFOST0 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOSR0_FIFOST1_Pos (16UL) /*!< FIFOST1 (Bit 16) */ + #define R_ADC_B0_ADFIFOSR0_FIFOST1_Msk (0xf0000UL) /*!< FIFOST1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADFIFOSR1 ======================================================= */ + #define R_ADC_B0_ADFIFOSR1_FIFOST2_Pos (0UL) /*!< FIFOST2 (Bit 0) */ + #define R_ADC_B0_ADFIFOSR1_FIFOST2_Msk (0xfUL) /*!< FIFOST2 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOSR1_FIFOST3_Pos (16UL) /*!< FIFOST3 (Bit 16) */ + #define R_ADC_B0_ADFIFOSR1_FIFOST3_Msk (0xf0000UL) /*!< FIFOST3 (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADFIFOSR2 ======================================================= */ + #define R_ADC_B0_ADFIFOSR2_FIFOST4_Pos (0UL) /*!< FIFOST4 (Bit 0) */ + #define R_ADC_B0_ADFIFOSR2_FIFOST4_Msk (0xfUL) /*!< FIFOST4 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOSR2_FIFOST5_Pos (16UL) /*!< FIFOST5 (Bit 16) */ + #define R_ADC_B0_ADFIFOSR2_FIFOST5_Msk (0xf0000UL) /*!< FIFOST5 (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADFIFOSR3 ======================================================= */ + #define R_ADC_B0_ADFIFOSR3_FIFOST6_Pos (0UL) /*!< FIFOST6 (Bit 0) */ + #define R_ADC_B0_ADFIFOSR3_FIFOST6_Msk (0xfUL) /*!< FIFOST6 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOSR3_FIFOST7_Pos (16UL) /*!< FIFOST7 (Bit 16) */ + #define R_ADC_B0_ADFIFOSR3_FIFOST7_Msk (0xf0000UL) /*!< FIFOST7 (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADFIFOSR4 ======================================================= */ + #define R_ADC_B0_ADFIFOSR4_FIFOST8_Pos (0UL) /*!< FIFOST8 (Bit 0) */ + #define R_ADC_B0_ADFIFOSR4_FIFOST8_Msk (0xfUL) /*!< FIFOST8 (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADFIFODCR ======================================================= */ + #define R_ADC_B0_ADFIFODCR_FIFODCn_Pos (0UL) /*!< FIFODCn (Bit 0) */ + #define R_ADC_B0_ADFIFODCR_FIFODCn_Msk (0x1ffUL) /*!< FIFODCn (Bitfield-Mask: 0x1ff) */ +/* ====================================================== ADFIFOERSR ======================================================= */ + #define R_ADC_B0_ADFIFOERSR_FIFOOVFn_Pos (0UL) /*!< FIFOOVFn (Bit 0) */ + #define R_ADC_B0_ADFIFOERSR_FIFOOVFn_Msk (0x1ffUL) /*!< FIFOOVFn (Bitfield-Mask: 0x1ff) */ + #define R_ADC_B0_ADFIFOERSR_FIFOFLFn_Pos (16UL) /*!< FIFOFLFn (Bit 16) */ + #define R_ADC_B0_ADFIFOERSR_FIFOFLFn_Msk (0x1ff0000UL) /*!< FIFOFLFn (Bitfield-Mask: 0x1ff) */ +/* ====================================================== ADFIFOERSCR ====================================================== */ + #define R_ADC_B0_ADFIFOERSCR_FIFOOVFCn_Pos (0UL) /*!< FIFOOVFCn (Bit 0) */ + #define R_ADC_B0_ADFIFOERSCR_FIFOOVFCn_Msk (0x1ffUL) /*!< FIFOOVFCn (Bitfield-Mask: 0x1ff) */ + #define R_ADC_B0_ADFIFOERSCR_FIFOFLCn_Pos (16UL) /*!< FIFOFLCn (Bit 16) */ + #define R_ADC_B0_ADFIFOERSCR_FIFOFLCn_Msk (0x1ff0000UL) /*!< FIFOFLCn (Bitfield-Mask: 0x1ff) */ +/* ======================================================= ADCMPTBSR ======================================================= */ + #define R_ADC_B0_ADCMPTBSR_CMPTBFn_Pos (0UL) /*!< CMPTBFn (Bit 0) */ + #define R_ADC_B0_ADCMPTBSR_CMPTBFn_Msk (0xffUL) /*!< CMPTBFn (Bitfield-Mask: 0xff) */ +/* ====================================================== ADCMPTBSCR ======================================================= */ + #define R_ADC_B0_ADCMPTBSCR_CMPTBCn_Pos (0UL) /*!< CMPTBCn (Bit 0) */ + #define R_ADC_B0_ADCMPTBSCR_CMPTBCn_Msk (0xffUL) /*!< CMPTBCn (Bitfield-Mask: 0xff) */ +/* ====================================================== ADCMPCHSR0 ======================================================= */ + #define R_ADC_B0_ADCMPCHSR0_CMPCHFn_Pos (0UL) /*!< CMPCHFn (Bit 0) */ + #define R_ADC_B0_ADCMPCHSR0_CMPCHFn_Msk (0x7fffffUL) /*!< CMPCHFn (Bitfield-Mask: 0x7fffff) */ +/* ======================================================= ADCMPEXSR ======================================================= */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF0_Pos (0UL) /*!< CMPEXF0 (Bit 0) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF0_Msk (0x1UL) /*!< CMPEXF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF1_Pos (1UL) /*!< CMPEXF1 (Bit 1) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF1_Msk (0x2UL) /*!< CMPEXF1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF4_Pos (4UL) /*!< CMPEXF4 (Bit 4) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF4_Msk (0x10UL) /*!< CMPEXF4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF5_Pos (5UL) /*!< CMPEXF5 (Bit 5) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF5_Msk (0x20UL) /*!< CMPEXF5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF6_Pos (6UL) /*!< CMPEXF6 (Bit 6) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF6_Msk (0x40UL) /*!< CMPEXF6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF8_Pos (8UL) /*!< CMPEXF8 (Bit 8) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF8_Msk (0x100UL) /*!< CMPEXF8 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF9_Pos (9UL) /*!< CMPEXF9 (Bit 9) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF9_Msk (0x200UL) /*!< CMPEXF9 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF16_Pos (16UL) /*!< CMPEXF16 (Bit 16) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF16_Msk (0x10000UL) /*!< CMPEXF16 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF17_Pos (17UL) /*!< CMPEXF17 (Bit 17) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF17_Msk (0x20000UL) /*!< CMPEXF17 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF18_Pos (18UL) /*!< CMPEXF18 (Bit 18) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF18_Msk (0x40000UL) /*!< CMPEXF18 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF20_Pos (20UL) /*!< CMPEXF20 (Bit 20) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF20_Msk (0x100000UL) /*!< CMPEXF20 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF21_Pos (21UL) /*!< CMPEXF21 (Bit 21) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF21_Msk (0x200000UL) /*!< CMPEXF21 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF22_Pos (22UL) /*!< CMPEXF22 (Bit 22) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF22_Msk (0x400000UL) /*!< CMPEXF22 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCMPCHSCR0 ====================================================== */ + #define R_ADC_B0_ADCMPCHSCR0_CMPCHCn_Pos (0UL) /*!< CMPCHCn (Bit 0) */ + #define R_ADC_B0_ADCMPCHSCR0_CMPCHCn_Msk (0x7fffffUL) /*!< CMPCHCn (Bitfield-Mask: 0x7fffff) */ +/* ====================================================== ADCMPEXSCR ======================================================= */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC0_Pos (0UL) /*!< CMPEXC0 (Bit 0) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC0_Msk (0x1UL) /*!< CMPEXC0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC1_Pos (1UL) /*!< CMPEXC1 (Bit 1) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC1_Msk (0x2UL) /*!< CMPEXC1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC4_Pos (4UL) /*!< CMPEXC4 (Bit 4) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC4_Msk (0x10UL) /*!< CMPEXC4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC5_Pos (5UL) /*!< CMPEXC5 (Bit 5) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC5_Msk (0x20UL) /*!< CMPEXC5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC6_Pos (6UL) /*!< CMPEXC6 (Bit 6) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC6_Msk (0x40UL) /*!< CMPEXC6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC8_Pos (8UL) /*!< CMPEXC8 (Bit 8) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC8_Msk (0x100UL) /*!< CMPEXC8 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC9_Pos (9UL) /*!< CMPEXC9 (Bit 9) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC9_Msk (0x200UL) /*!< CMPEXC9 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC16_Pos (16UL) /*!< CMPEXC16 (Bit 16) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC16_Msk (0x10000UL) /*!< CMPEXC16 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC17_Pos (17UL) /*!< CMPEXC17 (Bit 17) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC17_Msk (0x20000UL) /*!< CMPEXC17 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC18_Pos (18UL) /*!< CMPEXC18 (Bit 18) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC18_Msk (0x40000UL) /*!< CMPEXC18 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC20_Pos (20UL) /*!< CMPEXC20 (Bit 20) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC20_Msk (0x100000UL) /*!< CMPEXC20 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC21_Pos (21UL) /*!< CMPEXC21 (Bit 21) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC21_Msk (0x200000UL) /*!< CMPEXC21 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC22_Pos (22UL) /*!< CMPEXC22 (Bit 22) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC22_Msk (0x400000UL) /*!< CMPEXC22 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADLIMGRSR ======================================================= */ + #define R_ADC_B0_ADLIMGRSR_LIMGRFn_Pos (0UL) /*!< LIMGRFn (Bit 0) */ + #define R_ADC_B0_ADLIMGRSR_LIMGRFn_Msk (0x1ffUL) /*!< LIMGRFn (Bitfield-Mask: 0x1ff) */ +/* ====================================================== ADLIMCHSR0 ======================================================= */ + #define R_ADC_B0_ADLIMCHSR0_LIMCHFn_Pos (0UL) /*!< LIMCHFn (Bit 0) */ + #define R_ADC_B0_ADLIMCHSR0_LIMCHFn_Msk (0x7fffffUL) /*!< LIMCHFn (Bitfield-Mask: 0x7fffff) */ +/* ======================================================= ADLIMEXSR ======================================================= */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF0_Pos (0UL) /*!< LIMEXF0 (Bit 0) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF0_Msk (0x1UL) /*!< LIMEXF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF1_Pos (1UL) /*!< LIMEXF1 (Bit 1) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF1_Msk (0x2UL) /*!< LIMEXF1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF4_Pos (4UL) /*!< LIMEXF4 (Bit 4) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF4_Msk (0x10UL) /*!< LIMEXF4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF5_Pos (5UL) /*!< LIMEXF5 (Bit 5) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF5_Msk (0x20UL) /*!< LIMEXF5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF6_Pos (6UL) /*!< LIMEXF6 (Bit 6) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF6_Msk (0x40UL) /*!< LIMEXF6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF8_Pos (8UL) /*!< LIMEXF8 (Bit 8) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF8_Msk (0x100UL) /*!< LIMEXF8 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF9_Pos (9UL) /*!< LIMEXF9 (Bit 9) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF9_Msk (0x200UL) /*!< LIMEXF9 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF16_Pos (16UL) /*!< LIMEXF16 (Bit 16) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF16_Msk (0x10000UL) /*!< LIMEXF16 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF17_Pos (17UL) /*!< LIMEXF17 (Bit 17) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF17_Msk (0x20000UL) /*!< LIMEXF17 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF18_Pos (18UL) /*!< LIMEXF18 (Bit 18) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF18_Msk (0x40000UL) /*!< LIMEXF18 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF20_Pos (20UL) /*!< LIMEXF20 (Bit 20) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF20_Msk (0x100000UL) /*!< LIMEXF20 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF21_Pos (21UL) /*!< LIMEXF21 (Bit 21) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF21_Msk (0x200000UL) /*!< LIMEXF21 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF22_Pos (22UL) /*!< LIMEXF22 (Bit 22) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF22_Msk (0x400000UL) /*!< LIMEXF22 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADLIMGRSCR ======================================================= */ + #define R_ADC_B0_ADLIMGRSCR_LIMGRCn_Pos (0UL) /*!< LIMGRCn (Bit 0) */ + #define R_ADC_B0_ADLIMGRSCR_LIMGRCn_Msk (0x1ffUL) /*!< LIMGRCn (Bitfield-Mask: 0x1ff) */ +/* ====================================================== ADLIMCHSCR0 ====================================================== */ + #define R_ADC_B0_ADLIMCHSCR0_LIMCHCn_Pos (0UL) /*!< LIMCHCn (Bit 0) */ + #define R_ADC_B0_ADLIMCHSCR0_LIMCHCn_Msk (0x7fffffUL) /*!< LIMCHCn (Bitfield-Mask: 0x7fffff) */ +/* ====================================================== ADLIMEXSCR ======================================================= */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF0_Pos (0UL) /*!< LIMEXF0 (Bit 0) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF0_Msk (0x1UL) /*!< LIMEXF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF1_Pos (1UL) /*!< LIMEXF1 (Bit 1) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF1_Msk (0x2UL) /*!< LIMEXF1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF4_Pos (4UL) /*!< LIMEXF4 (Bit 4) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF4_Msk (0x10UL) /*!< LIMEXF4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF5_Pos (5UL) /*!< LIMEXF5 (Bit 5) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF5_Msk (0x20UL) /*!< LIMEXF5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF6_Pos (6UL) /*!< LIMEXF6 (Bit 6) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF6_Msk (0x40UL) /*!< LIMEXF6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF8_Pos (8UL) /*!< LIMEXF8 (Bit 8) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF8_Msk (0x100UL) /*!< LIMEXF8 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF9_Pos (9UL) /*!< LIMEXF9 (Bit 9) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF9_Msk (0x200UL) /*!< LIMEXF9 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF16_Pos (16UL) /*!< LIMEXF16 (Bit 16) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF16_Msk (0x10000UL) /*!< LIMEXF16 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF17_Pos (17UL) /*!< LIMEXF17 (Bit 17) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF17_Msk (0x20000UL) /*!< LIMEXF17 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF18_Pos (18UL) /*!< LIMEXF18 (Bit 18) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF18_Msk (0x40000UL) /*!< LIMEXF18 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF20_Pos (20UL) /*!< LIMEXF20 (Bit 20) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF20_Msk (0x100000UL) /*!< LIMEXF20 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF21_Pos (21UL) /*!< LIMEXF21 (Bit 21) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF21_Msk (0x200000UL) /*!< LIMEXF21 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF22_Pos (22UL) /*!< LIMEXF22 (Bit 22) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF22_Msk (0x400000UL) /*!< LIMEXF22 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADSCANENDSR ====================================================== */ + #define R_ADC_B0_ADSCANENDSR_SCENDFn_Pos (0UL) /*!< SCENDFn (Bit 0) */ + #define R_ADC_B0_ADSCANENDSR_SCENDFn_Msk (0x1ffUL) /*!< SCENDFn (Bitfield-Mask: 0x1ff) */ +/* ===================================================== ADSCANENDSCR ====================================================== */ + #define R_ADC_B0_ADSCANENDSCR_SCENDCn_Pos (0UL) /*!< SCENDCn (Bit 0) */ + #define R_ADC_B0_ADSCANENDSCR_SCENDCn_Msk (0x1ffUL) /*!< SCENDCn (Bitfield-Mask: 0x1ff) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC_B0_ADDR_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADDR_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADDR_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADDR_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADEXDR ========================================================= */ + #define R_ADC_B0_ADEXDR_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADEXDR_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADEXDR_DIAGSR_Pos (24UL) /*!< DIAGSR (Bit 24) */ + #define R_ADC_B0_ADEXDR_DIAGSR_Msk (0x7000000UL) /*!< DIAGSR (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADEXDR_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADEXDR_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR0 ======================================================= */ + #define R_ADC_B0_ADFIFODR0_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR0_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR0_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR0_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR0_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR0_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR1 ======================================================= */ + #define R_ADC_B0_ADFIFODR1_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR1_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR1_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR1_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR1_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR1_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR2 ======================================================= */ + #define R_ADC_B0_ADFIFODR2_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR2_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR2_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR2_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR2_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR2_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR3 ======================================================= */ + #define R_ADC_B0_ADFIFODR3_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR3_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR3_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR3_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR3_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR3_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR4 ======================================================= */ + #define R_ADC_B0_ADFIFODR4_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR4_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR4_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR4_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR4_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR4_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR5 ======================================================= */ + #define R_ADC_B0_ADFIFODR5_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR5_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR5_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR5_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR5_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR5_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR6 ======================================================= */ + #define R_ADC_B0_ADFIFODR6_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR6_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR6_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR6_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR6_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR6_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR7 ======================================================= */ + #define R_ADC_B0_ADFIFODR7_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR7_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR7_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR7_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR7_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR7_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR8 ======================================================= */ + #define R_ADC_B0_ADFIFODR8_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR8_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR8_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR8_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR8_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR8_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC_B ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_B_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_B_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ + #define R_DOC_B_DOCR_DOBW_Pos (3UL) /*!< DOBW (Bit 3) */ + #define R_DOC_B_DOCR_DOBW_Msk (0x8UL) /*!< DOBW (Bitfield-Mask: 0x01) */ + #define R_DOC_B_DOCR_DCSEL_Pos (4UL) /*!< DCSEL (Bit 4) */ + #define R_DOC_B_DOCR_DCSEL_Msk (0x70UL) /*!< DCSEL (Bitfield-Mask: 0x07) */ +/* ========================================================= DOSR ========================================================== */ + #define R_DOC_B_DOSR_DOPCF_Pos (0UL) /*!< DOPCF (Bit 0) */ + #define R_DOC_B_DOSR_DOPCF_Msk (0x1UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ +/* ========================================================= DOSCR ========================================================= */ + #define R_DOC_B_DOSCR_DOPCFCL_Pos (0UL) /*!< DOPCFCL (Bit 0) */ + #define R_DOC_B_DOSCR_DOPCFCL_Msk (0x1UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ +/* ========================================================= DODIR ========================================================= */ +/* ======================================================== DODSR0 ========================================================= */ +/* ======================================================== DODSR1 ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_SCI_B0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== RDR ========================================================== */ + #define R_SCI_B0_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI_B0_RDR_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI_B0_RDR_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI_B0_RDR_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI_B0_RDR_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_FPER_Pos (11UL) /*!< FPER (Bit 11) */ + #define R_SCI_B0_RDR_FPER_Msk (0x800UL) /*!< FPER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_FFER_Pos (12UL) /*!< FFER (Bit 12) */ + #define R_SCI_B0_RDR_FFER_Msk (0x1000UL) /*!< FFER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_ORER_Pos (24UL) /*!< ORER (Bit 24) */ + #define R_SCI_B0_RDR_ORER_Msk (0x1000000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_PER_Pos (27UL) /*!< PER (Bit 27) */ + #define R_SCI_B0_RDR_PER_Msk (0x8000000UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_FER_Pos (28UL) /*!< FER (Bit 28) */ + #define R_SCI_B0_RDR_FER_Msk (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01) */ +/* ======================================================== RDR_BY ========================================================= */ + #define R_SCI_B0_RDR_BY_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI_B0_RDR_BY_RDAT_Msk (0xffUL) /*!< RDAT (Bitfield-Mask: 0xff) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI_B0_TDR_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI_B0_TDR_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI_B0_TDR_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI_B0_TDR_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_TDR_TSYNC_Pos (12UL) /*!< TSYNC (Bit 12) */ + #define R_SCI_B0_TDR_TSYNC_Msk (0x1000UL) /*!< TSYNC (Bitfield-Mask: 0x01) */ +/* ======================================================== TDR_BY ========================================================= */ + #define R_SCI_B0_TDR_BY_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI_B0_TDR_BY_TDAT_Msk (0xffUL) /*!< TDAT (Bitfield-Mask: 0xff) */ +/* ========================================================= CCR0 ========================================================== */ + #define R_SCI_B0_CCR0_RE_Pos (0UL) /*!< RE (Bit 0) */ + #define R_SCI_B0_CCR0_RE_Msk (0x1UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_TE_Pos (4UL) /*!< TE (Bit 4) */ + #define R_SCI_B0_CCR0_TE_Msk (0x10UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_MPIE_Pos (8UL) /*!< MPIE (Bit 8) */ + #define R_SCI_B0_CCR0_MPIE_Msk (0x100UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_DCME_Pos (9UL) /*!< DCME (Bit 9) */ + #define R_SCI_B0_CCR0_DCME_Msk (0x200UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_IDSEL_Pos (10UL) /*!< IDSEL (Bit 10) */ + #define R_SCI_B0_CCR0_IDSEL_Msk (0x400UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_RIE_Pos (16UL) /*!< RIE (Bit 16) */ + #define R_SCI_B0_CCR0_RIE_Msk (0x10000UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_TIE_Pos (20UL) /*!< TIE (Bit 20) */ + #define R_SCI_B0_CCR0_TIE_Msk (0x100000UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_TEIE_Pos (21UL) /*!< TEIE (Bit 21) */ + #define R_SCI_B0_CCR0_TEIE_Msk (0x200000UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_SSE_Pos (24UL) /*!< SSE (Bit 24) */ + #define R_SCI_B0_CCR0_SSE_Msk (0x1000000UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR1 ========================================================== */ + #define R_SCI_B0_CCR1_CTSE_Pos (0UL) /*!< CTSE (Bit 0) */ + #define R_SCI_B0_CCR1_CTSE_Msk (0x1UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_CTSPEN_Pos (1UL) /*!< CTSPEN (Bit 1) */ + #define R_SCI_B0_CCR1_CTSPEN_Msk (0x2UL) /*!< CTSPEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SPB2DT_Pos (4UL) /*!< SPB2DT (Bit 4) */ + #define R_SCI_B0_CCR1_SPB2DT_Msk (0x10UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SPB2IO_Pos (5UL) /*!< SPB2IO (Bit 5) */ + #define R_SCI_B0_CCR1_SPB2IO_Msk (0x20UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_PE_Pos (8UL) /*!< PE (Bit 8) */ + #define R_SCI_B0_CCR1_PE_Msk (0x100UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_PM_Pos (9UL) /*!< PM (Bit 9) */ + #define R_SCI_B0_CCR1_PM_Msk (0x200UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_TINV_Pos (12UL) /*!< TINV (Bit 12) */ + #define R_SCI_B0_CCR1_TINV_Msk (0x1000UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_RINV_Pos (13UL) /*!< RINV (Bit 13) */ + #define R_SCI_B0_CCR1_RINV_Msk (0x2000UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SPLP_Pos (16UL) /*!< SPLP (Bit 16) */ + #define R_SCI_B0_CCR1_SPLP_Msk (0x10000UL) /*!< SPLP (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SHARPS_Pos (20UL) /*!< SHARPS (Bit 20) */ + #define R_SCI_B0_CCR1_SHARPS_Msk (0x100000UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_NFCS_Pos (24UL) /*!< NFCS (Bit 24) */ + #define R_SCI_B0_CCR1_NFCS_Msk (0x7000000UL) /*!< NFCS (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR1_NFEN_Pos (28UL) /*!< NFEN (Bit 28) */ + #define R_SCI_B0_CCR1_NFEN_Msk (0x10000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR2 ========================================================== */ + #define R_SCI_B0_CCR2_BCP_Pos (0UL) /*!< BCP (Bit 0) */ + #define R_SCI_B0_CCR2_BCP_Msk (0x7UL) /*!< BCP (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR2_BGDM_Pos (4UL) /*!< BGDM (Bit 4) */ + #define R_SCI_B0_CCR2_BGDM_Msk (0x10UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_ABCS_Pos (5UL) /*!< ABCS (Bit 5) */ + #define R_SCI_B0_CCR2_ABCS_Msk (0x20UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_ABCSE_Pos (6UL) /*!< ABCSE (Bit 6) */ + #define R_SCI_B0_CCR2_ABCSE_Msk (0x40UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_BRR_Pos (8UL) /*!< BRR (Bit 8) */ + #define R_SCI_B0_CCR2_BRR_Msk (0xff00UL) /*!< BRR (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_CCR2_BRME_Pos (16UL) /*!< BRME (Bit 16) */ + #define R_SCI_B0_CCR2_BRME_Msk (0x10000UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_CKS_Pos (20UL) /*!< CKS (Bit 20) */ + #define R_SCI_B0_CCR2_CKS_Msk (0x300000UL) /*!< CKS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_CCR2_MDDR_Pos (24UL) /*!< MDDR (Bit 24) */ + #define R_SCI_B0_CCR2_MDDR_Msk (0xff000000UL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= CCR3 ========================================================== */ + #define R_SCI_B0_CCR3_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SCI_B0_CCR3_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SCI_B0_CCR3_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_BPEN_Pos (7UL) /*!< BPEN (Bit 7) */ + #define R_SCI_B0_CCR3_BPEN_Msk (0x80UL) /*!< BPEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_CHR_Pos (8UL) /*!< CHR (Bit 8) */ + #define R_SCI_B0_CCR3_CHR_Msk (0x300UL) /*!< CHR (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_CCR3_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SCI_B0_CCR3_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_SINV_Pos (13UL) /*!< SINV (Bit 13) */ + #define R_SCI_B0_CCR3_SINV_Msk (0x2000UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_STP_Pos (14UL) /*!< STP (Bit 14) */ + #define R_SCI_B0_CCR3_STP_Msk (0x4000UL) /*!< STP (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_RXDESEL_Pos (15UL) /*!< RXDESEL (Bit 15) */ + #define R_SCI_B0_CCR3_RXDESEL_Msk (0x8000UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_MOD_Pos (16UL) /*!< MOD (Bit 16) */ + #define R_SCI_B0_CCR3_MOD_Msk (0x70000UL) /*!< MOD (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR3_MP_Pos (19UL) /*!< MP (Bit 19) */ + #define R_SCI_B0_CCR3_MP_Msk (0x80000UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_FM_Pos (20UL) /*!< FM (Bit 20) */ + #define R_SCI_B0_CCR3_FM_Msk (0x100000UL) /*!< FM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_DEN_Pos (21UL) /*!< DEN (Bit 21) */ + #define R_SCI_B0_CCR3_DEN_Msk (0x200000UL) /*!< DEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_CKE_Pos (24UL) /*!< CKE (Bit 24) */ + #define R_SCI_B0_CCR3_CKE_Msk (0x3000000UL) /*!< CKE (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_CCR3_GM_Pos (28UL) /*!< GM (Bit 28) */ + #define R_SCI_B0_CCR3_GM_Msk (0x10000000UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_BLK_Pos (29UL) /*!< BLK (Bit 29) */ + #define R_SCI_B0_CCR3_BLK_Msk (0x20000000UL) /*!< BLK (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR4 ========================================================== */ + #define R_SCI_B0_CCR4_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI_B0_CCR4_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ + #define R_SCI_B0_CCR4_ASEN_Pos (16UL) /*!< ASEN (Bit 16) */ + #define R_SCI_B0_CCR4_ASEN_Msk (0x10000UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR4_ATEN_Pos (17UL) /*!< ATEN (Bit 17) */ + #define R_SCI_B0_CCR4_ATEN_Msk (0x20000UL) /*!< ATEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR4_SCKSEL_Pos (19UL) /*!< SCKSEL (Bit 19) */ + #define R_SCI_B0_CCR4_SCKSEL_Msk (0x80000UL) /*!< SCKSEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR4_AST_Pos (24UL) /*!< AST (Bit 24) */ + #define R_SCI_B0_CCR4_AST_Msk (0x7000000UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR4_AJD_Pos (27UL) /*!< AJD (Bit 27) */ + #define R_SCI_B0_CCR4_AJD_Msk (0x8000000UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR4_ATT_Pos (28UL) /*!< ATT (Bit 28) */ + #define R_SCI_B0_CCR4_ATT_Msk (0x70000000UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR4_AET_Pos (31UL) /*!< AET (Bit 31) */ + #define R_SCI_B0_CCR4_AET_Msk (0x80000000UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= CESR ========================================================== */ + #define R_SCI_B0_CESR_RIST_Pos (0UL) /*!< RIST (Bit 0) */ + #define R_SCI_B0_CESR_RIST_Msk (0x1UL) /*!< RIST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CESR_TIST_Pos (4UL) /*!< TIST (Bit 4) */ + #define R_SCI_B0_CESR_TIST_Msk (0x10UL) /*!< TIST (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI_B0_ICR_IICDL_Pos (0UL) /*!< IICDL (Bit 0) */ + #define R_SCI_B0_ICR_IICDL_Msk (0x1fUL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_ICR_IICINTM_Pos (8UL) /*!< IICINTM (Bit 8) */ + #define R_SCI_B0_ICR_IICINTM_Msk (0x100UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICCSC_Pos (9UL) /*!< IICCSC (Bit 9) */ + #define R_SCI_B0_ICR_IICCSC_Msk (0x200UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICACKT_Pos (13UL) /*!< IICACKT (Bit 13) */ + #define R_SCI_B0_ICR_IICACKT_Msk (0x2000UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICSTAREQ_Pos (16UL) /*!< IICSTAREQ (Bit 16) */ + #define R_SCI_B0_ICR_IICSTAREQ_Msk (0x10000UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICRSTAREQ_Pos (17UL) /*!< IICRSTAREQ (Bit 17) */ + #define R_SCI_B0_ICR_IICRSTAREQ_Msk (0x20000UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICSTPREQ_Pos (18UL) /*!< IICSTPREQ (Bit 18) */ + #define R_SCI_B0_ICR_IICSTPREQ_Msk (0x40000UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICSDAS_Pos (20UL) /*!< IICSDAS (Bit 20) */ + #define R_SCI_B0_ICR_IICSDAS_Msk (0x300000UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_ICR_IICSCLS_Pos (22UL) /*!< IICSCLS (Bit 22) */ + #define R_SCI_B0_ICR_IICSCLS_Msk (0xc00000UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI_B0_FCR_DRES_Pos (0UL) /*!< DRES (Bit 0) */ + #define R_SCI_B0_FCR_DRES_Msk (0x1UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FCR_TTRG_Pos (8UL) /*!< TTRG (Bit 8) */ + #define R_SCI_B0_FCR_TTRG_Msk (0x1f00UL) /*!< TTRG (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_FCR_TFRST_Pos (15UL) /*!< TFRST (Bit 15) */ + #define R_SCI_B0_FCR_TFRST_Msk (0x8000UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FCR_RTRG_Pos (16UL) /*!< RTRG (Bit 16) */ + #define R_SCI_B0_FCR_RTRG_Msk (0x1f0000UL) /*!< RTRG (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_FCR_RFRST_Pos (23UL) /*!< RFRST (Bit 23) */ + #define R_SCI_B0_FCR_RFRST_Msk (0x800000UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FCR_RSTRG_Pos (24UL) /*!< RSTRG (Bit 24) */ + #define R_SCI_B0_FCR_RSTRG_Msk (0x1f000000UL) /*!< RSTRG (Bitfield-Mask: 0x1f) */ +/* ========================================================== MCR ========================================================== */ + #define R_SCI_B0_MCR_RMPOL_Pos (0UL) /*!< RMPOL (Bit 0) */ + #define R_SCI_B0_MCR_RMPOL_Msk (0x1UL) /*!< RMPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_TMPOL_Pos (1UL) /*!< TMPOL (Bit 1) */ + #define R_SCI_B0_MCR_TMPOL_Msk (0x2UL) /*!< TMPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_ERTEN_Pos (2UL) /*!< ERTEN (Bit 2) */ + #define R_SCI_B0_MCR_ERTEN_Msk (0x4UL) /*!< ERTEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SYNVAL_Pos (4UL) /*!< SYNVAL (Bit 4) */ + #define R_SCI_B0_MCR_SYNVAL_Msk (0x10UL) /*!< SYNVAL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SYNSEL_Pos (5UL) /*!< SYNSEL (Bit 5) */ + #define R_SCI_B0_MCR_SYNSEL_Msk (0x20UL) /*!< SYNSEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SBSEL_Pos (6UL) /*!< SBSEL (Bit 6) */ + #define R_SCI_B0_MCR_SBSEL_Msk (0x40UL) /*!< SBSEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_TPLEN_Pos (8UL) /*!< TPLEN (Bit 8) */ + #define R_SCI_B0_MCR_TPLEN_Msk (0xf00UL) /*!< TPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI_B0_MCR_TPPAT_Pos (12UL) /*!< TPPAT (Bit 12) */ + #define R_SCI_B0_MCR_TPPAT_Msk (0x3000UL) /*!< TPPAT (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_MCR_RPLEN_Pos (16UL) /*!< RPLEN (Bit 16) */ + #define R_SCI_B0_MCR_RPLEN_Msk (0xf0000UL) /*!< RPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI_B0_MCR_RPPAT_Pos (20UL) /*!< RPPAT (Bit 20) */ + #define R_SCI_B0_MCR_RPPAT_Msk (0x300000UL) /*!< RPPAT (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_MCR_PFEREN_Pos (24UL) /*!< PFEREN (Bit 24) */ + #define R_SCI_B0_MCR_PFEREN_Msk (0x1000000UL) /*!< PFEREN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SYEREN_Pos (25UL) /*!< SYEREN (Bit 25) */ + #define R_SCI_B0_MCR_SYEREN_Msk (0x2000000UL) /*!< SYEREN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SBEREN_Pos (26UL) /*!< SBEREN (Bit 26) */ + #define R_SCI_B0_MCR_SBEREN_Msk (0x4000000UL) /*!< SBEREN (Bitfield-Mask: 0x01) */ +/* ========================================================== DCR ========================================================== */ + #define R_SCI_B0_DCR_DEPOL_Pos (0UL) /*!< DEPOL (Bit 0) */ + #define R_SCI_B0_DCR_DEPOL_Msk (0x1UL) /*!< DEPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_DCR_DEAST_Pos (8UL) /*!< DEAST (Bit 8) */ + #define R_SCI_B0_DCR_DEAST_Msk (0x1f00UL) /*!< DEAST (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_DCR_DENGT_Pos (16UL) /*!< DENGT (Bit 16) */ + #define R_SCI_B0_DCR_DENGT_Msk (0x1f0000UL) /*!< DENGT (Bitfield-Mask: 0x1f) */ +/* ========================================================= XCR0 ========================================================== */ + #define R_SCI_B0_XCR0_TCSS_Pos (0UL) /*!< TCSS (Bit 0) */ + #define R_SCI_B0_XCR0_TCSS_Msk (0x3UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_XCR0_BFE_Pos (8UL) /*!< BFE (Bit 8) */ + #define R_SCI_B0_XCR0_BFE_Msk (0x100UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_CF0RE_Pos (9UL) /*!< CF0RE (Bit 9) */ + #define R_SCI_B0_XCR0_CF0RE_Msk (0x200UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_CF1DS_Pos (10UL) /*!< CF1DS (Bit 10) */ + #define R_SCI_B0_XCR0_CF1DS_Msk (0xc00UL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_XCR0_PIBE_Pos (12UL) /*!< PIBE (Bit 12) */ + #define R_SCI_B0_XCR0_PIBE_Msk (0x1000UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_PIBS_Pos (13UL) /*!< PIBS (Bit 13) */ + #define R_SCI_B0_XCR0_PIBS_Msk (0xe000UL) /*!< PIBS (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_XCR0_BFOIE_Pos (16UL) /*!< BFOIE (Bit 16) */ + #define R_SCI_B0_XCR0_BFOIE_Msk (0x10000UL) /*!< BFOIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_BCDIE_Pos (17UL) /*!< BCDIE (Bit 17) */ + #define R_SCI_B0_XCR0_BCDIE_Msk (0x20000UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_BFDIE_Pos (20UL) /*!< BFDIE (Bit 20) */ + #define R_SCI_B0_XCR0_BFDIE_Msk (0x100000UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_COFIE_Pos (21UL) /*!< COFIE (Bit 21) */ + #define R_SCI_B0_XCR0_COFIE_Msk (0x200000UL) /*!< COFIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_AEDIE_Pos (22UL) /*!< AEDIE (Bit 22) */ + #define R_SCI_B0_XCR0_AEDIE_Msk (0x400000UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_BCCS_Pos (24UL) /*!< BCCS (Bit 24) */ + #define R_SCI_B0_XCR0_BCCS_Msk (0x3000000UL) /*!< BCCS (Bitfield-Mask: 0x03) */ +/* ========================================================= XCR1 ========================================================== */ + #define R_SCI_B0_XCR1_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI_B0_XCR1_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR1_SDST_Pos (4UL) /*!< SDST (Bit 4) */ + #define R_SCI_B0_XCR1_SDST_Msk (0x10UL) /*!< SDST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR1_BMEN_Pos (5UL) /*!< BMEN (Bit 5) */ + #define R_SCI_B0_XCR1_BMEN_Msk (0x20UL) /*!< BMEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR1_PCF1D_Pos (8UL) /*!< PCF1D (Bit 8) */ + #define R_SCI_B0_XCR1_PCF1D_Msk (0xff00UL) /*!< PCF1D (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR1_SCF1D_Pos (16UL) /*!< SCF1D (Bit 16) */ + #define R_SCI_B0_XCR1_SCF1D_Msk (0xff0000UL) /*!< SCF1D (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR1_CF1CE_Pos (24UL) /*!< CF1CE (Bit 24) */ + #define R_SCI_B0_XCR1_CF1CE_Msk (0xff000000UL) /*!< CF1CE (Bitfield-Mask: 0xff) */ +/* ========================================================= XCR2 ========================================================== */ + #define R_SCI_B0_XCR2_CF0D_Pos (0UL) /*!< CF0D (Bit 0) */ + #define R_SCI_B0_XCR2_CF0D_Msk (0xffUL) /*!< CF0D (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR2_CF0CE_Pos (8UL) /*!< CF0CE (Bit 8) */ + #define R_SCI_B0_XCR2_CF0CE_Msk (0xff00UL) /*!< CF0CE (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR2_BFLW_Pos (16UL) /*!< BFLW (Bit 16) */ + #define R_SCI_B0_XCR2_BFLW_Msk (0xffff0000UL) /*!< BFLW (Bitfield-Mask: 0xffff) */ +/* ========================================================== CSR ========================================================== */ + #define R_SCI_B0_CSR_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI_B0_CSR_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_RXDMON_Pos (15UL) /*!< RXDMON (Bit 15) */ + #define R_SCI_B0_CSR_RXDMON_Msk (0x8000UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_DCMF_Pos (16UL) /*!< DCMF (Bit 16) */ + #define R_SCI_B0_CSR_DCMF_Msk (0x10000UL) /*!< DCMF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_DPER_Pos (17UL) /*!< DPER (Bit 17) */ + #define R_SCI_B0_CSR_DPER_Msk (0x20000UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_DFER_Pos (18UL) /*!< DFER (Bit 18) */ + #define R_SCI_B0_CSR_DFER_Msk (0x40000UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_ORER_Pos (24UL) /*!< ORER (Bit 24) */ + #define R_SCI_B0_CSR_ORER_Msk (0x1000000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_MFF_Pos (26UL) /*!< MFF (Bit 26) */ + #define R_SCI_B0_CSR_MFF_Msk (0x4000000UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_PER_Pos (27UL) /*!< PER (Bit 27) */ + #define R_SCI_B0_CSR_PER_Msk (0x8000000UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_FER_Pos (28UL) /*!< FER (Bit 28) */ + #define R_SCI_B0_CSR_FER_Msk (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_TDRE_Pos (29UL) /*!< TDRE (Bit 29) */ + #define R_SCI_B0_CSR_TDRE_Msk (0x20000000UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_TEND_Pos (30UL) /*!< TEND (Bit 30) */ + #define R_SCI_B0_CSR_TEND_Msk (0x40000000UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_RDRF_Pos (31UL) /*!< RDRF (Bit 31) */ + #define R_SCI_B0_CSR_RDRF_Msk (0x80000000UL) /*!< RDRF (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ + #define R_SCI_B0_ISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI_B0_ISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ISR_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI_B0_ISR_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ +/* ========================================================= FRSR ========================================================== */ + #define R_SCI_B0_FRSR_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI_B0_FRSR_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FRSR_R_Pos (8UL) /*!< R (Bit 8) */ + #define R_SCI_B0_FRSR_R_Msk (0x3f00UL) /*!< R (Bitfield-Mask: 0x3f) */ + #define R_SCI_B0_FRSR_PNUM_Pos (16UL) /*!< PNUM (Bit 16) */ + #define R_SCI_B0_FRSR_PNUM_Msk (0x3f0000UL) /*!< PNUM (Bitfield-Mask: 0x3f) */ + #define R_SCI_B0_FRSR_FNUM_Pos (24UL) /*!< FNUM (Bit 24) */ + #define R_SCI_B0_FRSR_FNUM_Msk (0x3f000000UL) /*!< FNUM (Bitfield-Mask: 0x3f) */ +/* ========================================================= FTSR ========================================================== */ + #define R_SCI_B0_FTSR_T_Pos (0UL) /*!< T (Bit 0) */ + #define R_SCI_B0_FTSR_T_Msk (0x3fUL) /*!< T (Bitfield-Mask: 0x3f) */ +/* ========================================================== MSR ========================================================== */ + #define R_SCI_B0_MSR_PFER_Pos (0UL) /*!< PFER (Bit 0) */ + #define R_SCI_B0_MSR_PFER_Msk (0x1UL) /*!< PFER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_SYER_Pos (1UL) /*!< SYER (Bit 1) */ + #define R_SCI_B0_MSR_SYER_Msk (0x2UL) /*!< SYER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_SBER_Pos (2UL) /*!< SBER (Bit 2) */ + #define R_SCI_B0_MSR_SBER_Msk (0x4UL) /*!< SBER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_MER_Pos (4UL) /*!< MER (Bit 4) */ + #define R_SCI_B0_MSR_MER_Msk (0x10UL) /*!< MER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_RSYNC_Pos (6UL) /*!< RSYNC (Bit 6) */ + #define R_SCI_B0_MSR_RSYNC_Msk (0x40UL) /*!< RSYNC (Bitfield-Mask: 0x01) */ +/* ========================================================= XSR0 ========================================================== */ + #define R_SCI_B0_XSR0_SFSF_Pos (0UL) /*!< SFSF (Bit 0) */ + #define R_SCI_B0_XSR0_SFSF_Msk (0x1UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_RXDSF_Pos (1UL) /*!< RXDSF (Bit 1) */ + #define R_SCI_B0_XSR0_RXDSF_Msk (0x2UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_BFOF_Pos (8UL) /*!< BFOF (Bit 8) */ + #define R_SCI_B0_XSR0_BFOF_Msk (0x100UL) /*!< BFOF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_BCDF_Pos (9UL) /*!< BCDF (Bit 9) */ + #define R_SCI_B0_XSR0_BCDF_Msk (0x200UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_BFDF_Pos (10UL) /*!< BFDF (Bit 10) */ + #define R_SCI_B0_XSR0_BFDF_Msk (0x400UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_CF0MF_Pos (11UL) /*!< CF0MF (Bit 11) */ + #define R_SCI_B0_XSR0_CF0MF_Msk (0x800UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_CF1MF_Pos (12UL) /*!< CF1MF (Bit 12) */ + #define R_SCI_B0_XSR0_CF1MF_Msk (0x1000UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_PIBDF_Pos (13UL) /*!< PIBDF (Bit 13) */ + #define R_SCI_B0_XSR0_PIBDF_Msk (0x2000UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_COF_Pos (14UL) /*!< COF (Bit 14) */ + #define R_SCI_B0_XSR0_COF_Msk (0x4000UL) /*!< COF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_AEDF_Pos (15UL) /*!< AEDF (Bit 15) */ + #define R_SCI_B0_XSR0_AEDF_Msk (0x8000UL) /*!< AEDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_CF0RD_Pos (16UL) /*!< CF0RD (Bit 16) */ + #define R_SCI_B0_XSR0_CF0RD_Msk (0xff0000UL) /*!< CF0RD (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XSR0_CF1RD_Pos (24UL) /*!< CF1RD (Bit 24) */ + #define R_SCI_B0_XSR0_CF1RD_Msk (0xff000000UL) /*!< CF1RD (Bitfield-Mask: 0xff) */ +/* ========================================================= XSR1 ========================================================== */ + #define R_SCI_B0_XSR1_TCNT_Pos (0UL) /*!< TCNT (Bit 0) */ + #define R_SCI_B0_XSR1_TCNT_Msk (0xffffUL) /*!< TCNT (Bitfield-Mask: 0xffff) */ +/* ========================================================= CFCLR ========================================================= */ + #define R_SCI_B0_CFCLR_ERSC_Pos (4UL) /*!< ERSC (Bit 4) */ + #define R_SCI_B0_CFCLR_ERSC_Msk (0x10UL) /*!< ERSC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_DCMFC_Pos (16UL) /*!< DCMFC (Bit 16) */ + #define R_SCI_B0_CFCLR_DCMFC_Msk (0x10000UL) /*!< DCMFC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_DPERC_Pos (17UL) /*!< DPERC (Bit 17) */ + #define R_SCI_B0_CFCLR_DPERC_Msk (0x20000UL) /*!< DPERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_DFERC_Pos (18UL) /*!< DFERC (Bit 18) */ + #define R_SCI_B0_CFCLR_DFERC_Msk (0x40000UL) /*!< DFERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_ORERC_Pos (24UL) /*!< ORERC (Bit 24) */ + #define R_SCI_B0_CFCLR_ORERC_Msk (0x1000000UL) /*!< ORERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_MFFC_Pos (26UL) /*!< MFFC (Bit 26) */ + #define R_SCI_B0_CFCLR_MFFC_Msk (0x4000000UL) /*!< MFFC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_PERC_Pos (27UL) /*!< PERC (Bit 27) */ + #define R_SCI_B0_CFCLR_PERC_Msk (0x8000000UL) /*!< PERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_FERC_Pos (28UL) /*!< FERC (Bit 28) */ + #define R_SCI_B0_CFCLR_FERC_Msk (0x10000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_TDREC_Pos (29UL) /*!< TDREC (Bit 29) */ + #define R_SCI_B0_CFCLR_TDREC_Msk (0x20000000UL) /*!< TDREC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_RDRFC_Pos (31UL) /*!< RDRFC (Bit 31) */ + #define R_SCI_B0_CFCLR_RDRFC_Msk (0x80000000UL) /*!< RDRFC (Bitfield-Mask: 0x01) */ +/* ======================================================== ICFCLR ========================================================= */ + #define R_SCI_B0_ICFCLR_IICSTIFC_Pos (3UL) /*!< IICSTIFC (Bit 3) */ + #define R_SCI_B0_ICFCLR_IICSTIFC_Msk (0x8UL) /*!< IICSTIFC (Bitfield-Mask: 0x01) */ +/* ========================================================= FFCLR ========================================================= */ + #define R_SCI_B0_FFCLR_DRC_Pos (0UL) /*!< DRC (Bit 0) */ + #define R_SCI_B0_FFCLR_DRC_Msk (0x1UL) /*!< DRC (Bitfield-Mask: 0x01) */ +/* ========================================================= MFCLR ========================================================= */ + #define R_SCI_B0_MFCLR_PFERC_Pos (0UL) /*!< PFERC (Bit 0) */ + #define R_SCI_B0_MFCLR_PFERC_Msk (0x1UL) /*!< PFERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MFCLR_SYERC_Pos (1UL) /*!< SYERC (Bit 1) */ + #define R_SCI_B0_MFCLR_SYERC_Msk (0x2UL) /*!< SYERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MFCLR_SBERC_Pos (2UL) /*!< SBERC (Bit 2) */ + #define R_SCI_B0_MFCLR_SBERC_Msk (0x4UL) /*!< SBERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MFCLR_MERC_Pos (4UL) /*!< MERC (Bit 4) */ + #define R_SCI_B0_MFCLR_MERC_Msk (0x10UL) /*!< MERC (Bitfield-Mask: 0x01) */ +/* ========================================================= XFCLR ========================================================= */ + #define R_SCI_B0_XFCLR_BFOC_Pos (8UL) /*!< BFOC (Bit 8) */ + #define R_SCI_B0_XFCLR_BFOC_Msk (0x100UL) /*!< BFOC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_BCDC_Pos (9UL) /*!< BCDC (Bit 9) */ + #define R_SCI_B0_XFCLR_BCDC_Msk (0x200UL) /*!< BCDC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_BFDC_Pos (10UL) /*!< BFDC (Bit 10) */ + #define R_SCI_B0_XFCLR_BFDC_Msk (0x400UL) /*!< BFDC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_CF0MC_Pos (11UL) /*!< CF0MC (Bit 11) */ + #define R_SCI_B0_XFCLR_CF0MC_Msk (0x800UL) /*!< CF0MC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_CF1MC_Pos (12UL) /*!< CF1MC (Bit 12) */ + #define R_SCI_B0_XFCLR_CF1MC_Msk (0x1000UL) /*!< CF1MC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_PIBDC_Pos (13UL) /*!< PIBDC (Bit 13) */ + #define R_SCI_B0_XFCLR_PIBDC_Msk (0x2000UL) /*!< PIBDC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_COFC_Pos (14UL) /*!< COFC (Bit 14) */ + #define R_SCI_B0_XFCLR_COFC_Msk (0x4000UL) /*!< COFC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_AEDC_Pos (15UL) /*!< AEDC (Bit 15) */ + #define R_SCI_B0_XFCLR_AEDC_Msk (0x8000UL) /*!< AEDC (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI_B0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDECR ========================================================= */ + #define R_SPI_B0_SPDECR_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI_B0_SPDECR_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPDECR_SLNDL_Pos (8UL) /*!< SLNDL (Bit 8) */ + #define R_SPI_B0_SPDECR_SLNDL_Msk (0x700UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPDECR_SPNDL_Pos (16UL) /*!< SPNDL (Bit 16) */ + #define R_SPI_B0_SPDECR_SPNDL_Msk (0x70000UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPDECR_ARST_Pos (24UL) /*!< ARST (Bit 24) */ + #define R_SPI_B0_SPDECR_ARST_Msk (0x7000000UL) /*!< ARST (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR ========================================================== */ + #define R_SPI_B0_SPCR_SPE_Pos (0UL) /*!< SPE (Bit 0) */ + #define R_SPI_B0_SPCR_SPE_Msk (0x1UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPSCKSEL_Pos (7UL) /*!< SPSCKSEL (Bit 7) */ + #define R_SPI_B0_SPCR_SPSCKSEL_Msk (0x80UL) /*!< SPSCKSEL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPPE_Pos (8UL) /*!< SPPE (Bit 8) */ + #define R_SPI_B0_SPCR_SPPE_Msk (0x100UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPOE_Pos (9UL) /*!< SPOE (Bit 9) */ + #define R_SPI_B0_SPCR_SPOE_Msk (0x200UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_PTE_Pos (11UL) /*!< PTE (Bit 11) */ + #define R_SPI_B0_SPCR_PTE_Msk (0x800UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SCKASE_Pos (12UL) /*!< SCKASE (Bit 12) */ + #define R_SPI_B0_SPCR_SCKASE_Msk (0x1000UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_BFDS_Pos (13UL) /*!< BFDS (Bit 13) */ + #define R_SPI_B0_SPCR_BFDS_Msk (0x2000UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_MODFEN_Pos (14UL) /*!< MODFEN (Bit 14) */ + #define R_SPI_B0_SPCR_MODFEN_Msk (0x4000UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPEIE_Pos (16UL) /*!< SPEIE (Bit 16) */ + #define R_SPI_B0_SPCR_SPEIE_Msk (0x10000UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPRIE_Pos (17UL) /*!< SPRIE (Bit 17) */ + #define R_SPI_B0_SPCR_SPRIE_Msk (0x20000UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPIIE_Pos (18UL) /*!< SPIIE (Bit 18) */ + #define R_SPI_B0_SPCR_SPIIE_Msk (0x40000UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPDRES_Pos (19UL) /*!< SPDRES (Bit 19) */ + #define R_SPI_B0_SPCR_SPDRES_Msk (0x80000UL) /*!< SPDRES (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPTIE_Pos (20UL) /*!< SPTIE (Bit 20) */ + #define R_SPI_B0_SPCR_SPTIE_Msk (0x100000UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_CENDIE_Pos (21UL) /*!< CENDIE (Bit 21) */ + #define R_SPI_B0_SPCR_CENDIE_Msk (0x200000UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPMS_Pos (24UL) /*!< SPMS (Bit 24) */ + #define R_SPI_B0_SPCR_SPMS_Msk (0x1000000UL) /*!< SPMS (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPFRF_Pos (25UL) /*!< SPFRF (Bit 25) */ + #define R_SPI_B0_SPCR_SPFRF_Msk (0x2000000UL) /*!< SPFRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_TXMD_Pos (28UL) /*!< TXMD (Bit 28) */ + #define R_SPI_B0_SPCR_TXMD_Msk (0x30000000UL) /*!< TXMD (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCR_MSTR_Pos (30UL) /*!< MSTR (Bit 30) */ + #define R_SPI_B0_SPCR_MSTR_Msk (0x40000000UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_BPEN_Pos (31UL) /*!< BPEN (Bit 31) */ + #define R_SPI_B0_SPCR_BPEN_Msk (0x80000000UL) /*!< BPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI_B0_SPCR2_RMFM_Pos (0UL) /*!< RMFM (Bit 0) */ + #define R_SPI_B0_SPCR2_RMFM_Msk (0x1fUL) /*!< RMFM (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCR2_RMEDTG_Pos (6UL) /*!< RMEDTG (Bit 6) */ + #define R_SPI_B0_SPCR2_RMEDTG_Msk (0x40UL) /*!< RMEDTG (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_RMSTTG_Pos (7UL) /*!< RMSTTG (Bit 7) */ + #define R_SPI_B0_SPCR2_RMSTTG_Msk (0x80UL) /*!< RMSTTG (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_SPDRC_Pos (8UL) /*!< SPDRC (Bit 8) */ + #define R_SPI_B0_SPCR2_SPDRC_Msk (0xff00UL) /*!< SPDRC (Bitfield-Mask: 0xff) */ + #define R_SPI_B0_SPCR2_SPLP_Pos (16UL) /*!< SPLP (Bit 16) */ + #define R_SPI_B0_SPCR2_SPLP_Msk (0x10000UL) /*!< SPLP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_SPLP2_Pos (17UL) /*!< SPLP2 (Bit 17) */ + #define R_SPI_B0_SPCR2_SPLP2_Msk (0x20000UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_MOIFV_Pos (20UL) /*!< MOIFV (Bit 20) */ + #define R_SPI_B0_SPCR2_MOIFV_Msk (0x100000UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_MOIFE_Pos (21UL) /*!< MOIFE (Bit 21) */ + #define R_SPI_B0_SPCR2_MOIFE_Msk (0x200000UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI_B0_SPCR3_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI_B0_SPCR3_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI_B0_SPCR3_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI_B0_SPCR3_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI_B0_SPCR3_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SPBR_Pos (8UL) /*!< SPBR (Bit 8) */ + #define R_SPI_B0_SPCR3_SPBR_Msk (0xff00UL) /*!< SPBR (Bitfield-Mask: 0xff) */ + #define R_SPI_B0_SPCR3_SPSLN_Pos (24UL) /*!< SPSLN (Bit 24) */ + #define R_SPI_B0_SPCR3_SPSLN_Msk (0x7000000UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD0 ========================================================= */ + #define R_SPI_B0_SPCMD0_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD0_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD0_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD0_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD0_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD0_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD0_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD0_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD0_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD0_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD0_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD0_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD0_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD1 ========================================================= */ + #define R_SPI_B0_SPCMD1_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD1_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD1_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD1_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD1_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD1_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD1_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD1_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD1_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD1_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD1_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD1_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD1_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD2 ========================================================= */ + #define R_SPI_B0_SPCMD2_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD2_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD2_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD2_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD2_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD2_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD2_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD2_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD2_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD2_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD2_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD2_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD2_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD3 ========================================================= */ + #define R_SPI_B0_SPCMD3_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD3_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD3_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD3_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD3_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD3_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD3_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD3_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD3_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD3_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD3_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD3_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD3_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD4 ========================================================= */ + #define R_SPI_B0_SPCMD4_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD4_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD4_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD4_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD4_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD4_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD4_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD4_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD4_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD4_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD4_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD4_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD4_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD5 ========================================================= */ + #define R_SPI_B0_SPCMD5_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD5_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD5_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD5_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD5_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD5_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD5_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD5_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD5_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD5_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD5_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD5_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD5_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD6 ========================================================= */ + #define R_SPI_B0_SPCMD6_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD6_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD6_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD6_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD6_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD6_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD6_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD6_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD6_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD6_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD6_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD6_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD6_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD7 ========================================================= */ + #define R_SPI_B0_SPCMD7_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD7_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD7_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD7_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD7_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD7_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD7_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD7_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD7_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD7_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD7_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD7_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD7_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI_B0_SPDCR_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI_B0_SPDCR_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPDCR_SPRDTD_Pos (3UL) /*!< SPRDTD (Bit 3) */ + #define R_SPI_B0_SPDCR_SPRDTD_Msk (0x8UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPDCR_SINV_Pos (4UL) /*!< SINV (Bit 4) */ + #define R_SPI_B0_SPDCR_SINV_Msk (0x10UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPDCR_SPFC_Pos (8UL) /*!< SPFC (Bit 8) */ + #define R_SPI_B0_SPDCR_SPFC_Msk (0x300UL) /*!< SPFC (Bitfield-Mask: 0x03) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI_B0_SPDCR2_RTRG_Pos (0UL) /*!< RTRG (Bit 0) */ + #define R_SPI_B0_SPDCR2_RTRG_Msk (0x3UL) /*!< RTRG (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPDCR2_TTRG_Pos (8UL) /*!< TTRG (Bit 8) */ + #define R_SPI_B0_SPDCR2_TTRG_Msk (0x300UL) /*!< TTRG (Bitfield-Mask: 0x03) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI_B0_SPSR_SPCP_Pos (8UL) /*!< SPCP (Bit 8) */ + #define R_SPI_B0_SPSR_SPCP_Msk (0x700UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPSR_SPECM_Pos (12UL) /*!< SPECM (Bit 12) */ + #define R_SPI_B0_SPSR_SPECM_Msk (0x7000UL) /*!< SPECM (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPSR_SPDRF_Pos (23UL) /*!< SPDRF (Bit 23) */ + #define R_SPI_B0_SPSR_SPDRF_Msk (0x800000UL) /*!< SPDRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_OVRF_Pos (24UL) /*!< OVRF (Bit 24) */ + #define R_SPI_B0_SPSR_OVRF_Msk (0x1000000UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_IDLNF_Pos (25UL) /*!< IDLNF (Bit 25) */ + #define R_SPI_B0_SPSR_IDLNF_Msk (0x2000000UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_MODF_Pos (26UL) /*!< MODF (Bit 26) */ + #define R_SPI_B0_SPSR_MODF_Msk (0x4000000UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_PERF_Pos (27UL) /*!< PERF (Bit 27) */ + #define R_SPI_B0_SPSR_PERF_Msk (0x8000000UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_UDRF_Pos (28UL) /*!< UDRF (Bit 28) */ + #define R_SPI_B0_SPSR_UDRF_Msk (0x10000000UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_SPTEF_Pos (29UL) /*!< SPTEF (Bit 29) */ + #define R_SPI_B0_SPSR_SPTEF_Msk (0x20000000UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_CENDF_Pos (30UL) /*!< CENDF (Bit 30) */ + #define R_SPI_B0_SPSR_CENDF_Msk (0x40000000UL) /*!< CENDF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_SPRF_Pos (31UL) /*!< SPRF (Bit 31) */ + #define R_SPI_B0_SPSR_SPRF_Msk (0x80000000UL) /*!< SPRF (Bitfield-Mask: 0x01) */ +/* ======================================================== SPTFSR ========================================================= */ + #define R_SPI_B0_SPTFSR_TFDN_Pos (0UL) /*!< TFDN (Bit 0) */ + #define R_SPI_B0_SPTFSR_TFDN_Msk (0x7UL) /*!< TFDN (Bitfield-Mask: 0x07) */ +/* ======================================================== SPRFSR ========================================================= */ + #define R_SPI_B0_SPRFSR_RFDN_Pos (0UL) /*!< RFDN (Bit 0) */ + #define R_SPI_B0_SPRFSR_RFDN_Msk (0x7UL) /*!< RFDN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPPSR ========================================================= */ + #define R_SPI_B0_SPPSR_SPEPS_Pos (0UL) /*!< SPEPS (Bit 0) */ + #define R_SPI_B0_SPPSR_SPEPS_Msk (0x1UL) /*!< SPEPS (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSRC ========================================================= */ + #define R_SPI_B0_SPSRC_SPDRFC_Pos (23UL) /*!< SPDRFC (Bit 23) */ + #define R_SPI_B0_SPSRC_SPDRFC_Msk (0x800000UL) /*!< SPDRFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_OVRFC_Pos (24UL) /*!< OVRFC (Bit 24) */ + #define R_SPI_B0_SPSRC_OVRFC_Msk (0x1000000UL) /*!< OVRFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_MODFC_Pos (26UL) /*!< MODFC (Bit 26) */ + #define R_SPI_B0_SPSRC_MODFC_Msk (0x4000000UL) /*!< MODFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_PERFC_Pos (27UL) /*!< PERFC (Bit 27) */ + #define R_SPI_B0_SPSRC_PERFC_Msk (0x8000000UL) /*!< PERFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_UDRFC_Pos (28UL) /*!< UDRFC (Bit 28) */ + #define R_SPI_B0_SPSRC_UDRFC_Msk (0x10000000UL) /*!< UDRFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_SPTEFC_Pos (29UL) /*!< SPTEFC (Bit 29) */ + #define R_SPI_B0_SPSRC_SPTEFC_Msk (0x20000000UL) /*!< SPTEFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_CENDFC_Pos (30UL) /*!< CENDFC (Bit 30) */ + #define R_SPI_B0_SPSRC_CENDFC_Msk (0x40000000UL) /*!< CENDFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_SPRFC_Pos (31UL) /*!< SPRFC (Bit 31) */ + #define R_SPI_B0_SPSRC_SPRFC_Msk (0x80000000UL) /*!< SPRFC (Bitfield-Mask: 0x01) */ +/* ========================================================= SPFCR ========================================================= */ + #define R_SPI_B0_SPFCR_SPFRST_Pos (0UL) /*!< SPFRST (Bit 0) */ + #define R_SPI_B0_SPFCR_SPFRST_Msk (0x1UL) /*!< SPFRST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_HS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_HS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_HS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_HSE_Pos (7UL) /*!< HSE (Bit 7) */ + #define R_USB_HS0_SYSCFG_HSE_Msk (0x80UL) /*!< HSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_HS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_HS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_HS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_HS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_HS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_HS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_HS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_HS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_HS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_HS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_HS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_HS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_HS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_HS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_HS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_HS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_HS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_HS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_HS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_HS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_HS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_HS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_HS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_HS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_HS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_HS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ========================================================= CFIFO ========================================================= */ + #define R_USB_HS0_CFIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_CFIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ + #define R_USB_HS0_D0FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_D0FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ + #define R_USB_HS0_D1FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_D1FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_HS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_HS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_HS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_HS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_HS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_HS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_HS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_HS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_HS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_HS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_HS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_HS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_HS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_HS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_HS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_HS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_HS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_HS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_HS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_HS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_HS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_HS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_HS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_HS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_HS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_L1RSMENDE_Pos (9UL) /*!< L1RSMENDE (Bit 9) */ + #define R_USB_HS0_INTENB1_L1RSMENDE_Msk (0x200UL) /*!< L1RSMENDE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_LPMENDE_Pos (8UL) /*!< LPMENDE (Bit 8) */ + #define R_USB_HS0_INTENB1_LPMENDE_Msk (0x100UL) /*!< LPMENDE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_HS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_HS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_HS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_HS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_HS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_HS0_BRDYENB_PIPEBRDYE_Msk (0x3ffUL) /*!< PIPEBRDYE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_HS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_HS0_NRDYENB_PIPENRDYE_Msk (0x3ffUL) /*!< PIPENRDYE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_HS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_HS0_BEMPENB_PIPEBEMPE_Msk (0x3ffUL) /*!< PIPEBEMPE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_HS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_HS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_HS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_HS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_HS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_HS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_HS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_HS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_HS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_HS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_HS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_HS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_HS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_HS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_HS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_HS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_HS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_HS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_HS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_HS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_HS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_HS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_HS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_HS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_HS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_HS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_HS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_HS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_HS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_HS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_HS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_HS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_HS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_HS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_HS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_HS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_HS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_HS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_HS0_BRDYSTS_PIPEBRDY_Msk (0x3ffUL) /*!< PIPEBRDY (Bitfield-Mask: 0x3ff) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_HS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_HS0_NRDYSTS_PIPENRDY_Msk (0x3ffUL) /*!< PIPENRDY (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_HS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_HS0_BEMPSTS_PIPEBEMP_Msk (0x3ffUL) /*!< PIPEBEMP (Bitfield-Mask: 0x3ff) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_HS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_HS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_HS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_HS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== UFRMNUM ======================================================== */ + #define R_USB_HS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_HS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ + #define R_USB_HS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_HS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_HS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_HS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_HS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_HS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_HS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_HS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_HS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_HS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_HS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_HS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_HS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_HS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_HS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_HS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_HS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_HS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_HS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_HS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_HS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_HS0_DCPCTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_HS0_DCPCTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_HS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_HS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_HS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_HS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_HS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PINGE_Pos (4UL) /*!< PINGE (Bit 4) */ + #define R_USB_HS0_DCPCTR_PINGE_Msk (0x10UL) /*!< PINGE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_HS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_HS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_HS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_HS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_HS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_HS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_HS0_PIPECFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_HS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_HS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_HS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPEBUF ======================================================== */ + #define R_USB_HS0_PIPEBUF_BUFSIZE_Pos (10UL) /*!< BUFSIZE (Bit 10) */ + #define R_USB_HS0_PIPEBUF_BUFSIZE_Msk (0x7c00UL) /*!< BUFSIZE (Bitfield-Mask: 0x1f) */ + #define R_USB_HS0_PIPEBUF_BUFNMB_Pos (0UL) /*!< BUFNMB (Bit 0) */ + #define R_USB_HS0_PIPEBUF_BUFNMB_Msk (0xffUL) /*!< BUFNMB (Bitfield-Mask: 0xff) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_HS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_HS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_HS0_PIPEMAXP_MXPS_Msk (0x7ffUL) /*!< MXPS (Bitfield-Mask: 0x7ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_HS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_HS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_HS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_HS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_HS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_HS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_HS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_HS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_HS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_HS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_HS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_HS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_HS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_HS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_HS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_HS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_HS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_HS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_HS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_HS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_HS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_HS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_HS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_HS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_HS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_HS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_HS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_HS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_HS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_HS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_HS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_HS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_HS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_HS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_HS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_HS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_HS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_HS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_HS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_HS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_HS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_HS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_HS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_HS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_HS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_HS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_HS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_HS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_HS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================= PHYTRIM1 ======================================================== */ + #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Pos (12UL) /*!< IMPOFFSET (Bit 12) */ + #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Msk (0x7000UL) /*!< IMPOFFSET (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_PHYTRIM1_HSIUP_Pos (8UL) /*!< HSIUP (Bit 8) */ + #define R_USB_HS0_PHYTRIM1_HSIUP_Msk (0xf00UL) /*!< HSIUP (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PHYTRIM1_PCOMPENB_Pos (7UL) /*!< PCOMPENB (Bit 7) */ + #define R_USB_HS0_PHYTRIM1_PCOMPENB_Msk (0x80UL) /*!< PCOMPENB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYTRIM1_DFALL_Pos (2UL) /*!< DFALL (Bit 2) */ + #define R_USB_HS0_PHYTRIM1_DFALL_Msk (0xcUL) /*!< DFALL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYTRIM1_DRISE_Pos (0UL) /*!< DRISE (Bit 0) */ + #define R_USB_HS0_PHYTRIM1_DRISE_Msk (0x3UL) /*!< DRISE (Bitfield-Mask: 0x03) */ +/* ======================================================= PHYTRIM2 ======================================================== */ + #define R_USB_HS0_PHYTRIM2_DIS_Pos (12UL) /*!< DIS (Bit 12) */ + #define R_USB_HS0_PHYTRIM2_DIS_Msk (0x7000UL) /*!< DIS (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_PHYTRIM2_PDR_Pos (8UL) /*!< PDR (Bit 8) */ + #define R_USB_HS0_PHYTRIM2_PDR_Msk (0x300UL) /*!< PDR (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYTRIM2_HSRXENMO_Pos (7UL) /*!< HSRXENMO (Bit 7) */ + #define R_USB_HS0_PHYTRIM2_HSRXENMO_Msk (0x80UL) /*!< HSRXENMO (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYTRIM2_SQU_Pos (0UL) /*!< SQU (Bit 0) */ + #define R_USB_HS0_PHYTRIM2_SQU_Msk (0xfUL) /*!< SQU (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_HS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_HS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_HS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_HS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_HS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_HS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_HS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_HS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_HS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_HS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_HS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_HS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_HS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_HS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_HS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_HS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_HS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_HS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_HS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_HS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_HS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_XSPI0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== WRAPCFG ======================================================== */ + #define R_XSPI0_WRAPCFG_CKSFTCS0_Pos (0UL) /*!< CKSFTCS0 (Bit 0) */ + #define R_XSPI0_WRAPCFG_CKSFTCS0_Msk (0x1fUL) /*!< CKSFTCS0 (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_WRAPCFG_DSSFTCS0_Pos (8UL) /*!< DSSFTCS0 (Bit 8) */ + #define R_XSPI0_WRAPCFG_DSSFTCS0_Msk (0x1f00UL) /*!< DSSFTCS0 (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_WRAPCFG_CKSFTCS1_Pos (16UL) /*!< CKSFTCS1 (Bit 16) */ + #define R_XSPI0_WRAPCFG_CKSFTCS1_Msk (0x1f0000UL) /*!< CKSFTCS1 (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_WRAPCFG_DSSFTCS1_Pos (24UL) /*!< DSSFTCS1 (Bit 24) */ + #define R_XSPI0_WRAPCFG_DSSFTCS1_Msk (0x1f000000UL) /*!< DSSFTCS1 (Bitfield-Mask: 0x1f) */ +/* ======================================================== COMCFG ========================================================= */ + #define R_XSPI0_COMCFG_ARBMD_Pos (0UL) /*!< ARBMD (Bit 0) */ + #define R_XSPI0_COMCFG_ARBMD_Msk (0x3UL) /*!< ARBMD (Bitfield-Mask: 0x03) */ + #define R_XSPI0_COMCFG_ECSINTOUTEN_Pos (4UL) /*!< ECSINTOUTEN (Bit 4) */ + #define R_XSPI0_COMCFG_ECSINTOUTEN_Msk (0x30UL) /*!< ECSINTOUTEN (Bitfield-Mask: 0x03) */ + #define R_XSPI0_COMCFG_OEASTEX_Pos (16UL) /*!< OEASTEX (Bit 16) */ + #define R_XSPI0_COMCFG_OEASTEX_Msk (0x10000UL) /*!< OEASTEX (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMCFG_OENEGEX_Pos (17UL) /*!< OENEGEX (Bit 17) */ + #define R_XSPI0_COMCFG_OENEGEX_Msk (0x20000UL) /*!< OENEGEX (Bitfield-Mask: 0x01) */ +/* ======================================================== BMCFGCH ======================================================== */ + #define R_XSPI0_BMCFGCH_WRMD_Pos (0UL) /*!< WRMD (Bit 0) */ + #define R_XSPI0_BMCFGCH_WRMD_Msk (0x1UL) /*!< WRMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCFGCH_MWRCOMB_Pos (7UL) /*!< MWRCOMB (Bit 7) */ + #define R_XSPI0_BMCFGCH_MWRCOMB_Msk (0x80UL) /*!< MWRCOMB (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCFGCH_MWRSIZE_Pos (8UL) /*!< MWRSIZE (Bit 8) */ + #define R_XSPI0_BMCFGCH_MWRSIZE_Msk (0xff00UL) /*!< MWRSIZE (Bitfield-Mask: 0xff) */ + #define R_XSPI0_BMCFGCH_PREEN_Pos (16UL) /*!< PREEN (Bit 16) */ + #define R_XSPI0_BMCFGCH_PREEN_Msk (0x10000UL) /*!< PREEN (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCFGCH_CMBTIM_Pos (24UL) /*!< CMBTIM (Bit 24) */ + #define R_XSPI0_BMCFGCH_CMBTIM_Msk (0xff000000UL) /*!< CMBTIM (Bitfield-Mask: 0xff) */ +/* ======================================================= LIOCFGCS ======================================================== */ + #define R_XSPI0_LIOCFGCS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */ + #define R_XSPI0_LIOCFGCS_PRTMD_Msk (0x3ffUL) /*!< PRTMD (Bitfield-Mask: 0x3ff) */ + #define R_XSPI0_LIOCFGCS_LATEMD_Pos (10UL) /*!< LATEMD (Bit 10) */ + #define R_XSPI0_LIOCFGCS_LATEMD_Msk (0x400UL) /*!< LATEMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_WRMSKMD_Pos (11UL) /*!< WRMSKMD (Bit 11) */ + #define R_XSPI0_LIOCFGCS_WRMSKMD_Msk (0x800UL) /*!< WRMSKMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_CSMIN_Pos (16UL) /*!< CSMIN (Bit 16) */ + #define R_XSPI0_LIOCFGCS_CSMIN_Msk (0xf0000UL) /*!< CSMIN (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_LIOCFGCS_CSASTEX_Pos (20UL) /*!< CSASTEX (Bit 20) */ + #define R_XSPI0_LIOCFGCS_CSASTEX_Msk (0x100000UL) /*!< CSASTEX (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_CSNEGEX_Pos (21UL) /*!< CSNEGEX (Bit 21) */ + #define R_XSPI0_LIOCFGCS_CSNEGEX_Msk (0x200000UL) /*!< CSNEGEX (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_SDRDRV_Pos (22UL) /*!< SDRDRV (Bit 22) */ + #define R_XSPI0_LIOCFGCS_SDRDRV_Msk (0x400000UL) /*!< SDRDRV (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_SDRSMPMD_Pos (23UL) /*!< SDRSMPMD (Bit 23) */ + #define R_XSPI0_LIOCFGCS_SDRSMPMD_Msk (0x800000UL) /*!< SDRSMPMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_SDRSMPSFT_Pos (24UL) /*!< SDRSMPSFT (Bit 24) */ + #define R_XSPI0_LIOCFGCS_SDRSMPSFT_Msk (0xf000000UL) /*!< SDRSMPSFT (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_LIOCFGCS_DDRSMPEX_Pos (28UL) /*!< DDRSMPEX (Bit 28) */ + #define R_XSPI0_LIOCFGCS_DDRSMPEX_Msk (0xf0000000UL) /*!< DDRSMPEX (Bitfield-Mask: 0x0f) */ +/* ======================================================== ABMCFG ========================================================= */ + #define R_XSPI0_ABMCFG_ODRMD_Pos (0UL) /*!< ODRMD (Bit 0) */ + #define R_XSPI0_ABMCFG_ODRMD_Msk (0x3UL) /*!< ODRMD (Bitfield-Mask: 0x03) */ + #define R_XSPI0_ABMCFG_CHSEL_Pos (16UL) /*!< CHSEL (Bit 16) */ + #define R_XSPI0_ABMCFG_CHSEL_Msk (0xffff0000UL) /*!< CHSEL (Bitfield-Mask: 0xffff) */ +/* ======================================================== BMCTL0 ========================================================= */ + #define R_XSPI0_BMCTL0_CH0CS0ACC_Pos (0UL) /*!< CH0CS0ACC (Bit 0) */ + #define R_XSPI0_BMCTL0_CH0CS0ACC_Msk (0x3UL) /*!< CH0CS0ACC (Bitfield-Mask: 0x03) */ + #define R_XSPI0_BMCTL0_CH0CS1ACC_Pos (2UL) /*!< CH0CS1ACC (Bit 2) */ + #define R_XSPI0_BMCTL0_CH0CS1ACC_Msk (0xcUL) /*!< CH0CS1ACC (Bitfield-Mask: 0x03) */ + #define R_XSPI0_BMCTL0_CH1CS0ACC_Pos (4UL) /*!< CH1CS0ACC (Bit 4) */ + #define R_XSPI0_BMCTL0_CH1CS0ACC_Msk (0x30UL) /*!< CH1CS0ACC (Bitfield-Mask: 0x03) */ + #define R_XSPI0_BMCTL0_CH1CS1ACC_Pos (6UL) /*!< CH1CS1ACC (Bit 6) */ + #define R_XSPI0_BMCTL0_CH1CS1ACC_Msk (0xc0UL) /*!< CH1CS1ACC (Bitfield-Mask: 0x03) */ +/* ======================================================== BMCTL1 ========================================================= */ + #define R_XSPI0_BMCTL1_MWRPUSHCH_Pos (8UL) /*!< MWRPUSHCH (Bit 8) */ + #define R_XSPI0_BMCTL1_MWRPUSHCH_Msk (0x100UL) /*!< MWRPUSHCH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCTL1_PBUFCLRCH_Pos (10UL) /*!< PBUFCLRCH (Bit 10) */ + #define R_XSPI0_BMCTL1_PBUFCLRCH_Msk (0x400UL) /*!< PBUFCLRCH (Bitfield-Mask: 0x01) */ +/* ======================================================== CMCTLCH ======================================================== */ + #define R_XSPI0_CMCTLCH_XIPENCODE_Pos (0UL) /*!< XIPENCODE (Bit 0) */ + #define R_XSPI0_CMCTLCH_XIPENCODE_Msk (0xffUL) /*!< XIPENCODE (Bitfield-Mask: 0xff) */ + #define R_XSPI0_CMCTLCH_XIPEXCODE_Pos (8UL) /*!< XIPEXCODE (Bit 8) */ + #define R_XSPI0_CMCTLCH_XIPEXCODE_Msk (0xff00UL) /*!< XIPEXCODE (Bitfield-Mask: 0xff) */ + #define R_XSPI0_CMCTLCH_XIPEN_Pos (16UL) /*!< XIPEN (Bit 16) */ + #define R_XSPI0_CMCTLCH_XIPEN_Msk (0x10000UL) /*!< XIPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== CDCTL0 ========================================================= */ + #define R_XSPI0_CDCTL0_TRREQ_Pos (0UL) /*!< TRREQ (Bit 0) */ + #define R_XSPI0_CDCTL0_TRREQ_Msk (0x1UL) /*!< TRREQ (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDCTL0_PERMD_Pos (1UL) /*!< PERMD (Bit 1) */ + #define R_XSPI0_CDCTL0_PERMD_Msk (0x2UL) /*!< PERMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDCTL0_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */ + #define R_XSPI0_CDCTL0_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDCTL0_TRNUM_Pos (4UL) /*!< TRNUM (Bit 4) */ + #define R_XSPI0_CDCTL0_TRNUM_Msk (0x30UL) /*!< TRNUM (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CDCTL0_PERITV_Pos (16UL) /*!< PERITV (Bit 16) */ + #define R_XSPI0_CDCTL0_PERITV_Msk (0x1f0000UL) /*!< PERITV (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CDCTL0_PERREP_Pos (24UL) /*!< PERREP (Bit 24) */ + #define R_XSPI0_CDCTL0_PERREP_Msk (0xf000000UL) /*!< PERREP (Bitfield-Mask: 0x0f) */ +/* ======================================================== CDCTL1 ========================================================= */ + #define R_XSPI0_CDCTL1_PEREXP_Pos (0UL) /*!< PEREXP (Bit 0) */ + #define R_XSPI0_CDCTL1_PEREXP_Msk (0xffffffffUL) /*!< PEREXP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDCTL2 ========================================================= */ + #define R_XSPI0_CDCTL2_PERMSK_Pos (0UL) /*!< PERMSK (Bit 0) */ + #define R_XSPI0_CDCTL2_PERMSK_Msk (0xffffffffUL) /*!< PERMSK (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LPCTL0 ========================================================= */ + #define R_XSPI0_LPCTL0_PATREQ_Pos (0UL) /*!< PATREQ (Bit 0) */ + #define R_XSPI0_LPCTL0_PATREQ_Msk (0x1UL) /*!< PATREQ (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL0_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */ + #define R_XSPI0_LPCTL0_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL0_XDPIN_Pos (4UL) /*!< XDPIN (Bit 4) */ + #define R_XSPI0_LPCTL0_XDPIN_Msk (0x30UL) /*!< XDPIN (Bitfield-Mask: 0x03) */ + #define R_XSPI0_LPCTL0_XD1LEN_Pos (16UL) /*!< XD1LEN (Bit 16) */ + #define R_XSPI0_LPCTL0_XD1LEN_Msk (0x1f0000UL) /*!< XD1LEN (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_LPCTL0_XD1VAL_Pos (23UL) /*!< XD1VAL (Bit 23) */ + #define R_XSPI0_LPCTL0_XD1VAL_Msk (0x800000UL) /*!< XD1VAL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL0_XD2LEN_Pos (24UL) /*!< XD2LEN (Bit 24) */ + #define R_XSPI0_LPCTL0_XD2LEN_Msk (0x1f000000UL) /*!< XD2LEN (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_LPCTL0_XD2VAL_Pos (31UL) /*!< XD2VAL (Bit 31) */ + #define R_XSPI0_LPCTL0_XD2VAL_Msk (0x80000000UL) /*!< XD2VAL (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTL1 ========================================================= */ + #define R_XSPI0_LPCTL1_PATREQ_Pos (0UL) /*!< PATREQ (Bit 0) */ + #define R_XSPI0_LPCTL1_PATREQ_Msk (0x3UL) /*!< PATREQ (Bitfield-Mask: 0x03) */ + #define R_XSPI0_LPCTL1_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */ + #define R_XSPI0_LPCTL1_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL1_RSTREP_Pos (4UL) /*!< RSTREP (Bit 4) */ + #define R_XSPI0_LPCTL1_RSTREP_Msk (0x30UL) /*!< RSTREP (Bitfield-Mask: 0x03) */ + #define R_XSPI0_LPCTL1_RSTWID_Pos (8UL) /*!< RSTWID (Bit 8) */ + #define R_XSPI0_LPCTL1_RSTWID_Msk (0x700UL) /*!< RSTWID (Bitfield-Mask: 0x07) */ + #define R_XSPI0_LPCTL1_RSTSU_Pos (12UL) /*!< RSTSU (Bit 12) */ + #define R_XSPI0_LPCTL1_RSTSU_Msk (0x7000UL) /*!< RSTSU (Bitfield-Mask: 0x07) */ +/* ======================================================== LIOCTL ========================================================= */ + #define R_XSPI0_LIOCTL_WPCS_Pos (0UL) /*!< WPCS (Bit 0) */ + #define R_XSPI0_LIOCTL_WPCS_Msk (0x1UL) /*!< WPCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCTL_RSTCS_Pos (16UL) /*!< RSTCS (Bit 16) */ + #define R_XSPI0_LIOCTL_RSTCS_Msk (0x10000UL) /*!< RSTCS (Bitfield-Mask: 0x01) */ +/* ======================================================== VERSTT ========================================================= */ + #define R_XSPI0_VERSTT_VER_Pos (0UL) /*!< VER (Bit 0) */ + #define R_XSPI0_VERSTT_VER_Msk (0xffffffffUL) /*!< VER (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== COMSTT ========================================================= */ + #define R_XSPI0_COMSTT_MEMACCCH_Pos (0UL) /*!< MEMACCCH (Bit 0) */ + #define R_XSPI0_COMSTT_MEMACCCH_Msk (0x1UL) /*!< MEMACCCH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_PBUFNECH_Pos (4UL) /*!< PBUFNECH (Bit 4) */ + #define R_XSPI0_COMSTT_PBUFNECH_Msk (0x10UL) /*!< PBUFNECH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_WRBUFNECH_Pos (6UL) /*!< WRBUFNECH (Bit 6) */ + #define R_XSPI0_COMSTT_WRBUFNECH_Msk (0x40UL) /*!< WRBUFNECH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_ECSCS_Pos (16UL) /*!< ECSCS (Bit 16) */ + #define R_XSPI0_COMSTT_ECSCS_Msk (0x10000UL) /*!< ECSCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_INTCS_Pos (17UL) /*!< INTCS (Bit 17) */ + #define R_XSPI0_COMSTT_INTCS_Msk (0x20000UL) /*!< INTCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_RSTOCS_Pos (18UL) /*!< RSTOCS (Bit 18) */ + #define R_XSPI0_COMSTT_RSTOCS_Msk (0x40000UL) /*!< RSTOCS (Bitfield-Mask: 0x01) */ +/* ======================================================== CASTTCS ======================================================== */ + #define R_XSPI0_CASTTCS_CASUC_Pos (0UL) /*!< CASUC (Bit 0) */ + #define R_XSPI0_CASTTCS_CASUC_Msk (0xffffffffUL) /*!< CASUC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= INTS ========================================================== */ + #define R_XSPI0_INTS_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ + #define R_XSPI0_INTS_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_PATCMP_Pos (1UL) /*!< PATCMP (Bit 1) */ + #define R_XSPI0_INTS_PATCMP_Msk (0x2UL) /*!< PATCMP (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_INICMP_Pos (2UL) /*!< INICMP (Bit 2) */ + #define R_XSPI0_INTS_INICMP_Msk (0x4UL) /*!< INICMP (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_PERTO_Pos (3UL) /*!< PERTO (Bit 3) */ + #define R_XSPI0_INTS_PERTO_Msk (0x8UL) /*!< PERTO (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_DSTOCS_Pos (4UL) /*!< DSTOCS (Bit 4) */ + #define R_XSPI0_INTS_DSTOCS_Msk (0x10UL) /*!< DSTOCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_ECSCS_Pos (8UL) /*!< ECSCS (Bit 8) */ + #define R_XSPI0_INTS_ECSCS_Msk (0x100UL) /*!< ECSCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_INTCS_Pos (12UL) /*!< INTCS (Bit 12) */ + #define R_XSPI0_INTS_INTCS_Msk (0x1000UL) /*!< INTCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_BRGOFCH_Pos (16UL) /*!< BRGOFCH (Bit 16) */ + #define R_XSPI0_INTS_BRGOFCH_Msk (0x10000UL) /*!< BRGOFCH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_BRGUFCH_Pos (18UL) /*!< BRGUFCH (Bit 18) */ + #define R_XSPI0_INTS_BRGUFCH_Msk (0x40000UL) /*!< BRGUFCH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_BUSERRCH_Pos (20UL) /*!< BUSERRCH (Bit 20) */ + #define R_XSPI0_INTS_BUSERRCH_Msk (0x100000UL) /*!< BUSERRCH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_CAFAILCS_Pos (28UL) /*!< CAFAILCS (Bit 28) */ + #define R_XSPI0_INTS_CAFAILCS_Msk (0x10000000UL) /*!< CAFAILCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_CASUCCS_Pos (30UL) /*!< CASUCCS (Bit 30) */ + #define R_XSPI0_INTS_CASUCCS_Msk (0x40000000UL) /*!< CASUCCS (Bitfield-Mask: 0x01) */ +/* ========================================================= INTC ========================================================== */ + #define R_XSPI0_INTC_CMDCMPC_Pos (0UL) /*!< CMDCMPC (Bit 0) */ + #define R_XSPI0_INTC_CMDCMPC_Msk (0x1UL) /*!< CMDCMPC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_PATCMPC_Pos (1UL) /*!< PATCMPC (Bit 1) */ + #define R_XSPI0_INTC_PATCMPC_Msk (0x2UL) /*!< PATCMPC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_INICMPC_Pos (2UL) /*!< INICMPC (Bit 2) */ + #define R_XSPI0_INTC_INICMPC_Msk (0x4UL) /*!< INICMPC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_PERTOC_Pos (3UL) /*!< PERTOC (Bit 3) */ + #define R_XSPI0_INTC_PERTOC_Msk (0x8UL) /*!< PERTOC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_DSTOCSC_Pos (4UL) /*!< DSTOCSC (Bit 4) */ + #define R_XSPI0_INTC_DSTOCSC_Msk (0x10UL) /*!< DSTOCSC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_ECSCSC_Pos (8UL) /*!< ECSCSC (Bit 8) */ + #define R_XSPI0_INTC_ECSCSC_Msk (0x100UL) /*!< ECSCSC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_INTCSC_Pos (12UL) /*!< INTCSC (Bit 12) */ + #define R_XSPI0_INTC_INTCSC_Msk (0x1000UL) /*!< INTCSC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_BRGOFCHC_Pos (16UL) /*!< BRGOFCHC (Bit 16) */ + #define R_XSPI0_INTC_BRGOFCHC_Msk (0x10000UL) /*!< BRGOFCHC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_BRGUFCHC_Pos (18UL) /*!< BRGUFCHC (Bit 18) */ + #define R_XSPI0_INTC_BRGUFCHC_Msk (0x40000UL) /*!< BRGUFCHC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_BUSERRCHC_Pos (20UL) /*!< BUSERRCHC (Bit 20) */ + #define R_XSPI0_INTC_BUSERRCHC_Msk (0x100000UL) /*!< BUSERRCHC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_CAFAILCSC_Pos (28UL) /*!< CAFAILCSC (Bit 28) */ + #define R_XSPI0_INTC_CAFAILCSC_Msk (0x10000000UL) /*!< CAFAILCSC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_CASUCCSC_Pos (30UL) /*!< CASUCCSC (Bit 30) */ + #define R_XSPI0_INTC_CASUCCSC_Msk (0x40000000UL) /*!< CASUCCSC (Bitfield-Mask: 0x01) */ +/* ========================================================= INTE ========================================================== */ + #define R_XSPI0_INTE_CMDCMPE_Pos (0UL) /*!< CMDCMPE (Bit 0) */ + #define R_XSPI0_INTE_CMDCMPE_Msk (0x1UL) /*!< CMDCMPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_PATCMPE_Pos (1UL) /*!< PATCMPE (Bit 1) */ + #define R_XSPI0_INTE_PATCMPE_Msk (0x2UL) /*!< PATCMPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_INICMPE_Pos (2UL) /*!< INICMPE (Bit 2) */ + #define R_XSPI0_INTE_INICMPE_Msk (0x4UL) /*!< INICMPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_PERTOE_Pos (3UL) /*!< PERTOE (Bit 3) */ + #define R_XSPI0_INTE_PERTOE_Msk (0x8UL) /*!< PERTOE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_DSTOCSE_Pos (4UL) /*!< DSTOCSE (Bit 4) */ + #define R_XSPI0_INTE_DSTOCSE_Msk (0x10UL) /*!< DSTOCSE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_ECSCSE_Pos (8UL) /*!< ECSCSE (Bit 8) */ + #define R_XSPI0_INTE_ECSCSE_Msk (0x100UL) /*!< ECSCSE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_INTCSE_Pos (12UL) /*!< INTCSE (Bit 12) */ + #define R_XSPI0_INTE_INTCSE_Msk (0x1000UL) /*!< INTCSE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_BRGOFCHE_Pos (16UL) /*!< BRGOFCHE (Bit 16) */ + #define R_XSPI0_INTE_BRGOFCHE_Msk (0x10000UL) /*!< BRGOFCHE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_BRGUFCHE_Pos (18UL) /*!< BRGUFCHE (Bit 18) */ + #define R_XSPI0_INTE_BRGUFCHE_Msk (0x40000UL) /*!< BRGUFCHE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_BUSERRCHE_Pos (20UL) /*!< BUSERRCHE (Bit 20) */ + #define R_XSPI0_INTE_BUSERRCHE_Msk (0x100000UL) /*!< BUSERRCHE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_CAFAILCSE_Pos (28UL) /*!< CAFAILCSE (Bit 28) */ + #define R_XSPI0_INTE_CAFAILCSE_Msk (0x10000000UL) /*!< CAFAILCSE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_CASUCCSE_Pos (30UL) /*!< CASUCCSE (Bit 30) */ + #define R_XSPI0_INTE_CASUCCSE_Msk (0x40000000UL) /*!< CASUCCSE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MIPI_PHY ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= DPHYREFCR ======================================================= */ + #define R_MIPI_PHY_DPHYREFCR_RFREQ_Pos (0UL) /*!< RFREQ (Bit 0) */ + #define R_MIPI_PHY_DPHYREFCR_RFREQ_Msk (0xffUL) /*!< RFREQ (Bitfield-Mask: 0xff) */ +/* ======================================================= DPHYPLFCR ======================================================= */ + #define R_MIPI_PHY_DPHYPLFCR_IDIV_Pos (0UL) /*!< IDIV (Bit 0) */ + #define R_MIPI_PHY_DPHYPLFCR_IDIV_Msk (0x3UL) /*!< IDIV (Bitfield-Mask: 0x03) */ + #define R_MIPI_PHY_DPHYPLFCR_NFMUL_Pos (8UL) /*!< NFMUL (Bit 8) */ + #define R_MIPI_PHY_DPHYPLFCR_NFMUL_Msk (0x300UL) /*!< NFMUL (Bitfield-Mask: 0x03) */ + #define R_MIPI_PHY_DPHYPLFCR_PMUL_Pos (12UL) /*!< PMUL (Bit 12) */ + #define R_MIPI_PHY_DPHYPLFCR_PMUL_Msk (0x3000UL) /*!< PMUL (Bitfield-Mask: 0x03) */ + #define R_MIPI_PHY_DPHYPLFCR_NMUL_Pos (16UL) /*!< NMUL (Bit 16) */ + #define R_MIPI_PHY_DPHYPLFCR_NMUL_Msk (0x1ff0000UL) /*!< NMUL (Bitfield-Mask: 0x1ff) */ +/* ======================================================= DPHYPLOCR ======================================================= */ + #define R_MIPI_PHY_DPHYPLOCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_MIPI_PHY_DPHYPLOCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= DPHYESCCR ======================================================= */ + #define R_MIPI_PHY_DPHYESCCR_ESCDIV_Pos (0UL) /*!< ESCDIV (Bit 0) */ + #define R_MIPI_PHY_DPHYESCCR_ESCDIV_Msk (0x1fUL) /*!< ESCDIV (Bitfield-Mask: 0x1f) */ +/* ======================================================= DPHYPWRCR ======================================================= */ + #define R_MIPI_PHY_DPHYPWRCR_PWRSEN_Pos (0UL) /*!< PWRSEN (Bit 0) */ + #define R_MIPI_PHY_DPHYPWRCR_PWRSEN_Msk (0x1UL) /*!< PWRSEN (Bitfield-Mask: 0x01) */ +/* ======================================================== DPHYSFR ======================================================== */ + #define R_MIPI_PHY_DPHYSFR_PWRSF_Pos (0UL) /*!< PWRSF (Bit 0) */ + #define R_MIPI_PHY_DPHYSFR_PWRSF_Msk (0x1UL) /*!< PWRSF (Bitfield-Mask: 0x01) */ + #define R_MIPI_PHY_DPHYSFR_PLLSF_Pos (8UL) /*!< PLLSF (Bit 8) */ + #define R_MIPI_PHY_DPHYSFR_PLLSF_Msk (0x100UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPHYOCR ======================================================== */ + #define R_MIPI_PHY_DPHYOCR_DPHYEN_Pos (0UL) /*!< DPHYEN (Bit 0) */ + #define R_MIPI_PHY_DPHYOCR_DPHYEN_Msk (0x1UL) /*!< DPHYEN (Bitfield-Mask: 0x01) */ +/* ======================================================= DPHYTIM1 ======================================================== */ + #define R_MIPI_PHY_DPHYTIM1_TINIT_Pos (0UL) /*!< TINIT (Bit 0) */ + #define R_MIPI_PHY_DPHYTIM1_TINIT_Msk (0x7ffffUL) /*!< TINIT (Bitfield-Mask: 0x7ffff) */ +/* ======================================================= DPHYTIM2 ======================================================== */ + #define R_MIPI_PHY_DPHYTIM2_TCLKPREP_Pos (0UL) /*!< TCLKPREP (Bit 0) */ + #define R_MIPI_PHY_DPHYTIM2_TCLKPREP_Msk (0xffUL) /*!< TCLKPREP (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM2_TCLKSETT_Pos (8UL) /*!< TCLKSETT (Bit 8) */ + #define R_MIPI_PHY_DPHYTIM2_TCLKSETT_Msk (0xff00UL) /*!< TCLKSETT (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM2_TCLKMISS_Pos (16UL) /*!< TCLKMISS (Bit 16) */ + #define R_MIPI_PHY_DPHYTIM2_TCLKMISS_Msk (0xff0000UL) /*!< TCLKMISS (Bitfield-Mask: 0xff) */ +/* ======================================================= DPHYTIM3 ======================================================== */ + #define R_MIPI_PHY_DPHYTIM3_THSPREP_Pos (0UL) /*!< THSPREP (Bit 0) */ + #define R_MIPI_PHY_DPHYTIM3_THSPREP_Msk (0xffUL) /*!< THSPREP (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM3_THSSETT_Pos (8UL) /*!< THSSETT (Bit 8) */ + #define R_MIPI_PHY_DPHYTIM3_THSSETT_Msk (0xff00UL) /*!< THSSETT (Bitfield-Mask: 0xff) */ +/* ======================================================= DPHYTIM4 ======================================================== */ + #define R_MIPI_PHY_DPHYTIM4_TCLKZERO_Pos (0UL) /*!< TCLKZERO (Bit 0) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKZERO_Msk (0xffUL) /*!< TCLKZERO (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKPRE_Pos (8UL) /*!< TCLKPRE (Bit 8) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKPRE_Msk (0xff00UL) /*!< TCLKPRE (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKPOST_Pos (16UL) /*!< TCLKPOST (Bit 16) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKPOST_Msk (0xff0000UL) /*!< TCLKPOST (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKTRL_Pos (24UL) /*!< TCLKTRL (Bit 24) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKTRL_Msk (0xff000000UL) /*!< TCLKTRL (Bitfield-Mask: 0xff) */ +/* ======================================================= DPHYTIM5 ======================================================== */ + #define R_MIPI_PHY_DPHYTIM5_THSZERO_Pos (0UL) /*!< THSZERO (Bit 0) */ + #define R_MIPI_PHY_DPHYTIM5_THSZERO_Msk (0xffUL) /*!< THSZERO (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM5_THSTRL_Pos (8UL) /*!< THSTRL (Bit 8) */ + #define R_MIPI_PHY_DPHYTIM5_THSTRL_Msk (0xff00UL) /*!< THSTRL (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM5_THSEXIT_Pos (16UL) /*!< THSEXIT (Bit 16) */ + #define R_MIPI_PHY_DPHYTIM5_THSEXIT_Msk (0xff0000UL) /*!< THSEXIT (Bitfield-Mask: 0xff) */ +/* ======================================================= DPHYTIM6 ======================================================== */ + #define R_MIPI_PHY_DPHYTIM6_TLPX_Pos (0UL) /*!< TLPX (Bit 0) */ + #define R_MIPI_PHY_DPHYTIM6_TLPX_Msk (0xffUL) /*!< TLPX (Bitfield-Mask: 0xff) */ +/* ======================================================== DPHYMDC ======================================================== */ + #define R_MIPI_PHY_DPHYMDC_MASTEREN_Pos (0UL) /*!< MASTEREN (Bit 0) */ + #define R_MIPI_PHY_DPHYMDC_MASTEREN_Msk (0x1UL) /*!< MASTEREN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MIPI_CSI ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MCG ========================================================== */ + #define R_MIPI_CSI_MCG_VER_Pos (0UL) /*!< VER (Bit 0) */ + #define R_MIPI_CSI_MCG_VER_Msk (0xfUL) /*!< VER (Bitfield-Mask: 0x0f) */ + #define R_MIPI_CSI_MCG_SDLN_Pos (8UL) /*!< SDLN (Bit 8) */ + #define R_MIPI_CSI_MCG_SDLN_Msk (0xf00UL) /*!< SDLN (Bitfield-Mask: 0x0f) */ + #define R_MIPI_CSI_MCG_GSNM_Pos (16UL) /*!< GSNM (Bit 16) */ + #define R_MIPI_CSI_MCG_GSNM_Msk (0xff0000UL) /*!< GSNM (Bitfield-Mask: 0xff) */ +/* ========================================================= MCT0 ========================================================== */ + #define R_MIPI_CSI_MCT0_VDLN_Pos (0UL) /*!< VDLN (Bit 0) */ + #define R_MIPI_CSI_MCT0_VDLN_Msk (0xfUL) /*!< VDLN (Bitfield-Mask: 0x0f) */ + #define R_MIPI_CSI_MCT0_ZLMD_Pos (16UL) /*!< ZLMD (Bit 16) */ + #define R_MIPI_CSI_MCT0_ZLMD_Msk (0x10000UL) /*!< ZLMD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MCT0_EDMD_Pos (17UL) /*!< EDMD (Bit 17) */ + #define R_MIPI_CSI_MCT0_EDMD_Msk (0x20000UL) /*!< EDMD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MCT0_RVMD_Pos (19UL) /*!< RVMD (Bit 19) */ + #define R_MIPI_CSI_MCT0_RVMD_Msk (0x80000UL) /*!< RVMD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MCT0_GRMD_Pos (20UL) /*!< GRMD (Bit 20) */ + #define R_MIPI_CSI_MCT0_GRMD_Msk (0x100000UL) /*!< GRMD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MCT0_ECCV13_Pos (24UL) /*!< ECCV13 (Bit 24) */ + #define R_MIPI_CSI_MCT0_ECCV13_Msk (0x1000000UL) /*!< ECCV13 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MCT0_LFSREN_Pos (25UL) /*!< LFSREN (Bit 25) */ + #define R_MIPI_CSI_MCT0_LFSREN_Msk (0x2000000UL) /*!< LFSREN (Bitfield-Mask: 0x01) */ +/* ========================================================= MCT2 ========================================================== */ + #define R_MIPI_CSI_MCT2_FRRCLK_Pos (0UL) /*!< FRRCLK (Bit 0) */ + #define R_MIPI_CSI_MCT2_FRRCLK_Msk (0x1ffUL) /*!< FRRCLK (Bitfield-Mask: 0x1ff) */ + #define R_MIPI_CSI_MCT2_FRRSKW_Pos (16UL) /*!< FRRSKW (Bit 16) */ + #define R_MIPI_CSI_MCT2_FRRSKW_Msk (0x1ff0000UL) /*!< FRRSKW (Bitfield-Mask: 0x1ff) */ +/* ========================================================= MCT3 ========================================================== */ + #define R_MIPI_CSI_MCT3_RXEN_Pos (0UL) /*!< RXEN (Bit 0) */ + #define R_MIPI_CSI_MCT3_RXEN_Msk (0x1UL) /*!< RXEN (Bitfield-Mask: 0x01) */ +/* ========================================================= RTCT ========================================================== */ + #define R_MIPI_CSI_RTCT_VSRST_Pos (0UL) /*!< VSRST (Bit 0) */ + #define R_MIPI_CSI_RTCT_VSRST_Msk (0x1UL) /*!< VSRST (Bitfield-Mask: 0x01) */ +/* ========================================================= RTST ========================================================== */ + #define R_MIPI_CSI_RTST_VSRSTS_Pos (0UL) /*!< VSRSTS (Bit 0) */ + #define R_MIPI_CSI_RTST_VSRSTS_Msk (0x1UL) /*!< VSRSTS (Bitfield-Mask: 0x01) */ +/* ========================================================= EPCT ========================================================== */ + #define R_MIPI_CSI_EPCT_SLP_Pos (0UL) /*!< SLP (Bit 0) */ + #define R_MIPI_CSI_EPCT_SLP_Msk (0x7fffUL) /*!< SLP (Bitfield-Mask: 0x7fff) */ + #define R_MIPI_CSI_EPCT_EPDOP_Pos (15UL) /*!< EPDOP (Bit 15) */ + #define R_MIPI_CSI_EPCT_EPDOP_Msk (0x8000UL) /*!< EPDOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_EPCT_SSP_Pos (16UL) /*!< SSP (Bit 16) */ + #define R_MIPI_CSI_EPCT_SSP_Msk (0x7fff0000UL) /*!< SSP (Bitfield-Mask: 0x7fff) */ + #define R_MIPI_CSI_EPCT_EPDEN_Pos (31UL) /*!< EPDEN (Bit 31) */ + #define R_MIPI_CSI_EPCT_EPDEN_Msk (0x80000000UL) /*!< EPDEN (Bitfield-Mask: 0x01) */ +/* ========================================================= EMCT ========================================================== */ + #define R_MIPI_CSI_EMCT_VLSIEN_Pos (4UL) /*!< VLSIEN (Bit 4) */ + #define R_MIPI_CSI_EMCT_VLSIEN_Msk (0x30UL) /*!< VLSIEN (Bitfield-Mask: 0x03) */ + #define R_MIPI_CSI_EMCT_EOTPEN_Pos (6UL) /*!< EOTPEN (Bit 6) */ + #define R_MIPI_CSI_EMCT_EOTPEN_Msk (0x40UL) /*!< EOTPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= MIST ========================================================== */ + #define R_MIPI_CSI_MIST_DL0S_Pos (0UL) /*!< DL0S (Bit 0) */ + #define R_MIPI_CSI_MIST_DL0S_Msk (0x1UL) /*!< DL0S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_DL1S_Pos (1UL) /*!< DL1S (Bit 1) */ + #define R_MIPI_CSI_MIST_DL1S_Msk (0x2UL) /*!< DL1S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_PMS_Pos (8UL) /*!< PMS (Bit 8) */ + #define R_MIPI_CSI_MIST_PMS_Msk (0x100UL) /*!< PMS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_GSTS_Pos (9UL) /*!< GSTS (Bit 9) */ + #define R_MIPI_CSI_MIST_GSTS_Msk (0x200UL) /*!< GSTS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_RXS_Pos (10UL) /*!< RXS (Bit 10) */ + #define R_MIPI_CSI_MIST_RXS_Msk (0x400UL) /*!< RXS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC0S_Pos (16UL) /*!< VC0S (Bit 16) */ + #define R_MIPI_CSI_MIST_VC0S_Msk (0x10000UL) /*!< VC0S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC1S_Pos (17UL) /*!< VC1S (Bit 17) */ + #define R_MIPI_CSI_MIST_VC1S_Msk (0x20000UL) /*!< VC1S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC2S_Pos (18UL) /*!< VC2S (Bit 18) */ + #define R_MIPI_CSI_MIST_VC2S_Msk (0x40000UL) /*!< VC2S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC3S_Pos (19UL) /*!< VC3S (Bit 19) */ + #define R_MIPI_CSI_MIST_VC3S_Msk (0x80000UL) /*!< VC3S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC4S_Pos (20UL) /*!< VC4S (Bit 20) */ + #define R_MIPI_CSI_MIST_VC4S_Msk (0x100000UL) /*!< VC4S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC5S_Pos (21UL) /*!< VC5S (Bit 21) */ + #define R_MIPI_CSI_MIST_VC5S_Msk (0x200000UL) /*!< VC5S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC6S_Pos (22UL) /*!< VC6S (Bit 22) */ + #define R_MIPI_CSI_MIST_VC6S_Msk (0x400000UL) /*!< VC6S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC7S_Pos (23UL) /*!< VC7S (Bit 23) */ + #define R_MIPI_CSI_MIST_VC7S_Msk (0x800000UL) /*!< VC7S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC8S_Pos (24UL) /*!< VC8S (Bit 24) */ + #define R_MIPI_CSI_MIST_VC8S_Msk (0x1000000UL) /*!< VC8S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC9S_Pos (25UL) /*!< VC9S (Bit 25) */ + #define R_MIPI_CSI_MIST_VC9S_Msk (0x2000000UL) /*!< VC9S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC10S_Pos (26UL) /*!< VC10S (Bit 26) */ + #define R_MIPI_CSI_MIST_VC10S_Msk (0x4000000UL) /*!< VC10S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC11S_Pos (27UL) /*!< VC11S (Bit 27) */ + #define R_MIPI_CSI_MIST_VC11S_Msk (0x8000000UL) /*!< VC11S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC12S_Pos (28UL) /*!< VC12S (Bit 28) */ + #define R_MIPI_CSI_MIST_VC12S_Msk (0x10000000UL) /*!< VC12S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC13S_Pos (29UL) /*!< VC13S (Bit 29) */ + #define R_MIPI_CSI_MIST_VC13S_Msk (0x20000000UL) /*!< VC13S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC14S_Pos (30UL) /*!< VC14S (Bit 30) */ + #define R_MIPI_CSI_MIST_VC14S_Msk (0x40000000UL) /*!< VC14S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC15S_Pos (31UL) /*!< VC15S (Bit 31) */ + #define R_MIPI_CSI_MIST_VC15S_Msk (0x80000000UL) /*!< VC15S (Bitfield-Mask: 0x01) */ +/* ========================================================= DTEL ========================================================== */ + #define R_MIPI_CSI_DTEL_DTEN_Pos (0UL) /*!< DTEN (Bit 0) */ + #define R_MIPI_CSI_DTEL_DTEN_Msk (0xffffffffUL) /*!< DTEN (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTEH ========================================================== */ + #define R_MIPI_CSI_DTEH_DTEN_Pos (0UL) /*!< DTEN (Bit 0) */ + #define R_MIPI_CSI_DTEH_DTEN_Msk (0xffffffffUL) /*!< DTEN (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RXST ========================================================== */ + #define R_MIPI_CSI_RXST_FRM0_Pos (0UL) /*!< FRM0 (Bit 0) */ + #define R_MIPI_CSI_RXST_FRM0_Msk (0x1UL) /*!< FRM0 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM1_Pos (1UL) /*!< FRM1 (Bit 1) */ + #define R_MIPI_CSI_RXST_FRM1_Msk (0x2UL) /*!< FRM1 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM2_Pos (2UL) /*!< FRM2 (Bit 2) */ + #define R_MIPI_CSI_RXST_FRM2_Msk (0x4UL) /*!< FRM2 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM3_Pos (3UL) /*!< FRM3 (Bit 3) */ + #define R_MIPI_CSI_RXST_FRM3_Msk (0x8UL) /*!< FRM3 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM4_Pos (4UL) /*!< FRM4 (Bit 4) */ + #define R_MIPI_CSI_RXST_FRM4_Msk (0x10UL) /*!< FRM4 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM5_Pos (5UL) /*!< FRM5 (Bit 5) */ + #define R_MIPI_CSI_RXST_FRM5_Msk (0x20UL) /*!< FRM5 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM6_Pos (6UL) /*!< FRM6 (Bit 6) */ + #define R_MIPI_CSI_RXST_FRM6_Msk (0x40UL) /*!< FRM6 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM7_Pos (7UL) /*!< FRM7 (Bit 7) */ + #define R_MIPI_CSI_RXST_FRM7_Msk (0x80UL) /*!< FRM7 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM8_Pos (8UL) /*!< FRM8 (Bit 8) */ + #define R_MIPI_CSI_RXST_FRM8_Msk (0x100UL) /*!< FRM8 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM9_Pos (9UL) /*!< FRM9 (Bit 9) */ + #define R_MIPI_CSI_RXST_FRM9_Msk (0x200UL) /*!< FRM9 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM10_Pos (10UL) /*!< FRM10 (Bit 10) */ + #define R_MIPI_CSI_RXST_FRM10_Msk (0x400UL) /*!< FRM10 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM11_Pos (11UL) /*!< FRM11 (Bit 11) */ + #define R_MIPI_CSI_RXST_FRM11_Msk (0x800UL) /*!< FRM11 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM12_Pos (12UL) /*!< FRM12 (Bit 12) */ + #define R_MIPI_CSI_RXST_FRM12_Msk (0x1000UL) /*!< FRM12 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM13_Pos (13UL) /*!< FRM13 (Bit 13) */ + #define R_MIPI_CSI_RXST_FRM13_Msk (0x2000UL) /*!< FRM13 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM14_Pos (14UL) /*!< FRM14 (Bit 14) */ + #define R_MIPI_CSI_RXST_FRM14_Msk (0x4000UL) /*!< FRM14 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM15_Pos (15UL) /*!< FRM15 (Bit 15) */ + #define R_MIPI_CSI_RXST_FRM15_Msk (0x8000UL) /*!< FRM15 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_RACT_Pos (16UL) /*!< RACT (Bit 16) */ + #define R_MIPI_CSI_RXST_RACT_Msk (0x10000UL) /*!< RACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_RACTDET_Pos (17UL) /*!< RACTDET (Bit 17) */ + #define R_MIPI_CSI_RXST_RACTDET_Msk (0x20000UL) /*!< RACTDET (Bitfield-Mask: 0x01) */ +/* ========================================================= RXSC ========================================================== */ + #define R_MIPI_CSI_RXSC_RACTDETC_Pos (17UL) /*!< RACTDETC (Bit 17) */ + #define R_MIPI_CSI_RXSC_RACTDETC_Msk (0x20000UL) /*!< RACTDETC (Bitfield-Mask: 0x01) */ +/* ========================================================= RXIE ========================================================== */ + #define R_MIPI_CSI_RXIE_RACTDETE_Pos (17UL) /*!< RACTDETE (Bit 17) */ + #define R_MIPI_CSI_RXIE_RACTDETE_Msk (0x20000UL) /*!< RACTDETE (Bitfield-Mask: 0x01) */ +/* ========================================================= DLST0 ========================================================= */ + #define R_MIPI_CSI_DLST0_ESH_Pos (0UL) /*!< ESH (Bit 0) */ + #define R_MIPI_CSI_DLST0_ESH_Msk (0x1UL) /*!< ESH (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST0_ESS_Pos (1UL) /*!< ESS (Bit 1) */ + #define R_MIPI_CSI_DLST0_ESS_Msk (0x2UL) /*!< ESS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST0_ECT_Pos (2UL) /*!< ECT (Bit 2) */ + #define R_MIPI_CSI_DLST0_ECT_Msk (0x4UL) /*!< ECT (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST0_EES_Pos (3UL) /*!< EES (Bit 3) */ + #define R_MIPI_CSI_DLST0_EES_Msk (0x8UL) /*!< EES (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST0_EUL_Pos (16UL) /*!< EUL (Bit 16) */ + #define R_MIPI_CSI_DLST0_EUL_Msk (0x10000UL) /*!< EUL (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST0_RUL_Pos (17UL) /*!< RUL (Bit 17) */ + #define R_MIPI_CSI_DLST0_RUL_Msk (0x20000UL) /*!< RUL (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST0_ULP_Pos (24UL) /*!< ULP (Bit 24) */ + #define R_MIPI_CSI_DLST0_ULP_Msk (0x1000000UL) /*!< ULP (Bitfield-Mask: 0x01) */ +/* ========================================================= DLST1 ========================================================= */ + #define R_MIPI_CSI_DLST1_ESH_Pos (0UL) /*!< ESH (Bit 0) */ + #define R_MIPI_CSI_DLST1_ESH_Msk (0x1UL) /*!< ESH (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST1_ESS_Pos (1UL) /*!< ESS (Bit 1) */ + #define R_MIPI_CSI_DLST1_ESS_Msk (0x2UL) /*!< ESS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST1_ECT_Pos (2UL) /*!< ECT (Bit 2) */ + #define R_MIPI_CSI_DLST1_ECT_Msk (0x4UL) /*!< ECT (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST1_EES_Pos (3UL) /*!< EES (Bit 3) */ + #define R_MIPI_CSI_DLST1_EES_Msk (0x8UL) /*!< EES (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST1_EUL_Pos (16UL) /*!< EUL (Bit 16) */ + #define R_MIPI_CSI_DLST1_EUL_Msk (0x10000UL) /*!< EUL (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST1_RUL_Pos (17UL) /*!< RUL (Bit 17) */ + #define R_MIPI_CSI_DLST1_RUL_Msk (0x20000UL) /*!< RUL (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST1_ULP_Pos (24UL) /*!< ULP (Bit 24) */ + #define R_MIPI_CSI_DLST1_ULP_Msk (0x1000000UL) /*!< ULP (Bitfield-Mask: 0x01) */ +/* ========================================================= DLSC0 ========================================================= */ + #define R_MIPI_CSI_DLSC0_ESHC_Pos (0UL) /*!< ESHC (Bit 0) */ + #define R_MIPI_CSI_DLSC0_ESHC_Msk (0x1UL) /*!< ESHC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC0_ESSC_Pos (1UL) /*!< ESSC (Bit 1) */ + #define R_MIPI_CSI_DLSC0_ESSC_Msk (0x2UL) /*!< ESSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC0_ECTC_Pos (2UL) /*!< ECTC (Bit 2) */ + #define R_MIPI_CSI_DLSC0_ECTC_Msk (0x4UL) /*!< ECTC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC0_EESC_Pos (3UL) /*!< EESC (Bit 3) */ + #define R_MIPI_CSI_DLSC0_EESC_Msk (0x8UL) /*!< EESC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC0_EULC_Pos (16UL) /*!< EULC (Bit 16) */ + #define R_MIPI_CSI_DLSC0_EULC_Msk (0x10000UL) /*!< EULC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC0_RULC_Pos (17UL) /*!< RULC (Bit 17) */ + #define R_MIPI_CSI_DLSC0_RULC_Msk (0x20000UL) /*!< RULC (Bitfield-Mask: 0x01) */ +/* ========================================================= DLSC1 ========================================================= */ + #define R_MIPI_CSI_DLSC1_ESHC_Pos (0UL) /*!< ESHC (Bit 0) */ + #define R_MIPI_CSI_DLSC1_ESHC_Msk (0x1UL) /*!< ESHC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC1_ESSC_Pos (1UL) /*!< ESSC (Bit 1) */ + #define R_MIPI_CSI_DLSC1_ESSC_Msk (0x2UL) /*!< ESSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC1_ECTC_Pos (2UL) /*!< ECTC (Bit 2) */ + #define R_MIPI_CSI_DLSC1_ECTC_Msk (0x4UL) /*!< ECTC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC1_EESC_Pos (3UL) /*!< EESC (Bit 3) */ + #define R_MIPI_CSI_DLSC1_EESC_Msk (0x8UL) /*!< EESC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC1_EULC_Pos (16UL) /*!< EULC (Bit 16) */ + #define R_MIPI_CSI_DLSC1_EULC_Msk (0x10000UL) /*!< EULC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC1_RULC_Pos (17UL) /*!< RULC (Bit 17) */ + #define R_MIPI_CSI_DLSC1_RULC_Msk (0x20000UL) /*!< RULC (Bitfield-Mask: 0x01) */ +/* ========================================================= DLIE0 ========================================================= */ + #define R_MIPI_CSI_DLIE0_ESHE_Pos (0UL) /*!< ESHE (Bit 0) */ + #define R_MIPI_CSI_DLIE0_ESHE_Msk (0x1UL) /*!< ESHE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE0_ESSE_Pos (1UL) /*!< ESSE (Bit 1) */ + #define R_MIPI_CSI_DLIE0_ESSE_Msk (0x2UL) /*!< ESSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE0_ECTE_Pos (2UL) /*!< ECTE (Bit 2) */ + #define R_MIPI_CSI_DLIE0_ECTE_Msk (0x4UL) /*!< ECTE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE0_EESE_Pos (3UL) /*!< EESE (Bit 3) */ + #define R_MIPI_CSI_DLIE0_EESE_Msk (0x8UL) /*!< EESE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE0_EULE_Pos (16UL) /*!< EULE (Bit 16) */ + #define R_MIPI_CSI_DLIE0_EULE_Msk (0x10000UL) /*!< EULE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE0_RULE_Pos (17UL) /*!< RULE (Bit 17) */ + #define R_MIPI_CSI_DLIE0_RULE_Msk (0x20000UL) /*!< RULE (Bitfield-Mask: 0x01) */ +/* ========================================================= DLIE1 ========================================================= */ + #define R_MIPI_CSI_DLIE1_ESHE_Pos (0UL) /*!< ESHE (Bit 0) */ + #define R_MIPI_CSI_DLIE1_ESHE_Msk (0x1UL) /*!< ESHE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE1_ESSE_Pos (1UL) /*!< ESSE (Bit 1) */ + #define R_MIPI_CSI_DLIE1_ESSE_Msk (0x2UL) /*!< ESSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE1_ECTE_Pos (2UL) /*!< ECTE (Bit 2) */ + #define R_MIPI_CSI_DLIE1_ECTE_Msk (0x4UL) /*!< ECTE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE1_EESE_Pos (3UL) /*!< EESE (Bit 3) */ + #define R_MIPI_CSI_DLIE1_EESE_Msk (0x8UL) /*!< EESE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE1_EULE_Pos (16UL) /*!< EULE (Bit 16) */ + #define R_MIPI_CSI_DLIE1_EULE_Msk (0x10000UL) /*!< EULE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE1_RULE_Pos (17UL) /*!< RULE (Bit 17) */ + #define R_MIPI_CSI_DLIE1_RULE_Msk (0x20000UL) /*!< RULE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST0 ========================================================= */ + #define R_MIPI_CSI_VCST0_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST0_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST0_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST0_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST0_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST0_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST0_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST0_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST0_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST0_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST0_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST0_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST0_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST0_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST0_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST0_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST1 ========================================================= */ + #define R_MIPI_CSI_VCST1_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST1_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST1_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST1_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST1_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST1_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST1_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST1_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST1_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST1_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST1_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST1_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST1_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST1_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST1_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST1_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST2 ========================================================= */ + #define R_MIPI_CSI_VCST2_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST2_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST2_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST2_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST2_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST2_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST2_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST2_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST2_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST2_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST2_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST2_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST2_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST2_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST2_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST2_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST3 ========================================================= */ + #define R_MIPI_CSI_VCST3_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST3_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST3_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST3_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST3_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST3_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST3_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST3_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST3_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST3_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST3_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST3_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST3_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST3_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST3_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST3_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST4 ========================================================= */ + #define R_MIPI_CSI_VCST4_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST4_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST4_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST4_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST4_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST4_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST4_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST4_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST4_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST4_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST4_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST4_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST4_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST4_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST4_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST4_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST5 ========================================================= */ + #define R_MIPI_CSI_VCST5_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST5_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST5_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST5_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST5_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST5_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST5_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST5_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST5_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST5_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST5_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST5_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST5_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST5_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST5_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST5_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST6 ========================================================= */ + #define R_MIPI_CSI_VCST6_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST6_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST6_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST6_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST6_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST6_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST6_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST6_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST6_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST6_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST6_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST6_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST6_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST6_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST6_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST6_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST7 ========================================================= */ + #define R_MIPI_CSI_VCST7_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST7_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST7_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST7_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST7_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST7_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST7_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST7_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST7_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST7_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST7_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST7_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST7_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST7_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST7_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST7_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST8 ========================================================= */ + #define R_MIPI_CSI_VCST8_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST8_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST8_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST8_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST8_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST8_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST8_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST8_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST8_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST8_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST8_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST8_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST8_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST8_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST8_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST8_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST9 ========================================================= */ + #define R_MIPI_CSI_VCST9_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST9_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST9_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST9_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST9_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST9_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST9_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST9_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST9_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST9_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST9_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST9_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST9_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST9_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST9_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST9_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ======================================================== VCST10 ========================================================= */ + #define R_MIPI_CSI_VCST10_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST10_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST10_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST10_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST10_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST10_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST10_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST10_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST10_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST10_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST10_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST10_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST10_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST10_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST10_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST10_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ======================================================== VCST11 ========================================================= */ + #define R_MIPI_CSI_VCST11_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST11_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST11_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST11_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST11_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST11_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST11_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST11_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST11_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST11_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST11_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST11_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST11_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST11_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST11_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST11_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ======================================================== VCST12 ========================================================= */ + #define R_MIPI_CSI_VCST12_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST12_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST12_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST12_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST12_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST12_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST12_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST12_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST12_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST12_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST12_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST12_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST12_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST12_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST12_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST12_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ======================================================== VCST13 ========================================================= */ + #define R_MIPI_CSI_VCST13_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST13_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST13_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST13_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST13_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST13_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST13_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST13_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST13_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST13_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST13_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST13_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST13_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST13_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST13_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST13_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ======================================================== VCST14 ========================================================= */ + #define R_MIPI_CSI_VCST14_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST14_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST14_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST14_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST14_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST14_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST14_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST14_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST14_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST14_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST14_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST14_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST14_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST14_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST14_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST14_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ======================================================== VCST15 ========================================================= */ + #define R_MIPI_CSI_VCST15_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST15_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST15_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST15_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST15_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST15_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST15_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST15_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST15_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST15_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST15_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST15_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST15_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST15_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST15_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST15_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC0 ========================================================= */ + #define R_MIPI_CSI_VCSC0_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC0_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC0_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC0_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC0_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC0_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC0_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC0_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC0_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC0_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC0_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC0_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC0_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC0_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC0_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC0_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC0_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC0_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC1 ========================================================= */ + #define R_MIPI_CSI_VCSC1_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC1_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC1_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC1_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC1_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC1_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC1_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC1_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC1_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC1_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC1_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC1_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC1_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC1_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC1_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC1_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC1_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC1_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC2 ========================================================= */ + #define R_MIPI_CSI_VCSC2_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC2_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC2_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC2_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC2_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC2_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC2_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC2_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC2_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC2_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC2_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC2_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC2_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC2_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC2_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC2_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC2_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC2_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC3 ========================================================= */ + #define R_MIPI_CSI_VCSC3_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC3_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC3_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC3_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC3_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC3_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC3_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC3_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC3_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC3_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC3_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC3_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC3_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC3_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC3_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC3_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC3_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC3_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC4 ========================================================= */ + #define R_MIPI_CSI_VCSC4_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC4_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC4_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC4_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC4_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC4_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC4_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC4_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC4_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC4_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC4_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC4_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC4_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC4_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC4_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC4_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC4_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC4_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC5 ========================================================= */ + #define R_MIPI_CSI_VCSC5_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC5_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC5_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC5_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC5_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC5_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC5_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC5_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC5_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC5_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC5_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC5_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC5_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC5_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC5_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC5_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC5_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC5_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC6 ========================================================= */ + #define R_MIPI_CSI_VCSC6_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC6_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC6_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC6_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC6_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC6_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC6_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC6_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC6_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC6_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC6_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC6_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC6_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC6_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC6_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC6_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC6_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC6_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC7 ========================================================= */ + #define R_MIPI_CSI_VCSC7_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC7_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC7_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC7_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC7_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC7_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC7_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC7_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC7_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC7_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC7_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC7_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC7_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC7_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC7_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC7_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC7_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC7_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC8 ========================================================= */ + #define R_MIPI_CSI_VCSC8_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC8_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC8_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC8_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC8_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC8_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC8_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC8_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC8_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC8_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC8_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC8_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC8_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC8_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC8_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC8_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC8_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC8_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC9 ========================================================= */ + #define R_MIPI_CSI_VCSC9_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC9_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC9_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC9_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC9_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC9_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC9_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC9_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC9_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC9_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC9_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC9_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC9_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC9_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC9_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC9_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC9_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC9_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ======================================================== VCSC10 ========================================================= */ + #define R_MIPI_CSI_VCSC10_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC10_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC10_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC10_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC10_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC10_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC10_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC10_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC10_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC10_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC10_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC10_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC10_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC10_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC10_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC10_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC10_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC10_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ======================================================== VCSC11 ========================================================= */ + #define R_MIPI_CSI_VCSC11_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC11_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC11_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC11_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC11_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC11_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC11_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC11_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC11_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC11_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC11_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC11_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC11_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC11_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC11_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC11_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC11_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC11_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ======================================================== VCSC12 ========================================================= */ + #define R_MIPI_CSI_VCSC12_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC12_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC12_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC12_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC12_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC12_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC12_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC12_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC12_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC12_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC12_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC12_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC12_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC12_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC12_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC12_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC12_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC12_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ======================================================== VCSC13 ========================================================= */ + #define R_MIPI_CSI_VCSC13_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC13_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC13_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC13_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC13_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC13_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC13_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC13_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC13_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC13_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC13_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC13_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC13_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC13_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC13_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC13_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC13_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC13_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ======================================================== VCSC14 ========================================================= */ + #define R_MIPI_CSI_VCSC14_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC14_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC14_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC14_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC14_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC14_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC14_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC14_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC14_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC14_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC14_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC14_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC14_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC14_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC14_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC14_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC14_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC14_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ======================================================== VCSC15 ========================================================= */ + #define R_MIPI_CSI_VCSC15_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC15_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC15_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC15_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC15_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC15_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC15_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC15_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC15_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC15_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC15_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC15_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC15_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC15_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC15_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC15_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC15_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC15_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE0 ========================================================= */ + #define R_MIPI_CSI_VCIE0_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE0_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE0_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE0_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE0_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE0_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE0_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE0_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE0_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE0_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE0_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE0_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE0_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE0_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE0_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE0_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE1 ========================================================= */ + #define R_MIPI_CSI_VCIE1_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE1_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE1_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE1_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE1_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE1_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE1_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE1_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE1_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE1_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE1_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE1_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE1_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE1_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE1_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE1_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE2 ========================================================= */ + #define R_MIPI_CSI_VCIE2_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE2_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE2_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE2_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE2_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE2_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE2_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE2_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE2_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE2_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE2_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE2_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE2_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE2_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE2_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE2_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE3 ========================================================= */ + #define R_MIPI_CSI_VCIE3_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE3_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE3_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE3_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE3_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE3_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE3_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE3_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE3_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE3_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE3_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE3_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE3_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE3_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE3_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE3_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE4 ========================================================= */ + #define R_MIPI_CSI_VCIE4_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE4_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE4_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE4_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE4_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE4_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE4_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE4_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE4_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE4_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE4_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE4_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE4_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE4_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE4_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE4_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE5 ========================================================= */ + #define R_MIPI_CSI_VCIE5_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE5_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE5_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE5_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE5_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE5_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE5_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE5_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE5_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE5_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE5_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE5_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE5_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE5_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE5_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE5_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE6 ========================================================= */ + #define R_MIPI_CSI_VCIE6_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE6_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE6_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE6_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE6_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE6_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE6_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE6_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE6_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE6_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE6_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE6_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE6_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE6_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE6_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE6_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE7 ========================================================= */ + #define R_MIPI_CSI_VCIE7_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE7_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE7_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE7_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE7_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE7_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE7_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE7_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE7_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE7_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE7_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE7_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE7_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE7_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE7_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE7_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE8 ========================================================= */ + #define R_MIPI_CSI_VCIE8_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE8_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE8_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE8_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE8_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE8_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE8_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE8_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE8_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE8_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE8_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE8_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE8_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE8_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE8_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE8_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE9 ========================================================= */ + #define R_MIPI_CSI_VCIE9_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE9_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE9_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE9_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE9_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE9_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE9_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE9_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE9_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE9_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE9_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE9_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE9_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE9_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE9_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE9_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ======================================================== VCIE10 ========================================================= */ + #define R_MIPI_CSI_VCIE10_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE10_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE10_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE10_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE10_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE10_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE10_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE10_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE10_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE10_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE10_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE10_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE10_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE10_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE10_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE10_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ======================================================== VCIE11 ========================================================= */ + #define R_MIPI_CSI_VCIE11_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE11_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE11_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE11_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE11_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE11_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE11_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE11_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE11_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE11_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE11_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE11_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE11_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE11_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE11_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE11_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ======================================================== VCIE12 ========================================================= */ + #define R_MIPI_CSI_VCIE12_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE12_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE12_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE12_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE12_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE12_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE12_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE12_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE12_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE12_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE12_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE12_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE12_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE12_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE12_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE12_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ======================================================== VCIE13 ========================================================= */ + #define R_MIPI_CSI_VCIE13_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE13_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE13_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE13_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE13_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE13_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE13_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE13_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE13_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE13_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE13_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE13_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE13_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE13_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE13_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE13_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ======================================================== VCIE14 ========================================================= */ + #define R_MIPI_CSI_VCIE14_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE14_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE14_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE14_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE14_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE14_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE14_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE14_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE14_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE14_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE14_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE14_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE14_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE14_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE14_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE14_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ======================================================== VCIE15 ========================================================= */ + #define R_MIPI_CSI_VCIE15_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE15_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE15_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE15_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE15_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE15_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE15_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE15_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE15_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE15_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE15_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE15_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE15_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE15_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE15_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE15_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= PMST ========================================================== */ + #define R_MIPI_CSI_PMST_DSX_Pos (0UL) /*!< DSX (Bit 0) */ + #define R_MIPI_CSI_PMST_DSX_Msk (0x1UL) /*!< DSX (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_DSN_Pos (1UL) /*!< DSN (Bit 1) */ + #define R_MIPI_CSI_PMST_DSN_Msk (0x2UL) /*!< DSN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_CSX_Pos (2UL) /*!< CSX (Bit 2) */ + #define R_MIPI_CSI_PMST_CSX_Msk (0x4UL) /*!< CSX (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_CSN_Pos (3UL) /*!< CSN (Bit 3) */ + #define R_MIPI_CSI_PMST_CSN_Msk (0x8UL) /*!< CSN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_DUX_Pos (4UL) /*!< DUX (Bit 4) */ + #define R_MIPI_CSI_PMST_DUX_Msk (0x10UL) /*!< DUX (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_DUN_Pos (5UL) /*!< DUN (Bit 5) */ + #define R_MIPI_CSI_PMST_DUN_Msk (0x20UL) /*!< DUN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_CUX_Pos (6UL) /*!< CUX (Bit 6) */ + #define R_MIPI_CSI_PMST_CUX_Msk (0x40UL) /*!< CUX (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_CUN_Pos (7UL) /*!< CUN (Bit 7) */ + #define R_MIPI_CSI_PMST_CUN_Msk (0x80UL) /*!< CUN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_CLSS_Pos (14UL) /*!< CLSS (Bit 14) */ + #define R_MIPI_CSI_PMST_CLSS_Msk (0x4000UL) /*!< CLSS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_CLUL_Pos (15UL) /*!< CLUL (Bit 15) */ + #define R_MIPI_CSI_PMST_CLUL_Msk (0x8000UL) /*!< CLUL (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_DLSS_Pos (16UL) /*!< DLSS (Bit 16) */ + #define R_MIPI_CSI_PMST_DLSS_Msk (0x30000UL) /*!< DLSS (Bitfield-Mask: 0x03) */ + #define R_MIPI_CSI_PMST_DLUL_Pos (24UL) /*!< DLUL (Bit 24) */ + #define R_MIPI_CSI_PMST_DLUL_Msk (0x3000000UL) /*!< DLUL (Bitfield-Mask: 0x03) */ +/* ========================================================= PMSC ========================================================== */ + #define R_MIPI_CSI_PMSC_DSXC_Pos (0UL) /*!< DSXC (Bit 0) */ + #define R_MIPI_CSI_PMSC_DSXC_Msk (0x1UL) /*!< DSXC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMSC_DSNC_Pos (1UL) /*!< DSNC (Bit 1) */ + #define R_MIPI_CSI_PMSC_DSNC_Msk (0x2UL) /*!< DSNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMSC_CSXC_Pos (2UL) /*!< CSXC (Bit 2) */ + #define R_MIPI_CSI_PMSC_CSXC_Msk (0x4UL) /*!< CSXC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMSC_CSNC_Pos (3UL) /*!< CSNC (Bit 3) */ + #define R_MIPI_CSI_PMSC_CSNC_Msk (0x8UL) /*!< CSNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMSC_DUXC_Pos (4UL) /*!< DUXC (Bit 4) */ + #define R_MIPI_CSI_PMSC_DUXC_Msk (0x10UL) /*!< DUXC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMSC_DUNC_Pos (5UL) /*!< DUNC (Bit 5) */ + #define R_MIPI_CSI_PMSC_DUNC_Msk (0x20UL) /*!< DUNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMSC_CUXC_Pos (6UL) /*!< CUXC (Bit 6) */ + #define R_MIPI_CSI_PMSC_CUXC_Msk (0x40UL) /*!< CUXC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMSC_CUNC_Pos (7UL) /*!< CUNC (Bit 7) */ + #define R_MIPI_CSI_PMSC_CUNC_Msk (0x80UL) /*!< CUNC (Bitfield-Mask: 0x01) */ +/* ========================================================= PMIE ========================================================== */ + #define R_MIPI_CSI_PMIE_DSXE_Pos (0UL) /*!< DSXE (Bit 0) */ + #define R_MIPI_CSI_PMIE_DSXE_Msk (0x1UL) /*!< DSXE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMIE_DSNE_Pos (1UL) /*!< DSNE (Bit 1) */ + #define R_MIPI_CSI_PMIE_DSNE_Msk (0x2UL) /*!< DSNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMIE_CSXE_Pos (2UL) /*!< CSXE (Bit 2) */ + #define R_MIPI_CSI_PMIE_CSXE_Msk (0x4UL) /*!< CSXE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMIE_CSNE_Pos (3UL) /*!< CSNE (Bit 3) */ + #define R_MIPI_CSI_PMIE_CSNE_Msk (0x8UL) /*!< CSNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMIE_DUXE_Pos (4UL) /*!< DUXE (Bit 4) */ + #define R_MIPI_CSI_PMIE_DUXE_Msk (0x10UL) /*!< DUXE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMIE_DUNE_Pos (5UL) /*!< DUNE (Bit 5) */ + #define R_MIPI_CSI_PMIE_DUNE_Msk (0x20UL) /*!< DUNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMIE_CUXE_Pos (6UL) /*!< CUXE (Bit 6) */ + #define R_MIPI_CSI_PMIE_CUXE_Msk (0x40UL) /*!< CUXE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMIE_CUNE_Pos (7UL) /*!< CUNE (Bit 7) */ + #define R_MIPI_CSI_PMIE_CUNE_Msk (0x80UL) /*!< CUNE (Bitfield-Mask: 0x01) */ +/* ========================================================= GSCT ========================================================== */ + #define R_MIPI_CSI_GSCT_SHTH_Pos (0UL) /*!< SHTH (Bit 0) */ + #define R_MIPI_CSI_GSCT_SHTH_Msk (0x7fUL) /*!< SHTH (Bitfield-Mask: 0x7f) */ + #define R_MIPI_CSI_GSCT_GFIF_Pos (16UL) /*!< GFIF (Bit 16) */ + #define R_MIPI_CSI_GSCT_GFIF_Msk (0x10000UL) /*!< GFIF (Bitfield-Mask: 0x01) */ +/* ========================================================= GSST ========================================================== */ + #define R_MIPI_CSI_GSST_GNE_Pos (0UL) /*!< GNE (Bit 0) */ + #define R_MIPI_CSI_GSST_GNE_Msk (0x1UL) /*!< GNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSST_GTH_Pos (1UL) /*!< GTH (Bit 1) */ + #define R_MIPI_CSI_GSST_GTH_Msk (0x2UL) /*!< GTH (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSST_GOV_Pos (4UL) /*!< GOV (Bit 4) */ + #define R_MIPI_CSI_GSST_GOV_Msk (0x10UL) /*!< GOV (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSST_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_MIPI_CSI_GSST_PNUM_Msk (0xff00UL) /*!< PNUM (Bitfield-Mask: 0xff) */ + #define R_MIPI_CSI_GSST_GCD_Pos (16UL) /*!< GCD (Bit 16) */ + #define R_MIPI_CSI_GSST_GCD_Msk (0x10000UL) /*!< GCD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSST_STRDS_Pos (17UL) /*!< STRDS (Bit 17) */ + #define R_MIPI_CSI_GSST_STRDS_Msk (0x20000UL) /*!< STRDS (Bitfield-Mask: 0x01) */ +/* ========================================================= GSSC ========================================================== */ + #define R_MIPI_CSI_GSSC_GOVC_Pos (4UL) /*!< GOVC (Bit 4) */ + #define R_MIPI_CSI_GSSC_GOVC_Msk (0x10UL) /*!< GOVC (Bitfield-Mask: 0x01) */ +/* ========================================================= GSIE ========================================================== */ + #define R_MIPI_CSI_GSIE_GNEE_Pos (0UL) /*!< GNEE (Bit 0) */ + #define R_MIPI_CSI_GSIE_GNEE_Msk (0x1UL) /*!< GNEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSIE_GTHE_Pos (1UL) /*!< GTHE (Bit 1) */ + #define R_MIPI_CSI_GSIE_GTHE_Msk (0x2UL) /*!< GTHE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSIE_GOVE_Pos (4UL) /*!< GOVE (Bit 4) */ + #define R_MIPI_CSI_GSIE_GOVE_Msk (0x10UL) /*!< GOVE (Bitfield-Mask: 0x01) */ +/* ========================================================= GSHT ========================================================== */ + #define R_MIPI_CSI_GSHT_SPDT_Pos (0UL) /*!< SPDT (Bit 0) */ + #define R_MIPI_CSI_GSHT_SPDT_Msk (0xffffUL) /*!< SPDT (Bitfield-Mask: 0xffff) */ + #define R_MIPI_CSI_GSHT_DTYP_Pos (16UL) /*!< DTYP (Bit 16) */ + #define R_MIPI_CSI_GSHT_DTYP_Msk (0x3f0000UL) /*!< DTYP (Bitfield-Mask: 0x3f) */ + #define R_MIPI_CSI_GSHT_SPVC_Pos (24UL) /*!< SPVC (Bit 24) */ + #define R_MIPI_CSI_GSHT_SPVC_Msk (0xf000000UL) /*!< SPVC (Bitfield-Mask: 0x0f) */ +/* ========================================================= GSIU ========================================================== */ + #define R_MIPI_CSI_GSIU_FINC_Pos (0UL) /*!< FINC (Bit 0) */ + #define R_MIPI_CSI_GSIU_FINC_Msk (0x1UL) /*!< FINC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSIU_GFCLR_Pos (8UL) /*!< GFCLR (Bit 8) */ + #define R_MIPI_CSI_GSIU_GFCLR_Msk (0x100UL) /*!< GFCLR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSIU_GFEN_Pos (16UL) /*!< GFEN (Bit 16) */ + #define R_MIPI_CSI_GSIU_GFEN_Msk (0x10000UL) /*!< GFEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CEU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CAPSR ========================================================= */ + #define R_CEU_CAPSR_CE_Pos (0UL) /*!< CE (Bit 0) */ + #define R_CEU_CAPSR_CE_Msk (0x1UL) /*!< CE (Bitfield-Mask: 0x01) */ + #define R_CEU_CAPSR_CPKIL_Pos (16UL) /*!< CPKIL (Bit 16) */ + #define R_CEU_CAPSR_CPKIL_Msk (0x10000UL) /*!< CPKIL (Bitfield-Mask: 0x01) */ +/* ========================================================= CAPCR ========================================================= */ + #define R_CEU_CAPCR_CTNCP_Pos (16UL) /*!< CTNCP (Bit 16) */ + #define R_CEU_CAPCR_CTNCP_Msk (0x10000UL) /*!< CTNCP (Bitfield-Mask: 0x01) */ + #define R_CEU_CAPCR_MTCM_Pos (20UL) /*!< MTCM (Bit 20) */ + #define R_CEU_CAPCR_MTCM_Msk (0x300000UL) /*!< MTCM (Bitfield-Mask: 0x03) */ + #define R_CEU_CAPCR_FDRP_Pos (24UL) /*!< FDRP (Bit 24) */ + #define R_CEU_CAPCR_FDRP_Msk (0xff000000UL) /*!< FDRP (Bitfield-Mask: 0xff) */ +/* ========================================================= CAMCR ========================================================= */ + #define R_CEU_CAMCR_HDPOL_Pos (0UL) /*!< HDPOL (Bit 0) */ + #define R_CEU_CAMCR_HDPOL_Msk (0x1UL) /*!< HDPOL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_VDPOL_Pos (1UL) /*!< VDPOL (Bit 1) */ + #define R_CEU_CAMCR_VDPOL_Msk (0x2UL) /*!< VDPOL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_JPG_Pos (4UL) /*!< JPG (Bit 4) */ + #define R_CEU_CAMCR_JPG_Msk (0x30UL) /*!< JPG (Bitfield-Mask: 0x03) */ + #define R_CEU_CAMCR_DTARY_Pos (8UL) /*!< DTARY (Bit 8) */ + #define R_CEU_CAMCR_DTARY_Msk (0x300UL) /*!< DTARY (Bitfield-Mask: 0x03) */ + #define R_CEU_CAMCR_DTIF_Pos (12UL) /*!< DTIF (Bit 12) */ + #define R_CEU_CAMCR_DTIF_Msk (0x1000UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_FLDPOL_Pos (16UL) /*!< FLDPOL (Bit 16) */ + #define R_CEU_CAMCR_FLDPOL_Msk (0x10000UL) /*!< FLDPOL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_DSEL_Pos (24UL) /*!< DSEL (Bit 24) */ + #define R_CEU_CAMCR_DSEL_Msk (0x1000000UL) /*!< DSEL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_FLDSEL_Pos (25UL) /*!< FLDSEL (Bit 25) */ + #define R_CEU_CAMCR_FLDSEL_Msk (0x2000000UL) /*!< FLDSEL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_HDSEL_Pos (26UL) /*!< HDSEL (Bit 26) */ + #define R_CEU_CAMCR_HDSEL_Msk (0x4000000UL) /*!< HDSEL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_VDSEL_Pos (27UL) /*!< VDSEL (Bit 27) */ + #define R_CEU_CAMCR_VDSEL_Msk (0x8000000UL) /*!< VDSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= CMCYR ========================================================= */ + #define R_CEU_CMCYR_HCYL_Pos (0UL) /*!< HCYL (Bit 0) */ + #define R_CEU_CMCYR_HCYL_Msk (0x3fffUL) /*!< HCYL (Bitfield-Mask: 0x3fff) */ + #define R_CEU_CMCYR_VCYL_Pos (16UL) /*!< VCYL (Bit 16) */ + #define R_CEU_CMCYR_VCYL_Msk (0x3fff0000UL) /*!< VCYL (Bitfield-Mask: 0x3fff) */ +/* ========================================================= CAMOR ========================================================= */ + #define R_CEU_CAMOR_HOFST_Pos (0UL) /*!< HOFST (Bit 0) */ + #define R_CEU_CAMOR_HOFST_Msk (0x1fffUL) /*!< HOFST (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAMOR_VOFST_Pos (16UL) /*!< VOFST (Bit 16) */ + #define R_CEU_CAMOR_VOFST_Msk (0xfff0000UL) /*!< VOFST (Bitfield-Mask: 0xfff) */ +/* ========================================================= CAPWR ========================================================= */ + #define R_CEU_CAPWR_HWDTH_Pos (0UL) /*!< HWDTH (Bit 0) */ + #define R_CEU_CAPWR_HWDTH_Msk (0x1fffUL) /*!< HWDTH (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAPWR_VWDTH_Pos (16UL) /*!< VWDTH (Bit 16) */ + #define R_CEU_CAPWR_VWDTH_Msk (0xfff0000UL) /*!< VWDTH (Bitfield-Mask: 0xfff) */ +/* ========================================================= CAIFR ========================================================= */ + #define R_CEU_CAIFR_FCI_Pos (0UL) /*!< FCI (Bit 0) */ + #define R_CEU_CAIFR_FCI_Msk (0x3UL) /*!< FCI (Bitfield-Mask: 0x03) */ + #define R_CEU_CAIFR_CIM_Pos (4UL) /*!< CIM (Bit 4) */ + #define R_CEU_CAIFR_CIM_Msk (0x10UL) /*!< CIM (Bitfield-Mask: 0x01) */ + #define R_CEU_CAIFR_IFS_Pos (8UL) /*!< IFS (Bit 8) */ + #define R_CEU_CAIFR_IFS_Msk (0x100UL) /*!< IFS (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCNTR ========================================================= */ + #define R_CEU_CRCNTR_RC_Pos (0UL) /*!< RC (Bit 0) */ + #define R_CEU_CRCNTR_RC_Msk (0x1UL) /*!< RC (Bitfield-Mask: 0x01) */ + #define R_CEU_CRCNTR_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_CEU_CRCNTR_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_CEU_CRCNTR_RVS_Pos (4UL) /*!< RVS (Bit 4) */ + #define R_CEU_CRCNTR_RVS_Msk (0x10UL) /*!< RVS (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCMPR ========================================================= */ + #define R_CEU_CRCMPR_RA_Pos (0UL) /*!< RA (Bit 0) */ + #define R_CEU_CRCMPR_RA_Msk (0x1UL) /*!< RA (Bitfield-Mask: 0x01) */ +/* ========================================================= CFLCR ========================================================= */ + #define R_CEU_CFLCR_HFRAC_Pos (0UL) /*!< HFRAC (Bit 0) */ + #define R_CEU_CFLCR_HFRAC_Msk (0xfffUL) /*!< HFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_HMANT_Pos (12UL) /*!< HMANT (Bit 12) */ + #define R_CEU_CFLCR_HMANT_Msk (0xf000UL) /*!< HMANT (Bitfield-Mask: 0x0f) */ + #define R_CEU_CFLCR_VFRAC_Pos (16UL) /*!< VFRAC (Bit 16) */ + #define R_CEU_CFLCR_VFRAC_Msk (0xfff0000UL) /*!< VFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_VMANT_Pos (28UL) /*!< VMANT (Bit 28) */ + #define R_CEU_CFLCR_VMANT_Msk (0xf0000000UL) /*!< VMANT (Bitfield-Mask: 0x0f) */ +/* ========================================================= CFSZR ========================================================= */ + #define R_CEU_CFSZR_HFCLP_Pos (0UL) /*!< HFCLP (Bit 0) */ + #define R_CEU_CFSZR_HFCLP_Msk (0xfffUL) /*!< HFCLP (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFSZR_VFCLP_Pos (16UL) /*!< VFCLP (Bit 16) */ + #define R_CEU_CFSZR_VFCLP_Msk (0xfff0000UL) /*!< VFCLP (Bitfield-Mask: 0xfff) */ +/* ========================================================= CDWDR ========================================================= */ + #define R_CEU_CDWDR_CHDW_Pos (0UL) /*!< CHDW (Bit 0) */ + #define R_CEU_CDWDR_CHDW_Msk (0x1fffUL) /*!< CHDW (Bitfield-Mask: 0x1fff) */ +/* ========================================================= CDAYR ========================================================= */ + #define R_CEU_CDAYR_CAYR_Pos (0UL) /*!< CAYR (Bit 0) */ + #define R_CEU_CDAYR_CAYR_Msk (0xffffffffUL) /*!< CAYR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDACR ========================================================= */ + #define R_CEU_CDACR_CACR_Pos (0UL) /*!< CACR (Bit 0) */ + #define R_CEU_CDACR_CACR_Msk (0xffffffffUL) /*!< CACR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDBYR ========================================================= */ + #define R_CEU_CDBYR_CBYR_Pos (0UL) /*!< CBYR (Bit 0) */ + #define R_CEU_CDBYR_CBYR_Msk (0xffffffffUL) /*!< CBYR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDBCR ========================================================= */ + #define R_CEU_CDBCR_CBCR_Pos (0UL) /*!< CBCR (Bit 0) */ + #define R_CEU_CDBCR_CBCR_Msk (0xffffffffUL) /*!< CBCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CBDSR ========================================================= */ + #define R_CEU_CBDSR_CBVS_Pos (0UL) /*!< CBVS (Bit 0) */ + #define R_CEU_CBDSR_CBVS_Msk (0x7fffffUL) /*!< CBVS (Bitfield-Mask: 0x7fffff) */ +/* ========================================================= CFWCR ========================================================= */ + #define R_CEU_CFWCR_FWE_Pos (0UL) /*!< FWE (Bit 0) */ + #define R_CEU_CFWCR_FWE_Msk (0x1UL) /*!< FWE (Bitfield-Mask: 0x01) */ + #define R_CEU_CFWCR_FWV_Pos (5UL) /*!< FWV (Bit 5) */ + #define R_CEU_CFWCR_FWV_Msk (0xffffffe0UL) /*!< FWV (Bitfield-Mask: 0x7ffffff) */ +/* ========================================================= CLFCR ========================================================= */ + #define R_CEU_CLFCR_LPF_Pos (0UL) /*!< LPF (Bit 0) */ + #define R_CEU_CLFCR_LPF_Msk (0x1UL) /*!< LPF (Bitfield-Mask: 0x01) */ +/* ========================================================= CDOCR ========================================================= */ + #define R_CEU_CDOCR_COBS_Pos (0UL) /*!< COBS (Bit 0) */ + #define R_CEU_CDOCR_COBS_Msk (0x1UL) /*!< COBS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_COWS_Pos (1UL) /*!< COWS (Bit 1) */ + #define R_CEU_CDOCR_COWS_Msk (0x2UL) /*!< COWS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_COLS_Pos (2UL) /*!< COLS (Bit 2) */ + #define R_CEU_CDOCR_COLS_Msk (0x4UL) /*!< COLS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_CDS_Pos (4UL) /*!< CDS (Bit 4) */ + #define R_CEU_CDOCR_CDS_Msk (0x10UL) /*!< CDS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_CBE_Pos (16UL) /*!< CBE (Bit 16) */ + #define R_CEU_CDOCR_CBE_Msk (0x10000UL) /*!< CBE (Bitfield-Mask: 0x01) */ +/* ========================================================= CEIER ========================================================= */ + #define R_CEU_CEIER_CPEIE_Pos (0UL) /*!< CPEIE (Bit 0) */ + #define R_CEU_CEIER_CPEIE_Msk (0x1UL) /*!< CPEIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CFEIE_Pos (1UL) /*!< CFEIE (Bit 1) */ + #define R_CEU_CEIER_CFEIE_Msk (0x2UL) /*!< CFEIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_IGRWIE_Pos (4UL) /*!< IGRWIE (Bit 4) */ + #define R_CEU_CEIER_IGRWIE_Msk (0x10UL) /*!< IGRWIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_HDIE_Pos (8UL) /*!< HDIE (Bit 8) */ + #define R_CEU_CEIER_HDIE_Msk (0x100UL) /*!< HDIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_VDIE_Pos (9UL) /*!< VDIE (Bit 9) */ + #define R_CEU_CEIER_VDIE_Msk (0x200UL) /*!< VDIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CPBE1IE_Pos (12UL) /*!< CPBE1IE (Bit 12) */ + #define R_CEU_CEIER_CPBE1IE_Msk (0x1000UL) /*!< CPBE1IE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CPBE2IE_Pos (13UL) /*!< CPBE2IE (Bit 13) */ + #define R_CEU_CEIER_CPBE2IE_Msk (0x2000UL) /*!< CPBE2IE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CPBE3IE_Pos (14UL) /*!< CPBE3IE (Bit 14) */ + #define R_CEU_CEIER_CPBE3IE_Msk (0x4000UL) /*!< CPBE3IE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CPBE4IE_Pos (15UL) /*!< CPBE4IE (Bit 15) */ + #define R_CEU_CEIER_CPBE4IE_Msk (0x8000UL) /*!< CPBE4IE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CDTOFIE_Pos (16UL) /*!< CDTOFIE (Bit 16) */ + #define R_CEU_CEIER_CDTOFIE_Msk (0x10000UL) /*!< CDTOFIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_IGHSIE_Pos (17UL) /*!< IGHSIE (Bit 17) */ + #define R_CEU_CEIER_IGHSIE_Msk (0x20000UL) /*!< IGHSIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_IGVSIE_Pos (18UL) /*!< IGVSIE (Bit 18) */ + #define R_CEU_CEIER_IGVSIE_Msk (0x40000UL) /*!< IGVSIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_VBPIE_Pos (20UL) /*!< VBPIE (Bit 20) */ + #define R_CEU_CEIER_VBPIE_Msk (0x100000UL) /*!< VBPIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_FWFIE_Pos (23UL) /*!< FWFIE (Bit 23) */ + #define R_CEU_CEIER_FWFIE_Msk (0x800000UL) /*!< FWFIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_NHDIE_Pos (24UL) /*!< NHDIE (Bit 24) */ + #define R_CEU_CEIER_NHDIE_Msk (0x1000000UL) /*!< NHDIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_NVDIE_Pos (25UL) /*!< NVDIE (Bit 25) */ + #define R_CEU_CEIER_NVDIE_Msk (0x2000000UL) /*!< NVDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CETCR ========================================================= */ + #define R_CEU_CETCR_CPE_Pos (0UL) /*!< CPE (Bit 0) */ + #define R_CEU_CETCR_CPE_Msk (0x1UL) /*!< CPE (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CFE_Pos (1UL) /*!< CFE (Bit 1) */ + #define R_CEU_CETCR_CFE_Msk (0x2UL) /*!< CFE (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_IGRW_Pos (4UL) /*!< IGRW (Bit 4) */ + #define R_CEU_CETCR_IGRW_Msk (0x10UL) /*!< IGRW (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_HD_Pos (8UL) /*!< HD (Bit 8) */ + #define R_CEU_CETCR_HD_Msk (0x100UL) /*!< HD (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_VD_Pos (9UL) /*!< VD (Bit 9) */ + #define R_CEU_CETCR_VD_Msk (0x200UL) /*!< VD (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CPBE1_Pos (12UL) /*!< CPBE1 (Bit 12) */ + #define R_CEU_CETCR_CPBE1_Msk (0x1000UL) /*!< CPBE1 (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CPBE2_Pos (13UL) /*!< CPBE2 (Bit 13) */ + #define R_CEU_CETCR_CPBE2_Msk (0x2000UL) /*!< CPBE2 (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CPBE3_Pos (14UL) /*!< CPBE3 (Bit 14) */ + #define R_CEU_CETCR_CPBE3_Msk (0x4000UL) /*!< CPBE3 (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CPBE4_Pos (15UL) /*!< CPBE4 (Bit 15) */ + #define R_CEU_CETCR_CPBE4_Msk (0x8000UL) /*!< CPBE4 (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CDTOF_Pos (16UL) /*!< CDTOF (Bit 16) */ + #define R_CEU_CETCR_CDTOF_Msk (0x10000UL) /*!< CDTOF (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_IGHS_Pos (17UL) /*!< IGHS (Bit 17) */ + #define R_CEU_CETCR_IGHS_Msk (0x20000UL) /*!< IGHS (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_IGVS_Pos (18UL) /*!< IGVS (Bit 18) */ + #define R_CEU_CETCR_IGVS_Msk (0x40000UL) /*!< IGVS (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_VBP_Pos (20UL) /*!< VBP (Bit 20) */ + #define R_CEU_CETCR_VBP_Msk (0x100000UL) /*!< VBP (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_FWF_Pos (23UL) /*!< FWF (Bit 23) */ + #define R_CEU_CETCR_FWF_Msk (0x800000UL) /*!< FWF (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_NHD_Pos (24UL) /*!< NHD (Bit 24) */ + #define R_CEU_CETCR_NHD_Msk (0x1000000UL) /*!< NHD (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_NVD_Pos (25UL) /*!< NVD (Bit 25) */ + #define R_CEU_CETCR_NVD_Msk (0x2000000UL) /*!< NVD (Bitfield-Mask: 0x01) */ +/* ========================================================= CSTSR ========================================================= */ + #define R_CEU_CSTSR_CPTON_Pos (0UL) /*!< CPTON (Bit 0) */ + #define R_CEU_CSTSR_CPTON_Msk (0x1UL) /*!< CPTON (Bitfield-Mask: 0x01) */ + #define R_CEU_CSTSR_CPFLD_Pos (16UL) /*!< CPFLD (Bit 16) */ + #define R_CEU_CSTSR_CPFLD_Msk (0x10000UL) /*!< CPFLD (Bitfield-Mask: 0x01) */ + #define R_CEU_CSTSR_CRST_Pos (24UL) /*!< CRST (Bit 24) */ + #define R_CEU_CSTSR_CRST_Msk (0x1000000UL) /*!< CRST (Bitfield-Mask: 0x01) */ +/* ========================================================= CDSSR ========================================================= */ + #define R_CEU_CDSSR_CDSS_Pos (0UL) /*!< CDSS (Bit 0) */ + #define R_CEU_CDSSR_CDSS_Msk (0xffffffffUL) /*!< CDSS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDAYR2 ========================================================= */ + #define R_CEU_CDAYR2_CAYR2_Pos (0UL) /*!< CAYR2 (Bit 0) */ + #define R_CEU_CDAYR2_CAYR2_Msk (0xffffffffUL) /*!< CAYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDACR2 ========================================================= */ + #define R_CEU_CDACR2_CACR2_Pos (0UL) /*!< CACR2 (Bit 0) */ + #define R_CEU_CDACR2_CACR2_Msk (0xffffffffUL) /*!< CACR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBYR2 ========================================================= */ + #define R_CEU_CDBYR2_CBYR2_Pos (0UL) /*!< CBYR2 (Bit 0) */ + #define R_CEU_CDBYR2_CBYR2_Msk (0xffffffffUL) /*!< CBYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBCR2 ========================================================= */ + #define R_CEU_CDBCR2_CBCR2_Pos (0UL) /*!< CBCR2 (Bit 0) */ + #define R_CEU_CDBCR2_CBCR2_Msk (0xffffffffUL) /*!< CBCR2 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== AXIBUSCTL2 ======================================================= */ + #define R_CEU_AXIBUSCTL2_AWCACHE_Pos (0UL) /*!< AWCACHE (Bit 0) */ + #define R_CEU_AXIBUSCTL2_AWCACHE_Msk (0xfUL) /*!< AWCACHE (Bitfield-Mask: 0x0f) */ +/* ======================================================== CAMOR_B ======================================================== */ + #define R_CEU_CAMOR_B_HOFST_Pos (0UL) /*!< HOFST (Bit 0) */ + #define R_CEU_CAMOR_B_HOFST_Msk (0x1fffUL) /*!< HOFST (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAMOR_B_VOFST_Pos (16UL) /*!< VOFST (Bit 16) */ + #define R_CEU_CAMOR_B_VOFST_Msk (0xfff0000UL) /*!< VOFST (Bitfield-Mask: 0xfff) */ +/* ======================================================== CAPWR_B ======================================================== */ + #define R_CEU_CAPWR_B_HWDTH_Pos (0UL) /*!< HWDTH (Bit 0) */ + #define R_CEU_CAPWR_B_HWDTH_Msk (0x1fffUL) /*!< HWDTH (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAPWR_B_VWDTH_Pos (16UL) /*!< VWDTH (Bit 16) */ + #define R_CEU_CAPWR_B_VWDTH_Msk (0xfff0000UL) /*!< VWDTH (Bitfield-Mask: 0xfff) */ +/* ======================================================== CFLCR_B ======================================================== */ + #define R_CEU_CFLCR_B_HFRAC_Pos (0UL) /*!< HFRAC (Bit 0) */ + #define R_CEU_CFLCR_B_HFRAC_Msk (0xfffUL) /*!< HFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_B_HMANT_Pos (12UL) /*!< HMANT (Bit 12) */ + #define R_CEU_CFLCR_B_HMANT_Msk (0xf000UL) /*!< HMANT (Bitfield-Mask: 0x0f) */ + #define R_CEU_CFLCR_B_VFRAC_Pos (16UL) /*!< VFRAC (Bit 16) */ + #define R_CEU_CFLCR_B_VFRAC_Msk (0xfff0000UL) /*!< VFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_B_VMANT_Pos (28UL) /*!< VMANT (Bit 28) */ + #define R_CEU_CFLCR_B_VMANT_Msk (0xf0000000UL) /*!< VMANT (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFSZR_B ======================================================== */ + #define R_CEU_CFSZR_B_HFCLP_Pos (0UL) /*!< HFCLP (Bit 0) */ + #define R_CEU_CFSZR_B_HFCLP_Msk (0xfffUL) /*!< HFCLP (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFSZR_B_VFCLP_Pos (16UL) /*!< VFCLP (Bit 16) */ + #define R_CEU_CFSZR_B_VFCLP_Msk (0xfff0000UL) /*!< VFCLP (Bitfield-Mask: 0xfff) */ +/* ======================================================== CDWDR_B ======================================================== */ + #define R_CEU_CDWDR_B_CHDW_Pos (0UL) /*!< CHDW (Bit 0) */ + #define R_CEU_CDWDR_B_CHDW_Msk (0x1fffUL) /*!< CHDW (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CDAYR_B ======================================================== */ + #define R_CEU_CDAYR_B_CAYR_Pos (0UL) /*!< CAYR (Bit 0) */ + #define R_CEU_CDAYR_B_CAYR_Msk (0xffffffffUL) /*!< CAYR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDACR_B ======================================================== */ + #define R_CEU_CDACR_B_CACR_Pos (0UL) /*!< CACR (Bit 0) */ + #define R_CEU_CDACR_B_CACR_Msk (0xffffffffUL) /*!< CACR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBYR_B ======================================================== */ + #define R_CEU_CDBYR_B_CBYR_Pos (0UL) /*!< CBYR (Bit 0) */ + #define R_CEU_CDBYR_B_CBYR_Msk (0xffffffffUL) /*!< CBYR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBCR_B ======================================================== */ + #define R_CEU_CDBCR_B_CBCR_Pos (0UL) /*!< CBCR (Bit 0) */ + #define R_CEU_CDBCR_B_CBCR_Msk (0xffffffffUL) /*!< CBCR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CBDSR_B ======================================================== */ + #define R_CEU_CBDSR_B_CBVS_Pos (0UL) /*!< CBVS (Bit 0) */ + #define R_CEU_CBDSR_B_CBVS_Msk (0x7fffffUL) /*!< CBVS (Bitfield-Mask: 0x7fffff) */ +/* ======================================================== CLFCR_B ======================================================== */ + #define R_CEU_CLFCR_B_LPF_Pos (0UL) /*!< LPF (Bit 0) */ + #define R_CEU_CLFCR_B_LPF_Msk (0x1UL) /*!< LPF (Bitfield-Mask: 0x01) */ +/* ======================================================== CDOCR_B ======================================================== */ + #define R_CEU_CDOCR_B_COBS_Pos (0UL) /*!< COBS (Bit 0) */ + #define R_CEU_CDOCR_B_COBS_Msk (0x1UL) /*!< COBS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_B_COWS_Pos (1UL) /*!< COWS (Bit 1) */ + #define R_CEU_CDOCR_B_COWS_Msk (0x2UL) /*!< COWS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_B_COLS_Pos (2UL) /*!< COLS (Bit 2) */ + #define R_CEU_CDOCR_B_COLS_Msk (0x4UL) /*!< COLS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_B_CDS_Pos (4UL) /*!< CDS (Bit 4) */ + #define R_CEU_CDOCR_B_CDS_Msk (0x10UL) /*!< CDS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_B_CBE_Pos (16UL) /*!< CBE (Bit 16) */ + #define R_CEU_CDOCR_B_CBE_Msk (0x10000UL) /*!< CBE (Bitfield-Mask: 0x01) */ +/* ======================================================= CDAYR2_B ======================================================== */ + #define R_CEU_CDAYR2_B_CAYR2_Pos (0UL) /*!< CAYR2 (Bit 0) */ + #define R_CEU_CDAYR2_B_CAYR2_Msk (0xffffffffUL) /*!< CAYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDACR2_B ======================================================== */ + #define R_CEU_CDACR2_B_CACR2_Pos (0UL) /*!< CACR2 (Bit 0) */ + #define R_CEU_CDACR2_B_CACR2_Msk (0xffffffffUL) /*!< CACR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDBYR2_B ======================================================== */ + #define R_CEU_CDBYR2_B_CBYR2_Pos (0UL) /*!< CBYR2 (Bit 0) */ + #define R_CEU_CDBYR2_B_CBYR2_Msk (0xffffffffUL) /*!< CBYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDBCR2_B ======================================================== */ + #define R_CEU_CDBCR2_B_CBCR2_Pos (0UL) /*!< CBCR2 (Bit 0) */ + #define R_CEU_CDBCR2_B_CBCR2_Msk (0xffffffffUL) /*!< CBCR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CAMOR_M ======================================================== */ + #define R_CEU_CAMOR_M_HOFST_Pos (0UL) /*!< HOFST (Bit 0) */ + #define R_CEU_CAMOR_M_HOFST_Msk (0x1fffUL) /*!< HOFST (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAMOR_M_VOFST_Pos (16UL) /*!< VOFST (Bit 16) */ + #define R_CEU_CAMOR_M_VOFST_Msk (0xfff0000UL) /*!< VOFST (Bitfield-Mask: 0xfff) */ +/* ======================================================== CAPWR_M ======================================================== */ + #define R_CEU_CAPWR_M_HWDTH_Pos (0UL) /*!< HWDTH (Bit 0) */ + #define R_CEU_CAPWR_M_HWDTH_Msk (0x1fffUL) /*!< HWDTH (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAPWR_M_VWDTH_Pos (16UL) /*!< VWDTH (Bit 16) */ + #define R_CEU_CAPWR_M_VWDTH_Msk (0xfff0000UL) /*!< VWDTH (Bitfield-Mask: 0xfff) */ +/* ======================================================== CFLCR_M ======================================================== */ + #define R_CEU_CFLCR_M_HFRAC_Pos (0UL) /*!< HFRAC (Bit 0) */ + #define R_CEU_CFLCR_M_HFRAC_Msk (0xfffUL) /*!< HFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_M_HMANT_Pos (12UL) /*!< HMANT (Bit 12) */ + #define R_CEU_CFLCR_M_HMANT_Msk (0xf000UL) /*!< HMANT (Bitfield-Mask: 0x0f) */ + #define R_CEU_CFLCR_M_VFRAC_Pos (16UL) /*!< VFRAC (Bit 16) */ + #define R_CEU_CFLCR_M_VFRAC_Msk (0xfff0000UL) /*!< VFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_M_VMANT_Pos (28UL) /*!< VMANT (Bit 28) */ + #define R_CEU_CFLCR_M_VMANT_Msk (0xf0000000UL) /*!< VMANT (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFSZR_M ======================================================== */ + #define R_CEU_CFSZR_M_HFCLP_Pos (0UL) /*!< HFCLP (Bit 0) */ + #define R_CEU_CFSZR_M_HFCLP_Msk (0xfffUL) /*!< HFCLP (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFSZR_M_VFCLP_Pos (16UL) /*!< VFCLP (Bit 16) */ + #define R_CEU_CFSZR_M_VFCLP_Msk (0xfff0000UL) /*!< VFCLP (Bitfield-Mask: 0xfff) */ +/* ======================================================== CDWDR_M ======================================================== */ + #define R_CEU_CDWDR_M_CHDW_Pos (0UL) /*!< CHDW (Bit 0) */ + #define R_CEU_CDWDR_M_CHDW_Msk (0x1fffUL) /*!< CHDW (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CDAYR_M ======================================================== */ + #define R_CEU_CDAYR_M_CAYR_Pos (0UL) /*!< CAYR (Bit 0) */ + #define R_CEU_CDAYR_M_CAYR_Msk (0xffffffffUL) /*!< CAYR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDACR_M ======================================================== */ + #define R_CEU_CDACR_M_CACR_Pos (0UL) /*!< CACR (Bit 0) */ + #define R_CEU_CDACR_M_CACR_Msk (0xffffffffUL) /*!< CACR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBYR_M ======================================================== */ + #define R_CEU_CDBYR_M_CBYR_Pos (0UL) /*!< CBYR (Bit 0) */ + #define R_CEU_CDBYR_M_CBYR_Msk (0xffffffffUL) /*!< CBYR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBCR_M ======================================================== */ + #define R_CEU_CDBCR_M_CBCR_Pos (0UL) /*!< CBCR (Bit 0) */ + #define R_CEU_CDBCR_M_CBCR_Msk (0xffffffffUL) /*!< CBCR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CBDSR_M ======================================================== */ + #define R_CEU_CBDSR_M_CBVS_Pos (0UL) /*!< CBVS (Bit 0) */ + #define R_CEU_CBDSR_M_CBVS_Msk (0x7fffffUL) /*!< CBVS (Bitfield-Mask: 0x7fffff) */ +/* ======================================================== CLFCR_M ======================================================== */ + #define R_CEU_CLFCR_M_LPF_Pos (0UL) /*!< LPF (Bit 0) */ + #define R_CEU_CLFCR_M_LPF_Msk (0x1UL) /*!< LPF (Bitfield-Mask: 0x01) */ +/* ======================================================== CDOCR_M ======================================================== */ + #define R_CEU_CDOCR_M_COBS_Pos (0UL) /*!< COBS (Bit 0) */ + #define R_CEU_CDOCR_M_COBS_Msk (0x1UL) /*!< COBS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_M_COWS_Pos (1UL) /*!< COWS (Bit 1) */ + #define R_CEU_CDOCR_M_COWS_Msk (0x2UL) /*!< COWS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_M_COLS_Pos (2UL) /*!< COLS (Bit 2) */ + #define R_CEU_CDOCR_M_COLS_Msk (0x4UL) /*!< COLS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_M_CDS_Pos (4UL) /*!< CDS (Bit 4) */ + #define R_CEU_CDOCR_M_CDS_Msk (0x10UL) /*!< CDS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_M_CBE_Pos (16UL) /*!< CBE (Bit 16) */ + #define R_CEU_CDOCR_M_CBE_Msk (0x10000UL) /*!< CBE (Bitfield-Mask: 0x01) */ +/* ======================================================= CDAYR2_M ======================================================== */ + #define R_CEU_CDAYR2_M_CAYR2_Pos (0UL) /*!< CAYR2 (Bit 0) */ + #define R_CEU_CDAYR2_M_CAYR2_Msk (0xffffffffUL) /*!< CAYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDACR2_M ======================================================== */ + #define R_CEU_CDACR2_M_CACR2_Pos (0UL) /*!< CACR2 (Bit 0) */ + #define R_CEU_CDACR2_M_CACR2_Msk (0xffffffffUL) /*!< CACR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDBYR2_M ======================================================== */ + #define R_CEU_CDBYR2_M_CBYR2_Pos (0UL) /*!< CBYR2 (Bit 0) */ + #define R_CEU_CDBYR2_M_CBYR2_Msk (0xffffffffUL) /*!< CBYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDBCR2_M ======================================================== */ + #define R_CEU_CDBCR2_M_CBCR2_Pos (0UL) /*!< CBCR2 (Bit 0) */ + #define R_CEU_CDBCR2_M_CBCR2_Msk (0xffffffffUL) /*!< CBCR2 (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_ULPT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== ULPTCNT ======================================================== */ + #define R_ULPT0_ULPTCNT_ULPTCNT_Pos (0UL) /*!< ULPTCNT (Bit 0) */ + #define R_ULPT0_ULPTCNT_ULPTCNT_Msk (0xffffffffUL) /*!< ULPTCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ULPTCMA ======================================================== */ + #define R_ULPT0_ULPTCMA_ULPTCMA_Pos (0UL) /*!< ULPTCMA (Bit 0) */ + #define R_ULPT0_ULPTCMA_ULPTCMA_Msk (0xffffffffUL) /*!< ULPTCMA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ULPTCMB ======================================================== */ + #define R_ULPT0_ULPTCMB_ULPTCMB_Pos (0UL) /*!< ULPTCMB (Bit 0) */ + #define R_ULPT0_ULPTCMB_ULPTCMB_Msk (0xffffffffUL) /*!< ULPTCMB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ULPTCR ========================================================= */ + #define R_ULPT0_ULPTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_ULPT0_ULPTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_ULPT0_ULPTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_ULPT0_ULPTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_ULPT0_ULPTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_ULPT0_ULPTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_ULPT0_ULPTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ +/* ======================================================== ULPTMR1 ======================================================== */ + #define R_ULPT0_ULPTMR1_TMOD1_Pos (1UL) /*!< TMOD1 (Bit 1) */ + #define R_ULPT0_ULPTMR1_TMOD1_Msk (0x2UL) /*!< TMOD1 (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_ULPT0_ULPTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR1_TCK1_Pos (5UL) /*!< TCK1 (Bit 5) */ + #define R_ULPT0_ULPTMR1_TCK1_Msk (0x20UL) /*!< TCK1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ULPTMR2 ======================================================== */ + #define R_ULPT0_ULPTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_ULPT0_ULPTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_ULPT0_ULPTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_ULPT0_ULPTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ +/* ======================================================== ULPTMR3 ======================================================== */ + #define R_ULPT0_ULPTMR3_TCNTCTL_Pos (0UL) /*!< TCNTCTL (Bit 0) */ + #define R_ULPT0_ULPTMR3_TCNTCTL_Msk (0x1UL) /*!< TCNTCTL (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR3_TEVPOL_Pos (1UL) /*!< TEVPOL (Bit 1) */ + #define R_ULPT0_ULPTMR3_TEVPOL_Msk (0x2UL) /*!< TEVPOL (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR3_TOPOL_Pos (2UL) /*!< TOPOL (Bit 2) */ + #define R_ULPT0_ULPTMR3_TOPOL_Msk (0x4UL) /*!< TOPOL (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR3_TEECTL_Pos (4UL) /*!< TEECTL (Bit 4) */ + #define R_ULPT0_ULPTMR3_TEECTL_Msk (0x30UL) /*!< TEECTL (Bitfield-Mask: 0x03) */ + #define R_ULPT0_ULPTMR3_TEEPOL_Pos (6UL) /*!< TEEPOL (Bit 6) */ + #define R_ULPT0_ULPTMR3_TEEPOL_Msk (0xc0UL) /*!< TEEPOL (Bitfield-Mask: 0x03) */ +/* ======================================================== ULPTIOC ======================================================== */ + #define R_ULPT0_ULPTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_ULPT0_ULPTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_ULPT0_ULPTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_ULPT0_ULPTIOC_TIOGT0_Pos (6UL) /*!< TIOGT0 (Bit 6) */ + #define R_ULPT0_ULPTIOC_TIOGT0_Msk (0x40UL) /*!< TIOGT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ULPTISR ======================================================== */ + #define R_ULPT0_ULPTISR_RCCPSEL2_Pos (2UL) /*!< RCCPSEL2 (Bit 2) */ + #define R_ULPT0_ULPTISR_RCCPSEL2_Msk (0x4UL) /*!< RCCPSEL2 (Bitfield-Mask: 0x01) */ +/* ======================================================= ULPTCMSR ======================================================== */ + #define R_ULPT0_ULPTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_ULPT0_ULPTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_ULPT0_ULPTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_ULPT0_ULPTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_ULPT0_ULPTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_ULPT0_ULPTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_ULPT0_ULPTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG_OCD ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== MCUERRSTAT ======================================================= */ + #define R_DEBUG_OCD_MCUERRSTAT_ZERO_Pos (0UL) /*!< ZERO (Bit 0) */ + #define R_DEBUG_OCD_MCUERRSTAT_ZERO_Msk (0x1UL) /*!< ZERO (Bitfield-Mask: 0x01) */ +/* ======================================================== MCUCTRL ======================================================== */ + #define R_DEBUG_OCD_MCUCTRL_EDBGRQ0_Pos (0UL) /*!< EDBGRQ0 (Bit 0) */ + #define R_DEBUG_OCD_MCUCTRL_EDBGRQ0_Msk (0x1UL) /*!< EDBGRQ0 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_OCD_MCUCTRL_EDBGRQ1_Pos (1UL) /*!< EDBGRQ1 (Bit 1) */ + #define R_DEBUG_OCD_MCUCTRL_EDBGRQ1_Msk (0x2UL) /*!< EDBGRQ1 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_OCD_MCUCTRL_DBIRQ0_Pos (8UL) /*!< DBIRQ0 (Bit 8) */ + #define R_DEBUG_OCD_MCUCTRL_DBIRQ0_Msk (0x100UL) /*!< DBIRQ0 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_OCD_MCUCTRL_DBIRQ1_Pos (9UL) /*!< DBIRQ1 (Bit 9) */ + #define R_DEBUG_OCD_MCUCTRL_DBIRQ1_Msk (0x200UL) /*!< DBIRQ1 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_OCD_MCUCTRL_CPUWAIT0_Pos (16UL) /*!< CPUWAIT0 (Bit 16) */ + #define R_DEBUG_OCD_MCUCTRL_CPUWAIT0_Msk (0x10000UL) /*!< CPUWAIT0 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_OCD_MCUCTRL_CPUWAIT1_Pos (17UL) /*!< CPUWAIT1 (Bit 17) */ + #define R_DEBUG_OCD_MCUCTRL_CPUWAIT1_Msk (0x20000UL) /*!< CPUWAIT1 (Bitfield-Mask: 0x01) */ +/* ========================================================= JBMDR ========================================================= */ + #define R_DEBUG_OCD_JBMDR_KEY_Pos (0UL) /*!< KEY (Bit 0) */ + #define R_DEBUG_OCD_JBMDR_KEY_Msk (0xffUL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================= JBRDR ========================================================= */ + #define R_DEBUG_OCD_JBRDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_DEBUG_OCD_JBRDR_RDAT_Msk (0xffffffffUL) /*!< RDAT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= JBTDR ========================================================= */ + #define R_DEBUG_OCD_JBTDR_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_DEBUG_OCD_JBTDR_TDAT_Msk (0xffffffffUL) /*!< TDAT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= JBSTR ========================================================= */ + #define R_DEBUG_OCD_JBSTR_RDF_Pos (0UL) /*!< RDF (Bit 0) */ + #define R_DEBUG_OCD_JBSTR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_DEBUG_OCD_JBSTR_TDE_Pos (1UL) /*!< TDE (Bit 1) */ + #define R_DEBUG_OCD_JBSTR_TDE_Msk (0x2UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= JBICR ========================================================= */ + #define R_DEBUG_OCD_JBICR_RDFIE_Pos (0UL) /*!< RDFIE (Bit 0) */ + #define R_DEBUG_OCD_JBICR_RDFIE_Msk (0x1UL) /*!< RDFIE (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTATM ======================================================= */ + #define R_DEBUG_OCD_FSBLSTATM_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_OCD_FSBLSTATM_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_OCD_FSBLSTATM_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_OCD_FSBLSTATM_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOTF ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== CONVAREAST ======================================================= */ + #define R_DOTF_CONVAREAST_CONVAREAST_Pos (12UL) /*!< CONVAREAST (Bit 12) */ + #define R_DOTF_CONVAREAST_CONVAREAST_Msk (0xfffff000UL) /*!< CONVAREAST (Bitfield-Mask: 0xfffff) */ +/* ======================================================= CONVAREAD ======================================================= */ + #define R_DOTF_CONVAREAD_CONVAREAD_Pos (12UL) /*!< CONVAREAD (Bit 12) */ + #define R_DOTF_CONVAREAD_CONVAREAD_Msk (0xfffff000UL) /*!< CONVAREAD (Bitfield-Mask: 0xfffff) */ +/* ========================================================= REG00 ========================================================= */ + #define R_DOTF_REG00_B09_Pos (9UL) /*!< B09 (Bit 9) */ + #define R_DOTF_REG00_B09_Msk (0x200UL) /*!< B09 (Bitfield-Mask: 0x01) */ + #define R_DOTF_REG00_B16_Pos (16UL) /*!< B16 (Bit 16) */ + #define R_DOTF_REG00_B16_Msk (0x10000UL) /*!< B16 (Bitfield-Mask: 0x01) */ + #define R_DOTF_REG00_B17_Pos (17UL) /*!< B17 (Bit 17) */ + #define R_DOTF_REG00_B17_Msk (0x20000UL) /*!< B17 (Bitfield-Mask: 0x01) */ + #define R_DOTF_REG00_B20_Pos (20UL) /*!< B20 (Bit 20) */ + #define R_DOTF_REG00_B20_Msk (0x100000UL) /*!< B20 (Bitfield-Mask: 0x01) */ + #define R_DOTF_REG00_B24_Pos (24UL) /*!< B24 (Bit 24) */ + #define R_DOTF_REG00_B24_Msk (0x3000000UL) /*!< B24 (Bitfield-Mask: 0x03) */ + #define R_DOTF_REG00_B28_Pos (28UL) /*!< B28 (Bit 28) */ + #define R_DOTF_REG00_B28_Msk (0x30000000UL) /*!< B28 (Bitfield-Mask: 0x03) */ +/* ========================================================= REG03 ========================================================= */ + #define R_DOTF_REG03_B00_Pos (0UL) /*!< B00 (Bit 0) */ + #define R_DOTF_REG03_B00_Msk (0xffffffffUL) /*!< B00 (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_AGTX0 ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_COMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RIPV ========================================================== */ + #define R_COMA_RIPV_TIPV_Pos (0UL) /*!< TIPV (Bit 0) */ + #define R_COMA_RIPV_TIPV_Msk (0xfUL) /*!< TIPV (Bitfield-Mask: 0x0f) */ + #define R_COMA_RIPV_GWIPV_Pos (4UL) /*!< GWIPV (Bit 4) */ + #define R_COMA_RIPV_GWIPV_Msk (0xf0UL) /*!< GWIPV (Bitfield-Mask: 0x0f) */ + #define R_COMA_RIPV_FWIPV_Pos (8UL) /*!< FWIPV (Bit 8) */ + #define R_COMA_RIPV_FWIPV_Msk (0xf00UL) /*!< FWIPV (Bitfield-Mask: 0x0f) */ + #define R_COMA_RIPV_EAIPV_Pos (12UL) /*!< EAIPV (Bit 12) */ + #define R_COMA_RIPV_EAIPV_Msk (0xf000UL) /*!< EAIPV (Bitfield-Mask: 0x0f) */ + #define R_COMA_RIPV_FBIPV_Pos (16UL) /*!< FBIPV (Bit 16) */ + #define R_COMA_RIPV_FBIPV_Msk (0xf0000UL) /*!< FBIPV (Bitfield-Mask: 0x0f) */ + #define R_COMA_RIPV_CAIPV_Pos (20UL) /*!< CAIPV (Bit 20) */ + #define R_COMA_RIPV_CAIPV_Msk (0xf00000UL) /*!< CAIPV (Bitfield-Mask: 0x0f) */ +/* ========================================================== RRC ========================================================== */ + #define R_COMA_RRC_RR_Pos (0UL) /*!< RR (Bit 0) */ + #define R_COMA_RRC_RR_Msk (0x1UL) /*!< RR (Bitfield-Mask: 0x01) */ +/* ========================================================= RCEC ========================================================== */ + #define R_COMA_RCEC_ACE_Pos (0UL) /*!< ACE (Bit 0) */ + #define R_COMA_RCEC_ACE_Msk (0x7fUL) /*!< ACE (Bitfield-Mask: 0x7f) */ + #define R_COMA_RCEC_RCE_Pos (16UL) /*!< RCE (Bit 16) */ + #define R_COMA_RCEC_RCE_Msk (0x10000UL) /*!< RCE (Bitfield-Mask: 0x01) */ +/* ========================================================= RCDC ========================================================== */ + #define R_COMA_RCDC_ACD_Pos (0UL) /*!< ACD (Bit 0) */ + #define R_COMA_RCDC_ACD_Msk (0x7fUL) /*!< ACD (Bitfield-Mask: 0x7f) */ + #define R_COMA_RCDC_RCD_Pos (16UL) /*!< RCD (Bit 16) */ + #define R_COMA_RCDC_RCD_Msk (0x10000UL) /*!< RCD (Bitfield-Mask: 0x01) */ +/* ======================================================= CABPIBWMC ======================================================= */ + #define R_COMA_CABPIBWMC_IBUWMPN_Pos (0UL) /*!< IBUWMPN (Bit 0) */ + #define R_COMA_CABPIBWMC_IBUWMPN_Msk (0x3ffUL) /*!< IBUWMPN (Bitfield-Mask: 0x3ff) */ + #define R_COMA_CABPIBWMC_IBSWMPN_Pos (16UL) /*!< IBSWMPN (Bit 16) */ + #define R_COMA_CABPIBWMC_IBSWMPN_Msk (0x3ff0000UL) /*!< IBSWMPN (Bitfield-Mask: 0x3ff) */ +/* ======================================================= CABPWMLC ======================================================== */ + #define R_COMA_CABPWMLC_WMFL_Pos (0UL) /*!< WMFL (Bit 0) */ + #define R_COMA_CABPWMLC_WMFL_Msk (0x1fffUL) /*!< WMFL (Bitfield-Mask: 0x1fff) */ + #define R_COMA_CABPWMLC_WMCL_Pos (16UL) /*!< WMCL (Bit 16) */ + #define R_COMA_CABPWMLC_WMCL_Msk (0x1fff0000UL) /*!< WMCL (Bitfield-Mask: 0x1fff) */ +/* ======================================================= CABPPFLC ======================================================== */ + #define R_COMA_CABPPFLC_PDL_Pos (0UL) /*!< PDL (Bit 0) */ + #define R_COMA_CABPPFLC_PDL_Msk (0x1fffUL) /*!< PDL (Bitfield-Mask: 0x1fff) */ + #define R_COMA_CABPPFLC_PAL_Pos (16UL) /*!< PAL (Bit 16) */ + #define R_COMA_CABPPFLC_PAL_Msk (0x1fff0000UL) /*!< PAL (Bitfield-Mask: 0x1fff) */ +/* ======================================================= CABPPWMLC ======================================================= */ + #define R_COMA_CABPPWMLC_PWMFL_Pos (0UL) /*!< PWMFL (Bit 0) */ + #define R_COMA_CABPPWMLC_PWMFL_Msk (0x1fffUL) /*!< PWMFL (Bitfield-Mask: 0x1fff) */ + #define R_COMA_CABPPWMLC_PWMCL_Pos (16UL) /*!< PWMCL (Bit 16) */ + #define R_COMA_CABPPWMLC_PWMCL_Msk (0x1fff0000UL) /*!< PWMCL (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CABPULC ======================================================== */ + #define R_COMA_CABPULC_MXNPN_Pos (0UL) /*!< MXNPN (Bit 0) */ + #define R_COMA_CABPULC_MXNPN_Msk (0x1fffUL) /*!< MXNPN (Bitfield-Mask: 0x1fff) */ + #define R_COMA_CABPULC_MNNPN_Pos (16UL) /*!< MNNPN (Bit 16) */ + #define R_COMA_CABPULC_MNNPN_Msk (0x1fff0000UL) /*!< MNNPN (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CABPIRM ======================================================== */ + #define R_COMA_CABPIRM_BPIOG_Pos (0UL) /*!< BPIOG (Bit 0) */ + #define R_COMA_CABPIRM_BPIOG_Msk (0x1UL) /*!< BPIOG (Bitfield-Mask: 0x01) */ + #define R_COMA_CABPIRM_BPR_Pos (1UL) /*!< BPR (Bit 1) */ + #define R_COMA_CABPIRM_BPR_Msk (0x2UL) /*!< BPR (Bitfield-Mask: 0x01) */ +/* ======================================================== CABPPCM ======================================================== */ + #define R_COMA_CABPPCM_RPC_Pos (0UL) /*!< RPC (Bit 0) */ + #define R_COMA_CABPPCM_RPC_Msk (0x1fffUL) /*!< RPC (Bitfield-Mask: 0x1fff) */ + #define R_COMA_CABPPCM_TPC_Pos (16UL) /*!< TPC (Bit 16) */ + #define R_COMA_CABPPCM_TPC_Msk (0x1fff0000UL) /*!< TPC (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CABPLCM ======================================================== */ + #define R_COMA_CABPLCM_LRC_Pos (0UL) /*!< LRC (Bit 0) */ + #define R_COMA_CABPLCM_LRC_Msk (0x1fffUL) /*!< LRC (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CABPCPM ======================================================== */ + #define R_COMA_CABPCPM_RPCP_Pos (0UL) /*!< RPCP (Bit 0) */ + #define R_COMA_CABPCPM_RPCP_Msk (0x1fffUL) /*!< RPCP (Bitfield-Mask: 0x1fff) */ +/* ======================================================= CABPMCPM ======================================================== */ + #define R_COMA_CABPMCPM_RPMCP_Pos (0UL) /*!< RPMCP (Bit 0) */ + #define R_COMA_CABPMCPM_RPMCP_Msk (0x1fffUL) /*!< RPMCP (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CARDNM ========================================================= */ + #define R_COMA_CARDNM_RDNRR_Pos (0UL) /*!< RDNRR (Bit 0) */ + #define R_COMA_CARDNM_RDNRR_Msk (0x1fffUL) /*!< RDNRR (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CARDMNM ======================================================== */ + #define R_COMA_CARDMNM_RDMNRR_Pos (0UL) /*!< RDMNRR (Bit 0) */ + #define R_COMA_CARDMNM_RDMNRR_Msk (0x1fffUL) /*!< RDMNRR (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CARDCN ========================================================= */ + #define R_COMA_CARDCN_RDN_Pos (0UL) /*!< RDN (Bit 0) */ + #define R_COMA_CARDCN_RDN_Msk (0xffffffffUL) /*!< RDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CAEIS0 ========================================================= */ + #define R_COMA_CAEIS0_PECCES_Pos (0UL) /*!< PECCES (Bit 0) */ + #define R_COMA_CAEIS0_PECCES_Msk (0x1UL) /*!< PECCES (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIS0_DSECCES_Pos (1UL) /*!< DSECCES (Bit 1) */ + #define R_COMA_CAEIS0_DSECCES_Msk (0x2UL) /*!< DSECCES (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIS0_BPECCES_Pos (2UL) /*!< BPECCES (Bit 2) */ + #define R_COMA_CAEIS0_BPECCES_Msk (0x4UL) /*!< BPECCES (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIS0_BPOPS_Pos (8UL) /*!< BPOPS (Bit 8) */ + #define R_COMA_CAEIS0_BPOPS_Msk (0x100UL) /*!< BPOPS (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIS0_WMCLOS_Pos (9UL) /*!< WMCLOS (Bit 9) */ + #define R_COMA_CAEIS0_WMCLOS_Msk (0x200UL) /*!< WMCLOS (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIS0_WMFLOS_Pos (10UL) /*!< WMFLOS (Bit 10) */ + #define R_COMA_CAEIS0_WMFLOS_Msk (0x400UL) /*!< WMFLOS (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIS0_EEIPLN_Pos (16UL) /*!< EEIPLN (Bit 16) */ + #define R_COMA_CAEIS0_EEIPLN_Msk (0xf0000UL) /*!< EEIPLN (Bitfield-Mask: 0x0f) */ +/* ======================================================== CAEIE0 ========================================================= */ + #define R_COMA_CAEIE0_PECCEE_Pos (0UL) /*!< PECCEE (Bit 0) */ + #define R_COMA_CAEIE0_PECCEE_Msk (0x1UL) /*!< PECCEE (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIE0_DSECCEE_Pos (1UL) /*!< DSECCEE (Bit 1) */ + #define R_COMA_CAEIE0_DSECCEE_Msk (0x2UL) /*!< DSECCEE (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIE0_BPECCEE_Pos (2UL) /*!< BPECCEE (Bit 2) */ + #define R_COMA_CAEIE0_BPECCEE_Msk (0x4UL) /*!< BPECCEE (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIE0_BPOPE_Pos (8UL) /*!< BPOPE (Bit 8) */ + #define R_COMA_CAEIE0_BPOPE_Msk (0x100UL) /*!< BPOPE (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIE0_WMCLOE_Pos (9UL) /*!< WMCLOE (Bit 9) */ + #define R_COMA_CAEIE0_WMCLOE_Msk (0x200UL) /*!< WMCLOE (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIE0_WMFLOE_Pos (10UL) /*!< WMFLOE (Bit 10) */ + #define R_COMA_CAEIE0_WMFLOE_Msk (0x400UL) /*!< WMFLOE (Bitfield-Mask: 0x01) */ +/* ======================================================== CAEID0 ========================================================= */ + #define R_COMA_CAEID0_PECCED_Pos (0UL) /*!< PECCED (Bit 0) */ + #define R_COMA_CAEID0_PECCED_Msk (0x1UL) /*!< PECCED (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEID0_DSECCED_Pos (1UL) /*!< DSECCED (Bit 1) */ + #define R_COMA_CAEID0_DSECCED_Msk (0x2UL) /*!< DSECCED (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEID0_BPECCED_Pos (2UL) /*!< BPECCED (Bit 2) */ + #define R_COMA_CAEID0_BPECCED_Msk (0x4UL) /*!< BPECCED (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEID0_BPOPD_Pos (8UL) /*!< BPOPD (Bit 8) */ + #define R_COMA_CAEID0_BPOPD_Msk (0x100UL) /*!< BPOPD (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEID0_WMCLOD_Pos (9UL) /*!< WMCLOD (Bit 9) */ + #define R_COMA_CAEID0_WMCLOD_Msk (0x200UL) /*!< WMCLOD (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEID0_WMFLOD_Pos (10UL) /*!< WMFLOD (Bit 10) */ + #define R_COMA_CAEID0_WMFLOD_Msk (0x400UL) /*!< WMFLOD (Bitfield-Mask: 0x01) */ +/* ======================================================== CAEIS1 ========================================================= */ + #define R_COMA_CAEIS1_PWMCLOS_Pos (0UL) /*!< PWMCLOS (Bit 0) */ + #define R_COMA_CAEIS1_PWMCLOS_Msk (0x7fUL) /*!< PWMCLOS (Bitfield-Mask: 0x7f) */ + #define R_COMA_CAEIS1_PWMFLOS_Pos (16UL) /*!< PWMFLOS (Bit 16) */ + #define R_COMA_CAEIS1_PWMFLOS_Msk (0x7f0000UL) /*!< PWMFLOS (Bitfield-Mask: 0x7f) */ +/* ======================================================== CAEIE1 ========================================================= */ + #define R_COMA_CAEIE1_PWMCLOE_Pos (0UL) /*!< PWMCLOE (Bit 0) */ + #define R_COMA_CAEIE1_PWMCLOE_Msk (0x7fUL) /*!< PWMCLOE (Bitfield-Mask: 0x7f) */ + #define R_COMA_CAEIE1_PWMFLOE_Pos (16UL) /*!< PWMFLOE (Bit 16) */ + #define R_COMA_CAEIE1_PWMFLOE_Msk (0x7f0000UL) /*!< PWMFLOE (Bitfield-Mask: 0x7f) */ +/* ======================================================== CAEID1 ========================================================= */ + #define R_COMA_CAEID1_PWMCLOD_Pos (0UL) /*!< PWMCLOD (Bit 0) */ + #define R_COMA_CAEID1_PWMCLOD_Msk (0x7fUL) /*!< PWMCLOD (Bitfield-Mask: 0x7f) */ + #define R_COMA_CAEID1_PWMFLOD_Pos (16UL) /*!< PWMFLOD (Bit 16) */ + #define R_COMA_CAEID1_PWMFLOD_Msk (0x7f0000UL) /*!< PWMFLOD (Bitfield-Mask: 0x7f) */ +/* ======================================================== CAMIS0 ========================================================= */ + #define R_COMA_CAMIS0_PFS_Pos (0UL) /*!< PFS (Bit 0) */ + #define R_COMA_CAMIS0_PFS_Msk (0x3UL) /*!< PFS (Bitfield-Mask: 0x03) */ +/* ======================================================== CAMIE0 ========================================================= */ + #define R_COMA_CAMIE0_PFE_Pos (0UL) /*!< PFE (Bit 0) */ + #define R_COMA_CAMIE0_PFE_Msk (0x3UL) /*!< PFE (Bitfield-Mask: 0x03) */ +/* ======================================================== CAMID0 ========================================================= */ + #define R_COMA_CAMID0_PFD_Pos (0UL) /*!< PFD (Bit 0) */ + #define R_COMA_CAMID0_PFD_Msk (0x3UL) /*!< PFD (Bitfield-Mask: 0x03) */ +/* ======================================================== CAMIS1 ========================================================= */ + #define R_COMA_CAMIS1_PPFS_Pos (0UL) /*!< PPFS (Bit 0) */ + #define R_COMA_CAMIS1_PPFS_Msk (0x3fffUL) /*!< PPFS (Bitfield-Mask: 0x3fff) */ +/* ======================================================== CAMIE1 ========================================================= */ + #define R_COMA_CAMIE1_PPFE_Pos (0UL) /*!< PPFE (Bit 0) */ + #define R_COMA_CAMIE1_PPFE_Msk (0x3fffUL) /*!< PPFE (Bitfield-Mask: 0x3fff) */ +/* ======================================================== CAMID1 ========================================================= */ + #define R_COMA_CAMID1_PPFD_Pos (0UL) /*!< PPFD (Bit 0) */ + #define R_COMA_CAMID1_PPFD_Msk (0x3fffUL) /*!< PPFD (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_CPU_CTRL ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== CPU0LCKUPCR ====================================================== */ + #define R_CPU_CTRL_CPU0LCKUPCR_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_CPU_CTRL_CPU0LCKUPCR_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ====================================================== CPU1LCKUPCR ====================================================== */ + #define R_CPU_CTRL_CPU1LCKUPCR_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_CPU_CTRL_CPU1LCKUPCR_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ===================================================== CPU0INITVTOR ====================================================== */ + #define R_CPU_CTRL_CPU0INITVTOR_CPUnINITVTOR_Pos (0UL) /*!< CPUnINITVTOR (Bit 0) */ + #define R_CPU_CTRL_CPU0INITVTOR_CPUnINITVTOR_Msk (0xffffffffUL) /*!< CPUnINITVTOR (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CPU1INITVTOR ====================================================== */ + #define R_CPU_CTRL_CPU1INITVTOR_CPUnINITVTOR_Pos (0UL) /*!< CPUnINITVTOR (Bit 0) */ + #define R_CPU_CTRL_CPU1INITVTOR_CPUnINITVTOR_Msk (0xffffffffUL) /*!< CPUnINITVTOR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== CPU0WAITCR ======================================================= */ + #define R_CPU_CTRL_CPU0WAITCR_CPUWAIT_Pos (0UL) /*!< CPUWAIT (Bit 0) */ + #define R_CPU_CTRL_CPU0WAITCR_CPUWAIT_Msk (0x1UL) /*!< CPUWAIT (Bitfield-Mask: 0x01) */ +/* ====================================================== CPU1WAITCR ======================================================= */ + #define R_CPU_CTRL_CPU1WAITCR_CPUWAIT_Pos (0UL) /*!< CPUWAIT (Bit 0) */ + #define R_CPU_CTRL_CPU1WAITCR_CPUWAIT_Msk (0x1UL) /*!< CPUWAIT (Bitfield-Mask: 0x01) */ +/* ====================================================== CPU0ACTCSR ======================================================= */ + #define R_CPU_CTRL_CPU0ACTCSR_ACTREQ_Pos (0UL) /*!< ACTREQ (Bit 0) */ + #define R_CPU_CTRL_CPU0ACTCSR_ACTREQ_Msk (0x1UL) /*!< ACTREQ (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0ACTCSR_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_CPU_CTRL_CPU0ACTCSR_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0ACTCSR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CPU_CTRL_CPU0ACTCSR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ====================================================== CPU1ACTCSR ======================================================= */ + #define R_CPU_CTRL_CPU1ACTCSR_ACTREQ_Pos (0UL) /*!< ACTREQ (Bit 0) */ + #define R_CPU_CTRL_CPU1ACTCSR_ACTREQ_Msk (0x1UL) /*!< ACTREQ (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1ACTCSR_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_CPU_CTRL_CPU1ACTCSR_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1ACTCSR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CPU_CTRL_CPU1ACTCSR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CPU0LMECR ======================================================= */ + #define R_CPU_CTRL_CPU0LMECR_SYRSTEN_Pos (0UL) /*!< SYRSTEN (Bit 0) */ + #define R_CPU_CTRL_CPU0LMECR_SYRSTEN_Msk (0x1UL) /*!< SYRSTEN (Bitfield-Mask: 0x01) */ +/* ======================================================== CPUIDR ========================================================= */ + #define R_CPU_CTRL_CPUIDR_CPUID_Pos (0UL) /*!< CPUID (Bit 0) */ + #define R_CPU_CTRL_CPUIDR_CPUID_Msk (0x1UL) /*!< CPUID (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0STATM ======================================================= */ + #define R_CPU_CTRL_CPU0STATM_SLEEPING_Pos (0UL) /*!< SLEEPING (Bit 0) */ + #define R_CPU_CTRL_CPU0STATM_SLEEPING_Msk (0x1UL) /*!< SLEEPING (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0STATM_SLEEPDEEP_Pos (1UL) /*!< SLEEPDEEP (Bit 1) */ + #define R_CPU_CTRL_CPU0STATM_SLEEPDEEP_Msk (0x2UL) /*!< SLEEPDEEP (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0STATM_SAHBSTP_Pos (4UL) /*!< SAHBSTP (Bit 4) */ + #define R_CPU_CTRL_CPU0STATM_SAHBSTP_Msk (0x10UL) /*!< SAHBSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU1STATM ======================================================= */ + #define R_CPU_CTRL_CPU1STATM_SLEEPING_Pos (0UL) /*!< SLEEPING (Bit 0) */ + #define R_CPU_CTRL_CPU1STATM_SLEEPING_Msk (0x1UL) /*!< SLEEPING (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1STATM_SLEEPDEEP_Pos (1UL) /*!< SLEEPDEEP (Bit 1) */ + #define R_CPU_CTRL_CPU1STATM_SLEEPDEEP_Msk (0x2UL) /*!< SLEEPDEEP (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1STATM_SAHBSTP_Pos (4UL) /*!< SAHBSTP (Bit 4) */ + #define R_CPU_CTRL_CPU1STATM_SAHBSTP_Msk (0x10UL) /*!< SAHBSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= SECEXTMON ======================================================= */ + #define R_CPU_CTRL_SECEXTMON_SECEXT_Pos (0UL) /*!< SECEXT (Bit 0) */ + #define R_CPU_CTRL_SECEXTMON_SECEXT_Msk (0x1UL) /*!< SECEXT (Bitfield-Mask: 0x01) */ +/* ======================================================== NSCPUCR ======================================================== */ + #define R_CPU_CTRL_NSCPUCR_RSTREQEN_Pos (0UL) /*!< RSTREQEN (Bit 0) */ + #define R_CPU_CTRL_NSCPUCR_RSTREQEN_Msk (0x1UL) /*!< RSTREQEN (Bitfield-Mask: 0x01) */ +/* ====================================================== CPU0LOCKCR ======================================================= */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKSVTAIR_Pos (0UL) /*!< LCKSVTAIR (Bit 0) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKSVTAIR_Msk (0x1UL) /*!< LCKSVTAIR (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKSMPU_Pos (1UL) /*!< LCKSMPU (Bit 1) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKSMPU_Msk (0x2UL) /*!< LCKSMPU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKSAU_Pos (2UL) /*!< LCKSAU (Bit 2) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKSAU_Msk (0x4UL) /*!< LCKSAU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKITGU_Pos (3UL) /*!< LCKITGU (Bit 3) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKITGU_Msk (0x8UL) /*!< LCKITGU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKDTGU_Pos (4UL) /*!< LCKDTGU (Bit 4) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKDTGU_Msk (0x10UL) /*!< LCKDTGU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKDCAIC_Pos (5UL) /*!< LCKDCAIC (Bit 5) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKDCAIC_Msk (0x20UL) /*!< LCKDCAIC (Bitfield-Mask: 0x01) */ +/* ====================================================== CPU1LOCKCR ======================================================= */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKSVTAIR_Pos (0UL) /*!< LCKSVTAIR (Bit 0) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKSVTAIR_Msk (0x1UL) /*!< LCKSVTAIR (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKSMPU_Pos (1UL) /*!< LCKSMPU (Bit 1) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKSMPU_Msk (0x2UL) /*!< LCKSMPU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKSAU_Pos (2UL) /*!< LCKSAU (Bit 2) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKSAU_Msk (0x4UL) /*!< LCKSAU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKITGU_Pos (3UL) /*!< LCKITGU (Bit 3) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKITGU_Msk (0x8UL) /*!< LCKITGU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKDTGU_Pos (4UL) /*!< LCKDTGU (Bit 4) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKDTGU_Msk (0x10UL) /*!< LCKDTGU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKDCAIC_Pos (5UL) /*!< LCKDCAIC (Bit 5) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKDCAIC_Msk (0x20UL) /*!< LCKDCAIC (Bitfield-Mask: 0x01) */ +/* ===================================================== CPU0LOCKCRNS ====================================================== */ + #define R_CPU_CTRL_CPU0LOCKCRNS_LCKNSVTOR_Pos (0UL) /*!< LCKNSVTOR (Bit 0) */ + #define R_CPU_CTRL_CPU0LOCKCRNS_LCKNSVTOR_Msk (0x1UL) /*!< LCKNSVTOR (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0LOCKCRNS_LCKNSMPU_Pos (1UL) /*!< LCKNSMPU (Bit 1) */ + #define R_CPU_CTRL_CPU0LOCKCRNS_LCKNSMPU_Msk (0x2UL) /*!< LCKNSMPU (Bitfield-Mask: 0x01) */ +/* ===================================================== CPU1LOCKCRNS ====================================================== */ + #define R_CPU_CTRL_CPU1LOCKCRNS_LCKNSVTOR_Pos (0UL) /*!< LCKNSVTOR (Bit 0) */ + #define R_CPU_CTRL_CPU1LOCKCRNS_LCKNSVTOR_Msk (0x1UL) /*!< LCKNSVTOR (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1LOCKCRNS_LCKNSMPU_Pos (1UL) /*!< LCKNSMPU (Bit 1) */ + #define R_CPU_CTRL_CPU1LOCKCRNS_LCKNSMPU_Msk (0x2UL) /*!< LCKNSMPU (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0CRPT ======================================================== */ + #define R_CPU_CTRL_CPU0CRPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_CPU_CTRL_CPU0CRPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0CRPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CPU_CTRL_CPU0CRPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CPU1CRPT ======================================================== */ + #define R_CPU_CTRL_CPU1CRPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_CPU_CTRL_CPU1CRPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1CRPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CPU_CTRL_CPU1CRPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= EC710CTL ======================================================== */ + #define R_ECCMB0_EC710CTL_ECEMF_Pos (0UL) /*!< ECEMF (Bit 0) */ + #define R_ECCMB0_EC710CTL_ECEMF_Msk (0x1UL) /*!< ECEMF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1F_Pos (1UL) /*!< ECER1F (Bit 1) */ + #define R_ECCMB0_EC710CTL_ECER1F_Msk (0x2UL) /*!< ECER1F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2F_Pos (2UL) /*!< ECER2F (Bit 2) */ + #define R_ECCMB0_EC710CTL_ECER2F_Msk (0x4UL) /*!< ECER2F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Pos (3UL) /*!< EC1EDIC (Bit 3) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Msk (0x8UL) /*!< EC1EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Pos (4UL) /*!< EC2EDIC (Bit 4) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Msk (0x10UL) /*!< EC2EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Pos (5UL) /*!< EC1ECP (Bit 5) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Msk (0x20UL) /*!< EC1ECP (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECERVF_Pos (6UL) /*!< ECERVF (Bit 6) */ + #define R_ECCMB0_EC710CTL_ECERVF_Msk (0x40UL) /*!< ECERVF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1C_Pos (9UL) /*!< ECER1C (Bit 9) */ + #define R_ECCMB0_EC710CTL_ECER1C_Msk (0x200UL) /*!< ECER1C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2C_Pos (10UL) /*!< ECER2C (Bit 10) */ + #define R_ECCMB0_EC710CTL_ECER2C_Msk (0x400UL) /*!< ECER2C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Pos (11UL) /*!< ECOVFF (Bit 11) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Msk (0x800UL) /*!< ECOVFF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EMCA_Pos (14UL) /*!< EMCA (Bit 14) */ + #define R_ECCMB0_EC710CTL_EMCA_Msk (0xc000UL) /*!< EMCA (Bitfield-Mask: 0x03) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Pos (16UL) /*!< ECSEDF0 (Bit 16) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Msk (0x10000UL) /*!< ECSEDF0 (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Pos (17UL) /*!< ECDEDF0 (Bit 17) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Msk (0x20000UL) /*!< ECDEDF0 (Bitfield-Mask: 0x01) */ +/* ======================================================= EC710TMC ======================================================== */ + #define R_ECCMB0_EC710TMC_ECDCS_Pos (1UL) /*!< ECDCS (Bit 1) */ + #define R_ECCMB0_EC710TMC_ECDCS_Msk (0x2UL) /*!< ECDCS (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Pos (7UL) /*!< ECTMCE (Bit 7) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Msk (0x80UL) /*!< ECTMCE (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ETMA_Pos (14UL) /*!< ETMA (Bit 14) */ + #define R_ECCMB0_EC710TMC_ETMA_Msk (0xc000UL) /*!< ETMA (Bitfield-Mask: 0x03) */ +/* ======================================================= EC710TED ======================================================== */ + #define R_ECCMB0_EC710TED_ECEDB_Pos (0UL) /*!< ECEDB (Bit 0) */ + #define R_ECCMB0_EC710TED_ECEDB_Msk (0xffffffffUL) /*!< ECEDB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EC710EAD0 ======================================================= */ + #define R_ECCMB0_EC710EAD0_ECEAD_Pos (0UL) /*!< ECEAD (Bit 0) */ + #define R_ECCMB0_EC710EAD0_ECEAD_Msk (0x3ffUL) /*!< ECEAD (Bitfield-Mask: 0x3ff) */ + +/* =========================================================================================================================== */ +/* ================ R_ESWM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= TPEMIMC0 ======================================================== */ + #define R_ESWM_TPEMIMC0_SEIM_Pos (0UL) /*!< SEIM (Bit 0) */ + #define R_ESWM_TPEMIMC0_SEIM_Msk (0x1UL) /*!< SEIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC0_SEIGM_Pos (1UL) /*!< SEIGM (Bit 1) */ + #define R_ESWM_TPEMIMC0_SEIGM_Msk (0x2UL) /*!< SEIGM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC0_SEICM_Pos (4UL) /*!< SEICM (Bit 4) */ + #define R_ESWM_TPEMIMC0_SEICM_Msk (0x70UL) /*!< SEICM (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC0_SSIM_Pos (16UL) /*!< SSIM (Bit 16) */ + #define R_ESWM_TPEMIMC0_SSIM_Msk (0x10000UL) /*!< SSIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC0_SSIGM_Pos (17UL) /*!< SSIGM (Bit 17) */ + #define R_ESWM_TPEMIMC0_SSIGM_Msk (0x20000UL) /*!< SSIGM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC0_SSICM_Pos (20UL) /*!< SSICM (Bit 20) */ + #define R_ESWM_TPEMIMC0_SSICM_Msk (0x700000UL) /*!< SSICM (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC1 ======================================================== */ + #define R_ESWM_TPEMIMC1_FEIM_Pos (0UL) /*!< FEIM (Bit 0) */ + #define R_ESWM_TPEMIMC1_FEIM_Msk (0x1UL) /*!< FEIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_FEIGM_Pos (1UL) /*!< FEIGM (Bit 1) */ + #define R_ESWM_TPEMIMC1_FEIGM_Msk (0x2UL) /*!< FEIGM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_FEICM_Pos (4UL) /*!< FEICM (Bit 4) */ + #define R_ESWM_TPEMIMC1_FEICM_Msk (0x70UL) /*!< FEICM (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC1_FSIM_Pos (8UL) /*!< FSIM (Bit 8) */ + #define R_ESWM_TPEMIMC1_FSIM_Msk (0x100UL) /*!< FSIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_FSIGM_Pos (9UL) /*!< FSIGM (Bit 9) */ + #define R_ESWM_TPEMIMC1_FSIGM_Msk (0x200UL) /*!< FSIGM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_FSICM_Pos (12UL) /*!< FSICM (Bit 12) */ + #define R_ESWM_TPEMIMC1_FSICM_Msk (0x7000UL) /*!< FSICM (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC1_CEIM_Pos (16UL) /*!< CEIM (Bit 16) */ + #define R_ESWM_TPEMIMC1_CEIM_Msk (0x10000UL) /*!< CEIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_CEIGM_Pos (17UL) /*!< CEIGM (Bit 17) */ + #define R_ESWM_TPEMIMC1_CEIGM_Msk (0x20000UL) /*!< CEIGM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_CEICM_Pos (20UL) /*!< CEICM (Bit 20) */ + #define R_ESWM_TPEMIMC1_CEICM_Msk (0x700000UL) /*!< CEICM (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC1_CSIM_Pos (24UL) /*!< CSIM (Bit 24) */ + #define R_ESWM_TPEMIMC1_CSIM_Msk (0x1000000UL) /*!< CSIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_CSIGM_Pos (25UL) /*!< CSIGM (Bit 25) */ + #define R_ESWM_TPEMIMC1_CSIGM_Msk (0x2000000UL) /*!< CSIGM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_CSICM_Pos (28UL) /*!< CSICM (Bit 28) */ + #define R_ESWM_TPEMIMC1_CSICM_Msk (0x70000000UL) /*!< CSICM (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC2 ======================================================== */ + #define R_ESWM_TPEMIMC2_GEIM0_Pos (0UL) /*!< GEIM0 (Bit 0) */ + #define R_ESWM_TPEMIMC2_GEIM0_Msk (0x1UL) /*!< GEIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC2_GEIGM0_Pos (1UL) /*!< GEIGM0 (Bit 1) */ + #define R_ESWM_TPEMIMC2_GEIGM0_Msk (0x2UL) /*!< GEIGM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC2_GEICM0_Pos (4UL) /*!< GEICM0 (Bit 4) */ + #define R_ESWM_TPEMIMC2_GEICM0_Msk (0x70UL) /*!< GEICM0 (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC2_GSIM0_Pos (8UL) /*!< GSIM0 (Bit 8) */ + #define R_ESWM_TPEMIMC2_GSIM0_Msk (0x100UL) /*!< GSIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC2_GSIGM0_Pos (9UL) /*!< GSIGM0 (Bit 9) */ + #define R_ESWM_TPEMIMC2_GSIGM0_Msk (0x200UL) /*!< GSIGM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC2_GSICM0_Pos (12UL) /*!< GSICM0 (Bit 12) */ + #define R_ESWM_TPEMIMC2_GSICM0_Msk (0x7000UL) /*!< GSICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC3 ======================================================== */ + #define R_ESWM_TPEMIMC3_EEIM0_Pos (0UL) /*!< EEIM0 (Bit 0) */ + #define R_ESWM_TPEMIMC3_EEIM0_Msk (0x1UL) /*!< EEIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC3_EEIGM0_Pos (1UL) /*!< EEIGM0 (Bit 1) */ + #define R_ESWM_TPEMIMC3_EEIGM0_Msk (0x2UL) /*!< EEIGM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC3_EEICM0_Pos (4UL) /*!< EEICM0 (Bit 4) */ + #define R_ESWM_TPEMIMC3_EEICM0_Msk (0x70UL) /*!< EEICM0 (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC3_ESIM0_Pos (8UL) /*!< ESIM0 (Bit 8) */ + #define R_ESWM_TPEMIMC3_ESIM0_Msk (0x100UL) /*!< ESIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC3_ESIGM0_Pos (9UL) /*!< ESIGM0 (Bit 9) */ + #define R_ESWM_TPEMIMC3_ESIGM0_Msk (0x200UL) /*!< ESIGM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC3_ESICM0_Pos (12UL) /*!< ESICM0 (Bit 12) */ + #define R_ESWM_TPEMIMC3_ESICM0_Msk (0x7000UL) /*!< ESICM0 (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC3_RSIM0_Pos (16UL) /*!< RSIM0 (Bit 16) */ + #define R_ESWM_TPEMIMC3_RSIM0_Msk (0x10000UL) /*!< RSIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC3_RSIGM0_Pos (17UL) /*!< RSIGM0 (Bit 17) */ + #define R_ESWM_TPEMIMC3_RSIGM0_Msk (0x20000UL) /*!< RSIGM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC3_RSICM0_Pos (20UL) /*!< RSICM0 (Bit 20) */ + #define R_ESWM_TPEMIMC3_RSICM0_Msk (0x700000UL) /*!< RSICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC4 ======================================================== */ + #define R_ESWM_TPEMIMC4_EEIM1_Pos (0UL) /*!< EEIM1 (Bit 0) */ + #define R_ESWM_TPEMIMC4_EEIM1_Msk (0x1UL) /*!< EEIM1 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC4_EEIGM1_Pos (1UL) /*!< EEIGM1 (Bit 1) */ + #define R_ESWM_TPEMIMC4_EEIGM1_Msk (0x2UL) /*!< EEIGM1 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC4_EEICM1_Pos (4UL) /*!< EEICM1 (Bit 4) */ + #define R_ESWM_TPEMIMC4_EEICM1_Msk (0x70UL) /*!< EEICM1 (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC4_ESIM1_Pos (8UL) /*!< ESIM1 (Bit 8) */ + #define R_ESWM_TPEMIMC4_ESIM1_Msk (0x100UL) /*!< ESIM1 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC4_ESIGM1_Pos (9UL) /*!< ESIGM1 (Bit 9) */ + #define R_ESWM_TPEMIMC4_ESIGM1_Msk (0x200UL) /*!< ESIGM1 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC4_ESICM1_Pos (12UL) /*!< ESICM1 (Bit 12) */ + #define R_ESWM_TPEMIMC4_ESICM1_Msk (0x7000UL) /*!< ESICM1 (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC4_RSIM1_Pos (16UL) /*!< RSIM1 (Bit 16) */ + #define R_ESWM_TPEMIMC4_RSIM1_Msk (0x10000UL) /*!< RSIM1 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC4_RSIGM1_Pos (17UL) /*!< RSIGM1 (Bit 17) */ + #define R_ESWM_TPEMIMC4_RSIGM1_Msk (0x20000UL) /*!< RSIGM1 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC4_RSICM1_Pos (20UL) /*!< RSICM1 (Bit 20) */ + #define R_ESWM_TPEMIMC4_RSICM1_Msk (0x700000UL) /*!< RSICM1 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC60 ======================================================= */ + #define R_ESWM_TPEMIMC60_GTSIM0_Pos (0UL) /*!< GTSIM0 (Bit 0) */ + #define R_ESWM_TPEMIMC60_GTSIM0_Msk (0x1UL) /*!< GTSIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC60_GTSICM0_Pos (1UL) /*!< GTSICM0 (Bit 1) */ + #define R_ESWM_TPEMIMC60_GTSICM0_Msk (0xeUL) /*!< GTSICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC61 ======================================================= */ + #define R_ESWM_TPEMIMC61_GTSIM0_Pos (0UL) /*!< GTSIM0 (Bit 0) */ + #define R_ESWM_TPEMIMC61_GTSIM0_Msk (0x1UL) /*!< GTSIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC61_GTSICM0_Pos (1UL) /*!< GTSICM0 (Bit 1) */ + #define R_ESWM_TPEMIMC61_GTSICM0_Msk (0xeUL) /*!< GTSICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC62 ======================================================= */ + #define R_ESWM_TPEMIMC62_GTSIM0_Pos (0UL) /*!< GTSIM0 (Bit 0) */ + #define R_ESWM_TPEMIMC62_GTSIM0_Msk (0x1UL) /*!< GTSIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC62_GTSICM0_Pos (1UL) /*!< GTSICM0 (Bit 1) */ + #define R_ESWM_TPEMIMC62_GTSICM0_Msk (0xeUL) /*!< GTSICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC63 ======================================================= */ + #define R_ESWM_TPEMIMC63_GTSIM0_Pos (0UL) /*!< GTSIM0 (Bit 0) */ + #define R_ESWM_TPEMIMC63_GTSIM0_Msk (0x1UL) /*!< GTSIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC63_GTSICM0_Pos (1UL) /*!< GTSICM0 (Bit 1) */ + #define R_ESWM_TPEMIMC63_GTSICM0_Msk (0xeUL) /*!< GTSICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC64 ======================================================= */ + #define R_ESWM_TPEMIMC64_GTSIM0_Pos (0UL) /*!< GTSIM0 (Bit 0) */ + #define R_ESWM_TPEMIMC64_GTSIM0_Msk (0x1UL) /*!< GTSIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC64_GTSICM0_Pos (1UL) /*!< GTSICM0 (Bit 1) */ + #define R_ESWM_TPEMIMC64_GTSICM0_Msk (0xeUL) /*!< GTSICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC70 ======================================================= */ + #define R_ESWM_TPEMIMC70_GDICM0_Pos (0UL) /*!< GDICM0 (Bit 0) */ + #define R_ESWM_TPEMIMC70_GDICM0_Msk (0x7UL) /*!< GDICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC71 ======================================================= */ + #define R_ESWM_TPEMIMC71_GDICM0_Pos (0UL) /*!< GDICM0 (Bit 0) */ + #define R_ESWM_TPEMIMC71_GDICM0_Msk (0x7UL) /*!< GDICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC72 ======================================================= */ + #define R_ESWM_TPEMIMC72_GDICM0_Pos (0UL) /*!< GDICM0 (Bit 0) */ + #define R_ESWM_TPEMIMC72_GDICM0_Msk (0x7UL) /*!< GDICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC73 ======================================================= */ + #define R_ESWM_TPEMIMC73_GDICM0_Pos (0UL) /*!< GDICM0 (Bit 0) */ + #define R_ESWM_TPEMIMC73_GDICM0_Msk (0x7UL) /*!< GDICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC74 ======================================================= */ + #define R_ESWM_TPEMIMC74_GDICM0_Pos (0UL) /*!< GDICM0 (Bit 0) */ + #define R_ESWM_TPEMIMC74_GDICM0_Msk (0x7UL) /*!< GDICM0 (Bitfield-Mask: 0x07) */ +/* ========================================================= TSIM ========================================================== */ + #define R_ESWM_TSIM_FIM_Pos (0UL) /*!< FIM (Bit 0) */ + #define R_ESWM_TSIM_FIM_Msk (0x1UL) /*!< FIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TSIM_CIM_Pos (1UL) /*!< CIM (Bit 1) */ + #define R_ESWM_TSIM_CIM_Msk (0x2UL) /*!< CIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TSIM_GIM_Pos (2UL) /*!< GIM (Bit 2) */ + #define R_ESWM_TSIM_GIM_Msk (0x4UL) /*!< GIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TSIM_EIM_Pos (4UL) /*!< EIM (Bit 4) */ + #define R_ESWM_TSIM_EIM_Msk (0x10UL) /*!< EIM (Bitfield-Mask: 0x01) */ +/* ========================================================= TFIM ========================================================== */ + #define R_ESWM_TFIM_FWEISIM_Pos (0UL) /*!< FWEISIM (Bit 0) */ + #define R_ESWM_TFIM_FWEISIM_Msk (0x1UL) /*!< FWEISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TFIM_FWMISIM0_Pos (9UL) /*!< FWMISIM0 (Bit 9) */ + #define R_ESWM_TFIM_FWMISIM0_Msk (0x200UL) /*!< FWMISIM0 (Bitfield-Mask: 0x01) */ +/* ========================================================= TCIM ========================================================== */ + #define R_ESWM_TCIM_RSSISIM_Pos (0UL) /*!< RSSISIM (Bit 0) */ + #define R_ESWM_TCIM_RSSISIM_Msk (0x1UL) /*!< RSSISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TCIM_CAEISIM_Pos (1UL) /*!< CAEISIM (Bit 1) */ + #define R_ESWM_TCIM_CAEISIM_Msk (0x2UL) /*!< CAEISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TCIM_CAMISIM_Pos (3UL) /*!< CAMISIM (Bit 3) */ + #define R_ESWM_TCIM_CAMISIM_Msk (0x8UL) /*!< CAMISIM (Bitfield-Mask: 0x01) */ +/* ========================================================= TGIM0 ========================================================= */ + #define R_ESWM_TGIM0_GWDISIM_Pos (0UL) /*!< GWDISIM (Bit 0) */ + #define R_ESWM_TGIM0_GWDISIM_Msk (0x1UL) /*!< GWDISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TGIM0_GWTSDISIM_Pos (1UL) /*!< GWTSDISIM (Bit 1) */ + #define R_ESWM_TGIM0_GWTSDISIM_Msk (0x2UL) /*!< GWTSDISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TGIM0_GWEISIM_Pos (2UL) /*!< GWEISIM (Bit 2) */ + #define R_ESWM_TGIM0_GWEISIM_Msk (0x4UL) /*!< GWEISIM (Bitfield-Mask: 0x01) */ +/* ========================================================= TEIM0 ========================================================= */ + #define R_ESWM_TEIM0_EAEISIM_Pos (0UL) /*!< EAEISIM (Bit 0) */ + #define R_ESWM_TEIM0_EAEISIM_Msk (0x1UL) /*!< EAEISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TEIM0_MEISIM_Pos (3UL) /*!< MEISIM (Bit 3) */ + #define R_ESWM_TEIM0_MEISIM_Msk (0x8UL) /*!< MEISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TEIM0_MMISIM_Pos (4UL) /*!< MMISIM (Bit 4) */ + #define R_ESWM_TEIM0_MMISIM_Msk (0x10UL) /*!< MMISIM (Bitfield-Mask: 0x01) */ +/* ========================================================= TEIM1 ========================================================= */ + #define R_ESWM_TEIM1_EAEISIM_Pos (0UL) /*!< EAEISIM (Bit 0) */ + #define R_ESWM_TEIM1_EAEISIM_Msk (0x1UL) /*!< EAEISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TEIM1_MEISIM_Pos (3UL) /*!< MEISIM (Bit 3) */ + #define R_ESWM_TEIM1_MEISIM_Msk (0x8UL) /*!< MEISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TEIM1_MMISIM_Pos (4UL) /*!< MMISIM (Bit 4) */ + #define R_ESWM_TEIM1_MMISIM_Msk (0x10UL) /*!< MMISIM (Bitfield-Mask: 0x01) */ +/* ========================================================= MIIRR ========================================================= */ + #define R_ESWM_MIIRR_RGRST_Pos (0UL) /*!< RGRST (Bit 0) */ + #define R_ESWM_MIIRR_RGRST_Msk (0x1UL) /*!< RGRST (Bitfield-Mask: 0x01) */ + #define R_ESWM_MIIRR_RMRST_Pos (8UL) /*!< RMRST (Bit 8) */ + #define R_ESWM_MIIRR_RMRST_Msk (0x100UL) /*!< RMRST (Bitfield-Mask: 0x01) */ +/* ======================================================== MIICR0 ========================================================= */ + #define R_ESWM_MIICR0_MIISEL_Pos (0UL) /*!< MIISEL (Bit 0) */ + #define R_ESWM_MIICR0_MIISEL_Msk (0x3UL) /*!< MIISEL (Bitfield-Mask: 0x03) */ + #define R_ESWM_MIICR0_DIVSTP_Pos (8UL) /*!< DIVSTP (Bit 8) */ + #define R_ESWM_MIICR0_DIVSTP_Msk (0x100UL) /*!< DIVSTP (Bitfield-Mask: 0x01) */ + #define R_ESWM_MIICR0_TXCIDE_Pos (12UL) /*!< TXCIDE (Bit 12) */ + #define R_ESWM_MIICR0_TXCIDE_Msk (0x1000UL) /*!< TXCIDE (Bitfield-Mask: 0x01) */ +/* ======================================================== MIICR1 ========================================================= */ + #define R_ESWM_MIICR1_MIISEL_Pos (0UL) /*!< MIISEL (Bit 0) */ + #define R_ESWM_MIICR1_MIISEL_Msk (0x3UL) /*!< MIISEL (Bitfield-Mask: 0x03) */ + #define R_ESWM_MIICR1_DIVSTP_Pos (8UL) /*!< DIVSTP (Bit 8) */ + #define R_ESWM_MIICR1_DIVSTP_Msk (0x100UL) /*!< DIVSTP (Bitfield-Mask: 0x01) */ + #define R_ESWM_MIICR1_TXCIDE_Pos (12UL) /*!< TXCIDE (Bit 12) */ + #define R_ESWM_MIICR1_TXCIDE_Msk (0x1000UL) /*!< TXCIDE (Bitfield-Mask: 0x01) */ +/* ======================================================== MCCESR ========================================================= */ + #define R_ESWM_MCCESR_MCCES_Pos (0UL) /*!< MCCES (Bit 0) */ + #define R_ESWM_MCCESR_MCCES_Msk (0x1UL) /*!< MCCES (Bitfield-Mask: 0x01) */ +/* ======================================================== TASSTSR ======================================================== */ + #define R_ESWM_TASSTSR_MSS_Pos (0UL) /*!< MSS (Bit 0) */ + #define R_ESWM_TASSTSR_MSS_Msk (0x1fUL) /*!< MSS (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHA0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= EAMC ========================================================== */ + #define R_ETHA0_EAMC_OPC_Pos (0UL) /*!< OPC (Bit 0) */ + #define R_ETHA0_EAMC_OPC_Msk (0x3UL) /*!< OPC (Bitfield-Mask: 0x03) */ +/* ========================================================= EAMS ========================================================== */ + #define R_ETHA0_EAMS_OPS_Pos (0UL) /*!< OPS (Bit 0) */ + #define R_ETHA0_EAMS_OPS_Msk (0x3UL) /*!< OPS (Bitfield-Mask: 0x03) */ +/* ========================================================= EAIRC ========================================================= */ + #define R_ETHA0_EAIRC_IPVR0_Pos (0UL) /*!< IPVR0 (Bit 0) */ + #define R_ETHA0_EAIRC_IPVR0_Msk (0x7UL) /*!< IPVR0 (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAIRC_IPVR1_Pos (4UL) /*!< IPVR1 (Bit 4) */ + #define R_ETHA0_EAIRC_IPVR1_Msk (0x70UL) /*!< IPVR1 (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAIRC_IPVR2_Pos (8UL) /*!< IPVR2 (Bit 8) */ + #define R_ETHA0_EAIRC_IPVR2_Msk (0x700UL) /*!< IPVR2 (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAIRC_IPVR3_Pos (12UL) /*!< IPVR3 (Bit 12) */ + #define R_ETHA0_EAIRC_IPVR3_Msk (0x7000UL) /*!< IPVR3 (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAIRC_IPVR4_Pos (16UL) /*!< IPVR4 (Bit 16) */ + #define R_ETHA0_EAIRC_IPVR4_Msk (0x70000UL) /*!< IPVR4 (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAIRC_IPVR5_Pos (20UL) /*!< IPVR5 (Bit 20) */ + #define R_ETHA0_EAIRC_IPVR5_Msk (0x700000UL) /*!< IPVR5 (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAIRC_IPVR6_Pos (24UL) /*!< IPVR6 (Bit 24) */ + #define R_ETHA0_EAIRC_IPVR6_Msk (0x7000000UL) /*!< IPVR6 (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAIRC_IPVR7_Pos (28UL) /*!< IPVR7 (Bit 28) */ + #define R_ETHA0_EAIRC_IPVR7_Msk (0x70000000UL) /*!< IPVR7 (Bitfield-Mask: 0x07) */ +/* ======================================================== EATDQSC ======================================================== */ + #define R_ETHA0_EATDQSC_TDQSL0_Pos (0UL) /*!< TDQSL0 (Bit 0) */ + #define R_ETHA0_EATDQSC_TDQSL0_Msk (0x1UL) /*!< TDQSL0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQSC_TDQSL1_Pos (1UL) /*!< TDQSL1 (Bit 1) */ + #define R_ETHA0_EATDQSC_TDQSL1_Msk (0x2UL) /*!< TDQSL1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQSC_TDQSL2_Pos (2UL) /*!< TDQSL2 (Bit 2) */ + #define R_ETHA0_EATDQSC_TDQSL2_Msk (0x4UL) /*!< TDQSL2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQSC_TDQSL3_Pos (3UL) /*!< TDQSL3 (Bit 3) */ + #define R_ETHA0_EATDQSC_TDQSL3_Msk (0x8UL) /*!< TDQSL3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQSC_TDQSL4_Pos (4UL) /*!< TDQSL4 (Bit 4) */ + #define R_ETHA0_EATDQSC_TDQSL4_Msk (0x10UL) /*!< TDQSL4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQSC_TDQSL5_Pos (5UL) /*!< TDQSL5 (Bit 5) */ + #define R_ETHA0_EATDQSC_TDQSL5_Msk (0x20UL) /*!< TDQSL5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQSC_TDQSL6_Pos (6UL) /*!< TDQSL6 (Bit 6) */ + #define R_ETHA0_EATDQSC_TDQSL6_Msk (0x40UL) /*!< TDQSL6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQSC_TDQSL7_Pos (7UL) /*!< TDQSL7 (Bit 7) */ + #define R_ETHA0_EATDQSC_TDQSL7_Msk (0x80UL) /*!< TDQSL7 (Bitfield-Mask: 0x01) */ +/* ======================================================== EATDQC ========================================================= */ + #define R_ETHA0_EATDQC_TDQD0_Pos (0UL) /*!< TDQD0 (Bit 0) */ + #define R_ETHA0_EATDQC_TDQD0_Msk (0x1UL) /*!< TDQD0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQD1_Pos (1UL) /*!< TDQD1 (Bit 1) */ + #define R_ETHA0_EATDQC_TDQD1_Msk (0x2UL) /*!< TDQD1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQD2_Pos (2UL) /*!< TDQD2 (Bit 2) */ + #define R_ETHA0_EATDQC_TDQD2_Msk (0x4UL) /*!< TDQD2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQD3_Pos (3UL) /*!< TDQD3 (Bit 3) */ + #define R_ETHA0_EATDQC_TDQD3_Msk (0x8UL) /*!< TDQD3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQD4_Pos (4UL) /*!< TDQD4 (Bit 4) */ + #define R_ETHA0_EATDQC_TDQD4_Msk (0x10UL) /*!< TDQD4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQD5_Pos (5UL) /*!< TDQD5 (Bit 5) */ + #define R_ETHA0_EATDQC_TDQD5_Msk (0x20UL) /*!< TDQD5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQD6_Pos (6UL) /*!< TDQD6 (Bit 6) */ + #define R_ETHA0_EATDQC_TDQD6_Msk (0x40UL) /*!< TDQD6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQD7_Pos (7UL) /*!< TDQD7 (Bit 7) */ + #define R_ETHA0_EATDQC_TDQD7_Msk (0x80UL) /*!< TDQD7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TCTDQD_Pos (8UL) /*!< TCTDQD (Bit 8) */ + #define R_ETHA0_EATDQC_TCTDQD_Msk (0x100UL) /*!< TCTDQD (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP0_Pos (16UL) /*!< TDQP0 (Bit 16) */ + #define R_ETHA0_EATDQC_TDQP0_Msk (0x10000UL) /*!< TDQP0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP1_Pos (17UL) /*!< TDQP1 (Bit 17) */ + #define R_ETHA0_EATDQC_TDQP1_Msk (0x20000UL) /*!< TDQP1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP2_Pos (18UL) /*!< TDQP2 (Bit 18) */ + #define R_ETHA0_EATDQC_TDQP2_Msk (0x40000UL) /*!< TDQP2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP3_Pos (19UL) /*!< TDQP3 (Bit 19) */ + #define R_ETHA0_EATDQC_TDQP3_Msk (0x80000UL) /*!< TDQP3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP4_Pos (20UL) /*!< TDQP4 (Bit 20) */ + #define R_ETHA0_EATDQC_TDQP4_Msk (0x100000UL) /*!< TDQP4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP5_Pos (21UL) /*!< TDQP5 (Bit 21) */ + #define R_ETHA0_EATDQC_TDQP5_Msk (0x200000UL) /*!< TDQP5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP6_Pos (22UL) /*!< TDQP6 (Bit 22) */ + #define R_ETHA0_EATDQC_TDQP6_Msk (0x400000UL) /*!< TDQP6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP7_Pos (23UL) /*!< TDQP7 (Bit 23) */ + #define R_ETHA0_EATDQC_TDQP7_Msk (0x800000UL) /*!< TDQP7 (Bitfield-Mask: 0x01) */ +/* ======================================================== EATDQAC ======================================================== */ + #define R_ETHA0_EATDQAC_TDQA0_Pos (0UL) /*!< TDQA0 (Bit 0) */ + #define R_ETHA0_EATDQAC_TDQA0_Msk (0xfUL) /*!< TDQA0 (Bitfield-Mask: 0x0f) */ + #define R_ETHA0_EATDQAC_TDQA1_Pos (4UL) /*!< TDQA1 (Bit 4) */ + #define R_ETHA0_EATDQAC_TDQA1_Msk (0xf0UL) /*!< TDQA1 (Bitfield-Mask: 0x0f) */ + #define R_ETHA0_EATDQAC_TDQA2_Pos (8UL) /*!< TDQA2 (Bit 8) */ + #define R_ETHA0_EATDQAC_TDQA2_Msk (0xf00UL) /*!< TDQA2 (Bitfield-Mask: 0x0f) */ + #define R_ETHA0_EATDQAC_TDQA3_Pos (12UL) /*!< TDQA3 (Bit 12) */ + #define R_ETHA0_EATDQAC_TDQA3_Msk (0xf000UL) /*!< TDQA3 (Bitfield-Mask: 0x0f) */ + #define R_ETHA0_EATDQAC_TDQA4_Pos (16UL) /*!< TDQA4 (Bit 16) */ + #define R_ETHA0_EATDQAC_TDQA4_Msk (0xf0000UL) /*!< TDQA4 (Bitfield-Mask: 0x0f) */ + #define R_ETHA0_EATDQAC_TDQA5_Pos (20UL) /*!< TDQA5 (Bit 20) */ + #define R_ETHA0_EATDQAC_TDQA5_Msk (0xf00000UL) /*!< TDQA5 (Bitfield-Mask: 0x0f) */ + #define R_ETHA0_EATDQAC_TDQA6_Pos (24UL) /*!< TDQA6 (Bit 24) */ + #define R_ETHA0_EATDQAC_TDQA6_Msk (0xf000000UL) /*!< TDQA6 (Bitfield-Mask: 0x0f) */ + #define R_ETHA0_EATDQAC_TDQA7_Pos (28UL) /*!< TDQA7 (Bit 28) */ + #define R_ETHA0_EATDQAC_TDQA7_Msk (0xf0000000UL) /*!< TDQA7 (Bitfield-Mask: 0x0f) */ +/* ======================================================== EATPEC ========================================================= */ + #define R_ETHA0_EATPEC_TTQ0_Pos (0UL) /*!< TTQ0 (Bit 0) */ + #define R_ETHA0_EATPEC_TTQ0_Msk (0x1UL) /*!< TTQ0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ1_Pos (1UL) /*!< TTQ1 (Bit 1) */ + #define R_ETHA0_EATPEC_TTQ1_Msk (0x2UL) /*!< TTQ1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ2_Pos (2UL) /*!< TTQ2 (Bit 2) */ + #define R_ETHA0_EATPEC_TTQ2_Msk (0x4UL) /*!< TTQ2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ3_Pos (3UL) /*!< TTQ3 (Bit 3) */ + #define R_ETHA0_EATPEC_TTQ3_Msk (0x8UL) /*!< TTQ3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ4_Pos (4UL) /*!< TTQ4 (Bit 4) */ + #define R_ETHA0_EATPEC_TTQ4_Msk (0x10UL) /*!< TTQ4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ5_Pos (5UL) /*!< TTQ5 (Bit 5) */ + #define R_ETHA0_EATPEC_TTQ5_Msk (0x20UL) /*!< TTQ5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ6_Pos (6UL) /*!< TTQ6 (Bit 6) */ + #define R_ETHA0_EATPEC_TTQ6_Msk (0x40UL) /*!< TTQ6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ7_Pos (7UL) /*!< TTQ7 (Bit 7) */ + #define R_ETHA0_EATPEC_TTQ7_Msk (0x80UL) /*!< TTQ7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ8_Pos (8UL) /*!< TTQ8 (Bit 8) */ + #define R_ETHA0_EATPEC_TTQ8_Msk (0x100UL) /*!< TTQ8 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ9_Pos (9UL) /*!< TTQ9 (Bit 9) */ + #define R_ETHA0_EATPEC_TTQ9_Msk (0x200UL) /*!< TTQ9 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_AFS_Pos (16UL) /*!< AFS (Bit 16) */ + #define R_ETHA0_EATPEC_AFS_Msk (0x30000UL) /*!< AFS (Bitfield-Mask: 0x03) */ +/* ======================================================= EATMFSC0 ======================================================== */ + #define R_ETHA0_EATMFSC0_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC0_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATMFSC1 ======================================================== */ + #define R_ETHA0_EATMFSC1_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC1_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATMFSC2 ======================================================== */ + #define R_ETHA0_EATMFSC2_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC2_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATMFSC3 ======================================================== */ + #define R_ETHA0_EATMFSC3_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC3_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATMFSC4 ======================================================== */ + #define R_ETHA0_EATMFSC4_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC4_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATMFSC5 ======================================================== */ + #define R_ETHA0_EATMFSC5_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC5_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATMFSC6 ======================================================== */ + #define R_ETHA0_EATMFSC6_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC6_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATMFSC7 ======================================================== */ + #define R_ETHA0_EATMFSC7_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC7_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATDQDC0 ======================================================== */ + #define R_ETHA0_EATDQDC0_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC0_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQDC1 ======================================================== */ + #define R_ETHA0_EATDQDC1_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC1_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQDC2 ======================================================== */ + #define R_ETHA0_EATDQDC2_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC2_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQDC3 ======================================================== */ + #define R_ETHA0_EATDQDC3_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC3_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQDC4 ======================================================== */ + #define R_ETHA0_EATDQDC4_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC4_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQDC5 ======================================================== */ + #define R_ETHA0_EATDQDC5_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC5_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQDC6 ======================================================== */ + #define R_ETHA0_EATDQDC6_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC6_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQDC7 ======================================================== */ + #define R_ETHA0_EATDQDC7_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC7_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM0 ======================================================== */ + #define R_ETHA0_EATDQM0_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM0_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM1 ======================================================== */ + #define R_ETHA0_EATDQM1_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM1_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM2 ======================================================== */ + #define R_ETHA0_EATDQM2_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM2_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM3 ======================================================== */ + #define R_ETHA0_EATDQM3_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM3_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM4 ======================================================== */ + #define R_ETHA0_EATDQM4_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM4_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM5 ======================================================== */ + #define R_ETHA0_EATDQM5_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM5_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM6 ======================================================== */ + #define R_ETHA0_EATDQM6_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM6_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM7 ======================================================== */ + #define R_ETHA0_EATDQM7_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM7_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM0 ======================================================= */ + #define R_ETHA0_EATDQMLM0_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM0_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM1 ======================================================= */ + #define R_ETHA0_EATDQMLM1_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM1_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM2 ======================================================= */ + #define R_ETHA0_EATDQMLM2_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM2_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM3 ======================================================= */ + #define R_ETHA0_EATDQMLM3_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM3_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM4 ======================================================= */ + #define R_ETHA0_EATDQMLM4_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM4_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM5 ======================================================= */ + #define R_ETHA0_EATDQMLM5_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM5_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM6 ======================================================= */ + #define R_ETHA0_EATDQMLM6_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM6_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM7 ======================================================= */ + #define R_ETHA0_EATDQMLM7_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM7_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EACTQC ========================================================= */ + #define R_ETHA0_EACTQC_CTQD_Pos (0UL) /*!< CTQD (Bit 0) */ + #define R_ETHA0_EACTQC_CTQD_Msk (0xffffUL) /*!< CTQD (Bitfield-Mask: 0xffff) */ +/* ======================================================= EACTDQDC ======================================================== */ + #define R_ETHA0_EACTDQDC_CTDQD_Pos (0UL) /*!< CTDQD (Bit 0) */ + #define R_ETHA0_EACTDQDC_CTDQD_Msk (0xfUL) /*!< CTDQD (Bitfield-Mask: 0x0f) */ +/* ======================================================== EACTDQM ======================================================== */ + #define R_ETHA0_EACTDQM_CTQDN_Pos (0UL) /*!< CTQDN (Bit 0) */ + #define R_ETHA0_EACTDQM_CTQDN_Msk (0x3ffUL) /*!< CTQDN (Bitfield-Mask: 0x3ff) */ +/* ======================================================= EACTDQMLM ======================================================= */ + #define R_ETHA0_EACTDQMLM_CTDMLQ_Pos (0UL) /*!< CTDMLQ (Bit 0) */ + #define R_ETHA0_EACTDQMLM_CTDMLQ_Msk (0xfUL) /*!< CTDMLQ (Bitfield-Mask: 0x0f) */ +/* ========================================================= EAVCC ========================================================= */ + #define R_ETHA0_EAVCC_VIM_Pos (0UL) /*!< VIM (Bit 0) */ + #define R_ETHA0_EAVCC_VIM_Msk (0x1UL) /*!< VIM (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAVCC_VEM_Pos (16UL) /*!< VEM (Bit 16) */ + #define R_ETHA0_EAVCC_VEM_Msk (0x70000UL) /*!< VEM (Bitfield-Mask: 0x07) */ +/* ========================================================= EAVTC ========================================================= */ + #define R_ETHA0_EAVTC_CTV_Pos (0UL) /*!< CTV (Bit 0) */ + #define R_ETHA0_EAVTC_CTV_Msk (0xfffUL) /*!< CTV (Bitfield-Mask: 0xfff) */ + #define R_ETHA0_EAVTC_CTP_Pos (12UL) /*!< CTP (Bit 12) */ + #define R_ETHA0_EAVTC_CTP_Msk (0x7000UL) /*!< CTP (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAVTC_CTD_Pos (15UL) /*!< CTD (Bit 15) */ + #define R_ETHA0_EAVTC_CTD_Msk (0x8000UL) /*!< CTD (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAVTC_STV_Pos (16UL) /*!< STV (Bit 16) */ + #define R_ETHA0_EAVTC_STV_Msk (0xfff0000UL) /*!< STV (Bitfield-Mask: 0xfff) */ + #define R_ETHA0_EAVTC_STP_Pos (28UL) /*!< STP (Bit 28) */ + #define R_ETHA0_EAVTC_STP_Msk (0x70000000UL) /*!< STP (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAVTC_STD_Pos (31UL) /*!< STD (Bit 31) */ + #define R_ETHA0_EAVTC_STD_Msk (0x80000000UL) /*!< STD (Bitfield-Mask: 0x01) */ +/* ======================================================== EARTFC ========================================================= */ + #define R_ETHA0_EARTFC_NT_Pos (0UL) /*!< NT (Bit 0) */ + #define R_ETHA0_EARTFC_NT_Msk (0x1UL) /*!< NT (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_RT_Pos (1UL) /*!< RT (Bit 1) */ + #define R_ETHA0_EARTFC_RT_Msk (0x2UL) /*!< RT (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_CST_Pos (2UL) /*!< CST (Bit 2) */ + #define R_ETHA0_EARTFC_CST_Msk (0x4UL) /*!< CST (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_CSRT_Pos (3UL) /*!< CSRT (Bit 3) */ + #define R_ETHA0_EARTFC_CSRT_Msk (0x8UL) /*!< CSRT (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_CT_Pos (4UL) /*!< CT (Bit 4) */ + #define R_ETHA0_EARTFC_CT_Msk (0x10UL) /*!< CT (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_CRT_Pos (5UL) /*!< CRT (Bit 5) */ + #define R_ETHA0_EARTFC_CRT_Msk (0x20UL) /*!< CRT (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_SCT_Pos (6UL) /*!< SCT (Bit 6) */ + #define R_ETHA0_EARTFC_SCT_Msk (0x40UL) /*!< SCT (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_SCRT_Pos (7UL) /*!< SCRT (Bit 7) */ + #define R_ETHA0_EARTFC_SCRT_Msk (0x80UL) /*!< SCRT (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_UT_Pos (8UL) /*!< UT (Bit 8) */ + #define R_ETHA0_EARTFC_UT_Msk (0x100UL) /*!< UT (Bitfield-Mask: 0x01) */ +/* ======================================================== EACAEC ========================================================= */ + #define R_ETHA0_EACAEC_CE0_Pos (0UL) /*!< CE0 (Bit 0) */ + #define R_ETHA0_EACAEC_CE0_Msk (0x1UL) /*!< CE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACAEC_CE1_Pos (1UL) /*!< CE1 (Bit 1) */ + #define R_ETHA0_EACAEC_CE1_Msk (0x2UL) /*!< CE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACAEC_CE2_Pos (2UL) /*!< CE2 (Bit 2) */ + #define R_ETHA0_EACAEC_CE2_Msk (0x4UL) /*!< CE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACAEC_CE3_Pos (3UL) /*!< CE3 (Bit 3) */ + #define R_ETHA0_EACAEC_CE3_Msk (0x8UL) /*!< CE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACAEC_CE4_Pos (4UL) /*!< CE4 (Bit 4) */ + #define R_ETHA0_EACAEC_CE4_Msk (0x10UL) /*!< CE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACAEC_CE5_Pos (5UL) /*!< CE5 (Bit 5) */ + #define R_ETHA0_EACAEC_CE5_Msk (0x20UL) /*!< CE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACAEC_CE6_Pos (6UL) /*!< CE6 (Bit 6) */ + #define R_ETHA0_EACAEC_CE6_Msk (0x40UL) /*!< CE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACAEC_CE7_Pos (7UL) /*!< CE7 (Bit 7) */ + #define R_ETHA0_EACAEC_CE7_Msk (0x80UL) /*!< CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= EACC ========================================================== */ + #define R_ETHA0_EACC_CC0_Pos (0UL) /*!< CC0 (Bit 0) */ + #define R_ETHA0_EACC_CC0_Msk (0x1UL) /*!< CC0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACC_CC1_Pos (1UL) /*!< CC1 (Bit 1) */ + #define R_ETHA0_EACC_CC1_Msk (0x2UL) /*!< CC1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACC_CC2_Pos (2UL) /*!< CC2 (Bit 2) */ + #define R_ETHA0_EACC_CC2_Msk (0x4UL) /*!< CC2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACC_CC3_Pos (3UL) /*!< CC3 (Bit 3) */ + #define R_ETHA0_EACC_CC3_Msk (0x8UL) /*!< CC3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACC_CC4_Pos (4UL) /*!< CC4 (Bit 4) */ + #define R_ETHA0_EACC_CC4_Msk (0x10UL) /*!< CC4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACC_CC5_Pos (5UL) /*!< CC5 (Bit 5) */ + #define R_ETHA0_EACC_CC5_Msk (0x20UL) /*!< CC5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACC_CC6_Pos (6UL) /*!< CC6 (Bit 6) */ + #define R_ETHA0_EACC_CC6_Msk (0x40UL) /*!< CC6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACC_CC7_Pos (7UL) /*!< CC7 (Bit 7) */ + #define R_ETHA0_EACC_CC7_Msk (0x80UL) /*!< CC7 (Bitfield-Mask: 0x01) */ +/* ======================================================= EACAIVC0 ======================================================== */ + #define R_ETHA0_EACAIVC0_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC0_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAIVC1 ======================================================== */ + #define R_ETHA0_EACAIVC1_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC1_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAIVC2 ======================================================== */ + #define R_ETHA0_EACAIVC2_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC2_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAIVC3 ======================================================== */ + #define R_ETHA0_EACAIVC3_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC3_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAIVC4 ======================================================== */ + #define R_ETHA0_EACAIVC4_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC4_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAIVC5 ======================================================== */ + #define R_ETHA0_EACAIVC5_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC5_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAIVC6 ======================================================== */ + #define R_ETHA0_EACAIVC6_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC6_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAIVC7 ======================================================== */ + #define R_ETHA0_EACAIVC7_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC7_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAULC0 ======================================================== */ + #define R_ETHA0_EACAULC0_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC0_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACAULC1 ======================================================== */ + #define R_ETHA0_EACAULC1_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC1_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACAULC2 ======================================================== */ + #define R_ETHA0_EACAULC2_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC2_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACAULC3 ======================================================== */ + #define R_ETHA0_EACAULC3_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC3_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACAULC4 ======================================================== */ + #define R_ETHA0_EACAULC4_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC4_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACAULC5 ======================================================== */ + #define R_ETHA0_EACAULC5_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC5_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACAULC6 ======================================================== */ + #define R_ETHA0_EACAULC6_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC6_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACAULC7 ======================================================== */ + #define R_ETHA0_EACAULC7_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC7_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================== EACOEM ========================================================= */ + #define R_ETHA0_EACOEM_CE0_Pos (0UL) /*!< CE0 (Bit 0) */ + #define R_ETHA0_EACOEM_CE0_Msk (0x1UL) /*!< CE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACOEM_CE1_Pos (1UL) /*!< CE1 (Bit 1) */ + #define R_ETHA0_EACOEM_CE1_Msk (0x2UL) /*!< CE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACOEM_CE2_Pos (2UL) /*!< CE2 (Bit 2) */ + #define R_ETHA0_EACOEM_CE2_Msk (0x4UL) /*!< CE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACOEM_CE3_Pos (3UL) /*!< CE3 (Bit 3) */ + #define R_ETHA0_EACOEM_CE3_Msk (0x8UL) /*!< CE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACOEM_CE4_Pos (4UL) /*!< CE4 (Bit 4) */ + #define R_ETHA0_EACOEM_CE4_Msk (0x10UL) /*!< CE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACOEM_CE5_Pos (5UL) /*!< CE5 (Bit 5) */ + #define R_ETHA0_EACOEM_CE5_Msk (0x20UL) /*!< CE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACOEM_CE6_Pos (6UL) /*!< CE6 (Bit 6) */ + #define R_ETHA0_EACOEM_CE6_Msk (0x40UL) /*!< CE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACOEM_CE7_Pos (7UL) /*!< CE7 (Bit 7) */ + #define R_ETHA0_EACOEM_CE7_Msk (0x80UL) /*!< CE7 (Bitfield-Mask: 0x01) */ +/* ======================================================= EACOIVM0 ======================================================== */ + #define R_ETHA0_EACOIVM0_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM0_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOIVM1 ======================================================== */ + #define R_ETHA0_EACOIVM1_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM1_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOIVM2 ======================================================== */ + #define R_ETHA0_EACOIVM2_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM2_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOIVM3 ======================================================== */ + #define R_ETHA0_EACOIVM3_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM3_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOIVM4 ======================================================== */ + #define R_ETHA0_EACOIVM4_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM4_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOIVM5 ======================================================== */ + #define R_ETHA0_EACOIVM5_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM5_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOIVM6 ======================================================== */ + #define R_ETHA0_EACOIVM6_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM6_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOIVM7 ======================================================== */ + #define R_ETHA0_EACOIVM7_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM7_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOULM0 ======================================================== */ + #define R_ETHA0_EACOULM0_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM0_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACOULM1 ======================================================== */ + #define R_ETHA0_EACOULM1_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM1_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACOULM2 ======================================================== */ + #define R_ETHA0_EACOULM2_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM2_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACOULM3 ======================================================== */ + #define R_ETHA0_EACOULM3_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM3_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACOULM4 ======================================================== */ + #define R_ETHA0_EACOULM4_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM4_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACOULM5 ======================================================== */ + #define R_ETHA0_EACOULM5_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM5_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACOULM6 ======================================================== */ + #define R_ETHA0_EACOULM6_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM6_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACOULM7 ======================================================== */ + #define R_ETHA0_EACOULM7_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM7_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================== EACGSM ========================================================= */ + #define R_ETHA0_EACGSM_CGS0_Pos (0UL) /*!< CGS0 (Bit 0) */ + #define R_ETHA0_EACGSM_CGS0_Msk (0x1UL) /*!< CGS0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACGSM_CGS1_Pos (1UL) /*!< CGS1 (Bit 1) */ + #define R_ETHA0_EACGSM_CGS1_Msk (0x2UL) /*!< CGS1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACGSM_CGS2_Pos (2UL) /*!< CGS2 (Bit 2) */ + #define R_ETHA0_EACGSM_CGS2_Msk (0x4UL) /*!< CGS2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACGSM_CGS3_Pos (3UL) /*!< CGS3 (Bit 3) */ + #define R_ETHA0_EACGSM_CGS3_Msk (0x8UL) /*!< CGS3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACGSM_CGS4_Pos (4UL) /*!< CGS4 (Bit 4) */ + #define R_ETHA0_EACGSM_CGS4_Msk (0x10UL) /*!< CGS4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACGSM_CGS5_Pos (5UL) /*!< CGS5 (Bit 5) */ + #define R_ETHA0_EACGSM_CGS5_Msk (0x20UL) /*!< CGS5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACGSM_CGS6_Pos (6UL) /*!< CGS6 (Bit 6) */ + #define R_ETHA0_EACGSM_CGS6_Msk (0x40UL) /*!< CGS6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACGSM_CGS7_Pos (7UL) /*!< CGS7 (Bit 7) */ + #define R_ETHA0_EACGSM_CGS7_Msk (0x80UL) /*!< CGS7 (Bitfield-Mask: 0x01) */ +/* ======================================================== EATASC ========================================================= */ + #define R_ETHA0_EATASC_TASE_Pos (0UL) /*!< TASE (Bit 0) */ + #define R_ETHA0_EATASC_TASE_Msk (0x1UL) /*!< TASE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASC_TASCC_Pos (1UL) /*!< TASCC (Bit 1) */ + #define R_ETHA0_EATASC_TASCC_Msk (0x2UL) /*!< TASCC (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASC_TASCI_Pos (2UL) /*!< TASCI (Bit 2) */ + #define R_ETHA0_EATASC_TASCI_Msk (0x4UL) /*!< TASCI (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASC_TASTS_Pos (8UL) /*!< TASTS (Bit 8) */ + #define R_ETHA0_EATASC_TASTS_Msk (0x100UL) /*!< TASTS (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASC_TASCA_Pos (16UL) /*!< TASCA (Bit 16) */ + #define R_ETHA0_EATASC_TASCA_Msk (0xff0000UL) /*!< TASCA (Bitfield-Mask: 0xff) */ +/* ======================================================= EATASIGSC ======================================================= */ + #define R_ETHA0_EATASIGSC_TASIGS0_Pos (0UL) /*!< TASIGS0 (Bit 0) */ + #define R_ETHA0_EATASIGSC_TASIGS0_Msk (0x1UL) /*!< TASIGS0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASIGS1_Pos (1UL) /*!< TASIGS1 (Bit 1) */ + #define R_ETHA0_EATASIGSC_TASIGS1_Msk (0x2UL) /*!< TASIGS1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASIGS2_Pos (2UL) /*!< TASIGS2 (Bit 2) */ + #define R_ETHA0_EATASIGSC_TASIGS2_Msk (0x4UL) /*!< TASIGS2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASIGS3_Pos (3UL) /*!< TASIGS3 (Bit 3) */ + #define R_ETHA0_EATASIGSC_TASIGS3_Msk (0x8UL) /*!< TASIGS3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASIGS4_Pos (4UL) /*!< TASIGS4 (Bit 4) */ + #define R_ETHA0_EATASIGSC_TASIGS4_Msk (0x10UL) /*!< TASIGS4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASIGS5_Pos (5UL) /*!< TASIGS5 (Bit 5) */ + #define R_ETHA0_EATASIGSC_TASIGS5_Msk (0x20UL) /*!< TASIGS5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASIGS6_Pos (6UL) /*!< TASIGS6 (Bit 6) */ + #define R_ETHA0_EATASIGSC_TASIGS6_Msk (0x40UL) /*!< TASIGS6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASIGS7_Pos (7UL) /*!< TASIGS7 (Bit 7) */ + #define R_ETHA0_EATASIGSC_TASIGS7_Msk (0x80UL) /*!< TASIGS7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASCTIGS_Pos (8UL) /*!< TASCTIGS (Bit 8) */ + #define R_ETHA0_EATASIGSC_TASCTIGS_Msk (0x100UL) /*!< TASCTIGS (Bitfield-Mask: 0x01) */ +/* ======================================================= EATASENC0 ======================================================= */ + #define R_ETHA0_EATASENC0_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC0_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENC1 ======================================================= */ + #define R_ETHA0_EATASENC1_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC1_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENC2 ======================================================= */ + #define R_ETHA0_EATASENC2_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC2_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENC3 ======================================================= */ + #define R_ETHA0_EATASENC3_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC3_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENC4 ======================================================= */ + #define R_ETHA0_EATASENC4_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC4_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENC5 ======================================================= */ + #define R_ETHA0_EATASENC5_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC5_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENC6 ======================================================= */ + #define R_ETHA0_EATASENC6_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC6_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENC7 ======================================================= */ + #define R_ETHA0_EATASENC7_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC7_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ====================================================== EATASCTENC ======================================================= */ + #define R_ETHA0_EATASCTENC_TASCTAEN_Pos (0UL) /*!< TASCTAEN (Bit 0) */ + #define R_ETHA0_EATASCTENC_TASCTAEN_Msk (0x1ffUL) /*!< TASCTAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM0 ======================================================= */ + #define R_ETHA0_EATASENM0_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM0_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM1 ======================================================= */ + #define R_ETHA0_EATASENM1_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM1_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM2 ======================================================= */ + #define R_ETHA0_EATASENM2_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM2_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM3 ======================================================= */ + #define R_ETHA0_EATASENM3_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM3_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM4 ======================================================= */ + #define R_ETHA0_EATASENM4_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM4_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM5 ======================================================= */ + #define R_ETHA0_EATASENM5_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM5_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM6 ======================================================= */ + #define R_ETHA0_EATASENM6_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM6_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM7 ======================================================= */ + #define R_ETHA0_EATASENM7_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM7_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ====================================================== EATASCTENM ======================================================= */ + #define R_ETHA0_EATASCTENM_TASCTOEN_Pos (0UL) /*!< TASCTOEN (Bit 0) */ + #define R_ETHA0_EATASCTENM_TASCTOEN_Msk (0x1ffUL) /*!< TASCTOEN (Bitfield-Mask: 0x1ff) */ +/* ====================================================== EATASCSTC0 ======================================================= */ + #define R_ETHA0_EATASCSTC0_TASACSTP0_Pos (0UL) /*!< TASACSTP0 (Bit 0) */ + #define R_ETHA0_EATASCSTC0_TASACSTP0_Msk (0xffffffffUL) /*!< TASACSTP0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== EATASCSTC1 ======================================================= */ + #define R_ETHA0_EATASCSTC1_TASACSTP1_Pos (0UL) /*!< TASACSTP1 (Bit 0) */ + #define R_ETHA0_EATASCSTC1_TASACSTP1_Msk (0xffffffffUL) /*!< TASACSTP1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== EATASCSTM0 ======================================================= */ + #define R_ETHA0_EATASCSTM0_TASOCSTP0_Pos (0UL) /*!< TASOCSTP0 (Bit 0) */ + #define R_ETHA0_EATASCSTM0_TASOCSTP0_Msk (0xffffffffUL) /*!< TASOCSTP0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== EATASCSTM1 ======================================================= */ + #define R_ETHA0_EATASCSTM1_TASOCSTP1_Pos (0UL) /*!< TASOCSTP1 (Bit 0) */ + #define R_ETHA0_EATASCSTM1_TASOCSTP1_Msk (0xffffffffUL) /*!< TASOCSTP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EATASCTC ======================================================== */ + #define R_ETHA0_EATASCTC_TASACT_Pos (0UL) /*!< TASACT (Bit 0) */ + #define R_ETHA0_EATASCTC_TASACT_Msk (0xffffffffUL) /*!< TASACT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EATASCTM ======================================================== */ + #define R_ETHA0_EATASCTM_TASOCT_Pos (0UL) /*!< TASOCT (Bit 0) */ + #define R_ETHA0_EATASCTM_TASOCT_Msk (0xffffffffUL) /*!< TASOCT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EATASGL0 ======================================================== */ + #define R_ETHA0_EATASGL0_TASGAL_Pos (0UL) /*!< TASGAL (Bit 0) */ + #define R_ETHA0_EATASGL0_TASGAL_Msk (0xffUL) /*!< TASGAL (Bitfield-Mask: 0xff) */ +/* ======================================================= EATASGL1 ======================================================== */ + #define R_ETHA0_EATASGL1_TASGTL_Pos (0UL) /*!< TASGTL (Bit 0) */ + #define R_ETHA0_EATASGL1_TASGTL_Msk (0xfffffffUL) /*!< TASGTL (Bitfield-Mask: 0xfffffff) */ + #define R_ETHA0_EATASGL1_TASGSL_Pos (28UL) /*!< TASGSL (Bit 28) */ + #define R_ETHA0_EATASGL1_TASGSL_Msk (0x10000000UL) /*!< TASGSL (Bitfield-Mask: 0x01) */ +/* ======================================================= EATASGLR ======================================================== */ + #define R_ETHA0_EATASGLR_GL_Pos (31UL) /*!< GL (Bit 31) */ + #define R_ETHA0_EATASGLR_GL_Msk (0x80000000UL) /*!< GL (Bitfield-Mask: 0x01) */ +/* ======================================================== EATASGR ======================================================== */ + #define R_ETHA0_EATASGR_TASGAR_Pos (0UL) /*!< TASGAR (Bit 0) */ + #define R_ETHA0_EATASGR_TASGAR_Msk (0xffUL) /*!< TASGAR (Bitfield-Mask: 0xff) */ +/* ======================================================= EATASGRR ======================================================== */ + #define R_ETHA0_EATASGRR_TASGTR_Pos (0UL) /*!< TASGTR (Bit 0) */ + #define R_ETHA0_EATASGRR_TASGTR_Msk (0xfffffffUL) /*!< TASGTR (Bitfield-Mask: 0xfffffff) */ + #define R_ETHA0_EATASGRR_TASGSR_Pos (28UL) /*!< TASGSR (Bit 28) */ + #define R_ETHA0_EATASGRR_TASGSR_Msk (0x10000000UL) /*!< TASGSR (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASGRR_TASREF_Pos (29UL) /*!< TASREF (Bit 29) */ + #define R_ETHA0_EATASGRR_TASREF_Msk (0x20000000UL) /*!< TASREF (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASGRR_GR_Pos (31UL) /*!< GR (Bit 31) */ + #define R_ETHA0_EATASGRR_GR_Msk (0x80000000UL) /*!< GR (Bitfield-Mask: 0x01) */ +/* ======================================================= EATASHCC ======================================================== */ + #define R_ETHA0_EATASHCC_TASJ_Pos (0UL) /*!< TASJ (Bit 0) */ + #define R_ETHA0_EATASHCC_TASJ_Msk (0xffffUL) /*!< TASJ (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATASRIRM ======================================================= */ + #define R_ETHA0_EATASRIRM_TASRIOG_Pos (0UL) /*!< TASRIOG (Bit 0) */ + #define R_ETHA0_EATASRIRM_TASRIOG_Msk (0x1UL) /*!< TASRIOG (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASRIRM_TASRR_Pos (1UL) /*!< TASRR (Bit 1) */ + #define R_ETHA0_EATASRIRM_TASRR_Msk (0x2UL) /*!< TASRR (Bitfield-Mask: 0x01) */ +/* ======================================================== EATASSM ======================================================== */ + #define R_ETHA0_EATASSM_TASGS0_Pos (0UL) /*!< TASGS0 (Bit 0) */ + #define R_ETHA0_EATASSM_TASGS0_Msk (0x1UL) /*!< TASGS0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASGS1_Pos (1UL) /*!< TASGS1 (Bit 1) */ + #define R_ETHA0_EATASSM_TASGS1_Msk (0x2UL) /*!< TASGS1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASGS2_Pos (2UL) /*!< TASGS2 (Bit 2) */ + #define R_ETHA0_EATASSM_TASGS2_Msk (0x4UL) /*!< TASGS2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASGS3_Pos (3UL) /*!< TASGS3 (Bit 3) */ + #define R_ETHA0_EATASSM_TASGS3_Msk (0x8UL) /*!< TASGS3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASGS4_Pos (4UL) /*!< TASGS4 (Bit 4) */ + #define R_ETHA0_EATASSM_TASGS4_Msk (0x10UL) /*!< TASGS4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASGS5_Pos (5UL) /*!< TASGS5 (Bit 5) */ + #define R_ETHA0_EATASSM_TASGS5_Msk (0x20UL) /*!< TASGS5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASGS6_Pos (6UL) /*!< TASGS6 (Bit 6) */ + #define R_ETHA0_EATASSM_TASGS6_Msk (0x40UL) /*!< TASGS6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASGS7_Pos (7UL) /*!< TASGS7 (Bit 7) */ + #define R_ETHA0_EATASSM_TASGS7_Msk (0x80UL) /*!< TASGS7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASCTGS_Pos (8UL) /*!< TASCTGS (Bit 8) */ + #define R_ETHA0_EATASSM_TASCTGS_Msk (0x100UL) /*!< TASCTGS (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASSO_Pos (16UL) /*!< TASSO (Bit 16) */ + #define R_ETHA0_EATASSM_TASSO_Msk (0x10000UL) /*!< TASSO (Bitfield-Mask: 0x01) */ +/* ====================================================== EAUSMFSECN ======================================================= */ + #define R_ETHA0_EAUSMFSECN_USMFSEN_Pos (0UL) /*!< USMFSEN (Bit 0) */ + #define R_ETHA0_EAUSMFSECN_USMFSEN_Msk (0xffffUL) /*!< USMFSEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== EATFECN ======================================================== */ + #define R_ETHA0_EATFECN_TFEN_Pos (0UL) /*!< TFEN (Bit 0) */ + #define R_ETHA0_EATFECN_TFEN_Msk (0xffffUL) /*!< TFEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== EAFSECN ======================================================== */ + #define R_ETHA0_EAFSECN_FSEN_Pos (0UL) /*!< FSEN (Bit 0) */ + #define R_ETHA0_EAFSECN_FSEN_Msk (0xffffUL) /*!< FSEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= EADQOECN ======================================================== */ + #define R_ETHA0_EADQOECN_DQOEN_Pos (0UL) /*!< DQOEN (Bit 0) */ + #define R_ETHA0_EADQOECN_DQOEN_Msk (0xffffUL) /*!< DQOEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= EADQSECN ======================================================== */ + #define R_ETHA0_EADQSECN_DQSEN_Pos (0UL) /*!< DQSEN (Bit 0) */ + #define R_ETHA0_EADQSECN_DQSEN_Msk (0xffffUL) /*!< DQSEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== EAEIS0 ========================================================= */ + #define R_ETHA0_EAEIS0_DECCES_Pos (0UL) /*!< DECCES (Bit 0) */ + #define R_ETHA0_EAEIS0_DECCES_Msk (0x1UL) /*!< DECCES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TECCES_Pos (1UL) /*!< TECCES (Bit 1) */ + #define R_ETHA0_EAEIS0_TECCES_Msk (0x2UL) /*!< TECCES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_PECCES_Pos (2UL) /*!< PECCES (Bit 2) */ + #define R_ETHA0_EAEIS0_PECCES_Msk (0x4UL) /*!< PECCES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_DSECCES_Pos (3UL) /*!< DSECCES (Bit 3) */ + #define R_ETHA0_EAEIS0_DSECCES_Msk (0x8UL) /*!< DSECCES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_L23UECCES_Pos (4UL) /*!< L23UECCES (Bit 4) */ + #define R_ETHA0_EAEIS0_L23UECCES_Msk (0x10UL) /*!< L23UECCES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_USMFSES_Pos (5UL) /*!< USMFSES (Bit 5) */ + #define R_ETHA0_EAEIS0_USMFSES_Msk (0x20UL) /*!< USMFSES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TFES_Pos (6UL) /*!< TFES (Bit 6) */ + #define R_ETHA0_EAEIS0_TFES_Msk (0x40UL) /*!< TFES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES0_Pos (8UL) /*!< FSES0 (Bit 8) */ + #define R_ETHA0_EAEIS0_FSES0_Msk (0x100UL) /*!< FSES0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES1_Pos (9UL) /*!< FSES1 (Bit 9) */ + #define R_ETHA0_EAEIS0_FSES1_Msk (0x200UL) /*!< FSES1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES2_Pos (10UL) /*!< FSES2 (Bit 10) */ + #define R_ETHA0_EAEIS0_FSES2_Msk (0x400UL) /*!< FSES2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES3_Pos (11UL) /*!< FSES3 (Bit 11) */ + #define R_ETHA0_EAEIS0_FSES3_Msk (0x800UL) /*!< FSES3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES4_Pos (12UL) /*!< FSES4 (Bit 12) */ + #define R_ETHA0_EAEIS0_FSES4_Msk (0x1000UL) /*!< FSES4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES5_Pos (13UL) /*!< FSES5 (Bit 13) */ + #define R_ETHA0_EAEIS0_FSES5_Msk (0x2000UL) /*!< FSES5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES6_Pos (14UL) /*!< FSES6 (Bit 14) */ + #define R_ETHA0_EAEIS0_FSES6_Msk (0x4000UL) /*!< FSES6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES7_Pos (15UL) /*!< FSES7 (Bit 15) */ + #define R_ETHA0_EAEIS0_FSES7_Msk (0x8000UL) /*!< FSES7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES0_Pos (16UL) /*!< TASGEES0 (Bit 16) */ + #define R_ETHA0_EAEIS0_TASGEES0_Msk (0x10000UL) /*!< TASGEES0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES1_Pos (17UL) /*!< TASGEES1 (Bit 17) */ + #define R_ETHA0_EAEIS0_TASGEES1_Msk (0x20000UL) /*!< TASGEES1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES2_Pos (18UL) /*!< TASGEES2 (Bit 18) */ + #define R_ETHA0_EAEIS0_TASGEES2_Msk (0x40000UL) /*!< TASGEES2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES3_Pos (19UL) /*!< TASGEES3 (Bit 19) */ + #define R_ETHA0_EAEIS0_TASGEES3_Msk (0x80000UL) /*!< TASGEES3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES4_Pos (20UL) /*!< TASGEES4 (Bit 20) */ + #define R_ETHA0_EAEIS0_TASGEES4_Msk (0x100000UL) /*!< TASGEES4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES5_Pos (21UL) /*!< TASGEES5 (Bit 21) */ + #define R_ETHA0_EAEIS0_TASGEES5_Msk (0x200000UL) /*!< TASGEES5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES6_Pos (22UL) /*!< TASGEES6 (Bit 22) */ + #define R_ETHA0_EAEIS0_TASGEES6_Msk (0x400000UL) /*!< TASGEES6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES7_Pos (23UL) /*!< TASGEES7 (Bit 23) */ + #define R_ETHA0_EAEIS0_TASGEES7_Msk (0x800000UL) /*!< TASGEES7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASCTGEES_Pos (24UL) /*!< TASCTGEES (Bit 24) */ + #define R_ETHA0_EAEIS0_TASCTGEES_Msk (0x1000000UL) /*!< TASCTGEES (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEIE0 ========================================================= */ + #define R_ETHA0_EAEIE0_DECCEE_Pos (0UL) /*!< DECCEE (Bit 0) */ + #define R_ETHA0_EAEIE0_DECCEE_Msk (0x1UL) /*!< DECCEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TECCEE_Pos (1UL) /*!< TECCEE (Bit 1) */ + #define R_ETHA0_EAEIE0_TECCEE_Msk (0x2UL) /*!< TECCEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_PECCEE_Pos (2UL) /*!< PECCEE (Bit 2) */ + #define R_ETHA0_EAEIE0_PECCEE_Msk (0x4UL) /*!< PECCEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_DSECCEE_Pos (3UL) /*!< DSECCEE (Bit 3) */ + #define R_ETHA0_EAEIE0_DSECCEE_Msk (0x8UL) /*!< DSECCEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_L23UECCEE_Pos (4UL) /*!< L23UECCEE (Bit 4) */ + #define R_ETHA0_EAEIE0_L23UECCEE_Msk (0x10UL) /*!< L23UECCEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_USMFSEE_Pos (5UL) /*!< USMFSEE (Bit 5) */ + #define R_ETHA0_EAEIE0_USMFSEE_Msk (0x20UL) /*!< USMFSEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TFEE_Pos (6UL) /*!< TFEE (Bit 6) */ + #define R_ETHA0_EAEIE0_TFEE_Msk (0x40UL) /*!< TFEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE0_Pos (8UL) /*!< FSEE0 (Bit 8) */ + #define R_ETHA0_EAEIE0_FSEE0_Msk (0x100UL) /*!< FSEE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE1_Pos (9UL) /*!< FSEE1 (Bit 9) */ + #define R_ETHA0_EAEIE0_FSEE1_Msk (0x200UL) /*!< FSEE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE2_Pos (10UL) /*!< FSEE2 (Bit 10) */ + #define R_ETHA0_EAEIE0_FSEE2_Msk (0x400UL) /*!< FSEE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE3_Pos (11UL) /*!< FSEE3 (Bit 11) */ + #define R_ETHA0_EAEIE0_FSEE3_Msk (0x800UL) /*!< FSEE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE4_Pos (12UL) /*!< FSEE4 (Bit 12) */ + #define R_ETHA0_EAEIE0_FSEE4_Msk (0x1000UL) /*!< FSEE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE5_Pos (13UL) /*!< FSEE5 (Bit 13) */ + #define R_ETHA0_EAEIE0_FSEE5_Msk (0x2000UL) /*!< FSEE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE6_Pos (14UL) /*!< FSEE6 (Bit 14) */ + #define R_ETHA0_EAEIE0_FSEE6_Msk (0x4000UL) /*!< FSEE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE7_Pos (15UL) /*!< FSEE7 (Bit 15) */ + #define R_ETHA0_EAEIE0_FSEE7_Msk (0x8000UL) /*!< FSEE7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE0_Pos (16UL) /*!< TASGEEE0 (Bit 16) */ + #define R_ETHA0_EAEIE0_TASGEEE0_Msk (0x10000UL) /*!< TASGEEE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE1_Pos (17UL) /*!< TASGEEE1 (Bit 17) */ + #define R_ETHA0_EAEIE0_TASGEEE1_Msk (0x20000UL) /*!< TASGEEE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE2_Pos (18UL) /*!< TASGEEE2 (Bit 18) */ + #define R_ETHA0_EAEIE0_TASGEEE2_Msk (0x40000UL) /*!< TASGEEE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE3_Pos (19UL) /*!< TASGEEE3 (Bit 19) */ + #define R_ETHA0_EAEIE0_TASGEEE3_Msk (0x80000UL) /*!< TASGEEE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE4_Pos (20UL) /*!< TASGEEE4 (Bit 20) */ + #define R_ETHA0_EAEIE0_TASGEEE4_Msk (0x100000UL) /*!< TASGEEE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE5_Pos (21UL) /*!< TASGEEE5 (Bit 21) */ + #define R_ETHA0_EAEIE0_TASGEEE5_Msk (0x200000UL) /*!< TASGEEE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE6_Pos (22UL) /*!< TASGEEE6 (Bit 22) */ + #define R_ETHA0_EAEIE0_TASGEEE6_Msk (0x400000UL) /*!< TASGEEE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE7_Pos (23UL) /*!< TASGEEE7 (Bit 23) */ + #define R_ETHA0_EAEIE0_TASGEEE7_Msk (0x800000UL) /*!< TASGEEE7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASCTGEEE_Pos (24UL) /*!< TASCTGEEE (Bit 24) */ + #define R_ETHA0_EAEIE0_TASCTGEEE_Msk (0x1000000UL) /*!< TASCTGEEE (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEID0 ========================================================= */ + #define R_ETHA0_EAEID0_DECCED_Pos (0UL) /*!< DECCED (Bit 0) */ + #define R_ETHA0_EAEID0_DECCED_Msk (0x1UL) /*!< DECCED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TECCED_Pos (1UL) /*!< TECCED (Bit 1) */ + #define R_ETHA0_EAEID0_TECCED_Msk (0x2UL) /*!< TECCED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_PECCED_Pos (2UL) /*!< PECCED (Bit 2) */ + #define R_ETHA0_EAEID0_PECCED_Msk (0x4UL) /*!< PECCED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_DSECCED_Pos (3UL) /*!< DSECCED (Bit 3) */ + #define R_ETHA0_EAEID0_DSECCED_Msk (0x8UL) /*!< DSECCED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_L23UECCED_Pos (4UL) /*!< L23UECCED (Bit 4) */ + #define R_ETHA0_EAEID0_L23UECCED_Msk (0x10UL) /*!< L23UECCED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_USMFSED_Pos (5UL) /*!< USMFSED (Bit 5) */ + #define R_ETHA0_EAEID0_USMFSED_Msk (0x20UL) /*!< USMFSED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TFED_Pos (6UL) /*!< TFED (Bit 6) */ + #define R_ETHA0_EAEID0_TFED_Msk (0x40UL) /*!< TFED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED0_Pos (8UL) /*!< FSED0 (Bit 8) */ + #define R_ETHA0_EAEID0_FSED0_Msk (0x100UL) /*!< FSED0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED1_Pos (9UL) /*!< FSED1 (Bit 9) */ + #define R_ETHA0_EAEID0_FSED1_Msk (0x200UL) /*!< FSED1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED2_Pos (10UL) /*!< FSED2 (Bit 10) */ + #define R_ETHA0_EAEID0_FSED2_Msk (0x400UL) /*!< FSED2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED3_Pos (11UL) /*!< FSED3 (Bit 11) */ + #define R_ETHA0_EAEID0_FSED3_Msk (0x800UL) /*!< FSED3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED4_Pos (12UL) /*!< FSED4 (Bit 12) */ + #define R_ETHA0_EAEID0_FSED4_Msk (0x1000UL) /*!< FSED4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED5_Pos (13UL) /*!< FSED5 (Bit 13) */ + #define R_ETHA0_EAEID0_FSED5_Msk (0x2000UL) /*!< FSED5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED6_Pos (14UL) /*!< FSED6 (Bit 14) */ + #define R_ETHA0_EAEID0_FSED6_Msk (0x4000UL) /*!< FSED6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED7_Pos (15UL) /*!< FSED7 (Bit 15) */ + #define R_ETHA0_EAEID0_FSED7_Msk (0x8000UL) /*!< FSED7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED0_Pos (16UL) /*!< TASGEED0 (Bit 16) */ + #define R_ETHA0_EAEID0_TASGEED0_Msk (0x10000UL) /*!< TASGEED0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED1_Pos (17UL) /*!< TASGEED1 (Bit 17) */ + #define R_ETHA0_EAEID0_TASGEED1_Msk (0x20000UL) /*!< TASGEED1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED2_Pos (18UL) /*!< TASGEED2 (Bit 18) */ + #define R_ETHA0_EAEID0_TASGEED2_Msk (0x40000UL) /*!< TASGEED2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED3_Pos (19UL) /*!< TASGEED3 (Bit 19) */ + #define R_ETHA0_EAEID0_TASGEED3_Msk (0x80000UL) /*!< TASGEED3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED4_Pos (20UL) /*!< TASGEED4 (Bit 20) */ + #define R_ETHA0_EAEID0_TASGEED4_Msk (0x100000UL) /*!< TASGEED4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED5_Pos (21UL) /*!< TASGEED5 (Bit 21) */ + #define R_ETHA0_EAEID0_TASGEED5_Msk (0x200000UL) /*!< TASGEED5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED6_Pos (22UL) /*!< TASGEED6 (Bit 22) */ + #define R_ETHA0_EAEID0_TASGEED6_Msk (0x400000UL) /*!< TASGEED6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED7_Pos (23UL) /*!< TASGEED7 (Bit 23) */ + #define R_ETHA0_EAEID0_TASGEED7_Msk (0x800000UL) /*!< TASGEED7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASCTGEED_Pos (24UL) /*!< TASCTGEED (Bit 24) */ + #define R_ETHA0_EAEID0_TASCTGEED_Msk (0x1000000UL) /*!< TASCTGEED (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEIS1 ========================================================= */ + #define R_ETHA0_EAEIS1_CULES0_Pos (0UL) /*!< CULES0 (Bit 0) */ + #define R_ETHA0_EAEIS1_CULES0_Msk (0x1UL) /*!< CULES0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_CULES1_Pos (1UL) /*!< CULES1 (Bit 1) */ + #define R_ETHA0_EAEIS1_CULES1_Msk (0x2UL) /*!< CULES1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_CULES2_Pos (2UL) /*!< CULES2 (Bit 2) */ + #define R_ETHA0_EAEIS1_CULES2_Msk (0x4UL) /*!< CULES2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_CULES3_Pos (3UL) /*!< CULES3 (Bit 3) */ + #define R_ETHA0_EAEIS1_CULES3_Msk (0x8UL) /*!< CULES3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_CULES4_Pos (4UL) /*!< CULES4 (Bit 4) */ + #define R_ETHA0_EAEIS1_CULES4_Msk (0x10UL) /*!< CULES4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_CULES5_Pos (5UL) /*!< CULES5 (Bit 5) */ + #define R_ETHA0_EAEIS1_CULES5_Msk (0x20UL) /*!< CULES5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_CULES6_Pos (6UL) /*!< CULES6 (Bit 6) */ + #define R_ETHA0_EAEIS1_CULES6_Msk (0x40UL) /*!< CULES6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_CULES7_Pos (7UL) /*!< CULES7 (Bit 7) */ + #define R_ETHA0_EAEIS1_CULES7_Msk (0x80UL) /*!< CULES7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES0_Pos (16UL) /*!< TASGES0 (Bit 16) */ + #define R_ETHA0_EAEIS1_TASGES0_Msk (0x10000UL) /*!< TASGES0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES1_Pos (17UL) /*!< TASGES1 (Bit 17) */ + #define R_ETHA0_EAEIS1_TASGES1_Msk (0x20000UL) /*!< TASGES1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES2_Pos (18UL) /*!< TASGES2 (Bit 18) */ + #define R_ETHA0_EAEIS1_TASGES2_Msk (0x40000UL) /*!< TASGES2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES3_Pos (19UL) /*!< TASGES3 (Bit 19) */ + #define R_ETHA0_EAEIS1_TASGES3_Msk (0x80000UL) /*!< TASGES3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES4_Pos (20UL) /*!< TASGES4 (Bit 20) */ + #define R_ETHA0_EAEIS1_TASGES4_Msk (0x100000UL) /*!< TASGES4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES5_Pos (21UL) /*!< TASGES5 (Bit 21) */ + #define R_ETHA0_EAEIS1_TASGES5_Msk (0x200000UL) /*!< TASGES5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES6_Pos (22UL) /*!< TASGES6 (Bit 22) */ + #define R_ETHA0_EAEIS1_TASGES6_Msk (0x400000UL) /*!< TASGES6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES7_Pos (23UL) /*!< TASGES7 (Bit 23) */ + #define R_ETHA0_EAEIS1_TASGES7_Msk (0x800000UL) /*!< TASGES7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASCTGES_Pos (24UL) /*!< TASCTGES (Bit 24) */ + #define R_ETHA0_EAEIS1_TASCTGES_Msk (0x1000000UL) /*!< TASCTGES (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEIE1 ========================================================= */ + #define R_ETHA0_EAEIE1_CULEE0_Pos (0UL) /*!< CULEE0 (Bit 0) */ + #define R_ETHA0_EAEIE1_CULEE0_Msk (0x1UL) /*!< CULEE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_CULEE1_Pos (1UL) /*!< CULEE1 (Bit 1) */ + #define R_ETHA0_EAEIE1_CULEE1_Msk (0x2UL) /*!< CULEE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_CULEE2_Pos (2UL) /*!< CULEE2 (Bit 2) */ + #define R_ETHA0_EAEIE1_CULEE2_Msk (0x4UL) /*!< CULEE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_CULEE3_Pos (3UL) /*!< CULEE3 (Bit 3) */ + #define R_ETHA0_EAEIE1_CULEE3_Msk (0x8UL) /*!< CULEE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_CULEE4_Pos (4UL) /*!< CULEE4 (Bit 4) */ + #define R_ETHA0_EAEIE1_CULEE4_Msk (0x10UL) /*!< CULEE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_CULEE5_Pos (5UL) /*!< CULEE5 (Bit 5) */ + #define R_ETHA0_EAEIE1_CULEE5_Msk (0x20UL) /*!< CULEE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_CULEE6_Pos (6UL) /*!< CULEE6 (Bit 6) */ + #define R_ETHA0_EAEIE1_CULEE6_Msk (0x40UL) /*!< CULEE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_CULEE7_Pos (7UL) /*!< CULEE7 (Bit 7) */ + #define R_ETHA0_EAEIE1_CULEE7_Msk (0x80UL) /*!< CULEE7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE0_Pos (16UL) /*!< TASGEE0 (Bit 16) */ + #define R_ETHA0_EAEIE1_TASGEE0_Msk (0x10000UL) /*!< TASGEE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE1_Pos (17UL) /*!< TASGEE1 (Bit 17) */ + #define R_ETHA0_EAEIE1_TASGEE1_Msk (0x20000UL) /*!< TASGEE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE2_Pos (18UL) /*!< TASGEE2 (Bit 18) */ + #define R_ETHA0_EAEIE1_TASGEE2_Msk (0x40000UL) /*!< TASGEE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE3_Pos (19UL) /*!< TASGEE3 (Bit 19) */ + #define R_ETHA0_EAEIE1_TASGEE3_Msk (0x80000UL) /*!< TASGEE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE4_Pos (20UL) /*!< TASGEE4 (Bit 20) */ + #define R_ETHA0_EAEIE1_TASGEE4_Msk (0x100000UL) /*!< TASGEE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE5_Pos (21UL) /*!< TASGEE5 (Bit 21) */ + #define R_ETHA0_EAEIE1_TASGEE5_Msk (0x200000UL) /*!< TASGEE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE6_Pos (22UL) /*!< TASGEE6 (Bit 22) */ + #define R_ETHA0_EAEIE1_TASGEE6_Msk (0x400000UL) /*!< TASGEE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE7_Pos (23UL) /*!< TASGEE7 (Bit 23) */ + #define R_ETHA0_EAEIE1_TASGEE7_Msk (0x800000UL) /*!< TASGEE7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASCTGEE_Pos (24UL) /*!< TASCTGEE (Bit 24) */ + #define R_ETHA0_EAEIE1_TASCTGEE_Msk (0x1000000UL) /*!< TASCTGEE (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEID1 ========================================================= */ + #define R_ETHA0_EAEID1_CULED0_Pos (0UL) /*!< CULED0 (Bit 0) */ + #define R_ETHA0_EAEID1_CULED0_Msk (0x1UL) /*!< CULED0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_CULED1_Pos (1UL) /*!< CULED1 (Bit 1) */ + #define R_ETHA0_EAEID1_CULED1_Msk (0x2UL) /*!< CULED1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_CULED2_Pos (2UL) /*!< CULED2 (Bit 2) */ + #define R_ETHA0_EAEID1_CULED2_Msk (0x4UL) /*!< CULED2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_CULED3_Pos (3UL) /*!< CULED3 (Bit 3) */ + #define R_ETHA0_EAEID1_CULED3_Msk (0x8UL) /*!< CULED3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_CULED4_Pos (4UL) /*!< CULED4 (Bit 4) */ + #define R_ETHA0_EAEID1_CULED4_Msk (0x10UL) /*!< CULED4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_CULED5_Pos (5UL) /*!< CULED5 (Bit 5) */ + #define R_ETHA0_EAEID1_CULED5_Msk (0x20UL) /*!< CULED5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_CULED6_Pos (6UL) /*!< CULED6 (Bit 6) */ + #define R_ETHA0_EAEID1_CULED6_Msk (0x40UL) /*!< CULED6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_CULED7_Pos (7UL) /*!< CULED7 (Bit 7) */ + #define R_ETHA0_EAEID1_CULED7_Msk (0x80UL) /*!< CULED7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED0_Pos (16UL) /*!< TASGED0 (Bit 16) */ + #define R_ETHA0_EAEID1_TASGED0_Msk (0x10000UL) /*!< TASGED0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED1_Pos (17UL) /*!< TASGED1 (Bit 17) */ + #define R_ETHA0_EAEID1_TASGED1_Msk (0x20000UL) /*!< TASGED1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED2_Pos (18UL) /*!< TASGED2 (Bit 18) */ + #define R_ETHA0_EAEID1_TASGED2_Msk (0x40000UL) /*!< TASGED2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED3_Pos (19UL) /*!< TASGED3 (Bit 19) */ + #define R_ETHA0_EAEID1_TASGED3_Msk (0x80000UL) /*!< TASGED3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED4_Pos (20UL) /*!< TASGED4 (Bit 20) */ + #define R_ETHA0_EAEID1_TASGED4_Msk (0x100000UL) /*!< TASGED4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED5_Pos (21UL) /*!< TASGED5 (Bit 21) */ + #define R_ETHA0_EAEID1_TASGED5_Msk (0x200000UL) /*!< TASGED5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED6_Pos (22UL) /*!< TASGED6 (Bit 22) */ + #define R_ETHA0_EAEID1_TASGED6_Msk (0x400000UL) /*!< TASGED6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED7_Pos (23UL) /*!< TASGED7 (Bit 23) */ + #define R_ETHA0_EAEID1_TASGED7_Msk (0x800000UL) /*!< TASGED7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASCTGED_Pos (24UL) /*!< TASCTGED (Bit 24) */ + #define R_ETHA0_EAEID1_TASCTGED_Msk (0x1000000UL) /*!< TASCTGED (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEIS2 ========================================================= */ + #define R_ETHA0_EAEIS2_DQOES0_Pos (0UL) /*!< DQOES0 (Bit 0) */ + #define R_ETHA0_EAEIS2_DQOES0_Msk (0x1UL) /*!< DQOES0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQOES1_Pos (1UL) /*!< DQOES1 (Bit 1) */ + #define R_ETHA0_EAEIS2_DQOES1_Msk (0x2UL) /*!< DQOES1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQOES2_Pos (2UL) /*!< DQOES2 (Bit 2) */ + #define R_ETHA0_EAEIS2_DQOES2_Msk (0x4UL) /*!< DQOES2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQOES3_Pos (3UL) /*!< DQOES3 (Bit 3) */ + #define R_ETHA0_EAEIS2_DQOES3_Msk (0x8UL) /*!< DQOES3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQOES4_Pos (4UL) /*!< DQOES4 (Bit 4) */ + #define R_ETHA0_EAEIS2_DQOES4_Msk (0x10UL) /*!< DQOES4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQOES5_Pos (5UL) /*!< DQOES5 (Bit 5) */ + #define R_ETHA0_EAEIS2_DQOES5_Msk (0x20UL) /*!< DQOES5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQOES6_Pos (6UL) /*!< DQOES6 (Bit 6) */ + #define R_ETHA0_EAEIS2_DQOES6_Msk (0x40UL) /*!< DQOES6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQOES7_Pos (7UL) /*!< DQOES7 (Bit 7) */ + #define R_ETHA0_EAEIS2_DQOES7_Msk (0x80UL) /*!< DQOES7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_CTDQOES_Pos (8UL) /*!< CTDQOES (Bit 8) */ + #define R_ETHA0_EAEIS2_CTDQOES_Msk (0x100UL) /*!< CTDQOES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES0_Pos (16UL) /*!< DQSES0 (Bit 16) */ + #define R_ETHA0_EAEIS2_DQSES0_Msk (0x10000UL) /*!< DQSES0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES1_Pos (17UL) /*!< DQSES1 (Bit 17) */ + #define R_ETHA0_EAEIS2_DQSES1_Msk (0x20000UL) /*!< DQSES1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES2_Pos (18UL) /*!< DQSES2 (Bit 18) */ + #define R_ETHA0_EAEIS2_DQSES2_Msk (0x40000UL) /*!< DQSES2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES3_Pos (19UL) /*!< DQSES3 (Bit 19) */ + #define R_ETHA0_EAEIS2_DQSES3_Msk (0x80000UL) /*!< DQSES3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES4_Pos (20UL) /*!< DQSES4 (Bit 20) */ + #define R_ETHA0_EAEIS2_DQSES4_Msk (0x100000UL) /*!< DQSES4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES5_Pos (21UL) /*!< DQSES5 (Bit 21) */ + #define R_ETHA0_EAEIS2_DQSES5_Msk (0x200000UL) /*!< DQSES5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES6_Pos (22UL) /*!< DQSES6 (Bit 22) */ + #define R_ETHA0_EAEIS2_DQSES6_Msk (0x400000UL) /*!< DQSES6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES7_Pos (23UL) /*!< DQSES7 (Bit 23) */ + #define R_ETHA0_EAEIS2_DQSES7_Msk (0x800000UL) /*!< DQSES7 (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEIE2 ========================================================= */ + #define R_ETHA0_EAEIE2_DQOEE0_Pos (0UL) /*!< DQOEE0 (Bit 0) */ + #define R_ETHA0_EAEIE2_DQOEE0_Msk (0x1UL) /*!< DQOEE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQOEE1_Pos (1UL) /*!< DQOEE1 (Bit 1) */ + #define R_ETHA0_EAEIE2_DQOEE1_Msk (0x2UL) /*!< DQOEE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQOEE2_Pos (2UL) /*!< DQOEE2 (Bit 2) */ + #define R_ETHA0_EAEIE2_DQOEE2_Msk (0x4UL) /*!< DQOEE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQOEE3_Pos (3UL) /*!< DQOEE3 (Bit 3) */ + #define R_ETHA0_EAEIE2_DQOEE3_Msk (0x8UL) /*!< DQOEE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQOEE4_Pos (4UL) /*!< DQOEE4 (Bit 4) */ + #define R_ETHA0_EAEIE2_DQOEE4_Msk (0x10UL) /*!< DQOEE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQOEE5_Pos (5UL) /*!< DQOEE5 (Bit 5) */ + #define R_ETHA0_EAEIE2_DQOEE5_Msk (0x20UL) /*!< DQOEE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQOEE6_Pos (6UL) /*!< DQOEE6 (Bit 6) */ + #define R_ETHA0_EAEIE2_DQOEE6_Msk (0x40UL) /*!< DQOEE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQOEE7_Pos (7UL) /*!< DQOEE7 (Bit 7) */ + #define R_ETHA0_EAEIE2_DQOEE7_Msk (0x80UL) /*!< DQOEE7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_CTDQOEE_Pos (8UL) /*!< CTDQOEE (Bit 8) */ + #define R_ETHA0_EAEIE2_CTDQOEE_Msk (0x100UL) /*!< CTDQOEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE0_Pos (16UL) /*!< DQSEE0 (Bit 16) */ + #define R_ETHA0_EAEIE2_DQSEE0_Msk (0x10000UL) /*!< DQSEE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE1_Pos (17UL) /*!< DQSEE1 (Bit 17) */ + #define R_ETHA0_EAEIE2_DQSEE1_Msk (0x20000UL) /*!< DQSEE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE2_Pos (18UL) /*!< DQSEE2 (Bit 18) */ + #define R_ETHA0_EAEIE2_DQSEE2_Msk (0x40000UL) /*!< DQSEE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE3_Pos (19UL) /*!< DQSEE3 (Bit 19) */ + #define R_ETHA0_EAEIE2_DQSEE3_Msk (0x80000UL) /*!< DQSEE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE4_Pos (20UL) /*!< DQSEE4 (Bit 20) */ + #define R_ETHA0_EAEIE2_DQSEE4_Msk (0x100000UL) /*!< DQSEE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE5_Pos (21UL) /*!< DQSEE5 (Bit 21) */ + #define R_ETHA0_EAEIE2_DQSEE5_Msk (0x200000UL) /*!< DQSEE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE6_Pos (22UL) /*!< DQSEE6 (Bit 22) */ + #define R_ETHA0_EAEIE2_DQSEE6_Msk (0x400000UL) /*!< DQSEE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE7_Pos (23UL) /*!< DQSEE7 (Bit 23) */ + #define R_ETHA0_EAEIE2_DQSEE7_Msk (0x800000UL) /*!< DQSEE7 (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEID2 ========================================================= */ + #define R_ETHA0_EAEID2_DQOED0_Pos (0UL) /*!< DQOED0 (Bit 0) */ + #define R_ETHA0_EAEID2_DQOED0_Msk (0x1UL) /*!< DQOED0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQOED1_Pos (1UL) /*!< DQOED1 (Bit 1) */ + #define R_ETHA0_EAEID2_DQOED1_Msk (0x2UL) /*!< DQOED1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQOED2_Pos (2UL) /*!< DQOED2 (Bit 2) */ + #define R_ETHA0_EAEID2_DQOED2_Msk (0x4UL) /*!< DQOED2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQOED3_Pos (3UL) /*!< DQOED3 (Bit 3) */ + #define R_ETHA0_EAEID2_DQOED3_Msk (0x8UL) /*!< DQOED3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQOED4_Pos (4UL) /*!< DQOED4 (Bit 4) */ + #define R_ETHA0_EAEID2_DQOED4_Msk (0x10UL) /*!< DQOED4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQOED5_Pos (5UL) /*!< DQOED5 (Bit 5) */ + #define R_ETHA0_EAEID2_DQOED5_Msk (0x20UL) /*!< DQOED5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQOED6_Pos (6UL) /*!< DQOED6 (Bit 6) */ + #define R_ETHA0_EAEID2_DQOED6_Msk (0x40UL) /*!< DQOED6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQOED7_Pos (7UL) /*!< DQOED7 (Bit 7) */ + #define R_ETHA0_EAEID2_DQOED7_Msk (0x80UL) /*!< DQOED7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_CTDQOED_Pos (8UL) /*!< CTDQOED (Bit 8) */ + #define R_ETHA0_EAEID2_CTDQOED_Msk (0x100UL) /*!< CTDQOED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED0_Pos (16UL) /*!< DQSED0 (Bit 16) */ + #define R_ETHA0_EAEID2_DQSED0_Msk (0x10000UL) /*!< DQSED0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED1_Pos (17UL) /*!< DQSED1 (Bit 17) */ + #define R_ETHA0_EAEID2_DQSED1_Msk (0x20000UL) /*!< DQSED1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED2_Pos (18UL) /*!< DQSED2 (Bit 18) */ + #define R_ETHA0_EAEID2_DQSED2_Msk (0x40000UL) /*!< DQSED2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED3_Pos (19UL) /*!< DQSED3 (Bit 19) */ + #define R_ETHA0_EAEID2_DQSED3_Msk (0x80000UL) /*!< DQSED3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED4_Pos (20UL) /*!< DQSED4 (Bit 20) */ + #define R_ETHA0_EAEID2_DQSED4_Msk (0x100000UL) /*!< DQSED4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED5_Pos (21UL) /*!< DQSED5 (Bit 21) */ + #define R_ETHA0_EAEID2_DQSED5_Msk (0x200000UL) /*!< DQSED5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED6_Pos (22UL) /*!< DQSED6 (Bit 22) */ + #define R_ETHA0_EAEID2_DQSED6_Msk (0x400000UL) /*!< DQSED6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED7_Pos (23UL) /*!< DQSED7 (Bit 23) */ + #define R_ETHA0_EAEID2_DQSED7_Msk (0x800000UL) /*!< DQSED7 (Bitfield-Mask: 0x01) */ +/* ========================================================= EASCR ========================================================= */ + #define R_ETHA0_EASCR_MRSL_Pos (0UL) /*!< MRSL (Bit 0) */ + #define R_ETHA0_EASCR_MRSL_Msk (0x1UL) /*!< MRSL (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_TRSL_Pos (1UL) /*!< TRSL (Bit 1) */ + #define R_ETHA0_EASCR_TRSL_Msk (0x2UL) /*!< TRSL (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_MCRSL_Pos (2UL) /*!< MCRSL (Bit 2) */ + #define R_ETHA0_EASCR_MCRSL_Msk (0x4UL) /*!< MCRSL (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_TGRSL_Pos (3UL) /*!< TGRSL (Bit 3) */ + #define R_ETHA0_EASCR_TGRSL_Msk (0x8UL) /*!< TGRSL (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_TASRSL_Pos (4UL) /*!< TASRSL (Bit 4) */ + #define R_ETHA0_EASCR_TASRSL_Msk (0x10UL) /*!< TASRSL (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_EIRSL_Pos (5UL) /*!< EIRSL (Bit 5) */ + #define R_ETHA0_EASCR_EIRSL_Msk (0x20UL) /*!< EIRSL (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_CRSL_Pos (6UL) /*!< CRSL (Bit 6) */ + #define R_ETHA0_EASCR_CRSL_Msk (0x40UL) /*!< CRSL (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL0_Pos (16UL) /*!< DQRSL0 (Bit 16) */ + #define R_ETHA0_EASCR_DQRSL0_Msk (0x10000UL) /*!< DQRSL0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL1_Pos (17UL) /*!< DQRSL1 (Bit 17) */ + #define R_ETHA0_EASCR_DQRSL1_Msk (0x20000UL) /*!< DQRSL1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL2_Pos (18UL) /*!< DQRSL2 (Bit 18) */ + #define R_ETHA0_EASCR_DQRSL2_Msk (0x40000UL) /*!< DQRSL2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL3_Pos (19UL) /*!< DQRSL3 (Bit 19) */ + #define R_ETHA0_EASCR_DQRSL3_Msk (0x80000UL) /*!< DQRSL3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL4_Pos (20UL) /*!< DQRSL4 (Bit 20) */ + #define R_ETHA0_EASCR_DQRSL4_Msk (0x100000UL) /*!< DQRSL4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL5_Pos (21UL) /*!< DQRSL5 (Bit 21) */ + #define R_ETHA0_EASCR_DQRSL5_Msk (0x200000UL) /*!< DQRSL5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL6_Pos (22UL) /*!< DQRSL6 (Bit 22) */ + #define R_ETHA0_EASCR_DQRSL6_Msk (0x400000UL) /*!< DQRSL6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL7_Pos (23UL) /*!< DQRSL7 (Bit 23) */ + #define R_ETHA0_EASCR_DQRSL7_Msk (0x800000UL) /*!< DQRSL7 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PTPIPV ========================================================= */ + #define R_GPTP_PTPIPV_IPV_Pos (0UL) /*!< IPV (Bit 0) */ + #define R_GPTP_PTPIPV_IPV_Msk (0xffffffffUL) /*!< IPV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== PTPTMEC ======================================================== */ + #define R_GPTP_PTPTMEC_TE_Pos (0UL) /*!< TE (Bit 0) */ + #define R_GPTP_PTPTMEC_TE_Msk (0x3UL) /*!< TE (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPTMDC ======================================================== */ + #define R_GPTP_PTPTMDC_TD_Pos (0UL) /*!< TD (Bit 0) */ + #define R_GPTP_PTPTMDC_TD_Msk (0x3UL) /*!< TD (Bitfield-Mask: 0x03) */ +/* ======================================================= PTPTIVC0 ======================================================== */ + #define R_GPTP_PTPTIVC0_TIV_Pos (0UL) /*!< TIV (Bit 0) */ + #define R_GPTP_PTPTIVC0_TIV_Msk (0xffffffffUL) /*!< TIV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPTIVC1 ======================================================== */ + #define R_GPTP_PTPTIVC1_TIV_Pos (0UL) /*!< TIV (Bit 0) */ + #define R_GPTP_PTPTIVC1_TIV_Msk (0xffffffffUL) /*!< TIV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPTOVCL0 ======================================================= */ + #define R_GPTP_PTPTOVCL0_TOVL_Pos (0UL) /*!< TOVL (Bit 0) */ + #define R_GPTP_PTPTOVCL0_TOVL_Msk (0x3fffffffUL) /*!< TOVL (Bitfield-Mask: 0x3fffffff) */ +/* ======================================================= PTPTOVCL1 ======================================================= */ + #define R_GPTP_PTPTOVCL1_TOVL_Pos (0UL) /*!< TOVL (Bit 0) */ + #define R_GPTP_PTPTOVCL1_TOVL_Msk (0x3fffffffUL) /*!< TOVL (Bitfield-Mask: 0x3fffffff) */ +/* ======================================================= PTPTOVCM0 ======================================================= */ + #define R_GPTP_PTPTOVCM0_TOVM_Pos (0UL) /*!< TOVM (Bit 0) */ + #define R_GPTP_PTPTOVCM0_TOVM_Msk (0xffffffffUL) /*!< TOVM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPTOVCM1 ======================================================= */ + #define R_GPTP_PTPTOVCM1_TOVM_Pos (0UL) /*!< TOVM (Bit 0) */ + #define R_GPTP_PTPTOVCM1_TOVM_Msk (0xffffffffUL) /*!< TOVM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPTOVCU0 ======================================================= */ + #define R_GPTP_PTPTOVCU0_TOVU_Pos (0UL) /*!< TOVU (Bit 0) */ + #define R_GPTP_PTPTOVCU0_TOVU_Msk (0xffffUL) /*!< TOVU (Bitfield-Mask: 0xffff) */ +/* ======================================================= PTPTOVCU1 ======================================================= */ + #define R_GPTP_PTPTOVCU1_TOVU_Pos (0UL) /*!< TOVU (Bit 0) */ + #define R_GPTP_PTPTOVCU1_TOVU_Msk (0xffffUL) /*!< TOVU (Bitfield-Mask: 0xffff) */ +/* ====================================================== PTPAVTPTML0 ====================================================== */ + #define R_GPTP_PTPAVTPTML0_AVTPL_Pos (0UL) /*!< AVTPL (Bit 0) */ + #define R_GPTP_PTPAVTPTML0_AVTPL_Msk (0xffffffffUL) /*!< AVTPL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPAVTPTML1 ====================================================== */ + #define R_GPTP_PTPAVTPTML1_AVTPL_Pos (0UL) /*!< AVTPL (Bit 0) */ + #define R_GPTP_PTPAVTPTML1_AVTPL_Msk (0xffffffffUL) /*!< AVTPL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPAVTPTMU0 ====================================================== */ + #define R_GPTP_PTPAVTPTMU0_AVTPU_Pos (0UL) /*!< AVTPU (Bit 0) */ + #define R_GPTP_PTPAVTPTMU0_AVTPU_Msk (0xffffffffUL) /*!< AVTPU (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPAVTPTMU1 ====================================================== */ + #define R_GPTP_PTPAVTPTMU1_AVTPU_Pos (0UL) /*!< AVTPU (Bit 0) */ + #define R_GPTP_PTPAVTPTMU1_AVTPU_Msk (0xffffffffUL) /*!< AVTPU (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPGPTPTML0 ====================================================== */ + #define R_GPTP_PTPGPTPTML0_GPTPL_Pos (0UL) /*!< GPTPL (Bit 0) */ + #define R_GPTP_PTPGPTPTML0_GPTPL_Msk (0x3fffffffUL) /*!< GPTPL (Bitfield-Mask: 0x3fffffff) */ +/* ====================================================== PTPGPTPTML1 ====================================================== */ + #define R_GPTP_PTPGPTPTML1_GPTPL_Pos (0UL) /*!< GPTPL (Bit 0) */ + #define R_GPTP_PTPGPTPTML1_GPTPL_Msk (0x3fffffffUL) /*!< GPTPL (Bitfield-Mask: 0x3fffffff) */ +/* ====================================================== PTPGPTPTMM0 ====================================================== */ + #define R_GPTP_PTPGPTPTMM0_GPTPM_Pos (0UL) /*!< GPTPM (Bit 0) */ + #define R_GPTP_PTPGPTPTMM0_GPTPM_Msk (0xffffffffUL) /*!< GPTPM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPGPTPTMM1 ====================================================== */ + #define R_GPTP_PTPGPTPTMM1_GPTPM_Pos (0UL) /*!< GPTPM (Bit 0) */ + #define R_GPTP_PTPGPTPTMM1_GPTPM_Msk (0xffffffffUL) /*!< GPTPM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPGPTPTMU0 ====================================================== */ + #define R_GPTP_PTPGPTPTMU0_GPTPU_Pos (0UL) /*!< GPTPU (Bit 0) */ + #define R_GPTP_PTPGPTPTMU0_GPTPU_Msk (0xffffUL) /*!< GPTPU (Bitfield-Mask: 0xffff) */ +/* ====================================================== PTPGPTPTMU1 ====================================================== */ + #define R_GPTP_PTPGPTPTMU1_GPTPU_Pos (0UL) /*!< GPTPU (Bit 0) */ + #define R_GPTP_PTPGPTPTMU1_GPTPU_Msk (0xffffUL) /*!< GPTPU (Bitfield-Mask: 0xffff) */ +/* ======================================================= PTPMCCC0 ======================================================== */ + #define R_GPTP_PTPMCCC0_MCPEE_Pos (0UL) /*!< MCPEE (Bit 0) */ + #define R_GPTP_PTPMCCC0_MCPEE_Msk (0x1UL) /*!< MCPEE (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC0_MCNEE_Pos (1UL) /*!< MCNEE (Bit 1) */ + #define R_GPTP_PTPMCCC0_MCNEE_Msk (0x2UL) /*!< MCNEE (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC0_MCTTS_Pos (2UL) /*!< MCTTS (Bit 2) */ + #define R_GPTP_PTPMCCC0_MCTTS_Msk (0x4UL) /*!< MCTTS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC0_MCTNS_Pos (3UL) /*!< MCTNS (Bit 3) */ + #define R_GPTP_PTPMCCC0_MCTNS_Msk (0x8UL) /*!< MCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC0_MCCR_Pos (16UL) /*!< MCCR (Bit 16) */ + #define R_GPTP_PTPMCCC0_MCCR_Msk (0x10000UL) /*!< MCCR (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPMCCC1 ======================================================== */ + #define R_GPTP_PTPMCCC1_MCPEE_Pos (0UL) /*!< MCPEE (Bit 0) */ + #define R_GPTP_PTPMCCC1_MCPEE_Msk (0x1UL) /*!< MCPEE (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC1_MCNEE_Pos (1UL) /*!< MCNEE (Bit 1) */ + #define R_GPTP_PTPMCCC1_MCNEE_Msk (0x2UL) /*!< MCNEE (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC1_MCTTS_Pos (2UL) /*!< MCTTS (Bit 2) */ + #define R_GPTP_PTPMCCC1_MCTTS_Msk (0x4UL) /*!< MCTTS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC1_MCTNS_Pos (3UL) /*!< MCTNS (Bit 3) */ + #define R_GPTP_PTPMCCC1_MCTNS_Msk (0x8UL) /*!< MCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC1_MCCR_Pos (16UL) /*!< MCCR (Bit 16) */ + #define R_GPTP_PTPMCCC1_MCCR_Msk (0x10000UL) /*!< MCCR (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPMCCML0 ======================================================= */ + #define R_GPTP_PTPMCCML0_MCCTVL_Pos (0UL) /*!< MCCTVL (Bit 0) */ + #define R_GPTP_PTPMCCML0_MCCTVL_Msk (0xffffffffUL) /*!< MCCTVL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPMCCML1 ======================================================= */ + #define R_GPTP_PTPMCCML1_MCCTVL_Pos (0UL) /*!< MCCTVL (Bit 0) */ + #define R_GPTP_PTPMCCML1_MCCTVL_Msk (0xffffffffUL) /*!< MCCTVL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPMCCMM0 ======================================================= */ + #define R_GPTP_PTPMCCMM0_MCCTVM_Pos (0UL) /*!< MCCTVM (Bit 0) */ + #define R_GPTP_PTPMCCMM0_MCCTVM_Msk (0xffffffffUL) /*!< MCCTVM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPMCCMM1 ======================================================= */ + #define R_GPTP_PTPMCCMM1_MCCTVM_Pos (0UL) /*!< MCCTVM (Bit 0) */ + #define R_GPTP_PTPMCCMM1_MCCTVM_Msk (0xffffffffUL) /*!< MCCTVM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPMCCMU0 ======================================================= */ + #define R_GPTP_PTPMCCMU0_MCCTVU_Pos (0UL) /*!< MCCTVU (Bit 0) */ + #define R_GPTP_PTPMCCMU0_MCCTVU_Msk (0xffffUL) /*!< MCCTVU (Bitfield-Mask: 0xffff) */ + #define R_GPTP_PTPMCCMU0_MCPEC_Pos (16UL) /*!< MCPEC (Bit 16) */ + #define R_GPTP_PTPMCCMU0_MCPEC_Msk (0x10000UL) /*!< MCPEC (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCMU0_MCNEC_Pos (17UL) /*!< MCNEC (Bit 17) */ + #define R_GPTP_PTPMCCMU0_MCNEC_Msk (0x20000UL) /*!< MCNEC (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCMU0_MCSWC_Pos (18UL) /*!< MCSWC (Bit 18) */ + #define R_GPTP_PTPMCCMU0_MCSWC_Msk (0x40000UL) /*!< MCSWC (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCMU0_MCCN_Pos (24UL) /*!< MCCN (Bit 24) */ + #define R_GPTP_PTPMCCMU0_MCCN_Msk (0x3000000UL) /*!< MCCN (Bitfield-Mask: 0x03) */ +/* ======================================================= PTPMCCMU1 ======================================================= */ + #define R_GPTP_PTPMCCMU1_MCCTVU_Pos (0UL) /*!< MCCTVU (Bit 0) */ + #define R_GPTP_PTPMCCMU1_MCCTVU_Msk (0xffffUL) /*!< MCCTVU (Bitfield-Mask: 0xffff) */ + #define R_GPTP_PTPMCCMU1_MCPEC_Pos (16UL) /*!< MCPEC (Bit 16) */ + #define R_GPTP_PTPMCCMU1_MCPEC_Msk (0x10000UL) /*!< MCPEC (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCMU1_MCNEC_Pos (17UL) /*!< MCNEC (Bit 17) */ + #define R_GPTP_PTPMCCMU1_MCNEC_Msk (0x20000UL) /*!< MCNEC (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCMU1_MCSWC_Pos (18UL) /*!< MCSWC (Bit 18) */ + #define R_GPTP_PTPMCCMU1_MCSWC_Msk (0x40000UL) /*!< MCSWC (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCMU1_MCCN_Pos (24UL) /*!< MCCN (Bit 24) */ + #define R_GPTP_PTPMCCMU1_MCCN_Msk (0x3000000UL) /*!< MCCN (Bitfield-Mask: 0x03) */ +/* ======================================================= PTPMCRC0 ======================================================== */ + #define R_GPTP_PTPMCRC0_MRTTS_Pos (0UL) /*!< MRTTS (Bit 0) */ + #define R_GPTP_PTPMCRC0_MRTTS_Msk (0x1UL) /*!< MRTTS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCRC0_MRAMS_Pos (1UL) /*!< MRAMS (Bit 1) */ + #define R_GPTP_PTPMCRC0_MRAMS_Msk (0x2UL) /*!< MRAMS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCRC0_MRTNS_Pos (2UL) /*!< MRTNS (Bit 2) */ + #define R_GPTP_PTPMCRC0_MRTNS_Msk (0x4UL) /*!< MRTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCRC0_MRPL_Pos (16UL) /*!< MRPL (Bit 16) */ + #define R_GPTP_PTPMCRC0_MRPL_Msk (0xffff0000UL) /*!< MRPL (Bitfield-Mask: 0xffff) */ +/* ======================================================= PTPMCRC1 ======================================================== */ + #define R_GPTP_PTPMCRC1_MRTTS_Pos (0UL) /*!< MRTTS (Bit 0) */ + #define R_GPTP_PTPMCRC1_MRTTS_Msk (0x1UL) /*!< MRTTS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCRC1_MRAMS_Pos (1UL) /*!< MRAMS (Bit 1) */ + #define R_GPTP_PTPMCRC1_MRAMS_Msk (0x2UL) /*!< MRAMS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCRC1_MRTNS_Pos (2UL) /*!< MRTNS (Bit 2) */ + #define R_GPTP_PTPMCRC1_MRTNS_Msk (0x4UL) /*!< MRTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCRC1_MRPL_Pos (16UL) /*!< MRPL (Bit 16) */ + #define R_GPTP_PTPMCRC1_MRPL_Msk (0xffff0000UL) /*!< MRPL (Bitfield-Mask: 0xffff) */ +/* ====================================================== PTPMCRTCL0 ======================================================= */ + #define R_GPTP_PTPMCRTCL0_MRTVL_Pos (0UL) /*!< MRTVL (Bit 0) */ + #define R_GPTP_PTPMCRTCL0_MRTVL_Msk (0xffffffffUL) /*!< MRTVL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPMCRTCL1 ======================================================= */ + #define R_GPTP_PTPMCRTCL1_MRTVL_Pos (0UL) /*!< MRTVL (Bit 0) */ + #define R_GPTP_PTPMCRTCL1_MRTVL_Msk (0xffffffffUL) /*!< MRTVL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPMCRTCM0 ======================================================= */ + #define R_GPTP_PTPMCRTCM0_MRTVM_Pos (0UL) /*!< MRTVM (Bit 0) */ + #define R_GPTP_PTPMCRTCM0_MRTVM_Msk (0xffffffffUL) /*!< MRTVM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPMCRTCM1 ======================================================= */ + #define R_GPTP_PTPMCRTCM1_MRTVM_Pos (0UL) /*!< MRTVM (Bit 0) */ + #define R_GPTP_PTPMCRTCM1_MRTVM_Msk (0xffffffffUL) /*!< MRTVM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPMCRTCU0 ======================================================= */ + #define R_GPTP_PTPMCRTCU0_MRTVU_Pos (0UL) /*!< MRTVU (Bit 0) */ + #define R_GPTP_PTPMCRTCU0_MRTVU_Msk (0xffffUL) /*!< MRTVU (Bitfield-Mask: 0xffff) */ + #define R_GPTP_PTPMCRTCU0_MRTT_Pos (16UL) /*!< MRTT (Bit 16) */ + #define R_GPTP_PTPMCRTCU0_MRTT_Msk (0x30000UL) /*!< MRTT (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPMCRTCU0_MCRN_Pos (18UL) /*!< MCRN (Bit 18) */ + #define R_GPTP_PTPMCRTCU0_MCRN_Msk (0x1c0000UL) /*!< MCRN (Bitfield-Mask: 0x07) */ + #define R_GPTP_PTPMCRTCU0_MRBCR_Pos (31UL) /*!< MRBCR (Bit 31) */ + #define R_GPTP_PTPMCRTCU0_MRBCR_Msk (0x80000000UL) /*!< MRBCR (Bitfield-Mask: 0x01) */ +/* ====================================================== PTPMCRTCU1 ======================================================= */ + #define R_GPTP_PTPMCRTCU1_MRTVU_Pos (0UL) /*!< MRTVU (Bit 0) */ + #define R_GPTP_PTPMCRTCU1_MRTVU_Msk (0xffffUL) /*!< MRTVU (Bitfield-Mask: 0xffff) */ + #define R_GPTP_PTPMCRTCU1_MRTT_Pos (16UL) /*!< MRTT (Bit 16) */ + #define R_GPTP_PTPMCRTCU1_MRTT_Msk (0x30000UL) /*!< MRTT (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPMCRTCU1_MCRN_Pos (18UL) /*!< MCRN (Bit 18) */ + #define R_GPTP_PTPMCRTCU1_MCRN_Msk (0x1c0000UL) /*!< MCRN (Bitfield-Mask: 0x07) */ + #define R_GPTP_PTPMCRTCU1_MRBCR_Pos (31UL) /*!< MRBCR (Bit 31) */ + #define R_GPTP_PTPMCRTCU1_MRBCR_Msk (0x80000000UL) /*!< MRBCR (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPMCPC0 ======================================================== */ + #define R_GPTP_PTPMCPC0_PE_Pos (0UL) /*!< PE (Bit 0) */ + #define R_GPTP_PTPMCPC0_PE_Msk (0x1UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCPC0_MRS_Pos (1UL) /*!< MRS (Bit 1) */ + #define R_GPTP_PTPMCPC0_MRS_Msk (0x2UL) /*!< MRS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPMCPC1 ======================================================== */ + #define R_GPTP_PTPMCPC1_PE_Pos (0UL) /*!< PE (Bit 0) */ + #define R_GPTP_PTPMCPC1_PE_Msk (0x1UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCPC1_MRS_Pos (1UL) /*!< MRS (Bit 1) */ + #define R_GPTP_PTPMCPC1_MRS_Msk (0x2UL) /*!< MRS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC00 ======================================================== */ + #define R_GPTP_PTPCCC00_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC00_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC00_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC00_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC01 ======================================================== */ + #define R_GPTP_PTPCCC01_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC01_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC01_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC01_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC02 ======================================================== */ + #define R_GPTP_PTPCCC02_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC02_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC02_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC02_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC03 ======================================================== */ + #define R_GPTP_PTPCCC03_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC03_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC03_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC03_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC04 ======================================================== */ + #define R_GPTP_PTPCCC04_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC04_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC04_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC04_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC05 ======================================================== */ + #define R_GPTP_PTPCCC05_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC05_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC05_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC05_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC06 ======================================================== */ + #define R_GPTP_PTPCCC06_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC06_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC06_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC06_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC07 ======================================================== */ + #define R_GPTP_PTPCCC07_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC07_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC07_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC07_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC10 ======================================================== */ + #define R_GPTP_PTPCCC10_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC10_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPCCC11 ======================================================== */ + #define R_GPTP_PTPCCC11_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC11_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPCCC12 ======================================================== */ + #define R_GPTP_PTPCCC12_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC12_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPCCC13 ======================================================== */ + #define R_GPTP_PTPCCC13_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC13_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPCCC14 ======================================================== */ + #define R_GPTP_PTPCCC14_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC14_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPCCC15 ======================================================== */ + #define R_GPTP_PTPCCC15_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC15_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPCCC16 ======================================================== */ + #define R_GPTP_PTPCCC16_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC16_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPCCC17 ======================================================== */ + #define R_GPTP_PTPCCC17_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC17_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== PTPIS0 ========================================================= */ + #define R_GPTP_PTPIS0_MCCS_Pos (0UL) /*!< MCCS (Bit 0) */ + #define R_GPTP_PTPIS0_MCCS_Msk (0x3UL) /*!< MCCS (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPIS0_MCCOES_Pos (16UL) /*!< MCCOES (Bit 16) */ + #define R_GPTP_PTPIS0_MCCOES_Msk (0x30000UL) /*!< MCCOES (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPIE0 ========================================================= */ + #define R_GPTP_PTPIE0_MCCE_Pos (0UL) /*!< MCCE (Bit 0) */ + #define R_GPTP_PTPIE0_MCCE_Msk (0x3UL) /*!< MCCE (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPIE0_MCCOEE_Pos (16UL) /*!< MCCOEE (Bit 16) */ + #define R_GPTP_PTPIE0_MCCOEE_Msk (0x30000UL) /*!< MCCOEE (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPID0 ========================================================= */ + #define R_GPTP_PTPID0_MCCD_Pos (0UL) /*!< MCCD (Bit 0) */ + #define R_GPTP_PTPID0_MCCD_Msk (0x3UL) /*!< MCCD (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPID0_MCCOED_Pos (16UL) /*!< MCCOED (Bit 16) */ + #define R_GPTP_PTPID0_MCCOED_Msk (0x30000UL) /*!< MCCOED (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPIS1 ========================================================= */ + #define R_GPTP_PTPIS1_MCRMS_Pos (0UL) /*!< MCRMS (Bit 0) */ + #define R_GPTP_PTPIS1_MCRMS_Msk (0x3UL) /*!< MCRMS (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPIE1 ========================================================= */ + #define R_GPTP_PTPIE1_MCRME_Pos (0UL) /*!< MCRME (Bit 0) */ + #define R_GPTP_PTPIE1_MCRME_Msk (0x3UL) /*!< MCRME (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPID1 ========================================================= */ + #define R_GPTP_PTPID1_MCRMD_Pos (0UL) /*!< MCRMD (Bit 0) */ + #define R_GPTP_PTPID1_MCRMD_Msk (0x3UL) /*!< MCRMD (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPSCR0 ======================================================== */ + #define R_GPTP_PTPSCR0_TRSL_Pos (0UL) /*!< TRSL (Bit 0) */ + #define R_GPTP_PTPSCR0_TRSL_Msk (0x3UL) /*!< TRSL (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPSCR0_MCRSL_Pos (16UL) /*!< MCRSL (Bit 16) */ + #define R_GPTP_PTPSCR0_MCRSL_Msk (0x30000UL) /*!< MCRSL (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPSCR1 ======================================================== */ + #define R_GPTP_PTPSCR1_MRRSL_Pos (0UL) /*!< MRRSL (Bit 0) */ + #define R_GPTP_PTPSCR1_MRRSL_Msk (0x3UL) /*!< MRRSL (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPSCR1_MRRRSL_Pos (16UL) /*!< MRRRSL (Bit 16) */ + #define R_GPTP_PTPSCR1_MRRRSL_Msk (0x30000UL) /*!< MRRRSL (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPSCR2 ======================================================== */ + #define R_GPTP_PTPSCR2_CCRSL_Pos (0UL) /*!< CCRSL (Bit 0) */ + #define R_GPTP_PTPSCR2_CCRSL_Msk (0x3UL) /*!< CCRSL (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPSCR2_VRSL_Pos (16UL) /*!< VRSL (Bit 16) */ + #define R_GPTP_PTPSCR2_VRSL_Msk (0x10000UL) /*!< VRSL (Bitfield-Mask: 0x01) */ +/* ======================================================== POTCFGR ======================================================== */ + #define R_GPTP_POTCFGR_REFSEL_Pos (0UL) /*!< REFSEL (Bit 0) */ + #define R_GPTP_POTCFGR_REFSEL_Msk (0x1UL) /*!< REFSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== POTCR0 ========================================================= */ + #define R_GPTP_POTCR0_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_GPTP_POTCR0_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ======================================================== POTCR1 ========================================================= */ + #define R_GPTP_POTCR1_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_GPTP_POTCR1_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ======================================================== POTCR2 ========================================================= */ + #define R_GPTP_POTCR2_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_GPTP_POTCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ======================================================== POTCR3 ========================================================= */ + #define R_GPTP_POTCR3_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_GPTP_POTCR3_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ======================================================= POTSTRU0 ======================================================== */ +/* ======================================================= POTSTRU1 ======================================================== */ +/* ======================================================= POTSTRU2 ======================================================== */ +/* ======================================================= POTSTRU3 ======================================================== */ +/* ======================================================= POTSTRM0 ======================================================== */ +/* ======================================================= POTSTRM1 ======================================================== */ +/* ======================================================= POTSTRM2 ======================================================== */ +/* ======================================================= POTSTRM3 ======================================================== */ +/* ======================================================= POTSTRL0 ======================================================== */ +/* ======================================================= POTSTRL1 ======================================================== */ +/* ======================================================= POTSTRL2 ======================================================== */ +/* ======================================================= POTSTRL3 ======================================================== */ +/* ======================================================= POTPERU0 ======================================================== */ +/* ======================================================= POTPERU1 ======================================================== */ +/* ======================================================= POTPERU2 ======================================================== */ +/* ======================================================= POTPERU3 ======================================================== */ +/* ======================================================= POTPERM0 ======================================================== */ +/* ======================================================= POTPERM1 ======================================================== */ +/* ======================================================= POTPERM2 ======================================================== */ +/* ======================================================= POTPERM3 ======================================================== */ +/* ======================================================= POTPERL0 ======================================================== */ +/* ======================================================= POTPERL1 ======================================================== */ +/* ======================================================= POTPERL2 ======================================================== */ +/* ======================================================= POTPERL3 ======================================================== */ +/* ======================================================== POTPWR0 ======================================================== */ +/* ======================================================== POTPWR1 ======================================================== */ +/* ======================================================== POTPWR2 ======================================================== */ +/* ======================================================== POTPWR3 ======================================================== */ +/* ======================================================= POTCPRU0 ======================================================== */ +/* ======================================================= POTCPRU1 ======================================================== */ +/* ======================================================= POTCPRU2 ======================================================== */ +/* ======================================================= POTCPRU3 ======================================================== */ +/* ======================================================= POTCPRM0 ======================================================== */ +/* ======================================================= POTCPRM1 ======================================================== */ +/* ======================================================= POTCPRM2 ======================================================== */ +/* ======================================================= POTCPRM3 ======================================================== */ +/* ======================================================= POTCPRL0 ======================================================== */ +/* ======================================================= POTCPRL1 ======================================================== */ +/* ======================================================= POTCPRL2 ======================================================== */ +/* ======================================================= POTCPRL3 ======================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_GWCA0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GWMC ========================================================== */ + #define R_GWCA0_GWMC_OPC_Pos (0UL) /*!< OPC (Bit 0) */ + #define R_GWCA0_GWMC_OPC_Msk (0x3UL) /*!< OPC (Bitfield-Mask: 0x03) */ +/* ========================================================= GWMS ========================================================== */ + #define R_GWCA0_GWMS_OPS_Pos (0UL) /*!< OPS (Bit 0) */ + #define R_GWCA0_GWMS_OPS_Msk (0x3UL) /*!< OPS (Bitfield-Mask: 0x03) */ +/* ========================================================= GWIRC ========================================================= */ + #define R_GWCA0_GWIRC_IPVR0_Pos (0UL) /*!< IPVR0 (Bit 0) */ + #define R_GWCA0_GWIRC_IPVR0_Msk (0x7UL) /*!< IPVR0 (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWIRC_IPVR1_Pos (4UL) /*!< IPVR1 (Bit 4) */ + #define R_GWCA0_GWIRC_IPVR1_Msk (0x70UL) /*!< IPVR1 (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWIRC_IPVR2_Pos (8UL) /*!< IPVR2 (Bit 8) */ + #define R_GWCA0_GWIRC_IPVR2_Msk (0x700UL) /*!< IPVR2 (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWIRC_IPVR3_Pos (12UL) /*!< IPVR3 (Bit 12) */ + #define R_GWCA0_GWIRC_IPVR3_Msk (0x7000UL) /*!< IPVR3 (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWIRC_IPVR4_Pos (16UL) /*!< IPVR4 (Bit 16) */ + #define R_GWCA0_GWIRC_IPVR4_Msk (0x70000UL) /*!< IPVR4 (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWIRC_IPVR5_Pos (20UL) /*!< IPVR5 (Bit 20) */ + #define R_GWCA0_GWIRC_IPVR5_Msk (0x700000UL) /*!< IPVR5 (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWIRC_IPVR6_Pos (24UL) /*!< IPVR6 (Bit 24) */ + #define R_GWCA0_GWIRC_IPVR6_Msk (0x7000000UL) /*!< IPVR6 (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWIRC_IPVR7_Pos (28UL) /*!< IPVR7 (Bit 28) */ + #define R_GWCA0_GWIRC_IPVR7_Msk (0x70000000UL) /*!< IPVR7 (Bitfield-Mask: 0x07) */ +/* ======================================================== GWRDQSC ======================================================== */ + #define R_GWCA0_GWRDQSC_RDQSL0_Pos (0UL) /*!< RDQSL0 (Bit 0) */ + #define R_GWCA0_GWRDQSC_RDQSL0_Msk (0x1UL) /*!< RDQSL0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQSC_RDQSL1_Pos (1UL) /*!< RDQSL1 (Bit 1) */ + #define R_GWCA0_GWRDQSC_RDQSL1_Msk (0x2UL) /*!< RDQSL1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQSC_RDQSL2_Pos (2UL) /*!< RDQSL2 (Bit 2) */ + #define R_GWCA0_GWRDQSC_RDQSL2_Msk (0x4UL) /*!< RDQSL2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQSC_RDQSL3_Pos (3UL) /*!< RDQSL3 (Bit 3) */ + #define R_GWCA0_GWRDQSC_RDQSL3_Msk (0x8UL) /*!< RDQSL3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQSC_RDQSL4_Pos (4UL) /*!< RDQSL4 (Bit 4) */ + #define R_GWCA0_GWRDQSC_RDQSL4_Msk (0x10UL) /*!< RDQSL4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQSC_RDQSL5_Pos (5UL) /*!< RDQSL5 (Bit 5) */ + #define R_GWCA0_GWRDQSC_RDQSL5_Msk (0x20UL) /*!< RDQSL5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQSC_RDQSL6_Pos (6UL) /*!< RDQSL6 (Bit 6) */ + #define R_GWCA0_GWRDQSC_RDQSL6_Msk (0x40UL) /*!< RDQSL6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQSC_RDQSL7_Pos (7UL) /*!< RDQSL7 (Bit 7) */ + #define R_GWCA0_GWRDQSC_RDQSL7_Msk (0x80UL) /*!< RDQSL7 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWRDQC ========================================================= */ + #define R_GWCA0_GWRDQC_RDQD0_Pos (0UL) /*!< RDQD0 (Bit 0) */ + #define R_GWCA0_GWRDQC_RDQD0_Msk (0x1UL) /*!< RDQD0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQD1_Pos (1UL) /*!< RDQD1 (Bit 1) */ + #define R_GWCA0_GWRDQC_RDQD1_Msk (0x2UL) /*!< RDQD1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQD2_Pos (2UL) /*!< RDQD2 (Bit 2) */ + #define R_GWCA0_GWRDQC_RDQD2_Msk (0x4UL) /*!< RDQD2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQD3_Pos (3UL) /*!< RDQD3 (Bit 3) */ + #define R_GWCA0_GWRDQC_RDQD3_Msk (0x8UL) /*!< RDQD3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQD4_Pos (4UL) /*!< RDQD4 (Bit 4) */ + #define R_GWCA0_GWRDQC_RDQD4_Msk (0x10UL) /*!< RDQD4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQD5_Pos (5UL) /*!< RDQD5 (Bit 5) */ + #define R_GWCA0_GWRDQC_RDQD5_Msk (0x20UL) /*!< RDQD5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQD6_Pos (6UL) /*!< RDQD6 (Bit 6) */ + #define R_GWCA0_GWRDQC_RDQD6_Msk (0x40UL) /*!< RDQD6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQD7_Pos (7UL) /*!< RDQD7 (Bit 7) */ + #define R_GWCA0_GWRDQC_RDQD7_Msk (0x80UL) /*!< RDQD7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP0_Pos (16UL) /*!< RDQP0 (Bit 16) */ + #define R_GWCA0_GWRDQC_RDQP0_Msk (0x10000UL) /*!< RDQP0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP1_Pos (17UL) /*!< RDQP1 (Bit 17) */ + #define R_GWCA0_GWRDQC_RDQP1_Msk (0x20000UL) /*!< RDQP1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP2_Pos (18UL) /*!< RDQP2 (Bit 18) */ + #define R_GWCA0_GWRDQC_RDQP2_Msk (0x40000UL) /*!< RDQP2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP3_Pos (19UL) /*!< RDQP3 (Bit 19) */ + #define R_GWCA0_GWRDQC_RDQP3_Msk (0x80000UL) /*!< RDQP3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP4_Pos (20UL) /*!< RDQP4 (Bit 20) */ + #define R_GWCA0_GWRDQC_RDQP4_Msk (0x100000UL) /*!< RDQP4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP5_Pos (21UL) /*!< RDQP5 (Bit 21) */ + #define R_GWCA0_GWRDQC_RDQP5_Msk (0x200000UL) /*!< RDQP5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP6_Pos (22UL) /*!< RDQP6 (Bit 22) */ + #define R_GWCA0_GWRDQC_RDQP6_Msk (0x400000UL) /*!< RDQP6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP7_Pos (23UL) /*!< RDQP7 (Bit 23) */ + #define R_GWCA0_GWRDQC_RDQP7_Msk (0x800000UL) /*!< RDQP7 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWRDQAC ======================================================== */ + #define R_GWCA0_GWRDQAC_RDQA0_Pos (0UL) /*!< RDQA0 (Bit 0) */ + #define R_GWCA0_GWRDQAC_RDQA0_Msk (0xfUL) /*!< RDQA0 (Bitfield-Mask: 0x0f) */ + #define R_GWCA0_GWRDQAC_RDQA1_Pos (4UL) /*!< RDQA1 (Bit 4) */ + #define R_GWCA0_GWRDQAC_RDQA1_Msk (0xf0UL) /*!< RDQA1 (Bitfield-Mask: 0x0f) */ + #define R_GWCA0_GWRDQAC_RDQA2_Pos (8UL) /*!< RDQA2 (Bit 8) */ + #define R_GWCA0_GWRDQAC_RDQA2_Msk (0xf00UL) /*!< RDQA2 (Bitfield-Mask: 0x0f) */ + #define R_GWCA0_GWRDQAC_RDQA3_Pos (12UL) /*!< RDQA3 (Bit 12) */ + #define R_GWCA0_GWRDQAC_RDQA3_Msk (0xf000UL) /*!< RDQA3 (Bitfield-Mask: 0x0f) */ + #define R_GWCA0_GWRDQAC_RDQA4_Pos (16UL) /*!< RDQA4 (Bit 16) */ + #define R_GWCA0_GWRDQAC_RDQA4_Msk (0xf0000UL) /*!< RDQA4 (Bitfield-Mask: 0x0f) */ + #define R_GWCA0_GWRDQAC_RDQA5_Pos (20UL) /*!< RDQA5 (Bit 20) */ + #define R_GWCA0_GWRDQAC_RDQA5_Msk (0xf00000UL) /*!< RDQA5 (Bitfield-Mask: 0x0f) */ + #define R_GWCA0_GWRDQAC_RDQA6_Pos (24UL) /*!< RDQA6 (Bit 24) */ + #define R_GWCA0_GWRDQAC_RDQA6_Msk (0xf000000UL) /*!< RDQA6 (Bitfield-Mask: 0x0f) */ + #define R_GWCA0_GWRDQAC_RDQA7_Pos (28UL) /*!< RDQA7 (Bit 28) */ + #define R_GWCA0_GWRDQAC_RDQA7_Msk (0xf0000000UL) /*!< RDQA7 (Bitfield-Mask: 0x0f) */ +/* ========================================================= GWRGC ========================================================= */ + #define R_GWCA0_GWRGC_RCPT_Pos (0UL) /*!< RCPT (Bit 0) */ + #define R_GWCA0_GWRGC_RCPT_Msk (0x1UL) /*!< RCPT (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRMFSC0 ======================================================== */ + #define R_GWCA0_GWRMFSC0_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC0_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRMFSC1 ======================================================== */ + #define R_GWCA0_GWRMFSC1_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC1_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRMFSC2 ======================================================== */ + #define R_GWCA0_GWRMFSC2_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC2_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRMFSC3 ======================================================== */ + #define R_GWCA0_GWRMFSC3_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC3_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRMFSC4 ======================================================== */ + #define R_GWCA0_GWRMFSC4_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC4_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRMFSC5 ======================================================== */ + #define R_GWCA0_GWRMFSC5_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC5_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRMFSC6 ======================================================== */ + #define R_GWCA0_GWRMFSC6_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC6_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRMFSC7 ======================================================== */ + #define R_GWCA0_GWRMFSC7_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC7_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRDQDC0 ======================================================== */ + #define R_GWCA0_GWRDQDC0_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC0_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQDC1 ======================================================== */ + #define R_GWCA0_GWRDQDC1_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC1_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQDC2 ======================================================== */ + #define R_GWCA0_GWRDQDC2_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC2_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQDC3 ======================================================== */ + #define R_GWCA0_GWRDQDC3_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC3_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQDC4 ======================================================== */ + #define R_GWCA0_GWRDQDC4_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC4_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQDC5 ======================================================== */ + #define R_GWCA0_GWRDQDC5_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC5_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQDC6 ======================================================== */ + #define R_GWCA0_GWRDQDC6_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC6_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQDC7 ======================================================== */ + #define R_GWCA0_GWRDQDC7_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC7_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM0 ======================================================== */ + #define R_GWCA0_GWRDQM0_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM0_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM1 ======================================================== */ + #define R_GWCA0_GWRDQM1_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM1_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM2 ======================================================== */ + #define R_GWCA0_GWRDQM2_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM2_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM3 ======================================================== */ + #define R_GWCA0_GWRDQM3_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM3_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM4 ======================================================== */ + #define R_GWCA0_GWRDQM4_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM4_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM5 ======================================================== */ + #define R_GWCA0_GWRDQM5_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM5_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM6 ======================================================== */ + #define R_GWCA0_GWRDQM6_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM6_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM7 ======================================================== */ + #define R_GWCA0_GWRDQM7_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM7_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM0 ======================================================= */ + #define R_GWCA0_GWRDQMLM0_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM0_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM1 ======================================================= */ + #define R_GWCA0_GWRDQMLM1_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM1_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM2 ======================================================= */ + #define R_GWCA0_GWRDQMLM2_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM2_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM3 ======================================================= */ + #define R_GWCA0_GWRDQMLM3_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM3_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM4 ======================================================= */ + #define R_GWCA0_GWRDQMLM4_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM4_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM5 ======================================================= */ + #define R_GWCA0_GWRDQMLM5_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM5_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM6 ======================================================= */ + #define R_GWCA0_GWRDQMLM6_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM6_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM7 ======================================================= */ + #define R_GWCA0_GWRDQMLM7_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM7_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWMTIRM ======================================================== */ + #define R_GWCA0_GWMTIRM_MTIOG_Pos (0UL) /*!< MTIOG (Bit 0) */ + #define R_GWCA0_GWMTIRM_MTIOG_Msk (0x1UL) /*!< MTIOG (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWMTIRM_MTR_Pos (1UL) /*!< MTR (Bit 1) */ + #define R_GWCA0_GWMTIRM_MTR_Msk (0x2UL) /*!< MTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GWMSTLS ======================================================== */ + #define R_GWCA0_GWMSTLS_MNRCNL_Pos (0UL) /*!< MNRCNL (Bit 0) */ + #define R_GWCA0_GWMSTLS_MNRCNL_Msk (0x7fUL) /*!< MNRCNL (Bitfield-Mask: 0x7f) */ + #define R_GWCA0_GWMSTLS_MNL_Pos (8UL) /*!< MNL (Bit 8) */ + #define R_GWCA0_GWMSTLS_MNL_Msk (0x700UL) /*!< MNL (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWMSTLS_MSENL_Pos (16UL) /*!< MSENL (Bit 16) */ + #define R_GWCA0_GWMSTLS_MSENL_Msk (0x7f0000UL) /*!< MSENL (Bitfield-Mask: 0x7f) */ +/* ======================================================== GWMSTLR ======================================================== */ + #define R_GWCA0_GWMSTLR_MTLF_Pos (0UL) /*!< MTLF (Bit 0) */ + #define R_GWCA0_GWMSTLR_MTLF_Msk (0x1UL) /*!< MTLF (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWMSTLR_MTL_Pos (31UL) /*!< MTL (Bit 31) */ + #define R_GWCA0_GWMSTLR_MTL_Msk (0x80000000UL) /*!< MTL (Bitfield-Mask: 0x01) */ +/* ======================================================== GWMSTSS ======================================================== */ + #define R_GWCA0_GWMSTSS_MSENS_Pos (0UL) /*!< MSENS (Bit 0) */ + #define R_GWCA0_GWMSTSS_MSENS_Msk (0x7fUL) /*!< MSENS (Bitfield-Mask: 0x7f) */ +/* ======================================================== GWMSTSR ======================================================== */ + #define R_GWCA0_GWMSTSR_MNRCNR_Pos (0UL) /*!< MNRCNR (Bit 0) */ + #define R_GWCA0_GWMSTSR_MNRCNR_Msk (0x7fUL) /*!< MNRCNR (Bitfield-Mask: 0x7f) */ + #define R_GWCA0_GWMSTSR_MNR_Pos (8UL) /*!< MNR (Bit 8) */ + #define R_GWCA0_GWMSTSR_MNR_Msk (0x700UL) /*!< MNR (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWMSTSR_MTSEF_Pos (16UL) /*!< MTSEF (Bit 16) */ + #define R_GWCA0_GWMSTSR_MTSEF_Msk (0x10000UL) /*!< MTSEF (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWMSTSR_MTS_Pos (31UL) /*!< MTS (Bit 31) */ + #define R_GWCA0_GWMSTSR_MTS_Msk (0x80000000UL) /*!< MTS (Bitfield-Mask: 0x01) */ +/* ======================================================== GWMAC0 ========================================================= */ + #define R_GWCA0_GWMAC0_MAUP_Pos (0UL) /*!< MAUP (Bit 0) */ + #define R_GWCA0_GWMAC0_MAUP_Msk (0xffffUL) /*!< MAUP (Bitfield-Mask: 0xffff) */ +/* ======================================================== GWMAC1 ========================================================= */ + #define R_GWCA0_GWMAC1_MADP_Pos (0UL) /*!< MADP (Bit 0) */ + #define R_GWCA0_GWMAC1_MADP_Msk (0xffffffffUL) /*!< MADP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GWVCC ========================================================= */ + #define R_GWCA0_GWVCC_VIM_Pos (0UL) /*!< VIM (Bit 0) */ + #define R_GWCA0_GWVCC_VIM_Msk (0x1UL) /*!< VIM (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWVCC_CTVUM_Pos (8UL) /*!< CTVUM (Bit 8) */ + #define R_GWCA0_GWVCC_CTVUM_Msk (0x100UL) /*!< CTVUM (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWVCC_VEM_Pos (16UL) /*!< VEM (Bit 16) */ + #define R_GWCA0_GWVCC_VEM_Msk (0x70000UL) /*!< VEM (Bitfield-Mask: 0x07) */ +/* ========================================================= GWVTC ========================================================= */ + #define R_GWCA0_GWVTC_CTV_Pos (0UL) /*!< CTV (Bit 0) */ + #define R_GWCA0_GWVTC_CTV_Msk (0xfffUL) /*!< CTV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWVTC_CTP_Pos (12UL) /*!< CTP (Bit 12) */ + #define R_GWCA0_GWVTC_CTP_Msk (0x7000UL) /*!< CTP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWVTC_CTD_Pos (15UL) /*!< CTD (Bit 15) */ + #define R_GWCA0_GWVTC_CTD_Msk (0x8000UL) /*!< CTD (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWVTC_STV_Pos (16UL) /*!< STV (Bit 16) */ + #define R_GWCA0_GWVTC_STV_Msk (0xfff0000UL) /*!< STV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWVTC_STP_Pos (28UL) /*!< STP (Bit 28) */ + #define R_GWCA0_GWVTC_STP_Msk (0x70000000UL) /*!< STP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWVTC_STD_Pos (31UL) /*!< STD (Bit 31) */ + #define R_GWCA0_GWVTC_STD_Msk (0x80000000UL) /*!< STD (Bitfield-Mask: 0x01) */ +/* ======================================================== GWTTFC ========================================================= */ + #define R_GWCA0_GWTTFC_NT_Pos (0UL) /*!< NT (Bit 0) */ + #define R_GWCA0_GWTTFC_NT_Msk (0x1UL) /*!< NT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_RT_Pos (1UL) /*!< RT (Bit 1) */ + #define R_GWCA0_GWTTFC_RT_Msk (0x2UL) /*!< RT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_CST_Pos (2UL) /*!< CST (Bit 2) */ + #define R_GWCA0_GWTTFC_CST_Msk (0x4UL) /*!< CST (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_CSRT_Pos (3UL) /*!< CSRT (Bit 3) */ + #define R_GWCA0_GWTTFC_CSRT_Msk (0x8UL) /*!< CSRT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_CT_Pos (4UL) /*!< CT (Bit 4) */ + #define R_GWCA0_GWTTFC_CT_Msk (0x10UL) /*!< CT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_CRT_Pos (5UL) /*!< CRT (Bit 5) */ + #define R_GWCA0_GWTTFC_CRT_Msk (0x20UL) /*!< CRT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_SCT_Pos (6UL) /*!< SCT (Bit 6) */ + #define R_GWCA0_GWTTFC_SCT_Msk (0x40UL) /*!< SCT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_SCRT_Pos (7UL) /*!< SCRT (Bit 7) */ + #define R_GWCA0_GWTTFC_SCRT_Msk (0x80UL) /*!< SCRT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_UT_Pos (8UL) /*!< UT (Bit 8) */ + #define R_GWCA0_GWTTFC_UT_Msk (0x100UL) /*!< UT (Bitfield-Mask: 0x01) */ +/* ======================================================= GWTDCAC00 ======================================================= */ + #define R_GWCA0_GWTDCAC00_TSCCAUP_Pos (0UL) /*!< TSCCAUP (Bit 0) */ + #define R_GWCA0_GWTDCAC00_TSCCAUP_Msk (0xffUL) /*!< TSCCAUP (Bitfield-Mask: 0xff) */ +/* ======================================================= GWTDCAC10 ======================================================= */ + #define R_GWCA0_GWTDCAC10_TSCCADP_Pos (0UL) /*!< TSCCADP (Bit 0) */ + #define R_GWCA0_GWTDCAC10_TSCCADP_Msk (0xffffffffUL) /*!< TSCCADP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GWTDCAC01 ======================================================= */ + #define R_GWCA0_GWTDCAC01_TSCCAUP_Pos (0UL) /*!< TSCCAUP (Bit 0) */ + #define R_GWCA0_GWTDCAC01_TSCCAUP_Msk (0xffUL) /*!< TSCCAUP (Bitfield-Mask: 0xff) */ +/* ======================================================= GWTDCAC11 ======================================================= */ + #define R_GWCA0_GWTDCAC11_TSCCADP_Pos (0UL) /*!< TSCCADP (Bit 0) */ + #define R_GWCA0_GWTDCAC11_TSCCADP_Msk (0xffffffffUL) /*!< TSCCADP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GWTSDCC0 ======================================================== */ + #define R_GWCA0_GWTSDCC0_TE_Pos (0UL) /*!< TE (Bit 0) */ + #define R_GWCA0_GWTSDCC0_TE_Msk (0x1UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTSDCC0_DCS_Pos (1UL) /*!< DCS (Bit 1) */ + #define R_GWCA0_GWTSDCC0_DCS_Msk (0x6UL) /*!< DCS (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWTSDCC0_OSID_Pos (8UL) /*!< OSID (Bit 8) */ + #define R_GWCA0_GWTSDCC0_OSID_Msk (0x700UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================= GWTSDCC1 ======================================================== */ + #define R_GWCA0_GWTSDCC1_TE_Pos (0UL) /*!< TE (Bit 0) */ + #define R_GWCA0_GWTSDCC1_TE_Msk (0x1UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTSDCC1_DCS_Pos (1UL) /*!< DCS (Bit 1) */ + #define R_GWCA0_GWTSDCC1_DCS_Msk (0x6UL) /*!< DCS (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWTSDCC1_OSID_Pos (8UL) /*!< OSID (Bit 8) */ + #define R_GWCA0_GWTSDCC1_OSID_Msk (0x700UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWTSNM ========================================================= */ + #define R_GWCA0_GWTSNM_TNTR_Pos (0UL) /*!< TNTR (Bit 0) */ + #define R_GWCA0_GWTSNM_TNTR_Msk (0xffUL) /*!< TNTR (Bitfield-Mask: 0xff) */ +/* ======================================================== GWTSMNM ======================================================== */ + #define R_GWCA0_GWTSMNM_TMNTR_Pos (0UL) /*!< TMNTR (Bit 0) */ + #define R_GWCA0_GWTSMNM_TMNTR_Msk (0xffUL) /*!< TMNTR (Bitfield-Mask: 0xff) */ +/* ========================================================= GWAC ========================================================== */ + #define R_GWCA0_GWAC_AMPR_Pos (0UL) /*!< AMPR (Bit 0) */ + #define R_GWCA0_GWAC_AMPR_Msk (0x1UL) /*!< AMPR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWAC_AMP_Pos (1UL) /*!< AMP (Bit 1) */ + #define R_GWCA0_GWAC_AMP_Msk (0x2UL) /*!< AMP (Bitfield-Mask: 0x01) */ +/* ======================================================= GWDCBAC0 ======================================================== */ + #define R_GWCA0_GWDCBAC0_DCBAUP_Pos (0UL) /*!< DCBAUP (Bit 0) */ + #define R_GWCA0_GWDCBAC0_DCBAUP_Msk (0xffUL) /*!< DCBAUP (Bitfield-Mask: 0xff) */ +/* ======================================================= GWDCBAC1 ======================================================== */ + #define R_GWCA0_GWDCBAC1_DCBADP_Pos (0UL) /*!< DCBADP (Bit 0) */ + #define R_GWCA0_GWDCBAC1_DCBADP_Msk (0xffffffffUL) /*!< DCBADP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GWMDNC ========================================================= */ + #define R_GWCA0_GWMDNC_RXDMN_Pos (0UL) /*!< RXDMN (Bit 0) */ + #define R_GWCA0_GWMDNC_RXDMN_Msk (0x1fUL) /*!< RXDMN (Bitfield-Mask: 0x1f) */ + #define R_GWCA0_GWMDNC_TXDMN_Pos (8UL) /*!< TXDMN (Bit 8) */ + #define R_GWCA0_GWMDNC_TXDMN_Msk (0x1f00UL) /*!< TXDMN (Bitfield-Mask: 0x1f) */ + #define R_GWCA0_GWMDNC_TSDMN_Pos (16UL) /*!< TSDMN (Bit 16) */ + #define R_GWCA0_GWMDNC_TSDMN_Msk (0x30000UL) /*!< TSDMN (Bitfield-Mask: 0x03) */ +/* ======================================================== GWTRC0 ========================================================= */ +/* ======================================================== GWTRC1 ========================================================= */ +/* ======================================================== GWTPC0 ========================================================= */ + #define R_GWCA0_GWTPC0_PPPL0_Pos (0UL) /*!< PPPL0 (Bit 0) */ + #define R_GWCA0_GWTPC0_PPPL0_Msk (0x1UL) /*!< PPPL0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL1_Pos (1UL) /*!< PPPL1 (Bit 1) */ + #define R_GWCA0_GWTPC0_PPPL1_Msk (0x2UL) /*!< PPPL1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL2_Pos (2UL) /*!< PPPL2 (Bit 2) */ + #define R_GWCA0_GWTPC0_PPPL2_Msk (0x4UL) /*!< PPPL2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL3_Pos (3UL) /*!< PPPL3 (Bit 3) */ + #define R_GWCA0_GWTPC0_PPPL3_Msk (0x8UL) /*!< PPPL3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL4_Pos (4UL) /*!< PPPL4 (Bit 4) */ + #define R_GWCA0_GWTPC0_PPPL4_Msk (0x10UL) /*!< PPPL4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL5_Pos (5UL) /*!< PPPL5 (Bit 5) */ + #define R_GWCA0_GWTPC0_PPPL5_Msk (0x20UL) /*!< PPPL5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL6_Pos (6UL) /*!< PPPL6 (Bit 6) */ + #define R_GWCA0_GWTPC0_PPPL6_Msk (0x40UL) /*!< PPPL6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL7_Pos (7UL) /*!< PPPL7 (Bit 7) */ + #define R_GWCA0_GWTPC0_PPPL7_Msk (0x80UL) /*!< PPPL7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL8_Pos (8UL) /*!< PPPL8 (Bit 8) */ + #define R_GWCA0_GWTPC0_PPPL8_Msk (0x100UL) /*!< PPPL8 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWTPC1 ========================================================= */ + #define R_GWCA0_GWTPC1_PPPL0_Pos (0UL) /*!< PPPL0 (Bit 0) */ + #define R_GWCA0_GWTPC1_PPPL0_Msk (0x1UL) /*!< PPPL0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL1_Pos (1UL) /*!< PPPL1 (Bit 1) */ + #define R_GWCA0_GWTPC1_PPPL1_Msk (0x2UL) /*!< PPPL1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL2_Pos (2UL) /*!< PPPL2 (Bit 2) */ + #define R_GWCA0_GWTPC1_PPPL2_Msk (0x4UL) /*!< PPPL2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL3_Pos (3UL) /*!< PPPL3 (Bit 3) */ + #define R_GWCA0_GWTPC1_PPPL3_Msk (0x8UL) /*!< PPPL3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL4_Pos (4UL) /*!< PPPL4 (Bit 4) */ + #define R_GWCA0_GWTPC1_PPPL4_Msk (0x10UL) /*!< PPPL4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL5_Pos (5UL) /*!< PPPL5 (Bit 5) */ + #define R_GWCA0_GWTPC1_PPPL5_Msk (0x20UL) /*!< PPPL5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL6_Pos (6UL) /*!< PPPL6 (Bit 6) */ + #define R_GWCA0_GWTPC1_PPPL6_Msk (0x40UL) /*!< PPPL6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL7_Pos (7UL) /*!< PPPL7 (Bit 7) */ + #define R_GWCA0_GWTPC1_PPPL7_Msk (0x80UL) /*!< PPPL7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL8_Pos (8UL) /*!< PPPL8 (Bit 8) */ + #define R_GWCA0_GWTPC1_PPPL8_Msk (0x100UL) /*!< PPPL8 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWARIRM ======================================================== */ + #define R_GWCA0_GWARIRM_ARIOG_Pos (0UL) /*!< ARIOG (Bit 0) */ + #define R_GWCA0_GWARIRM_ARIOG_Msk (0x1UL) /*!< ARIOG (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWARIRM_ARR_Pos (1UL) /*!< ARR (Bit 1) */ + #define R_GWCA0_GWARIRM_ARR_Msk (0x2UL) /*!< ARR (Bitfield-Mask: 0x01) */ +/* ======================================================== GWDCC0 ========================================================= */ + #define R_GWCA0_GWDCC0_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC0_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC0_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC0_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC0_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC0_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC0_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC0_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC0_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC0_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC0_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC0_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC0_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC0_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC0_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC0_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC1 ========================================================= */ + #define R_GWCA0_GWDCC1_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC1_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC1_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC1_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC1_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC1_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC1_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC1_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC1_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC1_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC1_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC1_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC1_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC1_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC1_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC1_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC2 ========================================================= */ + #define R_GWCA0_GWDCC2_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC2_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC2_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC2_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC2_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC2_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC2_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC2_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC2_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC2_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC2_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC2_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC2_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC2_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC2_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC2_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC3 ========================================================= */ + #define R_GWCA0_GWDCC3_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC3_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC3_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC3_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC3_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC3_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC3_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC3_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC3_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC3_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC3_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC3_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC3_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC3_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC3_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC3_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC4 ========================================================= */ + #define R_GWCA0_GWDCC4_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC4_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC4_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC4_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC4_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC4_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC4_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC4_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC4_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC4_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC4_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC4_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC4_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC4_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC4_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC4_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC5 ========================================================= */ + #define R_GWCA0_GWDCC5_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC5_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC5_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC5_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC5_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC5_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC5_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC5_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC5_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC5_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC5_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC5_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC5_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC5_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC5_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC5_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC6 ========================================================= */ + #define R_GWCA0_GWDCC6_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC6_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC6_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC6_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC6_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC6_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC6_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC6_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC6_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC6_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC6_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC6_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC6_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC6_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC6_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC6_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC7 ========================================================= */ + #define R_GWCA0_GWDCC7_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC7_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC7_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC7_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC7_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC7_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC7_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC7_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC7_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC7_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC7_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC7_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC7_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC7_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC7_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC7_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC8 ========================================================= */ + #define R_GWCA0_GWDCC8_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC8_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC8_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC8_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC8_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC8_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC8_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC8_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC8_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC8_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC8_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC8_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC8_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC8_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC8_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC8_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC9 ========================================================= */ + #define R_GWCA0_GWDCC9_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC9_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC9_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC9_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC9_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC9_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC9_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC9_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC9_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC9_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC9_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC9_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC9_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC9_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC9_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC9_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC10 ======================================================== */ + #define R_GWCA0_GWDCC10_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC10_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC10_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC10_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC10_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC10_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC10_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC10_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC10_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC10_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC10_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC10_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC10_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC10_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC10_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC10_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC11 ======================================================== */ + #define R_GWCA0_GWDCC11_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC11_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC11_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC11_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC11_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC11_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC11_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC11_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC11_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC11_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC11_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC11_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC11_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC11_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC11_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC11_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC12 ======================================================== */ + #define R_GWCA0_GWDCC12_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC12_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC12_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC12_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC12_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC12_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC12_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC12_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC12_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC12_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC12_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC12_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC12_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC12_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC12_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC12_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC13 ======================================================== */ + #define R_GWCA0_GWDCC13_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC13_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC13_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC13_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC13_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC13_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC13_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC13_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC13_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC13_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC13_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC13_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC13_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC13_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC13_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC13_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC14 ======================================================== */ + #define R_GWCA0_GWDCC14_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC14_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC14_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC14_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC14_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC14_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC14_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC14_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC14_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC14_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC14_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC14_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC14_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC14_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC14_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC14_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC15 ======================================================== */ + #define R_GWCA0_GWDCC15_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC15_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC15_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC15_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC15_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC15_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC15_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC15_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC15_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC15_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC15_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC15_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC15_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC15_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC15_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC15_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC16 ======================================================== */ + #define R_GWCA0_GWDCC16_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC16_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC16_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC16_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC16_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC16_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC16_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC16_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC16_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC16_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC16_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC16_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC16_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC16_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC16_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC16_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC17 ======================================================== */ + #define R_GWCA0_GWDCC17_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC17_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC17_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC17_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC17_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC17_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC17_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC17_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC17_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC17_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC17_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC17_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC17_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC17_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC17_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC17_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC18 ======================================================== */ + #define R_GWCA0_GWDCC18_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC18_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC18_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC18_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC18_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC18_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC18_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC18_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC18_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC18_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC18_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC18_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC18_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC18_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC18_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC18_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC19 ======================================================== */ + #define R_GWCA0_GWDCC19_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC19_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC19_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC19_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC19_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC19_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC19_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC19_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC19_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC19_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC19_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC19_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC19_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC19_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC19_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC19_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC20 ======================================================== */ + #define R_GWCA0_GWDCC20_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC20_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC20_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC20_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC20_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC20_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC20_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC20_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC20_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC20_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC20_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC20_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC20_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC20_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC20_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC20_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC21 ======================================================== */ + #define R_GWCA0_GWDCC21_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC21_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC21_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC21_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC21_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC21_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC21_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC21_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC21_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC21_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC21_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC21_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC21_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC21_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC21_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC21_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC22 ======================================================== */ + #define R_GWCA0_GWDCC22_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC22_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC22_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC22_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC22_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC22_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC22_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC22_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC22_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC22_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC22_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC22_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC22_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC22_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC22_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC22_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC23 ======================================================== */ + #define R_GWCA0_GWDCC23_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC23_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC23_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC23_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC23_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC23_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC23_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC23_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC23_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC23_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC23_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC23_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC23_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC23_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC23_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC23_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC24 ======================================================== */ + #define R_GWCA0_GWDCC24_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC24_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC24_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC24_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC24_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC24_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC24_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC24_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC24_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC24_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC24_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC24_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC24_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC24_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC24_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC24_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC25 ======================================================== */ + #define R_GWCA0_GWDCC25_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC25_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC25_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC25_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC25_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC25_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC25_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC25_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC25_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC25_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC25_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC25_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC25_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC25_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC25_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC25_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC26 ======================================================== */ + #define R_GWCA0_GWDCC26_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC26_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC26_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC26_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC26_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC26_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC26_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC26_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC26_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC26_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC26_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC26_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC26_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC26_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC26_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC26_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC27 ======================================================== */ + #define R_GWCA0_GWDCC27_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC27_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC27_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC27_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC27_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC27_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC27_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC27_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC27_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC27_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC27_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC27_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC27_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC27_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC27_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC27_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC28 ======================================================== */ + #define R_GWCA0_GWDCC28_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC28_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC28_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC28_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC28_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC28_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC28_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC28_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC28_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC28_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC28_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC28_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC28_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC28_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC28_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC28_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC29 ======================================================== */ + #define R_GWCA0_GWDCC29_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC29_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC29_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC29_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC29_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC29_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC29_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC29_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC29_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC29_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC29_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC29_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC29_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC29_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC29_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC29_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC30 ======================================================== */ + #define R_GWCA0_GWDCC30_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC30_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC30_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC30_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC30_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC30_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC30_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC30_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC30_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC30_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC30_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC30_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC30_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC30_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC30_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC30_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC31 ======================================================== */ + #define R_GWCA0_GWDCC31_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC31_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC31_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC31_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC31_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC31_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC31_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC31_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC31_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC31_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC31_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC31_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC31_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC31_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC31_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC31_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC32 ======================================================== */ + #define R_GWCA0_GWDCC32_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC32_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC32_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC32_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC32_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC32_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC32_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC32_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC32_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC32_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC32_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC32_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC32_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC32_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC32_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC32_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC33 ======================================================== */ + #define R_GWCA0_GWDCC33_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC33_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC33_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC33_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC33_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC33_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC33_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC33_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC33_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC33_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC33_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC33_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC33_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC33_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC33_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC33_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC34 ======================================================== */ + #define R_GWCA0_GWDCC34_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC34_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC34_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC34_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC34_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC34_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC34_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC34_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC34_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC34_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC34_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC34_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC34_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC34_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC34_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC34_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC35 ======================================================== */ + #define R_GWCA0_GWDCC35_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC35_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC35_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC35_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC35_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC35_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC35_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC35_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC35_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC35_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC35_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC35_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC35_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC35_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC35_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC35_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC36 ======================================================== */ + #define R_GWCA0_GWDCC36_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC36_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC36_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC36_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC36_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC36_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC36_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC36_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC36_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC36_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC36_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC36_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC36_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC36_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC36_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC36_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC37 ======================================================== */ + #define R_GWCA0_GWDCC37_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC37_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC37_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC37_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC37_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC37_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC37_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC37_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC37_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC37_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC37_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC37_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC37_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC37_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC37_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC37_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC38 ======================================================== */ + #define R_GWCA0_GWDCC38_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC38_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC38_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC38_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC38_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC38_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC38_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC38_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC38_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC38_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC38_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC38_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC38_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC38_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC38_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC38_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC39 ======================================================== */ + #define R_GWCA0_GWDCC39_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC39_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC39_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC39_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC39_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC39_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC39_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC39_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC39_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC39_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC39_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC39_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC39_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC39_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC39_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC39_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC40 ======================================================== */ + #define R_GWCA0_GWDCC40_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC40_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC40_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC40_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC40_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC40_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC40_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC40_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC40_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC40_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC40_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC40_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC40_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC40_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC40_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC40_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC41 ======================================================== */ + #define R_GWCA0_GWDCC41_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC41_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC41_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC41_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC41_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC41_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC41_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC41_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC41_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC41_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC41_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC41_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC41_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC41_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC41_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC41_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC42 ======================================================== */ + #define R_GWCA0_GWDCC42_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC42_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC42_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC42_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC42_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC42_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC42_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC42_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC42_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC42_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC42_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC42_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC42_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC42_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC42_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC42_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC43 ======================================================== */ + #define R_GWCA0_GWDCC43_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC43_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC43_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC43_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC43_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC43_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC43_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC43_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC43_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC43_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC43_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC43_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC43_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC43_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC43_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC43_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC44 ======================================================== */ + #define R_GWCA0_GWDCC44_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC44_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC44_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC44_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC44_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC44_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC44_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC44_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC44_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC44_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC44_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC44_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC44_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC44_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC44_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC44_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC45 ======================================================== */ + #define R_GWCA0_GWDCC45_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC45_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC45_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC45_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC45_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC45_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC45_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC45_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC45_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC45_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC45_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC45_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC45_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC45_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC45_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC45_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC46 ======================================================== */ + #define R_GWCA0_GWDCC46_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC46_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC46_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC46_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC46_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC46_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC46_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC46_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC46_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC46_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC46_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC46_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC46_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC46_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC46_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC46_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC47 ======================================================== */ + #define R_GWCA0_GWDCC47_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC47_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC47_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC47_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC47_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC47_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC47_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC47_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC47_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC47_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC47_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC47_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC47_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC47_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC47_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC47_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC48 ======================================================== */ + #define R_GWCA0_GWDCC48_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC48_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC48_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC48_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC48_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC48_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC48_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC48_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC48_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC48_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC48_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC48_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC48_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC48_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC48_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC48_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC49 ======================================================== */ + #define R_GWCA0_GWDCC49_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC49_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC49_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC49_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC49_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC49_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC49_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC49_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC49_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC49_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC49_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC49_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC49_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC49_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC49_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC49_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC50 ======================================================== */ + #define R_GWCA0_GWDCC50_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC50_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC50_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC50_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC50_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC50_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC50_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC50_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC50_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC50_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC50_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC50_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC50_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC50_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC50_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC50_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC51 ======================================================== */ + #define R_GWCA0_GWDCC51_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC51_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC51_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC51_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC51_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC51_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC51_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC51_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC51_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC51_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC51_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC51_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC51_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC51_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC51_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC51_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC52 ======================================================== */ + #define R_GWCA0_GWDCC52_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC52_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC52_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC52_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC52_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC52_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC52_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC52_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC52_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC52_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC52_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC52_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC52_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC52_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC52_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC52_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC53 ======================================================== */ + #define R_GWCA0_GWDCC53_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC53_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC53_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC53_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC53_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC53_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC53_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC53_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC53_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC53_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC53_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC53_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC53_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC53_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC53_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC53_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC54 ======================================================== */ + #define R_GWCA0_GWDCC54_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC54_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC54_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC54_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC54_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC54_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC54_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC54_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC54_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC54_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC54_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC54_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC54_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC54_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC54_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC54_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC55 ======================================================== */ + #define R_GWCA0_GWDCC55_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC55_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC55_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC55_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC55_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC55_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC55_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC55_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC55_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC55_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC55_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC55_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC55_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC55_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC55_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC55_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC56 ======================================================== */ + #define R_GWCA0_GWDCC56_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC56_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC56_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC56_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC56_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC56_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC56_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC56_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC56_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC56_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC56_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC56_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC56_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC56_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC56_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC56_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC57 ======================================================== */ + #define R_GWCA0_GWDCC57_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC57_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC57_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC57_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC57_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC57_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC57_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC57_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC57_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC57_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC57_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC57_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC57_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC57_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC57_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC57_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC58 ======================================================== */ + #define R_GWCA0_GWDCC58_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC58_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC58_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC58_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC58_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC58_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC58_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC58_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC58_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC58_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC58_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC58_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC58_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC58_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC58_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC58_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC59 ======================================================== */ + #define R_GWCA0_GWDCC59_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC59_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC59_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC59_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC59_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC59_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC59_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC59_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC59_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC59_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC59_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC59_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC59_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC59_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC59_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC59_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC60 ======================================================== */ + #define R_GWCA0_GWDCC60_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC60_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC60_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC60_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC60_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC60_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC60_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC60_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC60_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC60_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC60_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC60_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC60_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC60_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC60_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC60_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC61 ======================================================== */ + #define R_GWCA0_GWDCC61_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC61_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC61_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC61_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC61_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC61_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC61_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC61_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC61_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC61_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC61_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC61_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC61_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC61_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC61_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC61_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC62 ======================================================== */ + #define R_GWCA0_GWDCC62_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC62_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC62_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC62_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC62_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC62_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC62_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC62_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC62_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC62_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC62_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC62_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC62_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC62_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC62_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC62_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC63 ======================================================== */ + #define R_GWCA0_GWDCC63_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC63_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC63_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC63_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC63_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC63_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC63_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC63_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC63_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC63_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC63_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC63_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC63_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC63_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC63_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC63_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWAARSS ======================================================== */ + #define R_GWCA0_GWAARSS_AARA_Pos (0UL) /*!< AARA (Bit 0) */ + #define R_GWCA0_GWAARSS_AARA_Msk (0x7fUL) /*!< AARA (Bitfield-Mask: 0x7f) */ +/* ======================================================= GWAARSR0 ======================================================== */ + #define R_GWCA0_GWAARSR0_ACARU_Pos (0UL) /*!< ACARU (Bit 0) */ + #define R_GWCA0_GWAARSR0_ACARU_Msk (0xffUL) /*!< ACARU (Bitfield-Mask: 0xff) */ + #define R_GWCA0_GWAARSR0_AARSEF_Pos (16UL) /*!< AARSEF (Bit 16) */ + #define R_GWCA0_GWAARSR0_AARSEF_Msk (0x10000UL) /*!< AARSEF (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWAARSR0_AARSSF_Pos (17UL) /*!< AARSSF (Bit 17) */ + #define R_GWCA0_GWAARSR0_AARSSF_Msk (0x20000UL) /*!< AARSSF (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWAARSR0_AARS_Pos (31UL) /*!< AARS (Bit 31) */ + #define R_GWCA0_GWAARSR0_AARS_Msk (0x80000000UL) /*!< AARS (Bitfield-Mask: 0x01) */ +/* ======================================================= GWAARSR1 ======================================================== */ + #define R_GWCA0_GWAARSR1_ACARD_Pos (0UL) /*!< ACARD (Bit 0) */ + #define R_GWCA0_GWAARSR1_ACARD_Msk (0xffffffffUL) /*!< ACARD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GWIDAUAS0 ======================================================= */ + #define R_GWCA0_GWIDAUAS0_IDAUAS_Pos (0UL) /*!< IDAUAS (Bit 0) */ + #define R_GWCA0_GWIDAUAS0_IDAUAS_Msk (0xffffffUL) /*!< IDAUAS (Bitfield-Mask: 0xffffff) */ +/* ======================================================= GWIDAUAS1 ======================================================= */ + #define R_GWCA0_GWIDAUAS1_IDAUAS_Pos (0UL) /*!< IDAUAS (Bit 0) */ + #define R_GWCA0_GWIDAUAS1_IDAUAS_Msk (0xffffffUL) /*!< IDAUAS (Bitfield-Mask: 0xffffff) */ +/* ======================================================= GWIDAUAS2 ======================================================= */ + #define R_GWCA0_GWIDAUAS2_IDAUAS_Pos (0UL) /*!< IDAUAS (Bit 0) */ + #define R_GWCA0_GWIDAUAS2_IDAUAS_Msk (0xffffffUL) /*!< IDAUAS (Bitfield-Mask: 0xffffff) */ +/* ======================================================= GWIDAUAS3 ======================================================= */ + #define R_GWCA0_GWIDAUAS3_IDAUAS_Pos (0UL) /*!< IDAUAS (Bit 0) */ + #define R_GWCA0_GWIDAUAS3_IDAUAS_Msk (0xffffffUL) /*!< IDAUAS (Bitfield-Mask: 0xffffff) */ +/* ======================================================= GWIDASM0 ======================================================== */ + #define R_GWCA0_GWIDASM0_IDAS_Pos (0UL) /*!< IDAS (Bit 0) */ + #define R_GWCA0_GWIDASM0_IDAS_Msk (0xffffffUL) /*!< IDAS (Bitfield-Mask: 0xffffff) */ +/* ======================================================= GWIDASM1 ======================================================== */ + #define R_GWCA0_GWIDASM1_IDAS_Pos (0UL) /*!< IDAS (Bit 0) */ + #define R_GWCA0_GWIDASM1_IDAS_Msk (0xffffffUL) /*!< IDAS (Bitfield-Mask: 0xffffff) */ +/* ======================================================= GWIDASM2 ======================================================== */ + #define R_GWCA0_GWIDASM2_IDAS_Pos (0UL) /*!< IDAS (Bit 0) */ + #define R_GWCA0_GWIDASM2_IDAS_Msk (0xffffffUL) /*!< IDAS (Bitfield-Mask: 0xffffff) */ +/* ======================================================= GWIDASM3 ======================================================== */ + #define R_GWCA0_GWIDASM3_IDAS_Pos (0UL) /*!< IDAS (Bit 0) */ + #define R_GWCA0_GWIDASM3_IDAS_Msk (0xffffffUL) /*!< IDAS (Bitfield-Mask: 0xffffff) */ +/* ====================================================== GWIDASAM00 ======================================================= */ + #define R_GWCA0_GWIDASAM00_IDASAU_Pos (0UL) /*!< IDASAU (Bit 0) */ + #define R_GWCA0_GWIDASAM00_IDASAU_Msk (0xffUL) /*!< IDASAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDASAM10 ======================================================= */ + #define R_GWCA0_GWIDASAM10_IDASAL_Pos (0UL) /*!< IDASAL (Bit 0) */ + #define R_GWCA0_GWIDASAM10_IDASAL_Msk (0xffffffffUL) /*!< IDASAL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWIDASAM01 ======================================================= */ + #define R_GWCA0_GWIDASAM01_IDASAU_Pos (0UL) /*!< IDASAU (Bit 0) */ + #define R_GWCA0_GWIDASAM01_IDASAU_Msk (0xffUL) /*!< IDASAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDASAM11 ======================================================= */ + #define R_GWCA0_GWIDASAM11_IDASAL_Pos (0UL) /*!< IDASAL (Bit 0) */ + #define R_GWCA0_GWIDASAM11_IDASAL_Msk (0xffffffffUL) /*!< IDASAL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWIDASAM02 ======================================================= */ + #define R_GWCA0_GWIDASAM02_IDASAU_Pos (0UL) /*!< IDASAU (Bit 0) */ + #define R_GWCA0_GWIDASAM02_IDASAU_Msk (0xffUL) /*!< IDASAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDASAM12 ======================================================= */ + #define R_GWCA0_GWIDASAM12_IDASAL_Pos (0UL) /*!< IDASAL (Bit 0) */ + #define R_GWCA0_GWIDASAM12_IDASAL_Msk (0xffffffffUL) /*!< IDASAL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWIDASAM03 ======================================================= */ + #define R_GWCA0_GWIDASAM03_IDASAU_Pos (0UL) /*!< IDASAU (Bit 0) */ + #define R_GWCA0_GWIDASAM03_IDASAU_Msk (0xffUL) /*!< IDASAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDASAM13 ======================================================= */ + #define R_GWCA0_GWIDASAM13_IDASAL_Pos (0UL) /*!< IDASAL (Bit 0) */ + #define R_GWCA0_GWIDASAM13_IDASAL_Msk (0xffffffffUL) /*!< IDASAL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWIDACAM00 ======================================================= */ + #define R_GWCA0_GWIDACAM00_IDACAU_Pos (0UL) /*!< IDACAU (Bit 0) */ + #define R_GWCA0_GWIDACAM00_IDACAU_Msk (0xffUL) /*!< IDACAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDACAM10 ======================================================= */ + #define R_GWCA0_GWIDACAM10_IDACAL_Pos (0UL) /*!< IDACAL (Bit 0) */ + #define R_GWCA0_GWIDACAM10_IDACAL_Msk (0xffffffffUL) /*!< IDACAL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWIDACAM01 ======================================================= */ + #define R_GWCA0_GWIDACAM01_IDACAU_Pos (0UL) /*!< IDACAU (Bit 0) */ + #define R_GWCA0_GWIDACAM01_IDACAU_Msk (0xffUL) /*!< IDACAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDACAM11 ======================================================= */ + #define R_GWCA0_GWIDACAM11_IDACAL_Pos (0UL) /*!< IDACAL (Bit 0) */ + #define R_GWCA0_GWIDACAM11_IDACAL_Msk (0xffffffffUL) /*!< IDACAL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWIDACAM02 ======================================================= */ + #define R_GWCA0_GWIDACAM02_IDACAU_Pos (0UL) /*!< IDACAU (Bit 0) */ + #define R_GWCA0_GWIDACAM02_IDACAU_Msk (0xffUL) /*!< IDACAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDACAM12 ======================================================= */ + #define R_GWCA0_GWIDACAM12_IDACAL_Pos (0UL) /*!< IDACAL (Bit 0) */ + #define R_GWCA0_GWIDACAM12_IDACAL_Msk (0xffffffffUL) /*!< IDACAL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWIDACAM03 ======================================================= */ + #define R_GWCA0_GWIDACAM03_IDACAU_Pos (0UL) /*!< IDACAU (Bit 0) */ + #define R_GWCA0_GWIDACAM03_IDACAU_Msk (0xffUL) /*!< IDACAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDACAM13 ======================================================= */ + #define R_GWCA0_GWIDACAM13_IDACAL_Pos (0UL) /*!< IDACAL (Bit 0) */ + #define R_GWCA0_GWIDACAM13_IDACAL_Msk (0xffffffffUL) /*!< IDACAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GWGRLC ========================================================= */ + #define R_GWCA0_GWGRLC_GRLIV_Pos (0UL) /*!< GRLIV (Bit 0) */ + #define R_GWCA0_GWGRLC_GRLIV_Msk (0xffffUL) /*!< GRLIV (Bitfield-Mask: 0xffff) */ + #define R_GWCA0_GWGRLC_GRLE_Pos (16UL) /*!< GRLE (Bit 16) */ + #define R_GWCA0_GWGRLC_GRLE_Msk (0x10000UL) /*!< GRLE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWGRLC_GRLULRS_Pos (17UL) /*!< GRLULRS (Bit 17) */ + #define R_GWCA0_GWGRLC_GRLULRS_Msk (0x20000UL) /*!< GRLULRS (Bitfield-Mask: 0x01) */ +/* ======================================================= GWGRLULC ======================================================== */ + #define R_GWCA0_GWGRLULC_GRLUL_Pos (0UL) /*!< GRLUL (Bit 0) */ + #define R_GWCA0_GWGRLULC_GRLUL_Msk (0xffffffUL) /*!< GRLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC0 ========================================================= */ + #define R_GWCA0_GWRLC0_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC0_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC0_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC0_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC0 ======================================================== */ + #define R_GWCA0_GWRLULC0_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC0_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC1 ========================================================= */ + #define R_GWCA0_GWRLC1_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC1_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC1_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC1_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC1 ======================================================== */ + #define R_GWCA0_GWRLULC1_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC1_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC2 ========================================================= */ + #define R_GWCA0_GWRLC2_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC2_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC2_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC2_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC2 ======================================================== */ + #define R_GWCA0_GWRLULC2_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC2_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC3 ========================================================= */ + #define R_GWCA0_GWRLC3_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC3_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC3_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC3_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC3 ======================================================== */ + #define R_GWCA0_GWRLULC3_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC3_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC4 ========================================================= */ + #define R_GWCA0_GWRLC4_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC4_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC4_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC4_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC4 ======================================================== */ + #define R_GWCA0_GWRLULC4_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC4_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC5 ========================================================= */ + #define R_GWCA0_GWRLC5_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC5_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC5_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC5_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC5 ======================================================== */ + #define R_GWCA0_GWRLULC5_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC5_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC6 ========================================================= */ + #define R_GWCA0_GWRLC6_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC6_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC6_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC6_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC6 ======================================================== */ + #define R_GWCA0_GWRLULC6_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC6_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC7 ========================================================= */ + #define R_GWCA0_GWRLC7_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC7_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC7_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC7_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC7 ======================================================== */ + #define R_GWCA0_GWRLULC7_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC7_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWIDPC ========================================================= */ + #define R_GWCA0_GWIDPC_IDPV_Pos (0UL) /*!< IDPV (Bit 0) */ + #define R_GWCA0_GWIDPC_IDPV_Msk (0x3ffUL) /*!< IDPV (Bitfield-Mask: 0x3ff) */ +/* ======================================================== GWIDC0 ========================================================= */ + #define R_GWCA0_GWIDC0_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC0_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC1 ========================================================= */ + #define R_GWCA0_GWIDC1_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC1_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC2 ========================================================= */ + #define R_GWCA0_GWIDC2_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC2_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC3 ========================================================= */ + #define R_GWCA0_GWIDC3_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC3_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC4 ========================================================= */ + #define R_GWCA0_GWIDC4_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC4_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC5 ========================================================= */ + #define R_GWCA0_GWIDC5_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC5_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC6 ========================================================= */ + #define R_GWCA0_GWIDC6_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC6_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC7 ========================================================= */ + #define R_GWCA0_GWIDC7_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC7_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC8 ========================================================= */ + #define R_GWCA0_GWIDC8_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC8_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC9 ========================================================= */ + #define R_GWCA0_GWIDC9_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC9_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC10 ======================================================== */ + #define R_GWCA0_GWIDC10_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC10_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC11 ======================================================== */ + #define R_GWCA0_GWIDC11_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC11_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC12 ======================================================== */ + #define R_GWCA0_GWIDC12_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC12_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC13 ======================================================== */ + #define R_GWCA0_GWIDC13_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC13_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC14 ======================================================== */ + #define R_GWCA0_GWIDC14_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC14_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC15 ======================================================== */ + #define R_GWCA0_GWIDC15_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC15_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC16 ======================================================== */ + #define R_GWCA0_GWIDC16_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC16_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC17 ======================================================== */ + #define R_GWCA0_GWIDC17_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC17_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC18 ======================================================== */ + #define R_GWCA0_GWIDC18_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC18_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC19 ======================================================== */ + #define R_GWCA0_GWIDC19_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC19_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC20 ======================================================== */ + #define R_GWCA0_GWIDC20_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC20_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC21 ======================================================== */ + #define R_GWCA0_GWIDC21_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC21_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC22 ======================================================== */ + #define R_GWCA0_GWIDC22_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC22_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC23 ======================================================== */ + #define R_GWCA0_GWIDC23_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC23_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC24 ======================================================== */ + #define R_GWCA0_GWIDC24_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC24_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC25 ======================================================== */ + #define R_GWCA0_GWIDC25_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC25_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC26 ======================================================== */ + #define R_GWCA0_GWIDC26_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC26_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC27 ======================================================== */ + #define R_GWCA0_GWIDC27_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC27_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC28 ======================================================== */ + #define R_GWCA0_GWIDC28_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC28_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC29 ======================================================== */ + #define R_GWCA0_GWIDC29_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC29_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC30 ======================================================== */ + #define R_GWCA0_GWIDC30_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC30_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC31 ======================================================== */ + #define R_GWCA0_GWIDC31_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC31_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC32 ======================================================== */ + #define R_GWCA0_GWIDC32_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC32_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC33 ======================================================== */ + #define R_GWCA0_GWIDC33_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC33_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC34 ======================================================== */ + #define R_GWCA0_GWIDC34_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC34_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC35 ======================================================== */ + #define R_GWCA0_GWIDC35_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC35_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC36 ======================================================== */ + #define R_GWCA0_GWIDC36_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC36_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC37 ======================================================== */ + #define R_GWCA0_GWIDC37_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC37_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC38 ======================================================== */ + #define R_GWCA0_GWIDC38_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC38_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC39 ======================================================== */ + #define R_GWCA0_GWIDC39_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC39_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC40 ======================================================== */ + #define R_GWCA0_GWIDC40_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC40_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC41 ======================================================== */ + #define R_GWCA0_GWIDC41_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC41_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC42 ======================================================== */ + #define R_GWCA0_GWIDC42_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC42_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC43 ======================================================== */ + #define R_GWCA0_GWIDC43_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC43_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC44 ======================================================== */ + #define R_GWCA0_GWIDC44_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC44_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC45 ======================================================== */ + #define R_GWCA0_GWIDC45_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC45_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC46 ======================================================== */ + #define R_GWCA0_GWIDC46_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC46_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC47 ======================================================== */ + #define R_GWCA0_GWIDC47_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC47_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC48 ======================================================== */ + #define R_GWCA0_GWIDC48_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC48_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC49 ======================================================== */ + #define R_GWCA0_GWIDC49_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC49_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC50 ======================================================== */ + #define R_GWCA0_GWIDC50_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC50_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC51 ======================================================== */ + #define R_GWCA0_GWIDC51_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC51_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC52 ======================================================== */ + #define R_GWCA0_GWIDC52_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC52_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC53 ======================================================== */ + #define R_GWCA0_GWIDC53_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC53_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC54 ======================================================== */ + #define R_GWCA0_GWIDC54_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC54_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC55 ======================================================== */ + #define R_GWCA0_GWIDC55_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC55_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC56 ======================================================== */ + #define R_GWCA0_GWIDC56_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC56_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC57 ======================================================== */ + #define R_GWCA0_GWIDC57_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC57_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC58 ======================================================== */ + #define R_GWCA0_GWIDC58_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC58_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC59 ======================================================== */ + #define R_GWCA0_GWIDC59_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC59_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC60 ======================================================== */ + #define R_GWCA0_GWIDC60_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC60_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC61 ======================================================== */ + #define R_GWCA0_GWIDC61_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC61_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC62 ======================================================== */ + #define R_GWCA0_GWIDC62_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC62_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC63 ======================================================== */ + #define R_GWCA0_GWIDC63_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC63_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC64 ======================================================== */ + #define R_GWCA0_GWIDC64_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC64_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWRDCN ========================================================= */ + #define R_GWCA0_GWRDCN_RDN_Pos (0UL) /*!< RDN (Bit 0) */ + #define R_GWCA0_GWRDCN_RDN_Msk (0xffffffffUL) /*!< RDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GWTDCN ========================================================= */ + #define R_GWCA0_GWTDCN_TDN_Pos (0UL) /*!< TDN (Bit 0) */ + #define R_GWCA0_GWTDCN_TDN_Msk (0xffffffffUL) /*!< TDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GWTSCN ========================================================= */ + #define R_GWCA0_GWTSCN_TN_Pos (0UL) /*!< TN (Bit 0) */ + #define R_GWCA0_GWTSCN_TN_Msk (0xffffffffUL) /*!< TN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWTSOVFECN ======================================================= */ + #define R_GWCA0_GWTSOVFECN_TSOVFEN_Pos (0UL) /*!< TSOVFEN (Bit 0) */ + #define R_GWCA0_GWTSOVFECN_TSOVFEN_Msk (0xffffUL) /*!< TSOVFEN (Bitfield-Mask: 0xffff) */ +/* ====================================================== GWUSMFSECN ======================================================= */ + #define R_GWCA0_GWUSMFSECN_USMFSEN_Pos (0UL) /*!< USMFSEN (Bit 0) */ + #define R_GWCA0_GWUSMFSECN_USMFSEN_Msk (0xffffUL) /*!< USMFSEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== GWTFECN ======================================================== */ + #define R_GWCA0_GWTFECN_TFEN_Pos (0UL) /*!< TFEN (Bit 0) */ + #define R_GWCA0_GWTFECN_TFEN_Msk (0xffffUL) /*!< TFEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWSEQECN ======================================================== */ + #define R_GWCA0_GWSEQECN_SEQEN_Pos (0UL) /*!< SEQEN (Bit 0) */ + #define R_GWCA0_GWSEQECN_SEQEN_Msk (0xffffUL) /*!< SEQEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWTXDNECN ======================================================= */ + #define R_GWCA0_GWTXDNECN_TXDNEN_Pos (0UL) /*!< TXDNEN (Bit 0) */ + #define R_GWCA0_GWTXDNECN_TXDNEN_Msk (0xffffUL) /*!< TXDNEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== GWFSECN ======================================================== */ + #define R_GWCA0_GWFSECN_FSEN_Pos (0UL) /*!< FSEN (Bit 0) */ + #define R_GWCA0_GWFSECN_FSEN_Msk (0xffffUL) /*!< FSEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWTDFECN ======================================================== */ + #define R_GWCA0_GWTDFECN_TDFEN_Pos (0UL) /*!< TDFEN (Bit 0) */ + #define R_GWCA0_GWTDFECN_TDFEN_Msk (0xffffUL) /*!< TDFEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWTSDNECN ======================================================= */ + #define R_GWCA0_GWTSDNECN_TSDNEN_Pos (0UL) /*!< TSDNEN (Bit 0) */ + #define R_GWCA0_GWTSDNECN_TSDNEN_Msk (0xffffUL) /*!< TSDNEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWDQOECN ======================================================== */ + #define R_GWCA0_GWDQOECN_DQOEN_Pos (0UL) /*!< DQOEN (Bit 0) */ + #define R_GWCA0_GWDQOECN_DQOEN_Msk (0xffffUL) /*!< DQOEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWDQSECN ======================================================== */ + #define R_GWCA0_GWDQSECN_DQSEN_Pos (0UL) /*!< DQSEN (Bit 0) */ + #define R_GWCA0_GWDQSECN_DQSEN_Msk (0xffffUL) /*!< DQSEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== GWDFECN ======================================================== */ + #define R_GWCA0_GWDFECN_DFEN_Pos (0UL) /*!< DFEN (Bit 0) */ + #define R_GWCA0_GWDFECN_DFEN_Msk (0xffffUL) /*!< DFEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== GWDSECN ======================================================== */ + #define R_GWCA0_GWDSECN_DSEN_Pos (0UL) /*!< DSEN (Bit 0) */ + #define R_GWCA0_GWDSECN_DSEN_Msk (0xffffUL) /*!< DSEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWDSZECN ======================================================== */ + #define R_GWCA0_GWDSZECN_DSZEN_Pos (0UL) /*!< DSZEN (Bit 0) */ + #define R_GWCA0_GWDSZECN_DSZEN_Msk (0xffffUL) /*!< DSZEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWDCTECN ======================================================== */ + #define R_GWCA0_GWDCTECN_DCTEN_Pos (0UL) /*!< DCTEN (Bit 0) */ + #define R_GWCA0_GWDCTECN_DCTEN_Msk (0xffffUL) /*!< DCTEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRXDNECN ======================================================= */ + #define R_GWCA0_GWRXDNECN_RXDNEN_Pos (0UL) /*!< RXDNEN (Bit 0) */ + #define R_GWCA0_GWRXDNECN_RXDNEN_Msk (0xffffUL) /*!< RXDNEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== GWDIS0 ========================================================= */ +/* ======================================================== GWDIE0 ========================================================= */ +/* ======================================================== GWDID0 ========================================================= */ +/* ======================================================== GWDIDS0 ======================================================== */ +/* ======================================================== GWDIS1 ========================================================= */ +/* ======================================================== GWDIE1 ========================================================= */ +/* ======================================================== GWDID1 ========================================================= */ +/* ======================================================== GWDIDS1 ======================================================== */ +/* ======================================================== GWTSDIS ======================================================== */ + #define R_GWCA0_GWTSDIS_TSDIS0_Pos (0UL) /*!< TSDIS0 (Bit 0) */ + #define R_GWCA0_GWTSDIS_TSDIS0_Msk (0x1UL) /*!< TSDIS0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTSDIS_TSDIS1_Pos (1UL) /*!< TSDIS1 (Bit 1) */ + #define R_GWCA0_GWTSDIS_TSDIS1_Msk (0x2UL) /*!< TSDIS1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWTSDIE ======================================================== */ + #define R_GWCA0_GWTSDIE_TSDIE0_Pos (0UL) /*!< TSDIE0 (Bit 0) */ + #define R_GWCA0_GWTSDIE_TSDIE0_Msk (0x1UL) /*!< TSDIE0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTSDIE_TSDIE1_Pos (1UL) /*!< TSDIE1 (Bit 1) */ + #define R_GWCA0_GWTSDIE_TSDIE1_Msk (0x2UL) /*!< TSDIE1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWTSDID ======================================================== */ + #define R_GWCA0_GWTSDID_TSDID0_Pos (0UL) /*!< TSDID0 (Bit 0) */ + #define R_GWCA0_GWTSDID_TSDID0_Msk (0x1UL) /*!< TSDID0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTSDID_TSDID1_Pos (1UL) /*!< TSDID1 (Bit 1) */ + #define R_GWCA0_GWTSDID_TSDID1_Msk (0x2UL) /*!< TSDID1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIS0 ========================================================= */ + #define R_GWCA0_GWEIS0_AES_Pos (0UL) /*!< AES (Bit 0) */ + #define R_GWCA0_GWEIS0_AES_Msk (0x1UL) /*!< AES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_DECCES_Pos (1UL) /*!< DECCES (Bit 1) */ + #define R_GWCA0_GWEIS0_DECCES_Msk (0x2UL) /*!< DECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TECCES_Pos (2UL) /*!< TECCES (Bit 2) */ + #define R_GWCA0_GWEIS0_TECCES_Msk (0x4UL) /*!< TECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_PECCES_Pos (3UL) /*!< PECCES (Bit 3) */ + #define R_GWCA0_GWEIS0_PECCES_Msk (0x8UL) /*!< PECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_DSECCES_Pos (4UL) /*!< DSECCES (Bit 4) */ + #define R_GWCA0_GWEIS0_DSECCES_Msk (0x10UL) /*!< DSECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_MECCES_Pos (5UL) /*!< MECCES (Bit 5) */ + #define R_GWCA0_GWEIS0_MECCES_Msk (0x20UL) /*!< MECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_AECCES_Pos (6UL) /*!< AECCES (Bit 6) */ + #define R_GWCA0_GWEIS0_AECCES_Msk (0x40UL) /*!< AECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TSECCES_Pos (7UL) /*!< TSECCES (Bit 7) */ + #define R_GWCA0_GWEIS0_TSECCES_Msk (0x80UL) /*!< TSECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_L23UECCES_Pos (8UL) /*!< L23UECCES (Bit 8) */ + #define R_GWCA0_GWEIS0_L23UECCES_Msk (0x100UL) /*!< L23UECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TSOVFES_Pos (9UL) /*!< TSOVFES (Bit 9) */ + #define R_GWCA0_GWEIS0_TSOVFES_Msk (0x200UL) /*!< TSOVFES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_USMFSES_Pos (10UL) /*!< USMFSES (Bit 10) */ + #define R_GWCA0_GWEIS0_USMFSES_Msk (0x400UL) /*!< USMFSES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TFES_Pos (11UL) /*!< TFES (Bit 11) */ + #define R_GWCA0_GWEIS0_TFES_Msk (0x800UL) /*!< TFES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_SEQES_Pos (12UL) /*!< SEQES (Bit 12) */ + #define R_GWCA0_GWEIS0_SEQES_Msk (0x1000UL) /*!< SEQES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TXDNES_Pos (14UL) /*!< TXDNES (Bit 14) */ + #define R_GWCA0_GWEIS0_TXDNES_Msk (0x4000UL) /*!< TXDNES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TSHES_Pos (15UL) /*!< TSHES (Bit 15) */ + #define R_GWCA0_GWEIS0_TSHES_Msk (0x8000UL) /*!< TSHES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES0_Pos (16UL) /*!< FSES0 (Bit 16) */ + #define R_GWCA0_GWEIS0_FSES0_Msk (0x10000UL) /*!< FSES0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES1_Pos (17UL) /*!< FSES1 (Bit 17) */ + #define R_GWCA0_GWEIS0_FSES1_Msk (0x20000UL) /*!< FSES1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES2_Pos (18UL) /*!< FSES2 (Bit 18) */ + #define R_GWCA0_GWEIS0_FSES2_Msk (0x40000UL) /*!< FSES2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES3_Pos (19UL) /*!< FSES3 (Bit 19) */ + #define R_GWCA0_GWEIS0_FSES3_Msk (0x80000UL) /*!< FSES3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES4_Pos (20UL) /*!< FSES4 (Bit 20) */ + #define R_GWCA0_GWEIS0_FSES4_Msk (0x100000UL) /*!< FSES4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES5_Pos (21UL) /*!< FSES5 (Bit 21) */ + #define R_GWCA0_GWEIS0_FSES5_Msk (0x200000UL) /*!< FSES5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES6_Pos (22UL) /*!< FSES6 (Bit 22) */ + #define R_GWCA0_GWEIS0_FSES6_Msk (0x400000UL) /*!< FSES6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES7_Pos (23UL) /*!< FSES7 (Bit 23) */ + #define R_GWCA0_GWEIS0_FSES7_Msk (0x800000UL) /*!< FSES7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TDFES0_Pos (24UL) /*!< TDFES0 (Bit 24) */ + #define R_GWCA0_GWEIS0_TDFES0_Msk (0x1000000UL) /*!< TDFES0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TDFES1_Pos (25UL) /*!< TDFES1 (Bit 25) */ + #define R_GWCA0_GWEIS0_TDFES1_Msk (0x2000000UL) /*!< TDFES1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TSDNES0_Pos (28UL) /*!< TSDNES0 (Bit 28) */ + #define R_GWCA0_GWEIS0_TSDNES0_Msk (0x10000000UL) /*!< TSDNES0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TSDNES1_Pos (29UL) /*!< TSDNES1 (Bit 29) */ + #define R_GWCA0_GWEIS0_TSDNES1_Msk (0x20000000UL) /*!< TSDNES1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIE0 ========================================================= */ + #define R_GWCA0_GWEIE0_AEE_Pos (0UL) /*!< AEE (Bit 0) */ + #define R_GWCA0_GWEIE0_AEE_Msk (0x1UL) /*!< AEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_DECCEE_Pos (1UL) /*!< DECCEE (Bit 1) */ + #define R_GWCA0_GWEIE0_DECCEE_Msk (0x2UL) /*!< DECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TECCEE_Pos (2UL) /*!< TECCEE (Bit 2) */ + #define R_GWCA0_GWEIE0_TECCEE_Msk (0x4UL) /*!< TECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_PECCEE_Pos (3UL) /*!< PECCEE (Bit 3) */ + #define R_GWCA0_GWEIE0_PECCEE_Msk (0x8UL) /*!< PECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_DSECCEE_Pos (4UL) /*!< DSECCEE (Bit 4) */ + #define R_GWCA0_GWEIE0_DSECCEE_Msk (0x10UL) /*!< DSECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_MECCEE_Pos (5UL) /*!< MECCEE (Bit 5) */ + #define R_GWCA0_GWEIE0_MECCEE_Msk (0x20UL) /*!< MECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_AECCEE_Pos (6UL) /*!< AECCEE (Bit 6) */ + #define R_GWCA0_GWEIE0_AECCEE_Msk (0x40UL) /*!< AECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TSECCEE_Pos (7UL) /*!< TSECCEE (Bit 7) */ + #define R_GWCA0_GWEIE0_TSECCEE_Msk (0x80UL) /*!< TSECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_L23UECCEE_Pos (8UL) /*!< L23UECCEE (Bit 8) */ + #define R_GWCA0_GWEIE0_L23UECCEE_Msk (0x100UL) /*!< L23UECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TSOVFEE_Pos (9UL) /*!< TSOVFEE (Bit 9) */ + #define R_GWCA0_GWEIE0_TSOVFEE_Msk (0x200UL) /*!< TSOVFEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_USMFSEE_Pos (10UL) /*!< USMFSEE (Bit 10) */ + #define R_GWCA0_GWEIE0_USMFSEE_Msk (0x400UL) /*!< USMFSEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TFEE_Pos (11UL) /*!< TFEE (Bit 11) */ + #define R_GWCA0_GWEIE0_TFEE_Msk (0x800UL) /*!< TFEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_SEQEE_Pos (12UL) /*!< SEQEE (Bit 12) */ + #define R_GWCA0_GWEIE0_SEQEE_Msk (0x1000UL) /*!< SEQEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TXDNEE_Pos (14UL) /*!< TXDNEE (Bit 14) */ + #define R_GWCA0_GWEIE0_TXDNEE_Msk (0x4000UL) /*!< TXDNEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TSHEE_Pos (15UL) /*!< TSHEE (Bit 15) */ + #define R_GWCA0_GWEIE0_TSHEE_Msk (0x8000UL) /*!< TSHEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE0_Pos (16UL) /*!< FSEE0 (Bit 16) */ + #define R_GWCA0_GWEIE0_FSEE0_Msk (0x10000UL) /*!< FSEE0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE1_Pos (17UL) /*!< FSEE1 (Bit 17) */ + #define R_GWCA0_GWEIE0_FSEE1_Msk (0x20000UL) /*!< FSEE1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE2_Pos (18UL) /*!< FSEE2 (Bit 18) */ + #define R_GWCA0_GWEIE0_FSEE2_Msk (0x40000UL) /*!< FSEE2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE3_Pos (19UL) /*!< FSEE3 (Bit 19) */ + #define R_GWCA0_GWEIE0_FSEE3_Msk (0x80000UL) /*!< FSEE3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE4_Pos (20UL) /*!< FSEE4 (Bit 20) */ + #define R_GWCA0_GWEIE0_FSEE4_Msk (0x100000UL) /*!< FSEE4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE5_Pos (21UL) /*!< FSEE5 (Bit 21) */ + #define R_GWCA0_GWEIE0_FSEE5_Msk (0x200000UL) /*!< FSEE5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE6_Pos (22UL) /*!< FSEE6 (Bit 22) */ + #define R_GWCA0_GWEIE0_FSEE6_Msk (0x400000UL) /*!< FSEE6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE7_Pos (23UL) /*!< FSEE7 (Bit 23) */ + #define R_GWCA0_GWEIE0_FSEE7_Msk (0x800000UL) /*!< FSEE7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TDFEE0_Pos (24UL) /*!< TDFEE0 (Bit 24) */ + #define R_GWCA0_GWEIE0_TDFEE0_Msk (0x1000000UL) /*!< TDFEE0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TDFEE1_Pos (25UL) /*!< TDFEE1 (Bit 25) */ + #define R_GWCA0_GWEIE0_TDFEE1_Msk (0x2000000UL) /*!< TDFEE1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TSDNEE0_Pos (28UL) /*!< TSDNEE0 (Bit 28) */ + #define R_GWCA0_GWEIE0_TSDNEE0_Msk (0x10000000UL) /*!< TSDNEE0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TSDNEE1_Pos (29UL) /*!< TSDNEE1 (Bit 29) */ + #define R_GWCA0_GWEIE0_TSDNEE1_Msk (0x20000000UL) /*!< TSDNEE1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEID0 ========================================================= */ + #define R_GWCA0_GWEID0_AED_Pos (0UL) /*!< AED (Bit 0) */ + #define R_GWCA0_GWEID0_AED_Msk (0x1UL) /*!< AED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TECCED_Pos (1UL) /*!< TECCED (Bit 1) */ + #define R_GWCA0_GWEID0_TECCED_Msk (0x2UL) /*!< TECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_DECCED_Pos (2UL) /*!< DECCED (Bit 2) */ + #define R_GWCA0_GWEID0_DECCED_Msk (0x4UL) /*!< DECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_PECCED_Pos (3UL) /*!< PECCED (Bit 3) */ + #define R_GWCA0_GWEID0_PECCED_Msk (0x8UL) /*!< PECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_DSECCED_Pos (4UL) /*!< DSECCED (Bit 4) */ + #define R_GWCA0_GWEID0_DSECCED_Msk (0x10UL) /*!< DSECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_MECCED_Pos (5UL) /*!< MECCED (Bit 5) */ + #define R_GWCA0_GWEID0_MECCED_Msk (0x20UL) /*!< MECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_AECCED_Pos (6UL) /*!< AECCED (Bit 6) */ + #define R_GWCA0_GWEID0_AECCED_Msk (0x40UL) /*!< AECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TSECCED_Pos (7UL) /*!< TSECCED (Bit 7) */ + #define R_GWCA0_GWEID0_TSECCED_Msk (0x80UL) /*!< TSECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_L23UECCED_Pos (8UL) /*!< L23UECCED (Bit 8) */ + #define R_GWCA0_GWEID0_L23UECCED_Msk (0x100UL) /*!< L23UECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TSOVFED_Pos (9UL) /*!< TSOVFED (Bit 9) */ + #define R_GWCA0_GWEID0_TSOVFED_Msk (0x200UL) /*!< TSOVFED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_USMFSED_Pos (10UL) /*!< USMFSED (Bit 10) */ + #define R_GWCA0_GWEID0_USMFSED_Msk (0x400UL) /*!< USMFSED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TFED_Pos (11UL) /*!< TFED (Bit 11) */ + #define R_GWCA0_GWEID0_TFED_Msk (0x800UL) /*!< TFED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_SEQED_Pos (12UL) /*!< SEQED (Bit 12) */ + #define R_GWCA0_GWEID0_SEQED_Msk (0x1000UL) /*!< SEQED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_IIPED_Pos (13UL) /*!< IIPED (Bit 13) */ + #define R_GWCA0_GWEID0_IIPED_Msk (0x2000UL) /*!< IIPED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TXDNED_Pos (14UL) /*!< TXDNED (Bit 14) */ + #define R_GWCA0_GWEID0_TXDNED_Msk (0x4000UL) /*!< TXDNED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TSHED_Pos (15UL) /*!< TSHED (Bit 15) */ + #define R_GWCA0_GWEID0_TSHED_Msk (0x8000UL) /*!< TSHED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED0_Pos (16UL) /*!< FSED0 (Bit 16) */ + #define R_GWCA0_GWEID0_FSED0_Msk (0x10000UL) /*!< FSED0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED1_Pos (17UL) /*!< FSED1 (Bit 17) */ + #define R_GWCA0_GWEID0_FSED1_Msk (0x20000UL) /*!< FSED1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED2_Pos (18UL) /*!< FSED2 (Bit 18) */ + #define R_GWCA0_GWEID0_FSED2_Msk (0x40000UL) /*!< FSED2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED3_Pos (19UL) /*!< FSED3 (Bit 19) */ + #define R_GWCA0_GWEID0_FSED3_Msk (0x80000UL) /*!< FSED3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED4_Pos (20UL) /*!< FSED4 (Bit 20) */ + #define R_GWCA0_GWEID0_FSED4_Msk (0x100000UL) /*!< FSED4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED5_Pos (21UL) /*!< FSED5 (Bit 21) */ + #define R_GWCA0_GWEID0_FSED5_Msk (0x200000UL) /*!< FSED5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED6_Pos (22UL) /*!< FSED6 (Bit 22) */ + #define R_GWCA0_GWEID0_FSED6_Msk (0x400000UL) /*!< FSED6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED7_Pos (23UL) /*!< FSED7 (Bit 23) */ + #define R_GWCA0_GWEID0_FSED7_Msk (0x800000UL) /*!< FSED7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TDFED0_Pos (24UL) /*!< TDFED0 (Bit 24) */ + #define R_GWCA0_GWEID0_TDFED0_Msk (0x1000000UL) /*!< TDFED0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TDFED1_Pos (25UL) /*!< TDFED1 (Bit 25) */ + #define R_GWCA0_GWEID0_TDFED1_Msk (0x2000000UL) /*!< TDFED1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TSDNED0_Pos (28UL) /*!< TSDNED0 (Bit 28) */ + #define R_GWCA0_GWEID0_TSDNED0_Msk (0x10000000UL) /*!< TSDNED0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TSDNED1_Pos (29UL) /*!< TSDNED1 (Bit 29) */ + #define R_GWCA0_GWEID0_TSDNED1_Msk (0x20000000UL) /*!< TSDNED1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIS1 ========================================================= */ + #define R_GWCA0_GWEIS1_DQOES0_Pos (0UL) /*!< DQOES0 (Bit 0) */ + #define R_GWCA0_GWEIS1_DQOES0_Msk (0x1UL) /*!< DQOES0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQOES1_Pos (1UL) /*!< DQOES1 (Bit 1) */ + #define R_GWCA0_GWEIS1_DQOES1_Msk (0x2UL) /*!< DQOES1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQOES2_Pos (2UL) /*!< DQOES2 (Bit 2) */ + #define R_GWCA0_GWEIS1_DQOES2_Msk (0x4UL) /*!< DQOES2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQOES3_Pos (3UL) /*!< DQOES3 (Bit 3) */ + #define R_GWCA0_GWEIS1_DQOES3_Msk (0x8UL) /*!< DQOES3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQOES4_Pos (4UL) /*!< DQOES4 (Bit 4) */ + #define R_GWCA0_GWEIS1_DQOES4_Msk (0x10UL) /*!< DQOES4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQOES5_Pos (5UL) /*!< DQOES5 (Bit 5) */ + #define R_GWCA0_GWEIS1_DQOES5_Msk (0x20UL) /*!< DQOES5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQOES6_Pos (6UL) /*!< DQOES6 (Bit 6) */ + #define R_GWCA0_GWEIS1_DQOES6_Msk (0x40UL) /*!< DQOES6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQOES7_Pos (7UL) /*!< DQOES7 (Bit 7) */ + #define R_GWCA0_GWEIS1_DQOES7_Msk (0x80UL) /*!< DQOES7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES0_Pos (16UL) /*!< DQSES0 (Bit 16) */ + #define R_GWCA0_GWEIS1_DQSES0_Msk (0x10000UL) /*!< DQSES0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES1_Pos (17UL) /*!< DQSES1 (Bit 17) */ + #define R_GWCA0_GWEIS1_DQSES1_Msk (0x20000UL) /*!< DQSES1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES2_Pos (18UL) /*!< DQSES2 (Bit 18) */ + #define R_GWCA0_GWEIS1_DQSES2_Msk (0x40000UL) /*!< DQSES2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES3_Pos (19UL) /*!< DQSES3 (Bit 19) */ + #define R_GWCA0_GWEIS1_DQSES3_Msk (0x80000UL) /*!< DQSES3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES4_Pos (20UL) /*!< DQSES4 (Bit 20) */ + #define R_GWCA0_GWEIS1_DQSES4_Msk (0x100000UL) /*!< DQSES4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES5_Pos (21UL) /*!< DQSES5 (Bit 21) */ + #define R_GWCA0_GWEIS1_DQSES5_Msk (0x200000UL) /*!< DQSES5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES6_Pos (22UL) /*!< DQSES6 (Bit 22) */ + #define R_GWCA0_GWEIS1_DQSES6_Msk (0x400000UL) /*!< DQSES6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES7_Pos (23UL) /*!< DQSES7 (Bit 23) */ + #define R_GWCA0_GWEIS1_DQSES7_Msk (0x800000UL) /*!< DQSES7 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIE1 ========================================================= */ + #define R_GWCA0_GWEIE1_DQOEE0_Pos (0UL) /*!< DQOEE0 (Bit 0) */ + #define R_GWCA0_GWEIE1_DQOEE0_Msk (0x1UL) /*!< DQOEE0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQOEE1_Pos (1UL) /*!< DQOEE1 (Bit 1) */ + #define R_GWCA0_GWEIE1_DQOEE1_Msk (0x2UL) /*!< DQOEE1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQOEE2_Pos (2UL) /*!< DQOEE2 (Bit 2) */ + #define R_GWCA0_GWEIE1_DQOEE2_Msk (0x4UL) /*!< DQOEE2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQOEE3_Pos (3UL) /*!< DQOEE3 (Bit 3) */ + #define R_GWCA0_GWEIE1_DQOEE3_Msk (0x8UL) /*!< DQOEE3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQOEE4_Pos (4UL) /*!< DQOEE4 (Bit 4) */ + #define R_GWCA0_GWEIE1_DQOEE4_Msk (0x10UL) /*!< DQOEE4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQOEE5_Pos (5UL) /*!< DQOEE5 (Bit 5) */ + #define R_GWCA0_GWEIE1_DQOEE5_Msk (0x20UL) /*!< DQOEE5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQOEE6_Pos (6UL) /*!< DQOEE6 (Bit 6) */ + #define R_GWCA0_GWEIE1_DQOEE6_Msk (0x40UL) /*!< DQOEE6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQOEE7_Pos (7UL) /*!< DQOEE7 (Bit 7) */ + #define R_GWCA0_GWEIE1_DQOEE7_Msk (0x80UL) /*!< DQOEE7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE0_Pos (16UL) /*!< DQSEE0 (Bit 16) */ + #define R_GWCA0_GWEIE1_DQSEE0_Msk (0x10000UL) /*!< DQSEE0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE1_Pos (17UL) /*!< DQSEE1 (Bit 17) */ + #define R_GWCA0_GWEIE1_DQSEE1_Msk (0x20000UL) /*!< DQSEE1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE2_Pos (18UL) /*!< DQSEE2 (Bit 18) */ + #define R_GWCA0_GWEIE1_DQSEE2_Msk (0x40000UL) /*!< DQSEE2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE3_Pos (19UL) /*!< DQSEE3 (Bit 19) */ + #define R_GWCA0_GWEIE1_DQSEE3_Msk (0x80000UL) /*!< DQSEE3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE4_Pos (20UL) /*!< DQSEE4 (Bit 20) */ + #define R_GWCA0_GWEIE1_DQSEE4_Msk (0x100000UL) /*!< DQSEE4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE5_Pos (21UL) /*!< DQSEE5 (Bit 21) */ + #define R_GWCA0_GWEIE1_DQSEE5_Msk (0x200000UL) /*!< DQSEE5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE6_Pos (22UL) /*!< DQSEE6 (Bit 22) */ + #define R_GWCA0_GWEIE1_DQSEE6_Msk (0x400000UL) /*!< DQSEE6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE7_Pos (23UL) /*!< DQSEE7 (Bit 23) */ + #define R_GWCA0_GWEIE1_DQSEE7_Msk (0x800000UL) /*!< DQSEE7 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEID1 ========================================================= */ + #define R_GWCA0_GWEID1_DQOED0_Pos (0UL) /*!< DQOED0 (Bit 0) */ + #define R_GWCA0_GWEID1_DQOED0_Msk (0x1UL) /*!< DQOED0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQOED1_Pos (1UL) /*!< DQOED1 (Bit 1) */ + #define R_GWCA0_GWEID1_DQOED1_Msk (0x2UL) /*!< DQOED1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQOED2_Pos (2UL) /*!< DQOED2 (Bit 2) */ + #define R_GWCA0_GWEID1_DQOED2_Msk (0x4UL) /*!< DQOED2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQOED3_Pos (3UL) /*!< DQOED3 (Bit 3) */ + #define R_GWCA0_GWEID1_DQOED3_Msk (0x8UL) /*!< DQOED3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQOED4_Pos (4UL) /*!< DQOED4 (Bit 4) */ + #define R_GWCA0_GWEID1_DQOED4_Msk (0x10UL) /*!< DQOED4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQOED5_Pos (5UL) /*!< DQOED5 (Bit 5) */ + #define R_GWCA0_GWEID1_DQOED5_Msk (0x20UL) /*!< DQOED5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQOED6_Pos (6UL) /*!< DQOED6 (Bit 6) */ + #define R_GWCA0_GWEID1_DQOED6_Msk (0x40UL) /*!< DQOED6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQOED7_Pos (7UL) /*!< DQOED7 (Bit 7) */ + #define R_GWCA0_GWEID1_DQOED7_Msk (0x80UL) /*!< DQOED7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED0_Pos (16UL) /*!< DQSED0 (Bit 16) */ + #define R_GWCA0_GWEID1_DQSED0_Msk (0x10000UL) /*!< DQSED0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED1_Pos (17UL) /*!< DQSED1 (Bit 17) */ + #define R_GWCA0_GWEID1_DQSED1_Msk (0x20000UL) /*!< DQSED1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED2_Pos (18UL) /*!< DQSED2 (Bit 18) */ + #define R_GWCA0_GWEID1_DQSED2_Msk (0x40000UL) /*!< DQSED2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED3_Pos (19UL) /*!< DQSED3 (Bit 19) */ + #define R_GWCA0_GWEID1_DQSED3_Msk (0x80000UL) /*!< DQSED3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED4_Pos (20UL) /*!< DQSED4 (Bit 20) */ + #define R_GWCA0_GWEID1_DQSED4_Msk (0x100000UL) /*!< DQSED4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED5_Pos (21UL) /*!< DQSED5 (Bit 21) */ + #define R_GWCA0_GWEID1_DQSED5_Msk (0x200000UL) /*!< DQSED5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED6_Pos (22UL) /*!< DQSED6 (Bit 22) */ + #define R_GWCA0_GWEID1_DQSED6_Msk (0x400000UL) /*!< DQSED6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED7_Pos (23UL) /*!< DQSED7 (Bit 23) */ + #define R_GWCA0_GWEID1_DQSED7_Msk (0x800000UL) /*!< DQSED7 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIS20 ======================================================== */ +/* ======================================================== GWEIE20 ======================================================== */ +/* ======================================================== GWEID20 ======================================================== */ +/* ======================================================== GWEIS21 ======================================================== */ +/* ======================================================== GWEIE21 ======================================================== */ +/* ======================================================== GWEID21 ======================================================== */ +/* ======================================================== GWEIS3 ========================================================= */ + #define R_GWCA0_GWEIS3_IAOES0_Pos (0UL) /*!< IAOES0 (Bit 0) */ + #define R_GWCA0_GWEIS3_IAOES0_Msk (0x1UL) /*!< IAOES0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS3_IAOES1_Pos (1UL) /*!< IAOES1 (Bit 1) */ + #define R_GWCA0_GWEIS3_IAOES1_Msk (0x2UL) /*!< IAOES1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS3_IAOES2_Pos (2UL) /*!< IAOES2 (Bit 2) */ + #define R_GWCA0_GWEIS3_IAOES2_Msk (0x4UL) /*!< IAOES2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS3_IAOES3_Pos (3UL) /*!< IAOES3 (Bit 3) */ + #define R_GWCA0_GWEIS3_IAOES3_Msk (0x8UL) /*!< IAOES3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS3_IAOES4_Pos (4UL) /*!< IAOES4 (Bit 4) */ + #define R_GWCA0_GWEIS3_IAOES4_Msk (0x10UL) /*!< IAOES4 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIE3 ========================================================= */ + #define R_GWCA0_GWEIE3_IAOEE0_Pos (0UL) /*!< IAOEE0 (Bit 0) */ + #define R_GWCA0_GWEIE3_IAOEE0_Msk (0x1UL) /*!< IAOEE0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE3_IAOEE1_Pos (1UL) /*!< IAOEE1 (Bit 1) */ + #define R_GWCA0_GWEIE3_IAOEE1_Msk (0x2UL) /*!< IAOEE1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE3_IAOEE2_Pos (2UL) /*!< IAOEE2 (Bit 2) */ + #define R_GWCA0_GWEIE3_IAOEE2_Msk (0x4UL) /*!< IAOEE2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE3_IAOEE3_Pos (3UL) /*!< IAOEE3 (Bit 3) */ + #define R_GWCA0_GWEIE3_IAOEE3_Msk (0x8UL) /*!< IAOEE3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE3_IAOEE4_Pos (4UL) /*!< IAOEE4 (Bit 4) */ + #define R_GWCA0_GWEIE3_IAOEE4_Msk (0x10UL) /*!< IAOEE4 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEID3 ========================================================= */ + #define R_GWCA0_GWEID3_IAOED0_Pos (0UL) /*!< IAOED0 (Bit 0) */ + #define R_GWCA0_GWEID3_IAOED0_Msk (0x1UL) /*!< IAOED0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID3_IAOED1_Pos (1UL) /*!< IAOED1 (Bit 1) */ + #define R_GWCA0_GWEID3_IAOED1_Msk (0x2UL) /*!< IAOED1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID3_IAOED2_Pos (2UL) /*!< IAOED2 (Bit 2) */ + #define R_GWCA0_GWEID3_IAOED2_Msk (0x4UL) /*!< IAOED2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID3_IAOED3_Pos (3UL) /*!< IAOED3 (Bit 3) */ + #define R_GWCA0_GWEID3_IAOED3_Msk (0x8UL) /*!< IAOED3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID3_IAOED4_Pos (4UL) /*!< IAOED4 (Bit 4) */ + #define R_GWCA0_GWEID3_IAOED4_Msk (0x10UL) /*!< IAOED4 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIS4 ========================================================= */ + #define R_GWCA0_GWEIS4_DSSES_Pos (0UL) /*!< DSSES (Bit 0) */ + #define R_GWCA0_GWEIS4_DSSES_Msk (0x1UL) /*!< DSSES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS4_DSSEIOS_Pos (1UL) /*!< DSSEIOS (Bit 1) */ + #define R_GWCA0_GWEIS4_DSSEIOS_Msk (0x2UL) /*!< DSSEIOS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS4_DSSECN_Pos (8UL) /*!< DSSECN (Bit 8) */ + #define R_GWCA0_GWEIS4_DSSECN_Msk (0x3f00UL) /*!< DSSECN (Bitfield-Mask: 0x3f) */ + #define R_GWCA0_GWEIS4_DSES_Pos (16UL) /*!< DSES (Bit 16) */ + #define R_GWCA0_GWEIS4_DSES_Msk (0x10000UL) /*!< DSES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS4_DSEIOS_Pos (17UL) /*!< DSEIOS (Bit 17) */ + #define R_GWCA0_GWEIS4_DSEIOS_Msk (0x20000UL) /*!< DSEIOS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS4_DSECN_Pos (24UL) /*!< DSECN (Bit 24) */ + #define R_GWCA0_GWEIS4_DSECN_Msk (0x3f000000UL) /*!< DSECN (Bitfield-Mask: 0x3f) */ +/* ======================================================== GWEIE4 ========================================================= */ + #define R_GWCA0_GWEIE4_DSSEE_Pos (0UL) /*!< DSSEE (Bit 0) */ + #define R_GWCA0_GWEIE4_DSSEE_Msk (0x1UL) /*!< DSSEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE4_DSSEIOE_Pos (1UL) /*!< DSSEIOE (Bit 1) */ + #define R_GWCA0_GWEIE4_DSSEIOE_Msk (0x2UL) /*!< DSSEIOE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE4_DSEE_Pos (16UL) /*!< DSEE (Bit 16) */ + #define R_GWCA0_GWEIE4_DSEE_Msk (0x10000UL) /*!< DSEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE4_DSEIOE_Pos (17UL) /*!< DSEIOE (Bit 17) */ + #define R_GWCA0_GWEIE4_DSEIOE_Msk (0x20000UL) /*!< DSEIOE (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEID4 ========================================================= */ + #define R_GWCA0_GWEID4_DSSED_Pos (0UL) /*!< DSSED (Bit 0) */ + #define R_GWCA0_GWEID4_DSSED_Msk (0x1UL) /*!< DSSED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID4_DSSEIOD_Pos (1UL) /*!< DSSEIOD (Bit 1) */ + #define R_GWCA0_GWEID4_DSSEIOD_Msk (0x2UL) /*!< DSSEIOD (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID4_DSED_Pos (16UL) /*!< DSED (Bit 16) */ + #define R_GWCA0_GWEID4_DSED_Msk (0x10000UL) /*!< DSED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID4_DSEIOD_Pos (17UL) /*!< DSEIOD (Bit 17) */ + #define R_GWCA0_GWEID4_DSEIOD_Msk (0x20000UL) /*!< DSEIOD (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIS5 ========================================================= */ + #define R_GWCA0_GWEIS5_DCTES_Pos (0UL) /*!< DCTES (Bit 0) */ + #define R_GWCA0_GWEIS5_DCTES_Msk (0x1UL) /*!< DCTES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS5_DCTEIOS_Pos (1UL) /*!< DCTEIOS (Bit 1) */ + #define R_GWCA0_GWEIS5_DCTEIOS_Msk (0x2UL) /*!< DCTEIOS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS5_DCTECN_Pos (8UL) /*!< DCTECN (Bit 8) */ + #define R_GWCA0_GWEIS5_DCTECN_Msk (0x3f00UL) /*!< DCTECN (Bitfield-Mask: 0x3f) */ + #define R_GWCA0_GWEIS5_RXDNES_Pos (16UL) /*!< RXDNES (Bit 16) */ + #define R_GWCA0_GWEIS5_RXDNES_Msk (0x10000UL) /*!< RXDNES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS5_RXDNEIOS_Pos (17UL) /*!< RXDNEIOS (Bit 17) */ + #define R_GWCA0_GWEIS5_RXDNEIOS_Msk (0x20000UL) /*!< RXDNEIOS (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIE5 ========================================================= */ + #define R_GWCA0_GWEIE5_DCTEE_Pos (0UL) /*!< DCTEE (Bit 0) */ + #define R_GWCA0_GWEIE5_DCTEE_Msk (0x1UL) /*!< DCTEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE5_DCTEIOE_Pos (1UL) /*!< DCTEIOE (Bit 1) */ + #define R_GWCA0_GWEIE5_DCTEIOE_Msk (0x2UL) /*!< DCTEIOE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE5_RXDNEE_Pos (16UL) /*!< RXDNEE (Bit 16) */ + #define R_GWCA0_GWEIE5_RXDNEE_Msk (0x10000UL) /*!< RXDNEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE5_RXDNEIOE_Pos (17UL) /*!< RXDNEIOE (Bit 17) */ + #define R_GWCA0_GWEIE5_RXDNEIOE_Msk (0x20000UL) /*!< RXDNEIOE (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEID5 ========================================================= */ + #define R_GWCA0_GWEID5_DCTED_Pos (0UL) /*!< DCTED (Bit 0) */ + #define R_GWCA0_GWEID5_DCTED_Msk (0x1UL) /*!< DCTED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID5_DCTEIOD_Pos (1UL) /*!< DCTEIOD (Bit 1) */ + #define R_GWCA0_GWEID5_DCTEIOD_Msk (0x2UL) /*!< DCTEIOD (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID5_RXDNED_Pos (15UL) /*!< RXDNED (Bit 15) */ + #define R_GWCA0_GWEID5_RXDNED_Msk (0x8000UL) /*!< RXDNED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID5_RXDNEIOD_Pos (16UL) /*!< RXDNEIOD (Bit 16) */ + #define R_GWCA0_GWEID5_RXDNEIOD_Msk (0x10000UL) /*!< RXDNEIOD (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IPC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IPCSEM ========================================================= */ + #define R_IPC_IPCSEM_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ + #define R_IPC_IPCSEM_LOCK_Msk (0x1UL) /*!< LOCK (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MFWD ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FWGC ========================================================== */ + #define R_MFWD_FWGC_SVM_Pos (0UL) /*!< SVM (Bit 0) */ + #define R_MFWD_FWGC_SVM_Msk (0x3UL) /*!< SVM (Bitfield-Mask: 0x03) */ +/* ======================================================== FWTTC0 ========================================================= */ + #define R_MFWD_FWTTC0_CTT_Pos (0UL) /*!< CTT (Bit 0) */ + #define R_MFWD_FWTTC0_CTT_Msk (0xffffUL) /*!< CTT (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTTC0_STT_Pos (16UL) /*!< STT (Bit 16) */ + #define R_MFWD_FWTTC0_STT_Msk (0xffff0000UL) /*!< STT (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWTTC1 ========================================================= */ + #define R_MFWD_FWTTC1_RTT_Pos (0UL) /*!< RTT (Bit 0) */ + #define R_MFWD_FWTTC1_RTT_Msk (0xffffUL) /*!< RTT (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWCEPTC ======================================================== */ + #define R_MFWD_FWCEPTC_EPCSD_Pos (0UL) /*!< EPCSD (Bit 0) */ + #define R_MFWD_FWCEPTC_EPCSD_Msk (0x7fUL) /*!< EPCSD (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCEPTC_EPIPV_Pos (12UL) /*!< EPIPV (Bit 12) */ + #define R_MFWD_FWCEPTC_EPIPV_Msk (0x7000UL) /*!< EPIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCEPTC_EPCS_Pos (16UL) /*!< EPCS (Bit 16) */ + #define R_MFWD_FWCEPTC_EPCS_Msk (0x30000UL) /*!< EPCS (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCEPTC_EPSL_Pos (24UL) /*!< EPSL (Bit 24) */ + #define R_MFWD_FWCEPTC_EPSL_Msk (0x1000000UL) /*!< EPSL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCEPRC0 ======================================================== */ + #define R_MFWD_FWCEPRC0_EPHYEEF_Pos (0UL) /*!< EPHYEEF (Bit 0) */ + #define R_MFWD_FWCEPRC0_EPHYEEF_Msk (0x1UL) /*!< EPHYEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_EPCRCEEF_Pos (1UL) /*!< EPCRCEEF (Bit 1) */ + #define R_MFWD_FWCEPRC0_EPCRCEEF_Msk (0x2UL) /*!< EPCRCEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_ENIBEEF_Pos (2UL) /*!< ENIBEEF (Bit 2) */ + #define R_MFWD_FWCEPRC0_ENIBEEF_Msk (0x4UL) /*!< ENIBEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_EFCSEEF_Pos (3UL) /*!< EFCSEEF (Bit 3) */ + #define R_MFWD_FWCEPRC0_EFCSEEF_Msk (0x8UL) /*!< EFCSEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_EFFMEEF_Pos (4UL) /*!< EFFMEEF (Bit 4) */ + #define R_MFWD_FWCEPRC0_EFFMEEF_Msk (0x10UL) /*!< EFFMEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_ECFSEEF_Pos (5UL) /*!< ECFSEEF (Bit 5) */ + #define R_MFWD_FWCEPRC0_ECFSEEF_Msk (0x20UL) /*!< ECFSEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_ECFFCEEF_Pos (6UL) /*!< ECFFCEEF (Bit 6) */ + #define R_MFWD_FWCEPRC0_ECFFCEEF_Msk (0x40UL) /*!< ECFFCEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_ERFFEF_Pos (7UL) /*!< ERFFEF (Bit 7) */ + #define R_MFWD_FWCEPRC0_ERFFEF_Msk (0x80UL) /*!< ERFFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_ERPOOEF_Pos (8UL) /*!< ERPOOEF (Bit 8) */ + #define R_MFWD_FWCEPRC0_ERPOOEF_Msk (0x100UL) /*!< ERPOOEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_EBOEEF_Pos (9UL) /*!< EBOEEF (Bit 9) */ + #define R_MFWD_FWCEPRC0_EBOEEF_Msk (0x200UL) /*!< EBOEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_EUEEF_Pos (10UL) /*!< EUEEF (Bit 10) */ + #define R_MFWD_FWCEPRC0_EUEEF_Msk (0x400UL) /*!< EUEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_EOEEF_Pos (11UL) /*!< EOEEF (Bit 11) */ + #define R_MFWD_FWCEPRC0_EOEEF_Msk (0x800UL) /*!< EOEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_ETFEF_Pos (12UL) /*!< ETFEF (Bit 12) */ + #define R_MFWD_FWCEPRC0_ETFEF_Msk (0x1000UL) /*!< ETFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_GAREEEF_Pos (16UL) /*!< GAREEEF (Bit 16) */ + #define R_MFWD_FWCEPRC0_GAREEEF_Msk (0x10000UL) /*!< GAREEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_GAXEEF_Pos (17UL) /*!< GAXEEF (Bit 17) */ + #define R_MFWD_FWCEPRC0_GAXEEF_Msk (0x20000UL) /*!< GAXEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_GSEQEEF_Pos (18UL) /*!< GSEQEEF (Bit 18) */ + #define R_MFWD_FWCEPRC0_GSEQEEF_Msk (0x40000UL) /*!< GSEQEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_GTFEF_Pos (20UL) /*!< GTFEF (Bit 20) */ + #define R_MFWD_FWCEPRC0_GTFEF_Msk (0x100000UL) /*!< GTFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_GDNEEF_Pos (21UL) /*!< GDNEEF (Bit 21) */ + #define R_MFWD_FWCEPRC0_GDNEEF_Msk (0x200000UL) /*!< GDNEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_DDEEF_Pos (24UL) /*!< DDEEF (Bit 24) */ + #define R_MFWD_FWCEPRC0_DDEEF_Msk (0x1000000UL) /*!< DDEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_DDFSFEF_Pos (26UL) /*!< DDFSFEF (Bit 26) */ + #define R_MFWD_FWCEPRC0_DDFSFEF_Msk (0x4000000UL) /*!< DDFSFEF (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCEPRC1 ======================================================== */ + #define R_MFWD_FWCEPRC1_FMSDUFEF_Pos (0UL) /*!< FMSDUFEF (Bit 0) */ + #define R_MFWD_FWCEPRC1_FMSDUFEF_Msk (0x1UL) /*!< FMSDUFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC1_FMTRFEF_Pos (2UL) /*!< FMTRFEF (Bit 2) */ + #define R_MFWD_FWCEPRC1_FMTRFEF_Msk (0x4UL) /*!< FMTRFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC1_FIFFEF_Pos (8UL) /*!< FIFFEF (Bit 8) */ + #define R_MFWD_FWCEPRC1_FIFFEF_Msk (0x100UL) /*!< FIFFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC1_FSFFEF_Pos (9UL) /*!< FSFFEF (Bit 9) */ + #define R_MFWD_FWCEPRC1_FSFFEF_Msk (0x200UL) /*!< FSFFEF (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCEPRC2 ======================================================== */ + #define R_MFWD_FWCEPRC2_FLTHUFEF_Pos (0UL) /*!< FLTHUFEF (Bit 0) */ + #define R_MFWD_FWCEPRC2_FLTHUFEF_Msk (0x1UL) /*!< FLTHUFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FDMACUFEF_Pos (3UL) /*!< FDMACUFEF (Bit 3) */ + #define R_MFWD_FWCEPRC2_FDMACUFEF_Msk (0x8UL) /*!< FDMACUFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FSMACUFEF_Pos (4UL) /*!< FSMACUFEF (Bit 4) */ + #define R_MFWD_FWCEPRC2_FSMACUFEF_Msk (0x10UL) /*!< FSMACUFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FVLANUFEF_Pos (5UL) /*!< FVLANUFEF (Bit 5) */ + #define R_MFWD_FWCEPRC2_FVLANUFEF_Msk (0x20UL) /*!< FVLANUFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FDDNTFEF_Pos (8UL) /*!< FDDNTFEF (Bit 8) */ + #define R_MFWD_FWCEPRC2_FDDNTFEF_Msk (0x100UL) /*!< FDDNTFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FLTHNTFEF_Pos (9UL) /*!< FLTHNTFEF (Bit 9) */ + #define R_MFWD_FWCEPRC2_FLTHNTFEF_Msk (0x200UL) /*!< FLTHNTFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FLTWNTFEF_Pos (11UL) /*!< FLTWNTFEF (Bit 11) */ + #define R_MFWD_FWCEPRC2_FLTWNTFEF_Msk (0x800UL) /*!< FLTWNTFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FPBNTFEF_Pos (12UL) /*!< FPBNTFEF (Bit 12) */ + #define R_MFWD_FWCEPRC2_FPBNTFEF_Msk (0x1000UL) /*!< FPBNTFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FLTHSLFEF_Pos (16UL) /*!< FLTHSLFEF (Bit 16) */ + #define R_MFWD_FWCEPRC2_FLTHSLFEF_Msk (0x10000UL) /*!< FLTHSLFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FDMACSLFEF_Pos (19UL) /*!< FDMACSLFEF (Bit 19) */ + #define R_MFWD_FWCEPRC2_FDMACSLFEF_Msk (0x80000UL) /*!< FDMACSLFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FSMACSLFEF_Pos (20UL) /*!< FSMACSLFEF (Bit 20) */ + #define R_MFWD_FWCEPRC2_FSMACSLFEF_Msk (0x100000UL) /*!< FSMACSLFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FVLANSLFEF_Pos (21UL) /*!< FVLANSLFEF (Bit 21) */ + #define R_MFWD_FWCEPRC2_FVLANSLFEF_Msk (0x200000UL) /*!< FVLANSLFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FWMFEF_Pos (26UL) /*!< FWMFEF (Bit 26) */ + #define R_MFWD_FWCEPRC2_FWMFEF_Msk (0x4000000UL) /*!< FWMFEF (Bitfield-Mask: 0x01) */ +/* ======================================================== FWCLPTC ======================================================== */ + #define R_MFWD_FWCLPTC_LPCSD_Pos (0UL) /*!< LPCSD (Bit 0) */ + #define R_MFWD_FWCLPTC_LPCSD_Msk (0x7fUL) /*!< LPCSD (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCLPTC_LPIPV_Pos (12UL) /*!< LPIPV (Bit 12) */ + #define R_MFWD_FWCLPTC_LPIPV_Msk (0x7000UL) /*!< LPIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCLPTC_LPCS_Pos (16UL) /*!< LPCS (Bit 16) */ + #define R_MFWD_FWCLPTC_LPCS_Msk (0x30000UL) /*!< LPCS (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCLPTC_LPSL_Pos (24UL) /*!< LPSL (Bit 24) */ + #define R_MFWD_FWCLPTC_LPSL_Msk (0x1000000UL) /*!< LPSL (Bitfield-Mask: 0x01) */ +/* ======================================================== FWCLPRC ======================================================== */ + #define R_MFWD_FWCLPRC_USIDLF_Pos (0UL) /*!< USIDLF (Bit 0) */ + #define R_MFWD_FWCLPRC_USIDLF_Msk (0x1UL) /*!< USIDLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCLPRC_UDMACLF_Pos (4UL) /*!< UDMACLF (Bit 4) */ + #define R_MFWD_FWCLPRC_UDMACLF_Msk (0x10UL) /*!< UDMACLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCLPRC_USMACLF_Pos (5UL) /*!< USMACLF (Bit 5) */ + #define R_MFWD_FWCLPRC_USMACLF_Msk (0x20UL) /*!< USMACLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCLPRC_UPSMACLF_Pos (6UL) /*!< UPSMACLF (Bit 6) */ + #define R_MFWD_FWCLPRC_UPSMACLF_Msk (0x40UL) /*!< UPSMACLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCLPRC_UVLANLF_Pos (7UL) /*!< UVLANLF (Bit 7) */ + #define R_MFWD_FWCLPRC_UVLANLF_Msk (0x80UL) /*!< UVLANLF (Bitfield-Mask: 0x01) */ +/* ======================================================== FWCMPTC ======================================================== */ + #define R_MFWD_FWCMPTC_CMPCSD_Pos (0UL) /*!< CMPCSD (Bit 0) */ + #define R_MFWD_FWCMPTC_CMPCSD_Msk (0x7fUL) /*!< CMPCSD (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCMPTC_CMPIPV_Pos (12UL) /*!< CMPIPV (Bit 12) */ + #define R_MFWD_FWCMPTC_CMPIPV_Msk (0x7000UL) /*!< CMPIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCMPTC_CMPIPU_Pos (15UL) /*!< CMPIPU (Bit 15) */ + #define R_MFWD_FWCMPTC_CMPIPU_Msk (0x8000UL) /*!< CMPIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCMPTC_CMPCS_Pos (16UL) /*!< CMPCS (Bit 16) */ + #define R_MFWD_FWCMPTC_CMPCS_Msk (0x30000UL) /*!< CMPCS (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCMPTC_CMPSL_Pos (24UL) /*!< CMPSL (Bit 24) */ + #define R_MFWD_FWCMPTC_CMPSL_Msk (0x1000000UL) /*!< CMPSL (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEMPTC ======================================================== */ + #define R_MFWD_FWEMPTC_EMPIPV_Pos (12UL) /*!< EMPIPV (Bit 12) */ + #define R_MFWD_FWEMPTC_EMPIPV_Msk (0x7000UL) /*!< EMPIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWEMPTC_EMPIPU_Pos (15UL) /*!< EMPIPU (Bit 15) */ + #define R_MFWD_FWEMPTC_EMPIPU_Msk (0x8000UL) /*!< EMPIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEMPTC_EMPPS_Pos (16UL) /*!< EMPPS (Bit 16) */ + #define R_MFWD_FWEMPTC_EMPPS_Msk (0x30000UL) /*!< EMPPS (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWEMPTC_EMPSL_Pos (24UL) /*!< EMPSL (Bit 24) */ + #define R_MFWD_FWEMPTC_EMPSL_Msk (0x1000000UL) /*!< EMPSL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSDMPTC ======================================================== */ + #define R_MFWD_FWSDMPTC_SDMPCSD_Pos (0UL) /*!< SDMPCSD (Bit 0) */ + #define R_MFWD_FWSDMPTC_SDMPCSD_Msk (0x7fUL) /*!< SDMPCSD (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWSDMPTC_SDMPIPV_Pos (12UL) /*!< SDMPIPV (Bit 12) */ + #define R_MFWD_FWSDMPTC_SDMPIPV_Msk (0x7000UL) /*!< SDMPIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWSDMPTC_SDMPIPU_Pos (15UL) /*!< SDMPIPU (Bit 15) */ + #define R_MFWD_FWSDMPTC_SDMPIPU_Msk (0x8000UL) /*!< SDMPIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWSDMPTC_SDMPPS_Pos (16UL) /*!< SDMPPS (Bit 16) */ + #define R_MFWD_FWSDMPTC_SDMPPS_Msk (0x30000UL) /*!< SDMPPS (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWSDMPTC_SDMPSL_Pos (24UL) /*!< SDMPSL (Bit 24) */ + #define R_MFWD_FWSDMPTC_SDMPSL_Msk (0x1000000UL) /*!< SDMPSL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSDMPVC ======================================================== */ + #define R_MFWD_FWSDMPVC_SDMDV_Pos (0UL) /*!< SDMDV (Bit 0) */ + #define R_MFWD_FWSDMPVC_SDMDV_Msk (0x7fUL) /*!< SDMDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWSDMPVC_SDMSV_Pos (16UL) /*!< SDMSV (Bit 16) */ + #define R_MFWD_FWSDMPVC_SDMSV_Msk (0x7f0000UL) /*!< SDMSV (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWLBWMC0 ======================================================== */ + #define R_MFWD_FWLBWMC0_WMCLPR_Pos (0UL) /*!< WMCLPR (Bit 0) */ + #define R_MFWD_FWLBWMC0_WMCLPR_Msk (0xffffUL) /*!< WMCLPR (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWLBWMC0_WMFLPR_Pos (16UL) /*!< WMFLPR (Bit 16) */ + #define R_MFWD_FWLBWMC0_WMFLPR_Msk (0xffff0000UL) /*!< WMFLPR (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWLBWMC1 ======================================================== */ + #define R_MFWD_FWLBWMC1_WMCLPR_Pos (0UL) /*!< WMCLPR (Bit 0) */ + #define R_MFWD_FWLBWMC1_WMCLPR_Msk (0xffffUL) /*!< WMCLPR (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWLBWMC1_WMFLPR_Pos (16UL) /*!< WMFLPR (Bit 16) */ + #define R_MFWD_FWLBWMC1_WMFLPR_Msk (0xffff0000UL) /*!< WMFLPR (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWLBWMC2 ======================================================== */ + #define R_MFWD_FWLBWMC2_WMCLPR_Pos (0UL) /*!< WMCLPR (Bit 0) */ + #define R_MFWD_FWLBWMC2_WMCLPR_Msk (0xffffUL) /*!< WMCLPR (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWLBWMC2_WMFLPR_Pos (16UL) /*!< WMFLPR (Bit 16) */ + #define R_MFWD_FWLBWMC2_WMFLPR_Msk (0xffff0000UL) /*!< WMFLPR (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWPC00 ========================================================= */ + #define R_MFWD_FWPC00_LTHTA_Pos (0UL) /*!< LTHTA (Bit 0) */ + #define R_MFWD_FWPC00_LTHTA_Msk (0x1UL) /*!< LTHTA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_LTHRUS_Pos (1UL) /*!< LTHRUS (Bit 1) */ + #define R_MFWD_FWPC00_LTHRUS_Msk (0x2UL) /*!< LTHRUS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_LTHRUSS_Pos (2UL) /*!< LTHRUSS (Bit 2) */ + #define R_MFWD_FWPC00_LTHRUSS_Msk (0x4UL) /*!< LTHRUSS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_IP4UE_Pos (3UL) /*!< IP4UE (Bit 3) */ + #define R_MFWD_FWPC00_IP4UE_Msk (0x8UL) /*!< IP4UE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_IP4TE_Pos (4UL) /*!< IP4TE (Bit 4) */ + #define R_MFWD_FWPC00_IP4TE_Msk (0x10UL) /*!< IP4TE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_IP4OE_Pos (5UL) /*!< IP4OE (Bit 5) */ + #define R_MFWD_FWPC00_IP4OE_Msk (0x20UL) /*!< IP4OE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_IP6UE_Pos (6UL) /*!< IP6UE (Bit 6) */ + #define R_MFWD_FWPC00_IP6UE_Msk (0x40UL) /*!< IP6UE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_IP6TE_Pos (7UL) /*!< IP6TE (Bit 7) */ + #define R_MFWD_FWPC00_IP6TE_Msk (0x80UL) /*!< IP6TE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_IP6OE_Pos (8UL) /*!< IP6OE (Bit 8) */ + #define R_MFWD_FWPC00_IP6OE_Msk (0x100UL) /*!< IP6OE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_L2SE_Pos (9UL) /*!< L2SE (Bit 9) */ + #define R_MFWD_FWPC00_L2SE_Msk (0x200UL) /*!< L2SE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACDSA_Pos (20UL) /*!< MACDSA (Bit 20) */ + #define R_MFWD_FWPC00_MACDSA_Msk (0x100000UL) /*!< MACDSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACRUDA_Pos (21UL) /*!< MACRUDA (Bit 21) */ + #define R_MFWD_FWPC00_MACRUDA_Msk (0x200000UL) /*!< MACRUDA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACRUDSA_Pos (22UL) /*!< MACRUDSA (Bit 22) */ + #define R_MFWD_FWPC00_MACRUDSA_Msk (0x400000UL) /*!< MACRUDSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACSSA_Pos (23UL) /*!< MACSSA (Bit 23) */ + #define R_MFWD_FWPC00_MACSSA_Msk (0x800000UL) /*!< MACSSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACRUSA_Pos (24UL) /*!< MACRUSA (Bit 24) */ + #define R_MFWD_FWPC00_MACRUSA_Msk (0x1000000UL) /*!< MACRUSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACRUSSA_Pos (25UL) /*!< MACRUSSA (Bit 25) */ + #define R_MFWD_FWPC00_MACRUSSA_Msk (0x2000000UL) /*!< MACRUSSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACHLA_Pos (26UL) /*!< MACHLA (Bit 26) */ + #define R_MFWD_FWPC00_MACHLA_Msk (0x4000000UL) /*!< MACHLA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACHMA_Pos (27UL) /*!< MACHMA (Bit 27) */ + #define R_MFWD_FWPC00_MACHMA_Msk (0x8000000UL) /*!< MACHMA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_VLANSA_Pos (28UL) /*!< VLANSA (Bit 28) */ + #define R_MFWD_FWPC00_VLANSA_Msk (0x10000000UL) /*!< VLANSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_VLANRU_Pos (29UL) /*!< VLANRU (Bit 29) */ + #define R_MFWD_FWPC00_VLANRU_Msk (0x20000000UL) /*!< VLANRU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_VLANRUS_Pos (30UL) /*!< VLANRUS (Bit 30) */ + #define R_MFWD_FWPC00_VLANRUS_Msk (0x40000000UL) /*!< VLANRUS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWPC01 ========================================================= */ + #define R_MFWD_FWPC01_LTHTA_Pos (0UL) /*!< LTHTA (Bit 0) */ + #define R_MFWD_FWPC01_LTHTA_Msk (0x1UL) /*!< LTHTA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_LTHRUS_Pos (1UL) /*!< LTHRUS (Bit 1) */ + #define R_MFWD_FWPC01_LTHRUS_Msk (0x2UL) /*!< LTHRUS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_LTHRUSS_Pos (2UL) /*!< LTHRUSS (Bit 2) */ + #define R_MFWD_FWPC01_LTHRUSS_Msk (0x4UL) /*!< LTHRUSS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_IP4UE_Pos (3UL) /*!< IP4UE (Bit 3) */ + #define R_MFWD_FWPC01_IP4UE_Msk (0x8UL) /*!< IP4UE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_IP4TE_Pos (4UL) /*!< IP4TE (Bit 4) */ + #define R_MFWD_FWPC01_IP4TE_Msk (0x10UL) /*!< IP4TE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_IP4OE_Pos (5UL) /*!< IP4OE (Bit 5) */ + #define R_MFWD_FWPC01_IP4OE_Msk (0x20UL) /*!< IP4OE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_IP6UE_Pos (6UL) /*!< IP6UE (Bit 6) */ + #define R_MFWD_FWPC01_IP6UE_Msk (0x40UL) /*!< IP6UE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_IP6TE_Pos (7UL) /*!< IP6TE (Bit 7) */ + #define R_MFWD_FWPC01_IP6TE_Msk (0x80UL) /*!< IP6TE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_IP6OE_Pos (8UL) /*!< IP6OE (Bit 8) */ + #define R_MFWD_FWPC01_IP6OE_Msk (0x100UL) /*!< IP6OE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_L2SE_Pos (9UL) /*!< L2SE (Bit 9) */ + #define R_MFWD_FWPC01_L2SE_Msk (0x200UL) /*!< L2SE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACDSA_Pos (20UL) /*!< MACDSA (Bit 20) */ + #define R_MFWD_FWPC01_MACDSA_Msk (0x100000UL) /*!< MACDSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACRUDA_Pos (21UL) /*!< MACRUDA (Bit 21) */ + #define R_MFWD_FWPC01_MACRUDA_Msk (0x200000UL) /*!< MACRUDA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACRUDSA_Pos (22UL) /*!< MACRUDSA (Bit 22) */ + #define R_MFWD_FWPC01_MACRUDSA_Msk (0x400000UL) /*!< MACRUDSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACSSA_Pos (23UL) /*!< MACSSA (Bit 23) */ + #define R_MFWD_FWPC01_MACSSA_Msk (0x800000UL) /*!< MACSSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACRUSA_Pos (24UL) /*!< MACRUSA (Bit 24) */ + #define R_MFWD_FWPC01_MACRUSA_Msk (0x1000000UL) /*!< MACRUSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACRUSSA_Pos (25UL) /*!< MACRUSSA (Bit 25) */ + #define R_MFWD_FWPC01_MACRUSSA_Msk (0x2000000UL) /*!< MACRUSSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACHLA_Pos (26UL) /*!< MACHLA (Bit 26) */ + #define R_MFWD_FWPC01_MACHLA_Msk (0x4000000UL) /*!< MACHLA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACHMA_Pos (27UL) /*!< MACHMA (Bit 27) */ + #define R_MFWD_FWPC01_MACHMA_Msk (0x8000000UL) /*!< MACHMA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_VLANSA_Pos (28UL) /*!< VLANSA (Bit 28) */ + #define R_MFWD_FWPC01_VLANSA_Msk (0x10000000UL) /*!< VLANSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_VLANRU_Pos (29UL) /*!< VLANRU (Bit 29) */ + #define R_MFWD_FWPC01_VLANRU_Msk (0x20000000UL) /*!< VLANRU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_VLANRUS_Pos (30UL) /*!< VLANRUS (Bit 30) */ + #define R_MFWD_FWPC01_VLANRUS_Msk (0x40000000UL) /*!< VLANRUS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWPC02 ========================================================= */ + #define R_MFWD_FWPC02_LTHTA_Pos (0UL) /*!< LTHTA (Bit 0) */ + #define R_MFWD_FWPC02_LTHTA_Msk (0x1UL) /*!< LTHTA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_LTHRUS_Pos (1UL) /*!< LTHRUS (Bit 1) */ + #define R_MFWD_FWPC02_LTHRUS_Msk (0x2UL) /*!< LTHRUS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_LTHRUSS_Pos (2UL) /*!< LTHRUSS (Bit 2) */ + #define R_MFWD_FWPC02_LTHRUSS_Msk (0x4UL) /*!< LTHRUSS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_IP4UE_Pos (3UL) /*!< IP4UE (Bit 3) */ + #define R_MFWD_FWPC02_IP4UE_Msk (0x8UL) /*!< IP4UE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_IP4TE_Pos (4UL) /*!< IP4TE (Bit 4) */ + #define R_MFWD_FWPC02_IP4TE_Msk (0x10UL) /*!< IP4TE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_IP4OE_Pos (5UL) /*!< IP4OE (Bit 5) */ + #define R_MFWD_FWPC02_IP4OE_Msk (0x20UL) /*!< IP4OE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_IP6UE_Pos (6UL) /*!< IP6UE (Bit 6) */ + #define R_MFWD_FWPC02_IP6UE_Msk (0x40UL) /*!< IP6UE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_IP6TE_Pos (7UL) /*!< IP6TE (Bit 7) */ + #define R_MFWD_FWPC02_IP6TE_Msk (0x80UL) /*!< IP6TE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_IP6OE_Pos (8UL) /*!< IP6OE (Bit 8) */ + #define R_MFWD_FWPC02_IP6OE_Msk (0x100UL) /*!< IP6OE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_L2SE_Pos (9UL) /*!< L2SE (Bit 9) */ + #define R_MFWD_FWPC02_L2SE_Msk (0x200UL) /*!< L2SE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACDSA_Pos (20UL) /*!< MACDSA (Bit 20) */ + #define R_MFWD_FWPC02_MACDSA_Msk (0x100000UL) /*!< MACDSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACRUDA_Pos (21UL) /*!< MACRUDA (Bit 21) */ + #define R_MFWD_FWPC02_MACRUDA_Msk (0x200000UL) /*!< MACRUDA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACRUDSA_Pos (22UL) /*!< MACRUDSA (Bit 22) */ + #define R_MFWD_FWPC02_MACRUDSA_Msk (0x400000UL) /*!< MACRUDSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACSSA_Pos (23UL) /*!< MACSSA (Bit 23) */ + #define R_MFWD_FWPC02_MACSSA_Msk (0x800000UL) /*!< MACSSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACRUSA_Pos (24UL) /*!< MACRUSA (Bit 24) */ + #define R_MFWD_FWPC02_MACRUSA_Msk (0x1000000UL) /*!< MACRUSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACRUSSA_Pos (25UL) /*!< MACRUSSA (Bit 25) */ + #define R_MFWD_FWPC02_MACRUSSA_Msk (0x2000000UL) /*!< MACRUSSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACHLA_Pos (26UL) /*!< MACHLA (Bit 26) */ + #define R_MFWD_FWPC02_MACHLA_Msk (0x4000000UL) /*!< MACHLA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACHMA_Pos (27UL) /*!< MACHMA (Bit 27) */ + #define R_MFWD_FWPC02_MACHMA_Msk (0x8000000UL) /*!< MACHMA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_VLANSA_Pos (28UL) /*!< VLANSA (Bit 28) */ + #define R_MFWD_FWPC02_VLANSA_Msk (0x10000000UL) /*!< VLANSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_VLANRU_Pos (29UL) /*!< VLANRU (Bit 29) */ + #define R_MFWD_FWPC02_VLANRU_Msk (0x20000000UL) /*!< VLANRU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_VLANRUS_Pos (30UL) /*!< VLANRUS (Bit 30) */ + #define R_MFWD_FWPC02_VLANRUS_Msk (0x40000000UL) /*!< VLANRUS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWPC10 ========================================================= */ + #define R_MFWD_FWPC10_DDE_Pos (0UL) /*!< DDE (Bit 0) */ + #define R_MFWD_FWPC10_DDE_Msk (0x1UL) /*!< DDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC10_DDSL_Pos (1UL) /*!< DDSL (Bit 1) */ + #define R_MFWD_FWPC10_DDSL_Msk (0x2UL) /*!< DDSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC10_LTHFM_Pos (16UL) /*!< LTHFM (Bit 16) */ + #define R_MFWD_FWPC10_LTHFM_Msk (0x7f0000UL) /*!< LTHFM (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWPC11 ========================================================= */ + #define R_MFWD_FWPC11_DDE_Pos (0UL) /*!< DDE (Bit 0) */ + #define R_MFWD_FWPC11_DDE_Msk (0x1UL) /*!< DDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC11_DDSL_Pos (1UL) /*!< DDSL (Bit 1) */ + #define R_MFWD_FWPC11_DDSL_Msk (0x2UL) /*!< DDSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC11_LTHFM_Pos (16UL) /*!< LTHFM (Bit 16) */ + #define R_MFWD_FWPC11_LTHFM_Msk (0x7f0000UL) /*!< LTHFM (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWPC12 ========================================================= */ + #define R_MFWD_FWPC12_DDE_Pos (0UL) /*!< DDE (Bit 0) */ + #define R_MFWD_FWPC12_DDE_Msk (0x1UL) /*!< DDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC12_DDSL_Pos (1UL) /*!< DDSL (Bit 1) */ + #define R_MFWD_FWPC12_DDSL_Msk (0x2UL) /*!< DDSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC12_LTHFM_Pos (16UL) /*!< LTHFM (Bit 16) */ + #define R_MFWD_FWPC12_LTHFM_Msk (0x7f0000UL) /*!< LTHFM (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWPC20 ========================================================= */ + #define R_MFWD_FWPC20_LTWFM_Pos (16UL) /*!< LTWFM (Bit 16) */ + #define R_MFWD_FWPC20_LTWFM_Msk (0x7f0000UL) /*!< LTWFM (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWPC21 ========================================================= */ + #define R_MFWD_FWPC21_LTWFM_Pos (16UL) /*!< LTWFM (Bit 16) */ + #define R_MFWD_FWPC21_LTWFM_Msk (0x7f0000UL) /*!< LTWFM (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWPC22 ========================================================= */ + #define R_MFWD_FWPC22_LTWFM_Pos (16UL) /*!< LTWFM (Bit 16) */ + #define R_MFWD_FWPC22_LTWFM_Msk (0x7f0000UL) /*!< LTWFM (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTGC00 ======================================================== */ + #define R_MFWD_FWCTGC00_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC00_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC00_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC00_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC00_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC00_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC00_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC00_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC00_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC00_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC00_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC00_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC00_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC00_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC01 ======================================================== */ + #define R_MFWD_FWCTGC01_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC01_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC01_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC01_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC01_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC01_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC01_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC01_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC01_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC01_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC01_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC01_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC01_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC01_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC02 ======================================================== */ + #define R_MFWD_FWCTGC02_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC02_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC02_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC02_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC02_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC02_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC02_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC02_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC02_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC02_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC02_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC02_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC02_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC02_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC03 ======================================================== */ + #define R_MFWD_FWCTGC03_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC03_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC03_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC03_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC03_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC03_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC03_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC03_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC03_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC03_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC03_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC03_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC03_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC03_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC04 ======================================================== */ + #define R_MFWD_FWCTGC04_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC04_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC04_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC04_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC04_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC04_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC04_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC04_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC04_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC04_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC04_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC04_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC04_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC04_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC05 ======================================================== */ + #define R_MFWD_FWCTGC05_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC05_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC05_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC05_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC05_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC05_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC05_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC05_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC05_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC05_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC05_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC05_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC05_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC05_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC06 ======================================================== */ + #define R_MFWD_FWCTGC06_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC06_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC06_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC06_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC06_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC06_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC06_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC06_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC06_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC06_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC06_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC06_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC06_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC06_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC07 ======================================================== */ + #define R_MFWD_FWCTGC07_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC07_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC07_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC07_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC07_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC07_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC07_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC07_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC07_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC07_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC07_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC07_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC07_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC07_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC10 ======================================================== */ + #define R_MFWD_FWCTGC10_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC10_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTGC11 ======================================================== */ + #define R_MFWD_FWCTGC11_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC11_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTGC12 ======================================================== */ + #define R_MFWD_FWCTGC12_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC12_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTGC13 ======================================================== */ + #define R_MFWD_FWCTGC13_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC13_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTGC14 ======================================================== */ + #define R_MFWD_FWCTGC14_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC14_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTGC15 ======================================================== */ + #define R_MFWD_FWCTGC15_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC15_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTGC16 ======================================================== */ + #define R_MFWD_FWCTGC16_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC16_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTGC17 ======================================================== */ + #define R_MFWD_FWCTGC17_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC17_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTTC00 ======================================================== */ + #define R_MFWD_FWCTTC00_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC00_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC00_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC00_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC01 ======================================================== */ + #define R_MFWD_FWCTTC01_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC01_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC01_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC01_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC02 ======================================================== */ + #define R_MFWD_FWCTTC02_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC02_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC02_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC02_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC03 ======================================================== */ + #define R_MFWD_FWCTTC03_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC03_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC03_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC03_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC04 ======================================================== */ + #define R_MFWD_FWCTTC04_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC04_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC04_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC04_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC05 ======================================================== */ + #define R_MFWD_FWCTTC05_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC05_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC05_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC05_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC06 ======================================================== */ + #define R_MFWD_FWCTTC06_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC06_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC06_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC06_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC07 ======================================================== */ + #define R_MFWD_FWCTTC07_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC07_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC07_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC07_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC10 ======================================================== */ + #define R_MFWD_FWCTTC10_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC10_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC10_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC10_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC10_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC10_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC10_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC10_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC11 ======================================================== */ + #define R_MFWD_FWCTTC11_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC11_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC11_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC11_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC11_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC11_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC11_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC11_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC12 ======================================================== */ + #define R_MFWD_FWCTTC12_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC12_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC12_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC12_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC12_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC12_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC12_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC12_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC13 ======================================================== */ + #define R_MFWD_FWCTTC13_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC13_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC13_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC13_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC13_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC13_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC13_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC13_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC14 ======================================================== */ + #define R_MFWD_FWCTTC14_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC14_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC14_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC14_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC14_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC14_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC14_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC14_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC15 ======================================================== */ + #define R_MFWD_FWCTTC15_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC15_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC15_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC15_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC15_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC15_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC15_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC15_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC16 ======================================================== */ + #define R_MFWD_FWCTTC16_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC16_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC16_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC16_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC16_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC16_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC16_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC16_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC17 ======================================================== */ + #define R_MFWD_FWCTTC17_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC17_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC17_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC17_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC17_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC17_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC17_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC17_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC200 ======================================================= */ + #define R_MFWD_FWCTTC200_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC200_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTTC201 ======================================================= */ + #define R_MFWD_FWCTTC201_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC201_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTTC202 ======================================================= */ + #define R_MFWD_FWCTTC202_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC202_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTTC203 ======================================================= */ + #define R_MFWD_FWCTTC203_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC203_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTTC204 ======================================================= */ + #define R_MFWD_FWCTTC204_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC204_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTTC205 ======================================================= */ + #define R_MFWD_FWCTTC205_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC205_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTTC206 ======================================================= */ + #define R_MFWD_FWCTTC206_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC206_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTTC207 ======================================================= */ + #define R_MFWD_FWCTTC207_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC207_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTSC00 ======================================================== */ + #define R_MFWD_FWCTSC00_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC00_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC01 ======================================================== */ + #define R_MFWD_FWCTSC01_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC01_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC02 ======================================================== */ + #define R_MFWD_FWCTSC02_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC02_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC03 ======================================================== */ + #define R_MFWD_FWCTSC03_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC03_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC04 ======================================================== */ + #define R_MFWD_FWCTSC04_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC04_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC05 ======================================================== */ + #define R_MFWD_FWCTSC05_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC05_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC06 ======================================================== */ + #define R_MFWD_FWCTSC06_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC06_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC07 ======================================================== */ + #define R_MFWD_FWCTSC07_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC07_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC10 ======================================================== */ + #define R_MFWD_FWCTSC10_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC10_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC10_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC10_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC11 ======================================================== */ + #define R_MFWD_FWCTSC11_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC11_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC11_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC11_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC12 ======================================================== */ + #define R_MFWD_FWCTSC12_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC12_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC12_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC12_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC13 ======================================================== */ + #define R_MFWD_FWCTSC13_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC13_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC13_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC13_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC14 ======================================================== */ + #define R_MFWD_FWCTSC14_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC14_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC14_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC14_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC15 ======================================================== */ + #define R_MFWD_FWCTSC15_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC15_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC15_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC15_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC16 ======================================================== */ + #define R_MFWD_FWCTSC16_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC16_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC16_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC16_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC17 ======================================================== */ + #define R_MFWD_FWCTSC17_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC17_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC17_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC17_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC20 ======================================================== */ + #define R_MFWD_FWCTSC20_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC20_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC21 ======================================================== */ + #define R_MFWD_FWCTSC21_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC21_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC22 ======================================================== */ + #define R_MFWD_FWCTSC22_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC22_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC23 ======================================================== */ + #define R_MFWD_FWCTSC23_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC23_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC24 ======================================================== */ + #define R_MFWD_FWCTSC24_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC24_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC25 ======================================================== */ + #define R_MFWD_FWCTSC25_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC25_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC26 ======================================================== */ + #define R_MFWD_FWCTSC26_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC26_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC27 ======================================================== */ + #define R_MFWD_FWCTSC27_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC27_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC30 ======================================================== */ + #define R_MFWD_FWCTSC30_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC30_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC30_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC30_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC30_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC30_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC30_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC30_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC30_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC30_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC30_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC30_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC31 ======================================================== */ + #define R_MFWD_FWCTSC31_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC31_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC31_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC31_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC31_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC31_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC31_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC31_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC31_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC31_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC31_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC31_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC32 ======================================================== */ + #define R_MFWD_FWCTSC32_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC32_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC32_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC32_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC32_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC32_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC32_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC32_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC32_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC32_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC32_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC32_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC33 ======================================================== */ + #define R_MFWD_FWCTSC33_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC33_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC33_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC33_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC33_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC33_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC33_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC33_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC33_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC33_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC33_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC33_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC34 ======================================================== */ + #define R_MFWD_FWCTSC34_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC34_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC34_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC34_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC34_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC34_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC34_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC34_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC34_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC34_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC34_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC34_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC35 ======================================================== */ + #define R_MFWD_FWCTSC35_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC35_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC35_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC35_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC35_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC35_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC35_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC35_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC35_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC35_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC35_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC35_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC36 ======================================================== */ + #define R_MFWD_FWCTSC36_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC36_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC36_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC36_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC36_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC36_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC36_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC36_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC36_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC36_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC36_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC36_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC37 ======================================================== */ + #define R_MFWD_FWCTSC37_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC37_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC37_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC37_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC37_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC37_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC37_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC37_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC37_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC37_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC37_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC37_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC40 ======================================================== */ + #define R_MFWD_FWCTSC40_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC40_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC40_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC40_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWCTSC41 ======================================================== */ + #define R_MFWD_FWCTSC41_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC41_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC41_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC41_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWCTSC42 ======================================================== */ + #define R_MFWD_FWCTSC42_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC42_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC42_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC42_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWCTSC43 ======================================================== */ + #define R_MFWD_FWCTSC43_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC43_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC43_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC43_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWCTSC44 ======================================================== */ + #define R_MFWD_FWCTSC44_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC44_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC44_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC44_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWCTSC45 ======================================================== */ + #define R_MFWD_FWCTSC45_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC45_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC45_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC45_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWCTSC46 ======================================================== */ + #define R_MFWD_FWCTSC46_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC46_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC46_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC46_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWCTSC47 ======================================================== */ + #define R_MFWD_FWCTSC47_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC47_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC47_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC47_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWTWBFC0 ======================================================== */ + #define R_MFWD_FWTWBFC0_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC0_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC0_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC0_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC0_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC0_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC1 ======================================================== */ + #define R_MFWD_FWTWBFC1_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC1_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC1_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC1_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC1_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC1_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC2 ======================================================== */ + #define R_MFWD_FWTWBFC2_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC2_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC2_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC2_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC2_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC2_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC3 ======================================================== */ + #define R_MFWD_FWTWBFC3_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC3_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC3_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC3_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC3_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC3_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC4 ======================================================== */ + #define R_MFWD_FWTWBFC4_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC4_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC4_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC4_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC4_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC4_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC5 ======================================================== */ + #define R_MFWD_FWTWBFC5_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC5_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC5_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC5_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC5_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC5_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC6 ======================================================== */ + #define R_MFWD_FWTWBFC6_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC6_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC6_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC6_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC6_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC6_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC7 ======================================================== */ + #define R_MFWD_FWTWBFC7_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC7_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC7_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC7_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC7_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC7_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC8 ======================================================== */ + #define R_MFWD_FWTWBFC8_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC8_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC8_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC8_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC8_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC8_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC9 ======================================================== */ + #define R_MFWD_FWTWBFC9_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC9_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC9_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC9_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC9_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC9_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC10 ======================================================= */ + #define R_MFWD_FWTWBFC10_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC10_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC10_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC10_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC10_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC10_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC11 ======================================================= */ + #define R_MFWD_FWTWBFC11_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC11_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC11_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC11_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC11_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC11_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC12 ======================================================= */ + #define R_MFWD_FWTWBFC12_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC12_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC12_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC12_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC12_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC12_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC13 ======================================================= */ + #define R_MFWD_FWTWBFC13_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC13_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC13_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC13_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC13_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC13_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC14 ======================================================= */ + #define R_MFWD_FWTWBFC14_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC14_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC14_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC14_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC14_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC14_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC15 ======================================================= */ + #define R_MFWD_FWTWBFC15_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC15_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC15_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC15_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC15_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC15_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFVC0 ======================================================= */ + #define R_MFWD_FWTWBFVC0_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC0_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC0_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC0_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC1 ======================================================= */ + #define R_MFWD_FWTWBFVC1_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC1_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC1_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC1_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC2 ======================================================= */ + #define R_MFWD_FWTWBFVC2_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC2_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC2_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC2_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC3 ======================================================= */ + #define R_MFWD_FWTWBFVC3_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC3_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC3_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC3_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC4 ======================================================= */ + #define R_MFWD_FWTWBFVC4_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC4_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC4_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC4_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC5 ======================================================= */ + #define R_MFWD_FWTWBFVC5_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC5_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC5_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC5_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC6 ======================================================= */ + #define R_MFWD_FWTWBFVC6_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC6_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC6_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC6_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC7 ======================================================= */ + #define R_MFWD_FWTWBFVC7_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC7_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC7_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC7_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC8 ======================================================= */ + #define R_MFWD_FWTWBFVC8_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC8_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC8_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC8_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC9 ======================================================= */ + #define R_MFWD_FWTWBFVC9_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC9_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC9_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC9_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWTWBFVC10 ======================================================= */ + #define R_MFWD_FWTWBFVC10_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC10_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC10_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC10_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWTWBFVC11 ======================================================= */ + #define R_MFWD_FWTWBFVC11_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC11_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC11_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC11_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWTWBFVC12 ======================================================= */ + #define R_MFWD_FWTWBFVC12_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC12_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC12_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC12_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWTWBFVC13 ======================================================= */ + #define R_MFWD_FWTWBFVC13_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC13_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC13_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC13_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWTWBFVC14 ======================================================= */ + #define R_MFWD_FWTWBFVC14_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC14_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC14_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC14_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWTWBFVC15 ======================================================= */ + #define R_MFWD_FWTWBFVC15_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC15_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC15_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC15_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTHBFC0 ======================================================== */ + #define R_MFWD_FWTHBFC0_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC0_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC0_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC0_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC1 ======================================================== */ + #define R_MFWD_FWTHBFC1_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC1_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC1_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC1_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC2 ======================================================== */ + #define R_MFWD_FWTHBFC2_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC2_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC2_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC2_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC3 ======================================================== */ + #define R_MFWD_FWTHBFC3_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC3_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC3_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC3_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC4 ======================================================== */ + #define R_MFWD_FWTHBFC4_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC4_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC4_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC4_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC5 ======================================================== */ + #define R_MFWD_FWTHBFC5_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC5_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC5_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC5_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC6 ======================================================== */ + #define R_MFWD_FWTHBFC6_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC6_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC6_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC6_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC7 ======================================================== */ + #define R_MFWD_FWTHBFC7_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC7_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC7_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC7_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC8 ======================================================== */ + #define R_MFWD_FWTHBFC8_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC8_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC8_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC8_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC9 ======================================================== */ + #define R_MFWD_FWTHBFC9_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC9_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC9_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC9_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC10 ======================================================= */ + #define R_MFWD_FWTHBFC10_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC10_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC10_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC10_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC11 ======================================================= */ + #define R_MFWD_FWTHBFC11_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC11_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC11_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC11_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC12 ======================================================= */ + #define R_MFWD_FWTHBFC12_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC12_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC12_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC12_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC13 ======================================================= */ + #define R_MFWD_FWTHBFC13_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC13_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC13_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC13_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC14 ======================================================= */ + #define R_MFWD_FWTHBFC14_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC14_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC14_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC14_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC15 ======================================================= */ + #define R_MFWD_FWTHBFC15_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC15_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC15_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC15_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ====================================================== FWTHBFV0C0 ======================================================= */ + #define R_MFWD_FWTHBFV0C0_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C0_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C1 ======================================================= */ + #define R_MFWD_FWTHBFV0C1_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C1_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C2 ======================================================= */ + #define R_MFWD_FWTHBFV0C2_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C2_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C3 ======================================================= */ + #define R_MFWD_FWTHBFV0C3_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C3_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C4 ======================================================= */ + #define R_MFWD_FWTHBFV0C4_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C4_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C5 ======================================================= */ + #define R_MFWD_FWTHBFV0C5_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C5_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C6 ======================================================= */ + #define R_MFWD_FWTHBFV0C6_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C6_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C7 ======================================================= */ + #define R_MFWD_FWTHBFV0C7_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C7_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C8 ======================================================= */ + #define R_MFWD_FWTHBFV0C8_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C8_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C9 ======================================================= */ + #define R_MFWD_FWTHBFV0C9_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C9_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C10 ====================================================== */ + #define R_MFWD_FWTHBFV0C10_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C10_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C11 ====================================================== */ + #define R_MFWD_FWTHBFV0C11_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C11_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C12 ====================================================== */ + #define R_MFWD_FWTHBFV0C12_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C12_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C13 ====================================================== */ + #define R_MFWD_FWTHBFV0C13_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C13_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C14 ====================================================== */ + #define R_MFWD_FWTHBFV0C14_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C14_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C15 ====================================================== */ + #define R_MFWD_FWTHBFV0C15_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C15_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C0 ======================================================= */ + #define R_MFWD_FWTHBFV1C0_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C0_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C1 ======================================================= */ + #define R_MFWD_FWTHBFV1C1_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C1_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C2 ======================================================= */ + #define R_MFWD_FWTHBFV1C2_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C2_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C3 ======================================================= */ + #define R_MFWD_FWTHBFV1C3_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C3_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C4 ======================================================= */ + #define R_MFWD_FWTHBFV1C4_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C4_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C5 ======================================================= */ + #define R_MFWD_FWTHBFV1C5_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C5_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C6 ======================================================= */ + #define R_MFWD_FWTHBFV1C6_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C6_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C7 ======================================================= */ + #define R_MFWD_FWTHBFV1C7_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C7_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C8 ======================================================= */ + #define R_MFWD_FWTHBFV1C8_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C8_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C9 ======================================================= */ + #define R_MFWD_FWTHBFV1C9_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C9_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C10 ====================================================== */ + #define R_MFWD_FWTHBFV1C10_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C10_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C11 ====================================================== */ + #define R_MFWD_FWTHBFV1C11_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C11_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C12 ====================================================== */ + #define R_MFWD_FWTHBFV1C12_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C12_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C13 ====================================================== */ + #define R_MFWD_FWTHBFV1C13_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C13_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C14 ====================================================== */ + #define R_MFWD_FWTHBFV1C14_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C14_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C15 ====================================================== */ + #define R_MFWD_FWTHBFV1C15_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C15_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ======================================================= FWFOBFC0 ======================================================== */ + #define R_MFWD_FWFOBFC0_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC0_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC0_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC0_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC1 ======================================================== */ + #define R_MFWD_FWFOBFC1_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC1_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC1_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC1_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC2 ======================================================== */ + #define R_MFWD_FWFOBFC2_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC2_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC2_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC2_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC3 ======================================================== */ + #define R_MFWD_FWFOBFC3_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC3_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC3_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC3_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC4 ======================================================== */ + #define R_MFWD_FWFOBFC4_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC4_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC4_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC4_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC5 ======================================================== */ + #define R_MFWD_FWFOBFC5_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC5_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC5_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC5_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC6 ======================================================== */ + #define R_MFWD_FWFOBFC6_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC6_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC6_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC6_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC7 ======================================================== */ + #define R_MFWD_FWFOBFC7_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC7_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC7_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC7_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC8 ======================================================== */ + #define R_MFWD_FWFOBFC8_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC8_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC8_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC8_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC9 ======================================================== */ + #define R_MFWD_FWFOBFC9_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC9_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC9_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC9_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC10 ======================================================= */ + #define R_MFWD_FWFOBFC10_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC10_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC10_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC10_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC11 ======================================================= */ + #define R_MFWD_FWFOBFC11_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC11_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC11_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC11_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC12 ======================================================= */ + #define R_MFWD_FWFOBFC12_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC12_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC12_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC12_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC13 ======================================================= */ + #define R_MFWD_FWFOBFC13_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC13_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC13_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC13_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC14 ======================================================= */ + #define R_MFWD_FWFOBFC14_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC14_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC14_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC14_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC15 ======================================================= */ + #define R_MFWD_FWFOBFC15_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC15_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC15_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC15_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ====================================================== FWFOBFV0C0 ======================================================= */ + #define R_MFWD_FWFOBFV0C0_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C0_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C1 ======================================================= */ + #define R_MFWD_FWFOBFV0C1_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C1_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C2 ======================================================= */ + #define R_MFWD_FWFOBFV0C2_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C2_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C3 ======================================================= */ + #define R_MFWD_FWFOBFV0C3_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C3_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C4 ======================================================= */ + #define R_MFWD_FWFOBFV0C4_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C4_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C5 ======================================================= */ + #define R_MFWD_FWFOBFV0C5_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C5_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C6 ======================================================= */ + #define R_MFWD_FWFOBFV0C6_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C6_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C7 ======================================================= */ + #define R_MFWD_FWFOBFV0C7_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C7_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C8 ======================================================= */ + #define R_MFWD_FWFOBFV0C8_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C8_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C9 ======================================================= */ + #define R_MFWD_FWFOBFV0C9_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C9_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C10 ====================================================== */ + #define R_MFWD_FWFOBFV0C10_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C10_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C11 ====================================================== */ + #define R_MFWD_FWFOBFV0C11_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C11_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C12 ====================================================== */ + #define R_MFWD_FWFOBFV0C12_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C12_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C13 ====================================================== */ + #define R_MFWD_FWFOBFV0C13_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C13_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C14 ====================================================== */ + #define R_MFWD_FWFOBFV0C14_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C14_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C15 ====================================================== */ + #define R_MFWD_FWFOBFV0C15_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C15_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C0 ======================================================= */ + #define R_MFWD_FWFOBFV1C0_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C0_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C1 ======================================================= */ + #define R_MFWD_FWFOBFV1C1_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C1_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C2 ======================================================= */ + #define R_MFWD_FWFOBFV1C2_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C2_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C3 ======================================================= */ + #define R_MFWD_FWFOBFV1C3_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C3_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C4 ======================================================= */ + #define R_MFWD_FWFOBFV1C4_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C4_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C5 ======================================================= */ + #define R_MFWD_FWFOBFV1C5_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C5_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C6 ======================================================= */ + #define R_MFWD_FWFOBFV1C6_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C6_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C7 ======================================================= */ + #define R_MFWD_FWFOBFV1C7_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C7_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C8 ======================================================= */ + #define R_MFWD_FWFOBFV1C8_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C8_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C9 ======================================================= */ + #define R_MFWD_FWFOBFV1C9_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C9_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C10 ====================================================== */ + #define R_MFWD_FWFOBFV1C10_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C10_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C11 ====================================================== */ + #define R_MFWD_FWFOBFV1C11_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C11_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C12 ====================================================== */ + #define R_MFWD_FWFOBFV1C12_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C12_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C13 ====================================================== */ + #define R_MFWD_FWFOBFV1C13_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C13_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C14 ====================================================== */ + #define R_MFWD_FWFOBFV1C14_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C14_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C15 ====================================================== */ + #define R_MFWD_FWFOBFV1C15_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C15_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWRFC0 ========================================================= */ + #define R_MFWD_FWRFC0_RFM_Pos (8UL) /*!< RFM (Bit 8) */ + #define R_MFWD_FWRFC0_RFM_Msk (0x100UL) /*!< RFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWRFC0_RFOV_Pos (16UL) /*!< RFOV (Bit 16) */ + #define R_MFWD_FWRFC0_RFOV_Msk (0xff0000UL) /*!< RFOV (Bitfield-Mask: 0xff) */ +/* ======================================================== FWRFC1 ========================================================= */ + #define R_MFWD_FWRFC1_RFM_Pos (8UL) /*!< RFM (Bit 8) */ + #define R_MFWD_FWRFC1_RFM_Msk (0x100UL) /*!< RFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWRFC1_RFOV_Pos (16UL) /*!< RFOV (Bit 16) */ + #define R_MFWD_FWRFC1_RFOV_Msk (0xff0000UL) /*!< RFOV (Bitfield-Mask: 0xff) */ +/* ======================================================== FWRFVC0 ======================================================== */ + #define R_MFWD_FWRFVC0_RFSV_Pos (0UL) /*!< RFSV (Bit 0) */ + #define R_MFWD_FWRFVC0_RFSV_Msk (0xffUL) /*!< RFSV (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWRFVC0_RFRV_Pos (16UL) /*!< RFRV (Bit 16) */ + #define R_MFWD_FWRFVC0_RFRV_Msk (0xf0000UL) /*!< RFRV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWRFVC1 ======================================================== */ + #define R_MFWD_FWRFVC1_RFSV_Pos (0UL) /*!< RFSV (Bit 0) */ + #define R_MFWD_FWRFVC1_RFSV_Msk (0xffUL) /*!< RFSV (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWRFVC1_RFRV_Pos (16UL) /*!< RFRV (Bit 16) */ + #define R_MFWD_FWRFVC1_RFRV_Msk (0xf0000UL) /*!< RFRV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC0 ========================================================= */ + #define R_MFWD_FWCFC0_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC0_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC0_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC0_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC1 ========================================================= */ + #define R_MFWD_FWCFC1_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC1_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC1_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC1_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC2 ========================================================= */ + #define R_MFWD_FWCFC2_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC2_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC2_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC2_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC3 ========================================================= */ + #define R_MFWD_FWCFC3_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC3_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC3_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC3_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC4 ========================================================= */ + #define R_MFWD_FWCFC4_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC4_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC4_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC4_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC5 ========================================================= */ + #define R_MFWD_FWCFC5_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC5_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC5_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC5_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC6 ========================================================= */ + #define R_MFWD_FWCFC6_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC6_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC6_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC6_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC7 ========================================================= */ + #define R_MFWD_FWCFC7_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC7_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC7_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC7_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC8 ========================================================= */ + #define R_MFWD_FWCFC8_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC8_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC8_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC8_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC9 ========================================================= */ + #define R_MFWD_FWCFC9_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC9_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC9_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC9_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC10 ======================================================== */ + #define R_MFWD_FWCFC10_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC10_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC10_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC10_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC11 ======================================================== */ + #define R_MFWD_FWCFC11_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC11_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC11_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC11_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC12 ======================================================== */ + #define R_MFWD_FWCFC12_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC12_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC12_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC12_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC13 ======================================================== */ + #define R_MFWD_FWCFC13_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC13_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC13_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC13_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC14 ======================================================== */ + #define R_MFWD_FWCFC14_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC14_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC14_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC14_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC15 ======================================================== */ + #define R_MFWD_FWCFC15_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC15_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC15_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC15_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCFMC00 ======================================================== */ + #define R_MFWD_FWCFMC00_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC00_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC00_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC00_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC10 ======================================================== */ + #define R_MFWD_FWCFMC10_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC10_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC10_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC10_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC20 ======================================================== */ + #define R_MFWD_FWCFMC20_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC20_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC20_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC20_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC30 ======================================================== */ + #define R_MFWD_FWCFMC30_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC30_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC30_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC30_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC40 ======================================================== */ + #define R_MFWD_FWCFMC40_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC40_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC40_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC40_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC50 ======================================================== */ + #define R_MFWD_FWCFMC50_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC50_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC50_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC50_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC60 ======================================================== */ + #define R_MFWD_FWCFMC60_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC60_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC60_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC60_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC70 ======================================================== */ + #define R_MFWD_FWCFMC70_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC70_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC70_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC70_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC80 ======================================================== */ + #define R_MFWD_FWCFMC80_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC80_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC80_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC80_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC90 ======================================================== */ + #define R_MFWD_FWCFMC90_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC90_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC90_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC90_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC100 ======================================================= */ + #define R_MFWD_FWCFMC100_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC100_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC100_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC100_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC110 ======================================================= */ + #define R_MFWD_FWCFMC110_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC110_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC110_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC110_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC120 ======================================================= */ + #define R_MFWD_FWCFMC120_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC120_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC120_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC120_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC130 ======================================================= */ + #define R_MFWD_FWCFMC130_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC130_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC130_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC130_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC140 ======================================================= */ + #define R_MFWD_FWCFMC140_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC140_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC140_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC140_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC150 ======================================================= */ + #define R_MFWD_FWCFMC150_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC150_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC150_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC150_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC01 ======================================================== */ + #define R_MFWD_FWCFMC01_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC01_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC01_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC01_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC11 ======================================================== */ + #define R_MFWD_FWCFMC11_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC11_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC11_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC11_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC21 ======================================================== */ + #define R_MFWD_FWCFMC21_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC21_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC21_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC21_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC31 ======================================================== */ + #define R_MFWD_FWCFMC31_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC31_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC31_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC31_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC41 ======================================================== */ + #define R_MFWD_FWCFMC41_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC41_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC41_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC41_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC51 ======================================================== */ + #define R_MFWD_FWCFMC51_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC51_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC51_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC51_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC61 ======================================================== */ + #define R_MFWD_FWCFMC61_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC61_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC61_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC61_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC71 ======================================================== */ + #define R_MFWD_FWCFMC71_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC71_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC71_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC71_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC81 ======================================================== */ + #define R_MFWD_FWCFMC81_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC81_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC81_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC81_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC91 ======================================================== */ + #define R_MFWD_FWCFMC91_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC91_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC91_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC91_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC101 ======================================================= */ + #define R_MFWD_FWCFMC101_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC101_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC101_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC101_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC111 ======================================================= */ + #define R_MFWD_FWCFMC111_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC111_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC111_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC111_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC121 ======================================================= */ + #define R_MFWD_FWCFMC121_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC121_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC121_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC121_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC131 ======================================================= */ + #define R_MFWD_FWCFMC131_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC131_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC131_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC131_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC141 ======================================================= */ + #define R_MFWD_FWCFMC141_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC141_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC141_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC141_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC151 ======================================================= */ + #define R_MFWD_FWCFMC151_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC151_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC151_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC151_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC02 ======================================================== */ + #define R_MFWD_FWCFMC02_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC02_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC02_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC02_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC12 ======================================================== */ + #define R_MFWD_FWCFMC12_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC12_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC12_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC12_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC22 ======================================================== */ + #define R_MFWD_FWCFMC22_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC22_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC22_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC22_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC32 ======================================================== */ + #define R_MFWD_FWCFMC32_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC32_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC32_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC32_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC42 ======================================================== */ + #define R_MFWD_FWCFMC42_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC42_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC42_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC42_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC52 ======================================================== */ + #define R_MFWD_FWCFMC52_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC52_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC52_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC52_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC62 ======================================================== */ + #define R_MFWD_FWCFMC62_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC62_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC62_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC62_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC72 ======================================================== */ + #define R_MFWD_FWCFMC72_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC72_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC72_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC72_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC82 ======================================================== */ + #define R_MFWD_FWCFMC82_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC82_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC82_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC82_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC92 ======================================================== */ + #define R_MFWD_FWCFMC92_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC92_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC92_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC92_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC102 ======================================================= */ + #define R_MFWD_FWCFMC102_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC102_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC102_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC102_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC112 ======================================================= */ + #define R_MFWD_FWCFMC112_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC112_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC112_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC112_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC122 ======================================================= */ + #define R_MFWD_FWCFMC122_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC122_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC122_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC122_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC132 ======================================================= */ + #define R_MFWD_FWCFMC132_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC132_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC132_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC132_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC142 ======================================================= */ + #define R_MFWD_FWCFMC142_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC142_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC142_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC142_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC152 ======================================================= */ + #define R_MFWD_FWCFMC152_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC152_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC152_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC152_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC03 ======================================================== */ + #define R_MFWD_FWCFMC03_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC03_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC03_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC03_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC13 ======================================================== */ + #define R_MFWD_FWCFMC13_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC13_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC13_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC13_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC23 ======================================================== */ + #define R_MFWD_FWCFMC23_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC23_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC23_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC23_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC33 ======================================================== */ + #define R_MFWD_FWCFMC33_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC33_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC33_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC33_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC43 ======================================================== */ + #define R_MFWD_FWCFMC43_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC43_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC43_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC43_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC53 ======================================================== */ + #define R_MFWD_FWCFMC53_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC53_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC53_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC53_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC63 ======================================================== */ + #define R_MFWD_FWCFMC63_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC63_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC63_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC63_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC73 ======================================================== */ + #define R_MFWD_FWCFMC73_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC73_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC73_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC73_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC83 ======================================================== */ + #define R_MFWD_FWCFMC83_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC83_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC83_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC83_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC93 ======================================================== */ + #define R_MFWD_FWCFMC93_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC93_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC93_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC93_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC103 ======================================================= */ + #define R_MFWD_FWCFMC103_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC103_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC103_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC103_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC113 ======================================================= */ + #define R_MFWD_FWCFMC113_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC113_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC113_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC113_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC123 ======================================================= */ + #define R_MFWD_FWCFMC123_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC123_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC123_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC123_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC133 ======================================================= */ + #define R_MFWD_FWCFMC133_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC133_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC133_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC133_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC143 ======================================================= */ + #define R_MFWD_FWCFMC143_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC143_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC143_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC143_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC153 ======================================================= */ + #define R_MFWD_FWCFMC153_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC153_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC153_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC153_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC04 ======================================================== */ + #define R_MFWD_FWCFMC04_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC04_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC04_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC04_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC14 ======================================================== */ + #define R_MFWD_FWCFMC14_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC14_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC14_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC14_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC24 ======================================================== */ + #define R_MFWD_FWCFMC24_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC24_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC24_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC24_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC34 ======================================================== */ + #define R_MFWD_FWCFMC34_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC34_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC34_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC34_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC44 ======================================================== */ + #define R_MFWD_FWCFMC44_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC44_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC44_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC44_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC54 ======================================================== */ + #define R_MFWD_FWCFMC54_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC54_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC54_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC54_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC64 ======================================================== */ + #define R_MFWD_FWCFMC64_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC64_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC64_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC64_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC74 ======================================================== */ + #define R_MFWD_FWCFMC74_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC74_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC74_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC74_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC84 ======================================================== */ + #define R_MFWD_FWCFMC84_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC84_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC84_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC84_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC94 ======================================================== */ + #define R_MFWD_FWCFMC94_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC94_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC94_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC94_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC104 ======================================================= */ + #define R_MFWD_FWCFMC104_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC104_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC104_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC104_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC114 ======================================================= */ + #define R_MFWD_FWCFMC114_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC114_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC114_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC114_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC124 ======================================================= */ + #define R_MFWD_FWCFMC124_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC124_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC124_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC124_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC134 ======================================================= */ + #define R_MFWD_FWCFMC134_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC134_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC134_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC134_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC144 ======================================================= */ + #define R_MFWD_FWCFMC144_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC144_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC144_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC144_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC154 ======================================================= */ + #define R_MFWD_FWCFMC154_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC154_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC154_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC154_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC05 ======================================================== */ + #define R_MFWD_FWCFMC05_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC05_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC05_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC05_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC15 ======================================================== */ + #define R_MFWD_FWCFMC15_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC15_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC15_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC15_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC25 ======================================================== */ + #define R_MFWD_FWCFMC25_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC25_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC25_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC25_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC35 ======================================================== */ + #define R_MFWD_FWCFMC35_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC35_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC35_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC35_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC45 ======================================================== */ + #define R_MFWD_FWCFMC45_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC45_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC45_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC45_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC55 ======================================================== */ + #define R_MFWD_FWCFMC55_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC55_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC55_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC55_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC65 ======================================================== */ + #define R_MFWD_FWCFMC65_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC65_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC65_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC65_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC75 ======================================================== */ + #define R_MFWD_FWCFMC75_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC75_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC75_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC75_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC85 ======================================================== */ + #define R_MFWD_FWCFMC85_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC85_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC85_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC85_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC95 ======================================================== */ + #define R_MFWD_FWCFMC95_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC95_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC95_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC95_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC105 ======================================================= */ + #define R_MFWD_FWCFMC105_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC105_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC105_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC105_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC115 ======================================================= */ + #define R_MFWD_FWCFMC115_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC115_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC115_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC115_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC125 ======================================================= */ + #define R_MFWD_FWCFMC125_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC125_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC125_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC125_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC135 ======================================================= */ + #define R_MFWD_FWCFMC135_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC135_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC135_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC135_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC145 ======================================================= */ + #define R_MFWD_FWCFMC145_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC145_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC145_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC145_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC155 ======================================================= */ + #define R_MFWD_FWCFMC155_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC155_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC155_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC155_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC06 ======================================================== */ + #define R_MFWD_FWCFMC06_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC06_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC06_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC06_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC16 ======================================================== */ + #define R_MFWD_FWCFMC16_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC16_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC16_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC16_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC26 ======================================================== */ + #define R_MFWD_FWCFMC26_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC26_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC26_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC26_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC36 ======================================================== */ + #define R_MFWD_FWCFMC36_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC36_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC36_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC36_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC46 ======================================================== */ + #define R_MFWD_FWCFMC46_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC46_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC46_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC46_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC56 ======================================================== */ + #define R_MFWD_FWCFMC56_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC56_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC56_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC56_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC66 ======================================================== */ + #define R_MFWD_FWCFMC66_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC66_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC66_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC66_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC76 ======================================================== */ + #define R_MFWD_FWCFMC76_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC76_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC76_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC76_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC86 ======================================================== */ + #define R_MFWD_FWCFMC86_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC86_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC86_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC86_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC96 ======================================================== */ + #define R_MFWD_FWCFMC96_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC96_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC96_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC96_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC106 ======================================================= */ + #define R_MFWD_FWCFMC106_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC106_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC106_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC106_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC116 ======================================================= */ + #define R_MFWD_FWCFMC116_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC116_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC116_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC116_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC126 ======================================================= */ + #define R_MFWD_FWCFMC126_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC126_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC126_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC126_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC136 ======================================================= */ + #define R_MFWD_FWCFMC136_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC136_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC136_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC136_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC146 ======================================================= */ + #define R_MFWD_FWCFMC146_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC146_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC146_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC146_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC156 ======================================================= */ + #define R_MFWD_FWCFMC156_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC156_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC156_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC156_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================== FWIP4SC ======================================================== */ + #define R_MFWD_FWIP4SC_IP4IMDH_Pos (0UL) /*!< IP4IMDH (Bit 0) */ + #define R_MFWD_FWIP4SC_IP4IMDH_Msk (0x1UL) /*!< IP4IMDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IMSH_Pos (1UL) /*!< IP4IMSH (Bit 1) */ + #define R_MFWD_FWIP4SC_IP4IMSH_Msk (0x2UL) /*!< IP4IMSH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ISVH_Pos (2UL) /*!< IP4ISVH (Bit 2) */ + #define R_MFWD_FWIP4SC_IP4ISVH_Msk (0x4UL) /*!< IP4ISVH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ISPH_Pos (3UL) /*!< IP4ISPH (Bit 3) */ + #define R_MFWD_FWIP4SC_IP4ISPH_Msk (0x8UL) /*!< IP4ISPH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ISDH_Pos (4UL) /*!< IP4ISDH (Bit 4) */ + #define R_MFWD_FWIP4SC_IP4ISDH_Msk (0x10UL) /*!< IP4ISDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ICVH_Pos (5UL) /*!< IP4ICVH (Bit 5) */ + #define R_MFWD_FWIP4SC_IP4ICVH_Msk (0x20UL) /*!< IP4ICVH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ICPH_Pos (6UL) /*!< IP4ICPH (Bit 6) */ + #define R_MFWD_FWIP4SC_IP4ICPH_Msk (0x40UL) /*!< IP4ICPH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ICDH_Pos (7UL) /*!< IP4ICDH (Bit 7) */ + #define R_MFWD_FWIP4SC_IP4ICDH_Msk (0x80UL) /*!< IP4ICDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IISH_Pos (8UL) /*!< IP4IISH (Bit 8) */ + #define R_MFWD_FWIP4SC_IP4IISH_Msk (0x100UL) /*!< IP4IISH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IIDH_Pos (9UL) /*!< IP4IIDH (Bit 9) */ + #define R_MFWD_FWIP4SC_IP4IIDH_Msk (0x200UL) /*!< IP4IIDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IPH_Pos (10UL) /*!< IP4IPH (Bit 10) */ + #define R_MFWD_FWIP4SC_IP4IPH_Msk (0x400UL) /*!< IP4IPH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ISPTH_Pos (11UL) /*!< IP4ISPTH (Bit 11) */ + #define R_MFWD_FWIP4SC_IP4ISPTH_Msk (0x800UL) /*!< IP4ISPTH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IDPTH_Pos (12UL) /*!< IP4IDPTH (Bit 12) */ + #define R_MFWD_FWIP4SC_IP4IDPTH_Msk (0x1000UL) /*!< IP4IDPTH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ISVS_Pos (16UL) /*!< IP4ISVS (Bit 16) */ + #define R_MFWD_FWIP4SC_IP4ISVS_Msk (0x10000UL) /*!< IP4ISVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ISPS_Pos (17UL) /*!< IP4ISPS (Bit 17) */ + #define R_MFWD_FWIP4SC_IP4ISPS_Msk (0x20000UL) /*!< IP4ISPS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ISDS_Pos (18UL) /*!< IP4ISDS (Bit 18) */ + #define R_MFWD_FWIP4SC_IP4ISDS_Msk (0x40000UL) /*!< IP4ISDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ICVS_Pos (19UL) /*!< IP4ICVS (Bit 19) */ + #define R_MFWD_FWIP4SC_IP4ICVS_Msk (0x80000UL) /*!< IP4ICVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ICPS_Pos (20UL) /*!< IP4ICPS (Bit 20) */ + #define R_MFWD_FWIP4SC_IP4ICPS_Msk (0x100000UL) /*!< IP4ICPS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ICDS_Pos (21UL) /*!< IP4ICDS (Bit 21) */ + #define R_MFWD_FWIP4SC_IP4ICDS_Msk (0x200000UL) /*!< IP4ICDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IISS_Pos (22UL) /*!< IP4IISS (Bit 22) */ + #define R_MFWD_FWIP4SC_IP4IISS_Msk (0x400000UL) /*!< IP4IISS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IIDS_Pos (23UL) /*!< IP4IIDS (Bit 23) */ + #define R_MFWD_FWIP4SC_IP4IIDS_Msk (0x800000UL) /*!< IP4IIDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IDPTS_Pos (24UL) /*!< IP4IDPTS (Bit 24) */ + #define R_MFWD_FWIP4SC_IP4IDPTS_Msk (0x1000000UL) /*!< IP4IDPTS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWIP6SC ======================================================== */ + #define R_MFWD_FWIP6SC_IP6IMDH_Pos (0UL) /*!< IP6IMDH (Bit 0) */ + #define R_MFWD_FWIP6SC_IP6IMDH_Msk (0x1UL) /*!< IP6IMDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6IMSH_Pos (1UL) /*!< IP6IMSH (Bit 1) */ + #define R_MFWD_FWIP6SC_IP6IMSH_Msk (0x2UL) /*!< IP6IMSH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ISVH_Pos (2UL) /*!< IP6ISVH (Bit 2) */ + #define R_MFWD_FWIP6SC_IP6ISVH_Msk (0x4UL) /*!< IP6ISVH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ISPH_Pos (3UL) /*!< IP6ISPH (Bit 3) */ + #define R_MFWD_FWIP6SC_IP6ISPH_Msk (0x8UL) /*!< IP6ISPH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ISDH_Pos (4UL) /*!< IP6ISDH (Bit 4) */ + #define R_MFWD_FWIP6SC_IP6ISDH_Msk (0x10UL) /*!< IP6ISDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ICVH_Pos (5UL) /*!< IP6ICVH (Bit 5) */ + #define R_MFWD_FWIP6SC_IP6ICVH_Msk (0x20UL) /*!< IP6ICVH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ICPH_Pos (6UL) /*!< IP6ICPH (Bit 6) */ + #define R_MFWD_FWIP6SC_IP6ICPH_Msk (0x40UL) /*!< IP6ICPH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ICDH_Pos (7UL) /*!< IP6ICDH (Bit 7) */ + #define R_MFWD_FWIP6SC_IP6ICDH_Msk (0x80UL) /*!< IP6ICDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6IISH_Pos (8UL) /*!< IP6IISH (Bit 8) */ + #define R_MFWD_FWIP6SC_IP6IISH_Msk (0x100UL) /*!< IP6IISH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6IIDH_Pos (9UL) /*!< IP6IIDH (Bit 9) */ + #define R_MFWD_FWIP6SC_IP6IIDH_Msk (0x200UL) /*!< IP6IIDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6IPH_Pos (10UL) /*!< IP6IPH (Bit 10) */ + #define R_MFWD_FWIP6SC_IP6IPH_Msk (0x400UL) /*!< IP6IPH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ISPTH_Pos (11UL) /*!< IP6ISPTH (Bit 11) */ + #define R_MFWD_FWIP6SC_IP6ISPTH_Msk (0x800UL) /*!< IP6ISPTH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6IDPTH_Pos (12UL) /*!< IP6IDPTH (Bit 12) */ + #define R_MFWD_FWIP6SC_IP6IDPTH_Msk (0x1000UL) /*!< IP6IDPTH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ISVS_Pos (16UL) /*!< IP6ISVS (Bit 16) */ + #define R_MFWD_FWIP6SC_IP6ISVS_Msk (0x10000UL) /*!< IP6ISVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ISPS_Pos (17UL) /*!< IP6ISPS (Bit 17) */ + #define R_MFWD_FWIP6SC_IP6ISPS_Msk (0x20000UL) /*!< IP6ISPS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ISDS_Pos (18UL) /*!< IP6ISDS (Bit 18) */ + #define R_MFWD_FWIP6SC_IP6ISDS_Msk (0x40000UL) /*!< IP6ISDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ICVS_Pos (19UL) /*!< IP6ICVS (Bit 19) */ + #define R_MFWD_FWIP6SC_IP6ICVS_Msk (0x80000UL) /*!< IP6ICVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ICPS_Pos (20UL) /*!< IP6ICPS (Bit 20) */ + #define R_MFWD_FWIP6SC_IP6ICPS_Msk (0x100000UL) /*!< IP6ICPS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ICDS_Pos (21UL) /*!< IP6ICDS (Bit 21) */ + #define R_MFWD_FWIP6SC_IP6ICDS_Msk (0x200000UL) /*!< IP6ICDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6II0S_Pos (22UL) /*!< IP6II0S (Bit 22) */ + #define R_MFWD_FWIP6SC_IP6II0S_Msk (0x400000UL) /*!< IP6II0S (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6II1S_Pos (23UL) /*!< IP6II1S (Bit 23) */ + #define R_MFWD_FWIP6SC_IP6II1S_Msk (0x800000UL) /*!< IP6II1S (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6IDPTS_Pos (24UL) /*!< IP6IDPTS (Bit 24) */ + #define R_MFWD_FWIP6SC_IP6IDPTS_Msk (0x1000000UL) /*!< IP6IDPTS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWIP6OC ======================================================== */ + #define R_MFWD_FWIP6OC_IP6IPOM_Pos (0UL) /*!< IP6IPOM (Bit 0) */ + #define R_MFWD_FWIP6OC_IP6IPOM_Msk (0x1UL) /*!< IP6IPOM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6OC_IP6IPO_Pos (4UL) /*!< IP6IPO (Bit 4) */ + #define R_MFWD_FWIP6OC_IP6IPO_Msk (0xf0UL) /*!< IP6IPO (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWL2SC ========================================================= */ + #define R_MFWD_FWL2SC_L2IMDS_Pos (0UL) /*!< L2IMDS (Bit 0) */ + #define R_MFWD_FWL2SC_L2IMDS_Msk (0x1UL) /*!< L2IMDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL2SC_L2IMSS_Pos (1UL) /*!< L2IMSS (Bit 1) */ + #define R_MFWD_FWL2SC_L2IMSS_Msk (0x2UL) /*!< L2IMSS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL2SC_L2ISVS_Pos (2UL) /*!< L2ISVS (Bit 2) */ + #define R_MFWD_FWL2SC_L2ISVS_Msk (0x4UL) /*!< L2ISVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL2SC_L2ISPS_Pos (3UL) /*!< L2ISPS (Bit 3) */ + #define R_MFWD_FWL2SC_L2ISPS_Msk (0x8UL) /*!< L2ISPS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL2SC_L2ISDS_Pos (4UL) /*!< L2ISDS (Bit 4) */ + #define R_MFWD_FWL2SC_L2ISDS_Msk (0x10UL) /*!< L2ISDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL2SC_L2ICVS_Pos (5UL) /*!< L2ICVS (Bit 5) */ + #define R_MFWD_FWL2SC_L2ICVS_Msk (0x20UL) /*!< L2ICVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL2SC_L2ICPS_Pos (6UL) /*!< L2ICPS (Bit 6) */ + #define R_MFWD_FWL2SC_L2ICPS_Msk (0x40UL) /*!< L2ICPS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL2SC_L2ICDS_Pos (7UL) /*!< L2ICDS (Bit 7) */ + #define R_MFWD_FWL2SC_L2ICDS_Msk (0x80UL) /*!< L2ICDS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWSFHEC ======================================================== */ + #define R_MFWD_FWSFHEC_IP4HE_Pos (0UL) /*!< IP4HE (Bit 0) */ + #define R_MFWD_FWSFHEC_IP4HE_Msk (0xffffUL) /*!< IP4HE (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWSFHEC_IP6HE_Pos (16UL) /*!< IP6HE (Bit 16) */ + #define R_MFWD_FWSFHEC_IP6HE_Msk (0xffff0000UL) /*!< IP6HE (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWSHCR0 ======================================================== */ + #define R_MFWD_FWSHCR0_SHCMDP0_Pos (0UL) /*!< SHCMDP0 (Bit 0) */ + #define R_MFWD_FWSHCR0_SHCMDP0_Msk (0xffffffffUL) /*!< SHCMDP0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWSHCR1 ======================================================== */ + #define R_MFWD_FWSHCR1_SHCMSP0_Pos (0UL) /*!< SHCMSP0 (Bit 0) */ + #define R_MFWD_FWSHCR1_SHCMSP0_Msk (0xffffUL) /*!< SHCMSP0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWSHCR1_SHCMDP1_Pos (16UL) /*!< SHCMDP1 (Bit 16) */ + #define R_MFWD_FWSHCR1_SHCMDP1_Msk (0xffff0000UL) /*!< SHCMDP1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWSHCR2 ======================================================== */ + #define R_MFWD_FWSHCR2_SHCMSP1_Pos (0UL) /*!< SHCMSP1 (Bit 0) */ + #define R_MFWD_FWSHCR2_SHCMSP1_Msk (0xffffffffUL) /*!< SHCMSP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWSHCR3 ======================================================== */ + #define R_MFWD_FWSHCR3_SHCCV_Pos (0UL) /*!< SHCCV (Bit 0) */ + #define R_MFWD_FWSHCR3_SHCCV_Msk (0xfffUL) /*!< SHCCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWSHCR3_SHCCD_Pos (12UL) /*!< SHCCD (Bit 12) */ + #define R_MFWD_FWSHCR3_SHCCD_Msk (0x1000UL) /*!< SHCCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWSHCR3_SHCCP_Pos (13UL) /*!< SHCCP (Bit 13) */ + #define R_MFWD_FWSHCR3_SHCCP_Msk (0xe000UL) /*!< SHCCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWSHCR3_SHCSV_Pos (16UL) /*!< SHCSV (Bit 16) */ + #define R_MFWD_FWSHCR3_SHCSV_Msk (0xfff0000UL) /*!< SHCSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWSHCR3_SHCSD_Pos (28UL) /*!< SHCSD (Bit 28) */ + #define R_MFWD_FWSHCR3_SHCSD_Msk (0x10000000UL) /*!< SHCSD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWSHCR3_SHCSP_Pos (29UL) /*!< SHCSP (Bit 29) */ + #define R_MFWD_FWSHCR3_SHCSP_Msk (0xe0000000UL) /*!< SHCSP (Bitfield-Mask: 0x07) */ +/* ======================================================== FWSHCR4 ======================================================== */ + #define R_MFWD_FWSHCR4_SHCP_Pos (0UL) /*!< SHCP (Bit 0) */ + #define R_MFWD_FWSHCR4_SHCP_Msk (0xffUL) /*!< SHCP (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSHCR4_SHCFF_Pos (16UL) /*!< SHCFF (Bit 16) */ + #define R_MFWD_FWSHCR4_SHCFF_Msk (0x10000UL) /*!< SHCFF (Bitfield-Mask: 0x01) */ +/* ======================================================== FWSHCR5 ======================================================== */ + #define R_MFWD_FWSHCR5_SHCISP0_Pos (0UL) /*!< SHCISP0 (Bit 0) */ + #define R_MFWD_FWSHCR5_SHCISP0_Msk (0xffffffffUL) /*!< SHCISP0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWSHCR6 ======================================================== */ + #define R_MFWD_FWSHCR6_SHCISP1_Pos (0UL) /*!< SHCISP1 (Bit 0) */ + #define R_MFWD_FWSHCR6_SHCISP1_Msk (0xffffffffUL) /*!< SHCISP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWSHCR7 ======================================================== */ + #define R_MFWD_FWSHCR7_SHCISP2_Pos (0UL) /*!< SHCISP2 (Bit 0) */ + #define R_MFWD_FWSHCR7_SHCISP2_Msk (0xffffffffUL) /*!< SHCISP2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWSHCR8 ======================================================== */ + #define R_MFWD_FWSHCR8_SHCISP3_Pos (0UL) /*!< SHCISP3 (Bit 0) */ + #define R_MFWD_FWSHCR8_SHCISP3_Msk (0xffffffffUL) /*!< SHCISP3 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWSHCR9 ======================================================== */ + #define R_MFWD_FWSHCR9_SHCIDP0_Pos (0UL) /*!< SHCIDP0 (Bit 0) */ + #define R_MFWD_FWSHCR9_SHCIDP0_Msk (0xffffffffUL) /*!< SHCIDP0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWSHCR10 ======================================================== */ + #define R_MFWD_FWSHCR10_SHCIDP1_Pos (0UL) /*!< SHCIDP1 (Bit 0) */ + #define R_MFWD_FWSHCR10_SHCIDP1_Msk (0xffffffffUL) /*!< SHCIDP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWSHCR11 ======================================================== */ + #define R_MFWD_FWSHCR11_SHCIDP2_Pos (0UL) /*!< SHCIDP2 (Bit 0) */ + #define R_MFWD_FWSHCR11_SHCIDP2_Msk (0xffffffffUL) /*!< SHCIDP2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWSHCR12 ======================================================== */ + #define R_MFWD_FWSHCR12_SHCIDP3_Pos (0UL) /*!< SHCIDP3 (Bit 0) */ + #define R_MFWD_FWSHCR12_SHCIDP3_Msk (0xffffffffUL) /*!< SHCIDP3 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWSHCR13 ======================================================== */ + #define R_MFWD_FWSHCR13_SHCDP_Pos (0UL) /*!< SHCDP (Bit 0) */ + #define R_MFWD_FWSHCR13_SHCDP_Msk (0xffffUL) /*!< SHCDP (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWSHCR13_SHCSP_Pos (16UL) /*!< SHCSP (Bit 16) */ + #define R_MFWD_FWSHCR13_SHCSP_Msk (0xffff0000UL) /*!< SHCSP (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWSHCRR ======================================================== */ + #define R_MFWD_FWSHCRR_SHCR_Pos (0UL) /*!< SHCR (Bit 0) */ + #define R_MFWD_FWSHCRR_SHCR_Msk (0xffffUL) /*!< SHCR (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWSHCRR_SHC_Pos (31UL) /*!< SHC (Bit 31) */ + #define R_MFWD_FWSHCRR_SHC_Msk (0x80000000UL) /*!< SHC (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHHEC ======================================================== */ + #define R_MFWD_FWLTHHEC_LTHHMC_Pos (0UL) /*!< LTHHMC (Bit 0) */ + #define R_MFWD_FWLTHHEC_LTHHMC_Msk (0x3ffUL) /*!< LTHHMC (Bitfield-Mask: 0x3ff) */ + #define R_MFWD_FWLTHHEC_LTHHMUE_Pos (16UL) /*!< LTHHMUE (Bit 16) */ + #define R_MFWD_FWLTHHEC_LTHHMUE_Msk (0x7ff0000UL) /*!< LTHHMUE (Bitfield-Mask: 0x7ff) */ +/* ======================================================== FWLTHHC ======================================================== */ + #define R_MFWD_FWLTHHC_LTHHE_Pos (0UL) /*!< LTHHE (Bit 0) */ + #define R_MFWD_FWLTHHC_LTHHE_Msk (0x3ffUL) /*!< LTHHE (Bitfield-Mask: 0x3ff) */ +/* ======================================================= FWLTHTL0 ======================================================== */ + #define R_MFWD_FWLTHTL0_LTHSLP0_Pos (0UL) /*!< LTHSLP0 (Bit 0) */ + #define R_MFWD_FWLTHTL0_LTHSLP0_Msk (0x7UL) /*!< LTHSLP0 (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWLTHTL0_LTHSLL_Pos (8UL) /*!< LTHSLL (Bit 8) */ + #define R_MFWD_FWLTHTL0_LTHSLL_Msk (0x100UL) /*!< LTHSLL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTL0_LTHED_Pos (16UL) /*!< LTHED (Bit 16) */ + #define R_MFWD_FWLTHTL0_LTHED_Msk (0x10000UL) /*!< LTHED (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTL1 ======================================================== */ + #define R_MFWD_FWLTHTL1_LTHSLP1_Pos (0UL) /*!< LTHSLP1 (Bit 0) */ + #define R_MFWD_FWLTHTL1_LTHSLP1_Msk (0xffffffffUL) /*!< LTHSLP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTL2 ======================================================== */ + #define R_MFWD_FWLTHTL2_LTHSLP2_Pos (0UL) /*!< LTHSLP2 (Bit 0) */ + #define R_MFWD_FWLTHTL2_LTHSLP2_Msk (0xffffffffUL) /*!< LTHSLP2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTL3 ======================================================== */ + #define R_MFWD_FWLTHTL3_LTHSLP3_Pos (0UL) /*!< LTHSLP3 (Bit 0) */ + #define R_MFWD_FWLTHTL3_LTHSLP3_Msk (0xffffffffUL) /*!< LTHSLP3 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTL4 ======================================================== */ + #define R_MFWD_FWLTHTL4_LTHSLP4_Pos (0UL) /*!< LTHSLP4 (Bit 0) */ + #define R_MFWD_FWLTHTL4_LTHSLP4_Msk (0xffffffffUL) /*!< LTHSLP4 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTL5 ======================================================== */ + #define R_MFWD_FWLTHTL5_LTHMSDUNL_Pos (16UL) /*!< LTHMSDUNL (Bit 16) */ + #define R_MFWD_FWLTHTL5_LTHMSDUNL_Msk (0xf0000UL) /*!< LTHMSDUNL (Bitfield-Mask: 0x0f) */ + #define R_MFWD_FWLTHTL5_LTHMSDUVL_Pos (31UL) /*!< LTHMSDUVL (Bit 31) */ + #define R_MFWD_FWLTHTL5_LTHMSDUVL_Msk (0x80000000UL) /*!< LTHMSDUVL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTL6 ======================================================== */ + #define R_MFWD_FWLTHTL6_LTHFRERNL_Pos (0UL) /*!< LTHFRERNL (Bit 0) */ + #define R_MFWD_FWLTHTL6_LTHFRERNL_Msk (0x7fUL) /*!< LTHFRERNL (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWLTHTL6_LTHFRERVL_Pos (15UL) /*!< LTHFRERVL (Bit 15) */ + #define R_MFWD_FWLTHTL6_LTHFRERVL_Msk (0x8000UL) /*!< LTHFRERVL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTL6_LTHMTRNL_Pos (16UL) /*!< LTHMTRNL (Bit 16) */ + #define R_MFWD_FWLTHTL6_LTHMTRNL_Msk (0x1f0000UL) /*!< LTHMTRNL (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWLTHTL6_LTHMTRVL_Pos (31UL) /*!< LTHMTRVL (Bit 31) */ + #define R_MFWD_FWLTHTL6_LTHMTRVL_Msk (0x80000000UL) /*!< LTHMTRVL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTL7 ======================================================== */ + #define R_MFWD_FWLTHTL7_LTHRNL_Pos (0UL) /*!< LTHRNL (Bit 0) */ + #define R_MFWD_FWLTHTL7_LTHRNL_Msk (0xffUL) /*!< LTHRNL (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWLTHTL7_LTHRVL_Pos (15UL) /*!< LTHRVL (Bit 15) */ + #define R_MFWD_FWLTHTL7_LTHRVL_Msk (0x8000UL) /*!< LTHRVL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTL7_LTHSLVL_Pos (16UL) /*!< LTHSLVL (Bit 16) */ + #define R_MFWD_FWLTHTL7_LTHSLVL_Msk (0x7f0000UL) /*!< LTHSLVL (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWLTHTL80 ======================================================= */ + #define R_MFWD_FWLTHTL80_LTHCSDL_Pos (0UL) /*!< LTHCSDL (Bit 0) */ + #define R_MFWD_FWLTHTL80_LTHCSDL_Msk (0x7fUL) /*!< LTHCSDL (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWLTHTL9 ======================================================== */ + #define R_MFWD_FWLTHTL9_LTHDVL_Pos (0UL) /*!< LTHDVL (Bit 0) */ + #define R_MFWD_FWLTHTL9_LTHDVL_Msk (0x7fUL) /*!< LTHDVL (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWLTHTL9_LTHIPVL_Pos (16UL) /*!< LTHIPVL (Bit 16) */ + #define R_MFWD_FWLTHTL9_LTHIPVL_Msk (0x70000UL) /*!< LTHIPVL (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWLTHTL9_LTHIPUL_Pos (19UL) /*!< LTHIPUL (Bit 19) */ + #define R_MFWD_FWLTHTL9_LTHIPUL_Msk (0x80000UL) /*!< LTHIPUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTL9_LTHEMEL_Pos (20UL) /*!< LTHEMEL (Bit 20) */ + #define R_MFWD_FWLTHTL9_LTHEMEL_Msk (0x100000UL) /*!< LTHEMEL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTL9_LTHCMEL_Pos (21UL) /*!< LTHCMEL (Bit 21) */ + #define R_MFWD_FWLTHTL9_LTHCMEL_Msk (0x200000UL) /*!< LTHCMEL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTLR ======================================================== */ + #define R_MFWD_FWLTHTLR_LTHLF_Pos (0UL) /*!< LTHLF (Bit 0) */ + #define R_MFWD_FWLTHTLR_LTHLF_Msk (0x1UL) /*!< LTHLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTLR_LTHLSF_Pos (1UL) /*!< LTHLSF (Bit 1) */ + #define R_MFWD_FWLTHTLR_LTHLSF_Msk (0x2UL) /*!< LTHLSF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTLR_LTHLEF_Pos (2UL) /*!< LTHLEF (Bit 2) */ + #define R_MFWD_FWLTHTLR_LTHLEF_Msk (0x4UL) /*!< LTHLEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTLR_LTHLO_Pos (3UL) /*!< LTHLO (Bit 3) */ + #define R_MFWD_FWLTHTLR_LTHLO_Msk (0x8UL) /*!< LTHLO (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTLR_LTHLCN_Pos (16UL) /*!< LTHLCN (Bit 16) */ + #define R_MFWD_FWLTHTLR_LTHLCN_Msk (0x3ff0000UL) /*!< LTHLCN (Bitfield-Mask: 0x3ff) */ + #define R_MFWD_FWLTHTLR_LTHTL_Pos (31UL) /*!< LTHTL (Bit 31) */ + #define R_MFWD_FWLTHTLR_LTHTL_Msk (0x80000000UL) /*!< LTHTL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTIM ======================================================== */ + #define R_MFWD_FWLTHTIM_LTHTIOG_Pos (0UL) /*!< LTHTIOG (Bit 0) */ + #define R_MFWD_FWLTHTIM_LTHTIOG_Msk (0x1UL) /*!< LTHTIOG (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTIM_LTHTR_Pos (1UL) /*!< LTHTR (Bit 1) */ + #define R_MFWD_FWLTHTIM_LTHTR_Msk (0x2UL) /*!< LTHTR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTEM ======================================================== */ + #define R_MFWD_FWLTHTEM_LTHTEN_Pos (0UL) /*!< LTHTEN (Bit 0) */ + #define R_MFWD_FWLTHTEM_LTHTEN_Msk (0x7ffUL) /*!< LTHTEN (Bitfield-Mask: 0x7ff) */ + #define R_MFWD_FWLTHTEM_LTHTUEN_Pos (16UL) /*!< LTHTUEN (Bit 16) */ + #define R_MFWD_FWLTHTEM_LTHTUEN_Msk (0x7ff0000UL) /*!< LTHTUEN (Bitfield-Mask: 0x7ff) */ +/* ======================================================= FWLTHTS0 ======================================================== */ + #define R_MFWD_FWLTHTS0_LTHSSP0_Pos (0UL) /*!< LTHSSP0 (Bit 0) */ + #define R_MFWD_FWLTHTS0_LTHSSP0_Msk (0x7UL) /*!< LTHSSP0 (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWLTHTS0_LTHSSPFS_Pos (24UL) /*!< LTHSSPFS (Bit 24) */ + #define R_MFWD_FWLTHTS0_LTHSSPFS_Msk (0x1000000UL) /*!< LTHSSPFS (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTS1 ======================================================== */ + #define R_MFWD_FWLTHTS1_LTHSSP1_Pos (0UL) /*!< LTHSSP1 (Bit 0) */ + #define R_MFWD_FWLTHTS1_LTHSSP1_Msk (0xffffffffUL) /*!< LTHSSP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTS2 ======================================================== */ + #define R_MFWD_FWLTHTS2_LTHSSP2_Pos (0UL) /*!< LTHSSP2 (Bit 0) */ + #define R_MFWD_FWLTHTS2_LTHSSP2_Msk (0xffffffffUL) /*!< LTHSSP2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTS3 ======================================================== */ + #define R_MFWD_FWLTHTS3_LTHSSP3_Pos (0UL) /*!< LTHSSP3 (Bit 0) */ + #define R_MFWD_FWLTHTS3_LTHSSP3_Msk (0xffffffffUL) /*!< LTHSSP3 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTS4 ======================================================== */ + #define R_MFWD_FWLTHTS4_LTHSSP4_Pos (0UL) /*!< LTHSSP4 (Bit 0) */ + #define R_MFWD_FWLTHTS4_LTHSSP4_Msk (0xffffffffUL) /*!< LTHSSP4 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTSR0 ======================================================= */ + #define R_MFWD_FWLTHTSR0_LTHSEF_Pos (0UL) /*!< LTHSEF (Bit 0) */ + #define R_MFWD_FWLTHTSR0_LTHSEF_Msk (0x1UL) /*!< LTHSEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTSR0_LTHSNF_Pos (1UL) /*!< LTHSNF (Bit 1) */ + #define R_MFWD_FWLTHTSR0_LTHSNF_Msk (0x2UL) /*!< LTHSNF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTSR0_LTHSLS_Pos (8UL) /*!< LTHSLS (Bit 8) */ + #define R_MFWD_FWLTHTSR0_LTHSLS_Msk (0x100UL) /*!< LTHSLS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTSR0_LTHSCN_Pos (16UL) /*!< LTHSCN (Bit 16) */ + #define R_MFWD_FWLTHTSR0_LTHSCN_Msk (0x3ff0000UL) /*!< LTHSCN (Bitfield-Mask: 0x3ff) */ + #define R_MFWD_FWLTHTSR0_LTHTS_Pos (31UL) /*!< LTHTS (Bit 31) */ + #define R_MFWD_FWLTHTSR0_LTHTS_Msk (0x80000000UL) /*!< LTHTS (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTSR1 ======================================================= */ + #define R_MFWD_FWLTHTSR1_LTHMSDUNS_Pos (16UL) /*!< LTHMSDUNS (Bit 16) */ + #define R_MFWD_FWLTHTSR1_LTHMSDUNS_Msk (0xf0000UL) /*!< LTHMSDUNS (Bitfield-Mask: 0x0f) */ + #define R_MFWD_FWLTHTSR1_LTHMSDUVS_Pos (31UL) /*!< LTHMSDUVS (Bit 31) */ + #define R_MFWD_FWLTHTSR1_LTHMSDUVS_Msk (0x80000000UL) /*!< LTHMSDUVS (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTSR2 ======================================================= */ + #define R_MFWD_FWLTHTSR2_LTHFRERNS_Pos (0UL) /*!< LTHFRERNS (Bit 0) */ + #define R_MFWD_FWLTHTSR2_LTHFRERNS_Msk (0x3fUL) /*!< LTHFRERNS (Bitfield-Mask: 0x3f) */ + #define R_MFWD_FWLTHTSR2_LTHFRERVS_Pos (15UL) /*!< LTHFRERVS (Bit 15) */ + #define R_MFWD_FWLTHTSR2_LTHFRERVS_Msk (0x8000UL) /*!< LTHFRERVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTSR2_LTHMTRNS_Pos (16UL) /*!< LTHMTRNS (Bit 16) */ + #define R_MFWD_FWLTHTSR2_LTHMTRNS_Msk (0x1f0000UL) /*!< LTHMTRNS (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWLTHTSR2_LTHMTRVS_Pos (31UL) /*!< LTHMTRVS (Bit 31) */ + #define R_MFWD_FWLTHTSR2_LTHMTRVS_Msk (0x80000000UL) /*!< LTHMTRVS (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTSR3 ======================================================= */ + #define R_MFWD_FWLTHTSR3_LTHRNS_Pos (0UL) /*!< LTHRNS (Bit 0) */ + #define R_MFWD_FWLTHTSR3_LTHRNS_Msk (0xffUL) /*!< LTHRNS (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWLTHTSR3_LTHRVS_Pos (15UL) /*!< LTHRVS (Bit 15) */ + #define R_MFWD_FWLTHTSR3_LTHRVS_Msk (0x8000UL) /*!< LTHRVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTSR3_LTHSLVS_Pos (16UL) /*!< LTHSLVS (Bit 16) */ + #define R_MFWD_FWLTHTSR3_LTHSLVS_Msk (0x7f0000UL) /*!< LTHSLVS (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWLTHTSR40 ======================================================= */ + #define R_MFWD_FWLTHTSR40_LTHCSDS_Pos (0UL) /*!< LTHCSDS (Bit 0) */ + #define R_MFWD_FWLTHTSR40_LTHCSDS_Msk (0x7fUL) /*!< LTHCSDS (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWLTHTSR5 ======================================================= */ + #define R_MFWD_FWLTHTSR5_LTHDVS_Pos (0UL) /*!< LTHDVS (Bit 0) */ + #define R_MFWD_FWLTHTSR5_LTHDVS_Msk (0x7fUL) /*!< LTHDVS (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWLTHTSR5_LTHIPVS_Pos (16UL) /*!< LTHIPVS (Bit 16) */ + #define R_MFWD_FWLTHTSR5_LTHIPVS_Msk (0x70000UL) /*!< LTHIPVS (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWLTHTSR5_LTHIPUS_Pos (19UL) /*!< LTHIPUS (Bit 19) */ + #define R_MFWD_FWLTHTSR5_LTHIPUS_Msk (0x80000UL) /*!< LTHIPUS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTSR5_LTHEMES_Pos (20UL) /*!< LTHEMES (Bit 20) */ + #define R_MFWD_FWLTHTSR5_LTHEMES_Msk (0x100000UL) /*!< LTHEMES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTSR5_LTHCMES_Pos (21UL) /*!< LTHCMES (Bit 21) */ + #define R_MFWD_FWLTHTSR5_LTHCMES_Msk (0x200000UL) /*!< LTHCMES (Bitfield-Mask: 0x01) */ +/* ======================================================== FWLTHTR ======================================================== */ + #define R_MFWD_FWLTHTR_LTHAR_Pos (0UL) /*!< LTHAR (Bit 0) */ + #define R_MFWD_FWLTHTR_LTHAR_Msk (0x3ffUL) /*!< LTHAR (Bitfield-Mask: 0x3ff) */ +/* ======================================================= FWLTHTRR0 ======================================================= */ + #define R_MFWD_FWLTHTRR0_LTHREF_Pos (0UL) /*!< LTHREF (Bit 0) */ + #define R_MFWD_FWLTHTRR0_LTHREF_Msk (0x1UL) /*!< LTHREF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTRR0_LTHEVR_Pos (1UL) /*!< LTHEVR (Bit 1) */ + #define R_MFWD_FWLTHTRR0_LTHEVR_Msk (0x2UL) /*!< LTHEVR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTRR0_LTHTR_Pos (31UL) /*!< LTHTR (Bit 31) */ + #define R_MFWD_FWLTHTRR0_LTHTR_Msk (0x80000000UL) /*!< LTHTR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTRR1 ======================================================= */ + #define R_MFWD_FWLTHTRR1_LTHSRP0_Pos (0UL) /*!< LTHSRP0 (Bit 0) */ + #define R_MFWD_FWLTHTRR1_LTHSRP0_Msk (0x7UL) /*!< LTHSRP0 (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWLTHTRR1_LTHSLR_Pos (8UL) /*!< LTHSLR (Bit 8) */ + #define R_MFWD_FWLTHTRR1_LTHSLR_Msk (0x100UL) /*!< LTHSLR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTRR2 ======================================================= */ + #define R_MFWD_FWLTHTRR2_LTHSRP1_Pos (0UL) /*!< LTHSRP1 (Bit 0) */ + #define R_MFWD_FWLTHTRR2_LTHSRP1_Msk (0xffffffffUL) /*!< LTHSRP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTRR3 ======================================================= */ + #define R_MFWD_FWLTHTRR3_LTHSRP2_Pos (0UL) /*!< LTHSRP2 (Bit 0) */ + #define R_MFWD_FWLTHTRR3_LTHSRP2_Msk (0xffffffffUL) /*!< LTHSRP2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTRR4 ======================================================= */ + #define R_MFWD_FWLTHTRR4_LTHSRP3_Pos (0UL) /*!< LTHSRP3 (Bit 0) */ + #define R_MFWD_FWLTHTRR4_LTHSRP3_Msk (0xffffffffUL) /*!< LTHSRP3 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTRR5 ======================================================= */ + #define R_MFWD_FWLTHTRR5_LTHSRP4_Pos (0UL) /*!< LTHSRP4 (Bit 0) */ + #define R_MFWD_FWLTHTRR5_LTHSRP4_Msk (0xffffffffUL) /*!< LTHSRP4 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTRR6 ======================================================= */ + #define R_MFWD_FWLTHTRR6_LTHMSDUNR_Pos (16UL) /*!< LTHMSDUNR (Bit 16) */ + #define R_MFWD_FWLTHTRR6_LTHMSDUNR_Msk (0xf0000UL) /*!< LTHMSDUNR (Bitfield-Mask: 0x0f) */ + #define R_MFWD_FWLTHTRR6_LTHMSDUVR_Pos (31UL) /*!< LTHMSDUVR (Bit 31) */ + #define R_MFWD_FWLTHTRR6_LTHMSDUVR_Msk (0x80000000UL) /*!< LTHMSDUVR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTRR7 ======================================================= */ + #define R_MFWD_FWLTHTRR7_LTHFRERNR_Pos (0UL) /*!< LTHFRERNR (Bit 0) */ + #define R_MFWD_FWLTHTRR7_LTHFRERNR_Msk (0x3fUL) /*!< LTHFRERNR (Bitfield-Mask: 0x3f) */ + #define R_MFWD_FWLTHTRR7_LTHFRERVR_Pos (15UL) /*!< LTHFRERVR (Bit 15) */ + #define R_MFWD_FWLTHTRR7_LTHFRERVR_Msk (0x8000UL) /*!< LTHFRERVR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTRR7_LTHMTRNR_Pos (16UL) /*!< LTHMTRNR (Bit 16) */ + #define R_MFWD_FWLTHTRR7_LTHMTRNR_Msk (0x1f0000UL) /*!< LTHMTRNR (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWLTHTRR7_LTHMTRVR_Pos (31UL) /*!< LTHMTRVR (Bit 31) */ + #define R_MFWD_FWLTHTRR7_LTHMTRVR_Msk (0x80000000UL) /*!< LTHMTRVR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTRR8 ======================================================= */ + #define R_MFWD_FWLTHTRR8_LTHRNR_Pos (0UL) /*!< LTHRNR (Bit 0) */ + #define R_MFWD_FWLTHTRR8_LTHRNR_Msk (0xffUL) /*!< LTHRNR (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWLTHTRR8_LTHRVR_Pos (15UL) /*!< LTHRVR (Bit 15) */ + #define R_MFWD_FWLTHTRR8_LTHRVR_Msk (0x8000UL) /*!< LTHRVR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTRR8_LTHSLVR_Pos (16UL) /*!< LTHSLVR (Bit 16) */ + #define R_MFWD_FWLTHTRR8_LTHSLVR_Msk (0x7f0000UL) /*!< LTHSLVR (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWLTHTRR90 ======================================================= */ + #define R_MFWD_FWLTHTRR90_LTHCSDR_Pos (0UL) /*!< LTHCSDR (Bit 0) */ + #define R_MFWD_FWLTHTRR90_LTHCSDR_Msk (0x7fUL) /*!< LTHCSDR (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWLTHTRR10 ======================================================= */ + #define R_MFWD_FWLTHTRR10_LTHDVR_Pos (0UL) /*!< LTHDVR (Bit 0) */ + #define R_MFWD_FWLTHTRR10_LTHDVR_Msk (0x7fUL) /*!< LTHDVR (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWLTHTRR10_LTHIPVR_Pos (16UL) /*!< LTHIPVR (Bit 16) */ + #define R_MFWD_FWLTHTRR10_LTHIPVR_Msk (0x70000UL) /*!< LTHIPVR (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWLTHTRR10_LTHIPUR_Pos (19UL) /*!< LTHIPUR (Bit 19) */ + #define R_MFWD_FWLTHTRR10_LTHIPUR_Msk (0x80000UL) /*!< LTHIPUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTRR10_LTHEMER_Pos (20UL) /*!< LTHEMER (Bit 20) */ + #define R_MFWD_FWLTHTRR10_LTHEMER_Msk (0x100000UL) /*!< LTHEMER (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTRR10_LTHCMER_Pos (21UL) /*!< LTHCMER (Bit 21) */ + #define R_MFWD_FWLTHTRR10_LTHCMER_Msk (0x200000UL) /*!< LTHCMER (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACHEC ======================================================== */ + #define R_MFWD_FWMACHEC_MACHMC_Pos (0UL) /*!< MACHMC (Bit 0) */ + #define R_MFWD_FWMACHEC_MACHMC_Msk (0x7ffUL) /*!< MACHMC (Bitfield-Mask: 0x7ff) */ + #define R_MFWD_FWMACHEC_MACHMUE_Pos (16UL) /*!< MACHMUE (Bit 16) */ + #define R_MFWD_FWMACHEC_MACHMUE_Msk (0xfff0000UL) /*!< MACHMUE (Bitfield-Mask: 0xfff) */ +/* ======================================================== FWMACHC ======================================================== */ + #define R_MFWD_FWMACHC_MACHE_Pos (0UL) /*!< MACHE (Bit 0) */ + #define R_MFWD_FWMACHC_MACHE_Msk (0x7ffUL) /*!< MACHE (Bitfield-Mask: 0x7ff) */ +/* ======================================================= FWMACTL0 ======================================================== */ + #define R_MFWD_FWMACTL0_MACSLL_Pos (8UL) /*!< MACSLL (Bit 8) */ + #define R_MFWD_FWMACTL0_MACSLL_Msk (0x100UL) /*!< MACSLL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTL0_MACDEL_Pos (9UL) /*!< MACDEL (Bit 9) */ + #define R_MFWD_FWMACTL0_MACDEL_Msk (0x200UL) /*!< MACDEL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTL0_MACHLDL_Pos (10UL) /*!< MACHLDL (Bit 10) */ + #define R_MFWD_FWMACTL0_MACHLDL_Msk (0x400UL) /*!< MACHLDL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTL0_MACED_Pos (16UL) /*!< MACED (Bit 16) */ + #define R_MFWD_FWMACTL0_MACED_Msk (0x10000UL) /*!< MACED (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACTL1 ======================================================== */ + #define R_MFWD_FWMACTL1_MACMALP0_Pos (0UL) /*!< MACMALP0 (Bit 0) */ + #define R_MFWD_FWMACTL1_MACMALP0_Msk (0xffffUL) /*!< MACMALP0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWMACTL2 ======================================================== */ + #define R_MFWD_FWMACTL2_MACMALP1_Pos (0UL) /*!< MACMALP1 (Bit 0) */ + #define R_MFWD_FWMACTL2_MACMALP1_Msk (0xffffffffUL) /*!< MACMALP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWMACTL3 ======================================================== */ + #define R_MFWD_FWMACTL3_MACSSLVL_Pos (0UL) /*!< MACSSLVL (Bit 0) */ + #define R_MFWD_FWMACTL3_MACSSLVL_Msk (0x7fUL) /*!< MACSSLVL (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWMACTL3_MACDSLVL_Pos (16UL) /*!< MACDSLVL (Bit 16) */ + #define R_MFWD_FWMACTL3_MACDSLVL_Msk (0x7f0000UL) /*!< MACDSLVL (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWMACTL40 ======================================================= */ + #define R_MFWD_FWMACTL40_MACCSDL_Pos (0UL) /*!< MACCSDL (Bit 0) */ + #define R_MFWD_FWMACTL40_MACCSDL_Msk (0x7fUL) /*!< MACCSDL (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWMACTL5 ======================================================== */ + #define R_MFWD_FWMACTL5_MACDVL_Pos (0UL) /*!< MACDVL (Bit 0) */ + #define R_MFWD_FWMACTL5_MACDVL_Msk (0x7fUL) /*!< MACDVL (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWMACTL5_MACIPVL_Pos (16UL) /*!< MACIPVL (Bit 16) */ + #define R_MFWD_FWMACTL5_MACIPVL_Msk (0x70000UL) /*!< MACIPVL (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWMACTL5_MACIPUL_Pos (19UL) /*!< MACIPUL (Bit 19) */ + #define R_MFWD_FWMACTL5_MACIPUL_Msk (0x80000UL) /*!< MACIPUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTL5_MACEMEL_Pos (20UL) /*!< MACEMEL (Bit 20) */ + #define R_MFWD_FWMACTL5_MACEMEL_Msk (0x100000UL) /*!< MACEMEL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTL5_MACCMEL_Pos (21UL) /*!< MACCMEL (Bit 21) */ + #define R_MFWD_FWMACTL5_MACCMEL_Msk (0x200000UL) /*!< MACCMEL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACTLR ======================================================== */ + #define R_MFWD_FWMACTLR_MACLF_Pos (0UL) /*!< MACLF (Bit 0) */ + #define R_MFWD_FWMACTLR_MACLF_Msk (0x1UL) /*!< MACLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTLR_MACLSF_Pos (1UL) /*!< MACLSF (Bit 1) */ + #define R_MFWD_FWMACTLR_MACLSF_Msk (0x2UL) /*!< MACLSF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTLR_MACLEF_Pos (2UL) /*!< MACLEF (Bit 2) */ + #define R_MFWD_FWMACTLR_MACLEF_Msk (0x4UL) /*!< MACLEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTLR_MACLO_Pos (3UL) /*!< MACLO (Bit 3) */ + #define R_MFWD_FWMACTLR_MACLO_Msk (0x8UL) /*!< MACLO (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTLR_MACLCN_Pos (16UL) /*!< MACLCN (Bit 16) */ + #define R_MFWD_FWMACTLR_MACLCN_Msk (0x3ff0000UL) /*!< MACLCN (Bitfield-Mask: 0x3ff) */ + #define R_MFWD_FWMACTLR_MACTL_Pos (31UL) /*!< MACTL (Bit 31) */ + #define R_MFWD_FWMACTLR_MACTL_Msk (0x80000000UL) /*!< MACTL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACTIM ======================================================== */ + #define R_MFWD_FWMACTIM_MACTIOG_Pos (0UL) /*!< MACTIOG (Bit 0) */ + #define R_MFWD_FWMACTIM_MACTIOG_Msk (0x1UL) /*!< MACTIOG (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTIM_MACTR_Pos (1UL) /*!< MACTR (Bit 1) */ + #define R_MFWD_FWMACTIM_MACTR_Msk (0x2UL) /*!< MACTR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACTEM ======================================================== */ + #define R_MFWD_FWMACTEM_MACTEN_Pos (0UL) /*!< MACTEN (Bit 0) */ + #define R_MFWD_FWMACTEM_MACTEN_Msk (0x7ffUL) /*!< MACTEN (Bitfield-Mask: 0x7ff) */ + #define R_MFWD_FWMACTEM_MACTUEN_Pos (16UL) /*!< MACTUEN (Bit 16) */ + #define R_MFWD_FWMACTEM_MACTUEN_Msk (0x7ff0000UL) /*!< MACTUEN (Bitfield-Mask: 0x7ff) */ +/* ======================================================= FWMACTS0 ======================================================== */ + #define R_MFWD_FWMACTS0_MACMASP0_Pos (0UL) /*!< MACMASP0 (Bit 0) */ + #define R_MFWD_FWMACTS0_MACMASP0_Msk (0xffffUL) /*!< MACMASP0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWMACTS1 ======================================================== */ + #define R_MFWD_FWMACTS1_MACMASP1_Pos (0UL) /*!< MACMASP1 (Bit 0) */ + #define R_MFWD_FWMACTS1_MACMASP1_Msk (0xffffffffUL) /*!< MACMASP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWMACTSR0 ======================================================= */ + #define R_MFWD_FWMACTSR0_MACSEF_Pos (0UL) /*!< MACSEF (Bit 0) */ + #define R_MFWD_FWMACTSR0_MACSEF_Msk (0x1UL) /*!< MACSEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTSR0_MACSNF_Pos (1UL) /*!< MACSNF (Bit 1) */ + #define R_MFWD_FWMACTSR0_MACSNF_Msk (0x2UL) /*!< MACSNF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTSR0_MACSLS_Pos (8UL) /*!< MACSLS (Bit 8) */ + #define R_MFWD_FWMACTSR0_MACSLS_Msk (0x100UL) /*!< MACSLS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTSR0_MACDES_Pos (9UL) /*!< MACDES (Bit 9) */ + #define R_MFWD_FWMACTSR0_MACDES_Msk (0x200UL) /*!< MACDES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTSR0_MACHLDS_Pos (10UL) /*!< MACHLDS (Bit 10) */ + #define R_MFWD_FWMACTSR0_MACHLDS_Msk (0x400UL) /*!< MACHLDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTSR0_MACSCN_Pos (16UL) /*!< MACSCN (Bit 16) */ + #define R_MFWD_FWMACTSR0_MACSCN_Msk (0x3ff0000UL) /*!< MACSCN (Bitfield-Mask: 0x3ff) */ + #define R_MFWD_FWMACTSR0_MACTS_Pos (31UL) /*!< MACTS (Bit 31) */ + #define R_MFWD_FWMACTSR0_MACTS_Msk (0x80000000UL) /*!< MACTS (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACTSR1 ======================================================= */ + #define R_MFWD_FWMACTSR1_MACSSLVS_Pos (0UL) /*!< MACSSLVS (Bit 0) */ + #define R_MFWD_FWMACTSR1_MACSSLVS_Msk (0x7fUL) /*!< MACSSLVS (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWMACTSR1_MACDSLVS_Pos (16UL) /*!< MACDSLVS (Bit 16) */ + #define R_MFWD_FWMACTSR1_MACDSLVS_Msk (0x7f0000UL) /*!< MACDSLVS (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWMACTSR20 ======================================================= */ + #define R_MFWD_FWMACTSR20_MACCSDS_Pos (0UL) /*!< MACCSDS (Bit 0) */ + #define R_MFWD_FWMACTSR20_MACCSDS_Msk (0x7fUL) /*!< MACCSDS (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWMACTSR3 ======================================================= */ + #define R_MFWD_FWMACTSR3_MACDVS_Pos (0UL) /*!< MACDVS (Bit 0) */ + #define R_MFWD_FWMACTSR3_MACDVS_Msk (0x7fUL) /*!< MACDVS (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWMACTSR3_MACIPVS_Pos (16UL) /*!< MACIPVS (Bit 16) */ + #define R_MFWD_FWMACTSR3_MACIPVS_Msk (0x70000UL) /*!< MACIPVS (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWMACTSR3_MACIPUS_Pos (19UL) /*!< MACIPUS (Bit 19) */ + #define R_MFWD_FWMACTSR3_MACIPUS_Msk (0x80000UL) /*!< MACIPUS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTSR3_MACEMES_Pos (20UL) /*!< MACEMES (Bit 20) */ + #define R_MFWD_FWMACTSR3_MACEMES_Msk (0x100000UL) /*!< MACEMES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTSR3_MACCMES_Pos (21UL) /*!< MACCMES (Bit 21) */ + #define R_MFWD_FWMACTSR3_MACCMES_Msk (0x200000UL) /*!< MACCMES (Bitfield-Mask: 0x01) */ +/* ======================================================== FWMACTR ======================================================== */ + #define R_MFWD_FWMACTR_MACAR_Pos (0UL) /*!< MACAR (Bit 0) */ + #define R_MFWD_FWMACTR_MACAR_Msk (0x3ffUL) /*!< MACAR (Bitfield-Mask: 0x3ff) */ +/* ======================================================= FWMACTRR0 ======================================================= */ + #define R_MFWD_FWMACTRR0_MACEVR_Pos (0UL) /*!< MACEVR (Bit 0) */ + #define R_MFWD_FWMACTRR0_MACEVR_Msk (0x1UL) /*!< MACEVR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTRR0_MACREF_Pos (1UL) /*!< MACREF (Bit 1) */ + #define R_MFWD_FWMACTRR0_MACREF_Msk (0x2UL) /*!< MACREF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTRR0_MACTR_Pos (31UL) /*!< MACTR (Bit 31) */ + #define R_MFWD_FWMACTRR0_MACTR_Msk (0x80000000UL) /*!< MACTR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACTRR1 ======================================================= */ + #define R_MFWD_FWMACTRR1_MACSLR_Pos (8UL) /*!< MACSLR (Bit 8) */ + #define R_MFWD_FWMACTRR1_MACSLR_Msk (0x100UL) /*!< MACSLR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTRR1_MACDER_Pos (9UL) /*!< MACDER (Bit 9) */ + #define R_MFWD_FWMACTRR1_MACDER_Msk (0x200UL) /*!< MACDER (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTRR1_MACHLDR_Pos (10UL) /*!< MACHLDR (Bit 10) */ + #define R_MFWD_FWMACTRR1_MACHLDR_Msk (0x400UL) /*!< MACHLDR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTRR1_MACABR_Pos (11UL) /*!< MACABR (Bit 11) */ + #define R_MFWD_FWMACTRR1_MACABR_Msk (0x800UL) /*!< MACABR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACTRR2 ======================================================= */ + #define R_MFWD_FWMACTRR2_MACMARP0_Pos (0UL) /*!< MACMARP0 (Bit 0) */ + #define R_MFWD_FWMACTRR2_MACMARP0_Msk (0xffffUL) /*!< MACMARP0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWMACTRR3 ======================================================= */ + #define R_MFWD_FWMACTRR3_MACMARP1_Pos (0UL) /*!< MACMARP1 (Bit 0) */ + #define R_MFWD_FWMACTRR3_MACMARP1_Msk (0xffffffffUL) /*!< MACMARP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWMACTRR4 ======================================================= */ + #define R_MFWD_FWMACTRR4_MACSSLVR_Pos (0UL) /*!< MACSSLVR (Bit 0) */ + #define R_MFWD_FWMACTRR4_MACSSLVR_Msk (0x7fUL) /*!< MACSSLVR (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWMACTRR4_MACDSLVR_Pos (16UL) /*!< MACDSLVR (Bit 16) */ + #define R_MFWD_FWMACTRR4_MACDSLVR_Msk (0x7f0000UL) /*!< MACDSLVR (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWMACTRR50 ======================================================= */ + #define R_MFWD_FWMACTRR50_MACCSDR_Pos (0UL) /*!< MACCSDR (Bit 0) */ + #define R_MFWD_FWMACTRR50_MACCSDR_Msk (0x7fUL) /*!< MACCSDR (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWMACTRR6 ======================================================= */ + #define R_MFWD_FWMACTRR6_MACDVR_Pos (0UL) /*!< MACDVR (Bit 0) */ + #define R_MFWD_FWMACTRR6_MACDVR_Msk (0x7fUL) /*!< MACDVR (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWMACTRR6_MACIPVR_Pos (16UL) /*!< MACIPVR (Bit 16) */ + #define R_MFWD_FWMACTRR6_MACIPVR_Msk (0x70000UL) /*!< MACIPVR (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWMACTRR6_MACIPUR_Pos (19UL) /*!< MACIPUR (Bit 19) */ + #define R_MFWD_FWMACTRR6_MACIPUR_Msk (0x80000UL) /*!< MACIPUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTRR6_MACEMER_Pos (20UL) /*!< MACEMER (Bit 20) */ + #define R_MFWD_FWMACTRR6_MACEMER_Msk (0x100000UL) /*!< MACEMER (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTRR6_MACCMER_Pos (21UL) /*!< MACCMER (Bit 21) */ + #define R_MFWD_FWMACTRR6_MACCMER_Msk (0x200000UL) /*!< MACCMER (Bitfield-Mask: 0x01) */ +/* ====================================================== FWMACAGUSPC ====================================================== */ + #define R_MFWD_FWMACAGUSPC_MACAGUSP_Pos (0UL) /*!< MACAGUSP (Bit 0) */ + #define R_MFWD_FWMACAGUSPC_MACAGUSP_Msk (0x3ffUL) /*!< MACAGUSP (Bitfield-Mask: 0x3ff) */ +/* ======================================================= FWMACAGC ======================================================== */ + #define R_MFWD_FWMACAGC_MACAGT_Pos (0UL) /*!< MACAGT (Bit 0) */ + #define R_MFWD_FWMACAGC_MACAGT_Msk (0xffffUL) /*!< MACAGT (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWMACAGC_MACAGE_Pos (16UL) /*!< MACAGE (Bit 16) */ + #define R_MFWD_FWMACAGC_MACAGE_Msk (0x10000UL) /*!< MACAGE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACAGC_MACAGSL_Pos (17UL) /*!< MACAGSL (Bit 17) */ + #define R_MFWD_FWMACAGC_MACAGSL_Msk (0x20000UL) /*!< MACAGSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACAGC_MACAGPM_Pos (18UL) /*!< MACAGPM (Bit 18) */ + #define R_MFWD_FWMACAGC_MACAGPM_Msk (0x40000UL) /*!< MACAGPM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACAGC_MACDES_Pos (24UL) /*!< MACDES (Bit 24) */ + #define R_MFWD_FWMACAGC_MACDES_Msk (0x1000000UL) /*!< MACDES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACAGC_MACAGOG_Pos (28UL) /*!< MACAGOG (Bit 28) */ + #define R_MFWD_FWMACAGC_MACAGOG_Msk (0x10000000UL) /*!< MACAGOG (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACAGC_MACDESOG_Pos (29UL) /*!< MACDESOG (Bit 29) */ + #define R_MFWD_FWMACAGC_MACDESOG_Msk (0x20000000UL) /*!< MACDESOG (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACAGM0 ======================================================= */ + #define R_MFWD_FWMACAGM0_AGMACAP0_Pos (0UL) /*!< AGMACAP0 (Bit 0) */ + #define R_MFWD_FWMACAGM0_AGMACAP0_Msk (0xffffUL) /*!< AGMACAP0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWMACAGM1 ======================================================= */ + #define R_MFWD_FWMACAGM1_AGMACAP1_Pos (0UL) /*!< AGMACAP1 (Bit 0) */ + #define R_MFWD_FWMACAGM1_AGMACAP1_Msk (0xffffffffUL) /*!< AGMACAP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWVLANTEC ======================================================= */ + #define R_MFWD_FWVLANTEC_VLANTMUE_Pos (16UL) /*!< VLANTMUE (Bit 16) */ + #define R_MFWD_FWVLANTEC_VLANTMUE_Msk (0x1fff0000UL) /*!< VLANTMUE (Bitfield-Mask: 0x1fff) */ +/* ======================================================= FWVLANTL0 ======================================================= */ + #define R_MFWD_FWVLANTL0_VLANSLL_Pos (8UL) /*!< VLANSLL (Bit 8) */ + #define R_MFWD_FWVLANTL0_VLANSLL_Msk (0x100UL) /*!< VLANSLL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTL0_VLANHLDL_Pos (10UL) /*!< VLANHLDL (Bit 10) */ + #define R_MFWD_FWVLANTL0_VLANHLDL_Msk (0x400UL) /*!< VLANHLDL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTL0_VLANED_Pos (16UL) /*!< VLANED (Bit 16) */ + #define R_MFWD_FWVLANTL0_VLANED_Msk (0x10000UL) /*!< VLANED (Bitfield-Mask: 0x01) */ +/* ======================================================= FWVLANTL1 ======================================================= */ + #define R_MFWD_FWVLANTL1_VLANVIDL_Pos (0UL) /*!< VLANVIDL (Bit 0) */ + #define R_MFWD_FWVLANTL1_VLANVIDL_Msk (0xfffUL) /*!< VLANVIDL (Bitfield-Mask: 0xfff) */ +/* ======================================================= FWVLANTL2 ======================================================= */ + #define R_MFWD_FWVLANTL2_VLANSLVL_Pos (0UL) /*!< VLANSLVL (Bit 0) */ + #define R_MFWD_FWVLANTL2_VLANSLVL_Msk (0x7fUL) /*!< VLANSLVL (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWVLANTL30 ======================================================= */ + #define R_MFWD_FWVLANTL30_VLANCSDL_Pos (0UL) /*!< VLANCSDL (Bit 0) */ + #define R_MFWD_FWVLANTL30_VLANCSDL_Msk (0x7fUL) /*!< VLANCSDL (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWVLANTL4 ======================================================= */ + #define R_MFWD_FWVLANTL4_VLANDVL_Pos (0UL) /*!< VLANDVL (Bit 0) */ + #define R_MFWD_FWVLANTL4_VLANDVL_Msk (0x7fUL) /*!< VLANDVL (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWVLANTL4_VLANIPVL_Pos (16UL) /*!< VLANIPVL (Bit 16) */ + #define R_MFWD_FWVLANTL4_VLANIPVL_Msk (0x70000UL) /*!< VLANIPVL (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWVLANTL4_VLANIPUL_Pos (19UL) /*!< VLANIPUL (Bit 19) */ + #define R_MFWD_FWVLANTL4_VLANIPUL_Msk (0x80000UL) /*!< VLANIPUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTL4_VLANEMEL_Pos (20UL) /*!< VLANEMEL (Bit 20) */ + #define R_MFWD_FWVLANTL4_VLANEMEL_Msk (0x100000UL) /*!< VLANEMEL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTL4_VLANCMEL_Pos (21UL) /*!< VLANCMEL (Bit 21) */ + #define R_MFWD_FWVLANTL4_VLANCMEL_Msk (0x200000UL) /*!< VLANCMEL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWVLANTLR ======================================================= */ + #define R_MFWD_FWVLANTLR_VLANLF_Pos (0UL) /*!< VLANLF (Bit 0) */ + #define R_MFWD_FWVLANTLR_VLANLF_Msk (0x1UL) /*!< VLANLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTLR_VLANLSF_Pos (1UL) /*!< VLANLSF (Bit 1) */ + #define R_MFWD_FWVLANTLR_VLANLSF_Msk (0x2UL) /*!< VLANLSF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTLR_VLANLEF_Pos (2UL) /*!< VLANLEF (Bit 2) */ + #define R_MFWD_FWVLANTLR_VLANLEF_Msk (0x4UL) /*!< VLANLEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTLR_VLANLO_Pos (3UL) /*!< VLANLO (Bit 3) */ + #define R_MFWD_FWVLANTLR_VLANLO_Msk (0x8UL) /*!< VLANLO (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTLR_VLANTL_Pos (31UL) /*!< VLANTL (Bit 31) */ + #define R_MFWD_FWVLANTLR_VLANTL_Msk (0x80000000UL) /*!< VLANTL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWVLANTIM ======================================================= */ + #define R_MFWD_FWVLANTIM_VLANTIOG_Pos (0UL) /*!< VLANTIOG (Bit 0) */ + #define R_MFWD_FWVLANTIM_VLANTIOG_Msk (0x1UL) /*!< VLANTIOG (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTIM_VLANTR_Pos (1UL) /*!< VLANTR (Bit 1) */ + #define R_MFWD_FWVLANTIM_VLANTR_Msk (0x2UL) /*!< VLANTR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWVLANTEM ======================================================= */ + #define R_MFWD_FWVLANTEM_VLANTEN_Pos (0UL) /*!< VLANTEN (Bit 0) */ + #define R_MFWD_FWVLANTEM_VLANTEN_Msk (0x1fffUL) /*!< VLANTEN (Bitfield-Mask: 0x1fff) */ + #define R_MFWD_FWVLANTEM_VLANTUEN_Pos (16UL) /*!< VLANTUEN (Bit 16) */ + #define R_MFWD_FWVLANTEM_VLANTUEN_Msk (0x1fff0000UL) /*!< VLANTUEN (Bitfield-Mask: 0x1fff) */ +/* ======================================================= FWVLANTS ======================================================== */ + #define R_MFWD_FWVLANTS_VLANVIDS_Pos (0UL) /*!< VLANVIDS (Bit 0) */ + #define R_MFWD_FWVLANTS_VLANVIDS_Msk (0xfffUL) /*!< VLANVIDS (Bitfield-Mask: 0xfff) */ +/* ====================================================== FWVLANTSR0 ======================================================= */ + #define R_MFWD_FWVLANTSR0_VLANSEF_Pos (0UL) /*!< VLANSEF (Bit 0) */ + #define R_MFWD_FWVLANTSR0_VLANSEF_Msk (0x1UL) /*!< VLANSEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTSR0_VLANSNF_Pos (1UL) /*!< VLANSNF (Bit 1) */ + #define R_MFWD_FWVLANTSR0_VLANSNF_Msk (0x2UL) /*!< VLANSNF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTSR0_VLANSLS_Pos (8UL) /*!< VLANSLS (Bit 8) */ + #define R_MFWD_FWVLANTSR0_VLANSLS_Msk (0x100UL) /*!< VLANSLS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTSR0_VLANHLDS_Pos (10UL) /*!< VLANHLDS (Bit 10) */ + #define R_MFWD_FWVLANTSR0_VLANHLDS_Msk (0x400UL) /*!< VLANHLDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTSR0_VLANTS_Pos (31UL) /*!< VLANTS (Bit 31) */ + #define R_MFWD_FWVLANTSR0_VLANTS_Msk (0x80000000UL) /*!< VLANTS (Bitfield-Mask: 0x01) */ +/* ====================================================== FWVLANTSR1 ======================================================= */ + #define R_MFWD_FWVLANTSR1_VLANSLVS_Pos (0UL) /*!< VLANSLVS (Bit 0) */ + #define R_MFWD_FWVLANTSR1_VLANSLVS_Msk (0x7fUL) /*!< VLANSLVS (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWVLANTSR20 ====================================================== */ + #define R_MFWD_FWVLANTSR20_VLANCSDS_Pos (0UL) /*!< VLANCSDS (Bit 0) */ + #define R_MFWD_FWVLANTSR20_VLANCSDS_Msk (0x7fUL) /*!< VLANCSDS (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWVLANTSR3 ======================================================= */ + #define R_MFWD_FWVLANTSR3_VLANDVS_Pos (0UL) /*!< VLANDVS (Bit 0) */ + #define R_MFWD_FWVLANTSR3_VLANDVS_Msk (0x7fUL) /*!< VLANDVS (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWVLANTSR3_VLANIPVS_Pos (16UL) /*!< VLANIPVS (Bit 16) */ + #define R_MFWD_FWVLANTSR3_VLANIPVS_Msk (0x70000UL) /*!< VLANIPVS (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWVLANTSR3_VLANIPUS_Pos (19UL) /*!< VLANIPUS (Bit 19) */ + #define R_MFWD_FWVLANTSR3_VLANIPUS_Msk (0x80000UL) /*!< VLANIPUS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTSR3_VLANEMES_Pos (20UL) /*!< VLANEMES (Bit 20) */ + #define R_MFWD_FWVLANTSR3_VLANEMES_Msk (0x100000UL) /*!< VLANEMES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTSR3_VLANCMES_Pos (21UL) /*!< VLANCMES (Bit 21) */ + #define R_MFWD_FWVLANTSR3_VLANCMES_Msk (0x200000UL) /*!< VLANCMES (Bitfield-Mask: 0x01) */ +/* ======================================================== FWPBFC0 ======================================================== */ + #define R_MFWD_FWPBFC0_PBDV_Pos (0UL) /*!< PBDV (Bit 0) */ + #define R_MFWD_FWPBFC0_PBDV_Msk (0x7fUL) /*!< PBDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWPBFC0_PBIPV_Pos (16UL) /*!< PBIPV (Bit 16) */ + #define R_MFWD_FWPBFC0_PBIPV_Msk (0x70000UL) /*!< PBIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWPBFC0_PBIPU_Pos (19UL) /*!< PBIPU (Bit 19) */ + #define R_MFWD_FWPBFC0_PBIPU_Msk (0x80000UL) /*!< PBIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC0_PBEME_Pos (20UL) /*!< PBEME (Bit 20) */ + #define R_MFWD_FWPBFC0_PBEME_Msk (0x100000UL) /*!< PBEME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC0_PBCME_Pos (21UL) /*!< PBCME (Bit 21) */ + #define R_MFWD_FWPBFC0_PBCME_Msk (0x200000UL) /*!< PBCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC0_PBSL_Pos (22UL) /*!< PBSL (Bit 22) */ + #define R_MFWD_FWPBFC0_PBSL_Msk (0x400000UL) /*!< PBSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC0_IP4PDE_Pos (23UL) /*!< IP4PDE (Bit 23) */ + #define R_MFWD_FWPBFC0_IP4PDE_Msk (0x800000UL) /*!< IP4PDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC0_IP4PDM_Pos (24UL) /*!< IP4PDM (Bit 24) */ + #define R_MFWD_FWPBFC0_IP4PDM_Msk (0x1000000UL) /*!< IP4PDM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC0_IP6PDE_Pos (25UL) /*!< IP6PDE (Bit 25) */ + #define R_MFWD_FWPBFC0_IP6PDE_Msk (0x2000000UL) /*!< IP6PDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC0_FAIFP_Pos (26UL) /*!< FAIFP (Bit 26) */ + #define R_MFWD_FWPBFC0_FAIFP_Msk (0x4000000UL) /*!< FAIFP (Bitfield-Mask: 0x01) */ +/* ======================================================== FWPBFC1 ======================================================== */ + #define R_MFWD_FWPBFC1_PBDV_Pos (0UL) /*!< PBDV (Bit 0) */ + #define R_MFWD_FWPBFC1_PBDV_Msk (0x7fUL) /*!< PBDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWPBFC1_PBIPV_Pos (16UL) /*!< PBIPV (Bit 16) */ + #define R_MFWD_FWPBFC1_PBIPV_Msk (0x70000UL) /*!< PBIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWPBFC1_PBIPU_Pos (19UL) /*!< PBIPU (Bit 19) */ + #define R_MFWD_FWPBFC1_PBIPU_Msk (0x80000UL) /*!< PBIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC1_PBEME_Pos (20UL) /*!< PBEME (Bit 20) */ + #define R_MFWD_FWPBFC1_PBEME_Msk (0x100000UL) /*!< PBEME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC1_PBCME_Pos (21UL) /*!< PBCME (Bit 21) */ + #define R_MFWD_FWPBFC1_PBCME_Msk (0x200000UL) /*!< PBCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC1_PBSL_Pos (22UL) /*!< PBSL (Bit 22) */ + #define R_MFWD_FWPBFC1_PBSL_Msk (0x400000UL) /*!< PBSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC1_IP4PDE_Pos (23UL) /*!< IP4PDE (Bit 23) */ + #define R_MFWD_FWPBFC1_IP4PDE_Msk (0x800000UL) /*!< IP4PDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC1_IP4PDM_Pos (24UL) /*!< IP4PDM (Bit 24) */ + #define R_MFWD_FWPBFC1_IP4PDM_Msk (0x1000000UL) /*!< IP4PDM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC1_IP6PDE_Pos (25UL) /*!< IP6PDE (Bit 25) */ + #define R_MFWD_FWPBFC1_IP6PDE_Msk (0x2000000UL) /*!< IP6PDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC1_FAIFP_Pos (26UL) /*!< FAIFP (Bit 26) */ + #define R_MFWD_FWPBFC1_FAIFP_Msk (0x4000000UL) /*!< FAIFP (Bitfield-Mask: 0x01) */ +/* ======================================================== FWPBFC2 ======================================================== */ + #define R_MFWD_FWPBFC2_PBDV_Pos (0UL) /*!< PBDV (Bit 0) */ + #define R_MFWD_FWPBFC2_PBDV_Msk (0x7fUL) /*!< PBDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWPBFC2_PBIPV_Pos (16UL) /*!< PBIPV (Bit 16) */ + #define R_MFWD_FWPBFC2_PBIPV_Msk (0x70000UL) /*!< PBIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWPBFC2_PBIPU_Pos (19UL) /*!< PBIPU (Bit 19) */ + #define R_MFWD_FWPBFC2_PBIPU_Msk (0x80000UL) /*!< PBIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC2_PBEME_Pos (20UL) /*!< PBEME (Bit 20) */ + #define R_MFWD_FWPBFC2_PBEME_Msk (0x100000UL) /*!< PBEME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC2_PBCME_Pos (21UL) /*!< PBCME (Bit 21) */ + #define R_MFWD_FWPBFC2_PBCME_Msk (0x200000UL) /*!< PBCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC2_PBSL_Pos (22UL) /*!< PBSL (Bit 22) */ + #define R_MFWD_FWPBFC2_PBSL_Msk (0x400000UL) /*!< PBSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC2_IP4PDE_Pos (23UL) /*!< IP4PDE (Bit 23) */ + #define R_MFWD_FWPBFC2_IP4PDE_Msk (0x800000UL) /*!< IP4PDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC2_IP4PDM_Pos (24UL) /*!< IP4PDM (Bit 24) */ + #define R_MFWD_FWPBFC2_IP4PDM_Msk (0x1000000UL) /*!< IP4PDM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC2_IP6PDE_Pos (25UL) /*!< IP6PDE (Bit 25) */ + #define R_MFWD_FWPBFC2_IP6PDE_Msk (0x2000000UL) /*!< IP6PDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC2_FAIFP_Pos (26UL) /*!< FAIFP (Bit 26) */ + #define R_MFWD_FWPBFC2_FAIFP_Msk (0x4000000UL) /*!< FAIFP (Bitfield-Mask: 0x01) */ +/* ====================================================== FWPBFCSDC00 ====================================================== */ + #define R_MFWD_FWPBFCSDC00_PBCSD_Pos (0UL) /*!< PBCSD (Bit 0) */ + #define R_MFWD_FWPBFCSDC00_PBCSD_Msk (0x7fUL) /*!< PBCSD (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWPBFCSDC01 ====================================================== */ + #define R_MFWD_FWPBFCSDC01_PBCSD_Pos (0UL) /*!< PBCSD (Bit 0) */ + #define R_MFWD_FWPBFCSDC01_PBCSD_Msk (0x7fUL) /*!< PBCSD (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWPBFCSDC02 ====================================================== */ + #define R_MFWD_FWPBFCSDC02_PBCSD_Pos (0UL) /*!< PBCSD (Bit 0) */ + #define R_MFWD_FWPBFCSDC02_PBCSD_Msk (0x7fUL) /*!< PBCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWL23URL0 ======================================================= */ + #define R_MFWD_FWL23URL0_L23URNL_Pos (0UL) /*!< L23URNL (Bit 0) */ + #define R_MFWD_FWL23URL0_L23URNL_Msk (0xffUL) /*!< L23URNL (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URL0_L23URPVL_Pos (16UL) /*!< L23URPVL (Bit 16) */ + #define R_MFWD_FWL23URL0_L23URPVL_Msk (0x7f0000UL) /*!< L23URPVL (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWL23URL1 ======================================================= */ + #define R_MFWD_FWL23URL1_L23UMDALP0_Pos (0UL) /*!< L23UMDALP0 (Bit 0) */ + #define R_MFWD_FWL23URL1_L23UMDALP0_Msk (0xffffUL) /*!< L23UMDALP0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWL23URL1_L23UTTLUL_Pos (16UL) /*!< L23UTTLUL (Bit 16) */ + #define R_MFWD_FWL23URL1_L23UTTLUL_Msk (0x10000UL) /*!< L23UTTLUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23UMDAUL_Pos (17UL) /*!< L23UMDAUL (Bit 17) */ + #define R_MFWD_FWL23URL1_L23UMDAUL_Msk (0x20000UL) /*!< L23UMDAUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23UMSAUL_Pos (18UL) /*!< L23UMSAUL (Bit 18) */ + #define R_MFWD_FWL23URL1_L23UMSAUL_Msk (0x40000UL) /*!< L23UMSAUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23UCVIDUL_Pos (19UL) /*!< L23UCVIDUL (Bit 19) */ + #define R_MFWD_FWL23URL1_L23UCVIDUL_Msk (0x80000UL) /*!< L23UCVIDUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23UCPCPUL_Pos (20UL) /*!< L23UCPCPUL (Bit 20) */ + #define R_MFWD_FWL23URL1_L23UCPCPUL_Msk (0x100000UL) /*!< L23UCPCPUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23UCDEIUL_Pos (21UL) /*!< L23UCDEIUL (Bit 21) */ + #define R_MFWD_FWL23URL1_L23UCDEIUL_Msk (0x200000UL) /*!< L23UCDEIUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23USVIDUL_Pos (22UL) /*!< L23USVIDUL (Bit 22) */ + #define R_MFWD_FWL23URL1_L23USVIDUL_Msk (0x400000UL) /*!< L23USVIDUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23USPCPUL_Pos (23UL) /*!< L23USPCPUL (Bit 23) */ + #define R_MFWD_FWL23URL1_L23USPCPUL_Msk (0x800000UL) /*!< L23USPCPUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23USDEIUL_Pos (24UL) /*!< L23USDEIUL (Bit 24) */ + #define R_MFWD_FWL23URL1_L23USDEIUL_Msk (0x1000000UL) /*!< L23USDEIUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23URTUL_Pos (25UL) /*!< L23URTUL (Bit 25) */ + #define R_MFWD_FWL23URL1_L23URTUL_Msk (0x6000000UL) /*!< L23URTUL (Bitfield-Mask: 0x03) */ +/* ======================================================= FWL23URL2 ======================================================= */ + #define R_MFWD_FWL23URL2_L23UMDALP1_Pos (0UL) /*!< L23UMDALP1 (Bit 0) */ + #define R_MFWD_FWL23URL2_L23UMDALP1_Msk (0xffffffffUL) /*!< L23UMDALP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWL23URL3 ======================================================= */ + #define R_MFWD_FWL23URL3_L23UCVIDL_Pos (0UL) /*!< L23UCVIDL (Bit 0) */ + #define R_MFWD_FWL23URL3_L23UCVIDL_Msk (0xfffUL) /*!< L23UCVIDL (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWL23URL3_L23UCPCPL_Pos (12UL) /*!< L23UCPCPL (Bit 12) */ + #define R_MFWD_FWL23URL3_L23UCPCPL_Msk (0x7000UL) /*!< L23UCPCPL (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URL3_L23UCDEIL_Pos (15UL) /*!< L23UCDEIL (Bit 15) */ + #define R_MFWD_FWL23URL3_L23UCDEIL_Msk (0x8000UL) /*!< L23UCDEIL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL3_L23USVIDL_Pos (16UL) /*!< L23USVIDL (Bit 16) */ + #define R_MFWD_FWL23URL3_L23USVIDL_Msk (0xfff0000UL) /*!< L23USVIDL (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWL23URL3_L23USPCPL_Pos (28UL) /*!< L23USPCPL (Bit 28) */ + #define R_MFWD_FWL23URL3_L23USPCPL_Msk (0x70000000UL) /*!< L23USPCPL (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URL3_L23USDEIL_Pos (31UL) /*!< L23USDEIL (Bit 31) */ + #define R_MFWD_FWL23URL3_L23USDEIL_Msk (0x80000000UL) /*!< L23USDEIL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWL23URLR ======================================================= */ + #define R_MFWD_FWL23URLR_L23ULF_Pos (0UL) /*!< L23ULF (Bit 0) */ + #define R_MFWD_FWL23URLR_L23ULF_Msk (0x1UL) /*!< L23ULF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URLR_L23URL_Pos (31UL) /*!< L23URL (Bit 31) */ + #define R_MFWD_FWL23URLR_L23URL_Msk (0x80000000UL) /*!< L23URL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWL23UTIM ======================================================= */ + #define R_MFWD_FWL23UTIM_L23UTIOG_Pos (0UL) /*!< L23UTIOG (Bit 0) */ + #define R_MFWD_FWL23UTIM_L23UTIOG_Msk (0x1UL) /*!< L23UTIOG (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23UTIM_L23UTR_Pos (1UL) /*!< L23UTR (Bit 1) */ + #define R_MFWD_FWL23UTIM_L23UTR_Msk (0x2UL) /*!< L23UTR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWL23URR ======================================================== */ + #define R_MFWD_FWL23URR_L23RNR_Pos (0UL) /*!< L23RNR (Bit 0) */ + #define R_MFWD_FWL23URR_L23RNR_Msk (0xffUL) /*!< L23RNR (Bitfield-Mask: 0xff) */ +/* ====================================================== FWL23URRR0 ======================================================= */ + #define R_MFWD_FWL23URRR0_L23URPVR_Pos (0UL) /*!< L23URPVR (Bit 0) */ + #define R_MFWD_FWL23URRR0_L23URPVR_Msk (0x7fUL) /*!< L23URPVR (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWL23URRR0_L23UREF_Pos (16UL) /*!< L23UREF (Bit 16) */ + #define R_MFWD_FWL23URRR0_L23UREF_Msk (0x10000UL) /*!< L23UREF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR0_L23URR_Pos (31UL) /*!< L23URR (Bit 31) */ + #define R_MFWD_FWL23URRR0_L23URR_Msk (0x80000000UL) /*!< L23URR (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URRR1 ======================================================= */ + #define R_MFWD_FWL23URRR1_L23UMDARP0_Pos (0UL) /*!< L23UMDARP0 (Bit 0) */ + #define R_MFWD_FWL23URRR1_L23UMDARP0_Msk (0xffffUL) /*!< L23UMDARP0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWL23URRR1_L23UTTLUR_Pos (16UL) /*!< L23UTTLUR (Bit 16) */ + #define R_MFWD_FWL23URRR1_L23UTTLUR_Msk (0x10000UL) /*!< L23UTTLUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23UMDAUR_Pos (17UL) /*!< L23UMDAUR (Bit 17) */ + #define R_MFWD_FWL23URRR1_L23UMDAUR_Msk (0x20000UL) /*!< L23UMDAUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23UMSAUR_Pos (18UL) /*!< L23UMSAUR (Bit 18) */ + #define R_MFWD_FWL23URRR1_L23UMSAUR_Msk (0x40000UL) /*!< L23UMSAUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23UCVIDUR_Pos (19UL) /*!< L23UCVIDUR (Bit 19) */ + #define R_MFWD_FWL23URRR1_L23UCVIDUR_Msk (0x80000UL) /*!< L23UCVIDUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23UCPCPUR_Pos (20UL) /*!< L23UCPCPUR (Bit 20) */ + #define R_MFWD_FWL23URRR1_L23UCPCPUR_Msk (0x100000UL) /*!< L23UCPCPUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23UCDEIUR_Pos (21UL) /*!< L23UCDEIUR (Bit 21) */ + #define R_MFWD_FWL23URRR1_L23UCDEIUR_Msk (0x200000UL) /*!< L23UCDEIUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23USVIDUR_Pos (22UL) /*!< L23USVIDUR (Bit 22) */ + #define R_MFWD_FWL23URRR1_L23USVIDUR_Msk (0x400000UL) /*!< L23USVIDUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23USPCPUR_Pos (23UL) /*!< L23USPCPUR (Bit 23) */ + #define R_MFWD_FWL23URRR1_L23USPCPUR_Msk (0x800000UL) /*!< L23USPCPUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23USDEIUR_Pos (24UL) /*!< L23USDEIUR (Bit 24) */ + #define R_MFWD_FWL23URRR1_L23USDEIUR_Msk (0x1000000UL) /*!< L23USDEIUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23URTUR_Pos (25UL) /*!< L23URTUR (Bit 25) */ + #define R_MFWD_FWL23URRR1_L23URTUR_Msk (0x6000000UL) /*!< L23URTUR (Bitfield-Mask: 0x03) */ +/* ====================================================== FWL23URRR2 ======================================================= */ + #define R_MFWD_FWL23URRR2_L23UMDARP1_Pos (0UL) /*!< L23UMDARP1 (Bit 0) */ + #define R_MFWD_FWL23URRR2_L23UMDARP1_Msk (0xffffffffUL) /*!< L23UMDARP1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWL23URRR3 ======================================================= */ + #define R_MFWD_FWL23URRR3_L23UCVIDR_Pos (0UL) /*!< L23UCVIDR (Bit 0) */ + #define R_MFWD_FWL23URRR3_L23UCVIDR_Msk (0xfffUL) /*!< L23UCVIDR (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWL23URRR3_L23UCPCPR_Pos (12UL) /*!< L23UCPCPR (Bit 12) */ + #define R_MFWD_FWL23URRR3_L23UCPCPR_Msk (0x7000UL) /*!< L23UCPCPR (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URRR3_L23UCDEIR_Pos (15UL) /*!< L23UCDEIR (Bit 15) */ + #define R_MFWD_FWL23URRR3_L23UCDEIR_Msk (0x8000UL) /*!< L23UCDEIR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR3_L23USVIDR_Pos (16UL) /*!< L23USVIDR (Bit 16) */ + #define R_MFWD_FWL23URRR3_L23USVIDR_Msk (0xfff0000UL) /*!< L23USVIDR (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWL23URRR3_L23USPCPR_Pos (28UL) /*!< L23USPCPR (Bit 28) */ + #define R_MFWD_FWL23URRR3_L23USPCPR_Msk (0x70000000UL) /*!< L23USPCPR (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URRR3_L23USDEIR_Pos (31UL) /*!< L23USDEIR (Bit 31) */ + #define R_MFWD_FWL23URRR3_L23USDEIR_Msk (0x80000000UL) /*!< L23USDEIR (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC0 ======================================================= */ + #define R_MFWD_FWL23URMC0_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC0_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC0_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC0_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC0_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC0_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC0_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC0_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC1 ======================================================= */ + #define R_MFWD_FWL23URMC1_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC1_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC1_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC1_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC1_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC1_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC1_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC1_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC2 ======================================================= */ + #define R_MFWD_FWL23URMC2_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC2_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC2_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC2_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC2_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC2_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC2_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC2_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC3 ======================================================= */ + #define R_MFWD_FWL23URMC3_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC3_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC3_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC3_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC3_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC3_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC3_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC3_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC4 ======================================================= */ + #define R_MFWD_FWL23URMC4_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC4_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC4_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC4_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC4_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC4_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC4_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC4_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC5 ======================================================= */ + #define R_MFWD_FWL23URMC5_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC5_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC5_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC5_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC5_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC5_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC5_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC5_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC6 ======================================================= */ + #define R_MFWD_FWL23URMC6_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC6_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC6_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC6_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC6_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC6_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC6_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC6_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC7 ======================================================= */ + #define R_MFWD_FWL23URMC7_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC7_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC7_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC7_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC7_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC7_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC7_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC7_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC8 ======================================================= */ + #define R_MFWD_FWL23URMC8_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC8_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC8_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC8_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC8_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC8_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC8_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC8_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC9 ======================================================= */ + #define R_MFWD_FWL23URMC9_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC9_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC9_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC9_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC9_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC9_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC9_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC9_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC10 ====================================================== */ + #define R_MFWD_FWL23URMC10_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC10_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC10_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC10_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC10_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC10_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC10_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC10_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC11 ====================================================== */ + #define R_MFWD_FWL23URMC11_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC11_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC11_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC11_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC11_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC11_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC11_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC11_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC12 ====================================================== */ + #define R_MFWD_FWL23URMC12_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC12_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC12_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC12_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC12_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC12_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC12_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC12_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC13 ====================================================== */ + #define R_MFWD_FWL23URMC13_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC13_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC13_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC13_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC13_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC13_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC13_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC13_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC14 ====================================================== */ + #define R_MFWD_FWL23URMC14_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC14_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC14_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC14_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC14_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC14_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC14_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC14_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC15 ====================================================== */ + #define R_MFWD_FWL23URMC15_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC15_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC15_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC15_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC15_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC15_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC15_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC15_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC16 ====================================================== */ + #define R_MFWD_FWL23URMC16_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC16_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC16_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC16_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC16_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC16_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC16_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC16_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC17 ====================================================== */ + #define R_MFWD_FWL23URMC17_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC17_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC17_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC17_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC17_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC17_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC17_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC17_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC18 ====================================================== */ + #define R_MFWD_FWL23URMC18_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC18_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC18_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC18_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC18_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC18_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC18_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC18_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC19 ====================================================== */ + #define R_MFWD_FWL23URMC19_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC19_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC19_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC19_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC19_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC19_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC19_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC19_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC20 ====================================================== */ + #define R_MFWD_FWL23URMC20_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC20_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC20_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC20_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC20_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC20_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC20_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC20_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC21 ====================================================== */ + #define R_MFWD_FWL23URMC21_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC21_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC21_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC21_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC21_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC21_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC21_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC21_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC22 ====================================================== */ + #define R_MFWD_FWL23URMC22_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC22_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC22_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC22_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC22_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC22_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC22_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC22_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC23 ====================================================== */ + #define R_MFWD_FWL23URMC23_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC23_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC23_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC23_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC23_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC23_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC23_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC23_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC24 ====================================================== */ + #define R_MFWD_FWL23URMC24_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC24_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC24_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC24_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC24_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC24_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC24_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC24_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC25 ====================================================== */ + #define R_MFWD_FWL23URMC25_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC25_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC25_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC25_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC25_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC25_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC25_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC25_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC26 ====================================================== */ + #define R_MFWD_FWL23URMC26_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC26_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC26_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC26_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC26_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC26_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC26_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC26_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC27 ====================================================== */ + #define R_MFWD_FWL23URMC27_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC27_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC27_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC27_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC27_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC27_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC27_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC27_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC28 ====================================================== */ + #define R_MFWD_FWL23URMC28_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC28_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC28_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC28_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC28_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC28_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC28_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC28_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC29 ====================================================== */ + #define R_MFWD_FWL23URMC29_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC29_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC29_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC29_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC29_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC29_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC29_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC29_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC30 ====================================================== */ + #define R_MFWD_FWL23URMC30_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC30_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC30_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC30_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC30_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC30_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC30_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC30_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC31 ====================================================== */ + #define R_MFWD_FWL23URMC31_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC31_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC31_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC31_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC31_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC31_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC31_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC31_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC0 ======================================================== */ + #define R_MFWD_FWPMFGC0_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC0_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC0_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC0_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC1 ======================================================== */ + #define R_MFWD_FWPMFGC1_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC1_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC1_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC1_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC2 ======================================================== */ + #define R_MFWD_FWPMFGC2_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC2_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC2_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC2_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC3 ======================================================== */ + #define R_MFWD_FWPMFGC3_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC3_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC3_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC3_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC4 ======================================================== */ + #define R_MFWD_FWPMFGC4_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC4_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC4_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC4_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC5 ======================================================== */ + #define R_MFWD_FWPMFGC5_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC5_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC5_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC5_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC6 ======================================================== */ + #define R_MFWD_FWPMFGC6_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC6_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC6_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC6_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC7 ======================================================== */ + #define R_MFWD_FWPMFGC7_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC7_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC7_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC7_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC8 ======================================================== */ + #define R_MFWD_FWPMFGC8_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC8_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC8_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC8_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC9 ======================================================== */ + #define R_MFWD_FWPMFGC9_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC9_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC9_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC9_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC10 ======================================================= */ + #define R_MFWD_FWPMFGC10_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC10_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC10_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC10_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC11 ======================================================= */ + #define R_MFWD_FWPMFGC11_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC11_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC11_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC11_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC12 ======================================================= */ + #define R_MFWD_FWPMFGC12_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC12_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC12_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC12_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC13 ======================================================= */ + #define R_MFWD_FWPMFGC13_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC13_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC13_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC13_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC14 ======================================================= */ + #define R_MFWD_FWPMFGC14_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC14_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC14_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC14_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC15 ======================================================= */ + #define R_MFWD_FWPMFGC15_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC15_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC15_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC15_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMTRFC0 ======================================================= */ + #define R_MFWD_FWPMTRFC0_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC0_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC0_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC0_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC0_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC0_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC0_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC0_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC0_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC0_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC1 ======================================================= */ + #define R_MFWD_FWPMTRFC1_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC1_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC1_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC1_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC1_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC1_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC1_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC1_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC1_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC1_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC2 ======================================================= */ + #define R_MFWD_FWPMTRFC2_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC2_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC2_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC2_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC2_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC2_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC2_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC2_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC2_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC2_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC3 ======================================================= */ + #define R_MFWD_FWPMTRFC3_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC3_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC3_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC3_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC3_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC3_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC3_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC3_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC3_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC3_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC4 ======================================================= */ + #define R_MFWD_FWPMTRFC4_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC4_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC4_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC4_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC4_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC4_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC4_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC4_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC4_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC4_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC5 ======================================================= */ + #define R_MFWD_FWPMTRFC5_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC5_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC5_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC5_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC5_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC5_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC5_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC5_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC5_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC5_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC6 ======================================================= */ + #define R_MFWD_FWPMTRFC6_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC6_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC6_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC6_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC6_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC6_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC6_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC6_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC6_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC6_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC7 ======================================================= */ + #define R_MFWD_FWPMTRFC7_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC7_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC7_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC7_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC7_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC7_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC7_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC7_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC7_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC7_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC8 ======================================================= */ + #define R_MFWD_FWPMTRFC8_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC8_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC8_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC8_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC8_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC8_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC8_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC8_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC8_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC8_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC9 ======================================================= */ + #define R_MFWD_FWPMTRFC9_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC9_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC9_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC9_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC9_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC9_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC9_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC9_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC9_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC9_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC10 ======================================================= */ + #define R_MFWD_FWPMTRFC10_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC10_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC10_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC10_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC10_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC10_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC10_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC10_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC10_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC10_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC11 ======================================================= */ + #define R_MFWD_FWPMTRFC11_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC11_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC11_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC11_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC11_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC11_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC11_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC11_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC11_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC11_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC12 ======================================================= */ + #define R_MFWD_FWPMTRFC12_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC12_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC12_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC12_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC12_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC12_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC12_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC12_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC12_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC12_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC13 ======================================================= */ + #define R_MFWD_FWPMTRFC13_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC13_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC13_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC13_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC13_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC13_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC13_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC13_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC13_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC13_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC14 ======================================================= */ + #define R_MFWD_FWPMTRFC14_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC14_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC14_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC14_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC14_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC14_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC14_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC14_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC14_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC14_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC15 ======================================================= */ + #define R_MFWD_FWPMTRFC15_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC15_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC15_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC15_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC15_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC15_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC15_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC15_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC15_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC15_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC16 ======================================================= */ + #define R_MFWD_FWPMTRFC16_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC16_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC16_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC16_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC16_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC16_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC16_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC16_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC16_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC16_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC17 ======================================================= */ + #define R_MFWD_FWPMTRFC17_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC17_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC17_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC17_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC17_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC17_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC17_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC17_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC17_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC17_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC18 ======================================================= */ + #define R_MFWD_FWPMTRFC18_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC18_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC18_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC18_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC18_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC18_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC18_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC18_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC18_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC18_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC19 ======================================================= */ + #define R_MFWD_FWPMTRFC19_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC19_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC19_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC19_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC19_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC19_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC19_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC19_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC19_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC19_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC20 ======================================================= */ + #define R_MFWD_FWPMTRFC20_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC20_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC20_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC20_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC20_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC20_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC20_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC20_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC20_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC20_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC21 ======================================================= */ + #define R_MFWD_FWPMTRFC21_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC21_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC21_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC21_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC21_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC21_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC21_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC21_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC21_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC21_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC22 ======================================================= */ + #define R_MFWD_FWPMTRFC22_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC22_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC22_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC22_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC22_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC22_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC22_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC22_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC22_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC22_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC23 ======================================================= */ + #define R_MFWD_FWPMTRFC23_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC23_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC23_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC23_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC23_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC23_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC23_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC23_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC23_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC23_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC24 ======================================================= */ + #define R_MFWD_FWPMTRFC24_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC24_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC24_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC24_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC24_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC24_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC24_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC24_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC24_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC24_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC25 ======================================================= */ + #define R_MFWD_FWPMTRFC25_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC25_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC25_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC25_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC25_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC25_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC25_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC25_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC25_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC25_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC26 ======================================================= */ + #define R_MFWD_FWPMTRFC26_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC26_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC26_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC26_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC26_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC26_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC26_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC26_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC26_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC26_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC27 ======================================================= */ + #define R_MFWD_FWPMTRFC27_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC27_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC27_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC27_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC27_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC27_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC27_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC27_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC27_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC27_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC28 ======================================================= */ + #define R_MFWD_FWPMTRFC28_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC28_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC28_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC28_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC28_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC28_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC28_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC28_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC28_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC28_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC29 ======================================================= */ + #define R_MFWD_FWPMTRFC29_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC29_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC29_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC29_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC29_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC29_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC29_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC29_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC29_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC29_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC30 ======================================================= */ + #define R_MFWD_FWPMTRFC30_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC30_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC30_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC30_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC30_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC30_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC30_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC30_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC30_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC30_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC31 ======================================================= */ + #define R_MFWD_FWPMTRFC31_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC31_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC31_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC31_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC31_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC31_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC31_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC31_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC31_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC31_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRCBSC0 ====================================================== */ + #define R_MFWD_FWPMTRCBSC0_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC0_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC1 ====================================================== */ + #define R_MFWD_FWPMTRCBSC1_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC1_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC2 ====================================================== */ + #define R_MFWD_FWPMTRCBSC2_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC2_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC3 ====================================================== */ + #define R_MFWD_FWPMTRCBSC3_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC3_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC4 ====================================================== */ + #define R_MFWD_FWPMTRCBSC4_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC4_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC5 ====================================================== */ + #define R_MFWD_FWPMTRCBSC5_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC5_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC6 ====================================================== */ + #define R_MFWD_FWPMTRCBSC6_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC6_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC7 ====================================================== */ + #define R_MFWD_FWPMTRCBSC7_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC7_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC8 ====================================================== */ + #define R_MFWD_FWPMTRCBSC8_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC8_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC9 ====================================================== */ + #define R_MFWD_FWPMTRCBSC9_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC9_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC10 ====================================================== */ + #define R_MFWD_FWPMTRCBSC10_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC10_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC11 ====================================================== */ + #define R_MFWD_FWPMTRCBSC11_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC11_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC12 ====================================================== */ + #define R_MFWD_FWPMTRCBSC12_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC12_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC13 ====================================================== */ + #define R_MFWD_FWPMTRCBSC13_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC13_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC14 ====================================================== */ + #define R_MFWD_FWPMTRCBSC14_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC14_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC15 ====================================================== */ + #define R_MFWD_FWPMTRCBSC15_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC15_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC16 ====================================================== */ + #define R_MFWD_FWPMTRCBSC16_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC16_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC17 ====================================================== */ + #define R_MFWD_FWPMTRCBSC17_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC17_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC18 ====================================================== */ + #define R_MFWD_FWPMTRCBSC18_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC18_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC19 ====================================================== */ + #define R_MFWD_FWPMTRCBSC19_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC19_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC20 ====================================================== */ + #define R_MFWD_FWPMTRCBSC20_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC20_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC21 ====================================================== */ + #define R_MFWD_FWPMTRCBSC21_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC21_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC22 ====================================================== */ + #define R_MFWD_FWPMTRCBSC22_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC22_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC23 ====================================================== */ + #define R_MFWD_FWPMTRCBSC23_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC23_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC24 ====================================================== */ + #define R_MFWD_FWPMTRCBSC24_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC24_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC25 ====================================================== */ + #define R_MFWD_FWPMTRCBSC25_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC25_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC26 ====================================================== */ + #define R_MFWD_FWPMTRCBSC26_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC26_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC27 ====================================================== */ + #define R_MFWD_FWPMTRCBSC27_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC27_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC28 ====================================================== */ + #define R_MFWD_FWPMTRCBSC28_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC28_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC29 ====================================================== */ + #define R_MFWD_FWPMTRCBSC29_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC29_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC30 ====================================================== */ + #define R_MFWD_FWPMTRCBSC30_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC30_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC31 ====================================================== */ + #define R_MFWD_FWPMTRCBSC31_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC31_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCIRC0 ====================================================== */ + #define R_MFWD_FWPMTRCIRC0_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC0_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC1 ====================================================== */ + #define R_MFWD_FWPMTRCIRC1_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC1_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC2 ====================================================== */ + #define R_MFWD_FWPMTRCIRC2_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC2_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC3 ====================================================== */ + #define R_MFWD_FWPMTRCIRC3_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC3_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC4 ====================================================== */ + #define R_MFWD_FWPMTRCIRC4_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC4_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC5 ====================================================== */ + #define R_MFWD_FWPMTRCIRC5_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC5_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC6 ====================================================== */ + #define R_MFWD_FWPMTRCIRC6_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC6_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC7 ====================================================== */ + #define R_MFWD_FWPMTRCIRC7_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC7_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC8 ====================================================== */ + #define R_MFWD_FWPMTRCIRC8_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC8_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC9 ====================================================== */ + #define R_MFWD_FWPMTRCIRC9_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC9_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC10 ====================================================== */ + #define R_MFWD_FWPMTRCIRC10_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC10_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC11 ====================================================== */ + #define R_MFWD_FWPMTRCIRC11_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC11_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC12 ====================================================== */ + #define R_MFWD_FWPMTRCIRC12_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC12_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC13 ====================================================== */ + #define R_MFWD_FWPMTRCIRC13_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC13_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC14 ====================================================== */ + #define R_MFWD_FWPMTRCIRC14_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC14_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC15 ====================================================== */ + #define R_MFWD_FWPMTRCIRC15_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC15_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC16 ====================================================== */ + #define R_MFWD_FWPMTRCIRC16_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC16_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC17 ====================================================== */ + #define R_MFWD_FWPMTRCIRC17_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC17_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC18 ====================================================== */ + #define R_MFWD_FWPMTRCIRC18_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC18_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC19 ====================================================== */ + #define R_MFWD_FWPMTRCIRC19_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC19_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC20 ====================================================== */ + #define R_MFWD_FWPMTRCIRC20_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC20_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC21 ====================================================== */ + #define R_MFWD_FWPMTRCIRC21_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC21_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC22 ====================================================== */ + #define R_MFWD_FWPMTRCIRC22_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC22_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC23 ====================================================== */ + #define R_MFWD_FWPMTRCIRC23_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC23_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC24 ====================================================== */ + #define R_MFWD_FWPMTRCIRC24_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC24_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC25 ====================================================== */ + #define R_MFWD_FWPMTRCIRC25_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC25_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC26 ====================================================== */ + #define R_MFWD_FWPMTRCIRC26_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC26_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC27 ====================================================== */ + #define R_MFWD_FWPMTRCIRC27_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC27_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC28 ====================================================== */ + #define R_MFWD_FWPMTRCIRC28_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC28_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC29 ====================================================== */ + #define R_MFWD_FWPMTRCIRC29_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC29_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC30 ====================================================== */ + #define R_MFWD_FWPMTRCIRC30_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC30_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC31 ====================================================== */ + #define R_MFWD_FWPMTRCIRC31_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC31_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREBSC0 ====================================================== */ + #define R_MFWD_FWPMTREBSC0_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC0_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREBSC1 ====================================================== */ + #define R_MFWD_FWPMTREBSC1_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC1_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREBSC2 ====================================================== */ + #define R_MFWD_FWPMTREBSC2_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC2_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREBSC3 ====================================================== */ + #define R_MFWD_FWPMTREBSC3_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC3_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREBSC4 ====================================================== */ + #define R_MFWD_FWPMTREBSC4_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC4_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREBSC5 ====================================================== */ + #define R_MFWD_FWPMTREBSC5_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC5_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREBSC6 ====================================================== */ + #define R_MFWD_FWPMTREBSC6_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC6_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREBSC7 ====================================================== */ + #define R_MFWD_FWPMTREBSC7_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC7_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREIRC0 ====================================================== */ + #define R_MFWD_FWPMTREIRC0_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC0_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREIRC1 ====================================================== */ + #define R_MFWD_FWPMTREIRC1_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC1_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREIRC2 ====================================================== */ + #define R_MFWD_FWPMTREIRC2_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC2_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREIRC3 ====================================================== */ + #define R_MFWD_FWPMTREIRC3_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC3_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREIRC4 ====================================================== */ + #define R_MFWD_FWPMTREIRC4_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC4_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREIRC5 ====================================================== */ + #define R_MFWD_FWPMTREIRC5_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC5_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREIRC6 ====================================================== */ + #define R_MFWD_FWPMTREIRC6_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC6_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREIRC7 ====================================================== */ + #define R_MFWD_FWPMTREIRC7_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC7_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ======================================================= FWPMTRFM0 ======================================================= */ + #define R_MFWD_FWPMTRFM0_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM0_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM0_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM0_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM1 ======================================================= */ + #define R_MFWD_FWPMTRFM1_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM1_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM1_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM1_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM2 ======================================================= */ + #define R_MFWD_FWPMTRFM2_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM2_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM2_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM2_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM3 ======================================================= */ + #define R_MFWD_FWPMTRFM3_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM3_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM3_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM3_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM4 ======================================================= */ + #define R_MFWD_FWPMTRFM4_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM4_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM4_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM4_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM5 ======================================================= */ + #define R_MFWD_FWPMTRFM5_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM5_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM5_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM5_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM6 ======================================================= */ + #define R_MFWD_FWPMTRFM6_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM6_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM6_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM6_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM7 ======================================================= */ + #define R_MFWD_FWPMTRFM7_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM7_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM7_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM7_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM8 ======================================================= */ + #define R_MFWD_FWPMTRFM8_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM8_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM8_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM8_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM9 ======================================================= */ + #define R_MFWD_FWPMTRFM9_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM9_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM9_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM9_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM10 ======================================================= */ + #define R_MFWD_FWPMTRFM10_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM10_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM10_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM10_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM11 ======================================================= */ + #define R_MFWD_FWPMTRFM11_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM11_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM11_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM11_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM12 ======================================================= */ + #define R_MFWD_FWPMTRFM12_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM12_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM12_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM12_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM13 ======================================================= */ + #define R_MFWD_FWPMTRFM13_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM13_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM13_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM13_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM14 ======================================================= */ + #define R_MFWD_FWPMTRFM14_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM14_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM14_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM14_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM15 ======================================================= */ + #define R_MFWD_FWPMTRFM15_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM15_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM15_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM15_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM16 ======================================================= */ + #define R_MFWD_FWPMTRFM16_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM16_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM16_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM16_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM17 ======================================================= */ + #define R_MFWD_FWPMTRFM17_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM17_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM17_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM17_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM18 ======================================================= */ + #define R_MFWD_FWPMTRFM18_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM18_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM18_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM18_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM19 ======================================================= */ + #define R_MFWD_FWPMTRFM19_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM19_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM19_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM19_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM20 ======================================================= */ + #define R_MFWD_FWPMTRFM20_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM20_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM20_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM20_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM21 ======================================================= */ + #define R_MFWD_FWPMTRFM21_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM21_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM21_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM21_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM22 ======================================================= */ + #define R_MFWD_FWPMTRFM22_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM22_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM22_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM22_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM23 ======================================================= */ + #define R_MFWD_FWPMTRFM23_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM23_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM23_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM23_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM24 ======================================================= */ + #define R_MFWD_FWPMTRFM24_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM24_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM24_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM24_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM25 ======================================================= */ + #define R_MFWD_FWPMTRFM25_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM25_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM25_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM25_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM26 ======================================================= */ + #define R_MFWD_FWPMTRFM26_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM26_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM26_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM26_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM27 ======================================================= */ + #define R_MFWD_FWPMTRFM27_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM27_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM27_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM27_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM28 ======================================================= */ + #define R_MFWD_FWPMTRFM28_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM28_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM28_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM28_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM29 ======================================================= */ + #define R_MFWD_FWPMTRFM29_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM29_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM29_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM29_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM30 ======================================================= */ + #define R_MFWD_FWPMTRFM30_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM30_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM30_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM30_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM31 ======================================================= */ + #define R_MFWD_FWPMTRFM31_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM31_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM31_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM31_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================== FWFTL0 ========================================================= */ + #define R_MFWD_FWFTL0_FEAL_Pos (0UL) /*!< FEAL (Bit 0) */ + #define R_MFWD_FWFTL0_FEAL_Msk (0x7fUL) /*!< FEAL (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWFTL0_FSRPL_Pos (16UL) /*!< FSRPL (Bit 16) */ + #define R_MFWD_FWFTL0_FSRPL_Msk (0x7f0000UL) /*!< FSRPL (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWFTL1 ========================================================= */ + #define R_MFWD_FWFTL1_FSHLL_Pos (0UL) /*!< FSHLL (Bit 0) */ + #define R_MFWD_FWFTL1_FSHLL_Msk (0xfUL) /*!< FSHLL (Bitfield-Mask: 0x0f) */ + #define R_MFWD_FWFTL1_FTNSL_Pos (8UL) /*!< FTNSL (Bit 8) */ + #define R_MFWD_FWFTL1_FTNSL_Msk (0x100UL) /*!< FTNSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTL1_FSRPVL_Pos (9UL) /*!< FSRPVL (Bit 9) */ + #define R_MFWD_FWFTL1_FSRPVL_Msk (0x200UL) /*!< FSRPVL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTL1_FSRRTL_Pos (16UL) /*!< FSRRTL (Bit 16) */ + #define R_MFWD_FWFTL1_FSRRTL_Msk (0x3ff0000UL) /*!< FSRRTL (Bitfield-Mask: 0x3ff) */ +/* ======================================================== FWFTLR ========================================================= */ + #define R_MFWD_FWFTLR_FLF_Pos (0UL) /*!< FLF (Bit 0) */ + #define R_MFWD_FWFTLR_FLF_Msk (0x1UL) /*!< FLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTLR_FTL_Pos (31UL) /*!< FTL (Bit 31) */ + #define R_MFWD_FWFTLR_FTL_Msk (0x80000000UL) /*!< FTL (Bitfield-Mask: 0x01) */ +/* ======================================================== FWFTOC ========================================================= */ + #define R_MFWD_FWFTOC_TOT_Pos (0UL) /*!< TOT (Bit 0) */ + #define R_MFWD_FWFTOC_TOT_Msk (0xffffUL) /*!< TOT (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWFTOC_TOCE_Pos (16UL) /*!< TOCE (Bit 16) */ + #define R_MFWD_FWFTOC_TOCE_Msk (0x10000UL) /*!< TOCE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTOC_TOOG_Pos (17UL) /*!< TOOG (Bit 17) */ + #define R_MFWD_FWFTOC_TOOG_Msk (0x20000UL) /*!< TOOG (Bitfield-Mask: 0x01) */ +/* ======================================================== FWFTOPC ======================================================== */ + #define R_MFWD_FWFTOPC_USP_Pos (0UL) /*!< USP (Bit 0) */ + #define R_MFWD_FWFTOPC_USP_Msk (0x3ffUL) /*!< USP (Bitfield-Mask: 0x3ff) */ +/* ======================================================== FWFTIM ========================================================= */ + #define R_MFWD_FWFTIM_FTIOG_Pos (0UL) /*!< FTIOG (Bit 0) */ + #define R_MFWD_FWFTIM_FTIOG_Msk (0x1UL) /*!< FTIOG (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTIM_FTR_Pos (1UL) /*!< FTR (Bit 1) */ + #define R_MFWD_FWFTIM_FTR_Msk (0x2UL) /*!< FTR (Bitfield-Mask: 0x01) */ +/* ========================================================= FWFTR ========================================================= */ + #define R_MFWD_FWFTR_FEAR_Pos (0UL) /*!< FEAR (Bit 0) */ + #define R_MFWD_FWFTR_FEAR_Msk (0x7fUL) /*!< FEAR (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWFTRR0 ======================================================== */ + #define R_MFWD_FWFTRR0_FSHLR_Pos (0UL) /*!< FSHLR (Bit 0) */ + #define R_MFWD_FWFTRR0_FSHLR_Msk (0xfUL) /*!< FSHLR (Bitfield-Mask: 0x0f) */ + #define R_MFWD_FWFTRR0_FTNSR_Pos (8UL) /*!< FTNSR (Bit 8) */ + #define R_MFWD_FWFTRR0_FTNSR_Msk (0x100UL) /*!< FTNSR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTRR0_FSRPVR_Pos (9UL) /*!< FSRPVR (Bit 9) */ + #define R_MFWD_FWFTRR0_FSRPVR_Msk (0x200UL) /*!< FSRPVR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTRR0_FSRRTR_Pos (16UL) /*!< FSRRTR (Bit 16) */ + #define R_MFWD_FWFTRR0_FSRRTR_Msk (0x3ff0000UL) /*!< FSRRTR (Bitfield-Mask: 0x3ff) */ + #define R_MFWD_FWFTRR0_FTREF_Pos (30UL) /*!< FTREF (Bit 30) */ + #define R_MFWD_FWFTRR0_FTREF_Msk (0x40000000UL) /*!< FTREF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTRR0_FTR_Pos (31UL) /*!< FTR (Bit 31) */ + #define R_MFWD_FWFTRR0_FTR_Msk (0x80000000UL) /*!< FTR (Bitfield-Mask: 0x01) */ +/* ======================================================== FWFTRR1 ======================================================== */ + #define R_MFWD_FWFTRR1_FSHR_Pos (0UL) /*!< FSHR (Bit 0) */ + #define R_MFWD_FWFTRR1_FSHR_Msk (0x7fffUL) /*!< FSHR (Bitfield-Mask: 0x7fff) */ + #define R_MFWD_FWFTRR1_FSRPR_Pos (16UL) /*!< FSRPR (Bit 16) */ + #define R_MFWD_FWFTRR1_FSRPR_Msk (0x7f0000UL) /*!< FSRPR (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWFTRR2 ======================================================== */ + #define R_MFWD_FWFTRR2_FRSNR_Pos (0UL) /*!< FRSNR (Bit 0) */ + #define R_MFWD_FWFTRR2_FRSNR_Msk (0xffffUL) /*!< FRSNR (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWFTRR2_FRRTR_Pos (16UL) /*!< FRRTR (Bit 16) */ + #define R_MFWD_FWFTRR2_FRRTR_Msk (0x3ff0000UL) /*!< FRRTR (Bitfield-Mask: 0x3ff) */ +/* ======================================================= FWSEQNGC0 ======================================================= */ + #define R_MFWD_FWSEQNGC0_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC0_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC0_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC0_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC1 ======================================================= */ + #define R_MFWD_FWSEQNGC1_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC1_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC1_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC1_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC2 ======================================================= */ + #define R_MFWD_FWSEQNGC2_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC2_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC2_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC2_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC3 ======================================================= */ + #define R_MFWD_FWSEQNGC3_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC3_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC3_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC3_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC4 ======================================================= */ + #define R_MFWD_FWSEQNGC4_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC4_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC4_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC4_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC5 ======================================================= */ + #define R_MFWD_FWSEQNGC5_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC5_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC5_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC5_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC6 ======================================================= */ + #define R_MFWD_FWSEQNGC6_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC6_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC6_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC6_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC7 ======================================================= */ + #define R_MFWD_FWSEQNGC7_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC7_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC7_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC7_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC8 ======================================================= */ + #define R_MFWD_FWSEQNGC8_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC8_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC8_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC8_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC9 ======================================================= */ + #define R_MFWD_FWSEQNGC9_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC9_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC9_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC9_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC10 ======================================================= */ + #define R_MFWD_FWSEQNGC10_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC10_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC10_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC10_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC11 ======================================================= */ + #define R_MFWD_FWSEQNGC11_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC11_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC11_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC11_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC12 ======================================================= */ + #define R_MFWD_FWSEQNGC12_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC12_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC12_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC12_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC13 ======================================================= */ + #define R_MFWD_FWSEQNGC13_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC13_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC13_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC13_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC14 ======================================================= */ + #define R_MFWD_FWSEQNGC14_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC14_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC14_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC14_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC15 ======================================================= */ + #define R_MFWD_FWSEQNGC15_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC15_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC15_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC15_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC16 ======================================================= */ + #define R_MFWD_FWSEQNGC16_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC16_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC16_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC16_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC17 ======================================================= */ + #define R_MFWD_FWSEQNGC17_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC17_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC17_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC17_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC18 ======================================================= */ + #define R_MFWD_FWSEQNGC18_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC18_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC18_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC18_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC19 ======================================================= */ + #define R_MFWD_FWSEQNGC19_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC19_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC19_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC19_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC20 ======================================================= */ + #define R_MFWD_FWSEQNGC20_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC20_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC20_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC20_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC21 ======================================================= */ + #define R_MFWD_FWSEQNGC21_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC21_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC21_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC21_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC22 ======================================================= */ + #define R_MFWD_FWSEQNGC22_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC22_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC22_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC22_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC23 ======================================================= */ + #define R_MFWD_FWSEQNGC23_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC23_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC23_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC23_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC24 ======================================================= */ + #define R_MFWD_FWSEQNGC24_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC24_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC24_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC24_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC25 ======================================================= */ + #define R_MFWD_FWSEQNGC25_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC25_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC25_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC25_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC26 ======================================================= */ + #define R_MFWD_FWSEQNGC26_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC26_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC26_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC26_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC27 ======================================================= */ + #define R_MFWD_FWSEQNGC27_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC27_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC27_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC27_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC28 ======================================================= */ + #define R_MFWD_FWSEQNGC28_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC28_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC28_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC28_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC29 ======================================================= */ + #define R_MFWD_FWSEQNGC29_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC29_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC29_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC29_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC30 ======================================================= */ + #define R_MFWD_FWSEQNGC30_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC30_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC30_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC30_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC31 ======================================================= */ + #define R_MFWD_FWSEQNGC31_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC31_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC31_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC31_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGM0 ======================================================= */ + #define R_MFWD_FWSEQNGM0_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM0_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM1 ======================================================= */ + #define R_MFWD_FWSEQNGM1_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM1_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM2 ======================================================= */ + #define R_MFWD_FWSEQNGM2_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM2_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM3 ======================================================= */ + #define R_MFWD_FWSEQNGM3_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM3_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM4 ======================================================= */ + #define R_MFWD_FWSEQNGM4_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM4_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM5 ======================================================= */ + #define R_MFWD_FWSEQNGM5_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM5_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM6 ======================================================= */ + #define R_MFWD_FWSEQNGM6_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM6_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM7 ======================================================= */ + #define R_MFWD_FWSEQNGM7_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM7_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM8 ======================================================= */ + #define R_MFWD_FWSEQNGM8_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM8_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM9 ======================================================= */ + #define R_MFWD_FWSEQNGM9_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM9_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM10 ======================================================= */ + #define R_MFWD_FWSEQNGM10_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM10_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM11 ======================================================= */ + #define R_MFWD_FWSEQNGM11_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM11_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM12 ======================================================= */ + #define R_MFWD_FWSEQNGM12_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM12_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM13 ======================================================= */ + #define R_MFWD_FWSEQNGM13_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM13_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM14 ======================================================= */ + #define R_MFWD_FWSEQNGM14_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM14_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM15 ======================================================= */ + #define R_MFWD_FWSEQNGM15_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM15_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM16 ======================================================= */ + #define R_MFWD_FWSEQNGM16_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM16_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM17 ======================================================= */ + #define R_MFWD_FWSEQNGM17_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM17_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM18 ======================================================= */ + #define R_MFWD_FWSEQNGM18_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM18_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM19 ======================================================= */ + #define R_MFWD_FWSEQNGM19_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM19_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM20 ======================================================= */ + #define R_MFWD_FWSEQNGM20_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM20_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM21 ======================================================= */ + #define R_MFWD_FWSEQNGM21_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM21_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM22 ======================================================= */ + #define R_MFWD_FWSEQNGM22_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM22_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM23 ======================================================= */ + #define R_MFWD_FWSEQNGM23_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM23_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM24 ======================================================= */ + #define R_MFWD_FWSEQNGM24_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM24_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM25 ======================================================= */ + #define R_MFWD_FWSEQNGM25_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM25_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM26 ======================================================= */ + #define R_MFWD_FWSEQNGM26_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM26_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM27 ======================================================= */ + #define R_MFWD_FWSEQNGM27_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM27_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM28 ======================================================= */ + #define R_MFWD_FWSEQNGM28_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM28_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM29 ======================================================= */ + #define R_MFWD_FWSEQNGM29_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM29_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM30 ======================================================= */ + #define R_MFWD_FWSEQNGM30_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM30_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM31 ======================================================= */ + #define R_MFWD_FWSEQNGM31_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM31_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNRC ======================================================== */ + #define R_MFWD_FWSEQNRC_SEQNR_Pos (0UL) /*!< SEQNR (Bit 0) */ + #define R_MFWD_FWSEQNRC_SEQNR_Msk (0xffffffffUL) /*!< SEQNR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTFDCN0 ======================================================= */ + #define R_MFWD_FWCTFDCN0_CTFDN_Pos (0UL) /*!< CTFDN (Bit 0) */ + #define R_MFWD_FWCTFDCN0_CTFDN_Msk (0xffffffffUL) /*!< CTFDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTFDCN1 ======================================================= */ + #define R_MFWD_FWCTFDCN1_CTFDN_Pos (0UL) /*!< CTFDN (Bit 0) */ + #define R_MFWD_FWCTFDCN1_CTFDN_Msk (0xffffffffUL) /*!< CTFDN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWLTHFDCN0 ======================================================= */ + #define R_MFWD_FWLTHFDCN0_LTHFDN_Pos (0UL) /*!< LTHFDN (Bit 0) */ + #define R_MFWD_FWLTHFDCN0_LTHFDN_Msk (0xffffffffUL) /*!< LTHFDN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWLTHFDCN1 ======================================================= */ + #define R_MFWD_FWLTHFDCN1_LTHFDN_Pos (0UL) /*!< LTHFDN (Bit 0) */ + #define R_MFWD_FWLTHFDCN1_LTHFDN_Msk (0xffffffffUL) /*!< LTHFDN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWLTHFDCN2 ======================================================= */ + #define R_MFWD_FWLTHFDCN2_LTHFDN_Pos (0UL) /*!< LTHFDN (Bit 0) */ + #define R_MFWD_FWLTHFDCN2_LTHFDN_Msk (0xffffffffUL) /*!< LTHFDN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWLTWFDCN0 ======================================================= */ + #define R_MFWD_FWLTWFDCN0_LTWFDN_Pos (0UL) /*!< LTWFDN (Bit 0) */ + #define R_MFWD_FWLTWFDCN0_LTWFDN_Msk (0xffffffffUL) /*!< LTWFDN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWLTWFDCN1 ======================================================= */ + #define R_MFWD_FWLTWFDCN1_LTWFDN_Pos (0UL) /*!< LTWFDN (Bit 0) */ + #define R_MFWD_FWLTWFDCN1_LTWFDN_Msk (0xffffffffUL) /*!< LTWFDN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWLTWFDCN2 ======================================================= */ + #define R_MFWD_FWLTWFDCN2_LTWFDN_Pos (0UL) /*!< LTWFDN (Bit 0) */ + #define R_MFWD_FWLTWFDCN2_LTWFDN_Msk (0xffffffffUL) /*!< LTWFDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWPBFDCN0 ======================================================= */ + #define R_MFWD_FWPBFDCN0_PBFDN_Pos (0UL) /*!< PBFDN (Bit 0) */ + #define R_MFWD_FWPBFDCN0_PBFDN_Msk (0xffffffffUL) /*!< PBFDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWPBFDCN1 ======================================================= */ + #define R_MFWD_FWPBFDCN1_PBFDN_Pos (0UL) /*!< PBFDN (Bit 0) */ + #define R_MFWD_FWPBFDCN1_PBFDN_Msk (0xffffffffUL) /*!< PBFDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWPBFDCN2 ======================================================= */ + #define R_MFWD_FWPBFDCN2_PBFDN_Pos (0UL) /*!< PBFDN (Bit 0) */ + #define R_MFWD_FWPBFDCN2_PBFDN_Msk (0xffffffffUL) /*!< PBFDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWMHLCN0 ======================================================== */ + #define R_MFWD_FWMHLCN0_MHLN_Pos (0UL) /*!< MHLN (Bit 0) */ + #define R_MFWD_FWMHLCN0_MHLN_Msk (0xffffffffUL) /*!< MHLN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWMHLCN1 ======================================================== */ + #define R_MFWD_FWMHLCN1_MHLN_Pos (0UL) /*!< MHLN (Bit 0) */ + #define R_MFWD_FWMHLCN1_MHLN_Msk (0xffffffffUL) /*!< MHLN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWMHLCN2 ======================================================== */ + #define R_MFWD_FWMHLCN2_MHLN_Pos (0UL) /*!< MHLN (Bit 0) */ + #define R_MFWD_FWMHLCN2_MHLN_Msk (0xffffffffUL) /*!< MHLN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWDDFDCN0 ======================================================= */ + #define R_MFWD_FWDDFDCN0_DDFDN_Pos (0UL) /*!< DDFDN (Bit 0) */ + #define R_MFWD_FWDDFDCN0_DDFDN_Msk (0xffffffffUL) /*!< DDFDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWWMRDCN0 ======================================================= */ + #define R_MFWD_FWWMRDCN0_WMRDN_Pos (0UL) /*!< WMRDN (Bit 0) */ + #define R_MFWD_FWWMRDCN0_WMRDN_Msk (0xffffUL) /*!< WMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWWMRDCN1 ======================================================= */ + #define R_MFWD_FWWMRDCN1_WMRDN_Pos (0UL) /*!< WMRDN (Bit 0) */ + #define R_MFWD_FWWMRDCN1_WMRDN_Msk (0xffffUL) /*!< WMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWWMRDCN2 ======================================================= */ + #define R_MFWD_FWWMRDCN2_WMRDN_Pos (0UL) /*!< WMRDN (Bit 0) */ + #define R_MFWD_FWWMRDCN2_WMRDN_Msk (0xffffUL) /*!< WMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTRDCN0 ======================================================= */ + #define R_MFWD_FWCTRDCN0_CTRDN_Pos (0UL) /*!< CTRDN (Bit 0) */ + #define R_MFWD_FWCTRDCN0_CTRDN_Msk (0xffffUL) /*!< CTRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTRDCN1 ======================================================= */ + #define R_MFWD_FWCTRDCN1_CTRDN_Pos (0UL) /*!< CTRDN (Bit 0) */ + #define R_MFWD_FWCTRDCN1_CTRDN_Msk (0xffffUL) /*!< CTRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWLTHRDCN0 ======================================================= */ + #define R_MFWD_FWLTHRDCN0_LTHRDN_Pos (0UL) /*!< LTHRDN (Bit 0) */ + #define R_MFWD_FWLTHRDCN0_LTHRDN_Msk (0xffffUL) /*!< LTHRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWLTHRDCN1 ======================================================= */ + #define R_MFWD_FWLTHRDCN1_LTHRDN_Pos (0UL) /*!< LTHRDN (Bit 0) */ + #define R_MFWD_FWLTHRDCN1_LTHRDN_Msk (0xffffUL) /*!< LTHRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWLTHRDCN2 ======================================================= */ + #define R_MFWD_FWLTHRDCN2_LTHRDN_Pos (0UL) /*!< LTHRDN (Bit 0) */ + #define R_MFWD_FWLTHRDCN2_LTHRDN_Msk (0xffffUL) /*!< LTHRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWLTWRDCN0 ======================================================= */ + #define R_MFWD_FWLTWRDCN0_LTWRDN_Pos (0UL) /*!< LTWRDN (Bit 0) */ + #define R_MFWD_FWLTWRDCN0_LTWRDN_Msk (0xffffUL) /*!< LTWRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWLTWRDCN1 ======================================================= */ + #define R_MFWD_FWLTWRDCN1_LTWRDN_Pos (0UL) /*!< LTWRDN (Bit 0) */ + #define R_MFWD_FWLTWRDCN1_LTWRDN_Msk (0xffffUL) /*!< LTWRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWLTWRDCN2 ======================================================= */ + #define R_MFWD_FWLTWRDCN2_LTWRDN_Pos (0UL) /*!< LTWRDN (Bit 0) */ + #define R_MFWD_FWLTWRDCN2_LTWRDN_Msk (0xffffUL) /*!< LTWRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPBRDCN0 ======================================================= */ + #define R_MFWD_FWPBRDCN0_PBRDN_Pos (0UL) /*!< PBRDN (Bit 0) */ + #define R_MFWD_FWPBRDCN0_PBRDN_Msk (0xffffUL) /*!< PBRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPBRDCN1 ======================================================= */ + #define R_MFWD_FWPBRDCN1_PBRDN_Pos (0UL) /*!< PBRDN (Bit 0) */ + #define R_MFWD_FWPBRDCN1_PBRDN_Msk (0xffffUL) /*!< PBRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPBRDCN2 ======================================================= */ + #define R_MFWD_FWPBRDCN2_PBRDN_Pos (0UL) /*!< PBRDN (Bit 0) */ + #define R_MFWD_FWPBRDCN2_PBRDN_Msk (0xffffUL) /*!< PBRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWDDRDCN0 ======================================================= */ + #define R_MFWD_FWDDRDCN0_DDRDN_Pos (0UL) /*!< DDRDN (Bit 0) */ + #define R_MFWD_FWDDRDCN0_DDRDN_Msk (0xffffUL) /*!< DDRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN0 ======================================================= */ + #define R_MFWD_FWPMFDCN0_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN0_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN1 ======================================================= */ + #define R_MFWD_FWPMFDCN1_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN1_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN2 ======================================================= */ + #define R_MFWD_FWPMFDCN2_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN2_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN3 ======================================================= */ + #define R_MFWD_FWPMFDCN3_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN3_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN4 ======================================================= */ + #define R_MFWD_FWPMFDCN4_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN4_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN5 ======================================================= */ + #define R_MFWD_FWPMFDCN5_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN5_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN6 ======================================================= */ + #define R_MFWD_FWPMFDCN6_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN6_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN7 ======================================================= */ + #define R_MFWD_FWPMFDCN7_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN7_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN8 ======================================================= */ + #define R_MFWD_FWPMFDCN8_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN8_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN9 ======================================================= */ + #define R_MFWD_FWPMFDCN9_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN9_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMFDCN10 ======================================================= */ + #define R_MFWD_FWPMFDCN10_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN10_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMFDCN11 ======================================================= */ + #define R_MFWD_FWPMFDCN11_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN11_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMFDCN12 ======================================================= */ + #define R_MFWD_FWPMFDCN12_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN12_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMFDCN13 ======================================================= */ + #define R_MFWD_FWPMFDCN13_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN13_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMFDCN14 ======================================================= */ + #define R_MFWD_FWPMFDCN14_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN14_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMFDCN15 ======================================================= */ + #define R_MFWD_FWPMFDCN15_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN15_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN0 ======================================================= */ + #define R_MFWD_FWPMGDCN0_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN0_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN1 ======================================================= */ + #define R_MFWD_FWPMGDCN1_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN1_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN2 ======================================================= */ + #define R_MFWD_FWPMGDCN2_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN2_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN3 ======================================================= */ + #define R_MFWD_FWPMGDCN3_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN3_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN4 ======================================================= */ + #define R_MFWD_FWPMGDCN4_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN4_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN5 ======================================================= */ + #define R_MFWD_FWPMGDCN5_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN5_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN6 ======================================================= */ + #define R_MFWD_FWPMGDCN6_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN6_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN7 ======================================================= */ + #define R_MFWD_FWPMGDCN7_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN7_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN8 ======================================================= */ + #define R_MFWD_FWPMGDCN8_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN8_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN9 ======================================================= */ + #define R_MFWD_FWPMGDCN9_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN9_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN10 ======================================================= */ + #define R_MFWD_FWPMGDCN10_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN10_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN11 ======================================================= */ + #define R_MFWD_FWPMGDCN11_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN11_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN12 ======================================================= */ + #define R_MFWD_FWPMGDCN12_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN12_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN13 ======================================================= */ + #define R_MFWD_FWPMGDCN13_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN13_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN14 ======================================================= */ + #define R_MFWD_FWPMGDCN14_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN14_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN15 ======================================================= */ + #define R_MFWD_FWPMGDCN15_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN15_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN16 ======================================================= */ + #define R_MFWD_FWPMGDCN16_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN16_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN17 ======================================================= */ + #define R_MFWD_FWPMGDCN17_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN17_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN18 ======================================================= */ + #define R_MFWD_FWPMGDCN18_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN18_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN19 ======================================================= */ + #define R_MFWD_FWPMGDCN19_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN19_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN20 ======================================================= */ + #define R_MFWD_FWPMGDCN20_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN20_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN21 ======================================================= */ + #define R_MFWD_FWPMGDCN21_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN21_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN22 ======================================================= */ + #define R_MFWD_FWPMGDCN22_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN22_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN23 ======================================================= */ + #define R_MFWD_FWPMGDCN23_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN23_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN24 ======================================================= */ + #define R_MFWD_FWPMGDCN24_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN24_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN25 ======================================================= */ + #define R_MFWD_FWPMGDCN25_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN25_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN26 ======================================================= */ + #define R_MFWD_FWPMGDCN26_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN26_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN27 ======================================================= */ + #define R_MFWD_FWPMGDCN27_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN27_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN28 ======================================================= */ + #define R_MFWD_FWPMGDCN28_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN28_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN29 ======================================================= */ + #define R_MFWD_FWPMGDCN29_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN29_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN30 ======================================================= */ + #define R_MFWD_FWPMGDCN30_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN30_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN31 ======================================================= */ + #define R_MFWD_FWPMGDCN31_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN31_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN0 ======================================================= */ + #define R_MFWD_FWPMYDCN0_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN0_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN1 ======================================================= */ + #define R_MFWD_FWPMYDCN1_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN1_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN2 ======================================================= */ + #define R_MFWD_FWPMYDCN2_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN2_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN3 ======================================================= */ + #define R_MFWD_FWPMYDCN3_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN3_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN4 ======================================================= */ + #define R_MFWD_FWPMYDCN4_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN4_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN5 ======================================================= */ + #define R_MFWD_FWPMYDCN5_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN5_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN6 ======================================================= */ + #define R_MFWD_FWPMYDCN6_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN6_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN7 ======================================================= */ + #define R_MFWD_FWPMYDCN7_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN7_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN0 ======================================================= */ + #define R_MFWD_FWPMRDCN0_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN0_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN1 ======================================================= */ + #define R_MFWD_FWPMRDCN1_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN1_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN2 ======================================================= */ + #define R_MFWD_FWPMRDCN2_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN2_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN3 ======================================================= */ + #define R_MFWD_FWPMRDCN3_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN3_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN4 ======================================================= */ + #define R_MFWD_FWPMRDCN4_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN4_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN5 ======================================================= */ + #define R_MFWD_FWPMRDCN5_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN5_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN6 ======================================================= */ + #define R_MFWD_FWPMRDCN6_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN6_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN7 ======================================================= */ + #define R_MFWD_FWPMRDCN7_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN7_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN8 ======================================================= */ + #define R_MFWD_FWPMRDCN8_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN8_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN9 ======================================================= */ + #define R_MFWD_FWPMRDCN9_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN9_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN10 ======================================================= */ + #define R_MFWD_FWPMRDCN10_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN10_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN11 ======================================================= */ + #define R_MFWD_FWPMRDCN11_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN11_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN12 ======================================================= */ + #define R_MFWD_FWPMRDCN12_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN12_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN13 ======================================================= */ + #define R_MFWD_FWPMRDCN13_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN13_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN14 ======================================================= */ + #define R_MFWD_FWPMRDCN14_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN14_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN15 ======================================================= */ + #define R_MFWD_FWPMRDCN15_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN15_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN16 ======================================================= */ + #define R_MFWD_FWPMRDCN16_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN16_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN17 ======================================================= */ + #define R_MFWD_FWPMRDCN17_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN17_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN18 ======================================================= */ + #define R_MFWD_FWPMRDCN18_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN18_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN19 ======================================================= */ + #define R_MFWD_FWPMRDCN19_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN19_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN20 ======================================================= */ + #define R_MFWD_FWPMRDCN20_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN20_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN21 ======================================================= */ + #define R_MFWD_FWPMRDCN21_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN21_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN22 ======================================================= */ + #define R_MFWD_FWPMRDCN22_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN22_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN23 ======================================================= */ + #define R_MFWD_FWPMRDCN23_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN23_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN24 ======================================================= */ + #define R_MFWD_FWPMRDCN24_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN24_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN25 ======================================================= */ + #define R_MFWD_FWPMRDCN25_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN25_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN26 ======================================================= */ + #define R_MFWD_FWPMRDCN26_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN26_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN27 ======================================================= */ + #define R_MFWD_FWPMRDCN27_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN27_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN28 ======================================================= */ + #define R_MFWD_FWPMRDCN28_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN28_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN29 ======================================================= */ + #define R_MFWD_FWPMRDCN29_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN29_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN30 ======================================================= */ + #define R_MFWD_FWPMRDCN30_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN30_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN31 ======================================================= */ + #define R_MFWD_FWPMRDCN31_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN31_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN0 ======================================================= */ + #define R_MFWD_FWFRPPCN0_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN0_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN1 ======================================================= */ + #define R_MFWD_FWFRPPCN1_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN1_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN2 ======================================================= */ + #define R_MFWD_FWFRPPCN2_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN2_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN3 ======================================================= */ + #define R_MFWD_FWFRPPCN3_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN3_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN4 ======================================================= */ + #define R_MFWD_FWFRPPCN4_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN4_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN5 ======================================================= */ + #define R_MFWD_FWFRPPCN5_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN5_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN6 ======================================================= */ + #define R_MFWD_FWFRPPCN6_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN6_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN7 ======================================================= */ + #define R_MFWD_FWFRPPCN7_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN7_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN8 ======================================================= */ + #define R_MFWD_FWFRPPCN8_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN8_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN9 ======================================================= */ + #define R_MFWD_FWFRPPCN9_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN9_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN10 ======================================================= */ + #define R_MFWD_FWFRPPCN10_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN10_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN11 ======================================================= */ + #define R_MFWD_FWFRPPCN11_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN11_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN12 ======================================================= */ + #define R_MFWD_FWFRPPCN12_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN12_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN13 ======================================================= */ + #define R_MFWD_FWFRPPCN13_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN13_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN14 ======================================================= */ + #define R_MFWD_FWFRPPCN14_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN14_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN15 ======================================================= */ + #define R_MFWD_FWFRPPCN15_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN15_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN16 ======================================================= */ + #define R_MFWD_FWFRPPCN16_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN16_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN17 ======================================================= */ + #define R_MFWD_FWFRPPCN17_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN17_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN18 ======================================================= */ + #define R_MFWD_FWFRPPCN18_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN18_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN19 ======================================================= */ + #define R_MFWD_FWFRPPCN19_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN19_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN20 ======================================================= */ + #define R_MFWD_FWFRPPCN20_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN20_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN21 ======================================================= */ + #define R_MFWD_FWFRPPCN21_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN21_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN22 ======================================================= */ + #define R_MFWD_FWFRPPCN22_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN22_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN23 ======================================================= */ + #define R_MFWD_FWFRPPCN23_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN23_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN24 ======================================================= */ + #define R_MFWD_FWFRPPCN24_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN24_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN25 ======================================================= */ + #define R_MFWD_FWFRPPCN25_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN25_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN26 ======================================================= */ + #define R_MFWD_FWFRPPCN26_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN26_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN27 ======================================================= */ + #define R_MFWD_FWFRPPCN27_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN27_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN28 ======================================================= */ + #define R_MFWD_FWFRPPCN28_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN28_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN29 ======================================================= */ + #define R_MFWD_FWFRPPCN29_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN29_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN30 ======================================================= */ + #define R_MFWD_FWFRPPCN30_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN30_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN31 ======================================================= */ + #define R_MFWD_FWFRPPCN31_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN31_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN32 ======================================================= */ + #define R_MFWD_FWFRPPCN32_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN32_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN33 ======================================================= */ + #define R_MFWD_FWFRPPCN33_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN33_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN34 ======================================================= */ + #define R_MFWD_FWFRPPCN34_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN34_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN35 ======================================================= */ + #define R_MFWD_FWFRPPCN35_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN35_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN36 ======================================================= */ + #define R_MFWD_FWFRPPCN36_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN36_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN37 ======================================================= */ + #define R_MFWD_FWFRPPCN37_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN37_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN38 ======================================================= */ + #define R_MFWD_FWFRPPCN38_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN38_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN39 ======================================================= */ + #define R_MFWD_FWFRPPCN39_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN39_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN40 ======================================================= */ + #define R_MFWD_FWFRPPCN40_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN40_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN41 ======================================================= */ + #define R_MFWD_FWFRPPCN41_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN41_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN42 ======================================================= */ + #define R_MFWD_FWFRPPCN42_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN42_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN43 ======================================================= */ + #define R_MFWD_FWFRPPCN43_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN43_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN44 ======================================================= */ + #define R_MFWD_FWFRPPCN44_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN44_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN45 ======================================================= */ + #define R_MFWD_FWFRPPCN45_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN45_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN46 ======================================================= */ + #define R_MFWD_FWFRPPCN46_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN46_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN47 ======================================================= */ + #define R_MFWD_FWFRPPCN47_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN47_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN48 ======================================================= */ + #define R_MFWD_FWFRPPCN48_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN48_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN49 ======================================================= */ + #define R_MFWD_FWFRPPCN49_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN49_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN50 ======================================================= */ + #define R_MFWD_FWFRPPCN50_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN50_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN51 ======================================================= */ + #define R_MFWD_FWFRPPCN51_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN51_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN52 ======================================================= */ + #define R_MFWD_FWFRPPCN52_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN52_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN53 ======================================================= */ + #define R_MFWD_FWFRPPCN53_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN53_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN54 ======================================================= */ + #define R_MFWD_FWFRPPCN54_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN54_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN55 ======================================================= */ + #define R_MFWD_FWFRPPCN55_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN55_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN56 ======================================================= */ + #define R_MFWD_FWFRPPCN56_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN56_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN57 ======================================================= */ + #define R_MFWD_FWFRPPCN57_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN57_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN58 ======================================================= */ + #define R_MFWD_FWFRPPCN58_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN58_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN59 ======================================================= */ + #define R_MFWD_FWFRPPCN59_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN59_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN60 ======================================================= */ + #define R_MFWD_FWFRPPCN60_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN60_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN61 ======================================================= */ + #define R_MFWD_FWFRPPCN61_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN61_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN62 ======================================================= */ + #define R_MFWD_FWFRPPCN62_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN62_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN63 ======================================================= */ + #define R_MFWD_FWFRPPCN63_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN63_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN64 ======================================================= */ + #define R_MFWD_FWFRPPCN64_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN64_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN65 ======================================================= */ + #define R_MFWD_FWFRPPCN65_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN65_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN66 ======================================================= */ + #define R_MFWD_FWFRPPCN66_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN66_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN67 ======================================================= */ + #define R_MFWD_FWFRPPCN67_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN67_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN68 ======================================================= */ + #define R_MFWD_FWFRPPCN68_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN68_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN69 ======================================================= */ + #define R_MFWD_FWFRPPCN69_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN69_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN70 ======================================================= */ + #define R_MFWD_FWFRPPCN70_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN70_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN71 ======================================================= */ + #define R_MFWD_FWFRPPCN71_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN71_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN72 ======================================================= */ + #define R_MFWD_FWFRPPCN72_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN72_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN73 ======================================================= */ + #define R_MFWD_FWFRPPCN73_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN73_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN74 ======================================================= */ + #define R_MFWD_FWFRPPCN74_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN74_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN75 ======================================================= */ + #define R_MFWD_FWFRPPCN75_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN75_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN76 ======================================================= */ + #define R_MFWD_FWFRPPCN76_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN76_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN77 ======================================================= */ + #define R_MFWD_FWFRPPCN77_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN77_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN78 ======================================================= */ + #define R_MFWD_FWFRPPCN78_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN78_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN79 ======================================================= */ + #define R_MFWD_FWFRPPCN79_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN79_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN80 ======================================================= */ + #define R_MFWD_FWFRPPCN80_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN80_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN81 ======================================================= */ + #define R_MFWD_FWFRPPCN81_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN81_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN82 ======================================================= */ + #define R_MFWD_FWFRPPCN82_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN82_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN83 ======================================================= */ + #define R_MFWD_FWFRPPCN83_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN83_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN84 ======================================================= */ + #define R_MFWD_FWFRPPCN84_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN84_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN85 ======================================================= */ + #define R_MFWD_FWFRPPCN85_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN85_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN86 ======================================================= */ + #define R_MFWD_FWFRPPCN86_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN86_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN87 ======================================================= */ + #define R_MFWD_FWFRPPCN87_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN87_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN88 ======================================================= */ + #define R_MFWD_FWFRPPCN88_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN88_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN89 ======================================================= */ + #define R_MFWD_FWFRPPCN89_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN89_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN90 ======================================================= */ + #define R_MFWD_FWFRPPCN90_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN90_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN91 ======================================================= */ + #define R_MFWD_FWFRPPCN91_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN91_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN92 ======================================================= */ + #define R_MFWD_FWFRPPCN92_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN92_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN93 ======================================================= */ + #define R_MFWD_FWFRPPCN93_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN93_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN94 ======================================================= */ + #define R_MFWD_FWFRPPCN94_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN94_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN95 ======================================================= */ + #define R_MFWD_FWFRPPCN95_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN95_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN96 ======================================================= */ + #define R_MFWD_FWFRPPCN96_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN96_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN97 ======================================================= */ + #define R_MFWD_FWFRPPCN97_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN97_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN98 ======================================================= */ + #define R_MFWD_FWFRPPCN98_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN98_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN99 ======================================================= */ + #define R_MFWD_FWFRPPCN99_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN99_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN100 ====================================================== */ + #define R_MFWD_FWFRPPCN100_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN100_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN101 ====================================================== */ + #define R_MFWD_FWFRPPCN101_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN101_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN102 ====================================================== */ + #define R_MFWD_FWFRPPCN102_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN102_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN103 ====================================================== */ + #define R_MFWD_FWFRPPCN103_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN103_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN104 ====================================================== */ + #define R_MFWD_FWFRPPCN104_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN104_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN105 ====================================================== */ + #define R_MFWD_FWFRPPCN105_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN105_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN106 ====================================================== */ + #define R_MFWD_FWFRPPCN106_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN106_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN107 ====================================================== */ + #define R_MFWD_FWFRPPCN107_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN107_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN108 ====================================================== */ + #define R_MFWD_FWFRPPCN108_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN108_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN109 ====================================================== */ + #define R_MFWD_FWFRPPCN109_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN109_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN110 ====================================================== */ + #define R_MFWD_FWFRPPCN110_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN110_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN111 ====================================================== */ + #define R_MFWD_FWFRPPCN111_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN111_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN112 ====================================================== */ + #define R_MFWD_FWFRPPCN112_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN112_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN113 ====================================================== */ + #define R_MFWD_FWFRPPCN113_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN113_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN114 ====================================================== */ + #define R_MFWD_FWFRPPCN114_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN114_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN115 ====================================================== */ + #define R_MFWD_FWFRPPCN115_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN115_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN116 ====================================================== */ + #define R_MFWD_FWFRPPCN116_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN116_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN117 ====================================================== */ + #define R_MFWD_FWFRPPCN117_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN117_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN118 ====================================================== */ + #define R_MFWD_FWFRPPCN118_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN118_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN119 ====================================================== */ + #define R_MFWD_FWFRPPCN119_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN119_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN120 ====================================================== */ + #define R_MFWD_FWFRPPCN120_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN120_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN121 ====================================================== */ + #define R_MFWD_FWFRPPCN121_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN121_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN122 ====================================================== */ + #define R_MFWD_FWFRPPCN122_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN122_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN123 ====================================================== */ + #define R_MFWD_FWFRPPCN123_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN123_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN124 ====================================================== */ + #define R_MFWD_FWFRPPCN124_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN124_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN125 ====================================================== */ + #define R_MFWD_FWFRPPCN125_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN125_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN126 ====================================================== */ + #define R_MFWD_FWFRPPCN126_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN126_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN127 ====================================================== */ + #define R_MFWD_FWFRPPCN127_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN127_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN0 ======================================================= */ + #define R_MFWD_FWFRDPCN0_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN0_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN1 ======================================================= */ + #define R_MFWD_FWFRDPCN1_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN1_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN2 ======================================================= */ + #define R_MFWD_FWFRDPCN2_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN2_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN3 ======================================================= */ + #define R_MFWD_FWFRDPCN3_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN3_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN4 ======================================================= */ + #define R_MFWD_FWFRDPCN4_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN4_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN5 ======================================================= */ + #define R_MFWD_FWFRDPCN5_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN5_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN6 ======================================================= */ + #define R_MFWD_FWFRDPCN6_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN6_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN7 ======================================================= */ + #define R_MFWD_FWFRDPCN7_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN7_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN8 ======================================================= */ + #define R_MFWD_FWFRDPCN8_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN8_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN9 ======================================================= */ + #define R_MFWD_FWFRDPCN9_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN9_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN10 ======================================================= */ + #define R_MFWD_FWFRDPCN10_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN10_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN11 ======================================================= */ + #define R_MFWD_FWFRDPCN11_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN11_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN12 ======================================================= */ + #define R_MFWD_FWFRDPCN12_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN12_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN13 ======================================================= */ + #define R_MFWD_FWFRDPCN13_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN13_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN14 ======================================================= */ + #define R_MFWD_FWFRDPCN14_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN14_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN15 ======================================================= */ + #define R_MFWD_FWFRDPCN15_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN15_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN16 ======================================================= */ + #define R_MFWD_FWFRDPCN16_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN16_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN17 ======================================================= */ + #define R_MFWD_FWFRDPCN17_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN17_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN18 ======================================================= */ + #define R_MFWD_FWFRDPCN18_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN18_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN19 ======================================================= */ + #define R_MFWD_FWFRDPCN19_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN19_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN20 ======================================================= */ + #define R_MFWD_FWFRDPCN20_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN20_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN21 ======================================================= */ + #define R_MFWD_FWFRDPCN21_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN21_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN22 ======================================================= */ + #define R_MFWD_FWFRDPCN22_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN22_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN23 ======================================================= */ + #define R_MFWD_FWFRDPCN23_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN23_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN24 ======================================================= */ + #define R_MFWD_FWFRDPCN24_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN24_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN25 ======================================================= */ + #define R_MFWD_FWFRDPCN25_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN25_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN26 ======================================================= */ + #define R_MFWD_FWFRDPCN26_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN26_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN27 ======================================================= */ + #define R_MFWD_FWFRDPCN27_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN27_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN28 ======================================================= */ + #define R_MFWD_FWFRDPCN28_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN28_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN29 ======================================================= */ + #define R_MFWD_FWFRDPCN29_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN29_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN30 ======================================================= */ + #define R_MFWD_FWFRDPCN30_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN30_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN31 ======================================================= */ + #define R_MFWD_FWFRDPCN31_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN31_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN32 ======================================================= */ + #define R_MFWD_FWFRDPCN32_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN32_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN33 ======================================================= */ + #define R_MFWD_FWFRDPCN33_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN33_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN34 ======================================================= */ + #define R_MFWD_FWFRDPCN34_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN34_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN35 ======================================================= */ + #define R_MFWD_FWFRDPCN35_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN35_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN36 ======================================================= */ + #define R_MFWD_FWFRDPCN36_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN36_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN37 ======================================================= */ + #define R_MFWD_FWFRDPCN37_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN37_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN38 ======================================================= */ + #define R_MFWD_FWFRDPCN38_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN38_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN39 ======================================================= */ + #define R_MFWD_FWFRDPCN39_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN39_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN40 ======================================================= */ + #define R_MFWD_FWFRDPCN40_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN40_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN41 ======================================================= */ + #define R_MFWD_FWFRDPCN41_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN41_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN42 ======================================================= */ + #define R_MFWD_FWFRDPCN42_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN42_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN43 ======================================================= */ + #define R_MFWD_FWFRDPCN43_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN43_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN44 ======================================================= */ + #define R_MFWD_FWFRDPCN44_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN44_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN45 ======================================================= */ + #define R_MFWD_FWFRDPCN45_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN45_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN46 ======================================================= */ + #define R_MFWD_FWFRDPCN46_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN46_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN47 ======================================================= */ + #define R_MFWD_FWFRDPCN47_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN47_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN48 ======================================================= */ + #define R_MFWD_FWFRDPCN48_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN48_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN49 ======================================================= */ + #define R_MFWD_FWFRDPCN49_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN49_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN50 ======================================================= */ + #define R_MFWD_FWFRDPCN50_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN50_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN51 ======================================================= */ + #define R_MFWD_FWFRDPCN51_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN51_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN52 ======================================================= */ + #define R_MFWD_FWFRDPCN52_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN52_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN53 ======================================================= */ + #define R_MFWD_FWFRDPCN53_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN53_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN54 ======================================================= */ + #define R_MFWD_FWFRDPCN54_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN54_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN55 ======================================================= */ + #define R_MFWD_FWFRDPCN55_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN55_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN56 ======================================================= */ + #define R_MFWD_FWFRDPCN56_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN56_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN57 ======================================================= */ + #define R_MFWD_FWFRDPCN57_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN57_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN58 ======================================================= */ + #define R_MFWD_FWFRDPCN58_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN58_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN59 ======================================================= */ + #define R_MFWD_FWFRDPCN59_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN59_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN60 ======================================================= */ + #define R_MFWD_FWFRDPCN60_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN60_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN61 ======================================================= */ + #define R_MFWD_FWFRDPCN61_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN61_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN62 ======================================================= */ + #define R_MFWD_FWFRDPCN62_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN62_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN63 ======================================================= */ + #define R_MFWD_FWFRDPCN63_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN63_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN64 ======================================================= */ + #define R_MFWD_FWFRDPCN64_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN64_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN65 ======================================================= */ + #define R_MFWD_FWFRDPCN65_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN65_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN66 ======================================================= */ + #define R_MFWD_FWFRDPCN66_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN66_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN67 ======================================================= */ + #define R_MFWD_FWFRDPCN67_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN67_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN68 ======================================================= */ + #define R_MFWD_FWFRDPCN68_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN68_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN69 ======================================================= */ + #define R_MFWD_FWFRDPCN69_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN69_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN70 ======================================================= */ + #define R_MFWD_FWFRDPCN70_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN70_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN71 ======================================================= */ + #define R_MFWD_FWFRDPCN71_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN71_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN72 ======================================================= */ + #define R_MFWD_FWFRDPCN72_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN72_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN73 ======================================================= */ + #define R_MFWD_FWFRDPCN73_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN73_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN74 ======================================================= */ + #define R_MFWD_FWFRDPCN74_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN74_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN75 ======================================================= */ + #define R_MFWD_FWFRDPCN75_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN75_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN76 ======================================================= */ + #define R_MFWD_FWFRDPCN76_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN76_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN77 ======================================================= */ + #define R_MFWD_FWFRDPCN77_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN77_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN78 ======================================================= */ + #define R_MFWD_FWFRDPCN78_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN78_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN79 ======================================================= */ + #define R_MFWD_FWFRDPCN79_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN79_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN80 ======================================================= */ + #define R_MFWD_FWFRDPCN80_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN80_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN81 ======================================================= */ + #define R_MFWD_FWFRDPCN81_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN81_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN82 ======================================================= */ + #define R_MFWD_FWFRDPCN82_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN82_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN83 ======================================================= */ + #define R_MFWD_FWFRDPCN83_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN83_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN84 ======================================================= */ + #define R_MFWD_FWFRDPCN84_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN84_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN85 ======================================================= */ + #define R_MFWD_FWFRDPCN85_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN85_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN86 ======================================================= */ + #define R_MFWD_FWFRDPCN86_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN86_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN87 ======================================================= */ + #define R_MFWD_FWFRDPCN87_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN87_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN88 ======================================================= */ + #define R_MFWD_FWFRDPCN88_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN88_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN89 ======================================================= */ + #define R_MFWD_FWFRDPCN89_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN89_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN90 ======================================================= */ + #define R_MFWD_FWFRDPCN90_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN90_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN91 ======================================================= */ + #define R_MFWD_FWFRDPCN91_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN91_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN92 ======================================================= */ + #define R_MFWD_FWFRDPCN92_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN92_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN93 ======================================================= */ + #define R_MFWD_FWFRDPCN93_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN93_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN94 ======================================================= */ + #define R_MFWD_FWFRDPCN94_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN94_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN95 ======================================================= */ + #define R_MFWD_FWFRDPCN95_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN95_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN96 ======================================================= */ + #define R_MFWD_FWFRDPCN96_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN96_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN97 ======================================================= */ + #define R_MFWD_FWFRDPCN97_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN97_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN98 ======================================================= */ + #define R_MFWD_FWFRDPCN98_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN98_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN99 ======================================================= */ + #define R_MFWD_FWFRDPCN99_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN99_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN100 ====================================================== */ + #define R_MFWD_FWFRDPCN100_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN100_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN101 ====================================================== */ + #define R_MFWD_FWFRDPCN101_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN101_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN102 ====================================================== */ + #define R_MFWD_FWFRDPCN102_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN102_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN103 ====================================================== */ + #define R_MFWD_FWFRDPCN103_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN103_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN104 ====================================================== */ + #define R_MFWD_FWFRDPCN104_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN104_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN105 ====================================================== */ + #define R_MFWD_FWFRDPCN105_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN105_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN106 ====================================================== */ + #define R_MFWD_FWFRDPCN106_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN106_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN107 ====================================================== */ + #define R_MFWD_FWFRDPCN107_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN107_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN108 ====================================================== */ + #define R_MFWD_FWFRDPCN108_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN108_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN109 ====================================================== */ + #define R_MFWD_FWFRDPCN109_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN109_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN110 ====================================================== */ + #define R_MFWD_FWFRDPCN110_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN110_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN111 ====================================================== */ + #define R_MFWD_FWFRDPCN111_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN111_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN112 ====================================================== */ + #define R_MFWD_FWFRDPCN112_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN112_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN113 ====================================================== */ + #define R_MFWD_FWFRDPCN113_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN113_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN114 ====================================================== */ + #define R_MFWD_FWFRDPCN114_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN114_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN115 ====================================================== */ + #define R_MFWD_FWFRDPCN115_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN115_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN116 ====================================================== */ + #define R_MFWD_FWFRDPCN116_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN116_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN117 ====================================================== */ + #define R_MFWD_FWFRDPCN117_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN117_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN118 ====================================================== */ + #define R_MFWD_FWFRDPCN118_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN118_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN119 ====================================================== */ + #define R_MFWD_FWFRDPCN119_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN119_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN120 ====================================================== */ + #define R_MFWD_FWFRDPCN120_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN120_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN121 ====================================================== */ + #define R_MFWD_FWFRDPCN121_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN121_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN122 ====================================================== */ + #define R_MFWD_FWFRDPCN122_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN122_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN123 ====================================================== */ + #define R_MFWD_FWFRDPCN123_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN123_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN124 ====================================================== */ + #define R_MFWD_FWFRDPCN124_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN124_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN125 ====================================================== */ + #define R_MFWD_FWFRDPCN125_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN125_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN126 ====================================================== */ + #define R_MFWD_FWFRDPCN126_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN126_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN127 ====================================================== */ + #define R_MFWD_FWFRDPCN127_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN127_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWEIS00 ======================================================== */ + #define R_MFWD_FWEIS00_LTHSPFS_Pos (0UL) /*!< LTHSPFS (Bit 0) */ + #define R_MFWD_FWEIS00_LTHSPFS_Msk (0x1UL) /*!< LTHSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTHNTFS_Pos (2UL) /*!< LTHNTFS (Bit 2) */ + #define R_MFWD_FWEIS00_LTHNTFS_Msk (0x4UL) /*!< LTHNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTHUFS_Pos (3UL) /*!< LTHUFS (Bit 3) */ + #define R_MFWD_FWEIS00_LTHUFS_Msk (0x8UL) /*!< LTHUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTWDSPFS_Pos (10UL) /*!< LTWDSPFS (Bit 10) */ + #define R_MFWD_FWEIS00_LTWDSPFS_Msk (0x400UL) /*!< LTWDSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTWSSPFS_Pos (11UL) /*!< LTWSSPFS (Bit 11) */ + #define R_MFWD_FWEIS00_LTWSSPFS_Msk (0x800UL) /*!< LTWSSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTWVSPFS_Pos (12UL) /*!< LTWVSPFS (Bit 12) */ + #define R_MFWD_FWEIS00_LTWVSPFS_Msk (0x1000UL) /*!< LTWVSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTWNTFS_Pos (13UL) /*!< LTWNTFS (Bit 13) */ + #define R_MFWD_FWEIS00_LTWNTFS_Msk (0x2000UL) /*!< LTWNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTWSUFS_Pos (14UL) /*!< LTWSUFS (Bit 14) */ + #define R_MFWD_FWEIS00_LTWSUFS_Msk (0x4000UL) /*!< LTWSUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTWDUFS_Pos (15UL) /*!< LTWDUFS (Bit 15) */ + #define R_MFWD_FWEIS00_LTWDUFS_Msk (0x8000UL) /*!< LTWDUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTWVUFS_Pos (16UL) /*!< LTWVUFS (Bit 16) */ + #define R_MFWD_FWEIS00_LTWVUFS_Msk (0x10000UL) /*!< LTWVUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_PBNTFS_Pos (17UL) /*!< PBNTFS (Bit 17) */ + #define R_MFWD_FWEIS00_PBNTFS_Msk (0x20000UL) /*!< PBNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_SMHLFS_Pos (18UL) /*!< SMHLFS (Bit 18) */ + #define R_MFWD_FWEIS00_SMHLFS_Msk (0x40000UL) /*!< SMHLFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_SMHMFS_Pos (19UL) /*!< SMHMFS (Bit 19) */ + #define R_MFWD_FWEIS00_SMHMFS_Msk (0x80000UL) /*!< SMHMFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_WMCFS_Pos (22UL) /*!< WMCFS (Bit 22) */ + #define R_MFWD_FWEIS00_WMCFS_Msk (0x400000UL) /*!< WMCFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_WMFFS_Pos (23UL) /*!< WMFFS (Bit 23) */ + #define R_MFWD_FWEIS00_WMFFS_Msk (0x800000UL) /*!< WMFFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_WMISFS_Pos (24UL) /*!< WMISFS (Bit 24) */ + #define R_MFWD_FWEIS00_WMISFS_Msk (0x1000000UL) /*!< WMISFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_WMIUFS_Pos (25UL) /*!< WMIUFS (Bit 25) */ + #define R_MFWD_FWEIS00_WMIUFS_Msk (0x2000000UL) /*!< WMIUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_DDES_Pos (26UL) /*!< DDES (Bit 26) */ + #define R_MFWD_FWEIS00_DDES_Msk (0x4000000UL) /*!< DDES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_DDSES_Pos (28UL) /*!< DDSES (Bit 28) */ + #define R_MFWD_FWEIS00_DDSES_Msk (0x10000000UL) /*!< DDSES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_DDNTFS_Pos (29UL) /*!< DDNTFS (Bit 29) */ + #define R_MFWD_FWEIS00_DDNTFS_Msk (0x20000000UL) /*!< DDNTFS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIS01 ======================================================== */ + #define R_MFWD_FWEIS01_LTHSPFS_Pos (0UL) /*!< LTHSPFS (Bit 0) */ + #define R_MFWD_FWEIS01_LTHSPFS_Msk (0x1UL) /*!< LTHSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTHNTFS_Pos (2UL) /*!< LTHNTFS (Bit 2) */ + #define R_MFWD_FWEIS01_LTHNTFS_Msk (0x4UL) /*!< LTHNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTHUFS_Pos (3UL) /*!< LTHUFS (Bit 3) */ + #define R_MFWD_FWEIS01_LTHUFS_Msk (0x8UL) /*!< LTHUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTWDSPFS_Pos (10UL) /*!< LTWDSPFS (Bit 10) */ + #define R_MFWD_FWEIS01_LTWDSPFS_Msk (0x400UL) /*!< LTWDSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTWSSPFS_Pos (11UL) /*!< LTWSSPFS (Bit 11) */ + #define R_MFWD_FWEIS01_LTWSSPFS_Msk (0x800UL) /*!< LTWSSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTWVSPFS_Pos (12UL) /*!< LTWVSPFS (Bit 12) */ + #define R_MFWD_FWEIS01_LTWVSPFS_Msk (0x1000UL) /*!< LTWVSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTWNTFS_Pos (13UL) /*!< LTWNTFS (Bit 13) */ + #define R_MFWD_FWEIS01_LTWNTFS_Msk (0x2000UL) /*!< LTWNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTWSUFS_Pos (14UL) /*!< LTWSUFS (Bit 14) */ + #define R_MFWD_FWEIS01_LTWSUFS_Msk (0x4000UL) /*!< LTWSUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTWDUFS_Pos (15UL) /*!< LTWDUFS (Bit 15) */ + #define R_MFWD_FWEIS01_LTWDUFS_Msk (0x8000UL) /*!< LTWDUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTWVUFS_Pos (16UL) /*!< LTWVUFS (Bit 16) */ + #define R_MFWD_FWEIS01_LTWVUFS_Msk (0x10000UL) /*!< LTWVUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_PBNTFS_Pos (17UL) /*!< PBNTFS (Bit 17) */ + #define R_MFWD_FWEIS01_PBNTFS_Msk (0x20000UL) /*!< PBNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_SMHLFS_Pos (18UL) /*!< SMHLFS (Bit 18) */ + #define R_MFWD_FWEIS01_SMHLFS_Msk (0x40000UL) /*!< SMHLFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_SMHMFS_Pos (19UL) /*!< SMHMFS (Bit 19) */ + #define R_MFWD_FWEIS01_SMHMFS_Msk (0x80000UL) /*!< SMHMFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_WMCFS_Pos (22UL) /*!< WMCFS (Bit 22) */ + #define R_MFWD_FWEIS01_WMCFS_Msk (0x400000UL) /*!< WMCFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_WMFFS_Pos (23UL) /*!< WMFFS (Bit 23) */ + #define R_MFWD_FWEIS01_WMFFS_Msk (0x800000UL) /*!< WMFFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_WMISFS_Pos (24UL) /*!< WMISFS (Bit 24) */ + #define R_MFWD_FWEIS01_WMISFS_Msk (0x1000000UL) /*!< WMISFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_WMIUFS_Pos (25UL) /*!< WMIUFS (Bit 25) */ + #define R_MFWD_FWEIS01_WMIUFS_Msk (0x2000000UL) /*!< WMIUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_DDES_Pos (26UL) /*!< DDES (Bit 26) */ + #define R_MFWD_FWEIS01_DDES_Msk (0x4000000UL) /*!< DDES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_DDSES_Pos (28UL) /*!< DDSES (Bit 28) */ + #define R_MFWD_FWEIS01_DDSES_Msk (0x10000000UL) /*!< DDSES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_DDNTFS_Pos (29UL) /*!< DDNTFS (Bit 29) */ + #define R_MFWD_FWEIS01_DDNTFS_Msk (0x20000000UL) /*!< DDNTFS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIS02 ======================================================== */ + #define R_MFWD_FWEIS02_LTHSPFS_Pos (0UL) /*!< LTHSPFS (Bit 0) */ + #define R_MFWD_FWEIS02_LTHSPFS_Msk (0x1UL) /*!< LTHSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTHNTFS_Pos (2UL) /*!< LTHNTFS (Bit 2) */ + #define R_MFWD_FWEIS02_LTHNTFS_Msk (0x4UL) /*!< LTHNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTHUFS_Pos (3UL) /*!< LTHUFS (Bit 3) */ + #define R_MFWD_FWEIS02_LTHUFS_Msk (0x8UL) /*!< LTHUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTWDSPFS_Pos (10UL) /*!< LTWDSPFS (Bit 10) */ + #define R_MFWD_FWEIS02_LTWDSPFS_Msk (0x400UL) /*!< LTWDSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTWSSPFS_Pos (11UL) /*!< LTWSSPFS (Bit 11) */ + #define R_MFWD_FWEIS02_LTWSSPFS_Msk (0x800UL) /*!< LTWSSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTWVSPFS_Pos (12UL) /*!< LTWVSPFS (Bit 12) */ + #define R_MFWD_FWEIS02_LTWVSPFS_Msk (0x1000UL) /*!< LTWVSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTWNTFS_Pos (13UL) /*!< LTWNTFS (Bit 13) */ + #define R_MFWD_FWEIS02_LTWNTFS_Msk (0x2000UL) /*!< LTWNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTWSUFS_Pos (14UL) /*!< LTWSUFS (Bit 14) */ + #define R_MFWD_FWEIS02_LTWSUFS_Msk (0x4000UL) /*!< LTWSUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTWDUFS_Pos (15UL) /*!< LTWDUFS (Bit 15) */ + #define R_MFWD_FWEIS02_LTWDUFS_Msk (0x8000UL) /*!< LTWDUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTWVUFS_Pos (16UL) /*!< LTWVUFS (Bit 16) */ + #define R_MFWD_FWEIS02_LTWVUFS_Msk (0x10000UL) /*!< LTWVUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_PBNTFS_Pos (17UL) /*!< PBNTFS (Bit 17) */ + #define R_MFWD_FWEIS02_PBNTFS_Msk (0x20000UL) /*!< PBNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_SMHLFS_Pos (18UL) /*!< SMHLFS (Bit 18) */ + #define R_MFWD_FWEIS02_SMHLFS_Msk (0x40000UL) /*!< SMHLFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_SMHMFS_Pos (19UL) /*!< SMHMFS (Bit 19) */ + #define R_MFWD_FWEIS02_SMHMFS_Msk (0x80000UL) /*!< SMHMFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_WMCFS_Pos (22UL) /*!< WMCFS (Bit 22) */ + #define R_MFWD_FWEIS02_WMCFS_Msk (0x400000UL) /*!< WMCFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_WMFFS_Pos (23UL) /*!< WMFFS (Bit 23) */ + #define R_MFWD_FWEIS02_WMFFS_Msk (0x800000UL) /*!< WMFFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_WMISFS_Pos (24UL) /*!< WMISFS (Bit 24) */ + #define R_MFWD_FWEIS02_WMISFS_Msk (0x1000000UL) /*!< WMISFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_WMIUFS_Pos (25UL) /*!< WMIUFS (Bit 25) */ + #define R_MFWD_FWEIS02_WMIUFS_Msk (0x2000000UL) /*!< WMIUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_DDES_Pos (26UL) /*!< DDES (Bit 26) */ + #define R_MFWD_FWEIS02_DDES_Msk (0x4000000UL) /*!< DDES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_DDSES_Pos (28UL) /*!< DDSES (Bit 28) */ + #define R_MFWD_FWEIS02_DDSES_Msk (0x10000000UL) /*!< DDSES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_DDNTFS_Pos (29UL) /*!< DDNTFS (Bit 29) */ + #define R_MFWD_FWEIS02_DDNTFS_Msk (0x20000000UL) /*!< DDNTFS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIE00 ======================================================== */ + #define R_MFWD_FWEIE00_LTHSPFE_Pos (0UL) /*!< LTHSPFE (Bit 0) */ + #define R_MFWD_FWEIE00_LTHSPFE_Msk (0x1UL) /*!< LTHSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTHNTFE_Pos (2UL) /*!< LTHNTFE (Bit 2) */ + #define R_MFWD_FWEIE00_LTHNTFE_Msk (0x4UL) /*!< LTHNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTHUFE_Pos (3UL) /*!< LTHUFE (Bit 3) */ + #define R_MFWD_FWEIE00_LTHUFE_Msk (0x8UL) /*!< LTHUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTWDSPFE_Pos (10UL) /*!< LTWDSPFE (Bit 10) */ + #define R_MFWD_FWEIE00_LTWDSPFE_Msk (0x400UL) /*!< LTWDSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTWSSPFE_Pos (11UL) /*!< LTWSSPFE (Bit 11) */ + #define R_MFWD_FWEIE00_LTWSSPFE_Msk (0x800UL) /*!< LTWSSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTWVSPFE_Pos (12UL) /*!< LTWVSPFE (Bit 12) */ + #define R_MFWD_FWEIE00_LTWVSPFE_Msk (0x1000UL) /*!< LTWVSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTWNTFE_Pos (13UL) /*!< LTWNTFE (Bit 13) */ + #define R_MFWD_FWEIE00_LTWNTFE_Msk (0x2000UL) /*!< LTWNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTWSUFE_Pos (14UL) /*!< LTWSUFE (Bit 14) */ + #define R_MFWD_FWEIE00_LTWSUFE_Msk (0x4000UL) /*!< LTWSUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTWDUFE_Pos (15UL) /*!< LTWDUFE (Bit 15) */ + #define R_MFWD_FWEIE00_LTWDUFE_Msk (0x8000UL) /*!< LTWDUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTWVUFE_Pos (16UL) /*!< LTWVUFE (Bit 16) */ + #define R_MFWD_FWEIE00_LTWVUFE_Msk (0x10000UL) /*!< LTWVUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_PBNTFE_Pos (17UL) /*!< PBNTFE (Bit 17) */ + #define R_MFWD_FWEIE00_PBNTFE_Msk (0x20000UL) /*!< PBNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_SMHLFE_Pos (18UL) /*!< SMHLFE (Bit 18) */ + #define R_MFWD_FWEIE00_SMHLFE_Msk (0x40000UL) /*!< SMHLFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_SMHMFE_Pos (19UL) /*!< SMHMFE (Bit 19) */ + #define R_MFWD_FWEIE00_SMHMFE_Msk (0x80000UL) /*!< SMHMFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_WMCFE_Pos (22UL) /*!< WMCFE (Bit 22) */ + #define R_MFWD_FWEIE00_WMCFE_Msk (0x400000UL) /*!< WMCFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_WMFFE_Pos (23UL) /*!< WMFFE (Bit 23) */ + #define R_MFWD_FWEIE00_WMFFE_Msk (0x800000UL) /*!< WMFFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_WMISFE_Pos (24UL) /*!< WMISFE (Bit 24) */ + #define R_MFWD_FWEIE00_WMISFE_Msk (0x1000000UL) /*!< WMISFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_WMIUFE_Pos (25UL) /*!< WMIUFE (Bit 25) */ + #define R_MFWD_FWEIE00_WMIUFE_Msk (0x2000000UL) /*!< WMIUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_DDEE_Pos (26UL) /*!< DDEE (Bit 26) */ + #define R_MFWD_FWEIE00_DDEE_Msk (0x4000000UL) /*!< DDEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_DDFEE_Pos (27UL) /*!< DDFEE (Bit 27) */ + #define R_MFWD_FWEIE00_DDFEE_Msk (0x8000000UL) /*!< DDFEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_DDSEE_Pos (28UL) /*!< DDSEE (Bit 28) */ + #define R_MFWD_FWEIE00_DDSEE_Msk (0x10000000UL) /*!< DDSEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_DDNTFE_Pos (29UL) /*!< DDNTFE (Bit 29) */ + #define R_MFWD_FWEIE00_DDNTFE_Msk (0x20000000UL) /*!< DDNTFE (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIE01 ======================================================== */ + #define R_MFWD_FWEIE01_LTHSPFE_Pos (0UL) /*!< LTHSPFE (Bit 0) */ + #define R_MFWD_FWEIE01_LTHSPFE_Msk (0x1UL) /*!< LTHSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTHNTFE_Pos (2UL) /*!< LTHNTFE (Bit 2) */ + #define R_MFWD_FWEIE01_LTHNTFE_Msk (0x4UL) /*!< LTHNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTHUFE_Pos (3UL) /*!< LTHUFE (Bit 3) */ + #define R_MFWD_FWEIE01_LTHUFE_Msk (0x8UL) /*!< LTHUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTWDSPFE_Pos (10UL) /*!< LTWDSPFE (Bit 10) */ + #define R_MFWD_FWEIE01_LTWDSPFE_Msk (0x400UL) /*!< LTWDSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTWSSPFE_Pos (11UL) /*!< LTWSSPFE (Bit 11) */ + #define R_MFWD_FWEIE01_LTWSSPFE_Msk (0x800UL) /*!< LTWSSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTWVSPFE_Pos (12UL) /*!< LTWVSPFE (Bit 12) */ + #define R_MFWD_FWEIE01_LTWVSPFE_Msk (0x1000UL) /*!< LTWVSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTWNTFE_Pos (13UL) /*!< LTWNTFE (Bit 13) */ + #define R_MFWD_FWEIE01_LTWNTFE_Msk (0x2000UL) /*!< LTWNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTWSUFE_Pos (14UL) /*!< LTWSUFE (Bit 14) */ + #define R_MFWD_FWEIE01_LTWSUFE_Msk (0x4000UL) /*!< LTWSUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTWDUFE_Pos (15UL) /*!< LTWDUFE (Bit 15) */ + #define R_MFWD_FWEIE01_LTWDUFE_Msk (0x8000UL) /*!< LTWDUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTWVUFE_Pos (16UL) /*!< LTWVUFE (Bit 16) */ + #define R_MFWD_FWEIE01_LTWVUFE_Msk (0x10000UL) /*!< LTWVUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_PBNTFE_Pos (17UL) /*!< PBNTFE (Bit 17) */ + #define R_MFWD_FWEIE01_PBNTFE_Msk (0x20000UL) /*!< PBNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_SMHLFE_Pos (18UL) /*!< SMHLFE (Bit 18) */ + #define R_MFWD_FWEIE01_SMHLFE_Msk (0x40000UL) /*!< SMHLFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_SMHMFE_Pos (19UL) /*!< SMHMFE (Bit 19) */ + #define R_MFWD_FWEIE01_SMHMFE_Msk (0x80000UL) /*!< SMHMFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_WMCFE_Pos (22UL) /*!< WMCFE (Bit 22) */ + #define R_MFWD_FWEIE01_WMCFE_Msk (0x400000UL) /*!< WMCFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_WMFFE_Pos (23UL) /*!< WMFFE (Bit 23) */ + #define R_MFWD_FWEIE01_WMFFE_Msk (0x800000UL) /*!< WMFFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_WMISFE_Pos (24UL) /*!< WMISFE (Bit 24) */ + #define R_MFWD_FWEIE01_WMISFE_Msk (0x1000000UL) /*!< WMISFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_WMIUFE_Pos (25UL) /*!< WMIUFE (Bit 25) */ + #define R_MFWD_FWEIE01_WMIUFE_Msk (0x2000000UL) /*!< WMIUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_DDEE_Pos (26UL) /*!< DDEE (Bit 26) */ + #define R_MFWD_FWEIE01_DDEE_Msk (0x4000000UL) /*!< DDEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_DDFEE_Pos (27UL) /*!< DDFEE (Bit 27) */ + #define R_MFWD_FWEIE01_DDFEE_Msk (0x8000000UL) /*!< DDFEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_DDSEE_Pos (28UL) /*!< DDSEE (Bit 28) */ + #define R_MFWD_FWEIE01_DDSEE_Msk (0x10000000UL) /*!< DDSEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_DDNTFE_Pos (29UL) /*!< DDNTFE (Bit 29) */ + #define R_MFWD_FWEIE01_DDNTFE_Msk (0x20000000UL) /*!< DDNTFE (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIE02 ======================================================== */ + #define R_MFWD_FWEIE02_LTHSPFE_Pos (0UL) /*!< LTHSPFE (Bit 0) */ + #define R_MFWD_FWEIE02_LTHSPFE_Msk (0x1UL) /*!< LTHSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTHNTFE_Pos (2UL) /*!< LTHNTFE (Bit 2) */ + #define R_MFWD_FWEIE02_LTHNTFE_Msk (0x4UL) /*!< LTHNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTHUFE_Pos (3UL) /*!< LTHUFE (Bit 3) */ + #define R_MFWD_FWEIE02_LTHUFE_Msk (0x8UL) /*!< LTHUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTWDSPFE_Pos (10UL) /*!< LTWDSPFE (Bit 10) */ + #define R_MFWD_FWEIE02_LTWDSPFE_Msk (0x400UL) /*!< LTWDSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTWSSPFE_Pos (11UL) /*!< LTWSSPFE (Bit 11) */ + #define R_MFWD_FWEIE02_LTWSSPFE_Msk (0x800UL) /*!< LTWSSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTWVSPFE_Pos (12UL) /*!< LTWVSPFE (Bit 12) */ + #define R_MFWD_FWEIE02_LTWVSPFE_Msk (0x1000UL) /*!< LTWVSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTWNTFE_Pos (13UL) /*!< LTWNTFE (Bit 13) */ + #define R_MFWD_FWEIE02_LTWNTFE_Msk (0x2000UL) /*!< LTWNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTWSUFE_Pos (14UL) /*!< LTWSUFE (Bit 14) */ + #define R_MFWD_FWEIE02_LTWSUFE_Msk (0x4000UL) /*!< LTWSUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTWDUFE_Pos (15UL) /*!< LTWDUFE (Bit 15) */ + #define R_MFWD_FWEIE02_LTWDUFE_Msk (0x8000UL) /*!< LTWDUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTWVUFE_Pos (16UL) /*!< LTWVUFE (Bit 16) */ + #define R_MFWD_FWEIE02_LTWVUFE_Msk (0x10000UL) /*!< LTWVUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_PBNTFE_Pos (17UL) /*!< PBNTFE (Bit 17) */ + #define R_MFWD_FWEIE02_PBNTFE_Msk (0x20000UL) /*!< PBNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_SMHLFE_Pos (18UL) /*!< SMHLFE (Bit 18) */ + #define R_MFWD_FWEIE02_SMHLFE_Msk (0x40000UL) /*!< SMHLFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_SMHMFE_Pos (19UL) /*!< SMHMFE (Bit 19) */ + #define R_MFWD_FWEIE02_SMHMFE_Msk (0x80000UL) /*!< SMHMFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_WMCFE_Pos (22UL) /*!< WMCFE (Bit 22) */ + #define R_MFWD_FWEIE02_WMCFE_Msk (0x400000UL) /*!< WMCFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_WMFFE_Pos (23UL) /*!< WMFFE (Bit 23) */ + #define R_MFWD_FWEIE02_WMFFE_Msk (0x800000UL) /*!< WMFFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_WMISFE_Pos (24UL) /*!< WMISFE (Bit 24) */ + #define R_MFWD_FWEIE02_WMISFE_Msk (0x1000000UL) /*!< WMISFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_WMIUFE_Pos (25UL) /*!< WMIUFE (Bit 25) */ + #define R_MFWD_FWEIE02_WMIUFE_Msk (0x2000000UL) /*!< WMIUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_DDEE_Pos (26UL) /*!< DDEE (Bit 26) */ + #define R_MFWD_FWEIE02_DDEE_Msk (0x4000000UL) /*!< DDEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_DDFEE_Pos (27UL) /*!< DDFEE (Bit 27) */ + #define R_MFWD_FWEIE02_DDFEE_Msk (0x8000000UL) /*!< DDFEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_DDSEE_Pos (28UL) /*!< DDSEE (Bit 28) */ + #define R_MFWD_FWEIE02_DDSEE_Msk (0x10000000UL) /*!< DDSEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_DDNTFE_Pos (29UL) /*!< DDNTFE (Bit 29) */ + #define R_MFWD_FWEIE02_DDNTFE_Msk (0x20000000UL) /*!< DDNTFE (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEID00 ======================================================== */ + #define R_MFWD_FWEID00_LTHSPFD_Pos (0UL) /*!< LTHSPFD (Bit 0) */ + #define R_MFWD_FWEID00_LTHSPFD_Msk (0x1UL) /*!< LTHSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTHNTFD_Pos (2UL) /*!< LTHNTFD (Bit 2) */ + #define R_MFWD_FWEID00_LTHNTFD_Msk (0x4UL) /*!< LTHNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTHUFD_Pos (3UL) /*!< LTHUFD (Bit 3) */ + #define R_MFWD_FWEID00_LTHUFD_Msk (0x8UL) /*!< LTHUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTWDSPFD_Pos (10UL) /*!< LTWDSPFD (Bit 10) */ + #define R_MFWD_FWEID00_LTWDSPFD_Msk (0x400UL) /*!< LTWDSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTWSSPFD_Pos (11UL) /*!< LTWSSPFD (Bit 11) */ + #define R_MFWD_FWEID00_LTWSSPFD_Msk (0x800UL) /*!< LTWSSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTWVSPFD_Pos (12UL) /*!< LTWVSPFD (Bit 12) */ + #define R_MFWD_FWEID00_LTWVSPFD_Msk (0x1000UL) /*!< LTWVSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTWNTFD_Pos (13UL) /*!< LTWNTFD (Bit 13) */ + #define R_MFWD_FWEID00_LTWNTFD_Msk (0x2000UL) /*!< LTWNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTWSUFD_Pos (14UL) /*!< LTWSUFD (Bit 14) */ + #define R_MFWD_FWEID00_LTWSUFD_Msk (0x4000UL) /*!< LTWSUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTWDUFD_Pos (15UL) /*!< LTWDUFD (Bit 15) */ + #define R_MFWD_FWEID00_LTWDUFD_Msk (0x8000UL) /*!< LTWDUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTWVUFD_Pos (16UL) /*!< LTWVUFD (Bit 16) */ + #define R_MFWD_FWEID00_LTWVUFD_Msk (0x10000UL) /*!< LTWVUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_PBNTFD_Pos (17UL) /*!< PBNTFD (Bit 17) */ + #define R_MFWD_FWEID00_PBNTFD_Msk (0x20000UL) /*!< PBNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_SMHLFD_Pos (18UL) /*!< SMHLFD (Bit 18) */ + #define R_MFWD_FWEID00_SMHLFD_Msk (0x40000UL) /*!< SMHLFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_SMHMFD_Pos (19UL) /*!< SMHMFD (Bit 19) */ + #define R_MFWD_FWEID00_SMHMFD_Msk (0x80000UL) /*!< SMHMFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_WMCFD_Pos (22UL) /*!< WMCFD (Bit 22) */ + #define R_MFWD_FWEID00_WMCFD_Msk (0x400000UL) /*!< WMCFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_WMFFD_Pos (23UL) /*!< WMFFD (Bit 23) */ + #define R_MFWD_FWEID00_WMFFD_Msk (0x800000UL) /*!< WMFFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_WMISFD_Pos (24UL) /*!< WMISFD (Bit 24) */ + #define R_MFWD_FWEID00_WMISFD_Msk (0x1000000UL) /*!< WMISFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_WMIUFD_Pos (25UL) /*!< WMIUFD (Bit 25) */ + #define R_MFWD_FWEID00_WMIUFD_Msk (0x2000000UL) /*!< WMIUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_DDED_Pos (26UL) /*!< DDED (Bit 26) */ + #define R_MFWD_FWEID00_DDED_Msk (0x4000000UL) /*!< DDED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_DDFED_Pos (27UL) /*!< DDFED (Bit 27) */ + #define R_MFWD_FWEID00_DDFED_Msk (0x8000000UL) /*!< DDFED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_DDSED_Pos (28UL) /*!< DDSED (Bit 28) */ + #define R_MFWD_FWEID00_DDSED_Msk (0x10000000UL) /*!< DDSED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_DDNTFD_Pos (29UL) /*!< DDNTFD (Bit 29) */ + #define R_MFWD_FWEID00_DDNTFD_Msk (0x20000000UL) /*!< DDNTFD (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEID01 ======================================================== */ + #define R_MFWD_FWEID01_LTHSPFD_Pos (0UL) /*!< LTHSPFD (Bit 0) */ + #define R_MFWD_FWEID01_LTHSPFD_Msk (0x1UL) /*!< LTHSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTHNTFD_Pos (2UL) /*!< LTHNTFD (Bit 2) */ + #define R_MFWD_FWEID01_LTHNTFD_Msk (0x4UL) /*!< LTHNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTHUFD_Pos (3UL) /*!< LTHUFD (Bit 3) */ + #define R_MFWD_FWEID01_LTHUFD_Msk (0x8UL) /*!< LTHUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTWDSPFD_Pos (10UL) /*!< LTWDSPFD (Bit 10) */ + #define R_MFWD_FWEID01_LTWDSPFD_Msk (0x400UL) /*!< LTWDSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTWSSPFD_Pos (11UL) /*!< LTWSSPFD (Bit 11) */ + #define R_MFWD_FWEID01_LTWSSPFD_Msk (0x800UL) /*!< LTWSSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTWVSPFD_Pos (12UL) /*!< LTWVSPFD (Bit 12) */ + #define R_MFWD_FWEID01_LTWVSPFD_Msk (0x1000UL) /*!< LTWVSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTWNTFD_Pos (13UL) /*!< LTWNTFD (Bit 13) */ + #define R_MFWD_FWEID01_LTWNTFD_Msk (0x2000UL) /*!< LTWNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTWSUFD_Pos (14UL) /*!< LTWSUFD (Bit 14) */ + #define R_MFWD_FWEID01_LTWSUFD_Msk (0x4000UL) /*!< LTWSUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTWDUFD_Pos (15UL) /*!< LTWDUFD (Bit 15) */ + #define R_MFWD_FWEID01_LTWDUFD_Msk (0x8000UL) /*!< LTWDUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTWVUFD_Pos (16UL) /*!< LTWVUFD (Bit 16) */ + #define R_MFWD_FWEID01_LTWVUFD_Msk (0x10000UL) /*!< LTWVUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_PBNTFD_Pos (17UL) /*!< PBNTFD (Bit 17) */ + #define R_MFWD_FWEID01_PBNTFD_Msk (0x20000UL) /*!< PBNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_SMHLFD_Pos (18UL) /*!< SMHLFD (Bit 18) */ + #define R_MFWD_FWEID01_SMHLFD_Msk (0x40000UL) /*!< SMHLFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_SMHMFD_Pos (19UL) /*!< SMHMFD (Bit 19) */ + #define R_MFWD_FWEID01_SMHMFD_Msk (0x80000UL) /*!< SMHMFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_WMCFD_Pos (22UL) /*!< WMCFD (Bit 22) */ + #define R_MFWD_FWEID01_WMCFD_Msk (0x400000UL) /*!< WMCFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_WMFFD_Pos (23UL) /*!< WMFFD (Bit 23) */ + #define R_MFWD_FWEID01_WMFFD_Msk (0x800000UL) /*!< WMFFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_WMISFD_Pos (24UL) /*!< WMISFD (Bit 24) */ + #define R_MFWD_FWEID01_WMISFD_Msk (0x1000000UL) /*!< WMISFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_WMIUFD_Pos (25UL) /*!< WMIUFD (Bit 25) */ + #define R_MFWD_FWEID01_WMIUFD_Msk (0x2000000UL) /*!< WMIUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_DDED_Pos (26UL) /*!< DDED (Bit 26) */ + #define R_MFWD_FWEID01_DDED_Msk (0x4000000UL) /*!< DDED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_DDFED_Pos (27UL) /*!< DDFED (Bit 27) */ + #define R_MFWD_FWEID01_DDFED_Msk (0x8000000UL) /*!< DDFED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_DDSED_Pos (28UL) /*!< DDSED (Bit 28) */ + #define R_MFWD_FWEID01_DDSED_Msk (0x10000000UL) /*!< DDSED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_DDNTFD_Pos (29UL) /*!< DDNTFD (Bit 29) */ + #define R_MFWD_FWEID01_DDNTFD_Msk (0x20000000UL) /*!< DDNTFD (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEID02 ======================================================== */ + #define R_MFWD_FWEID02_LTHSPFD_Pos (0UL) /*!< LTHSPFD (Bit 0) */ + #define R_MFWD_FWEID02_LTHSPFD_Msk (0x1UL) /*!< LTHSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTHNTFD_Pos (2UL) /*!< LTHNTFD (Bit 2) */ + #define R_MFWD_FWEID02_LTHNTFD_Msk (0x4UL) /*!< LTHNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTHUFD_Pos (3UL) /*!< LTHUFD (Bit 3) */ + #define R_MFWD_FWEID02_LTHUFD_Msk (0x8UL) /*!< LTHUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTWDSPFD_Pos (10UL) /*!< LTWDSPFD (Bit 10) */ + #define R_MFWD_FWEID02_LTWDSPFD_Msk (0x400UL) /*!< LTWDSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTWSSPFD_Pos (11UL) /*!< LTWSSPFD (Bit 11) */ + #define R_MFWD_FWEID02_LTWSSPFD_Msk (0x800UL) /*!< LTWSSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTWVSPFD_Pos (12UL) /*!< LTWVSPFD (Bit 12) */ + #define R_MFWD_FWEID02_LTWVSPFD_Msk (0x1000UL) /*!< LTWVSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTWNTFD_Pos (13UL) /*!< LTWNTFD (Bit 13) */ + #define R_MFWD_FWEID02_LTWNTFD_Msk (0x2000UL) /*!< LTWNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTWSUFD_Pos (14UL) /*!< LTWSUFD (Bit 14) */ + #define R_MFWD_FWEID02_LTWSUFD_Msk (0x4000UL) /*!< LTWSUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTWDUFD_Pos (15UL) /*!< LTWDUFD (Bit 15) */ + #define R_MFWD_FWEID02_LTWDUFD_Msk (0x8000UL) /*!< LTWDUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTWVUFD_Pos (16UL) /*!< LTWVUFD (Bit 16) */ + #define R_MFWD_FWEID02_LTWVUFD_Msk (0x10000UL) /*!< LTWVUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_PBNTFD_Pos (17UL) /*!< PBNTFD (Bit 17) */ + #define R_MFWD_FWEID02_PBNTFD_Msk (0x20000UL) /*!< PBNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_SMHLFD_Pos (18UL) /*!< SMHLFD (Bit 18) */ + #define R_MFWD_FWEID02_SMHLFD_Msk (0x40000UL) /*!< SMHLFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_SMHMFD_Pos (19UL) /*!< SMHMFD (Bit 19) */ + #define R_MFWD_FWEID02_SMHMFD_Msk (0x80000UL) /*!< SMHMFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_WMCFD_Pos (22UL) /*!< WMCFD (Bit 22) */ + #define R_MFWD_FWEID02_WMCFD_Msk (0x400000UL) /*!< WMCFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_WMFFD_Pos (23UL) /*!< WMFFD (Bit 23) */ + #define R_MFWD_FWEID02_WMFFD_Msk (0x800000UL) /*!< WMFFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_WMISFD_Pos (24UL) /*!< WMISFD (Bit 24) */ + #define R_MFWD_FWEID02_WMISFD_Msk (0x1000000UL) /*!< WMISFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_WMIUFD_Pos (25UL) /*!< WMIUFD (Bit 25) */ + #define R_MFWD_FWEID02_WMIUFD_Msk (0x2000000UL) /*!< WMIUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_DDED_Pos (26UL) /*!< DDED (Bit 26) */ + #define R_MFWD_FWEID02_DDED_Msk (0x4000000UL) /*!< DDED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_DDFED_Pos (27UL) /*!< DDFED (Bit 27) */ + #define R_MFWD_FWEID02_DDFED_Msk (0x8000000UL) /*!< DDFED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_DDSED_Pos (28UL) /*!< DDSED (Bit 28) */ + #define R_MFWD_FWEID02_DDSED_Msk (0x10000000UL) /*!< DDSED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_DDNTFD_Pos (29UL) /*!< DDNTFD (Bit 29) */ + #define R_MFWD_FWEID02_DDNTFD_Msk (0x20000000UL) /*!< DDNTFD (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIS1 ========================================================= */ + #define R_MFWD_FWEIS1_LTHTEES_Pos (0UL) /*!< LTHTEES (Bit 0) */ + #define R_MFWD_FWEIS1_LTHTEES_Msk (0x1UL) /*!< LTHTEES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS1_LTHTSES_Pos (1UL) /*!< LTHTSES (Bit 1) */ + #define R_MFWD_FWEIS1_LTHTSES_Msk (0x2UL) /*!< LTHTSES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS1_MACTEES_Pos (4UL) /*!< MACTEES (Bit 4) */ + #define R_MFWD_FWEIS1_MACTEES_Msk (0x10UL) /*!< MACTEES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS1_MACTSES_Pos (5UL) /*!< MACTSES (Bit 5) */ + #define R_MFWD_FWEIS1_MACTSES_Msk (0x20UL) /*!< MACTSES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS1_VLANTEES_Pos (6UL) /*!< VLANTEES (Bit 6) */ + #define R_MFWD_FWEIS1_VLANTEES_Msk (0x40UL) /*!< VLANTEES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS1_VLANTSES_Pos (7UL) /*!< VLANTSES (Bit 7) */ + #define R_MFWD_FWEIS1_VLANTSES_Msk (0x80UL) /*!< VLANTSES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS1_L23UEES_Pos (8UL) /*!< L23UEES (Bit 8) */ + #define R_MFWD_FWEIS1_L23UEES_Msk (0x100UL) /*!< L23UEES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS1_AREES_Pos (16UL) /*!< AREES (Bit 16) */ + #define R_MFWD_FWEIS1_AREES_Msk (0x10000UL) /*!< AREES (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIE1 ========================================================= */ + #define R_MFWD_FWEIE1_LTHTEEE_Pos (0UL) /*!< LTHTEEE (Bit 0) */ + #define R_MFWD_FWEIE1_LTHTEEE_Msk (0x1UL) /*!< LTHTEEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE1_LTHTSEE_Pos (1UL) /*!< LTHTSEE (Bit 1) */ + #define R_MFWD_FWEIE1_LTHTSEE_Msk (0x2UL) /*!< LTHTSEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE1_MACTEEE_Pos (4UL) /*!< MACTEEE (Bit 4) */ + #define R_MFWD_FWEIE1_MACTEEE_Msk (0x10UL) /*!< MACTEEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE1_MACTSEE_Pos (5UL) /*!< MACTSEE (Bit 5) */ + #define R_MFWD_FWEIE1_MACTSEE_Msk (0x20UL) /*!< MACTSEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE1_VLANTEEE_Pos (6UL) /*!< VLANTEEE (Bit 6) */ + #define R_MFWD_FWEIE1_VLANTEEE_Msk (0x40UL) /*!< VLANTEEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE1_VLANTSEE_Pos (7UL) /*!< VLANTSEE (Bit 7) */ + #define R_MFWD_FWEIE1_VLANTSEE_Msk (0x80UL) /*!< VLANTSEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE1_L23UEEE_Pos (8UL) /*!< L23UEEE (Bit 8) */ + #define R_MFWD_FWEIE1_L23UEEE_Msk (0x100UL) /*!< L23UEEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE1_AREEE_Pos (16UL) /*!< AREEE (Bit 16) */ + #define R_MFWD_FWEIE1_AREEE_Msk (0x10000UL) /*!< AREEE (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEID1 ========================================================= */ + #define R_MFWD_FWEID1_LTHTEED_Pos (0UL) /*!< LTHTEED (Bit 0) */ + #define R_MFWD_FWEID1_LTHTEED_Msk (0x1UL) /*!< LTHTEED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID1_LTHTSED_Pos (1UL) /*!< LTHTSED (Bit 1) */ + #define R_MFWD_FWEID1_LTHTSED_Msk (0x2UL) /*!< LTHTSED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID1_MACTEED_Pos (4UL) /*!< MACTEED (Bit 4) */ + #define R_MFWD_FWEID1_MACTEED_Msk (0x10UL) /*!< MACTEED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID1_MACTSED_Pos (5UL) /*!< MACTSED (Bit 5) */ + #define R_MFWD_FWEID1_MACTSED_Msk (0x20UL) /*!< MACTSED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID1_VLANTEED_Pos (6UL) /*!< VLANTEED (Bit 6) */ + #define R_MFWD_FWEID1_VLANTEED_Msk (0x40UL) /*!< VLANTEED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID1_VLANTSED_Pos (7UL) /*!< VLANTSED (Bit 7) */ + #define R_MFWD_FWEID1_VLANTSED_Msk (0x80UL) /*!< VLANTSED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID1_L23UEED_Pos (8UL) /*!< L23UEED (Bit 8) */ + #define R_MFWD_FWEID1_L23UEED_Msk (0x100UL) /*!< L23UEED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID1_AREED_Pos (16UL) /*!< AREED (Bit 16) */ + #define R_MFWD_FWEID1_AREED_Msk (0x10000UL) /*!< AREED (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIS2 ========================================================= */ + #define R_MFWD_FWEIS2_PMFS_Pos (0UL) /*!< PMFS (Bit 0) */ + #define R_MFWD_FWEIS2_PMFS_Msk (0xffffUL) /*!< PMFS (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWEIE2 ========================================================= */ + #define R_MFWD_FWEIE2_PMFE_Pos (0UL) /*!< PMFE (Bit 0) */ + #define R_MFWD_FWEIE2_PMFE_Msk (0xffffUL) /*!< PMFE (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWEID2 ========================================================= */ + #define R_MFWD_FWEID2_PMFD_Pos (0UL) /*!< PMFD (Bit 0) */ + #define R_MFWD_FWEID2_PMFD_Msk (0xffffUL) /*!< PMFD (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWEIS5 ========================================================= */ + #define R_MFWD_FWEIS5_PMRFS_Pos (0UL) /*!< PMRFS (Bit 0) */ + #define R_MFWD_FWEIS5_PMRFS_Msk (0xffffffffUL) /*!< PMRFS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE5 ========================================================= */ + #define R_MFWD_FWEIE5_PMRFE_Pos (0UL) /*!< PMRFE (Bit 0) */ + #define R_MFWD_FWEIE5_PMRFE_Msk (0xffffffffUL) /*!< PMRFE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID5 ========================================================= */ + #define R_MFWD_FWEID5_PMRFD_Pos (0UL) /*!< PMRFD (Bit 0) */ + #define R_MFWD_FWEID5_PMRFD_Msk (0xffffffffUL) /*!< PMRFD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS60 ======================================================== */ + #define R_MFWD_FWEIS60_FFS_Pos (0UL) /*!< FFS (Bit 0) */ + #define R_MFWD_FWEIS60_FFS_Msk (0xffffffffUL) /*!< FFS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS61 ======================================================== */ + #define R_MFWD_FWEIS61_FFS_Pos (0UL) /*!< FFS (Bit 0) */ + #define R_MFWD_FWEIS61_FFS_Msk (0xffffffffUL) /*!< FFS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS62 ======================================================== */ + #define R_MFWD_FWEIS62_FFS_Pos (0UL) /*!< FFS (Bit 0) */ + #define R_MFWD_FWEIS62_FFS_Msk (0xffffffffUL) /*!< FFS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS63 ======================================================== */ + #define R_MFWD_FWEIS63_FFS_Pos (0UL) /*!< FFS (Bit 0) */ + #define R_MFWD_FWEIS63_FFS_Msk (0xffffffffUL) /*!< FFS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE60 ======================================================== */ + #define R_MFWD_FWEIE60_FFE_Pos (0UL) /*!< FFE (Bit 0) */ + #define R_MFWD_FWEIE60_FFE_Msk (0xffffffffUL) /*!< FFE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE61 ======================================================== */ + #define R_MFWD_FWEIE61_FFE_Pos (0UL) /*!< FFE (Bit 0) */ + #define R_MFWD_FWEIE61_FFE_Msk (0xffffffffUL) /*!< FFE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE62 ======================================================== */ + #define R_MFWD_FWEIE62_FFE_Pos (0UL) /*!< FFE (Bit 0) */ + #define R_MFWD_FWEIE62_FFE_Msk (0xffffffffUL) /*!< FFE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE63 ======================================================== */ + #define R_MFWD_FWEIE63_FFE_Pos (0UL) /*!< FFE (Bit 0) */ + #define R_MFWD_FWEIE63_FFE_Msk (0xffffffffUL) /*!< FFE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID60 ======================================================== */ + #define R_MFWD_FWEID60_FFD_Pos (0UL) /*!< FFD (Bit 0) */ + #define R_MFWD_FWEID60_FFD_Msk (0xffffffffUL) /*!< FFD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID61 ======================================================== */ + #define R_MFWD_FWEID61_FFD_Pos (0UL) /*!< FFD (Bit 0) */ + #define R_MFWD_FWEID61_FFD_Msk (0xffffffffUL) /*!< FFD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID62 ======================================================== */ + #define R_MFWD_FWEID62_FFD_Pos (0UL) /*!< FFD (Bit 0) */ + #define R_MFWD_FWEID62_FFD_Msk (0xffffffffUL) /*!< FFD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID63 ======================================================== */ + #define R_MFWD_FWEID63_FFD_Pos (0UL) /*!< FFD (Bit 0) */ + #define R_MFWD_FWEID63_FFD_Msk (0xffffffffUL) /*!< FFD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS70 ======================================================== */ + #define R_MFWD_FWEIS70_FOORS_Pos (0UL) /*!< FOORS (Bit 0) */ + #define R_MFWD_FWEIS70_FOORS_Msk (0xffffffffUL) /*!< FOORS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS71 ======================================================== */ + #define R_MFWD_FWEIS71_FOORS_Pos (0UL) /*!< FOORS (Bit 0) */ + #define R_MFWD_FWEIS71_FOORS_Msk (0xffffffffUL) /*!< FOORS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS72 ======================================================== */ + #define R_MFWD_FWEIS72_FOORS_Pos (0UL) /*!< FOORS (Bit 0) */ + #define R_MFWD_FWEIS72_FOORS_Msk (0xffffffffUL) /*!< FOORS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS73 ======================================================== */ + #define R_MFWD_FWEIS73_FOORS_Pos (0UL) /*!< FOORS (Bit 0) */ + #define R_MFWD_FWEIS73_FOORS_Msk (0xffffffffUL) /*!< FOORS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE70 ======================================================== */ + #define R_MFWD_FWEIE70_FOORE_Pos (0UL) /*!< FOORE (Bit 0) */ + #define R_MFWD_FWEIE70_FOORE_Msk (0xffffffffUL) /*!< FOORE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE71 ======================================================== */ + #define R_MFWD_FWEIE71_FOORE_Pos (0UL) /*!< FOORE (Bit 0) */ + #define R_MFWD_FWEIE71_FOORE_Msk (0xffffffffUL) /*!< FOORE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE72 ======================================================== */ + #define R_MFWD_FWEIE72_FOORE_Pos (0UL) /*!< FOORE (Bit 0) */ + #define R_MFWD_FWEIE72_FOORE_Msk (0xffffffffUL) /*!< FOORE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE73 ======================================================== */ + #define R_MFWD_FWEIE73_FOORE_Pos (0UL) /*!< FOORE (Bit 0) */ + #define R_MFWD_FWEIE73_FOORE_Msk (0xffffffffUL) /*!< FOORE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID70 ======================================================== */ + #define R_MFWD_FWEID70_FOORD_Pos (0UL) /*!< FOORD (Bit 0) */ + #define R_MFWD_FWEID70_FOORD_Msk (0xffffffffUL) /*!< FOORD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID71 ======================================================== */ + #define R_MFWD_FWEID71_FOORD_Pos (0UL) /*!< FOORD (Bit 0) */ + #define R_MFWD_FWEID71_FOORD_Msk (0xffffffffUL) /*!< FOORD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID72 ======================================================== */ + #define R_MFWD_FWEID72_FOORD_Pos (0UL) /*!< FOORD (Bit 0) */ + #define R_MFWD_FWEID72_FOORD_Msk (0xffffffffUL) /*!< FOORD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID73 ======================================================== */ + #define R_MFWD_FWEID73_FOORD_Pos (0UL) /*!< FOORD (Bit 0) */ + #define R_MFWD_FWEID73_FOORD_Msk (0xffffffffUL) /*!< FOORD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS80 ======================================================== */ + #define R_MFWD_FWEIS80_TOS_Pos (0UL) /*!< TOS (Bit 0) */ + #define R_MFWD_FWEIS80_TOS_Msk (0xffffffffUL) /*!< TOS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS81 ======================================================== */ + #define R_MFWD_FWEIS81_TOS_Pos (0UL) /*!< TOS (Bit 0) */ + #define R_MFWD_FWEIS81_TOS_Msk (0xffffffffUL) /*!< TOS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS82 ======================================================== */ + #define R_MFWD_FWEIS82_TOS_Pos (0UL) /*!< TOS (Bit 0) */ + #define R_MFWD_FWEIS82_TOS_Msk (0xffffffffUL) /*!< TOS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS83 ======================================================== */ + #define R_MFWD_FWEIS83_TOS_Pos (0UL) /*!< TOS (Bit 0) */ + #define R_MFWD_FWEIS83_TOS_Msk (0xffffffffUL) /*!< TOS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE80 ======================================================== */ + #define R_MFWD_FWEIE80_TOE_Pos (0UL) /*!< TOE (Bit 0) */ + #define R_MFWD_FWEIE80_TOE_Msk (0xffffffffUL) /*!< TOE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE81 ======================================================== */ + #define R_MFWD_FWEIE81_TOE_Pos (0UL) /*!< TOE (Bit 0) */ + #define R_MFWD_FWEIE81_TOE_Msk (0xffffffffUL) /*!< TOE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE82 ======================================================== */ + #define R_MFWD_FWEIE82_TOE_Pos (0UL) /*!< TOE (Bit 0) */ + #define R_MFWD_FWEIE82_TOE_Msk (0xffffffffUL) /*!< TOE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE83 ======================================================== */ + #define R_MFWD_FWEIE83_TOE_Pos (0UL) /*!< TOE (Bit 0) */ + #define R_MFWD_FWEIE83_TOE_Msk (0xffffffffUL) /*!< TOE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID80 ======================================================== */ + #define R_MFWD_FWEID80_TOD_Pos (0UL) /*!< TOD (Bit 0) */ + #define R_MFWD_FWEID80_TOD_Msk (0xffffffffUL) /*!< TOD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID81 ======================================================== */ + #define R_MFWD_FWEID81_TOD_Pos (0UL) /*!< TOD (Bit 0) */ + #define R_MFWD_FWEID81_TOD_Msk (0xffffffffUL) /*!< TOD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID82 ======================================================== */ + #define R_MFWD_FWEID82_TOD_Pos (0UL) /*!< TOD (Bit 0) */ + #define R_MFWD_FWEID82_TOD_Msk (0xffffffffUL) /*!< TOD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID83 ======================================================== */ + #define R_MFWD_FWEID83_TOD_Pos (0UL) /*!< TOD (Bit 0) */ + #define R_MFWD_FWEID83_TOD_Msk (0xffffffffUL) /*!< TOD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWMIS0 ========================================================= */ + #define R_MFWD_FWMIS0_LTHTFS_Pos (0UL) /*!< LTHTFS (Bit 0) */ + #define R_MFWD_FWMIS0_LTHTFS_Msk (0x1UL) /*!< LTHTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMIS0_MACTFS_Pos (2UL) /*!< MACTFS (Bit 2) */ + #define R_MFWD_FWMIS0_MACTFS_Msk (0x4UL) /*!< MACTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMIS0_VLANTFS_Pos (3UL) /*!< VLANTFS (Bit 3) */ + #define R_MFWD_FWMIS0_VLANTFS_Msk (0x8UL) /*!< VLANTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMIS0_MACADAS_Pos (17UL) /*!< MACADAS (Bit 17) */ + #define R_MFWD_FWMIS0_MACADAS_Msk (0x20000UL) /*!< MACADAS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWMIE0 ========================================================= */ + #define R_MFWD_FWMIE0_LTHTFE_Pos (0UL) /*!< LTHTFE (Bit 0) */ + #define R_MFWD_FWMIE0_LTHTFE_Msk (0x1UL) /*!< LTHTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMIE0_MACTFE_Pos (2UL) /*!< MACTFE (Bit 2) */ + #define R_MFWD_FWMIE0_MACTFE_Msk (0x4UL) /*!< MACTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMIE0_VLANTFE_Pos (3UL) /*!< VLANTFE (Bit 3) */ + #define R_MFWD_FWMIE0_VLANTFE_Msk (0x8UL) /*!< VLANTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMIE0_MACADAE_Pos (17UL) /*!< MACADAE (Bit 17) */ + #define R_MFWD_FWMIE0_MACADAE_Msk (0x20000UL) /*!< MACADAE (Bitfield-Mask: 0x01) */ +/* ======================================================== FWMID0 ========================================================= */ + #define R_MFWD_FWMID0_LTHTFD_Pos (0UL) /*!< LTHTFD (Bit 0) */ + #define R_MFWD_FWMID0_LTHTFD_Msk (0x1UL) /*!< LTHTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMID0_MACTFD_Pos (2UL) /*!< MACTFD (Bit 2) */ + #define R_MFWD_FWMID0_MACTFD_Msk (0x4UL) /*!< MACTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMID0_VLANTFD_Pos (3UL) /*!< VLANTFD (Bit 3) */ + #define R_MFWD_FWMID0_VLANTFD_Msk (0x8UL) /*!< VLANTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMID0_MACADAD_Pos (17UL) /*!< MACADAD (Bit 17) */ + #define R_MFWD_FWMID0_MACADAD_Msk (0x20000UL) /*!< MACADAD (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MIPI_DSI ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ISR ========================================================== */ + #define R_MIPI_DSI_ISR_SQ0_Pos (0UL) /*!< SQ0 (Bit 0) */ + #define R_MIPI_DSI_ISR_SQ0_Msk (0x1UL) /*!< SQ0 (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ISR_SQ1_Pos (4UL) /*!< SQ1 (Bit 4) */ + #define R_MIPI_DSI_ISR_SQ1_Msk (0x10UL) /*!< SQ1 (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ISR_VM_Pos (8UL) /*!< VM (Bit 8) */ + #define R_MIPI_DSI_ISR_VM_Msk (0x100UL) /*!< VM (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ISR_RCV_Pos (12UL) /*!< RCV (Bit 12) */ + #define R_MIPI_DSI_ISR_RCV_Msk (0x1000UL) /*!< RCV (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ISR_FERR_Pos (16UL) /*!< FERR (Bit 16) */ + #define R_MIPI_DSI_ISR_FERR_Msk (0x10000UL) /*!< FERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ISR_PPI_Pos (20UL) /*!< PPI (Bit 20) */ + #define R_MIPI_DSI_ISR_PPI_Msk (0x100000UL) /*!< PPI (Bitfield-Mask: 0x01) */ +/* ======================================================== LINKSR ========================================================= */ + #define R_MIPI_DSI_LINKSR_SQ0RUN_Pos (0UL) /*!< SQ0RUN (Bit 0) */ + #define R_MIPI_DSI_LINKSR_SQ0RUN_Msk (0x1UL) /*!< SQ0RUN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_LINKSR_SQ1RUN_Pos (4UL) /*!< SQ1RUN (Bit 4) */ + #define R_MIPI_DSI_LINKSR_SQ1RUN_Msk (0x10UL) /*!< SQ1RUN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_LINKSR_VRUN_Pos (8UL) /*!< VRUN (Bit 8) */ + #define R_MIPI_DSI_LINKSR_VRUN_Msk (0x100UL) /*!< VRUN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_LINKSR_HSBUSY_Pos (12UL) /*!< HSBUSY (Bit 12) */ + #define R_MIPI_DSI_LINKSR_HSBUSY_Msk (0x1000UL) /*!< HSBUSY (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_LINKSR_LPBUSY_Pos (13UL) /*!< LPBUSY (Bit 13) */ + #define R_MIPI_DSI_LINKSR_LPBUSY_Msk (0x2000UL) /*!< LPBUSY (Bitfield-Mask: 0x01) */ +/* ======================================================== TXSETR ========================================================= */ + #define R_MIPI_DSI_TXSETR_NUMLANE_Pos (0UL) /*!< NUMLANE (Bit 0) */ + #define R_MIPI_DSI_TXSETR_NUMLANE_Msk (0x3UL) /*!< NUMLANE (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_TXSETR_CLEN_Pos (8UL) /*!< CLEN (Bit 8) */ + #define R_MIPI_DSI_TXSETR_CLEN_Msk (0x100UL) /*!< CLEN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_TXSETR_DLEN_Pos (9UL) /*!< DLEN (Bit 9) */ + #define R_MIPI_DSI_TXSETR_DLEN_Msk (0x200UL) /*!< DLEN (Bitfield-Mask: 0x01) */ +/* ======================================================= HSCLKSETR ======================================================= */ + #define R_MIPI_DSI_HSCLKSETR_HSCLST_Pos (0UL) /*!< HSCLST (Bit 0) */ + #define R_MIPI_DSI_HSCLKSETR_HSCLST_Msk (0x1UL) /*!< HSCLST (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_HSCLKSETR_HSCLMD_Pos (1UL) /*!< HSCLMD (Bit 1) */ + #define R_MIPI_DSI_HSCLKSETR_HSCLMD_Msk (0x2UL) /*!< HSCLMD (Bitfield-Mask: 0x01) */ +/* ======================================================= ULPSSETR ======================================================== */ + #define R_MIPI_DSI_ULPSSETR_WKUP_Pos (0UL) /*!< WKUP (Bit 0) */ + #define R_MIPI_DSI_ULPSSETR_WKUP_Msk (0xffUL) /*!< WKUP (Bitfield-Mask: 0xff) */ +/* ======================================================== ULPSCR ========================================================= */ + #define R_MIPI_DSI_ULPSCR_CLENT_Pos (24UL) /*!< CLENT (Bit 24) */ + #define R_MIPI_DSI_ULPSCR_CLENT_Msk (0x1000000UL) /*!< CLENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ULPSCR_CLEXIT_Pos (25UL) /*!< CLEXIT (Bit 25) */ + #define R_MIPI_DSI_ULPSCR_CLEXIT_Msk (0x2000000UL) /*!< CLEXIT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ULPSCR_DLENT_Pos (28UL) /*!< DLENT (Bit 28) */ + #define R_MIPI_DSI_ULPSCR_DLENT_Msk (0x10000000UL) /*!< DLENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ULPSCR_DLEXIT_Pos (29UL) /*!< DLEXIT (Bit 29) */ + #define R_MIPI_DSI_ULPSCR_DLEXIT_Msk (0x20000000UL) /*!< DLEXIT (Bitfield-Mask: 0x01) */ +/* ========================================================= RSTCR ========================================================= */ + #define R_MIPI_DSI_RSTCR_SWRST_Pos (0UL) /*!< SWRST (Bit 0) */ + #define R_MIPI_DSI_RSTCR_SWRST_Msk (0x1UL) /*!< SWRST (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTCR_FTXSTP_Pos (16UL) /*!< FTXSTP (Bit 16) */ + #define R_MIPI_DSI_RSTCR_FTXSTP_Msk (0x10000UL) /*!< FTXSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= RSTSR ========================================================= */ + #define R_MIPI_DSI_RSTSR_RSTHS_Pos (0UL) /*!< RSTHS (Bit 0) */ + #define R_MIPI_DSI_RSTSR_RSTHS_Msk (0x1UL) /*!< RSTHS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_RSTLP_Pos (1UL) /*!< RSTLP (Bit 1) */ + #define R_MIPI_DSI_RSTSR_RSTLP_Msk (0x2UL) /*!< RSTLP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_RSTAPB_Pos (2UL) /*!< RSTAPB (Bit 2) */ + #define R_MIPI_DSI_RSTSR_RSTAPB_Msk (0x4UL) /*!< RSTAPB (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_RSTAXI_Pos (3UL) /*!< RSTAXI (Bit 3) */ + #define R_MIPI_DSI_RSTSR_RSTAXI_Msk (0x8UL) /*!< RSTAXI (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_RSTV_Pos (4UL) /*!< RSTV (Bit 4) */ + #define R_MIPI_DSI_RSTSR_RSTV_Msk (0x10UL) /*!< RSTV (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_DL0STP_Pos (8UL) /*!< DL0STP (Bit 8) */ + #define R_MIPI_DSI_RSTSR_DL0STP_Msk (0x100UL) /*!< DL0STP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_DL1STP_Pos (9UL) /*!< DL1STP (Bit 9) */ + #define R_MIPI_DSI_RSTSR_DL1STP_Msk (0x200UL) /*!< DL1STP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_DL0DIR_Pos (15UL) /*!< DL0DIR (Bit 15) */ + #define R_MIPI_DSI_RSTSR_DL0DIR_Msk (0x8000UL) /*!< DL0DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DSISETR ======================================================== */ + #define R_MIPI_DSI_DSISETR_MRPSZ_Pos (0UL) /*!< MRPSZ (Bit 0) */ + #define R_MIPI_DSI_DSISETR_MRPSZ_Msk (0xffffUL) /*!< MRPSZ (Bitfield-Mask: 0xffff) */ + #define R_MIPI_DSI_DSISETR_ECCEN_Pos (16UL) /*!< ECCEN (Bit 16) */ + #define R_MIPI_DSI_DSISETR_ECCEN_Msk (0x10000UL) /*!< ECCEN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_VC0CRCEN_Pos (20UL) /*!< VC0CRCEN (Bit 20) */ + #define R_MIPI_DSI_DSISETR_VC0CRCEN_Msk (0x100000UL) /*!< VC0CRCEN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_VC1CRCEN_Pos (21UL) /*!< VC1CRCEN (Bit 21) */ + #define R_MIPI_DSI_DSISETR_VC1CRCEN_Msk (0x200000UL) /*!< VC1CRCEN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_VC2CRCEN_Pos (22UL) /*!< VC2CRCEN (Bit 22) */ + #define R_MIPI_DSI_DSISETR_VC2CRCEN_Msk (0x400000UL) /*!< VC2CRCEN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_VC3CRCEN_Pos (23UL) /*!< VC3CRCEN (Bit 23) */ + #define R_MIPI_DSI_DSISETR_VC3CRCEN_Msk (0x800000UL) /*!< VC3CRCEN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_SCREN_Pos (29UL) /*!< SCREN (Bit 29) */ + #define R_MIPI_DSI_DSISETR_SCREN_Msk (0x20000000UL) /*!< SCREN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_EXTEMD_Pos (30UL) /*!< EXTEMD (Bit 30) */ + #define R_MIPI_DSI_DSISETR_EXTEMD_Msk (0x40000000UL) /*!< EXTEMD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_EOTPEN_Pos (31UL) /*!< EOTPEN (Bit 31) */ + #define R_MIPI_DSI_DSISETR_EOTPEN_Msk (0x80000000UL) /*!< EOTPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== TXPPD0R ======================================================== */ + #define R_MIPI_DSI_TXPPD0R_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_TXPPD0R_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD0R_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_TXPPD0R_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD0R_DATA2_Pos (16UL) /*!< DATA2 (Bit 16) */ + #define R_MIPI_DSI_TXPPD0R_DATA2_Msk (0xff0000UL) /*!< DATA2 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD0R_DATA3_Pos (24UL) /*!< DATA3 (Bit 24) */ + #define R_MIPI_DSI_TXPPD0R_DATA3_Msk (0xff000000UL) /*!< DATA3 (Bitfield-Mask: 0xff) */ +/* ======================================================== TXPPD1R ======================================================== */ + #define R_MIPI_DSI_TXPPD1R_DATA4_Pos (0UL) /*!< DATA4 (Bit 0) */ + #define R_MIPI_DSI_TXPPD1R_DATA4_Msk (0xffUL) /*!< DATA4 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD1R_DATA5_Pos (8UL) /*!< DATA5 (Bit 8) */ + #define R_MIPI_DSI_TXPPD1R_DATA5_Msk (0xff00UL) /*!< DATA5 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD1R_DATA6_Pos (16UL) /*!< DATA6 (Bit 16) */ + #define R_MIPI_DSI_TXPPD1R_DATA6_Msk (0xff0000UL) /*!< DATA6 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD1R_DATA7_Pos (24UL) /*!< DATA7 (Bit 24) */ + #define R_MIPI_DSI_TXPPD1R_DATA7_Msk (0xff000000UL) /*!< DATA7 (Bitfield-Mask: 0xff) */ +/* ======================================================== TXPPD2R ======================================================== */ + #define R_MIPI_DSI_TXPPD2R_DATA8_Pos (0UL) /*!< DATA8 (Bit 0) */ + #define R_MIPI_DSI_TXPPD2R_DATA8_Msk (0xffUL) /*!< DATA8 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD2R_DATA9_Pos (8UL) /*!< DATA9 (Bit 8) */ + #define R_MIPI_DSI_TXPPD2R_DATA9_Msk (0xff00UL) /*!< DATA9 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD2R_DATA10_Pos (16UL) /*!< DATA10 (Bit 16) */ + #define R_MIPI_DSI_TXPPD2R_DATA10_Msk (0xff0000UL) /*!< DATA10 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD2R_DATA11_Pos (24UL) /*!< DATA11 (Bit 24) */ + #define R_MIPI_DSI_TXPPD2R_DATA11_Msk (0xff000000UL) /*!< DATA11 (Bitfield-Mask: 0xff) */ +/* ======================================================== TXPPD3R ======================================================== */ + #define R_MIPI_DSI_TXPPD3R_DATA12_Pos (0UL) /*!< DATA12 (Bit 0) */ + #define R_MIPI_DSI_TXPPD3R_DATA12_Msk (0xffUL) /*!< DATA12 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD3R_DATA13_Pos (8UL) /*!< DATA13 (Bit 8) */ + #define R_MIPI_DSI_TXPPD3R_DATA13_Msk (0xff00UL) /*!< DATA13 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD3R_DATA14_Pos (16UL) /*!< DATA14 (Bit 16) */ + #define R_MIPI_DSI_TXPPD3R_DATA14_Msk (0xff0000UL) /*!< DATA14 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD3R_DATA15_Pos (24UL) /*!< DATA15 (Bit 24) */ + #define R_MIPI_DSI_TXPPD3R_DATA15_Msk (0xff000000UL) /*!< DATA15 (Bitfield-Mask: 0xff) */ +/* ========================================================= RXSR ========================================================== */ + #define R_MIPI_DSI_RXSR_BTAREND_Pos (0UL) /*!< BTAREND (Bit 0) */ + #define R_MIPI_DSI_RXSR_BTAREND_Msk (0x1UL) /*!< BTAREND (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_LRXHTO_Pos (1UL) /*!< LRXHTO (Bit 1) */ + #define R_MIPI_DSI_RXSR_LRXHTO_Msk (0x2UL) /*!< LRXHTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_TATO_Pos (2UL) /*!< TATO (Bit 2) */ + #define R_MIPI_DSI_RXSR_TATO_Msk (0x4UL) /*!< TATO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RXRESP_Pos (8UL) /*!< RXRESP (Bit 8) */ + #define R_MIPI_DSI_RXSR_RXRESP_Msk (0x100UL) /*!< RXRESP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RXEOTP_Pos (10UL) /*!< RXEOTP (Bit 10) */ + #define R_MIPI_DSI_RXSR_RXEOTP_Msk (0x400UL) /*!< RXEOTP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RXTE_Pos (13UL) /*!< RXTE (Bit 13) */ + #define R_MIPI_DSI_RXSR_RXTE_Msk (0x2000UL) /*!< RXTE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RXACK_Pos (14UL) /*!< RXACK (Bit 14) */ + #define R_MIPI_DSI_RXSR_RXACK_Msk (0x4000UL) /*!< RXACK (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_EXTEDET_Pos (15UL) /*!< EXTEDET (Bit 15) */ + #define R_MIPI_DSI_RXSR_EXTEDET_Msk (0x8000UL) /*!< EXTEDET (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_MLFERR_Pos (16UL) /*!< MLFERR (Bit 16) */ + #define R_MIPI_DSI_RXSR_MLFERR_Msk (0x10000UL) /*!< MLFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_ECCERRM_Pos (17UL) /*!< ECCERRM (Bit 17) */ + #define R_MIPI_DSI_RXSR_ECCERRM_Msk (0x20000UL) /*!< ECCERRM (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_UNEXERR_Pos (18UL) /*!< UNEXERR (Bit 18) */ + #define R_MIPI_DSI_RXSR_UNEXERR_Msk (0x40000UL) /*!< UNEXERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_WCERR_Pos (20UL) /*!< WCERR (Bit 20) */ + #define R_MIPI_DSI_RXSR_WCERR_Msk (0x100000UL) /*!< WCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_CRCERR_Pos (21UL) /*!< CRCERR (Bit 21) */ + #define R_MIPI_DSI_RXSR_CRCERR_Msk (0x200000UL) /*!< CRCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_IBERR_Pos (22UL) /*!< IBERR (Bit 22) */ + #define R_MIPI_DSI_RXSR_IBERR_Msk (0x400000UL) /*!< IBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RXOVFERR_Pos (23UL) /*!< RXOVFERR (Bit 23) */ + #define R_MIPI_DSI_RXSR_RXOVFERR_Msk (0x800000UL) /*!< RXOVFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_PRTOERR_Pos (24UL) /*!< PRTOERR (Bit 24) */ + #define R_MIPI_DSI_RXSR_PRTOERR_Msk (0x1000000UL) /*!< PRTOERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_NORESERR_Pos (25UL) /*!< NORESERR (Bit 25) */ + #define R_MIPI_DSI_RXSR_NORESERR_Msk (0x2000000UL) /*!< NORESERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RSIZEERR_Pos (26UL) /*!< RSIZEERR (Bit 26) */ + #define R_MIPI_DSI_RXSR_RSIZEERR_Msk (0x4000000UL) /*!< RSIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_ECCERRS_Pos (28UL) /*!< ECCERRS (Bit 28) */ + #define R_MIPI_DSI_RXSR_ECCERRS_Msk (0x10000000UL) /*!< ECCERRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXSR_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ========================================================= RXSCR ========================================================= */ + #define R_MIPI_DSI_RXSCR_BTAREND_Pos (0UL) /*!< BTAREND (Bit 0) */ + #define R_MIPI_DSI_RXSCR_BTAREND_Msk (0x1UL) /*!< BTAREND (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_LRXHTO_Pos (1UL) /*!< LRXHTO (Bit 1) */ + #define R_MIPI_DSI_RXSCR_LRXHTO_Msk (0x2UL) /*!< LRXHTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_TATO_Pos (2UL) /*!< TATO (Bit 2) */ + #define R_MIPI_DSI_RXSCR_TATO_Msk (0x4UL) /*!< TATO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RXRESP_Pos (8UL) /*!< RXRESP (Bit 8) */ + #define R_MIPI_DSI_RXSCR_RXRESP_Msk (0x100UL) /*!< RXRESP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RXEOTP_Pos (10UL) /*!< RXEOTP (Bit 10) */ + #define R_MIPI_DSI_RXSCR_RXEOTP_Msk (0x400UL) /*!< RXEOTP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RXTE_Pos (13UL) /*!< RXTE (Bit 13) */ + #define R_MIPI_DSI_RXSCR_RXTE_Msk (0x2000UL) /*!< RXTE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RXACK_Pos (14UL) /*!< RXACK (Bit 14) */ + #define R_MIPI_DSI_RXSCR_RXACK_Msk (0x4000UL) /*!< RXACK (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_EXTEDET_Pos (15UL) /*!< EXTEDET (Bit 15) */ + #define R_MIPI_DSI_RXSCR_EXTEDET_Msk (0x8000UL) /*!< EXTEDET (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_MLFERR_Pos (16UL) /*!< MLFERR (Bit 16) */ + #define R_MIPI_DSI_RXSCR_MLFERR_Msk (0x10000UL) /*!< MLFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_ECCERRM_Pos (17UL) /*!< ECCERRM (Bit 17) */ + #define R_MIPI_DSI_RXSCR_ECCERRM_Msk (0x20000UL) /*!< ECCERRM (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_UNEXERR_Pos (18UL) /*!< UNEXERR (Bit 18) */ + #define R_MIPI_DSI_RXSCR_UNEXERR_Msk (0x40000UL) /*!< UNEXERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_WCERR_Pos (20UL) /*!< WCERR (Bit 20) */ + #define R_MIPI_DSI_RXSCR_WCERR_Msk (0x100000UL) /*!< WCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_CRCERR_Pos (21UL) /*!< CRCERR (Bit 21) */ + #define R_MIPI_DSI_RXSCR_CRCERR_Msk (0x200000UL) /*!< CRCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_IBERR_Pos (22UL) /*!< IBERR (Bit 22) */ + #define R_MIPI_DSI_RXSCR_IBERR_Msk (0x400000UL) /*!< IBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RXOVFERR_Pos (23UL) /*!< RXOVFERR (Bit 23) */ + #define R_MIPI_DSI_RXSCR_RXOVFERR_Msk (0x800000UL) /*!< RXOVFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_PRTOERR_Pos (24UL) /*!< PRTOERR (Bit 24) */ + #define R_MIPI_DSI_RXSCR_PRTOERR_Msk (0x1000000UL) /*!< PRTOERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_NORESERR_Pos (25UL) /*!< NORESERR (Bit 25) */ + #define R_MIPI_DSI_RXSCR_NORESERR_Msk (0x2000000UL) /*!< NORESERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RSIZEERR_Pos (26UL) /*!< RSIZEERR (Bit 26) */ + #define R_MIPI_DSI_RXSCR_RSIZEERR_Msk (0x4000000UL) /*!< RSIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_ECCERRS_Pos (28UL) /*!< ECCERRS (Bit 28) */ + #define R_MIPI_DSI_RXSCR_ECCERRS_Msk (0x10000000UL) /*!< ECCERRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXSCR_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ========================================================= RXIER ========================================================= */ + #define R_MIPI_DSI_RXIER_BTAREND_Pos (0UL) /*!< BTAREND (Bit 0) */ + #define R_MIPI_DSI_RXIER_BTAREND_Msk (0x1UL) /*!< BTAREND (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_LRXHTO_Pos (1UL) /*!< LRXHTO (Bit 1) */ + #define R_MIPI_DSI_RXIER_LRXHTO_Msk (0x2UL) /*!< LRXHTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_TATO_Pos (2UL) /*!< TATO (Bit 2) */ + #define R_MIPI_DSI_RXIER_TATO_Msk (0x4UL) /*!< TATO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RXRESP_Pos (8UL) /*!< RXRESP (Bit 8) */ + #define R_MIPI_DSI_RXIER_RXRESP_Msk (0x100UL) /*!< RXRESP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RXEOTP_Pos (10UL) /*!< RXEOTP (Bit 10) */ + #define R_MIPI_DSI_RXIER_RXEOTP_Msk (0x400UL) /*!< RXEOTP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RXTE_Pos (13UL) /*!< RXTE (Bit 13) */ + #define R_MIPI_DSI_RXIER_RXTE_Msk (0x2000UL) /*!< RXTE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RXACK_Pos (14UL) /*!< RXACK (Bit 14) */ + #define R_MIPI_DSI_RXIER_RXACK_Msk (0x4000UL) /*!< RXACK (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_EXTEDET_Pos (15UL) /*!< EXTEDET (Bit 15) */ + #define R_MIPI_DSI_RXIER_EXTEDET_Msk (0x8000UL) /*!< EXTEDET (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_MLFERR_Pos (16UL) /*!< MLFERR (Bit 16) */ + #define R_MIPI_DSI_RXIER_MLFERR_Msk (0x10000UL) /*!< MLFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_ECCERRM_Pos (17UL) /*!< ECCERRM (Bit 17) */ + #define R_MIPI_DSI_RXIER_ECCERRM_Msk (0x20000UL) /*!< ECCERRM (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_UNEXERR_Pos (18UL) /*!< UNEXERR (Bit 18) */ + #define R_MIPI_DSI_RXIER_UNEXERR_Msk (0x40000UL) /*!< UNEXERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_WCERR_Pos (20UL) /*!< WCERR (Bit 20) */ + #define R_MIPI_DSI_RXIER_WCERR_Msk (0x100000UL) /*!< WCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_CRCERR_Pos (21UL) /*!< CRCERR (Bit 21) */ + #define R_MIPI_DSI_RXIER_CRCERR_Msk (0x200000UL) /*!< CRCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_IBERR_Pos (22UL) /*!< IBERR (Bit 22) */ + #define R_MIPI_DSI_RXIER_IBERR_Msk (0x400000UL) /*!< IBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RXOVFERR_Pos (23UL) /*!< RXOVFERR (Bit 23) */ + #define R_MIPI_DSI_RXIER_RXOVFERR_Msk (0x800000UL) /*!< RXOVFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_PRTOERR_Pos (24UL) /*!< PRTOERR (Bit 24) */ + #define R_MIPI_DSI_RXIER_PRTOERR_Msk (0x1000000UL) /*!< PRTOERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_NORESERR_Pos (25UL) /*!< NORESERR (Bit 25) */ + #define R_MIPI_DSI_RXIER_NORESERR_Msk (0x2000000UL) /*!< NORESERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RSIZEERR_Pos (26UL) /*!< RSIZEERR (Bit 26) */ + #define R_MIPI_DSI_RXIER_RSIZEERR_Msk (0x4000000UL) /*!< RSIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_ECCERRS_Pos (28UL) /*!< ECCERRS (Bit 28) */ + #define R_MIPI_DSI_RXIER_ECCERRS_Msk (0x10000000UL) /*!< ECCERRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXIER_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ==================================================== PRESPTOBTASETR ===================================================== */ + #define R_MIPI_DSI_PRESPTOBTASETR_PRTBTA_Pos (0UL) /*!< PRTBTA (Bit 0) */ + #define R_MIPI_DSI_PRESPTOBTASETR_PRTBTA_Msk (0xffffffffUL) /*!< PRTBTA (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== PRESPTOLPSETR ===================================================== */ + #define R_MIPI_DSI_PRESPTOLPSETR_LPWTO_Pos (0UL) /*!< LPWTO (Bit 0) */ + #define R_MIPI_DSI_PRESPTOLPSETR_LPWTO_Msk (0xffffUL) /*!< LPWTO (Bitfield-Mask: 0xffff) */ + #define R_MIPI_DSI_PRESPTOLPSETR_LPRTO_Pos (16UL) /*!< LPRTO (Bit 16) */ + #define R_MIPI_DSI_PRESPTOLPSETR_LPRTO_Msk (0xffff0000UL) /*!< LPRTO (Bitfield-Mask: 0xffff) */ +/* ===================================================== PRESPTOHSSETR ===================================================== */ + #define R_MIPI_DSI_PRESPTOHSSETR_HSWTO_Pos (0UL) /*!< HSWTO (Bit 0) */ + #define R_MIPI_DSI_PRESPTOHSSETR_HSWTO_Msk (0xffffUL) /*!< HSWTO (Bitfield-Mask: 0xffff) */ + #define R_MIPI_DSI_PRESPTOHSSETR_HSRTO_Pos (16UL) /*!< HSRTO (Bit 16) */ + #define R_MIPI_DSI_PRESPTOHSSETR_HSRTO_Msk (0xffff0000UL) /*!< HSRTO (Bitfield-Mask: 0xffff) */ +/* ======================================================= AKEPLATIR ======================================================= */ + #define R_MIPI_DSI_AKEPLATIR_EREP_Pos (0UL) /*!< EREP (Bit 0) */ + #define R_MIPI_DSI_AKEPLATIR_EREP_Msk (0xffffUL) /*!< EREP (Bitfield-Mask: 0xffff) */ + #define R_MIPI_DSI_AKEPLATIR_VC_Pos (16UL) /*!< VC (Bit 16) */ + #define R_MIPI_DSI_AKEPLATIR_VC_Msk (0xf0000UL) /*!< VC (Bitfield-Mask: 0x0f) */ +/* ======================================================= AKEPACMSR ======================================================= */ + #define R_MIPI_DSI_AKEPACMSR_AEREP_Pos (0UL) /*!< AEREP (Bit 0) */ + #define R_MIPI_DSI_AKEPACMSR_AEREP_Msk (0xffffUL) /*!< AEREP (Bitfield-Mask: 0xffff) */ + #define R_MIPI_DSI_AKEPACMSR_AVC_Pos (16UL) /*!< AVC (Bit 16) */ + #define R_MIPI_DSI_AKEPACMSR_AVC_Msk (0xf0000UL) /*!< AVC (Bitfield-Mask: 0x0f) */ +/* ======================================================== AKEPSCR ======================================================== */ + #define R_MIPI_DSI_AKEPSCR_AEREP_Pos (0UL) /*!< AEREP (Bit 0) */ + #define R_MIPI_DSI_AKEPSCR_AEREP_Msk (0xffffUL) /*!< AEREP (Bitfield-Mask: 0xffff) */ + #define R_MIPI_DSI_AKEPSCR_AVC_Pos (16UL) /*!< AVC (Bit 16) */ + #define R_MIPI_DSI_AKEPSCR_AVC_Msk (0xf0000UL) /*!< AVC (Bitfield-Mask: 0x0f) */ +/* ======================================================== RXRSSR ========================================================= */ + #define R_MIPI_DSI_RXRSSR_SLT0VLD_Pos (0UL) /*!< SLT0VLD (Bit 0) */ + #define R_MIPI_DSI_RXRSSR_SLT0VLD_Msk (0x1UL) /*!< SLT0VLD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSSR_SLT1VLD_Pos (1UL) /*!< SLT1VLD (Bit 1) */ + #define R_MIPI_DSI_RXRSSR_SLT1VLD_Msk (0x2UL) /*!< SLT1VLD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSSR_SLT2VLD_Pos (2UL) /*!< SLT2VLD (Bit 2) */ + #define R_MIPI_DSI_RXRSSR_SLT2VLD_Msk (0x4UL) /*!< SLT2VLD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSSR_SLT3VLD_Pos (3UL) /*!< SLT3VLD (Bit 3) */ + #define R_MIPI_DSI_RXRSSR_SLT3VLD_Msk (0x8UL) /*!< SLT3VLD (Bitfield-Mask: 0x01) */ +/* ======================================================== RXRSSCR ======================================================== */ + #define R_MIPI_DSI_RXRSSCR_SLT0VLD_Pos (0UL) /*!< SLT0VLD (Bit 0) */ + #define R_MIPI_DSI_RXRSSCR_SLT0VLD_Msk (0x1UL) /*!< SLT0VLD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSSCR_SLT1VLD_Pos (1UL) /*!< SLT1VLD (Bit 1) */ + #define R_MIPI_DSI_RXRSSCR_SLT1VLD_Msk (0x2UL) /*!< SLT1VLD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSSCR_SLT2VLD_Pos (2UL) /*!< SLT2VLD (Bit 2) */ + #define R_MIPI_DSI_RXRSSCR_SLT2VLD_Msk (0x4UL) /*!< SLT2VLD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSSCR_SLT3VLD_Pos (3UL) /*!< SLT3VLD (Bit 3) */ + #define R_MIPI_DSI_RXRSSCR_SLT3VLD_Msk (0x8UL) /*!< SLT3VLD (Bitfield-Mask: 0x01) */ +/* ====================================================== RXRINFOOWSR ====================================================== */ + #define R_MIPI_DSI_RXRINFOOWSR_SL0OW_Pos (0UL) /*!< SL0OW (Bit 0) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL0OW_Msk (0x1UL) /*!< SL0OW (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL1OW_Pos (1UL) /*!< SL1OW (Bit 1) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL1OW_Msk (0x2UL) /*!< SL1OW (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL2OW_Pos (2UL) /*!< SL2OW (Bit 2) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL2OW_Msk (0x4UL) /*!< SL2OW (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL3OW_Pos (3UL) /*!< SL3OW (Bit 3) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL3OW_Msk (0x8UL) /*!< SL3OW (Bitfield-Mask: 0x01) */ +/* ===================================================== RXRINFOOWSCR ====================================================== */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL0OW_Pos (0UL) /*!< SL0OW (Bit 0) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL0OW_Msk (0x1UL) /*!< SL0OW (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL1OW_Pos (1UL) /*!< SL1OW (Bit 1) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL1OW_Msk (0x2UL) /*!< SL1OW (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL2OW_Pos (2UL) /*!< SL2OW (Bit 2) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL2OW_Msk (0x4UL) /*!< SL2OW (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL3OW_Pos (3UL) /*!< SL3OW (Bit 3) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL3OW_Msk (0x8UL) /*!< SL3OW (Bitfield-Mask: 0x01) */ +/* ======================================================== RXRSS0R ======================================================== */ + #define R_MIPI_DSI_RXRSS0R_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS0R_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS0R_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS0R_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_RXRSS0R_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS0R_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_RXRSS0R_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS0R_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_RXRSS0R_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_RXSUC_Pos (25UL) /*!< RXSUC (Bit 25) */ + #define R_MIPI_DSI_RXRSS0R_RXSUC_Msk (0x2000000UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_RXRSS0R_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_RXRSS0R_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_RXRSS0R_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_RXCERR_Pos (29UL) /*!< RXCERR (Bit 29) */ + #define R_MIPI_DSI_RXRSS0R_RXCERR_Msk (0x20000000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXRSS0R_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_INFOOW_Pos (31UL) /*!< INFOOW (Bit 31) */ + #define R_MIPI_DSI_RXRSS0R_INFOOW_Msk (0x80000000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================== RXRSS1R ======================================================== */ + #define R_MIPI_DSI_RXRSS1R_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS1R_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS1R_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS1R_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_RXRSS1R_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS1R_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_RXRSS1R_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS1R_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_RXRSS1R_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_RXSUC_Pos (25UL) /*!< RXSUC (Bit 25) */ + #define R_MIPI_DSI_RXRSS1R_RXSUC_Msk (0x2000000UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_RXRSS1R_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_RXRSS1R_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_RXRSS1R_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_RXCERR_Pos (29UL) /*!< RXCERR (Bit 29) */ + #define R_MIPI_DSI_RXRSS1R_RXCERR_Msk (0x20000000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXRSS1R_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_INFOOW_Pos (31UL) /*!< INFOOW (Bit 31) */ + #define R_MIPI_DSI_RXRSS1R_INFOOW_Msk (0x80000000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================== RXRSS2R ======================================================== */ + #define R_MIPI_DSI_RXRSS2R_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS2R_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS2R_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS2R_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_RXRSS2R_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS2R_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_RXRSS2R_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS2R_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_RXRSS2R_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_RXSUC_Pos (25UL) /*!< RXSUC (Bit 25) */ + #define R_MIPI_DSI_RXRSS2R_RXSUC_Msk (0x2000000UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_RXRSS2R_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_RXRSS2R_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_RXRSS2R_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_RXCERR_Pos (29UL) /*!< RXCERR (Bit 29) */ + #define R_MIPI_DSI_RXRSS2R_RXCERR_Msk (0x20000000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXRSS2R_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_INFOOW_Pos (31UL) /*!< INFOOW (Bit 31) */ + #define R_MIPI_DSI_RXRSS2R_INFOOW_Msk (0x80000000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================== RXRSS3R ======================================================== */ + #define R_MIPI_DSI_RXRSS3R_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS3R_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS3R_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS3R_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_RXRSS3R_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS3R_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_RXRSS3R_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS3R_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_RXRSS3R_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_RXSUC_Pos (25UL) /*!< RXSUC (Bit 25) */ + #define R_MIPI_DSI_RXRSS3R_RXSUC_Msk (0x2000000UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_RXRSS3R_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_RXRSS3R_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_RXRSS3R_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_RXCERR_Pos (29UL) /*!< RXCERR (Bit 29) */ + #define R_MIPI_DSI_RXRSS3R_RXCERR_Msk (0x20000000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXRSS3R_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_INFOOW_Pos (31UL) /*!< INFOOW (Bit 31) */ + #define R_MIPI_DSI_RXRSS3R_INFOOW_Msk (0x80000000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================= RXRSS0R_L ======================================================= */ + #define R_MIPI_DSI_RXRSS0R_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS0R_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS0R_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ======================================================= RXRSS1R_L ======================================================= */ + #define R_MIPI_DSI_RXRSS1R_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS1R_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS1R_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ======================================================= RXRSS2R_L ======================================================= */ + #define R_MIPI_DSI_RXRSS2R_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS2R_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS2R_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ======================================================= RXRSS3R_L ======================================================= */ + #define R_MIPI_DSI_RXRSS3R_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS3R_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS3R_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS0R_LL ======================================================= */ + #define R_MIPI_DSI_RXRSS0R_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS1R_LL ======================================================= */ + #define R_MIPI_DSI_RXRSS1R_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS2R_LL ======================================================= */ + #define R_MIPI_DSI_RXRSS2R_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS3R_LL ======================================================= */ + #define R_MIPI_DSI_RXRSS3R_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS0R_LH ======================================================= */ + #define R_MIPI_DSI_RXRSS0R_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS1R_LH ======================================================= */ + #define R_MIPI_DSI_RXRSS1R_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS2R_LH ======================================================= */ + #define R_MIPI_DSI_RXRSS2R_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS3R_LH ======================================================= */ + #define R_MIPI_DSI_RXRSS3R_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ======================================================= RXRSS0R_H ======================================================= */ + #define R_MIPI_DSI_RXRSS0R_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS0R_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS0R_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS0R_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_RXRSS0R_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_RXSUC_Pos (9UL) /*!< RXSUC (Bit 9) */ + #define R_MIPI_DSI_RXRSS0R_H_RXSUC_Msk (0x200UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_RXFERR_Pos (10UL) /*!< RXFERR (Bit 10) */ + #define R_MIPI_DSI_RXRSS0R_H_RXFERR_Msk (0x400UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_RXFAIL_Pos (11UL) /*!< RXFAIL (Bit 11) */ + #define R_MIPI_DSI_RXRSS0R_H_RXFAIL_Msk (0x800UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_RXPFAIL_Pos (12UL) /*!< RXPFAIL (Bit 12) */ + #define R_MIPI_DSI_RXRSS0R_H_RXPFAIL_Msk (0x1000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_RXCERR_Pos (13UL) /*!< RXCERR (Bit 13) */ + #define R_MIPI_DSI_RXRSS0R_H_RXCERR_Msk (0x2000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_RXAKE_Pos (14UL) /*!< RXAKE (Bit 14) */ + #define R_MIPI_DSI_RXRSS0R_H_RXAKE_Msk (0x4000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_INFOOW_Pos (15UL) /*!< INFOOW (Bit 15) */ + #define R_MIPI_DSI_RXRSS0R_H_INFOOW_Msk (0x8000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================= RXRSS1R_H ======================================================= */ + #define R_MIPI_DSI_RXRSS1R_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS1R_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS1R_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS1R_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_RXRSS1R_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_RXSUC_Pos (9UL) /*!< RXSUC (Bit 9) */ + #define R_MIPI_DSI_RXRSS1R_H_RXSUC_Msk (0x200UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_RXFERR_Pos (10UL) /*!< RXFERR (Bit 10) */ + #define R_MIPI_DSI_RXRSS1R_H_RXFERR_Msk (0x400UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_RXFAIL_Pos (11UL) /*!< RXFAIL (Bit 11) */ + #define R_MIPI_DSI_RXRSS1R_H_RXFAIL_Msk (0x800UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_RXPFAIL_Pos (12UL) /*!< RXPFAIL (Bit 12) */ + #define R_MIPI_DSI_RXRSS1R_H_RXPFAIL_Msk (0x1000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_RXCERR_Pos (13UL) /*!< RXCERR (Bit 13) */ + #define R_MIPI_DSI_RXRSS1R_H_RXCERR_Msk (0x2000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_RXAKE_Pos (14UL) /*!< RXAKE (Bit 14) */ + #define R_MIPI_DSI_RXRSS1R_H_RXAKE_Msk (0x4000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_INFOOW_Pos (15UL) /*!< INFOOW (Bit 15) */ + #define R_MIPI_DSI_RXRSS1R_H_INFOOW_Msk (0x8000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================= RXRSS2R_H ======================================================= */ + #define R_MIPI_DSI_RXRSS2R_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS2R_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS2R_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS2R_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_RXRSS2R_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_RXSUC_Pos (9UL) /*!< RXSUC (Bit 9) */ + #define R_MIPI_DSI_RXRSS2R_H_RXSUC_Msk (0x200UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_RXFERR_Pos (10UL) /*!< RXFERR (Bit 10) */ + #define R_MIPI_DSI_RXRSS2R_H_RXFERR_Msk (0x400UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_RXFAIL_Pos (11UL) /*!< RXFAIL (Bit 11) */ + #define R_MIPI_DSI_RXRSS2R_H_RXFAIL_Msk (0x800UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_RXPFAIL_Pos (12UL) /*!< RXPFAIL (Bit 12) */ + #define R_MIPI_DSI_RXRSS2R_H_RXPFAIL_Msk (0x1000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_RXCERR_Pos (13UL) /*!< RXCERR (Bit 13) */ + #define R_MIPI_DSI_RXRSS2R_H_RXCERR_Msk (0x2000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_RXAKE_Pos (14UL) /*!< RXAKE (Bit 14) */ + #define R_MIPI_DSI_RXRSS2R_H_RXAKE_Msk (0x4000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_INFOOW_Pos (15UL) /*!< INFOOW (Bit 15) */ + #define R_MIPI_DSI_RXRSS2R_H_INFOOW_Msk (0x8000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================= RXRSS3R_H ======================================================= */ + #define R_MIPI_DSI_RXRSS3R_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS3R_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS3R_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS3R_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_RXRSS3R_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_RXSUC_Pos (9UL) /*!< RXSUC (Bit 9) */ + #define R_MIPI_DSI_RXRSS3R_H_RXSUC_Msk (0x200UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_RXFERR_Pos (10UL) /*!< RXFERR (Bit 10) */ + #define R_MIPI_DSI_RXRSS3R_H_RXFERR_Msk (0x400UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_RXFAIL_Pos (11UL) /*!< RXFAIL (Bit 11) */ + #define R_MIPI_DSI_RXRSS3R_H_RXFAIL_Msk (0x800UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_RXPFAIL_Pos (12UL) /*!< RXPFAIL (Bit 12) */ + #define R_MIPI_DSI_RXRSS3R_H_RXPFAIL_Msk (0x1000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_RXCERR_Pos (13UL) /*!< RXCERR (Bit 13) */ + #define R_MIPI_DSI_RXRSS3R_H_RXCERR_Msk (0x2000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_RXAKE_Pos (14UL) /*!< RXAKE (Bit 14) */ + #define R_MIPI_DSI_RXRSS3R_H_RXAKE_Msk (0x4000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_INFOOW_Pos (15UL) /*!< INFOOW (Bit 15) */ + #define R_MIPI_DSI_RXRSS3R_H_INFOOW_Msk (0x8000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ====================================================== RXRSS0R_HL ======================================================= */ + #define R_MIPI_DSI_RXRSS0R_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS0R_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS0R_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ====================================================== RXRSS1R_HL ======================================================= */ + #define R_MIPI_DSI_RXRSS1R_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS1R_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS1R_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ====================================================== RXRSS2R_HL ======================================================= */ + #define R_MIPI_DSI_RXRSS2R_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS2R_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS2R_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ====================================================== RXRSS3R_HL ======================================================= */ + #define R_MIPI_DSI_RXRSS3R_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS3R_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS3R_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ====================================================== RXRSS0R_HH ======================================================= */ + #define R_MIPI_DSI_RXRSS0R_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXSUC_Pos (1UL) /*!< RXSUC (Bit 1) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXSUC_Msk (0x2UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXFERR_Pos (2UL) /*!< RXFERR (Bit 2) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXFERR_Msk (0x4UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXFAIL_Pos (3UL) /*!< RXFAIL (Bit 3) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXFAIL_Msk (0x8UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXPFAIL_Pos (4UL) /*!< RXPFAIL (Bit 4) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXPFAIL_Msk (0x10UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXCERR_Pos (5UL) /*!< RXCERR (Bit 5) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXCERR_Msk (0x20UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXAKE_Pos (6UL) /*!< RXAKE (Bit 6) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXAKE_Msk (0x40UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_INFOOW_Pos (7UL) /*!< INFOOW (Bit 7) */ + #define R_MIPI_DSI_RXRSS0R_HH_INFOOW_Msk (0x80UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ====================================================== RXRSS1R_HH ======================================================= */ + #define R_MIPI_DSI_RXRSS1R_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXSUC_Pos (1UL) /*!< RXSUC (Bit 1) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXSUC_Msk (0x2UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXFERR_Pos (2UL) /*!< RXFERR (Bit 2) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXFERR_Msk (0x4UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXFAIL_Pos (3UL) /*!< RXFAIL (Bit 3) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXFAIL_Msk (0x8UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXPFAIL_Pos (4UL) /*!< RXPFAIL (Bit 4) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXPFAIL_Msk (0x10UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXCERR_Pos (5UL) /*!< RXCERR (Bit 5) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXCERR_Msk (0x20UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXAKE_Pos (6UL) /*!< RXAKE (Bit 6) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXAKE_Msk (0x40UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_INFOOW_Pos (7UL) /*!< INFOOW (Bit 7) */ + #define R_MIPI_DSI_RXRSS1R_HH_INFOOW_Msk (0x80UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ====================================================== RXRSS2R_HH ======================================================= */ + #define R_MIPI_DSI_RXRSS2R_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXSUC_Pos (1UL) /*!< RXSUC (Bit 1) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXSUC_Msk (0x2UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXFERR_Pos (2UL) /*!< RXFERR (Bit 2) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXFERR_Msk (0x4UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXFAIL_Pos (3UL) /*!< RXFAIL (Bit 3) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXFAIL_Msk (0x8UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXPFAIL_Pos (4UL) /*!< RXPFAIL (Bit 4) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXPFAIL_Msk (0x10UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXCERR_Pos (5UL) /*!< RXCERR (Bit 5) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXCERR_Msk (0x20UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXAKE_Pos (6UL) /*!< RXAKE (Bit 6) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXAKE_Msk (0x40UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_INFOOW_Pos (7UL) /*!< INFOOW (Bit 7) */ + #define R_MIPI_DSI_RXRSS2R_HH_INFOOW_Msk (0x80UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ====================================================== RXRSS3R_HH ======================================================= */ + #define R_MIPI_DSI_RXRSS3R_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXSUC_Pos (1UL) /*!< RXSUC (Bit 1) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXSUC_Msk (0x2UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXFERR_Pos (2UL) /*!< RXFERR (Bit 2) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXFERR_Msk (0x4UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXFAIL_Pos (3UL) /*!< RXFAIL (Bit 3) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXFAIL_Msk (0x8UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXPFAIL_Pos (4UL) /*!< RXPFAIL (Bit 4) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXPFAIL_Msk (0x10UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXCERR_Pos (5UL) /*!< RXCERR (Bit 5) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXCERR_Msk (0x20UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXAKE_Pos (6UL) /*!< RXAKE (Bit 6) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXAKE_Msk (0x40UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_INFOOW_Pos (7UL) /*!< INFOOW (Bit 7) */ + #define R_MIPI_DSI_RXRSS3R_HH_INFOOW_Msk (0x80UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================== RXPPD0R ======================================================== */ + #define R_MIPI_DSI_RXPPD0R_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXPPD0R_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD0R_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXPPD0R_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD0R_DATA2_Pos (16UL) /*!< DATA2 (Bit 16) */ + #define R_MIPI_DSI_RXPPD0R_DATA2_Msk (0xff0000UL) /*!< DATA2 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD0R_DATA3_Pos (24UL) /*!< DATA3 (Bit 24) */ + #define R_MIPI_DSI_RXPPD0R_DATA3_Msk (0xff000000UL) /*!< DATA3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RXPPD1R ======================================================== */ + #define R_MIPI_DSI_RXPPD1R_DATA4_Pos (0UL) /*!< DATA4 (Bit 0) */ + #define R_MIPI_DSI_RXPPD1R_DATA4_Msk (0xffUL) /*!< DATA4 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD1R_DATA5_Pos (8UL) /*!< DATA5 (Bit 8) */ + #define R_MIPI_DSI_RXPPD1R_DATA5_Msk (0xff00UL) /*!< DATA5 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD1R_DATA6_Pos (16UL) /*!< DATA6 (Bit 16) */ + #define R_MIPI_DSI_RXPPD1R_DATA6_Msk (0xff0000UL) /*!< DATA6 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD1R_DATA7_Pos (24UL) /*!< DATA7 (Bit 24) */ + #define R_MIPI_DSI_RXPPD1R_DATA7_Msk (0xff000000UL) /*!< DATA7 (Bitfield-Mask: 0xff) */ +/* ======================================================== RXPPD2R ======================================================== */ + #define R_MIPI_DSI_RXPPD2R_DATA8_Pos (0UL) /*!< DATA8 (Bit 0) */ + #define R_MIPI_DSI_RXPPD2R_DATA8_Msk (0xffUL) /*!< DATA8 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD2R_DATA9_Pos (8UL) /*!< DATA9 (Bit 8) */ + #define R_MIPI_DSI_RXPPD2R_DATA9_Msk (0xff00UL) /*!< DATA9 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD2R_DATA10_Pos (16UL) /*!< DATA10 (Bit 16) */ + #define R_MIPI_DSI_RXPPD2R_DATA10_Msk (0xff0000UL) /*!< DATA10 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD2R_DATA11_Pos (24UL) /*!< DATA11 (Bit 24) */ + #define R_MIPI_DSI_RXPPD2R_DATA11_Msk (0xff000000UL) /*!< DATA11 (Bitfield-Mask: 0xff) */ +/* ======================================================== RXPPD3R ======================================================== */ + #define R_MIPI_DSI_RXPPD3R_DATA12_Pos (0UL) /*!< DATA12 (Bit 0) */ + #define R_MIPI_DSI_RXPPD3R_DATA12_Msk (0xffUL) /*!< DATA12 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD3R_DATA13_Pos (8UL) /*!< DATA13 (Bit 8) */ + #define R_MIPI_DSI_RXPPD3R_DATA13_Msk (0xff00UL) /*!< DATA13 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD3R_DATA14_Pos (16UL) /*!< DATA14 (Bit 16) */ + #define R_MIPI_DSI_RXPPD3R_DATA14_Msk (0xff0000UL) /*!< DATA14 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD3R_DATA15_Pos (24UL) /*!< DATA15 (Bit 24) */ + #define R_MIPI_DSI_RXPPD3R_DATA15_Msk (0xff000000UL) /*!< DATA15 (Bitfield-Mask: 0xff) */ +/* ====================================================== HSTXTOSETR ======================================================= */ + #define R_MIPI_DSI_HSTXTOSETR_HTXTO_Pos (0UL) /*!< HTXTO (Bit 0) */ + #define R_MIPI_DSI_HSTXTOSETR_HTXTO_Msk (0xffffffffUL) /*!< HTXTO (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== LRXHTOSETR ======================================================= */ + #define R_MIPI_DSI_LRXHTOSETR_LRXHTO_Pos (0UL) /*!< LRXHTO (Bit 0) */ + #define R_MIPI_DSI_LRXHTOSETR_LRXHTO_Msk (0xffffffffUL) /*!< LRXHTO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TATOSETR ======================================================== */ + #define R_MIPI_DSI_TATOSETR_TATO_Pos (0UL) /*!< TATO (Bit 0) */ + #define R_MIPI_DSI_TATOSETR_TATO_Msk (0xffffffffUL) /*!< TATO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FERRSR ========================================================= */ + #define R_MIPI_DSI_FERRSR_HTXTO_Pos (0UL) /*!< HTXTO (Bit 0) */ + #define R_MIPI_DSI_FERRSR_HTXTO_Msk (0x1UL) /*!< HTXTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_LRXHTO_Pos (1UL) /*!< LRXHTO (Bit 1) */ + #define R_MIPI_DSI_FERRSR_LRXHTO_Msk (0x2UL) /*!< LRXHTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_TATO_Pos (2UL) /*!< TATO (Bit 2) */ + #define R_MIPI_DSI_FERRSR_TATO_Msk (0x4UL) /*!< TATO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_ESCENT_Pos (16UL) /*!< ESCENT (Bit 16) */ + #define R_MIPI_DSI_FERRSR_ESCENT_Msk (0x10000UL) /*!< ESCENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_SYNCESC_Pos (17UL) /*!< SYNCESC (Bit 17) */ + #define R_MIPI_DSI_FERRSR_SYNCESC_Msk (0x20000UL) /*!< SYNCESC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_CTRL_Pos (18UL) /*!< CTRL (Bit 18) */ + #define R_MIPI_DSI_FERRSR_CTRL_Msk (0x40000UL) /*!< CTRL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_CLP0_Pos (19UL) /*!< CLP0 (Bit 19) */ + #define R_MIPI_DSI_FERRSR_CLP0_Msk (0x80000UL) /*!< CLP0 (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_CLP1_Pos (20UL) /*!< CLP1 (Bit 20) */ + #define R_MIPI_DSI_FERRSR_CLP1_Msk (0x100000UL) /*!< CLP1 (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_CLP0S_Pos (27UL) /*!< CLP0S (Bit 27) */ + #define R_MIPI_DSI_FERRSR_CLP0S_Msk (0x8000000UL) /*!< CLP0S (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_CLP1S_Pos (28UL) /*!< CLP1S (Bit 28) */ + #define R_MIPI_DSI_FERRSR_CLP1S_Msk (0x10000000UL) /*!< CLP1S (Bitfield-Mask: 0x01) */ +/* ======================================================== FERRSCR ======================================================== */ + #define R_MIPI_DSI_FERRSCR_HTXTO_Pos (0UL) /*!< HTXTO (Bit 0) */ + #define R_MIPI_DSI_FERRSCR_HTXTO_Msk (0x1UL) /*!< HTXTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_LRXHTO_Pos (1UL) /*!< LRXHTO (Bit 1) */ + #define R_MIPI_DSI_FERRSCR_LRXHTO_Msk (0x2UL) /*!< LRXHTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_TATO_Pos (2UL) /*!< TATO (Bit 2) */ + #define R_MIPI_DSI_FERRSCR_TATO_Msk (0x4UL) /*!< TATO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_ESCENT_Pos (16UL) /*!< ESCENT (Bit 16) */ + #define R_MIPI_DSI_FERRSCR_ESCENT_Msk (0x10000UL) /*!< ESCENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_SYNCESC_Pos (17UL) /*!< SYNCESC (Bit 17) */ + #define R_MIPI_DSI_FERRSCR_SYNCESC_Msk (0x20000UL) /*!< SYNCESC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_CTRL_Pos (18UL) /*!< CTRL (Bit 18) */ + #define R_MIPI_DSI_FERRSCR_CTRL_Msk (0x40000UL) /*!< CTRL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_CLP0_Pos (19UL) /*!< CLP0 (Bit 19) */ + #define R_MIPI_DSI_FERRSCR_CLP0_Msk (0x80000UL) /*!< CLP0 (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_CLP1_Pos (20UL) /*!< CLP1 (Bit 20) */ + #define R_MIPI_DSI_FERRSCR_CLP1_Msk (0x100000UL) /*!< CLP1 (Bitfield-Mask: 0x01) */ +/* ======================================================== FERRIER ======================================================== */ + #define R_MIPI_DSI_FERRIER_HTXTO_Pos (0UL) /*!< HTXTO (Bit 0) */ + #define R_MIPI_DSI_FERRIER_HTXTO_Msk (0x1UL) /*!< HTXTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_LRXHTO_Pos (1UL) /*!< LRXHTO (Bit 1) */ + #define R_MIPI_DSI_FERRIER_LRXHTO_Msk (0x2UL) /*!< LRXHTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_TATO_Pos (2UL) /*!< TATO (Bit 2) */ + #define R_MIPI_DSI_FERRIER_TATO_Msk (0x4UL) /*!< TATO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_ESCENT_Pos (16UL) /*!< ESCENT (Bit 16) */ + #define R_MIPI_DSI_FERRIER_ESCENT_Msk (0x10000UL) /*!< ESCENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_SYNCESC_Pos (17UL) /*!< SYNCESC (Bit 17) */ + #define R_MIPI_DSI_FERRIER_SYNCESC_Msk (0x20000UL) /*!< SYNCESC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_CTRL_Pos (18UL) /*!< CTRL (Bit 18) */ + #define R_MIPI_DSI_FERRIER_CTRL_Msk (0x40000UL) /*!< CTRL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_CLP0_Pos (19UL) /*!< CLP0 (Bit 19) */ + #define R_MIPI_DSI_FERRIER_CLP0_Msk (0x80000UL) /*!< CLP0 (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_CLP1_Pos (20UL) /*!< CLP1 (Bit 20) */ + #define R_MIPI_DSI_FERRIER_CLP1_Msk (0x100000UL) /*!< CLP1 (Bitfield-Mask: 0x01) */ +/* ====================================================== CLSTPTSETR ======================================================= */ + #define R_MIPI_DSI_CLSTPTSETR_CLKSTPT_Pos (2UL) /*!< CLKSTPT (Bit 2) */ + #define R_MIPI_DSI_CLSTPTSETR_CLKSTPT_Msk (0xffcUL) /*!< CLKSTPT (Bitfield-Mask: 0x3ff) */ + #define R_MIPI_DSI_CLSTPTSETR_CLKBFHT_Pos (16UL) /*!< CLKBFHT (Bit 16) */ + #define R_MIPI_DSI_CLSTPTSETR_CLKBFHT_Msk (0xff0000UL) /*!< CLKBFHT (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_CLSTPTSETR_CLKKPT_Pos (24UL) /*!< CLKKPT (Bit 24) */ + #define R_MIPI_DSI_CLSTPTSETR_CLKKPT_Msk (0xff000000UL) /*!< CLKKPT (Bitfield-Mask: 0xff) */ +/* ====================================================== LPTRNSTSETR ====================================================== */ + #define R_MIPI_DSI_LPTRNSTSETR_GOLPBKT_Pos (0UL) /*!< GOLPBKT (Bit 0) */ + #define R_MIPI_DSI_LPTRNSTSETR_GOLPBKT_Msk (0x3ffUL) /*!< GOLPBKT (Bitfield-Mask: 0x3ff) */ +/* ========================================================= PLSR ========================================================== */ + #define R_MIPI_DSI_PLSR_CLUAN_Pos (0UL) /*!< CLUAN (Bit 0) */ + #define R_MIPI_DSI_PLSR_CLUAN_Msk (0x1UL) /*!< CLUAN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_CLSTP_Pos (1UL) /*!< CLSTP (Bit 1) */ + #define R_MIPI_DSI_PLSR_CLSTP_Msk (0x2UL) /*!< CLSTP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0RLE_Pos (2UL) /*!< DL0RLE (Bit 2) */ + #define R_MIPI_DSI_PLSR_DL0RLE_Msk (0x4UL) /*!< DL0RLE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0RUE_Pos (3UL) /*!< DL0RUE (Bit 3) */ + #define R_MIPI_DSI_PLSR_DL0RUE_Msk (0x8UL) /*!< DL0RUE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0UAN_Pos (4UL) /*!< DL0UAN (Bit 4) */ + #define R_MIPI_DSI_PLSR_DL0UAN_Msk (0x10UL) /*!< DL0UAN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL1UAN_Pos (5UL) /*!< DL1UAN (Bit 5) */ + #define R_MIPI_DSI_PLSR_DL1UAN_Msk (0x20UL) /*!< DL1UAN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0STP_Pos (8UL) /*!< DL0STP (Bit 8) */ + #define R_MIPI_DSI_PLSR_DL0STP_Msk (0x100UL) /*!< DL0STP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL1STP_Pos (9UL) /*!< DL1STP (Bit 9) */ + #define R_MIPI_DSI_PLSR_DL1STP_Msk (0x200UL) /*!< DL1STP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0RX2TX_Pos (12UL) /*!< DL0RX2TX (Bit 12) */ + #define R_MIPI_DSI_PLSR_DL0RX2TX_Msk (0x1000UL) /*!< DL0RX2TX (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0TX2RX_Pos (13UL) /*!< DL0TX2RX (Bit 13) */ + #define R_MIPI_DSI_PLSR_DL0TX2RX_Msk (0x2000UL) /*!< DL0TX2RX (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0DIR_Pos (15UL) /*!< DL0DIR (Bit 15) */ + #define R_MIPI_DSI_PLSR_DL0DIR_Msk (0x8000UL) /*!< DL0DIR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_CLULPENT_Pos (24UL) /*!< CLULPENT (Bit 24) */ + #define R_MIPI_DSI_PLSR_CLULPENT_Msk (0x1000000UL) /*!< CLULPENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_CLULPEXT_Pos (25UL) /*!< CLULPEXT (Bit 25) */ + #define R_MIPI_DSI_PLSR_CLULPEXT_Msk (0x2000000UL) /*!< CLULPEXT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_CLLP2HS_Pos (26UL) /*!< CLLP2HS (Bit 26) */ + #define R_MIPI_DSI_PLSR_CLLP2HS_Msk (0x4000000UL) /*!< CLLP2HS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_CLHS2LP_Pos (27UL) /*!< CLHS2LP (Bit 27) */ + #define R_MIPI_DSI_PLSR_CLHS2LP_Msk (0x8000000UL) /*!< CLHS2LP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DLULPENT_Pos (28UL) /*!< DLULPENT (Bit 28) */ + #define R_MIPI_DSI_PLSR_DLULPENT_Msk (0x10000000UL) /*!< DLULPENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DLULPEXT_Pos (29UL) /*!< DLULPEXT (Bit 29) */ + #define R_MIPI_DSI_PLSR_DLULPEXT_Msk (0x20000000UL) /*!< DLULPEXT (Bitfield-Mask: 0x01) */ +/* ========================================================= PLSCR ========================================================= */ + #define R_MIPI_DSI_PLSCR_DL0RX2TX_Pos (12UL) /*!< DL0RX2TX (Bit 12) */ + #define R_MIPI_DSI_PLSCR_DL0RX2TX_Msk (0x1000UL) /*!< DL0RX2TX (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_DL0TX2RX_Pos (13UL) /*!< DL0TX2RX (Bit 13) */ + #define R_MIPI_DSI_PLSCR_DL0TX2RX_Msk (0x2000UL) /*!< DL0TX2RX (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_CLULPENT_Pos (24UL) /*!< CLULPENT (Bit 24) */ + #define R_MIPI_DSI_PLSCR_CLULPENT_Msk (0x1000000UL) /*!< CLULPENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_CLULPEXT_Pos (25UL) /*!< CLULPEXT (Bit 25) */ + #define R_MIPI_DSI_PLSCR_CLULPEXT_Msk (0x2000000UL) /*!< CLULPEXT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_CLLP2HS_Pos (26UL) /*!< CLLP2HS (Bit 26) */ + #define R_MIPI_DSI_PLSCR_CLLP2HS_Msk (0x4000000UL) /*!< CLLP2HS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_CLHS2LP_Pos (27UL) /*!< CLHS2LP (Bit 27) */ + #define R_MIPI_DSI_PLSCR_CLHS2LP_Msk (0x8000000UL) /*!< CLHS2LP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_DLULPENT_Pos (28UL) /*!< DLULPENT (Bit 28) */ + #define R_MIPI_DSI_PLSCR_DLULPENT_Msk (0x10000000UL) /*!< DLULPENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_DLULPEXT_Pos (29UL) /*!< DLULPEXT (Bit 29) */ + #define R_MIPI_DSI_PLSCR_DLULPEXT_Msk (0x20000000UL) /*!< DLULPEXT (Bitfield-Mask: 0x01) */ +/* ========================================================= PLIER ========================================================= */ + #define R_MIPI_DSI_PLIER_DL0RX2TX_Pos (12UL) /*!< DL0RX2TX (Bit 12) */ + #define R_MIPI_DSI_PLIER_DL0RX2TX_Msk (0x1000UL) /*!< DL0RX2TX (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_DL0TX2RX_Pos (13UL) /*!< DL0TX2RX (Bit 13) */ + #define R_MIPI_DSI_PLIER_DL0TX2RX_Msk (0x2000UL) /*!< DL0TX2RX (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_CLULPENT_Pos (24UL) /*!< CLULPENT (Bit 24) */ + #define R_MIPI_DSI_PLIER_CLULPENT_Msk (0x1000000UL) /*!< CLULPENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_CLULPEXT_Pos (25UL) /*!< CLULPEXT (Bit 25) */ + #define R_MIPI_DSI_PLIER_CLULPEXT_Msk (0x2000000UL) /*!< CLULPEXT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_CLLP2HS_Pos (26UL) /*!< CLLP2HS (Bit 26) */ + #define R_MIPI_DSI_PLIER_CLLP2HS_Msk (0x4000000UL) /*!< CLLP2HS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_CLHS2LP_Pos (27UL) /*!< CLHS2LP (Bit 27) */ + #define R_MIPI_DSI_PLIER_CLHS2LP_Msk (0x8000000UL) /*!< CLHS2LP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_DLULPENT_Pos (28UL) /*!< DLULPENT (Bit 28) */ + #define R_MIPI_DSI_PLIER_DLULPENT_Msk (0x10000000UL) /*!< DLULPENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_DLULPEXT_Pos (29UL) /*!< DLULPEXT (Bit 29) */ + #define R_MIPI_DSI_PLIER_DLULPEXT_Msk (0x20000000UL) /*!< DLULPEXT (Bitfield-Mask: 0x01) */ +/* ======================================================== VMSET0R ======================================================== */ + #define R_MIPI_DSI_VMSET0R_VSTART_Pos (0UL) /*!< VSTART (Bit 0) */ + #define R_MIPI_DSI_VMSET0R_VSTART_Msk (0x1UL) /*!< VSTART (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSET0R_VSTOP_Pos (1UL) /*!< VSTOP (Bit 1) */ + #define R_MIPI_DSI_VMSET0R_VSTOP_Msk (0x2UL) /*!< VSTOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSET0R_HSANOLP_Pos (8UL) /*!< HSANOLP (Bit 8) */ + #define R_MIPI_DSI_VMSET0R_HSANOLP_Msk (0x100UL) /*!< HSANOLP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSET0R_HBPNOLP_Pos (9UL) /*!< HBPNOLP (Bit 9) */ + #define R_MIPI_DSI_VMSET0R_HBPNOLP_Msk (0x200UL) /*!< HBPNOLP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSET0R_HFPNOLP_Pos (10UL) /*!< HFPNOLP (Bit 10) */ + #define R_MIPI_DSI_VMSET0R_HFPNOLP_Msk (0x400UL) /*!< HFPNOLP (Bitfield-Mask: 0x01) */ +/* ======================================================== VMSET1R ======================================================== */ + #define R_MIPI_DSI_VMSET1R_DLY_Pos (2UL) /*!< DLY (Bit 2) */ + #define R_MIPI_DSI_VMSET1R_DLY_Msk (0x3ffcUL) /*!< DLY (Bitfield-Mask: 0xfff) */ +/* ========================================================= VMSR ========================================================== */ + #define R_MIPI_DSI_VMSR_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_MIPI_DSI_VMSR_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSR_STOP_Pos (1UL) /*!< STOP (Bit 1) */ + #define R_MIPI_DSI_VMSR_STOP_Msk (0x2UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSR_RUNNING_Pos (2UL) /*!< RUNNING (Bit 2) */ + #define R_MIPI_DSI_VMSR_RUNNING_Msk (0x4UL) /*!< RUNNING (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSR_VIRDY_Pos (3UL) /*!< VIRDY (Bit 3) */ + #define R_MIPI_DSI_VMSR_VIRDY_Msk (0x8UL) /*!< VIRDY (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSR_TIMERR_Pos (20UL) /*!< TIMERR (Bit 20) */ + #define R_MIPI_DSI_VMSR_TIMERR_Msk (0x100000UL) /*!< TIMERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSR_VBUFUDF_Pos (22UL) /*!< VBUFUDF (Bit 22) */ + #define R_MIPI_DSI_VMSR_VBUFUDF_Msk (0x400000UL) /*!< VBUFUDF (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSR_VBUFOVF_Pos (23UL) /*!< VBUFOVF (Bit 23) */ + #define R_MIPI_DSI_VMSR_VBUFOVF_Msk (0x800000UL) /*!< VBUFOVF (Bitfield-Mask: 0x01) */ +/* ========================================================= VMSCR ========================================================= */ + #define R_MIPI_DSI_VMSCR_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_MIPI_DSI_VMSCR_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSCR_STOP_Pos (1UL) /*!< STOP (Bit 1) */ + #define R_MIPI_DSI_VMSCR_STOP_Msk (0x2UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSCR_VIRDY_Pos (3UL) /*!< VIRDY (Bit 3) */ + #define R_MIPI_DSI_VMSCR_VIRDY_Msk (0x8UL) /*!< VIRDY (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSCR_TIMERR_Pos (20UL) /*!< TIMERR (Bit 20) */ + #define R_MIPI_DSI_VMSCR_TIMERR_Msk (0x100000UL) /*!< TIMERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSCR_VBUFUDF_Pos (22UL) /*!< VBUFUDF (Bit 22) */ + #define R_MIPI_DSI_VMSCR_VBUFUDF_Msk (0x400000UL) /*!< VBUFUDF (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSCR_VBUFOVF_Pos (23UL) /*!< VBUFOVF (Bit 23) */ + #define R_MIPI_DSI_VMSCR_VBUFOVF_Msk (0x800000UL) /*!< VBUFOVF (Bitfield-Mask: 0x01) */ +/* ========================================================= VMIER ========================================================= */ + #define R_MIPI_DSI_VMIER_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_MIPI_DSI_VMIER_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMIER_STOP_Pos (1UL) /*!< STOP (Bit 1) */ + #define R_MIPI_DSI_VMIER_STOP_Msk (0x2UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMIER_VIRDY_Pos (3UL) /*!< VIRDY (Bit 3) */ + #define R_MIPI_DSI_VMIER_VIRDY_Msk (0x8UL) /*!< VIRDY (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMIER_TIMERR_Pos (20UL) /*!< TIMERR (Bit 20) */ + #define R_MIPI_DSI_VMIER_TIMERR_Msk (0x100000UL) /*!< TIMERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMIER_VBUFUDF_Pos (22UL) /*!< VBUFUDF (Bit 22) */ + #define R_MIPI_DSI_VMIER_VBUFUDF_Msk (0x400000UL) /*!< VBUFUDF (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMIER_VBUFOVF_Pos (23UL) /*!< VBUFOVF (Bit 23) */ + #define R_MIPI_DSI_VMIER_VBUFOVF_Msk (0x800000UL) /*!< VBUFOVF (Bitfield-Mask: 0x01) */ +/* ======================================================= VMPPSETR ======================================================== */ + #define R_MIPI_DSI_VMPPSETR_TXESYNC_Pos (15UL) /*!< TXESYNC (Bit 15) */ + #define R_MIPI_DSI_VMPPSETR_TXESYNC_Msk (0x8000UL) /*!< TXESYNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMPPSETR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_VMPPSETR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_VMPPSETR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_VMPPSETR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ======================================================= VMVSSETR ======================================================== */ + #define R_MIPI_DSI_VMVSSETR_VSA_Pos (0UL) /*!< VSA (Bit 0) */ + #define R_MIPI_DSI_VMVSSETR_VSA_Msk (0xfffUL) /*!< VSA (Bitfield-Mask: 0xfff) */ + #define R_MIPI_DSI_VMVSSETR_VSPOL_Pos (15UL) /*!< VSPOL (Bit 15) */ + #define R_MIPI_DSI_VMVSSETR_VSPOL_Msk (0x8000UL) /*!< VSPOL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMVSSETR_VACT_Pos (16UL) /*!< VACT (Bit 16) */ + #define R_MIPI_DSI_VMVSSETR_VACT_Msk (0x7fff0000UL) /*!< VACT (Bitfield-Mask: 0x7fff) */ +/* ======================================================= VMVPSETR ======================================================== */ + #define R_MIPI_DSI_VMVPSETR_VBP_Pos (0UL) /*!< VBP (Bit 0) */ + #define R_MIPI_DSI_VMVPSETR_VBP_Msk (0x1fffUL) /*!< VBP (Bitfield-Mask: 0x1fff) */ + #define R_MIPI_DSI_VMVPSETR_VFP_Pos (16UL) /*!< VFP (Bit 16) */ + #define R_MIPI_DSI_VMVPSETR_VFP_Msk (0x1fff0000UL) /*!< VFP (Bitfield-Mask: 0x1fff) */ +/* ======================================================= VMHSSETR ======================================================== */ + #define R_MIPI_DSI_VMHSSETR_HSA_Pos (0UL) /*!< HSA (Bit 0) */ + #define R_MIPI_DSI_VMHSSETR_HSA_Msk (0xfffUL) /*!< HSA (Bitfield-Mask: 0xfff) */ + #define R_MIPI_DSI_VMHSSETR_HSPOL_Pos (15UL) /*!< HSPOL (Bit 15) */ + #define R_MIPI_DSI_VMHSSETR_HSPOL_Msk (0x8000UL) /*!< HSPOL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMHSSETR_HACT_Pos (16UL) /*!< HACT (Bit 16) */ + #define R_MIPI_DSI_VMHSSETR_HACT_Msk (0x7fff0000UL) /*!< HACT (Bitfield-Mask: 0x7fff) */ +/* ======================================================= VMHPSETR ======================================================== */ + #define R_MIPI_DSI_VMHPSETR_HBP_Pos (0UL) /*!< HBP (Bit 0) */ + #define R_MIPI_DSI_VMHPSETR_HBP_Msk (0x1fffUL) /*!< HBP (Bitfield-Mask: 0x1fff) */ + #define R_MIPI_DSI_VMHPSETR_HFP_Pos (16UL) /*!< HFP (Bit 16) */ + #define R_MIPI_DSI_VMHPSETR_HFP_Msk (0x1fff0000UL) /*!< HFP (Bitfield-Mask: 0x1fff) */ +/* ====================================================== SQCH0SET0R ======================================================= */ + #define R_MIPI_DSI_SQCH0SET0R_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_MIPI_DSI_SQCH0SET0R_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ======================================================== SQCH0SR ======================================================== */ + #define R_MIPI_DSI_SQCH0SR_RUNNING_Pos (2UL) /*!< RUNNING (Bit 2) */ + #define R_MIPI_DSI_SQCH0SR_RUNNING_Msk (0x4UL) /*!< RUNNING (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_AACTFIN_Pos (4UL) /*!< AACTFIN (Bit 4) */ + #define R_MIPI_DSI_SQCH0SR_AACTFIN_Msk (0x10UL) /*!< AACTFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_ADESFIN_Pos (8UL) /*!< ADESFIN (Bit 8) */ + #define R_MIPI_DSI_SQCH0SR_ADESFIN_Msk (0x100UL) /*!< ADESFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_DABORT_Pos (16UL) /*!< DABORT (Bit 16) */ + #define R_MIPI_DSI_SQCH0SR_DABORT_Msk (0x10000UL) /*!< DABORT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_SIZEERR_Pos (19UL) /*!< SIZEERR (Bit 19) */ + #define R_MIPI_DSI_SQCH0SR_SIZEERR_Msk (0x80000UL) /*!< SIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_TXIBERR_Pos (24UL) /*!< TXIBERR (Bit 24) */ + #define R_MIPI_DSI_SQCH0SR_TXIBERR_Msk (0x1000000UL) /*!< TXIBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_SQCH0SR_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_SQCH0SR_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_SQCH0SR_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_RXCORERR_Pos (29UL) /*!< RXCORERR (Bit 29) */ + #define R_MIPI_DSI_SQCH0SR_RXCORERR_Msk (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_SQCH0SR_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ======================================================= SQCH0SCR ======================================================== */ + #define R_MIPI_DSI_SQCH0SCR_AACTFIN_Pos (4UL) /*!< AACTFIN (Bit 4) */ + #define R_MIPI_DSI_SQCH0SCR_AACTFIN_Msk (0x10UL) /*!< AACTFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_ADESFIN_Pos (8UL) /*!< ADESFIN (Bit 8) */ + #define R_MIPI_DSI_SQCH0SCR_ADESFIN_Msk (0x100UL) /*!< ADESFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_DABORT_Pos (16UL) /*!< DABORT (Bit 16) */ + #define R_MIPI_DSI_SQCH0SCR_DABORT_Msk (0x10000UL) /*!< DABORT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_SIZEERR_Pos (19UL) /*!< SIZEERR (Bit 19) */ + #define R_MIPI_DSI_SQCH0SCR_SIZEERR_Msk (0x80000UL) /*!< SIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_TXIBERR_Pos (24UL) /*!< TXIBERR (Bit 24) */ + #define R_MIPI_DSI_SQCH0SCR_TXIBERR_Msk (0x1000000UL) /*!< TXIBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_SQCH0SCR_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_SQCH0SCR_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_SQCH0SCR_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_RXCORERR_Pos (29UL) /*!< RXCORERR (Bit 29) */ + #define R_MIPI_DSI_SQCH0SCR_RXCORERR_Msk (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_SQCH0SCR_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ======================================================= SQCH0IER ======================================================== */ + #define R_MIPI_DSI_SQCH0IER_AACTFIN_Pos (4UL) /*!< AACTFIN (Bit 4) */ + #define R_MIPI_DSI_SQCH0IER_AACTFIN_Msk (0x10UL) /*!< AACTFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_ADESFIN_Pos (8UL) /*!< ADESFIN (Bit 8) */ + #define R_MIPI_DSI_SQCH0IER_ADESFIN_Msk (0x100UL) /*!< ADESFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_DABORT_Pos (16UL) /*!< DABORT (Bit 16) */ + #define R_MIPI_DSI_SQCH0IER_DABORT_Msk (0x10000UL) /*!< DABORT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_SIZEERR_Pos (19UL) /*!< SIZEERR (Bit 19) */ + #define R_MIPI_DSI_SQCH0IER_SIZEERR_Msk (0x80000UL) /*!< SIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_TXIBERR_Pos (24UL) /*!< TXIBERR (Bit 24) */ + #define R_MIPI_DSI_SQCH0IER_TXIBERR_Msk (0x1000000UL) /*!< TXIBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_SQCH0IER_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_SQCH0IER_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_SQCH0IER_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_RXCORERR_Pos (29UL) /*!< RXCORERR (Bit 29) */ + #define R_MIPI_DSI_SQCH0IER_RXCORERR_Msk (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_SQCH0IER_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ====================================================== SQCH1SET0R ======================================================= */ + #define R_MIPI_DSI_SQCH1SET0R_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_MIPI_DSI_SQCH1SET0R_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ======================================================== SQCH1SR ======================================================== */ + #define R_MIPI_DSI_SQCH1SR_RUNNING_Pos (2UL) /*!< RUNNING (Bit 2) */ + #define R_MIPI_DSI_SQCH1SR_RUNNING_Msk (0x4UL) /*!< RUNNING (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_AACTFIN_Pos (4UL) /*!< AACTFIN (Bit 4) */ + #define R_MIPI_DSI_SQCH1SR_AACTFIN_Msk (0x10UL) /*!< AACTFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_ADESFIN_Pos (8UL) /*!< ADESFIN (Bit 8) */ + #define R_MIPI_DSI_SQCH1SR_ADESFIN_Msk (0x100UL) /*!< ADESFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_DABORT_Pos (16UL) /*!< DABORT (Bit 16) */ + #define R_MIPI_DSI_SQCH1SR_DABORT_Msk (0x10000UL) /*!< DABORT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_SIZEERR_Pos (19UL) /*!< SIZEERR (Bit 19) */ + #define R_MIPI_DSI_SQCH1SR_SIZEERR_Msk (0x80000UL) /*!< SIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_TXIBERR_Pos (24UL) /*!< TXIBERR (Bit 24) */ + #define R_MIPI_DSI_SQCH1SR_TXIBERR_Msk (0x1000000UL) /*!< TXIBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_SQCH1SR_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_SQCH1SR_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_SQCH1SR_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_RXCORERR_Pos (29UL) /*!< RXCORERR (Bit 29) */ + #define R_MIPI_DSI_SQCH1SR_RXCORERR_Msk (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_SQCH1SR_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ======================================================= SQCH1SCR ======================================================== */ + #define R_MIPI_DSI_SQCH1SCR_AACTFIN_Pos (4UL) /*!< AACTFIN (Bit 4) */ + #define R_MIPI_DSI_SQCH1SCR_AACTFIN_Msk (0x10UL) /*!< AACTFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_ADESFIN_Pos (8UL) /*!< ADESFIN (Bit 8) */ + #define R_MIPI_DSI_SQCH1SCR_ADESFIN_Msk (0x100UL) /*!< ADESFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_DABORT_Pos (16UL) /*!< DABORT (Bit 16) */ + #define R_MIPI_DSI_SQCH1SCR_DABORT_Msk (0x10000UL) /*!< DABORT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_SIZEERR_Pos (19UL) /*!< SIZEERR (Bit 19) */ + #define R_MIPI_DSI_SQCH1SCR_SIZEERR_Msk (0x80000UL) /*!< SIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_TXIBERR_Pos (24UL) /*!< TXIBERR (Bit 24) */ + #define R_MIPI_DSI_SQCH1SCR_TXIBERR_Msk (0x1000000UL) /*!< TXIBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_SQCH1SCR_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_SQCH1SCR_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_SQCH1SCR_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_RXCORERR_Pos (29UL) /*!< RXCORERR (Bit 29) */ + #define R_MIPI_DSI_SQCH1SCR_RXCORERR_Msk (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_SQCH1SCR_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ======================================================= SQCH1IER ======================================================== */ + #define R_MIPI_DSI_SQCH1IER_AACTFIN_Pos (4UL) /*!< AACTFIN (Bit 4) */ + #define R_MIPI_DSI_SQCH1IER_AACTFIN_Msk (0x10UL) /*!< AACTFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_ADESFIN_Pos (8UL) /*!< ADESFIN (Bit 8) */ + #define R_MIPI_DSI_SQCH1IER_ADESFIN_Msk (0x100UL) /*!< ADESFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_DABORT_Pos (16UL) /*!< DABORT (Bit 16) */ + #define R_MIPI_DSI_SQCH1IER_DABORT_Msk (0x10000UL) /*!< DABORT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_SIZEERR_Pos (19UL) /*!< SIZEERR (Bit 19) */ + #define R_MIPI_DSI_SQCH1IER_SIZEERR_Msk (0x80000UL) /*!< SIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_TXIBERR_Pos (24UL) /*!< TXIBERR (Bit 24) */ + #define R_MIPI_DSI_SQCH1IER_TXIBERR_Msk (0x1000000UL) /*!< TXIBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_SQCH1IER_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_SQCH1IER_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_SQCH1IER_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_RXCORERR_Pos (29UL) /*!< RXCORERR (Bit 29) */ + #define R_MIPI_DSI_SQCH1IER_RXCORERR_Msk (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_SQCH1IER_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ====================================================== SQCH0DSC0AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC0AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC0AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC0AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC0AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC0AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC0AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC0AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC0AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC0AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC0AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC0AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC0AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC1AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC1AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC1AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC1AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC1AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC1AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC1AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC1AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC1AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC1AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC1AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC1AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC1AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC2AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC2AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC2AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC2AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC2AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC2AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC2AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC2AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC2AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC2AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC2AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC2AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC2AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC3AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC3AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC3AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC3AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC3AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC3AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC3AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC3AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC3AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC3AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC3AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC3AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC3AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC4AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC4AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC4AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC4AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC4AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC4AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC4AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC4AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC4AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC4AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC4AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC4AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC4AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC5AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC5AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC5AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC5AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC5AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC5AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC5AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC5AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC5AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC5AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC5AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC5AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC5AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC6AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC6AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC6AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC6AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC6AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC6AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC6AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC6AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC6AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC6AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC6AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC6AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC6AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC7AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC7AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC7AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC7AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC7AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC7AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC7AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC7AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC7AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC7AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC7AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC7AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC7AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC0AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC0AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC0AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC1AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC1AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC1AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC2AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC2AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC2AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC3AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC3AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC3AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC4AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC4AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC4AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC5AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC5AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC5AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC6AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC6AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC6AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC7AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC7AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC7AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC0AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC0AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC0AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC1AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC2AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC3AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC4AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC5AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC6AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC7AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC0AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC1AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC2AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC3AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC4AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC5AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC6AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC7AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC0AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC1AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC2AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC3AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC4AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC5AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC6AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC7AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC0BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC0BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC0BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC1BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC1BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC1BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC2BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC2BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC2BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC3BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC3BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC3BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC4BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC4BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC4BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC5BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC5BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC5BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC6BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC6BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC6BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC7BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC7BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC7BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC0CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC0CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC0CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC0CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC1CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC1CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC1CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC1CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC2CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC2CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC2CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC2CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC3CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC3CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC3CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC3CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC4CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC4CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC4CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC4CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC5CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC5CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC5CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC5CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC6CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC6CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC6CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC6CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC7CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC7CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC7CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC7CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC0CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC1CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC2CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC3CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC4CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC5CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC6CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC7CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC0CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC1CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC2CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC3CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC4CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC5CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC6CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC7CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC0CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC0CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC0CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC1CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC1CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC1CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC2CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC2CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC2CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC3CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC3CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC3CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC4CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC4CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC4CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC5CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC5CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC5CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC6CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC6CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC6CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC7CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC7CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC7CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC0CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC0CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC1CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC1CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC2CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC2CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC3CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC3CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC4CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC4CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC5CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC5CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC6CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC6CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC7CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC7CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC0CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC0DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC1DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC2DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC3DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC4DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC5DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC6DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC7DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== SQCH0DSC0DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC1DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC2DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC3DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC4DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC5DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC6DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC7DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ==================================================== SQCH0DSC0DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC0DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC0DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC1DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC2DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC3DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC4DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC5DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC6DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC7DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ==================================================== SQCH0DSC0DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC0DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC0AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC0AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC0AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC0AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC0AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC0AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC0AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC0AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC0AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC0AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC0AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC0AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC0AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC1AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC1AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC1AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC1AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC1AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC1AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC1AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC1AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC1AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC1AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC1AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC1AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC1AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC2AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC2AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC2AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC2AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC2AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC2AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC2AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC2AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC2AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC2AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC2AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC2AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC2AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC3AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC3AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC3AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC3AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC3AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC3AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC3AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC3AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC3AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC3AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC3AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC3AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC3AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC4AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC4AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC4AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC4AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC4AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC4AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC4AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC4AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC4AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC4AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC4AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC4AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC4AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC5AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC5AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC5AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC5AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC5AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC5AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC5AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC5AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC5AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC5AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC5AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC5AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC5AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC6AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC6AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC6AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC6AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC6AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC6AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC6AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC6AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC6AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC6AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC6AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC6AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC6AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC7AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC7AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC7AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC7AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC7AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC7AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC7AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC7AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC7AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC7AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC7AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC7AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC7AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC0AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC0AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC0AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC1AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC1AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC1AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC2AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC2AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC2AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC3AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC3AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC3AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC4AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC4AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC4AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC5AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC5AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC5AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC6AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC6AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC6AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC7AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC7AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC7AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC0AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC0AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC0AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC1AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC2AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC3AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC4AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC5AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC6AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC7AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC0AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC1AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC2AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC3AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC4AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC5AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC6AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC7AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC0AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC1AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC2AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC3AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC4AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC5AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC6AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC7AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC0BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC0BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC0BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC1BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC1BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC1BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC2BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC2BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC2BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC3BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC3BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC3BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC4BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC4BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC4BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC5BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC5BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC5BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC6BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC6BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC6BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC7BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC7BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC7BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC0CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC0CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC0CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC0CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC1CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC1CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC1CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC1CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC2CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC2CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC2CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC2CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC3CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC3CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC3CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC3CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC4CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC4CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC4CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC4CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC5CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC5CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC5CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC5CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC6CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC6CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC6CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC6CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC7CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC7CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC7CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC7CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC0CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC1CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC2CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC3CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC4CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC5CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC6CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC7CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC0CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC1CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC2CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC3CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC4CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC5CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC6CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC7CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC0CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC0CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC0CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC1CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC1CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC1CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC2CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC2CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC2CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC3CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC3CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC3CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC4CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC4CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC4CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC5CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC5CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC5CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC6CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC6CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC6CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC7CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC7CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC7CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC0CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC0CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC1CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC1CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC2CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC2CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC3CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC3CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC4CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC4CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC5CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC5CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC6CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC6CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC7CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC7CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC0CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC0DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC0DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC1DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC1DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC2DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC2DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC3DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC3DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC4DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC4DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC5DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC5DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC6DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC6DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC7DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC7DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== SQCH1DSC0DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC1DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC2DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC3DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC4DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC5DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC6DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC7DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ==================================================== SQCH1DSC0DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC0DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC0DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC0DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_MRMS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MRCPFB ========================================================= */ + #define R_MRMS_MRCPFB_MPFBEN_Pos (0UL) /*!< MPFBEN (Bit 0) */ + #define R_MRMS_MRCPFB_MPFBEN_Msk (0x1UL) /*!< MPFBEN (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCFREQ ======================================================== */ + #define R_MRMS_MRCFREQ_MRCMHZ_Pos (0UL) /*!< MRCMHZ (Bit 0) */ + #define R_MRMS_MRCFREQ_MRCMHZ_Msk (0x3ffUL) /*!< MRCMHZ (Bitfield-Mask: 0x3ff) */ + #define R_MRMS_MRCFREQ_KEY_Pos (24UL) /*!< KEY (Bit 24) */ + #define R_MRMS_MRCFREQ_KEY_Msk (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== MREFREQ ======================================================== */ + #define R_MRMS_MREFREQ_MREMHZ_Pos (0UL) /*!< MREMHZ (Bit 0) */ + #define R_MRMS_MREFREQ_MREMHZ_Msk (0xffUL) /*!< MREMHZ (Bitfield-Mask: 0xff) */ + #define R_MRMS_MREFREQ_KEY_Pos (24UL) /*!< KEY (Bit 24) */ + #define R_MRMS_MREFREQ_KEY_Msk (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== MRCDECC ======================================================== */ + #define R_MRMS_MRCDECC_DECDISC_Pos (0UL) /*!< DECDISC (Bit 0) */ + #define R_MRMS_MRCDECC_DECDISC_Msk (0x1UL) /*!< DECDISC (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCDECC_ECCSELC_Pos (1UL) /*!< ECCSELC (Bit 1) */ + #define R_MRMS_MRCDECC_ECCSELC_Msk (0x2UL) /*!< ECCSELC (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCDECC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MRCDECC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= MRCRAEINT ======================================================= */ + #define R_MRMS_MRCRAEINT_INTENBDC_Pos (0UL) /*!< INTENBDC (Bit 0) */ + #define R_MRMS_MRCRAEINT_INTENBDC_Msk (0x1UL) /*!< INTENBDC (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCRAEINT_INTENBTC_Pos (1UL) /*!< INTENBTC (Bit 1) */ + #define R_MRMS_MRCRAEINT_INTENBTC_Msk (0x2UL) /*!< INTENBTC (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCRAES ======================================================== */ + #define R_MRMS_MRCRAES_DECERRC_Pos (0UL) /*!< DECERRC (Bit 0) */ + #define R_MRMS_MRCRAES_DECERRC_Msk (0x1UL) /*!< DECERRC (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCRAES_TEDERRC_Pos (1UL) /*!< TEDERRC (Bit 1) */ + #define R_MRMS_MRCRAES_TEDERRC_Msk (0x2UL) /*!< TEDERRC (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCRTEA ======================================================== */ + #define R_MRMS_MRCRTEA_MRCRTEA_Pos (5UL) /*!< MRCRTEA (Bit 5) */ + #define R_MRMS_MRCRTEA_MRCRTEA_Msk (0xffffffe0UL) /*!< MRCRTEA (Bitfield-Mask: 0x7ffffff) */ +/* ======================================================== MRCRDEA ======================================================== */ + #define R_MRMS_MRCRDEA_MRCRDEA_Pos (5UL) /*!< MRCRDEA (Bit 5) */ + #define R_MRMS_MRCRDEA_MRCRDEA_Msk (0xffffffe0UL) /*!< MRCRDEA (Bitfield-Mask: 0x7ffffff) */ +/* ======================================================= MRERAINT ======================================================== */ + #define R_MRMS_MRERAINT_INTENBDE_Pos (0UL) /*!< INTENBDE (Bit 0) */ + #define R_MRMS_MRERAINT_INTENBDE_Msk (0x1UL) /*!< INTENBDE (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRERAINT_INTENBTE_Pos (1UL) /*!< INTENBTE (Bit 1) */ + #define R_MRMS_MRERAINT_INTENBTE_Msk (0x2UL) /*!< INTENBTE (Bitfield-Mask: 0x01) */ +/* ======================================================== MRERAES ======================================================== */ + #define R_MRMS_MRERAES_DECERRE_Pos (0UL) /*!< DECERRE (Bit 0) */ + #define R_MRMS_MRERAES_DECERRE_Msk (0x1UL) /*!< DECERRE (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRERAES_TEDERRE_Pos (1UL) /*!< TEDERRE (Bit 1) */ + #define R_MRMS_MRERAES_TEDERRE_Msk (0x2UL) /*!< TEDERRE (Bitfield-Mask: 0x01) */ +/* ======================================================== MRERTEA ======================================================== */ + #define R_MRMS_MRERTEA_MRERTEA_Pos (4UL) /*!< MRERTEA (Bit 4) */ + #define R_MRMS_MRERTEA_MRERTEA_Msk (0xfffffff0UL) /*!< MRERTEA (Bitfield-Mask: 0xfffffff) */ +/* ======================================================== MRERDEA ======================================================== */ + #define R_MRMS_MRERDEA_MRERDEA_Pos (4UL) /*!< MRERDEA (Bit 4) */ + #define R_MRMS_MRERDEA_MRERDEA_Msk (0xfffffff0UL) /*!< MRERDEA (Bitfield-Mask: 0xfffffff) */ +/* ========================================================= MSAR ========================================================== */ + #define R_MRMS_MSAR_MREECCSA_Pos (0UL) /*!< MREECCSA (Bit 0) */ + #define R_MRMS_MSAR_MREECCSA_Msk (0x1UL) /*!< MREECCSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MREFREQSA_Pos (1UL) /*!< MREFREQSA (Bit 1) */ + #define R_MRMS_MSAR_MREFREQSA_Msk (0x2UL) /*!< MREFREQSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MRCECCSA_Pos (2UL) /*!< MRCECCSA (Bit 2) */ + #define R_MRMS_MSAR_MRCECCSA_Msk (0x4UL) /*!< MRCECCSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MRCFREQSA_Pos (3UL) /*!< MRCFREQSA (Bit 3) */ + #define R_MRMS_MSAR_MRCFREQSA_Msk (0x8UL) /*!< MRCFREQSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MPFBENSA_Pos (4UL) /*!< MPFBENSA (Bit 4) */ + #define R_MRMS_MSAR_MPFBENSA_Msk (0x10UL) /*!< MPFBENSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MACICMISA_Pos (9UL) /*!< MACICMISA (Bit 9) */ + #define R_MRMS_MSAR_MACICMISA_Msk (0x200UL) /*!< MACICMISA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MACICMRSA_Pos (10UL) /*!< MACICMRSA (Bit 10) */ + #define R_MRMS_MSAR_MACICMRSA_Msk (0x400UL) /*!< MACICMRSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MACITRSA_Pos (11UL) /*!< MACITRSA (Bit 11) */ + #define R_MRMS_MSAR_MACITRSA_Msk (0x800UL) /*!< MACITRSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MRCPSA_Pos (13UL) /*!< MRCPSA (Bit 13) */ + #define R_MRMS_MSAR_MRCPSA_Msk (0x2000UL) /*!< MRCPSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MREPSEQSA_Pos (14UL) /*!< MREPSEQSA (Bit 14) */ + #define R_MRMS_MSAR_MREPSEQSA_Msk (0x4000UL) /*!< MREPSEQSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MRCPSEQSA_Pos (15UL) /*!< MRCPSEQSA (Bit 15) */ + #define R_MRMS_MSAR_MRCPSEQSA_Msk (0x8000UL) /*!< MRCPSEQSA (Bitfield-Mask: 0x01) */ +/* ========================================================= MREZS ========================================================= */ + #define R_MRMS_MREZS_WHUKZF_Pos (0UL) /*!< WHUKZF (Bit 0) */ + #define R_MRMS_MREZS_WHUKZF_Msk (0x1UL) /*!< WHUKZF (Bitfield-Mask: 0x01) */ + #define R_MRMS_MREZS_WHUKEXE_Pos (1UL) /*!< WHUKEXE (Bit 1) */ + #define R_MRMS_MREZS_WHUKEXE_Msk (0x2UL) /*!< WHUKEXE (Bitfield-Mask: 0x01) */ +/* ========================================================= MREZC ========================================================= */ + #define R_MRMS_MREZC_WHUKZE_Pos (0UL) /*!< WHUKZE (Bit 0) */ + #define R_MRMS_MREZC_WHUKZE_Msk (0x7UL) /*!< WHUKZE (Bitfield-Mask: 0x07) */ + #define R_MRMS_MREZC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MREZC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== MASTAT ========================================================= */ + #define R_MRMS_MASTAT_MREAE_Pos (3UL) /*!< MREAE (Bit 3) */ + #define R_MRMS_MASTAT_MREAE_Msk (0x8UL) /*!< MREAE (Bitfield-Mask: 0x01) */ + #define R_MRMS_MASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */ + #define R_MRMS_MASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */ +/* ======================================================== MPAEINT ======================================================== */ + #define R_MRMS_MPAEINT_MREAEIE_Pos (3UL) /*!< MREAEIE (Bit 3) */ + #define R_MRMS_MPAEINT_MREAEIE_Msk (0x8UL) /*!< MREAEIE (Bitfield-Mask: 0x01) */ + #define R_MRMS_MPAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */ + #define R_MRMS_MPAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */ +/* ======================================================== MRDYIE ========================================================= */ + #define R_MRMS_MRDYIE_MRDYIE_Pos (0UL) /*!< MRDYIE (Bit 0) */ + #define R_MRMS_MRDYIE_MRDYIE_Msk (0x1UL) /*!< MRDYIE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSADDR ========================================================= */ + #define R_MRMS_MSADDR_MSADDR_Pos (0UL) /*!< MSADDR (Bit 0) */ + #define R_MRMS_MSADDR_MSADDR_Msk (0xffffffffUL) /*!< MSADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= MCNTSELR ======================================================== */ + #define R_MRMS_MCNTSELR_CNTSEL_Pos (0UL) /*!< CNTSEL (Bit 0) */ + #define R_MRMS_MCNTSELR_CNTSEL_Msk (0x7UL) /*!< CNTSEL (Bitfield-Mask: 0x07) */ +/* ======================================================= MCNTDTR0 ======================================================== */ + #define R_MRMS_MCNTDTR0_CNTRDAT_Pos (0UL) /*!< CNTRDAT (Bit 0) */ + #define R_MRMS_MCNTDTR0_CNTRDAT_Msk (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= MCNTDTR1 ======================================================== */ + #define R_MRMS_MCNTDTR1_CNTRDAT_Pos (0UL) /*!< CNTRDAT (Bit 0) */ + #define R_MRMS_MCNTDTR1_CNTRDAT_Msk (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= MCTRCNTR ======================================================== */ + #define R_MRMS_MCTRCNTR_TRTRG_Pos (0UL) /*!< TRTRG (Bit 0) */ + #define R_MRMS_MCTRCNTR_TRTRG_Msk (0x1UL) /*!< TRTRG (Bitfield-Mask: 0x01) */ + #define R_MRMS_MCTRCNTR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MCTRCNTR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== MCTRLSR ======================================================== */ + #define R_MRMS_MCTRLSR_TRLIST_Pos (0UL) /*!< TRLIST (Bit 0) */ + #define R_MRMS_MCTRLSR_TRLIST_Msk (0x7UL) /*!< TRLIST (Bitfield-Mask: 0x07) */ +/* ======================================================= MCTRSTATR ======================================================= */ + #define R_MRMS_MCTRSTATR_TRBUSY_Pos (0UL) /*!< TRBUSY (Bit 0) */ + #define R_MRMS_MCTRSTATR_TRBUSY_Msk (0x1UL) /*!< TRBUSY (Bitfield-Mask: 0x01) */ + #define R_MRMS_MCTRSTATR_TRMD_Pos (2UL) /*!< TRMD (Bit 2) */ + #define R_MRMS_MCTRSTATR_TRMD_Msk (0x4UL) /*!< TRMD (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTATR ========================================================= */ + #define R_MRMS_MSTATR_CFGSETERR_Pos (5UL) /*!< CFGSETERR (Bit 5) */ + #define R_MRMS_MSTATR_CFGSETERR_Msk (0x20UL) /*!< CFGSETERR (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */ + #define R_MRMS_MSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */ + #define R_MRMS_MSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSTATR_MRDY_Pos (15UL) /*!< MRDY (Bit 15) */ + #define R_MRMS_MSTATR_MRDY_Msk (0x8000UL) /*!< MRDY (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSTATR_TZFERR_Pos (19UL) /*!< TZFERR (Bit 19) */ + #define R_MRMS_MSTATR_TZFERR_Msk (0x80000UL) /*!< TZFERR (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSTATR_OTERR_Pos (20UL) /*!< OTERR (Bit 20) */ + #define R_MRMS_MSTATR_OTERR_Msk (0x100000UL) /*!< OTERR (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSTATR_SECERR_Pos (21UL) /*!< SECERR (Bit 21) */ + #define R_MRMS_MSTATR_SECERR_Msk (0x200000UL) /*!< SECERR (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSTATR_ILGCOMERR_Pos (23UL) /*!< ILGCOMERR (Bit 23) */ + #define R_MRMS_MSTATR_ILGCOMERR_Msk (0x800000UL) /*!< ILGCOMERR (Bitfield-Mask: 0x01) */ +/* ======================================================== MENTRYR ======================================================== */ + #define R_MRMS_MENTRYR_MENTRY_Pos (7UL) /*!< MENTRY (Bit 7) */ + #define R_MRMS_MENTRYR_MENTRY_Msk (0x80UL) /*!< MENTRY (Bitfield-Mask: 0x01) */ + #define R_MRMS_MENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= MSUINITR ======================================================== */ + #define R_MRMS_MSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */ + #define R_MRMS_MSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================= MCMDR ========================================================= */ + #define R_MRMS_MCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */ + #define R_MRMS_MCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */ + #define R_MRMS_MCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */ + #define R_MRMS_MCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */ +/* ======================================================= MSUASMON ======================================================== */ + #define R_MRMS_MSUASMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */ + #define R_MRMS_MSUASMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSUASMON_BTSIZE_Pos (29UL) /*!< BTSIZE (Bit 29) */ + #define R_MRMS_MSUASMON_BTSIZE_Msk (0x60000000UL) /*!< BTSIZE (Bitfield-Mask: 0x03) */ + #define R_MRMS_MSUASMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */ + #define R_MRMS_MSUASMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */ +/* ======================================================== MSUACR ========================================================= */ + #define R_MRMS_MSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */ + #define R_MRMS_MSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */ + #define R_MRMS_MSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================= MRPSC ========================================================= */ + #define R_MRMS_MRPSC_MHSPEN_Pos (0UL) /*!< MHSPEN (Bit 0) */ + #define R_MRMS_MRPSC_MHSPEN_Msk (0x1UL) /*!< MHSPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCPC0 ========================================================= */ + #define R_MRMS_MRCPC0_MRCPNEN_Pos (0UL) /*!< MRCPNEN (Bit 0) */ + #define R_MRMS_MRCPC0_MRCPNEN_Msk (0x1UL) /*!< MRCPNEN (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCPC0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MRCPC0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== MRCPC1 ========================================================= */ + #define R_MRMS_MRCPC1_MRCPSEN_Pos (0UL) /*!< MRCPSEN (Bit 0) */ + #define R_MRMS_MRCPC1_MRCPSEN_Msk (0x1UL) /*!< MRCPSEN (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCPC1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MRCPC1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= MRCBPROT0 ======================================================= */ + #define R_MRMS_MRCBPROT0_BPCN0_Pos (0UL) /*!< BPCN0 (Bit 0) */ + #define R_MRMS_MRCBPROT0_BPCN0_Msk (0x1UL) /*!< BPCN0 (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCBPROT0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MRCBPROT0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= MRCBPROT1 ======================================================= */ + #define R_MRMS_MRCBPROT1_BPCN1_Pos (0UL) /*!< BPCN1 (Bit 0) */ + #define R_MRMS_MRCBPROT1_BPCN1_Msk (0x1UL) /*!< BPCN1 (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCBPROT1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MRCBPROT1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================= MRCPS ========================================================= */ + #define R_MRMS_MRCPS_PRGERRC_Pos (0UL) /*!< PRGERRC (Bit 0) */ + #define R_MRMS_MRCPS_PRGERRC_Msk (0x1UL) /*!< PRGERRC (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCPS_ECCERRC_Pos (1UL) /*!< ECCERRC (Bit 1) */ + #define R_MRMS_MRCPS_ECCERRC_Msk (0x2UL) /*!< ECCERRC (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCPS_ABUFEMP_Pos (5UL) /*!< ABUFEMP (Bit 5) */ + #define R_MRMS_MRCPS_ABUFEMP_Msk (0x20UL) /*!< ABUFEMP (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCPS_ABUFFULL_Pos (6UL) /*!< ABUFFULL (Bit 6) */ + #define R_MRMS_MRCPS_ABUFFULL_Msk (0x40UL) /*!< ABUFFULL (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCPS_PRGBSYC_Pos (7UL) /*!< PRGBSYC (Bit 7) */ + #define R_MRMS_MRCPS_PRGBSYC_Msk (0x80UL) /*!< PRGBSYC (Bitfield-Mask: 0x01) */ +/* ======================================================= MRCPAEINT ======================================================= */ + #define R_MRMS_MRCPAEINT_MRCAEIE_Pos (7UL) /*!< MRCAEIE (Bit 7) */ + #define R_MRMS_MRCPAEINT_MRCAEIE_Msk (0x80UL) /*!< MRCAEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCPEA ========================================================= */ + #define R_MRMS_MRCPEA_MCPEA_Pos (5UL) /*!< MCPEA (Bit 5) */ + #define R_MRMS_MRCPEA_MCPEA_Msk (0xffffffe0UL) /*!< MCPEA (Bitfield-Mask: 0x7ffffff) */ +/* ======================================================== MRCFLR ========================================================= */ + #define R_MRMS_MRCFLR_MRCFL_Pos (0UL) /*!< MRCFL (Bit 0) */ + #define R_MRMS_MRCFLR_MRCFL_Msk (0x1UL) /*!< MRCFL (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCFLR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MRCFLR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== MRCEECC ======================================================== */ + #define R_MRMS_MRCEECC_ECCBYPC_Pos (0UL) /*!< ECCBYPC (Bit 0) */ + #define R_MRMS_MRCEECC_ECCBYPC_Msk (0x1UL) /*!< ECCBYPC (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCEECC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MRCEECC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_NPU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_NPU_ID_arch_major_rev_Pos (28UL) /*!< arch_major_rev (Bit 28) */ + #define R_NPU_ID_arch_major_rev_Msk (0xf0000000UL) /*!< arch_major_rev (Bitfield-Mask: 0x0f) */ + #define R_NPU_ID_arch_minor_rev_Pos (20UL) /*!< arch_minor_rev (Bit 20) */ + #define R_NPU_ID_arch_minor_rev_Msk (0xff00000UL) /*!< arch_minor_rev (Bitfield-Mask: 0xff) */ + #define R_NPU_ID_arch_patch_rev_Pos (16UL) /*!< arch_patch_rev (Bit 16) */ + #define R_NPU_ID_arch_patch_rev_Msk (0xf0000UL) /*!< arch_patch_rev (Bitfield-Mask: 0x0f) */ + #define R_NPU_ID_product_major_Pos (12UL) /*!< product_major (Bit 12) */ + #define R_NPU_ID_product_major_Msk (0xf000UL) /*!< product_major (Bitfield-Mask: 0x0f) */ + #define R_NPU_ID_version_major_Pos (8UL) /*!< version_major (Bit 8) */ + #define R_NPU_ID_version_major_Msk (0xf00UL) /*!< version_major (Bitfield-Mask: 0x0f) */ + #define R_NPU_ID_version_minor_Pos (4UL) /*!< version_minor (Bit 4) */ + #define R_NPU_ID_version_minor_Msk (0xf0UL) /*!< version_minor (Bitfield-Mask: 0x0f) */ + #define R_NPU_ID_version_status_Pos (0UL) /*!< version_status (Bit 0) */ + #define R_NPU_ID_version_status_Msk (0xfUL) /*!< version_status (Bitfield-Mask: 0x0f) */ +/* ======================================================== STATUS ========================================================= */ + #define R_NPU_STATUS_irq_history_mask_Pos (16UL) /*!< irq_history_mask (Bit 16) */ + #define R_NPU_STATUS_irq_history_mask_Msk (0xffff0000UL) /*!< irq_history_mask (Bitfield-Mask: 0xffff) */ + #define R_NPU_STATUS_faulting_channel_Pos (12UL) /*!< faulting_channel (Bit 12) */ + #define R_NPU_STATUS_faulting_channel_Msk (0xf000UL) /*!< faulting_channel (Bitfield-Mask: 0x0f) */ + #define R_NPU_STATUS_faulting_interface_Pos (11UL) /*!< faulting_interface (Bit 11) */ + #define R_NPU_STATUS_faulting_interface_Msk (0x800UL) /*!< faulting_interface (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_ecc_fault_Pos (8UL) /*!< ecc_fault (Bit 8) */ + #define R_NPU_STATUS_ecc_fault_Msk (0x100UL) /*!< ecc_fault (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_pmu_irq_raised_Pos (6UL) /*!< pmu_irq_raised (Bit 6) */ + #define R_NPU_STATUS_pmu_irq_raised_Msk (0x40UL) /*!< pmu_irq_raised (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_cmd_end_reached_Pos (5UL) /*!< cmd_end_reached (Bit 5) */ + #define R_NPU_STATUS_cmd_end_reached_Msk (0x20UL) /*!< cmd_end_reached (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_cmd_parse_error_Pos (4UL) /*!< cmd_parse_error (Bit 4) */ + #define R_NPU_STATUS_cmd_parse_error_Msk (0x10UL) /*!< cmd_parse_error (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_reset_status_Pos (3UL) /*!< reset_status (Bit 3) */ + #define R_NPU_STATUS_reset_status_Msk (0x8UL) /*!< reset_status (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_bus_status_Pos (2UL) /*!< bus_status (Bit 2) */ + #define R_NPU_STATUS_bus_status_Msk (0x4UL) /*!< bus_status (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_irq_raised_Pos (1UL) /*!< irq_raised (Bit 1) */ + #define R_NPU_STATUS_irq_raised_Msk (0x2UL) /*!< irq_raised (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_state_Pos (0UL) /*!< state (Bit 0) */ + #define R_NPU_STATUS_state_Msk (0x1UL) /*!< state (Bitfield-Mask: 0x01) */ +/* ========================================================== CMD ========================================================== */ + #define R_NPU_CMD_clear_irq_history_Pos (16UL) /*!< clear_irq_history (Bit 16) */ + #define R_NPU_CMD_clear_irq_history_Msk (0xffff0000UL) /*!< clear_irq_history (Bitfield-Mask: 0xffff) */ + #define R_NPU_CMD_power_q_enable_Pos (3UL) /*!< power_q_enable (Bit 3) */ + #define R_NPU_CMD_power_q_enable_Msk (0x8UL) /*!< power_q_enable (Bitfield-Mask: 0x01) */ + #define R_NPU_CMD_clock_q_enable_Pos (2UL) /*!< clock_q_enable (Bit 2) */ + #define R_NPU_CMD_clock_q_enable_Msk (0x4UL) /*!< clock_q_enable (Bitfield-Mask: 0x01) */ + #define R_NPU_CMD_clear_irq_Pos (1UL) /*!< clear_irq (Bit 1) */ + #define R_NPU_CMD_clear_irq_Msk (0x2UL) /*!< clear_irq (Bitfield-Mask: 0x01) */ + #define R_NPU_CMD_transition_to_running_state_Pos (0UL) /*!< transition_to_running_state (Bit 0) */ + #define R_NPU_CMD_transition_to_running_state_Msk (0x1UL) /*!< transition_to_running_state (Bitfield-Mask: 0x01) */ +/* ========================================================= RESET ========================================================= */ + #define R_NPU_RESET_pending_CSL_Pos (1UL) /*!< pending_CSL (Bit 1) */ + #define R_NPU_RESET_pending_CSL_Msk (0x2UL) /*!< pending_CSL (Bitfield-Mask: 0x01) */ + #define R_NPU_RESET_pending_CPL_Pos (0UL) /*!< pending_CPL (Bit 0) */ + #define R_NPU_RESET_pending_CPL_Msk (0x1UL) /*!< pending_CPL (Bitfield-Mask: 0x01) */ +/* ======================================================== QBASE0 ========================================================= */ + #define R_NPU_QBASE0_QBASE0_Pos (0UL) /*!< QBASE0 (Bit 0) */ + #define R_NPU_QBASE0_QBASE0_Msk (0xffffffffUL) /*!< QBASE0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== QBASE1 ========================================================= */ + #define R_NPU_QBASE1_QBASE1_Pos (0UL) /*!< QBASE1 (Bit 0) */ + #define R_NPU_QBASE1_QBASE1_Msk (0xffffffffUL) /*!< QBASE1 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= QREAD ========================================================= */ + #define R_NPU_QREAD_QREAD_Pos (0UL) /*!< QREAD (Bit 0) */ + #define R_NPU_QREAD_QREAD_Msk (0xffffffffUL) /*!< QREAD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== QCONFIG ======================================================== */ + #define R_NPU_QCONFIG_QCONFIG_Pos (0UL) /*!< QCONFIG (Bit 0) */ + #define R_NPU_QCONFIG_QCONFIG_Msk (0xffffffffUL) /*!< QCONFIG (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= QSIZE ========================================================= */ + #define R_NPU_QSIZE_QSIZE_Pos (0UL) /*!< QSIZE (Bit 0) */ + #define R_NPU_QSIZE_QSIZE_Msk (0xffffffffUL) /*!< QSIZE (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PROT ========================================================== */ + #define R_NPU_PROT_active_CSL_Pos (1UL) /*!< active_CSL (Bit 1) */ + #define R_NPU_PROT_active_CSL_Msk (0x2UL) /*!< active_CSL (Bitfield-Mask: 0x01) */ + #define R_NPU_PROT_active_CPL_Pos (0UL) /*!< active_CPL (Bit 0) */ + #define R_NPU_PROT_active_CPL_Msk (0x1UL) /*!< active_CPL (Bitfield-Mask: 0x01) */ +/* ======================================================== CONFIG ========================================================= */ + #define R_NPU_CONFIG_product_Pos (28UL) /*!< product (Bit 28) */ + #define R_NPU_CONFIG_product_Msk (0xf0000000UL) /*!< product (Bitfield-Mask: 0x0f) */ + #define R_NPU_CONFIG_custom_dma_Pos (27UL) /*!< custom_dma (Bit 27) */ + #define R_NPU_CONFIG_custom_dma_Msk (0x8000000UL) /*!< custom_dma (Bitfield-Mask: 0x01) */ + #define R_NPU_CONFIG_shram_size_Pos (8UL) /*!< shram_size (Bit 8) */ + #define R_NPU_CONFIG_shram_size_Msk (0xff00UL) /*!< shram_size (Bitfield-Mask: 0xff) */ + #define R_NPU_CONFIG_cmd_stream_version_Pos (4UL) /*!< cmd_stream_version (Bit 4) */ + #define R_NPU_CONFIG_cmd_stream_version_Msk (0xf0UL) /*!< cmd_stream_version (Bitfield-Mask: 0x0f) */ + #define R_NPU_CONFIG_macs_per_cc_Pos (0UL) /*!< macs_per_cc (Bit 0) */ + #define R_NPU_CONFIG_macs_per_cc_Msk (0xfUL) /*!< macs_per_cc (Bitfield-Mask: 0x0f) */ +/* ========================================================= LOCK ========================================================== */ + #define R_NPU_LOCK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ + #define R_NPU_LOCK_LOCK_Msk (0xffffffffUL) /*!< LOCK (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= REGIONCFG ======================================================= */ + #define R_NPU_REGIONCFG_region7_Pos (14UL) /*!< region7 (Bit 14) */ + #define R_NPU_REGIONCFG_region7_Msk (0xc000UL) /*!< region7 (Bitfield-Mask: 0x03) */ + #define R_NPU_REGIONCFG_region6_Pos (12UL) /*!< region6 (Bit 12) */ + #define R_NPU_REGIONCFG_region6_Msk (0x3000UL) /*!< region6 (Bitfield-Mask: 0x03) */ + #define R_NPU_REGIONCFG_region5_Pos (10UL) /*!< region5 (Bit 10) */ + #define R_NPU_REGIONCFG_region5_Msk (0xc00UL) /*!< region5 (Bitfield-Mask: 0x03) */ + #define R_NPU_REGIONCFG_region4_Pos (8UL) /*!< region4 (Bit 8) */ + #define R_NPU_REGIONCFG_region4_Msk (0x300UL) /*!< region4 (Bitfield-Mask: 0x03) */ + #define R_NPU_REGIONCFG_region3_Pos (6UL) /*!< region3 (Bit 6) */ + #define R_NPU_REGIONCFG_region3_Msk (0xc0UL) /*!< region3 (Bitfield-Mask: 0x03) */ + #define R_NPU_REGIONCFG_region2_Pos (4UL) /*!< region2 (Bit 4) */ + #define R_NPU_REGIONCFG_region2_Msk (0x30UL) /*!< region2 (Bitfield-Mask: 0x03) */ + #define R_NPU_REGIONCFG_region1_Pos (2UL) /*!< region1 (Bit 2) */ + #define R_NPU_REGIONCFG_region1_Msk (0xcUL) /*!< region1 (Bitfield-Mask: 0x03) */ + #define R_NPU_REGIONCFG_region0_Pos (0UL) /*!< region0 (Bit 0) */ + #define R_NPU_REGIONCFG_region0_Msk (0x3UL) /*!< region0 (Bitfield-Mask: 0x03) */ +/* ====================================================== AXI_LIMIT0 ======================================================= */ + #define R_NPU_AXI_LIMIT0_max_outstanding_write_m1_Pos (24UL) /*!< max_outstanding_write_m1 (Bit 24) */ + #define R_NPU_AXI_LIMIT0_max_outstanding_write_m1_Msk (0xff000000UL) /*!< max_outstanding_write_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT0_max_outstanding_read_m1_Pos (16UL) /*!< max_outstanding_read_m1 (Bit 16) */ + #define R_NPU_AXI_LIMIT0_max_outstanding_read_m1_Msk (0xff0000UL) /*!< max_outstanding_read_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT0_memtype_Pos (4UL) /*!< memtype (Bit 4) */ + #define R_NPU_AXI_LIMIT0_memtype_Msk (0xf0UL) /*!< memtype (Bitfield-Mask: 0x0f) */ + #define R_NPU_AXI_LIMIT0_max_beats_Pos (0UL) /*!< max_beats (Bit 0) */ + #define R_NPU_AXI_LIMIT0_max_beats_Msk (0x3UL) /*!< max_beats (Bitfield-Mask: 0x03) */ +/* ====================================================== AXI_LIMIT1 ======================================================= */ + #define R_NPU_AXI_LIMIT1_max_outstanding_write_m1_Pos (24UL) /*!< max_outstanding_write_m1 (Bit 24) */ + #define R_NPU_AXI_LIMIT1_max_outstanding_write_m1_Msk (0xff000000UL) /*!< max_outstanding_write_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT1_max_outstanding_read_m1_Pos (16UL) /*!< max_outstanding_read_m1 (Bit 16) */ + #define R_NPU_AXI_LIMIT1_max_outstanding_read_m1_Msk (0xff0000UL) /*!< max_outstanding_read_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT1_memtype_Pos (4UL) /*!< memtype (Bit 4) */ + #define R_NPU_AXI_LIMIT1_memtype_Msk (0xf0UL) /*!< memtype (Bitfield-Mask: 0x0f) */ + #define R_NPU_AXI_LIMIT1_max_beats_Pos (0UL) /*!< max_beats (Bit 0) */ + #define R_NPU_AXI_LIMIT1_max_beats_Msk (0x3UL) /*!< max_beats (Bitfield-Mask: 0x03) */ +/* ====================================================== AXI_LIMIT2 ======================================================= */ + #define R_NPU_AXI_LIMIT2_max_outstanding_write_m1_Pos (24UL) /*!< max_outstanding_write_m1 (Bit 24) */ + #define R_NPU_AXI_LIMIT2_max_outstanding_write_m1_Msk (0xff000000UL) /*!< max_outstanding_write_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT2_max_outstanding_read_m1_Pos (16UL) /*!< max_outstanding_read_m1 (Bit 16) */ + #define R_NPU_AXI_LIMIT2_max_outstanding_read_m1_Msk (0xff0000UL) /*!< max_outstanding_read_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT2_memtype_Pos (4UL) /*!< memtype (Bit 4) */ + #define R_NPU_AXI_LIMIT2_memtype_Msk (0xf0UL) /*!< memtype (Bitfield-Mask: 0x0f) */ + #define R_NPU_AXI_LIMIT2_max_beats_Pos (0UL) /*!< max_beats (Bit 0) */ + #define R_NPU_AXI_LIMIT2_max_beats_Msk (0x3UL) /*!< max_beats (Bitfield-Mask: 0x03) */ +/* ====================================================== AXI_LIMIT3 ======================================================= */ + #define R_NPU_AXI_LIMIT3_max_outstanding_write_m1_Pos (24UL) /*!< max_outstanding_write_m1 (Bit 24) */ + #define R_NPU_AXI_LIMIT3_max_outstanding_write_m1_Msk (0xff000000UL) /*!< max_outstanding_write_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT3_max_outstanding_read_m1_Pos (16UL) /*!< max_outstanding_read_m1 (Bit 16) */ + #define R_NPU_AXI_LIMIT3_max_outstanding_read_m1_Msk (0xff0000UL) /*!< max_outstanding_read_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT3_memtype_Pos (4UL) /*!< memtype (Bit 4) */ + #define R_NPU_AXI_LIMIT3_memtype_Msk (0xf0UL) /*!< memtype (Bitfield-Mask: 0x0f) */ + #define R_NPU_AXI_LIMIT3_max_beats_Pos (0UL) /*!< max_beats (Bit 0) */ + #define R_NPU_AXI_LIMIT3_max_beats_Msk (0x3UL) /*!< max_beats (Bitfield-Mask: 0x03) */ +/* ======================================================== BASEP0 ========================================================= */ + #define R_NPU_BASEP0_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP0_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP1 ========================================================= */ + #define R_NPU_BASEP1_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP1_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP2 ========================================================= */ + #define R_NPU_BASEP2_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP2_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP3 ========================================================= */ + #define R_NPU_BASEP3_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP3_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP4 ========================================================= */ + #define R_NPU_BASEP4_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP4_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP5 ========================================================= */ + #define R_NPU_BASEP5_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP5_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP6 ========================================================= */ + #define R_NPU_BASEP6_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP6_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP7 ========================================================= */ + #define R_NPU_BASEP7_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP7_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP8 ========================================================= */ + #define R_NPU_BASEP8_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP8_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP9 ========================================================= */ + #define R_NPU_BASEP9_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP9_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP10 ======================================================== */ + #define R_NPU_BASEP10_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP10_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP11 ======================================================== */ + #define R_NPU_BASEP11_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP11_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP12 ======================================================== */ + #define R_NPU_BASEP12_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP12_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP13 ======================================================== */ + #define R_NPU_BASEP13_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP13_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP14 ======================================================== */ + #define R_NPU_BASEP14_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP14_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP15 ======================================================== */ + #define R_NPU_BASEP15_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP15_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID4 ========================================================== */ + #define R_NPU_PID4_PID4_Pos (0UL) /*!< PID4 (Bit 0) */ + #define R_NPU_PID4_PID4_Msk (0xffffffffUL) /*!< PID4 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID5 ========================================================== */ + #define R_NPU_PID5_PID5_Pos (0UL) /*!< PID5 (Bit 0) */ + #define R_NPU_PID5_PID5_Msk (0xffffffffUL) /*!< PID5 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID6 ========================================================== */ + #define R_NPU_PID6_PID6_Pos (0UL) /*!< PID6 (Bit 0) */ + #define R_NPU_PID6_PID6_Msk (0xffffffffUL) /*!< PID6 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID7 ========================================================== */ + #define R_NPU_PID7_PID7_Pos (0UL) /*!< PID7 (Bit 0) */ + #define R_NPU_PID7_PID7_Msk (0xffffffffUL) /*!< PID7 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID0 ========================================================== */ + #define R_NPU_PID0_PID0_Pos (0UL) /*!< PID0 (Bit 0) */ + #define R_NPU_PID0_PID0_Msk (0xffffffffUL) /*!< PID0 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID1 ========================================================== */ + #define R_NPU_PID1_PID1_Pos (0UL) /*!< PID1 (Bit 0) */ + #define R_NPU_PID1_PID1_Msk (0xffffffffUL) /*!< PID1 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID2 ========================================================== */ + #define R_NPU_PID2_PID2_Pos (0UL) /*!< PID2 (Bit 0) */ + #define R_NPU_PID2_PID2_Msk (0xffffffffUL) /*!< PID2 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID3 ========================================================== */ + #define R_NPU_PID3_PID3_Pos (0UL) /*!< PID3 (Bit 0) */ + #define R_NPU_PID3_PID3_Msk (0xffffffffUL) /*!< PID3 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CID0 ========================================================== */ + #define R_NPU_CID0_CID0_Pos (0UL) /*!< CID0 (Bit 0) */ + #define R_NPU_CID0_CID0_Msk (0xffffffffUL) /*!< CID0 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CID1 ========================================================== */ + #define R_NPU_CID1_CID1_Pos (0UL) /*!< CID1 (Bit 0) */ + #define R_NPU_CID1_CID1_Msk (0xffffffffUL) /*!< CID1 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CID2 ========================================================== */ + #define R_NPU_CID2_CID2_Pos (0UL) /*!< CID2 (Bit 0) */ + #define R_NPU_CID2_CID2_Msk (0xffffffffUL) /*!< CID2 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CID3 ========================================================== */ + #define R_NPU_CID3_CID3_Pos (0UL) /*!< CID3 (Bit 0) */ + #define R_NPU_CID3_CID3_Msk (0xffffffffUL) /*!< CID3 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PMCR ========================================================== */ + #define R_NPU_PMCR_num_event_cnt_Pos (11UL) /*!< num_event_cnt (Bit 11) */ + #define R_NPU_PMCR_num_event_cnt_Msk (0xf800UL) /*!< num_event_cnt (Bitfield-Mask: 0x1f) */ + #define R_NPU_PMCR_mask_en_Pos (3UL) /*!< mask_en (Bit 3) */ + #define R_NPU_PMCR_mask_en_Msk (0x8UL) /*!< mask_en (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCR_cycle_cnt_rst_Pos (2UL) /*!< cycle_cnt_rst (Bit 2) */ + #define R_NPU_PMCR_cycle_cnt_rst_Msk (0x4UL) /*!< cycle_cnt_rst (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCR_event_cnt_rst_Pos (1UL) /*!< event_cnt_rst (Bit 1) */ + #define R_NPU_PMCR_event_cnt_rst_Msk (0x2UL) /*!< event_cnt_rst (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCR_cnt_en_Pos (0UL) /*!< cnt_en (Bit 0) */ + #define R_NPU_PMCR_cnt_en_Msk (0x1UL) /*!< cnt_en (Bitfield-Mask: 0x01) */ +/* ====================================================== PMCNTENSET ======================================================= */ + #define R_NPU_PMCNTENSET_CYCLE_CNT_Pos (31UL) /*!< CYCLE_CNT (Bit 31) */ + #define R_NPU_PMCNTENSET_CYCLE_CNT_Msk (0x80000000UL) /*!< CYCLE_CNT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_3_Pos (3UL) /*!< EVENT_CNT_3 (Bit 3) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_3_Msk (0x8UL) /*!< EVENT_CNT_3 (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_2_Pos (2UL) /*!< EVENT_CNT_2 (Bit 2) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_2_Msk (0x4UL) /*!< EVENT_CNT_2 (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_1_Pos (1UL) /*!< EVENT_CNT_1 (Bit 1) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_1_Msk (0x2UL) /*!< EVENT_CNT_1 (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_0_Pos (0UL) /*!< EVENT_CNT_0 (Bit 0) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_0_Msk (0x1UL) /*!< EVENT_CNT_0 (Bitfield-Mask: 0x01) */ +/* ====================================================== PMCNTENCLR ======================================================= */ + #define R_NPU_PMCNTENCLR_CYCLE_CNT_Pos (31UL) /*!< CYCLE_CNT (Bit 31) */ + #define R_NPU_PMCNTENCLR_CYCLE_CNT_Msk (0x80000000UL) /*!< CYCLE_CNT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_3_Pos (3UL) /*!< EVENT_CNT_3 (Bit 3) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_3_Msk (0x8UL) /*!< EVENT_CNT_3 (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_2_Pos (2UL) /*!< EVENT_CNT_2 (Bit 2) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_2_Msk (0x4UL) /*!< EVENT_CNT_2 (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_1_Pos (1UL) /*!< EVENT_CNT_1 (Bit 1) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_1_Msk (0x2UL) /*!< EVENT_CNT_1 (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_0_Pos (0UL) /*!< EVENT_CNT_0 (Bit 0) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_0_Msk (0x1UL) /*!< EVENT_CNT_0 (Bitfield-Mask: 0x01) */ +/* ======================================================= PMOVSSET ======================================================== */ + #define R_NPU_PMOVSSET_CYCLE_CNT_OVF_Pos (31UL) /*!< CYCLE_CNT_OVF (Bit 31) */ + #define R_NPU_PMOVSSET_CYCLE_CNT_OVF_Msk (0x80000000UL) /*!< CYCLE_CNT_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSSET_EVENT_CNT_3_OVF_Pos (3UL) /*!< EVENT_CNT_3_OVF (Bit 3) */ + #define R_NPU_PMOVSSET_EVENT_CNT_3_OVF_Msk (0x8UL) /*!< EVENT_CNT_3_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSSET_EVENT_CNT_2_OVF_Pos (2UL) /*!< EVENT_CNT_2_OVF (Bit 2) */ + #define R_NPU_PMOVSSET_EVENT_CNT_2_OVF_Msk (0x4UL) /*!< EVENT_CNT_2_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSSET_EVENT_CNT_1_OVF_Pos (1UL) /*!< EVENT_CNT_1_OVF (Bit 1) */ + #define R_NPU_PMOVSSET_EVENT_CNT_1_OVF_Msk (0x2UL) /*!< EVENT_CNT_1_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSSET_EVENT_CNT_0_OVF_Pos (0UL) /*!< EVENT_CNT_0_OVF (Bit 0) */ + #define R_NPU_PMOVSSET_EVENT_CNT_0_OVF_Msk (0x1UL) /*!< EVENT_CNT_0_OVF (Bitfield-Mask: 0x01) */ +/* ======================================================= PMOVSCLR ======================================================== */ + #define R_NPU_PMOVSCLR_CYCLE_CNT_OVF_Pos (31UL) /*!< CYCLE_CNT_OVF (Bit 31) */ + #define R_NPU_PMOVSCLR_CYCLE_CNT_OVF_Msk (0x80000000UL) /*!< CYCLE_CNT_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_3_OVF_Pos (3UL) /*!< EVENT_CNT_3_OVF (Bit 3) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_3_OVF_Msk (0x8UL) /*!< EVENT_CNT_3_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_2_OVF_Pos (2UL) /*!< EVENT_CNT_2_OVF (Bit 2) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_2_OVF_Msk (0x4UL) /*!< EVENT_CNT_2_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_1_OVF_Pos (1UL) /*!< EVENT_CNT_1_OVF (Bit 1) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_1_OVF_Msk (0x2UL) /*!< EVENT_CNT_1_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_0_OVF_Pos (0UL) /*!< EVENT_CNT_0_OVF (Bit 0) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_0_OVF_Msk (0x1UL) /*!< EVENT_CNT_0_OVF (Bitfield-Mask: 0x01) */ +/* ======================================================= PMINTSET ======================================================== */ + #define R_NPU_PMINTSET_CYCLE_CNT_INT_Pos (31UL) /*!< CYCLE_CNT_INT (Bit 31) */ + #define R_NPU_PMINTSET_CYCLE_CNT_INT_Msk (0x80000000UL) /*!< CYCLE_CNT_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTSET_EVENT_CNT_3_INT_Pos (3UL) /*!< EVENT_CNT_3_INT (Bit 3) */ + #define R_NPU_PMINTSET_EVENT_CNT_3_INT_Msk (0x8UL) /*!< EVENT_CNT_3_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTSET_EVENT_CNT_2_INT_Pos (2UL) /*!< EVENT_CNT_2_INT (Bit 2) */ + #define R_NPU_PMINTSET_EVENT_CNT_2_INT_Msk (0x4UL) /*!< EVENT_CNT_2_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTSET_EVENT_CNT_1_INT_Pos (1UL) /*!< EVENT_CNT_1_INT (Bit 1) */ + #define R_NPU_PMINTSET_EVENT_CNT_1_INT_Msk (0x2UL) /*!< EVENT_CNT_1_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTSET_EVENT_CNT_0_INT_Pos (0UL) /*!< EVENT_CNT_0_INT (Bit 0) */ + #define R_NPU_PMINTSET_EVENT_CNT_0_INT_Msk (0x1UL) /*!< EVENT_CNT_0_INT (Bitfield-Mask: 0x01) */ +/* ======================================================= PMINTCLR ======================================================== */ + #define R_NPU_PMINTCLR_CYCLE_CNT_INT_Pos (31UL) /*!< CYCLE_CNT_INT (Bit 31) */ + #define R_NPU_PMINTCLR_CYCLE_CNT_INT_Msk (0x80000000UL) /*!< CYCLE_CNT_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTCLR_EVENT_CNT_3_INT_Pos (3UL) /*!< EVENT_CNT_3_INT (Bit 3) */ + #define R_NPU_PMINTCLR_EVENT_CNT_3_INT_Msk (0x8UL) /*!< EVENT_CNT_3_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTCLR_EVENT_CNT_2_INT_Pos (2UL) /*!< EVENT_CNT_2_INT (Bit 2) */ + #define R_NPU_PMINTCLR_EVENT_CNT_2_INT_Msk (0x4UL) /*!< EVENT_CNT_2_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTCLR_EVENT_CNT_1_INT_Pos (1UL) /*!< EVENT_CNT_1_INT (Bit 1) */ + #define R_NPU_PMINTCLR_EVENT_CNT_1_INT_Msk (0x2UL) /*!< EVENT_CNT_1_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTCLR_EVENT_CNT_0_INT_Pos (0UL) /*!< EVENT_CNT_0_INT (Bit 0) */ + #define R_NPU_PMINTCLR_EVENT_CNT_0_INT_Msk (0x1UL) /*!< EVENT_CNT_0_INT (Bitfield-Mask: 0x01) */ +/* ====================================================== PMCCNTR_LO ======================================================= */ + #define R_NPU_PMCCNTR_LO_CYCLE_CNT_LO_Pos (0UL) /*!< CYCLE_CNT_LO (Bit 0) */ + #define R_NPU_PMCCNTR_LO_CYCLE_CNT_LO_Msk (0xffffffffUL) /*!< CYCLE_CNT_LO (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PMCCNTR_HI ======================================================= */ + #define R_NPU_PMCCNTR_HI_CYCLE_CNT_HI_Pos (0UL) /*!< CYCLE_CNT_HI (Bit 0) */ + #define R_NPU_PMCCNTR_HI_CYCLE_CNT_HI_Msk (0xffffffffUL) /*!< CYCLE_CNT_HI (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PMCAXI_CHAN ====================================================== */ + #define R_NPU_PMCAXI_CHAN_BW_CH_SEL_EN_Pos (10UL) /*!< BW_CH_SEL_EN (Bit 10) */ + #define R_NPU_PMCAXI_CHAN_BW_CH_SEL_EN_Msk (0x400UL) /*!< BW_CH_SEL_EN (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCAXI_CHAN_AXI_CNT_SEL_Pos (8UL) /*!< AXI_CNT_SEL (Bit 8) */ + #define R_NPU_PMCAXI_CHAN_AXI_CNT_SEL_Msk (0x300UL) /*!< AXI_CNT_SEL (Bitfield-Mask: 0x03) */ + #define R_NPU_PMCAXI_CHAN_CH_SEL_Pos (0UL) /*!< CH_SEL (Bit 0) */ + #define R_NPU_PMCAXI_CHAN_CH_SEL_Msk (0xfUL) /*!< CH_SEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== PMU_EVCNTR0 ====================================================== */ + #define R_NPU_PMU_EVCNTR0_PMEVCNTR_Pos (0UL) /*!< PMEVCNTR (Bit 0) */ + #define R_NPU_PMU_EVCNTR0_PMEVCNTR_Msk (0xffffffffUL) /*!< PMEVCNTR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PMU_EVCNTR1 ====================================================== */ + #define R_NPU_PMU_EVCNTR1_PMEVCNTR_Pos (0UL) /*!< PMEVCNTR (Bit 0) */ + #define R_NPU_PMU_EVCNTR1_PMEVCNTR_Msk (0xffffffffUL) /*!< PMEVCNTR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PMU_EVCNTR2 ====================================================== */ + #define R_NPU_PMU_EVCNTR2_PMEVCNTR_Pos (0UL) /*!< PMEVCNTR (Bit 0) */ + #define R_NPU_PMU_EVCNTR2_PMEVCNTR_Msk (0xffffffffUL) /*!< PMEVCNTR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PMU_EVCNTR3 ====================================================== */ + #define R_NPU_PMU_EVCNTR3_PMEVCNTR_Pos (0UL) /*!< PMEVCNTR (Bit 0) */ + #define R_NPU_PMU_EVCNTR3_PMEVCNTR_Msk (0xffffffffUL) /*!< PMEVCNTR (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== PMU_EVTYPER0 ====================================================== */ + #define R_NPU_PMU_EVTYPER0_EV_TYPE_Pos (0UL) /*!< EV_TYPE (Bit 0) */ + #define R_NPU_PMU_EVTYPER0_EV_TYPE_Msk (0xffffffffUL) /*!< EV_TYPE (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== PMU_EVTYPER1 ====================================================== */ + #define R_NPU_PMU_EVTYPER1_EV_TYPE_Pos (0UL) /*!< EV_TYPE (Bit 0) */ + #define R_NPU_PMU_EVTYPER1_EV_TYPE_Msk (0xffffffffUL) /*!< EV_TYPE (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== PMU_EVTYPER2 ====================================================== */ + #define R_NPU_PMU_EVTYPER2_EV_TYPE_Pos (0UL) /*!< EV_TYPE (Bit 0) */ + #define R_NPU_PMU_EVTYPER2_EV_TYPE_Msk (0xffffffffUL) /*!< EV_TYPE (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== PMU_EVTYPER3 ====================================================== */ + #define R_NPU_PMU_EVTYPER3_EV_TYPE_Pos (0UL) /*!< EV_TYPE (Bit 0) */ + #define R_NPU_PMU_EVTYPER3_EV_TYPE_Msk (0xffffffffUL) /*!< EV_TYPE (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_PDM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PDCSTRTR ======================================================== */ + #define R_PDM_PDCSTRTR_STRTRG0_Pos (0UL) /*!< STRTRG0 (Bit 0) */ + #define R_PDM_PDCSTRTR_STRTRG0_Msk (0x1UL) /*!< STRTRG0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSTRTR_STRTRG1_Pos (1UL) /*!< STRTRG1 (Bit 1) */ + #define R_PDM_PDCSTRTR_STRTRG1_Msk (0x2UL) /*!< STRTRG1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSTRTR_STRTRG2_Pos (2UL) /*!< STRTRG2 (Bit 2) */ + #define R_PDM_PDCSTRTR_STRTRG2_Msk (0x4UL) /*!< STRTRG2 (Bitfield-Mask: 0x01) */ +/* ======================================================= PDCSTPTR ======================================================== */ + #define R_PDM_PDCSTPTR_STPTRG0_Pos (0UL) /*!< STPTRG0 (Bit 0) */ + #define R_PDM_PDCSTPTR_STPTRG0_Msk (0x1UL) /*!< STPTRG0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSTPTR_STPTRG1_Pos (1UL) /*!< STPTRG1 (Bit 1) */ + #define R_PDM_PDCSTPTR_STPTRG1_Msk (0x2UL) /*!< STPTRG1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSTPTR_STPTRG2_Pos (2UL) /*!< STPTRG2 (Bit 2) */ + #define R_PDM_PDCSTPTR_STPTRG2_Msk (0x4UL) /*!< STPTRG2 (Bitfield-Mask: 0x01) */ +/* ======================================================= PDCCHGTR ======================================================== */ + #define R_PDM_PDCCHGTR_CHGTRG0_Pos (0UL) /*!< CHGTRG0 (Bit 0) */ + #define R_PDM_PDCCHGTR_CHGTRG0_Msk (0x1UL) /*!< CHGTRG0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCCHGTR_CHGTRG1_Pos (1UL) /*!< CHGTRG1 (Bit 1) */ + #define R_PDM_PDCCHGTR_CHGTRG1_Msk (0x2UL) /*!< CHGTRG1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCCHGTR_CHGTRG2_Pos (2UL) /*!< CHGTRG2 (Bit 2) */ + #define R_PDM_PDCCHGTR_CHGTRG2_Msk (0x4UL) /*!< CHGTRG2 (Bitfield-Mask: 0x01) */ +/* ======================================================== PDCICR ========================================================= */ + #define R_PDM_PDCICR_ISDE0_Pos (8UL) /*!< ISDE0 (Bit 8) */ + #define R_PDM_PDCICR_ISDE0_Msk (0x100UL) /*!< ISDE0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_ISDE1_Pos (9UL) /*!< ISDE1 (Bit 9) */ + #define R_PDM_PDCICR_ISDE1_Msk (0x200UL) /*!< ISDE1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_ISDE2_Pos (10UL) /*!< ISDE2 (Bit 10) */ + #define R_PDM_PDCICR_ISDE2_Msk (0x400UL) /*!< ISDE2 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_IDRE0_Pos (16UL) /*!< IDRE0 (Bit 16) */ + #define R_PDM_PDCICR_IDRE0_Msk (0x10000UL) /*!< IDRE0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_IDRE1_Pos (17UL) /*!< IDRE1 (Bit 17) */ + #define R_PDM_PDCICR_IDRE1_Msk (0x20000UL) /*!< IDRE1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_IDRE2_Pos (18UL) /*!< IDRE2 (Bit 18) */ + #define R_PDM_PDCICR_IDRE2_Msk (0x40000UL) /*!< IDRE2 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_IEDE0_Pos (24UL) /*!< IEDE0 (Bit 24) */ + #define R_PDM_PDCICR_IEDE0_Msk (0x1000000UL) /*!< IEDE0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_IEDE1_Pos (25UL) /*!< IEDE1 (Bit 25) */ + #define R_PDM_PDCICR_IEDE1_Msk (0x2000000UL) /*!< IEDE1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_IEDE2_Pos (26UL) /*!< IEDE2 (Bit 26) */ + #define R_PDM_PDCICR_IEDE2_Msk (0x4000000UL) /*!< IEDE2 (Bitfield-Mask: 0x01) */ +/* ========================================================= PDCSR ========================================================= */ + #define R_PDM_PDCSR_STATE0_Pos (0UL) /*!< STATE0 (Bit 0) */ + #define R_PDM_PDCSR_STATE0_Msk (0x1UL) /*!< STATE0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_STATE1_Pos (1UL) /*!< STATE1 (Bit 1) */ + #define R_PDM_PDCSR_STATE1_Msk (0x2UL) /*!< STATE1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_STATE2_Pos (2UL) /*!< STATE2 (Bit 2) */ + #define R_PDM_PDCSR_STATE2_Msk (0x4UL) /*!< STATE2 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_SDF0_Pos (8UL) /*!< SDF0 (Bit 8) */ + #define R_PDM_PDCSR_SDF0_Msk (0x100UL) /*!< SDF0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_SDF1_Pos (9UL) /*!< SDF1 (Bit 9) */ + #define R_PDM_PDCSR_SDF1_Msk (0x200UL) /*!< SDF1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_SDF2_Pos (10UL) /*!< SDF2 (Bit 10) */ + #define R_PDM_PDCSR_SDF2_Msk (0x400UL) /*!< SDF2 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_DRF0_Pos (16UL) /*!< DRF0 (Bit 16) */ + #define R_PDM_PDCSR_DRF0_Msk (0x10000UL) /*!< DRF0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_DRF1_Pos (17UL) /*!< DRF1 (Bit 17) */ + #define R_PDM_PDCSR_DRF1_Msk (0x20000UL) /*!< DRF1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_DRF2_Pos (18UL) /*!< DRF2 (Bit 18) */ + #define R_PDM_PDCSR_DRF2_Msk (0x40000UL) /*!< DRF2 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_EDF0_Pos (24UL) /*!< EDF0 (Bit 24) */ + #define R_PDM_PDCSR_EDF0_Msk (0x1000000UL) /*!< EDF0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_EDF1_Pos (25UL) /*!< EDF1 (Bit 25) */ + #define R_PDM_PDCSR_EDF1_Msk (0x2000000UL) /*!< EDF1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_EDF2_Pos (26UL) /*!< EDF2 (Bit 26) */ + #define R_PDM_PDCSR_EDF2_Msk (0x4000000UL) /*!< EDF2 (Bitfield-Mask: 0x01) */ +/* ======================================================== PDCSCR ========================================================= */ + #define R_PDM_PDCSCR_SDFC0_Pos (8UL) /*!< SDFC0 (Bit 8) */ + #define R_PDM_PDCSCR_SDFC0_Msk (0x100UL) /*!< SDFC0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSCR_SDFC1_Pos (9UL) /*!< SDFC1 (Bit 9) */ + #define R_PDM_PDCSCR_SDFC1_Msk (0x200UL) /*!< SDFC1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSCR_SDFC2_Pos (10UL) /*!< SDFC2 (Bit 10) */ + #define R_PDM_PDCSCR_SDFC2_Msk (0x400UL) /*!< SDFC2 (Bitfield-Mask: 0x01) */ +/* ======================================================== PDCSDCR ======================================================== */ + #define R_PDM_PDCSDCR_SDE0_Pos (0UL) /*!< SDE0 (Bit 0) */ + #define R_PDM_PDCSDCR_SDE0_Msk (0x1UL) /*!< SDE0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSDCR_SDE1_Pos (1UL) /*!< SDE1 (Bit 1) */ + #define R_PDM_PDCSDCR_SDE1_Msk (0x2UL) /*!< SDE1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSDCR_SDE2_Pos (2UL) /*!< SDE2 (Bit 2) */ + #define R_PDM_PDCSDCR_SDE2_Msk (0x4UL) /*!< SDE2 (Bitfield-Mask: 0x01) */ +/* ======================================================== PDCDRCR ======================================================== */ + #define R_PDM_PDCDRCR_DATRE0_Pos (0UL) /*!< DATRE0 (Bit 0) */ + #define R_PDM_PDCDRCR_DATRE0_Msk (0x1UL) /*!< DATRE0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCDRCR_DATRE1_Pos (1UL) /*!< DATRE1 (Bit 1) */ + #define R_PDM_PDCDRCR_DATRE1_Msk (0x2UL) /*!< DATRE1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCDRCR_DATRE2_Pos (2UL) /*!< DATRE2 (Bit 2) */ + #define R_PDM_PDCDRCR_DATRE2_Msk (0x4UL) /*!< DATRE2 (Bitfield-Mask: 0x01) */ +/* ======================================================== PDCDCR ========================================================= */ + #define R_PDM_PDCDCR_DATC0_Pos (0UL) /*!< DATC0 (Bit 0) */ + #define R_PDM_PDCDCR_DATC0_Msk (0x1UL) /*!< DATC0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCDCR_DATC1_Pos (1UL) /*!< DATC1 (Bit 1) */ + #define R_PDM_PDCDCR_DATC1_Msk (0x2UL) /*!< DATC1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCDCR_DATC2_Pos (2UL) /*!< DATC2 (Bit 2) */ + #define R_PDM_PDCDCR_DATC2_Msk (0x4UL) /*!< DATC2 (Bitfield-Mask: 0x01) */ +/* ========================================================= PDVR ========================================================== */ + #define R_PDM_PDVR_VER_Pos (0UL) /*!< VER (Bit 0) */ + #define R_PDM_PDVR_VER_Msk (0xfffUL) /*!< VER (Bitfield-Mask: 0xfff) */ + +/* =========================================================================================================================== */ +/* ================ R_RMAC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= MPSM ========================================================== */ + #define R_RMAC0_MPSM_PSME_Pos (0UL) /*!< PSME (Bit 0) */ + #define R_RMAC0_MPSM_PSME_Msk (0x1UL) /*!< PSME (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPSM_MFF_Pos (2UL) /*!< MFF (Bit 2) */ + #define R_RMAC0_MPSM_MFF_Msk (0x4UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPSM_PDA_Pos (3UL) /*!< PDA (Bit 3) */ + #define R_RMAC0_MPSM_PDA_Msk (0xf8UL) /*!< PDA (Bitfield-Mask: 0x1f) */ + #define R_RMAC0_MPSM_PRA_Pos (8UL) /*!< PRA (Bit 8) */ + #define R_RMAC0_MPSM_PRA_Msk (0x1f00UL) /*!< PRA (Bitfield-Mask: 0x1f) */ + #define R_RMAC0_MPSM_POP_Pos (13UL) /*!< POP (Bit 13) */ + #define R_RMAC0_MPSM_POP_Msk (0x6000UL) /*!< POP (Bitfield-Mask: 0x03) */ + #define R_RMAC0_MPSM_PRD_Pos (16UL) /*!< PRD (Bit 16) */ + #define R_RMAC0_MPSM_PRD_Msk (0xffff0000UL) /*!< PRD (Bitfield-Mask: 0xffff) */ +/* ========================================================= MPIC ========================================================== */ + #define R_RMAC0_MPIC_PIS_Pos (0UL) /*!< PIS (Bit 0) */ + #define R_RMAC0_MPIC_PIS_Msk (0x7UL) /*!< PIS (Bitfield-Mask: 0x07) */ + #define R_RMAC0_MPIC_LSC_Pos (3UL) /*!< LSC (Bit 3) */ + #define R_RMAC0_MPIC_LSC_Msk (0x38UL) /*!< LSC (Bitfield-Mask: 0x07) */ + #define R_RMAC0_MPIC_PIP_Pos (8UL) /*!< PIP (Bit 8) */ + #define R_RMAC0_MPIC_PIP_Msk (0x100UL) /*!< PIP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPIC_PIPP_Pos (9UL) /*!< PIPP (Bit 9) */ + #define R_RMAC0_MPIC_PIPP_Msk (0x200UL) /*!< PIPP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPIC_PLSPP_Pos (10UL) /*!< PLSPP (Bit 10) */ + #define R_RMAC0_MPIC_PLSPP_Msk (0x400UL) /*!< PLSPP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPIC_PSMCS_Pos (16UL) /*!< PSMCS (Bit 16) */ + #define R_RMAC0_MPIC_PSMCS_Msk (0x7f0000UL) /*!< PSMCS (Bitfield-Mask: 0x7f) */ + #define R_RMAC0_MPIC_PSMDP_Pos (23UL) /*!< PSMDP (Bit 23) */ + #define R_RMAC0_MPIC_PSMDP_Msk (0x800000UL) /*!< PSMDP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPIC_PSMHT_Pos (24UL) /*!< PSMHT (Bit 24) */ + #define R_RMAC0_MPIC_PSMHT_Msk (0x7000000UL) /*!< PSMHT (Bitfield-Mask: 0x07) */ + #define R_RMAC0_MPIC_PSMCT_Pos (28UL) /*!< PSMCT (Bit 28) */ + #define R_RMAC0_MPIC_PSMCT_Msk (0x70000000UL) /*!< PSMCT (Bitfield-Mask: 0x07) */ +/* ========================================================= MPIM ========================================================== */ + #define R_RMAC0_MPIM_PLS_Pos (0UL) /*!< PLS (Bit 0) */ + #define R_RMAC0_MPIM_PLS_Msk (0x1UL) /*!< PLS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPIM_LPIA_Pos (1UL) /*!< LPIA (Bit 1) */ + #define R_RMAC0_MPIM_LPIA_Msk (0x2UL) /*!< LPIA (Bitfield-Mask: 0x01) */ +/* ========================================================= MIOC ========================================================== */ + #define R_RMAC0_MIOC_MIOC_Pos (0UL) /*!< MIOC (Bit 0) */ + #define R_RMAC0_MIOC_MIOC_Msk (0xffffffffUL) /*!< MIOC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MTFFC ========================================================= */ + #define R_RMAC0_MTFFC_DPAD_Pos (0UL) /*!< DPAD (Bit 0) */ + #define R_RMAC0_MTFFC_DPAD_Msk (0x1UL) /*!< DPAD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTFFC_FCM_Pos (1UL) /*!< FCM (Bit 1) */ + #define R_RMAC0_MTFFC_FCM_Msk (0x2UL) /*!< FCM (Bitfield-Mask: 0x01) */ +/* ========================================================= MTPFC ========================================================= */ + #define R_RMAC0_MTPFC_PT_Pos (0UL) /*!< PT (Bit 0) */ + #define R_RMAC0_MTPFC_PT_Msk (0xffffUL) /*!< PT (Bitfield-Mask: 0xffff) */ + #define R_RMAC0_MTPFC_PFRT_Pos (16UL) /*!< PFRT (Bit 16) */ + #define R_RMAC0_MTPFC_PFRT_Msk (0xff0000UL) /*!< PFRT (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MTPFC_PFM_Pos (26UL) /*!< PFM (Bit 26) */ + #define R_RMAC0_MTPFC_PFM_Msk (0x4000000UL) /*!< PFM (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTPFC_PFRLV_Pos (27UL) /*!< PFRLV (Bit 27) */ + #define R_RMAC0_MTPFC_PFRLV_Msk (0xf8000000UL) /*!< PFRLV (Bitfield-Mask: 0x1f) */ +/* ======================================================== MTPFC2 ========================================================= */ + #define R_RMAC0_MTPFC2_PFCTTZ_Pos (0UL) /*!< PFCTTZ (Bit 0) */ + #define R_RMAC0_MTPFC2_PFCTTZ_Msk (0x3UL) /*!< PFCTTZ (Bitfield-Mask: 0x03) */ + #define R_RMAC0_MTPFC2_MPFCFR0_Pos (8UL) /*!< MPFCFR0 (Bit 8) */ + #define R_RMAC0_MTPFC2_MPFCFR0_Msk (0x100UL) /*!< MPFCFR0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTPFC2_MPFCFR1_Pos (9UL) /*!< MPFCFR1 (Bit 9) */ + #define R_RMAC0_MTPFC2_MPFCFR1_Msk (0x200UL) /*!< MPFCFR1 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTPFC2_PFTTZ_Pos (16UL) /*!< PFTTZ (Bit 16) */ + #define R_RMAC0_MTPFC2_PFTTZ_Msk (0x10000UL) /*!< PFTTZ (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTPFC2_MPFR_Pos (17UL) /*!< MPFR (Bit 17) */ + #define R_RMAC0_MTPFC2_MPFR_Msk (0x20000UL) /*!< MPFR (Bitfield-Mask: 0x01) */ +/* ======================================================== MTPFC30 ======================================================== */ + #define R_RMAC0_MTPFC30_PFCPG_Pos (0UL) /*!< PFCPG (Bit 0) */ + #define R_RMAC0_MTPFC30_PFCPG_Msk (0xffUL) /*!< PFCPG (Bitfield-Mask: 0xff) */ +/* ======================================================== MTPFC31 ======================================================== */ + #define R_RMAC0_MTPFC31_PFCPG_Pos (0UL) /*!< PFCPG (Bit 0) */ + #define R_RMAC0_MTPFC31_PFCPG_Msk (0xffUL) /*!< PFCPG (Bitfield-Mask: 0xff) */ +/* ======================================================== MTATC0 ========================================================= */ + #define R_RMAC0_MTATC0_TRTP_Pos (0UL) /*!< TRTP (Bit 0) */ + #define R_RMAC0_MTATC0_TRTP_Msk (0xffUL) /*!< TRTP (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MTATC0_TRTL_Pos (8UL) /*!< TRTL (Bit 8) */ + #define R_RMAC0_MTATC0_TRTL_Msk (0x700UL) /*!< TRTL (Bitfield-Mask: 0x07) */ +/* ======================================================== MTATC1 ========================================================= */ + #define R_RMAC0_MTATC1_TRTP_Pos (0UL) /*!< TRTP (Bit 0) */ + #define R_RMAC0_MTATC1_TRTP_Msk (0xffUL) /*!< TRTP (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MTATC1_TRTL_Pos (8UL) /*!< TRTL (Bit 8) */ + #define R_RMAC0_MTATC1_TRTL_Msk (0x700UL) /*!< TRTL (Bitfield-Mask: 0x07) */ +/* ========================================================= MTIM ========================================================== */ + #define R_RMAC0_MTIM_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_RMAC0_MTIM_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ +/* ========================================================= MRGC ========================================================== */ + #define R_RMAC0_MRGC_RCPT_Pos (0UL) /*!< RCPT (Bit 0) */ + #define R_RMAC0_MRGC_RCPT_Msk (0x1UL) /*!< RCPT (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRGC_PFRC_Pos (1UL) /*!< PFRC (Bit 1) */ + #define R_RMAC0_MRGC_PFRC_Msk (0x2UL) /*!< PFRC (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRGC_PFRTZ_Pos (2UL) /*!< PFRTZ (Bit 2) */ + #define R_RMAC0_MRGC_PFRTZ_Msk (0x4UL) /*!< PFRTZ (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRGC_MPDE_Pos (3UL) /*!< MPDE (Bit 3) */ + #define R_RMAC0_MRGC_MPDE_Msk (0x8UL) /*!< MPDE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRGC_RFCFE_Pos (4UL) /*!< RFCFE (Bit 4) */ + #define R_RMAC0_MRGC_RFCFE_Msk (0x10UL) /*!< RFCFE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRGC_PFCRC_Pos (16UL) /*!< PFCRC (Bit 16) */ + #define R_RMAC0_MRGC_PFCRC_Msk (0xff0000UL) /*!< PFCRC (Bitfield-Mask: 0xff) */ +/* ======================================================== MRMAC0 ========================================================= */ + #define R_RMAC0_MRMAC0_MAU_Pos (0UL) /*!< MAU (Bit 0) */ + #define R_RMAC0_MRMAC0_MAU_Msk (0xffffUL) /*!< MAU (Bitfield-Mask: 0xffff) */ +/* ======================================================== MRMAC1 ========================================================= */ + #define R_RMAC0_MRMAC1_MAL_Pos (0UL) /*!< MAL (Bit 0) */ + #define R_RMAC0_MRMAC1_MAL_Msk (0xffffffffUL) /*!< MAL (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MRAFC ========================================================= */ + #define R_RMAC0_MRAFC_UCENE_Pos (0UL) /*!< UCENE (Bit 0) */ + #define R_RMAC0_MRAFC_UCENE_Msk (0x1UL) /*!< UCENE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MCENE_Pos (1UL) /*!< MCENE (Bit 1) */ + #define R_RMAC0_MRAFC_MCENE_Msk (0x2UL) /*!< MCENE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_BCENE_Pos (2UL) /*!< BCENE (Bit 2) */ + #define R_RMAC0_MRAFC_BCENE_Msk (0x4UL) /*!< BCENE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MSTENE_Pos (3UL) /*!< MSTENE (Bit 3) */ + #define R_RMAC0_MRAFC_MSTENE_Msk (0x8UL) /*!< MSTENE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_BSTENE_Pos (4UL) /*!< BSTENE (Bit 4) */ + #define R_RMAC0_MRAFC_BSTENE_Msk (0x10UL) /*!< BSTENE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MCACE_Pos (5UL) /*!< MCACE (Bit 5) */ + #define R_RMAC0_MRAFC_MCACE_Msk (0x20UL) /*!< MCACE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_BCACE_Pos (6UL) /*!< BCACE (Bit 6) */ + #define R_RMAC0_MRAFC_BCACE_Msk (0x40UL) /*!< BCACE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_NDAREE_Pos (7UL) /*!< NDAREE (Bit 7) */ + #define R_RMAC0_MRAFC_NDAREE_Msk (0x80UL) /*!< NDAREE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_SDSFREE_Pos (8UL) /*!< SDSFREE (Bit 8) */ + #define R_RMAC0_MRAFC_SDSFREE_Msk (0x100UL) /*!< SDSFREE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_NSAREE_Pos (9UL) /*!< NSAREE (Bit 9) */ + #define R_RMAC0_MRAFC_NSAREE_Msk (0x200UL) /*!< NSAREE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MSAREE_Pos (10UL) /*!< MSAREE (Bit 10) */ + #define R_RMAC0_MRAFC_MSAREE_Msk (0x400UL) /*!< MSAREE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_UCENP_Pos (16UL) /*!< UCENP (Bit 16) */ + #define R_RMAC0_MRAFC_UCENP_Msk (0x10000UL) /*!< UCENP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MCENP_Pos (17UL) /*!< MCENP (Bit 17) */ + #define R_RMAC0_MRAFC_MCENP_Msk (0x20000UL) /*!< MCENP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_BCENP_Pos (18UL) /*!< BCENP (Bit 18) */ + #define R_RMAC0_MRAFC_BCENP_Msk (0x40000UL) /*!< BCENP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MSTENP_Pos (19UL) /*!< MSTENP (Bit 19) */ + #define R_RMAC0_MRAFC_MSTENP_Msk (0x80000UL) /*!< MSTENP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_BSTENP_Pos (20UL) /*!< BSTENP (Bit 20) */ + #define R_RMAC0_MRAFC_BSTENP_Msk (0x100000UL) /*!< BSTENP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MCACP_Pos (21UL) /*!< MCACP (Bit 21) */ + #define R_RMAC0_MRAFC_MCACP_Msk (0x200000UL) /*!< MCACP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_BCACP_Pos (22UL) /*!< BCACP (Bit 22) */ + #define R_RMAC0_MRAFC_BCACP_Msk (0x400000UL) /*!< BCACP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_NDAREP_Pos (23UL) /*!< NDAREP (Bit 23) */ + #define R_RMAC0_MRAFC_NDAREP_Msk (0x800000UL) /*!< NDAREP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_SDSFREP_Pos (24UL) /*!< SDSFREP (Bit 24) */ + #define R_RMAC0_MRAFC_SDSFREP_Msk (0x1000000UL) /*!< SDSFREP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_NSAREP_Pos (25UL) /*!< NSAREP (Bit 25) */ + #define R_RMAC0_MRAFC_NSAREP_Msk (0x2000000UL) /*!< NSAREP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MSAREP_Pos (26UL) /*!< MSAREP (Bit 26) */ + #define R_RMAC0_MRAFC_MSAREP_Msk (0x4000000UL) /*!< MSAREP (Bitfield-Mask: 0x01) */ +/* ========================================================= MRSCE ========================================================= */ + #define R_RMAC0_MRSCE_CMFE_Pos (0UL) /*!< CMFE (Bit 0) */ + #define R_RMAC0_MRSCE_CMFE_Msk (0xffffUL) /*!< CMFE (Bitfield-Mask: 0xffff) */ + #define R_RMAC0_MRSCE_CBFE_Pos (16UL) /*!< CBFE (Bit 16) */ + #define R_RMAC0_MRSCE_CBFE_Msk (0xffff0000UL) /*!< CBFE (Bitfield-Mask: 0xffff) */ +/* ========================================================= MRSCP ========================================================= */ + #define R_RMAC0_MRSCP_CMFP_Pos (0UL) /*!< CMFP (Bit 0) */ + #define R_RMAC0_MRSCP_CMFP_Msk (0xffffUL) /*!< CMFP (Bitfield-Mask: 0xffff) */ + #define R_RMAC0_MRSCP_CBFP_Pos (16UL) /*!< CBFP (Bit 16) */ + #define R_RMAC0_MRSCP_CBFP_Msk (0xffff0000UL) /*!< CBFP (Bitfield-Mask: 0xffff) */ +/* ========================================================= MRSCC ========================================================= */ + #define R_RMAC0_MRSCC_MSCCE_Pos (0UL) /*!< MSCCE (Bit 0) */ + #define R_RMAC0_MRSCC_MSCCE_Msk (0x1UL) /*!< MSCCE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRSCC_BSCCE_Pos (1UL) /*!< BSCCE (Bit 1) */ + #define R_RMAC0_MRSCC_BSCCE_Msk (0x2UL) /*!< BSCCE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRSCC_MSCCP_Pos (16UL) /*!< MSCCP (Bit 16) */ + #define R_RMAC0_MRSCC_MSCCP_Msk (0x10000UL) /*!< MSCCP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRSCC_BSCCP_Pos (17UL) /*!< BSCCP (Bit 17) */ + #define R_RMAC0_MRSCC_BSCCP_Msk (0x20000UL) /*!< BSCCP (Bitfield-Mask: 0x01) */ +/* ======================================================== MRFSCE ========================================================= */ + #define R_RMAC0_MRFSCE_EMXS_Pos (0UL) /*!< EMXS (Bit 0) */ + #define R_RMAC0_MRFSCE_EMXS_Msk (0xffffUL) /*!< EMXS (Bitfield-Mask: 0xffff) */ + #define R_RMAC0_MRFSCE_EMNS_Pos (16UL) /*!< EMNS (Bit 16) */ + #define R_RMAC0_MRFSCE_EMNS_Msk (0xffff0000UL) /*!< EMNS (Bitfield-Mask: 0xffff) */ +/* ======================================================== MRFSCP ========================================================= */ + #define R_RMAC0_MRFSCP_PMXS_Pos (0UL) /*!< PMXS (Bit 0) */ + #define R_RMAC0_MRFSCP_PMXS_Msk (0xffffUL) /*!< PMXS (Bitfield-Mask: 0xffff) */ + #define R_RMAC0_MRFSCP_PMNS_Pos (16UL) /*!< PMNS (Bit 16) */ + #define R_RMAC0_MRFSCP_PMNS_Msk (0xffff0000UL) /*!< PMNS (Bitfield-Mask: 0xffff) */ +/* ========================================================= MTRC ========================================================== */ + #define R_RMAC0_MTRC_TRHFME0_Pos (0UL) /*!< TRHFME0 (Bit 0) */ + #define R_RMAC0_MTRC_TRHFME0_Msk (0x1UL) /*!< TRHFME0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTRC_TRHFME1_Pos (1UL) /*!< TRHFME1 (Bit 1) */ + #define R_RMAC0_MTRC_TRHFME1_Msk (0x2UL) /*!< TRHFME1 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTRC_TRDDE_Pos (24UL) /*!< TRDDE (Bit 24) */ + #define R_RMAC0_MTRC_TRDDE_Msk (0x1000000UL) /*!< TRDDE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTRC_TRDDP_Pos (25UL) /*!< TRDDP (Bit 25) */ + #define R_RMAC0_MTRC_TRDDP_Msk (0x2000000UL) /*!< TRDDP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTRC_TCTSE_Pos (26UL) /*!< TCTSE (Bit 26) */ + #define R_RMAC0_MTRC_TCTSE_Msk (0x4000000UL) /*!< TCTSE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTRC_TCTSP_Pos (27UL) /*!< TCTSP (Bit 27) */ + #define R_RMAC0_MTRC_TCTSP_Msk (0x8000000UL) /*!< TCTSP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTRC_DTN_Pos (28UL) /*!< DTN (Bit 28) */ + #define R_RMAC0_MTRC_DTN_Msk (0x10000000UL) /*!< DTN (Bitfield-Mask: 0x01) */ +/* ========================================================= MRPFM ========================================================= */ + #define R_RMAC0_MRPFM_PTCA_Pos (0UL) /*!< PTCA (Bit 0) */ + #define R_RMAC0_MRPFM_PTCA_Msk (0x1UL) /*!< PTCA (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRPFM_PFCTCA_Pos (16UL) /*!< PFCTCA (Bit 16) */ + #define R_RMAC0_MRPFM_PFCTCA_Msk (0xff0000UL) /*!< PFCTCA (Bitfield-Mask: 0xff) */ +/* ========================================================= MPFC0 ========================================================= */ + #define R_RMAC0_MPFC0_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC0_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC0_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC0_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC0_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC0_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC0_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC0_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC1 ========================================================= */ + #define R_RMAC0_MPFC1_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC1_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC1_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC1_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC1_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC1_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC1_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC1_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC2 ========================================================= */ + #define R_RMAC0_MPFC2_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC2_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC2_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC2_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC2_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC2_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC2_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC2_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC3 ========================================================= */ + #define R_RMAC0_MPFC3_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC3_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC3_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC3_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC3_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC3_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC3_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC3_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC4 ========================================================= */ + #define R_RMAC0_MPFC4_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC4_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC4_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC4_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC4_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC4_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC4_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC4_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC5 ========================================================= */ + #define R_RMAC0_MPFC5_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC5_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC5_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC5_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC5_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC5_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC5_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC5_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC6 ========================================================= */ + #define R_RMAC0_MPFC6_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC6_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC6_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC6_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC6_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC6_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC6_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC6_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC7 ========================================================= */ + #define R_RMAC0_MPFC7_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC7_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC7_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC7_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC7_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC7_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC7_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC7_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC8 ========================================================= */ + #define R_RMAC0_MPFC8_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC8_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC8_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC8_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC8_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC8_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC8_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC8_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC9 ========================================================= */ + #define R_RMAC0_MPFC9_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC9_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC9_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC9_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC9_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC9_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC9_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC9_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MPFC10 ========================================================= */ + #define R_RMAC0_MPFC10_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC10_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC10_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC10_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC10_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC10_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC10_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC10_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MPFC11 ========================================================= */ + #define R_RMAC0_MPFC11_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC11_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC11_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC11_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC11_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC11_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC11_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC11_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MPFC12 ========================================================= */ + #define R_RMAC0_MPFC12_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC12_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC12_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC12_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC12_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC12_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC12_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC12_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MPFC13 ========================================================= */ + #define R_RMAC0_MPFC13_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC13_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC13_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC13_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC13_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC13_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC13_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC13_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MPFC14 ========================================================= */ + #define R_RMAC0_MPFC14_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC14_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC14_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC14_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC14_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC14_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC14_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC14_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MPFC15 ========================================================= */ + #define R_RMAC0_MPFC15_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC15_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC15_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC15_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC15_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC15_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC15_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC15_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MLVC ========================================================== */ + #define R_RMAC0_MLVC_LVT_Pos (0UL) /*!< LVT (Bit 0) */ + #define R_RMAC0_MLVC_LVT_Msk (0x7fUL) /*!< LVT (Bitfield-Mask: 0x7f) */ + #define R_RMAC0_MLVC_PASE_Pos (8UL) /*!< PASE (Bit 8) */ + #define R_RMAC0_MLVC_PASE_Msk (0x100UL) /*!< PASE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MLVC_PLV_Pos (16UL) /*!< PLV (Bit 16) */ + #define R_RMAC0_MLVC_PLV_Msk (0x10000UL) /*!< PLV (Bitfield-Mask: 0x01) */ +/* ========================================================= MEEEC ========================================================= */ + #define R_RMAC0_MEEEC_LPITR_Pos (0UL) /*!< LPITR (Bit 0) */ + #define R_RMAC0_MEEEC_LPITR_Msk (0x1UL) /*!< LPITR (Bitfield-Mask: 0x01) */ +/* ========================================================= MLBC ========================================================== */ + #define R_RMAC0_MLBC_LBME_Pos (0UL) /*!< LBME (Bit 0) */ + #define R_RMAC0_MLBC_LBME_Msk (0x1UL) /*!< LBME (Bitfield-Mask: 0x01) */ +/* ======================================================== MXGMIIC ======================================================== */ + #define R_RMAC0_MXGMIIC_LFS_TXRFS_Pos (0UL) /*!< LFS_TXRFS (Bit 0) */ + #define R_RMAC0_MXGMIIC_LFS_TXRFS_Msk (0x1UL) /*!< LFS_TXRFS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MXGMIIC_LFS_TXIDLE_Pos (1UL) /*!< LFS_TXIDLE (Bit 1) */ + #define R_RMAC0_MXGMIIC_LFS_TXIDLE_Msk (0x2UL) /*!< LFS_TXIDLE (Bitfield-Mask: 0x01) */ +/* ========================================================= MPCH ========================================================== */ + #define R_RMAC0_MPCH_TXPCH_M_Pos (0UL) /*!< TXPCH_M (Bit 0) */ + #define R_RMAC0_MPCH_TXPCH_M_Msk (0x1UL) /*!< TXPCH_M (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPCH_TXPCH_ETYPE_Pos (2UL) /*!< TXPCH_ETYPE (Bit 2) */ + #define R_RMAC0_MPCH_TXPCH_ETYPE_Msk (0xcUL) /*!< TXPCH_ETYPE (Bitfield-Mask: 0x03) */ + #define R_RMAC0_MPCH_TXPCH_PID_Pos (4UL) /*!< TXPCH_PID (Bit 4) */ + #define R_RMAC0_MPCH_TXPCH_PID_Msk (0xf0UL) /*!< TXPCH_PID (Bitfield-Mask: 0x0f) */ + #define R_RMAC0_MPCH_IETPTE_Pos (8UL) /*!< IETPTE (Bit 8) */ + #define R_RMAC0_MPCH_IETPTE_Msk (0x100UL) /*!< IETPTE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPCH_CTPTE_Pos (9UL) /*!< CTPTE (Bit 9) */ + #define R_RMAC0_MPCH_CTPTE_Msk (0x200UL) /*!< CTPTE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPCH_IETRIOD_Pos (10UL) /*!< IETRIOD (Bit 10) */ + #define R_RMAC0_MPCH_IETRIOD_Msk (0x400UL) /*!< IETRIOD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPCH_CTRIOD_Pos (11UL) /*!< CTRIOD (Bit 11) */ + #define R_RMAC0_MPCH_CTRIOD_Msk (0x800UL) /*!< CTRIOD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPCH_RXPCH_TSM_Pos (16UL) /*!< RXPCH_TSM (Bit 16) */ + #define R_RMAC0_MPCH_RXPCH_TSM_Msk (0x10000UL) /*!< RXPCH_TSM (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPCH_RPHCRCD_Pos (17UL) /*!< RPHCRCD (Bit 17) */ + #define R_RMAC0_MPCH_RPHCRCD_Msk (0x20000UL) /*!< RPHCRCD (Bitfield-Mask: 0x01) */ +/* ========================================================= MANM ========================================================== */ + #define R_RMAC0_MANM_RX_AN_MES_Pos (0UL) /*!< RX_AN_MES (Bit 0) */ + #define R_RMAC0_MANM_RX_AN_MES_Msk (0xffffUL) /*!< RX_AN_MES (Bitfield-Mask: 0xffff) */ +/* ========================================================= MEIS ========================================================== */ + #define R_RMAC0_MEIS_TSLS_Pos (0UL) /*!< TSLS (Bit 0) */ + #define R_RMAC0_MEIS_TSLS_Msk (0x1UL) /*!< TSLS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_TIES_Pos (1UL) /*!< TIES (Bit 1) */ + #define R_RMAC0_MEIS_TIES_Msk (0x2UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_PRES_Pos (2UL) /*!< PRES (Bit 2) */ + #define R_RMAC0_MEIS_PRES_Msk (0x4UL) /*!< PRES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_PFRROS_Pos (3UL) /*!< PFRROS (Bit 3) */ + #define R_RMAC0_MEIS_PFRROS_Msk (0x8UL) /*!< PFRROS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FCDS_Pos (4UL) /*!< FCDS (Bit 4) */ + #define R_RMAC0_MEIS_FCDS_Msk (0x10UL) /*!< FCDS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_TCES_Pos (5UL) /*!< TCES (Bit 5) */ + #define R_RMAC0_MEIS_TCES_Msk (0x20UL) /*!< TCES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_TBCIS_Pos (6UL) /*!< TBCIS (Bit 6) */ + #define R_RMAC0_MEIS_TBCIS_Msk (0x40UL) /*!< TBCIS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_BFES_Pos (7UL) /*!< BFES (Bit 7) */ + #define R_RMAC0_MEIS_BFES_Msk (0x80UL) /*!< BFES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FCES_Pos (8UL) /*!< FCES (Bit 8) */ + #define R_RMAC0_MEIS_FCES_Msk (0x100UL) /*!< FCES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_REOES_Pos (9UL) /*!< REOES (Bit 9) */ + #define R_RMAC0_MEIS_REOES_Msk (0x200UL) /*!< REOES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_RPOES_Pos (10UL) /*!< RPOES (Bit 10) */ + #define R_RMAC0_MEIS_RPOES_Msk (0x400UL) /*!< RPOES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_RPCRES_Pos (11UL) /*!< RPCRES (Bit 11) */ + #define R_RMAC0_MEIS_RPCRES_Msk (0x800UL) /*!< RPCRES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_CTLES0_Pos (12UL) /*!< CTLES0 (Bit 12) */ + #define R_RMAC0_MEIS_CTLES0_Msk (0x1000UL) /*!< CTLES0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_CTLES1_Pos (13UL) /*!< CTLES1 (Bit 13) */ + #define R_RMAC0_MEIS_CTLES1_Msk (0x2000UL) /*!< CTLES1 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_PDES_Pos (20UL) /*!< PDES (Bit 20) */ + #define R_RMAC0_MEIS_PDES_Msk (0x100000UL) /*!< PDES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_PNAES_Pos (21UL) /*!< PNAES (Bit 21) */ + #define R_RMAC0_MEIS_PNAES_Msk (0x200000UL) /*!< PNAES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FCMCES_Pos (22UL) /*!< FCMCES (Bit 22) */ + #define R_RMAC0_MEIS_FCMCES_Msk (0x400000UL) /*!< FCMCES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FFMES_Pos (23UL) /*!< FFMES (Bit 23) */ + #define R_RMAC0_MEIS_FFMES_Msk (0x800000UL) /*!< FFMES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_CFCES_Pos (24UL) /*!< CFCES (Bit 24) */ + #define R_RMAC0_MEIS_CFCES_Msk (0x1000000UL) /*!< CFCES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FRCES_Pos (25UL) /*!< FRCES (Bit 25) */ + #define R_RMAC0_MEIS_FRCES_Msk (0x2000000UL) /*!< FRCES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_RPOOMS_Pos (26UL) /*!< RPOOMS (Bit 26) */ + #define R_RMAC0_MEIS_RPOOMS_Msk (0x4000000UL) /*!< RPOOMS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FFS_Pos (27UL) /*!< FFS (Bit 27) */ + #define R_RMAC0_MEIS_FFS_Msk (0x8000000UL) /*!< FFS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FUES_Pos (28UL) /*!< FUES (Bit 28) */ + #define R_RMAC0_MEIS_FUES_Msk (0x10000000UL) /*!< FUES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FOES_Pos (29UL) /*!< FOES (Bit 29) */ + #define R_RMAC0_MEIS_FOES_Msk (0x20000000UL) /*!< FOES (Bitfield-Mask: 0x01) */ +/* ========================================================= MEIE ========================================================== */ + #define R_RMAC0_MEIE_TSLE_Pos (0UL) /*!< TSLE (Bit 0) */ + #define R_RMAC0_MEIE_TSLE_Msk (0x1UL) /*!< TSLE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_TIEE_Pos (1UL) /*!< TIEE (Bit 1) */ + #define R_RMAC0_MEIE_TIEE_Msk (0x2UL) /*!< TIEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_PMSEE_Pos (2UL) /*!< PMSEE (Bit 2) */ + #define R_RMAC0_MEIE_PMSEE_Msk (0x4UL) /*!< PMSEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_PFRROE_Pos (3UL) /*!< PFRROE (Bit 3) */ + #define R_RMAC0_MEIE_PFRROE_Msk (0x8UL) /*!< PFRROE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FCDE_Pos (4UL) /*!< FCDE (Bit 4) */ + #define R_RMAC0_MEIE_FCDE_Msk (0x10UL) /*!< FCDE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_TCEE_Pos (5UL) /*!< TCEE (Bit 5) */ + #define R_RMAC0_MEIE_TCEE_Msk (0x20UL) /*!< TCEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_TBCIE_Pos (6UL) /*!< TBCIE (Bit 6) */ + #define R_RMAC0_MEIE_TBCIE_Msk (0x40UL) /*!< TBCIE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_BFEE_Pos (7UL) /*!< BFEE (Bit 7) */ + #define R_RMAC0_MEIE_BFEE_Msk (0x80UL) /*!< BFEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FCEE_Pos (8UL) /*!< FCEE (Bit 8) */ + #define R_RMAC0_MEIE_FCEE_Msk (0x100UL) /*!< FCEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_REOEE_Pos (9UL) /*!< REOEE (Bit 9) */ + #define R_RMAC0_MEIE_REOEE_Msk (0x200UL) /*!< REOEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_RPOEE_Pos (10UL) /*!< RPOEE (Bit 10) */ + #define R_RMAC0_MEIE_RPOEE_Msk (0x400UL) /*!< RPOEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_RPCREE_Pos (11UL) /*!< RPCREE (Bit 11) */ + #define R_RMAC0_MEIE_RPCREE_Msk (0x800UL) /*!< RPCREE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_CTLEE0_Pos (12UL) /*!< CTLEE0 (Bit 12) */ + #define R_RMAC0_MEIE_CTLEE0_Msk (0x1000UL) /*!< CTLEE0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_CTLEE1_Pos (13UL) /*!< CTLEE1 (Bit 13) */ + #define R_RMAC0_MEIE_CTLEE1_Msk (0x2000UL) /*!< CTLEE1 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_PDEE_Pos (20UL) /*!< PDEE (Bit 20) */ + #define R_RMAC0_MEIE_PDEE_Msk (0x100000UL) /*!< PDEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_PNAEE_Pos (21UL) /*!< PNAEE (Bit 21) */ + #define R_RMAC0_MEIE_PNAEE_Msk (0x200000UL) /*!< PNAEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FCMCEE_Pos (22UL) /*!< FCMCEE (Bit 22) */ + #define R_RMAC0_MEIE_FCMCEE_Msk (0x400000UL) /*!< FCMCEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FFMEE_Pos (23UL) /*!< FFMEE (Bit 23) */ + #define R_RMAC0_MEIE_FFMEE_Msk (0x800000UL) /*!< FFMEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_CFCEE_Pos (24UL) /*!< CFCEE (Bit 24) */ + #define R_RMAC0_MEIE_CFCEE_Msk (0x1000000UL) /*!< CFCEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FRCEE_Pos (25UL) /*!< FRCEE (Bit 25) */ + #define R_RMAC0_MEIE_FRCEE_Msk (0x2000000UL) /*!< FRCEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_RPOOME_Pos (26UL) /*!< RPOOME (Bit 26) */ + #define R_RMAC0_MEIE_RPOOME_Msk (0x4000000UL) /*!< RPOOME (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FFE_Pos (27UL) /*!< FFE (Bit 27) */ + #define R_RMAC0_MEIE_FFE_Msk (0x8000000UL) /*!< FFE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FUEE_Pos (28UL) /*!< FUEE (Bit 28) */ + #define R_RMAC0_MEIE_FUEE_Msk (0x10000000UL) /*!< FUEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FOEE_Pos (29UL) /*!< FOEE (Bit 29) */ + #define R_RMAC0_MEIE_FOEE_Msk (0x20000000UL) /*!< FOEE (Bitfield-Mask: 0x01) */ +/* ========================================================= MEID ========================================================== */ + #define R_RMAC0_MEID_TSLD_Pos (0UL) /*!< TSLD (Bit 0) */ + #define R_RMAC0_MEID_TSLD_Msk (0x1UL) /*!< TSLD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_TIED_Pos (1UL) /*!< TIED (Bit 1) */ + #define R_RMAC0_MEID_TIED_Msk (0x2UL) /*!< TIED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_PRED_Pos (2UL) /*!< PRED (Bit 2) */ + #define R_RMAC0_MEID_PRED_Msk (0x4UL) /*!< PRED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_PFRROD_Pos (3UL) /*!< PFRROD (Bit 3) */ + #define R_RMAC0_MEID_PFRROD_Msk (0x8UL) /*!< PFRROD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FCDD_Pos (4UL) /*!< FCDD (Bit 4) */ + #define R_RMAC0_MEID_FCDD_Msk (0x10UL) /*!< FCDD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_TCED_Pos (5UL) /*!< TCED (Bit 5) */ + #define R_RMAC0_MEID_TCED_Msk (0x20UL) /*!< TCED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_TBCID_Pos (6UL) /*!< TBCID (Bit 6) */ + #define R_RMAC0_MEID_TBCID_Msk (0x40UL) /*!< TBCID (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_BFED_Pos (7UL) /*!< BFED (Bit 7) */ + #define R_RMAC0_MEID_BFED_Msk (0x80UL) /*!< BFED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FCED_Pos (8UL) /*!< FCED (Bit 8) */ + #define R_RMAC0_MEID_FCED_Msk (0x100UL) /*!< FCED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_REOED_Pos (9UL) /*!< REOED (Bit 9) */ + #define R_RMAC0_MEID_REOED_Msk (0x200UL) /*!< REOED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_RPOED_Pos (10UL) /*!< RPOED (Bit 10) */ + #define R_RMAC0_MEID_RPOED_Msk (0x400UL) /*!< RPOED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_RPCRED_Pos (11UL) /*!< RPCRED (Bit 11) */ + #define R_RMAC0_MEID_RPCRED_Msk (0x800UL) /*!< RPCRED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_CTLED0_Pos (12UL) /*!< CTLED0 (Bit 12) */ + #define R_RMAC0_MEID_CTLED0_Msk (0x1000UL) /*!< CTLED0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_CTLED1_Pos (13UL) /*!< CTLED1 (Bit 13) */ + #define R_RMAC0_MEID_CTLED1_Msk (0x2000UL) /*!< CTLED1 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_PDED_Pos (20UL) /*!< PDED (Bit 20) */ + #define R_RMAC0_MEID_PDED_Msk (0x100000UL) /*!< PDED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_PNAED_Pos (21UL) /*!< PNAED (Bit 21) */ + #define R_RMAC0_MEID_PNAED_Msk (0x200000UL) /*!< PNAED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FCMCED_Pos (22UL) /*!< FCMCED (Bit 22) */ + #define R_RMAC0_MEID_FCMCED_Msk (0x400000UL) /*!< FCMCED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FFMED_Pos (23UL) /*!< FFMED (Bit 23) */ + #define R_RMAC0_MEID_FFMED_Msk (0x800000UL) /*!< FFMED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_CFCED_Pos (24UL) /*!< CFCED (Bit 24) */ + #define R_RMAC0_MEID_CFCED_Msk (0x1000000UL) /*!< CFCED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FRCED_Pos (25UL) /*!< FRCED (Bit 25) */ + #define R_RMAC0_MEID_FRCED_Msk (0x2000000UL) /*!< FRCED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_RPOOMD_Pos (26UL) /*!< RPOOMD (Bit 26) */ + #define R_RMAC0_MEID_RPOOMD_Msk (0x4000000UL) /*!< RPOOMD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FFD_Pos (27UL) /*!< FFD (Bit 27) */ + #define R_RMAC0_MEID_FFD_Msk (0x8000000UL) /*!< FFD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FUED_Pos (28UL) /*!< FUED (Bit 28) */ + #define R_RMAC0_MEID_FUED_Msk (0x10000000UL) /*!< FUED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FOED_Pos (29UL) /*!< FOED (Bit 29) */ + #define R_RMAC0_MEID_FOED_Msk (0x20000000UL) /*!< FOED (Bitfield-Mask: 0x01) */ +/* ========================================================= MMIS0 ========================================================= */ + #define R_RMAC0_MMIS0_PLSCS_Pos (0UL) /*!< PLSCS (Bit 0) */ + #define R_RMAC0_MMIS0_PLSCS_Msk (0x1UL) /*!< PLSCS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_PIDS_Pos (1UL) /*!< PIDS (Bit 1) */ + #define R_RMAC0_MMIS0_PIDS_Msk (0x2UL) /*!< PIDS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_LVSS_Pos (2UL) /*!< LVSS (Bit 2) */ + #define R_RMAC0_MMIS0_LVSS_Msk (0x4UL) /*!< LVSS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_LVFS_Pos (3UL) /*!< LVFS (Bit 3) */ + #define R_RMAC0_MMIS0_LVFS_Msk (0x8UL) /*!< LVFS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_VFRS_Pos (4UL) /*!< VFRS (Bit 4) */ + #define R_RMAC0_MMIS0_VFRS_Msk (0x10UL) /*!< VFRS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_ANDETS_Pos (6UL) /*!< ANDETS (Bit 6) */ + #define R_RMAC0_MMIS0_ANDETS_Msk (0x40UL) /*!< ANDETS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_XLFDS_Pos (8UL) /*!< XLFDS (Bit 8) */ + #define R_RMAC0_MMIS0_XLFDS_Msk (0x100UL) /*!< XLFDS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_XLFES_Pos (9UL) /*!< XLFES (Bit 9) */ + #define R_RMAC0_MMIS0_XLFES_Msk (0x200UL) /*!< XLFES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_XLFSDS_Pos (10UL) /*!< XLFSDS (Bit 10) */ + #define R_RMAC0_MMIS0_XLFSDS_Msk (0x400UL) /*!< XLFSDS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_XRFSDS_Pos (11UL) /*!< XRFSDS (Bit 11) */ + #define R_RMAC0_MMIS0_XRFSDS_Msk (0x800UL) /*!< XRFSDS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_XLISDS_Pos (12UL) /*!< XLISDS (Bit 12) */ + #define R_RMAC0_MMIS0_XLISDS_Msk (0x1000UL) /*!< XLISDS (Bitfield-Mask: 0x01) */ +/* ========================================================= MMIE0 ========================================================= */ + #define R_RMAC0_MMIE0_PLSCE_Pos (0UL) /*!< PLSCE (Bit 0) */ + #define R_RMAC0_MMIE0_PLSCE_Msk (0x1UL) /*!< PLSCE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_PIDE_Pos (1UL) /*!< PIDE (Bit 1) */ + #define R_RMAC0_MMIE0_PIDE_Msk (0x2UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_LVSE_Pos (2UL) /*!< LVSE (Bit 2) */ + #define R_RMAC0_MMIE0_LVSE_Msk (0x4UL) /*!< LVSE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_LVFE_Pos (3UL) /*!< LVFE (Bit 3) */ + #define R_RMAC0_MMIE0_LVFE_Msk (0x8UL) /*!< LVFE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_VFRE_Pos (4UL) /*!< VFRE (Bit 4) */ + #define R_RMAC0_MMIE0_VFRE_Msk (0x10UL) /*!< VFRE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_ANDETE_Pos (6UL) /*!< ANDETE (Bit 6) */ + #define R_RMAC0_MMIE0_ANDETE_Msk (0x40UL) /*!< ANDETE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_XLFDE_Pos (8UL) /*!< XLFDE (Bit 8) */ + #define R_RMAC0_MMIE0_XLFDE_Msk (0x100UL) /*!< XLFDE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_XLFEE_Pos (9UL) /*!< XLFEE (Bit 9) */ + #define R_RMAC0_MMIE0_XLFEE_Msk (0x200UL) /*!< XLFEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_XLFSDE_Pos (10UL) /*!< XLFSDE (Bit 10) */ + #define R_RMAC0_MMIE0_XLFSDE_Msk (0x400UL) /*!< XLFSDE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_XRFSDE_Pos (11UL) /*!< XRFSDE (Bit 11) */ + #define R_RMAC0_MMIE0_XRFSDE_Msk (0x800UL) /*!< XRFSDE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_XLISDE_Pos (12UL) /*!< XLISDE (Bit 12) */ + #define R_RMAC0_MMIE0_XLISDE_Msk (0x1000UL) /*!< XLISDE (Bitfield-Mask: 0x01) */ +/* ========================================================= MMID0 ========================================================= */ + #define R_RMAC0_MMID0_PLSCD_Pos (0UL) /*!< PLSCD (Bit 0) */ + #define R_RMAC0_MMID0_PLSCD_Msk (0x1UL) /*!< PLSCD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_PIDD_Pos (1UL) /*!< PIDD (Bit 1) */ + #define R_RMAC0_MMID0_PIDD_Msk (0x2UL) /*!< PIDD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_LVSD_Pos (2UL) /*!< LVSD (Bit 2) */ + #define R_RMAC0_MMID0_LVSD_Msk (0x4UL) /*!< LVSD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_LVFD_Pos (3UL) /*!< LVFD (Bit 3) */ + #define R_RMAC0_MMID0_LVFD_Msk (0x8UL) /*!< LVFD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_VFRD_Pos (4UL) /*!< VFRD (Bit 4) */ + #define R_RMAC0_MMID0_VFRD_Msk (0x10UL) /*!< VFRD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_ANDETD_Pos (6UL) /*!< ANDETD (Bit 6) */ + #define R_RMAC0_MMID0_ANDETD_Msk (0x40UL) /*!< ANDETD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_XLFDD_Pos (8UL) /*!< XLFDD (Bit 8) */ + #define R_RMAC0_MMID0_XLFDD_Msk (0x100UL) /*!< XLFDD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_XLFED_Pos (9UL) /*!< XLFED (Bit 9) */ + #define R_RMAC0_MMID0_XLFED_Msk (0x200UL) /*!< XLFED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_XLFSDD_Pos (10UL) /*!< XLFSDD (Bit 10) */ + #define R_RMAC0_MMID0_XLFSDD_Msk (0x400UL) /*!< XLFSDD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_XRFSDD_Pos (11UL) /*!< XRFSDD (Bit 11) */ + #define R_RMAC0_MMID0_XRFSDD_Msk (0x800UL) /*!< XRFSDD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_XLISDD_Pos (12UL) /*!< XLISDD (Bit 12) */ + #define R_RMAC0_MMID0_XLISDD_Msk (0x1000UL) /*!< XLISDD (Bitfield-Mask: 0x01) */ +/* ========================================================= MMIS1 ========================================================= */ + #define R_RMAC0_MMIS1_PRACS_Pos (0UL) /*!< PRACS (Bit 0) */ + #define R_RMAC0_MMIS1_PRACS_Msk (0x1UL) /*!< PRACS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS1_PWACS_Pos (1UL) /*!< PWACS (Bit 1) */ + #define R_RMAC0_MMIS1_PWACS_Msk (0x2UL) /*!< PWACS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS1_PAACS_Pos (2UL) /*!< PAACS (Bit 2) */ + #define R_RMAC0_MMIS1_PAACS_Msk (0x4UL) /*!< PAACS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS1_PPRACS_Pos (3UL) /*!< PPRACS (Bit 3) */ + #define R_RMAC0_MMIS1_PPRACS_Msk (0x8UL) /*!< PPRACS (Bitfield-Mask: 0x01) */ +/* ========================================================= MMIE1 ========================================================= */ + #define R_RMAC0_MMIE1_PRACE_Pos (0UL) /*!< PRACE (Bit 0) */ + #define R_RMAC0_MMIE1_PRACE_Msk (0x1UL) /*!< PRACE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE1_PWACE_Pos (1UL) /*!< PWACE (Bit 1) */ + #define R_RMAC0_MMIE1_PWACE_Msk (0x2UL) /*!< PWACE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE1_PAACE_Pos (2UL) /*!< PAACE (Bit 2) */ + #define R_RMAC0_MMIE1_PAACE_Msk (0x4UL) /*!< PAACE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE1_PPRACE_Pos (3UL) /*!< PPRACE (Bit 3) */ + #define R_RMAC0_MMIE1_PPRACE_Msk (0x8UL) /*!< PPRACE (Bitfield-Mask: 0x01) */ +/* ========================================================= MMID1 ========================================================= */ + #define R_RMAC0_MMID1_PRACD_Pos (0UL) /*!< PRACD (Bit 0) */ + #define R_RMAC0_MMID1_PRACD_Msk (0x1UL) /*!< PRACD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID1_PWACD_Pos (1UL) /*!< PWACD (Bit 1) */ + #define R_RMAC0_MMID1_PWACD_Msk (0x2UL) /*!< PWACD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID1_PAACD_Pos (2UL) /*!< PAACD (Bit 2) */ + #define R_RMAC0_MMID1_PAACD_Msk (0x4UL) /*!< PAACD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID1_PPRACD_Pos (3UL) /*!< PPRACD (Bit 3) */ + #define R_RMAC0_MMID1_PPRACD_Msk (0x8UL) /*!< PPRACD (Bitfield-Mask: 0x01) */ +/* ========================================================= MMIS2 ========================================================= */ + #define R_RMAC0_MMIS2_MPDIS_Pos (0UL) /*!< MPDIS (Bit 0) */ + #define R_RMAC0_MMIS2_MPDIS_Msk (0x1UL) /*!< MPDIS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS2_LPIAIS_Pos (1UL) /*!< LPIAIS (Bit 1) */ + #define R_RMAC0_MMIS2_LPIAIS_Msk (0x2UL) /*!< LPIAIS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS2_LPIDIS_Pos (2UL) /*!< LPIDIS (Bit 2) */ + #define R_RMAC0_MMIS2_LPIDIS_Msk (0x4UL) /*!< LPIDIS (Bitfield-Mask: 0x01) */ +/* ========================================================= MMIE2 ========================================================= */ + #define R_RMAC0_MMIE2_MPDIE_Pos (0UL) /*!< MPDIE (Bit 0) */ + #define R_RMAC0_MMIE2_MPDIE_Msk (0x1UL) /*!< MPDIE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE2_LPIAIE_Pos (1UL) /*!< LPIAIE (Bit 1) */ + #define R_RMAC0_MMIE2_LPIAIE_Msk (0x2UL) /*!< LPIAIE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE2_LPIDIE_Pos (2UL) /*!< LPIDIE (Bit 2) */ + #define R_RMAC0_MMIE2_LPIDIE_Msk (0x4UL) /*!< LPIDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= MMID2 ========================================================= */ + #define R_RMAC0_MMID2_MPDID_Pos (0UL) /*!< MPDID (Bit 0) */ + #define R_RMAC0_MMID2_MPDID_Msk (0x1UL) /*!< MPDID (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID2_LPIAID_Pos (1UL) /*!< LPIAID (Bit 1) */ + #define R_RMAC0_MMID2_LPIAID_Msk (0x2UL) /*!< LPIAID (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID2_LPIDID_Pos (2UL) /*!< LPIDID (Bit 2) */ + #define R_RMAC0_MMID2_LPIDID_Msk (0x4UL) /*!< LPIDID (Bitfield-Mask: 0x01) */ +/* ======================================================== MMPFTCT ======================================================== */ + #define R_RMAC0_MMPFTCT_MPFTC_Pos (0UL) /*!< MPFTC (Bit 0) */ + #define R_RMAC0_MMPFTCT_MPFTC_Msk (0xffffUL) /*!< MPFTC (Bitfield-Mask: 0xffff) */ +/* ======================================================== MAPFTCT ======================================================== */ + #define R_RMAC0_MAPFTCT_APFTC_Pos (0UL) /*!< APFTC (Bit 0) */ + #define R_RMAC0_MAPFTCT_APFTC_Msk (0xffffUL) /*!< APFTC (Bitfield-Mask: 0xffff) */ +/* ======================================================== MPFRCT ========================================================= */ + #define R_RMAC0_MPFRCT_PFRC_Pos (0UL) /*!< PFRC (Bit 0) */ + #define R_RMAC0_MPFRCT_PFRC_Msk (0xffffUL) /*!< PFRC (Bitfield-Mask: 0xffff) */ +/* ======================================================== MFCICT ========================================================= */ + #define R_RMAC0_MFCICT_FCIC_Pos (0UL) /*!< FCIC (Bit 0) */ + #define R_RMAC0_MFCICT_FCIC_Msk (0xffffUL) /*!< FCIC (Bitfield-Mask: 0xffff) */ +/* ======================================================== MEEECT ========================================================= */ + #define R_RMAC0_MEEECT_EEERC_Pos (0UL) /*!< EEERC (Bit 0) */ + #define R_RMAC0_MEEECT_EEERC_Msk (0xffffUL) /*!< EEERC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MMPCFTCT0 ======================================================= */ + #define R_RMAC0_MMPCFTCT0_MPCFCTC_Pos (0UL) /*!< MPCFCTC (Bit 0) */ + #define R_RMAC0_MMPCFTCT0_MPCFCTC_Msk (0xffffUL) /*!< MPCFCTC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MMPCFTCT1 ======================================================= */ + #define R_RMAC0_MMPCFTCT1_MPCFCTC_Pos (0UL) /*!< MPCFCTC (Bit 0) */ + #define R_RMAC0_MMPCFTCT1_MPCFCTC_Msk (0xffffUL) /*!< MPCFCTC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MAPCFTCT0 ======================================================= */ + #define R_RMAC0_MAPCFTCT0_APCFCTC_Pos (0UL) /*!< APCFCTC (Bit 0) */ + #define R_RMAC0_MAPCFTCT0_APCFCTC_Msk (0xffffUL) /*!< APCFCTC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MAPCFTCT1 ======================================================= */ + #define R_RMAC0_MAPCFTCT1_APCFCTC_Pos (0UL) /*!< APCFCTC (Bit 0) */ + #define R_RMAC0_MAPCFTCT1_APCFCTC_Msk (0xffffUL) /*!< APCFCTC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT0 ======================================================== */ + #define R_RMAC0_MPCFRCT0_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT0_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT1 ======================================================== */ + #define R_RMAC0_MPCFRCT1_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT1_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT2 ======================================================== */ + #define R_RMAC0_MPCFRCT2_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT2_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT3 ======================================================== */ + #define R_RMAC0_MPCFRCT3_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT3_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT4 ======================================================== */ + #define R_RMAC0_MPCFRCT4_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT4_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT5 ======================================================== */ + #define R_RMAC0_MPCFRCT5_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT5_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT6 ======================================================== */ + #define R_RMAC0_MPCFRCT6_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT6_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT7 ======================================================== */ + #define R_RMAC0_MPCFRCT7_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT7_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================== MROVFC ========================================================= */ + #define R_RMAC0_MROVFC_ROVFC_Pos (0UL) /*!< ROVFC (Bit 0) */ + #define R_RMAC0_MROVFC_ROVFC_Msk (0xffffffffUL) /*!< ROVFC (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= MRHCRCEC ======================================================== */ + #define R_RMAC0_MRHCRCEC_RHCRCEC_Pos (0UL) /*!< RHCRCEC (Bit 0) */ + #define R_RMAC0_MRHCRCEC_RHCRCEC_Msk (0xffffUL) /*!< RHCRCEC (Bitfield-Mask: 0xffff) */ +/* ======================================================== MRGFCE ========================================================= */ + #define R_RMAC0_MRGFCE_RGFNE_Pos (0UL) /*!< RGFNE (Bit 0) */ + #define R_RMAC0_MRGFCE_RGFNE_Msk (0xffffffffUL) /*!< RGFNE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRGFCP ========================================================= */ + #define R_RMAC0_MRGFCP_RGFNP_Pos (0UL) /*!< RGFNP (Bit 0) */ + #define R_RMAC0_MRGFCP_RGFNP_Msk (0xffffffffUL) /*!< RGFNP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MRBFC ========================================================= */ + #define R_RMAC0_MRBFC_RBFN_Pos (0UL) /*!< RBFN (Bit 0) */ + #define R_RMAC0_MRBFC_RBFN_Msk (0xffffffffUL) /*!< RBFN (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MRMFC ========================================================= */ + #define R_RMAC0_MRMFC_RMFN_Pos (0UL) /*!< RMFN (Bit 0) */ + #define R_RMAC0_MRMFC_RMFN_Msk (0xffffffffUL) /*!< RMFN (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MRUFC ========================================================= */ + #define R_RMAC0_MRUFC_RUFN_Pos (0UL) /*!< RUFN (Bit 0) */ + #define R_RMAC0_MRUFC_RUFN_Msk (0xffffffffUL) /*!< RUFN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRPEFC ========================================================= */ + #define R_RMAC0_MRPEFC_RPEFN_Pos (0UL) /*!< RPEFN (Bit 0) */ + #define R_RMAC0_MRPEFC_RPEFN_Msk (0xffffUL) /*!< RPEFN (Bitfield-Mask: 0xffff) */ +/* ======================================================== MRNEFC ========================================================= */ + #define R_RMAC0_MRNEFC_RNEFN_Pos (0UL) /*!< RNEFN (Bit 0) */ + #define R_RMAC0_MRNEFC_RNEFN_Msk (0xffffUL) /*!< RNEFN (Bitfield-Mask: 0xffff) */ +/* ======================================================== MRFMEFC ======================================================== */ + #define R_RMAC0_MRFMEFC_RFMEFN_Pos (0UL) /*!< RFMEFN (Bit 0) */ + #define R_RMAC0_MRFMEFC_RFMEFN_Msk (0xffffffffUL) /*!< RFMEFN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= MRFFMEFC ======================================================== */ + #define R_RMAC0_MRFFMEFC_RFFMEFN_Pos (0UL) /*!< RFFMEFN (Bit 0) */ + #define R_RMAC0_MRFFMEFC_RFFMEFN_Msk (0xffffUL) /*!< RFFMEFN (Bitfield-Mask: 0xffff) */ +/* ======================================================= MRCFCEFC ======================================================== */ + #define R_RMAC0_MRCFCEFC_RCFCEFN_Pos (0UL) /*!< RCFCEFN (Bit 0) */ + #define R_RMAC0_MRCFCEFC_RCFCEFN_Msk (0xffffUL) /*!< RCFCEFN (Bitfield-Mask: 0xffff) */ +/* ======================================================== MRFCEFC ======================================================== */ + #define R_RMAC0_MRFCEFC_RFCEFN_Pos (0UL) /*!< RFCEFN (Bit 0) */ + #define R_RMAC0_MRFCEFC_RFCEFN_Msk (0xffffUL) /*!< RFCEFN (Bitfield-Mask: 0xffff) */ +/* ======================================================= MRRCFEFC ======================================================== */ + #define R_RMAC0_MRRCFEFC_RRCFEFN_Pos (0UL) /*!< RRCFEFN (Bit 0) */ + #define R_RMAC0_MRRCFEFC_RRCFEFN_Msk (0xffffUL) /*!< RRCFEFN (Bitfield-Mask: 0xffff) */ +/* ========================================================= MRFC ========================================================== */ + #define R_RMAC0_MRFC_RFN_Pos (0UL) /*!< RFN (Bit 0) */ + #define R_RMAC0_MRFC_RFN_Msk (0xffffffffUL) /*!< RFN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRGUEFC ======================================================== */ + #define R_RMAC0_MRGUEFC_RUEFN_Pos (0UL) /*!< RUEFN (Bit 0) */ + #define R_RMAC0_MRGUEFC_RUEFN_Msk (0xffffffffUL) /*!< RUEFN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRBUEFC ======================================================== */ + #define R_RMAC0_MRBUEFC_RUEFN_Pos (0UL) /*!< RUEFN (Bit 0) */ + #define R_RMAC0_MRBUEFC_RUEFN_Msk (0xffffffffUL) /*!< RUEFN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRGOEFC ======================================================== */ + #define R_RMAC0_MRGOEFC_RGOEFN_Pos (0UL) /*!< RGOEFN (Bit 0) */ + #define R_RMAC0_MRGOEFC_RGOEFN_Msk (0xffffffffUL) /*!< RGOEFN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRBOEFC ======================================================== */ + #define R_RMAC0_MRBOEFC_RBOEFN_Pos (0UL) /*!< RBOEFN (Bit 0) */ + #define R_RMAC0_MRBOEFC_RBOEFN_Msk (0xffffffffUL) /*!< RBOEFN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRXBCEU ======================================================== */ + #define R_RMAC0_MRXBCEU_RBNEU_Pos (0UL) /*!< RBNEU (Bit 0) */ + #define R_RMAC0_MRXBCEU_RBNEU_Msk (0xffffffffUL) /*!< RBNEU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRXBCEL ======================================================== */ + #define R_RMAC0_MRXBCEL_RBNEL_Pos (0UL) /*!< RBNEL (Bit 0) */ + #define R_RMAC0_MRXBCEL_RBNEL_Msk (0xffffffffUL) /*!< RBNEL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRXBCPU ======================================================== */ + #define R_RMAC0_MRXBCPU_RBNPU_Pos (0UL) /*!< RBNPU (Bit 0) */ + #define R_RMAC0_MRXBCPU_RBNPU_Msk (0xffffffffUL) /*!< RBNPU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRXBCPL ======================================================== */ + #define R_RMAC0_MRXBCPL_RBNPL_Pos (0UL) /*!< RBNPL (Bit 0) */ + #define R_RMAC0_MRXBCPL_RBNPL_Msk (0xffffffffUL) /*!< RBNPL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MTGFCE ========================================================= */ + #define R_RMAC0_MTGFCE_TGFNE_Pos (0UL) /*!< TGFNE (Bit 0) */ + #define R_RMAC0_MTGFCE_TGFNE_Msk (0xffffffffUL) /*!< TGFNE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MTGFCP ========================================================= */ + #define R_RMAC0_MTGFCP_TGFNP_Pos (0UL) /*!< TGFNP (Bit 0) */ + #define R_RMAC0_MTGFCP_TGFNP_Msk (0xffffffffUL) /*!< TGFNP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MTBFC ========================================================= */ + #define R_RMAC0_MTBFC_TBFN_Pos (0UL) /*!< TBFN (Bit 0) */ + #define R_RMAC0_MTBFC_TBFN_Msk (0xffffffffUL) /*!< TBFN (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MTMFC ========================================================= */ + #define R_RMAC0_MTMFC_TMFN_Pos (0UL) /*!< TMFN (Bit 0) */ + #define R_RMAC0_MTMFC_TMFN_Msk (0xffffffffUL) /*!< TMFN (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MTUFC ========================================================= */ + #define R_RMAC0_MTUFC_TUFN_Pos (0UL) /*!< TUFN (Bit 0) */ + #define R_RMAC0_MTUFC_TUFN_Msk (0xffffffffUL) /*!< TUFN (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MTEFC ========================================================= */ + #define R_RMAC0_MTEFC_TEFN_Pos (0UL) /*!< TEFN (Bit 0) */ + #define R_RMAC0_MTEFC_TEFN_Msk (0xffffUL) /*!< TEFN (Bitfield-Mask: 0xffff) */ +/* ======================================================== MTXBCEU ======================================================== */ + #define R_RMAC0_MTXBCEU_TBNEU_Pos (0UL) /*!< TBNEU (Bit 0) */ + #define R_RMAC0_MTXBCEU_TBNEU_Msk (0xffffffffUL) /*!< TBNEU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MTXBCEL ======================================================== */ + #define R_RMAC0_MTXBCEL_TBNEL_Pos (0UL) /*!< TBNEL (Bit 0) */ + #define R_RMAC0_MTXBCEL_TBNEL_Msk (0xffffffffUL) /*!< TBNEL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MTXBCPU ======================================================== */ + #define R_RMAC0_MTXBCPU_TBNPU_Pos (0UL) /*!< TBNPU (Bit 0) */ + #define R_RMAC0_MTXBCPU_TBNPU_Msk (0xffffffffUL) /*!< TBNPU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MTXBCPL ======================================================== */ + #define R_RMAC0_MTXBCPL_TBNPL_Pos (0UL) /*!< TBNPL (Bit 0) */ + #define R_RMAC0_MTXBCPL_TBNPL_Msk (0xffffffffUL) /*!< TBNPL (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_TCM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= TCMPRCR_S ======================================================= */ + #define R_TCM_TCMPRCR_S_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_TCM_TCMPRCR_S_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMPRCR_S_KW_Pos (8UL) /*!< KW (Bit 8) */ + #define R_TCM_TCMPRCR_S_KW_Msk (0xff00UL) /*!< KW (Bitfield-Mask: 0xff) */ +/* ====================================================== TCMPRCR_NS ======================================================= */ + #define R_TCM_TCMPRCR_NS_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_TCM_TCMPRCR_NS_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMPRCR_NS_KW_Pos (8UL) /*!< KW (Bit 8) */ + #define R_TCM_TCMPRCR_NS_KW_Msk (0xff00UL) /*!< KW (Bitfield-Mask: 0xff) */ +/* ======================================================== TCMCRC ========================================================= */ + #define R_TCM_TCMCRC_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_TCM_TCMCRC_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMCRC_ECCMOD_Pos (2UL) /*!< ECCMOD (Bit 2) */ + #define R_TCM_TCMCRC_ECCMOD_Msk (0xcUL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ + #define R_TCM_TCMCRC_E1STSEN_Pos (4UL) /*!< E1STSEN (Bit 4) */ + #define R_TCM_TCMCRC_E1STSEN_Msk (0x10UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMCRC_TSTBYP_Pos (7UL) /*!< TSTBYP (Bit 7) */ + #define R_TCM_TCMCRC_TSTBYP_Msk (0x80UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== TCMCRS ========================================================= */ + #define R_TCM_TCMCRS_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_TCM_TCMCRS_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMCRS_ECCMOD_Pos (2UL) /*!< ECCMOD (Bit 2) */ + #define R_TCM_TCMCRS_ECCMOD_Msk (0xcUL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ + #define R_TCM_TCMCRS_E1STSEN_Pos (4UL) /*!< E1STSEN (Bit 4) */ + #define R_TCM_TCMCRS_E1STSEN_Msk (0x10UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMCRS_TSTBYP_Pos (7UL) /*!< TSTBYP (Bit 7) */ + #define R_TCM_TCMCRS_TSTBYP_Msk (0x80UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== TCMESR ========================================================= */ + #define R_TCM_TCMESR_ERRC0_Pos (0UL) /*!< ERRC0 (Bit 0) */ + #define R_TCM_TCMESR_ERRC0_Msk (0x1UL) /*!< ERRC0 (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMESR_ERRC1_Pos (1UL) /*!< ERRC1 (Bit 1) */ + #define R_TCM_TCMESR_ERRC1_Msk (0x2UL) /*!< ERRC1 (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMESR_ERRS0_Pos (2UL) /*!< ERRS0 (Bit 2) */ + #define R_TCM_TCMESR_ERRS0_Msk (0x4UL) /*!< ERRS0 (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMESR_ERRS1_Pos (3UL) /*!< ERRS1 (Bit 3) */ + #define R_TCM_TCMESR_ERRS1_Msk (0x8UL) /*!< ERRS1 (Bitfield-Mask: 0x01) */ +/* ======================================================= TCMESCLR ======================================================== */ + #define R_TCM_TCMESCLR_CLRC0_Pos (0UL) /*!< CLRC0 (Bit 0) */ + #define R_TCM_TCMESCLR_CLRC0_Msk (0x1UL) /*!< CLRC0 (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMESCLR_CLRC1_Pos (1UL) /*!< CLRC1 (Bit 1) */ + #define R_TCM_TCMESCLR_CLRC1_Msk (0x2UL) /*!< CLRC1 (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMESCLR_CLRS0_Pos (2UL) /*!< CLRS0 (Bit 2) */ + #define R_TCM_TCMESCLR_CLRS0_Msk (0x4UL) /*!< CLRS0 (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMESCLR_CLRS1_Pos (3UL) /*!< CLRS1 (Bit 3) */ + #define R_TCM_TCMESCLR_CLRS1_Msk (0x8UL) /*!< CLRS1 (Bitfield-Mask: 0x01) */ +/* ======================================================= TCMEARC0 ======================================================== */ + #define R_TCM_TCMEARC0_EAR_Pos (2UL) /*!< EAR (Bit 2) */ + #define R_TCM_TCMEARC0_EAR_Msk (0x3fffcUL) /*!< EAR (Bitfield-Mask: 0xffff) */ +/* ======================================================= TCMEARC1 ======================================================== */ + #define R_TCM_TCMEARC1_EAR_Pos (2UL) /*!< EAR (Bit 2) */ + #define R_TCM_TCMEARC1_EAR_Msk (0x3fffcUL) /*!< EAR (Bitfield-Mask: 0xffff) */ +/* ======================================================= TCMEARS0 ======================================================== */ + #define R_TCM_TCMEARS0_EAR_Pos (2UL) /*!< EAR (Bit 2) */ + #define R_TCM_TCMEARS0_EAR_Msk (0x3fffcUL) /*!< EAR (Bitfield-Mask: 0xffff) */ +/* ======================================================= TCMEARS1 ======================================================== */ + #define R_TCM_TCMEARS1_EAR_Pos (2UL) /*!< EAR (Bit 2) */ + #define R_TCM_TCMEARS1_EAR_Msk (0x3fffcUL) /*!< EAR (Bitfield-Mask: 0xffff) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R7KA8P1KF_CORE0_H */ + +/** @} */ /* End of group R7KA8P1KF_core0 */ + +/** @} */ /* End of group Renesas */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7KA8P1KF_core1.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7KA8P1KF_core1.h new file mode 100644 index 00000000000..883acf9c890 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7KA8P1KF_core1.h @@ -0,0 +1,94482 @@ +/* + * Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause + * + * @file ./out/R7KA8P1KF_core1.h + * @brief CMSIS HeaderFile + * @version 0.1 + */ + +/** @addtogroup Renesas + * @{ + */ + +/** @addtogroup R7KA8P1KF_core1 + * @{ + */ + +#ifndef R7KA8P1KF_CORE1_H + #define R7KA8P1KF_CORE1_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ + #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ + #define __MPU_PRESENT 1 /*!< MPU present */ + #define __FPU_PRESENT 1 /*!< FPU present */ + #define __FPU_DP 0 /*!< Double Precision FPU */ + #define __DSP_PRESENT 1 /*!< DSP extension present */ + #define __ICACHE_PRESENT 0 /*!< Instruction Cache present */ + #define __DCACHE_PRESENT 0 /*!< Data Cache present */ + #define __SAUREGION_PRESENT 1 /*!< SAU region present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "system.h" /*!< R7KA8P1KF_core1 System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_BUS_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ + + struct + { + __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint8_t : 3; + __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ + uint8_t : 2; + } SDCCR_b; + }; + + union + { + __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ + + struct + { + __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ + uint8_t : 7; + } SDCMOD_b; + }; + + union + { + __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ + + struct + { + __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ + uint8_t : 7; + } SDAMOD_b; + }; + __IM uint8_t RESERVED; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ + + struct + { + __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ + uint8_t : 7; + } SDSELF_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ + + struct + { + __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ + __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count + * Setting. ( REFW+1 Cycles ) */ + } SDRFCR_b; + }; + + union + { + __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ + + struct + { + __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ + uint8_t : 7; + } SDRFEN_b; + }; + __IM uint8_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ + } ADD_b; + }; + + union + { + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ + + struct + { + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ + + struct + { + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; + } STAT_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x00000004) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ + + struct + { + __IOM uint8_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint8_t : 7; + } IRQEN_b; + }; + __IM uint8_t RESERVED2[7]; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ + + struct + { + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; + }; + __IM uint8_t RESERVED1[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ + + struct + { + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; + }; +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ + +/** + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t SPI0BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t SPI1BI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU1TCMBI_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t PBBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; + }; + __IM uint32_t RESERVED13; + + union + { + __IOM uint32_t PABI; /*!< (@ 0x00000080) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t PIBI; /*!< (@ 0x00000088) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; + __IM uint32_t RESERVED15; + + union + { + __IOM uint32_t PSBI; /*!< (@ 0x00000090) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; + }; +} R_BUS_BUSSABT0_Type; /*!< Size = 148 (0x94) */ + +/** + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; + + union + { + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; + }; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; + }; +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ + +/** + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ + + struct + { + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ + + struct + { + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ + + struct + { + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; + }; + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; + }; +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ + +/** + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ + uint16_t : 10; + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status) + */ +typedef struct +{ + union + { + __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */ + + struct + { + __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */ + __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */ + __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */ + __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */ + } NCFG_b; + }; + + union + { + __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */ + + struct + { + __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */ + __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */ + __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */ + uint32_t : 4; + __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */ + __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */ + __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */ + __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */ + __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */ + __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */ + __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */ + __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */ + __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */ + __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */ + __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */ + __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt + * enable */ + uint32_t : 1; + __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */ + __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */ + __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */ + __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */ + uint32_t : 3; + __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */ + __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */ + } CTR_b; + }; + + union + { + __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */ + + struct + { + __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */ + __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */ + __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */ + __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */ + __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */ + __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */ + __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */ + __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */ + __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */ + uint32_t : 7; + __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */ + __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */ + } STS_b; + }; + + union + { + __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */ + + struct + { + __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */ + __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */ + __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */ + __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */ + __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */ + __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */ + __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */ + __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */ + __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */ + __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */ + __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */ + __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */ + __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */ + __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */ + __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */ + uint32_t : 1; + __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */ + uint32_t : 1; + } ERFL_b; + }; +} R_CANFD_CFDC_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */ + + struct + { + __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */ + __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */ + uint32_t : 3; + __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */ + uint32_t : 4; + __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */ + uint32_t : 4; + } DCFG_b; + }; + + union + { + __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */ + + struct + { + __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */ + uint32_t : 5; + __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */ + __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */ + __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */ + uint32_t : 5; + __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */ + uint32_t : 4; + __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */ + __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */ + __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */ + uint32_t : 1; + } FDCFG_b; + }; + + union + { + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */ + + struct + { + __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */ + __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */ + uint32_t : 30; + } FDCTR_b; + }; + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */ + + struct + { + __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */ + __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */ + __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */ + uint32_t : 5; + __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */ + __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */ + __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */ + } FDSTS_b; + }; + + union + { + __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */ + + struct + { + __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */ + uint32_t : 3; + __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */ + uint32_t : 4; + } FDCRC_b; + }; + __IM uint32_t RESERVED[3]; +} R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers */ + + struct + { + __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */ + __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */ + __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */ + __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */ + } ID_b; + }; + + union + { + __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers */ + + struct + { + __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */ + __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */ + __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */ + __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */ + } M_b; + }; + + union + { + __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers */ + + struct + { + __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */ + uint32_t : 3; + __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */ + __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction + * Pointer */ + uint32_t : 2; + __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */ + __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */ + } P0_b; + }; + + union + { + __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */ + + struct + { + __IOM uint32_t GAFLFDP : 9; /*!< [8..0] Global Acceptance Filter List FIFO Direction Pointer */ + uint32_t : 23; + } P1_b; + }; +} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List) + */ +typedef struct +{ + union + { + __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */ + + struct + { + __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */ + __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */ + uint32_t : 6; + __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */ + } ACC0_b; + }; + + union + { + __IOM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */ + + struct + { + __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */ + __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */ + uint32_t : 14; + } ACC1_b; + }; +} R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */ + + struct + { + __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */ + __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */ + + struct + { + __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */ + uint32_t : 12; + __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */ + + struct + { + __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */ + + struct + { + __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDRF_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */ + + struct + { + __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ + __IOM uint32_t THLEN : 1; /*!< [29..29] THL Entry enable */ + __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ + __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */ + + struct + { + __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */ + uint32_t : 12; + __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */ + + struct + { + __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */ + + struct + { + __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDCF_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */ + + struct + { + __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ + __IOM uint32_t THLEN : 1; /*!< [29..29] Tx History List Entry */ + __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ + __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */ + + struct + { + __IOM uint32_t TMTS : 16; /*!< [15..0] TX Message Buffer Timestamp Field */ + uint32_t : 12; + __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */ + + struct + { + __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */ + } FDCTR_b; + }; + + union + { + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */ + + struct + { + __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDTM_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDRM_RM [RM] (RX Message Buffer Access Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ + + struct + { + __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */ + __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ + + struct + { + __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ + uint32_t : 12; + __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ + + struct + { + __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */ + + struct + { + __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDRM_RM_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Clusters) + */ +typedef struct +{ + __IOM R_CANFD_CFDRM_RM_Type RM[8]; /*!< (@ 0x00000000) RX Message Buffer Access Registers */ + __IM uint32_t RESERVED[104]; +} R_CANFD_CFDRM_Type; /*!< Size = 1024 (0x400) */ + +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + + struct + { + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; + }; + __IM uint8_t RESERVED[3]; +} R_ELC_ELSEGR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..52]) + */ +typedef struct +{ + union + { + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + + struct + { + __IOM uint16_t ELS : 10; /*!< [9..0] Event Link Select */ + uint16_t : 6; + } HA_b; + }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_GLCDC_BG [BG] (Background Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t EN; /*!< (@ 0x00000000) Background Plane Setting Operation Control Register */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Background plane generation module operation enable */ + uint32_t : 7; + __IOM uint32_t VEN : 1; /*!< [8..8] Control of LCDC internal register value reflection to + * internal operations */ + uint32_t : 7; + __IOM uint32_t SWRST : 1; /*!< [16..16] Entire module SW reset control */ + uint32_t : 15; + } EN_b; + }; + + union + { + __IOM uint32_t PERI; /*!< (@ 0x00000004) Background Plane Setting Free-Running Period + * Register */ + + struct + { + __IOM uint32_t FH : 11; /*!< [10..0] Background plane horizontal synchronization signal period + * on the basis of pixel clock (PXCLK). */ + uint32_t : 5; + __IOM uint32_t FV : 11; /*!< [26..16] Background plane vertical synchronization signal period + * on the basis of line. */ + uint32_t : 5; + } PERI_b; + }; + + union + { + __IOM uint32_t SYNC; /*!< (@ 0x00000008) Background Plane Setting Synchronization Position + * Register */ + + struct + { + __IOM uint32_t HP : 4; /*!< [3..0] Background plane horizontal synchronization signal assertion + * position on the basis of pixel clock (PXCLK). */ + uint32_t : 12; + __IOM uint32_t VP : 4; /*!< [19..16] Background plane vertical synchronization signal assertion + * position on the basis of line. */ + uint32_t : 12; + } SYNC_b; + }; + + union + { + __IOM uint32_t VSIZE; /*!< (@ 0x0000000C) Background Plane Setting Full Image Vertical + * Size Register */ + + struct + { + __IOM uint32_t VW : 11; /*!< [10..0] Background plane vertical valid pixel width on the basis + * of line */ + uint32_t : 5; + __IOM uint32_t VP : 11; /*!< [26..16] Background plane vertical valid pixel start position + * on the basis of line */ + uint32_t : 5; + } VSIZE_b; + }; + + union + { + __IOM uint32_t HSIZE; /*!< (@ 0x00000010) Background Plane Setting Full Image Horizontal + * Size Register */ + + struct + { + __IOM uint32_t HW : 11; /*!< [10..0] Background plane horizontall valid pixel width on the + * basis of pixel clock (PXCLK) Note: When serial RGB is selected + * as the output format for the output control block, add + * two to the horizontal enable signal width and set the resulting + * value to this field. */ + uint32_t : 5; + __IOM uint32_t HP : 11; /*!< [26..16] Background plane horizontal valid pixel start position + * on the basis of pixel clock (PXCLK). */ + uint32_t : 5; + } HSIZE_b; + }; + + union + { + __IOM uint32_t BGC; /*!< (@ 0x00000014) Background Plane Setting Background Color Register */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B value for background plane valid pixel area Unsigned; + * 8-bit integer */ + __IOM uint32_t G : 8; /*!< [15..8] G value for background plane valid pixel area Unsigned; + * 8-bit integer */ + __IOM uint32_t R : 8; /*!< [23..16] R value for background plane valid pixel area. Unsigned; + * 8-bit integer. */ + uint32_t : 8; + } BGC_b; + }; + + union + { + __IM uint32_t MON; /*!< (@ 0x00000018) Background Plane Setting Status Monitor Register */ + + struct + { + __IM uint32_t EN : 1; /*!< [0..0] Background plane generation module operation state monitor. */ + uint32_t : 7; + __IM uint32_t VEN : 1; /*!< [8..8] Entire module internal operation reflection control signal + * monitor. The signal state for controlling reflection of + * the register values to the internal operations upon assertion + * of the vertical synchronization signal. */ + uint32_t : 7; + __IM uint32_t SWRST : 1; /*!< [16..16] Entire module SW reset state monitor. */ + uint32_t : 15; + } MON_b; + }; +} R_GLCDC_BG_Type; /*!< Size = 28 (0x1c) */ + +/** + * @brief R_GLCDC_GR [GR] (Layer Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t VEN; /*!< (@ 0x00000000) Graphics Register Update Control Register */ + + struct + { + __IOM uint32_t PVEN : 1; /*!< [0..0] Control of graphics n module register value reflection + * to internal operations. Reflection of the register values + * to the internal operation at the assertion of the vertical + * synchronization signal (VS). */ + uint32_t : 31; + } VEN_b; + }; + + union + { + __IOM uint32_t FLMRD; /*!< (@ 0x00000004) Graphics Frame Buffer Read Control Register */ + + struct + { + __IOM uint32_t RENB : 1; /*!< [0..0] Graphics data (frame buffer data) read enable. */ + uint32_t : 31; + } FLMRD_b; + }; + + union + { + __IM uint32_t FLM1; /*!< (@ 0x00000008) Graphics Frame Buffer Control Register 1 */ + + struct + { + __IM uint32_t BSTMD : 2; /*!< [1..0] Burst transfer control for graphics data (frame buffer + * data) access */ + uint32_t : 30; + } FLM1_b; + }; + + union + { + __IOM uint32_t FLM2; /*!< (@ 0x0000000C) Graphics Frame Buffer Control Register 2 */ + + struct + { + __IOM uint32_t BASE : 32; /*!< [31..0] Base address for accessing graphics data (frame buffer + * data) Set the head address in the frame buffer where graphics + * data is to be stored. GRn_FLM2.BASE[5:0] should be fixed + * to 0 during 64-byte burst transfer. */ + } FLM2_b; + }; + + union + { + __IOM uint32_t FLM3; /*!< (@ 0x00000010) Graphics Frame Buffer Control Register 3 */ + + struct + { + uint32_t : 16; + __IOM uint32_t LNOFF : 16; /*!< [31..16] Macro line offset address for accessing graphics data + * (frame buffer data) Signed; 16-bit integer */ + } FLM3_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t FLM5; /*!< (@ 0x00000018) Graphics Frame Buffer Control Register 5 */ + + struct + { + __IOM uint32_t DATANUM : 16; /*!< [15..0] Number of data transfer times per line for accessing + * graphics data (frame buffer data), where one transfer is + * defined as 16-beat burst access (64-byte boundary) */ + __IOM uint32_t LNNUM : 11; /*!< [26..16] Number of lines per frame for accessing graphics data + * (frame buffer data). */ + uint32_t : 5; + } FLM5_b; + }; + + union + { + __IOM uint32_t FLM6; /*!< (@ 0x0000001C) Graphics Frame Buffer Control Register 6 */ + + struct + { + uint32_t : 28; + __IOM uint32_t FORMAT : 3; /*!< [30..28] Data format for accessing graphics data (frame buffer + * data). */ + uint32_t : 1; + } FLM6_b; + }; + + union + { + __IOM uint32_t AB1; /*!< (@ 0x00000020) Graphics Alpha Blending Control Register 1 */ + + struct + { + __IOM uint32_t DISPSEL : 2; /*!< [1..0] Graphics display plane control. */ + uint32_t : 2; + __IOM uint32_t GRCDISPON : 1; /*!< [4..4] Graphics image area border display control. */ + uint32_t : 3; + __IOM uint32_t ARCDISPON : 1; /*!< [8..8] Image area border display control for rectangular area + * alpha blending. */ + uint32_t : 3; + __IOM uint32_t ARCON : 1; /*!< [12..12] Rectangular area alpha blending control. */ + uint32_t : 19; + } AB1_b; + }; + + union + { + __IOM uint32_t AB2; /*!< (@ 0x00000024) Graphics Alpha Blending Control Register 2 */ + + struct + { + __IOM uint32_t GRCVW : 11; /*!< [10..0] Vertical width of graphics image area. */ + uint32_t : 5; + __IOM uint32_t GRCVS : 11; /*!< [26..16] Vertical start position of graphics image area. */ + uint32_t : 5; + } AB2_b; + }; + + union + { + __IOM uint32_t AB3; /*!< (@ 0x00000028) Graphics Alpha Blending Control Register 3 */ + + struct + { + __IOM uint32_t GRCHW : 11; /*!< [10..0] Horizontal width of graphics image area. */ + uint32_t : 5; + __IOM uint32_t GRCHS : 11; /*!< [26..16] Horizontal start position of graphics image area. */ + uint32_t : 5; + } AB3_b; + }; + + union + { + __IOM uint32_t AB4; /*!< (@ 0x0000002C) Graphics Alpha Blending Control Register 4 */ + + struct + { + __IOM uint32_t ARCVW : 11; /*!< [10..0] Vertical width of rectangular area alpha blending image + * area. */ + uint32_t : 5; + __IOM uint32_t ARCVS : 11; /*!< [26..16] Vertical start position of rectangular area alpha blending + * image area */ + uint32_t : 5; + } AB4_b; + }; + + union + { + __IOM uint32_t AB5; /*!< (@ 0x00000030) Graphics Alpha Blending Control Register 5 */ + + struct + { + __IOM uint32_t ARCHW : 11; /*!< [10..0] Horizontal width of rectangular area alpha blending + * image area. */ + uint32_t : 5; + __IOM uint32_t ARCHS : 11; /*!< [26..16] Horizontal start position of rectangular area alpha + * blending image area. */ + uint32_t : 5; + } AB5_b; + }; + + union + { + __IOM uint32_t AB6; /*!< (@ 0x00000034) Graphics Alpha Blending Control Register 6 */ + + struct + { + __IOM uint32_t ARCRATE : 8; /*!< [7..0] Frame rate for alpha blending in rectangular area. */ + uint32_t : 8; + __IOM uint32_t ARCCOEF : 9; /*!< [24..16] Alpha coefficient for alpha blending in rectangular + * area (-255 to 255). [8]: Sign (0: addition, 1: subtraction) + * [7:0]: Variation (absolute value) */ + uint32_t : 7; + } AB6_b; + }; + + union + { + __IOM uint32_t AB7; /*!< (@ 0x00000038) Graphics Alpha Blending Control Register 7 */ + + struct + { + __IOM uint32_t CKON : 1; /*!< [0..0] RGB-index chroma-key processing control. */ + uint32_t : 15; + __IOM uint32_t ARCDEF : 8; /*!< [23..16] Initial alpha value for alpha blending in rectangular + * area. */ + uint32_t : 8; + } AB7_b; + }; + + union + { + __IOM uint32_t AB8; /*!< (@ 0x0000003C) Graphics Alpha Blending Control Register 8 */ + + struct + { + __IOM uint32_t CKKR : 8; /*!< [7..0] R signal for RGB-index chroma-key processing Unsigned; + * 8 bits. */ + __IOM uint32_t CKKB : 8; /*!< [15..8] B signal for RGB-index chroma-key processing Unsigned; + * 8 bits. */ + __IOM uint32_t CKKG : 8; /*!< [23..16] G signal for RGB-index chroma-key processing Unsigned; + * 8 bits. */ + uint32_t : 8; + } AB8_b; + }; + + union + { + __IOM uint32_t AB9; /*!< (@ 0x00000040) Graphics Alpha Blending Control Register 9 */ + + struct + { + __IOM uint32_t CKR : 8; /*!< [7..0] R value after RGB-index chroma-key processing replacement + * Unsigned; 8 bits. */ + __IOM uint32_t CKB : 8; /*!< [15..8] B value after RGB-index chroma-key processing replacement + * Unsigned; 8 bits. */ + __IOM uint32_t CKG : 8; /*!< [23..16] G value after RGB-index chroma-key processing replacement + * Unsigned; 8 bits. */ + __IOM uint32_t CKA : 8; /*!< [31..24] A value after RGB-index chroma-key processing replacement. */ + } AB9_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t BASE; /*!< (@ 0x0000004C) Graphics Background Color Control Register */ + + struct + { + __IOM uint32_t R : 8; /*!< [7..0] Background color R value Unsigned; 8 bits */ + __IOM uint32_t B : 8; /*!< [15..8] Background color B value Unsigned; 8 bits */ + __IOM uint32_t G : 8; /*!< [23..16] Background color G value Unsigned; 8 bits */ + uint32_t : 8; + } BASE_b; + }; + + union + { + __IOM uint32_t CLUTINT; /*!< (@ 0x00000050) Graphics CLUT Table Interrupt Control Register */ + + struct + { + __IOM uint32_t LINE : 11; /*!< [10..0] Number of detection lines */ + uint32_t : 5; + __IOM uint32_t SEL : 1; /*!< [16..16] CLUT table control */ + uint32_t : 15; + } CLUTINT_b; + }; + + union + { + __IM uint32_t MON; /*!< (@ 0x00000054) Graphics Status Monitor Register */ + + struct + { + __IM uint32_t ARCST : 1; /*!< [0..0] Status monitor for alpha blending in rectangular area */ + uint32_t : 15; + __IM uint32_t UNDFLST : 1; /*!< [16..16] Status monitor for underflow */ + uint32_t : 15; + } MON_b; + }; + __IM uint32_t RESERVED2[42]; +} R_GLCDC_GR_Type; /*!< Size = 256 (0x100) */ + +/** + * @brief R_GLCDC_GAM [GAM] (Gamma Settings) + */ +typedef struct +{ + union + { + __IOM uint32_t LATCH; /*!< (@ 0x00000000) Gamma Register Update Control Register */ + + struct + { + __IOM uint32_t VEN : 1; /*!< [0..0] Control of gamma correction x module register value reflection + * to internal operations. The register values to be reflected + * to the internal operations at the assertion of the vertical + * synchronization signal (VS). */ + uint32_t : 31; + } LATCH_b; + }; + + union + { + __IOM uint32_t GAM_SW; /*!< (@ 0x00000004) Gamma Correction Block Function Switch Register */ + + struct + { + __IOM uint32_t GAMON : 1; /*!< [0..0] Gamma correction on/off control */ + uint32_t : 31; + } GAM_SW_b; + }; + + union + { + __IOM uint32_t LUT[8]; /*!< (@ 0x00000008) Gamma Correction Block Table Setting Register */ + + struct + { + __IOM uint32_t _HIGH : 11; /*!< [10..0] Gain value of area 0. Unsigned 11-bit fixed point. */ + uint32_t : 5; + __IOM uint32_t _LOW : 11; /*!< [26..16] Gain value of area 0. Unsigned 11-bit fixed point. */ + uint32_t : 5; + } LUT_b[8]; + }; + + union + { + __IOM uint32_t AREA[5]; /*!< (@ 0x00000028) Gamma Correction Block Area Setting Register */ + + struct + { + __IOM uint32_t _HIGH : 10; /*!< [9..0] Start threshold of area 1 Unsigned 10-bit integer */ + __IOM uint32_t _MID : 10; /*!< [19..10] Start threshold of area 1 Unsigned 10-bit integer */ + __IOM uint32_t _LOW : 10; /*!< [29..20] Start threshold of area 1 Unsigned 10-bit integer */ + uint32_t : 2; + } AREA_b[5]; + }; + __IM uint32_t RESERVED; +} R_GLCDC_GAM_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_GLCDC_OUT [OUT] (Output Control Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t VLATCH; /*!< (@ 0x00000000) Output Control Block Register Update Control + * Register */ + + struct + { + __IOM uint32_t VEN : 1; /*!< [0..0] Control of output control module register value reflection + * to internal operations. The register values to be reflected + * to the internal operations at the assertion of the vertical + * synchronization signal (VS). */ + uint32_t : 31; + } VLATCH_b; + }; + + union + { + __IOM uint32_t SET; /*!< (@ 0x00000004) Output Control Block Output Interface Register */ + + struct + { + __IOM uint32_t PHASE : 2; /*!< [1..0] Data delay in serial RGB format (based on OUTCLK) */ + uint32_t : 2; + __IOM uint32_t DIRSEL : 1; /*!< [4..4] Invalid data position control in serial RGB format */ + uint32_t : 3; + __IOM uint32_t FRQSEL : 2; /*!< [9..8] Clock frequency division control */ + uint32_t : 2; + __IOM uint32_t FORMAT : 2; /*!< [13..12] Output format select */ + uint32_t : 10; + __IOM uint32_t SWAPON : 1; /*!< [24..24] Pixel order control */ + uint32_t : 3; + __IOM uint32_t ENDIANON : 1; /*!< [28..28] Bit endian change control */ + uint32_t : 3; + } SET_b; + }; + + union + { + __IOM uint32_t BRIGHT1; /*!< (@ 0x00000008) Output Control Block Brightness Correction Register + * 1 */ + + struct + { + __IOM uint32_t BRTG : 10; /*!< [9..0] Brightness (DC) adjustment of G signal Unsigned; 10 bits; + +512 with offset; integer */ + uint32_t : 22; + } BRIGHT1_b; + }; + + union + { + __IOM uint32_t BRIGHT2; /*!< (@ 0x0000000C) Output Control Block Brightness Correction Register + * 2 */ + + struct + { + __IOM uint32_t BRTR : 10; /*!< [9..0] Brightness (DC) adjustment of R signal Unsigned; 10 bits; + +512 with offset; integer */ + uint32_t : 6; + __IOM uint32_t BRTB : 10; /*!< [25..16] Brightness (DC) adjustment of B signal Unsigned; 10 + * bits; +512 with offset; integer */ + uint32_t : 6; + } BRIGHT2_b; + }; + + union + { + __IOM uint32_t CONTRAST; /*!< (@ 0x00000010) Output Control Block Contrast Correction Register */ + + struct + { + __IOM uint32_t CONTR : 8; /*!< [7..0] Contrast (GAIN) adjustment of R signal Unsigned; 8 bits + * fixed point */ + __IOM uint32_t CONTB : 8; /*!< [15..8] Contrast (GAIN) adjustment of B signal Unsigned; 8 bits + * fixed point */ + __IOM uint32_t CONTG : 8; /*!< [23..16] Contrast (GAIN) adjustment of G signal Unsigned; 8 + * bits fixed point. */ + uint32_t : 8; + } CONTRAST_b; + }; + + union + { + __IOM uint32_t PDTHA; /*!< (@ 0x00000014) Output Control Block Panel Dither Correction + * Register */ + + struct + { + __IOM uint32_t PD : 2; /*!< [1..0] Pattern value (D) of 2 x 2 pattern dither Unsigned 2-bit + * integer */ + uint32_t : 2; + __IOM uint32_t PC : 2; /*!< [5..4] Pattern value (C) of 2 x 2 pattern dither Unsigned 2-bit + * integer */ + uint32_t : 2; + __IOM uint32_t PB : 2; /*!< [9..8] Pattern value (B) of 2 x 2 pattern dither Unsigned 2-bit + * integer */ + uint32_t : 2; + __IOM uint32_t PA : 2; /*!< [13..12] Pattern value (A) of 2 x 2 pattern dither Unsigned + * 2-bit integer */ + uint32_t : 2; + __IOM uint32_t FORM : 2; /*!< [17..16] Output format select */ + uint32_t : 2; + __IOM uint32_t SEL : 2; /*!< [21..20] Operation mode */ + uint32_t : 10; + } PDTHA_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t CLKPHASE; /*!< (@ 0x00000024) Output Control Block Output Phase Control Register */ + + struct + { + uint32_t : 3; + __IOM uint32_t TCON3EDGE : 1; /*!< [3..3] LCD_TCON3 Output Phase Control */ + __IOM uint32_t TCON2EDGE : 1; /*!< [4..4] LCD_TCON2 Output Phase Control */ + __IOM uint32_t TCON1EDGE : 1; /*!< [5..5] LCD_TCON1 Output Phase Control */ + __IOM uint32_t TCON0EDGE : 1; /*!< [6..6] LCD_TCON0 Output Phase Control */ + uint32_t : 1; + __IOM uint32_t LCDEDGE : 1; /*!< [8..8] LCD_DATA Output Phase Control */ + uint32_t : 3; + __IOM uint32_t FRONTGAM : 1; /*!< [12..12] Correction control */ + uint32_t : 19; + } CLKPHASE_b; + }; +} R_GLCDC_OUT_Type; /*!< Size = 40 (0x28) */ + +/** + * @brief R_GLCDC_TCON [TCON] (Timing Control Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t TIM; /*!< (@ 0x00000004) TCON Reference Timing Setting Register */ + + struct + { + __IOM uint32_t OFFSET : 11; /*!< [10..0] Horizontal synchronization signal generation reference + * timing Sets the offset from the assertion of the internal + * horizontal synchronization signal in terms of pixels. */ + uint32_t : 5; + __IOM uint32_t HALF : 11; /*!< [26..16] Vertical synchronization signal generation change timing + * Sets the delay from the assertion of the internal horizontal + * synchronization signal in terms of pixels. */ + uint32_t : 5; + } TIM_b; + }; + + union + { + __IOM uint32_t STVA1; /*!< (@ 0x00000008) TCON Vertical Timing Setting Register A1 */ + + struct + { + __IOM uint32_t VW : 11; /*!< [10..0] STVx1 second change timing Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t VS : 11; /*!< [26..16] STVx1 first change timing */ + uint32_t : 5; + } STVA1_b; + }; + + union + { + __IOM uint32_t STVA2; /*!< (@ 0x0000000C) TCON Vertical Timing Setting Register A2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for VSOUT (controlled by + * TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2 + * register) pin */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control */ + uint32_t : 27; + } STVA2_b; + }; + + union + { + __IOM uint32_t STVB1; /*!< (@ 0x00000010) TCON Vertical Timing Setting Register B1 */ + + struct + { + __IOM uint32_t VW : 11; /*!< [10..0] STVx1 second change timing Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t VS : 11; /*!< [26..16] STVx1 first change timing */ + uint32_t : 5; + } STVB1_b; + }; + + union + { + __IOM uint32_t STVB2; /*!< (@ 0x00000014) TCON Vertical Timing Setting Register B2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for VSOUT (controlled by + * TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2 + * register) pin */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control */ + uint32_t : 27; + } STVB2_b; + }; + + union + { + __IOM uint32_t STHA1; /*!< (@ 0x00000018) TCON Horizontal Timing Setting Register STHA1 */ + + struct + { + __IOM uint32_t HW : 11; /*!< [10..0] STHx1 second change timing. Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t HS : 11; /*!< [26..16] STHx1 first change timing */ + uint32_t : 5; + } STHA1_b; + }; + + union + { + __IOM uint32_t STHA2; /*!< (@ 0x0000001C) TCON Horizontal Timing Setting Register STHA2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for LCD_TCON2 (controlled + * by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2 + * register) pin. */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control. */ + uint32_t : 3; + __IOM uint32_t HSSEL : 1; /*!< [8..8] STHx signal generation reference timing control. */ + uint32_t : 23; + } STHA2_b; + }; + + union + { + __IOM uint32_t STHB1; /*!< (@ 0x00000020) TCON Horizontal Timing Setting Register STHB1 */ + + struct + { + __IOM uint32_t HW : 11; /*!< [10..0] STHx1 second change timing. Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t HS : 11; /*!< [26..16] STHx1 first change timing */ + uint32_t : 5; + } STHB1_b; + }; + + union + { + __IOM uint32_t STHB2; /*!< (@ 0x00000024) TCON Horizontal Timing Setting Register STHB2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for LCD_TCON2 (controlled + * by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2 + * register) pin. */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control. */ + uint32_t : 3; + __IOM uint32_t HSSEL : 1; /*!< [8..8] STHx signal generation reference timing control. */ + uint32_t : 23; + } STHB2_b; + }; + + union + { + __IOM uint32_t DE; /*!< (@ 0x00000028) TCON Data Enable Polarity Setting Register */ + + struct + { + __IOM uint32_t INV : 1; /*!< [0..0] DE signal polarity inversion control. */ + uint32_t : 31; + } DE_b; + }; +} R_GLCDC_TCON_Type; /*!< Size = 44 (0x2c) */ + +/** + * @brief R_GLCDC_SYSCNT [SYSCNT] (GLCDC System Control Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t DTCTEN; /*!< (@ 0x00000000) System control block State Detection Control + * Register */ + + struct + { + __IOM uint32_t VPOSDTC : 1; /*!< [0..0] Specified line detection control */ + __IOM uint32_t L1UNDFDTC : 1; /*!< [1..1] Graphics 1 underflow detection control */ + __IOM uint32_t L2UNDFDTC : 1; /*!< [2..2] Graphics 2 underflow detection control */ + uint32_t : 29; + } DTCTEN_b; + }; + + union + { + __IOM uint32_t INTEN; /*!< (@ 0x00000004) System control block Interrupt Request Enable + * Control Register */ + + struct + { + __IOM uint32_t VPOSINTEN : 1; /*!< [0..0] Interrupt request signal GLCDC_VPOS enable control. */ + __IOM uint32_t L1UNDFINTEN : 1; /*!< [1..1] Interrupt request signal GLCDC_L1UNDF enable control. */ + __IOM uint32_t L2UNDFINTEN : 1; /*!< [2..2] Interrupt request signal GLCDC_L2UNDF enable control. */ + uint32_t : 29; + } INTEN_b; + }; + + union + { + __IOM uint32_t STCLR; /*!< (@ 0x00000008) System control block Status Clear Register */ + + struct + { + __IOM uint32_t VPOSCLR : 1; /*!< [0..0] Graphics 2 specified line detection flag clear field */ + __IOM uint32_t L1UNDFCLR : 1; /*!< [1..1] Graphics 1 underflow detection flag clear field */ + __IOM uint32_t L2UNDFCLR : 1; /*!< [2..2] Graphics 2 underflow detection flag clear field */ + uint32_t : 29; + } STCLR_b; + }; + + union + { + __IM uint32_t STMON; /*!< (@ 0x0000000C) System control block Status Monitor Register */ + + struct + { + __IM uint32_t VPOS : 1; /*!< [0..0] Graphics 2 specified line detection flag */ + __IM uint32_t L1UNDF : 1; /*!< [1..1] Graphics 1 underflow detection flag */ + __IM uint32_t L2UNDF : 1; /*!< [2..2] Graphics 2 underflow detection flag */ + uint32_t : 29; + } STMON_b; + }; + + union + { + __IOM uint32_t PANEL_CLK; /*!< (@ 0x00000010) System control block Version and Panel Clock + * Control Register */ + + struct + { + __IOM uint32_t DCDR : 6; /*!< [5..0] Clock division ratio setting control Refer toTable 2.7.1 + * for details about setting value. Note: Settings that are + * not listed in table 2.7.1 are prohibited. */ + __IOM uint32_t CLKEN : 1; /*!< [6..6] Panel clock output enable control Note: Before changing + * the PIXSEL,CLKSEL or DCDR bit, this bit must be set to + * 0. */ + uint32_t : 1; + __IOM uint32_t CLKSEL : 1; /*!< [8..8] Panel clock supply source select */ + uint32_t : 3; + __IOM uint32_t PIXSEL : 1; /*!< [12..12] Pixel clock select control. Must be set to the same + * value as OUT_SET.FRQSEL[1]. */ + uint32_t : 3; + __IM uint32_t VER : 16; /*!< [31..16] Version information Version information of the GLCDC */ + } PANEL_CLK_b; + }; +} R_GLCDC_SYSCNT_Type; /*!< Size = 20 (0x14) */ + +/** + * @brief R_GPT_ODC_GTDLYR [GTDLYR] (PWM DELAY RISING) + */ +typedef struct +{ + union + { + __IOM uint16_t A; /*!< (@ 0x00000000) GTIOCA Output Delay Register */ + + struct + { + __IOM uint16_t DLY : 7; /*!< [6..0] GTIOCnA Output Rising Edge Delay Setting */ + uint16_t : 9; + } A_b; + }; + + union + { + __IOM uint16_t B; /*!< (@ 0x00000002) GTIOCB Output Delay Register */ + + struct + { + __IOM uint16_t DLY : 7; /*!< [6..0] GTIOCnB Output Rising Edge Delay Setting */ + uint16_t : 9; + } B_b; + }; +} R_GPT_ODC_GTDLYR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + + struct + { + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control) + */ +typedef struct +{ + union + { + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ + __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ + __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ + __IOM uint16_t PP : 1; /*!< [3..3] Privilege protection */ + uint16_t : 12; + } AC_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + + struct + { + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ + } S_b; + }; + + union + { + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + + struct + { + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ + } E_b; + }; + __IM uint32_t RESERVED1; +} R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t EN; /*!< (@ 0x00000000) MMPU enable register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } EN_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t ENPT; /*!< (@ 0x00000004) MMPU enable protect register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } ENPT_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t RPT; /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t RPT_SEC; /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only) */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_SEC_b; + }; + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4[60]; + __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control */ + __IM uint32_t RESERVED5[32]; +} R_MPU_MMPU_GROUP_Type; /*!< Size = 512 (0x200) */ + +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; + }; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + uint32_t : 1; + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Event on Rising. */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + uint16_t : 1; + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Event on Rising. */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + uint8_t : 1; + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ + __IM uint16_t RESERVED; +} R_PMISC_PMSAR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ + union + { + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + + struct + { + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 1; + __IOM uint8_t TCEN : 1; /*!< [7..7] Time Capture Event Input Pin Enable */ + } RTCCR_b; + }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; + + union + { + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union + { + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union + { + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ + + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union + { + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3[3]; + + union + { + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ + + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union + { + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + + struct + { + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; + }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) PIPE Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter ClearSetting this bit to 1 allows + * clearing the transaction counter to 0. */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter EnableEnables or disables the transaction + * counter function. */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) PIPE Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction CounterWhen writing to: Specify the number + * of total packets (number of transactions) to be received + * by the relevant PIPE.When read from: When TRENB = 0: Indicate + * the specified number of transactions.When TRENB = 1: Indicate + * the number of currently counted transactions. */ + } N_b; + }; +} R_USB_HS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_XSPI0_CMCFGCS [CMCFGCS] (xSPI Command Map Configuration registers) + */ +typedef struct +{ + union + { + __IOM uint32_t CMCFG0; /*!< (@ 0x00000000) xSPI Command Map Configuration register 0 */ + + struct + { + __IOM uint32_t FFMT : 2; /*!< [1..0] Frame format */ + __IOM uint32_t ADDSIZE : 2; /*!< [3..2] Address size */ + __IOM uint32_t WPBSTMD : 1; /*!< [4..4] Wrapping burst mode */ + __IOM uint32_t ARYAMD : 1; /*!< [5..5] Array address mode */ + uint32_t : 10; + __IOM uint32_t ADDRPEN : 8; /*!< [23..16] Address Replace Enable */ + __IOM uint32_t ADDRPCD : 8; /*!< [31..24] Address Replace Code */ + } CMCFG0_b; + }; + + union + { + __IOM uint32_t CMCFG1; /*!< (@ 0x00000004) xSPI Command Map Configuration register 1 */ + + struct + { + __IOM uint32_t RDCMD : 16; /*!< [15..0] Read command */ + __IOM uint32_t RDLATE : 5; /*!< [20..16] Read latency cycle */ + uint32_t : 11; + } CMCFG1_b; + }; + + union + { + __IOM uint32_t CMCFG2; /*!< (@ 0x00000008) xSPI Command Map Configuration register 2 */ + + struct + { + __IOM uint32_t WRCMD : 16; /*!< [15..0] Write command */ + __IOM uint32_t WRLATE : 5; /*!< [20..16] Write latency cycle */ + uint32_t : 11; + } CMCFG2_b; + }; + __IM uint32_t RESERVED; +} R_XSPI0_CMCFGCS_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_XSPI0_CDBUF [CDBUF] (xSPI BUF register) + */ +typedef struct +{ + union + { + __IOM uint32_t CDT; /*!< (@ 0x00000000) xSPI Command Manual Type buf */ + + struct + { + __IOM uint32_t CMDSIZE : 2; /*!< [1..0] Command Size */ + __IOM uint32_t ADDSIZE : 3; /*!< [4..2] Address size */ + __IOM uint32_t DATASIZE : 4; /*!< [8..5] Write/Read Data Size */ + __IOM uint32_t LATE : 5; /*!< [13..9] Latency cycle */ + uint32_t : 1; + __IOM uint32_t TRTYPE : 1; /*!< [15..15] Transaction Type */ + __IOM uint32_t CMD : 16; /*!< [31..16] Command (1-2byte) */ + } CDT_b; + }; + + union + { + __IOM uint32_t CDA; /*!< (@ 0x00000004) xSPI Command Manual Address buf */ + + struct + { + __IOM uint32_t ADD : 32; /*!< [31..0] Address */ + } CDA_b; + }; + + union + { + __IOM uint32_t CDD0; /*!< (@ 0x00000008) xSPI Command Manual Data 0 buf */ + + struct + { + __IOM uint32_t DATA : 32; /*!< [31..0] Write/Read Data */ + } CDD0_b; + }; + + union + { + __IOM uint32_t CDD1; /*!< (@ 0x0000000C) xSPI Command Manual Data 1 buf */ + + struct + { + __IOM uint32_t DATA : 32; /*!< [31..0] Write/Read Data */ + } CDD1_b; + }; +} R_XSPI0_CDBUF_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_XSPI0_CCCTLCS [CCCTLCS] (xSPI CS register) + */ +typedef struct +{ + union + { + __IOM uint32_t CCCTL0; /*!< (@ 0x00000000) xSPI Command Calibration Control register 0 */ + + struct + { + __IOM uint32_t CAEN : 1; /*!< [0..0] Automatic Calibration Enable */ + __IOM uint32_t CANOWR : 1; /*!< [1..1] Calibration no write mode */ + uint32_t : 6; + __IOM uint32_t CAITV : 5; /*!< [12..8] Calibration interval */ + uint32_t : 3; + __IOM uint32_t CASFTSTA : 5; /*!< [20..16] Calibration DS shift start value */ + uint32_t : 3; + __IOM uint32_t CASFTEND : 5; /*!< [28..24] Calibration DS shift end value */ + uint32_t : 3; + } CCCTL0_b; + }; + + union + { + __IOM uint32_t CCCTL1; /*!< (@ 0x00000004) xSPI Command Calibration Control register 1 */ + + struct + { + __IOM uint32_t CACMDSIZE : 2; /*!< [1..0] Command Size */ + __IOM uint32_t CAADDSIZE : 3; /*!< [4..2] Address size */ + __IOM uint32_t CADATASIZE : 4; /*!< [8..5] Write/Read Data Size */ + uint32_t : 7; + __IOM uint32_t CAWRLATE : 5; /*!< [20..16] Write Latency cycle */ + uint32_t : 3; + __IOM uint32_t CARDLATE : 5; /*!< [28..24] Read Latency cycle */ + uint32_t : 3; + } CCCTL1_b; + }; + + union + { + __IOM uint32_t CCCTL2; /*!< (@ 0x00000008) xSPI Command Calibration Control register 2 */ + + struct + { + __IOM uint32_t CAWRCMD : 16; /*!< [15..0] Calibration pattern write command */ + __IOM uint32_t CARDCMD : 16; /*!< [31..16] Calibration pattern read command */ + } CCCTL2_b; + }; + + union + { + __IOM uint32_t CCCTL3; /*!< (@ 0x0000000C) xSPI Command Calibration Control register 3 */ + + struct + { + __IOM uint32_t CAADD : 32; /*!< [31..0] Calibration pattern address */ + } CCCTL3_b; + }; + + union + { + __IOM uint32_t CCCTL4; /*!< (@ 0x00000010) xSPI Command Calibration Control register 4 */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL4_b; + }; + + union + { + __IOM uint32_t CCCTL5; /*!< (@ 0x00000014) xSPI Command Calibration Control register 5 */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL5_b; + }; + + union + { + __IOM uint32_t CCCTL6; /*!< (@ 0x00000018) xSPI Command Calibration Control register 6 */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL6_b; + }; + + union + { + __IOM uint32_t CCCTL7; /*!< (@ 0x0000001C) xSPI Command Calibration Control register 7 */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL7_b; + }; +} R_XSPI0_CCCTLCS_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) + */ +typedef struct +{ + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; + }; + + union + { + __IOM uint8_t AGTMR2; /*!< (@ 0x00000002) AGT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; + }; + + union + { + __IOM uint8_t AGTIOSEL_ALT; /*!< (@ 0x00000003) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_ALT_b; + }; + + union + { + __IOM uint8_t AGTIOC; /*!< (@ 0x00000004) AGT I/O Control Register */ + + struct + { + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; + }; + + union + { + __IOM uint8_t AGTISR; /*!< (@ 0x00000005) AGT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; + }; + + union + { + __IOM uint8_t AGTCMSR; /*!< (@ 0x00000006) AGT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; + }; + + union + { + __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000007) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; + }; +} R_AGTX0_AGT16_CTRL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers) + */ +typedef struct +{ + union + { + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + + struct + { + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + + struct + { + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + + struct + { + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IM uint16_t RESERVED; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL */ +} R_AGTX0_AGT16_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers) + */ +typedef struct +{ + union + { + __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT 32-bit Counter Register */ + + struct + { + __IOM uint32_t AGT : 32; /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ + + struct + { + __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ + + struct + { + __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL */ +} R_AGTX0_AGT32_Type; /*!< Size = 20 (0x14) */ + +/** + * @brief R_COMA_CABPPPFLC [CABPPPFLC] ([0..2]) + */ +typedef struct +{ + union + { + __IOM uint32_t LEVEL0; /*!< (@ 0x00000000) Port 0 Buffer Pointer Pause Frame Level 0 Configuration + * Register */ + + struct + { + __IOM uint32_t PPDL : 10; /*!< [9..0] Pause De-Assertion Level */ + uint32_t : 6; + __IOM uint32_t PPAL : 10; /*!< [25..16] Pause Assertion Level */ + uint32_t : 6; + } LEVEL0_b; + }; + + union + { + __IOM uint32_t LEVEL1; /*!< (@ 0x00000004) Port 0 Buffer Pointer Pause Frame Level 1 Configuration + * Register */ + + struct + { + __IOM uint32_t PPDL : 10; /*!< [9..0] Pause De-Assertion Level */ + uint32_t : 6; + __IOM uint32_t PPAL : 10; /*!< [25..16] Pause Assertion Level */ + uint32_t : 6; + } LEVEL1_b; + }; +} R_COMA_CABPPPFLC_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_IPC_IPCNMI [IPCNMI] (Inter-Processor NMI Registers) + */ +typedef struct +{ + union + { + __IM uint32_t STA; /*!< (@ 0x00000000) NMI Request Status Register */ + + struct + { + __IM uint32_t NMI : 1; /*!< [0..0] Status of the interrupt request */ + uint32_t : 31; + } STA_b; + }; + + union + { + __OM uint32_t SET; /*!< (@ 0x00000004) NMI Request Set Register */ + + struct + { + __OM uint32_t SET : 1; /*!< [0..0] Sets the NMI request */ + uint32_t : 31; + } SET_b; + }; + + union + { + __OM uint32_t CLR; /*!< (@ 0x00000008) NMI Request Clear Register */ + + struct + { + __OM uint32_t CLR : 1; /*!< [0..0] Clears the NMI request */ + uint32_t : 31; + } CLR_b; + }; + __IM uint32_t RESERVED; +} R_IPC_IPCNMI_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_IPC_IPC_CH [CH] (Inter-Processor Communications Channel Registers) + */ +typedef struct +{ + union + { + __IM uint32_t STA; /*!< (@ 0x00000000) Inter-Processor Status Register */ + + struct + { + __IM uint32_t IRQ0 : 1; /*!< [0..0] Indicates the status of the interrupt request */ + __IM uint32_t IRQ1 : 1; /*!< [1..1] Indicates the status of the interrupt request */ + __IM uint32_t IRQ2 : 1; /*!< [2..2] Indicates the status of the interrupt request */ + __IM uint32_t IRQ3 : 1; /*!< [3..3] Indicates the status of the interrupt request */ + __IM uint32_t IRQ4 : 1; /*!< [4..4] Indicates the status of the interrupt request */ + __IM uint32_t IRQ5 : 1; /*!< [5..5] Indicates the status of the interrupt request */ + __IM uint32_t IRQ6 : 1; /*!< [6..6] Indicates the status of the interrupt request */ + __IM uint32_t IRQ7 : 1; /*!< [7..7] Indicates the status of the interrupt request */ + uint32_t : 8; + __IM uint32_t RDY : 1; /*!< [16..16] This bit is set when FIFO is not empty */ + __IM uint32_t FULL : 1; /*!< [17..17] FIFO is full */ + uint32_t : 6; + __IM uint32_t RERR : 1; /*!< [24..24] Indicates that the message FIFO 00 tried to read Data + * despite Empty */ + __IM uint32_t FERR : 1; /*!< [25..25] Indicates that the message FIFO 00 tried to send more + * data even though it was full */ + uint32_t : 6; + } STA_b; + }; + + union + { + __OM uint32_t SET; /*!< (@ 0x00000004) Inter-Processor IRQ Request Set Register */ + + struct + { + __OM uint32_t SET0 : 1; /*!< [0..0] Sets IPCmSTA0.IRQn */ + __OM uint32_t SET1 : 1; /*!< [1..1] Sets IPCmSTA0.IRQn */ + __OM uint32_t SET2 : 1; /*!< [2..2] Sets IPCmSTA0.IRQn */ + __OM uint32_t SET3 : 1; /*!< [3..3] Sets IPCmSTA0.IRQn */ + __OM uint32_t SET4 : 1; /*!< [4..4] Sets IPCmSTA0.IRQn */ + __OM uint32_t SET5 : 1; /*!< [5..5] Sets IPCmSTA0.IRQn */ + __OM uint32_t SET6 : 1; /*!< [6..6] Sets IPCmSTA0.IRQn */ + __OM uint32_t SET7 : 1; /*!< [7..7] Sets IPCmSTA0.IRQn */ + uint32_t : 24; + } SET_b; + }; + + union + { + __OM uint32_t TXD; /*!< (@ 0x00000008) Inter-Processor FIFO Transfer Data Register */ + + struct + { + __OM uint32_t TXD : 32; /*!< [31..0] Transfer data */ + } TXD_b; + }; + + union + { + __IM uint32_t RXD; /*!< (@ 0x0000000C) Inter-Processor FIFO Receive Data Register */ + + struct + { + __IM uint32_t RXD : 32; /*!< [31..0] Receive data */ + } RXD_b; + }; + + union + { + __OM uint32_t CLR; /*!< (@ 0x00000010) Inter-Processor Clear Register */ + + struct + { + __OM uint32_t CLR0 : 1; /*!< [0..0] Clears the interrupt request for IPCmSTA0.IRQn */ + __OM uint32_t CLR1 : 1; /*!< [1..1] Clears the interrupt request for IPCmSTA0.IRQn */ + __OM uint32_t CLR2 : 1; /*!< [2..2] Clears the interrupt request for IPCmSTA0.IRQn */ + __OM uint32_t CLR3 : 1; /*!< [3..3] Clears the interrupt request for IPCmSTA0.IRQn */ + __OM uint32_t CLR4 : 1; /*!< [4..4] Clears the interrupt request for IPCmSTA0.IRQn */ + __OM uint32_t CLR5 : 1; /*!< [5..5] Clears the interrupt request for IPCmSTA0.IRQn */ + __OM uint32_t CLR6 : 1; /*!< [6..6] Clears the interrupt request for IPCmSTA0.IRQn */ + __OM uint32_t CLR7 : 1; /*!< [7..7] Clears the interrupt request for IPCmSTA0.IRQn */ + uint32_t : 8; + __OM uint32_t RST : 1; /*!< [16..16] Resets message FIFO */ + uint32_t : 7; + __OM uint32_t RCLR : 1; /*!< [24..24] Resets IPCmSTA0.RERR */ + __OM uint32_t FCLR : 1; /*!< [25..25] Resets IPCmSTA0.FERR */ + uint32_t : 6; + } CLR_b; + }; + __IM uint32_t RESERVED[3]; +} R_IPC_IPC_CH_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_IPC_IPC [IPC] (Inter-Processor Registers) + */ +typedef struct +{ + __IOM R_IPC_IPC_CH_Type CH[2]; /*!< (@ 0x00000000) Inter-Processor Communications Channel Registers */ +} R_IPC_IPC_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PDM_CH [CH] (PDM Channel-Specific Registers) + */ +typedef struct +{ + union + { + __OM uint32_t PDSTRTR; /*!< (@ 0x00000000) Software Start Trigger Register */ + + struct + { + __OM uint32_t STRTRG : 1; /*!< [0..0] Start trigger */ + uint32_t : 31; + } PDSTRTR_b; + }; + + union + { + __OM uint32_t PDSTPTR; /*!< (@ 0x00000004) Software Stop Trigger Register */ + + struct + { + __OM uint32_t STPTRG : 1; /*!< [0..0] Stop trigger */ + uint32_t : 31; + } PDSTPTR_b; + }; + + union + { + __OM uint32_t PDCHGTR; /*!< (@ 0x00000008) Software Change Trigger Register */ + + struct + { + __OM uint32_t CHGTRG : 1; /*!< [0..0] Change trigger */ + uint32_t : 31; + } PDCHGTR_b; + }; + + union + { + __IOM uint32_t PDICR; /*!< (@ 0x0000000C) Interrupt Control Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t ISDE : 1; /*!< [1..1] Sound detection interrupt enable bit */ + __IOM uint32_t IDRE : 1; /*!< [2..2] Data reception interrupt enable bit */ + uint32_t : 13; + __IOM uint32_t IEDE : 1; /*!< [16..16] Error detection interrupt enable bit */ + uint32_t : 15; + } PDICR_b; + }; + + union + { + __IOM uint32_t PDSDCR; /*!< (@ 0x00000010) Status Detection Control Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t SDE : 1; /*!< [1..1] Sound detection enable bit */ + uint32_t : 14; + __IOM uint32_t SCDE : 1; /*!< [16..16] Short circuit detection enable bit */ + __IOM uint32_t OVLDE : 1; /*!< [17..17] Overvoltage lower limit exceeded detection enable bit */ + __IOM uint32_t OVUDE : 1; /*!< [18..18] Overvoltage upper limit exceeded detection enable bit */ + uint32_t : 8; + __IOM uint32_t BFOWDE : 1; /*!< [27..27] Buffer overwriting detection enable bit */ + uint32_t : 4; + } PDSDCR_b; + }; + + union + { + __IM uint32_t PDSR; /*!< (@ 0x00000014) Status Register */ + + struct + { + __IM uint32_t STATE : 1; /*!< [0..0] State */ + __IM uint32_t SDF : 1; /*!< [1..1] Sound detection flag */ + __IM uint32_t DRF : 1; /*!< [2..2] Data reception flag */ + uint32_t : 13; + __IM uint32_t SCDF : 1; /*!< [16..16] Short circuit detection flag */ + __IM uint32_t OVLDF : 1; /*!< [17..17] Overvoltage lower limit exceeded detection flag */ + __IM uint32_t OVUDF : 1; /*!< [18..18] Overvoltage upper limit exceeded detection flag */ + uint32_t : 8; + __IM uint32_t BFOWDF : 1; /*!< [27..27] Buffer overwriting detection flag */ + uint32_t : 4; + } PDSR_b; + }; + + union + { + __OM uint32_t PDSCR; /*!< (@ 0x00000018) Status Clear Register */ + + struct + { + uint32_t : 1; + __OM uint32_t SDFC : 1; /*!< [1..1] Sound detection flag clear */ + uint32_t : 14; + __OM uint32_t SCDFC : 1; /*!< [16..16] Short circuit detection flag clear */ + __OM uint32_t OVLDFC : 1; /*!< [17..17] Overvoltage lower limit exceeded detection flag clear */ + __OM uint32_t OVUDFC : 1; /*!< [18..18] Overvoltage upper limit exceeded detection flag clear */ + uint32_t : 8; + __OM uint32_t BFOWDFC : 1; /*!< [27..27] Buffer overwriting detection flag clear */ + uint32_t : 4; + } PDSCR_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t PDMDSR; /*!< (@ 0x00000020) Mode Setting Register */ + + struct + { + __IOM uint32_t INPSEL : 1; /*!< [0..0] Input data select */ + uint32_t : 3; + __IOM uint32_t SFMD : 3; /*!< [6..4] Sinc filter mode setting */ + uint32_t : 1; + __IOM uint32_t HFIS : 2; /*!< [9..8] High-pass filter input shift setting */ + uint32_t : 2; + __IOM uint32_t CFIS : 2; /*!< [13..12] Compensation filter input shift setting */ + uint32_t : 2; + __IOM uint32_t LFIS : 2; /*!< [17..16] Low-pass (half-band decimation) filter input shift + * setting */ + uint32_t : 6; + __IOM uint32_t SDMAMD : 2; /*!< [25..24] Moving average mode for sound detection data */ + uint32_t : 2; + __IOM uint32_t DBIS : 4; /*!< [31..28] Data buffer input shift setting */ + } PDMDSR_b; + }; + + union + { + __IOM uint32_t PDSFCR; /*!< (@ 0x00000024) Sinc filter Control Register */ + + struct + { + __IOM uint32_t CKDIV : 4; /*!< [3..0] PDM_CLKn's dividend ratio to core clock */ + uint32_t : 12; + __IOM uint32_t SINCDEC : 8; /*!< [23..16] Sinc filter decimation ratio */ + __IOM uint32_t SINCRNG : 5; /*!< [28..24] Sinc filter output valid range */ + uint32_t : 3; + } PDSFCR_b; + }; + + union + { + __IOM uint32_t PDHFCS0R; /*!< (@ 0x00000028) High-pass filter Coefficient s(0) Register */ + + struct + { + __IOM uint32_t HFS0 : 16; /*!< [15..0] High-pass filter coefficient s(0) */ + uint32_t : 16; + } PDHFCS0R_b; + }; + + union + { + __IOM uint32_t PDHFCK1R; /*!< (@ 0x0000002C) High-pass filter Coefficient k(1) Register */ + + struct + { + __IOM uint32_t HFK1 : 16; /*!< [15..0] High-pass filter coefficient k(1) */ + uint32_t : 16; + } PDHFCK1R_b; + }; + + union + { + __IOM uint32_t PDHFCHR[2]; /*!< (@ 0x00000030) High-pass filter Coefficient h([0..1]) Registers */ + + struct + { + __IOM uint32_t HFHn : 16; /*!< [15..0] High-pass filter coefficient h(n) */ + uint32_t : 16; + } PDHFCHR_b[2]; + }; + + union + { + __IOM uint32_t PDCFCHR[11]; /*!< (@ 0x00000038) Compensation filter Coefficient h([0..10]) Registers */ + + struct + { + __IOM uint32_t CFHn : 13; /*!< [12..0] Compensation filter coefficient h(n) */ + uint32_t : 19; + } PDCFCHR_b[11]; + }; + + union + { + __IOM uint32_t PDLFCH010R; /*!< (@ 0x00000064) Low-pass filter Coefficient h0(10) Register */ + + struct + { + __IOM uint32_t LFH010 : 13; /*!< [12..0] Low-pass (half-band decimation) filter coefficient h0(10) */ + uint32_t : 19; + } PDLFCH010R_b; + }; + + union + { + __IOM uint32_t PDLFCH1R[20]; /*!< (@ 0x00000068) Low-pass filter Coefficient h1([0..19]) Registers */ + + struct + { + __IOM uint32_t LFH1n : 13; /*!< [12..0] Low-pass (half-band decimation) filter coefficient h1(n) */ + uint32_t : 19; + } PDLFCH1R_b[20]; + }; + + union + { + __IOM uint32_t PDSDLTR; /*!< (@ 0x000000B8) Sound Detection Lower Threshold Register */ + + struct + { + __IOM uint32_t SDETL : 20; /*!< [19..0] Sound detection lower limit */ + uint32_t : 12; + } PDSDLTR_b; + }; + + union + { + __IOM uint32_t PDSDUTR; /*!< (@ 0x000000BC) Sound Detection Upper Threshold Register */ + + struct + { + __IOM uint32_t SDETU : 20; /*!< [19..0] Sound detection upper limit */ + uint32_t : 12; + } PDSDUTR_b; + }; + + union + { + __IOM uint32_t PDDBCR; /*!< (@ 0x000000C0) Data Buffer Control Register */ + + struct + { + __IOM uint32_t DATRITHR : 3; /*!< [2..0] Data reception interrupt threshold */ + uint32_t : 29; + } PDDBCR_b; + }; + + union + { + __IOM uint32_t PDSCTSR; /*!< (@ 0x000000C4) Short Circuit Threshold Setting Register */ + + struct + { + __IOM uint32_t SCDL : 13; /*!< [12..0] Short circuit detection Low Continuous detection count */ + uint32_t : 3; + __IOM uint32_t SCDH : 13; /*!< [28..16] Short circuit detection High Continuous detection count */ + uint32_t : 3; + } PDSCTSR_b; + }; + + union + { + __IOM uint32_t PDOVLTR; /*!< (@ 0x000000C8) Overvoltage Lower Threshold Register */ + + struct + { + __IOM uint32_t OVDL : 20; /*!< [19..0] Overvoltage detection lower limit */ + uint32_t : 12; + } PDOVLTR_b; + }; + + union + { + __IOM uint32_t PDOVUTR; /*!< (@ 0x000000CC) Overvoltage Upper Threshold Register */ + + struct + { + __IOM uint32_t OVDU : 20; /*!< [19..0] Overvoltage detection upper limit */ + uint32_t : 12; + } PDOVUTR_b; + }; + __IM uint32_t RESERVED1[4]; + + union + { + __IOM uint32_t PDDRCR; /*!< (@ 0x000000E0) Data Read Control Register */ + + struct + { + __IOM uint32_t DATRE : 1; /*!< [0..0] Data read enable bit */ + uint32_t : 31; + } PDDRCR_b; + }; + + union + { + __OM uint32_t PDDCR; /*!< (@ 0x000000E4) Data Clear Register */ + + struct + { + __OM uint32_t DATC : 1; /*!< [0..0] Data clear */ + uint32_t : 31; + } PDDCR_b; + }; + + union + { + __IM uint32_t PDDRR; /*!< (@ 0x000000E8) Data Read Register */ + + struct + { + __IM uint32_t DAT : 20; /*!< [19..0] Data */ + uint32_t : 12; + } PDDRR_b; + }; + + union + { + __IM uint32_t PDDSR; /*!< (@ 0x000000EC) Data Status Register */ + + struct + { + __IM uint32_t DATNUM : 8; /*!< [7..0] Number of data stored in buffer */ + uint32_t : 24; + } PDDSR_b; + }; + __IM uint32_t RESERVED2[4]; +} R_PDM_CH_Type; /*!< Size = 256 (0x100) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief High-Speed Analog Comparator (R_ACMPHS0) + */ + +typedef struct /*!< (@ 0x40236000) R_ACMPHS0 Structure */ +{ + union + { + __IOM uint8_t CMPCTL; /*!< (@ 0x00000000) Comparator Control Register */ + + struct + { + __IOM uint8_t CINV : 1; /*!< [0..0] Comparator output polarity selection */ + __IOM uint8_t COE : 1; /*!< [1..1] Comparator output enable */ + __IOM uint8_t CSTEN : 1; /*!< [2..2] Interrupt Select */ + __IOM uint8_t CEG : 2; /*!< [4..3] Selection of valid edge (Edge selector) */ + __IOM uint8_t CDFS : 2; /*!< [6..5] Noise filter selection */ + __IOM uint8_t HCMPON : 1; /*!< [7..7] Comparator operation control */ + } CMPCTL_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t CMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ + + struct + { + __IOM uint8_t CMPSEL : 4; /*!< [3..0] Comparator Input Selection */ + uint8_t : 4; + } CMPSEL0_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t CMPSEL1; /*!< (@ 0x00000008) Comparator Reference Voltage Select Register */ + + struct + { + __IOM uint8_t CRVS : 6; /*!< [5..0] Reference Voltage Selection */ + uint8_t : 2; + } CMPSEL1_b; + }; + __IM uint8_t RESERVED2[3]; + + union + { + __IM uint8_t CMPMON; /*!< (@ 0x0000000C) Comparator Output Monitor Register */ + + struct + { + __IM uint8_t CMPMON : 1; /*!< [0..0] Comparator output monitor */ + uint8_t : 7; + } CMPMON_b; + }; + __IM uint8_t RESERVED3[3]; + + union + { + __IOM uint8_t CPIOC; /*!< (@ 0x00000010) Comparator Output Control Register */ + + struct + { + __IOM uint8_t CPOE : 1; /*!< [0..0] Comparator output selection */ + uint8_t : 6; + __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ + } CPIOC_b; + }; + __IM uint8_t RESERVED4[47]; + + union + { + __IOM uint8_t CPINTCTL; /*!< (@ 0x00000040) Comparator Interrupt Control Register */ + + struct + { + __IOM uint8_t MSKE : 1; /*!< [0..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 7; + } CPINTCTL_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t CPMSKCTL; /*!< (@ 0x00000044) Comparator Interrupt Mask Control Register */ + + struct + { + __IOM uint8_t MSKSEL : 3; /*!< [2..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 5; + } CPMSKCTL_b; + }; +} R_ACMPHS0_Type; /*!< Size = 69 (0x45) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Peripheral Security Control Unit (R_PSCU) + */ + +typedef struct /*!< (@ 0x40204000) R_PSCU Structure */ +{ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + + struct + { + __IOM uint32_t PSARB0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARB1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARB2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARB3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARB4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARB5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARB6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARB7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARB8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARB9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARB10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARB11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARB12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARB13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARB14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARB15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARB16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARB17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARB18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARB19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARB20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARB21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARB22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARB23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARB24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARB25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARB26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARB27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARB28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARB29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARB30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARB31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ + } PSARB_b; + }; + + union + { + __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ + + struct + { + __IOM uint32_t PSARC0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARC1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARC2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARC3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARC4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARC5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARC6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARC7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARC8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARC9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARC10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARC11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARC12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARC13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARC14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARC15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARC16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARC17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARC18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARC19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARC20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARC21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARC22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARC23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARC24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARC25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARC26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARC27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARC28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARC29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARC30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARC31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ + } PSARC_b; + }; + + union + { + __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ + + struct + { + __IOM uint32_t PSARD0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARD1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARD2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARD3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARD4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARD5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARD6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARD7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARD8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARD9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARD10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARD11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARD12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARD13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARD14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARD15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARD16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARD17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARD18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARD19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARD20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARD21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARD22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARD23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARD24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARD25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARD26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARD27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARD28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARD29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARD30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARD31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ + } PSARD_b; + }; + + union + { + __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ + + struct + { + __IOM uint32_t PSARE0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARE1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARE2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARE3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARE4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARE5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARE6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARE7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARE8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARE9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARE10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARE11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARE12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARE13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARE14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARE15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARE16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARE17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARE18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARE19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARE20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARE21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARE22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARE23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARE24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARE25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARE26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARE27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARE28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARE29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARE30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARE31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ + } PSARE_b; + }; + + union + { + __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ + + struct + { + __IOM uint32_t MSSAR0 : 1; /*!< [0..0] Module stop security attribution bit 0 */ + __IOM uint32_t MSSAR1 : 1; /*!< [1..1] Module stop security attribution bit 1 */ + __IOM uint32_t MSSAR2 : 1; /*!< [2..2] Module stop security attribution bit 2 */ + __IOM uint32_t MSSAR3 : 1; /*!< [3..3] Module stop security attribution bit 3 */ + __IOM uint32_t MSSAR4 : 1; /*!< [4..4] Module stop security attribution bit 4 */ + __IOM uint32_t MSSAR5 : 1; /*!< [5..5] Module stop security attribution bit 5 */ + __IOM uint32_t MSSAR6 : 1; /*!< [6..6] Module stop security attribution bit 6 */ + __IOM uint32_t MSSAR7 : 1; /*!< [7..7] Module stop security attribution bit 7 */ + __IOM uint32_t MSSAR8 : 1; /*!< [8..8] Module stop security attribution bit 8 */ + __IOM uint32_t MSSAR9 : 1; /*!< [9..9] Module stop security attribution bit 9 */ + __IOM uint32_t MSSAR10 : 1; /*!< [10..10] Module stop security attribution bit 10 */ + __IOM uint32_t MSSAR11 : 1; /*!< [11..11] Module stop security attribution bit 11 */ + __IOM uint32_t MSSAR12 : 1; /*!< [12..12] Module stop security attribution bit 12 */ + __IOM uint32_t MSSAR13 : 1; /*!< [13..13] Module stop security attribution bit 13 */ + __IOM uint32_t MSSAR14 : 1; /*!< [14..14] Module stop security attribution bit 14 */ + __IOM uint32_t MSSAR15 : 1; /*!< [15..15] Module stop security attribution bit 15 */ + __IOM uint32_t MSSAR16 : 1; /*!< [16..16] Module stop security attribution bit 16 */ + __IOM uint32_t MSSAR17 : 1; /*!< [17..17] Module stop security attribution bit 17 */ + __IOM uint32_t MSSAR18 : 1; /*!< [18..18] Module stop security attribution bit 18 */ + __IOM uint32_t MSSAR19 : 1; /*!< [19..19] Module stop security attribution bit 19 */ + __IOM uint32_t MSSAR20 : 1; /*!< [20..20] Module stop security attribution bit 20 */ + __IOM uint32_t MSSAR21 : 1; /*!< [21..21] Module stop security attribution bit 21 */ + __IOM uint32_t MSSAR22 : 1; /*!< [22..22] Module stop security attribution bit 22 */ + __IOM uint32_t MSSAR23 : 1; /*!< [23..23] Module stop security attribution bit 23 */ + __IOM uint32_t MSSAR24 : 1; /*!< [24..24] Module stop security attribution bit 24 */ + __IOM uint32_t MSSAR25 : 1; /*!< [25..25] Module stop security attribution bit 25 */ + __IOM uint32_t MSSAR26 : 1; /*!< [26..26] Module stop security attribution bit 26 */ + __IOM uint32_t MSSAR27 : 1; /*!< [27..27] Module stop security attribution bit 27 */ + __IOM uint32_t MSSAR28 : 1; /*!< [28..28] Module stop security attribution bit 28 */ + __IOM uint32_t MSSAR29 : 1; /*!< [29..29] Module stop security attribution bit 29 */ + __IOM uint32_t MSSAR30 : 1; /*!< [30..30] Module stop security attribution bit 30 */ + __IOM uint32_t MSSAR31 : 1; /*!< [31..31] Module stop security attribution bit 31 */ + } MSSAR_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t PPARB; /*!< (@ 0x0000001C) Peripheral Privilege Attribution Register B */ + + struct + { + __IOM uint32_t PPARB0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARB1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARB2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARB3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARB4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARB5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARB6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARB7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARB8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARB9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARB10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARB11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARB12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARB13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARB14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARB15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARB16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARB17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARB18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARB19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARB20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARB21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARB22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARB23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARB24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARB25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARB26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARB27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARB28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARB29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARB30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARB31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ + } PPARB_b; + }; + + union + { + __IOM uint32_t PPARC; /*!< (@ 0x00000020) Peripheral Privilege Attribution Register C */ + + struct + { + __IOM uint32_t PPARC0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARC1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARC2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARC3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARC4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARC5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARC6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARC7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARC8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARC9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARC10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARC11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARC12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARC13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARC14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARC15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARC16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARC17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARC18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARC19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARC20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARC21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARC22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARC23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARC24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARC25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARC26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARC27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARC28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARC29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARC30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARC31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ + } PPARC_b; + }; + + union + { + __IOM uint32_t PPARD; /*!< (@ 0x00000024) Peripheral Privilege Attribution Register D */ + + struct + { + __IOM uint32_t PPARD0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARD1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARD2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARD3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARD4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARD5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARD6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARD7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARD8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARD9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARD10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARD11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARD12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARD13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARD14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARD15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARD16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARD17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARD18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARD19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARD20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARD21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARD22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARD23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARD24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARD25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARD26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARD27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARD28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARD29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARD30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARD31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ + } PPARD_b; + }; + + union + { + __IOM uint32_t PPARE; /*!< (@ 0x00000028) Peripheral Privilege Attribution Register E */ + + struct + { + __IOM uint32_t PPARE0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARE1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARE2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARE3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARE4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARE5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARE6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARE7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARE8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARE9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARE10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARE11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARE12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARE13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARE14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARE15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARE16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARE17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARE18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARE19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARE20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARE21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARE22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARE23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARE24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARE25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARE26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARE27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARE28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARE29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARE30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARE31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ + } PPARE_b; + }; + + union + { + __IOM uint32_t MSPAR; /*!< (@ 0x0000002C) Module Stop Privilege Attribution Register */ + + struct + { + __IOM uint32_t MSPAR0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t MSPAR1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t MSPAR2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t MSPAR3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t MSPAR4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t MSPAR5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t MSPAR6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t MSPAR7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t MSPAR8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t MSPAR9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t MSPAR10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t MSPAR11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t MSPAR12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t MSPAR13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t MSPAR14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t MSPAR15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t MSPAR16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t MSPAR17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t MSPAR18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t MSPAR19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t MSPAR20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t MSPAR21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t MSPAR22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t MSPAR23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t MSPAR24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t MSPAR25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t MSPAR26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t MSPAR27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t MSPAR28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t MSPAR29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t MSPAR30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t MSPAR31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ + } MSPAR_b; + }; + + union + { + __IM uint32_t CFSAMONA; /*!< (@ 0x00000030) Code MRAM Security Attribution Monitor Register */ + + struct + { + uint32_t : 15; + __IM uint32_t CFS2 : 9; /*!< [23..15] Code Secure area */ + uint32_t : 8; + } CFSAMONA_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IM uint32_t DLMMON; /*!< (@ 0x00000038) Device Lifecycle Management State Monitor Register */ + + struct + { + __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ + uint32_t : 28; + } DLMMON_b; + }; + + union + { + __IM uint32_t SFSAMON; /*!< (@ 0x0000003C) SiP Flash Security Attribution Monitor Register */ + + struct + { + uint32_t : 15; + __IM uint32_t SFS : 9; /*!< [23..15] SiP Flash Secure Area */ + uint32_t : 8; + } SFSAMON_b; + }; +} R_PSCU_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + + union + { + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ + }; + __IM uint32_t RESERVED4[58]; + + union + { + union + { + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + }; + __IM uint32_t RESERVED5[46]; + + union + { + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ + }; + __IM uint32_t RESERVED6[27]; + + union + { + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ + + struct + { + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; + }; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED10[16]; + + union + { + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ + }; + __IM uint32_t RESERVED11[28]; + + union + { + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ + }; + __IM uint32_t RESERVED12[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6924 (0x1b0c) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40202400) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; + }; + + union + { + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + + struct + { + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; + }; + + union + { + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + + struct + { + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; + }; + + union + { + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + + struct + { + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; + }; + + union + { + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + + struct + { + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; + }; + + union + { + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; + }; + + union + { + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + + struct + { + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; + }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CANFD0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD0) + */ + +typedef struct /*!< (@ 0x40380000) R_CANFD0 Structure */ +{ + __IOM R_CANFD_CFDC_Type CFDC[1]; /*!< (@ 0x00000000) Channel Control/Status */ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CFDGCFG; /*!< (@ 0x00000014) Global Configuration Register */ + + struct + { + __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */ + __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */ + __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */ + __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */ + __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */ + __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD message Payload overflow configuration */ + uint32_t : 2; + __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */ + __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */ + uint32_t : 3; + __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */ + } CFDGCFG_b; + }; + + union + { + __IOM uint32_t CFDGCTR; /*!< (@ 0x00000018) Global Control Register */ + + struct + { + __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */ + __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */ + uint32_t : 5; + __IOM uint32_t DEIE : 1; /*!< [8..8] DLC check Interrupt Enable */ + __IOM uint32_t MEIE : 1; /*!< [9..9] Message lost Error Interrupt Enable */ + __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */ + __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable */ + uint32_t : 4; + __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */ + uint32_t : 15; + } CFDGCTR_b; + }; + + union + { + __IOM uint32_t CFDGSTS; /*!< (@ 0x0000001C) Global Status Register */ + + struct + { + __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */ + __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */ + __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */ + __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation */ + uint32_t : 28; + } CFDGSTS_b; + }; + + union + { + __IOM uint32_t CFDGERFL; /*!< (@ 0x00000020) Global Error Flag Register */ + + struct + { + __IOM uint32_t DEF : 1; /*!< [0..0] DLC Error Flag */ + __IM uint32_t MES : 1; /*!< [1..1] Message Lost Error Status */ + __IM uint32_t THLES : 1; /*!< [2..2] TX History List Entry Lost Error Status */ + __IOM uint32_t CMPOF : 1; /*!< [3..3] CAN-FD message payload overflow Flag */ + uint32_t : 12; + __IOM uint32_t EEF0 : 1; /*!< [16..16] ECC Error Flag for Channel 0 */ + uint32_t : 15; + } CFDGERFL_b; + }; + + union + { + __IOM uint32_t CFDGTSC; /*!< (@ 0x00000024) Global Timestamp Counter Register */ + + struct + { + __IM uint32_t TS : 16; /*!< [15..0] Timestamp Value */ + uint32_t : 16; + } CFDGTSC_b; + }; + + union + { + __IOM uint32_t CFDGAFLECTR; /*!< (@ 0x00000028) Global Acceptance Filter List Entry Control Register */ + + struct + { + __IOM uint32_t AFLPN : 4; /*!< [3..0] Acceptance Filter List Page Number */ + uint32_t : 4; + __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable */ + uint32_t : 23; + } CFDGAFLECTR_b; + }; + + union + { + __IOM uint32_t CFDGAFLCFG0; /*!< (@ 0x0000002C) Global Acceptance Filter List Configuration Register + * 0 */ + + struct + { + __IOM uint32_t RNC1 : 9; /*!< [8..0] Rule Number for Channel 1 */ + uint32_t : 7; + __IOM uint32_t RNC0 : 9; /*!< [24..16] Rule Number for Channel 0 */ + uint32_t : 7; + } CFDGAFLCFG0_b; + }; + + union + { + __IOM uint32_t CFDRMNB; /*!< (@ 0x00000030) RX Message Buffer Number Register */ + + struct + { + __IOM uint32_t NRXMB : 8; /*!< [7..0] Number of RX Message Buffers */ + __IOM uint32_t RMPLS : 3; /*!< [10..8] Reception Message Buffer Payload Data Size */ + uint32_t : 21; + } CFDRMNB_b; + }; + + union + { + __IOM uint32_t CFDRMND0; /*!< (@ 0x00000034) RX Message Buffer New Data Register 0 */ + + struct + { + __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status */ + } CFDRMND0_b; + }; + + union + { + __IOM uint32_t CFDRMIEC; /*!< (@ 0x00000038) RX Message Buffer Interrupt Enable Configuration + * Register */ + + struct + { + __IOM uint32_t RMIE : 32; /*!< [31..0] RX Message Buffer Interrupt Enable */ + } CFDRMIEC_b; + }; + + union + { + __IOM uint32_t CFDRFCC[2]; /*!< (@ 0x0000003C) RX FIFO Configuration / Control Registers */ + + struct + { + __IOM uint32_t RFE : 1; /*!< [0..0] RX FIFO Enable */ + __IOM uint32_t RFIE : 1; /*!< [1..1] RX FIFO Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t RFPLS : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration */ + uint32_t : 1; + __IOM uint32_t RFDC : 3; /*!< [10..8] RX FIFO Depth Configuration */ + uint32_t : 1; + __IOM uint32_t RFIM : 1; /*!< [12..12] RX FIFO Interrupt Mode */ + __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value */ + uint32_t : 16; + } CFDRFCC_b[2]; + }; + + union + { + __IOM uint32_t CFDRFSTS[2]; /*!< (@ 0x00000044) RX FIFO Status Registers */ + + struct + { + __IM uint32_t RFEMP : 1; /*!< [0..0] RX FIFO Empty */ + __IM uint32_t RFFLL : 1; /*!< [1..1] RX FIFO Full */ + __IOM uint32_t RFMLT : 1; /*!< [2..2] RX FIFO Message Lost */ + __IOM uint32_t RFIF : 1; /*!< [3..3] RX FIFO Interrupt Flag */ + uint32_t : 4; + __IM uint32_t RFMC : 8; /*!< [15..8] RX FIFO Message Count */ + uint32_t : 16; + } CFDRFSTS_b[2]; + }; + + union + { + __IOM uint32_t CFDRFPCTR[2]; /*!< (@ 0x0000004C) RX FIFO Pointer Control Registers */ + + struct + { + __OM uint32_t RFPC : 8; /*!< [7..0] RX FIFO Pointer Control */ + uint32_t : 24; + } CFDRFPCTR_b[2]; + }; + + union + { + __IOM uint32_t CFDCFCC[1]; /*!< (@ 0x00000054) Common FIFO Configuration / Control Registers */ + + struct + { + __IOM uint32_t CFE : 1; /*!< [0..0] Common FIFO Enable */ + __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable */ + __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CFPLS : 3; /*!< [6..4] Common FIFO Payload Data size configuration */ + uint32_t : 1; + __IOM uint32_t CFM : 2; /*!< [9..8] Common FIFO Mode */ + __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select */ + __IOM uint32_t CFITR : 1; /*!< [11..11] Common FIFO Interval Timer Resolution */ + __IOM uint32_t CFIM : 1; /*!< [12..12] Common FIFO Interrupt Mode */ + __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value */ + __IOM uint32_t CFTML : 5; /*!< [20..16] Common FIFO TX Message Buffer Link */ + __IOM uint32_t CFDC : 3; /*!< [23..21] Common FIFO Depth Configuration */ + __IOM uint32_t CFITT : 8; /*!< [31..24] Common FIFO Interval Transmission Time */ + } CFDCFCC_b[1]; + }; + + union + { + __IOM uint32_t CFDCFSTS[1]; /*!< (@ 0x00000058) Common FIFO Status Registers */ + + struct + { + __IM uint32_t CFEMP : 1; /*!< [0..0] Common FIFO Empty */ + __IM uint32_t CFFLL : 1; /*!< [1..1] Common FIFO Full */ + __IOM uint32_t CFMLT : 1; /*!< [2..2] Common FIFO Message Lost */ + __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag */ + __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag */ + uint32_t : 3; + __IM uint32_t CFMC : 8; /*!< [15..8] Common FIFO Message Count */ + uint32_t : 16; + } CFDCFSTS_b[1]; + }; + + union + { + __IOM uint32_t CFDCFPCTR[1]; /*!< (@ 0x0000005C) Common FIFO Pointer Control Registers */ + + struct + { + __OM uint32_t CFPC : 8; /*!< [7..0] Common FIFO Pointer Control */ + uint32_t : 24; + } CFDCFPCTR_b[1]; + }; + + union + { + __IM uint32_t CFDFESTS; /*!< (@ 0x00000060) FIFO Empty Status Register */ + + struct + { + __IM uint32_t RFXEMP : 2; /*!< [1..0] RX FIF0 Empty Status */ + uint32_t : 6; + __IM uint32_t CFXEMP : 1; /*!< [8..8] Common FIF0 Empty Status */ + uint32_t : 23; + } CFDFESTS_b; + }; + + union + { + __IM uint32_t CFDFFSTS; /*!< (@ 0x00000064) FIFO Full Status Register */ + + struct + { + __IM uint32_t RFXFLL : 2; /*!< [1..0] RX FIF0 Full Status */ + uint32_t : 6; + __IM uint32_t CFXFLL : 1; /*!< [8..8] Common FIF0 Full Status */ + uint32_t : 23; + } CFDFFSTS_b; + }; + + union + { + __IM uint32_t CFDFMSTS; /*!< (@ 0x00000068) FIFO Message Lost Status Register */ + + struct + { + __IM uint32_t RFXMLT : 2; /*!< [1..0] RX FIFO Msg Lost Status */ + uint32_t : 6; + __IM uint32_t CFXMLT : 1; /*!< [8..8] Common FIFO Msg Lost Status */ + uint32_t : 23; + } CFDFMSTS_b; + }; + + union + { + __IOM uint32_t CFDRFISTS; /*!< (@ 0x0000006C) RX FIFO Interrupt Flag Status Register */ + + struct + { + __IM uint32_t RFXIF : 2; /*!< [1..0] RX FIFO[x] Interrupt Flag Status */ + uint32_t : 30; + } CFDRFISTS_b; + }; + + union + { + __IOM uint8_t CFDTMC[4]; /*!< (@ 0x00000070) TX Message Buffer Control Registers */ + + struct + { + __IOM uint8_t TMTR : 1; /*!< [0..0] TX Message Buffer Transmission Request */ + __IOM uint8_t TMTAR : 1; /*!< [1..1] TX Message Buffer Transmission abort Request */ + __IOM uint8_t TMOM : 1; /*!< [2..2] TX Message Buffer One-shot Mode */ + uint8_t : 5; + } CFDTMC_b[4]; + }; + + union + { + __IOM uint8_t CFDTMSTS[4]; /*!< (@ 0x00000074) TX Message Buffer Status Registers */ + + struct + { + __IM uint8_t TMTSTS : 1; /*!< [0..0] TX Message Buffer Transmission Status */ + __IOM uint8_t TMTRF : 2; /*!< [2..1] TX Message Buffer Transmission Result Flag */ + __IM uint8_t TMTRM : 1; /*!< [3..3] TX Message Buffer Transmission Request Mirrored */ + __IM uint8_t TMTARM : 1; /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored */ + uint8_t : 3; + } CFDTMSTS_b[4]; + }; + + union + { + __IM uint32_t CFDTMTRSTS[1]; /*!< (@ 0x00000078) TX Message Buffer Transmission Request Status + * Register */ + + struct + { + __IM uint32_t CFDTMTRSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Request Status */ + uint32_t : 28; + } CFDTMTRSTS_b[1]; + }; + + union + { + __IM uint32_t CFDTMTARSTS[1]; /*!< (@ 0x0000007C) TX Message Buffer Transmission Abort Request + * Status Register */ + + struct + { + __IM uint32_t CFDTMTARSTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Request Status */ + uint32_t : 28; + } CFDTMTARSTS_b[1]; + }; + + union + { + __IM uint32_t CFDTMTCSTS[1]; /*!< (@ 0x00000080) TX Message Buffer Transmission Completion Status + * Register */ + + struct + { + __IM uint32_t CFDTMTCSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Completion Status */ + uint32_t : 28; + } CFDTMTCSTS_b[1]; + }; + + union + { + __IM uint32_t CFDTMTASTS[1]; /*!< (@ 0x00000084) TX Message Buffer Transmission Abort Status Register */ + + struct + { + __IM uint32_t CFDTMTASTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Status */ + uint32_t : 28; + } CFDTMTASTS_b[1]; + }; + + union + { + __IOM uint32_t CFDTMIEC[1]; /*!< (@ 0x00000088) TX Message Buffer Interrupt Enable Configuration + * Register */ + + struct + { + __IOM uint32_t TMIEg : 4; /*!< [3..0] TX Message Buffer Interrupt Enable */ + uint32_t : 28; + } CFDTMIEC_b[1]; + }; + + union + { + __IOM uint32_t CFDTXQCC0[1]; /*!< (@ 0x0000008C) TX Queue Configuration / Control Registers 0 */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + uint32_t : 4; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 2; /*!< [9..8] TX Queue Depth Configuration */ + uint32_t : 22; + } CFDTXQCC0_b[1]; + }; + + union + { + __IOM uint32_t CFDTXQSTS0[1]; /*!< (@ 0x00000090) TX Queue Status Registers 0 */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 18; + } CFDTXQSTS0_b[1]; + }; + + union + { + __IOM uint32_t CFDTXQPCTR0[1]; /*!< (@ 0x00000094) TX Queue Pointer Control Registers 0 */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR0_b[1]; + }; + + union + { + __IOM uint32_t CFDTHLCC[1]; /*!< (@ 0x00000098) TX History List Configuration / Control Register */ + + struct + { + __IOM uint32_t THLE : 1; /*!< [0..0] TX History List Enable */ + uint32_t : 7; + __IOM uint32_t THLIE : 1; /*!< [8..8] TX History List Interrupt Enable */ + __IOM uint32_t THLIM : 1; /*!< [9..9] TX History List Interrupt Mode */ + __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable */ + uint32_t : 21; + } CFDTHLCC_b[1]; + }; + + union + { + __IOM uint32_t CFDTHLSTS[1]; /*!< (@ 0x0000009C) TX History List Status Register */ + + struct + { + __IM uint32_t THLEMP : 1; /*!< [0..0] TX History List Empty */ + __IM uint32_t THLFLL : 1; /*!< [1..1] TX History List Full */ + __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost */ + __IOM uint32_t THLIF : 1; /*!< [3..3] TX History List Interrupt Flag */ + uint32_t : 4; + __IM uint32_t THLMC : 6; /*!< [13..8] TX History List Message Count */ + uint32_t : 18; + } CFDTHLSTS_b[1]; + }; + + union + { + __IOM uint32_t CFDTHLPCTR[1]; /*!< (@ 0x000000A0) TX History List Pointer Control Registers */ + + struct + { + __OM uint32_t THLPC : 8; /*!< [7..0] TX History List Pointer Control */ + uint32_t : 24; + } CFDTHLPCTR_b[1]; + }; + + union + { + __IOM uint32_t CFDGTINTSTS0; /*!< (@ 0x000000A4) Global TX Interrupt Status Register 0 */ + + struct + { + __IM uint32_t TSIF0 : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0 */ + __IM uint32_t TAIF0 : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0 */ + __IM uint32_t TQIF0 : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0 */ + __IM uint32_t CFTIF0 : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0 */ + __IM uint32_t THIF0 : 1; /*!< [4..4] TX History List Interrupt Channel 0 */ + uint32_t : 27; + } CFDGTINTSTS0_b; + }; + + union + { + __IOM uint32_t CFDGTSTCFG; /*!< (@ 0x000000A8) Global Test Configuration Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select */ + uint32_t : 6; + } CFDGTSTCFG_b; + }; + + union + { + __IOM uint32_t CFDGTSTCTR; /*!< (@ 0x000000AC) Global Test Control Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t RTME : 1; /*!< [2..2] RAM Test Mode Enable */ + uint32_t : 29; + } CFDGTSTCTR_b; + }; + + union + { + __IOM uint32_t CFDGFDCFG; /*!< (@ 0x000000B0) Global FD Configuration register */ + + struct + { + __IOM uint32_t RPED : 1; /*!< [0..0] RES bit Protocol exception disable */ + uint32_t : 7; + __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration */ + uint32_t : 22; + } CFDGFDCFG_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t CFDGLOCKK; /*!< (@ 0x000000B8) Global Lock Key Register */ + + struct + { + __OM uint32_t LOCK : 16; /*!< [15..0] Lock Key */ + uint32_t : 16; + } CFDGLOCKK_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFDGAFLIGNENT; /*!< (@ 0x000000C0) Global AFL Ignore Entry Register */ + + struct + { + __IOM uint32_t IRN : 5; /*!< [4..0] Ignore Rule Number */ + uint32_t : 27; + } CFDGAFLIGNENT_b; + }; + + union + { + __IOM uint32_t CFDGAFLIGNCTR; /*!< (@ 0x000000C4) Global AFL Ignore Control Register */ + + struct + { + __IOM uint32_t IREN : 1; /*!< [0..0] Ignore Rule Enable */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key code */ + uint32_t : 16; + } CFDGAFLIGNCTR_b; + }; + + union + { + __IOM uint32_t CFDCDTCT; /*!< (@ 0x000000C8) DMA Transfer Control Register */ + + struct + { + __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0 */ + __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1 */ + uint32_t : 6; + __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0 */ + uint32_t : 23; + } CFDCDTCT_b; + }; + + union + { + __IM uint32_t CFDCDTSTS; /*!< (@ 0x000000CC) DMA Transfer Status Register */ + + struct + { + __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0 */ + __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1 */ + uint32_t : 6; + __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel + * 0 */ + uint32_t : 23; + } CFDCDTSTS_b; + }; + __IM uint32_t RESERVED3[2]; + + union + { + __IOM uint32_t CFDGRSTC; /*!< (@ 0x000000D8) Global SW reset Register */ + + struct + { + __IOM uint32_t SRST : 1; /*!< [0..0] SW reset */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key code */ + uint32_t : 16; + } CFDGRSTC_b; + }; + __IM uint32_t RESERVED4[9]; + __IOM R_CANFD_CFDC2_Type CFDC2[1]; /*!< (@ 0x00000100) Channel Configuration Registers */ + __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00000120) Global Acceptance Filter List Registers */ + __IM uint32_t RESERVED5[24]; + + union + { + __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00000280) RAM Test Page Access Registers */ + + struct + { + __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */ + } CFDRPGACC_b[64]; + }; + __IM uint32_t RESERVED6[104]; + __IOM R_CANFD_CFDRF_Type CFDRF[2]; /*!< (@ 0x00000520) RX FIFO Access Registers */ + __IOM R_CANFD_CFDCF_Type CFDCF[1]; /*!< (@ 0x000005B8) Common FIFO Access Registers */ + __IOM R_CANFD_CFDTM_Type CFDTM[4]; /*!< (@ 0x00000604) TX Message Buffer Access Registers */ + __IM uint32_t RESERVED7[3]; + __IOM R_CANFD_CFDTHL_Type CFDTHL[1]; /*!< (@ 0x00000740) Channel TX History List */ + __IM uint32_t RESERVED8[118]; + __IOM R_CANFD_CFDRM_Type CFDRM[4]; /*!< (@ 0x00000920) RX Message Buffer Access Clusters */ +} R_CANFD_Type; /*!< Size = 6432 (0x1920) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40310000) R_CRC Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + + union + { + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + + struct + { + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union + { + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union + { + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; + }; + + union + { + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + + struct + { + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; + }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC_B0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief 12-bit D/A converter (R_DAC_B0) + */ + +typedef struct /*!< (@ 0x40233000) R_DAC_B0 Structure */ +{ + union + { + __IOM uint16_t DADR; /*!< (@ 0x00000000) D/A Data Register */ + + struct + { + __IOM uint16_t DADR : 16; /*!< [15..0] D/A converted data */ + } DADR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint32_t DACR0; /*!< (@ 0x00000004) D/A Control Register 0 */ + + struct + { + __IOM uint32_t DACEN : 1; /*!< [0..0] DA enable bit */ + uint32_t : 14; + __IOM uint32_t DAE : 1; /*!< [15..15] DA batch conversion control bit */ + uint32_t : 15; + __IOM uint32_t DAOUTDIS : 1; /*!< [31..31] Analog output disable bit */ + } DACR0_b; + }; + + union + { + __IOM uint32_t DACR1; /*!< (@ 0x00000008) D/A Control Register 1 */ + + struct + { + uint32_t : 16; + __IOM uint32_t DPSEL : 1; /*!< [16..16] Data placement selection bit */ + uint32_t : 15; + } DACR1_b; + }; + + union + { + __IOM uint32_t DACR2; /*!< (@ 0x0000000C) D/A Control Register 2 */ + + struct + { + uint32_t : 8; + __IOM uint32_t OFSSEL : 1; /*!< [8..8] DAC-HM operating voltage mode select bit */ + uint32_t : 23; + } DACR2_b; + }; +} R_DAC_B0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ + +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ + union + { + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + + struct + { + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + + struct + { + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT1 : 1; /*!< [2..2] Mask bit for WDT1 reset/interrupt in the OCD run mode */ + uint32_t : 11; + __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ + __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + __IOM uint32_t DBGSTOP_NVMERR : 1; /*!< [26..26] Mask bit for MRAM ECC error reset/interrupt */ + uint32_t : 1; + __IOM uint32_t DBGSTOP_CTERR0 : 1; /*!< [28..28] Mask bit for CPU0's Cache/TCM ECC error reset */ + __IOM uint32_t DBGSTOP_CTERR1 : 1; /*!< [29..29] This bit is reserved. It can be R/W but no effect */ + uint32_t : 1; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t DBGAUTH0; /*!< (@ 0x00000020) Debug Authentication Control Register0 */ + + struct + { + __IOM uint32_t DBGEN0 : 1; /*!< [0..0] CPU0 invasive debug enable */ + __IOM uint32_t DBGEN1 : 1; /*!< [1..1] CPU1 invasive debug enable */ + uint32_t : 2; + __IOM uint32_t NIDEN0 : 1; /*!< [4..4] CPU0 non-invasive debug enable */ + __IOM uint32_t NIDEN1 : 1; /*!< [5..5] CPU1 non-invasive debug enable */ + uint32_t : 10; + __IOM uint32_t DEVICEEN : 1; /*!< [16..16] APB-AP (AP1) authentication */ + uint32_t : 14; + __IM uint32_t SWDBG : 1; /*!< [31..31] Software control of debug function */ + } DBGAUTH0_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t TRPORTCR; /*!< (@ 0x00000030) Trace Port Control Register */ + + struct + { + __IOM uint32_t OE : 1; /*!< [0..0] Data Out Enable bit indicates whether Trace Clock, Trace + * Data and SWO outputs are enabled or not. */ + uint32_t : 1; + __IOM uint32_t DRV : 2; /*!< [3..2] Port Drive Capability Control indicate trace port buffer + * speed */ + uint32_t : 4; + __IOM uint32_t PORTSEL : 2; /*!< [9..8] None */ + uint32_t : 6; + __IOM uint32_t SWOSEL : 1; /*!< [16..16] Select SWO between CPU0 and CPU1 */ + uint32_t : 15; + } TRPORTCR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t TRPORTSZ; /*!< (@ 0x00000038) Trace Port Size Control Register */ + + struct + { + __IOM uint32_t PORTSIZE : 32; /*!< [31..0] Indicates how many pins of TRACEDATA are available. */ + } TRPORTSZ_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t CACHEDBGCR; /*!< (@ 0x00000040) Cache Debug Control Register */ + + struct + { + __IOM uint32_t L1RSTDIS : 1; /*!< [0..0] Disable L1 cache automatic invalidation of CPU0 */ + uint32_t : 31; + } CACHEDBGCR_b; + }; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint32_t DBGNVMCR; /*!< (@ 0x00000050) Debug Non-volatile Memory Control Register */ + + struct + { + __IOM uint32_t NVMWE : 1; /*!< [0..0] Non-volatile memory write enable */ + uint32_t : 31; + } DBGNVMCR_b; + }; + __IM uint32_t RESERVED6[43]; + + union + { + __IOM uint32_t ALCTRL; /*!< (@ 0x00000100) Authentication Level Control Register */ + + struct + { + __IOM uint32_t AL : 8; /*!< [7..0] AL monitor */ + uint32_t : 22; + __IOM uint32_t FAILCNT : 2; /*!< [31..30] Number of times responding incorrect response data */ + } ALCTRL_b; + }; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ + + struct + { + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; + }; +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller Common (R_DMA) + */ + +typedef struct /*!< (@ 0x4000A800) R_DMA Structure */ +{ + union + { + __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ + + struct + { + __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ + uint8_t : 7; + } DMAST_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ + + struct + { + __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ + uint8_t : 3; + __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ + uint8_t : 3; + } DMCTL_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[11]; + + union + { + __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ + + struct + { + __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ + uint32_t : 4; + __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ + uint32_t : 7; + __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ + uint32_t : 15; + } DMECHR_b; + }; + __IM uint32_t RESERVED6[15]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000080) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] DMAC Event Link Select */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; +} R_DMA_Type; /*!< Size = 160 (0xa0) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller (R_DMAC0) + */ + +typedef struct /*!< (@ 0x4000A000) R_DMAC0 Structure */ +{ + union + { + __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ + + struct + { + __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ + } DMSAR_b; + }; + + union + { + __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ + + struct + { + __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ + } DMDAR_b; + }; + + union + { + __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ + __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ + uint32_t : 6; + } DMCRA_b; + }; + + union + { + __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block + * transfer counter. */ + __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or + * repeat transfer operations. */ + } DMCRB_b; + }; + + union + { + __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ + + struct + { + __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ + uint16_t : 6; + __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ + __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ + uint16_t : 1; + __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ + __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ + } DMTMD_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ + + struct + { + __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ + __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ + __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ + uint8_t : 3; + } DMINT_b; + }; + + union + { + __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ + + struct + { + __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the + * extended repeat area on the destination address. For details + * on the settings. */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ + __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended + * repeat area on the source address. For details on the settings. */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ + } DMAMD_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ + + struct + { + __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected + * as the address update mode for transfer source or destination. */ + } DMOFR_b; + }; + + union + { + __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ + + struct + { + __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ + uint8_t : 7; + } DMCNT_b; + }; + + union + { + __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ + + struct + { + __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ + uint8_t : 3; + __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ + uint8_t : 3; + } DMREQ_b; + }; + + union + { + __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ + + struct + { + __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ + uint8_t : 3; + __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ + uint8_t : 2; + __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ + } DMSTS_b; + }; + __IM uint8_t RESERVED2; + __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ + __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ + + union + { + __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ + + struct + { + __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMSBS_b; + }; + + union + { + __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ + + struct + { + __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMDBS_b; + }; + + union + { + __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ + + struct + { + __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ + uint8_t : 7; + } DMBWR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DMAC0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x40311000) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + + struct + { + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; + }; + + union + { + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + + struct + { + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; + }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_DRW ================ */ +/* =========================================================================================================================== */ + +/** + * @brief 2D Drawing Engine (R_DRW) + */ + +typedef struct /*!< (@ 0x40444000) R_DRW Structure */ +{ + union + { + union + { + __OM uint32_t CONTROL; /*!< (@ 0x00000000) Geometry Control Register */ + + struct + { + __OM uint32_t LIM1ENABLE : 1; /*!< [0..0] Enable limiter 1 */ + __OM uint32_t LIM2ENABLE : 1; /*!< [1..1] Enable limiter 2 */ + __OM uint32_t LIM3ENABLE : 1; /*!< [2..2] Enable limiter 3 */ + __OM uint32_t LIM4ENABLE : 1; /*!< [3..3] Enable limiter 4 */ + __OM uint32_t LIM5ENABLE : 1; /*!< [4..4] Enable limiter 5 */ + __OM uint32_t LIM6ENABLE : 1; /*!< [5..5] Enable limiter 6 */ + __OM uint32_t QUAD1ENABLE : 1; /*!< [6..6] Enable quadratic coupling of limiters 1 and 2 */ + __OM uint32_t QUAD2ENABLE : 1; /*!< [7..7] Enable quadratic coupling of limiters 3 and 4 */ + __OM uint32_t QUAD3ENABLE : 1; /*!< [8..8] Enable quadratic coupling of limiters 5 and 6 */ + __OM uint32_t LIM1THRESHOLD : 1; /*!< [9..9] Enable limiter 1 threshold mode */ + __OM uint32_t LIM2THRESHOLD : 1; /*!< [10..10] Enable limiter 2 threshold mode */ + __OM uint32_t LIM3THRESHOLD : 1; /*!< [11..11] Enable limiter 3 threshold mode */ + __OM uint32_t LIM4THRESHOLD : 1; /*!< [12..12] Enable limiter 4 threshold mode */ + __OM uint32_t LIM5THRESHOLD : 1; /*!< [13..13] Enable limiter 5 threshold mode */ + __OM uint32_t LIM6THRESHOLD : 1; /*!< [14..14] Enable limiter 6 threshold mode */ + __OM uint32_t BAND1ENABLE : 1; /*!< [15..15] Enable band postprocess for limiter 1 (see L1BAND) */ + __OM uint32_t BAND2ENABLE : 1; /*!< [16..16] Enable band postprocess for limiter 1 (see L1BAND) */ + __OM uint32_t UNION12 : 1; /*!< [17..17] Combine limter 1 & 2 as union (output is called A) */ + __OM uint32_t UNION34 : 1; /*!< [18..18] Combine limter 3 & 4 as union (output is called B) */ + __OM uint32_t UNION56 : 1; /*!< [19..19] Combine limter 5 & 6 as union (output is called D) */ + __OM uint32_t UNIONAB : 1; /*!< [20..20] Combine outputs A & B as union (output is called C) */ + __OM uint32_t UNIONCD : 1; /*!< [21..21] Combine outputs C & D as union (output is final) */ + __OM uint32_t SPANABORT : 1; /*!< [22..22] Shape is horizontally convex, only a single span per + * scanline */ + __OM uint32_t SPANSTORE : 1; /*!< [23..23] Nextline span start is always equal or left to current-line + * span start */ + uint32_t : 8; + } CONTROL_b; + }; + + union + { + __IM uint32_t STATUS; /*!< (@ 0x00000000) Status Control Register */ + + struct + { + __IM uint32_t BUSYENUM : 1; /*!< [0..0] Enumeration unit status */ + __IM uint32_t BUSYWRITE : 1; /*!< [1..1] Framebuffer writeback status */ + __IM uint32_t CACHEDIRTY : 1; /*!< [2..2] Framebuffer cache status */ + __IM uint32_t DLISTACTIVE : 1; /*!< [3..3] Display list reader status */ + __IM uint32_t ENUMIRQ : 1; /*!< [4..4] enumeration finished interrupt triggered */ + __IM uint32_t DLISTIRQ : 1; /*!< [5..5] display list finished interrupt triggered */ + __IM uint32_t BUSIRQ : 1; /*!< [6..6] bus error interrupt triggered */ + uint32_t : 1; + __IM uint32_t BUSERRMFB : 1; /*!< [8..8] framebuffer bus error interrupt triggered */ + __IM uint32_t BUSERRMTXMRL : 1; /*!< [9..9] texture bus error interrupt triggered */ + __IM uint32_t BUSERRMDL : 1; /*!< [10..10] display list bus error interrupt triggered */ + uint32_t : 21; + } STATUS_b; + }; + }; + + union + { + union + { + __OM uint32_t CONTROL2; /*!< (@ 0x00000004) Surface Control Register */ + + struct + { + __OM uint32_t PATTERNENABLE : 1; /*!< [0..0] Pixel source is a pattern color (blend of COLOR1 and + * COLOR2 depending on PATTERN and pattern index) */ + __OM uint32_t TEXTUREENABLE : 1; /*!< [1..1] Pixel source is read from texture and used as an alpha + * to blend between COLOR1 and COLOR2 */ + __OM uint32_t PATTERNSOURCEL5 : 1; /*!< [2..2] Limiter 5 is used as pattern index instead of the default + * U limiter.Limiter 5 can be combined with limiter 6 to form + * a quadratic limiter which can be used to make quadratic + * pattern functions to draw radial patterns. */ + __OM uint32_t USEACB : 1; /*!< [3..3] Alpha blend mode */ + __OM uint32_t READFORMAT32 : 2; /*!< [5..4] Bit 4 and 3 of the texture buffer format.See READFORMAT + * above for description */ + __OM uint32_t BSFA : 1; /*!< [6..6] Blend source factor for alpha channel in alpha channel + * blending mode (USEACB = 1) */ + __OM uint32_t BDFA : 1; /*!< [7..7] Blend destinetion factor for alpha channel in alpha channel + * blending mode (USEACB = 1) */ + __OM uint32_t WRITEFORMAT2 : 1; /*!< [8..8] Bit 3 of framebuffer pixel formatSee WRITEFORMAT above + * description. */ + __OM uint32_t BSF : 1; /*!< [9..9] Blend source factorsrc factor is alpha (factor is 1 per + * default) */ + __OM uint32_t BDF : 1; /*!< [10..10] Blend destination factordst factor is alpha (factor + * is 1 per default) */ + __OM uint32_t BSI : 1; /*!< [11..11] Blend source factor is invertedsrc factor will be inverted + * (meaning 1-a or 1-1 depending on BSF) */ + __OM uint32_t BDI : 1; /*!< [12..12] Blend destination factor is inverteddst factor will + * be inverted (meaning 1-a or 1-1 depending on BDF) */ + __OM uint32_t BC2 : 1; /*!< [13..13] Blend color 2 instead of framebuffer pixel */ + __OM uint32_t TEXTURECLAMPX : 1; /*!< [14..14] Calculating U limiter outside use textureThe bit describes + * what happens if the U limiter (x direction in texture space) + * calculates a U value outside of the used texture */ + __OM uint32_t TEXTURECLAMPY : 1; /*!< [15..15] Calculating V limiter outside use textureThe bit describes + * what happens if the V limiter (y direction in texture space) + * calculates a V value outside of the used texture */ + __OM uint32_t TEXTUREFILTERX : 1; /*!< [16..16] Linear filtering on texture U axis */ + __OM uint32_t TEXTUREFILTERY : 1; /*!< [17..17] Linear filtering on texture V axis */ + __OM uint32_t READFORMAT10 : 2; /*!< [19..18] Pixel format of the texture buffer{READFORMAT32,READFORMAT10}0000: + * 8 bpp a(8)0001: 16 bpp RGB(565)0010: 32 bpp aRGB(8888)0011: + * 16 bpp aRGB(4444)0100: 16 bpp aRGB(1555)0101: 8 bpp aCLUT(44) + * 4 bit alpha and 4 bit indexed color1001: 8 bpp CLUT(8)/I(8), + * 8 bit indexed color/luminance1010: 4 bpp CLUT(4)/I(4), + * 4 bit indexed color/luminance1011: 2 bpp CLUT(2)/I(2), + * 2 bit indexed color/luminance 1100: 1 bpp CLUT(1)/I(1), + * 1 bit indexed color/luminance */ + __OM uint32_t WRITEFORMAT10 : 2; /*!< [21..20] Pixel format of the framebuffer */ + __OM uint32_t WRITEALPHA : 2; /*!< [23..22] Writeback alpha source for framebufferSet the 'alpha + * source' for the framebuffer(USEACB = 0)Blend alpha in color + * 2 instead of framebuffer alpha((USEACB = 1))In not alpha + * channel blending mode (USEACB = 0):Set the 'alpha source' + * for the framebuffer.In alpha channel blending mode (USEACB + * = 1):Blend alpha in color 2 instead of framebuffer alpha00B: + * BC2A = 1: use alpha from framebuffer as destination (DST_A)else: + * BC2A = 0: use alpha in color 2 as destination (DST_A) */ + __OM uint32_t RLEENABLE : 1; /*!< [24..24] RLE enable */ + __OM uint32_t CLUTENABLE : 1; /*!< [25..25] CLUT enable */ + __OM uint32_t COLKEYENABLE : 1; /*!< [26..26] color keying enable */ + __OM uint32_t CLUTFORMAT : 1; /*!< [27..27] Format of the CLUT */ + __OM uint32_t BSIA : 1; /*!< [28..28] Blend source factor inverted in alpha channel (USEACB + * = 1) */ + __OM uint32_t BDIA : 1; /*!< [29..29] Blend destination factor inverted in alpha channel + * (USEACB = 1) */ + __OM uint32_t RLEPIXELWIDTH : 2; /*!< [31..30] Texel width for RLE unit */ + } CONTROL2_b; + }; + + union + { + __IM uint32_t HWREVISION; /*!< (@ 0x00000004) Hardware Version and Feature Set ID Register */ + + struct + { + __IM uint32_t REV : 12; /*!< [11..0] Revision number */ + uint32_t : 5; + __IM uint32_t DLR : 1; /*!< [17..17] Display list reader feature */ + __IM uint32_t FBCACHE : 1; /*!< [18..18] Framebuffer cache feature */ + __IM uint32_t TXCACHE : 1; /*!< [19..19] Texture cache feature */ + __IM uint32_t PERFCOUNT : 1; /*!< [20..20] Two performance counter feature */ + __IM uint32_t TEXCLU : 1; /*!< [21..21] Texture CLUT with 16 or 256 entries feature */ + uint32_t : 1; + __IM uint32_t RLEUNIT : 1; /*!< [23..23] RLE unit feature */ + __IM uint32_t TEXCLUT256 : 1; /*!< [24..24] Texture CLUT feature */ + __IM uint32_t COLORKEY : 1; /*!< [25..25] Colorkey feature */ + uint32_t : 1; + __IM uint32_t ACBLEND : 1; /*!< [27..27] Alpha channel blending feature */ + uint32_t : 4; + } HWREVISION_b; + }; + }; + __IM uint32_t RESERVED[2]; + + union + { + __OM uint32_t L1START; /*!< (@ 0x00000010) Limiter 1 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L1START_b; + }; + + union + { + __OM uint32_t L2START; /*!< (@ 0x00000014) Limiter 2 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L2START_b; + }; + + union + { + __OM uint32_t L3START; /*!< (@ 0x00000018) Limiter 3 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L3START_b; + }; + + union + { + __OM uint32_t L4START; /*!< (@ 0x0000001C) Limiter 4 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L4START_b; + }; + + union + { + __OM uint32_t L5START; /*!< (@ 0x00000020) Limiter 5 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L5START_b; + }; + + union + { + __OM uint32_t L6START; /*!< (@ 0x00000024) Limiter 6 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L6START_b; + }; + + union + { + __OM uint32_t L1XADD; /*!< (@ 0x00000028) Limiter 1 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L1XADD_b; + }; + + union + { + __OM uint32_t L2XADD; /*!< (@ 0x0000002C) Limiter 2 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L2XADD_b; + }; + + union + { + __OM uint32_t L3XADD; /*!< (@ 0x00000030) Limiter 3 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L3XADD_b; + }; + + union + { + __OM uint32_t L4XADD; /*!< (@ 0x00000034) Limiter 4 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L4XADD_b; + }; + + union + { + __OM uint32_t L5XADD; /*!< (@ 0x00000038) Limiter 5 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L5XADD_b; + }; + + union + { + __OM uint32_t L6XADD; /*!< (@ 0x0000003C) Limiter 6 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L6XADD_b; + }; + + union + { + __OM uint32_t L1YADD; /*!< (@ 0x00000040) Limiter 1 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L1YADD_b; + }; + + union + { + __OM uint32_t L2YADD; /*!< (@ 0x00000044) Limiter 2 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L2YADD_b; + }; + + union + { + __OM uint32_t L3YADD; /*!< (@ 0x00000048) Limiter 3 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L3YADD_b; + }; + + union + { + __OM uint32_t L4YADD; /*!< (@ 0x0000004C) Limiter 4 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L4YADD_b; + }; + + union + { + __OM uint32_t L5YADD; /*!< (@ 0x00000050) Limiter 5 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L5YADD_b; + }; + + union + { + __OM uint32_t L6YADD; /*!< (@ 0x00000054) Limiter 6 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L6YADD_b; + }; + + union + { + __OM uint32_t L1BAND; /*!< (@ 0x00000058) Limiter 1 Band Width Parameter Register */ + + struct + { + __OM uint32_t LBAND : 32; /*!< [31..0] Limiter m band width parameter */ + } L1BAND_b; + }; + + union + { + __OM uint32_t L2BAND; /*!< (@ 0x0000005C) Limiter 2 Band Width Parameter Register */ + + struct + { + __OM uint32_t LBAND : 32; /*!< [31..0] Limiter m band width parameter */ + } L2BAND_b; + }; + __IM uint32_t RESERVED1; + + union + { + __OM uint32_t COLOR1; /*!< (@ 0x00000064) Base Color Register */ + + struct + { + __OM uint32_t COLOR1B : 8; /*!< [7..0] Blue channel of color 1 */ + __OM uint32_t COLOR1G : 8; /*!< [15..8] Green channel of color 1 */ + __OM uint32_t COLOR1R : 8; /*!< [23..16] Red channel of color 1 */ + __OM uint32_t COLOR1A : 8; /*!< [31..24] Alpha channel of color 1(0x00: transparent. . . 0xFF: + * opaque) */ + } COLOR1_b; + }; + + union + { + __OM uint32_t COLOR2; /*!< (@ 0x00000068) Secondary Color Register */ + + struct + { + __OM uint32_t COLOR2B : 8; /*!< [7..0] Blue channel of color 2 */ + __OM uint32_t COLOR2G : 8; /*!< [15..8] Green channel of color 2 */ + __OM uint32_t COLOR2R : 8; /*!< [23..16] Red channel of color 2 */ + __OM uint32_t COLOR2A : 8; /*!< [31..24] Alpha channel of color 2(0x00: transparent. . . 0xFF: + * opaque) */ + } COLOR2_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __OM uint32_t PATTERN; /*!< (@ 0x00000074) Pattern Register */ + + struct + { + __OM uint32_t PATTERN : 8; /*!< [7..0] Bitmap of the pattern */ + uint32_t : 24; + } PATTERN_b; + }; + + union + { + __OM uint32_t SIZE; /*!< (@ 0x00000078) Bounding Box Dimension Register */ + + struct + { + __OM uint32_t SIZEX : 16; /*!< [15..0] Width of the bounding box in pixelsvalid range: 0 to + * 1024 */ + __OM uint32_t SIZEY : 16; /*!< [31..16] Height of the bounding box in pixelsvalid range: 0 + * to 1024 */ + } SIZE_b; + }; + + union + { + __OM uint32_t PITCH; /*!< (@ 0x0000007C) Framebuffer Pitch And Spanstore Delay Register */ + + struct + { + __OM uint32_t PITCH : 16; /*!< [15..0] pitch of the framebuffer. A negative width can be used + * to render bottom-up instead of top-down */ + __OM uint32_t SSD : 16; /*!< [31..16] Spanstore delay */ + } PITCH_b; + }; + + union + { + __OM uint32_t ORIGIN; /*!< (@ 0x00000080) Framebuffer Base Address Register */ + + struct + { + __OM uint32_t ORIGIN : 32; /*!< [31..0] Address of the first pixel in framebuffer */ + } ORIGIN_b; + }; + __IM uint32_t RESERVED3[3]; + + union + { + __OM uint32_t LUSTART; /*!< (@ 0x00000090) U Limiter Start Value Register */ + + struct + { + __OM uint32_t LUSTART : 32; /*!< [31..0] U limiter start value */ + } LUSTART_b; + }; + + union + { + __OM uint32_t LUXADD; /*!< (@ 0x00000094) U Limiter X-Axis Increment Register */ + + struct + { + __OM uint32_t LUXADD : 32; /*!< [31..0] U limiter x-axis increment */ + } LUXADD_b; + }; + + union + { + __OM uint32_t LUYADD; /*!< (@ 0x00000098) U Limiter Y-Axis Increment Register */ + + struct + { + __OM uint32_t LUYADD : 32; /*!< [31..0] U limiter y-axis increment */ + } LUYADD_b; + }; + + union + { + __OM uint32_t LVSTARTI; /*!< (@ 0x0000009C) V Limiter Start Value Integer Part Register */ + + struct + { + __OM uint32_t LVSTARTI : 32; /*!< [31..0] V limiter start value integer part */ + } LVSTARTI_b; + }; + + union + { + __OM uint32_t LVSTARTF; /*!< (@ 0x000000A0) V Limiter Start Value Fractional Part Register */ + + struct + { + __OM uint32_t LVSTARTF : 16; /*!< [15..0] V limiter start value fractional part */ + uint32_t : 16; + } LVSTARTF_b; + }; + + union + { + __OM uint32_t LVXADDI; /*!< (@ 0x000000A4) V Limiter X-Axis Increment Integer Part Register */ + + struct + { + __OM uint32_t LVXADDI : 32; /*!< [31..0] V limiter x-axis increment integer part */ + } LVXADDI_b; + }; + + union + { + __OM uint32_t LVYADDI; /*!< (@ 0x000000A8) V Limiter Y-Axis Increment Integer Part Register */ + + struct + { + __OM uint32_t LVYADDI : 32; /*!< [31..0] V limiter y-axis increment integer part */ + } LVYADDI_b; + }; + + union + { + __OM uint32_t LVYXADDF; /*!< (@ 0x000000AC) V Limiter Increment Fractional Parts Register */ + + struct + { + __OM uint32_t LVXADDF : 16; /*!< [15..0] V xlimiter increment fractional part */ + __OM uint32_t LVYADDF : 16; /*!< [31..16] V y limiter increment fractional part */ + } LVYXADDF_b; + }; + __IM uint32_t RESERVED4; + + union + { + __OM uint32_t TEXPITCH; /*!< (@ 0x000000B4) Texels Per Texture Line Register */ + + struct + { + __OM uint32_t TEXPITCH : 32; /*!< [31..0] Texels per texture linevalid range: 0 to 2048 */ + } TEXPITCH_b; + }; + + union + { + __OM uint32_t TEXMASK; /*!< (@ 0x000000B8) Texture Size or Texture Address Mask Register */ + + struct + { + __OM uint32_t TEXUMASK : 11; /*!< [10..0] U maskSet TEXUMASK[10:0] = texture_width -1In texture + * wrapping mode (CONTROL2.TEXTURECLAMPX = 0): texture_width + * must be a power of 2.In texture clamping mode (CONTROL2.TEXTURECLAMPX + * = 1):all widths up to 2048 are allowed. */ + __OM uint32_t TEXVMASK : 21; /*!< [31..11] V maskSet TEXVMASK[20:0] = TEXPITCH * (texture_height + * - 1).In texture wrapping mode (CONTROL2.TEXTURECLAMPY = + * 0): texture_height must be a power of 2In texture clamping + * mode (CONTROL2.TEXTURECLAMPY = 1):all heights up to 1024 + * are allowed. */ + } TEXMASK_b; + }; + + union + { + __OM uint32_t TEXORIGIN; /*!< (@ 0x000000BC) Texture Base Address Register */ + + struct + { + __OM uint32_t TEXORIGIN : 32; /*!< [31..0] Texture base address */ + } TEXORIGIN_b; + }; + + union + { + __OM uint32_t IRQCTL; /*!< (@ 0x000000C0) Interrupt Control Register */ + + struct + { + __OM uint32_t ENUMIRQEN : 1; /*!< [0..0] ENUMIRQ interrupt mask enable */ + __OM uint32_t DLISTIRQEN : 1; /*!< [1..1] DLISTIRQ interrupt mask enable */ + __OM uint32_t ENUMIRQCLR : 1; /*!< [2..2] Clear enumeration interrupt ENUMIRQ */ + __OM uint32_t DLISTIRQCLR : 1; /*!< [3..3] Clear display list interrupt DLISTIRQ */ + __OM uint32_t BUSIRQEN : 1; /*!< [4..4] BUSIRQ interrupt mask enable */ + __OM uint32_t BUSIRQCLR : 1; /*!< [5..5] Clear bus error interrupt BUSIRQ */ + uint32_t : 26; + } IRQCTL_b; + }; + + union + { + __OM uint32_t CACHECTL; /*!< (@ 0x000000C4) Cache Control Register */ + + struct + { + __OM uint32_t CENABLEFX : 1; /*!< [0..0] Framebuffer cache enable */ + __OM uint32_t CFLUSHFX : 1; /*!< [1..1] Flush framebuffer cache */ + __OM uint32_t CENABLETX : 1; /*!< [2..2] Texture cache enable */ + __OM uint32_t CFLUSHTX : 1; /*!< [3..3] Flush texture cache */ + uint32_t : 28; + } CACHECTL_b; + }; + + union + { + __OM uint32_t DLISTSTART; /*!< (@ 0x000000C8) Display List Start Address Register */ + + struct + { + __OM uint32_t DLISTSTART : 32; /*!< [31..0] Display list start address */ + } DLISTSTART_b; + }; + + union + { + __IOM uint32_t PERFCOUNT1; /*!< (@ 0x000000CC) Performance Counter 1 */ + + struct + { + __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT + * = 0000 0000H. */ + } PERFCOUNT1_b; + }; + + union + { + __IOM uint32_t PERFCOUNT2; /*!< (@ 0x000000D0) Performance Counter 2 */ + + struct + { + __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT + * = 0000 0000H. */ + } PERFCOUNT2_b; + }; + + union + { + __OM uint32_t PERFTRIGGER; /*!< (@ 0x000000D4) Performance Counters Control Register */ + + struct + { + __OM uint32_t PERFTRIGGER1 : 16; /*!< [15..0] Selects the internal event that will increment PERFCOUNT1 + * register. */ + __OM uint32_t PERFTRIGGER2 : 16; /*!< [31..16] Selects the internal event that will increment PERFCOUNT2 + * register */ + } PERFTRIGGER_b; + }; + __IM uint32_t RESERVED5; + + union + { + __OM uint32_t TEXCLADDR; /*!< (@ 0x000000DC) CLUT Start Address Register */ + + struct + { + __OM uint32_t CLADDR : 8; /*!< [7..0] Texture CLUT start address for indexed texture format */ + uint32_t : 24; + } TEXCLADDR_b; + }; + + union + { + __OM uint32_t TEXCLDATA; /*!< (@ 0x000000E0) CLUT Data Register */ + + struct + { + __OM uint32_t CLDATA : 32; /*!< [31..0] Texture CLUT data for Indexed texture format */ + } TEXCLDATA_b; + }; + + union + { + __OM uint32_t TEXCLOFFSET; /*!< (@ 0x000000E4) CLUT Offset Register */ + + struct + { + __OM uint32_t CLOFFSET : 8; /*!< [7..0] Texture CLUT offset for Indexed texture format. CLOFFSET[7:0] + * is or'ed with the original index */ + uint32_t : 24; + } TEXCLOFFSET_b; + }; + + union + { + __OM uint32_t COLKEY; /*!< (@ 0x000000E8) Color Key Register */ + + struct + { + __OM uint32_t COLKEYB : 8; /*!< [7..0] Blue channel of color key */ + __OM uint32_t COLKEYG : 8; /*!< [15..8] Green channel of color key */ + __OM uint32_t COLKEYR : 8; /*!< [23..16] Red channel of color key */ + uint32_t : 8; + } COLKEY_b; + }; + __IM uint32_t RESERVED6[5]; + + union + { + __IOM uint32_t DBWER; /*!< (@ 0x00000100) DRW Bufferable Write Enable Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t BWE : 1; /*!< [2..2] Bufferable Write Enable */ + uint32_t : 29; + } DBWER_b; + }; +} R_DRW_Type; /*!< Size = 260 (0x104) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ + +typedef struct /*!< (@ 0x4000AC00) R_DTC Structure */ +{ + union + { + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_b; + }; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + + struct + { + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + + struct + { + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; + }; + + union + { + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_SEC_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + + struct + { + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; + }; + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Event Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x40201000) R_ELC Structure */ +{ + union + { + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IOM R_ELC_ELSEGR_Type ELSEGR[4]; /*!< (@ 0x00000004) Event Link Software Event Generation Register */ + __IM uint32_t RESERVED2[3]; + __IOM R_ELC_ELSR_Type ELSR[53]; /*!< (@ 0x00000020) Event Link Setting Register [0..52] */ + __IM uint32_t RESERVED3[3]; + + union + { + __IOM uint32_t ELCSARA; /*!< (@ 0x00000100) Event Link Controller Security Attribution Register + * A */ + + struct + { + __IOM uint32_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint32_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint32_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1 Security + * Attribution */ + __IOM uint32_t ELSEGR2 : 1; /*!< [3..3] Event Link Software Event Generation Register 2 Security + * Attribution */ + __IOM uint32_t ELSEGR3 : 1; /*!< [4..4] Event Link Software Event Generation Register 3 Security + * Attribution */ + uint32_t : 27; + } ELCSARA_b; + }; + + union + { + __IOM uint32_t ELCSARB; /*!< (@ 0x00000104) Event Link Controller Security Attribution Register + * B */ + + struct + { + __IOM uint32_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0 Security Attribution */ + __IOM uint32_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1 Security Attribution */ + __IOM uint32_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2 Security Attribution */ + __IOM uint32_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3 Security Attribution */ + __IOM uint32_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4 Security Attribution */ + __IOM uint32_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5 Security Attribution */ + __IOM uint32_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6 Security Attribution */ + __IOM uint32_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7 Security Attribution */ + __IOM uint32_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8 Security Attribution */ + __IOM uint32_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9 Security Attribution */ + __IOM uint32_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10 Security Attribution */ + __IOM uint32_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11 Security Attribution */ + __IOM uint32_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12 Security Attribution */ + __IOM uint32_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13 Security Attribution */ + __IOM uint32_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14 Security Attribution */ + __IOM uint32_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15 Security Attribution */ + __IOM uint32_t ELSR16 : 1; /*!< [16..16] Event Link Setting Register 16 Security Attribution */ + __IOM uint32_t ELSR17 : 1; /*!< [17..17] Event Link Setting Register 17 Security Attribution */ + __IOM uint32_t ELSR18 : 1; /*!< [18..18] Event Link Setting Register 18 Security Attribution */ + __IOM uint32_t ELSR19 : 1; /*!< [19..19] Event Link Setting Register 19 Security Attribution */ + __IOM uint32_t ELSR20 : 1; /*!< [20..20] Event Link Setting Register 20 Security Attribution */ + __IOM uint32_t ELSR21 : 1; /*!< [21..21] Event Link Setting Register 21 Security Attribution */ + __IOM uint32_t ELSR22 : 1; /*!< [22..22] Event Link Setting Register 22 Security Attribution */ + __IOM uint32_t ELSR23 : 1; /*!< [23..23] Event Link Setting Register 23 Security Attribution */ + __IOM uint32_t ELSR24 : 1; /*!< [24..24] Event Link Setting Register 24 Security Attribution */ + __IOM uint32_t ELSR25 : 1; /*!< [25..25] Event Link Setting Register 25 Security Attribution */ + __IOM uint32_t ELSR26 : 1; /*!< [26..26] Event Link Setting Register 26 Security Attribution */ + __IOM uint32_t ELSR27 : 1; /*!< [27..27] Event Link Setting Register 27 Security Attribution */ + __IOM uint32_t ELSR28 : 1; /*!< [28..28] Event Link Setting Register 28 Security Attribution */ + __IOM uint32_t ELSR29 : 1; /*!< [29..29] Event Link Setting Register 29 Security Attribution */ + __IOM uint32_t ELSR30 : 1; /*!< [30..30] Event Link Setting Register 30 Security Attribution */ + __IOM uint32_t ELSR31 : 1; /*!< [31..31] Event Link Setting Register 31 Security Attribution */ + } ELCSARB_b; + }; + + union + { + __IOM uint32_t ELCSARC; /*!< (@ 0x00000108) Event Link Controller Security Attribution Register + * C */ + + struct + { + __IOM uint32_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0 Security Attribution */ + __IOM uint32_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1 Security Attribution */ + __IOM uint32_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2 Security Attribution */ + __IOM uint32_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3 Security Attribution */ + __IOM uint32_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4 Security Attribution */ + __IOM uint32_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5 Security Attribution */ + __IOM uint32_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6 Security Attribution */ + __IOM uint32_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7 Security Attribution */ + __IOM uint32_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8 Security Attribution */ + __IOM uint32_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9 Security Attribution */ + __IOM uint32_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10 Security Attribution */ + __IOM uint32_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11 Security Attribution */ + __IOM uint32_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12 Security Attribution */ + __IOM uint32_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13 Security Attribution */ + __IOM uint32_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14 Security Attribution */ + __IOM uint32_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15 Security Attribution */ + __IOM uint32_t ELSR16 : 1; /*!< [16..16] Event Link Setting Register 16 Security Attribution */ + __IOM uint32_t ELSR17 : 1; /*!< [17..17] Event Link Setting Register 17 Security Attribution */ + __IOM uint32_t ELSR18 : 1; /*!< [18..18] Event Link Setting Register 18 Security Attribution */ + __IOM uint32_t ELSR19 : 1; /*!< [19..19] Event Link Setting Register 19 Security Attribution */ + __IOM uint32_t ELSR20 : 1; /*!< [20..20] Event Link Setting Register 20 Security Attribution */ + __IOM uint32_t ELSR21 : 1; /*!< [21..21] Event Link Setting Register 21 Security Attribution */ + __IOM uint32_t ELSR22 : 1; /*!< [22..22] Event Link Setting Register 22 Security Attribution */ + __IOM uint32_t ELSR23 : 1; /*!< [23..23] Event Link Setting Register 23 Security Attribution */ + __IOM uint32_t ELSR24 : 1; /*!< [24..24] Event Link Setting Register 24 Security Attribution */ + __IOM uint32_t ELSR25 : 1; /*!< [25..25] Event Link Setting Register 25 Security Attribution */ + __IOM uint32_t ELSR26 : 1; /*!< [26..26] Event Link Setting Register 26 Security Attribution */ + __IOM uint32_t ELSR27 : 1; /*!< [27..27] Event Link Setting Register 27 Security Attribution */ + __IOM uint32_t ELSR28 : 1; /*!< [28..28] Event Link Setting Register 28 Security Attribution */ + __IOM uint32_t ELSR29 : 1; /*!< [29..29] Event Link Setting Register 29 Security Attribution */ + __IOM uint32_t ELSR30 : 1; /*!< [30..30] Event Link Setting Register 30 Security Attribution */ + __IOM uint32_t ELSR31 : 1; /*!< [31..31] Event Link Setting Register 31 Security Attribution */ + } ELCSARC_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t ELCPARA; /*!< (@ 0x00000110) Event Link Controller Privilege Attribution Register + * A */ + + struct + { + __IOM uint32_t ELCR : 1; /*!< [0..0] Event Link Controller Register Privilege Attribution */ + __IOM uint32_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Privilege + * Attribution */ + __IOM uint32_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1 Privilege + * Attribution */ + __IOM uint32_t ELSEGR2 : 1; /*!< [3..3] Event Link Software Event Generation Register 2 Privilege + * Attribution */ + __IOM uint32_t ELSEGR3 : 1; /*!< [4..4] Event Link Software Event Generation Register 3 Privilege + * Attribution */ + uint32_t : 27; + } ELCPARA_b; + }; + + union + { + __IOM uint32_t ELCPARB; /*!< (@ 0x00000114) Event Link Controller Privilege Attribution Register + * B */ + + struct + { + __IOM uint32_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0 Privilege Attribution */ + __IOM uint32_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1 Privilege Attribution */ + __IOM uint32_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2 Privilege Attribution */ + __IOM uint32_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3 Privilege Attribution */ + __IOM uint32_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4 Privilege Attribution */ + __IOM uint32_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5 Privilege Attribution */ + __IOM uint32_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6 Privilege Attribution */ + __IOM uint32_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7 Privilege Attribution */ + __IOM uint32_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8 Privilege Attribution */ + __IOM uint32_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9 Privilege Attribution */ + __IOM uint32_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10 Privilege Attribution */ + __IOM uint32_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11 Privilege Attribution */ + __IOM uint32_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12 Privilege Attribution */ + __IOM uint32_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13 Privilege Attribution */ + __IOM uint32_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14 Privilege Attribution */ + __IOM uint32_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15 Privilege Attribution */ + __IOM uint32_t ELSR16 : 1; /*!< [16..16] Event Link Setting Register 16 Privilege Attribution */ + __IOM uint32_t ELSR17 : 1; /*!< [17..17] Event Link Setting Register 17 Privilege Attribution */ + __IOM uint32_t ELSR18 : 1; /*!< [18..18] Event Link Setting Register 18 Privilege Attribution */ + __IOM uint32_t ELSR19 : 1; /*!< [19..19] Event Link Setting Register 19 Privilege Attribution */ + __IOM uint32_t ELSR20 : 1; /*!< [20..20] Event Link Setting Register 20 Privilege Attribution */ + __IOM uint32_t ELSR21 : 1; /*!< [21..21] Event Link Setting Register 21 Privilege Attribution */ + __IOM uint32_t ELSR22 : 1; /*!< [22..22] Event Link Setting Register 22 Privilege Attribution */ + __IOM uint32_t ELSR23 : 1; /*!< [23..23] Event Link Setting Register 23 Privilege Attribution */ + __IOM uint32_t ELSR24 : 1; /*!< [24..24] Event Link Setting Register 24 Privilege Attribution */ + __IOM uint32_t ELSR25 : 1; /*!< [25..25] Event Link Setting Register 25 Privilege Attribution */ + __IOM uint32_t ELSR26 : 1; /*!< [26..26] Event Link Setting Register 26 Privilege Attribution */ + __IOM uint32_t ELSR27 : 1; /*!< [27..27] Event Link Setting Register 27 Privilege Attribution */ + __IOM uint32_t ELSR28 : 1; /*!< [28..28] Event Link Setting Register 28 Privilege Attribution */ + __IOM uint32_t ELSR29 : 1; /*!< [29..29] Event Link Setting Register 29 Privilege Attribution */ + __IOM uint32_t ELSR30 : 1; /*!< [30..30] Event Link Setting Register 30 Privilege Attribution */ + __IOM uint32_t ELSR31 : 1; /*!< [31..31] Event Link Setting Register 31 Privilege Attribution */ + } ELCPARB_b; + }; + + union + { + __IOM uint32_t ELCPARC; /*!< (@ 0x00000118) Event Link Controller Privilege Attribution Register + * C */ + + struct + { + __IOM uint32_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0 Privilege Attribution */ + __IOM uint32_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1 Privilege Attribution */ + __IOM uint32_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2 Privilege Attribution */ + __IOM uint32_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3 Privilege Attribution */ + __IOM uint32_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4 Privilege Attribution */ + __IOM uint32_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5 Privilege Attribution */ + __IOM uint32_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6 Privilege Attribution */ + __IOM uint32_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7 Privilege Attribution */ + __IOM uint32_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8 Privilege Attribution */ + __IOM uint32_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9 Privilege Attribution */ + __IOM uint32_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10 Privilege Attribution */ + __IOM uint32_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11 Privilege Attribution */ + __IOM uint32_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12 Privilege Attribution */ + __IOM uint32_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13 Privilege Attribution */ + __IOM uint32_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14 Privilege Attribution */ + __IOM uint32_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15 Privilege Attribution */ + __IOM uint32_t ELSR16 : 1; /*!< [16..16] Event Link Setting Register 16 Privilege Attribution */ + __IOM uint32_t ELSR17 : 1; /*!< [17..17] Event Link Setting Register 17 Privilege Attribution */ + __IOM uint32_t ELSR18 : 1; /*!< [18..18] Event Link Setting Register 18 Privilege Attribution */ + __IOM uint32_t ELSR19 : 1; /*!< [19..19] Event Link Setting Register 19 Privilege Attribution */ + __IOM uint32_t ELSR20 : 1; /*!< [20..20] Event Link Setting Register 20 Privilege Attribution */ + __IOM uint32_t ELSR21 : 1; /*!< [21..21] Event Link Setting Register 21 Privilege Attribution */ + __IOM uint32_t ELSR22 : 1; /*!< [22..22] Event Link Setting Register 22 Privilege Attribution */ + __IOM uint32_t ELSR23 : 1; /*!< [23..23] Event Link Setting Register 23 Privilege Attribution */ + __IOM uint32_t ELSR24 : 1; /*!< [24..24] Event Link Setting Register 24 Privilege Attribution */ + __IOM uint32_t ELSR25 : 1; /*!< [25..25] Event Link Setting Register 25 Privilege Attribution */ + __IOM uint32_t ELSR26 : 1; /*!< [26..26] Event Link Setting Register 26 Privilege Attribution */ + __IOM uint32_t ELSR27 : 1; /*!< [27..27] Event Link Setting Register 27 Privilege Attribution */ + __IOM uint32_t ELSR28 : 1; /*!< [28..28] Event Link Setting Register 28 Privilege Attribution */ + __IOM uint32_t ELSR29 : 1; /*!< [29..29] Event Link Setting Register 29 Privilege Attribution */ + __IOM uint32_t ELSR30 : 1; /*!< [30..30] Event Link Setting Register 30 Privilege Attribution */ + __IOM uint32_t ELSR31 : 1; /*!< [31..31] Event Link Setting Register 31 Privilege Attribution */ + } ELCPARC_b; + }; +} R_ELC_Type; /*!< Size = 284 (0x11c) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EDMAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet DMA Controller (R_ETHERC_EDMAC) + */ + +typedef struct /*!< (@ 0x40354000) R_ETHERC_EDMAC Structure */ +{ + union + { + __IOM uint32_t EDMR; /*!< (@ 0x00000000) EDMAC Mode Register */ + + struct + { + __OM uint32_t SWR : 1; /*!< [0..0] Software Reset */ + uint32_t : 3; + __IOM uint32_t DL : 2; /*!< [5..4] Transmit/Receive DescriptorLength */ + __IOM uint32_t DE : 1; /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting + * applies to data for the transmit/receive buffer. It does + * not apply to transmit/receive descriptors and registers. */ + uint32_t : 25; + } EDMR_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t EDTRR; /*!< (@ 0x00000008) EDMAC Transmit Request Register */ + + struct + { + __OM uint32_t TR : 1; /*!< [0..0] Transmit Request */ + uint32_t : 31; + } EDTRR_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t EDRRR; /*!< (@ 0x00000010) EDMAC Receive Request Register */ + + struct + { + __IOM uint32_t RR : 1; /*!< [0..0] Receive Request */ + uint32_t : 31; + } EDRRR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t TDLAR; /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register */ + + struct + { + __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } TDLAR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t RDLAR; /*!< (@ 0x00000020) Receive Descriptor List Start Address Register */ + + struct + { + __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } RDLAR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t EESR; /*!< (@ 0x00000028) ETHERC/EDMAC Status Register */ + + struct + { + __IOM uint32_t CERF : 1; /*!< [0..0] CRC Error Flag */ + __IOM uint32_t PRE : 1; /*!< [1..1] PHY-LSI Receive Error Flag */ + __IOM uint32_t RTSF : 1; /*!< [2..2] Frame-Too-Short Error Flag */ + __IOM uint32_t RTLF : 1; /*!< [3..3] Frame-Too-Long Error Flag */ + __IOM uint32_t RRF : 1; /*!< [4..4] Alignment Error Flag */ + uint32_t : 2; + __IOM uint32_t RMAF : 1; /*!< [7..7] Multicast Address Frame Receive Flag */ + __IOM uint32_t TRO : 1; /*!< [8..8] Transmit Retry Over Flag */ + __IOM uint32_t CD : 1; /*!< [9..9] Late Collision Detect Flag */ + __IOM uint32_t DLC : 1; /*!< [10..10] Loss of Carrier Detect Flag */ + __IOM uint32_t CND : 1; /*!< [11..11] Carrier Not Detect Flag */ + uint32_t : 4; + __IOM uint32_t RFOF : 1; /*!< [16..16] Receive FIFO Overflow Flag */ + __IOM uint32_t RDE : 1; /*!< [17..17] Receive Descriptor Empty Flag */ + __IOM uint32_t FR : 1; /*!< [18..18] Frame Receive Flag */ + __IOM uint32_t TFUF : 1; /*!< [19..19] Transmit FIFO Underflow Flag */ + __IOM uint32_t TDE : 1; /*!< [20..20] Transmit Descriptor Empty Flag */ + __IOM uint32_t TC : 1; /*!< [21..21] Frame Transfer Complete Flag */ + __IM uint32_t ECI : 1; /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source + * in the ETHERCn.ECSR register is cleared, the ECI flag is + * also cleared. */ + __IOM uint32_t ADE : 1; /*!< [23..23] Address Error Flag */ + __IOM uint32_t RFCOF : 1; /*!< [24..24] Receive Frame Counter Overflow Flag */ + __IOM uint32_t RABT : 1; /*!< [25..25] Receive Abort Detect Flag */ + __IOM uint32_t TABT : 1; /*!< [26..26] Transmit Abort Detect Flag */ + uint32_t : 3; + __IOM uint32_t TWB : 1; /*!< [30..30] Write-Back Complete Flag */ + uint32_t : 1; + } EESR_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t EESIPR; /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register */ + + struct + { + __IOM uint32_t CERFIP : 1; /*!< [0..0] CRC Error Interrupt Request Enable */ + __IOM uint32_t PREIP : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable */ + __IOM uint32_t RTSFIP : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable */ + __IOM uint32_t RTLFIP : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable */ + __IOM uint32_t RRFIP : 1; /*!< [4..4] Alignment Error Interrupt Request Enable */ + uint32_t : 2; + __IOM uint32_t RMAFIP : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable */ + __IOM uint32_t TROIP : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable */ + __IOM uint32_t CDIP : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable */ + __IOM uint32_t DLCIP : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable */ + __IOM uint32_t CNDIP : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable */ + uint32_t : 4; + __IOM uint32_t RFOFIP : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable */ + __IOM uint32_t RDEIP : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t FRIP : 1; /*!< [18..18] Frame Receive Interrupt Request Enable */ + __IOM uint32_t TFUFIP : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable */ + __IOM uint32_t TDEIP : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t TCIP : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable */ + __IOM uint32_t ECIIP : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable */ + __IOM uint32_t ADEIP : 1; /*!< [23..23] Address Error Interrupt Request Enable */ + __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable */ + __IOM uint32_t RABTIP : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable */ + __IOM uint32_t TABTIP : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable */ + uint32_t : 3; + __IOM uint32_t TWBIP : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable */ + uint32_t : 1; + } EESIPR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t TRSCER; /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable + * Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t RRFCE : 1; /*!< [4..4] RRF Flag Copy Enable */ + uint32_t : 2; + __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable */ + uint32_t : 24; + } TRSCER_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t RMFCR; /*!< (@ 0x00000040) Missed-Frame Counter Register */ + + struct + { + __IOM uint32_t MFC : 16; /*!< [15..0] Missed-Frame CounterThese bits indicate the number of + * frames that are discarded and not transferred to the receive + * buffer during reception. */ + uint32_t : 16; + } RMFCR_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t TFTR; /*!< (@ 0x00000048) Transmit FIFO Threshold Register */ + + struct + { + __IOM uint32_t TFT : 11; /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is + * the set value multiplied by 4. Example: 00Dh: 52 bytes + * 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes */ + uint32_t : 21; + } TFTR_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t FDR; /*!< (@ 0x00000050) Transmit FIFO Threshold Register */ + + struct + { + __IOM uint32_t RFD : 5; /*!< [4..0] Transmit FIFO Depth */ + uint32_t : 3; + __IOM uint32_t TFD : 5; /*!< [12..8] Receive FIFO Depth */ + uint32_t : 19; + } FDR_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t RMCR; /*!< (@ 0x00000058) Receive Method Control Register */ + + struct + { + __IOM uint32_t RNR : 1; /*!< [0..0] Receive Request Reset */ + uint32_t : 31; + } RMCR_b; + }; + __IM uint32_t RESERVED11[2]; + + union + { + __IOM uint32_t TFUCR; /*!< (@ 0x00000064) Transmit FIFO Underflow Counter */ + + struct + { + __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how + * many times the transmit FIFO has underflowed. The counter + * stops when the counter value reaches FFFFh. */ + uint32_t : 16; + } TFUCR_b; + }; + + union + { + __IOM uint32_t RFOCR; /*!< (@ 0x00000068) Receive FIFO Overflow Counter */ + + struct + { + __IOM uint32_t OVER : 16; /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many + * times the receive FIFO has overflowed. The counter stops + * when the counter value reaches FFFFh. */ + uint32_t : 16; + } RFOCR_b; + }; + + union + { + __IOM uint32_t IOSR; /*!< (@ 0x0000006C) Independent Output Signal Setting Register */ + + struct + { + __IOM uint32_t ELB : 1; /*!< [0..0] External Loopback Mode */ + uint32_t : 31; + } IOSR_b; + }; + + union + { + __IOM uint32_t FCFTR; /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register */ + + struct + { + __IOM uint32_t RFDO : 3; /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 + * bytes of data is stored in the receive FIFO.) */ + uint32_t : 13; + __IOM uint32_t RFFO : 3; /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) + * receive frames have been stored in the receive FIFO.) */ + uint32_t : 13; + } FCFTR_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t RPADIR; /*!< (@ 0x00000078) Receive Data Padding Insert Register */ + + struct + { + __IOM uint32_t PADR : 6; /*!< [5..0] Padding Slot */ + uint32_t : 10; + __IOM uint32_t PADS : 2; /*!< [17..16] Padding Size */ + uint32_t : 14; + } RPADIR_b; + }; + + union + { + __IOM uint32_t TRIMD; /*!< (@ 0x0000007C) Transmit Interrupt Setting Register */ + + struct + { + __IOM uint32_t TIS : 1; /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in + * the mode selected by the TIM bit to notify an interrupt. */ + uint32_t : 3; + __IOM uint32_t TIM : 1; /*!< [4..4] Transmit Interrupt Mode */ + uint32_t : 27; + } TRIMD_b; + }; + __IM uint32_t RESERVED13[18]; + + union + { + __IOM uint32_t RBWAR; /*!< (@ 0x000000C8) Receive Buffer Write Address Register */ + + struct + { + __IM uint32_t RBWAR : 32; /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register + * indicates the last address that the EDMAC has written data + * to when writing to the receive buffer.Refer to the address + * indicated by the RBWAR register to recognize which address + * in the receive buffer the EDMAC is writing data to. Note + * that the address that the EDMAC is outputting to the receive + * buffer may not match the read value of the RBWAR register + * during data reception. */ + } RBWAR_b; + }; + + union + { + __IOM uint32_t RDFAR; /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register */ + + struct + { + __IM uint32_t RDFAR : 32; /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register + * indicates the start address of the last fetched receive + * descriptor when the EDMAC fetches descriptor information + * from the receive descriptor.Refer to the address indicated + * by the RDFAR register to recognize which receive descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the receive descriptor that the + * EDMAC fetches may not match the read value of the RDFAR + * register during data reception. */ + } RDFAR_b; + }; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t TBRAR; /*!< (@ 0x000000D4) Transmit Buffer Read Address Register */ + + struct + { + __IM uint32_t TBRAR : 32; /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register + * indicates the last address that the EDMAC has read data + * from when reading data from the transmit buffer.Refer to + * the address indicated by the TBRAR register to recognize + * which address in the transmit buffer the EDMAC is reading + * from. Note that the address that the EDMAC is outputting + * to the transmit buffer may not match the read value of + * the TBRAR register. */ + } TBRAR_b; + }; + + union + { + __IM uint32_t TDFAR; /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register */ + + struct + { + __IM uint32_t TDFAR : 32; /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR + * register indicates the start address of the last fetched + * transmit descriptor when the EDMAC fetches descriptor information + * from the transmit descriptor.Refer to the address indicated + * by the TDFAR register to recognize which transmit descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the transmit descriptor that the + * EDMAC fetches may not match the read value of the TDFAR + * register. */ + } TDFAR_b; + }; +} R_ETHERC_EDMAC_Type; /*!< Size = 220 (0xdc) */ + +/* =========================================================================================================================== */ +/* ================ R_GLCDC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Graphics LCD Controller (R_GLCDC) + */ + +typedef struct /*!< (@ 0x40342000) R_GLCDC Structure */ +{ + union + { + __IOM uint32_t GR1_CLUT0[256]; /*!< (@ 0x00000000) Color Palette 0 Plane for Graphics 1 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR1_CLUT0_b[256]; + }; + + union + { + __IOM uint32_t GR1_CLUT1[256]; /*!< (@ 0x00000400) Color Palette 1 Plane for Graphics 1 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR1_CLUT1_b[256]; + }; + + union + { + __IOM uint32_t GR2_CLUT0[256]; /*!< (@ 0x00000800) Color Palette 0 Plane for Graphics 2 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR2_CLUT0_b[256]; + }; + + union + { + __IOM uint32_t GR2_CLUT1[256]; /*!< (@ 0x00000C00) Color Palette 1 Plane for Graphics 2 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR2_CLUT1_b[256]; + }; + __IOM R_GLCDC_BG_Type BG; /*!< (@ 0x00001000) Background Registers */ + __IM uint32_t RESERVED[57]; + __IOM R_GLCDC_GR_Type GR[2]; /*!< (@ 0x00001100) Layer Registers */ + __IOM R_GLCDC_GAM_Type GAM[3]; /*!< (@ 0x00001300) Gamma Settings */ + __IOM R_GLCDC_OUT_Type OUT; /*!< (@ 0x000013C0) Output Control Registers */ + __IM uint32_t RESERVED1[6]; + __IOM R_GLCDC_TCON_Type TCON; /*!< (@ 0x00001400) Timing Control Registers */ + __IM uint32_t RESERVED2[5]; + __IOM R_GLCDC_SYSCNT_Type SYSCNT; /*!< (@ 0x00001440) GLCDC System Control Registers */ +} R_GLCDC_Type; /*!< Size = 5204 (0x1454) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40322000) R_GPT0 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + __OM uint32_t CCLR14 : 1; /*!< [14..14] Channel GTCNT Count Clear */ + __OM uint32_t CCLR15 : 1; /*!< [15..15] Channel GTCNT Count Clear */ + __OM uint32_t CCLR16 : 1; /*!< [16..16] Channel GTCNT Count Clear */ + __OM uint32_t CCLR17 : 1; /*!< [17..17] Channel GTCNT Count Clear */ + __OM uint32_t CCLR18 : 1; /*!< [18..18] Channel GTCNT Count Clear */ + __OM uint32_t CCLR19 : 1; /*!< [19..19] Channel GTCNT Count Clear */ + __OM uint32_t CCLR20 : 1; /*!< [20..20] Channel GTCNT Count Clear */ + __OM uint32_t CCLR21 : 1; /*!< [21..21] Channel GTCNT Count Clear */ + __OM uint32_t CCLR22 : 1; /*!< [22..22] Channel GTCNT Count Clear */ + __OM uint32_t CCLR23 : 1; /*!< [23..23] Channel GTCNT Count Clear */ + __OM uint32_t CCLR24 : 1; /*!< [24..24] Channel GTCNT Count Clear */ + __OM uint32_t CCLR25 : 1; /*!< [25..25] Channel GTCNT Count Clear */ + __OM uint32_t CCLR26 : 1; /*!< [26..26] Channel GTCNT Count Clear */ + __OM uint32_t CCLR27 : 1; /*!< [27..27] Channel GTCNT Count Clear */ + __OM uint32_t CCLR28 : 1; /*!< [28..28] Channel GTCNT Count Clear */ + __OM uint32_t CCLR29 : 1; /*!< [29..29] Channel GTCNT Count Clear */ + __OM uint32_t CCLR30 : 1; /*!< [30..30] Channel GTCNT Count Clear */ + __OM uint32_t CCLR31 : 1; /*!< [31..31] Channel GTCNT Count Clear */ + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; + __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ + __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ + __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ + __IOM uint32_t CPSCD : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable */ + uint32_t : 2; + __IOM uint32_t SSCEN : 1; /*!< [15..15] Synchronous Set/Clear Enable */ + __IOM uint32_t MD : 4; /*!< [19..16] Mode Select */ + uint32_t : 3; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + __IOM uint32_t CKEG : 2; /*!< [28..27] Clock Edge Select */ + uint32_t : 3; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + uint32_t : 1; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + * Clear Enable */ + __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous + * Clear Enable */ + __IOM uint32_t SCFC : 1; /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFD : 1; /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFE : 1; /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFF : 1; /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFPO : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable */ + __IOM uint32_t SCFPU : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable */ + __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion + * Start Request Enable */ + __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D + * Conversion Start Request Enable */ + __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion + * Start Request Enable */ + __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D + * Conversion Start Request Enable */ + uint32_t : 4; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 4; + __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable */ + uint32_t : 1; + __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable */ + uint32_t : 5; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + + struct + { + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + + struct + { + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; + }; + + union + { + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + + struct + { + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + + struct + { + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + + struct + { + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + + struct + { + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ + + struct + { + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + + struct + { + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + + struct + { + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + struct + { + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + + struct + { + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + + struct + { + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + + union + { + __IOM uint32_t GTADSMR; /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request + * Signal Monitoring Register */ + + struct + { + __IOM uint32_t ADSMS0 : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output + * Enabling */ + uint32_t : 7; + __IOM uint32_t ADSMS1 : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output + * Enabling */ + uint32_t : 7; + } GTADSMR_b; + }; + + union + { + __IOM uint32_t GTEITC; /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping + * Counter Control Register */ + + struct + { + __IOM uint32_t EIVTC1 : 2; /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t EIVTT1 : 4; /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting */ + uint32_t : 4; + __IM uint32_t EITCNT1 : 4; /*!< [15..12] Extended Interrupt Skipping Counter 1 */ + __IOM uint32_t EIVTC2 : 2; /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source + * select */ + uint32_t : 2; + __IOM uint32_t EIVTT2 : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting */ + __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value */ + __IM uint32_t EITCNT2 : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2 */ + } GTEITC_b; + }; + + union + { + __IOM uint32_t GTEITLI1; /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping + * Setting Register 1 */ + + struct + { + __IOM uint32_t EITLA : 3; /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLB : 3; /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLC : 3; /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLD : 3; /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLE : 3; /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLF : 3; /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLV : 3; /*!< [26..24] Overflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLU : 3; /*!< [30..28] Underflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + } GTEITLI1_b; + }; + + union + { + __IOM uint32_t GTEITLI2; /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping + * Setting Register 2 */ + + struct + { + __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended + * Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended + * Skipping Function Select */ + uint32_t : 25; + } GTEITLI2_b; + }; + + union + { + __IOM uint32_t GTEITLB; /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping + * Setting Register */ + + struct + { + __IOM uint32_t EBTLCA : 3; /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLCB : 3; /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLPR : 3; /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 5; + __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + } GTEITLB_b; + }; + + union + { + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ + + struct + { + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; + }; + + union + { + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + + struct + { + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; + }; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDAE : 1; /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDDE : 1; /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable */ + uint32_t : 4; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDAD : 1; /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDDD : 1; /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable */ + uint32_t : 4; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + __IOM uint32_t SSCE : 1; /*!< [17..17] Synchronous Set/Clear Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + __IOM uint32_t SSCD : 1; /*!< [25..25] Synchronous Set/Clear Simultaneous Disable */ + uint32_t : 6; + } GTSECR_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t GTBER2; /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2 */ + + struct + { + __IOM uint32_t CCTCA : 1; /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTCB : 1; /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTPR : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable */ + __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTDV : 1; /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer + * Disable */ + uint32_t : 2; + __IOM uint32_t CMTCA : 2; /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer + * Enable */ + __IOM uint32_t CMTCB : 2; /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer + * Enable */ + uint32_t : 1; + __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer + * Enable */ + __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer + * Enable */ + uint32_t : 1; + __IOM uint32_t CPTCA : 1; /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTCB : 1; /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTPR : 1; /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTDV : 1; /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer + * Transfer Disable */ + uint32_t : 2; + __IOM uint32_t CP3DB : 1; /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select */ + __IOM uint32_t CPBTD : 1; /*!< [25..25] Complementary PWM mode Buffer Transfer Disable */ + __IOM uint32_t OLTTA : 2; /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select */ + __IOM uint32_t OLTTB : 2; /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select */ + uint32_t : 2; + } GTBER2_b; + }; + + union + { + __IOM uint32_t GTOLBR; /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register */ + + struct + { + __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits */ + uint32_t : 11; + __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits */ + uint32_t : 11; + } GTOLBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t GTICCR; /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input + * Capture Control Register */ + + struct + { + __IOM uint32_t ICAFA : 1; /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture + * to Other Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFB : 1; /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture + * to Other Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFC : 1; /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFD : 1; /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFE : 1; /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFF : 1; /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture + * Source Enable */ + __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture + * Source Enable */ + __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input + * Capture Source Enable */ + uint32_t : 5; + __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select */ + __IOM uint32_t ICBFA : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture + * to Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFB : 1; /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture + * to Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFC : 1; /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFD : 1; /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFE : 1; /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to + * Other Channel GTCCRb Input Capture Source Enable */ + __IOM uint32_t ICBFF : 1; /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture + * Source Enable */ + __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input + * Capture Source Enable */ + __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input + * Capture Source Enable */ + uint32_t : 5; + __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select */ + } GTICCR_b; + }; +} R_GPT0_Type; /*!< Size = 240 (0xf0) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_GTCLK ================ */ +/* =========================================================================================================================== */ + +/** + * @brief GTCLK (R_GPT_GTCLK) + */ + +typedef struct /*!< (@ 0x40323F10) R_GPT_GTCLK Structure */ +{ + union + { + __IOM uint32_t GTCLKCR; /*!< (@ 0x00000000) General PWM Timer Clock Control Register */ + + struct + { + __IOM uint32_t BPEN : 1; /*!< [0..0] Synchronization Circuit Bypass Enable */ + uint32_t : 31; + } GTCLKCR_b; + }; +} R_GPT_GTCLK_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_ODC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief PWM Delay Generation Circuit (R_GPT_ODC) + */ + +typedef struct /*!< (@ 0x40324000) R_GPT_ODC Structure */ +{ + union + { + __IOM uint16_t GTDLYCR1; /*!< (@ 0x00000000) PWM Output Delay Control Register1 */ + + struct + { + __IOM uint16_t DLLEN : 1; /*!< [0..0] DLL Operation Enable */ + __IOM uint16_t DLYRST : 1; /*!< [1..1] PWM Delay Generation Circuit Reset */ + uint16_t : 6; + __IOM uint16_t FRANGE : 2; /*!< [9..8] GPT core clock Frequency Range */ + uint16_t : 6; + } GTDLYCR1_b; + }; + + union + { + __IOM uint16_t GTDLYCR2; /*!< (@ 0x00000002) PWM Output Delay Control Register2 */ + + struct + { + __IOM uint16_t DLYBS0 : 1; /*!< [0..0] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS1 : 1; /*!< [1..1] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS2 : 1; /*!< [2..2] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS3 : 1; /*!< [3..3] PWM Delay Generation Circuit bypass */ + uint16_t : 4; + __IOM uint16_t DLYEN0 : 1; /*!< [8..8] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYEN1 : 1; /*!< [9..9] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYEN2 : 1; /*!< [10..10] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYEN3 : 1; /*!< [11..11] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYDENB0 : 1; /*!< [12..12] PWM Delay Generation Circuit Disenable for GTIOCB */ + uint16_t : 3; + } GTDLYCR2_b; + }; + __IM uint16_t RESERVED[10]; + __IOM R_GPT_ODC_GTDLYR_Type GTDLYR[4]; /*!< (@ 0x00000018) PWM DELAY RISING */ + __IOM R_GPT_ODC_GTDLYR_Type GTDLYF[4]; /*!< (@ 0x00000028) PWM DELAY FALLING */ +} R_GPT_ODC_Type; /*!< Size = 56 (0x38) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Output Phase Switching for GPT (R_GPT_OPS) + */ + +typedef struct /*!< (@ 0x40323F00) R_GPT_OPS Structure */ +{ + union + { + __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ + + struct + { + __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + uint32_t : 1; + __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ + uint32_t : 7; + __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the + * input phase from the software settings and external input. */ + __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ + __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ + __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ + __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ + __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ + uint32_t : 2; + __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ + __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ + uint32_t : 2; + __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter + * sampling clock setting of the external input. */ + } OPSCR_b; + }; +} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ + +typedef struct /*!< (@ 0x40212000) R_GPT_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; + }; + __IM uint32_t RESERVED[15]; + + union + { + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ + + struct + { + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ + + struct + { + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; + }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ + union + { + __IOM uint8_t IRQCRa[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCRa_b[16]; + }; + + union + { + __IM uint8_t NMICR; /*!< (@ 0x00000010) NMI Pin Interrupt Control Register */ + + struct + { + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint8_t IRQCRb[16]; /*!< (@ 0x00000014) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCRb_b[16]; + }; + __IM uint32_t RESERVED2[7]; + + union + { + __IOM uint32_t INTSELR[32]; /*!< (@ 0x00000040) Interrupt request select Register */ + + struct + { + __IOM uint32_t IS0 : 1; /*!< [0..0] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS1 : 1; /*!< [1..1] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS2 : 1; /*!< [2..2] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS3 : 1; /*!< [3..3] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS4 : 1; /*!< [4..4] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS5 : 1; /*!< [5..5] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS6 : 1; /*!< [6..6] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS7 : 1; /*!< [7..7] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS8 : 1; /*!< [8..8] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS9 : 1; /*!< [9..9] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS10 : 1; /*!< [10..10] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS11 : 1; /*!< [11..11] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS12 : 1; /*!< [12..12] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS13 : 1; /*!< [13..13] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS14 : 1; /*!< [14..14] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS15 : 1; /*!< [15..15] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS16 : 1; /*!< [16..16] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS17 : 1; /*!< [17..17] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS18 : 1; /*!< [18..18] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS19 : 1; /*!< [19..19] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS20 : 1; /*!< [20..20] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS21 : 1; /*!< [21..21] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS22 : 1; /*!< [22..22] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS23 : 1; /*!< [23..23] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS24 : 1; /*!< [24..24] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS25 : 1; /*!< [25..25] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS26 : 1; /*!< [26..26] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS27 : 1; /*!< [27..27] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS28 : 1; /*!< [28..28] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS29 : 1; /*!< [29..29] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS30 : 1; /*!< [30..30] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS31 : 1; /*!< [31..31] Selects which CPU receives interrupt requests */ + } INTSELR_b[32]; + }; + __IM uint32_t RESERVED3[6160]; + + union + { + __IOM uint32_t NMIER; /*!< (@ 0x00006100) Non-Maskable Interrupt Enable Register */ + + struct + { + __IOM uint32_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint32_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint32_t PVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint32_t PVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t SOSTEN : 1; /*!< [5..5] Sub Oscillation Stop Detection Interrupt Enable */ + __IOM uint32_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint32_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + uint32_t : 4; + __IOM uint32_t BUSEN : 1; /*!< [12..12] BUS error Interrupt Enable */ + __IOM uint32_t CMEN : 1; /*!< [13..13] Common Memory error Interrupt Enable */ + __IOM uint32_t LMEN : 1; /*!< [14..14] Local Memory Error Interrupt Enable */ + __IOM uint32_t LUEN : 1; /*!< [15..15] LockUp Interrupt Enable */ + __IOM uint32_t FPUFLTEN : 1; /*!< [16..16] FPU FAULT Interrupt Enable */ + __IOM uint32_t MRCRDEN : 1; /*!< [17..17] MRAM MRC read Error Interrupt Enable */ + __IOM uint32_t MRERDEN : 1; /*!< [18..18] MRAM MRE read Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t IPCEN : 1; /*!< [20..20] IPC NMI CPU mutual Interrupt Enable */ + uint32_t : 11; + } NMIER_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IOM uint32_t NMICLR; /*!< (@ 0x00006110) Non-Maskable Interrupt Status Clear Register */ + + struct + { + __IOM uint32_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __IOM uint32_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __IOM uint32_t PVD1CLR : 1; /*!< [2..2] PVD1 Clear */ + __IOM uint32_t PVD2CLR : 1; /*!< [3..3] PVD2 Clear */ + uint32_t : 1; + __IOM uint32_t SOSTCLR : 1; /*!< [5..5] Sub OST Clear */ + __IOM uint32_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __IOM uint32_t NMICLR : 1; /*!< [7..7] NMI Clear */ + uint32_t : 4; + __IOM uint32_t BUSCLR : 1; /*!< [12..12] Bus Clear */ + __IOM uint32_t CMCLR : 1; /*!< [13..13] CM Clear */ + __IOM uint32_t LMCLR : 1; /*!< [14..14] LM Clear */ + __IOM uint32_t LUCLR : 1; /*!< [15..15] LU Clear */ + __IOM uint32_t FPUFLTCLR : 1; /*!< [16..16] FPU FAULT Clear */ + __IOM uint32_t MRCRDCLR : 1; /*!< [17..17] MRAM MRC read Error Interrupt Clear */ + __IOM uint32_t MRERDCLR : 1; /*!< [18..18] MRAM MRE read Error Interrupt Clear */ + uint32_t : 1; + __IOM uint32_t IPCCLR : 1; /*!< [20..20] IPC NMI CPU mutual Interrupt Clear */ + uint32_t : 11; + } NMICLR_b; + }; + __IM uint32_t RESERVED5[3]; + + union + { + __IM uint32_t NMISR; /*!< (@ 0x00006120) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint32_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint32_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint32_t PVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint32_t PVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + uint32_t : 1; + __IM uint32_t SOSTST : 1; /*!< [5..5] Sub Oscillation Stop Detection Interrupt Status Flag */ + __IM uint32_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint32_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + uint32_t : 4; + __IM uint32_t BUSST : 1; /*!< [12..12] BUS error Interrupt Status Flag */ + __IM uint32_t CMST : 1; /*!< [13..13] Common Memory error Interrupt Status Flag */ + __IM uint32_t LMST : 1; /*!< [14..14] Local Memory Error Interrupt Status Flag */ + __IM uint32_t LUST : 1; /*!< [15..15] LockUp Interrupt Status Flag */ + __IM uint32_t FPUFLTST : 1; /*!< [16..16] FPU FAULT Interrupt Status Flag */ + __IM uint32_t MRCRDST : 1; /*!< [17..17] MRAM MRC read Error Interrupt Status Flag */ + __IM uint32_t MRERDST : 1; /*!< [18..18] MRAM MRE read Error Interrupt Status Flag */ + uint32_t : 1; + __IM uint32_t IPCST : 1; /*!< [20..20] IPC NMI CPU mutual Interrupt Status Flag */ + uint32_t : 11; + } NMISR_b; + }; + __IM uint32_t RESERVED6[31]; + + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000061A0) Wake Up Interrupt Enable Register 0 */ + + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ0 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ1 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ2 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ3 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ4 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ5 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ6 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ7 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ8 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ9 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ10 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ11 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ12 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ13 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ14 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ15 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t WUPEN0 : 1; /*!< [16..16] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 0 */ + __IOM uint32_t WUPEN1 : 1; /*!< [17..17] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 1 */ + __IOM uint32_t WUPEN2 : 1; /*!< [18..18] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 2 */ + __IOM uint32_t WUPEN3 : 1; /*!< [19..19] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 3 */ + __IOM uint32_t WUPEN4 : 1; /*!< [20..20] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 4 */ + __IOM uint32_t WUPEN5 : 1; /*!< [21..21] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 5 */ + __IOM uint32_t WUPEN6 : 1; /*!< [22..22] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 6 */ + __IOM uint32_t WUPEN7 : 1; /*!< [23..23] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 7 */ + __IOM uint32_t WUPEN8 : 1; /*!< [24..24] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 8 */ + __IOM uint32_t WUPEN9 : 1; /*!< [25..25] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 9 */ + __IOM uint32_t WUPEN10 : 1; /*!< [26..26] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 10 */ + __IOM uint32_t WUPEN11 : 1; /*!< [27..27] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 11 */ + __IOM uint32_t WUPEN12 : 1; /*!< [28..28] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 12 */ + __IOM uint32_t WUPEN13 : 1; /*!< [29..29] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 13 */ + __IOM uint32_t WUPEN14 : 1; /*!< [30..30] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 14 */ + __IOM uint32_t WUPEN15 : 1; /*!< [31..31] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 15 */ + } WUPEN_b; + }; + + union + { + __IOM uint32_t WUPEN1; /*!< (@ 0x000061A4) Wake Up Interrupt Enable Register 1 */ + + struct + { + __IOM uint32_t WUPEN16 : 1; /*!< [0..0] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 16 */ + __IOM uint32_t WUPEN17 : 1; /*!< [1..1] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 17 */ + __IOM uint32_t WUPEN18 : 1; /*!< [2..2] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 18 */ + __IOM uint32_t WUPEN19 : 1; /*!< [3..3] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 19 */ + __IOM uint32_t WUPEN20 : 1; /*!< [4..4] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 20 */ + __IOM uint32_t WUPEN21 : 1; /*!< [5..5] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 21 */ + __IOM uint32_t WUPEN22 : 1; /*!< [6..6] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 22 */ + __IOM uint32_t WUPEN23 : 1; /*!< [7..7] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 23 */ + __IOM uint32_t WUPEN24 : 1; /*!< [8..8] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 24 */ + __IOM uint32_t WUPEN25 : 1; /*!< [9..9] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 25 */ + __IOM uint32_t WUPEN26 : 1; /*!< [10..10] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 26 */ + __IOM uint32_t WUPEN27 : 1; /*!< [11..11] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 27 */ + __IOM uint32_t WUPEN28 : 1; /*!< [12..12] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 28 */ + __IOM uint32_t WUPEN29 : 1; /*!< [13..13] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 29 */ + __IOM uint32_t WUPEN30 : 1; /*!< [14..14] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 30 */ + __IOM uint32_t WUPEN31 : 1; /*!< [15..15] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 31 */ + __IOM uint32_t IRQWUPEN16 : 1; /*!< [16..16] IRQ16 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN17 : 1; /*!< [17..17] IRQ17 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN18 : 1; /*!< [18..18] IRQ18 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN19 : 1; /*!< [19..19] IRQ19 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN20 : 1; /*!< [20..20] IRQ20 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN21 : 1; /*!< [21..21] IRQ21 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN22 : 1; /*!< [22..22] IRQ22 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN23 : 1; /*!< [23..23] IRQ23 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN24 : 1; /*!< [24..24] IRQ24 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN25 : 1; /*!< [25..25] IRQ25 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN26 : 1; /*!< [26..26] IRQ26 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN27 : 1; /*!< [27..27] IRQ27 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN28 : 1; /*!< [28..28] IRQ28 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN29 : 1; /*!< [29..29] IRQ29 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN30 : 1; /*!< [30..30] IRQ30 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN31 : 1; /*!< [31..31] IRQ31 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + } WUPEN1_b; + }; + __IM uint32_t RESERVED7[26]; + + union + { + __IOM uint32_t DSLPWUPIRQEN[3]; /*!< (@ 0x00006210) Deep Sleep Wake Up IRQ Enable Register */ + + struct + { + __IOM uint32_t IRQ0 : 1; /*!< [0..0] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ1 : 1; /*!< [1..1] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ2 : 1; /*!< [2..2] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ3 : 1; /*!< [3..3] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ4 : 1; /*!< [4..4] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ5 : 1; /*!< [5..5] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ6 : 1; /*!< [6..6] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ7 : 1; /*!< [7..7] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ8 : 1; /*!< [8..8] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ9 : 1; /*!< [9..9] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ10 : 1; /*!< [10..10] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ11 : 1; /*!< [11..11] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ12 : 1; /*!< [12..12] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ13 : 1; /*!< [13..13] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ14 : 1; /*!< [14..14] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ15 : 1; /*!< [15..15] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ16 : 1; /*!< [16..16] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ17 : 1; /*!< [17..17] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ18 : 1; /*!< [18..18] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ19 : 1; /*!< [19..19] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ20 : 1; /*!< [20..20] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ21 : 1; /*!< [21..21] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ22 : 1; /*!< [22..22] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ23 : 1; /*!< [23..23] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ24 : 1; /*!< [24..24] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ25 : 1; /*!< [25..25] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ26 : 1; /*!< [26..26] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ27 : 1; /*!< [27..27] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ28 : 1; /*!< [28..28] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ29 : 1; /*!< [29..29] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ30 : 1; /*!< [30..30] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ31 : 1; /*!< [31..31] IRQ Deep Sleep Returns Enable bit */ + } DSLPWUPIRQEN_b[3]; + }; + __IM uint32_t RESERVED8[25]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00006280) DMAC Event Link Setting Registers */ + + struct + { + __IOM uint32_t DELS : 10; /*!< [9..0] DMAC Event Link Select */ + uint32_t : 6; + __IOM uint32_t IR : 1; /*!< [16..16] DMAC Activation Request Status Flag */ + uint32_t : 15; + } DELSR_b[8]; + }; + __IM uint32_t RESERVED9[24]; + + union + { + __IOM uint32_t IELSR[96]; /*!< (@ 0x00006300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 10; /*!< [9..0] ICU Event Link Select */ + uint32_t : 6; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; + }; +} R_ICU_Type; /*!< Size = 25728 (0x6480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ + +typedef struct /*!< (@ 0x4025E000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40202200) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t IWDTCR; /*!< (@ 0x00000002) IWDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } IWDTCR_b; + }; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; + + union + { + __IOM uint8_t IWDTRCR; /*!< (@ 0x00000006) IWDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } IWDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t IWDTCSTPR; /*!< (@ 0x00000008) IWDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } IWDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_IWDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_I3C0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I3C Bus Interface (R_I3C0) + */ + +typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure */ +{ + union + { + __IOM uint32_t PRTS; /*!< (@ 0x00000000) Protocol Selection Register */ + + struct + { + __IOM uint32_t PRTMD : 1; /*!< [0..0] Protocol Mode */ + uint32_t : 31; + } PRTS_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t CECTL; /*!< (@ 0x00000010) Clock Enable Control Resisters */ + + struct + { + __IOM uint32_t CLKE : 1; /*!< [0..0] Clock Enable */ + uint32_t : 31; + } CECTL_b; + }; + + union + { + __IOM uint32_t BCTL; /*!< (@ 0x00000014) Bus Control Register */ + + struct + { + __IOM uint32_t INCBA : 1; /*!< [0..0] Include I3C Broadcast Address */ + uint32_t : 6; + __IOM uint32_t BMDS : 1; /*!< [7..7] Bus Mode Selection */ + __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control */ + uint32_t : 20; + __IOM uint32_t ABT : 1; /*!< [29..29] Abort */ + __IOM uint32_t RSM : 1; /*!< [30..30] Resume */ + __IOM uint32_t BUSE : 1; /*!< [31..31] Bus Enable */ + } BCTL_b; + }; + + union + { + __IOM uint32_t MSDVAD; /*!< (@ 0x00000018) Master Device Address Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t MDYAD : 7; /*!< [22..16] Master Dynamic Address */ + uint32_t : 8; + __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid */ + } MSDVAD_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ + + struct + { + __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ + __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ + __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ + __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ + __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ + __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ + __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ + uint32_t : 2; + __IOM uint32_t HCMDQRST : 1; /*!< [9..9] High Priority Command Queue Software Reset */ + __IOM uint32_t HRSPQRST : 1; /*!< [10..10] High Priority Response Queue Software Rese */ + __IOM uint32_t HTDBRST : 1; /*!< [11..11] High Priority Tx Data Buffer Software Reset */ + __IOM uint32_t HRDBRST : 1; /*!< [12..12] High Priority Rx Data Buffer Software Reset */ + uint32_t : 3; + __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ + uint32_t : 15; + } RSTCTL_b; + }; + + union + { + __IOM uint32_t PRSST; /*!< (@ 0x00000024) Present State Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t CRMS : 1; /*!< [2..2] Current Master */ + uint32_t : 1; + __IM uint32_t TRMD : 1; /*!< [4..4] Transmit/Receive Mode */ + uint32_t : 2; + __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect */ + uint32_t : 24; + } PRSST_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t INST; /*!< (@ 0x00000030) Internal Status Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEF : 1; /*!< [10..10] Internal Error Flag */ + uint32_t : 21; + } INST_b; + }; + + union + { + __IOM uint32_t INSTE; /*!< (@ 0x00000034) Internal Status Enable Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEE : 1; /*!< [10..10] Internal Error Enable */ + uint32_t : 21; + } INSTE_b; + }; + + union + { + __IOM uint32_t INIE; /*!< (@ 0x00000038) Internal Interrupt Enable Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEIE : 1; /*!< [10..10] Internal Error Interrupt Enable */ + uint32_t : 21; + } INIE_b; + }; + + union + { + __IOM uint32_t INSTFC; /*!< (@ 0x0000003C) Internal Status Force Register */ + + struct + { + uint32_t : 10; + __OM uint32_t INEFC : 1; /*!< [10..10] Internal Error Force */ + uint32_t : 21; + } INSTFC_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IM uint32_t DVCT; /*!< (@ 0x00000044) Device Characteristic Table Register */ + + struct + { + uint32_t : 19; + __IM uint32_t IDX : 5; /*!< [23..19] DCT Table Index */ + uint32_t : 8; + } DVCT_b; + }; + __IM uint32_t RESERVED4[4]; + + union + { + __IOM uint32_t IBINCTL; /*!< (@ 0x00000058) IBI Notify Control Register */ + + struct + { + __IOM uint32_t NRHJCTL : 1; /*!< [0..0] Notify Rejected Hot-Join Control */ + __IOM uint32_t NRMRCTL : 1; /*!< [1..1] Notify Rejected Master Request Control */ + uint32_t : 1; + __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control */ + uint32_t : 28; + } IBINCTL_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t BFCTL; /*!< (@ 0x00000060) Bus Function Control Register */ + + struct + { + __IOM uint32_t MALE : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable */ + __IOM uint32_t NALE : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint32_t SALE : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable */ + uint32_t : 5; + __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable */ + uint32_t : 3; + __IOM uint32_t SMBS : 1; /*!< [12..12] SMBus/I2C Bus Selection */ + uint32_t : 1; + __IOM uint32_t FMPE : 1; /*!< [14..14] Fast-mode Plus Enable */ + __IOM uint32_t HSME : 1; /*!< [15..15] High Speed Mode Enable */ + uint32_t : 16; + } BFCTL_b; + }; + + union + { + __IOM uint32_t SVCTL; /*!< (@ 0x00000064) Slave Control Register */ + + struct + { + __IOM uint32_t GCAE : 1; /*!< [0..0] General Call Address Enable */ + uint32_t : 4; + __IOM uint32_t HSMCE : 1; /*!< [5..5] Hs-mode Master Code Enable */ + __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ + uint32_t : 8; + __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ + __IOM uint32_t SVAEn : 3; /*!< [18..16] Slave Address Enable */ + uint32_t : 13; + } SVCTL_b; + }; + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t REFCKCTL; /*!< (@ 0x00000070) Reference Clock Control Register */ + + struct + { + __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection */ + uint32_t : 29; + } REFCKCTL_b; + }; + + union + { + __IOM uint32_t STDBR; /*!< (@ 0x00000074) Standard Bit Rate Register */ + + struct + { + __IOM uint32_t SBRLO : 8; /*!< [7..0] Count value of the Low-level period of SCL clock */ + __IOM uint32_t SBRHO : 8; /*!< [15..8] Count value of the High-level period of SCL clock */ + __IOM uint32_t SBRLP : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull */ + uint32_t : 2; + __IOM uint32_t SBRHP : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull */ + uint32_t : 1; + __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain */ + } STDBR_b; + }; + + union + { + __IOM uint32_t EXTBR; /*!< (@ 0x00000078) Extended Bit Rate Register */ + + struct + { + __IOM uint32_t EBRLO : 8; /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain */ + __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ + __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ + uint32_t : 2; + __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate High-Level Period Push-Pull */ + uint32_t : 2; + } EXTBR_b; + }; + + union + { + __IOM uint32_t BFRECDT; /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register */ + + struct + { + __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle */ + uint32_t : 23; + } BFRECDT_b; + }; + + union + { + __IOM uint32_t BAVLCDT; /*!< (@ 0x00000080) Bus Available Condition Detection Time Register */ + + struct + { + __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle */ + uint32_t : 23; + } BAVLCDT_b; + }; + + union + { + __IOM uint32_t BIDLCDT; /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register */ + + struct + { + __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle */ + uint32_t : 14; + } BIDLCDT_b; + }; + + union + { + __IOM uint32_t OUTCTL; /*!< (@ 0x00000088) Output Control Register */ + + struct + { + __IOM uint32_t SDOC : 1; /*!< [0..0] SDA Output Control */ + __IOM uint32_t SCOC : 1; /*!< [1..1] SCL Output Control */ + __OM uint32_t SOCWP : 1; /*!< [2..2] SCL/SDA Output Control Write Protect */ + uint32_t : 1; + __IOM uint32_t EXCYC : 1; /*!< [4..4] Extra SCL Clock Cycle Output */ + uint32_t : 3; + __IOM uint32_t SDOD : 3; /*!< [10..8] SDA Output Delay */ + uint32_t : 4; + __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection */ + uint32_t : 16; + } OUTCTL_b; + }; + + union + { + __IOM uint32_t INCTL; /*!< (@ 0x0000008C) Input Control Register */ + + struct + { + __IOM uint32_t DNFS : 4; /*!< [3..0] Digital Noise Filter Stage Selection */ + __IOM uint32_t DNFE : 1; /*!< [4..4] Digital Noise Filter Circuit Enable */ + uint32_t : 27; + } INCTL_b; + }; + + union + { + __IOM uint32_t TMOCTL; /*!< (@ 0x00000090) Timeout Control Register */ + + struct + { + __IOM uint32_t TODTS : 2; /*!< [1..0] Timeout Detection Time Selection */ + uint32_t : 2; + __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control */ + __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control */ + __IOM uint32_t TOMDS : 2; /*!< [7..6] Timeout Operation Mode Selection */ + uint32_t : 24; + } TMOCTL_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t WUCTL; /*!< (@ 0x00000098) Wake Up Unit Control Register */ + + struct + { + __IOM uint32_t WUACKS : 1; /*!< [0..0] Wake-Up Acknowledge Selection */ + uint32_t : 3; + __IOM uint32_t WUANFS : 1; /*!< [4..4] Wake-Up Analog Noise Filter Selection */ + uint32_t : 1; + __IOM uint32_t WUFSYNE : 1; /*!< [6..6] Wake-Up function PCLKA Synchronous Enable */ + __IOM uint32_t WUFE : 1; /*!< [7..7] Wake-Up function Enable. */ + uint32_t : 24; + } WUCTL_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t ACKCTL; /*!< (@ 0x000000A0) Acknowledge Control Register */ + + struct + { + __IM uint32_t ACKR : 1; /*!< [0..0] Acknowledge Reception */ + __IOM uint32_t ACKT : 1; /*!< [1..1] Acknowledge Transmission */ + __OM uint32_t ACKTWP : 1; /*!< [2..2] ACKT Write Protect */ + uint32_t : 29; + } ACKCTL_b; + }; + + union + { + __IOM uint32_t SCSTRCTL; /*!< (@ 0x000000A4) SCL Stretch Control Register */ + + struct + { + __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable */ + __IOM uint32_t RWE : 1; /*!< [1..1] Receive Wait Enable */ + uint32_t : 30; + } SCSTRCTL_b; + }; + __IM uint32_t RESERVED9[2]; + + union + { + __IOM uint32_t SCSTLCTL; /*!< (@ 0x000000B0) SCL Stalling Control Register */ + + struct + { + __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle */ + uint32_t : 12; + __IOM uint32_t AAPE : 1; /*!< [28..28] Assigend Address Phase Enable */ + __IOM uint32_t TRAPE : 1; /*!< [29..29] Transition Phase Enable */ + __IOM uint32_t PARPE : 1; /*!< [30..30] Parity Phase Enable */ + __IOM uint32_t ACKPE : 1; /*!< [31..31] ACK phase Enable */ + } SCSTLCTL_b; + }; + __IM uint32_t RESERVED10[3]; + + union + { + __IOM uint32_t SVTDLG0; /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0 */ + + struct + { + uint32_t : 16; + __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ + } SVTDLG0_b; + }; + __IM uint32_t RESERVED11[23]; + + union + { + __IOM uint32_t STCTL; /*!< (@ 0x00000120) Synchronous Timing Control Register */ + + struct + { + __IOM uint32_t STOE : 1; /*!< [0..0] Synchronous Timing output Enable */ + uint32_t : 31; + } STCTL_b; + }; + + union + { + __IOM uint32_t ATCTL; /*!< (@ 0x00000124) Asynchronous Timing Control Register */ + + struct + { + __IOM uint32_t ATTRGS : 1; /*!< [0..0] Asynchronous Timing Trigger Select */ + __IOM uint32_t MREFOE : 1; /*!< [1..1] MREF Output Enable (Capture Event / Counter Overflow) */ + __IOM uint32_t AMEOE : 1; /*!< [2..2] Additional Master-initiated bus Event Output Enable */ + uint32_t : 5; + __IOM uint32_t CDIV : 8; /*!< [15..8] TCLK Counter Divide Setting */ + uint32_t : 16; + } ATCTL_b; + }; + + union + { + __IOM uint32_t ATTRG; /*!< (@ 0x00000128) Asynchronous Timing Trigger Register */ + + struct + { + __OM uint32_t ATSTRG : 1; /*!< [0..0] Asynchronous Timing Software Trigger */ + uint32_t : 31; + } ATTRG_b; + }; + + union + { + __IOM uint32_t ATCCNTE; /*!< (@ 0x0000012C) Asynchronous Timing Contorol Counter enable Register */ + + struct + { + __IOM uint32_t ATCE : 1; /*!< [0..0] Asynchronous Timing Counter Enable for MREF, MC2, SC1, + * SC2. */ + uint32_t : 31; + } ATCCNTE_b; + }; + __IM uint32_t RESERVED12[4]; + + union + { + __IOM uint32_t CNDCTL; /*!< (@ 0x00000140) Condition Control Register */ + + struct + { + __IOM uint32_t STCND : 1; /*!< [0..0] START (S) Condition Issuance */ + __IOM uint32_t SRCND : 1; /*!< [1..1] Repeated START (Sr) Condition Issuance */ + __IOM uint32_t SPCND : 1; /*!< [2..2] STOP (P) Condition Issuance */ + uint32_t : 29; + } CNDCTL_b; + }; + __IM uint32_t RESERVED13[3]; + __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ + __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ + __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ + __IM uint32_t RESERVED14[8]; + __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ + __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ + + union + { + __OM uint32_t HCMDQP; /*!< (@ 0x00000184) High Priority Command Queue Port Register */ + + struct + { + __OM uint32_t HCMDQP : 32; /*!< [31..0] High Priority Command Queue Port */ + } HCMDQP_b; + }; + + union + { + __IM uint32_t HRSPQP; /*!< (@ 0x00000188) High Priority Response Queue Port Register */ + + struct + { + __IM uint32_t HRSPQP : 32; /*!< [31..0] High Priority Response Queue Port */ + } HRSPQP_b; + }; + + union + { + __IOM uint32_t HTDTBP; /*!< (@ 0x0000018C) High Priority Transfer Data Buffer Port Register */ + + struct + { + __IOM uint32_t HTDTBP : 32; /*!< [31..0] High Priority Transfer Data Buffer Port */ + } HTDTBP_b; + }; + + union + { + __IOM uint32_t NQTHCTL; /*!< (@ 0x00000190) Normal Queue Threshold Control Register */ + + struct + { + __IOM uint32_t CMDQTH : 8; /*!< [7..0] Normal Command Ready Queue Threshold */ + __IOM uint32_t RSPQTH : 8; /*!< [15..8] Normal Response Queue Threshold */ + __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size */ + __IOM uint32_t IBIQTH : 8; /*!< [31..24] Normal IBI Queue Threshold */ + } NQTHCTL_b; + }; + + union + { + __IOM uint32_t NTBTHCTL0; /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control + * Register 0 */ + + struct + { + __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold */ + uint32_t : 5; + __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold */ + uint32_t : 5; + } NTBTHCTL0_b; + }; + __IM uint32_t RESERVED15[10]; + + union + { + __IOM uint32_t NRQTHCTL; /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control + * Register */ + + struct + { + __IOM uint32_t RSQTH : 8; /*!< [7..0] Normal Receive Status Queue Threshold */ + uint32_t : 24; + } NRQTHCTL_b; + }; + + union + { + __IOM uint32_t HQTHCTL; /*!< (@ 0x000001C4) High Priority Queue Threshold Control Register */ + + struct + { + __IOM uint32_t CMDQTH : 8; /*!< [7..0] High Priority Command Queue Threshold */ + __IOM uint32_t RSPQTH : 8; /*!< [15..8] High Priority Response Queue Threshold */ + uint32_t : 16; + } HQTHCTL_b; + }; + + union + { + __IOM uint32_t HTBTHCTL; /*!< (@ 0x000001C8) High Priority Transfer Data Buffer Threshold + * Control Register */ + + struct + { + __IOM uint32_t TXDBTH : 3; /*!< [2..0] High Priority Tx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t RXDBTH : 3; /*!< [10..8] High Priority Rx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t TXSTTH : 3; /*!< [18..16] High Priority Tx Start Threshold */ + uint32_t : 5; + __IOM uint32_t RXSTTH : 3; /*!< [26..24] High Priority Rx Start Threshold */ + uint32_t : 5; + } HTBTHCTL_b; + }; + __IM uint32_t RESERVED16; + + union + { + __IOM uint32_t BST; /*!< (@ 0x000001D0) Bus Status Register */ + + struct + { + __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag */ + __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag */ + __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag */ + uint32_t : 1; + __IOM uint32_t NACKDF : 1; /*!< [4..4] NACK Detection Flag */ + uint32_t : 3; + __IOM uint32_t TENDF : 1; /*!< [8..8] Transmit End Flag */ + uint32_t : 7; + __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ + uint32_t : 3; + __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ + uint32_t : 3; + __IOM uint32_t WUCNDDF : 1; /*!< [24..24] Wake-Up Condition Detection Flag */ + uint32_t : 7; + } BST_b; + }; + + union + { + __IOM uint32_t BSTE; /*!< (@ 0x000001D4) Bus Status Enable Register */ + + struct + { + __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable */ + __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable */ + __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable */ + uint32_t : 1; + __IOM uint32_t NACKDE : 1; /*!< [4..4] NACK Detection Enable */ + uint32_t : 3; + __IOM uint32_t TENDE : 1; /*!< [8..8] Transmit End Enable */ + uint32_t : 7; + __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ + uint32_t : 3; + __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ + uint32_t : 3; + __IOM uint32_t WUCNDDE : 1; /*!< [24..24] Wake-up Condition Detection Enable */ + uint32_t : 7; + } BSTE_b; + }; + + union + { + __IOM uint32_t BIE; /*!< (@ 0x000001D8) Bus Interrupt Enable Register */ + + struct + { + __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable */ + __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable */ + __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t NACKDIE : 1; /*!< [4..4] NACK Detection Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TENDIE : 1; /*!< [8..8] Transmit End Interrupt Enable */ + uint32_t : 7; + __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t WUCNDDIE : 1; /*!< [24..24] Wake-Up Condition Detection Interrupt Enable */ + uint32_t : 7; + } BIE_b; + }; + + union + { + __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ + + struct + { + __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ + __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ + __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ + uint32_t : 1; + __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ + uint32_t : 3; + __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ + uint32_t : 7; + __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ + uint32_t : 3; + __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ + uint32_t : 3; + __IOM uint32_t WUCNDDFC : 1; /*!< [24..24] Wake-Up Condition Detection Force */ + uint32_t : 7; + } BSTFC_b; + }; + + union + { + __IOM uint32_t NTST; /*!< (@ 0x000001E0) Normal Transfer Status Register */ + + struct + { + __IOM uint32_t TDBEF0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0 */ + __IOM uint32_t RDBFF0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0 */ + __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag */ + __IOM uint32_t CMDQEF : 1; /*!< [3..3] Normal Command Queue Empty Flag */ + __IOM uint32_t RSPQFF : 1; /*!< [4..4] Normal Response Queue Full Flag */ + __IOM uint32_t TABTF : 1; /*!< [5..5] Normal Transfer Abort Flag */ + uint32_t : 3; + __IOM uint32_t TEF : 1; /*!< [9..9] Normal Transfer Error Flag */ + uint32_t : 10; + __IOM uint32_t RSQFF : 1; /*!< [20..20] Normal Receive Status Queue Full Flag */ + uint32_t : 11; + } NTST_b; + }; + + union + { + __IOM uint32_t NTSTE; /*!< (@ 0x000001E4) Normal Transfer Status Enable Register */ + + struct + { + __IOM uint32_t TDBEE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0 */ + __IOM uint32_t RDBFE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0 */ + __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable */ + __IOM uint32_t CMDQEE : 1; /*!< [3..3] Normal Command Queue Empty Enable */ + __IOM uint32_t RSPQFE : 1; /*!< [4..4] Normal Response Queue Full Enable */ + __IOM uint32_t TABTE : 1; /*!< [5..5] Normal Transfer Abort Enable */ + uint32_t : 3; + __IOM uint32_t TEE : 1; /*!< [9..9] Normal Transfer Error Enable */ + uint32_t : 10; + __IOM uint32_t RSQFE : 1; /*!< [20..20] Normal Receive Status Queue Full Enable */ + uint32_t : 11; + } NTSTE_b; + }; + + union + { + __IOM uint32_t NTIE; /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register */ + + struct + { + __IOM uint32_t TDBEIE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0 */ + __IOM uint32_t RDBFIE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0 */ + __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable */ + __IOM uint32_t CMDQEIE : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable */ + __IOM uint32_t RSPQFIE : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable */ + __IOM uint32_t TABTIE : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TEIE : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable */ + uint32_t : 10; + __IOM uint32_t RSQFIE : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable */ + uint32_t : 11; + } NTIE_b; + }; + + union + { + __IOM uint32_t NTSTFC; /*!< (@ 0x000001EC) Normal Transfer Status Force Register */ + + struct + { + __OM uint32_t TDBEFC0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0 */ + __OM uint32_t RDBFFC0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0 */ + __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force */ + __OM uint32_t CMDQEFC : 1; /*!< [3..3] Normal Command Queue Empty Force */ + __OM uint32_t RSPQFFC : 1; /*!< [4..4] Normal Response Queue Full Force */ + __OM uint32_t TABTFC : 1; /*!< [5..5] Normal Transfer Abort Force */ + uint32_t : 3; + __OM uint32_t TEFC : 1; /*!< [9..9] Normal Transfer Error Force */ + uint32_t : 10; + __OM uint32_t RSQFFC : 1; /*!< [20..20] Normal Receive Status Queue Full Force */ + uint32_t : 11; + } NTSTFC_b; + }; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint32_t HTST; /*!< (@ 0x00000200) High Priority Transfer Status Register */ + + struct + { + __IOM uint32_t TDBEF : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Flag */ + __IOM uint32_t RDBFF : 1; /*!< [1..1] High Priority Rx Data Buffer Full Flag */ + uint32_t : 1; + __IOM uint32_t CMDQEF : 1; /*!< [3..3] High Priority Command Queue Empty Flag */ + __IOM uint32_t RSPQFF : 1; /*!< [4..4] High Priority Response Queue Full Flag */ + __IOM uint32_t TABTF : 1; /*!< [5..5] High Priority Transfer Abort Flag */ + uint32_t : 3; + __IOM uint32_t TEF : 1; /*!< [9..9] High Priority Transfer Error Flag */ + uint32_t : 22; + } HTST_b; + }; + + union + { + __IOM uint32_t HTSTE; /*!< (@ 0x00000204) High Priority Transfer Status Enable Register */ + + struct + { + __IOM uint32_t TDBEE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Enable */ + __IOM uint32_t RDBFE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEE : 1; /*!< [3..3] High Priority Command Queue Empty Enable */ + __IOM uint32_t RSPQFE : 1; /*!< [4..4] High Priority Response Queue Full Enable */ + __IOM uint32_t TABTE : 1; /*!< [5..5] High Priority Transfer Abort Enable */ + uint32_t : 3; + __IOM uint32_t TEE : 1; /*!< [9..9] High Priority Transfer Error Enable */ + uint32_t : 22; + } HTSTE_b; + }; + + union + { + __IOM uint32_t HTIE; /*!< (@ 0x00000208) High Priority Transfer Interrupt Enable Register */ + + struct + { + __IOM uint32_t TDBEIE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Interrupt Enable */ + __IOM uint32_t RDBFIE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEIE : 1; /*!< [3..3] High Priority Command Queue Empty Interrupt Enable */ + __IOM uint32_t RSPQFIE : 1; /*!< [4..4] High Priority Response Queue Full Interrupt Enable */ + __IOM uint32_t TABTIE : 1; /*!< [5..5] High Priority Transfer Abort Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TEIE : 1; /*!< [9..9] High Priority Transfer Error Interrupt Enable */ + uint32_t : 22; + } HTIE_b; + }; + + union + { + __IOM uint32_t HTSTFC; /*!< (@ 0x0000020C) High Priority Transfer Status Force Register */ + + struct + { + __OM uint32_t TDBEFC : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Force */ + __OM uint32_t RDBFFC : 1; /*!< [1..1] High Priority Rx Data Buffer Full Force */ + uint32_t : 1; + __OM uint32_t CMDQEFC : 1; /*!< [3..3] High Priority Command Queue Empty Force */ + __OM uint32_t RSPQFFC : 1; /*!< [4..4] High Priority Response Queue Full Force */ + __OM uint32_t TABTFC : 1; /*!< [5..5] High Priority Transfer Abort Force */ + uint32_t : 3; + __OM uint32_t TEFC : 1; /*!< [9..9] High Priority Transfer Error Force */ + uint32_t : 22; + } HTSTFC_b; + }; + + union + { + __IM uint32_t BCST; /*!< (@ 0x00000210) Bus Condition Status Register */ + + struct + { + __IM uint32_t BFREF : 1; /*!< [0..0] Bus Free Detection Flag */ + __IM uint32_t BAVLF : 1; /*!< [1..1] Bus Available Detection Flag */ + __IM uint32_t BIDLF : 1; /*!< [2..2] Bus Idle Detection Flag */ + uint32_t : 29; + } BCST_b; + }; + + union + { + __IOM uint32_t SVST; /*!< (@ 0x00000214) Slave Status Register */ + + struct + { + __IOM uint32_t GCAF : 1; /*!< [0..0] General Call Address Detection Flag */ + uint32_t : 4; + __IOM uint32_t HSMCF : 1; /*!< [5..5] Hs-mode Master Code Detection Flag */ + __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ + uint32_t : 8; + __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ + __IOM uint32_t SVAFn : 3; /*!< [18..16] Slave Address Detection Flag */ + uint32_t : 13; + } SVST_b; + }; + + union + { + __IM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Operating Status Register */ + + struct + { + __IM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ + uint32_t : 31; + } WUST_b; + }; + + union + { + __IM uint32_t MRCCPT; /*!< (@ 0x0000021C) MsyncCNT Counter Capture Register */ + + struct + { + __IM uint32_t MRCCPT : 32; /*!< [31..0] MSyncCNT Counter Capture */ + } MRCCPT_b; + }; + __IM uint32_t RESERVED18; + + union + { + __IOM uint32_t DATBAS0; /*!< (@ 0x00000224) Device Address Table Basic Register 0 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS0_b; + }; + __IM uint32_t RESERVED19; + + union + { + __IOM uint32_t DATBAS1; /*!< (@ 0x0000022C) Device Address Table Basic Register 1 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS1_b; + }; + __IM uint32_t RESERVED20; + + union + { + __IOM uint32_t DATBAS2; /*!< (@ 0x00000234) Device Address Table Basic Register 2 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS2_b; + }; + __IM uint32_t RESERVED21; + + union + { + __IOM uint32_t DATBAS3; /*!< (@ 0x0000023C) Device Address Table Basic Register 3 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS3_b; + }; + __IM uint32_t RESERVED22; + + union + { + __IOM uint32_t DATBAS4; /*!< (@ 0x00000244) Device Address Table Basic Register 4 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS4_b; + }; + __IM uint32_t RESERVED23; + + union + { + __IOM uint32_t DATBAS5; /*!< (@ 0x0000024C) Device Address Table Basic Register 5 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS5_b; + }; + __IM uint32_t RESERVED24; + + union + { + __IOM uint32_t DATBAS6; /*!< (@ 0x00000254) Device Address Table Basic Register 6 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS6_b; + }; + __IM uint32_t RESERVED25; + + union + { + __IOM uint32_t DATBAS7; /*!< (@ 0x0000025C) Device Address Table Basic Register 7 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS7_b; + }; + __IM uint32_t RESERVED26[16]; + + union + { + __IOM uint32_t EXDATBAS; /*!< (@ 0x000002A0) Extended Device Address Table Basic Register */ + + struct + { + __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address */ + uint32_t : 9; + __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count */ + __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ + } EXDATBAS_b; + }; + __IM uint32_t RESERVED27[3]; + + union + { + __IOM uint32_t SDATBAS0; /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS0_b; + }; + + union + { + __IOM uint32_t SDATBAS1; /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS1_b; + }; + + union + { + __IOM uint32_t SDATBAS2; /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS2_b; + }; + __IM uint32_t RESERVED28[5]; + + union + { + __IOM uint32_t MSDCT0; /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT0_b; + }; + + union + { + __IOM uint32_t MSDCT1; /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT1_b; + }; + + union + { + __IOM uint32_t MSDCT2; /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT2_b; + }; + + union + { + __IOM uint32_t MSDCT3; /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT3_b; + }; + + union + { + __IOM uint32_t MSDCT4; /*!< (@ 0x000002E0) Master Device Characteristic Table Register 4 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT4_b; + }; + + union + { + __IOM uint32_t MSDCT5; /*!< (@ 0x000002E4) Master Device Characteristic Table Register 5 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT5_b; + }; + + union + { + __IOM uint32_t MSDCT6; /*!< (@ 0x000002E8) Master Device Characteristic Table Register 6 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT6_b; + }; + + union + { + __IOM uint32_t MSDCT7; /*!< (@ 0x000002EC) Master Device Characteristic Table Register 7 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT7_b; + }; + __IM uint32_t RESERVED29[12]; + + union + { + __IOM uint32_t SVDCT; /*!< (@ 0x00000320) Slave Device Characteristic Table Register */ + + struct + { + __IOM uint32_t TDCR : 8; /*!< [7..0] Transfar Device Characteristic Register */ + __IOM uint32_t TBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t TBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t TBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } SVDCT_b; + }; + __IOM uint32_t SDCTPIDL; /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional + * ID Low Register */ + __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional + * ID High Register */ + __IM uint32_t RESERVED30; + + union + { + __IM uint32_t SVDVAD0; /*!< (@ 0x00000330) Slave Device Address Register 0 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD0_b; + }; + + union + { + __IM uint32_t SVDVAD1; /*!< (@ 0x00000334) Slave Device Address Register 1 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD1_b; + }; + + union + { + __IM uint32_t SVDVAD2; /*!< (@ 0x00000338) Slave Device Address Register 2 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD2_b; + }; + __IM uint32_t RESERVED31[5]; + + union + { + __IOM uint32_t CSECMD; /*!< (@ 0x00000350) CCC Slave Events Command Register */ + + struct + { + __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable */ + __IOM uint32_t MSRQE : 1; /*!< [1..1] Mastership Requests Enable */ + uint32_t : 1; + __IOM uint32_t HJEVE : 1; /*!< [3..3] Hot-Join Event Enable */ + uint32_t : 28; + } CSECMD_b; + }; + + union + { + __IOM uint32_t CEACTST; /*!< (@ 0x00000354) CCC Enter Activity State Register */ + + struct + { + __IOM uint32_t ACTST : 4; /*!< [3..0] Activity State */ + uint32_t : 28; + } CEACTST_b; + }; + + union + { + __IOM uint32_t CMWLG; /*!< (@ 0x00000358) CCC Max Write Length Register */ + + struct + { + __IOM uint32_t MWLG : 16; /*!< [15..0] Max Write Length */ + uint32_t : 16; + } CMWLG_b; + }; + + union + { + __IOM uint32_t CMRLG; /*!< (@ 0x0000035C) CCC Max Read Length Register */ + + struct + { + __IOM uint32_t MRLG : 16; /*!< [15..0] Max Read Length */ + __IOM uint32_t IBIPSZ : 8; /*!< [23..16] IBI Payload Size */ + uint32_t : 8; + } CMRLG_b; + }; + + union + { + __IM uint32_t CETSTMD; /*!< (@ 0x00000360) CCC Enter Test Mode Register */ + + struct + { + __IM uint32_t TSTMD : 8; /*!< [7..0] Test Mode */ + uint32_t : 24; + } CETSTMD_b; + }; + + union + { + __IOM uint32_t CGDVST; /*!< (@ 0x00000364) CCC Get Device Status Register */ + + struct + { + __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt */ + uint32_t : 1; + __IOM uint32_t PRTE : 1; /*!< [5..5] Protocol Error */ + __IOM uint32_t ACTMD : 2; /*!< [7..6] Slave Device's current Activity Mode */ + __IOM uint32_t VDRSV : 8; /*!< [15..8] Vendor Reserved */ + uint32_t : 16; + } CGDVST_b; + }; + + union + { + __IOM uint32_t CMDSPW; /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register */ + + struct + { + __IOM uint32_t MSWDR : 3; /*!< [2..0] Maximum Sustained Write Data Rate */ + uint32_t : 29; + } CMDSPW_b; + }; + + union + { + __IOM uint32_t CMDSPR; /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register */ + + struct + { + __IOM uint32_t MSRDR : 3; /*!< [2..0] Maximum Sustained Read Data Rate */ + __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO) */ + uint32_t : 26; + } CMDSPR_b; + }; + + union + { + __IOM uint32_t CMDSPT; /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register */ + + struct + { + __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time */ + uint32_t : 7; + __IOM uint32_t MRTE : 1; /*!< [31..31] Maximum Read Turnaround Time Enable */ + } CMDSPT_b; + }; + + union + { + __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) + * Register */ + + struct + { + __IOM uint32_t SPTSYN : 1; /*!< [0..0] Supports Sync Mode */ + __IOM uint32_t SPTASYN0 : 1; /*!< [1..1] Support Async Mode 0 */ + __IOM uint32_t SPTASYN1 : 1; /*!< [2..2] Support Async Mode 1 */ + uint32_t : 5; + __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ + __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ + uint32_t : 8; + } CETSM_b; + }; + + union + { + __IOM uint32_t CETSS; /*!< (@ 0x00000378) CCC Exchange Timing Support Information S (State) + * Register */ + + struct + { + __IOM uint32_t SYNE : 1; /*!< [0..0] Sync Mode Enabled */ + __IOM uint32_t ASYNE : 2; /*!< [2..1] Async Mode Enabled */ + uint32_t : 4; + __IOM uint32_t ICOVF : 1; /*!< [7..7] Internal Counter Overflow */ + uint32_t : 24; + } CETSS_b; + }; + + union + { + __IOM uint32_t CGHDRCAP; /*!< (@ 0x0000037C) CCC Get HDR Capability Register */ + + struct + { + __IOM uint32_t DDREN : 1; /*!< [0..0] HDR-DDR Operation Enable */ + __IOM uint32_t TSPEN : 1; /*!< [1..1] HDR-TSP Operation Enable */ + __IOM uint32_t TSLEN : 1; /*!< [2..2] HDR-TSL Operation Enable */ + uint32_t : 29; + } CGHDRCAP_b; + }; + + union + { + __IOM uint32_t BITCNT; /*!< (@ 0x00000380) Bit Count Register */ + + struct + { + __IOM uint32_t BCNT : 5; /*!< [4..0] Bit Counter */ + uint32_t : 2; + __OM uint32_t BCNTWP : 1; /*!< [7..7] BCNT Write Protect */ + uint32_t : 24; + } BITCNT_b; + }; + __IM uint32_t RESERVED32[4]; + + union + { + __IM uint32_t NQSTLV; /*!< (@ 0x00000394) Normal Queue Status Level Register */ + + struct + { + __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level */ + __IM uint32_t RSPQLV : 8; /*!< [15..8] Normal Response Queue Level */ + __IM uint32_t IBIQLV : 8; /*!< [23..16] Normal IBI Queue Level */ + __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count */ + uint32_t : 3; + } NQSTLV_b; + }; + + union + { + __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register 0 */ + + struct + { + __IM uint32_t TDBFLV : 8; /*!< [7..0] Normal Transmit Data Buffer Free Level */ + __IM uint32_t RDBLV : 8; /*!< [15..8] Normal Receive Data Buffer Level */ + uint32_t : 16; + } NDBSTLV0_b; + }; + __IM uint32_t RESERVED33[9]; + + union + { + __IM uint32_t NRSQSTLV; /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register */ + + struct + { + __IM uint32_t RSQLV : 8; /*!< [7..0] Normal Receive Status Queue Level */ + uint32_t : 24; + } NRSQSTLV_b; + }; + + union + { + __IM uint32_t HQSTLV; /*!< (@ 0x000003C4) High Priority Queue Status Level Register */ + + struct + { + __IM uint32_t CMDQLV : 8; /*!< [7..0] High Priority Command Queue Level */ + __IM uint32_t RSPQLV : 8; /*!< [15..8] High Priority Response Queue Level */ + uint32_t : 16; + } HQSTLV_b; + }; + + union + { + __IM uint32_t HDBSTLV; /*!< (@ 0x000003C8) High Priority Data Buffer Status Level Register */ + + struct + { + __IM uint32_t TDBFLV : 8; /*!< [7..0] High Priority Tx Data Buffer Free Level */ + __IM uint32_t RDBLV : 8; /*!< [15..8] High Priority Rx Data Buffer Level */ + uint32_t : 16; + } HDBSTLV_b; + }; + + union + { + __IM uint32_t PRSTDBG; /*!< (@ 0x000003CC) Present State Debug Register */ + + struct + { + __IM uint32_t SCILV : 1; /*!< [0..0] SCL Line Signal Level */ + __IM uint32_t SDILV : 1; /*!< [1..1] SDA Line Signal Level */ + __IM uint32_t SCOLV : 1; /*!< [2..2] SCL Output Level */ + __IM uint32_t SDOLV : 1; /*!< [3..3] SDA Output Level */ + uint32_t : 28; + } PRSTDBG_b; + }; + + union + { + __IM uint32_t MSERRCNT; /*!< (@ 0x000003D0) Master Error Counters Register */ + + struct + { + __IM uint32_t M2ECNT : 8; /*!< [7..0] M2 Error Counter */ + uint32_t : 24; + } MSERRCNT_b; + }; + __IM uint32_t RESERVED34[3]; + + union + { + __IM uint32_t SC1CPT; /*!< (@ 0x000003E0) SC1 Capture monitor Register */ + + struct + { + __IM uint32_t SC1C : 16; /*!< [15..0] SC1 Capture */ + uint32_t : 16; + } SC1CPT_b; + }; + + union + { + __IM uint32_t SC2CPT; /*!< (@ 0x000003E4) SC2 Capture monitor Register */ + + struct + { + __IM uint32_t SC2C : 16; /*!< [15..0] SC2 Capture */ + uint32_t : 16; + } SC2CPT_b; + }; +} R_I3C0_Type; /*!< Size = 1000 (0x3e8) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Master MPU (R_MPU_MMPU) + */ + +typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) MMPU Operation After Detection Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t OADPT; /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OADPT_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[62]; + __IOM R_MPU_MMPU_GROUP_Type DMAC0; /*!< (@ 0x00000100) DMAC0 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DMAC1; /*!< (@ 0x00000300) DMAC1 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type EDMAC; /*!< (@ 0x00000500) EDMAC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type GLCDC; /*!< (@ 0x00000700) GLCDC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type NPU; /*!< (@ 0x00001100) NPU MMPU Registers */ +} R_MPU_MMPU_Type; /*!< Size = 4864 (0x1300) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40203000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + + struct + { + __IOM uint32_t MSTPB0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPB4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPD4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRD_b; + }; + + union + { + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + + struct + { + __IOM uint32_t MSTPE0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPE1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPE2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPE3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPE5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPE6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPE7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPE8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPE9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRE_b; + }; + + union + { + __IOM uint16_t LSMRWDIS; /*!< (@ 0x00000010) Low Speed Module R/W Disable Control Register */ + + struct + { + __IOM uint16_t RTCRWDIS : 1; /*!< [0..0] RTC Register R/W Enable Control */ + __IOM uint16_t WDTDIS : 1; /*!< [1..1] WDT Operate Clock Control */ + __IOM uint16_t IWDTIDS : 1; /*!< [2..2] IWDT Register Clock Control */ + uint16_t : 4; + __IOM uint16_t WREN : 1; /*!< [7..7] Write Enable for bits [2:0] */ + __OM uint16_t PRKEY : 8; /*!< [15..8] LSMRWDIS Key Code */ + } LSMRWDIS_b; + }; + }; +} R_MSTP_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (R_PORT0) + */ + +typedef struct /*!< (@ 0x40400000) R_PORT0 Structure */ +{ + union + { + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; + + struct + { + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000000) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000002) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + }; + }; + + union + { + union + { + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; + + struct + { + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000004) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000006) Event input data register */ + + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + }; + }; + + union + { + union + { + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t POSR; /*!< (@ 0x00000008) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + + union + { + __OM uint16_t PORR; /*!< (@ 0x0000000A) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; + + struct + { + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000C) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000E) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + }; + }; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x40400800) R_PFS Structure */ +{ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-MISC (R_PMISC) + */ + +typedef struct /*!< (@ 0x40400D00) R_PMISC Structure */ +{ + union + { + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint8_t PWPR; /*!< (@ 0x0000000C) Write-Protect Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3[3]; + + union + { + __IOM uint8_t PWPRS; /*!< (@ 0x00000014) Write-Protect Register for Secure */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5[13]; + __IOM R_PMISC_PMSAR_Type PMSAR[15]; /*!< (@ 0x00000030) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 108 (0x6c) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Realtime Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x40202000) R_RTC Structure */ +{ + union + { + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + + struct + { + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ + __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using + * time error adjustment function inlow-consumption clock + * mode. */ + } R64CNT_b; + }; + __IM uint8_t RESERVED; + + union + { + union + { + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ + + struct + { + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; + }; + + union + { + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ + + struct + { + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ + + struct + { + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; + }; + + union + { + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ + + struct + { + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; + }; + + union + { + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; + }; + }; + __IM uint8_t RESERVED3; + + union + { + union + { + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ + + struct + { + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; + }; + + union + { + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; + }; + + union + { + union + { + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ + + struct + { + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; + }; + + union + { + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ + + struct + { + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; + }; + }; + __IM uint8_t RESERVED7; + + union + { + union + { + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ + + struct + { + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; + }; + + union + { + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; + }; + }; + __IM uint8_t RESERVED8; + + union + { + union + { + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; + + union + { + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; + }; + }; + __IM uint8_t RESERVED9; + + union + { + union + { + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ + + struct + { + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; + }; + + union + { + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; + }; + }; + __IM uint8_t RESERVED10; + + union + { + union + { + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; + + union + { + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; + }; + __IM uint8_t RESERVED11; + + union + { + union + { + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; + }; + + union + { + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; + }; + }; + __IM uint8_t RESERVED12; + + union + { + union + { + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; + + union + { + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; + }; + + union + { + union + { + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; + + union + { + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ + + struct + { + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ + + struct + { + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + + struct + { + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + + struct + { + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; + }; + + union + { + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + + struct + { + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; + }; + + union + { + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + + struct + { + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; + }; + __IM uint8_t RESERVED19; + + union + { + __IOM uint16_t RADJ2; /*!< (@ 0x00000030) Time Error Adjustment Register 2 */ + + struct + { + uint16_t : 5; + __IOM uint16_t FADJ : 11; /*!< [15..5] Fractional Adjust Value */ + } RADJ2_b; + }; + __IM uint16_t RESERVED20[7]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ + +typedef struct /*!< (@ 0x40358000) R_SCI0 Structure */ +{ + union + { + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + + struct + { + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; + }; + + union + { + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union + { + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + + struct + { + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; + }; + + union + { + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union + { + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_MANC; /*!< (@ 0x00000004) Serial Status Register for Manchester Mode (SCMR.SMIF + * = 0, and MMR.MANEN = 1) */ + + struct + { + __IOM uint8_t MER : 1; /*!< [0..0] Manchester Error Flag Valid for Manchester mode only */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_MANC_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; + }; + + union + { + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + + struct + { + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; + }; + + union + { + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + + struct + { + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; + }; + + union + { + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + + struct + { + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; + }; + + union + { + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + + struct + { + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; + }; + + union + { + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + + struct + { + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; + }; + + union + { + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + + struct + { + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; + }; + + union + { + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + + struct + { + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; + }; + + union + { + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + + struct + { + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; + }; + + union + { + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + + struct + { + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; + }; + + union + { + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union + { + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; + + union + { + __IOM uint16_t TDRHL_MAN; /*!< (@ 0x0000000E) Transmit Data Register for Manchester Mode (MMR.MANEN + * = 1) */ + + struct + { + __IOM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data */ + __IOM uint16_t MPBT : 1; /*!< [9..9] Multi-processor Transfer Bit Flag */ + uint16_t : 2; + __IOM uint16_t TSYNC : 1; /*!< [12..12] Transmit SYNC data bit */ + uint16_t : 3; + } TDRHL_MAN_b; + }; + + struct + { + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; + + union + { + __IM uint16_t RDRHL_MAN; /*!< (@ 0x00000010) Receive Data Register for Manchester Mode (MMR.MANEN + * = 1) */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial Receive Data */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor Bit */ + uint16_t : 2; + __IM uint16_t RSYNC : 1; /*!< [12..12] Receive SYNC data bit */ + uint16_t : 3; + } RDRHL_MAN_b; + }; + + struct + { + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; + + union + { + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + + struct + { + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; + }; + + union + { + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + + struct + { + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; + }; + + union + { + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + + struct + { + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; + }; + + union + { + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + + struct + { + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; + }; + + union + { + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + + struct + { + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; + }; + + union + { + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + + struct + { + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; + }; + + union + { + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + + struct + { + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; + }; + + union + { + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + + struct + { + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + + struct + { + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; + }; + + union + { + __IOM uint8_t MMR; /*!< (@ 0x00000020) Manchester Mode Register */ + + struct + { + __IOM uint8_t RMPOL : 1; /*!< [0..0] Polarity of Received Manchester Code */ + __IOM uint8_t TMPOL : 1; /*!< [1..1] Polarity of Transmit Manchester Code */ + __IOM uint8_t ERTEN : 1; /*!< [2..2] Manchester Edge Retiming Enable */ + uint8_t : 1; + __IOM uint8_t SYNVAL : 1; /*!< [4..4] SYNC Value Setting */ + __IOM uint8_t SYNSEL : 1; /*!< [5..5] SYNC Select */ + __IOM uint8_t SBSEL : 1; /*!< [6..6] Start Bit Select */ + __IOM uint8_t MANEN : 1; /*!< [7..7] Manchester Mode Enable */ + } MMR_b; + }; + }; + + union + { + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + + struct + { + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; + }; + + union + { + union + { + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + + struct + { + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; + }; + + union + { + __IOM uint8_t TMPR; /*!< (@ 0x00000022) Transmit Manchester Preface Setting Register */ + + struct + { + __IOM uint8_t TPLEN : 4; /*!< [3..0] Transmit Preface Length */ + __IOM uint8_t TPPAT : 2; /*!< [5..4] Transmit Preface Pattern */ + uint8_t : 2; + } TMPR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + + struct + { + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; + }; + + union + { + __IOM uint8_t RMPR; /*!< (@ 0x00000023) Receive Manchester Preface Setting Register */ + + struct + { + __IOM uint8_t RPLEN : 4; /*!< [3..0] Receive Preface Length */ + __IOM uint8_t RPPAT : 2; /*!< [5..4] Receive Preface Pattern */ + uint8_t : 2; + } RMPR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + + struct + { + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; + }; + + union + { + __IOM uint8_t MESR; /*!< (@ 0x00000024) Manchester Extended Error Status Register */ + + struct + { + __IOM uint8_t PFER : 1; /*!< [0..0] Preface Error Flag */ + __IOM uint8_t SYER : 1; /*!< [1..1] SYNC Error Flag */ + __IOM uint8_t SBER : 1; /*!< [2..2] Start Bit Error Flag */ + uint8_t : 5; + } MESR_b; + }; + }; + + union + { + union + { + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + + struct + { + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; + }; + + union + { + __IOM uint8_t MECR; /*!< (@ 0x00000025) Manchester Extended Error Control Register */ + + struct + { + __IOM uint8_t PFEREN : 1; /*!< [0..0] Preface Error Flag */ + __IOM uint8_t SYEREN : 1; /*!< [1..1] Receive SYNC Error Enable */ + __IOM uint8_t SBEREN : 1; /*!< [2..2] Start Bit Error Enable */ + uint8_t : 5; + } MECR_b; + }; + }; + + union + { + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + + struct + { + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; + }; + + union + { + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + + struct + { + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; + }; + + union + { + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + + struct + { + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; + }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + + union + { + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + + struct + { + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; + }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + + union + { + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + + struct + { + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; + }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + + struct + { + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; + }; + + union + { + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + + struct + { + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; + }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ + __IM uint16_t RESERVED1[4]; + + union + { + __IOM uint8_t SCIMSKEN; /*!< (@ 0x0000003C) SCI5 TXD Output Mask Enable Register */ + + struct + { + __IOM uint8_t MSKEN : 1; /*!< [0..0] SCI5 TXD Output Mask Enable */ + uint8_t : 7; + } SCIMSKEN_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_SCI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SD/MMC Host Interface (R_SDHI0) + */ + +typedef struct /*!< (@ 0x40252000) R_SDHI0 Structure */ +{ + union + { + __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ + + struct + { + __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] + * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: + * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ + __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ + __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used + * in normal mode, see section 1.4.10, Example of SD_CMD Register + * Setting to select mode/response type. */ + __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ + __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data + * is handled) */ + __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command + * with data is handled) */ + __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block + * transfer) */ + uint32_t : 16; + } SD_CMD_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ + + struct + { + __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ + } SD_ARG_b; + }; + + union + { + __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ + + struct + { + __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ + uint32_t : 16; + } SD_ARG1_b; + }; + + union + { + __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ + + struct + { + __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, + * CMD12 is issued to halt the transfer through the SD host + * interface.However, if a command sequence is halted because + * of a communications error or timeout, CMD12 is not issued. + * Although continued buffer access is possible even after + * STP has been set to 1, the buffer access error bit (ERR5 + * or ERR4) in SD_INFO2 will be set accordingly.- When STP + * has been set to 1 during transfer for single block write, + * the access end flag is set when SD_BUF becomes emp */ + uint32_t : 7; + __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When + * SD_CMD is set as follows to start the command sequence + * while SEC is set to 1, CMD12 is automatically issued to + * stop multi-block transfer with the number of blocks which + * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] + * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is + * automatically issued, multiple block transfer)When the + * command sequence is halted because of a communications + * error or timeout, CMD12 is not automatically i */ + uint32_t : 23; + } SD_STOP_b; + }; + + union + { + __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ + + struct + { + __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value + * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ + } SD_SECCNT_b; + }; + + union + { + __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ + + struct + { + __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP10_b; + }; + + union + { + __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ + + struct + { + __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP1_b; + }; + + union + { + __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ + + struct + { + __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP32_b; + }; + + union + { + __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ + + struct + { + __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP3_b; + }; + + union + { + __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ + + struct + { + __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP54_b; + }; + + union + { + __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ + + struct + { + __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP5_b; + }; + + union + { + __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ + + struct + { + __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ + uint32_t : 8; + } SD_RSP76_b; + }; + + union + { + __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ + + struct + { + __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ + uint32_t : 24; + } SD_RSP7_b; + }; + + union + { + __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ + uint32_t : 1; + __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ + __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ + __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ + __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ + uint32_t : 1; + __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ + __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ + __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ + __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ + uint32_t : 21; + } SD_INFO1_b; + }; + + union + { + __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ + + struct + { + __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ + __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ + __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ + __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ + __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ + __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ + __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ + __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified + * by SD_PORTSEL. */ + __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ + __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ + uint32_t : 3; + __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, + * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN + * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 + * cycles of SDCLK have elapsed after setting of the CBSY + * bit to 0 due to completion of the command sequence. */ + __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ + __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ + uint32_t : 16; + } SD_INFO2_b; + }; + + union + { + __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ + __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ + __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ + uint32_t : 3; + __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ + __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ + uint32_t : 22; + } SD_INFO1_MASK_b; + }; + + union + { + __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ + + struct + { + __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ + __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ + __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ + __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ + __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ + __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ + __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ + __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ + uint32_t : 5; + __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ + uint32_t : 16; + } SD_INFO2_MASK_b; + }; + + union + { + __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ + + struct + { + __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ + __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ + __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ + uint32_t : 22; + } SD_CLK_CTRL_b; + }; + + union + { + __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ + + struct + { + __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 + * and 512 bytes for the transfer of single blocks.In cases + * of multiple block transfer with automatic issuing of CMD12 + * (CMD18 and CMD25), the only specifiable transfer data size + * is 512 bytes. Furthermore, in cases of multiple block transfer + * without automatic issuing of CMD12, as well as 512 bytes, + * 32, 64, 128, and 256 bytes are specifiable. However, in + * the reading of 32, 64, 128, and 256 bytes for the transfer + * of multiple blocks, this is restricted to mult */ + uint32_t : 22; + } SD_SIZE_b; + }; + + union + { + __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ + + struct + { + __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ + __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ + __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating + * timeout, software reset should be executed to terminate + * command sequence. */ + uint32_t : 4; + __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ + uint32_t : 1; + __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset + * and when the SOFT_RST.SDRST flag is 0. */ + uint32_t : 16; + } SD_OPTION_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ + + struct + { + __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command + * issued within a command sequence */ + __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by + * setting a command index in SD_CMD, this is Indicated in + * CMDE0. */ + __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to + * a command issued within a command sequence */ + __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is + * issued by setting a command index in SD_CMD, this is indicated + * in RSPLENE0. */ + __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ + __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ + uint32_t : 2; + __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a + * command issued within a command sequence */ + __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued + * by setting a command index in SD_CMD, this is indicated + * in RSPCRCE0. */ + __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ + __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ + __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal + * value is 010b) */ + uint32_t : 17; + } SD_ERR_STS1_b; + }; + + union + { + __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ + + struct + { + __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ + __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ + __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ + __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ + __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ + __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ + __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ + uint32_t : 25; + } SD_ERR_STS2_b; + }; + + union + { + __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ + + struct + { + __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write + * data is written to this register. When reading from the + * SD card, the read data is read from this register. This + * register is internally connected to two 512-byte buffers.If + * both buffers are not empty when executing multiple block + * read, SD/MMC clock is stopped to suspend receiving data. + * When one of buffers is empty, SD/MMC clock is supplied + * to resume receiving data. */ + } SD_BUF0_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ + + struct + { + __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ + uint32_t : 1; + __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ + uint32_t : 5; + __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ + __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ + uint32_t : 22; + } SDIO_MODE_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ + uint32_t : 13; + __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ + __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ + uint32_t : 16; + } SDIO_INFO1_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ + uint32_t : 13; + __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ + __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ + uint32_t : 16; + } SDIO_INFO1_MASK_b; + }; + __IM uint32_t RESERVED3[79]; + + union + { + __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ + uint32_t : 30; + } SD_DMAEN_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ + + struct + { + __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ + uint32_t : 31; + } SOFT_RST_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ + uint32_t : 23; + } SDIF_MODE_b; + }; + __IM uint32_t RESERVED6[4]; + + union + { + __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ + + struct + { + uint32_t : 6; + __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ + __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ + uint32_t : 24; + } EXT_SWAP_b; + }; +} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ + +typedef struct /*!< (@ 0x4035C000) R_SPI0 Structure */ +{ + union + { + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + + struct + { + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + + struct + { + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; + }; + + union + { + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + + struct + { + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; + }; + + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; + }; + + union + { + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + + struct + { + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; + }; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ + +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ + union + { + __IOM uint16_t SRAMPRCR; /*!< (@ 0x00000000) SRAM Protection Control Register for Secure */ + + struct + { + __IOM uint16_t PR : 1; /*!< [0..0] Register Write Control */ + uint16_t : 7; + __OM uint16_t KW : 8; /*!< [15..8] Write Key Code */ + } SRAMPRCR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t SRAMPRCR_NS; /*!< (@ 0x00000004) SRAM Protection Control Register for Non-Secure */ + + struct + { + __IOM uint16_t PR : 1; /*!< [0..0] Register Write Control */ + uint16_t : 7; + __OM uint16_t KW : 8; /*!< [15..8] Write Key Code */ + } SRAMPRCR_NS_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) SRAM Wait State Control Register */ + + struct + { + __IOM uint8_t WTEN : 1; /*!< [0..0] SRAM wait enable */ + uint8_t : 7; + } SRAMWTSC_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4; + + union + { + __IOM uint8_t SRAMCR0; /*!< (@ 0x00000010) SRAM Control Register 0 */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after error detection */ + uint8_t : 1; + __IOM uint8_t ECCMOD : 2; /*!< [3..2] ECC Operating Mode Select */ + __IOM uint8_t E1STSEN : 1; /*!< [4..4] ECC 1-bit Error Update Enable */ + uint8_t : 2; + __IOM uint8_t TSTBYP : 1; /*!< [7..7] ECC Test Enable / ECC Bypass Select */ + } SRAMCR0_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint8_t SRAMCR1; /*!< (@ 0x00000014) SRAM Control Register 1 */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after error detection */ + uint8_t : 1; + __IOM uint8_t ECCMOD : 2; /*!< [3..2] ECC Operating Mode Select */ + __IOM uint8_t E1STSEN : 1; /*!< [4..4] ECC 1-bit Error Update Enable */ + uint8_t : 2; + __IOM uint8_t TSTBYP : 1; /*!< [7..7] ECC Test Enable / ECC Bypass Select */ + } SRAMCR1_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + + union + { + __IOM uint8_t SRAMCR2; /*!< (@ 0x00000018) SRAM Control Register 2 */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after error detection */ + uint8_t : 1; + __IOM uint8_t ECCMOD : 2; /*!< [3..2] ECC Operating Mode Select */ + __IOM uint8_t E1STSEN : 1; /*!< [4..4] ECC 1-bit Error Update Enable */ + uint8_t : 2; + __IOM uint8_t TSTBYP : 1; /*!< [7..7] ECC Test Enable / ECC Bypass Select */ + } SRAMCR2_b; + }; + __IM uint8_t RESERVED9; + __IM uint16_t RESERVED10; + + union + { + __IOM uint8_t SRAMCR3; /*!< (@ 0x0000001C) SRAM Control Register 3 */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after error detection */ + uint8_t : 1; + __IOM uint8_t ECCMOD : 2; /*!< [3..2] ECC Operating Mode Select */ + __IOM uint8_t E1STSEN : 1; /*!< [4..4] ECC 1-bit Error Update Enable */ + uint8_t : 2; + __IOM uint8_t TSTBYP : 1; /*!< [7..7] ECC Test Enable / ECC Bypass Select */ + } SRAMCR3_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[4]; + + union + { + __IOM uint8_t SRAMECCRGN0; /*!< (@ 0x00000030) SRAM ECC Region Control Register 0 */ + + struct + { + __IOM uint8_t ECCRGN : 3; /*!< [2..0] ECC target Region select */ + uint8_t : 5; + } SRAMECCRGN0_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; + + union + { + __IOM uint8_t SRAMECCRGN1; /*!< (@ 0x00000034) SRAM ECC Region Control Register 1 */ + + struct + { + __IOM uint8_t ECCRGN : 3; /*!< [2..0] ECC target Region select */ + uint8_t : 5; + } SRAMECCRGN1_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t SRAMECCRGN2; /*!< (@ 0x00000038) SRAM ECC Region Control Register 2 */ + + struct + { + __IOM uint8_t ECCRGN : 3; /*!< [2..0] ECC target Region select */ + uint8_t : 5; + } SRAMECCRGN2_b; + }; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; + + union + { + __IOM uint8_t SRAMECCRGN3; /*!< (@ 0x0000003C) SRAM ECC Region Control Register 3 */ + + struct + { + __IOM uint8_t ECCRGN : 3; /*!< [2..0] ECC target Region select */ + uint8_t : 5; + } SRAMECCRGN3_b; + }; + __IM uint8_t RESERVED20; + __IM uint16_t RESERVED21; + + union + { + __IM uint16_t SRAMESR; /*!< (@ 0x00000040) SRAM Error Status Register For ECC RAM */ + + struct + { + __IM uint16_t ERR00 : 1; /*!< [0..0] SRAM0 1-bit ECC Error Status */ + __IM uint16_t ERR01 : 1; /*!< [1..1] SRAM0 2-bit ECC Error Status */ + __IM uint16_t ERR10 : 1; /*!< [2..2] SRAM1 1-bit ECC Error Status */ + __IM uint16_t ERR11 : 1; /*!< [3..3] SRAM1 2-bit ECC Error Status */ + __IM uint16_t ERR20 : 1; /*!< [4..4] SRAM2 1-bit ECC Error Status */ + __IM uint16_t ERR21 : 1; /*!< [5..5] SRAM2 2-bit ECC Error Status */ + __IM uint16_t ERR30 : 1; /*!< [6..6] SRAM3 1-bit ECC Error Status */ + __IM uint16_t ERR31 : 1; /*!< [7..7] SRAM3 2-bit ECC Error Status */ + uint16_t : 8; + } SRAMESR_b; + }; + __IM uint16_t RESERVED22; + __IM uint32_t RESERVED23; + + union + { + __OM uint16_t SRAMESCLR; /*!< (@ 0x00000048) SRAM Error Status Clear Register For ECC RAM */ + + struct + { + __OM uint16_t CLR00 : 1; /*!< [0..0] SRAM0 1-bit ECC Error Status Clear */ + __OM uint16_t CLR01 : 1; /*!< [1..1] SRAM0 2-bit ECC Error Status Clear */ + __OM uint16_t CLR10 : 1; /*!< [2..2] SRAM1 1-bit ECC Error Status Clear */ + __OM uint16_t CLR11 : 1; /*!< [3..3] SRAM1 2-bit ECC Error Status Clear */ + __OM uint16_t CLR20 : 1; /*!< [4..4] SRAM2 1-bit ECC Error Status Clear */ + __OM uint16_t CLR21 : 1; /*!< [5..5] SRAM2 2-bit ECC Error Status Clear */ + __OM uint16_t CLR30 : 1; /*!< [6..6] SRAM3 1-bit ECC Error Status Clear */ + __OM uint16_t CLR31 : 1; /*!< [7..7] SRAM3 2-bit ECC Error Status Clear */ + uint16_t : 8; + } SRAMESCLR_b; + }; + __IM uint16_t RESERVED24; + __IM uint32_t RESERVED25; + + union + { + __IM uint32_t SRAMEAR00; /*!< (@ 0x00000050) SRAM Error Address Register 00 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR00_b; + }; + + union + { + __IM uint32_t SRAMEAR01; /*!< (@ 0x00000054) SRAM Error Address Register 01 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR01_b; + }; + __IM uint32_t RESERVED26[2]; + + union + { + __IM uint32_t SRAMEAR10; /*!< (@ 0x00000060) SRAM Error Address Register 10 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR10_b; + }; + + union + { + __IM uint32_t SRAMEAR11; /*!< (@ 0x00000064) SRAM Error Address Register 11 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR11_b; + }; + __IM uint32_t RESERVED27[2]; + + union + { + __IM uint32_t SRAMEAR20; /*!< (@ 0x00000070) SRAM Error Address Register 20 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR20_b; + }; + + union + { + __IM uint32_t SRAMEAR21; /*!< (@ 0x00000074) SRAM Error Address Register 21 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR21_b; + }; + __IM uint32_t RESERVED28[2]; + + union + { + __IM uint32_t SRAMEAR30; /*!< (@ 0x00000080) SRAM Error Address Register 30 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR30_b; + }; + + union + { + __IM uint32_t SRAMEAR31; /*!< (@ 0x00000084) SRAM Error Address Register 31 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR31_b; + }; +} R_SRAM_Type; /*!< Size = 136 (0x88) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0) + */ + +typedef struct /*!< (@ 0x4025D000) R_SSI0 Structure */ +{ + union + { + __IOM uint32_t SSICR; /*!< (@ 0x00000000) Control Register */ + + struct + { + __IOM uint32_t REN : 1; /*!< [0..0] Receive Enable */ + __IOM uint32_t TEN : 1; /*!< [1..1] Transmit Enable */ + uint32_t : 1; + __IOM uint32_t MUEN : 1; /*!< [3..3] Mute EnableNOTE: When this module is muted, the value + * of outputting serial data is rewritten to 0 but data transmission + * is not stopped. Write dummy data to the SSIFTDR not to + * generate a transmit underflow because the number of data + * in the transmit FIFO is decreasing. */ + __IOM uint32_t CKDV : 4; /*!< [7..4] Serial Oversampling Clock Division Ratio */ + __IOM uint32_t DEL : 1; /*!< [8..8] Serial Data Delay */ + __IOM uint32_t PDTA : 1; /*!< [9..9] Parallel Data Alignment */ + __IOM uint32_t SDTA : 1; /*!< [10..10] Serial Data Alignment */ + __IOM uint32_t SPDP : 1; /*!< [11..11] Serial Padding Polarity */ + __IOM uint32_t LRCKP : 1; /*!< [12..12] Serial WS Polarity */ + __IOM uint32_t BCKP : 1; /*!< [13..13] Serial Bit Clock Polarity */ + __IOM uint32_t MST : 1; /*!< [14..14] Serial WS Direction NOTE: Only the following settings + * are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings + * are prohibited. */ + uint32_t : 1; + __IOM uint32_t SWL : 3; /*!< [18..16] System Word LengthSet the system word length to the + * bit clock frequency/2 fs. */ + __IOM uint32_t DWL : 3; /*!< [21..19] Data Word Length */ + __IOM uint32_t FRM : 2; /*!< [23..22] Channels */ + uint32_t : 1; + __IOM uint32_t IIEN : 1; /*!< [25..25] Idle Mode Interrupt Enable */ + __IOM uint32_t ROIEN : 1; /*!< [26..26] Receive Overflow Interrupt Enable */ + __IOM uint32_t RUIEN : 1; /*!< [27..27] Receive Underflow Interrupt Enable */ + __IOM uint32_t TOIEN : 1; /*!< [28..28] Transmit Overflow Interrupt Enable */ + __IOM uint32_t TUIEN : 1; /*!< [29..29] Transmit Underflow Interrupt Enable */ + __IOM uint32_t CKS : 1; /*!< [30..30] Oversampling Clock Select */ + uint32_t : 1; + } SSICR_b; + }; + + union + { + __IOM uint32_t SSISR; /*!< (@ 0x00000004) Status Register */ + + struct + { + __IM uint32_t IDST : 1; /*!< [0..0] Idle Mode Status Flag */ + __IM uint32_t RSWNO : 1; /*!< [1..1] Receive Serial Word Number */ + __IM uint32_t RCHNO : 2; /*!< [3..2] Receive Channel Number.These bits are read as 00b. */ + __IM uint32_t TSWNO : 1; /*!< [4..4] Transmit Serial Word Number */ + __IM uint32_t TCHNO : 2; /*!< [6..5] Transmit Channel Number */ + uint32_t : 18; + __IM uint32_t IIRQ : 1; /*!< [25..25] Idle Mode Interrupt Status Flag */ + __IOM uint32_t ROIRQ : 1; /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t RUIRQ : 1; /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TOIRQ : 1; /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TUIRQ : 1; /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + uint32_t : 2; + } SSISR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t SSIFCR; /*!< (@ 0x00000010) FIFO Control Register */ + + struct + { + __IOM uint32_t RFRST : 1; /*!< [0..0] Receive FIFO Data Register Reset */ + __IOM uint32_t TFRST : 1; /*!< [1..1] Transmit FIFO Data Register Reset */ + __IOM uint32_t RIE : 1; /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by + * clearing either the RDF flag (see the description of the + * RDF bit for details) or RIE bit. */ + __IOM uint32_t TIE : 1; /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by + * clearing either the TDE flag (see the description of the + * TDE bit for details) or TIE bit. */ + __IOM uint32_t RTRG : 2; /*!< [5..4] Receive Data Trigger Number */ + __IOM uint32_t TTRG : 2; /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis + * are the number of empty stages in SSIFTDR at which the + * TDE flag is set. */ + uint32_t : 3; + __IOM uint32_t BSW : 1; /*!< [11..11] Byte Swap Enable */ + uint32_t : 4; + __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset */ + uint32_t : 14; + __IOM uint32_t AUCKE : 1; /*!< [31..31] Oversampling Clock Enable */ + } SSIFCR_b; + }; + + union + { + __IOM uint32_t SSIFSR; /*!< (@ 0x00000014) FIFO Status Register */ + + struct + { + __IOM uint32_t RDF : 1; /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register + * is a 32-byte FIFO register, the maximum number of data + * bytes that can be read from it while the RDF flag is 1 + * is indicated in the RDC[3:0] flags. If reading data from + * the SSIFRDR register is continued after all the data is + * read, undefined values will be read. */ + uint32_t : 7; + __IM uint32_t RDC : 6; /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data + * units stored in SSIFRDR) */ + uint32_t : 2; + __IOM uint32_t TDE : 1; /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register + * is a 32-byte FIFO register, the maximum number of bytes + * that can be written to it while the TDE flag is 1 is 8 + * - TDC[3:0]. If writing data to the SSIFTDR register is + * continued after all the data is written, writing will be + * invalid and an overflow occurs. */ + uint32_t : 7; + __IM uint32_t TDC : 6; /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of + * data units stored in SSIFTDR) */ + uint32_t : 2; + } SSIFSR_b; + }; + + union + { + union + { + __OM uint32_t SSIFTDR; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + + struct + { + __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of + * eight stages of 32-bit registers for storing data to be + * serially transmitted. NOTE: that when the SSIFTDR register + * is full of data (32 bytes), the next data cannot be written + * to it. If writing is attempted, it will be ignored and + * an overflow occurs. */ + } SSIFTDR_b; + }; + __OM uint16_t SSIFTDR16; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + __OM uint8_t SSIFTDR8; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + }; + + union + { + union + { + __IM uint32_t SSIFRDR; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + + struct + { + __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight + * stages of 32-bit registers for storing serially received + * data. */ + } SSIFRDR_b; + }; + __IM uint16_t SSIFRDR16; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + __IM uint8_t SSIFRDR8; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + }; + + union + { + __IOM uint32_t SSIOFR; /*!< (@ 0x00000020) Audio Format Register */ + + struct + { + __IOM uint32_t OMOD : 2; /*!< [1..0] Audio Format Select */ + uint32_t : 6; + __IOM uint32_t LRCONT : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation */ + __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in + * Idle Status */ + uint32_t : 22; + } SSIOFR_b; + }; + + union + { + __IOM uint32_t SSISCR; /*!< (@ 0x00000024) Status Control Register */ + + struct + { + __IOM uint32_t RDFS : 5; /*!< [4..0] RDF Setting Condition Select */ + uint32_t : 3; + __IOM uint32_t TDES : 5; /*!< [12..8] TDE Setting Condition Select */ + uint32_t : 19; + } SSISCR_b; + }; +} R_SSI0_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Pins (R_SYSTEM) + */ + +typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint8_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t OPE : 1; /*!< [6..6] Output Port Enable */ + uint8_t : 1; + } SBYCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t SSCR2; /*!< (@ 0x0000000E) Software Standby Control Register 2 */ + + struct + { + __IOM uint8_t SS2FSR : 1; /*!< [0..0] Software Standby 2 Fast Return */ + uint8_t : 7; + } SSCR2_b; + }; + __IM uint8_t RESERVED2; + + union + { + __IM uint8_t MRSCR; /*!< (@ 0x00000010) MRAM Standby Control Register */ + + struct + { + __IM uint8_t MRSWCF : 1; /*!< [0..0] MRAM Stabilization wait completion flag */ + uint8_t : 7; + } MRSCR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t VSCR; /*!< (@ 0x00000014) Voltage Scaling Control Register */ + + struct + { + __IOM uint8_t VSCM : 3; /*!< [2..0] Voltage Scaling Control Mode */ + uint8_t : 1; + __IOM uint8_t VSCMTSF : 1; /*!< [4..4] Voltage Scaling Control Mode Transition Status Flag */ + uint8_t : 3; + } VSCR_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint8_t SRMONR; /*!< (@ 0x00000018) SRAM Monitor Register */ + + struct + { + __IOM uint8_t MON : 2; /*!< [1..0] SRAM Voltage Monitor */ + uint8_t : 6; + } SRMONR_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ + + struct + { + __IOM uint32_t PCKD : 4; /*!< [3..0] Peripheral Module Clock D (PCLKD) Select */ + __IOM uint32_t PCKC : 4; /*!< [7..4] Peripheral Module Clock C (PCLKC) Select */ + __IOM uint32_t PCKB : 4; /*!< [11..8] Peripheral Module Clock B (PCLKB) Select */ + __IOM uint32_t PCKA : 4; /*!< [15..12] Peripheral Module Clock A (PCLKA) Select */ + __IOM uint32_t BCK : 4; /*!< [19..16] External Bus Clock (BCLK) Select */ + __IOM uint32_t PCKE : 4; /*!< [23..20] Peripheral Module Clock E (PCLKE) Select */ + __IOM uint32_t ICK : 4; /*!< [27..24] System Clock (ICLK) Select */ + __IOM uint32_t FCK : 4; /*!< [31..28] MRAM Clock (MRPCLK) Select */ + } SCKDIVCR_b; + }; + + union + { + __IOM uint16_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ + + struct + { + __IOM uint16_t CPUCK : 4; /*!< [3..0] CPU0 Clock (CPUCLK0) Select */ + __IOM uint16_t CPUCK1 : 4; /*!< [7..4] CPU1 Clock (CPUCLK1) Select */ + __IOM uint16_t NPUCK : 4; /*!< [11..8] NPU Clock (NPUCLK) Select */ + __IOM uint16_t MRICK : 4; /*!< [15..12] MRAM bus Clock (MRICLK) Select */ + } SCKDIVCR2_b; + }; + + union + { + __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ + + struct + { + __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ + uint8_t : 5; + } SCKSCR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL1 Control Register */ + + struct + { + __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL1 Stop Control */ + uint8_t : 7; + } PLLCR_b; + }; + __IM uint8_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ + + struct + { + __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ + uint8_t : 6; + __IOM uint8_t EBCKASEL : 1; /*!< [7..7] External Bus Asynchronous Select */ + } BCKCR_b; + }; + + union + { + __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ + + struct + { + __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT + * is prohibited when SCKDIVCR.ICK selects division by 1 and + * SCKSCR.CKSEL[2:0] bits select thesystem clock source that + * is faster than 32 MHz (ICLK > 32 MHz). */ + uint8_t : 7; + } MEMWAIT_b; + }; + + union + { + __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ + uint8_t : 7; + } MOSCCR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; + + union + { + __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ + uint8_t : 7; + } HOCOCR_b; + }; + __IM uint8_t RESERVED16; + + union + { + __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ + uint8_t : 7; + } MOCOCR_b; + }; + + union + { + __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ + + struct + { + __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ + uint8_t : 7; + } FLLCR1_b; + }; + + union + { + __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ + + struct + { + __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication Control */ + uint16_t : 5; + } FLLCR2_b; + }; + + union + { + __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ + + struct + { + __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF + * bit value after a reset is 1 when the OFS1.HOCOEN bit is + * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ + uint8_t : 2; + __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + uint8_t : 1; + __IM uint8_t PLLSF : 1; /*!< [5..5] PLL1 Clock Oscillation Stabilization Flag */ + __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ + uint8_t : 1; + } OSCSF_b; + }; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ + + struct + { + __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock Out source select */ + uint8_t : 1; + __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ + __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ + } CKOCR_b; + }; + + union + { + __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ + + struct + { + __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ + __IOM uint8_t TRCKSEL : 1; /*!< [4..4] Trace Clock Control Register */ + uint8_t : 2; + __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ + } TRCKCR_b; + }; + + union + { + __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ + + struct + { + __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ + } OSTDCR_b; + }; + + union + { + __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ + uint8_t : 7; + } OSTDSR_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IM uint8_t OSCMONR; /*!< (@ 0x00000043) Oscillator Monitor Register */ + + struct + { + uint8_t : 1; + __IM uint8_t MOCOMON : 1; /*!< [1..1] MOCO operation monitor */ + __IM uint8_t LOCOMON : 1; /*!< [2..2] LOCO operation monitor */ + uint8_t : 5; + } OSCMONR_b; + }; + __IM uint32_t RESERVED19; + __IM uint16_t RESERVED20; + + union + { + __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ + + struct + { + __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ + uint8_t : 7; + } PLL2CR_b; + }; + __IM uint8_t RESERVED21; + + union + { + union + { + __IOM uint16_t PLLCCR2; /*!< (@ 0x0000004C) PLL1 Clock Control Register 2 */ + + struct + { + __IOM uint16_t PLODIVP : 4; /*!< [3..0] PLL1 Output Frequency Division Ratio Select for output + * clock P */ + __IOM uint16_t PLODIVQ : 4; /*!< [7..4] PLL1 Output Frequency Division Ratio Select for output + * clock Q */ + __IOM uint16_t PLODIVR : 4; /*!< [11..8] PLL1 Output Frequency Division Ratio Select for output + * clock R */ + uint16_t : 4; + } PLLCCR2_b; + }; + + union + { + __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */ + + struct + { + __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock + * (valid only when LPOPTEN = 1) */ + __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */ + __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W + * clock (valid only when LPOPT.LPOPTEN = 1) */ + uint8_t : 3; + __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */ + } LPOPT_b; + }; + }; + + union + { + __IOM uint16_t PLL2CCR2; /*!< (@ 0x0000004E) PLL2 Clock Control Register 2 */ + + struct + { + __IOM uint16_t PL2ODIVP : 4; /*!< [3..0] PLL2 Output Frequency Division Ratio Select for output + * clock P */ + __IOM uint16_t PL2ODIVQ : 4; /*!< [7..4] PLL2 Output Frequency Division Ratio Select for output + * clock Q */ + __IOM uint16_t PL2ODIVR : 4; /*!< [11..8] PLL2 Output Frequency Division Ratio Select for output + * clock R */ + uint16_t : 4; + } PLL2CCR2_b; + }; + + union + { + __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ + + struct + { + __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ + uint8_t : 4; + __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ + } SLCDSCKCR_b; + }; + __IM uint8_t RESERVED22; + + union + { + __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ + + struct + { + __IOM uint8_t EBCKOEN : 1; /*!< [0..0] EBCLK Pin Output Control */ + uint8_t : 7; + } EBCKOCR_b; + }; + + union + { + __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ + + struct + { + __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ + uint8_t : 7; + } SDCKOCR_b; + }; + + union + { + __IOM uint8_t SCICKDIVCR; /*!< (@ 0x00000054) SCI clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] SCI clock (SCICLK) Division Select */ + uint8_t : 4; + } SCICKDIVCR_b; + }; + + union + { + __IOM uint8_t SCICKCR; /*!< (@ 0x00000055) SCI clock control register */ + + struct + { + __IOM uint8_t SCICKSEL : 4; /*!< [3..0] SCI clock (SCICLK) Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] SCI clock (SCICLK) Switching Request */ + __IM uint8_t CKSRDY : 1; /*!< [7..7] SCI clock (SCICLK) Switching Ready state flag */ + } SCICKCR_b; + }; + + union + { + __IOM uint8_t SPICKDIVCR; /*!< (@ 0x00000056) SPI clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] SPI clock (SPICLK) Division Select */ + uint8_t : 4; + } SPICKDIVCR_b; + }; + + union + { + __IOM uint8_t SPICKCR; /*!< (@ 0x00000057) SPI clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] SPI clock (SPICLK) Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] SPI clock (SPICLK) Switching Request */ + __IM uint8_t CKSRDY : 1; /*!< [7..7] SPI clock (SPICLK) Switching Ready state flag */ + } SPICKCR_b; + }; + __IM uint16_t RESERVED23; + + union + { + __IOM uint8_t ADCCKDIVCR; /*!< (@ 0x0000005A) ADC clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] Clock Division Select */ + uint8_t : 4; + } ADCCKDIVCR_b; + }; + + union + { + __IOM uint8_t ADCCKCR; /*!< (@ 0x0000005B) ADC clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } ADCCKCR_b; + }; + + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000005C) GPT Clock Division Control Register */ + + struct + { + __IOM uint8_t GPTCKDIV : 4; /*!< [3..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 4; + } GPTCKDIVCR_b; + }; + + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x0000005D) GPT clock control register */ + + struct + { + __IOM uint8_t GPTCKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } GPTCKCR_b; + }; + + union + { + __IOM uint8_t LCDCKDIVCR; /*!< (@ 0x0000005E) LCD clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] LCD clock (LCDCLK) Division Select */ + uint8_t : 4; + } LCDCKDIVCR_b; + }; + + union + { + __IOM uint8_t LCDCKCR; /*!< (@ 0x0000005F) LCD clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] LCD clock (LCDCLK) Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] LCD clock (LCDCLK) Switching Request */ + __IM uint8_t CKSRDY : 1; /*!< [7..7] LCD clock (LCDCLK) Switching Ready state flag */ + } LCDCKCR_b; + }; + __IM uint8_t RESERVED24; + + union + { + __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming */ + } MOCOUTCR_b; + }; + + union + { + __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming */ + } HOCOUTCR_b; + }; + __IM uint8_t RESERVED25; + __IM uint32_t RESERVED26[2]; + + union + { + __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ + + struct + { + __IOM uint8_t USBCKDIV : 4; /*!< [3..0] USB Clock (USBCLK) Division Select */ + uint8_t : 4; + } USBCKDIVCR_b; + }; + + union + { + __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t OCTACKDIV : 4; /*!< [3..0] Octal-SPI Clock (OCTACLK) Division Select */ + uint8_t : 4; + } OCTACKDIVCR_b; + }; + + union + { + __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ + + struct + { + __IOM uint8_t CANFDCKDIV : 4; /*!< [3..0] CANFD Clock (CANFDCLK) Division Select */ + uint8_t : 4; + } CANFDCKDIVCR_b; + }; + + union + { + __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */ + + struct + { + __IOM uint8_t USB60CKDIV : 4; /*!< [3..0] USB clock (USB60CLK) Division Select */ + uint8_t : 4; + } USB60CKDIVCR_b; + }; + + union + { + __IOM uint8_t I3CCKDIVCR; /*!< (@ 0x00000070) I3C Clock Division control register */ + + struct + { + __IOM uint8_t I3CCKDIV : 4; /*!< [3..0] I3C clock (I3CCLK) Division Select */ + uint8_t : 4; + } I3CCKDIVCR_b; + }; + __IM uint8_t RESERVED27; + __IM uint16_t RESERVED28; + + union + { + __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCKSEL : 4; /*!< [3..0] USB Clock (USBCLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ + __IOM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ + } USBCKCR_b; + }; + + union + { + __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ + + struct + { + __IOM uint8_t OCTACKSEL : 4; /*!< [3..0] Octal-SPI Clock (OCTACLK) Source Select */ + uint8_t : 2; + __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ + __IOM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ + } OCTACKCR_b; + }; + + union + { + __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ + + struct + { + __IOM uint8_t CANFDCKSEL : 4; /*!< [3..0] CANFD Clock (CANFDCLK) Source Select */ + uint8_t : 2; + __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ + __IOM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ + } CANFDCKCR_b; + }; + + union + { + __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ + + struct + { + __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ + __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ + } USB60CKCR_b; + }; + + union + { + __IOM uint8_t I3CCKCR; /*!< (@ 0x00000078) I3C Clock Control Register */ + + struct + { + __IOM uint8_t I3CCKSEL : 4; /*!< [3..0] I3C clock (I3CCLK) source select */ + uint8_t : 2; + __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */ + __IOM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */ + } I3CCKCR_b; + }; + __IM uint8_t RESERVED29; + __IM uint16_t RESERVED30; + + union + { + __IOM uint8_t MOSCSCR; /*!< (@ 0x0000007C) Main Clock Oscillator Standby Control Register */ + + struct + { + __IOM uint8_t MOSCSOKP : 1; /*!< [0..0] Main Clock Oscillator Standby Oscillation Keep select */ + uint8_t : 7; + } MOSCSCR_b; + }; + + union + { + __IOM uint8_t HOCOSCR; /*!< (@ 0x0000007D) High-Speed On-Chip Oscillator Standby Control + * Register */ + + struct + { + __IOM uint8_t HOSCSOKP : 1; /*!< [0..0] HOCO Standby Oscillation Keep select */ + uint8_t : 7; + } HOCOSCR_b; + }; + __IM uint16_t RESERVED31; + __IM uint32_t RESERVED32; + + union + { + __IOM uint8_t MOCOSCR; /*!< (@ 0x00000084) Middle-Speed On-Chip Oscillator Standby Control + * Register */ + + struct + { + __IOM uint8_t MOCOSOKP : 1; /*!< [0..0] MOCO Standby Oscillation Keep select */ + uint8_t : 7; + } MOCOSCR_b; + }; + __IM uint8_t RESERVED33; + __IM uint16_t RESERVED34; + __IM uint32_t RESERVED35[5]; + __IM uint16_t RESERVED36; + + union + { + __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ + + struct + { + __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ + uint8_t : 3; + __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ + uint8_t : 3; + } FLSTOP_b; + }; + + union + { + __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ + + struct + { + __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ + uint8_t : 6; + } PSMCR_b; + }; + + union + { + __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ + + struct + { + __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ + uint8_t : 2; + __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } OPCCR_b; + }; + __IM uint8_t RESERVED37; + + union + { + __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ + + struct + { + __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ + uint8_t : 4; + } MOSCWTCR_b; + }; + __IM uint8_t RESERVED38[2]; + + union + { + __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ + + struct + { + __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of + * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ + uint8_t : 5; + } HOCOWTCR_b; + }; + __IM uint16_t RESERVED39[2]; + + union + { + __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ + + struct + { + __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ + uint8_t : 3; + __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } SOPCCR_b; + }; + __IM uint8_t RESERVED40; + + union + { + __IOM uint32_t PLLCCR; /*!< (@ 0x000000AC) PLL1 Clock Control Register */ + + struct + { + __IOM uint32_t PLIDIV : 2; /*!< [1..0] PLL1 Input Frequency Division Ratio Select */ + uint32_t : 2; + __IOM uint32_t PLSRCSEL : 1; /*!< [4..4] PLL1 Clock Source Select */ + uint32_t : 1; + __IOM uint32_t PLLMULNF : 2; /*!< [7..6] PLL1 Frequency Multiplication Fractional Factor Select */ + __IOM uint32_t PLLMUL : 9; /*!< [16..8] PLL1 Frequency Multiplication Factor Select */ + uint32_t : 15; + } PLLCCR_b; + }; + __IM uint32_t RESERVED41[4]; + + union + { + __IOM uint32_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ + + struct + { + __IOM uint32_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect Flag */ + __IOM uint32_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect Flag */ + __IOM uint32_t SWRF : 1; /*!< [2..2] Software Reset Detect Flag */ + uint32_t : 1; + __IOM uint32_t CLURF : 1; /*!< [4..4] CPU0 Lockup Reset Detect flags */ + __IOM uint32_t LM0RF : 1; /*!< [5..5] Local memory 0 error Reset Detect Flag */ + uint32_t : 4; + __IOM uint32_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect Flag */ + uint32_t : 3; + __IOM uint32_t CMRF : 1; /*!< [14..14] Common memory error Reset Detect Flag */ + uint32_t : 2; + __IOM uint32_t WDT1RF : 1; /*!< [17..17] Watchdog Timer1 Reset Detect Flag */ + uint32_t : 2; + __IOM uint32_t CLU1RF : 1; /*!< [20..20] CPU1 Lockup Reset Detect Flag */ + __IOM uint32_t LM1RF : 1; /*!< [21..21] Local memory 1 error Reset Detect Flag */ + __IOM uint32_t NWRF : 1; /*!< [22..22] Network Reset Detect Flag */ + uint32_t : 9; + } RSTSR1_b; + }; + __IM uint32_t RESERVED42; + + union + { + __IOM uint32_t PLL2CCR; /*!< (@ 0x000000C8) PLL2 Clock Control Register */ + + struct + { + __IOM uint32_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ + uint32_t : 2; + __IOM uint32_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ + uint32_t : 1; + __IOM uint32_t PLL2MULNF : 2; /*!< [7..6] PLL2 Frequency Multiplication Fractional Factor Select */ + __IOM uint32_t PLL2MUL : 9; /*!< [16..8] PLL2 Frequency Multiplication Factor Select */ + uint32_t : 15; + } PLL2CCR_b; + }; + + union + { + __IM uint8_t SYRACCR; /*!< (@ 0x000000CC) System Register Access Control Register */ + + struct + { + __IM uint8_t BUSY : 1; /*!< [0..0] Access Ready Monitor */ + uint8_t : 7; + } SYRACCR_b; + }; + __IM uint8_t RESERVED43; + __IM uint16_t RESERVED44; + + union + { + __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock + * (UCLK). */ + uint8_t : 7; + } USBCKCR_ALT_b; + }; + + union + { + __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control + * Register */ + + struct + { + __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ + uint8_t : 6; + __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ + } SDADCCKCR_b; + }; + __IM uint16_t RESERVED45; + + union + { + __IOM uint8_t BCKADIVCR; /*!< (@ 0x000000D4) Asynchronous external Bus clock Division control + * register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] Clock Division Select */ + uint8_t : 4; + } BCKADIVCR_b; + }; + + union + { + __IOM uint8_t ESWCKDIVCR; /*!< (@ 0x000000D5) EtherSW clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] Clock Division Select */ + uint8_t : 4; + } ESWCKDIVCR_b; + }; + + union + { + __IOM uint8_t ESWPCKDIVCR; /*!< (@ 0x000000D6) EtherSW-PHY clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] Clock Division Select */ + uint8_t : 4; + } ESWPCKDIVCR_b; + }; + + union + { + __IOM uint8_t ESCCKDIVCR; /*!< (@ 0x000000D7) EtherCAT clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] Clock Division Select */ + uint8_t : 4; + } ESCCKDIVCR_b; + }; + + union + { + __IOM uint8_t ETHPCKDIVCR; /*!< (@ 0x000000D8) Ether-PHY clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] Clock Division Select */ + uint8_t : 4; + } ETHPCKDIVCR_b; + }; + __IM uint8_t RESERVED46; + + union + { + __IOM uint8_t BCKACR; /*!< (@ 0x000000DA) Asynchronous external bus clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IOM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } BCKACR_b; + }; + + union + { + __IOM uint8_t ESWCKCR; /*!< (@ 0x000000DB) EtherSW clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IOM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } ESWCKCR_b; + }; + + union + { + __IOM uint8_t ESWPCKCR; /*!< (@ 0x000000DC) EtherSW-PHY clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IOM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } ESWPCKCR_b; + }; + + union + { + __IOM uint8_t ESCCKCR; /*!< (@ 0x000000DD) EtherCAT clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IOM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } ESCCKCR_b; + }; + + union + { + __IOM uint8_t ETHPCKCR; /*!< (@ 0x000000DE) Ether-PHY clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IOM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } ETHPCKCR_b; + }; + __IM uint8_t RESERVED47; + + union + { + __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD1CR1_b; + }; + + union + { + __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD1SR_b; + }; + + union + { + __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD2CR1_b; + }; + + union + { + __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD2SR_b; + }; + + union + { + __IOM uint8_t LVD3CR1; /*!< (@ 0x000000E4) Voltage Monitor 3 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD3CR1_b; + }; + + union + { + __IOM uint8_t LVD3SR; /*!< (@ 0x000000E5) Voltage Monitor 3 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD3SR_b; + }; + + union + { + __IOM uint8_t LVD4CR1; /*!< (@ 0x000000E6) Voltage Monitor 4 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD4CR1_b; + }; + __IM uint8_t RESERVED48; + + union + { + __IOM uint8_t LVD5CR1; /*!< (@ 0x000000E8) Voltage Monitor 5 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD5CR1_b; + }; + __IM uint8_t RESERVED49; + __IM uint16_t RESERVED50; + __IM uint32_t RESERVED51; + + union + { + __IOM uint8_t CRVSYSCR; /*!< (@ 0x000000F0) Clock Recovery System Control Register */ + + struct + { + __IOM uint8_t CRVEN : 1; /*!< [0..0] Clock Recovery Enable */ + uint8_t : 7; + } CRVSYSCR_b; + }; + __IM uint8_t RESERVED52; + __IM uint16_t RESERVED53; + __IM uint32_t RESERVED54[3]; + + union + { + __IOM uint8_t CPUDSCR; /*!< (@ 0x00000100) CPU Deep Sleep Control Register */ + + struct + { + __IOM uint8_t PGD0 : 1; /*!< [0..0] Power Gating Disable for CPU0 */ + __IOM uint8_t PGD1 : 1; /*!< [1..1] Power Gating Disable for CPU1 */ + uint8_t : 6; + } CPUDSCR_b; + }; + __IM uint8_t RESERVED55; + __IM uint16_t RESERVED56; + __IM uint32_t RESERVED57[3]; + + union + { + __IOM uint8_t PDCTRGD; /*!< (@ 0x00000110) General Power Domain GD Control Register */ + + struct + { + __IOM uint8_t PDDE : 1; /*!< [0..0] Power control enable */ + uint8_t : 5; + __IOM uint8_t PDCSF : 1; /*!< [6..6] Power control status flag */ + __IOM uint8_t PDPGSF : 1; /*!< [7..7] Power gating status flag */ + } PDCTRGD_b; + }; + __IM uint8_t RESERVED58; + __IM uint16_t RESERVED59; + + union + { + __IOM uint8_t PDCTRNPU; /*!< (@ 0x00000114) General Power Domain NPU Control Register */ + + struct + { + __IOM uint8_t PDDE : 1; /*!< [0..0] Power control enable */ + uint8_t : 5; + __IOM uint8_t PDCSF : 1; /*!< [6..6] Power control status flag */ + __IOM uint8_t PDPGSF : 1; /*!< [7..7] Power gating status flag */ + } PDCTRNPU_b; + }; + __IM uint8_t RESERVED60; + __IM uint16_t RESERVED61; + + union + { + __IOM uint8_t PDCTRESWM; /*!< (@ 0x00000118) General Power Domain ESWM Control Register */ + + struct + { + __IOM uint8_t PDDE : 1; /*!< [0..0] Power control enable */ + uint8_t : 5; + __IOM uint8_t PDCSF : 1; /*!< [6..6] Power control status flag */ + __IOM uint8_t PDPGSF : 1; /*!< [7..7] Power gating status flag */ + } PDCTRESWM_b; + }; + __IM uint8_t RESERVED62; + __IM uint16_t RESERVED63; + __IM uint32_t RESERVED64[9]; + + union + { + __IOM uint16_t PDRAMSCR0; /*!< (@ 0x00000140) SRAM power domain Standby Control Register 0 */ + + struct + { + __IOM uint16_t RKEEP0 : 1; /*!< [0..0] RAM Retention bit 0 */ + __IOM uint16_t RKEEP1 : 1; /*!< [1..1] RAM Retention bit 1 */ + __IOM uint16_t RKEEP2 : 1; /*!< [2..2] RAM Retention bit 2 */ + __IOM uint16_t RKEEP3 : 1; /*!< [3..3] RAM Retention bit 3 */ + __IOM uint16_t RKEEP4 : 1; /*!< [4..4] RAM Retention bit 4 */ + __IOM uint16_t RKEEP5 : 1; /*!< [5..5] RAM Retention bit 5 */ + __IOM uint16_t RKEEP6 : 1; /*!< [6..6] RAM Retention bit 6 */ + __IOM uint16_t RKEEP7 : 1; /*!< [7..7] RAM Retention bit 7 */ + __IOM uint16_t RKEEP8 : 1; /*!< [8..8] RAM Retention bit 8 */ + __IOM uint16_t RKEEP9 : 1; /*!< [9..9] RAM Retention bit 9 */ + __IOM uint16_t RKEEP10 : 1; /*!< [10..10] RAM Retention bit 10 */ + __IOM uint16_t RKEEP11 : 1; /*!< [11..11] RAM Retention bit 11 */ + __IOM uint16_t RKEEP12 : 1; /*!< [12..12] RAM Retention bit 12 */ + __IOM uint16_t RKEEP13 : 1; /*!< [13..13] RAM Retention bit 13 */ + __IOM uint16_t RKEEP14 : 1; /*!< [14..14] RAM Retention bit 14 */ + __IOM uint16_t RKEEP15 : 1; /*!< [15..15] RAM Retention bit 15 */ + } PDRAMSCR0_b; + }; + + union + { + __IOM uint8_t PDRAMSCR1; /*!< (@ 0x00000142) SRAM power domain Standby Control Register 1 */ + + struct + { + __IOM uint8_t RKEEP0 : 1; /*!< [0..0] RAM Retention bit 0 */ + __IOM uint8_t RKEEP1 : 1; /*!< [1..1] RAM Retention bit 1 */ + __IOM uint8_t RKEEP2 : 1; /*!< [2..2] RAM Retention bit 2 */ + __IOM uint8_t RKEEP3 : 1; /*!< [3..3] RAM Retention bit 3 */ + __IOM uint8_t RKEEP4 : 1; /*!< [4..4] RAM Retention bit 4 */ + __IOM uint8_t RKEEP5 : 1; /*!< [5..5] RAM Retention bit 5 */ + __IOM uint8_t RKEEP6 : 1; /*!< [6..6] RAM Retention bit 6 */ + __IOM uint8_t RKEEP7 : 1; /*!< [7..7] RAM Retention bit 7 */ + } PDRAMSCR1_b; + }; + __IM uint8_t RESERVED65; + __IM uint32_t RESERVED66[155]; + + union + { + __IOM uint16_t VBRSABAR; /*!< (@ 0x000003B0) VBATT Backup Register Security Attribute Boundary + * Address Register */ + + struct + { + __IOM uint16_t SABA : 16; /*!< [15..0] Security Attribute Boundary Address */ + } VBRSABAR_b; + }; + __IM uint16_t RESERVED67; + + union + { + __IOM uint16_t VBRPABARS; /*!< (@ 0x000003B4) VBATT Backup Register Privilege Attribute Boundary + * Address Register for Secure Region */ + + struct + { + __IOM uint16_t PABAS : 16; /*!< [15..0] Privilege Attribute Boundary Address for Secure Region */ + } VBRPABARS_b; + }; + __IM uint16_t RESERVED68; + + union + { + __IOM uint16_t VBRPABARNS; /*!< (@ 0x000003B8) VBATT Backup Register Privilege Attribute Boundary + * Address Register for Non-secure Region */ + + struct + { + __IOM uint16_t PABANS : 16; /*!< [15..0] Privilege Attribute Boundary Address for Non-secure + * Region */ + } VBRPABARNS_b; + }; + __IM uint16_t RESERVED69; + __IM uint32_t RESERVED70; + + union + { + __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute + * Register */ + + struct + { + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ + } CGFSAR_b; + }; + + union + { + __IOM uint32_t RSTSAR; /*!< (@ 0x000003C4) Reset Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + uint32_t : 27; + } RSTSAR_b; + }; + + union + { + __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC5 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC6 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC7 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ + } LPMSAR_b; + }; + + union + { + __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + uint32_t : 30; + } LVDSAR_b; + }; + + union + { + __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non-secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non-secure Attribute bit 2 */ + __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non-secure Attribute bit 3 */ + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non-secure Attribute bit 4 */ + __IOM uint32_t NONSEC5 : 1; /*!< [5..5] Non-secure Attribute bit 5 */ + __IOM uint32_t NONSEC6 : 1; /*!< [6..6] Non-secure Attribute bit 6 */ + __IOM uint32_t NONSEC7 : 1; /*!< [7..7] Non-secure Attribute bit 7 */ + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non-secure Attribute bit 8 */ + uint32_t : 23; + } BBFSAR_b; + }; + __IM uint32_t RESERVED71; + + union + { + __IOM uint32_t PGCSAR; /*!< (@ 0x000003D8) Power Gating Control Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non-secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non-secure Attribute bit 2 */ + __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non-secure Attribute bit 3 */ + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non-secure Attribute bit 4 */ + __IOM uint32_t NONSEC5 : 1; /*!< [5..5] Non-secure Attribute bit 5 */ + __IOM uint32_t NONSEC6 : 1; /*!< [6..6] Non-secure Attribute bit 6 */ + __IOM uint32_t NONSEC7 : 1; /*!< [7..7] Non-secure Attribute bit 7 */ + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non-secure Attribute bit 8 */ + __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non-secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non-secure Attribute bit 10 */ + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non-secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non-secure Attribute bit 12 */ + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non-secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non-secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non-secure Attribute bit 15 */ + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non-secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non-secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non-secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non-secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non-secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non-secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non-secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non-secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non-secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non-secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non-secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non-secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non-secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non-secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non-secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non-secure Attribute bit 31 */ + } PGCSAR_b; + }; + __IM uint32_t RESERVED72; + + union + { + __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution + * Register */ + + struct + { + __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit + * 0 */ + __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit + * 1 */ + __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit + * 2 */ + __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit + * 3 */ + __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit + * 4 */ + __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit + * 5 */ + __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit + * 6 */ + __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit + * 7 */ + __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit + * 8 */ + __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit + * 9 */ + __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit + * 10 */ + __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit + * 11 */ + __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit + * 12 */ + __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit + * 13 */ + __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit + * 14 */ + __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit + * 15 */ + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + __IOM uint32_t DPFSA21 : 1; /*!< [21..21] Deep Standby Interrupt Factor Security Attribute bit + * 21 */ + __IOM uint32_t DPFSA22 : 1; /*!< [22..22] Deep Standby Interrupt Factor Security Attribute bit + * 22 */ + __IOM uint32_t DPFSA23 : 1; /*!< [23..23] Deep Standby Interrupt Factor Security Attribute bit + * 23 */ + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + __IOM uint32_t DPFSA25 : 1; /*!< [25..25] Deep Standby Interrupt Factor Security Attribute bit + * 25 */ + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + __IOM uint32_t DPFSA28 : 1; /*!< [28..28] Deep Standby Interrupt Factor Security Attribute bit + * 28 */ + __IOM uint32_t DPFSA29 : 1; /*!< [29..29] Deep Standby Interrupt Factor Security Attribute bit + * 29 */ + __IOM uint32_t DPFSA30 : 1; /*!< [30..30] Deep Standby Interrupt Factor Security Attribute bit + * 30 */ + __IOM uint32_t DPFSA31 : 1; /*!< [31..31] Deep Standby Interrupt Factor Security Attribute bit + * 31 */ + } DPFSAR_b; + }; + + union + { + __IOM uint32_t RSCSAR; /*!< (@ 0x000003E4) RAM Standby Control Security Attribution Register */ + + struct + { + __IOM uint32_t RSCSA0 : 1; /*!< [0..0] RAM Standby Control Security Attribute bit 0 */ + __IOM uint32_t RSCSA1 : 1; /*!< [1..1] RAM Standby Control Security Attribute bit 1 */ + __IOM uint32_t RSCSA2 : 1; /*!< [2..2] RAM Standby Control Security Attribute bit 2 */ + __IOM uint32_t RSCSA3 : 1; /*!< [3..3] RAM Standby Control Security Attribute bit 3 */ + __IOM uint32_t RSCSA4 : 1; /*!< [4..4] RAM Standby Control Security Attribute bit 4 */ + __IOM uint32_t RSCSA5 : 1; /*!< [5..5] RAM Standby Control Security Attribute bit 5 */ + __IOM uint32_t RSCSA6 : 1; /*!< [6..6] RAM Standby Control Security Attribute bit 6 */ + __IOM uint32_t RSCSA7 : 1; /*!< [7..7] RAM Standby Control Security Attribute bit 7 */ + __IOM uint32_t RSCSA8 : 1; /*!< [8..8] RAM Standby Control Security Attribute bit 8 */ + __IOM uint32_t RSCSA9 : 1; /*!< [9..9] RAM Standby Control Security Attribute bit 9 */ + __IOM uint32_t RSCSA10 : 1; /*!< [10..10] RAM Standby Control Security Attribute bit 10 */ + __IOM uint32_t RSCSA11 : 1; /*!< [11..11] RAM Standby Control Security Attribute bit 11 */ + __IOM uint32_t RSCSA12 : 1; /*!< [12..12] RAM Standby Control Security Attribute bit 12 */ + __IOM uint32_t RSCSA13 : 1; /*!< [13..13] RAM Standby Control Security Attribute bit 13 */ + __IOM uint32_t RSCSA14 : 1; /*!< [14..14] RAM Standby Control Security Attribute bit 14 */ + __IOM uint32_t RSCSA15 : 1; /*!< [15..15] RAM Standby Control Security Attribute bit 15 */ + __IOM uint32_t RSCSA16 : 1; /*!< [16..16] RAM Standby Control Security Attribute bit 16 */ + __IOM uint32_t RSCSA17 : 1; /*!< [17..17] RAM Standby Control Security Attribute bit 17 */ + __IOM uint32_t RSCSA18 : 1; /*!< [18..18] RAM Standby Control Security Attribute bit 18 */ + __IOM uint32_t RSCSA19 : 1; /*!< [19..19] RAM Standby Control Security Attribute bit 19 */ + __IOM uint32_t RSCSA20 : 1; /*!< [20..20] RAM Standby Control Security Attribute bit 20 */ + __IOM uint32_t RSCSA21 : 1; /*!< [21..21] RAM Standby Control Security Attribute bit 21 */ + __IOM uint32_t RSCSA22 : 1; /*!< [22..22] RAM Standby Control Security Attribute bit 22 */ + __IOM uint32_t RSCSA23 : 1; /*!< [23..23] RAM Standby Control Security Attribute bit 23 */ + __IOM uint32_t RSCSA24 : 1; /*!< [24..24] RAM Standby Control Security Attribute bit 24 */ + __IOM uint32_t RSCSA25 : 1; /*!< [25..25] RAM Standby Control Security Attribute bit 25 */ + __IOM uint32_t RSCSA26 : 1; /*!< [26..26] RAM Standby Control Security Attribute bit 26 */ + __IOM uint32_t RSCSA27 : 1; /*!< [27..27] RAM Standby Control Security Attribute bit 27 */ + __IOM uint32_t RSCSA28 : 1; /*!< [28..28] RAM Standby Control Security Attribute bit 28 */ + __IOM uint32_t RSCSA29 : 1; /*!< [29..29] RAM Standby Control Security Attribute bit 29 */ + __IOM uint32_t RSCSA30 : 1; /*!< [30..30] RAM Standby Control Security Attribute bit 30 */ + __IOM uint32_t RSCSA31 : 1; /*!< [31..31] RAM Standby Control Security Attribute bit 31 */ + } RSCSAR_b; + }; + + union + { + __IOM uint32_t DPFSAR1; /*!< (@ 0x000003E8) Deep Standby Interrupt Factor Security Attribution + * Register 1 */ + + struct + { + __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit + * 0 */ + __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit + * 1 */ + __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit + * 2 */ + __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit + * 3 */ + __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit + * 4 */ + __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit + * 5 */ + __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit + * 6 */ + __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit + * 7 */ + __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit + * 8 */ + __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit + * 9 */ + __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit + * 10 */ + __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit + * 11 */ + __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit + * 12 */ + __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit + * 13 */ + __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit + * 14 */ + __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit + * 15 */ + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + __IOM uint32_t DPFSA21 : 1; /*!< [21..21] Deep Standby Interrupt Factor Security Attribute bit + * 21 */ + __IOM uint32_t DPFSA22 : 1; /*!< [22..22] Deep Standby Interrupt Factor Security Attribute bit + * 22 */ + __IOM uint32_t DPFSA23 : 1; /*!< [23..23] Deep Standby Interrupt Factor Security Attribute bit + * 23 */ + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + __IOM uint32_t DPFSA25 : 1; /*!< [25..25] Deep Standby Interrupt Factor Security Attribute bit + * 25 */ + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + __IOM uint32_t DPFSA28 : 1; /*!< [28..28] Deep Standby Interrupt Factor Security Attribute bit + * 28 */ + __IOM uint32_t DPFSA29 : 1; /*!< [29..29] Deep Standby Interrupt Factor Security Attribute bit + * 29 */ + __IOM uint32_t DPFSA30 : 1; /*!< [30..30] Deep Standby Interrupt Factor Security Attribute bit + * 30 */ + __IOM uint32_t DPFSA31 : 1; /*!< [31..31] Deep Standby Interrupt Factor Security Attribute bit + * 31 */ + } DPFSAR1_b; + }; + __IM uint32_t RESERVED73[3]; + __IM uint16_t RESERVED74; + + union + { + __IOM uint16_t PRCR; /*!< (@ 0x000003FA) Protect Register for Secure Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power modes, and the battery backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the PVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] Enables writing to the registers related to the security + * and privilege setting registers. */ + __IOM uint16_t PRC5 : 1; /*!< [5..5] Enables writing to the registers related the reset control. */ + uint16_t : 2; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRC Key Code */ + } PRCR_b; + }; + __IM uint16_t RESERVED75; + + union + { + __IOM uint16_t PRCR_NS; /*!< (@ 0x000003FE) Protect Register for Non-secure Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power modes, and the battery backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the PVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] Enables writing to the registers related to the privilege + * setting registers. */ + uint16_t : 3; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRC Key Code */ + } PRCR_NS_b; + }; + + union + { + __IOM uint8_t LOCOCR; /*!< (@ 0x00000400) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint8_t : 7; + } LOCOCR_b; + }; + __IM uint8_t RESERVED76; + + union + { + __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000402) LOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming */ + } LOCOUTCR_b; + }; + __IM uint8_t RESERVED77; + __IM uint32_t RESERVED78[2]; + __IM uint16_t RESERVED79; + __IM uint8_t RESERVED80; + + union + { + __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ + + struct + { + __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ + uint8_t : 6; + } STCONR_b; + }; + __IM uint32_t RESERVED81; + __IM uint16_t RESERVED82; + + union + { + __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ + + struct + { + __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ + uint8_t : 6; + } FWEPROR_b; + }; + __IM uint8_t RESERVED83; + __IM uint32_t RESERVED84; + __IM uint16_t RESERVED85; + + union + { + __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ + + struct + { + __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ + uint8_t : 7; + } VBATTMONR_b; + }; + + union + { + __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ + uint8_t : 7; + } VBTCR1_b; + }; + __IM uint32_t RESERVED86[8]; + + union + { + __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ + + struct + { + __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ + __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ + uint8_t : 2; + __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ + __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ + __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ + __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ + } DCDCCTL_b; + }; + + union + { + __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ + + struct + { + __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ + uint8_t : 6; + } VCCSEL_b; + }; + __IM uint16_t RESERVED87; + __IM uint32_t RESERVED88[15]; + __IM uint16_t RESERVED89; + + union + { + __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ + + struct + { + __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ + uint8_t : 6; + } SOMRG_b; + }; + __IM uint8_t RESERVED90; + __IM uint32_t RESERVED91[11]; + + union + { + __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ + uint8_t : 1; + __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ + } VBTCR2_b; + }; + + union + { + __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ + + struct + { + __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ + __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ + uint8_t : 2; + __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ + uint8_t : 3; + } VBTSR_b; + }; + + union + { + __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ + + struct + { + __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ + uint8_t : 7; + } VBTCMPCR_b; + }; + __IM uint8_t RESERVED92; + + union + { + __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control + * Register */ + + struct + { + __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ + __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ + uint8_t : 6; + } VBTLVDICR_b; + }; + __IM uint8_t RESERVED93; + + union + { + __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ + + struct + { + __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ + uint8_t : 7; + } VBTWCTLR_b; + }; + __IM uint8_t RESERVED94; + + union + { + __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ + __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH0OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH1OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ + __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH2OTSR_b; + }; + __IM uint8_t RESERVED95; + + union + { + __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ + + struct + { + __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ + __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ + __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ + __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ + __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ + __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ + uint8_t : 2; + } VBTOCTLR_b; + }; + + union + { + __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ + + struct + { + __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ + __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ + __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ + __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ + __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ + __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWTER_b; + }; + + union + { + __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ + + struct + { + __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ + uint8_t : 5; + } VBTWEGR_b; + }; + + union + { + __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ + + struct + { + __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ + __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ + __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ + __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ + __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ + __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ + uint8_t : 2; + } VBTWFR_b; + }; + __IM uint32_t RESERVED96[336]; + + union + { + __IOM uint8_t DPSBYCR; /*!< (@ 0x00000A00) Deep Standby Control Register */ + + struct + { + __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ + __IOM uint8_t DCSSMODE : 2; /*!< [3..2] DCDC SSMODE */ + uint8_t : 2; + __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ + __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ + } DPSBYCR_b; + }; + __IM uint8_t RESERVED97; + __IM uint16_t RESERVED98; + __IM uint32_t RESERVED99; + + union + { + __IOM uint8_t DPSIER0; /*!< (@ 0x00000A08) Deep Standby Interrupt Enable Register 0 */ + + struct + { + __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER0_b; + }; + __IM uint8_t RESERVED100; + __IM uint16_t RESERVED101; + + union + { + __IOM uint8_t DPSIER1; /*!< (@ 0x00000A0C) Deep Standby Interrupt Enable Register 1 */ + + struct + { + __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER1_b; + }; + __IM uint8_t RESERVED102; + __IM uint16_t RESERVED103; + + union + { + __IOM uint8_t DPSIER2; /*!< (@ 0x00000A10) Deep Standby Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t DPVD1IE : 1; /*!< [0..0] PVD1 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DPVD2IE : 1; /*!< [1..1] PVD2 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ + __IOM uint8_t DPVD3IE : 1; /*!< [5..5] PVD3 Deep Standby Cancel Signal Enable */ + uint8_t : 2; + } DPSIER2_b; + }; + __IM uint8_t RESERVED104; + __IM uint16_t RESERVED105; + + union + { + __IOM uint8_t DPSIER3; /*!< (@ 0x00000A14) Deep Standby Interrupt Enable Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DULPT0IE : 1; /*!< [2..2] ULPT0 Overflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DULPT1IE : 1; /*!< [3..3] ULPT1 Overflow Deep Standby Cancel Signal Enable */ + uint8_t : 1; + __IOM uint8_t DIWDTIE : 1; /*!< [5..5] IWDT Overflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DSOSTDIE : 1; /*!< [6..6] Sub-clock Oscillation stop detection Deep Standby Cancel + * Signal Enable */ + __IOM uint8_t DVBATTADIE : 1; /*!< [7..7] VBATT Tamper Detection Deep Standby Cancel Signal Enable */ + } DPSIER3_b; + }; + __IM uint8_t RESERVED106; + __IM uint16_t RESERVED107; + + union + { + __IOM uint8_t DPSIFR0; /*!< (@ 0x00000A18) Deep Standby Interrupt Flag Register 0 */ + + struct + { + __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR0_b; + }; + __IM uint8_t RESERVED108; + __IM uint16_t RESERVED109; + + union + { + __IOM uint8_t DPSIFR1; /*!< (@ 0x00000A1C) Deep Standby Interrupt Flag Register 1 */ + + struct + { + __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR1_b; + }; + __IM uint8_t RESERVED110; + __IM uint16_t RESERVED111; + + union + { + __IOM uint8_t DPSIFR2; /*!< (@ 0x00000A20) Deep Standby Interrupt Flag Register 2 */ + + struct + { + __IOM uint8_t DPVD1IF : 1; /*!< [0..0] PVD1 Deep Standby Cancel Flag */ + __IOM uint8_t DPVD2IF : 1; /*!< [1..1] PVD2 Deep Standby Cancel Flag */ + __IOM uint8_t DRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ + __IOM uint8_t DPVD3IF : 1; /*!< [5..5] PVD5 Deep Standby Cancel Flag */ + uint8_t : 2; + } DPSIFR2_b; + }; + __IM uint8_t RESERVED112; + __IM uint16_t RESERVED113; + + union + { + __IOM uint8_t DPSIFR3; /*!< (@ 0x00000A24) Deep Standby Interrupt Flag Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DULPT0IF : 1; /*!< [2..2] ULPT0 Overflow Deep Standby Cancel Flag */ + __IOM uint8_t DULPT1IF : 1; /*!< [3..3] ULPT1 Overflow Deep Standby Cancel Flag */ + uint8_t : 1; + __IOM uint8_t DIWDTIF : 1; /*!< [5..5] IWDT Overflow Deep Standby Cancel Flag */ + __IOM uint8_t DSOSTDIF : 1; /*!< [6..6] Sub-clock Oscillation stop detection Deep Standby Cancel + * Flag */ + __IOM uint8_t DVBATTADIF : 1; /*!< [7..7] VBATT Tamper Detection Deep Standby Cancel Flag */ + } DPSIFR3_b; + }; + __IM uint8_t RESERVED114; + __IM uint16_t RESERVED115; + + union + { + __IOM uint8_t DPSIEGR0; /*!< (@ 0x00000A28) Deep Standby Interrupt Edge Register 0 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR0_b; + }; + __IM uint8_t RESERVED116; + __IM uint16_t RESERVED117; + + union + { + __IOM uint8_t DPSIEGR1; /*!< (@ 0x00000A2C) Deep Standby Interrupt Edge Register 1 */ + + struct + { + __IOM uint8_t DIRQ8EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ9EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ10EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ11EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ12EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ13EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ14EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ15EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR1_b; + }; + __IM uint8_t RESERVED118; + __IM uint16_t RESERVED119; + + union + { + __IOM uint8_t DPSIEGR2; /*!< (@ 0x00000A30) Deep Standby Interrupt Edge Register 2 */ + + struct + { + __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ + __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ + uint8_t : 2; + __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ + __IOM uint8_t DLVD3IEG : 1; /*!< [5..5] LVD3 Edge Select */ + uint8_t : 2; + } DPSIEGR2_b; + }; + __IM uint8_t RESERVED120; + __IM uint16_t RESERVED121; + + union + { + __IOM uint8_t DPSIEGR3; /*!< (@ 0x00000A34) Deep Standby Interrupt Edge Register 3 */ + + struct + { + __IOM uint8_t DIRQ16EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ17EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ18EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ19EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ20EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ21EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ22EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ23EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR3_b; + }; + __IM uint8_t RESERVED122; + __IM uint16_t RESERVED123; + + union + { + __IOM uint8_t SYOCDCR; /*!< (@ 0x00000A38) System Control OCD Control Register */ + + struct + { + __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ + uint8_t : 6; + __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ + } SYOCDCR_b; + }; + __IM uint8_t RESERVED124; + __IM uint16_t RESERVED125; + __IM uint32_t RESERVED126; + + union + { + __IOM uint8_t RSTSR0; /*!< (@ 0x00000A40) Reset Status Register 0 */ + + struct + { + __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect Flag */ + __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect Flag */ + __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect Flag */ + __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect Flag */ + uint8_t : 1; + __IOM uint8_t LVD4RF : 1; /*!< [5..5] Voltage Monitor 4 Reset Detect Flag */ + __IOM uint8_t LVD5RF : 1; /*!< [6..6] Voltage Monitor 5 Reset Detect Flag */ + __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset Flag */ + } RSTSR0_b; + }; + __IM uint8_t RESERVED127; + __IM uint16_t RESERVED128; + + union + { + __IOM uint8_t RSTSR2; /*!< (@ 0x00000A44) Reset Status Register 2 */ + + struct + { + __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ + uint8_t : 7; + } RSTSR2_b; + }; + __IM uint8_t RESERVED129; + __IM uint16_t RESERVED130; + + union + { + __IOM uint8_t RSTSR3; /*!< (@ 0x00000A48) Reset Status Register 3 */ + + struct + { + __IOM uint8_t CVMRF : 1; /*!< [0..0] Core Voltage Monitor Reset Detect Flag */ + uint8_t : 3; + __IOM uint8_t OCPRF : 1; /*!< [4..4] Overcurrent Protection Reset Detect Flag */ + uint8_t : 2; + __IOM uint8_t TEMPRF : 1; /*!< [7..7] Temperature Monitor Reset Detect Flag */ + } RSTSR3_b; + }; + __IM uint8_t RESERVED131; + __IM uint16_t RESERVED132; + __IM uint32_t RESERVED133; + + union + { + __IOM uint8_t MOMCR; /*!< (@ 0x00000A50) Main Clock Oscillator Mode Oscillation Control + * Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t MODRV0 : 3; /*!< [3..1] Main Clock Oscillator Drive Capability 0 Switching */ + uint8_t : 2; + __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ + uint8_t : 1; + } MOMCR_b; + }; + __IM uint8_t RESERVED134; + __IM uint16_t RESERVED135; + __IM uint32_t RESERVED136; + + union + { + __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000A58) Voltage Monitoring 1 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 5; /*!< [4..0] Detection Voltage Level Select(Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection Enable */ + } LVD1CMPCR_b; + }; + __IM uint8_t RESERVED137; + __IM uint16_t RESERVED138; + + union + { + __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000A5C) Voltage Monitoring 2 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 5; /*!< [4..0] Detection Voltage Level Select(Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection Enable */ + } LVD2CMPCR_b; + }; + __IM uint8_t RESERVED139; + __IM uint16_t RESERVED140; + + union + { + __IOM uint8_t LVD3CMPCR; /*!< (@ 0x00000A60) Voltage Monitoring 3 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 5; /*!< [4..0] Detection Voltage Level Select(Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection Enable */ + } LVD3CMPCR_b; + }; + __IM uint8_t RESERVED141; + __IM uint16_t RESERVED142; + + union + { + __IOM uint8_t LVD4CMPCR; /*!< (@ 0x00000A64) Voltage Monitoring 4 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 5; /*!< [4..0] Detection Voltage Level Select(Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection Enable */ + } LVD4CMPCR_b; + }; + __IM uint8_t RESERVED143; + __IM uint16_t RESERVED144; + + union + { + __IOM uint8_t LVD5CMPCR; /*!< (@ 0x00000A68) Voltage Monitoring 5 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 5; /*!< [4..0] Detection Voltage Level Select(Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection Enable */ + } LVD5CMPCR_b; + }; + __IM uint8_t RESERVED145; + __IM uint16_t RESERVED146; + __IM uint32_t RESERVED147; + + union + { + __IOM uint8_t LVD1CR0; /*!< (@ 0x00000A70) Voltage Monitor 1 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD1CR0_b; + }; + __IM uint8_t RESERVED148; + __IM uint16_t RESERVED149; + + union + { + __IOM uint8_t LVD2CR0; /*!< (@ 0x00000A74) Voltage Monitor 2 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD2CR0_b; + }; + __IM uint8_t RESERVED150; + __IM uint16_t RESERVED151; + + union + { + __IOM uint8_t LVD3CR0; /*!< (@ 0x00000A78) Voltage Monitor 3 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD3CR0_b; + }; + __IM uint8_t RESERVED152; + __IM uint16_t RESERVED153; + + union + { + __IOM uint8_t LVD4CR0; /*!< (@ 0x00000A7C) Voltage Monitor 4 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD4CR0_b; + }; + __IM uint8_t RESERVED154; + __IM uint16_t RESERVED155; + + union + { + __IOM uint8_t LVD5CR0; /*!< (@ 0x00000A80) Voltage Monitor 5 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD5CR0_b; + }; + __IM uint8_t RESERVED156; + __IM uint16_t RESERVED157; + + union + { + __IOM uint8_t VBATTMNSELR; /*!< (@ 0x00000A84) Battery Backup Voltage Monitor Function Select + * Register */ + + struct + { + __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ + uint8_t : 7; + } VBATTMNSELR_b; + }; + __IM uint8_t RESERVED158; + __IM uint16_t RESERVED159; + + union + { + __IOM uint8_t VBTBPCR1; /*!< (@ 0x00000A88) VBATT Battery Power Supply Control Register 1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power Supply Switch Stop */ + uint8_t : 7; + } VBTBPCR1_b; + }; + __IM uint8_t RESERVED160; + __IM uint16_t RESERVED161; + __IM uint32_t RESERVED162; + + union + { + __IOM uint8_t LPSCR; /*!< (@ 0x00000A90) Low Power State Control Register */ + + struct + { + __IOM uint8_t LPMD : 4; /*!< [3..0] Low power mode setting bit */ + uint8_t : 4; + } LPSCR_b; + }; + __IM uint8_t RESERVED163; + __IM uint16_t RESERVED164; + __IM uint32_t RESERVED165; + + union + { + __IOM uint8_t SSCR1; /*!< (@ 0x00000A98) Software Standby Control Register 1 */ + + struct + { + __IOM uint8_t SS2FR : 1; /*!< [0..0] Software Standby 2 Fast Return */ + uint8_t : 1; + __IOM uint8_t SS2LP : 2; /*!< [3..2] Software Standby 2 Low Power Select */ + uint8_t : 4; + } SSCR1_b; + }; + __IM uint8_t RESERVED166; + __IM uint16_t RESERVED167; + + union + { + __IOM uint8_t SVSCR; /*!< (@ 0x00000A9C) SSTBY Voltage Scaling Control Register */ + + struct + { + __IOM uint8_t SVSCM : 3; /*!< [2..0] SSTBY Voltage Scaling Control Mode */ + uint8_t : 5; + } SVSCR_b; + }; + __IM uint8_t RESERVED168; + __IM uint16_t RESERVED169; + __IM uint32_t RESERVED170[4]; + + union + { + __IOM uint8_t LVOCR; /*!< (@ 0x00000AB0) Low Voltage Operation Control Register */ + + struct + { + __IOM uint8_t LVO0E : 1; /*!< [0..0] Low Voltage Operation 0 Enable */ + __IOM uint8_t LVO1E : 1; /*!< [1..1] Low Voltage Operation 1 Enable */ + uint8_t : 6; + } LVOCR_b; + }; + __IM uint8_t RESERVED171; + __IM uint16_t RESERVED172; + + union + { + __IOM uint8_t MWMCR; /*!< (@ 0x00000AB4) MRAM-OTP Write Mode Control Register */ + + struct + { + __IOM uint8_t MWM : 2; /*!< [1..0] MRAM-OTP Write Mode */ + uint8_t : 6; + } MWMCR_b; + }; + __IM uint8_t RESERVED173; + __IM uint16_t RESERVED174; + __IM uint32_t RESERVED175[6]; + + union + { + __IOM uint8_t SYRSTMSK0; /*!< (@ 0x00000AD0) System Reset Mask Control Register 0 */ + + struct + { + __IOM uint8_t IWDTMASK : 1; /*!< [0..0] Independent Watchdog Timer Reset Mask */ + __IOM uint8_t WDT0MASK : 1; /*!< [1..1] Watchdog Timer Reset Mask */ + __IOM uint8_t SWMASK : 1; /*!< [2..2] Software Reset Mask */ + uint8_t : 1; + __IOM uint8_t CLU0MASK : 1; /*!< [4..4] CPU Lockup Reset Mask */ + __IOM uint8_t LM0MASK : 1; /*!< [5..5] Local Memory 0 Error Reset Mask */ + __IOM uint8_t CMMASK : 1; /*!< [6..6] Common Memory Error Reset Mask */ + __IOM uint8_t BUSMASK : 1; /*!< [7..7] Bus Error Reset Mask */ + } SYRSTMSK0_b; + }; + __IM uint8_t RESERVED176; + __IM uint16_t RESERVED177; + + union + { + __IOM uint8_t SYRSTMSK1; /*!< (@ 0x00000AD4) System Reset Mask Control Register 1 */ + + struct + { + uint8_t : 1; + __IOM uint8_t WDT1MASK : 1; /*!< [1..1] CPU1 Watchdog Timer Reset Mask */ + uint8_t : 2; + __IOM uint8_t CLU1MASK : 1; /*!< [4..4] CPU1 Lockup Reset Mask */ + __IOM uint8_t LM1MASK : 1; /*!< [5..5] Local Memory 1 Error Reset Mask */ + uint8_t : 2; + } SYRSTMSK1_b; + }; + __IM uint8_t RESERVED178; + __IM uint16_t RESERVED179; + + union + { + __IOM uint8_t SYRSTMSK2; /*!< (@ 0x00000AD8) System Reset Mask Control Register 2 */ + + struct + { + __IOM uint8_t PVD1MASK : 1; /*!< [0..0] Voltage Monitor 1 Reset Mask */ + __IOM uint8_t PVD2MASK : 1; /*!< [1..1] Voltage Monitor 2 Reset Mask */ + uint8_t : 6; + } SYRSTMSK2_b; + }; + __IM uint8_t RESERVED180; + __IM uint16_t RESERVED181; + + union + { + __IOM uint8_t TEMPRCR; /*!< (@ 0x00000ADC) Temperature Monitor Reset Control Register */ + + struct + { + __IOM uint8_t TEMPREN : 1; /*!< [0..0] Temperature Monitor Reset Enable */ + __IOM uint8_t TSNEN : 1; /*!< [1..1] Temperature Monitor Sensor Enable */ + __IOM uint8_t CMPEN : 1; /*!< [2..2] Comparator Enable */ + __IOM uint8_t TSNKEEP : 1; /*!< [3..3] Temperature Monitor Sensor Latch Control */ + uint8_t : 4; + } TEMPRCR_b; + }; + __IM uint8_t RESERVED182; + __IM uint16_t RESERVED183; + + union + { + __IOM uint8_t TEMPRLR; /*!< (@ 0x00000AE0) Temperature Monitor Reset Lock Register */ + + struct + { + __IOM uint8_t LOCK : 1; /*!< [0..0] Temperature Monitor Reset Control Register Lock */ + uint8_t : 7; + } TEMPRLR_b; + }; + __IM uint8_t RESERVED184; + __IM uint16_t RESERVED185; + __IM uint32_t RESERVED186[7]; + + union + { + __IOM uint8_t LDOSCR; /*!< (@ 0x00000B00) LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */ + __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */ + __IOM uint8_t LDOSTP2 : 1; /*!< [2..2] LDO2 Stop */ + __IOM uint8_t LDOSTP3 : 1; /*!< [3..3] LDO3 Stop */ + __IOM uint8_t LDOSTP4 : 1; /*!< [4..4] LDO4 Stop */ + __IOM uint8_t LDOSTP5 : 1; /*!< [5..5] LDO5 Stop */ + __IOM uint8_t LDOSTP6 : 1; /*!< [6..6] LDO6 Stop */ + __IOM uint8_t LDOSTP7 : 1; /*!< [7..7] LDO7 Stop */ + } LDOSCR_b; + }; + __IM uint8_t RESERVED187; + __IM uint16_t RESERVED188; + + union + { + __IOM uint8_t PLL1LDOCR; /*!< (@ 0x00000B04) PLL1-LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP : 1; /*!< [0..0] LDO Stop */ + __IOM uint8_t SKEEP : 1; /*!< [1..1] STBY Keep */ + uint8_t : 6; + } PLL1LDOCR_b; + }; + __IM uint8_t RESERVED189; + __IM uint16_t RESERVED190; + + union + { + __IOM uint8_t PLL2LDOCR; /*!< (@ 0x00000B08) PLL2-LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP : 1; /*!< [0..0] LDO Stop */ + __IOM uint8_t SKEEP : 1; /*!< [1..1] STBY Keep */ + uint8_t : 6; + } PLL2LDOCR_b; + }; + __IM uint8_t RESERVED191; + __IM uint16_t RESERVED192; + + union + { + __IOM uint8_t HOCOLDOCR; /*!< (@ 0x00000B0C) HOCO-LDO Control Register */ + + struct + { + __IOM uint8_t LDOSTP : 1; /*!< [0..0] LDO0 Stop */ + __IOM uint8_t SKEEP : 1; /*!< [1..1] STBY Keep */ + uint8_t : 6; + } HOCOLDOCR_b; + }; + __IM uint8_t RESERVED193; + __IM uint16_t RESERVED194; + + union + { + __IOM uint8_t MOMCR2; /*!< (@ 0x00000B10) Main Clock Oscillator Mode Oscillation Control + * Register 2 */ + + struct + { + __IOM uint8_t MOMODE : 1; /*!< [0..0] Main Clock Oscillator Mode Select */ + uint8_t : 7; + } MOMCR2_b; + }; + __IM uint8_t RESERVED195; + __IM uint16_t RESERVED196; + __IM uint32_t RESERVED197[3]; + + union + { + __IOM uint8_t LVD1FCR; /*!< (@ 0x00000B20) Voltage Monitor 1 Function Control Register */ + + struct + { + __IOM uint8_t RHSEL : 1; /*!< [0..0] Rise Hysteresis Select */ + uint8_t : 7; + } LVD1FCR_b; + }; + __IM uint8_t RESERVED198; + __IM uint16_t RESERVED199; + + union + { + __IOM uint8_t LVD2FCR; /*!< (@ 0x00000B24) Voltage Monitor 2 Function Control Register */ + + struct + { + __IOM uint8_t RHSEL : 1; /*!< [0..0] Rise Hysteresis Select */ + uint8_t : 7; + } LVD2FCR_b; + }; + __IM uint8_t RESERVED200; + __IM uint16_t RESERVED201; + + union + { + __IOM uint8_t LVD3FCR; /*!< (@ 0x00000B28) Voltage Monitor 3 Function Control Register */ + + struct + { + __IOM uint8_t RHSEL : 1; /*!< [0..0] Rise Hysteresis Select */ + uint8_t : 7; + } LVD3FCR_b; + }; + __IM uint8_t RESERVED202; + __IM uint16_t RESERVED203; + + union + { + __IOM uint8_t LVD4FCR; /*!< (@ 0x00000B2C) Voltage Monitor 4 Function Control Register */ + + struct + { + __IOM uint8_t RHSEL : 1; /*!< [0..0] Rise Hysteresis Select */ + uint8_t : 7; + } LVD4FCR_b; + }; + __IM uint8_t RESERVED204; + __IM uint16_t RESERVED205; + + union + { + __IOM uint8_t LVD5FCR; /*!< (@ 0x00000B30) Voltage Monitor 5 Function Control Register */ + + struct + { + __IOM uint8_t RHSEL : 1; /*!< [0..0] Rise Hysteresis Select */ + uint8_t : 7; + } LVD5FCR_b; + }; + __IM uint8_t RESERVED206; + __IM uint16_t RESERVED207; + + union + { + __IOM uint8_t PVDLR; /*!< (@ 0x00000B34) Voltage Monitor Lock Register */ + + struct + { + __IOM uint8_t LOCK : 1; /*!< [0..0] LOCK control */ + uint8_t : 7; + } PVDLR_b; + }; + __IM uint8_t RESERVED208; + __IM uint16_t RESERVED209; + __IM uint32_t RESERVED210[2]; + + union + { + __IOM uint8_t DPSIER4; /*!< (@ 0x00000B40) Deep Standby Interrupt Enable Register 4 */ + + struct + { + __IOM uint8_t DIRQ16E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ17E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ18E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ19E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ20E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ21E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ22E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ23E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER4_b; + }; + __IM uint8_t RESERVED211; + __IM uint16_t RESERVED212; + + union + { + __IOM uint8_t DPSIER5; /*!< (@ 0x00000B44) Deep Standby Interrupt Enable Register 5 */ + + struct + { + __IOM uint8_t DIRQ24E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ25E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ26E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ27E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ28E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ29E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ30E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ31E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER5_b; + }; + __IM uint8_t RESERVED213; + __IM uint16_t RESERVED214; + + union + { + __IOM uint8_t DPSIFR4; /*!< (@ 0x00000B48) Deep Standby Interrupt Flag Register 4 */ + + struct + { + __IOM uint8_t DIRQ16F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ17F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ18F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ19F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ20F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ21F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ22F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ23F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR4_b; + }; + __IM uint8_t RESERVED215; + __IM uint16_t RESERVED216; + + union + { + __IOM uint8_t DPSIFR5; /*!< (@ 0x00000B4C) Deep Standby Interrupt Flag Register 5 */ + + struct + { + __IOM uint8_t DIRQ24F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ25F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ26F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ27F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ28F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ29F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ30F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ31F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR5_b; + }; + __IM uint8_t RESERVED217; + __IM uint16_t RESERVED218; + + union + { + __IOM uint8_t DPSIEGR4; /*!< (@ 0x00000B50) Deep Standby Interrupt Edge Register 4 */ + + struct + { + __IOM uint8_t DIRQ24EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ25EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ26EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ27EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ28EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ29EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ30EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ31EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR4_b; + }; + __IM uint8_t RESERVED219; + __IM uint16_t RESERVED220; + __IM uint32_t RESERVED221[3]; + + union + { + __IOM uint8_t VBTSWMON; /*!< (@ 0x00000B60) LVDVBATSW control Monitor Register */ + + struct + { + __IOM uint8_t VLVLMON : 3; /*!< [2..0] VDETBAT Level Monitor */ + uint8_t : 1; + __IOM uint8_t VDETEMON : 1; /*!< [4..4] Voltage drop detection enable Monitor */ + uint8_t : 3; + } VBTSWMON_b; + }; + __IM uint8_t RESERVED222; + __IM uint16_t RESERVED223; + + union + { + __IOM uint8_t VBTSWSCR; /*!< (@ 0x00000B64) LVDVBATSW Start-up stable wait Control Register */ + + struct + { + __IOM uint8_t VBTSWE : 1; /*!< [0..0] LVDVBATSW output enable */ + uint8_t : 7; + } VBTSWSCR_b; + }; + __IM uint8_t RESERVED224; + __IM uint16_t RESERVED225; + __IM uint32_t RESERVED226[38]; + + union + { + __IOM uint8_t SOSCCR; /*!< (@ 0x00000C00) Sub-Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ + uint8_t : 7; + } SOSCCR_b; + }; + + union + { + __IOM uint8_t SOMCR; /*!< (@ 0x00000C01) Sub Clock Oscillator Mode Control Register */ + + struct + { + __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ + uint8_t : 4; + __IOM uint8_t SOSEL : 1; /*!< [6..6] Sub-Clock Oscillator Switching */ + uint8_t : 1; + } SOMCR_b; + }; + __IM uint16_t RESERVED227; + + union + { + __IOM uint8_t SOSTDCR; /*!< (@ 0x00000C04) Sub-clock Oscillation Stop Detection Control + * Register */ + + struct + { + __IOM uint8_t SOSTDIE : 1; /*!< [0..0] Sub-clock Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t SOSTDE : 1; /*!< [7..7] Sub-clock Oscillation Stop Detection Function Enable */ + } SOSTDCR_b; + }; + + union + { + __IOM uint8_t SOSTDSR; /*!< (@ 0x00000C05) Sub-clock Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t SOSTDF : 1; /*!< [0..0] Sub-clock Oscillation Stop Detection Flag */ + uint8_t : 7; + } SOSTDSR_b; + }; + __IM uint16_t RESERVED228; + __IM uint32_t RESERVED229[14]; + + union + { + __IOM uint8_t VBTBER; /*!< (@ 0x00000C40) VBATT Backup Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ + uint8_t : 4; + } VBTBER_b; + }; + __IM uint8_t RESERVED230; + __IM uint16_t RESERVED231; + __IM uint8_t RESERVED232; + + union + { + __IOM uint8_t VBTBPCR2; /*!< (@ 0x00000C45) VBATT Battery Power Supply Control Register 2 */ + + struct + { + __IOM uint8_t VDETLVL : 3; /*!< [2..0] VDETBAT Level Select */ + uint8_t : 1; + __IOM uint8_t VDETE : 1; /*!< [4..4] Voltage drop detection enable */ + uint8_t : 3; + } VBTBPCR2_b; + }; + + union + { + __IOM uint8_t VBTBPSR; /*!< (@ 0x00000C46) VBATT Battery Power Supply Status Register */ + + struct + { + __IOM uint8_t VBPORF : 1; /*!< [0..0] VBATT_POR Flag */ + uint8_t : 3; + __IOM uint8_t VBPORM : 1; /*!< [4..4] VBATT_POR Monitor */ + __IOM uint8_t BPWSWM : 1; /*!< [5..5] Battery Power Supply Switch Status Monitor */ + uint8_t : 2; + } VBTBPSR_b; + }; + __IM uint8_t RESERVED233; + + union + { + __IOM uint8_t VBTADSR; /*!< (@ 0x00000C48) VBATT Tamper detection Status Register */ + + struct + { + __IOM uint8_t VBTADF0 : 1; /*!< [0..0] VBATT Tamper Detection flag 0 */ + __IOM uint8_t VBTADF1 : 1; /*!< [1..1] VBATT Tamper Detection flag 1 */ + __IOM uint8_t VBTADF2 : 1; /*!< [2..2] VBATT Tamper Detection flag 2 */ + uint8_t : 5; + } VBTADSR_b; + }; + + union + { + __IOM uint8_t VBTADCR1; /*!< (@ 0x00000C49) VBATT Tamper detection Control Register 1 */ + + struct + { + __IOM uint8_t VBTADIE0 : 1; /*!< [0..0] VBATT Tamper Detection Interrupt Enable 0 */ + __IOM uint8_t VBTADIE1 : 1; /*!< [1..1] VBATT Tamper Detection Interrupt Enable 1 */ + __IOM uint8_t VBTADIE2 : 1; /*!< [2..2] VBATT Tamper Detection Interrupt Enable 2 */ + uint8_t : 1; + __IOM uint8_t VBTADCLE0 : 1; /*!< [4..4] VBATT Tamper Detection Backup Register Clear Enable 0 */ + __IOM uint8_t VBTADCLE1 : 1; /*!< [5..5] VBATT Tamper Detection Backup Register Clear Enable 1 */ + __IOM uint8_t VBTADCLE2 : 1; /*!< [6..6] VBATT Tamper Detection Backup Register Clear Enable 2 */ + uint8_t : 1; + } VBTADCR1_b; + }; + + union + { + __IOM uint8_t VBTADCR2; /*!< (@ 0x00000C4A) VBATT Tamper detection Control Register 2 */ + + struct + { + __IOM uint8_t VBRTCES0 : 1; /*!< [0..0] VBATT RTC Time Capture Event Source Select 0 */ + __IOM uint8_t VBRTCES1 : 1; /*!< [1..1] VBATT RTC Time Capture Event Source Select 1 */ + __IOM uint8_t VBRTCES2 : 1; /*!< [2..2] VBATT RTC Time Capture Event Source Select 2 */ + uint8_t : 5; + } VBTADCR2_b; + }; + __IM uint8_t RESERVED234; + + union + { + __IOM uint8_t VBTICTLR; /*!< (@ 0x00000C4C) VBATT Input Control Register */ + + struct + { + __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ + __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ + __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ + uint8_t : 5; + } VBTICTLR_b; + }; + + union + { + __IOM uint8_t VBTICTLR2; /*!< (@ 0x00000C4D) VBATT Input Control Register 2 */ + + struct + { + __IOM uint8_t VCH0NCE : 1; /*!< [0..0] VBATT CH0 Input Noise Canceler Enable */ + __IOM uint8_t VCH1NCE : 1; /*!< [1..1] VBATT CH1 Input Noise Canceler Enable */ + __IOM uint8_t VCH2NCE : 1; /*!< [2..2] VBATT CH2 Input Noise Canceler Enable */ + uint8_t : 1; + __IOM uint8_t VCH0EG : 1; /*!< [4..4] VBATT CH0 Input Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [5..5] VBATT CH1 Input Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [6..6] VBATT CH2 Input Edge Select */ + uint8_t : 1; + } VBTICTLR2_b; + }; + + union + { + __IOM uint8_t VBTIMONR; /*!< (@ 0x00000C4E) VBATT Input Monitor Register */ + + struct + { + __IOM uint8_t VCH0MON : 1; /*!< [0..0] VBATT CH0 Input monitor */ + __IOM uint8_t VCH1MON : 1; /*!< [1..1] VBATT CH1 Input monitor */ + __IOM uint8_t VCH2MON : 1; /*!< [2..2] VBATT CH2 Input monitor */ + uint8_t : 5; + } VBTIMONR_b; + }; + __IM uint8_t RESERVED235; + + union + { + __IOM uint8_t VBTNCWCR; /*!< (@ 0x00000C50) VBATT Noise Canceler Width Control Register */ + + struct + { + __IOM uint8_t VINCW : 3; /*!< [2..0] VBATT Input Noise Canceler Width select */ + uint8_t : 5; + } VBTNCWCR_b; + }; + __IM uint8_t RESERVED236; + __IM uint16_t RESERVED237; + + union + { + __IOM uint8_t VBTADCR3; /*!< (@ 0x00000C54) VBATT Tamper detection Control Register 3 */ + + struct + { + __IOM uint8_t VBTADZE0 : 1; /*!< [0..0] VBATT Tamper Detection Zeroization Enable 0 */ + __IOM uint8_t VBTADZE1 : 1; /*!< [1..1] VBATT Tamper Detection Zeroization Enable 1 */ + __IOM uint8_t VBTADZE2 : 1; /*!< [2..2] VBATT Tamper Detection Zeroization Enable 2 */ + uint8_t : 5; + } VBTADCR3_b; + }; + __IM uint8_t RESERVED238; + __IM uint16_t RESERVED239; + __IM uint32_t RESERVED240[42]; + + union + { + __IOM uint8_t VBTBKR[128]; /*!< (@ 0x00000D00) VBATT Backup Register [0..127] */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store + * data powered by VBATT.The value of this register is retained + * even when VCC is not powered but VBATT is powered.VBTBKR + * is initialized by VBATT selected voltage power-on-reset. */ + } VBTBKR_b[128]; + }; +} R_SYSTEM_Type; /*!< Size = 3456 (0xd80) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CAL) + */ + +typedef struct /*!< (@ 0x02C1EDA0) R_TSN_CAL Structure */ +{ + union + { + __IM uint32_t TSCDR; /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register */ + + struct + { + __IM uint32_t TSCDR : 32; /*!< [31..0] The 32 bit TSCDR register stores temperature sensor + * calibration converted value. */ + } TSCDR_b; + }; +} R_TSN_CAL_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CTRL) + */ + +typedef struct /*!< (@ 0x40235000) R_TSN_CTRL Structure */ +{ + union + { + __IOM uint8_t TSCR; /*!< (@ 0x00000000) Temperature Sensor Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t TSOE : 1; /*!< [4..4] Temperature Sensor Enable */ + uint8_t : 2; + __IOM uint8_t TSEN : 1; /*!< [7..7] Temperature Sensor Output Enable */ + } TSCR_b; + }; +} R_TSN_CTRL_Type; /*!< Size = 1 (0x1) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 Module (R_USB_FS0) + */ + +typedef struct /*!< (@ 0x40250000) R_USB_FS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 2; + __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */ + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + uint16_t : 1; + __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ + uint16_t : 1; + __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ + uint16_t : 5; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is + * used when switching from device B to device A while in + * OTG mode. If the HNPBTOA bit is 1, the internal function + * control keeps the suspended state until the HNP processing + * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is + * set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 4; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } DVCHGR_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate + * the USB address assigned by the host when the USBHS processed + * the SET_ADDRESS request successfully. */ + uint16_t : 1; + __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ + uint16_t : 4; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType + * value. */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount + * of data (maximum packet size) in payloads for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 2; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + + struct + { + __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ + uint16_t : 12; + } PIPESEL_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number + * for the selected pipe.Setting 0000b means unused pipe. */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + uint16_t : 1; + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to + * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes + * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and + * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to + * 64 bytes (040h) (Bits [8:7] are not provided.) */ + uint16_t : 3; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval + * error detection timing for the selected pipe in terms of + * frames, which is expressed as nth power of 2. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */ + + struct + { + __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */ + __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */ + __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ + __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */ + uint16_t : 1; + __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ + __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */ + __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */ + uint16_t : 6; + } USBBCCTRL0_b; + }; + __IM uint16_t RESERVED16; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */ + + struct + { + __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */ + uint16_t : 15; + } UCKSEL_b; + }; + __IM uint16_t RESERVED18; + __IM uint32_t RESERVED19; + + union + { + __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */ + + struct + { + __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */ + uint16_t : 6; + __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */ + uint16_t : 8; + } USBMC_b; + }; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */ + + struct + { + __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */ + __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */ + uint32_t : 28; + } PHYSLEW_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED23[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED25[5]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; + __IM uint32_t RESERVED26[165]; + + union + { + __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin + * Monitor Register */ + + struct + { + __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */ + __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */ + uint32_t : 1; + __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */ + __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */ + uint32_t : 11; + __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ + __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */ + uint32_t : 2; + __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal + * of the USB. */ + __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal + * of the USB. */ + uint32_t : 1; + __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the + * USB. */ + uint32_t : 8; + } DPUSR0R_FS_b; + }; + + union + { + __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt + * Register */ + + struct + { + __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */ + __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */ + uint32_t : 2; + __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */ + __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */ + uint32_t : 1; + __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */ + uint32_t : 8; + __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */ + __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */ + uint32_t : 2; + __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */ + __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */ + uint32_t : 1; + __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */ + uint32_t : 8; + } DPUSR1R_FS_b; + }; +} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */ + +/* =========================================================================================================================== */ +/* ================ R_VIN ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Video Input Module (R_VIN) + */ + +typedef struct /*!< (@ 0x40347400) R_VIN Structure */ +{ + union + { + __IOM uint32_t MC; /*!< (@ 0x00000000) Main Control Register */ + + struct + { + __IOM uint32_t ME : 1; /*!< [0..0] Module Enable */ + __IOM uint32_t BPS : 1; /*!< [1..1] Color Space Conversion Bypass Mode */ + uint32_t : 1; + __IOM uint32_t IM : 2; /*!< [4..3] Interlace Mode */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [6..6] Endian Type */ + uint32_t : 7; + __IOM uint32_t DC : 2; /*!< [15..14] Dithering Mode Control */ + __IOM uint32_t INF : 3; /*!< [18..16] Input Interface Format */ + uint32_t : 1; + __IOM uint32_t LUTE : 1; /*!< [20..20] Lookup Table Enable */ + uint32_t : 1; + __OM uint32_t ST : 1; /*!< [22..22] Initialization control at STartup */ + uint32_t : 1; + __IOM uint32_t DC2 : 1; /*!< [24..24] Dithering mode Control 2 */ + __IOM uint32_t YUV444 : 1; /*!< [25..25] YUV444 conversion */ + __IOM uint32_t SCLE : 1; /*!< [26..26] This bit is used to enable or disable scaling by the + * UDS. */ + uint32_t : 1; + __IOM uint32_t CLP : 2; /*!< [29..28] Pixel Data Clipping */ + uint32_t : 2; + } MC_b; + }; + + union + { + __IM uint32_t MS; /*!< (@ 0x00000004) Module Status Register */ + + struct + { + __IM uint32_t CA : 1; /*!< [0..0] Video Capture Active Status */ + __IM uint32_t AV : 1; /*!< [1..1] Active Video Status */ + __IM uint32_t FS : 1; /*!< [2..2] Field Status */ + __IM uint32_t FBS : 2; /*!< [4..3] Frame Buffer Status */ + uint32_t : 11; + __IM uint32_t MA : 1; /*!< [16..16] External frame Memory capture Active status */ + uint32_t : 2; + __IM uint32_t FMS : 2; /*!< [20..19] External Frame Memory buffer Status */ + uint32_t : 11; + } MS_b; + }; + + union + { + __IOM uint32_t FC; /*!< (@ 0x00000008) Frame Capture Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC : 1; /*!< [1..1] Continuous Frame Capture Mode */ + uint32_t : 30; + } FC_b; + }; + + union + { + __IOM uint32_t SLPRC; /*!< (@ 0x0000000C) Start Line Pre-Clip Register */ + + struct + { + __IOM uint32_t SLPRC : 12; /*!< [11..0] Start Line PRe-Clip */ + uint32_t : 20; + } SLPRC_b; + }; + + union + { + __IOM uint32_t ELPRC; /*!< (@ 0x00000010) End Line Pre-Clip Register */ + + struct + { + __IOM uint32_t ELPRC : 12; /*!< [11..0] End Line PRe-Clip */ + uint32_t : 20; + } ELPRC_b; + }; + + union + { + __IOM uint32_t SPPRC; /*!< (@ 0x00000014) Start Pixel Pre-Clip Register */ + + struct + { + __IOM uint32_t SPPRC : 12; /*!< [11..0] Start Pixel Pre-Clip */ + uint32_t : 20; + } SPPRC_b; + }; + + union + { + __IOM uint32_t EPPRC; /*!< (@ 0x00000018) End Pixel Pre-Clip Register */ + + struct + { + __IOM uint32_t EPPRC : 12; /*!< [11..0] End Pixel PRe-Clip */ + uint32_t : 20; + } EPPRC_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CSI_IFMD; /*!< (@ 0x00000020) CSI2 Interface Mode Register */ + + struct + { + __IOM uint32_t VC_SEL : 4; /*!< [3..0] Virtual Channel SELect */ + uint32_t : 4; + __IOM uint32_t DT : 6; /*!< [13..8] Data Type select */ + uint32_t : 11; + __IOM uint32_t DES0 : 1; /*!< [25..25] Data Extension Select */ + uint32_t : 6; + } CSI_IFMD_b; + }; + + union + { + __IOM uint32_t CSIFLD; /*!< (@ 0x00000024) Field detection control Register */ + + struct + { + __IOM uint32_t FLD_EN : 1; /*!< [0..0] FieLD detect ENable */ + uint32_t : 3; + __IOM uint32_t FLD_SEL : 2; /*!< [5..4] even FieLD DETect SELect */ + uint32_t : 10; + __IOM uint32_t FLD_NUM : 1; /*!< [16..16] even FieLD NUMber setting */ + uint32_t : 15; + } CSIFLD_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t IS; /*!< (@ 0x0000002C) Image Stride Register */ + + struct + { + __IOM uint32_t IS : 13; /*!< [12..0] Image Stride (Setting unit: pixel) */ + uint32_t : 19; + } IS_b; + }; + + union + { + __IOM uint32_t MB1; /*!< (@ 0x00000030) Memory Base 1 Register */ + + struct + { + uint32_t : 7; + __IOM uint32_t MB1 : 25; /*!< [31..7] Memory Base Address 1 */ + } MB1_b; + }; + + union + { + __IOM uint32_t MB2; /*!< (@ 0x00000034) Memory Base 2 Register */ + + struct + { + uint32_t : 7; + __IOM uint32_t MB2 : 25; /*!< [31..7] Memory Base Address 2 */ + } MB2_b; + }; + + union + { + __IOM uint32_t MB3; /*!< (@ 0x00000038) Memory Base 3 Register */ + + struct + { + uint32_t : 7; + __IOM uint32_t MB3 : 25; /*!< [31..7] Memory Base Address 3 */ + } MB3_b; + }; + + union + { + __IM uint32_t LC; /*!< (@ 0x0000003C) Line Count Register */ + + struct + { + __IM uint32_t LC : 12; /*!< [11..0] Line Count */ + uint32_t : 20; + } LC_b; + }; + + union + { + __IOM uint32_t IE; /*!< (@ 0x00000040) Interrupt Enable Register */ + + struct + { + __IOM uint32_t FOE : 1; /*!< [0..0] FIFO Overflow Interrupt Enable */ + __IOM uint32_t EFE : 1; /*!< [1..1] End of Frame Interrupt Enable */ + __IOM uint32_t SIE : 1; /*!< [2..2] Scanline Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t FIE : 1; /*!< [4..4] Field Interrupt Enable */ + __IOM uint32_t FME : 1; /*!< [5..5] Frame Memory write completion interrupt Enable */ + uint32_t : 2; + __IOM uint32_t PRCLIPHEE : 1; /*!< [8..8] PRCLIPH Error interrupt Enable */ + __IOM uint32_t PRCLIPVEE : 1; /*!< [9..9] PRCLIPV Error interrupt Enable */ + uint32_t : 4; + __IOM uint32_t ROE : 1; /*!< [14..14] Response Overflow interrupt Enable */ + __IOM uint32_t AREE : 1; /*!< [15..15] Axi Resp Error interrupt Enable */ + __IOM uint32_t VRE : 1; /*!< [16..16] VSYNC Deasserting Detect Interrupt Enable */ + __IOM uint32_t VFE : 1; /*!< [17..17] Vsync asserting detect interrupt Enable */ + uint32_t : 13; + __IOM uint32_t FIE2 : 1; /*!< [31..31] Field Interrupt Enable 2 */ + } IE_b; + }; + + union + { + __IOM uint32_t INTS; /*!< (@ 0x00000044) Interrupt Status Register */ + + struct + { + __IOM uint32_t FOS : 1; /*!< [0..0] FIFO Overflow Interrupt Status */ + __IOM uint32_t EFS : 1; /*!< [1..1] End of Frame Interrupt Status */ + __IOM uint32_t SIS : 1; /*!< [2..2] Scanline Interrupt Status */ + uint32_t : 1; + __IOM uint32_t FIS : 1; /*!< [4..4] Field Interrupt Status */ + __IOM uint32_t FMS : 1; /*!< [5..5] Frame Memory write completion interrupt Status */ + uint32_t : 2; + __IOM uint32_t PRCLIPHES : 1; /*!< [8..8] PRCLIPH Error interrupt Status */ + __IOM uint32_t PRCLIPVES : 1; /*!< [9..9] PRCLIPV Error interrupt Status */ + uint32_t : 4; + __IOM uint32_t ROS : 1; /*!< [14..14] Response Overflow interrupt Status */ + __IOM uint32_t ARES : 1; /*!< [15..15] Axi Resp Error interrupt Status */ + __IOM uint32_t VRS : 1; /*!< [16..16] VSYNC Deasserting Detect Interrupt Status */ + __IOM uint32_t VFS : 1; /*!< [17..17] VSYNC Asserting Detect Interrupt Status */ + uint32_t : 13; + __IOM uint32_t FIS2 : 1; /*!< [31..31] Field Interrupt Status 2 */ + } INTS_b; + }; + + union + { + __IOM uint32_t SI; /*!< (@ 0x00000048) Scanline Interrupt Register */ + + struct + { + __IOM uint32_t SI : 12; /*!< [11..0] Scanline Interrupt Setting */ + uint32_t : 20; + } SI_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t MTCSTOP; /*!< (@ 0x00000054) AXI transfer stop control register */ + + struct + { + __IOM uint32_t STOPREQ : 1; /*!< [0..0] axi forced STOP REQuest */ + __IM uint32_t STOPACK : 1; /*!< [1..1] for axi forced STOP request, ACKnowledgement */ + uint32_t : 14; + __IM uint32_t OUTSTAND : 6; /*!< [21..16] OUTSTANDing current number */ + uint32_t : 10; + } MTCSTOP_b; + }; + + union + { + __IOM uint32_t DMR; /*!< (@ 0x00000058) Data Mode Register */ + + struct + { + __IOM uint32_t DTMD : 2; /*!< [1..0] Data Conversion Mode */ + __IOM uint32_t ABIT : 1; /*!< [2..2] Alpha Bit */ + uint32_t : 1; + __IOM uint32_t BPSM : 1; /*!< [4..4] Output Data Byte Swap Mode */ + uint32_t : 3; + __IOM uint32_t EXRGB : 1; /*!< [8..8] Extension RGB Conversion Mode */ + uint32_t : 2; + __IOM uint32_t YC_THR : 1; /*!< [11..11] YC Data Through Mode */ + __IOM uint32_t YMODE : 3; /*!< [14..12] YC Data Transfer Mode */ + uint32_t : 9; + __IOM uint32_t A8BIT : 8; /*!< [31..24] Alpha 8 */ + } DMR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t UVAOF; /*!< (@ 0x00000060) UV Address Offset Register */ + + struct + { + uint32_t : 7; + __IOM uint32_t UVAOF : 25; /*!< [31..7] UV Data Address Offset */ + } UVAOF_b; + }; + __IM uint32_t RESERVED4[7]; + + union + { + __IOM uint32_t UDS_CTRL; /*!< (@ 0x00000080) Scaling Control Registers */ + + struct + { + uint32_t : 16; + __IOM uint32_t NE_BCB : 1; /*!< [16..16] B/Cb Interpolation Method When Bilinear/Nearest Neighbor + * Interpolation is Selected */ + __IOM uint32_t NE_GY : 1; /*!< [17..17] G/Y Interpolation Method When Bilinear/Nearest Neighbor + * Interpolation is Selected */ + __IOM uint32_t NE_RCR : 1; /*!< [18..18] R/Cr Interpolation Method When Bilinear/Nearest Neighbor + * Interpolation is Selected */ + uint32_t : 1; + __IOM uint32_t BC : 1; /*!< [20..20] Pixel Component Interpolation Method at Scale-Up/Down */ + uint32_t : 7; + __IOM uint32_t BLADV : 1; /*!< [28..28] BiLinear or nearest neighbor interpolation characteristic + * ADVanced mode */ + uint32_t : 1; + __IOM uint32_t AMD : 1; /*!< [30..30] Advanced MoDe: Pixel Count at Scale-Up */ + uint32_t : 1; + } UDS_CTRL_b; + }; + + union + { + __IOM uint32_t UDS_SCALE; /*!< (@ 0x00000084) Scaling Factor Registers */ + + struct + { + __IOM uint32_t VFRAC : 12; /*!< [11..0] Multiplier (Fractional Part) of Vertical Scaling Factor */ + __IOM uint32_t VMANT : 4; /*!< [15..12] Multiplier (Integral Part) of Vertical Scaling Factor */ + __IOM uint32_t HFRAC : 12; /*!< [27..16] Multiplier (Fractional Part) of Horizontal Scaling + * Factor */ + __IOM uint32_t HMANT : 4; /*!< [31..28] Multiplier (Integral Part) of Horizontal Scaling Factor */ + } UDS_SCALE_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t UDS_PASS_BWIDTH; /*!< (@ 0x00000090) Passband Registers */ + + struct + { + __IOM uint32_t BWIDTH_V : 7; /*!< [6..0] Vertical Signal Passband at Image Scale-Up/Down */ + uint32_t : 9; + __IOM uint32_t BWIDTH_H : 7; /*!< [22..16] Horizontal Signal Passband at Image Scale-Up/Down */ + uint32_t : 9; + } UDS_PASS_BWIDTH_b; + }; + __IM uint32_t RESERVED6[4]; + + union + { + __IOM uint32_t UDS_CLIP_SIZE; /*!< (@ 0x000000A4) UDS Output Size Clipping Registers */ + + struct + { + __IOM uint32_t CL_VSIZE : 12; /*!< [11..0] Clipping Size of Vertical Pixel Count after Scale-Up/-Down */ + uint32_t : 4; + __IOM uint32_t CL_HSIZE : 12; /*!< [27..16] Clipping Size of Horizontal Pixel Count after Scale-Up/-Down */ + uint32_t : 4; + } UDS_CLIP_SIZE_b; + }; + __IM uint32_t RESERVED7[22]; + + union + { + __IOM uint32_t LUTP; /*!< (@ 0x00000100) Lookup Table Pointer Register */ + + struct + { + __IOM uint32_t LTCRPR : 10; /*!< [9..0] Lookup Table Cr Pointer */ + __IOM uint32_t LTCBPR : 10; /*!< [19..10] Lookup Table Cb Pointer */ + __IOM uint32_t LTYPR : 10; /*!< [29..20] Lookup Table Y Pointer */ + uint32_t : 2; + } LUTP_b; + }; + + union + { + __IOM uint32_t LUTD; /*!< (@ 0x00000104) Lookup Table Data Register */ + + struct + { + __IOM uint32_t LTCRDT : 8; /*!< [7..0] Lookup Table Cr Data */ + __IOM uint32_t LTCBDT : 8; /*!< [15..8] Lookup Table Cb Data */ + __IOM uint32_t LTYDT : 8; /*!< [23..16] Lookup Table Y Data */ + uint32_t : 8; + } LUTD_b; + }; + __IM uint32_t RESERVED8[72]; + + union + { + __IOM uint32_t YCCR1; /*!< (@ 0x00000228) RGB to Y Calculation Setting Register 1 */ + + struct + { + __IOM uint32_t YCLRP : 13; /*!< [12..0] R Multiplication Coefficient for Y Calculation */ + uint32_t : 19; + } YCCR1_b; + }; + + union + { + __IOM uint32_t YCCR2; /*!< (@ 0x0000022C) RGB to Y Calculation Setting Register 2 */ + + struct + { + __IOM uint32_t YCLGP : 13; /*!< [12..0] G Multiplication Coefficient for Y Calculation */ + uint32_t : 3; + __IOM uint32_t YCLBP : 13; /*!< [28..16] B Multiplication Coefficient for Y Calculation */ + uint32_t : 3; + } YCCR2_b; + }; + + union + { + __IOM uint32_t YCCR3; /*!< (@ 0x00000230) RGB to Y Calculation Setting Register 3 */ + + struct + { + __IOM uint32_t YCLAP : 12; /*!< [11..0] Y Calculation Data Normalized Additional Value */ + uint32_t : 11; + __IOM uint32_t YCLHEN : 1; /*!< [23..23] Y Calculation Shift Down Result Round-Off Enable */ + __IOM uint32_t YCLSFT : 5; /*!< [28..24] Y Calculation Shift Down Volume */ + uint32_t : 3; + } YCCR3_b; + }; + + union + { + __IOM uint32_t CBCCR1; /*!< (@ 0x00000234) RGB to Cb Calculation Setting Register 1 */ + + struct + { + __IOM uint32_t CBCLRP : 13; /*!< [12..0] R Multiplication Coefficient for Cb Calculation */ + uint32_t : 19; + } CBCCR1_b; + }; + + union + { + __IOM uint32_t CBCCR2; /*!< (@ 0x00000238) RGB to Cb Calculation Setting Register 2 */ + + struct + { + __IOM uint32_t CBCLGP : 13; /*!< [12..0] G Multiplication Coefficient for Cb Calculation */ + uint32_t : 3; + __IOM uint32_t CBCLBP : 13; /*!< [28..16] B Multiplication Coefficient for Cb Calculation */ + uint32_t : 3; + } CBCCR2_b; + }; + + union + { + __IOM uint32_t CBCCR3; /*!< (@ 0x0000023C) RGB to Cb Calculation Setting Register 3 */ + + struct + { + __IOM uint32_t CBCLAP : 12; /*!< [11..0] Cb Calculation Data Normalized Additional Value */ + uint32_t : 11; + __IOM uint32_t CBCLHEN : 1; /*!< [23..23] Cb Calculation Shift Down Result Round-Off Enable */ + __IOM uint32_t CBCLSFT : 5; /*!< [28..24] Cb Calculation Shift Down Volume */ + uint32_t : 3; + } CBCCR3_b; + }; + + union + { + __IOM uint32_t CRCCR1; /*!< (@ 0x00000240) RGB to Cr Calculation Setting Register 1 */ + + struct + { + __IOM uint32_t CRCLRP : 13; /*!< [12..0] R Multiplication Coefficient for Cr Calculation */ + uint32_t : 19; + } CRCCR1_b; + }; + + union + { + __IOM uint32_t CRCCR2; /*!< (@ 0x00000244) RGB to Cr Calculation Setting Register 2 */ + + struct + { + __IOM uint32_t CRCLGP : 13; /*!< [12..0] G Multiplication Coefficient for Cr Calculation */ + uint32_t : 3; + __IOM uint32_t CRCLBP : 13; /*!< [28..16] B Multiplication Coefficient for Cr Calculation */ + uint32_t : 3; + } CRCCR2_b; + }; + + union + { + __IOM uint32_t CRCCR3; /*!< (@ 0x00000248) RGB to Cr Calculation Setting Register 3 */ + + struct + { + __IOM uint32_t CRCLAP : 12; /*!< [11..0] Cr Calculation Data Normalized Additional Value */ + uint32_t : 11; + __IOM uint32_t CRCLHEN : 1; /*!< [23..23] Cr Calculation Shift Down Result Round-Off Enable */ + __IOM uint32_t CRCLSFT : 5; /*!< [28..24] Cr Calculation Shift Down Volume */ + uint32_t : 3; + } CRCCR3_b; + }; + __IM uint32_t RESERVED9[45]; + + union + { + __IOM uint32_t CSCE1; /*!< (@ 0x00000300) YC to RGB Calculation Setting Extension Register + * 1 */ + + struct + { + __IOM uint32_t YMUL2 : 14; /*!< [13..0] Y Multiplication Coefficient 2 for RGB Calculation */ + uint32_t : 2; + __IOM uint32_t ROUND : 1; /*!< [16..16] ROUND off enable */ + uint32_t : 15; + } CSCE1_b; + }; + + union + { + __IOM uint32_t CSCE2; /*!< (@ 0x00000304) YC to RGB Calculation Setting Extension Register + * 2 */ + + struct + { + __IOM uint32_t CSUB2 : 12; /*!< [11..0] CbCr Subtraction Coefficient 2 for RGB Calculation */ + uint32_t : 4; + __IOM uint32_t YSUB2 : 12; /*!< [27..16] Y Subtraction Coefficient 2 for RGB Calculation */ + uint32_t : 4; + } CSCE2_b; + }; + + union + { + __IOM uint32_t CSCE3; /*!< (@ 0x00000308) YC to RGB Calculation Setting Extension Register + * 3 */ + + struct + { + __IOM uint32_t GCRMUL2 : 14; /*!< [13..0] Cr Multiplication Coefficient 2 for G Calculation */ + uint32_t : 2; + __IOM uint32_t RCRMUL2 : 14; /*!< [29..16] Cr Multiplication Coefficient 2 for R Calculation */ + uint32_t : 2; + } CSCE3_b; + }; + + union + { + __IOM uint32_t CSCE4; /*!< (@ 0x0000030C) YC to RGB Calculation Setting Extension Register + * 4 */ + + struct + { + __IOM uint32_t BCBMUL2 : 14; /*!< [13..0] Cb Multiplication Coefficient 2 for B Calculation */ + uint32_t : 2; + __IOM uint32_t GCBMUL2 : 14; /*!< [29..16] Cb Multiplication Coefficient 2 for G Calculation */ + uint32_t : 2; + } CSCE4_b; + }; +} R_VIN_Type; /*!< Size = 784 (0x310) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer (R_WDT) + */ + +typedef struct /*!< (@ 0x40202600) R_WDT Structure */ +{ + union + { + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + + struct + { + __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter + * of the WDT. */ + } WDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } WDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_WDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief R_CACHE (R_CACHE) + */ + +typedef struct /*!< (@ 0x4001C000) R_CACHE Structure */ +{ + union + { + __IOM uint32_t CCACTL; /*!< (@ 0x00000000) C-Cache Control Register */ + + struct + { + __IOM uint32_t ENC : 1; /*!< [0..0] C-Cache Enable */ + uint32_t : 7; + __IOM uint32_t FC : 1; /*!< [8..8] C-Cache flush bit */ + __IOM uint32_t WB : 1; /*!< [9..9] C-cache write back */ + uint32_t : 22; + } CCACTL_b; + }; + + union + { + __IOM uint32_t CCAFCT; /*!< (@ 0x00000004) C-Cache Flush Control Register */ + + struct + { + __IOM uint32_t FC : 1; /*!< [0..0] C-Cache Flush */ + __IOM uint32_t WB : 1; /*!< [1..1] C-Cache write back */ + uint32_t : 30; + } CCAFCT_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CCAWTA; /*!< (@ 0x0000000C) C-Cache Write Attribute */ + + struct + { + __IOM uint32_t WT : 1; /*!< [0..0] C-Cache write through */ + __IOM uint32_t WA : 1; /*!< [1..1] C-Cache write allocation */ + uint32_t : 30; + } CCAWTA_b; + }; + + union + { + __IOM uint32_t CCAEDST; /*!< (@ 0x00000010) C-Cache Error Detection Status */ + + struct + { + __IOM uint32_t ESD0 : 1; /*!< [0..0] C-Cache data error status 0 */ + __IOM uint32_t ESD1 : 1; /*!< [1..1] C-Cache data error status 1 */ + __IOM uint32_t ESTC : 1; /*!< [2..2] C-Cache Tag clean line invalidate status */ + __IOM uint32_t ESTD : 1; /*!< [3..3] C-Cache Tag dirty line invalidate status */ + __IOM uint32_t EST2 : 1; /*!< [4..4] C-Cache Tag 2bit error status */ + uint32_t : 27; + } CCAEDST_b; + }; + + union + { + __IOM uint32_t CCATAA; /*!< (@ 0x00000014) C-Cache Test Access Address */ + + struct + { + uint32_t : 2; + __IOM uint32_t OFFSET : 3; /*!< [4..2] address offset */ + __IOM uint32_t ENTRY : 7; /*!< [11..5] address entry */ + uint32_t : 4; + __IOM uint32_t TARGET : 3; /*!< [18..16] access target */ + uint32_t : 4; + __IOM uint32_t RW : 1; /*!< [23..23] read write */ + uint32_t : 6; + __IOM uint32_t WAY : 2; /*!< [31..30] address way */ + } CCATAA_b; + }; + + union + { + __IOM uint32_t CCATAD; /*!< (@ 0x00000018) C-Cache Test Access Data */ + + struct + { + __IOM uint32_t DATA : 32; /*!< [31..0] Cache data */ + } CCATAD_b; + }; + __IM uint32_t RESERVED1[9]; + + union + { + __IOM uint32_t SCACTL; /*!< (@ 0x00000040) S-Cache Control Register */ + + struct + { + __IOM uint32_t ENS : 1; /*!< [0..0] S-Cache Enable */ + uint32_t : 7; + __IOM uint32_t FS : 1; /*!< [8..8] S-Cache flush bit */ + __IOM uint32_t WB : 1; /*!< [9..9] S-cache write back */ + uint32_t : 22; + } SCACTL_b; + }; + + union + { + __IOM uint32_t SCAFCT; /*!< (@ 0x00000044) S-Cache Flush Control Register */ + + struct + { + __IOM uint32_t FS : 1; /*!< [0..0] S-Cache Flush */ + __IOM uint32_t WB : 1; /*!< [1..1] S-Cache write back */ + uint32_t : 30; + } SCAFCT_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t SCAWTA; /*!< (@ 0x0000004C) S-Cache Write Attribute */ + + struct + { + __IOM uint32_t WT : 1; /*!< [0..0] S-Cache write through */ + __IOM uint32_t WA : 1; /*!< [1..1] S-Cache write allocation */ + uint32_t : 30; + } SCAWTA_b; + }; + + union + { + __IOM uint32_t SCAEDST; /*!< (@ 0x00000050) S-Cache Error Detection Status */ + + struct + { + __IOM uint32_t ESD0 : 1; /*!< [0..0] S-Cache data error status 0 */ + __IOM uint32_t ESD1 : 1; /*!< [1..1] S-Cache data error status 1 */ + __IOM uint32_t ESTC : 1; /*!< [2..2] S-Cache Tag clean line invalidate status */ + __IOM uint32_t ESTD : 1; /*!< [3..3] S-Cache Tag dirty line invalidate status */ + __IOM uint32_t EST2 : 1; /*!< [4..4] S-Cache Tag 2bit error status */ + uint32_t : 27; + } SCAEDST_b; + }; + + union + { + __IOM uint32_t SCATAA; /*!< (@ 0x00000054) S-Cache Test Access Address */ + + struct + { + uint32_t : 2; + __IOM uint32_t OFFSET : 3; /*!< [4..2] address offset */ + __IOM uint32_t ENTRY : 7; /*!< [11..5] address entry */ + uint32_t : 4; + __IOM uint32_t TARGET : 3; /*!< [18..16] access target */ + uint32_t : 4; + __IOM uint32_t RW : 1; /*!< [23..23] read write */ + uint32_t : 6; + __IOM uint32_t WAY : 2; /*!< [31..30] address way */ + } SCATAA_b; + }; + + union + { + __IOM uint32_t SCATAD; /*!< (@ 0x00000058) C-Cache Test Access Data */ + + struct + { + __IOM uint32_t DATA : 32; /*!< [31..0] Cache data */ + } SCATAD_b; + }; + __IM uint32_t RESERVED3[105]; + + union + { + __IOM uint32_t CAPOAD; /*!< (@ 0x00000200) Cache Parity Error Operation After Detection + * Register */ + + struct + { + __IOM uint32_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint32_t : 2; + __IOM uint32_t ECCMOD1 : 1; /*!< [3..3] ECC enable */ + __IOM uint32_t E1STSEN : 1; /*!< [4..4] ECC 1-Bit Error Information Update Enable */ + uint32_t : 27; + } CAPOAD_b; + }; + + union + { + __IOM uint32_t CAPRCR; /*!< (@ 0x00000204) Cache Protection Register */ + + struct + { + __IOM uint32_t PRCR : 1; /*!< [0..0] Register Write Control */ + __IOM uint32_t KW : 7; /*!< [7..1] Write key code */ + uint32_t : 24; + } CAPRCR_b; + }; +} R_CACHE_Type; /*!< Size = 520 (0x208) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU System Security Control Unit (R_CPSCU) + */ + +typedef struct /*!< (@ 0x40008000) R_CPSCU Structure */ +{ + union + { + __IOM uint32_t CSAR; /*!< (@ 0x00000000) Cache Security Attribution Register */ + + struct + { + __IOM uint32_t CACHESA : 1; /*!< [0..0] Security Attributes of Registers for Cache Control */ + __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration */ + __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error */ + uint32_t : 29; + } CSAR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t SRAMSAR; /*!< (@ 0x00000010) SRAM Security Attribution Register */ + + struct + { + __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] SRAM0 Register Security Attribution */ + __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] SRAM1 Register Security Attribution */ + __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] SRAM2 Register Security Attribution */ + __IOM uint32_t SRAMSA3 : 1; /*!< [3..3] SRAM3 Register Security Attribution */ + uint32_t : 4; + __IOM uint32_t SRAMWTSA : 1; /*!< [8..8] Security attribution for SRAMWTSC */ + uint32_t : 23; + } SRAMSAR_b; + }; + + union + { + __IOM uint32_t STBRAMSAR; /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register */ + + struct + { + __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM */ + uint32_t : 28; + } STBRAMSAR_b; + }; + __IM uint32_t RESERVED1[6]; + + union + { + __IOM uint32_t DTCSAR; /*!< (@ 0x00000030) DTC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DTCSTSA0 : 1; /*!< [0..0] DTC0 Security Attribution */ + uint32_t : 15; + __IOM uint32_t DTCSTSA1 : 1; /*!< [16..16] DTC1 Security Attribution */ + uint32_t : 15; + } DTCSAR_b; + }; + + union + { + __IOM uint32_t DMACSAR; /*!< (@ 0x00000034) DMAC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DMASTSA0 : 1; /*!< [0..0] DMAC0 DMAST Security Attribution */ + uint32_t : 15; + __IOM uint32_t DMASTSA1 : 1; /*!< [16..16] DMAC1 DMAST Security Attribution */ + uint32_t : 15; + } DMACSAR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t ICUSARA; /*!< (@ 0x00000040) Interrupt Controller Unit Security Attribution + * Register A */ + + struct + { + __IOM uint32_t SAIRQCR0 : 1; /*!< [0..0] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR1 : 1; /*!< [1..1] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR2 : 1; /*!< [2..2] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR3 : 1; /*!< [3..3] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR4 : 1; /*!< [4..4] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR5 : 1; /*!< [5..5] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR6 : 1; /*!< [6..6] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR7 : 1; /*!< [7..7] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR8 : 1; /*!< [8..8] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR9 : 1; /*!< [9..9] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR10 : 1; /*!< [10..10] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR11 : 1; /*!< [11..11] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR12 : 1; /*!< [12..12] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR13 : 1; /*!< [13..13] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR14 : 1; /*!< [14..14] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR15 : 1; /*!< [15..15] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR16 : 1; /*!< [16..16] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR17 : 1; /*!< [17..17] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR18 : 1; /*!< [18..18] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR19 : 1; /*!< [19..19] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR20 : 1; /*!< [20..20] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR21 : 1; /*!< [21..21] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR22 : 1; /*!< [22..22] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR23 : 1; /*!< [23..23] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR24 : 1; /*!< [24..24] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR25 : 1; /*!< [25..25] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR26 : 1; /*!< [26..26] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR27 : 1; /*!< [27..27] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR28 : 1; /*!< [28..28] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR29 : 1; /*!< [29..29] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR30 : 1; /*!< [30..30] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR31 : 1; /*!< [31..31] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + } ICUSARA_b; + }; + + union + { + __IOM uint32_t ICUSARB; /*!< (@ 0x00000044) Interrupt Controller Unit Security Attribution + * Register B */ + + struct + { + __IOM uint32_t SANMI0 : 1; /*!< [0..0] Security Attributes of registers */ + __IOM uint32_t SANMI1 : 1; /*!< [1..1] Security Attributes of registers */ + __IOM uint32_t SANMI2 : 1; /*!< [2..2] Security Attributes of registers */ + uint32_t : 29; + } ICUSARB_b; + }; + + union + { + __IOM uint32_t ICUSARC; /*!< (@ 0x00000048) ICU Security Attribution Register C */ + + struct + { + __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel */ + uint32_t : 24; + } ICUSARC_b; + }; + + union + { + __IOM uint32_t ICUSARD; /*!< (@ 0x0000004C) ICU Security Attribution Register D */ + + struct + { + __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0 */ + uint32_t : 31; + } ICUSARD_b; + }; + + union + { + __IOM uint32_t ICUSARE; /*!< (@ 0x00000050) Interrupt Controller Unit Security Attribution + * Register E */ + + struct + { + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security attributes of registers for WUPEN0.b16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b19 */ + __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security attributes of registers for WUPEN0.b20 */ + uint32_t : 3; + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security attributes of registers for WUPEN0.b24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security attributes of registers for WUPEN0.b25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security attributes of registers for WUPEN0.b27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security attributes of registers for WUPEN0.b28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security attributes of registers for WUPEN0.b29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security attributes of registers for WUPEN0.b30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security attributes of registers for WUPEN0.b31 */ + } ICUSARE_b; + }; + + union + { + __IOM uint32_t ICUSARF; /*!< (@ 0x00000054) Interrupt Controller Unit Security Attribution + * Register F */ + + struct + { + __IOM uint32_t SAAGT3UDWUP : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0 */ + __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ + __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ + __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b3 */ + uint32_t : 3; + __IOM uint32_t SASOSCWUP : 1; /*!< [7..7] Security attributes of registers for WUPEN1.b7 */ + __IOM uint32_t SAULP0UWUP : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b8 */ + __IOM uint32_t SAULP0AWUP : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b9 */ + __IOM uint32_t SAULP0BWUP : 1; /*!< [10..10] Security attributes of registers for WUPEN1.b10 */ + __IOM uint32_t SAI3CWUP : 1; /*!< [11..11] Security attributes of registers for WUPEN1.b11 */ + __IOM uint32_t SAULP1UWUP : 1; /*!< [12..12] Security attributes of registers for WUPEN1.b12 */ + __IOM uint32_t SAULP1AWUP : 1; /*!< [13..13] Security attributes of registers for WUPEN1.b13 */ + __IOM uint32_t SAULP1BWUP : 1; /*!< [14..14] Security attributes of registers for WUPEN1.b14 */ + __IOM uint32_t SAPDMWUP : 1; /*!< [15..15] Security attributes of registers for WUPEN1.b15 */ + uint32_t : 16; + } ICUSARF_b; + }; + __IM uint32_t RESERVED3[6]; + + union + { + __IOM uint32_t ICUSARG; /*!< (@ 0x00000070) Interrupt Controller Unit Security Attribution + * Register G */ + + struct + { + __IOM uint32_t SAIELSR0 : 1; /*!< [0..0] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR1 : 1; /*!< [1..1] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR2 : 1; /*!< [2..2] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR3 : 1; /*!< [3..3] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR4 : 1; /*!< [4..4] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR5 : 1; /*!< [5..5] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR6 : 1; /*!< [6..6] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR7 : 1; /*!< [7..7] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR8 : 1; /*!< [8..8] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR9 : 1; /*!< [9..9] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR10 : 1; /*!< [10..10] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR11 : 1; /*!< [11..11] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR12 : 1; /*!< [12..12] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR13 : 1; /*!< [13..13] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR14 : 1; /*!< [14..14] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR15 : 1; /*!< [15..15] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR16 : 1; /*!< [16..16] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR17 : 1; /*!< [17..17] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR18 : 1; /*!< [18..18] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR19 : 1; /*!< [19..19] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR20 : 1; /*!< [20..20] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR21 : 1; /*!< [21..21] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR22 : 1; /*!< [22..22] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR23 : 1; /*!< [23..23] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR24 : 1; /*!< [24..24] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR25 : 1; /*!< [25..25] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR26 : 1; /*!< [26..26] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR27 : 1; /*!< [27..27] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR28 : 1; /*!< [28..28] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR29 : 1; /*!< [29..29] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR30 : 1; /*!< [30..30] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR31 : 1; /*!< [31..31] Security attributes of registers for ICU0 event link + * setting0 */ + } ICUSARG_b; + }; + + union + { + __IOM uint32_t ICUSARH; /*!< (@ 0x00000074) Interrupt Controller Unit Security Attribution + * Register H */ + + struct + { + __IOM uint32_t SAIELSR32 : 1; /*!< [0..0] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR33 : 1; /*!< [1..1] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR34 : 1; /*!< [2..2] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR35 : 1; /*!< [3..3] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR36 : 1; /*!< [4..4] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR37 : 1; /*!< [5..5] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR38 : 1; /*!< [6..6] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR39 : 1; /*!< [7..7] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR40 : 1; /*!< [8..8] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR41 : 1; /*!< [9..9] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR42 : 1; /*!< [10..10] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR43 : 1; /*!< [11..11] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR44 : 1; /*!< [12..12] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR45 : 1; /*!< [13..13] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR46 : 1; /*!< [14..14] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR47 : 1; /*!< [15..15] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR48 : 1; /*!< [16..16] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR49 : 1; /*!< [17..17] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR50 : 1; /*!< [18..18] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR51 : 1; /*!< [19..19] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR52 : 1; /*!< [20..20] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR53 : 1; /*!< [21..21] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR54 : 1; /*!< [22..22] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR55 : 1; /*!< [23..23] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR56 : 1; /*!< [24..24] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR57 : 1; /*!< [25..25] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR58 : 1; /*!< [26..26] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR59 : 1; /*!< [27..27] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR60 : 1; /*!< [28..28] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR61 : 1; /*!< [29..29] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR62 : 1; /*!< [30..30] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR63 : 1; /*!< [31..31] Security attributes of registers for ICU0 event link + * setting1 */ + } ICUSARH_b; + }; + + union + { + __IOM uint32_t ICUSARI; /*!< (@ 0x00000078) Interrupt Controller Unit Security Attribution + * Register I */ + + struct + { + __IOM uint32_t SAIELSR64 : 1; /*!< [0..0] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR65 : 1; /*!< [1..1] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR66 : 1; /*!< [2..2] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR67 : 1; /*!< [3..3] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR68 : 1; /*!< [4..4] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR69 : 1; /*!< [5..5] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR70 : 1; /*!< [6..6] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR71 : 1; /*!< [7..7] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR72 : 1; /*!< [8..8] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR73 : 1; /*!< [9..9] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR74 : 1; /*!< [10..10] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR75 : 1; /*!< [11..11] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR76 : 1; /*!< [12..12] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR77 : 1; /*!< [13..13] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR78 : 1; /*!< [14..14] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR79 : 1; /*!< [15..15] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR80 : 1; /*!< [16..16] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR81 : 1; /*!< [17..17] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR82 : 1; /*!< [18..18] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR83 : 1; /*!< [19..19] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR84 : 1; /*!< [20..20] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR85 : 1; /*!< [21..21] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR86 : 1; /*!< [22..22] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR87 : 1; /*!< [23..23] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR88 : 1; /*!< [24..24] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR89 : 1; /*!< [25..25] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR90 : 1; /*!< [26..26] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR91 : 1; /*!< [27..27] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR92 : 1; /*!< [28..28] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR93 : 1; /*!< [29..29] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR94 : 1; /*!< [30..30] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR95 : 1; /*!< [31..31] Security attributes of registers for ICU0 event link + * setting2 */ + } ICUSARI_b; + }; + + union + { + __IOM uint32_t ICUSARJ; /*!< (@ 0x0000007C) Interrupt Controller Unit Security Attribution + * Register J */ + + struct + { + __IOM uint32_t SAIELSR0 : 1; /*!< [0..0] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR1 : 1; /*!< [1..1] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR2 : 1; /*!< [2..2] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR3 : 1; /*!< [3..3] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR4 : 1; /*!< [4..4] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR5 : 1; /*!< [5..5] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR6 : 1; /*!< [6..6] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR7 : 1; /*!< [7..7] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR8 : 1; /*!< [8..8] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR9 : 1; /*!< [9..9] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR10 : 1; /*!< [10..10] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR11 : 1; /*!< [11..11] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR12 : 1; /*!< [12..12] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR13 : 1; /*!< [13..13] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR14 : 1; /*!< [14..14] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR15 : 1; /*!< [15..15] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR16 : 1; /*!< [16..16] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR17 : 1; /*!< [17..17] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR18 : 1; /*!< [18..18] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR19 : 1; /*!< [19..19] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR20 : 1; /*!< [20..20] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR21 : 1; /*!< [21..21] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR22 : 1; /*!< [22..22] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR23 : 1; /*!< [23..23] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR24 : 1; /*!< [24..24] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR25 : 1; /*!< [25..25] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR26 : 1; /*!< [26..26] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR27 : 1; /*!< [27..27] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR28 : 1; /*!< [28..28] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR29 : 1; /*!< [29..29] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR30 : 1; /*!< [30..30] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR31 : 1; /*!< [31..31] Security attributes of registers for ICU1 event link + * setting0 */ + } ICUSARJ_b; + }; + + union + { + __IOM uint32_t ICUSARK; /*!< (@ 0x00000080) Interrupt Controller Unit Security Attribution + * Register K */ + + struct + { + __IOM uint32_t SAIELSR32 : 1; /*!< [0..0] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR33 : 1; /*!< [1..1] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR34 : 1; /*!< [2..2] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR35 : 1; /*!< [3..3] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR36 : 1; /*!< [4..4] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR37 : 1; /*!< [5..5] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR38 : 1; /*!< [6..6] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR39 : 1; /*!< [7..7] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR40 : 1; /*!< [8..8] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR41 : 1; /*!< [9..9] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR42 : 1; /*!< [10..10] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR43 : 1; /*!< [11..11] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR44 : 1; /*!< [12..12] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR45 : 1; /*!< [13..13] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR46 : 1; /*!< [14..14] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR47 : 1; /*!< [15..15] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR48 : 1; /*!< [16..16] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR49 : 1; /*!< [17..17] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR50 : 1; /*!< [18..18] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR51 : 1; /*!< [19..19] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR52 : 1; /*!< [20..20] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR53 : 1; /*!< [21..21] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR54 : 1; /*!< [22..22] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR55 : 1; /*!< [23..23] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR56 : 1; /*!< [24..24] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR57 : 1; /*!< [25..25] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR58 : 1; /*!< [26..26] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR59 : 1; /*!< [27..27] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR60 : 1; /*!< [28..28] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR61 : 1; /*!< [29..29] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR62 : 1; /*!< [30..30] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR63 : 1; /*!< [31..31] Security attributes of registers for ICU1 event link + * setting1 */ + } ICUSARK_b; + }; + + union + { + __IOM uint32_t ICUSARL; /*!< (@ 0x00000084) Interrupt Controller Unit Security Attribution + * Register L */ + + struct + { + __IOM uint32_t SAIELSR64 : 1; /*!< [0..0] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR65 : 1; /*!< [1..1] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR66 : 1; /*!< [2..2] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR67 : 1; /*!< [3..3] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR68 : 1; /*!< [4..4] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR69 : 1; /*!< [5..5] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR70 : 1; /*!< [6..6] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR71 : 1; /*!< [7..7] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR72 : 1; /*!< [8..8] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR73 : 1; /*!< [9..9] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR74 : 1; /*!< [10..10] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR75 : 1; /*!< [11..11] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR76 : 1; /*!< [12..12] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR77 : 1; /*!< [13..13] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR78 : 1; /*!< [14..14] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR79 : 1; /*!< [15..15] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR80 : 1; /*!< [16..16] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR81 : 1; /*!< [17..17] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR82 : 1; /*!< [18..18] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR83 : 1; /*!< [19..19] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR84 : 1; /*!< [20..20] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR85 : 1; /*!< [21..21] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR86 : 1; /*!< [22..22] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR87 : 1; /*!< [23..23] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR88 : 1; /*!< [24..24] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR89 : 1; /*!< [25..25] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR90 : 1; /*!< [26..26] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR91 : 1; /*!< [27..27] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR92 : 1; /*!< [28..28] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR93 : 1; /*!< [29..29] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR94 : 1; /*!< [30..30] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR95 : 1; /*!< [31..31] Security attributes of registers for ICU1 event link + * setting2 */ + } ICUSARL_b; + }; + __IM uint32_t RESERVED4[30]; + + union + { + __IOM uint32_t BUSSARA; /*!< (@ 0x00000100) Bus Security Attribution Register A */ + + struct + { + __IOM uint32_t BUSSA0 : 1; /*!< [0..0] Bus Security Attribution A0 */ + uint32_t : 31; + } BUSSARA_b; + }; + + union + { + __IOM uint32_t BUSSARB; /*!< (@ 0x00000104) Bus Security Attribution Register B */ + + struct + { + __IOM uint32_t BUSSB0 : 1; /*!< [0..0] Bus Security Attribution B0 */ + uint32_t : 31; + } BUSSARB_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t BUSSARC; /*!< (@ 0x00000110) Bus Security Attribution Register C */ + + struct + { + __IOM uint32_t BUSSC0 : 1; /*!< [0..0] Bus Security Attribution C0 */ + uint32_t : 31; + } BUSSARC_b; + }; + + union + { + __IOM uint32_t BUSPARC; /*!< (@ 0x00000114) Bus Privileged Attribution Register C */ + + struct + { + __IOM uint32_t BUSPA0 : 1; /*!< [0..0] External bus controller privilege attribution */ + uint32_t : 31; + } BUSPARC_b; + }; + __IM uint32_t RESERVED6[2]; + + union + { + __IM uint32_t NMISR; /*!< (@ 0x00000120) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint32_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Status Flag */ + __IM uint32_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Status Flag */ + __IM uint32_t PVD1ST : 1; /*!< [2..2] Voltage Monitor 1 Interrupt Status Flag */ + __IM uint32_t PVD2ST : 1; /*!< [3..3] Voltage Monitor 2 Interrupt Status Flag */ + uint32_t : 1; + __IM uint32_t SOSTST : 1; /*!< [5..5] Sub Oscillation Stop Detection Interrupt Status Flag */ + __IM uint32_t OSTST : 1; /*!< [6..6] Main Clock Oscillation Stop Detection Interrupt Status + * Flag */ + __IM uint32_t NMIST : 1; /*!< [7..7] NMI Pin Interrupt Status Flag */ + uint32_t : 4; + __IM uint32_t BUSST : 1; /*!< [12..12] Bus Error Interrupt Status Flag */ + __IM uint32_t CMST : 1; /*!< [13..13] Common Memory Error Interrupt Status Flag */ + __IM uint32_t LMST : 1; /*!< [14..14] Local Memory Error Interrupt Status Flag */ + __IM uint32_t LUST : 1; /*!< [15..15] LockUp Error Interrupt Status Flag */ + __IM uint32_t FPUEXCST : 1; /*!< [16..16] FPU Exception Interrupt Status Flag */ + __IM uint32_t MRCRDST : 1; /*!< [17..17] MRAM MRC read Error Interrupt Status Flag */ + __IM uint32_t MRERDST : 1; /*!< [18..18] MRAM MRE read Error Interrupt Status Flag */ + uint32_t : 1; + __IM uint32_t IPCST : 1; /*!< [20..20] IPC NMI CPU mutual Interrupt Status Flag */ + uint32_t : 11; + } NMISR_b; + }; + __IM uint32_t RESERVED7[3]; + + union + { + __IOM uint32_t MMPUSARA; /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution + * Register A */ + + struct + { + __IOM uint32_t MMPUASA0 : 1; /*!< [0..0] MMPUA0 Security Attribution */ + __IOM uint32_t MMPUASA1 : 1; /*!< [1..1] MMPUA1 Security Attribution */ + __IOM uint32_t MMPUASA2 : 1; /*!< [2..2] MMPUA2 Security Attribution */ + __IOM uint32_t MMPUASA3 : 1; /*!< [3..3] MMPUA3 Security Attribution */ + __IOM uint32_t MMPUASA4 : 1; /*!< [4..4] MMPUA4 Security Attribution */ + __IOM uint32_t MMPUASA5 : 1; /*!< [5..5] MMPUA5 Security Attribution */ + __IOM uint32_t MMPUASA6 : 1; /*!< [6..6] MMPUA6 Security Attribution */ + __IOM uint32_t MMPUASA7 : 1; /*!< [7..7] MMPUA7 Security Attribution */ + __IOM uint32_t MMPUASA8 : 1; /*!< [8..8] MMPUA8 Security Attribution */ + __IOM uint32_t MMPUASA9 : 1; /*!< [9..9] MMPUA9 Security Attribution */ + __IOM uint32_t MMPUASA10 : 1; /*!< [10..10] MMPUA10 Security Attribution */ + __IOM uint32_t MMPUASA11 : 1; /*!< [11..11] MMPUA11 Security Attribution */ + __IOM uint32_t MMPUASA12 : 1; /*!< [12..12] MMPUA12 Security Attribution */ + __IOM uint32_t MMPUASA13 : 1; /*!< [13..13] MMPUA13 Security Attribution */ + __IOM uint32_t MMPUASA14 : 1; /*!< [14..14] MMPUA14 Security Attribution */ + __IOM uint32_t MMPUASA15 : 1; /*!< [15..15] MMPUA15 Security Attribution */ + __IOM uint32_t MMPUASA16 : 1; /*!< [16..16] MMPUA16 Security Attribution */ + __IOM uint32_t MMPUASA17 : 1; /*!< [17..17] MMPUA17 Security Attribution */ + __IOM uint32_t MMPUASA18 : 1; /*!< [18..18] MMPUA18 Security Attribution */ + __IOM uint32_t MMPUASA19 : 1; /*!< [19..19] MMPUA19 Security Attribution */ + __IOM uint32_t MMPUASA20 : 1; /*!< [20..20] MMPUA20 Security Attribution */ + __IOM uint32_t MMPUASA21 : 1; /*!< [21..21] MMPUA21 Security Attribution */ + __IOM uint32_t MMPUASA22 : 1; /*!< [22..22] MMPUA22 Security Attribution */ + __IOM uint32_t MMPUASA23 : 1; /*!< [23..23] MMPUA23 Security Attribution */ + __IOM uint32_t MMPUASA24 : 1; /*!< [24..24] MMPUA24 Security Attribution */ + __IOM uint32_t MMPUASA25 : 1; /*!< [25..25] MMPUA25 Security Attribution */ + __IOM uint32_t MMPUASA26 : 1; /*!< [26..26] MMPUA26 Security Attribution */ + __IOM uint32_t MMPUASA27 : 1; /*!< [27..27] MMPUA27 Security Attribution */ + __IOM uint32_t MMPUASA28 : 1; /*!< [28..28] MMPUA28 Security Attribution */ + __IOM uint32_t MMPUASA29 : 1; /*!< [29..29] MMPUA29 Security Attribution */ + __IOM uint32_t MMPUASA30 : 1; /*!< [30..30] MMPUA30 Security Attribution */ + __IOM uint32_t MMPUASA31 : 1; /*!< [31..31] MMPUA31 Security Attribution */ + } MMPUSARA_b; + }; + + union + { + __IOM uint32_t MMPUSARB; /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution + * Register B */ + + struct + { + __IOM uint32_t MMPUBSA0 : 1; /*!< [0..0] MMPUB0 Security Attribution */ + __IOM uint32_t MMPUBSA1 : 1; /*!< [1..1] MMPUB1 Security Attribution */ + __IOM uint32_t MMPUBSA2 : 1; /*!< [2..2] MMPUB2 Security Attribution */ + __IOM uint32_t MMPUBSA3 : 1; /*!< [3..3] MMPUB3 Security Attribution */ + __IOM uint32_t MMPUBSA4 : 1; /*!< [4..4] MMPUB4 Security Attribution */ + __IOM uint32_t MMPUBSA5 : 1; /*!< [5..5] MMPUB5 Security Attribution */ + __IOM uint32_t MMPUBSA6 : 1; /*!< [6..6] MMPUB6 Security Attribution */ + __IOM uint32_t MMPUBSA7 : 1; /*!< [7..7] MMPUB7 Security Attribution */ + __IOM uint32_t MMPUBSA8 : 1; /*!< [8..8] MMPUB8 Security Attribution */ + __IOM uint32_t MMPUBSA9 : 1; /*!< [9..9] MMPUB9 Security Attribution */ + __IOM uint32_t MMPUBSA10 : 1; /*!< [10..10] MMPUB10 Security Attribution */ + __IOM uint32_t MMPUBSA11 : 1; /*!< [11..11] MMPUB11 Security Attribution */ + __IOM uint32_t MMPUBSA12 : 1; /*!< [12..12] MMPUB12 Security Attribution */ + __IOM uint32_t MMPUBSA13 : 1; /*!< [13..13] MMPUB13 Security Attribution */ + __IOM uint32_t MMPUBSA14 : 1; /*!< [14..14] MMPUB14 Security Attribution */ + __IOM uint32_t MMPUBSA15 : 1; /*!< [15..15] MMPUB15 Security Attribution */ + __IOM uint32_t MMPUBSA16 : 1; /*!< [16..16] MMPUB16 Security Attribution */ + __IOM uint32_t MMPUBSA17 : 1; /*!< [17..17] MMPUB17 Security Attribution */ + __IOM uint32_t MMPUBSA18 : 1; /*!< [18..18] MMPUB18 Security Attribution */ + __IOM uint32_t MMPUBSA19 : 1; /*!< [19..19] MMPUB19 Security Attribution */ + __IOM uint32_t MMPUBSA20 : 1; /*!< [20..20] MMPUB20 Security Attribution */ + __IOM uint32_t MMPUBSA21 : 1; /*!< [21..21] MMPUB21 Security Attribution */ + __IOM uint32_t MMPUBSA22 : 1; /*!< [22..22] MMPUB22 Security Attribution */ + __IOM uint32_t MMPUBSA23 : 1; /*!< [23..23] MMPUB23 Security Attribution */ + __IOM uint32_t MMPUBSA24 : 1; /*!< [24..24] MMPUB24 Security Attribution */ + __IOM uint32_t MMPUBSA25 : 1; /*!< [25..25] MMPUB25 Security Attribution */ + __IOM uint32_t MMPUBSA26 : 1; /*!< [26..26] MMPUB26 Security Attribution */ + __IOM uint32_t MMPUBSA27 : 1; /*!< [27..27] MMPUB27 Security Attribution */ + __IOM uint32_t MMPUBSA28 : 1; /*!< [28..28] MMPUB28 Security Attribution */ + __IOM uint32_t MMPUBSA29 : 1; /*!< [29..29] MMPUB29 Security Attribution */ + __IOM uint32_t MMPUBSA30 : 1; /*!< [30..30] MMPUB30 Security Attribution */ + __IOM uint32_t MMPUBSA31 : 1; /*!< [31..31] MMPUB31 Security Attribution */ + } MMPUSARB_b; + }; + __IM uint32_t RESERVED8[14]; + + union + { + __IOM uint32_t CPUSAR; /*!< (@ 0x00000170) CPU Security Attribution Register */ + + struct + { + __IOM uint32_t CPUSA0 : 1; /*!< [0..0] CPU Security Attribution 0 */ + __IOM uint32_t CPUSA1 : 1; /*!< [1..1] CPU Security Attribution 1 */ + uint32_t : 30; + } CPUSAR_b; + }; + __IM uint32_t RESERVED9[3]; + + union + { + __IOM uint32_t DEBUGSAR; /*!< (@ 0x00000180) Debug Security Attribution Register */ + + struct + { + __IOM uint32_t DBGSA0 : 1; /*!< [0..0] Debug Security Attribution 0 */ + uint32_t : 31; + } DEBUGSAR_b; + }; + __IM uint32_t RESERVED10[7]; + + union + { + __IOM uint32_t DMACCHSAR; /*!< (@ 0x000001A0) DMAC channel Security Attribution Register */ + + struct + { + __IOM uint32_t SADMAC00 : 1; /*!< [0..0] Security attributes of registers for DMAC0 channel */ + __IOM uint32_t SADMAC01 : 1; /*!< [1..1] Security attributes of registers for DMAC0 channel */ + __IOM uint32_t SADMAC02 : 1; /*!< [2..2] Security attributes of registers for DMAC0 channel */ + __IOM uint32_t SADMAC03 : 1; /*!< [3..3] Security attributes of registers for DMAC0 channel */ + __IOM uint32_t SADMAC04 : 1; /*!< [4..4] Security attributes of registers for DMAC0 channel */ + __IOM uint32_t SADMAC05 : 1; /*!< [5..5] Security attributes of registers for DMAC0 channel */ + __IOM uint32_t SADMAC06 : 1; /*!< [6..6] Security attributes of registers for DMAC0 channel */ + __IOM uint32_t SADMAC07 : 1; /*!< [7..7] Security attributes of registers for DMAC0 channel */ + uint32_t : 8; + __IOM uint32_t SADMAC10 : 1; /*!< [16..16] Security attributes of registers for DMAC1 channel */ + __IOM uint32_t SADMAC11 : 1; /*!< [17..17] Security attributes of registers for DMAC1 channel */ + __IOM uint32_t SADMAC12 : 1; /*!< [18..18] Security attributes of registers for DMAC1 channel */ + __IOM uint32_t SADMAC13 : 1; /*!< [19..19] Security attributes of registers for DMAC1 channel */ + __IOM uint32_t SADMAC14 : 1; /*!< [20..20] Security attributes of registers for DMAC1 channel */ + __IOM uint32_t SADMAC15 : 1; /*!< [21..21] Security attributes of registers for DMAC1 channel */ + __IOM uint32_t SADMAC16 : 1; /*!< [22..22] Security attributes of registers for DMAC1 channel */ + __IOM uint32_t SADMAC17 : 1; /*!< [23..23] Security attributes of registers for DMAC1 channel */ + uint32_t : 8; + } DMACCHSAR_b; + }; + __IM uint32_t RESERVED11[3]; + + union + { + __IOM uint32_t CPUDSAR; /*!< (@ 0x000001B0) CPU Debug Security Attribution Register */ + + struct + { + __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0 */ + uint32_t : 31; + } CPUDSAR_b; + }; + __IM uint32_t RESERVED12[15]; + + union + { + __IOM uint32_t DMACCHPAR; /*!< (@ 0x000001F0) DMA Channel Privilege Attribution Register */ + + struct + { + __IOM uint32_t PADMAC00 : 1; /*!< [0..0] Privilege attributes of outputs and registers for DMAC0 + * channel */ + __IOM uint32_t PADMAC01 : 1; /*!< [1..1] Privilege attributes of outputs and registers for DMAC0 + * channel */ + __IOM uint32_t PADMAC02 : 1; /*!< [2..2] Privilege attributes of outputs and registers for DMAC0 + * channel */ + __IOM uint32_t PADMAC03 : 1; /*!< [3..3] Privilege attributes of outputs and registers for DMAC0 + * channel */ + __IOM uint32_t PADMAC04 : 1; /*!< [4..4] Privilege attributes of outputs and registers for DMAC0 + * channel */ + __IOM uint32_t PADMAC05 : 1; /*!< [5..5] Privilege attributes of outputs and registers for DMAC0 + * channel */ + __IOM uint32_t PADMAC06 : 1; /*!< [6..6] Privilege attributes of outputs and registers for DMAC0 + * channel */ + __IOM uint32_t PADMAC07 : 1; /*!< [7..7] Privilege attributes of outputs and registers for DMAC0 + * channel */ + uint32_t : 8; + __IOM uint32_t PADMAC10 : 1; /*!< [16..16] Privilege attributes of outputs and registers for DMAC1 + * channel */ + __IOM uint32_t PADMAC11 : 1; /*!< [17..17] Privilege attributes of outputs and registers for DMAC1 + * channel */ + __IOM uint32_t PADMAC12 : 1; /*!< [18..18] Privilege attributes of outputs and registers for DMAC1 + * channel */ + __IOM uint32_t PADMAC13 : 1; /*!< [19..19] Privilege attributes of outputs and registers for DMAC1 + * channel */ + __IOM uint32_t PADMAC14 : 1; /*!< [20..20] Privilege attributes of outputs and registers for DMAC1 + * channel */ + __IOM uint32_t PADMAC15 : 1; /*!< [21..21] Privilege attributes of outputs and registers for DMAC1 + * channel */ + __IOM uint32_t PADMAC16 : 1; /*!< [22..22] Privilege attributes of outputs and registers for DMAC1 + * channel */ + __IOM uint32_t PADMAC17 : 1; /*!< [23..23] Privilege attributes of outputs and registers for DMAC1 + * channel */ + uint32_t : 8; + } DMACCHPAR_b; + }; + __IM uint32_t RESERVED13[131]; + + union + { + __IOM uint32_t SRAMSABAR0; /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure */ + uint32_t : 11; + } SRAMSABAR0_b; + }; + + union + { + __IOM uint32_t SRAMSABAR1; /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure */ + uint32_t : 11; + } SRAMSABAR1_b; + }; + + union + { + __IOM uint32_t SRAMSABAR2; /*!< (@ 0x00000408) SRAM Security Attribute Boundary Address Register */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure */ + uint32_t : 11; + } SRAMSABAR2_b; + }; + + union + { + __IOM uint32_t SRAMSABAR3; /*!< (@ 0x0000040C) SRAM Security Attribute Boundary Address Register */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure */ + uint32_t : 11; + } SRAMSABAR3_b; + }; + __IM uint32_t RESERVED14[60]; + + union + { + __IOM uint32_t CACHESAR; /*!< (@ 0x00000500) Cache Security Attribution Register */ + + struct + { + __IOM uint32_t CACHESA : 1; /*!< [0..0] Security attributes of registers for CACHE Control */ + uint32_t : 1; + __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security attributes of registers for CACHE Error */ + uint32_t : 29; + } CACHESAR_b; + }; + + union + { + __IOM uint32_t TCMSAR; /*!< (@ 0x00000504) TCM Security Attribution Register */ + + struct + { + __IOM uint32_t TCMSA : 1; /*!< [0..0] Security attributes of registers for TCM Control */ + uint32_t : 31; + } TCMSAR_b; + }; + + union + { + __IOM uint32_t TCMSABARC; /*!< (@ 0x00000508) TCM Security Attribute Boundary Address Register */ + + struct + { + uint32_t : 13; + __IOM uint32_t TCMSABA : 6; /*!< [18..13] Boundary address between secure and non-secure. (Start + * address of non-secure region) */ + uint32_t : 13; + } TCMSABARC_b; + }; + + union + { + __IOM uint32_t TCMSABARS; /*!< (@ 0x0000050C) TCM Security Attribute Boundary Address Register */ + + struct + { + uint32_t : 13; + __IOM uint32_t TCMSABA : 6; /*!< [18..13] Boundary address between secure and non-secure. (Start + * address of non-secure region) */ + uint32_t : 13; + } TCMSABARS_b; + }; + + union + { + __IOM uint32_t SRAMESAR; /*!< (@ 0x00000510) SRAM ECC region Security Attribute Register */ + + struct + { + __IOM uint32_t SRAMESA : 1; /*!< [0..0] ECC region Security Attribution */ + uint32_t : 31; + } SRAMESAR_b; + }; + __IM uint32_t RESERVED15[59]; + + union + { + __IOM uint32_t TEVTRCR; /*!< (@ 0x00000600) Trusted Event Route Control Register */ + + struct + { + __IOM uint32_t TEVTE : 1; /*!< [0..0] Trusted Event Route Control Register for ELC */ + __IOM uint32_t TEVTEICU0 : 1; /*!< [1..1] Trusted Event Route Control Register for ICU0 */ + __IOM uint32_t TEVTEICU1 : 1; /*!< [2..2] Trusted Event Route Control Register for ICU1 */ + uint32_t : 29; + } TEVTRCR_b; + }; + __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint32_t IPCSAR; /*!< (@ 0x00000610) IPC Security Attribution Register */ + + struct + { + __IOM uint32_t SAIPCSEM0 : 1; /*!< [0..0] Security attributes of registers for IPCSEMn */ + __IOM uint32_t SAIPCSEM1 : 1; /*!< [1..1] Security attributes of registers for IPCSEMn */ + uint32_t : 6; + __IOM uint32_t SAIPCNMI0 : 1; /*!< [8..8] Security attributes of the registers */ + __IOM uint32_t SAIPCNMI1 : 1; /*!< [9..9] Security attributes of the registers */ + uint32_t : 6; + __IOM uint32_t SAIPCIR0 : 1; /*!< [16..16] Security attributes of registers for IPC0STA0, IPC0ISET0, + * IPC0TXD0, IPC0RXD0 and IPC0CLR0 */ + __IOM uint32_t SAIPCIR1 : 1; /*!< [17..17] Security attributes of registers for IPC0STA1, IPC0ISET1, + * IPC0TXD1, IPC0RXD1 and IPC0CLR1 */ + __IOM uint32_t SAIPCIR2 : 1; /*!< [18..18] Security attributes of registers for IPC1STA0, IPC1ISET0, + * IPC1TXD0, IPC1RXD0 and IPC1CLR0 */ + __IOM uint32_t SAIPCIR3 : 1; /*!< [19..19] Security attributes of registers for IPC1STA1, IPC1ISET1, + * IPC1TXD1, IPC1RXD1 and IPC1CLR1 */ + uint32_t : 12; + } IPCSAR_b; + }; + + union + { + __IOM uint32_t IPCPAR; /*!< (@ 0x00000614) IPC Privileged Attribution Register */ + + struct + { + __IOM uint32_t PAIPCSEM0 : 1; /*!< [0..0] Privileged attributes of registers for IPCSEMn */ + __IOM uint32_t PAIPCSEM1 : 1; /*!< [1..1] Privileged attributes of registers for IPCSEMn */ + uint32_t : 6; + __IOM uint32_t PAIPCNMI0 : 1; /*!< [8..8] Privileged attributes of registers */ + __IOM uint32_t PAIPCNMI1 : 1; /*!< [9..9] Privileged attributes of registers */ + uint32_t : 6; + __IOM uint32_t PAIPCIR0 : 1; /*!< [16..16] Privileged attributes of registers for IPC0STA0, IPC0ISET0, + * IPC0TXD0, IPC0RXD0 and IPC0CLR0 */ + __IOM uint32_t PAIPCIR1 : 1; /*!< [17..17] Privileged attributes of registers for IPC0STA1, IPC0ISET1, + * IPC0TXD1, IPC0RXD1 and IPC0CLR1 */ + __IOM uint32_t PAIPCIR2 : 1; /*!< [18..18] Privileged attributes of registers for IPC1STA0, IPC1ISET0, + * IPC1TXD0, IPC1RXD0 and IPC1CLR0 */ + __IOM uint32_t PAIPCIR3 : 1; /*!< [19..19] Privileged attributes of registers for IPC1STA1, IPC1ISET1, + * IPC1TXD1, IPC1RXD1 and IPC1CLR1 */ + uint32_t : 12; + } IPCPAR_b; + }; +} R_CPSCU_Type; /*!< Size = 1560 (0x618) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC_B0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief 12-bit A/D Converter (R_ADC_B0) + */ + +typedef struct /*!< (@ 0x40338000) R_ADC_B0 Structure */ +{ + union + { + __IOM uint32_t ADCLKENR; /*!< (@ 0x00000000) A/D Conversion Clock Enable Register */ + + struct + { + __IOM uint32_t CLKEN : 1; /*!< [0..0] ADCLK Operating Enable bit */ + uint32_t : 31; + } ADCLKENR_b; + }; + + union + { + __IM uint32_t ADCLKSR; /*!< (@ 0x00000004) A/D Conversion Clock Status Register */ + + struct + { + __IM uint32_t CLKSR : 1; /*!< [0..0] ADCLK status bit */ + uint32_t : 31; + } ADCLKSR_b; + }; + + union + { + __IOM uint32_t ADCLKCR; /*!< (@ 0x00000008) A/D Conversion Clock Control Register */ + + struct + { + __IOM uint32_t CLKSEL : 2; /*!< [1..0] ADCLK Clock Source Select */ + uint32_t : 14; + __IOM uint32_t DIVR : 3; /*!< [18..16] Clock Division Ratio Select */ + uint32_t : 13; + } ADCLKCR_b; + }; + + union + { + __IOM uint32_t ADSYCR; /*!< (@ 0x0000000C) A/D Converter Synchronous Operation Control Register */ + + struct + { + __IOM uint32_t ADSYCYC : 11; /*!< [10..0] A/D Converter Synchronous Operation Period Cycle */ + uint32_t : 5; + __IOM uint32_t ADSYDIS0 : 1; /*!< [16..16] ADC0 Synchronous Operation Select */ + __IOM uint32_t ADSYDIS1 : 1; /*!< [17..17] ADC1 Synchronous Operation Select */ + uint32_t : 14; + } ADSYCR_b; + }; + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t ADERINTCR; /*!< (@ 0x00000020) A/D Conversion Error Interrupt Enable Register */ + + struct + { + __IOM uint32_t ADEIE0 : 1; /*!< [0..0] ADC0 A/D Conversion Error Interrupt Enable */ + __IOM uint32_t ADEIE1 : 1; /*!< [1..1] ADC1 A/D Conversion Error Interrupt Enable */ + uint32_t : 30; + } ADERINTCR_b; + }; + + union + { + __IOM uint32_t ADOVFINTCR; /*!< (@ 0x00000024) A/D Conversion Overflow Interrupt Enable Register */ + + struct + { + __IOM uint32_t ADOVFIE0 : 1; /*!< [0..0] ADC0 A/D Conversion Overflow Interrupt Enable */ + __IOM uint32_t ADOVFIE1 : 1; /*!< [1..1] ADC1 A/D Conversion Overflow Interrupt Enable */ + uint32_t : 30; + } ADOVFINTCR_b; + }; + + union + { + __IOM uint32_t ADCALINTCR; /*!< (@ 0x00000028) Calibration interrupt Enable Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t CALENDIE0 : 1; /*!< [16..16] ADC0 Calibration End Interrupt Enable */ + __IOM uint32_t CALENDIE1 : 1; /*!< [17..17] ADC1 Calibration End Interrupt Enable */ + uint32_t : 14; + } ADCALINTCR_b; + }; + __IM uint32_t RESERVED1[5]; + + union + { + __IOM uint32_t ADMDR; /*!< (@ 0x00000040) A/D Converter Mode Selection Register */ + + struct + { + __IOM uint32_t ADMD0 : 4; /*!< [3..0] ADC0 Mode Selection */ + uint32_t : 4; + __IOM uint32_t ADMD1 : 4; /*!< [11..8] ADC1 Mode Selection */ + uint32_t : 20; + } ADMDR_b; + }; + + union + { + __IOM uint32_t ADGSPCR; /*!< (@ 0x00000044) A/D Group scan Priority Control Register */ + + struct + { + __IOM uint32_t PGS0 : 1; /*!< [0..0] ADC0 Group Priority Control Setting */ + __IOM uint32_t RSCN0 : 1; /*!< [1..1] ADC0 Group Priority Control Setting 2 */ + __IOM uint32_t LGRRS0 : 1; /*!< [2..2] ADC0 Group Priority Control Setting 3 */ + __IOM uint32_t GRP0 : 1; /*!< [3..3] ADC0 Group Priority Control Setting 4 */ + uint32_t : 4; + __IOM uint32_t PGS1 : 1; /*!< [8..8] ADC1 Group Priority Control Setting */ + __IOM uint32_t RSCN1 : 1; /*!< [9..9] ADC1 Group Priority Control Setting 2 */ + __IOM uint32_t LGRRS1 : 1; /*!< [10..10] ADC1 Group Priority Control Setting 3 */ + __IOM uint32_t GRP1 : 1; /*!< [11..11] ADC1 Group Priority Control Setting 4 */ + uint32_t : 20; + } ADGSPCR_b; + }; + + union + { + __IOM uint32_t ADSGER; /*!< (@ 0x00000048) Scan Group Enable Register */ + + struct + { + __IOM uint32_t SGREn : 9; /*!< [8..0] Scan Group n Enable */ + uint32_t : 23; + } ADSGER_b; + }; + + union + { + __IOM uint32_t ADSGCR0; /*!< (@ 0x0000004C) Scan Group Control Register 0 */ + + struct + { + __IOM uint32_t SGADS0 : 2; /*!< [1..0] Scan Group 0 A/D Converter Selection */ + uint32_t : 6; + __IOM uint32_t SGADS1 : 2; /*!< [9..8] Scan Group 1 A/D Converter Selection */ + uint32_t : 6; + __IOM uint32_t SGADS2 : 2; /*!< [17..16] Scan Group 2 A/D Converter Selection */ + uint32_t : 6; + __IOM uint32_t SGADS3 : 2; /*!< [25..24] Scan Group 3 A/D Converter Selection */ + uint32_t : 6; + } ADSGCR0_b; + }; + + union + { + __IOM uint32_t ADSGCR1; /*!< (@ 0x00000050) Scan Group Control Register 1 */ + + struct + { + __IOM uint32_t SGADS4 : 2; /*!< [1..0] Scan Group 4 A/D Converter Selection */ + uint32_t : 6; + __IOM uint32_t SGADS5 : 2; /*!< [9..8] Scan Group 5 A/D Converter Selection */ + uint32_t : 6; + __IOM uint32_t SGADS6 : 2; /*!< [17..16] Scan Group 6 A/D Converter Selection */ + uint32_t : 6; + __IOM uint32_t SGADS7 : 2; /*!< [25..24] Scan Group 7 A/D Converter Selection */ + uint32_t : 6; + } ADSGCR1_b; + }; + + union + { + __IOM uint32_t ADSGCR2; /*!< (@ 0x00000054) Scan Group Control Register 2 */ + + struct + { + __IOM uint32_t SGADS8 : 2; /*!< [1..0] Scan Group 8 A/D Converter Selection */ + uint32_t : 30; + } ADSGCR2_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t ADINTCR; /*!< (@ 0x0000005C) Scan End Interrupt Enable Register */ + + struct + { + __IOM uint32_t ADIEn : 9; /*!< [8..0] Scan Group n Scan End Interrupt Enable */ + uint32_t : 23; + } ADINTCR_b; + }; + __IM uint32_t RESERVED3[24]; + + union + { + __IOM uint32_t ADTRGEXT0; /*!< (@ 0x000000C0) External Trigger Enable Register 0 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT0_b; + }; + + union + { + __IOM uint32_t ADTRGELC0; /*!< (@ 0x000000C4) ELC Trigger Enable Register 0 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC0_b; + }; + + union + { + __IOM uint32_t ADTRGGPT0; /*!< (@ 0x000000C8) GPT Trigger Enable Register 0 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT0_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t ADTRGEXT1; /*!< (@ 0x000000D0) External Trigger Enable Register 1 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT1_b; + }; + + union + { + __IOM uint32_t ADTRGELC1; /*!< (@ 0x000000D4) ELC Trigger Enable Register 1 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC1_b; + }; + + union + { + __IOM uint32_t ADTRGGPT1; /*!< (@ 0x000000D8) GPT Trigger Enable Register 1 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT1_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t ADTRGEXT2; /*!< (@ 0x000000E0) External Trigger Enable Register 2 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT2_b; + }; + + union + { + __IOM uint32_t ADTRGELC2; /*!< (@ 0x000000E4) ELC Trigger Enable Register 2 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC2_b; + }; + + union + { + __IOM uint32_t ADTRGGPT2; /*!< (@ 0x000000E8) GPT Trigger Enable Register 2 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT2_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t ADTRGEXT3; /*!< (@ 0x000000F0) External Trigger Enable Register 3 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT3_b; + }; + + union + { + __IOM uint32_t ADTRGELC3; /*!< (@ 0x000000F4) ELC Trigger Enable Register 3 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC3_b; + }; + + union + { + __IOM uint32_t ADTRGGPT3; /*!< (@ 0x000000F8) GPT Trigger Enable Register 3 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT3_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t ADTRGEXT4; /*!< (@ 0x00000100) External Trigger Enable Register 4 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT4_b; + }; + + union + { + __IOM uint32_t ADTRGELC4; /*!< (@ 0x00000104) ELC Trigger Enable Register 4 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC4_b; + }; + + union + { + __IOM uint32_t ADTRGGPT4; /*!< (@ 0x00000108) GPT Trigger Enable Register 4 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT4_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t ADTRGEXT5; /*!< (@ 0x00000110) External Trigger Enable Register 5 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT5_b; + }; + + union + { + __IOM uint32_t ADTRGELC5; /*!< (@ 0x00000114) ELC Trigger Enable Register 5 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC5_b; + }; + + union + { + __IOM uint32_t ADTRGGPT5; /*!< (@ 0x00000118) GPT Trigger Enable Register 5 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT5_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t ADTRGEXT6; /*!< (@ 0x00000120) External Trigger Enable Register 6 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT6_b; + }; + + union + { + __IOM uint32_t ADTRGELC6; /*!< (@ 0x00000124) ELC Trigger Enable Register 6 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC6_b; + }; + + union + { + __IOM uint32_t ADTRGGPT6; /*!< (@ 0x00000128) GPT Trigger Enable Register 6 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT6_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t ADTRGEXT7; /*!< (@ 0x00000130) External Trigger Enable Register 7 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT7_b; + }; + + union + { + __IOM uint32_t ADTRGELC7; /*!< (@ 0x00000134) ELC Trigger Enable Register 7 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC7_b; + }; + + union + { + __IOM uint32_t ADTRGGPT7; /*!< (@ 0x00000138) GPT Trigger Enable Register 7 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT7_b; + }; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t ADTRGEXT8; /*!< (@ 0x00000140) External Trigger Enable Register 8 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT8_b; + }; + + union + { + __IOM uint32_t ADTRGELC8; /*!< (@ 0x00000144) ELC Trigger Enable Register 8 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC8_b; + }; + + union + { + __IOM uint32_t ADTRGGPT8; /*!< (@ 0x00000148) GPT Trigger Enable Register 8 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT8_b; + }; + __IM uint32_t RESERVED12[29]; + + union + { + __IOM uint32_t ADTRGDLR0; /*!< (@ 0x000001C0) A/D Conversion Start Trigger Delay Register 0 */ + + struct + { + __IOM uint32_t TRGDLY0 : 8; /*!< [7..0] Scan Group 0 Trigger Input Delay Configuration */ + uint32_t : 8; + __IOM uint32_t TRGDLY1 : 8; /*!< [23..16] Scan Group 1 Trigger Input Delay Configuration */ + uint32_t : 8; + } ADTRGDLR0_b; + }; + + union + { + __IOM uint32_t ADTRGDLR1; /*!< (@ 0x000001C4) A/D Conversion Start Trigger Delay Register 1 */ + + struct + { + __IOM uint32_t TRGDLY2 : 8; /*!< [7..0] Scan Group 2 Trigger Input Delay Configuration */ + uint32_t : 8; + __IOM uint32_t TRGDLY3 : 8; /*!< [23..16] Scan Group 3 Trigger Input Delay Configuration */ + uint32_t : 8; + } ADTRGDLR1_b; + }; + + union + { + __IOM uint32_t ADTRGDLR2; /*!< (@ 0x000001C8) A/D Conversion Start Trigger Delay Register 2 */ + + struct + { + __IOM uint32_t TRGDLY4 : 8; /*!< [7..0] Scan Group 4 Trigger Input Delay Configuration */ + uint32_t : 8; + __IOM uint32_t TRGDLY5 : 8; /*!< [23..16] Scan Group 5 Trigger Input Delay Configuration */ + uint32_t : 8; + } ADTRGDLR2_b; + }; + + union + { + __IOM uint32_t ADTRGDLR3; /*!< (@ 0x000001CC) A/D Conversion Start Trigger Delay Register 3 */ + + struct + { + __IOM uint32_t TRGDLY6 : 8; /*!< [7..0] Scan Group 6 Trigger Input Delay Configuration */ + uint32_t : 8; + __IOM uint32_t TRGDLY7 : 8; /*!< [23..16] Scan Group 7 Trigger Input Delay Configuration */ + uint32_t : 8; + } ADTRGDLR3_b; + }; + + union + { + __IOM uint32_t ADTRGDLR4; /*!< (@ 0x000001D0) A/D Conversion Start Trigger Delay Register 4 */ + + struct + { + __IOM uint32_t TRGDLY8 : 8; /*!< [7..0] Scan Group 8 Trigger Input Delay Configuration */ + uint32_t : 24; + } ADTRGDLR4_b; + }; + __IM uint32_t RESERVED13[11]; + + union + { + __IOM uint32_t ADSGDCR0; /*!< (@ 0x00000200) Scan Group Diagnosis Function Control Register + * 0 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR0_b; + }; + + union + { + __IOM uint32_t ADSGDCR1; /*!< (@ 0x00000204) Scan Group Diagnosis Function Control Register + * 1 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR1_b; + }; + + union + { + __IOM uint32_t ADSGDCR2; /*!< (@ 0x00000208) Scan Group Diagnosis Function Control Register + * 2 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR2_b; + }; + + union + { + __IOM uint32_t ADSGDCR3; /*!< (@ 0x0000020C) Scan Group Diagnosis Function Control Register + * 3 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR3_b; + }; + + union + { + __IOM uint32_t ADSGDCR4; /*!< (@ 0x00000210) Scan Group Diagnosis Function Control Register + * 4 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR4_b; + }; + + union + { + __IOM uint32_t ADSGDCR5; /*!< (@ 0x00000214) Scan Group Diagnosis Function Control Register + * 5 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR5_b; + }; + + union + { + __IOM uint32_t ADSGDCR6; /*!< (@ 0x00000218) Scan Group Diagnosis Function Control Register + * 6 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR6_b; + }; + + union + { + __IOM uint32_t ADSGDCR7; /*!< (@ 0x0000021C) Scan Group Diagnosis Function Control Register + * 7 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR7_b; + }; + + union + { + __IOM uint32_t ADSGDCR8; /*!< (@ 0x00000220) Scan Group Diagnosis Function Control Register + * 8 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR8_b; + }; + __IM uint32_t RESERVED14[7]; + + union + { + __IOM uint32_t ADSSTR0; /*!< (@ 0x00000240) Sampling State Table Register 0 */ + + struct + { + __IOM uint32_t SST0 : 10; /*!< [9..0] Sampling State Table 0 */ + uint32_t : 6; + __IOM uint32_t SST1 : 10; /*!< [25..16] Sampling State Table 1 */ + uint32_t : 6; + } ADSSTR0_b; + }; + + union + { + __IOM uint32_t ADSSTR1; /*!< (@ 0x00000244) Sampling State Table Register 1 */ + + struct + { + __IOM uint32_t SST2 : 10; /*!< [9..0] Sampling State Table 2 */ + uint32_t : 6; + __IOM uint32_t SST3 : 10; /*!< [25..16] Sampling State Table 3 */ + uint32_t : 6; + } ADSSTR1_b; + }; + + union + { + __IOM uint32_t ADSSTR2; /*!< (@ 0x00000248) Sampling State Table Register 2 */ + + struct + { + __IOM uint32_t SST4 : 10; /*!< [9..0] Sampling State Table 4 */ + uint32_t : 6; + __IOM uint32_t SST5 : 10; /*!< [25..16] Sampling State Table 5 */ + uint32_t : 6; + } ADSSTR2_b; + }; + + union + { + __IOM uint32_t ADSSTR3; /*!< (@ 0x0000024C) Sampling State Table Register 3 */ + + struct + { + __IOM uint32_t SST6 : 10; /*!< [9..0] Sampling State Table 6 */ + uint32_t : 6; + __IOM uint32_t SST7 : 10; /*!< [25..16] Sampling State Table 7 */ + uint32_t : 6; + } ADSSTR3_b; + }; + + union + { + __IOM uint32_t ADSSTR4; /*!< (@ 0x00000250) Sampling State Table Register 4 */ + + struct + { + __IOM uint32_t SST8 : 10; /*!< [9..0] Sampling State Table 8 */ + uint32_t : 6; + __IOM uint32_t SST9 : 10; /*!< [25..16] Sampling State Table 9 */ + uint32_t : 6; + } ADSSTR4_b; + }; + + union + { + __IOM uint32_t ADSSTR5; /*!< (@ 0x00000254) Sampling State Table Register 5 */ + + struct + { + __IOM uint32_t SST10 : 10; /*!< [9..0] Sampling State Table 10 */ + uint32_t : 6; + __IOM uint32_t SST11 : 10; /*!< [25..16] Sampling State Table 11 */ + uint32_t : 6; + } ADSSTR5_b; + }; + + union + { + __IOM uint32_t ADSSTR6; /*!< (@ 0x00000258) Sampling State Table Register 6 */ + + struct + { + __IOM uint32_t SST12 : 10; /*!< [9..0] Sampling State Table 12 */ + uint32_t : 6; + __IOM uint32_t SST13 : 10; /*!< [25..16] Sampling State Table 13 */ + uint32_t : 6; + } ADSSTR6_b; + }; + + union + { + __IOM uint32_t ADSSTR7; /*!< (@ 0x0000025C) Sampling State Table Register 7 */ + + struct + { + __IOM uint32_t SST14 : 10; /*!< [9..0] Sampling State Table 14 */ + uint32_t : 6; + __IOM uint32_t SST15 : 10; /*!< [25..16] Sampling State Table 15 */ + uint32_t : 6; + } ADSSTR7_b; + }; + + union + { + __IOM uint32_t ADCNVSTR; /*!< (@ 0x00000260) A/D Conversion State Register */ + + struct + { + __IOM uint32_t CST0 : 6; /*!< [5..0] A/D Converter Unit 0 (ADC0) */ + uint32_t : 2; + __IOM uint32_t CST1 : 6; /*!< [13..8] A/D Converter Unit 1 (ADC1) */ + uint32_t : 18; + } ADCNVSTR_b; + }; + + union + { + __IOM uint32_t ADCALSTCR; /*!< (@ 0x00000264) A/D Converter Calibration State Register */ + + struct + { + __IOM uint32_t CALADSST : 10; /*!< [9..0] A/D Converter Calibration Sampling Time Configuration */ + uint32_t : 6; + __IOM uint32_t CALADCST : 6; /*!< [21..16] A/D Converter Calibration Conversion Time Configuration. */ + uint32_t : 10; + } ADCALSTCR_b; + }; + __IM uint32_t RESERVED15[6]; + + union + { + __IOM uint32_t ADSHCR0; /*!< (@ 0x00000280) Channel-Dedicated Sample-and-Hold Circuit Control + * Register 0 */ + + struct + { + __IOM uint32_t SHEN0 : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Unit 0 Select */ + __IOM uint32_t SHEN1 : 1; /*!< [1..1] Channel-Dedicated Sample-and-Hold Circuit Unit 1 Select */ + __IOM uint32_t SHEN2 : 1; /*!< [2..2] Channel-Dedicated Sample-and-Hold Circuit Unit 2 Select */ + uint32_t : 13; + __IOM uint32_t SHMD0 : 1; /*!< [16..16] Channel-dedicated Sample-and-hold Circuit Unit 0 Input + * Mode Select */ + __IOM uint32_t SHMD1 : 1; /*!< [17..17] Channel-dedicated Sample-and-hold Circuit Unit 1 Input + * Mode Select */ + __IOM uint32_t SHMD2 : 1; /*!< [18..18] Channel-dedicated Sample-and-hold Circuit Unit 2 Input + * Mode Select */ + uint32_t : 13; + } ADSHCR0_b; + }; + __IM uint32_t RESERVED16; + + union + { + __IOM uint32_t ADSHSTR0; /*!< (@ 0x00000288) Channel-Dedicated Sample & Hold Circuit State + * Register 0 */ + + struct + { + __IOM uint32_t SHSST : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Unit 0 to 2 */ + uint32_t : 8; + __IOM uint32_t SHHST : 3; /*!< [18..16] Channel-Dedicated Sample-and-Hold Circuit Unit 0 to + * 2 */ + uint32_t : 13; + } ADSHSTR0_b; + }; + + union + { + __IOM uint32_t ADSHCR1; /*!< (@ 0x0000028C) Channel-Dedicated Sample-and-Hold Circuit Control + * Register 1 */ + + struct + { + __IOM uint32_t SHEN4 : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Unit 4 Select */ + __IOM uint32_t SHEN5 : 1; /*!< [1..1] Channel-Dedicated Sample-and-Hold Circuit Unit 5 Select */ + __IOM uint32_t SHEN6 : 1; /*!< [2..2] Channel-Dedicated Sample-and-Hold Circuit Unit 6 Select */ + uint32_t : 13; + __IOM uint32_t SHMD4 : 1; /*!< [16..16] Channel-dedicated Sample-and-hold Circuit Unit 4 Input + * Mode Select */ + __IOM uint32_t SHMD5 : 1; /*!< [17..17] Channel-dedicated Sample-and-hold Circuit Unit 5 Input + * Mode Select */ + __IOM uint32_t SHMD6 : 1; /*!< [18..18] Channel-dedicated Sample-and-hold Circuit Unit 6 Input + * Mode Select */ + uint32_t : 13; + } ADSHCR1_b; + }; + __IM uint32_t RESERVED17; + + union + { + __IOM uint32_t ADSHSTR1; /*!< (@ 0x00000294) Channel-Dedicated Sample & Hold Circuit State + * Register 1 */ + + struct + { + __IOM uint32_t SHSST : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Unit 4 to 6 */ + uint32_t : 8; + __IOM uint32_t SHHST : 3; /*!< [18..16] Channel-Dedicated Sample-and-Hold Circuit Unit 4 to + * 6 */ + uint32_t : 13; + } ADSHSTR1_b; + }; + __IM uint32_t RESERVED18[6]; + + union + { + __IOM uint32_t ADCALSHCR; /*!< (@ 0x000002B0) Channel-Dedicated Sample & Hold Circuit Calibration + * State Register */ + + struct + { + __IOM uint32_t CALSHSST : 8; /*!< [7..0] Channel-Dedicated Sample & Hold Circuit Calibration Sampling + * Time Configuration */ + uint32_t : 8; + __IOM uint32_t CALSHHST : 3; /*!< [18..16] Channel-Dedicated Sample & Hold Circuit Calibration + * Holding Time Configuration */ + uint32_t : 13; + } ADCALSHCR_b; + }; + __IM uint32_t RESERVED19[27]; + + union + { + __IOM uint32_t ADREFCR; /*!< (@ 0x00000320) Internal Reference Voltage Monitor Enable Register */ + + struct + { + __IOM uint32_t VDE : 1; /*!< [0..0] Internal Reference Voltage A/D Conversion Select */ + uint32_t : 31; + } ADREFCR_b; + }; + __IM uint32_t RESERVED20[7]; + + union + { + __IOM uint32_t ADDFSR0; /*!< (@ 0x00000340) A/D Converter Digital Filter Selection Register + * 0 */ + + struct + { + __IOM uint32_t DFSEL0 : 2; /*!< [1..0] A/D Converter unit the 1st digital filter characteristic + * selection. */ + uint32_t : 6; + __IOM uint32_t DFSEL1 : 2; /*!< [9..8] A/D Converter unit the 2nd digital filter characteristic + * selection. */ + uint32_t : 6; + __IOM uint32_t DFSEL2 : 2; /*!< [17..16] A/D Converter unit the 2nd digital filter characteristic + * selection. */ + uint32_t : 6; + __IOM uint32_t DFSEL3 : 2; /*!< [25..24] A/D Converter unit the 4th digital filter characteristic + * selection. */ + uint32_t : 6; + } ADDFSR0_b; + }; + + union + { + __IOM uint32_t ADDFSR1; /*!< (@ 0x00000344) A/D Converter Digital Filter Selection Register + * 1 */ + + struct + { + __IOM uint32_t DFSEL0 : 2; /*!< [1..0] A/D Converter unit the 1st digital filter characteristic + * selection. */ + uint32_t : 6; + __IOM uint32_t DFSEL1 : 2; /*!< [9..8] A/D Converter unit the 2nd digital filter characteristic + * selection. */ + uint32_t : 6; + __IOM uint32_t DFSEL2 : 2; /*!< [17..16] A/D Converter unit the 2nd digital filter characteristic + * selection. */ + uint32_t : 6; + __IOM uint32_t DFSEL3 : 2; /*!< [25..24] A/D Converter unit the 4th digital filter characteristic + * selection. */ + uint32_t : 6; + } ADDFSR1_b; + }; + __IM uint32_t RESERVED21[6]; + + union + { + __IOM uint32_t ADUOFTR0; /*!< (@ 0x00000360) User Offset Table Register 0 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR0_b; + }; + + union + { + __IOM uint32_t ADUOFTR1; /*!< (@ 0x00000364) User Offset Table Register 1 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR1_b; + }; + + union + { + __IOM uint32_t ADUOFTR2; /*!< (@ 0x00000368) User Offset Table Register 2 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR2_b; + }; + + union + { + __IOM uint32_t ADUOFTR3; /*!< (@ 0x0000036C) User Offset Table Register 3 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR3_b; + }; + + union + { + __IOM uint32_t ADUOFTR4; /*!< (@ 0x00000370) User Offset Table Register 4 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR4_b; + }; + + union + { + __IOM uint32_t ADUOFTR5; /*!< (@ 0x00000374) User Offset Table Register 5 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR5_b; + }; + + union + { + __IOM uint32_t ADUOFTR6; /*!< (@ 0x00000378) User Offset Table Register 6 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR6_b; + }; + + union + { + __IOM uint32_t ADUOFTR7; /*!< (@ 0x0000037C) User Offset Table Register 7 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR7_b; + }; + + union + { + __IOM uint32_t ADUGTR0; /*!< (@ 0x00000380) User Gain Table Register 0 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR0_b; + }; + + union + { + __IOM uint32_t ADUGTR1; /*!< (@ 0x00000384) User Gain Table Register 1 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR1_b; + }; + + union + { + __IOM uint32_t ADUGTR2; /*!< (@ 0x00000388) User Gain Table Register 2 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR2_b; + }; + + union + { + __IOM uint32_t ADUGTR3; /*!< (@ 0x0000038C) User Gain Table Register 3 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR3_b; + }; + + union + { + __IOM uint32_t ADUGTR4; /*!< (@ 0x00000390) User Gain Table Register 4 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR4_b; + }; + + union + { + __IOM uint32_t ADUGTR5; /*!< (@ 0x00000394) User Gain Table Register 5 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR5_b; + }; + + union + { + __IOM uint32_t ADUGTR6; /*!< (@ 0x00000398) User Gain Table Register 6 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR6_b; + }; + + union + { + __IOM uint32_t ADUGTR7; /*!< (@ 0x0000039C) User Gain Table Register 7 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR7_b; + }; + + union + { + __IOM uint32_t ADLIMINTCR; /*!< (@ 0x000003A0) Limiter Clip Interrupt Enable Register */ + + struct + { + __IOM uint32_t LIMIEn : 9; /*!< [8..0] Limiter Clip Interrupt n Enable bit */ + uint32_t : 23; + } ADLIMINTCR_b; + }; + + union + { + __IOM uint32_t ADLIMTR0; /*!< (@ 0x000003A4) Limiter Clip Table Register 0 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR0_b; + }; + + union + { + __IOM uint32_t ADLIMTR1; /*!< (@ 0x000003A8) Limiter Clip Table Register 1 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR1_b; + }; + + union + { + __IOM uint32_t ADLIMTR2; /*!< (@ 0x000003AC) Limiter Clip Table Register 2 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR2_b; + }; + + union + { + __IOM uint32_t ADLIMTR3; /*!< (@ 0x000003B0) Limiter Clip Table Register 3 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR3_b; + }; + + union + { + __IOM uint32_t ADLIMTR4; /*!< (@ 0x000003B4) Limiter Clip Table Register 4 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR4_b; + }; + + union + { + __IOM uint32_t ADLIMTR5; /*!< (@ 0x000003B8) Limiter Clip Table Register 5 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR5_b; + }; + + union + { + __IOM uint32_t ADLIMTR6; /*!< (@ 0x000003BC) Limiter Clip Table Register 6 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR6_b; + }; + + union + { + __IOM uint32_t ADLIMTR7; /*!< (@ 0x000003C0) Limiter Clip Table Register 7 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR7_b; + }; + __IM uint32_t RESERVED22[15]; + + union + { + __IOM uint32_t ADCMPENR; /*!< (@ 0x00000400) Compare Match Enable Register */ + + struct + { + __IOM uint32_t CMPENn : 8; /*!< [7..0] Compare Match n Enable */ + uint32_t : 24; + } ADCMPENR_b; + }; + + union + { + __IOM uint32_t ADCMPINTCR; /*!< (@ 0x00000404) Compare Match Interrupt Enable Register */ + + struct + { + __IOM uint32_t CMPIEn : 4; /*!< [3..0] Compare Match Interrupt n Enable */ + uint32_t : 28; + } ADCMPINTCR_b; + }; + + union + { + __IOM uint32_t ADCCMPCR0; /*!< (@ 0x00000408) Composite Compare Match Configuration Register + * 0 */ + + struct + { + __IOM uint32_t CCMPCND : 2; /*!< [1..0] Composite Compare Match Condition Selection */ + uint32_t : 14; + __IOM uint32_t CCMPTBLm : 8; /*!< [23..16] Composite Compare Match Condition Table Selection */ + uint32_t : 8; + } ADCCMPCR0_b; + }; + + union + { + __IOM uint32_t ADCCMPCR1; /*!< (@ 0x0000040C) Composite Compare Match Configuration Register + * 1 */ + + struct + { + __IOM uint32_t CCMPCND : 2; /*!< [1..0] Composite Compare Match Condition Selection */ + uint32_t : 14; + __IOM uint32_t CCMPTBLm : 8; /*!< [23..16] Composite Compare Match Condition Table Selection */ + uint32_t : 8; + } ADCCMPCR1_b; + }; + __IM uint32_t RESERVED23[14]; + + union + { + __IOM uint32_t ADCMPMDR0; /*!< (@ 0x00000448) Compare Match Mode Selection Register 0 */ + + struct + { + __IOM uint32_t CMPMD0 : 2; /*!< [1..0] Compare Match 0 : Match Mode Selection */ + uint32_t : 6; + __IOM uint32_t CMPMD1 : 2; /*!< [9..8] Compare Match 1 : Match Mode Selection */ + uint32_t : 6; + __IOM uint32_t CMPMD2 : 2; /*!< [17..16] Compare Match 2 : Match Mode Selection */ + uint32_t : 6; + __IOM uint32_t CMPMD3 : 2; /*!< [25..24] Compare Match 3 : Match Mode Selection */ + uint32_t : 6; + } ADCMPMDR0_b; + }; + + union + { + __IOM uint32_t ADCMPMDR1; /*!< (@ 0x0000044C) Compare Match Mode Selection Register 1 */ + + struct + { + __IOM uint32_t CMPMD4 : 2; /*!< [1..0] Compare Match 4 : Match Mode Selection */ + uint32_t : 6; + __IOM uint32_t CMPMD5 : 2; /*!< [9..8] Compare Match 5 : Match Mode Selection */ + uint32_t : 6; + __IOM uint32_t CMPMD6 : 2; /*!< [17..16] Compare Match 6 : Match Mode Selection */ + uint32_t : 6; + __IOM uint32_t CMPMD7 : 2; /*!< [25..24] Compare Match 7 : Match Mode Selection */ + uint32_t : 6; + } ADCMPMDR1_b; + }; + __IM uint32_t RESERVED24[2]; + + union + { + __IOM uint32_t ADCMPTBR0; /*!< (@ 0x00000458) Compare Match Table Register 0 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR0_b; + }; + + union + { + __IOM uint32_t ADCMPTBR1; /*!< (@ 0x0000045C) Compare Match Table Register 1 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR1_b; + }; + + union + { + __IOM uint32_t ADCMPTBR2; /*!< (@ 0x00000460) Compare Match Table Register 2 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR2_b; + }; + + union + { + __IOM uint32_t ADCMPTBR3; /*!< (@ 0x00000464) Compare Match Table Register 3 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR3_b; + }; + + union + { + __IOM uint32_t ADCMPTBR4; /*!< (@ 0x00000468) Compare Match Table Register 4 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR4_b; + }; + + union + { + __IOM uint32_t ADCMPTBR5; /*!< (@ 0x0000046C) Compare Match Table Register 5 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR5_b; + }; + + union + { + __IOM uint32_t ADCMPTBR6; /*!< (@ 0x00000470) Compare Match Table Register 6 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR6_b; + }; + + union + { + __IOM uint32_t ADCMPTBR7; /*!< (@ 0x00000474) Compare Match Table Register 7 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR7_b; + }; + __IM uint32_t RESERVED25[18]; + + union + { + __IOM uint32_t ADFIFOCR; /*!< (@ 0x000004C0) FIFO Control Register */ + + struct + { + __IOM uint32_t FIFOEN0 : 1; /*!< [0..0] Scan Group 0 FIFO Enable */ + __IOM uint32_t FIFOEN1 : 1; /*!< [1..1] Scan Group 1 FIFO Enable */ + __IOM uint32_t FIFOEN2 : 1; /*!< [2..2] Scan Group 2 FIFO Enable */ + __IOM uint32_t FIFOEN3 : 1; /*!< [3..3] Scan Group 3 FIFO Enable */ + __IOM uint32_t FIFOEN4 : 1; /*!< [4..4] Scan Group 4 FIFO Enable */ + __IOM uint32_t FIFOEN5 : 1; /*!< [5..5] Scan Group 5 FIFO Enable */ + __IOM uint32_t FIFOEN6 : 1; /*!< [6..6] Scan Group 6 FIFO Enable */ + __IOM uint32_t FIFOEN7 : 1; /*!< [7..7] Scan Group 7 FIFO Enable */ + __IOM uint32_t FIFOEN8 : 1; /*!< [8..8] Scan Group 8 FIFO Enable */ + uint32_t : 23; + } ADFIFOCR_b; + }; + + union + { + __IOM uint32_t ADFIFOINTCR; /*!< (@ 0x000004C4) FIFO Interrupt Control Register */ + + struct + { + __IOM uint32_t FIFOIE0 : 1; /*!< [0..0] Scan Group 0 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE1 : 1; /*!< [1..1] Scan Group 1 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE2 : 1; /*!< [2..2] Scan Group 2 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE3 : 1; /*!< [3..3] Scan Group 3 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE4 : 1; /*!< [4..4] Scan Group 4 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE5 : 1; /*!< [5..5] Scan Group 5 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE6 : 1; /*!< [6..6] Scan Group 6 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE7 : 1; /*!< [7..7] Scan Group 7 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE8 : 1; /*!< [8..8] Scan Group 8 FIFO Interrupt Enable */ + uint32_t : 23; + } ADFIFOINTCR_b; + }; + + union + { + __IOM uint32_t ADFIFOINTLR0; /*!< (@ 0x000004C8) FIFO Interrupt Generation Level Register 0 */ + + struct + { + __IOM uint32_t FIFOILV0 : 4; /*!< [3..0] Scan Group 0 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + __IOM uint32_t FIFOILV1 : 4; /*!< [19..16] Scan Group 1 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + } ADFIFOINTLR0_b; + }; + + union + { + __IOM uint32_t ADFIFOINTLR1; /*!< (@ 0x000004CC) FIFO Interrupt Generation Level Register 1 */ + + struct + { + __IOM uint32_t FIFOILV2 : 4; /*!< [3..0] Scan Group 2 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + __IOM uint32_t FIFOILV3 : 4; /*!< [19..16] Scan Group 3 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + } ADFIFOINTLR1_b; + }; + + union + { + __IOM uint32_t ADFIFOINTLR2; /*!< (@ 0x000004D0) FIFO Interrupt Generation Level Register 2 */ + + struct + { + __IOM uint32_t FIFOILV4 : 4; /*!< [3..0] Scan Group 4 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + __IOM uint32_t FIFOILV5 : 4; /*!< [19..16] Scan Group 5 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + } ADFIFOINTLR2_b; + }; + + union + { + __IOM uint32_t ADFIFOINTLR3; /*!< (@ 0x000004D4) FIFO Interrupt Generation Level Register 3 */ + + struct + { + __IOM uint32_t FIFOILV6 : 4; /*!< [3..0] Scan Group 6 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + __IOM uint32_t FIFOILV7 : 4; /*!< [19..16] Scan Group 7 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + } ADFIFOINTLR3_b; + }; + + union + { + __IOM uint32_t ADFIFOINTLR4; /*!< (@ 0x000004D8) FIFO Interrupt Generation Level Register 4 */ + + struct + { + __IOM uint32_t FIFOILV8 : 4; /*!< [3..0] Scan Group 8 FIFO Interrupt Output Timing Setting */ + uint32_t : 28; + } ADFIFOINTLR4_b; + }; + __IM uint32_t RESERVED26[73]; + + union + { + __IOM uint32_t ADCHCR0; /*!< (@ 0x00000600) A/D Conversion Channel Configuration Register + * 0 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR0_b; + }; + + union + { + __IOM uint32_t ADDOPCRA0; /*!< (@ 0x00000604) A/D Conversion Data Operation Control A Register + * 0 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA0_b; + }; + + union + { + __IOM uint32_t ADDOPCRB0; /*!< (@ 0x00000608) A/D Conversion Data Operation Control B Register + * 0 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB0_b; + }; + + union + { + __IOM uint32_t ADDOPCRC0; /*!< (@ 0x0000060C) A/D Conversion Data Operation Control C Register + * 0 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC0_b; + }; + + union + { + __IOM uint32_t ADCHCR1; /*!< (@ 0x00000610) A/D Conversion Channel Configuration Register + * 1 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR1_b; + }; + + union + { + __IOM uint32_t ADDOPCRA1; /*!< (@ 0x00000614) A/D Conversion Data Operation Control A Register + * 1 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA1_b; + }; + + union + { + __IOM uint32_t ADDOPCRB1; /*!< (@ 0x00000618) A/D Conversion Data Operation Control B Register + * 1 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB1_b; + }; + + union + { + __IOM uint32_t ADDOPCRC1; /*!< (@ 0x0000061C) A/D Conversion Data Operation Control C Register + * 1 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC1_b; + }; + + union + { + __IOM uint32_t ADCHCR2; /*!< (@ 0x00000620) A/D Conversion Channel Configuration Register + * 2 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR2_b; + }; + + union + { + __IOM uint32_t ADDOPCRA2; /*!< (@ 0x00000624) A/D Conversion Data Operation Control A Register + * 2 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA2_b; + }; + + union + { + __IOM uint32_t ADDOPCRB2; /*!< (@ 0x00000628) A/D Conversion Data Operation Control B Register + * 2 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB2_b; + }; + + union + { + __IOM uint32_t ADDOPCRC2; /*!< (@ 0x0000062C) A/D Conversion Data Operation Control C Register + * 2 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC2_b; + }; + + union + { + __IOM uint32_t ADCHCR3; /*!< (@ 0x00000630) A/D Conversion Channel Configuration Register + * 3 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR3_b; + }; + + union + { + __IOM uint32_t ADDOPCRA3; /*!< (@ 0x00000634) A/D Conversion Data Operation Control A Register + * 3 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA3_b; + }; + + union + { + __IOM uint32_t ADDOPCRB3; /*!< (@ 0x00000638) A/D Conversion Data Operation Control B Register + * 3 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB3_b; + }; + + union + { + __IOM uint32_t ADDOPCRC3; /*!< (@ 0x0000063C) A/D Conversion Data Operation Control C Register + * 3 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC3_b; + }; + + union + { + __IOM uint32_t ADCHCR4; /*!< (@ 0x00000640) A/D Conversion Channel Configuration Register + * 4 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR4_b; + }; + + union + { + __IOM uint32_t ADDOPCRA4; /*!< (@ 0x00000644) A/D Conversion Data Operation Control A Register + * 4 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA4_b; + }; + + union + { + __IOM uint32_t ADDOPCRB4; /*!< (@ 0x00000648) A/D Conversion Data Operation Control B Register + * 4 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB4_b; + }; + + union + { + __IOM uint32_t ADDOPCRC4; /*!< (@ 0x0000064C) A/D Conversion Data Operation Control C Register + * 4 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC4_b; + }; + + union + { + __IOM uint32_t ADCHCR5; /*!< (@ 0x00000650) A/D Conversion Channel Configuration Register + * 5 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR5_b; + }; + + union + { + __IOM uint32_t ADDOPCRA5; /*!< (@ 0x00000654) A/D Conversion Data Operation Control A Register + * 5 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA5_b; + }; + + union + { + __IOM uint32_t ADDOPCRB5; /*!< (@ 0x00000658) A/D Conversion Data Operation Control B Register + * 5 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB5_b; + }; + + union + { + __IOM uint32_t ADDOPCRC5; /*!< (@ 0x0000065C) A/D Conversion Data Operation Control C Register + * 5 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC5_b; + }; + + union + { + __IOM uint32_t ADCHCR6; /*!< (@ 0x00000660) A/D Conversion Channel Configuration Register + * 6 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR6_b; + }; + + union + { + __IOM uint32_t ADDOPCRA6; /*!< (@ 0x00000664) A/D Conversion Data Operation Control A Register + * 6 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA6_b; + }; + + union + { + __IOM uint32_t ADDOPCRB6; /*!< (@ 0x00000668) A/D Conversion Data Operation Control B Register + * 6 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB6_b; + }; + + union + { + __IOM uint32_t ADDOPCRC6; /*!< (@ 0x0000066C) A/D Conversion Data Operation Control C Register + * 6 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC6_b; + }; + + union + { + __IOM uint32_t ADCHCR7; /*!< (@ 0x00000670) A/D Conversion Channel Configuration Register + * 7 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR7_b; + }; + + union + { + __IOM uint32_t ADDOPCRA7; /*!< (@ 0x00000674) A/D Conversion Data Operation Control A Register + * 7 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA7_b; + }; + + union + { + __IOM uint32_t ADDOPCRB7; /*!< (@ 0x00000678) A/D Conversion Data Operation Control B Register + * 7 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB7_b; + }; + + union + { + __IOM uint32_t ADDOPCRC7; /*!< (@ 0x0000067C) A/D Conversion Data Operation Control C Register + * 7 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC7_b; + }; + + union + { + __IOM uint32_t ADCHCR8; /*!< (@ 0x00000680) A/D Conversion Channel Configuration Register + * 8 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR8_b; + }; + + union + { + __IOM uint32_t ADDOPCRA8; /*!< (@ 0x00000684) A/D Conversion Data Operation Control A Register + * 8 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA8_b; + }; + + union + { + __IOM uint32_t ADDOPCRB8; /*!< (@ 0x00000688) A/D Conversion Data Operation Control B Register + * 8 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB8_b; + }; + + union + { + __IOM uint32_t ADDOPCRC8; /*!< (@ 0x0000068C) A/D Conversion Data Operation Control C Register + * 8 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC8_b; + }; + + union + { + __IOM uint32_t ADCHCR9; /*!< (@ 0x00000690) A/D Conversion Channel Configuration Register + * 9 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR9_b; + }; + + union + { + __IOM uint32_t ADDOPCRA9; /*!< (@ 0x00000694) A/D Conversion Data Operation Control A Register + * 9 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA9_b; + }; + + union + { + __IOM uint32_t ADDOPCRB9; /*!< (@ 0x00000698) A/D Conversion Data Operation Control B Register + * 9 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB9_b; + }; + + union + { + __IOM uint32_t ADDOPCRC9; /*!< (@ 0x0000069C) A/D Conversion Data Operation Control C Register + * 9 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC9_b; + }; + + union + { + __IOM uint32_t ADCHCR10; /*!< (@ 0x000006A0) A/D Conversion Channel Configuration Register + * 10 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR10_b; + }; + + union + { + __IOM uint32_t ADDOPCRA10; /*!< (@ 0x000006A4) A/D Conversion Data Operation Control A Register + * 10 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA10_b; + }; + + union + { + __IOM uint32_t ADDOPCRB10; /*!< (@ 0x000006A8) A/D Conversion Data Operation Control B Register + * 10 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB10_b; + }; + + union + { + __IOM uint32_t ADDOPCRC10; /*!< (@ 0x000006AC) A/D Conversion Data Operation Control C Register + * 10 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC10_b; + }; + + union + { + __IOM uint32_t ADCHCR11; /*!< (@ 0x000006B0) A/D Conversion Channel Configuration Register + * 11 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR11_b; + }; + + union + { + __IOM uint32_t ADDOPCRA11; /*!< (@ 0x000006B4) A/D Conversion Data Operation Control A Register + * 11 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA11_b; + }; + + union + { + __IOM uint32_t ADDOPCRB11; /*!< (@ 0x000006B8) A/D Conversion Data Operation Control B Register + * 11 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB11_b; + }; + + union + { + __IOM uint32_t ADDOPCRC11; /*!< (@ 0x000006BC) A/D Conversion Data Operation Control C Register + * 11 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC11_b; + }; + + union + { + __IOM uint32_t ADCHCR12; /*!< (@ 0x000006C0) A/D Conversion Channel Configuration Register + * 12 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR12_b; + }; + + union + { + __IOM uint32_t ADDOPCRA12; /*!< (@ 0x000006C4) A/D Conversion Data Operation Control A Register + * 12 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA12_b; + }; + + union + { + __IOM uint32_t ADDOPCRB12; /*!< (@ 0x000006C8) A/D Conversion Data Operation Control B Register + * 12 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB12_b; + }; + + union + { + __IOM uint32_t ADDOPCRC12; /*!< (@ 0x000006CC) A/D Conversion Data Operation Control C Register + * 12 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC12_b; + }; + + union + { + __IOM uint32_t ADCHCR13; /*!< (@ 0x000006D0) A/D Conversion Channel Configuration Register + * 13 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR13_b; + }; + + union + { + __IOM uint32_t ADDOPCRA13; /*!< (@ 0x000006D4) A/D Conversion Data Operation Control A Register + * 13 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA13_b; + }; + + union + { + __IOM uint32_t ADDOPCRB13; /*!< (@ 0x000006D8) A/D Conversion Data Operation Control B Register + * 13 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB13_b; + }; + + union + { + __IOM uint32_t ADDOPCRC13; /*!< (@ 0x000006DC) A/D Conversion Data Operation Control C Register + * 13 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC13_b; + }; + + union + { + __IOM uint32_t ADCHCR14; /*!< (@ 0x000006E0) A/D Conversion Channel Configuration Register + * 14 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR14_b; + }; + + union + { + __IOM uint32_t ADDOPCRA14; /*!< (@ 0x000006E4) A/D Conversion Data Operation Control A Register + * 14 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA14_b; + }; + + union + { + __IOM uint32_t ADDOPCRB14; /*!< (@ 0x000006E8) A/D Conversion Data Operation Control B Register + * 14 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB14_b; + }; + + union + { + __IOM uint32_t ADDOPCRC14; /*!< (@ 0x000006EC) A/D Conversion Data Operation Control C Register + * 14 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC14_b; + }; + + union + { + __IOM uint32_t ADCHCR15; /*!< (@ 0x000006F0) A/D Conversion Channel Configuration Register + * 15 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR15_b; + }; + + union + { + __IOM uint32_t ADDOPCRA15; /*!< (@ 0x000006F4) A/D Conversion Data Operation Control A Register + * 15 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA15_b; + }; + + union + { + __IOM uint32_t ADDOPCRB15; /*!< (@ 0x000006F8) A/D Conversion Data Operation Control B Register + * 15 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB15_b; + }; + + union + { + __IOM uint32_t ADDOPCRC15; /*!< (@ 0x000006FC) A/D Conversion Data Operation Control C Register + * 15 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC15_b; + }; + + union + { + __IOM uint32_t ADCHCR16; /*!< (@ 0x00000700) A/D Conversion Channel Configuration Register + * 16 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR16_b; + }; + + union + { + __IOM uint32_t ADDOPCRA16; /*!< (@ 0x00000704) A/D Conversion Data Operation Control A Register + * 16 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA16_b; + }; + + union + { + __IOM uint32_t ADDOPCRB16; /*!< (@ 0x00000708) A/D Conversion Data Operation Control B Register + * 16 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB16_b; + }; + + union + { + __IOM uint32_t ADDOPCRC16; /*!< (@ 0x0000070C) A/D Conversion Data Operation Control C Register + * 16 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC16_b; + }; + + union + { + __IOM uint32_t ADCHCR17; /*!< (@ 0x00000710) A/D Conversion Channel Configuration Register + * 17 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR17_b; + }; + + union + { + __IOM uint32_t ADDOPCRA17; /*!< (@ 0x00000714) A/D Conversion Data Operation Control A Register + * 17 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA17_b; + }; + + union + { + __IOM uint32_t ADDOPCRB17; /*!< (@ 0x00000718) A/D Conversion Data Operation Control B Register + * 17 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB17_b; + }; + + union + { + __IOM uint32_t ADDOPCRC17; /*!< (@ 0x0000071C) A/D Conversion Data Operation Control C Register + * 17 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC17_b; + }; + + union + { + __IOM uint32_t ADCHCR18; /*!< (@ 0x00000720) A/D Conversion Channel Configuration Register + * 18 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR18_b; + }; + + union + { + __IOM uint32_t ADDOPCRA18; /*!< (@ 0x00000724) A/D Conversion Data Operation Control A Register + * 18 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA18_b; + }; + + union + { + __IOM uint32_t ADDOPCRB18; /*!< (@ 0x00000728) A/D Conversion Data Operation Control B Register + * 18 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB18_b; + }; + + union + { + __IOM uint32_t ADDOPCRC18; /*!< (@ 0x0000072C) A/D Conversion Data Operation Control C Register + * 18 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC18_b; + }; + + union + { + __IOM uint32_t ADCHCR19; /*!< (@ 0x00000730) A/D Conversion Channel Configuration Register + * 19 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR19_b; + }; + + union + { + __IOM uint32_t ADDOPCRA19; /*!< (@ 0x00000734) A/D Conversion Data Operation Control A Register + * 19 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA19_b; + }; + + union + { + __IOM uint32_t ADDOPCRB19; /*!< (@ 0x00000738) A/D Conversion Data Operation Control B Register + * 19 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB19_b; + }; + + union + { + __IOM uint32_t ADDOPCRC19; /*!< (@ 0x0000073C) A/D Conversion Data Operation Control C Register + * 19 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC19_b; + }; + + union + { + __IOM uint32_t ADCHCR20; /*!< (@ 0x00000740) A/D Conversion Channel Configuration Register + * 20 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR20_b; + }; + + union + { + __IOM uint32_t ADDOPCRA20; /*!< (@ 0x00000744) A/D Conversion Data Operation Control A Register + * 20 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA20_b; + }; + + union + { + __IOM uint32_t ADDOPCRB20; /*!< (@ 0x00000748) A/D Conversion Data Operation Control B Register + * 20 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB20_b; + }; + + union + { + __IOM uint32_t ADDOPCRC20; /*!< (@ 0x0000074C) A/D Conversion Data Operation Control C Register + * 20 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC20_b; + }; + + union + { + __IOM uint32_t ADCHCR21; /*!< (@ 0x00000750) A/D Conversion Channel Configuration Register + * 21 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR21_b; + }; + + union + { + __IOM uint32_t ADDOPCRA21; /*!< (@ 0x00000754) A/D Conversion Data Operation Control A Register + * 21 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA21_b; + }; + + union + { + __IOM uint32_t ADDOPCRB21; /*!< (@ 0x00000758) A/D Conversion Data Operation Control B Register + * 21 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB21_b; + }; + + union + { + __IOM uint32_t ADDOPCRC21; /*!< (@ 0x0000075C) A/D Conversion Data Operation Control C Register + * 21 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC21_b; + }; + + union + { + __IOM uint32_t ADCHCR22; /*!< (@ 0x00000760) A/D Conversion Channel Configuration Register + * 22 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR22_b; + }; + + union + { + __IOM uint32_t ADDOPCRA22; /*!< (@ 0x00000764) A/D Conversion Data Operation Control A Register + * 22 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA22_b; + }; + + union + { + __IOM uint32_t ADDOPCRB22; /*!< (@ 0x00000768) A/D Conversion Data Operation Control B Register + * 22 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB22_b; + }; + + union + { + __IOM uint32_t ADDOPCRC22; /*!< (@ 0x0000076C) A/D Conversion Data Operation Control C Register + * 22 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC22_b; + }; + + union + { + __IOM uint32_t ADCHCR23; /*!< (@ 0x00000770) A/D Conversion Channel Configuration Register + * 23 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR23_b; + }; + + union + { + __IOM uint32_t ADDOPCRA23; /*!< (@ 0x00000774) A/D Conversion Data Operation Control A Register + * 23 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA23_b; + }; + + union + { + __IOM uint32_t ADDOPCRB23; /*!< (@ 0x00000778) A/D Conversion Data Operation Control B Register + * 23 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB23_b; + }; + + union + { + __IOM uint32_t ADDOPCRC23; /*!< (@ 0x0000077C) A/D Conversion Data Operation Control C Register + * 23 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC23_b; + }; + + union + { + __IOM uint32_t ADCHCR24; /*!< (@ 0x00000780) A/D Conversion Channel Configuration Register + * 24 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR24_b; + }; + + union + { + __IOM uint32_t ADDOPCRA24; /*!< (@ 0x00000784) A/D Conversion Data Operation Control A Register + * 24 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA24_b; + }; + + union + { + __IOM uint32_t ADDOPCRB24; /*!< (@ 0x00000788) A/D Conversion Data Operation Control B Register + * 24 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB24_b; + }; + + union + { + __IOM uint32_t ADDOPCRC24; /*!< (@ 0x0000078C) A/D Conversion Data Operation Control C Register + * 24 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC24_b; + }; + + union + { + __IOM uint32_t ADCHCR25; /*!< (@ 0x00000790) A/D Conversion Channel Configuration Register + * 25 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR25_b; + }; + + union + { + __IOM uint32_t ADDOPCRA25; /*!< (@ 0x00000794) A/D Conversion Data Operation Control A Register + * 25 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA25_b; + }; + + union + { + __IOM uint32_t ADDOPCRB25; /*!< (@ 0x00000798) A/D Conversion Data Operation Control B Register + * 25 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB25_b; + }; + + union + { + __IOM uint32_t ADDOPCRC25; /*!< (@ 0x0000079C) A/D Conversion Data Operation Control C Register + * 25 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC25_b; + }; + + union + { + __IOM uint32_t ADCHCR26; /*!< (@ 0x000007A0) A/D Conversion Channel Configuration Register + * 26 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR26_b; + }; + + union + { + __IOM uint32_t ADDOPCRA26; /*!< (@ 0x000007A4) A/D Conversion Data Operation Control A Register + * 26 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA26_b; + }; + + union + { + __IOM uint32_t ADDOPCRB26; /*!< (@ 0x000007A8) A/D Conversion Data Operation Control B Register + * 26 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB26_b; + }; + + union + { + __IOM uint32_t ADDOPCRC26; /*!< (@ 0x000007AC) A/D Conversion Data Operation Control C Register + * 26 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC26_b; + }; + + union + { + __IOM uint32_t ADCHCR27; /*!< (@ 0x000007B0) A/D Conversion Channel Configuration Register + * 27 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR27_b; + }; + + union + { + __IOM uint32_t ADDOPCRA27; /*!< (@ 0x000007B4) A/D Conversion Data Operation Control A Register + * 27 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA27_b; + }; + + union + { + __IOM uint32_t ADDOPCRB27; /*!< (@ 0x000007B8) A/D Conversion Data Operation Control B Register + * 27 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB27_b; + }; + + union + { + __IOM uint32_t ADDOPCRC27; /*!< (@ 0x000007BC) A/D Conversion Data Operation Control C Register + * 27 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC27_b; + }; + + union + { + __IOM uint32_t ADCHCR28; /*!< (@ 0x000007C0) A/D Conversion Channel Configuration Register + * 28 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR28_b; + }; + + union + { + __IOM uint32_t ADDOPCRA28; /*!< (@ 0x000007C4) A/D Conversion Data Operation Control A Register + * 28 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA28_b; + }; + + union + { + __IOM uint32_t ADDOPCRB28; /*!< (@ 0x000007C8) A/D Conversion Data Operation Control B Register + * 28 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB28_b; + }; + + union + { + __IOM uint32_t ADDOPCRC28; /*!< (@ 0x000007CC) A/D Conversion Data Operation Control C Register + * 28 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC28_b; + }; + + union + { + __IOM uint32_t ADCHCR29; /*!< (@ 0x000007D0) A/D Conversion Channel Configuration Register + * 29 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR29_b; + }; + + union + { + __IOM uint32_t ADDOPCRA29; /*!< (@ 0x000007D4) A/D Conversion Data Operation Control A Register + * 29 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA29_b; + }; + + union + { + __IOM uint32_t ADDOPCRB29; /*!< (@ 0x000007D8) A/D Conversion Data Operation Control B Register + * 29 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB29_b; + }; + + union + { + __IOM uint32_t ADDOPCRC29; /*!< (@ 0x000007DC) A/D Conversion Data Operation Control C Register + * 29 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC29_b; + }; + + union + { + __IOM uint32_t ADCHCR30; /*!< (@ 0x000007E0) A/D Conversion Channel Configuration Register + * 30 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR30_b; + }; + + union + { + __IOM uint32_t ADDOPCRA30; /*!< (@ 0x000007E4) A/D Conversion Data Operation Control A Register + * 30 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA30_b; + }; + + union + { + __IOM uint32_t ADDOPCRB30; /*!< (@ 0x000007E8) A/D Conversion Data Operation Control B Register + * 30 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB30_b; + }; + + union + { + __IOM uint32_t ADDOPCRC30; /*!< (@ 0x000007EC) A/D Conversion Data Operation Control C Register + * 30 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC30_b; + }; + + union + { + __IOM uint32_t ADCHCR31; /*!< (@ 0x000007F0) A/D Conversion Channel Configuration Register + * 31 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR31_b; + }; + + union + { + __IOM uint32_t ADDOPCRA31; /*!< (@ 0x000007F4) A/D Conversion Data Operation Control A Register + * 31 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA31_b; + }; + + union + { + __IOM uint32_t ADDOPCRB31; /*!< (@ 0x000007F8) A/D Conversion Data Operation Control B Register + * 31 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB31_b; + }; + + union + { + __IOM uint32_t ADDOPCRC31; /*!< (@ 0x000007FC) A/D Conversion Data Operation Control C Register + * 31 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC31_b; + }; + + union + { + __IOM uint32_t ADCHCR32; /*!< (@ 0x00000800) A/D Conversion Channel Configuration Register + * 32 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR32_b; + }; + + union + { + __IOM uint32_t ADDOPCRA32; /*!< (@ 0x00000804) A/D Conversion Data Operation Control A Register + * 32 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA32_b; + }; + + union + { + __IOM uint32_t ADDOPCRB32; /*!< (@ 0x00000808) A/D Conversion Data Operation Control B Register + * 32 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB32_b; + }; + + union + { + __IOM uint32_t ADDOPCRC32; /*!< (@ 0x0000080C) A/D Conversion Data Operation Control C Register + * 32 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC32_b; + }; + __IM uint32_t RESERVED27[252]; + + union + { + __OM uint32_t ADCALSTR; /*!< (@ 0x00000C00) A/D Converter Calibration Start Register */ + + struct + { + __OM uint32_t ADCALST0 : 3; /*!< [2..0] A/D Converter Unit 0 (ADC0) Calibration Start Control + * bits */ + uint32_t : 5; + __OM uint32_t ADCALST1 : 3; /*!< [10..8] A/D Converter Unit 1 (ADC1) Calibration Start Control + * bits */ + uint32_t : 21; + } ADCALSTR_b; + }; + __IM uint32_t RESERVED28; + + union + { + __IOM uint32_t ADTRGENR; /*!< (@ 0x00000C08) A/D Conversion Start Trigger Enable Register */ + + struct + { + __IOM uint32_t STTRGENn : 9; /*!< [8..0] Scan Group n A/D Conversion Start Trigger Enable */ + uint32_t : 23; + } ADTRGENR_b; + }; + __IM uint32_t RESERVED29; + + union + { + __OM uint32_t ADSYSTR; /*!< (@ 0x00000C10) A/D Conversion Synchronous Software Start Register */ + + struct + { + __OM uint32_t ADSYSTn : 9; /*!< [8..0] Scan Group n : A/D Conversion start */ + uint32_t : 23; + } ADSYSTR_b; + }; + __IM uint32_t RESERVED30[3]; + + union + { + __OM uint32_t ADSTR[9]; /*!< (@ 0x00000C20) A/D Conversion Software Start Register [0..8] */ + + struct + { + __OM uint32_t ADST : 1; /*!< [0..0] Scan Group n A/D Conversion Start */ + uint32_t : 31; + } ADSTR_b[9]; + }; + __IM uint32_t RESERVED31[7]; + + union + { + __OM uint32_t ADSTOPR; /*!< (@ 0x00000C60) A/D Conversion Stop Register */ + + struct + { + __OM uint32_t ADSTOP0 : 1; /*!< [0..0] A/D Converter Unit 0 Force Stop bit */ + uint32_t : 7; + __OM uint32_t ADSTOP1 : 1; /*!< [8..8] A/D Converter Unit 1 Force Stop bit */ + uint32_t : 23; + } ADSTOPR_b; + }; + __IM uint32_t RESERVED32[7]; + + union + { + __IM uint32_t ADSR; /*!< (@ 0x00000C80) A/D Conversion Status Register */ + + struct + { + __IM uint32_t ADACT0 : 1; /*!< [0..0] A/D Converter Unit 0 (ADC0) A/D Conversion Status */ + __IM uint32_t ADACT1 : 1; /*!< [1..1] A/D Converter Unit 1 (ADC1) A/D Conversion Status */ + uint32_t : 14; + __IM uint32_t CALACT0 : 1; /*!< [16..16] A/D Converter Unit 0 (ADC0) : Calibration Status */ + __IM uint32_t CALACT1 : 1; /*!< [17..17] A/D Converter Unit 1 (ADC1) : Calibration Status */ + uint32_t : 14; + } ADSR_b; + }; + + union + { + __IM uint32_t ADGRSR; /*!< (@ 0x00000C84) Scan Group Status Register */ + + struct + { + __IM uint32_t ACTGRn : 9; /*!< [8..0] Scan Group n Status */ + uint32_t : 23; + } ADGRSR_b; + }; + + union + { + __IM uint32_t ADERSR; /*!< (@ 0x00000C88) A/D Conversion Error Status Register */ + + struct + { + __IM uint32_t ADERF0 : 1; /*!< [0..0] A/D Converter Unit 0 (ADC0) Error Flag */ + __IM uint32_t ADERF1 : 1; /*!< [1..1] A/D Converter Unit 1 (ADC1) Error Flag */ + uint32_t : 30; + } ADERSR_b; + }; + + union + { + __OM uint32_t ADERSCR; /*!< (@ 0x00000C8C) A/D Conversion Error Status Clear Register */ + + struct + { + __OM uint32_t ADERCLR0 : 1; /*!< [0..0] A/D Converter Unit 0 Error Flag Clear */ + __OM uint32_t ADERCLR1 : 1; /*!< [1..1] A/D Converter Unit 1 Error Flag Clear */ + uint32_t : 30; + } ADERSCR_b; + }; + __IM uint32_t RESERVED33[2]; + + union + { + __IM uint32_t ADCALENDSR; /*!< (@ 0x00000C98) A/D Converter Calibration End Status Register */ + + struct + { + __IM uint32_t CALENDF0 : 1; /*!< [0..0] A/D Converter Unit 0 Calibration End flag */ + __IM uint32_t CALENDF1 : 1; /*!< [1..1] A/D Converter Unit 1 Calibration End flag */ + uint32_t : 30; + } ADCALENDSR_b; + }; + + union + { + __OM uint32_t ADCALENDSCR; /*!< (@ 0x00000C9C) A/D Converter Calibration End Status Clear Register */ + + struct + { + __OM uint32_t CALENDC0 : 1; /*!< [0..0] A/D Converter Unit 0 Calibration End Flag Clear */ + __OM uint32_t CALENDC1 : 1; /*!< [1..1] A/D Converter Unit 1 Calibration End Flag Clear */ + uint32_t : 30; + } ADCALENDSCR_b; + }; + + union + { + __IM uint32_t ADOVFERSR; /*!< (@ 0x00000CA0) A/D Conversion Overflow Error Status Register */ + + struct + { + __IM uint32_t ADOVFEF0 : 1; /*!< [0..0] A/D Converter Unit 0 (ADC0) Overflow Error Flag */ + __IM uint32_t ADOVFEF1 : 1; /*!< [1..1] A/D Converter Unit 1 (ADC1) Overflow Error Flag */ + uint32_t : 30; + } ADOVFERSR_b; + }; + + union + { + __IM uint32_t ADOVFCHSR0; /*!< (@ 0x00000CA4) A/D Conversion Overflow Channel Status Register + * 0 */ + + struct + { + __IM uint32_t OVFCHFn : 23; /*!< [22..0] Analog Input Channel No. n : Overflow Flag */ + uint32_t : 9; + } ADOVFCHSR0_b; + }; + __IM uint32_t RESERVED34[2]; + + union + { + __IM uint32_t ADOVFEXSR; /*!< (@ 0x00000CB0) Extended Analog A/D Conversion Overflow Status + * Register */ + + struct + { + __IM uint32_t OVFEXF0 : 1; /*!< [0..0] Self-diagnosis Channel for A/D unit 0: Overflow Flag */ + __IM uint32_t OVFEXF1 : 1; /*!< [1..1] Self-diagnosis Channel for A/D unit 1: Overflow Flag */ + uint32_t : 2; + __IM uint32_t OVFEXF4 : 1; /*!< [4..4] Temperature Sensor Channel: Overflow Flag */ + __IM uint32_t OVFEXF5 : 1; /*!< [5..5] Internal Reference Voltage Channel: Overflow Flag */ + __IM uint32_t OVFEXF6 : 1; /*!< [6..6] VBATT 1/3 voltage monitor output Channel: Overflow Flag */ + uint32_t : 1; + __IM uint32_t OVFEXF8 : 1; /*!< [8..8] D/A Converter 0 Channel: Overflow Flag */ + __IM uint32_t OVFEXF9 : 1; /*!< [9..9] D/A Converter 1 Channel: Overflow Flag */ + uint32_t : 6; + __IM uint32_t OVFEXF16 : 1; /*!< [16..16] Self-diagnosis Channel for Sample-and-hold circuit + * unit0: Overflow Flag */ + __IM uint32_t OVFEXF17 : 1; /*!< [17..17] Self-diagnosis Channel for Sample-and-hold circuit + * unit1: Overflow Flag */ + __IM uint32_t OVFEXF18 : 1; /*!< [18..18] Self-diagnosis Channel for Sample-and-hold circuit + * unit2: Overflow Flag */ + uint32_t : 1; + __IM uint32_t OVFEXF20 : 1; /*!< [20..20] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Overflow Flag */ + __IM uint32_t OVFEXF21 : 1; /*!< [21..21] Self-diagnosis Channel for Sample-and-hold circuit + * unit5: Overflow Flag */ + __IM uint32_t OVFEXF22 : 1; /*!< [22..22] Self-diagnosis Channel for Sample-and-hold circuit + * unit6: Overflow Flag */ + uint32_t : 9; + } ADOVFEXSR_b; + }; + + union + { + __OM uint32_t ADOVFERSCR; /*!< (@ 0x00000CB4) A/D Conversion Overflow Error Status Clear Register */ + + struct + { + __OM uint32_t ADOVFEC0 : 1; /*!< [0..0] A/D Converter Unit 0 (ADC0) Overflow Error Flag Clear */ + __OM uint32_t ADOVFEC1 : 1; /*!< [1..1] A/D Converter Unit 1 (ADC1) Overflow Error Flag Clear */ + uint32_t : 30; + } ADOVFERSCR_b; + }; + + union + { + __OM uint32_t ADOVFCHSCR0; /*!< (@ 0x00000CB8) A/D Conversion Overflow Channel Status Clear + * Register 0 */ + + struct + { + __OM uint32_t OVFCHCn : 23; /*!< [22..0] Analog Input Channel No. n : Overflow Flag Clear */ + uint32_t : 9; + } ADOVFCHSCR0_b; + }; + __IM uint32_t RESERVED35[2]; + + union + { + __OM uint32_t ADOVFEXSCR; /*!< (@ 0x00000CC4) Extended Analog A/D Conversion Overflow Status + * Clear Register */ + + struct + { + __OM uint32_t OVFEXC0 : 1; /*!< [0..0] Self-diagnosis Channel for A/D unit 0: Compare Match + * Flag Clear */ + __OM uint32_t OVFEXC1 : 1; /*!< [1..1] Self-diagnosis Channel for A/D unit 1: Compare Match + * Flag Clear */ + uint32_t : 2; + __OM uint32_t OVFEXC4 : 1; /*!< [4..4] Temperature Sensor Channel: Compare Match Flag Clear */ + __OM uint32_t OVFEXC5 : 1; /*!< [5..5] Internal Reference Voltage Channel: Compare Match Flag + * Clear */ + __OM uint32_t OVFEXC6 : 1; /*!< [6..6] VBATT 1/3 voltage monitor output Channel: Compare Match + * Flag Clear */ + uint32_t : 1; + __OM uint32_t OVFEXC8 : 1; /*!< [8..8] D/A Converter 0 Channel: Compare Match Flag Clear */ + __OM uint32_t OVFEXC9 : 1; /*!< [9..9] D/A Converter 1 Channel: Compare Match Flag Clear */ + uint32_t : 6; + __OM uint32_t OVFEXC16 : 1; /*!< [16..16] Self-diagnosis Channel for Sample-and-hold circuit + * unit0: Compare Match Flag Clear */ + __OM uint32_t OVFEXC17 : 1; /*!< [17..17] Self-diagnosis Channel for Sample-and-hold circuit + * unit1: Compare Match Flag Clear */ + __OM uint32_t OVFEXC18 : 1; /*!< [18..18] Self-diagnosis Channel for Sample-and-hold circuit + * unit2: Compare Match Flag Clear */ + uint32_t : 1; + __OM uint32_t OVFEXC20 : 1; /*!< [20..20] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Compare Match Flag Clear */ + __OM uint32_t OVFEXC21 : 1; /*!< [21..21] Self-diagnosis Channel for Sample-and-hold circuit + * unit5: Compare Match Flag Clear */ + __OM uint32_t OVFEXC22 : 1; /*!< [22..22] Self-diagnosis Channel for Sample-and-hold circuit + * unit6: Compare Match Flag Clear */ + uint32_t : 9; + } ADOVFEXSCR_b; + }; + __IM uint32_t RESERVED36[2]; + + union + { + __IM uint32_t ADFIFOSR0; /*!< (@ 0x00000CD0) FIFO Status Register 0 */ + + struct + { + __IM uint32_t FIFOST0 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 0 */ + uint32_t : 12; + __IM uint32_t FIFOST1 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 1 */ + uint32_t : 12; + } ADFIFOSR0_b; + }; + + union + { + __IM uint32_t ADFIFOSR1; /*!< (@ 0x00000CD4) FIFO Status Register 1 */ + + struct + { + __IM uint32_t FIFOST2 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 2 */ + uint32_t : 12; + __IM uint32_t FIFOST3 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 3 */ + uint32_t : 12; + } ADFIFOSR1_b; + }; + + union + { + __IM uint32_t ADFIFOSR2; /*!< (@ 0x00000CD8) FIFO Status Register 2 */ + + struct + { + __IM uint32_t FIFOST4 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 4 */ + uint32_t : 12; + __IM uint32_t FIFOST5 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 5 */ + uint32_t : 12; + } ADFIFOSR2_b; + }; + + union + { + __IM uint32_t ADFIFOSR3; /*!< (@ 0x00000CDC) FIFO Status Register 3 */ + + struct + { + __IM uint32_t FIFOST6 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 6 */ + uint32_t : 12; + __IM uint32_t FIFOST7 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 7 */ + uint32_t : 12; + } ADFIFOSR3_b; + }; + + union + { + __IM uint32_t ADFIFOSR4; /*!< (@ 0x00000CE0) FIFO Status Register 4 */ + + struct + { + __IM uint32_t FIFOST8 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 8 */ + uint32_t : 28; + } ADFIFOSR4_b; + }; + __IM uint32_t RESERVED37[3]; + + union + { + __OM uint32_t ADFIFODCR; /*!< (@ 0x00000CF0) FIFO Data Clear Register */ + + struct + { + __OM uint32_t FIFODCn : 9; /*!< [8..0] Scan Group n FIFO Data Clear */ + uint32_t : 23; + } ADFIFODCR_b; + }; + + union + { + __IM uint32_t ADFIFOERSR; /*!< (@ 0x00000CF4) FIFO Error Status Register */ + + struct + { + __IM uint32_t FIFOOVFn : 9; /*!< [8..0] Scan Group n FIFO Overflow Flag */ + uint32_t : 7; + __IM uint32_t FIFOFLFn : 9; /*!< [24..16] Scan Group n FIFO Data Full Flag */ + uint32_t : 7; + } ADFIFOERSR_b; + }; + + union + { + __OM uint32_t ADFIFOERSCR; /*!< (@ 0x00000CF8) FIFO Error Status Clear Register */ + + struct + { + __OM uint32_t FIFOOVFCn : 9; /*!< [8..0] Scan Group n FIFO Overflow Flag Clear */ + uint32_t : 7; + __OM uint32_t FIFOFLCn : 9; /*!< [24..16] Scan Group n FIFO Data Full Flag Clear */ + uint32_t : 7; + } ADFIFOERSCR_b; + }; + __IM uint32_t RESERVED38; + + union + { + __IM uint32_t ADCMPTBSR; /*!< (@ 0x00000D00) Compare Match Table Status Register */ + + struct + { + __IM uint32_t CMPTBFn : 8; /*!< [7..0] Compare Match Table n Match Flag */ + uint32_t : 24; + } ADCMPTBSR_b; + }; + + union + { + __OM uint32_t ADCMPTBSCR; /*!< (@ 0x00000D04) Compare Match Table Status Clear Register */ + + struct + { + __OM uint32_t CMPTBCn : 8; /*!< [7..0] Compare Match Table n : Match Flag Clear */ + uint32_t : 24; + } ADCMPTBSCR_b; + }; + + union + { + __IM uint32_t ADCMPCHSR0; /*!< (@ 0x00000D08) Compare Match Channel Status Register 0 */ + + struct + { + __IM uint32_t CMPCHFn : 23; /*!< [22..0] Analog Channel No. n : Compare Match Flag */ + uint32_t : 9; + } ADCMPCHSR0_b; + }; + __IM uint32_t RESERVED39[2]; + + union + { + __IM uint32_t ADCMPEXSR; /*!< (@ 0x00000D14) Extended Analog Compare Match Status Register */ + + struct + { + __IM uint32_t CMPEXF0 : 1; /*!< [0..0] Self-diagnosis Channel for A/D unit 0: Compare Match + * Flag */ + __IM uint32_t CMPEXF1 : 1; /*!< [1..1] Self-diagnosis Channel for A/D unit 1: Compare Match + * Flag */ + uint32_t : 2; + __IM uint32_t CMPEXF4 : 1; /*!< [4..4] Temperature Sensor Channel: Compare Match Flag */ + __IM uint32_t CMPEXF5 : 1; /*!< [5..5] Internal Reference Voltage Channel: Compare Match Flag */ + __IM uint32_t CMPEXF6 : 1; /*!< [6..6] VBATT 1/3 voltage monitor output Channel: Compare Match + * Flag */ + uint32_t : 1; + __IM uint32_t CMPEXF8 : 1; /*!< [8..8] D/A Converter 0 Channel : Compare Match Flag */ + __IM uint32_t CMPEXF9 : 1; /*!< [9..9] D/A Converter 1 Channel: Compare Match Flag */ + uint32_t : 6; + __IM uint32_t CMPEXF16 : 1; /*!< [16..16] Self-diagnosis Channel for Sample-and-hold circuit + * unit0: Compare Match Flag */ + __IM uint32_t CMPEXF17 : 1; /*!< [17..17] Self-diagnosis Channel for Sample-and-hold circuit + * unit1: Compare Match Flag */ + __IM uint32_t CMPEXF18 : 1; /*!< [18..18] Self-diagnosis Channel for Sample-and-hold circuit + * unit2: Compare Match Flag */ + uint32_t : 1; + __IM uint32_t CMPEXF20 : 1; /*!< [20..20] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Compare Match Flag */ + __IM uint32_t CMPEXF21 : 1; /*!< [21..21] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Compare Match Flag */ + __IM uint32_t CMPEXF22 : 1; /*!< [22..22] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Compare Match Flag */ + uint32_t : 9; + } ADCMPEXSR_b; + }; + + union + { + __OM uint32_t ADCMPCHSCR0; /*!< (@ 0x00000D18) Compare Match Channel Status Clear Register 0 */ + + struct + { + __OM uint32_t CMPCHCn : 23; /*!< [22..0] Analog Channel No. n : Compare Match Flag Clear bit */ + uint32_t : 9; + } ADCMPCHSCR0_b; + }; + __IM uint32_t RESERVED40[2]; + + union + { + __OM uint32_t ADCMPEXSCR; /*!< (@ 0x00000D24) Extended Analog Compare Match Status Clear Register */ + + struct + { + __OM uint32_t CMPEXC0 : 1; /*!< [0..0] Self-diagnosis Channel for A/D unit 0: Compare Match + * Flag Clear */ + __OM uint32_t CMPEXC1 : 1; /*!< [1..1] Self-diagnosis Channel for A/D unit 1: Compare Match + * Flag Clear */ + uint32_t : 2; + __OM uint32_t CMPEXC4 : 1; /*!< [4..4] Temperature Sensor Channel: Compare Match Flag Clear */ + __OM uint32_t CMPEXC5 : 1; /*!< [5..5] Internal Reference Voltage Channel: Compare Match Flag + * Clear */ + __OM uint32_t CMPEXC6 : 1; /*!< [6..6] VBATT 1/3 voltage monitor output Channel: Compare Match + * Flag Clear */ + uint32_t : 1; + __OM uint32_t CMPEXC8 : 1; /*!< [8..8] D/A Converter 0 Channel: Compare Match Flag Clear */ + __OM uint32_t CMPEXC9 : 1; /*!< [9..9] D/A Converter 1 Channel : Compare Match Flag Clear */ + uint32_t : 6; + __OM uint32_t CMPEXC16 : 1; /*!< [16..16] Self-diagnosis Channel for Sample-and-hold circuit + * unit0: Compare Match Flag Clear */ + __OM uint32_t CMPEXC17 : 1; /*!< [17..17] Self-diagnosis Channel for Sample-and-hold circuit + * unit1: Compare Match Flag Clear */ + __OM uint32_t CMPEXC18 : 1; /*!< [18..18] Self-diagnosis Channel for Sample-and-hold circuit + * unit2: Compare Match Flag Clear */ + uint32_t : 1; + __OM uint32_t CMPEXC20 : 1; /*!< [20..20] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Compare Match Flag Clear */ + __OM uint32_t CMPEXC21 : 1; /*!< [21..21] Self-diagnosis Channel for Sample-and-hold circuit + * unit5: Compare Match Flag Clear */ + __OM uint32_t CMPEXC22 : 1; /*!< [22..22] Self-diagnosis Channel for Sample-and-hold circuit + * unit6: Compare Match Flag Clear */ + uint32_t : 9; + } ADCMPEXSCR_b; + }; + + union + { + __IM uint32_t ADLIMGRSR; /*!< (@ 0x00000D28) Limiter Clip Scan Group Status Register */ + + struct + { + __IM uint32_t LIMGRFn : 9; /*!< [8..0] Scan Group n Limiter Clip Flag */ + uint32_t : 23; + } ADLIMGRSR_b; + }; + + union + { + __IM uint32_t ADLIMCHSR0; /*!< (@ 0x00000D2C) Limiter Clip Channel Status Register 0 */ + + struct + { + __IM uint32_t LIMCHFn : 23; /*!< [22..0] Analog Channel No. n : Limiter Clip Flag bit */ + uint32_t : 9; + } ADLIMCHSR0_b; + }; + __IM uint32_t RESERVED41[2]; + + union + { + __IM uint32_t ADLIMEXSR; /*!< (@ 0x00000D38) Extended Analog Limiter Clip Status Register */ + + struct + { + __IM uint32_t LIMEXF0 : 1; /*!< [0..0] Self-diagnosis Channel for A/D unit 0: Limiter Clip Flag */ + __IM uint32_t LIMEXF1 : 1; /*!< [1..1] Temperature Sensor Channel for A/D unit 1: Limiter Clip + * Flag */ + uint32_t : 2; + __IM uint32_t LIMEXF4 : 1; /*!< [4..4] Temperature Sensor Channel: Limiter Clip Flag */ + __IM uint32_t LIMEXF5 : 1; /*!< [5..5] Internal Reference Voltage Channel: Limiter Clip Flag */ + __IM uint32_t LIMEXF6 : 1; /*!< [6..6] VBATT 1/3 voltage monitor output Channel: Limiter Clip + * Flag */ + uint32_t : 1; + __IM uint32_t LIMEXF8 : 1; /*!< [8..8] D/A Converter 0 Channel: Limiter Clip Flag */ + __IM uint32_t LIMEXF9 : 1; /*!< [9..9] D/A Converter 1 Channel: Limiter Clip Flag */ + uint32_t : 6; + __IM uint32_t LIMEXF16 : 1; /*!< [16..16] Self-diagnosis Channel for Sample-and-hold circuit + * unit0: Limiter Clip Flag */ + __IM uint32_t LIMEXF17 : 1; /*!< [17..17] Self-diagnosis Channel for Sample-and-hold circuit + * unit1: Limiter Clip Flag */ + __IM uint32_t LIMEXF18 : 1; /*!< [18..18] Self-diagnosis Channel for Sample-and-hold circuit + * unit2: Limiter Clip Flag */ + uint32_t : 1; + __IM uint32_t LIMEXF20 : 1; /*!< [20..20] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Limiter Clip Flag */ + __IM uint32_t LIMEXF21 : 1; /*!< [21..21] Self-diagnosis Channel for Sample-and-hold circuit + * unit5: Limiter Clip Flag */ + __IM uint32_t LIMEXF22 : 1; /*!< [22..22] Self-diagnosis Channel for Sample-and-hold circuit + * unit6: Limiter Clip Flag */ + uint32_t : 9; + } ADLIMEXSR_b; + }; + + union + { + __OM uint32_t ADLIMGRSCR; /*!< (@ 0x00000D3C) Limiter Clip Scan Group Status Clear Register */ + + struct + { + __OM uint32_t LIMGRCn : 9; /*!< [8..0] Scan Group n Limiter Clip Flag Clear */ + uint32_t : 23; + } ADLIMGRSCR_b; + }; + + union + { + __OM uint32_t ADLIMCHSCR0; /*!< (@ 0x00000D40) Limiter Clip Channel Status Clear Register 0 */ + + struct + { + __OM uint32_t LIMCHCn : 23; /*!< [22..0] Analog Channel No. n Limiter Clip Flag Clear bit */ + uint32_t : 9; + } ADLIMCHSCR0_b; + }; + __IM uint32_t RESERVED42[2]; + + union + { + __OM uint32_t ADLIMEXSCR; /*!< (@ 0x00000D4C) Extended Analog Limiter Clip Status Clear Register */ + + struct + { + __OM uint32_t LIMEXF0 : 1; /*!< [0..0] Self-diagnosis Channel for A/D unit 0: Limiter Clip Flag + * Clear */ + __OM uint32_t LIMEXF1 : 1; /*!< [1..1] Self-diagnosis Channel for A/D unit 1: Limiter Clip Flag + * Clear */ + uint32_t : 2; + __OM uint32_t LIMEXF4 : 1; /*!< [4..4] Temperature Sensor Channel: Limiter Clip Flag Clear */ + __OM uint32_t LIMEXF5 : 1; /*!< [5..5] Internal Reference Voltage Channel: Limiter Clip Flag + * Clear */ + __OM uint32_t LIMEXF6 : 1; /*!< [6..6] VBATT 1/3 voltage monitor output Channel: Limiter Clip + * Flag Clear */ + uint32_t : 1; + __OM uint32_t LIMEXF8 : 1; /*!< [8..8] D/A Converter 0 Channel: Limiter Clip Flag Clear */ + __OM uint32_t LIMEXF9 : 1; /*!< [9..9] D/A Converter 1 Channel: Limiter Clip Flag Clear */ + uint32_t : 6; + __OM uint32_t LIMEXF16 : 1; /*!< [16..16] Self-diagnosis Channel for Sample-and-hold circuit + * unit0: Limiter Clip Flag Clear */ + __OM uint32_t LIMEXF17 : 1; /*!< [17..17] Self-diagnosis Channel for Sample-and-hold circuit + * unit1: Limiter Clip Flag Clear */ + __OM uint32_t LIMEXF18 : 1; /*!< [18..18] Self-diagnosis Channel for Sample-and-hold circuit + * unit2: Limiter Clip Flag Clear */ + uint32_t : 1; + __OM uint32_t LIMEXF20 : 1; /*!< [20..20] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Limiter Clip Flag Clear */ + __OM uint32_t LIMEXF21 : 1; /*!< [21..21] Self-diagnosis Channel for Sample-and-hold circuit + * unit5: Limiter Clip Flag Clear */ + __OM uint32_t LIMEXF22 : 1; /*!< [22..22] Self-diagnosis Channel for Sample-and-hold circuit + * unit6: Limiter Clip Flag Clear */ + uint32_t : 9; + } ADLIMEXSCR_b; + }; + + union + { + __IM uint32_t ADSCANENDSR; /*!< (@ 0x00000D50) Scan End Status Register */ + + struct + { + __IM uint32_t SCENDFn : 9; /*!< [8..0] Scan Group n Scan End Flag */ + uint32_t : 23; + } ADSCANENDSR_b; + }; + + union + { + __OM uint32_t ADSCANENDSCR; /*!< (@ 0x00000D54) Scan End Status Clear Register */ + + struct + { + __OM uint32_t SCENDCn : 9; /*!< [8..0] Scan Group n Scan End Flag Clear */ + uint32_t : 23; + } ADSCANENDSCR_b; + }; + __IM uint32_t RESERVED43[1194]; + + union + { + __IM uint32_t ADDR[23]; /*!< (@ 0x00002000) A/D Data Register [0..22] */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D conversion data */ + uint32_t : 15; + __IM uint32_t ERR : 1; /*!< [31..31] A/D conversion data error status */ + } ADDR_b[23]; + }; + __IM uint32_t RESERVED44[73]; + + union + { + __IM uint32_t ADEXDR[23]; /*!< (@ 0x00002180) A/D Extended Analog Data Register [0..22] */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D conversion data */ + uint32_t : 8; + __IM uint32_t DIAGSR : 3; /*!< [26..24] Self-Diagnosis Status */ + uint32_t : 4; + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Error Status */ + } ADEXDR_b[23]; + }; + __IM uint32_t RESERVED45[9]; + + union + { + __IM uint32_t ADFIFODR0; /*!< (@ 0x00002200) FIFO Data Register 0 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR0_b; + }; + + union + { + __IM uint32_t ADFIFODR1; /*!< (@ 0x00002204) FIFO Data Register 1 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR1_b; + }; + + union + { + __IM uint32_t ADFIFODR2; /*!< (@ 0x00002208) FIFO Data Register 2 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR2_b; + }; + + union + { + __IM uint32_t ADFIFODR3; /*!< (@ 0x0000220C) FIFO Data Register 3 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR3_b; + }; + + union + { + __IM uint32_t ADFIFODR4; /*!< (@ 0x00002210) FIFO Data Register 4 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR4_b; + }; + + union + { + __IM uint32_t ADFIFODR5; /*!< (@ 0x00002214) FIFO Data Register 5 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR5_b; + }; + + union + { + __IM uint32_t ADFIFODR6; /*!< (@ 0x00002218) FIFO Data Register 6 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR6_b; + }; + + union + { + __IM uint32_t ADFIFODR7; /*!< (@ 0x0000221C) FIFO Data Register 7 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR7_b; + }; + + union + { + __IM uint32_t ADFIFODR8; /*!< (@ 0x00002220) FIFO Data Register 8 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR8_b; + }; +} R_ADC_B0_Type; /*!< Size = 8740 (0x2224) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC_B ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC_B) + */ + +typedef struct /*!< (@ 0x40311000) R_DOC_B Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t DOBW : 1; /*!< [3..3] Data Operation Bit Width Select */ + __IOM uint8_t DCSEL : 3; /*!< [6..4] Detection Condition Select */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint8_t DOSR; /*!< (@ 0x00000004) DOC Flag Status Register */ + + struct + { + __IM uint8_t DOPCF : 1; /*!< [0..0] Data Operation Circuit Flag */ + uint8_t : 7; + } DOSR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t DOSCR; /*!< (@ 0x00000008) DOC Flag Status Clear Register */ + + struct + { + __OM uint8_t DOPCFCL : 1; /*!< [0..0] DOPCF Clear */ + uint8_t : 7; + } DOSCR_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DODIR; /*!< (@ 0x0000000C) DOC Data Input Register */ + __IOM uint32_t DODSR0; /*!< (@ 0x00000010) DOC Data Setting Register 0 */ + __IOM uint32_t DODSR1; /*!< (@ 0x00000014) DOC Data Setting Register 1 */ +} R_DOC_B_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI_B0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communication Interface 0 (R_SCI_B0) + */ + +typedef struct /*!< (@ 0x40358000) R_SCI_B0 Structure */ +{ + union + { + union + { + __IM uint32_t RDR; /*!< (@ 0x00000000) Receive Data Register */ + + struct + { + __IM uint32_t RDAT : 9; /*!< [8..0] Serial receive data */ + __IM uint32_t MPB : 1; /*!< [9..9] Multi-processor flag */ + __IM uint32_t DR : 1; /*!< [10..10] Receive data ready flag */ + __IM uint32_t FPER : 1; /*!< [11..11] FIFO parity error flag */ + __IM uint32_t FFER : 1; /*!< [12..12] FIFO framing error flag */ + uint32_t : 11; + __IM uint32_t ORER : 1; /*!< [24..24] Overrun Error flag */ + uint32_t : 2; + __IM uint32_t PER : 1; /*!< [27..27] Parity error flag */ + __IM uint32_t FER : 1; /*!< [28..28] Framing error flag */ + uint32_t : 3; + } RDR_b; + }; + + union + { + __IOM uint8_t RDR_BY; /*!< (@ 0x00000000) Receive Data Register (byte access) */ + + struct + { + __IOM uint8_t RDAT : 8; /*!< [7..0] Serial receive data */ + } RDR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t TDR; /*!< (@ 0x00000004) Transmit Data Register */ + + struct + { + __IOM uint32_t TDAT : 9; /*!< [8..0] Serial transmit data */ + __IOM uint32_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag */ + uint32_t : 2; + __IOM uint32_t TSYNC : 1; /*!< [12..12] Transmit SYNC data */ + uint32_t : 19; + } TDR_b; + }; + + union + { + __IOM uint8_t TDR_BY; /*!< (@ 0x00000004) Transmit Data Register (byte access) */ + + struct + { + __IOM uint8_t TDAT : 8; /*!< [7..0] Serial transmit data */ + } TDR_BY_b; + }; + }; + + union + { + __IOM uint32_t CCR0; /*!< (@ 0x00000008) Common Control Register 0 */ + + struct + { + __IOM uint32_t RE : 1; /*!< [0..0] Receive Enable */ + uint32_t : 3; + __IOM uint32_t TE : 1; /*!< [4..4] Transmit Enable */ + uint32_t : 3; + __IOM uint32_t MPIE : 1; /*!< [8..8] Multi-Processor Interrupt Enable */ + __IOM uint32_t DCME : 1; /*!< [9..9] Data Compare Match Enable */ + __IOM uint32_t IDSEL : 1; /*!< [10..10] ID frame select */ + uint32_t : 5; + __IOM uint32_t RIE : 1; /*!< [16..16] Receive Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TIE : 1; /*!< [20..20] Transmit Interrupt Enable */ + __IOM uint32_t TEIE : 1; /*!< [21..21] Transmit End Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SSE : 1; /*!< [24..24] SSn Pin Function Enable */ + uint32_t : 7; + } CCR0_b; + }; + + union + { + __IOM uint32_t CCR1; /*!< (@ 0x0000000C) Common Control Register 1 */ + + struct + { + __IOM uint32_t CTSE : 1; /*!< [0..0] CTS Enable */ + __IOM uint32_t CTSPEN : 1; /*!< [1..1] CTS external pin Enable */ + uint32_t : 2; + __IOM uint32_t SPB2DT : 1; /*!< [4..4] Serial port break data select */ + __IOM uint32_t SPB2IO : 1; /*!< [5..5] Serial port break I/O */ + uint32_t : 2; + __IOM uint32_t PE : 1; /*!< [8..8] Parity Enable */ + __IOM uint32_t PM : 1; /*!< [9..9] Parity Mode */ + uint32_t : 2; + __IOM uint32_t TINV : 1; /*!< [12..12] TXD invert */ + __IOM uint32_t RINV : 1; /*!< [13..13] RXD invert */ + uint32_t : 2; + __IOM uint32_t SPLP : 1; /*!< [16..16] Loopback Control */ + uint32_t : 3; + __IOM uint32_t SHARPS : 1; /*!< [20..20] Half-duplex communication select */ + uint32_t : 3; + __IOM uint32_t NFCS : 3; /*!< [26..24] Noise Filter Clock Select */ + uint32_t : 1; + __IOM uint32_t NFEN : 1; /*!< [28..28] Digital Noise Filter Function Enable */ + uint32_t : 3; + } CCR1_b; + }; + + union + { + __IOM uint32_t CCR2; /*!< (@ 0x00000010) Common Control Register 2 */ + + struct + { + __IOM uint32_t BCP : 3; /*!< [2..0] Base Clock Pulse */ + uint32_t : 1; + __IOM uint32_t BGDM : 1; /*!< [4..4] Baud Rate Generator Double-Speed Mode Select */ + __IOM uint32_t ABCS : 1; /*!< [5..5] Asynchronous Mode Base Clock Select */ + __IOM uint32_t ABCSE : 1; /*!< [6..6] Asynchronous Mode Extended Base Clock Select */ + uint32_t : 1; + __IOM uint32_t BRR : 8; /*!< [15..8] Bit rate setting */ + __IOM uint32_t BRME : 1; /*!< [16..16] Bit Modulation Enable */ + uint32_t : 3; + __IOM uint32_t CKS : 2; /*!< [21..20] Clock Select */ + uint32_t : 2; + __IOM uint32_t MDDR : 8; /*!< [31..24] Modulation Duty Setting */ + } CCR2_b; + }; + + union + { + __IOM uint32_t CCR3; /*!< (@ 0x00000014) Common Control Register 3 */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] Clock Phase Select */ + __IOM uint32_t CPOL : 1; /*!< [1..1] Clock Polarity Select */ + uint32_t : 5; + __IOM uint32_t BPEN : 1; /*!< [7..7] Synchronizer bypass enable */ + __IOM uint32_t CHR : 2; /*!< [9..8] Character Length */ + uint32_t : 2; + __IOM uint32_t LSBF : 1; /*!< [12..12] LSB First select */ + __IOM uint32_t SINV : 1; /*!< [13..13] Transmitted/Received Data Invert */ + __IOM uint32_t STP : 1; /*!< [14..14] Stop Bit Length */ + __IOM uint32_t RXDESEL : 1; /*!< [15..15] Asynchronous Start Bit Edge Detection Select */ + __IOM uint32_t MOD : 3; /*!< [18..16] Communication mode select */ + __IOM uint32_t MP : 1; /*!< [19..19] Multi-Processor Mode */ + __IOM uint32_t FM : 1; /*!< [20..20] FIFO Mode select */ + __IOM uint32_t DEN : 1; /*!< [21..21] Driver enable */ + uint32_t : 2; + __IOM uint32_t CKE : 2; /*!< [25..24] Clock enable */ + uint32_t : 2; + __IOM uint32_t GM : 1; /*!< [28..28] GSM Mode */ + __IOM uint32_t BLK : 1; /*!< [29..29] Block Transfer Mode */ + uint32_t : 2; + } CCR3_b; + }; + + union + { + __IOM uint32_t CCR4; /*!< (@ 0x00000018) Common Control Register 4 */ + + struct + { + __IOM uint32_t CMPD : 9; /*!< [8..0] Compare Match Data */ + uint32_t : 7; + __IOM uint32_t ASEN : 1; /*!< [16..16] Adjust receive sampling timing enable */ + __IOM uint32_t ATEN : 1; /*!< [17..17] Adjust transmit timing enable */ + uint32_t : 1; + __IOM uint32_t SCKSEL : 1; /*!< [19..19] Master receive clock selection bit. */ + uint32_t : 4; + __IOM uint32_t AST : 3; /*!< [26..24] Adjustment value for receive Sampling Timing */ + __IOM uint32_t AJD : 1; /*!< [27..27] Adjustment Direction for receive sampling timing */ + __IOM uint32_t ATT : 3; /*!< [30..28] Adjustment value for Transmit timing */ + __IOM uint32_t AET : 1; /*!< [31..31] Adjustment edge for transmit timing */ + } CCR4_b; + }; + + union + { + __IM uint8_t CESR; /*!< (@ 0x0000001C) Communication Enable Status Register */ + + struct + { + __IM uint8_t RIST : 1; /*!< [0..0] RE Internal status */ + uint8_t : 3; + __IM uint8_t TIST : 1; /*!< [4..4] TE Internal status */ + uint8_t : 3; + } CESR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t ICR; /*!< (@ 0x00000020) Simple I2C Control Register */ + + struct + { + __IOM uint32_t IICDL : 5; /*!< [4..0] SDA Delay Output Select */ + uint32_t : 3; + __IOM uint32_t IICINTM : 1; /*!< [8..8] IIC Interrupt Mode Select */ + __IOM uint32_t IICCSC : 1; /*!< [9..9] Clock Synchronization */ + uint32_t : 3; + __IOM uint32_t IICACKT : 1; /*!< [13..13] ACK Transmission Data */ + uint32_t : 2; + __IOM uint32_t IICSTAREQ : 1; /*!< [16..16] Start Condition Generation */ + __IOM uint32_t IICRSTAREQ : 1; /*!< [17..17] Restart Condition Generation */ + __IOM uint32_t IICSTPREQ : 1; /*!< [18..18] Stop Condition Generation */ + uint32_t : 1; + __IOM uint32_t IICSDAS : 2; /*!< [21..20] SDA Output Select */ + __IOM uint32_t IICSCLS : 2; /*!< [23..22] SCL Output Select */ + uint32_t : 8; + } ICR_b; + }; + + union + { + __IOM uint32_t FCR; /*!< (@ 0x00000024) FIFO Control Register */ + + struct + { + __IOM uint32_t DRES : 1; /*!< [0..0] Receive data ready error select bit */ + uint32_t : 7; + __IOM uint32_t TTRG : 5; /*!< [12..8] Transmit FIFO data trigger number */ + uint32_t : 2; + __OM uint32_t TFRST : 1; /*!< [15..15] Transmit FIFO Data Register Reset */ + __IOM uint32_t RTRG : 5; /*!< [20..16] Receive FIFO data trigger number */ + uint32_t : 2; + __OM uint32_t RFRST : 1; /*!< [23..23] Receive FIFO Data Register Reset */ + __IOM uint32_t RSTRG : 5; /*!< [28..24] RTS Output Active Trigger Number Select */ + uint32_t : 3; + } FCR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t MCR; /*!< (@ 0x0000002C) Manchester Control Register */ + + struct + { + __IOM uint32_t RMPOL : 1; /*!< [0..0] Polarity of Received Manchester Code */ + __IOM uint32_t TMPOL : 1; /*!< [1..1] Polarity of Transmit Manchester Code */ + __IOM uint32_t ERTEN : 1; /*!< [2..2] Manchester Edge Retiming Enable */ + uint32_t : 1; + __IOM uint32_t SYNVAL : 1; /*!< [4..4] SYNC value Setting */ + __IOM uint32_t SYNSEL : 1; /*!< [5..5] SYNC Select */ + __IOM uint32_t SBSEL : 1; /*!< [6..6] Start Bit Select */ + uint32_t : 1; + __IOM uint32_t TPLEN : 4; /*!< [11..8] Transmit preface length */ + __IOM uint32_t TPPAT : 2; /*!< [13..12] Transmit preface pattern */ + uint32_t : 2; + __IOM uint32_t RPLEN : 4; /*!< [19..16] Receive Preface Length */ + __IOM uint32_t RPPAT : 2; /*!< [21..20] Receive Preface Pattern */ + uint32_t : 2; + __IOM uint32_t PFEREN : 1; /*!< [24..24] Preface Error Enable */ + __IOM uint32_t SYEREN : 1; /*!< [25..25] Receive SYNC Error Enable */ + __IOM uint32_t SBEREN : 1; /*!< [26..26] Start Bit Error Enable */ + uint32_t : 5; + } MCR_b; + }; + + union + { + __IOM uint32_t DCR; /*!< (@ 0x00000030) Driver Control Register */ + + struct + { + __IOM uint32_t DEPOL : 1; /*!< [0..0] Driver effective polarity select */ + uint32_t : 7; + __IOM uint32_t DEAST : 5; /*!< [12..8] Driver Assertion Time */ + uint32_t : 3; + __IOM uint32_t DENGT : 5; /*!< [20..16] Driver negate time */ + uint32_t : 11; + } DCR_b; + }; + + union + { + __IOM uint32_t XCR0; /*!< (@ 0x00000034) Simple LIN(SCIX) Control Register 0 */ + + struct + { + __IOM uint32_t TCSS : 2; /*!< [1..0] Timer count clock source selection */ + uint32_t : 6; + __IOM uint32_t BFE : 1; /*!< [8..8] Break Field enable */ + __IOM uint32_t CF0RE : 1; /*!< [9..9] Control Field 0 enable */ + __IOM uint32_t CF1DS : 2; /*!< [11..10] Control Field1 compare data select */ + __IOM uint32_t PIBE : 1; /*!< [12..12] Priority interrupt bit enable */ + __IOM uint32_t PIBS : 3; /*!< [15..13] Priority interrupt bit select */ + __IOM uint32_t BFOIE : 1; /*!< [16..16] Break Field output completion interrupt enable */ + __IOM uint32_t BCDIE : 1; /*!< [17..17] Bus conflict detection interrupt enable */ + uint32_t : 2; + __IOM uint32_t BFDIE : 1; /*!< [20..20] Break Field detection interrupt enable */ + __IOM uint32_t COFIE : 1; /*!< [21..21] Counter overflow interrupt enable */ + __IOM uint32_t AEDIE : 1; /*!< [22..22] Active edge detection interrupt enable */ + uint32_t : 1; + __IOM uint32_t BCCS : 2; /*!< [25..24] Bus conflict detection clock selection */ + uint32_t : 6; + } XCR0_b; + }; + + union + { + __IOM uint32_t XCR1; /*!< (@ 0x00000038) Simple LIN(SCIX) Control Register 1 */ + + struct + { + __IOM uint32_t TCST : 1; /*!< [0..0] Break Field output timer count start trigger */ + uint32_t : 3; + __IOM uint32_t SDST : 1; /*!< [4..4] Start Frame detection enable */ + __IOM uint32_t BMEN : 1; /*!< [5..5] Bit rate measurement enable */ + uint32_t : 2; + __IOM uint32_t PCF1D : 8; /*!< [15..8] Priority compare data for Control Field 1 */ + __IOM uint32_t SCF1D : 8; /*!< [23..16] Secondary compare data for Control Field 1 */ + __IOM uint32_t CF1CE : 8; /*!< [31..24] Control Field 1 compare bit enable */ + } XCR1_b; + }; + + union + { + __IOM uint32_t XCR2; /*!< (@ 0x0000003C) Simple LIN(SCIX) Control Register 2 */ + + struct + { + __IOM uint32_t CF0D : 8; /*!< [7..0] Control Field 0compare data */ + __IOM uint32_t CF0CE : 8; /*!< [15..8] Control Field 0 compare bit enable */ + __IOM uint32_t BFLW : 16; /*!< [31..16] Break Field length setting */ + } XCR2_b; + }; + __IM uint32_t RESERVED3[2]; + + union + { + __IM uint32_t CSR; /*!< (@ 0x00000048) Common Status Register */ + + struct + { + uint32_t : 4; + __IM uint32_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + uint32_t : 10; + __IM uint32_t RXDMON : 1; /*!< [15..15] Serial input data monitor bit */ + __IM uint32_t DCMF : 1; /*!< [16..16] Data Compare Match Flag */ + __IM uint32_t DPER : 1; /*!< [17..17] Data Compare Match Parity Error Flag */ + __IM uint32_t DFER : 1; /*!< [18..18] Data Compare Match Framing Error Flag */ + uint32_t : 5; + __IM uint32_t ORER : 1; /*!< [24..24] Overrun Error Flag */ + uint32_t : 1; + __IM uint32_t MFF : 1; /*!< [26..26] Mode Fault Flag */ + __IM uint32_t PER : 1; /*!< [27..27] Parity Error Flag */ + __IM uint32_t FER : 1; /*!< [28..28] Framing Error Flag */ + __IM uint32_t TDRE : 1; /*!< [29..29] Transmit Data Empty Flag */ + __IM uint32_t TEND : 1; /*!< [30..30] Transmit End Flag */ + __IM uint32_t RDRF : 1; /*!< [31..31] Receive Data Full Flag */ + } CSR_b; + }; + + union + { + __IM uint32_t ISR; /*!< (@ 0x0000004C) Simple I2C Status Register */ + + struct + { + __IM uint32_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint32_t : 2; + __IM uint32_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag */ + uint32_t : 28; + } ISR_b; + }; + + union + { + __IM uint32_t FRSR; /*!< (@ 0x00000050) FIFO Receive Status Register */ + + struct + { + __IM uint32_t DR : 1; /*!< [0..0] Receive Data Ready flag */ + uint32_t : 7; + __IM uint32_t R : 6; /*!< [13..8] Receive-FIFO Data Count */ + uint32_t : 2; + __IM uint32_t PNUM : 6; /*!< [21..16] Parity Error Count */ + uint32_t : 2; + __IM uint32_t FNUM : 6; /*!< [29..24] Framing Error Count */ + uint32_t : 2; + } FRSR_b; + }; + + union + { + __IM uint32_t FTSR; /*!< (@ 0x00000054) FIFO Transmit Status Register */ + + struct + { + __IM uint32_t T : 6; /*!< [5..0] Transmit-FIFO Data Count */ + uint32_t : 26; + } FTSR_b; + }; + + union + { + __IM uint32_t MSR; /*!< (@ 0x00000058) Manchester Status Register */ + + struct + { + __IM uint32_t PFER : 1; /*!< [0..0] Preface Error flag */ + __IM uint32_t SYER : 1; /*!< [1..1] SYNC Error flag */ + __IM uint32_t SBER : 1; /*!< [2..2] Start Bit Error flag */ + uint32_t : 1; + __IM uint32_t MER : 1; /*!< [4..4] Manchester Error Flag */ + uint32_t : 1; + __IM uint32_t RSYNC : 1; /*!< [6..6] Receive SYNC data bit */ + uint32_t : 25; + } MSR_b; + }; + + union + { + __IM uint32_t XSR0; /*!< (@ 0x0000005C) Simple LIN (SCIX) Status Register 0 */ + + struct + { + __IM uint32_t SFSF : 1; /*!< [0..0] Start Frame Status flag */ + __IM uint32_t RXDSF : 1; /*!< [1..1] RXDn input status flag */ + uint32_t : 6; + __IM uint32_t BFOF : 1; /*!< [8..8] Break Field Output completion flag */ + __IM uint32_t BCDF : 1; /*!< [9..9] Bus Conflict detection flag */ + __IM uint32_t BFDF : 1; /*!< [10..10] Break Field detection flag */ + __IM uint32_t CF0MF : 1; /*!< [11..11] Control Field 0 compare match flag */ + __IM uint32_t CF1MF : 1; /*!< [12..12] Control Field 1 compare match flag */ + __IM uint32_t PIBDF : 1; /*!< [13..13] Priority interrupt bit detection flag */ + __IM uint32_t COF : 1; /*!< [14..14] Counter Overflow flag */ + __IM uint32_t AEDF : 1; /*!< [15..15] Active Edge detection flag */ + __IM uint32_t CF0RD : 8; /*!< [23..16] Control Field 0 received data */ + __IM uint32_t CF1RD : 8; /*!< [31..24] Control Field 1 received data */ + } XSR0_b; + }; + + union + { + __IM uint32_t XSR1; /*!< (@ 0x00000060) Simple LIN(SCIX) Status Register 1 */ + + struct + { + __IM uint32_t TCNT : 16; /*!< [15..0] Timer Count Capture value */ + uint32_t : 16; + } XSR1_b; + }; + __IM uint32_t RESERVED4; + + union + { + __OM uint32_t CFCLR; /*!< (@ 0x00000068) Common Flag Clear Register */ + + struct + { + uint32_t : 4; + __OM uint32_t ERSC : 1; /*!< [4..4] ERS clear bit */ + uint32_t : 11; + __OM uint32_t DCMFC : 1; /*!< [16..16] DCMF clear bit */ + __OM uint32_t DPERC : 1; /*!< [17..17] DPER clear bit */ + __OM uint32_t DFERC : 1; /*!< [18..18] DFER clear bit */ + uint32_t : 5; + __OM uint32_t ORERC : 1; /*!< [24..24] ORER clear bit */ + uint32_t : 1; + __OM uint32_t MFFC : 1; /*!< [26..26] MFF clear bit */ + __OM uint32_t PERC : 1; /*!< [27..27] PER clear bit */ + __OM uint32_t FERC : 1; /*!< [28..28] FER clear bit */ + __OM uint32_t TDREC : 1; /*!< [29..29] TDRE clear bit */ + uint32_t : 1; + __OM uint32_t RDRFC : 1; /*!< [31..31] RDRF clear bit */ + } CFCLR_b; + }; + + union + { + __OM uint32_t ICFCLR; /*!< (@ 0x0000006C) Simple I2C Flag Clear Register */ + + struct + { + uint32_t : 3; + __OM uint32_t IICSTIFC : 1; /*!< [3..3] IICSTIF clear bit */ + uint32_t : 28; + } ICFCLR_b; + }; + + union + { + __OM uint32_t FFCLR; /*!< (@ 0x00000070) FIFO Flag Clear Register */ + + struct + { + __OM uint32_t DRC : 1; /*!< [0..0] DR clear bit */ + uint32_t : 31; + } FFCLR_b; + }; + + union + { + __OM uint32_t MFCLR; /*!< (@ 0x00000074) Manchester Flag Clear Register */ + + struct + { + __OM uint32_t PFERC : 1; /*!< [0..0] PFER clear bit */ + __OM uint32_t SYERC : 1; /*!< [1..1] SYER clear bit */ + __OM uint32_t SBERC : 1; /*!< [2..2] SBER clear bit */ + uint32_t : 1; + __OM uint32_t MERC : 1; /*!< [4..4] MER clear bit */ + uint32_t : 27; + } MFCLR_b; + }; + + union + { + __OM uint32_t XFCLR; /*!< (@ 0x00000078) Simple LIN(SCIX) Flag Clear Register */ + + struct + { + uint32_t : 8; + __OM uint32_t BFOC : 1; /*!< [8..8] BFOF clear bit */ + __OM uint32_t BCDC : 1; /*!< [9..9] BCDF clear bit */ + __OM uint32_t BFDC : 1; /*!< [10..10] BFDF clear bit */ + __OM uint32_t CF0MC : 1; /*!< [11..11] CF0MF clear bit */ + __OM uint32_t CF1MC : 1; /*!< [12..12] CF1MF clear bit */ + __OM uint32_t PIBDC : 1; /*!< [13..13] PIBDF clear bit */ + __OM uint32_t COFC : 1; /*!< [14..14] COFF clear bit */ + __OM uint32_t AEDC : 1; /*!< [15..15] AEDF clear bit */ + uint32_t : 16; + } XFCLR_b; + }; +} R_SCI_B0_Type; /*!< Size = 124 (0x7c) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI_B0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface 0 (R_SPI_B0) + */ + +typedef struct /*!< (@ 0x4035C000) R_SPI_B0 Structure */ +{ + __IOM uint32_t SPDR; /*!< (@ 0x00000000) RSPI Data Register */ + + union + { + __IOM uint32_t SPDECR; /*!< (@ 0x00000004) RSPI Delay Control Register */ + + struct + { + __IOM uint32_t SCKDL : 3; /*!< [2..0] RSPCK Delay */ + uint32_t : 5; + __IOM uint32_t SLNDL : 3; /*!< [10..8] SSL Negation Delay */ + uint32_t : 5; + __IOM uint32_t SPNDL : 3; /*!< [18..16] RSPI Next-Access Delay */ + uint32_t : 5; + __IOM uint32_t ARST : 3; /*!< [26..24] Receive Sampling Timing Adjustment bits */ + uint32_t : 5; + } SPDECR_b; + }; + + union + { + __IOM uint32_t SPCR; /*!< (@ 0x00000008) RSPI Control Register */ + + struct + { + __IOM uint32_t SPE : 1; /*!< [0..0] RSPI Function Enable */ + uint32_t : 6; + __IOM uint32_t SPSCKSEL : 1; /*!< [7..7] RSPI Master Receive Clock Select */ + __IOM uint32_t SPPE : 1; /*!< [8..8] Parity Enable */ + __IOM uint32_t SPOE : 1; /*!< [9..9] Parity Mode */ + uint32_t : 1; + __IOM uint32_t PTE : 1; /*!< [11..11] Parity Self-Diagnosis Enable */ + __IOM uint32_t SCKASE : 1; /*!< [12..12] RSPCK Auto-Stop Function Enable */ + __IOM uint32_t BFDS : 1; /*!< [13..13] Between Burst Transfer Frames Delay Select */ + __IOM uint32_t MODFEN : 1; /*!< [14..14] Mode Fault Error Detection Enable */ + uint32_t : 1; + __IOM uint32_t SPEIE : 1; /*!< [16..16] RSPI Error Interrupt Enable */ + __IOM uint32_t SPRIE : 1; /*!< [17..17] RSPI Receive Buffer Full Interrupt Enable */ + __IOM uint32_t SPIIE : 1; /*!< [18..18] RSPI Idle Interrupt Enable */ + __IOM uint32_t SPDRES : 1; /*!< [19..19] RSPI receive data ready error select */ + __IOM uint32_t SPTIE : 1; /*!< [20..20] RSPI Transmit Buffer Empty Interrupt Enable */ + __IOM uint32_t CENDIE : 1; /*!< [21..21] RSPI Communication End Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SPMS : 1; /*!< [24..24] RSPI Mode Select */ + __IOM uint32_t SPFRF : 1; /*!< [25..25] RSPI Frame Format Select */ + uint32_t : 2; + __IOM uint32_t TXMD : 2; /*!< [29..28] Communication Mode Select */ + __IOM uint32_t MSTR : 1; /*!< [30..30] RSPI Master/Slave Mode Select */ + __IOM uint32_t BPEN : 1; /*!< [31..31] Synchronization Circuit Bypass Enable */ + } SPCR_b; + }; + + union + { + __IOM uint32_t SPCR2; /*!< (@ 0x0000000C) RSPI Control Register 2 */ + + struct + { + __IOM uint32_t RMFM : 5; /*!< [4..0] Frame processing count setting in Master Receive only */ + uint32_t : 1; + __OM uint32_t RMEDTG : 1; /*!< [6..6] End Trigger in Master Receive only */ + __OM uint32_t RMSTTG : 1; /*!< [7..7] Start Trigger in Master Receive only */ + __IOM uint32_t SPDRC : 8; /*!< [15..8] RSPI received data ready detect adjustment */ + __IOM uint32_t SPLP : 1; /*!< [16..16] RSPI Loopback */ + __IOM uint32_t SPLP2 : 1; /*!< [17..17] RSPI Loopback 2 */ + uint32_t : 2; + __IOM uint32_t MOIFV : 1; /*!< [20..20] MOSI Idle Fixed Value */ + __IOM uint32_t MOIFE : 1; /*!< [21..21] MOSI Idle Fixed Value Enable */ + uint32_t : 10; + } SPCR2_b; + }; + + union + { + __IOM uint32_t SPCR3; /*!< (@ 0x00000010) RSPI Control Register 3 */ + + struct + { + __IOM uint32_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity */ + __IOM uint32_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity */ + __IOM uint32_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity */ + __IOM uint32_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity */ + uint32_t : 4; + __IOM uint32_t SPBR : 8; /*!< [15..8] SPI Bit Rate */ + uint32_t : 8; + __IOM uint32_t SPSLN : 3; /*!< [26..24] RSPI Sequence Length */ + uint32_t : 5; + } SPCR3_b; + }; + + union + { + __IOM uint32_t SPCMD0; /*!< (@ 0x00000014) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD0_b; + }; + + union + { + __IOM uint32_t SPCMD1; /*!< (@ 0x00000018) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD1_b; + }; + + union + { + __IOM uint32_t SPCMD2; /*!< (@ 0x0000001C) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD2_b; + }; + + union + { + __IOM uint32_t SPCMD3; /*!< (@ 0x00000020) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD3_b; + }; + + union + { + __IOM uint32_t SPCMD4; /*!< (@ 0x00000024) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD4_b; + }; + + union + { + __IOM uint32_t SPCMD5; /*!< (@ 0x00000028) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD5_b; + }; + + union + { + __IOM uint32_t SPCMD6; /*!< (@ 0x0000002C) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD6_b; + }; + + union + { + __IOM uint32_t SPCMD7; /*!< (@ 0x00000030) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD7_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t SPDCR; /*!< (@ 0x00000040) RSPI Data Control Register */ + + struct + { + __IOM uint32_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + uint32_t : 2; + __IOM uint32_t SPRDTD : 1; /*!< [3..3] RSPI Receive Data or Transmit Data Select */ + __IOM uint32_t SINV : 1; /*!< [4..4] Serial data invert bit */ + uint32_t : 3; + __IOM uint32_t SPFC : 2; /*!< [9..8] Frame Count */ + uint32_t : 22; + } SPDCR_b; + }; + + union + { + __IOM uint32_t SPDCR2; /*!< (@ 0x00000044) RSPI Data Control Register 2 */ + + struct + { + __IOM uint32_t RTRG : 2; /*!< [1..0] Receive FIFO threshold setting */ + uint32_t : 6; + __IOM uint32_t TTRG : 2; /*!< [9..8] Transmission FIFO threshold setting */ + uint32_t : 22; + } SPDCR2_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IM uint32_t SPSR; /*!< (@ 0x00000050) SPI Status Register */ + + struct + { + uint32_t : 8; + __IM uint32_t SPCP : 3; /*!< [10..8] RSPI Command Pointer */ + uint32_t : 1; + __IM uint32_t SPECM : 3; /*!< [14..12] RSPI Error Command */ + uint32_t : 8; + __IM uint32_t SPDRF : 1; /*!< [23..23] RSPI Receive Data Ready Flag */ + __IM uint32_t OVRF : 1; /*!< [24..24] Overrun Error Flag */ + __IM uint32_t IDLNF : 1; /*!< [25..25] RSPI Idle Flag */ + __IM uint32_t MODF : 1; /*!< [26..26] Mode Fault Error Flag */ + __IM uint32_t PERF : 1; /*!< [27..27] Parity Error Flag */ + __IM uint32_t UDRF : 1; /*!< [28..28] Underrun Error Flag */ + __IM uint32_t SPTEF : 1; /*!< [29..29] RSPI Transmit Buffer Empty Flag */ + __IM uint32_t CENDF : 1; /*!< [30..30] Communication End Flag */ + __IM uint32_t SPRF : 1; /*!< [31..31] RSPI Receive Buffer Full Flag */ + } SPSR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IM uint32_t SPTFSR; /*!< (@ 0x00000058) RSPI Transfer FIFO Status Register */ + + struct + { + __IM uint32_t TFDN : 3; /*!< [2..0] Transmit FIFO data empty stage number */ + uint32_t : 29; + } SPTFSR_b; + }; + + union + { + __IM uint32_t SPRFSR; /*!< (@ 0x0000005C) RSPI Receive FIFO Status Register */ + + struct + { + __IM uint32_t RFDN : 3; /*!< [2..0] Receive FIFO data store stage number */ + uint32_t : 29; + } SPRFSR_b; + }; + + union + { + __IM uint32_t SPPSR; /*!< (@ 0x00000060) RSPI Poling Register */ + + struct + { + __IM uint32_t SPEPS : 1; /*!< [0..0] RSPI Poling Status */ + uint32_t : 31; + } SPPSR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t SPSRC; /*!< (@ 0x00000068) RSPI Status Clear Register */ + + struct + { + uint32_t : 23; + __OM uint32_t SPDRFC : 1; /*!< [23..23] RSPI Receive Data Ready Flag Clear */ + __OM uint32_t OVRFC : 1; /*!< [24..24] Overrun Error Flag Clear */ + uint32_t : 1; + __OM uint32_t MODFC : 1; /*!< [26..26] Mode Fault Error Flag Clear */ + __OM uint32_t PERFC : 1; /*!< [27..27] Parity Error Flag Clear */ + __OM uint32_t UDRFC : 1; /*!< [28..28] Underrun Error Flag Clear */ + __OM uint32_t SPTEFC : 1; /*!< [29..29] RSPI Transmit Buffer Empty Flag Clear */ + __OM uint32_t CENDFC : 1; /*!< [30..30] Communication End Flag Clear */ + __OM uint32_t SPRFC : 1; /*!< [31..31] RSPI Receive Buffer Full Flag Clear */ + } SPSRC_b; + }; + + union + { + __IOM uint32_t SPFCR; /*!< (@ 0x0000006C) RSPI FIFO Clear Register */ + + struct + { + __OM uint32_t SPFRST : 1; /*!< [0..0] RSPI FIFO clear */ + uint32_t : 31; + } SPFCR_b; + }; +} R_SPI_B0_Type; /*!< Size = 112 (0x70) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_HS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 High-Speed Module (R_USB_HS0) + */ + +typedef struct /*!< (@ 0x40351000) R_USB_HS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 3; + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + __IOM uint16_t HSE : 1; /*!< [7..7] High-Speed Operation Enable */ + __IOM uint16_t CNEN : 1; /*!< [8..8] Single End Receiver Enable */ + uint16_t : 7; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] ID0 Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB1_OVRCURA/USB1_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Operation Enable for the Host Controller Operation */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Signal Output for the Host Controller Operation */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output for the Host Controller Operation */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Remote Wakeup Detection Enable for the Host Controller + * Operation */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Remote Wakeup Output for the Device Controller Operation */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USBHS_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USBHS_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control Use this bit + * when switching from device B to device A in OTGmode. If + * the HNPBTOA bit is 1, the internal function controlremains + * in the Suspend state until the HNP processing endseven + * if SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port.Read receive data from the FIFO buffer or + * write transmit data to the FIFO buffer by accessing these + * bits. */ + } CFIFO_b; + }; + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port Read receive data from the FIFO buffer or + * write transmit data to the FIFO buffer by accessing these + * bits. */ + } D0FIFO_b; + }; + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO PortRead receive data from the FIFO buffer or write + * transmit data to the FIFO buffer by accessing these bits. */ + } D1FIFO_b; + }; + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] FIFO Port Access Direction when DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t LPMENDE : 1; /*!< [8..8] LPM Transaction End Interrupt Enable */ + __IOM uint16_t L1RSMENDE : 1; /*!< [9..9] L1 Resume End Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] OVRCRE Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPEBRDYE : 10; /*!< [9..0] BRDY Interrupt Enable for Each Pipe */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPENRDYE : 10; /*!< [9..0] NRDY Interrupt Enable for Each Pipe */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPEBEMPE : 10; /*!< [9..0] BEMP Interrupt Enable for Each Pipe */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Pin Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Interrupt Edge Processing Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] PIPEBRDY Interrupt Status Clear Timing.This bit can be + * set only in the initial setting (before communications).The + * setting cannot be changed once communication starts. */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select.The transfer efficiency + * can be improved by setting this bit to 1 if no low-speed + * device is connected directly or via FS-HUB to the USB port. */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] USB Connection Detection Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPEBRDY : 10; /*!< [9..0] BRDY Interrupt Status for Each Pipe */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPENRDY : 10; /*!< [9..0] NRDY Interrupt Status for Each Pipe */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPEBEMP : 10; /*!< [9..0] BEMP Interrupt Status for Each Pipe */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame Number.Indicate the latest frame number. */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] CRC Error Detection Status */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + + struct + { + __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } UFRMNUM_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ + uint16_t : 5; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] USB request bmRequestType value Finction controller selected + * : read-only Host controller selected : read-write */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] USB request bRequest value Finction controller selected + * : read-only Host controller selected : read-write */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] Value of USB request wValue Finction controller selected + * : read-only Host controller selected : read-write */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] Value of USB request wIndex Finction controller selected + * : read-only Host controller selected : read-write */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] Value of USB request wLength Finction controller selected + * : read-only Host controller selected : read-write */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Blocking on End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits specify the maximum data + * payload (maximum packet size) for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the + * destination function device for control transfer when the + * host controller function is selected. */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 1; + __IOM uint16_t PINGE : 1; /*!< [4..4] PING Token Issue Enable */ + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + __IM uint16_t CSSTS : 1; /*!< [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] Split Transaction CSPLIT Status Clear */ + __IOM uint16_t SUREQ : 1; /*!< [14..14] SETUP Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint Number */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + + union + { + __IOM uint16_t PIPEBUF; /*!< (@ 0x0000006A) Pipe Buffer Register */ + + struct + { + __IOM uint16_t BUFNMB : 8; /*!< [7..0] Buffer NumberThese bits specify the FIFO buffer number + * of the selected pipe (04h to 87h). */ + uint16_t : 2; + __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes */ + uint16_t : 1; + } PIPEBUF_b; + }; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 11; /*!< [10..0] Maximum Packet SizeThese bits specify the maximum data + * payload (maximum packet size) for the selected pipe.A size + * of 1h to 40h bytes can be set for PIPE6 to PIPE9. */ + uint16_t : 1; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the + * peripheral device when the host controller function is + * selected. */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalThese bits specify the + * transfer interval timing for the selected pipe as n-th + * power of 2 of the frame timing. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) PIPE Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PIDThese bits specify the response type for + * the next transaction of the relevant pipe. */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe BusyThis bit indicates whether the relevant pipe + * is being used for the USB bus */ + __IM uint16_t SQMON : 1; /*!< [6..6] Toggle Bit ConfirmationThis bit indicates the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit SetThis bit is set to 1 when the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe is set for DATA1 */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit ClearThis bit is set to 1 when the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe is cleared to DATA0 */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear ModeThis bit enables or disables auto + * buffer clear mode for the relevant pipe */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response ModeThis bit enables or disables auto + * response mode for the relevant pipe. */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer MonitorThis bit indicates the FIFO + * buffer status for the relevant pipe in the transmitting + * direction. */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer StatusThis bit indicates the FIFO buffer status + * for the relevant pipe. */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[3]; + __IOM R_USB_HS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED14[11]; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED15[7]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED16[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED17; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED18; + + union + { + __IOM uint16_t PHYTRIM1; /*!< (@ 0x00000150) PHY Timing Register 1 */ + + struct + { + __IOM uint16_t DRISE : 2; /*!< [1..0] FS/LS Rising-Edge Output Waveform Adjustment Function */ + __IOM uint16_t DFALL : 2; /*!< [3..2] FS/LS Falling-Edge Output Waveform Adjustment Function */ + uint16_t : 3; + __IOM uint16_t PCOMPENB : 1; /*!< [7..7] PVDD Start-up Detection */ + __IOM uint16_t HSIUP : 4; /*!< [11..8] HS Output Level Setting */ + __IOM uint16_t IMPOFFSET : 3; /*!< [14..12] terminating resistance offset value setting.Offset + * value for adjusting the terminating resistance. */ + uint16_t : 1; + } PHYTRIM1_b; + }; + + union + { + __IOM uint16_t PHYTRIM2; /*!< (@ 0x00000152) PHY Timing Register 2 */ + + struct + { + __IOM uint16_t SQU : 4; /*!< [3..0] Squelch Detection Level */ + uint16_t : 3; + __IOM uint16_t HSRXENMO : 1; /*!< [7..7] HS Receive Enable Control Mode */ + __IOM uint16_t PDR : 2; /*!< [9..8] HS Output Adjustment Function */ + uint16_t : 2; + __IOM uint16_t DIS : 3; /*!< [14..12] Disconnect Detection Level */ + uint16_t : 1; + } PHYTRIM2_b; + }; + __IM uint32_t RESERVED19[3]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; +} R_USB_HS0_Type; /*!< Size = 364 (0x16c) */ + +/* =========================================================================================================================== */ +/* ================ R_XSPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief eXpanded SPI (R_XSPI0) + */ + +typedef struct /*!< (@ 0x40268000) R_XSPI0 Structure */ +{ + union + { + __IOM uint32_t WRAPCFG; /*!< (@ 0x00000000) xSPI Wrapper Configuration register */ + + struct + { + __IOM uint32_t CKSFTCS0 : 5; /*!< [4..0] CK shift for slave0 */ + uint32_t : 3; + __IOM uint32_t DSSFTCS0 : 5; /*!< [12..8] DS shift for slave0 */ + uint32_t : 3; + __IOM uint32_t CKSFTCS1 : 5; /*!< [20..16] CK shift for slave1 */ + uint32_t : 3; + __IOM uint32_t DSSFTCS1 : 5; /*!< [28..24] DS shift for slave1 */ + uint32_t : 3; + } WRAPCFG_b; + }; + + union + { + __IOM uint32_t COMCFG; /*!< (@ 0x00000004) xSPI Common Configuration register */ + + struct + { + __IOM uint32_t ARBMD : 2; /*!< [1..0] Channel arbitration mode */ + uint32_t : 2; + __IOM uint32_t ECSINTOUTEN : 2; /*!< [5..4] ECS/INT Output Enable */ + uint32_t : 10; + __IOM uint32_t OEASTEX : 1; /*!< [16..16] Output Enable Asserting extension */ + __IOM uint32_t OENEGEX : 1; /*!< [17..17] Output Enable Negating extension */ + uint32_t : 14; + } COMCFG_b; + }; + + union + { + __IOM uint32_t BMCFGCH[2]; /*!< (@ 0x00000008) xSPI Bridge Map Configuration register */ + + struct + { + __IOM uint32_t WRMD : 1; /*!< [0..0] AHB Write Response mode */ + uint32_t : 6; + __IOM uint32_t MWRCOMB : 1; /*!< [7..7] Memory Write Combination mode */ + __IOM uint32_t MWRSIZE : 8; /*!< [15..8] Memory Write Size */ + __IOM uint32_t PREEN : 1; /*!< [16..16] Prefetch enable */ + uint32_t : 7; + __IOM uint32_t CMBTIM : 8; /*!< [31..24] Combination timer */ + } BMCFGCH_b[2]; + }; + __IOM R_XSPI0_CMCFGCS_Type CMCFGCS[2]; /*!< (@ 0x00000010) xSPI Command Map Configuration registers */ + __IM uint32_t RESERVED[8]; + + union + { + __IOM uint32_t LIOCFGCS[2]; /*!< (@ 0x00000050) xSPI Link I/O Configuration register CS[0..1] */ + + struct + { + __IOM uint32_t PRTMD : 10; /*!< [9..0] Protocol mode */ + __IOM uint32_t LATEMD : 1; /*!< [10..10] Latency mode */ + __IOM uint32_t WRMSKMD : 1; /*!< [11..11] Write mask mode */ + uint32_t : 4; + __IOM uint32_t CSMIN : 4; /*!< [19..16] CS minimum idle term */ + __IOM uint32_t CSASTEX : 1; /*!< [20..20] CS asserting extension */ + __IOM uint32_t CSNEGEX : 1; /*!< [21..21] CS negating extension */ + __IOM uint32_t SDRDRV : 1; /*!< [22..22] SDR driving timing */ + __IOM uint32_t SDRSMPMD : 1; /*!< [23..23] SDR Sampling mode */ + __IOM uint32_t SDRSMPSFT : 4; /*!< [27..24] SDR Sampling window shift */ + __IOM uint32_t DDRSMPEX : 4; /*!< [31..28] DDR sampling window extend */ + } LIOCFGCS_b[2]; + }; + + union + { + __IOM uint32_t ABMCFG; /*!< (@ 0x00000058) xSPI AXI Bridge Map Config */ + + struct + { + __IOM uint32_t ODRMD : 2; /*!< [1..0] AXI Transfer Ordering Mode */ + uint32_t : 14; + __IOM uint32_t CHSEL : 16; /*!< [31..16] AXI ID to Bridge Channel Select */ + } ABMCFG_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t BMCTL0; /*!< (@ 0x00000060) xSPI Bridge Map Control register 0 */ + + struct + { + __IOM uint32_t CH0CS0ACC : 2; /*!< [1..0] System bus ch0 to slave0 memory area access enable */ + __IOM uint32_t CH0CS1ACC : 2; /*!< [3..2] System bus ch0 to slave1 memory area access enable */ + __IOM uint32_t CH1CS0ACC : 2; /*!< [5..4] System bus ch1 to slave0 memory area access enable */ + __IOM uint32_t CH1CS1ACC : 2; /*!< [7..6] System bus ch1 to slave1 memory area access enable */ + uint32_t : 24; + } BMCTL0_b; + }; + + union + { + __OM uint32_t BMCTL1; /*!< (@ 0x00000064) xSPI Bridge Map Control register 1 */ + + struct + { + uint32_t : 8; + __OM uint32_t MWRPUSHCH0 : 1; /*!< [8..8] Memory Write Data Push for ch0 */ + __OM uint32_t MWRPUSHCH1 : 1; /*!< [9..9] Memory Write Data Push for ch1 */ + __OM uint32_t PBUFCLRCH0 : 1; /*!< [10..10] Prefetch Buffer clear for ch0 */ + __OM uint32_t PBUFCLRCH1 : 1; /*!< [11..11] Prefetch Buffer clear for ch1 */ + uint32_t : 20; + } BMCTL1_b; + }; + + union + { + __IOM uint32_t CMCTLCH[2]; /*!< (@ 0x00000068) xSPI Command Map Control register */ + + struct + { + __IOM uint32_t XIPENCODE : 8; /*!< [7..0] XiP mode enter code */ + __IOM uint32_t XIPEXCODE : 8; /*!< [15..8] XiP mode exit code */ + __IOM uint32_t XIPEN : 1; /*!< [16..16] XiP mode enable */ + uint32_t : 15; + } CMCTLCH_b[2]; + }; + + union + { + __IOM uint32_t CDCTL0; /*!< (@ 0x00000070) xSPI Command Manual Control register 0 */ + + struct + { + __IOM uint32_t TRREQ : 1; /*!< [0..0] Transaction request */ + __IOM uint32_t PERMD : 1; /*!< [1..1] Periodic mode */ + uint32_t : 1; + __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */ + __IOM uint32_t TRNUM : 2; /*!< [5..4] Transaction number */ + uint32_t : 10; + __IOM uint32_t PERITV : 5; /*!< [20..16] Periodic transaction interval */ + uint32_t : 3; + __IOM uint32_t PERREP : 4; /*!< [27..24] Periodic transaction repeat */ + uint32_t : 4; + } CDCTL0_b; + }; + + union + { + __IOM uint32_t CDCTL1; /*!< (@ 0x00000074) xSPI Command Manual Control register 1 */ + + struct + { + __IOM uint32_t PEREXP : 32; /*!< [31..0] Periodic transaction expected value */ + } CDCTL1_b; + }; + + union + { + __IOM uint32_t CDCTL2; /*!< (@ 0x00000078) xSPI Command Manual Control register 2 */ + + struct + { + __IOM uint32_t PERMSK : 32; /*!< [31..0] Periodic transaction masked value */ + } CDCTL2_b; + }; + __IM uint32_t RESERVED2; + __IOM R_XSPI0_CDBUF_Type CDBUF[4]; /*!< (@ 0x00000080) xSPI BUF register */ + __IM uint32_t RESERVED3[16]; + + union + { + __IOM uint32_t LPCTL0; /*!< (@ 0x00000100) xSPI Link Pattern Control register 0 */ + + struct + { + __IOM uint32_t PATREQ : 1; /*!< [0..0] Pattern request */ + uint32_t : 2; + __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */ + __IOM uint32_t XDPIN : 2; /*!< [5..4] XiP Disable pattern pin */ + uint32_t : 10; + __IOM uint32_t XD1LEN : 5; /*!< [20..16] XiP Disable pattern 1st phase length */ + uint32_t : 2; + __IOM uint32_t XD1VAL : 1; /*!< [23..23] XiP Disable pattern 1st phase value */ + __IOM uint32_t XD2LEN : 5; /*!< [28..24] XiP Disable pattern 2nd phase length */ + uint32_t : 2; + __IOM uint32_t XD2VAL : 1; /*!< [31..31] XiP Disable pattern 2nd phase value */ + } LPCTL0_b; + }; + + union + { + __IOM uint32_t LPCTL1; /*!< (@ 0x00000104) xSPI Link Pattern Control register 1 */ + + struct + { + __IOM uint32_t PATREQ : 2; /*!< [1..0] Pattern request */ + uint32_t : 1; + __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */ + __IOM uint32_t RSTREP : 2; /*!< [5..4] Reset pattern repeat */ + uint32_t : 2; + __IOM uint32_t RSTWID : 3; /*!< [10..8] Reset pattern width */ + uint32_t : 1; + __IOM uint32_t RSTSU : 3; /*!< [14..12] Reset pattern data output setup time */ + uint32_t : 17; + } LPCTL1_b; + }; + + union + { + __IOM uint32_t LIOCTL; /*!< (@ 0x00000108) xSPI Link I/O Control register */ + + struct + { + __IOM uint32_t WPCS0 : 1; /*!< [0..0] WP drive for slave 0 */ + __IOM uint32_t WPCS1 : 1; /*!< [1..1] WP drive for slave 1 */ + uint32_t : 14; + __IOM uint32_t RSTCS0 : 1; /*!< [16..16] Reset drive for slave 0 */ + __IOM uint32_t RSTCS1 : 1; /*!< [17..17] Reset drive for slave 1 */ + uint32_t : 14; + } LIOCTL_b; + }; + __IM uint32_t RESERVED4[9]; + __IOM R_XSPI0_CCCTLCS_Type CCCTLCS[2]; /*!< (@ 0x00000130) xSPI CS register */ + __IM uint32_t RESERVED5[4]; + + union + { + __IM uint32_t VERSTT; /*!< (@ 0x00000180) xSPI Version register */ + + struct + { + __IM uint32_t VER : 32; /*!< [31..0] Version */ + } VERSTT_b; + }; + + union + { + __IM uint32_t COMSTT; /*!< (@ 0x00000184) xSPI Common Status register */ + + struct + { + __IM uint32_t MEMACCCH0 : 1; /*!< [0..0] Memory access ongoing from ch0 */ + __IM uint32_t MEMACCCH1 : 1; /*!< [1..1] Memory access ongoing from ch1 */ + uint32_t : 2; + __IM uint32_t PBUFNECH0 : 1; /*!< [4..4] Prefetch Buffer Not Empty for ch0 */ + __IM uint32_t PBUFNECH1 : 1; /*!< [5..5] Prefetch Buffer Not Empty for ch1 */ + __IM uint32_t WRBUFNECH0 : 1; /*!< [6..6] Write Buffer Not Empty for ch0 */ + __IM uint32_t WRBUFNECH1 : 1; /*!< [7..7] Write Buffer Not Empty for ch1 */ + uint32_t : 8; + __IM uint32_t ECSCS0 : 1; /*!< [16..16] ECS monitor for slave0 */ + __IM uint32_t INTCS0 : 1; /*!< [17..17] INT monitor for slave0 */ + __IM uint32_t RSTOCS0 : 1; /*!< [18..18] RSTO monitor for slave0 */ + uint32_t : 1; + __IM uint32_t ECSCS1 : 1; /*!< [20..20] ECS monitor for slave1 */ + __IM uint32_t INTCS1 : 1; /*!< [21..21] INT monitor for slave1 */ + __IM uint32_t RSTOCS1 : 1; /*!< [22..22] RSTO monitor for slave1 */ + uint32_t : 9; + } COMSTT_b; + }; + + union + { + __IM uint32_t CASTTCS[2]; /*!< (@ 0x00000188) xSPI Calibration Status register */ + + struct + { + __IM uint32_t CASUC : 32; /*!< [31..0] Calibration Success */ + } CASTTCS_b[2]; + }; + + union + { + __IM uint32_t INTS; /*!< (@ 0x00000190) xSPI Interrupt Status register */ + + struct + { + __IM uint32_t CMDCMP : 1; /*!< [0..0] Command Completed */ + __IM uint32_t PATCMP : 1; /*!< [1..1] Pattern Completed */ + __IM uint32_t INICMP : 1; /*!< [2..2] Initial Sequence Completed */ + __IM uint32_t PERTO : 1; /*!< [3..3] Periodic transaction timeout */ + __IM uint32_t DSTOCS0 : 1; /*!< [4..4] DS timeout for slave0 */ + __IM uint32_t DSTOCS1 : 1; /*!< [5..5] DS timeout for slave1 */ + uint32_t : 2; + __IM uint32_t ECSCS0 : 1; /*!< [8..8] ECC error detection for slave0 */ + __IM uint32_t ECSCS1 : 1; /*!< [9..9] ECC error detection for slave1 */ + uint32_t : 2; + __IM uint32_t INTCS0 : 1; /*!< [12..12] Interrupt detection for slave0 */ + __IM uint32_t INTCS1 : 1; /*!< [13..13] Interrupt detection for slave1 */ + uint32_t : 2; + __IM uint32_t BRGOFCH0 : 1; /*!< [16..16] Bridge Buffer overflow for CH0 */ + __IM uint32_t BRGOFCH1 : 1; /*!< [17..17] Bridge Buffer overflow for CH1 */ + __IM uint32_t BRGUFCH0 : 1; /*!< [18..18] Bridge Buffer underflow for CH0 */ + __IM uint32_t BRGUFCH1 : 1; /*!< [19..19] Bridge Buffer underflow for CH1 */ + __IM uint32_t BUSERRCH0 : 1; /*!< [20..20] AHB bus error for CH0 */ + __IM uint32_t BUSERRCH1 : 1; /*!< [21..21] AHB bus error for CH1 */ + uint32_t : 6; + __IM uint32_t CAFAILCS0 : 1; /*!< [28..28] Calibration failed for slave0 */ + __IM uint32_t CAFAILCS1 : 1; /*!< [29..29] Calibration failed for slave1 */ + __IM uint32_t CASUCCS0 : 1; /*!< [30..30] Calibration success for slave0 */ + __IM uint32_t CASUCCS1 : 1; /*!< [31..31] Calibration success for slave1 */ + } INTS_b; + }; + + union + { + __OM uint32_t INTC; /*!< (@ 0x00000194) xSPI Interrupt Clear register */ + + struct + { + __OM uint32_t CMDCMPC : 1; /*!< [0..0] Command Completed interrupt clear */ + __OM uint32_t PATCMPC : 1; /*!< [1..1] Pattern Completed interrupt clear */ + __OM uint32_t INICMPC : 1; /*!< [2..2] Initial Sequence Completed interrupt clear */ + __OM uint32_t PERTOC : 1; /*!< [3..3] Periodic transaction timeout interrupt clear */ + __OM uint32_t DSTOCS0C : 1; /*!< [4..4] DS timeout for slave0 interrupt clear */ + __OM uint32_t DSTOCS1C : 1; /*!< [5..5] DS timeout for slave1 interrupt clear */ + uint32_t : 2; + __OM uint32_t ECSCS0C : 1; /*!< [8..8] ECC error detection for slave0 interrupt clear */ + __OM uint32_t ECSCS1C : 1; /*!< [9..9] ECC error detection for slave1 interrupt clear */ + uint32_t : 2; + __OM uint32_t INTCS0C : 1; /*!< [12..12] Interrupt detection for slave0 interrupt clear */ + __OM uint32_t INTCS1C : 1; /*!< [13..13] Interrupt detection for slave1 interrupt clear */ + uint32_t : 2; + __OM uint32_t BRGOFCH0C : 1; /*!< [16..16] Bridge Buffer overflow for CH0 interrupt clear */ + __OM uint32_t BRGOFCH1C : 1; /*!< [17..17] Bridge Buffer overflow for CH1 interrupt clear */ + __OM uint32_t BRGUFCH0C : 1; /*!< [18..18] Bridge Buffer underflow for CH0 interrupt clear */ + __OM uint32_t BRGUFCH1C : 1; /*!< [19..19] Bridge Buffer underflow for CH1 interrupt clear */ + __OM uint32_t BUSERRCH0C : 1; /*!< [20..20] AHB bus error for CH0 interrupt clear */ + __OM uint32_t BUSERRCH1C : 1; /*!< [21..21] AHB bus error for CH1 interrupt clear */ + uint32_t : 6; + __OM uint32_t CAFAILCS0C : 1; /*!< [28..28] Calibration failed for slave0 interrupt clear */ + __OM uint32_t CAFAILCS1C : 1; /*!< [29..29] Calibration failed for slave1 interrupt clear */ + __OM uint32_t CASUCCS0C : 1; /*!< [30..30] Calibration success for slave0 interrupt clear */ + __OM uint32_t CASUCCS1C : 1; /*!< [31..31] Calibration success for slave1 interrupt clear */ + } INTC_b; + }; + + union + { + __IOM uint32_t INTE; /*!< (@ 0x00000198) xSPI Interrupt Enable register */ + + struct + { + __IOM uint32_t CMDCMPE : 1; /*!< [0..0] Command Completed interrupt enable */ + __IOM uint32_t PATCMPE : 1; /*!< [1..1] Pattern Completed interrupt enable */ + __IOM uint32_t INICMPE : 1; /*!< [2..2] Initial Sequence Completed interrupt enable */ + __IOM uint32_t PERTOE : 1; /*!< [3..3] Periodic transaction timeout interrupt enable */ + __IOM uint32_t DSTOCS0E : 1; /*!< [4..4] DS timeout for slave0 interrupt enable */ + __IOM uint32_t DSTOCS1E : 1; /*!< [5..5] DS timeout for slave1 interrupt enable */ + uint32_t : 2; + __IOM uint32_t ECSCS0E : 1; /*!< [8..8] ECC error detection for slave0 interrupt enable */ + __IOM uint32_t ECSCS1E : 1; /*!< [9..9] ECC error detection for slave1 interrupt enable */ + uint32_t : 2; + __IOM uint32_t INTCS0E : 1; /*!< [12..12] Interrupt detection for slave0 interrupt enable */ + __IOM uint32_t INTCS1E : 1; /*!< [13..13] Interrupt detection for slave1 interrupt enable */ + uint32_t : 2; + __IOM uint32_t BRGOFCH0E : 1; /*!< [16..16] Bridge Buffer overflow for CH0 interrupt enable */ + __IOM uint32_t BRGOFCH1E : 1; /*!< [17..17] Bridge Buffer overflow for CH1 interrupt enable */ + __IOM uint32_t BRGUFCH0E : 1; /*!< [18..18] Bridge Buffer underflow for CH0 interrupt enable */ + __IOM uint32_t BRGUFCH1E : 1; /*!< [19..19] Bridge Buffer underflow for CH1 interrupt enable */ + __IOM uint32_t BUSERRCH0E : 1; /*!< [20..20] AHB bus error for CH0 interrupt enable */ + __IOM uint32_t BUSERRCH1E : 1; /*!< [21..21] AHB bus error for CH1 interrupt enable */ + uint32_t : 6; + __IOM uint32_t CAFAILCS0E : 1; /*!< [28..28] Calibration failed for slave0 interrupt enable */ + __IOM uint32_t CAFAILCS1E : 1; /*!< [29..29] Calibration failed for slave1 interrupt enable */ + __IOM uint32_t CASUCCS0E : 1; /*!< [30..30] Calibration success for slave0 interrupt enable */ + __IOM uint32_t CASUCCS1E : 1; /*!< [31..31] Calibration success for slave1 interrupt enable */ + } INTE_b; + }; +} R_XSPI0_Type; /*!< Size = 412 (0x19c) */ + +/* =========================================================================================================================== */ +/* ================ R_MIPI_PHY ================ */ +/* =========================================================================================================================== */ + +/** + * @brief D-PHY Controller Top (R_MIPI_PHY) + */ + +typedef struct /*!< (@ 0x40346C00) R_MIPI_PHY Structure */ +{ + union + { + __IOM uint32_t DPHYREFCR; /*!< (@ 0x00000000) D-PHY Reference Clock Setting Register */ + + struct + { + __IOM uint32_t RFREQ : 8; /*!< [7..0] Reference Clock Frequency Setting */ + uint32_t : 24; + } DPHYREFCR_b; + }; + + union + { + __IOM uint32_t DPHYPLFCR; /*!< (@ 0x00000004) D-PHY PLL Frequency Control Register */ + + struct + { + __IOM uint32_t IDIV : 2; /*!< [1..0] D-PHY PLL Input Frequency Division Ratio Select */ + uint32_t : 6; + __IOM uint32_t NFMUL : 2; /*!< [9..8] D-PHY PLL Frequency Multiplication Factor Select (Fractional + * Part) */ + uint32_t : 2; + __IOM uint32_t PMUL : 2; /*!< [13..12] D-PHY PLL Output Frequency Division Ratio Select */ + uint32_t : 2; + __IOM uint32_t NMUL : 9; /*!< [24..16] D-PHY PLL Frequency Multiplication Factor Select (Integer + * Part) */ + uint32_t : 7; + } DPHYPLFCR_b; + }; + + union + { + __IOM uint32_t DPHYPLOCR; /*!< (@ 0x00000008) D-PHY PLL Operation Control Register */ + + struct + { + __IOM uint32_t PLLSTP : 1; /*!< [0..0] D-PHY PLL Operation Control */ + uint32_t : 31; + } DPHYPLOCR_b; + }; + + union + { + __IOM uint32_t DPHYESCCR; /*!< (@ 0x0000000C) D-PHY Escape Mode Clock Control Register */ + + struct + { + __IOM uint32_t ESCDIV : 5; /*!< [4..0] Escape Mode Transfer Clock Division Ratio */ + uint32_t : 27; + } DPHYESCCR_b; + }; + + union + { + __IOM uint32_t DPHYPWRCR; /*!< (@ 0x00000010) D-PHY Power Supplying Control Register */ + + struct + { + __IOM uint32_t PWRSEN : 1; /*!< [0..0] D-PHY Power Supplying Control */ + uint32_t : 31; + } DPHYPWRCR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IM uint32_t DPHYSFR; /*!< (@ 0x0000001C) D-PHY Status Flag Register */ + + struct + { + __IM uint32_t PWRSF : 1; /*!< [0..0] D-PHY LDO Power-on Status Flag */ + uint32_t : 7; + __IM uint32_t PLLSF : 1; /*!< [8..8] D-PHY PLL Oscillation Stabilization Flag */ + uint32_t : 23; + } DPHYSFR_b; + }; + + union + { + __IOM uint32_t DPHYOCR; /*!< (@ 0x00000020) D-PHY Operation Control Register */ + + struct + { + __IOM uint32_t DPHYEN : 1; /*!< [0..0] D-PHY Operation Control */ + uint32_t : 31; + } DPHYOCR_b; + }; + + union + { + __IOM uint32_t DPHYTIM1; /*!< (@ 0x00000024) D-PHY Timing Control Register 1 */ + + struct + { + __IOM uint32_t TINIT : 19; /*!< [18..0] D-PHY T_INIT Parameter Setting */ + uint32_t : 13; + } DPHYTIM1_b; + }; + + union + { + __IOM uint32_t DPHYTIM2; /*!< (@ 0x00000028) D-PHY Timing Control Register 2 */ + + struct + { + __IOM uint32_t TCLKPREP : 8; /*!< [7..0] D-PHY T_CLK_PREPARE Parameter Setting */ + __IOM uint32_t TCLKSETT : 8; /*!< [15..8] D-PHY T_CLK_SETTLE Parameter Setting */ + __IOM uint32_t TCLKMISS : 8; /*!< [23..16] D-PHY T_CLK_MISS Parameter Setting */ + uint32_t : 8; + } DPHYTIM2_b; + }; + + union + { + __IOM uint32_t DPHYTIM3; /*!< (@ 0x0000002C) D-PHY Timing Control Register 3 */ + + struct + { + __IOM uint32_t THSPREP : 8; /*!< [7..0] D-PHY T_THS_PREPARE Parameter Setting */ + __IOM uint32_t THSSETT : 8; /*!< [15..8] D-PHY T_THS_SETTLE Parameter Setting */ + uint32_t : 16; + } DPHYTIM3_b; + }; + + union + { + __IOM uint32_t DPHYTIM4; /*!< (@ 0x00000030) D-PHY Timing Control Register 4 */ + + struct + { + __IOM uint32_t TCLKZERO : 8; /*!< [7..0] D-PHY T_CLK_ZERO Parameter Setting */ + __IOM uint32_t TCLKPRE : 8; /*!< [15..8] D-PHY T_TCLK_PRE Parameter Setting */ + __IOM uint32_t TCLKPOST : 8; /*!< [23..16] D-PHY T_TCLK_POST Parameter Setting */ + __IOM uint32_t TCLKTRL : 8; /*!< [31..24] D-PHY T_TCLK_TRAIL Parameter Setting */ + } DPHYTIM4_b; + }; + + union + { + __IOM uint32_t DPHYTIM5; /*!< (@ 0x00000034) D-PHY Timing Control Register 5 */ + + struct + { + __IOM uint32_t THSZERO : 8; /*!< [7..0] D-PHY T_THS_ZERO Parameter Setting */ + __IOM uint32_t THSTRL : 8; /*!< [15..8] D-PHY T_THS_TRAIL Parameter Setting */ + __IOM uint32_t THSEXIT : 8; /*!< [23..16] D-PHY T_THS_EXIT Parameter Setting */ + uint32_t : 8; + } DPHYTIM5_b; + }; + + union + { + __IOM uint32_t DPHYTIM6; /*!< (@ 0x00000038) D-PHY Timing Control Register 6 */ + + struct + { + __IOM uint32_t TLPX : 8; /*!< [7..0] D-PHY T_TLPX Parameter Setting */ + uint32_t : 24; + } DPHYTIM6_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t DPHYMDC; /*!< (@ 0x00000048) D-PHY Mode Control Register */ + + struct + { + __IOM uint32_t MASTEREN : 1; /*!< [0..0] D-PHY Master/Slave Select */ + uint32_t : 31; + } DPHYMDC_b; + }; +} R_MIPI_PHY_Type; /*!< Size = 76 (0x4c) */ + +/* =========================================================================================================================== */ +/* ================ R_MIPI_CSI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief MIPI_CSI Register area (R_MIPI_CSI) + */ + +typedef struct /*!< (@ 0x40347000) R_MIPI_CSI Structure */ +{ + union + { + __IM uint32_t MCG; /*!< (@ 0x00000000) Module Configuration Register */ + + struct + { + __IM uint32_t VER : 4; /*!< [3..0] VERsion of this ip */ + uint32_t : 4; + __IM uint32_t SDLN : 4; /*!< [11..8] Number of Supported Data Lanes */ + uint32_t : 4; + __IM uint32_t GSNM : 8; /*!< [23..16] NuMber of Generic Short packt FIFO */ + uint32_t : 8; + } MCG_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t MCT0; /*!< (@ 0x00000010) Module Control Register 0 */ + + struct + { + __IOM uint32_t VDLN : 4; /*!< [3..0] Numer of Valid Data Lanes */ + uint32_t : 12; + __IOM uint32_t ZLMD : 1; /*!< [16..16] Zero Length long packet output MoDe */ + __IOM uint32_t EDMD : 1; /*!< [17..17] ErrframeData notification MoDe */ + uint32_t : 1; + __IOM uint32_t RVMD : 1; /*!< [19..19] ReserVed packet reception MoDe */ + __IOM uint32_t GRMD : 1; /*!< [20..20] Generic csi-2 Rule MoDe */ + uint32_t : 3; + __IOM uint32_t ECCV13 : 1; /*!< [24..24] ECC check csi-2 Ver 1.3 mode */ + __IOM uint32_t LFSREN : 1; /*!< [25..25] LFSR Enable mode */ + uint32_t : 6; + } MCT0_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t MCT2; /*!< (@ 0x00000018) Module Control Register 2 */ + + struct + { + __IOM uint32_t FRRCLK : 9; /*!< [8..0] clock FRequency Rate to judge packet reception end */ + uint32_t : 7; + __IOM uint32_t FRRSKW : 9; /*!< [24..16] clock FRequency Rate to adjust data lane SKew */ + uint32_t : 7; + } MCT2_b; + }; + + union + { + __IOM uint32_t MCT3; /*!< (@ 0x0000001C) Module Control Register 3 */ + + struct + { + __IOM uint32_t RXEN : 1; /*!< [0..0] RX (reception) Enable */ + uint32_t : 31; + } MCT3_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __OM uint32_t RTCT; /*!< (@ 0x00000028) Reset Control Register */ + + struct + { + __OM uint32_t VSRST : 1; /*!< [0..0] Video pixel interface Software ReSeT */ + uint32_t : 31; + } RTCT_b; + }; + + union + { + __IM uint32_t RTST; /*!< (@ 0x0000002C) Reset Status Register */ + + struct + { + __IM uint32_t VSRSTS : 1; /*!< [0..0] Video pixel interface Software ReSeT Status */ + uint32_t : 31; + } RTST_b; + }; + __IM uint32_t RESERVED3[4]; + + union + { + __IOM uint32_t EPCT; /*!< (@ 0x00000040) EPD Option Control Register */ + + struct + { + __IOM uint32_t SLP : 15; /*!< [14..0] Long Packet Spacers */ + __IOM uint32_t EPDOP : 1; /*!< [15..15] EPD OPtion select */ + __IOM uint32_t SSP : 15; /*!< [30..16] epd Short Packet Spacers */ + __IOM uint32_t EPDEN : 1; /*!< [31..31] ENable EPD operation */ + } EPCT_b; + }; + + union + { + __IOM uint32_t EMCT; /*!< (@ 0x00000044) EPD Misc Option Control Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t VLSIEN : 2; /*!< [5..4] ENable Variable-Length Spacer Insertions */ + __IOM uint32_t EOTPEN : 1; /*!< [6..6] ENable EOTP */ + uint32_t : 25; + } EMCT_b; + }; + __IM uint32_t RESERVED4[2]; + + union + { + __IM uint32_t MIST; /*!< (@ 0x00000050) Module Interrupt Status Register */ + + struct + { + __IM uint32_t DL0S : 1; /*!< [0..0] interrupt Status related to Data Lane 0 */ + __IM uint32_t DL1S : 1; /*!< [1..1] interrupt Status related to Data Lane 1 */ + uint32_t : 6; + __IM uint32_t PMS : 1; /*!< [8..8] interrupt Status related to Power Management */ + __IM uint32_t GSTS : 1; /*!< [9..9] interrupt Status related to Generic ShorT packet */ + __IM uint32_t RXS : 1; /*!< [10..10] interrupt Status related to RX (Reception) */ + uint32_t : 5; + __IM uint32_t VC0S : 1; /*!< [16..16] interrupt Status related to Vitrtual Channel 0 */ + __IM uint32_t VC1S : 1; /*!< [17..17] interrupt Status related to Vitrtual Channel 1 */ + __IM uint32_t VC2S : 1; /*!< [18..18] interrupt Status related to Vitrtual Channel 2 */ + __IM uint32_t VC3S : 1; /*!< [19..19] interrupt Status related to Vitrtual Channel 3 */ + __IM uint32_t VC4S : 1; /*!< [20..20] interrupt Status related to Vitrtual Channel 4 */ + __IM uint32_t VC5S : 1; /*!< [21..21] interrupt Status related to Vitrtual Channel 5 */ + __IM uint32_t VC6S : 1; /*!< [22..22] interrupt Status related to Vitrtual Channel 6 */ + __IM uint32_t VC7S : 1; /*!< [23..23] interrupt Status related to Vitrtual Channel 7 */ + __IM uint32_t VC8S : 1; /*!< [24..24] interrupt Status related to Vitrtual Channel 8 */ + __IM uint32_t VC9S : 1; /*!< [25..25] interrupt Status related to Vitrtual Channel 9 */ + __IM uint32_t VC10S : 1; /*!< [26..26] interrupt Status related to Vitrtual Channel 10 */ + __IM uint32_t VC11S : 1; /*!< [27..27] interrupt Status related to Vitrtual Channel 11 */ + __IM uint32_t VC12S : 1; /*!< [28..28] interrupt Status related to Vitrtual Channel 12 */ + __IM uint32_t VC13S : 1; /*!< [29..29] interrupt Status related to Vitrtual Channel 13 */ + __IM uint32_t VC14S : 1; /*!< [30..30] interrupt Status related to Vitrtual Channel 14 */ + __IM uint32_t VC15S : 1; /*!< [31..31] interrupt Status related to Vitrtual Channel 15 */ + } MIST_b; + }; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint32_t DTEL; /*!< (@ 0x00000060) Receive Data Type Enable Low Register */ + + struct + { + __IOM uint32_t DTEN : 32; /*!< [31..0] Data Type ENable (DT = 0x00 to 0x1F) */ + } DTEL_b; + }; + + union + { + __IOM uint32_t DTEH; /*!< (@ 0x00000064) Receive Data Type Enable High Register */ + + struct + { + __IOM uint32_t DTEN : 32; /*!< [31..0] Data Type ENable (DT = 0x20 to 0x3F) */ + } DTEH_b; + }; + __IM uint32_t RESERVED6[2]; + + union + { + __IM uint32_t RXST; /*!< (@ 0x00000070) Receive Status Register */ + + struct + { + __IM uint32_t FRM0 : 1; /*!< [0..0] FRaMe of virtual channel 0 active */ + __IM uint32_t FRM1 : 1; /*!< [1..1] FRaMe of virtual channel 1 active */ + __IM uint32_t FRM2 : 1; /*!< [2..2] FRaMe of virtual channel 2 active */ + __IM uint32_t FRM3 : 1; /*!< [3..3] FRaMe of virtual channel 3 active */ + __IM uint32_t FRM4 : 1; /*!< [4..4] FRaMe of virtual channel 4 active */ + __IM uint32_t FRM5 : 1; /*!< [5..5] FRaMe of virtual channel 5 active */ + __IM uint32_t FRM6 : 1; /*!< [6..6] FRaMe of virtual channel 6 active */ + __IM uint32_t FRM7 : 1; /*!< [7..7] FRaMe of virtual channel 7 active */ + __IM uint32_t FRM8 : 1; /*!< [8..8] FRaMe of virtual channel 8 active */ + __IM uint32_t FRM9 : 1; /*!< [9..9] FRaMe of virtual channel 9 active */ + __IM uint32_t FRM10 : 1; /*!< [10..10] FRaMe of virtual channel 10 active */ + __IM uint32_t FRM11 : 1; /*!< [11..11] FRaMe of virtual channel 11 active */ + __IM uint32_t FRM12 : 1; /*!< [12..12] FRaMe of virtual channel 12 active */ + __IM uint32_t FRM13 : 1; /*!< [13..13] FRaMe of virtual channel 13 active */ + __IM uint32_t FRM14 : 1; /*!< [14..14] FRaMe of virtual channel 14 active */ + __IM uint32_t FRM15 : 1; /*!< [15..15] FRaMe of virtual channel 15 active */ + __IM uint32_t RACT : 1; /*!< [16..16] Rx (Reception) ACTive status */ + __IM uint32_t RACTDET : 1; /*!< [17..17] Rx (Reception) ACTive DETect */ + uint32_t : 14; + } RXST_b; + }; + + union + { + __OM uint32_t RXSC; /*!< (@ 0x00000074) Receive Status Clear Register */ + + struct + { + uint32_t : 17; + __OM uint32_t RACTDETC : 1; /*!< [17..17] Rx (Reception) ACTive DETect status Clear */ + uint32_t : 14; + } RXSC_b; + }; + + union + { + __IOM uint32_t RXIE; /*!< (@ 0x00000078) Receive Interrupt Enable Register */ + + struct + { + uint32_t : 17; + __IOM uint32_t RACTDETE : 1; /*!< [17..17] Rx (Reception) ACTive DETect interrupt Enable */ + uint32_t : 14; + } RXIE_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IM uint32_t DLST0; /*!< (@ 0x00000080) Data Lane (N) Status Register */ + + struct + { + __IM uint32_t ESH : 1; /*!< [0..0] ErrSotHs detect on data lane (N) status */ + __IM uint32_t ESS : 1; /*!< [1..1] ErrSotSynchs detect on data lane (N) status */ + __IM uint32_t ECT : 1; /*!< [2..2] ErrConTrol detect on data lane (N) status */ + __IM uint32_t EES : 1; /*!< [3..3] ErrESc detect on data lane (N) status */ + uint32_t : 12; + __IM uint32_t EUL : 1; /*!< [16..16] Exit from ULps detect on data lane (N) status */ + __IM uint32_t RUL : 1; /*!< [17..17] entry to ULps detect on data lane (N) status */ + uint32_t : 6; + __IM uint32_t ULP : 1; /*!< [24..24] rxULPsesc of data lane (N) status */ + uint32_t : 7; + } DLST0_b; + }; + + union + { + __OM uint32_t DLSC0; /*!< (@ 0x00000084) Data Lane (N) Status Clear Register */ + + struct + { + __OM uint32_t ESHC : 1; /*!< [0..0] ErrSotHs detect on data lane (N) status Clear */ + __OM uint32_t ESSC : 1; /*!< [1..1] ErrSotSynchs detect on data lane (N) status Clear */ + __OM uint32_t ECTC : 1; /*!< [2..2] ErrConTrol detect on data lane (N) status Clear */ + __OM uint32_t EESC : 1; /*!< [3..3] ErrESc detect on data lane (N) status Clear */ + uint32_t : 12; + __OM uint32_t EULC : 1; /*!< [16..16] Exit from ULps detect on data lane (N) status Clear */ + __OM uint32_t RULC : 1; /*!< [17..17] Entry to ULps detect on data lane (N) status Clear */ + uint32_t : 14; + } DLSC0_b; + }; + + union + { + __IOM uint32_t DLIE0; /*!< (@ 0x00000088) Data Lane (N) Interrupt Enable Register */ + + struct + { + __IOM uint32_t ESHE : 1; /*!< [0..0] ErrSotHs detect on data lane (N) interrupt Enable */ + __IOM uint32_t ESSE : 1; /*!< [1..1] ErrSotSynchs detect on data lane (N) interrupt Enable */ + __IOM uint32_t ECTE : 1; /*!< [2..2] ErrConTrol detect on data lane (N) interrupt Enable */ + __IOM uint32_t EESE : 1; /*!< [3..3] ErrESc detect on data lane (N) interrupt Enable */ + uint32_t : 12; + __IOM uint32_t EULE : 1; /*!< [16..16] Exit to ULps detect on data lane (N) interrupt Enable */ + __IOM uint32_t RULE : 1; /*!< [17..17] Entry to ULps detect on data lane (N) interrupt Enable */ + uint32_t : 14; + } DLIE0_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IM uint32_t DLST1; /*!< (@ 0x00000090) Data Lane (N) Status Register */ + + struct + { + __IM uint32_t ESH : 1; /*!< [0..0] ErrSotHs detect on data lane (N) status */ + __IM uint32_t ESS : 1; /*!< [1..1] ErrSotSynchs detect on data lane (N) status */ + __IM uint32_t ECT : 1; /*!< [2..2] ErrConTrol detect on data lane (N) status */ + __IM uint32_t EES : 1; /*!< [3..3] ErrESc detect on data lane (N) status */ + uint32_t : 12; + __IM uint32_t EUL : 1; /*!< [16..16] Exit from ULps detect on data lane (N) status */ + __IM uint32_t RUL : 1; /*!< [17..17] entry to ULps detect on data lane (N) status */ + uint32_t : 6; + __IM uint32_t ULP : 1; /*!< [24..24] rxULPsesc of data lane (N) status */ + uint32_t : 7; + } DLST1_b; + }; + + union + { + __OM uint32_t DLSC1; /*!< (@ 0x00000094) Data Lane (N) Status Clear Register */ + + struct + { + __OM uint32_t ESHC : 1; /*!< [0..0] ErrSotHs detect on data lane (N) status Clear */ + __OM uint32_t ESSC : 1; /*!< [1..1] ErrSotSynchs detect on data lane (N) status Clear */ + __OM uint32_t ECTC : 1; /*!< [2..2] ErrConTrol detect on data lane (N) status Clear */ + __OM uint32_t EESC : 1; /*!< [3..3] ErrESc detect on data lane (N) status Clear */ + uint32_t : 12; + __OM uint32_t EULC : 1; /*!< [16..16] Exit from ULps detect on data lane (N) status Clear */ + __OM uint32_t RULC : 1; /*!< [17..17] Entry to ULps detect on data lane (N) status Clear */ + uint32_t : 14; + } DLSC1_b; + }; + + union + { + __IOM uint32_t DLIE1; /*!< (@ 0x00000098) Data Lane (N) Interrupt Enable Register */ + + struct + { + __IOM uint32_t ESHE : 1; /*!< [0..0] ErrSotHs detect on data lane (N) interrupt Enable */ + __IOM uint32_t ESSE : 1; /*!< [1..1] ErrSotSynchs detect on data lane (N) interrupt Enable */ + __IOM uint32_t ECTE : 1; /*!< [2..2] ErrConTrol detect on data lane (N) interrupt Enable */ + __IOM uint32_t EESE : 1; /*!< [3..3] ErrESc detect on data lane (N) interrupt Enable */ + uint32_t : 12; + __IOM uint32_t EULE : 1; /*!< [16..16] Exit to ULps detect on data lane (N) interrupt Enable */ + __IOM uint32_t RULE : 1; /*!< [17..17] Entry to ULps detect on data lane (N) interrupt Enable */ + uint32_t : 14; + } DLIE1_b; + }; + __IM uint32_t RESERVED9[25]; + + union + { + __IM uint32_t VCST0; /*!< (@ 0x00000100) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST0_b; + }; + + union + { + __OM uint32_t VCSC0; /*!< (@ 0x00000104) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC0_b; + }; + + union + { + __IOM uint32_t VCIE0; /*!< (@ 0x00000108) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE0_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IM uint32_t VCST1; /*!< (@ 0x00000110) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST1_b; + }; + + union + { + __OM uint32_t VCSC1; /*!< (@ 0x00000114) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC1_b; + }; + + union + { + __IOM uint32_t VCIE1; /*!< (@ 0x00000118) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE1_b; + }; + __IM uint32_t RESERVED11; + + union + { + __IM uint32_t VCST2; /*!< (@ 0x00000120) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST2_b; + }; + + union + { + __OM uint32_t VCSC2; /*!< (@ 0x00000124) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC2_b; + }; + + union + { + __IOM uint32_t VCIE2; /*!< (@ 0x00000128) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE2_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IM uint32_t VCST3; /*!< (@ 0x00000130) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST3_b; + }; + + union + { + __OM uint32_t VCSC3; /*!< (@ 0x00000134) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC3_b; + }; + + union + { + __IOM uint32_t VCIE3; /*!< (@ 0x00000138) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE3_b; + }; + __IM uint32_t RESERVED13; + + union + { + __IM uint32_t VCST4; /*!< (@ 0x00000140) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST4_b; + }; + + union + { + __OM uint32_t VCSC4; /*!< (@ 0x00000144) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC4_b; + }; + + union + { + __IOM uint32_t VCIE4; /*!< (@ 0x00000148) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE4_b; + }; + __IM uint32_t RESERVED14; + + union + { + __IM uint32_t VCST5; /*!< (@ 0x00000150) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST5_b; + }; + + union + { + __OM uint32_t VCSC5; /*!< (@ 0x00000154) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC5_b; + }; + + union + { + __IOM uint32_t VCIE5; /*!< (@ 0x00000158) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE5_b; + }; + __IM uint32_t RESERVED15; + + union + { + __IM uint32_t VCST6; /*!< (@ 0x00000160) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST6_b; + }; + + union + { + __OM uint32_t VCSC6; /*!< (@ 0x00000164) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC6_b; + }; + + union + { + __IOM uint32_t VCIE6; /*!< (@ 0x00000168) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE6_b; + }; + __IM uint32_t RESERVED16; + + union + { + __IM uint32_t VCST7; /*!< (@ 0x00000170) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST7_b; + }; + + union + { + __OM uint32_t VCSC7; /*!< (@ 0x00000174) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC7_b; + }; + + union + { + __IOM uint32_t VCIE7; /*!< (@ 0x00000178) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE7_b; + }; + __IM uint32_t RESERVED17; + + union + { + __IM uint32_t VCST8; /*!< (@ 0x00000180) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST8_b; + }; + + union + { + __OM uint32_t VCSC8; /*!< (@ 0x00000184) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC8_b; + }; + + union + { + __IOM uint32_t VCIE8; /*!< (@ 0x00000188) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE8_b; + }; + __IM uint32_t RESERVED18; + + union + { + __IM uint32_t VCST9; /*!< (@ 0x00000190) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST9_b; + }; + + union + { + __OM uint32_t VCSC9; /*!< (@ 0x00000194) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC9_b; + }; + + union + { + __IOM uint32_t VCIE9; /*!< (@ 0x00000198) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE9_b; + }; + __IM uint32_t RESERVED19; + + union + { + __IM uint32_t VCST10; /*!< (@ 0x000001A0) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST10_b; + }; + + union + { + __OM uint32_t VCSC10; /*!< (@ 0x000001A4) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC10_b; + }; + + union + { + __IOM uint32_t VCIE10; /*!< (@ 0x000001A8) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE10_b; + }; + __IM uint32_t RESERVED20; + + union + { + __IM uint32_t VCST11; /*!< (@ 0x000001B0) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST11_b; + }; + + union + { + __OM uint32_t VCSC11; /*!< (@ 0x000001B4) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC11_b; + }; + + union + { + __IOM uint32_t VCIE11; /*!< (@ 0x000001B8) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE11_b; + }; + __IM uint32_t RESERVED21; + + union + { + __IM uint32_t VCST12; /*!< (@ 0x000001C0) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST12_b; + }; + + union + { + __OM uint32_t VCSC12; /*!< (@ 0x000001C4) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC12_b; + }; + + union + { + __IOM uint32_t VCIE12; /*!< (@ 0x000001C8) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE12_b; + }; + __IM uint32_t RESERVED22; + + union + { + __IM uint32_t VCST13; /*!< (@ 0x000001D0) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST13_b; + }; + + union + { + __OM uint32_t VCSC13; /*!< (@ 0x000001D4) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC13_b; + }; + + union + { + __IOM uint32_t VCIE13; /*!< (@ 0x000001D8) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE13_b; + }; + __IM uint32_t RESERVED23; + + union + { + __IM uint32_t VCST14; /*!< (@ 0x000001E0) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST14_b; + }; + + union + { + __OM uint32_t VCSC14; /*!< (@ 0x000001E4) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC14_b; + }; + + union + { + __IOM uint32_t VCIE14; /*!< (@ 0x000001E8) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE14_b; + }; + __IM uint32_t RESERVED24; + + union + { + __IM uint32_t VCST15; /*!< (@ 0x000001F0) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST15_b; + }; + + union + { + __OM uint32_t VCSC15; /*!< (@ 0x000001F4) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC15_b; + }; + + union + { + __IOM uint32_t VCIE15; /*!< (@ 0x000001F8) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE15_b; + }; + __IM uint32_t RESERVED25; + + union + { + __IM uint32_t PMST; /*!< (@ 0x00000200) Power Management Status Register */ + + struct + { + __IM uint32_t DSX : 1; /*!< [0..0] eXit from Stop state detect on all valid Data lanes status */ + __IM uint32_t DSN : 1; /*!< [1..1] eNtry to Stop state detect on all valid Data lanes status */ + __IM uint32_t CSX : 1; /*!< [2..2] eXit from Stop state detect on Clock lane status */ + __IM uint32_t CSN : 1; /*!< [3..3] eNtry to Stop state detect on Clock lane status */ + __IM uint32_t DUX : 1; /*!< [4..4] eXit from Ulps detect on all valid Data lanes status */ + __IM uint32_t DUN : 1; /*!< [5..5] eNtry to Ulps detect on all valid Data lanes status */ + __IM uint32_t CUX : 1; /*!< [6..6] eXit frum Ulps detect on Clock lane status */ + __IM uint32_t CUN : 1; /*!< [7..7] eNtry to Ulps detect on Clock lane status */ + uint32_t : 6; + __IM uint32_t CLSS : 1; /*!< [14..14] Stop State of Clock Lane status */ + __IM uint32_t CLUL : 1; /*!< [15..15] rxULpsclknot (inverted) of Clock Lane status */ + __IM uint32_t DLSS : 2; /*!< [17..16] Stop State of Data Lanes status */ + uint32_t : 6; + __IM uint32_t DLUL : 2; /*!< [25..24] rxULpsesc of Data Lanes status */ + uint32_t : 6; + } PMST_b; + }; + + union + { + __OM uint32_t PMSC; /*!< (@ 0x00000204) Power Management Status Clear Register */ + + struct + { + __OM uint32_t DSXC : 1; /*!< [0..0] eXit from Stop state detect on all valid Data lanes status + * Clear */ + __OM uint32_t DSNC : 1; /*!< [1..1] eNtry to Stop state detect on all valid Data lanes status + * Clear */ + __OM uint32_t CSXC : 1; /*!< [2..2] eXit from Stop state detect on Clock lane status Clear */ + __OM uint32_t CSNC : 1; /*!< [3..3] eNtry to Stop state detect on Clock lane status Clear */ + __OM uint32_t DUXC : 1; /*!< [4..4] eXit from Ulps detect on all valid Data lanes status + * Clear */ + __OM uint32_t DUNC : 1; /*!< [5..5] eNtry to Ulps detect on all valid Data lanes status Clear */ + __OM uint32_t CUXC : 1; /*!< [6..6] eXit frum Ulps detect on Clock lane status Clear */ + __OM uint32_t CUNC : 1; /*!< [7..7] eNtry to Ulps detect on Clock lane status Clear */ + uint32_t : 24; + } PMSC_b; + }; + + union + { + __IOM uint32_t PMIE; /*!< (@ 0x00000208) Power Management Interrupt Enable Register */ + + struct + { + __IOM uint32_t DSXE : 1; /*!< [0..0] eXit from Stop state detect on all valid Data lanes interrupt + * Enable */ + __IOM uint32_t DSNE : 1; /*!< [1..1] eNtry to Stop state detect on all valid Data lanes interrupt + * Enable */ + __IOM uint32_t CSXE : 1; /*!< [2..2] eXit from Stop state detect on Clock lane interrupt Enable */ + __IOM uint32_t CSNE : 1; /*!< [3..3] eNtry to Stop state detect on Clock lane interrupt Enable */ + __IOM uint32_t DUXE : 1; /*!< [4..4] eXit from Ulps detect on all valid Data lanes interrupt + * Enable */ + __IOM uint32_t DUNE : 1; /*!< [5..5] eNtry to Ulps detect on all valid Data lanes interrupt + * Enable */ + __IOM uint32_t CUXE : 1; /*!< [6..6] eXit from Ulps detect on Clock lane interrupt Enable */ + __IOM uint32_t CUNE : 1; /*!< [7..7] eNtry to Ulps detect on Clock lane interrupt Enable */ + uint32_t : 24; + } PMIE_b; + }; + __IM uint32_t RESERVED26[29]; + + union + { + __IOM uint32_t GSCT; /*!< (@ 0x00000280) Generic Short Packet Control Register */ + + struct + { + __IOM uint32_t SHTH : 7; /*!< [6..0] Stored generic short packet THreshold */ + uint32_t : 9; + __IOM uint32_t GFIF : 1; /*!< [16..16] Generic short packet store in FIFo */ + uint32_t : 15; + } GSCT_b; + }; + + union + { + __IM uint32_t GSST; /*!< (@ 0x00000284) Generic Short Packet Status Register */ + + struct + { + __IM uint32_t GNE : 1; /*!< [0..0] Generic short packet fifo Not Empty */ + __IM uint32_t GTH : 1; /*!< [1..1] more than THreshold Generic short packets existed in + * fifo */ + uint32_t : 2; + __IM uint32_t GOV : 1; /*!< [4..4] Generic short packet fifo OVerflow status */ + uint32_t : 3; + __IM uint32_t PNUM : 8; /*!< [15..8] NUMber of stored generic short Packets in fifo */ + __IM uint32_t GCD : 1; /*!< [16..16] Generic short packet fifo Clear status */ + __IM uint32_t STRDS : 1; /*!< [17..17] generic short packet SToRe DiSable */ + uint32_t : 14; + } GSST_b; + }; + + union + { + __OM uint32_t GSSC; /*!< (@ 0x00000288) Generic Short Packet Status Clear Register */ + + struct + { + uint32_t : 4; + __OM uint32_t GOVC : 1; /*!< [4..4] Generic short packet fifo OVerflow status Clear */ + uint32_t : 27; + } GSSC_b; + }; + + union + { + __IOM uint32_t GSIE; /*!< (@ 0x0000028C) Generic Short Packet Interrupt Enable Register */ + + struct + { + __IOM uint32_t GNEE : 1; /*!< [0..0] Generic short packet fifo Not Empty interrupt Enable */ + __IOM uint32_t GTHE : 1; /*!< [1..1] more than THreshold Generic short packets existed in + * fifo interrupt Enable */ + uint32_t : 2; + __IOM uint32_t GOVE : 1; /*!< [4..4] Generic short packet fifo OVerflow interrupt Enable */ + uint32_t : 27; + } GSIE_b; + }; + + union + { + __IM uint32_t GSHT; /*!< (@ 0x00000290) Generic Short Packet Register */ + + struct + { + __IM uint32_t SPDT : 16; /*!< [15..0] Stored Packet DaTa */ + __IM uint32_t DTYP : 6; /*!< [21..16] Stored packet Data TYPe */ + uint32_t : 2; + __IM uint32_t SPVC : 4; /*!< [27..24] Stored Packet Virtual Channel */ + uint32_t : 4; + } GSHT_b; + }; + + union + { + __IOM uint32_t GSIU; /*!< (@ 0x00000294) Generic Short Packet Information Update Register */ + + struct + { + __OM uint32_t FINC : 1; /*!< [0..0] generic short packet Fifo update (INCrement internal + * pointer) */ + uint32_t : 7; + __IOM uint32_t GFCLR : 1; /*!< [8..8] Generic short packet Fifo CLeaR */ + uint32_t : 7; + __OM uint32_t GFEN : 1; /*!< [16..16] Generic short packet Fifo ENable */ + uint32_t : 15; + } GSIU_b; + }; +} R_MIPI_CSI_Type; /*!< Size = 664 (0x298) */ + +/* =========================================================================================================================== */ +/* ================ R_CEU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Capture Engine Unit (R_CEU) + */ + +typedef struct /*!< (@ 0x40348000) R_CEU Structure */ +{ + union + { + __IOM uint32_t CAPSR; /*!< (@ 0x00000000) Capture Start Register */ + + struct + { + __IOM uint32_t CE : 1; /*!< [0..0] Capture enable */ + uint32_t : 15; + __IOM uint32_t CPKIL : 1; /*!< [16..16] Write 1 to this bit to perform a software reset of + * capturing. */ + uint32_t : 15; + } CAPSR_b; + }; + + union + { + __IOM uint32_t CAPCR; /*!< (@ 0x00000004) Capture Control Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t CTNCP : 1; /*!< [16..16] When capturing is started with this bit set to 1, capturing + * continues until the CE bit in CAPSR is cleared to 0 or + * a software reset is initiated by the CPKIL bit in CAPSR + * (see ). Continuous capture must be set before capturing + * is started. */ + uint32_t : 3; + __IOM uint32_t MTCM : 2; /*!< [21..20] Specify the unit for transferring data to a bus bridge + * module. */ + uint32_t : 2; + __IOM uint32_t FDRP : 8; /*!< [31..24] Set the frame drop interval in continuous-frame capture. */ + } CAPCR_b; + }; + + union + { + __IOM uint32_t CAMCR; /*!< (@ 0x00000008) Capture interface control register */ + + struct + { + __IOM uint32_t HDPOL : 1; /*!< [0..0] Sets the polarity for detection of the horizontal sync + * signal input from an external module. */ + __IOM uint32_t VDPOL : 1; /*!< [1..1] Sets the polarity for detection of the vertical sync + * signal input from an external module. */ + uint32_t : 2; + __IOM uint32_t JPG : 2; /*!< [5..4] These bits select the fetched data type. */ + uint32_t : 2; + __IOM uint32_t DTARY : 2; /*!< [9..8] Set the input order of the luminance component and chrominance + * component. */ + uint32_t : 2; + __IOM uint32_t DTIF : 1; /*!< [12..12] Sets the digital image input pins from which data is + * to be captured. */ + uint32_t : 3; + __IOM uint32_t FLDPOL : 1; /*!< [16..16] Sets the polarity of the field identification signal + * (FLD) from an external module. */ + uint32_t : 7; + __IOM uint32_t DSEL : 1; /*!< [24..24] Sets the edge for fetching the image data (D7 to D0) + * from an external module. */ + __IOM uint32_t FLDSEL : 1; /*!< [25..25] Sets the edge for capturing the field identification + * signal (FLD) from an external module. */ + __IOM uint32_t HDSEL : 1; /*!< [26..26] Sets the edge for capturing the horizontal sync signal + * (HD) from an external module. */ + __IOM uint32_t VDSEL : 1; /*!< [27..27] Sets the edge for capturing the vertical sync signal + * (VD) from an external module. */ + uint32_t : 4; + } CAMCR_b; + }; + + union + { + __IOM uint32_t CMCYR; /*!< (@ 0x0000000C) Capture Interface Cycle Register */ + + struct + { + __IOM uint32_t HCYL : 14; /*!< [13..0] Horizontal Cycle Count of External Module */ + uint32_t : 2; + __IOM uint32_t VCYL : 14; /*!< [29..16] Vertical HD Count of External Module */ + uint32_t : 2; + } CMCYR_b; + }; + + union + { + __IOM uint32_t CAMOR; /*!< (@ 0x00000010) Capture Interface Offset Register */ + + struct + { + __IOM uint32_t HOFST : 13; /*!< [12..0] Specify the capture start location in terms of the number + * of clock cycles from a horizontal sync signal (1-cycle + * units). */ + uint32_t : 3; + __IOM uint32_t VOFST : 12; /*!< [27..16] Specify the capture start location in terms of the + * HD count from a vertical sync signal (1-HD units). */ + uint32_t : 4; + } CAMOR_b; + }; + + union + { + __IOM uint32_t CAPWR; /*!< (@ 0x00000014) Capture Interface Width Register */ + + struct + { + __IOM uint32_t HWDTH : 13; /*!< [12..0] Specify the horizontal capture period. */ + uint32_t : 3; + __IOM uint32_t VWDTH : 12; /*!< [27..16] Specify the vertical capture period (4-HD units). */ + uint32_t : 4; + } CAPWR_b; + }; + + union + { + __IOM uint32_t CAIFR; /*!< (@ 0x00000018) Capture Interface Input Format Register */ + + struct + { + __IOM uint32_t FCI : 2; /*!< [1..0] Set the timing to start capturing. */ + uint32_t : 2; + __IOM uint32_t CIM : 1; /*!< [4..4] Sets the images to be captured. */ + uint32_t : 3; + __IOM uint32_t IFS : 1; /*!< [8..8] Sets the input mode for capturing images. */ + uint32_t : 23; + } CAIFR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t CRCNTR; /*!< (@ 0x00000028) CEU Register Control Register */ + + struct + { + __IOM uint32_t RC : 1; /*!< [0..0] Specifies switching of the register plane used by the + * CEU in synchronization with VD. */ + __IOM uint32_t RS : 1; /*!< [1..1] Specifies which register plane is used by the CEU in + * synchronization with VD. */ + uint32_t : 2; + __IOM uint32_t RVS : 1; /*!< [4..4] Sets the timing to switch the register plane in both-field + * capture. */ + uint32_t : 27; + } CRCNTR_b; + }; + + union + { + __IOM uint32_t CRCMPR; /*!< (@ 0x0000002C) CEU Register Forcible Control Register */ + + struct + { + __IOM uint32_t RA : 1; /*!< [0..0] Indicates the register plane currently specified. */ + uint32_t : 31; + } CRCMPR_b; + }; + + union + { + __IOM uint32_t CFLCR; /*!< (@ 0x00000030) Capture Filter Control Register */ + + struct + { + __IOM uint32_t HFRAC : 12; /*!< [11..0] Fraction Part of Horizontal Scale-Down Factor */ + __IOM uint32_t HMANT : 4; /*!< [15..12] Mantissa Part of Horizontal Scale-Down Factor */ + __IOM uint32_t VFRAC : 12; /*!< [27..16] Fraction Part of Vertical Scale-Down Factor */ + __IOM uint32_t VMANT : 4; /*!< [31..28] Mantissa Part of Vertical Scale-Down Factor */ + } CFLCR_b; + }; + + union + { + __IOM uint32_t CFSZR; /*!< (@ 0x00000034) Capture Filter Size Clip Register */ + + struct + { + __IOM uint32_t HFCLP : 12; /*!< [11..0] Specify the horizontal clipping value of the filter + * output size (4-pixel units). */ + uint32_t : 4; + __IOM uint32_t VFCLP : 12; /*!< [27..16] Set the vertical clipping value of the filter output + * size (4-pixel units). */ + uint32_t : 4; + } CFSZR_b; + }; + + union + { + __IOM uint32_t CDWDR; /*!< (@ 0x00000038) Capture Destination Width Register */ + + struct + { + __IOM uint32_t CHDW : 13; /*!< [12..0] Specify the horizontal image size in the memory area + * where the captured image is to be stored (4-byte units). */ + uint32_t : 19; + } CDWDR_b; + }; + + union + { + __IOM uint32_t CDAYR; /*!< (@ 0x0000003C) Capture Data Address Y Register */ + + struct + { + __IOM uint32_t CAYR : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR_b; + }; + + union + { + __IOM uint32_t CDACR; /*!< (@ 0x00000040) Capture Data Address C Register */ + + struct + { + __IOM uint32_t CACR : 32; /*!< [31..0] Capture Data Address C */ + } CDACR_b; + }; + + union + { + __IOM uint32_t CDBYR; /*!< (@ 0x00000044) Capture Data Bottom-Field Address Y Register */ + + struct + { + __IOM uint32_t CBYR : 32; /*!< [31..0] Set the address for storing the Y (luminance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBYR_b; + }; + + union + { + __IOM uint32_t CDBCR; /*!< (@ 0x00000048) Capture Data Bottom-Field Address C Register */ + + struct + { + __IOM uint32_t CBCR : 32; /*!< [31..0] Set the address for storing the C (chrominance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBCR_b; + }; + + union + { + __IOM uint32_t CBDSR; /*!< (@ 0x0000004C) Capture Bundle Destination Size Register */ + + struct + { + __IOM uint32_t CBVS : 23; /*!< [22..0] Select the number of lines or number of bytes for output + * to the memory in a bundle write. */ + uint32_t : 9; + } CBDSR_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t CFWCR; /*!< (@ 0x0000005C) Firewall Operation Control Register */ + + struct + { + __IOM uint32_t FWE : 1; /*!< [0..0] With the setting of FWE = 1, when an address exceeds + * the value set with FWV, the address is retained and an + * interrupt source FWF is set. After this, the address is + * not incremented and data is overwritten on the upper limit + * address. */ + uint32_t : 4; + __IOM uint32_t FWV : 27; /*!< [31..5] Specify the upper limit of a write address. */ + } CFWCR_b; + }; + + union + { + __IOM uint32_t CLFCR; /*!< (@ 0x00000060) Capture Low-Pass Filter Control Register */ + + struct + { + __IOM uint32_t LPF : 1; /*!< [0..0] Enables or disables operation of the low-pass filter. */ + uint32_t : 31; + } CLFCR_b; + }; + + union + { + __IOM uint32_t CDOCR; /*!< (@ 0x00000064) Capture Data Output Control Register */ + + struct + { + __IOM uint32_t COBS : 1; /*!< [0..0] Controls swapping in 8-bit units for data output from + * the CEU. */ + __IOM uint32_t COWS : 1; /*!< [1..1] Controls swapping in 16-bit units for data output from + * the CEU. */ + __IOM uint32_t COLS : 1; /*!< [2..2] Controls swapping in 32-bit units for data output from + * the CEU. */ + uint32_t : 1; + __IOM uint32_t CDS : 1; /*!< [4..4] Sets the image format when outputting the image data + * captured in the YCbCr422 format to the memory. */ + uint32_t : 11; + __IOM uint32_t CBE : 1; /*!< [16..16] Controls the number of lines of captured data to be + * written to the memory. */ + uint32_t : 15; + } CDOCR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t CEIER; /*!< (@ 0x00000070) Capture Event Interrupt Enable Register */ + + struct + { + __IOM uint32_t CPEIE : 1; /*!< [0..0] One-Frame Capture End Interrupt Enable */ + __IOM uint32_t CFEIE : 1; /*!< [1..1] CFE Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t IGRWIE : 1; /*!< [4..4] Register-Access-During-Capture Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t HDIE : 1; /*!< [8..8] HD Interrupt Enable */ + __IOM uint32_t VDIE : 1; /*!< [9..9] VD Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t CPBE1IE : 1; /*!< [12..12] CPBE1 Interrupt Enable */ + __IOM uint32_t CPBE2IE : 1; /*!< [13..13] CPBE2 Interrupt Enable */ + __IOM uint32_t CPBE3IE : 1; /*!< [14..14] CPBE3 Interrupt Enable */ + __IOM uint32_t CPBE4IE : 1; /*!< [15..15] CPBE4 Interrupt Enable */ + __IOM uint32_t CDTOFIE : 1; /*!< [16..16] CDTOF Interrupt Enable */ + __IOM uint32_t IGHSIE : 1; /*!< [17..17] IGHS Interrupt Enable */ + __IOM uint32_t IGVSIE : 1; /*!< [18..18] IGVS Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t VBPIE : 1; /*!< [20..20] VBP Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t FWFIE : 1; /*!< [23..23] FWF Interrupt Enable */ + __IOM uint32_t NHDIE : 1; /*!< [24..24] Non-HD Interrupt Enable */ + __IOM uint32_t NVDIE : 1; /*!< [25..25] Non-VD Interrupt Enable */ + uint32_t : 6; + } CEIER_b; + }; + + union + { + __IOM uint32_t CETCR; /*!< (@ 0x00000074) Capture Event Flag Clear Register */ + + struct + { + __IOM uint32_t CPE : 1; /*!< [0..0] An interrupt indicating that capturing of one frame from + * an external module has finished. */ + __IOM uint32_t CFE : 1; /*!< [1..1] An interrupt indicating that capturing of one field from + * an external module has finished. */ + uint32_t : 2; + __IOM uint32_t IGRW : 1; /*!< [4..4] An interrupt indicating that during capturing, access + * was attempted to a register to which writing during operation + * is prohibited. */ + uint32_t : 3; + __IOM uint32_t HD : 1; /*!< [8..8] An interrupt indicating that HD (horizontal sync signal) + * was input from an external module. */ + __IOM uint32_t VD : 1; /*!< [9..9] An interrupt indicating that VD (vertical sync signal) + * was input from an external module. */ + uint32_t : 2; + __IOM uint32_t CPBE1 : 1; /*!< [12..12] An interrupt indicating that writing to CDAYR and CDACR + * in a bundle write has finished. */ + __IOM uint32_t CPBE2 : 1; /*!< [13..13] An interrupt indicating that writing to CDAYR2 and + * CDACR2 in a bundle write has finished. */ + __IOM uint32_t CPBE3 : 1; /*!< [14..14] An interrupt indicating that writing to CDBYR and CDBCR + * in a bundle write has finished. */ + __IOM uint32_t CPBE4 : 1; /*!< [15..15] An interrupt indicating that writing to CDBYR2 and + * CDBCR2 in a bundle write has finished. */ + __IOM uint32_t CDTOF : 1; /*!< [16..16] An interrupt indicating that data overflowed in the + * CRAM of the write buffer */ + __IOM uint32_t IGHS : 1; /*!< [17..17] An interrupt generated when the number of HD cycles + * set in CMCYR differ from the number of HD cycles input + * from an external module. */ + __IOM uint32_t IGVS : 1; /*!< [18..18] An interrupt generated when the number of VD cycles + * set in CMCYR differ from the number of VD cycles input + * from an external module. */ + uint32_t : 1; + __IOM uint32_t VBP : 1; /*!< [20..20] An interrupt indicating that VD has been input while + * the CEU holds data (insufficient vertical-sync front porch). */ + uint32_t : 2; + __IOM uint32_t FWF : 1; /*!< [23..23] The interrupt is generated when data is written to + * the address that exceeds the value specified with CFWCR.FMV. */ + __IOM uint32_t NHD : 1; /*!< [24..24] An interrupt indicating that no HD was input. */ + __IOM uint32_t NVD : 1; /*!< [25..25] An interrupt indicating that no VD was input. */ + uint32_t : 6; + } CETCR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IM uint32_t CSTSR; /*!< (@ 0x0000007C) Capture Status Register */ + + struct + { + __IM uint32_t CPTON : 1; /*!< [0..0] Indicates that the CEU is operating. */ + uint32_t : 15; + __IM uint32_t CPFLD : 1; /*!< [16..16] Indicates which field is being captured. */ + uint32_t : 7; + __IM uint32_t CRST : 1; /*!< [24..24] Indicates which register plane is currently used. */ + uint32_t : 7; + } CSTSR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IM uint32_t CDSSR; /*!< (@ 0x00000084) Capture Data Size Register */ + + struct + { + __IM uint32_t CDSS : 32; /*!< [31..0] Indicate the size of data written to the memory in data + * enable fetch. */ + } CDSSR_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t CDAYR2; /*!< (@ 0x00000090) Capture Data Address Y Register 2 */ + + struct + { + __IOM uint32_t CAYR2 : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR2_b; + }; + + union + { + __IOM uint32_t CDACR2; /*!< (@ 0x00000094) Capture Data Address C Register 2 */ + + struct + { + __IOM uint32_t CACR2 : 32; /*!< [31..0] Capture Data Address C2 */ + } CDACR2_b; + }; + + union + { + __IOM uint32_t CDBYR2; /*!< (@ 0x00000098) Capture Data Bottom-Field Address Y Register + * 2 */ + + struct + { + __IOM uint32_t CBYR2 : 32; /*!< [31..0] Set the address for storing the Y component data of + * the captured bottom-field data (4-pixel units). */ + } CDBYR2_b; + }; + + union + { + __IOM uint32_t CDBCR2; /*!< (@ 0x0000009C) Capture Data Bottom-Field Address C Register + * 2 */ + + struct + { + __IOM uint32_t CBCR2 : 32; /*!< [31..0] Set the address for storing the C component data of + * the captured bottom-field data (4-pixel units). */ + } CDBCR2_b; + }; + + union + { + __IOM uint32_t AXIBUSCTL2; /*!< (@ 0x000000A0) AXI Bus Control Register 2 */ + + struct + { + __IOM uint32_t AWCACHE : 4; /*!< [3..0] AWCACHE[3:0] Signals for Capture Engine Unit */ + uint32_t : 28; + } AXIBUSCTL2_b; + }; + __IM uint32_t RESERVED6[987]; + + union + { + __IOM uint32_t CAMOR_B; /*!< (@ 0x00001010) Capture Interface Offset Register */ + + struct + { + __IOM uint32_t HOFST : 13; /*!< [12..0] Specify the capture start location in terms of the number + * of clock cycles from a horizontal sync signal (1-cycle + * units). */ + uint32_t : 3; + __IOM uint32_t VOFST : 12; /*!< [27..16] Specify the capture start location in terms of the + * HD count from a vertical sync signal (1-HD units). */ + uint32_t : 4; + } CAMOR_B_b; + }; + + union + { + __IOM uint32_t CAPWR_B; /*!< (@ 0x00001014) Capture Interface Width Register */ + + struct + { + __IOM uint32_t HWDTH : 13; /*!< [12..0] Specify the horizontal capture period. */ + uint32_t : 3; + __IOM uint32_t VWDTH : 12; /*!< [27..16] Specify the vertical capture period (4-HD units). */ + uint32_t : 4; + } CAPWR_B_b; + }; + __IM uint32_t RESERVED7[6]; + + union + { + __IOM uint32_t CFLCR_B; /*!< (@ 0x00001030) Capture Filter Control Register */ + + struct + { + __IOM uint32_t HFRAC : 12; /*!< [11..0] Fraction Part of Horizontal Scale-Down Factor */ + __IOM uint32_t HMANT : 4; /*!< [15..12] Mantissa Part of Horizontal Scale-Down Factor */ + __IOM uint32_t VFRAC : 12; /*!< [27..16] Fraction Part of Vertical Scale-Down Factor */ + __IOM uint32_t VMANT : 4; /*!< [31..28] Mantissa Part of Vertical Scale-Down Factor */ + } CFLCR_B_b; + }; + + union + { + __IOM uint32_t CFSZR_B; /*!< (@ 0x00001034) Capture Filter Size Clip Register */ + + struct + { + __IOM uint32_t HFCLP : 12; /*!< [11..0] Specify the horizontal clipping value of the filter + * output size (4-pixel units). */ + uint32_t : 4; + __IOM uint32_t VFCLP : 12; /*!< [27..16] Set the vertical clipping value of the filter output + * size (4-pixel units). */ + uint32_t : 4; + } CFSZR_B_b; + }; + + union + { + __IOM uint32_t CDWDR_B; /*!< (@ 0x00001038) Capture Destination Width Register */ + + struct + { + __IOM uint32_t CHDW : 13; /*!< [12..0] Specify the horizontal image size in the memory area + * where the captured image is to be stored (4-byte units). */ + uint32_t : 19; + } CDWDR_B_b; + }; + + union + { + __IOM uint32_t CDAYR_B; /*!< (@ 0x0000103C) Capture Data Address Y Register */ + + struct + { + __IOM uint32_t CAYR : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR_B_b; + }; + + union + { + __IOM uint32_t CDACR_B; /*!< (@ 0x00001040) Capture Data Address C Register */ + + struct + { + __IOM uint32_t CACR : 32; /*!< [31..0] Capture Data Address C */ + } CDACR_B_b; + }; + + union + { + __IOM uint32_t CDBYR_B; /*!< (@ 0x00001044) Capture Data Bottom-Field Address Y Register */ + + struct + { + __IOM uint32_t CBYR : 32; /*!< [31..0] Set the address for storing the Y (luminance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBYR_B_b; + }; + + union + { + __IOM uint32_t CDBCR_B; /*!< (@ 0x00001048) Capture Data Bottom-Field Address C Register */ + + struct + { + __IOM uint32_t CBCR : 32; /*!< [31..0] Set the address for storing the C (chrominance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBCR_B_b; + }; + + union + { + __IOM uint32_t CBDSR_B; /*!< (@ 0x0000104C) Capture Bundle Destination Size Register */ + + struct + { + __IOM uint32_t CBVS : 23; /*!< [22..0] Select the number of lines or number of bytes for output + * to the memory in a bundle write. */ + uint32_t : 9; + } CBDSR_B_b; + }; + __IM uint32_t RESERVED8[4]; + + union + { + __IOM uint32_t CLFCR_B; /*!< (@ 0x00001060) Capture Low-Pass Filter Control Register */ + + struct + { + __IOM uint32_t LPF : 1; /*!< [0..0] Enables or disables operation of the low-pass filter. */ + uint32_t : 31; + } CLFCR_B_b; + }; + + union + { + __IOM uint32_t CDOCR_B; /*!< (@ 0x00001064) Capture Data Output Control Register */ + + struct + { + __IOM uint32_t COBS : 1; /*!< [0..0] Controls swapping in 8-bit units for data output from + * the CEU. */ + __IOM uint32_t COWS : 1; /*!< [1..1] Controls swapping in 16-bit units for data output from + * the CEU. */ + __IOM uint32_t COLS : 1; /*!< [2..2] Controls swapping in 32-bit units for data output from + * the CEU. */ + uint32_t : 1; + __IOM uint32_t CDS : 1; /*!< [4..4] Sets the image format when outputting the image data + * captured in the YCbCr422 format to the memory. */ + uint32_t : 11; + __IOM uint32_t CBE : 1; /*!< [16..16] Controls the number of lines of captured data to be + * written to the memory. */ + uint32_t : 15; + } CDOCR_B_b; + }; + __IM uint32_t RESERVED9[10]; + + union + { + __IOM uint32_t CDAYR2_B; /*!< (@ 0x00001090) Capture Data Address Y Register 2 */ + + struct + { + __IOM uint32_t CAYR2 : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR2_B_b; + }; + + union + { + __IOM uint32_t CDACR2_B; /*!< (@ 0x00001094) Capture Data Address C Register 2 */ + + struct + { + __IOM uint32_t CACR2 : 32; /*!< [31..0] Capture Data Address C2 */ + } CDACR2_B_b; + }; + + union + { + __IOM uint32_t CDBYR2_B; /*!< (@ 0x00001098) Capture Data Bottom-Field Address Y Register + * 2 */ + + struct + { + __IOM uint32_t CBYR2 : 32; /*!< [31..0] Set the address for storing the Y component data of + * the captured bottom-field data (4-pixel units). */ + } CDBYR2_B_b; + }; + + union + { + __IOM uint32_t CDBCR2_B; /*!< (@ 0x0000109C) Capture Data Bottom-Field Address C Register + * 2 */ + + struct + { + __IOM uint32_t CBCR2 : 32; /*!< [31..0] Set the address for storing the C component data of + * the captured bottom-field data (4-pixel units). */ + } CDBCR2_B_b; + }; + __IM uint32_t RESERVED10[988]; + + union + { + __IOM uint32_t CAMOR_M; /*!< (@ 0x00002010) Capture Interface Offset Register */ + + struct + { + __IOM uint32_t HOFST : 13; /*!< [12..0] Specify the capture start location in terms of the number + * of clock cycles from a horizontal sync signal (1-cycle + * units). */ + uint32_t : 3; + __IOM uint32_t VOFST : 12; /*!< [27..16] Specify the capture start location in terms of the + * HD count from a vertical sync signal (1-HD units). */ + uint32_t : 4; + } CAMOR_M_b; + }; + + union + { + __IOM uint32_t CAPWR_M; /*!< (@ 0x00002014) Capture Interface Width Register */ + + struct + { + __IOM uint32_t HWDTH : 13; /*!< [12..0] Specify the horizontal capture period. */ + uint32_t : 3; + __IOM uint32_t VWDTH : 12; /*!< [27..16] Specify the vertical capture period (4-HD units). */ + uint32_t : 4; + } CAPWR_M_b; + }; + __IM uint32_t RESERVED11[6]; + + union + { + __IOM uint32_t CFLCR_M; /*!< (@ 0x00002030) Capture Filter Control Register */ + + struct + { + __IOM uint32_t HFRAC : 12; /*!< [11..0] Fraction Part of Horizontal Scale-Down Factor */ + __IOM uint32_t HMANT : 4; /*!< [15..12] Mantissa Part of Horizontal Scale-Down Factor */ + __IOM uint32_t VFRAC : 12; /*!< [27..16] Fraction Part of Vertical Scale-Down Factor */ + __IOM uint32_t VMANT : 4; /*!< [31..28] Mantissa Part of Vertical Scale-Down Factor */ + } CFLCR_M_b; + }; + + union + { + __IOM uint32_t CFSZR_M; /*!< (@ 0x00002034) Capture Filter Size Clip Register */ + + struct + { + __IOM uint32_t HFCLP : 12; /*!< [11..0] Specify the horizontal clipping value of the filter + * output size (4-pixel units). */ + uint32_t : 4; + __IOM uint32_t VFCLP : 12; /*!< [27..16] Set the vertical clipping value of the filter output + * size (4-pixel units). */ + uint32_t : 4; + } CFSZR_M_b; + }; + + union + { + __IOM uint32_t CDWDR_M; /*!< (@ 0x00002038) Capture Destination Width Register */ + + struct + { + __IOM uint32_t CHDW : 13; /*!< [12..0] Specify the horizontal image size in the memory area + * where the captured image is to be stored (4-byte units). */ + uint32_t : 19; + } CDWDR_M_b; + }; + + union + { + __IOM uint32_t CDAYR_M; /*!< (@ 0x0000203C) Capture Data Address Y Register */ + + struct + { + __IOM uint32_t CAYR : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR_M_b; + }; + + union + { + __IOM uint32_t CDACR_M; /*!< (@ 0x00002040) Capture Data Address C Register */ + + struct + { + __IOM uint32_t CACR : 32; /*!< [31..0] Capture Data Address C */ + } CDACR_M_b; + }; + + union + { + __IOM uint32_t CDBYR_M; /*!< (@ 0x00002044) Capture Data Bottom-Field Address Y Register */ + + struct + { + __IOM uint32_t CBYR : 32; /*!< [31..0] Set the address for storing the Y (luminance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBYR_M_b; + }; + + union + { + __IOM uint32_t CDBCR_M; /*!< (@ 0x00002048) Capture Data Bottom-Field Address C Register */ + + struct + { + __IOM uint32_t CBCR : 32; /*!< [31..0] Set the address for storing the C (chrominance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBCR_M_b; + }; + + union + { + __IOM uint32_t CBDSR_M; /*!< (@ 0x0000204C) Capture Bundle Destination Size Register */ + + struct + { + __IOM uint32_t CBVS : 23; /*!< [22..0] Select the number of lines or number of bytes for output + * to the memory in a bundle write. */ + uint32_t : 9; + } CBDSR_M_b; + }; + __IM uint32_t RESERVED12[4]; + + union + { + __IOM uint32_t CLFCR_M; /*!< (@ 0x00002060) Capture Low-Pass Filter Control Register */ + + struct + { + __IOM uint32_t LPF : 1; /*!< [0..0] Enables or disables operation of the low-pass filter. */ + uint32_t : 31; + } CLFCR_M_b; + }; + + union + { + __IOM uint32_t CDOCR_M; /*!< (@ 0x00002064) Capture Data Output Control Register */ + + struct + { + __IOM uint32_t COBS : 1; /*!< [0..0] Controls swapping in 8-bit units for data output from + * the CEU. */ + __IOM uint32_t COWS : 1; /*!< [1..1] Controls swapping in 16-bit units for data output from + * the CEU. */ + __IOM uint32_t COLS : 1; /*!< [2..2] Controls swapping in 32-bit units for data output from + * the CEU. */ + uint32_t : 1; + __IOM uint32_t CDS : 1; /*!< [4..4] Sets the image format when outputting the image data + * captured in the YCbCr422 format to the memory. */ + uint32_t : 11; + __IOM uint32_t CBE : 1; /*!< [16..16] Controls the number of lines of captured data to be + * written to the memory. */ + uint32_t : 15; + } CDOCR_M_b; + }; + __IM uint32_t RESERVED13[10]; + + union + { + __IOM uint32_t CDAYR2_M; /*!< (@ 0x00002090) Capture Data Address Y Register 2 */ + + struct + { + __IOM uint32_t CAYR2 : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR2_M_b; + }; + + union + { + __IOM uint32_t CDACR2_M; /*!< (@ 0x00002094) Capture Data Address C Register 2 */ + + struct + { + __IOM uint32_t CACR2 : 32; /*!< [31..0] Capture Data Address C2 */ + } CDACR2_M_b; + }; + + union + { + __IOM uint32_t CDBYR2_M; /*!< (@ 0x00002098) Capture Data Bottom-Field Address Y Register + * 2 */ + + struct + { + __IOM uint32_t CBYR2 : 32; /*!< [31..0] Set the address for storing the Y component data of + * the captured bottom-field data (4-pixel units). */ + } CDBYR2_M_b; + }; + + union + { + __IOM uint32_t CDBCR2_M; /*!< (@ 0x0000209C) Capture Data Bottom-Field Address C Register + * 2 */ + + struct + { + __IOM uint32_t CBCR2 : 32; /*!< [31..0] Set the address for storing the C component data of + * the captured bottom-field data (4-pixel units). */ + } CDBCR2_M_b; + }; +} R_CEU_Type; /*!< Size = 8352 (0x20a0) */ + +/* =========================================================================================================================== */ +/* ================ R_ULPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ultra-Low Power Timer 0 (R_ULPT0) + */ + +typedef struct /*!< (@ 0x40220000) R_ULPT0 Structure */ +{ + union + { + __IOM uint32_t ULPTCNT; /*!< (@ 0x00000000) ULPT Counter Register */ + + struct + { + __IOM uint32_t ULPTCNT : 32; /*!< [31..0] 32bit counter and reload registerNOTE : When 1 is written + * to the TSTOP bit in the ULPTCR register, the 32-bit counter + * is forcibly stopped and set to FFFFFFFFH. */ + } ULPTCNT_b; + }; + + union + { + __IOM uint32_t ULPTCMA; /*!< (@ 0x00000004) ULPT Compare Match A Register */ + + struct + { + __IOM uint32_t ULPTCMA : 32; /*!< [31..0] ULPT Compare Match A RegisterNOTE : When 1 is written + * to the TSTOP bit in the ULPTCR register, set to FFFFFFFFH */ + } ULPTCMA_b; + }; + + union + { + __IOM uint32_t ULPTCMB; /*!< (@ 0x00000008) ULPT Compare Match B Register */ + + struct + { + __IOM uint32_t ULPTCMB : 32; /*!< [31..0] AGT Compare Match B RegisterNOTE : When 1 is written + * to the TSTOP bit in the ULPTCR register, set to FFFFFFFFH */ + } ULPTCMB_b; + }; + + union + { + __IOM uint8_t ULPTCR; /*!< (@ 0x0000000C) ULPT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] ULPT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] ULPT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] ULPT count forced stop */ + uint8_t : 2; + __IOM uint8_t TUNDF : 1; /*!< [5..5] ULPT underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] ULPT compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] ULPT compare match B flag */ + } ULPTCR_b; + }; + + union + { + __IOM uint8_t ULPTMR1; /*!< (@ 0x0000000D) ULPT Mode Register 1 */ + + struct + { + uint8_t : 1; + __IOM uint8_t TMOD1 : 1; /*!< [1..1] ULPT operating mode select */ + uint8_t : 1; + __IOM uint8_t TEDGPL : 1; /*!< [3..3] ULPTEVI edge polarity select */ + uint8_t : 1; + __IOM uint8_t TCK1 : 1; /*!< [5..5] ULPT count source select */ + uint8_t : 2; + } ULPTMR1_b; + }; + + union + { + __IOM uint8_t ULPTMR2; /*!< (@ 0x0000000E) ULPT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] fsub/LOCO count source clock frequency division ratio + * select */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] ULPT Low Power Mode */ + } ULPTMR2_b; + }; + + union + { + __IOM uint8_t ULPTMR3; /*!< (@ 0x0000000F) ULPT Mode Register 3 */ + + struct + { + __IOM uint8_t TCNTCTL : 1; /*!< [0..0] ULPT count function select */ + __IOM uint8_t TEVPOL : 1; /*!< [1..1] ULPTEVI polarity switch */ + __IOM uint8_t TOPOL : 1; /*!< [2..2] ULPTO polarity select */ + uint8_t : 1; + __IOM uint8_t TEECTL : 2; /*!< [5..4] ULPTEE function select */ + __IOM uint8_t TEEPOL : 2; /*!< [7..6] ULPTEE edge polarity select */ + } ULPTMR3_b; + }; + + union + { + __IOM uint8_t ULPTIOC; /*!< (@ 0x00000010) ULPT I/O Control Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t TOE : 1; /*!< [2..2] ULPTO output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] ULPTEVI input filter select */ + __IOM uint8_t TIOGT0 : 1; /*!< [6..6] ULPTEVI count control */ + uint8_t : 1; + } ULPTIOC_b; + }; + + union + { + __IOM uint8_t ULPTISR; /*!< (@ 0x00000011) ULPT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t RCCPSEL2 : 1; /*!< [2..2] ULPTEE polarty selection */ + uint8_t : 5; + } ULPTISR_b; + }; + + union + { + __IOM uint8_t ULPTCMSR; /*!< (@ 0x00000012) ULPT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] ULPTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] ULPTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] ULPTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] ULPTOB polarity select */ + uint8_t : 1; + } ULPTCMSR_b; + }; + __IM uint8_t RESERVED; +} R_ULPT0_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG_OCD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief On-Chip Debug Function (R_DEBUG_OCD) + */ + +typedef struct /*!< (@ 0x40011000) R_DEBUG_OCD Structure */ +{ + union + { + __IM uint32_t MCUERRSTAT; /*!< (@ 0x00000000) MCU Error Status Register */ + + struct + { + __IM uint32_t ZERO : 1; /*!< [0..0] Zeroization status flag */ + uint32_t : 31; + } MCUERRSTAT_b; + }; + + union + { + __IOM uint32_t MCUCTRL; /*!< (@ 0x00000004) MCU Control Register */ + + struct + { + __IOM uint32_t EDBGRQ0 : 1; /*!< [0..0] External Debug Request for CPU0 */ + __IOM uint32_t EDBGRQ1 : 1; /*!< [1..1] External Debug Request for CPU1 */ + uint32_t : 6; + __IOM uint32_t DBIRQ0 : 1; /*!< [8..8] Writing 1 to the bit wakes up the CPU0 from Deep Sleep + * mode or the MCU from Software Standby Mode or Deep Software + * Standby mode */ + __IOM uint32_t DBIRQ1 : 1; /*!< [9..9] Writing 1 to the bit wakes up the CPU1 from Deep Sleep + * mode or the MCU from Software Standby Mode or Deep Software + * Standby mode */ + uint32_t : 6; + __IOM uint32_t CPUWAIT0 : 1; /*!< [16..16] CPU0 WAIT SETTING */ + __IOM uint32_t CPUWAIT1 : 1; /*!< [17..17] CPU1 WAIT SETTING */ + uint32_t : 14; + } MCUCTRL_b; + }; + __IM uint32_t RESERVED[62]; + + union + { + __IOM uint32_t JBMDR; /*!< (@ 0x00000100) JTAG Boot Mode Entry Register */ + + struct + { + __IOM uint32_t KEY : 8; /*!< [7..0] Mode entry key */ + uint32_t : 24; + } JBMDR_b; + }; + __IM uint32_t RESERVED1[7]; + + union + { + __IOM uint32_t JBRDR; /*!< (@ 0x00000120) JTAG Boot Receive Data Register */ + + struct + { + __IOM uint32_t RDAT : 32; /*!< [31..0] Received data register */ + } JBRDR_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t JBTDR; /*!< (@ 0x00000130) JTAG Boot Transmit Data Register */ + + struct + { + __IOM uint32_t TDAT : 32; /*!< [31..0] Transmitted data register */ + } JBTDR_b; + }; + __IM uint32_t RESERVED3[3]; + + union + { + __IOM uint32_t JBSTR; /*!< (@ 0x00000140) JTAG Boot Status Register */ + + struct + { + __IOM uint32_t RDF : 1; /*!< [0..0] Receive buffer full */ + __IOM uint32_t TDE : 1; /*!< [1..1] Transmit data empty */ + uint32_t : 30; + } JBSTR_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IOM uint32_t JBICR; /*!< (@ 0x00000150) JTAG Boot Interrupt Control Register */ + + struct + { + __IOM uint32_t RDFIE : 1; /*!< [0..0] Receive buffer full interrupt enabled */ + uint32_t : 31; + } JBICR_b; + }; + __IM uint32_t RESERVED5[107]; + + union + { + __IM uint32_t FSBLSTATM; /*!< (@ 0x00000300) First Stage Boot Loader Status Monitor Register */ + + struct + { + __IM uint32_t CS : 1; /*!< [0..0] FSBL completion status */ + __IM uint32_t RS : 1; /*!< [1..1] FSBL result status */ + uint32_t : 30; + } FSBLSTATM_b; + }; +} R_DEBUG_OCD_Type; /*!< Size = 772 (0x304) */ + +/* =========================================================================================================================== */ +/* ================ R_DOTF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Decryption On The Fly (R_DOTF) + */ + +typedef struct /*!< (@ 0x40268800) R_DOTF Structure */ +{ + union + { + __IOM uint32_t CONVAREAST; /*!< (@ 0x00000000) DOTF Conversion Area Start Address Register */ + + struct + { + uint32_t : 12; + __IOM uint32_t CONVAREAST : 20; /*!< [31..12] First address of decryption processing area */ + } CONVAREAST_b; + }; + + union + { + __IOM uint32_t CONVAREAD; /*!< (@ 0x00000004) DOTF Conversion Area End Address Register */ + + struct + { + uint32_t : 12; + __IOM uint32_t CONVAREAD : 20; /*!< [31..12] End address of decryption processing area */ + } CONVAREAD_b; + }; + __IM uint32_t RESERVED[30]; + + union + { + __IOM uint32_t REG00; /*!< (@ 0x00000080) Register 0 */ + + struct + { + uint32_t : 9; + __IOM uint32_t B09 : 1; /*!< [9..9] Bit 09 */ + uint32_t : 6; + __IOM uint32_t B16 : 1; /*!< [16..16] Bit 09 */ + __IOM uint32_t B17 : 1; /*!< [17..17] Bit 17 */ + uint32_t : 2; + __IOM uint32_t B20 : 1; /*!< [20..20] Bit 20 */ + uint32_t : 3; + __IOM uint32_t B24 : 2; /*!< [25..24] Bit24-25 */ + uint32_t : 2; + __IOM uint32_t B28 : 2; /*!< [29..28] Bit28-29 */ + uint32_t : 2; + } REG00_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t REG03; /*!< (@ 0x0000008C) Register 03 */ + + struct + { + __IOM uint32_t B00 : 32; /*!< [31..0] Bit 0 */ + } REG03_b; + }; +} R_DOTF_Type; /*!< Size = 144 (0x90) */ + +/* =========================================================================================================================== */ +/* ================ R_AGTX0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGTX0) + */ + +typedef struct /*!< (@ 0x40221000) R_AGTX0 Structure */ +{ + union + { + __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers */ + __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers */ + }; +} R_AGTX0_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_COMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Common Agent (R_COMA) + */ + +typedef struct /*!< (@ 0x403C9000) R_COMA Structure */ +{ + union + { + __IM uint32_t RIPV; /*!< (@ 0x00000000) IP Version Register */ + + struct + { + __IM uint32_t TIPV : 4; /*!< [3..0] Top Module IP Version Number */ + __IM uint32_t GWIPV : 4; /*!< [7..4] Gateway CPU Agent IP Version Number */ + __IM uint32_t FWIPV : 4; /*!< [11..8] Forwarding Engine IP Version Number */ + __IM uint32_t EAIPV : 4; /*!< [15..12] Ethernet Agent IP Version Number */ + __IM uint32_t FBIPV : 4; /*!< [19..16] Fabric Bus IP Version Number */ + __IM uint32_t CAIPV : 4; /*!< [23..20] Common Agent IP Version Number */ + uint32_t : 8; + } RIPV_b; + }; + + union + { + __IOM uint32_t RRC; /*!< (@ 0x00000004) Reset Configuration Register */ + + struct + { + __IOM uint32_t RR : 1; /*!< [0..0] Software Reset */ + uint32_t : 31; + } RRC_b; + }; + + union + { + __IOM uint32_t RCEC; /*!< (@ 0x00000008) Clock Enable Configuration Register */ + + struct + { + __IOM uint32_t ACE : 7; /*!< [6..0] Agent Clock Enable */ + uint32_t : 9; + __IOM uint32_t RCE : 1; /*!< [16..16] Clock Enable */ + uint32_t : 15; + } RCEC_b; + }; + + union + { + __IM uint32_t RCDC; /*!< (@ 0x0000000C) Clock Disable Configuration Register */ + + struct + { + __IM uint32_t ACD : 7; /*!< [6..0] Agent Clock Disable */ + uint32_t : 9; + __IM uint32_t RCD : 1; /*!< [16..16] Clock Disable */ + uint32_t : 15; + } RCDC_b; + }; + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t CABPIBWMC[8]; /*!< (@ 0x00000020) Buffer Pool IPV Based Watermark Configuration + * Register [0..7] */ + + struct + { + __IOM uint32_t IBUWMPN : 10; /*!< [9..0] IPV Based Unsecure Watermark Pointer Number */ + uint32_t : 6; + __IOM uint32_t IBSWMPN : 10; /*!< [25..16] IPV Based Secure Watermark Pointer Number */ + uint32_t : 6; + } CABPIBWMC_b[8]; + }; + + union + { + __IOM uint32_t CABPWMLC; /*!< (@ 0x00000040) Buffer Pool Watermark Level Configuration Register */ + + struct + { + __IOM uint32_t WMFL : 13; /*!< [12..0] Watermark Flush Level */ + uint32_t : 3; + __IOM uint32_t WMCL : 13; /*!< [28..16] Watermark Critical Level */ + uint32_t : 3; + } CABPWMLC_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t CABPPFLC[2]; /*!< (@ 0x00000050) Buffer Pointer Pause Frame Level [0..1] Configuration + * Register */ + + struct + { + __IOM uint32_t PDL : 13; /*!< [12..0] Pause De-Assertion Level */ + uint32_t : 3; + __IOM uint32_t PAL : 13; /*!< [28..16] Pause Assertion Level */ + uint32_t : 3; + } CABPPFLC_b[2]; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t CABPPWMLC[3]; /*!< (@ 0x00000060) Port [0..2] Buffer Pool Watermark Level Configuration + * Register */ + + struct + { + __IOM uint32_t PWMFL : 13; /*!< [12..0] Watermark Flush Level */ + uint32_t : 3; + __IOM uint32_t PWMCL : 13; /*!< [28..16] Watermark Critical Level */ + uint32_t : 3; + } CABPPWMLC_b[3]; + }; + __IM uint32_t RESERVED3[13]; + __IOM R_COMA_CABPPPFLC_Type CABPPPFLC0; /*!< (@ 0x000000A0) 0 */ + __IOM R_COMA_CABPPPFLC_Type CABPPPFLC1; /*!< (@ 0x000000A8) 1 */ + __IOM R_COMA_CABPPPFLC_Type CABPPPFLC2; /*!< (@ 0x000000B0) 2 */ + __IM uint32_t RESERVED4[18]; + + union + { + __IOM uint32_t CABPULC[3]; /*!< (@ 0x00000100) Buffer Pointer Utilization Level Configuration + * Register [0..2] */ + + struct + { + __IOM uint32_t MXNPN : 13; /*!< [12..0] Maximum Number of Pointer for Port */ + uint32_t : 3; + __IOM uint32_t MNNPN : 13; /*!< [28..16] Minimum Number of Pointer for Port */ + uint32_t : 3; + } CABPULC_b[3]; + }; + __IM uint32_t RESERVED5[13]; + + union + { + __IOM uint32_t CABPIRM; /*!< (@ 0x00000140) Buffer Pool Initialization Register Monitoring + * Register */ + + struct + { + __IOM uint32_t BPIOG : 1; /*!< [0..0] Buffer Pool Initialization Ongoing */ + __IOM uint32_t BPR : 1; /*!< [1..1] Buffer Pool Ready */ + uint32_t : 30; + } CABPIRM_b; + }; + + union + { + __IM uint32_t CABPPCM; /*!< (@ 0x00000144) Buffer Pool Pointer Count Monitoring Register */ + + struct + { + __IM uint32_t RPC : 13; /*!< [12..0] Remaining Pointer Count */ + uint32_t : 3; + __IM uint32_t TPC : 13; /*!< [28..16] Total Pointer Count */ + uint32_t : 3; + } CABPPCM_b; + }; + + union + { + __IM uint32_t CABPLCM; /*!< (@ 0x00000148) Buffer Pool Pointer Least Count Monitoring Register */ + + struct + { + __IM uint32_t LRC : 13; /*!< [12..0] Least Remaining Pointer Count */ + uint32_t : 19; + } CABPLCM_b; + }; + __IM uint32_t RESERVED6[13]; + + union + { + __IM uint32_t CABPCPM[3]; /*!< (@ 0x00000180) Port [0..2] Buffer Pointer Count Monitoring Register */ + + struct + { + __IM uint32_t RPCP : 13; /*!< [12..0] Received Pointer Count */ + uint32_t : 19; + } CABPCPM_b[3]; + }; + __IM uint32_t RESERVED7[29]; + + union + { + __IM uint32_t CABPMCPM[3]; /*!< (@ 0x00000200) Port [0..2] Buffer Pointer Maximum Count Monitoring + * Register */ + + struct + { + __IM uint32_t RPMCP : 13; /*!< [12..0] Received Pointer Maximum Count */ + uint32_t : 19; + } CABPMCPM_b[3]; + }; + __IM uint32_t RESERVED8[61]; + + union + { + __IM uint32_t CARDNM; /*!< (@ 0x00000300) Rejected Descriptor Number Monitoring Register */ + + struct + { + __IM uint32_t RDNRR : 13; /*!< [12..0] Rejected Descriptor Number in Reject RAM */ + uint32_t : 19; + } CARDNM_b; + }; + + union + { + __IM uint32_t CARDMNM; /*!< (@ 0x00000304) Rejected Descriptor Maximum Number Monitoring + * Register */ + + struct + { + __IM uint32_t RDMNRR : 13; /*!< [12..0] Rejected Descriptor Maximum Number in Reject RAM */ + uint32_t : 19; + } CARDMNM_b; + }; + __IM uint32_t RESERVED9[2]; + + union + { + __IM uint32_t CARDCN; /*!< (@ 0x00000310) Rejected Descriptor Counter Register */ + + struct + { + __IM uint32_t RDN : 32; /*!< [31..0] Rejected Descriptor Number */ + } CARDCN_b; + }; + __IM uint32_t RESERVED10[59]; + + union + { + __IOM uint32_t CAEIS0; /*!< (@ 0x00000400) Error Interrupt Status Register 0 */ + + struct + { + __IOM uint32_t PECCES : 1; /*!< [0..0] Pointer ECC Error Interrupt Status */ + __IOM uint32_t DSECCES : 1; /*!< [1..1] Descriptor ECC Error Interrupt Status */ + __IOM uint32_t BPECCES : 1; /*!< [2..2] Buffer Pool ECC Error Interrupt Status */ + uint32_t : 5; + __IOM uint32_t BPOPS : 1; /*!< [8..8] Buffer Pool Out of Pointer Status */ + __IOM uint32_t WMCLOS : 1; /*!< [9..9] Watermark Critical Level Overtook Status */ + __IOM uint32_t WMFLOS : 1; /*!< [10..10] Watermark Flush Level Overtook Status */ + uint32_t : 5; + __IM uint32_t EEIPLN : 4; /*!< [19..16] ECC Error Inducing Pointer Loss Number */ + uint32_t : 12; + } CAEIS0_b; + }; + + union + { + __IOM uint32_t CAEIE0; /*!< (@ 0x00000404) Error Interrupt Enable Register 0 */ + + struct + { + __IOM uint32_t PECCEE : 1; /*!< [0..0] Pointer ECC Error Interrupt Enable */ + __IOM uint32_t DSECCEE : 1; /*!< [1..1] Descriptor ECC Error Interrupt Enable */ + __IOM uint32_t BPECCEE : 1; /*!< [2..2] Buffer Pool ECC Error Interrupt Enable */ + uint32_t : 5; + __IOM uint32_t BPOPE : 1; /*!< [8..8] Buffer Pool Out of Pointer Enable */ + __IOM uint32_t WMCLOE : 1; /*!< [9..9] Watermark Critical Level Overtook Enable */ + __IOM uint32_t WMFLOE : 1; /*!< [10..10] Watermark Flush Level Overtook Enable */ + uint32_t : 21; + } CAEIE0_b; + }; + + union + { + __IM uint32_t CAEID0; /*!< (@ 0x00000408) Error Interrupt Disable Register 0 */ + + struct + { + __IM uint32_t PECCED : 1; /*!< [0..0] Pointer ECC Error Interrupt Disable */ + __IM uint32_t DSECCED : 1; /*!< [1..1] Descriptor ECC Error Interrupt Disable */ + __IM uint32_t BPECCED : 1; /*!< [2..2] Buffer Pool ECC Error Interrupt Disable */ + uint32_t : 5; + __IM uint32_t BPOPD : 1; /*!< [8..8] Buffer Pool Out of Pointer Disable */ + __IM uint32_t WMCLOD : 1; /*!< [9..9] Watermark Critical Level Overtook Disable */ + __IM uint32_t WMFLOD : 1; /*!< [10..10] Watermark Flush Level Overtook Disable */ + uint32_t : 21; + } CAEID0_b; + }; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t CAEIS1; /*!< (@ 0x00000410) Error Interrupt Status Register 1 */ + + struct + { + __IOM uint32_t PWMCLOS : 7; /*!< [6..0] Port Watermark Critical Level Overtook Status */ + uint32_t : 9; + __IOM uint32_t PWMFLOS : 7; /*!< [22..16] Port Watermark Flush Level Overtook Status */ + uint32_t : 9; + } CAEIS1_b; + }; + + union + { + __IOM uint32_t CAEIE1; /*!< (@ 0x00000414) Error Interrupt Enable Register 1 */ + + struct + { + __IOM uint32_t PWMCLOE : 7; /*!< [6..0] Port Watermark Critical Level Overtook Enable */ + uint32_t : 9; + __IOM uint32_t PWMFLOE : 7; /*!< [22..16] Port Watermark Flush Level Overtook Enable */ + uint32_t : 9; + } CAEIE1_b; + }; + + union + { + __IM uint32_t CAEID1; /*!< (@ 0x00000418) Error Interrupt Disable Register 1 */ + + struct + { + __IM uint32_t PWMCLOD : 7; /*!< [6..0] Port Watermark Critical Level Overtook Disable */ + uint32_t : 9; + __IM uint32_t PWMFLOD : 7; /*!< [22..16] Port Watermark Flush Level Overtook Disable */ + uint32_t : 9; + } CAEID1_b; + }; + __IM uint32_t RESERVED12[9]; + + union + { + __IOM uint32_t CAMIS0; /*!< (@ 0x00000440) Monitoring Interrupt Status Register 0 */ + + struct + { + __IOM uint32_t PFS : 2; /*!< [1..0] Pause Frame Status */ + uint32_t : 30; + } CAMIS0_b; + }; + + union + { + __IOM uint32_t CAMIE0; /*!< (@ 0x00000444) Monitoring Interrupt Enable Register 0 */ + + struct + { + __IOM uint32_t PFE : 2; /*!< [1..0] Pause Frame Enable */ + uint32_t : 30; + } CAMIE0_b; + }; + + union + { + __IM uint32_t CAMID0; /*!< (@ 0x00000448) Monitoring Interrupt Disable Register 0 */ + + struct + { + __IM uint32_t PFD : 2; /*!< [1..0] Pause Frame Disable */ + uint32_t : 30; + } CAMID0_b; + }; + __IM uint32_t RESERVED13; + + union + { + __IOM uint32_t CAMIS1; /*!< (@ 0x00000450) Monitoring Interrupt Status Register 1 */ + + struct + { + __IOM uint32_t PPFS : 14; /*!< [13..0] Port Pause Frame Status */ + uint32_t : 18; + } CAMIS1_b; + }; + + union + { + __IOM uint32_t CAMIE1; /*!< (@ 0x00000454) Monitoring Interrupt Enable Register 1 */ + + struct + { + __IOM uint32_t PPFE : 14; /*!< [13..0] Port Pause Frame Enable */ + uint32_t : 18; + } CAMIE1_b; + }; + + union + { + __IM uint32_t CAMID1; /*!< (@ 0x00000458) Monitoring Interrupt Disable Register 1 */ + + struct + { + __IM uint32_t PPFD : 14; /*!< [13..0] Port Pause Frame Disable */ + uint32_t : 18; + } CAMID1_b; + }; +} R_COMA_Type; /*!< Size = 1116 (0x45c) */ + +/* =========================================================================================================================== */ +/* ================ R_CPU_CTRL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Individual CPU Control (R_CPU_CTRL) + */ + +typedef struct /*!< (@ 0x4000F000) R_CPU_CTRL Structure */ +{ + __IM uint32_t RESERVED[12]; + + union + { + __IOM uint8_t CPU0LCKUPCR; /*!< (@ 0x00000030) CPU0 Lockup Control Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after detection of CPUn lockup */ + uint8_t : 7; + } CPU0LCKUPCR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t CPU1LCKUPCR; /*!< (@ 0x00000034) CPU1 Lockup Control Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after detection of CPUn lockup */ + uint8_t : 7; + } CPU1LCKUPCR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t CPU0INITVTOR; /*!< (@ 0x00000040) CPU0 Initial Vector Base Address Register */ + + struct + { + __IOM uint32_t CPUnINITVTOR : 32; /*!< [31..0] CPUn Initial Vector Base Address */ + } CPU0INITVTOR_b; + }; + + union + { + __IOM uint32_t CPU1INITVTOR; /*!< (@ 0x00000044) CPU1 Initial Vector Base Address Register */ + + struct + { + __IOM uint32_t CPUnINITVTOR : 32; /*!< [31..0] CPUn Initial Vector Base Address */ + } CPU1INITVTOR_b; + }; + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint8_t CPU0WAITCR; /*!< (@ 0x00000050) CPU0 CPUWAIT Control Register */ + + struct + { + __IOM uint8_t CPUWAIT : 1; /*!< [0..0] Writing 1 to stall the CPUn when it is out of reset */ + uint8_t : 7; + } CPU0WAITCR_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + + union + { + __IOM uint8_t CPU1WAITCR; /*!< (@ 0x00000054) CPU1 CPUWAIT Control Register */ + + struct + { + __IOM uint8_t CPUWAIT : 1; /*!< [0..0] Writing 1 to stall the CPUn when it is out of reset */ + uint8_t : 7; + } CPU1WAITCR_b; + }; + __IM uint8_t RESERVED9; + __IM uint16_t RESERVED10; + __IM uint32_t RESERVED11[2]; + + union + { + __IOM uint16_t CPU0ACTCSR; /*!< (@ 0x00000060) CPU0 Activation Control and Status Register */ + + struct + { + __IOM uint16_t ACTREQ : 1; /*!< [0..0] CPUn activation request */ + uint16_t : 6; + __IM uint16_t ACT : 1; /*!< [7..7] CPUn activation state */ + __IOM uint16_t KEY : 8; /*!< [15..8] Key code */ + } CPU0ACTCSR_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t CPU1ACTCSR; /*!< (@ 0x00000064) CPU1 Activation Control and Status Register */ + + struct + { + __IOM uint16_t ACTREQ : 1; /*!< [0..0] CPUn activation request */ + uint16_t : 6; + __IM uint16_t ACT : 1; /*!< [7..7] CPUn activation state */ + __IOM uint16_t KEY : 8; /*!< [15..8] Key code */ + } CPU1ACTCSR_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[2]; + + union + { + __IOM uint8_t CPU0LMECR; /*!< (@ 0x00000070) CPU0 Local Memory Error Control Register */ + + struct + { + __IOM uint8_t SYRSTEN : 1; /*!< [0..0] System Reset request enable */ + uint8_t : 7; + } CPU0LMECR_b; + }; + __IM uint8_t RESERVED15; + __IM uint16_t RESERVED16; + __IM uint32_t RESERVED17; + + union + { + __IOM uint8_t CPUIDR; /*!< (@ 0x00000078) CPU Identification Register */ + + struct + { + __IM uint8_t CPUID : 1; /*!< [0..0] CPU Identification */ + uint8_t : 7; + } CPUIDR_b; + }; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; + __IM uint32_t RESERVED20; + + union + { + __IOM uint8_t CPU0STATM; /*!< (@ 0x00000080) CPU0 Status Monitor Register */ + + struct + { + __IM uint8_t SLEEPING : 1; /*!< [0..0] Sleeping State */ + __IM uint8_t SLEEPDEEP : 1; /*!< [1..1] Indicates that the processor is at a Deep Sleep mode */ + uint8_t : 2; + __IM uint8_t SAHBSTP : 1; /*!< [4..4] S-AHB Status Flag */ + uint8_t : 3; + } CPU0STATM_b; + }; + __IM uint8_t RESERVED21; + __IM uint16_t RESERVED22; + + union + { + __IOM uint8_t CPU1STATM; /*!< (@ 0x00000084) CPU1 Status Monitor Register */ + + struct + { + __IM uint8_t SLEEPING : 1; /*!< [0..0] Sleeping State */ + __IM uint8_t SLEEPDEEP : 1; /*!< [1..1] Indicates that the processor is at a Deep Sleep mode */ + uint8_t : 2; + __IM uint8_t SAHBSTP : 1; /*!< [4..4] S-AHB Status Flag */ + uint8_t : 3; + } CPU1STATM_b; + }; + __IM uint8_t RESERVED23; + __IM uint16_t RESERVED24; + __IM uint32_t RESERVED25[2]; + + union + { + __IOM uint8_t SECEXTMON; /*!< (@ 0x00000090) CPU SECEXT Monitor Register */ + + struct + { + __IM uint8_t SECEXT0 : 1; /*!< [0..0] CPU0 Security Extension */ + __IM uint8_t SECEXT1 : 1; /*!< [1..1] CPU1 Security Extension */ + uint8_t : 6; + } SECEXTMON_b; + }; + __IM uint8_t RESERVED26; + __IM uint16_t RESERVED27; + + union + { + __IOM uint32_t NSCPUCR; /*!< (@ 0x00000094) Non-secure CPU Control Register */ + + struct + { + __IOM uint32_t RSTREQEN : 1; /*!< [0..0] System Reset Request Enable */ + uint32_t : 31; + } NSCPUCR_b; + }; + __IM uint32_t RESERVED28[218]; + + union + { + __IOM uint8_t CPU0LOCKCR; /*!< (@ 0x00000400) CPU0 Function Lock Control Register */ + + struct + { + __IOM uint8_t LCKSVTAIR : 1; /*!< [0..0] Disables writes to secure registers VTOR_S, AIRCR.PRIS, + * AIRCR.BFHFNMINS */ + __IOM uint8_t LCKSMPU : 1; /*!< [1..1] Disables writes to registers that are associated with + * the Secure MPU region */ + __IOM uint8_t LCKSAU : 1; /*!< [2..2] Disables writes to registers that are associated with + * the SAU region */ + __IOM uint8_t LCKITGU : 1; /*!< [3..3] Disables writes to registers that are associated with + * the ITCM interface */ + __IOM uint8_t LCKDTGU : 1; /*!< [4..4] Disables writes to registers that are associated with + * the DTCM interface */ + __IOM uint8_t LCKDCAIC : 1; /*!< [5..5] Disable access to the instruction cache direct cache + * access registers DCAICLR and DCAICRR */ + uint8_t : 2; + } CPU0LOCKCR_b; + }; + __IM uint8_t RESERVED29; + __IM uint16_t RESERVED30; + + union + { + __IOM uint8_t CPU1LOCKCR; /*!< (@ 0x00000404) CPU1 Function Lock Control Register */ + + struct + { + __IOM uint8_t LCKSVTAIR : 1; /*!< [0..0] Disables writes to secure registers VTOR_S, AIRCR.PRIS, + * AIRCR.BFHFNMINS */ + __IOM uint8_t LCKSMPU : 1; /*!< [1..1] Disables writes to registers that are associated with + * the Secure MPU region */ + __IOM uint8_t LCKSAU : 1; /*!< [2..2] Disables writes to registers that are associated with + * the SAU region */ + __IOM uint8_t LCKITGU : 1; /*!< [3..3] Disables writes to registers that are associated with + * the ITCM interface */ + __IOM uint8_t LCKDTGU : 1; /*!< [4..4] Disables writes to registers that are associated with + * the DTCM interface */ + __IOM uint8_t LCKDCAIC : 1; /*!< [5..5] Disable access to the instruction cache direct cache + * access registers DCAICLR and DCAICRR */ + uint8_t : 2; + } CPU1LOCKCR_b; + }; + __IM uint8_t RESERVED31; + __IM uint16_t RESERVED32; + __IM uint32_t RESERVED33[62]; + + union + { + __IOM uint8_t CPU0LOCKCRNS; /*!< (@ 0x00000500) CPU0 Non-secure Function Lock Control Register */ + + struct + { + __IOM uint8_t LCKNSVTOR : 1; /*!< [0..0] Disables writes to the VTOR_NS register */ + __IOM uint8_t LCKNSMPU : 1; /*!< [1..1] Disables writes to registers that are associated with + * the Non-secure MPU region */ + uint8_t : 6; + } CPU0LOCKCRNS_b; + }; + __IM uint8_t RESERVED34; + __IM uint16_t RESERVED35; + + union + { + __IOM uint8_t CPU1LOCKCRNS; /*!< (@ 0x00000504) CPU1 Non-secure Function Lock Control Register */ + + struct + { + __IOM uint8_t LCKNSVTOR : 1; /*!< [0..0] Disables writes to the VTOR_NS register */ + __IOM uint8_t LCKNSMPU : 1; /*!< [1..1] Disables writes to registers that are associated with + * the Non-secure MPU region */ + uint8_t : 6; + } CPU1LOCKCRNS_b; + }; + __IM uint8_t RESERVED36; + __IM uint16_t RESERVED37; + __IM uint32_t RESERVED38[206]; + + union + { + __IOM uint16_t CPU0CRPT; /*!< (@ 0x00000840) CPU0 Control Register Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key to enable/disable writing to PROTECT */ + } CPU0CRPT_b; + }; + __IM uint16_t RESERVED39; + + union + { + __IOM uint16_t CPU1CRPT; /*!< (@ 0x00000844) CPU1 Control Register Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key to enable/disable writing to PROTECT */ + } CPU1CRPT_b; + }; + __IM uint16_t RESERVED40; +} R_CPU_CTRL_Type; /*!< Size = 2120 (0x848) */ + +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CANFD ECC (R_ECCMB0) + */ + +typedef struct /*!< (@ 0x4036F200) R_ECCMB0 Structure */ +{ + union + { + __IOM uint32_t EC710CTL; /*!< (@ 0x00000000) ECC Control Register */ + + struct + { + __IM uint32_t ECEMF : 1; /*!< [0..0] ECC Error Message Flag */ + __IM uint32_t ECER1F : 1; /*!< [1..1] ECC Error Detection and Correction Flag */ + __IM uint32_t ECER2F : 1; /*!< [2..2] 2-bit ECC Error Detection Flag */ + __IOM uint32_t EC1EDIC : 1; /*!< [3..3] ECC 1-bit Error Detection Interrupt Control */ + __IOM uint32_t EC2EDIC : 1; /*!< [4..4] ECC 2-bit Error Detection Interrupt Control */ + __IOM uint32_t EC1ECP : 1; /*!< [5..5] ECC 1-bit Error Correction Permission */ + __IOM uint32_t ECERVF : 1; /*!< [6..6] ECC Error Judgment Enable Flag */ + uint32_t : 2; + __IOM uint32_t ECER1C : 1; /*!< [9..9] Accumulating ECC Error Detection and Correction Flag + * Clear */ + __IOM uint32_t ECER2C : 1; /*!< [10..10] 2-bit ECC Error Detection Flag Clear */ + __IM uint32_t ECOVFF : 1; /*!< [11..11] ECC Overflow Detection Flag */ + uint32_t : 2; + __IOM uint32_t EMCA : 2; /*!< [15..14] Access Control to ECC Mode Select bit */ + __IM uint32_t ECSEDF0 : 1; /*!< [16..16] ECC Single bit Error Address Detection Flag */ + __IM uint32_t ECDEDF0 : 1; /*!< [17..17] ECC Dual Bit Error Address Detection Flag */ + uint32_t : 14; + } EC710CTL_b; + }; + + union + { + __IOM uint16_t EC710TMC; /*!< (@ 0x00000004) ECC Test Mode Control Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ECDCS : 1; /*!< [1..1] ECC Decode Input Select */ + uint16_t : 5; + __IOM uint16_t ECTMCE : 1; /*!< [7..7] ECC Test Mode Control Enable */ + uint16_t : 6; + __IOM uint16_t ETMA : 2; /*!< [15..14] ECC Test Mode Bit Access Control */ + } EC710TMC_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t EC710TED; /*!< (@ 0x0000000C) ECC Test Substitute Data Register */ + + struct + { + __IOM uint32_t ECEDB : 32; /*!< [31..0] ECC Test Substitute Data */ + } EC710TED_b; + }; + + union + { + __IM uint32_t EC710EAD0; /*!< (@ 0x00000010) ECC Error Address Register */ + + struct + { + __IM uint32_t ECEAD : 10; /*!< [9..0] ECC Error Address */ + uint32_t : 22; + } EC710EAD0_b; + }; +} R_ECCMB0_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_ESWM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Layer 3 Ethernet Switch Module (R_ESWM) + */ + +typedef struct /*!< (@ 0x403C8000) R_ESWM Structure */ +{ + union + { + __IOM uint32_t TPEMIMC0; /*!< (@ 0x00000000) Error and Monitoring Interrupt Mapping Configuration + * Register 0 */ + + struct + { + __IOM uint32_t SEIM : 1; /*!< [0..0] Switch Error Interrupt Mapping */ + __IOM uint32_t SEIGM : 1; /*!< [1..1] Switch Error Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t SEICM : 3; /*!< [6..4] Switch Error Interrupt Core Mapping */ + uint32_t : 9; + __IOM uint32_t SSIM0 : 1; /*!< [16..16] Switch Status Interrupt 0 Mapping */ + __IOM uint32_t SSIGM0 : 1; /*!< [17..17] Switch Status Interrupt 0 GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t SSICM0 : 3; /*!< [22..20] Switch Status Interrupt 0 Core Mapping */ + uint32_t : 1; + __IOM uint32_t SSIM1 : 1; /*!< [24..24] Switch Status Interrupt 1 Mapping */ + __IOM uint32_t SSIGM1 : 1; /*!< [25..25] Switch Status Interrupt 1 GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t SSICM1 : 3; /*!< [30..28] Switch Status Interrupt 1 Core Mapping */ + uint32_t : 1; + } TPEMIMC0_b; + }; + + union + { + __IOM uint32_t TPEMIMC1; /*!< (@ 0x00000004) Error and Monitoring Interrupt Mapping Configuration + * Register 1 */ + + struct + { + __IOM uint32_t FEIM : 1; /*!< [0..0] MFWD Error Interrupt Mapping */ + __IOM uint32_t FEIGM : 1; /*!< [1..1] MFWD Error Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t FEICM : 3; /*!< [6..4] MFWD Error Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t FSIM : 1; /*!< [8..8] MFWD Status Interrupt Mapping */ + __IOM uint32_t FSIGM : 1; /*!< [9..9] MFWD Status Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t FSICM : 3; /*!< [14..12] MFWD Status Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t CEIM : 1; /*!< [16..16] COMA Error Interrupt Mapping */ + __IOM uint32_t CEIGM : 1; /*!< [17..17] COMA Error Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t CEICM : 3; /*!< [22..20] COMA Error Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t CSIM : 1; /*!< [24..24] COMA Status Interrupt Mapping */ + __IOM uint32_t CSIGM : 1; /*!< [25..25] COMA Status Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t CSICM : 3; /*!< [30..28] COMA Status Interrupt Core Mapping */ + uint32_t : 1; + } TPEMIMC1_b; + }; + + union + { + __IOM uint32_t TPEMIMC2; /*!< (@ 0x00000008) Error and Monitoring Interrupt Mapping Configuration + * Register 2 */ + + struct + { + __IOM uint32_t GEIM0 : 1; /*!< [0..0] GWCA0 Error Interrupt Mapping */ + __IOM uint32_t GEIGM0 : 1; /*!< [1..1] GWCA0 Error Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t GEICM0 : 3; /*!< [6..4] GWCA0 Error Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t GSIM0 : 1; /*!< [8..8] GWCA0 Status Interrupt Mapping */ + __IOM uint32_t GSIGM0 : 1; /*!< [9..9] GWCA0 Status Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t GSICM0 : 3; /*!< [14..12] GWCA0 Status Interrupt Core Mapping */ + uint32_t : 17; + } TPEMIMC2_b; + }; + + union + { + __IOM uint32_t TPEMIMC3; /*!< (@ 0x0000000C) Error and Monitoring Interrupt Mapping Configuration + * Register 3 */ + + struct + { + __IOM uint32_t EEIM0 : 1; /*!< [0..0] ETHA0 Error Interrupt Mapping */ + __IOM uint32_t EEIGM0 : 1; /*!< [1..1] ETHA0 Error Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t EEICM0 : 3; /*!< [6..4] ETHA0 Error Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t ESIM0 : 1; /*!< [8..8] ETHA0 Status Interrupt Mapping */ + __IOM uint32_t ESIGM0 : 1; /*!< [9..9] ETHA0 Status Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t ESICM0 : 3; /*!< [14..12] ETHA0 Status Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t RSIM0 : 1; /*!< [16..16] RMAC0 Status Interrupt Mapping */ + __IOM uint32_t RSIGM0 : 1; /*!< [17..17] RMAC0 Status Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t RSICM0 : 3; /*!< [22..20] RMAC0 Status Interrupt Core Mapping */ + uint32_t : 9; + } TPEMIMC3_b; + }; + + union + { + __IOM uint32_t TPEMIMC4; /*!< (@ 0x00000010) Error and Monitoring Interrupt Mapping Configuration + * Register 4 */ + + struct + { + __IOM uint32_t EEIM1 : 1; /*!< [0..0] ETHA1 Error Interrupt Mapping */ + __IOM uint32_t EEIGM1 : 1; /*!< [1..1] ETHA1 Error Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t EEICM1 : 3; /*!< [6..4] ETHA1 Error Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t ESIM1 : 1; /*!< [8..8] ETHA1 Status Interrupt Mapping */ + __IOM uint32_t ESIGM1 : 1; /*!< [9..9] ETHA1 Status Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t ESICM1 : 3; /*!< [14..12] ETHA1 Status Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t RSIM1 : 1; /*!< [16..16] RMAC1 Status Interrupt Mapping */ + __IOM uint32_t RSIGM1 : 1; /*!< [17..17] RMAC1 Status Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t RSICM1 : 3; /*!< [22..20] RMAC1 Status Interrupt Core Mapping */ + uint32_t : 9; + } TPEMIMC4_b; + }; + __IM uint32_t RESERVED[27]; + + union + { + __IOM uint32_t TPEMIMC60; /*!< (@ 0x00000080) Error and Monitoring Interrupt Mapping Configuration + * Register 60 */ + + struct + { + __IOM uint32_t GTSIM0 : 1; /*!< [0..0] GWCA0 Timestamp Interrupt Mapping */ + __IOM uint32_t GTSICM0 : 3; /*!< [3..1] GWCA0 Timestamp Interrupt Core Mapping */ + uint32_t : 28; + } TPEMIMC60_b; + }; + + union + { + __IOM uint32_t TPEMIMC61; /*!< (@ 0x00000084) Error and Monitoring Interrupt Mapping Configuration + * Register 61 */ + + struct + { + __IOM uint32_t GTSIM0 : 1; /*!< [0..0] GWCA0 Timestamp Interrupt Mapping */ + __IOM uint32_t GTSICM0 : 3; /*!< [3..1] GWCA0 Timestamp Interrupt Core Mapping */ + uint32_t : 28; + } TPEMIMC61_b; + }; + + union + { + __IOM uint32_t TPEMIMC62; /*!< (@ 0x00000088) Error and Monitoring Interrupt Mapping Configuration + * Register 62 */ + + struct + { + __IOM uint32_t GTSIM0 : 1; /*!< [0..0] GWCA0 Timestamp Interrupt Mapping */ + __IOM uint32_t GTSICM0 : 3; /*!< [3..1] GWCA0 Timestamp Interrupt Core Mapping */ + uint32_t : 28; + } TPEMIMC62_b; + }; + + union + { + __IOM uint32_t TPEMIMC63; /*!< (@ 0x0000008C) Error and Monitoring Interrupt Mapping Configuration + * Register 63 */ + + struct + { + __IOM uint32_t GTSIM0 : 1; /*!< [0..0] GWCA0 Timestamp Interrupt Mapping */ + __IOM uint32_t GTSICM0 : 3; /*!< [3..1] GWCA0 Timestamp Interrupt Core Mapping */ + uint32_t : 28; + } TPEMIMC63_b; + }; + + union + { + __IOM uint32_t TPEMIMC64; /*!< (@ 0x00000090) Error and Monitoring Interrupt Mapping Configuration + * Register 64 */ + + struct + { + __IOM uint32_t GTSIM0 : 1; /*!< [0..0] GWCA0 Timestamp Interrupt Mapping */ + __IOM uint32_t GTSICM0 : 3; /*!< [3..1] GWCA0 Timestamp Interrupt Core Mapping */ + uint32_t : 28; + } TPEMIMC64_b; + }; + __IM uint32_t RESERVED1[27]; + + union + { + __IOM uint32_t TPEMIMC70; /*!< (@ 0x00000100) Error and Monitoring Interrupt Mapping Configuration + * Register 70 */ + + struct + { + __IOM uint32_t GDICM0 : 3; /*!< [2..0] GWCA0 Data Interrupt Core Mapping */ + uint32_t : 29; + } TPEMIMC70_b; + }; + + union + { + __IOM uint32_t TPEMIMC71; /*!< (@ 0x00000104) Error and Monitoring Interrupt Mapping Configuration + * Register 71 */ + + struct + { + __IOM uint32_t GDICM0 : 3; /*!< [2..0] GWCA0 Data Interrupt Core Mapping */ + uint32_t : 29; + } TPEMIMC71_b; + }; + + union + { + __IOM uint32_t TPEMIMC72; /*!< (@ 0x00000108) Error and Monitoring Interrupt Mapping Configuration + * Register 72 */ + + struct + { + __IOM uint32_t GDICM0 : 3; /*!< [2..0] GWCA0 Data Interrupt Core Mapping */ + uint32_t : 29; + } TPEMIMC72_b; + }; + + union + { + __IOM uint32_t TPEMIMC73; /*!< (@ 0x0000010C) Error and Monitoring Interrupt Mapping Configuration + * Register 73 */ + + struct + { + __IOM uint32_t GDICM0 : 3; /*!< [2..0] GWCA0 Data Interrupt Core Mapping */ + uint32_t : 29; + } TPEMIMC73_b; + }; + + union + { + __IOM uint32_t TPEMIMC74; /*!< (@ 0x00000110) Error and Monitoring Interrupt Mapping Configuration + * Register 74 */ + + struct + { + __IOM uint32_t GDICM0 : 3; /*!< [2..0] GWCA0 Data Interrupt Core Mapping */ + uint32_t : 29; + } TPEMIMC74_b; + }; + __IM uint32_t RESERVED2[379]; + + union + { + __IM uint32_t TSIM; /*!< (@ 0x00000700) Summarized Interrupt Mirroring Register */ + + struct + { + __IM uint32_t FIM : 1; /*!< [0..0] MFWD Interrupt Mirroring */ + __IM uint32_t CIM : 1; /*!< [1..1] COMA Interrupt Mirroring */ + __IM uint32_t GIM0 : 1; /*!< [2..2] GWCA0 Interrupt Monitoring */ + __IM uint32_t GIM1 : 1; /*!< [3..3] GWCA1 Interrupt Monitoring */ + __IM uint32_t EIM0 : 1; /*!< [4..4] ETHA0 Interrupt Monitoring */ + __IM uint32_t EIM1 : 1; /*!< [5..5] ETHA1 Interrupt Monitoring */ + __IM uint32_t EIM2 : 1; /*!< [6..6] ETHA2 Interrupt Monitoring */ + uint32_t : 25; + } TSIM_b; + }; + + union + { + __IM uint32_t TFIM; /*!< (@ 0x00000704) MFWD Interrupt Mirroring Register */ + + struct + { + __IM uint32_t FWEISIM0 : 1; /*!< [0..0] FWEIS0 Interrupt Mirroring */ + __IM uint32_t FWEISIM1 : 1; /*!< [1..1] FWEIS1 Interrupt Mirroring */ + __IM uint32_t FWEISIM2 : 1; /*!< [2..2] FWEIS2 Interrupt Mirroring */ + __IM uint32_t FWEISIM3 : 1; /*!< [3..3] FWEIS3 Interrupt Mirroring */ + __IM uint32_t FWEISIM4 : 1; /*!< [4..4] FWEIS4 Interrupt Mirroring */ + __IM uint32_t FWEISIM5 : 1; /*!< [5..5] FWEIS5 Interrupt Mirroring */ + __IM uint32_t FWEISIM6 : 1; /*!< [6..6] FWEIS6 Interrupt Mirroring */ + __IM uint32_t FWEISIM7 : 1; /*!< [7..7] FWEIS7 Interrupt Mirroring */ + __IM uint32_t FWEISIM8 : 1; /*!< [8..8] FWEIS8 Interrupt Mirroring */ + __IM uint32_t FWMISIM0 : 1; /*!< [9..9] FWMIS0 Interrupt Mirroring */ + uint32_t : 22; + } TFIM_b; + }; + + union + { + __IM uint32_t TCIM; /*!< (@ 0x00000708) COMA Interrupt Mirroring Register */ + + struct + { + __IM uint32_t RSSISIM : 1; /*!< [0..0] RSSIS Interrupt Mirroring */ + __IM uint32_t CAEISIM0 : 1; /*!< [1..1] CAEIS0 Interrupt Mirroring */ + __IM uint32_t CAEISIM1 : 1; /*!< [2..2] CAEIS1 Interrupt Mirroring */ + __IM uint32_t CAMISIM0 : 1; /*!< [3..3] CAMIS0 Interrupt Mirroring */ + __IM uint32_t CAMISIM1 : 1; /*!< [4..4] CAMIS1 Interrupt Mirroring */ + uint32_t : 27; + } TCIM_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IM uint32_t TGIM0; /*!< (@ 0x00000710) GWCA0 Interrupt Mirroring Register */ + + struct + { + __IM uint32_t GWDISIM : 1; /*!< [0..0] GWDIS Interrupt Mirroring */ + __IM uint32_t GWTSDISIM : 1; /*!< [1..1] GWTSDIS Interrupt Mirroring */ + __IM uint32_t GWEISIM0 : 1; /*!< [2..2] GWEIS0 Interrupt Mirroring */ + __IM uint32_t GWEISIM1 : 1; /*!< [3..3] GWEIS1 Interrupt Mirroring */ + __IM uint32_t GWEISIM2 : 1; /*!< [4..4] GWEIS2 Interrupt Mirroring */ + __IM uint32_t GWEISIM3 : 1; /*!< [5..5] GWEIS3 Interrupt Mirroring */ + __IM uint32_t GWEISIM4 : 1; /*!< [6..6] GWEIS4 Interrupt Mirroring */ + __IM uint32_t GWEISIM5 : 1; /*!< [7..7] GWEIS5 Interrupt Mirroring */ + uint32_t : 24; + } TGIM0_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IM uint32_t TEIM0; /*!< (@ 0x00000720) ETHA0 Interrupt Mirroring Register */ + + struct + { + __IM uint32_t EAEISIM0 : 1; /*!< [0..0] EAEIS0 Interrupt Mirroring */ + __IM uint32_t EAEISIM1 : 1; /*!< [1..1] EAEIS1 Interrupt Mirroring */ + __IM uint32_t EAEISIM2 : 1; /*!< [2..2] EAEIS2 Interrupt Mirroring */ + __IM uint32_t MEISIM : 1; /*!< [3..3] MEIS Interrupt Mirroring */ + __IM uint32_t MMISIM : 1; /*!< [4..4] MMIS0 Interrupt Mirroring */ + uint32_t : 27; + } TEIM0_b; + }; + + union + { + __IM uint32_t TEIM1; /*!< (@ 0x00000724) ETHA1 Interrupt Mirroring Register */ + + struct + { + __IM uint32_t EAEISIM0 : 1; /*!< [0..0] EAEIS0 Interrupt Mirroring */ + __IM uint32_t EAEISIM1 : 1; /*!< [1..1] EAEIS1 Interrupt Mirroring */ + __IM uint32_t EAEISIM2 : 1; /*!< [2..2] EAEIS2 Interrupt Mirroring */ + __IM uint32_t MEISIM : 1; /*!< [3..3] MEIS Interrupt Mirroring */ + __IM uint32_t MMISIM : 1; /*!< [4..4] MMIS0 Interrupt Mirroring */ + uint32_t : 27; + } TEIM1_b; + }; + __IM uint32_t RESERVED5[25398]; + + union + { + __IOM uint32_t MIIRR; /*!< (@ 0x00019400) Media Interface Reset Register */ + + struct + { + __IOM uint32_t RGRST0 : 1; /*!< [0..0] RGMII0 Interface Reset */ + __IOM uint32_t RGRST1 : 1; /*!< [1..1] RGMII1 Interface Reset */ + uint32_t : 6; + __IOM uint32_t RMRST0 : 1; /*!< [8..8] RMII0 Interface Reset */ + __IOM uint32_t RMRST1 : 1; /*!< [9..9] RMII1 Interface Reset */ + uint32_t : 22; + } MIIRR_b; + }; + + union + { + __IOM uint32_t MIICR0; /*!< (@ 0x00019404) Media Interface Control Register 0 */ + + struct + { + __IOM uint32_t MIISEL : 2; /*!< [1..0] MII Select */ + uint32_t : 6; + __IOM uint32_t DIVSTP : 1; /*!< [8..8] Clock Divider Stop */ + uint32_t : 3; + __IOM uint32_t TXCIDE : 1; /*!< [12..12] TXC Internal Delay Enable in RGMII */ + uint32_t : 19; + } MIICR0_b; + }; + + union + { + __IOM uint32_t MIICR1; /*!< (@ 0x00019408) Media Interface Control Register 1 */ + + struct + { + __IOM uint32_t MIISEL : 2; /*!< [1..0] MII Select */ + uint32_t : 6; + __IOM uint32_t DIVSTP : 1; /*!< [8..8] Clock Divider Stop */ + uint32_t : 3; + __IOM uint32_t TXCIDE : 1; /*!< [12..12] TXC Internal Delay Enable in RGMII */ + uint32_t : 19; + } MIICR1_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t MCCESR; /*!< (@ 0x00019410) Media Clock Capture Event Select Register */ + + struct + { + __IOM uint32_t MCCES0 : 1; /*!< [0..0] Media Clock Capture Event Select 0 */ + __IOM uint32_t MCCES1 : 1; /*!< [1..1] Media Clock Capture Event Select 1 */ + uint32_t : 30; + } MCCESR_b; + }; + __IM uint32_t RESERVED7[3]; + + union + { + __IOM uint32_t TASSTSR; /*!< (@ 0x00019420) TAS Status Monitor Signal Select Register */ + + struct + { + __IOM uint32_t MSS0 : 5; /*!< [4..0] Select signal to output ET_TAS_STA pin from race_etha0_tas_gate_state[8 + * 0] and race_etha1_tas_gate_state[8:0] */ + uint32_t : 3; + __IOM uint32_t MSS1 : 5; /*!< [12..8] Select signal to output ET_TAS_STA pin from race_etha0_tas_gate_state[ + * :0] and race_etha1_tas_gate_state[8:0] */ + uint32_t : 3; + __IOM uint32_t MSS2 : 5; /*!< [20..16] Select signal to output ET_TAS_STA pin from race_etha0_tas_gate_state + * 8:0] and race_etha1_tas_gate_state[8:0] */ + uint32_t : 3; + __IOM uint32_t MSS3 : 5; /*!< [28..24] Select signal to output ET_TAS_STA pin from race_etha0_tas_gate_state + * 8:0] and race_etha1_tas_gate_state[8:0] */ + uint32_t : 3; + } TASSTSR_b; + }; +} R_ESWM_Type; /*!< Size = 103460 (0x19424) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHA0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet Agent (R_ETHA0) + */ + +typedef struct /*!< (@ 0x403CA000) R_ETHA0 Structure */ +{ + union + { + __IOM uint32_t EAMC; /*!< (@ 0x00000000) Ethernet Agent Mode Configuration Register (EAMC) */ + + struct + { + __IOM uint32_t OPC : 2; /*!< [1..0] OPC */ + uint32_t : 30; + } EAMC_b; + }; + + union + { + __IOM uint32_t EAMS; /*!< (@ 0x00000004) Ethernet Agent Mode Status Register (EAMS) */ + + struct + { + __IOM uint32_t OPS : 2; /*!< [1..0] OPS */ + uint32_t : 30; + } EAMS_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t EAIRC; /*!< (@ 0x00000010) Ethernet Agent IPV Remapping Configuration Register + * [802.1Q] (EAIRC) */ + + struct + { + __IOM uint32_t IPVR0 : 3; /*!< [2..0] IPVR0 */ + uint32_t : 1; + __IOM uint32_t IPVR1 : 3; /*!< [6..4] IPVR1 */ + uint32_t : 1; + __IOM uint32_t IPVR2 : 3; /*!< [10..8] IPVR2 */ + uint32_t : 1; + __IOM uint32_t IPVR3 : 3; /*!< [14..12] IPVR3 */ + uint32_t : 1; + __IOM uint32_t IPVR4 : 3; /*!< [18..16] IPVR4 */ + uint32_t : 1; + __IOM uint32_t IPVR5 : 3; /*!< [22..20] IPVR5 */ + uint32_t : 1; + __IOM uint32_t IPVR6 : 3; /*!< [26..24] IPVR6 */ + uint32_t : 1; + __IOM uint32_t IPVR7 : 3; /*!< [30..28] IPVR7 */ + uint32_t : 1; + } EAIRC_b; + }; + + union + { + __IOM uint32_t EATDQSC; /*!< (@ 0x00000014) Ethernet Agent TX Descriptor Queue Security Configuration + * Register (EATDQSC) */ + + struct + { + __IOM uint32_t TDQSL0 : 1; /*!< [0..0] TDQSL0 */ + __IOM uint32_t TDQSL1 : 1; /*!< [1..1] TDQSL1 */ + __IOM uint32_t TDQSL2 : 1; /*!< [2..2] TDQSL2 */ + __IOM uint32_t TDQSL3 : 1; /*!< [3..3] TDQSL3 */ + __IOM uint32_t TDQSL4 : 1; /*!< [4..4] TDQSL4 */ + __IOM uint32_t TDQSL5 : 1; /*!< [5..5] TDQSL5 */ + __IOM uint32_t TDQSL6 : 1; /*!< [6..6] TDQSL6 */ + __IOM uint32_t TDQSL7 : 1; /*!< [7..7] TDQSL7 */ + uint32_t : 24; + } EATDQSC_b; + }; + + union + { + __IOM uint32_t EATDQC; /*!< (@ 0x00000018) Ethernet Agent TX Descriptor Queue Configuration + * Register (EATDQC) */ + + struct + { + __IOM uint32_t TDQD0 : 1; /*!< [0..0] TDQD0 */ + __IOM uint32_t TDQD1 : 1; /*!< [1..1] TDQD1 */ + __IOM uint32_t TDQD2 : 1; /*!< [2..2] TDQD2 */ + __IOM uint32_t TDQD3 : 1; /*!< [3..3] TDQD3 */ + __IOM uint32_t TDQD4 : 1; /*!< [4..4] TDQD4 */ + __IOM uint32_t TDQD5 : 1; /*!< [5..5] TDQD5 */ + __IOM uint32_t TDQD6 : 1; /*!< [6..6] TDQD6 */ + __IOM uint32_t TDQD7 : 1; /*!< [7..7] TDQD7 */ + __IOM uint32_t TCTDQD : 1; /*!< [8..8] TCTDQD */ + uint32_t : 7; + __IOM uint32_t TDQP0 : 1; /*!< [16..16] TDQP0 */ + __IOM uint32_t TDQP1 : 1; /*!< [17..17] TDQP1 */ + __IOM uint32_t TDQP2 : 1; /*!< [18..18] TDQP2 */ + __IOM uint32_t TDQP3 : 1; /*!< [19..19] TDQP3 */ + __IOM uint32_t TDQP4 : 1; /*!< [20..20] TDQP4 */ + __IOM uint32_t TDQP5 : 1; /*!< [21..21] TDQP5 */ + __IOM uint32_t TDQP6 : 1; /*!< [22..22] TDQP6 */ + __IOM uint32_t TDQP7 : 1; /*!< [23..23] TDQP7 */ + uint32_t : 8; + } EATDQC_b; + }; + + union + { + __IOM uint32_t EATDQAC; /*!< (@ 0x0000001C) Ethernet Agent TX Descriptor Queue Arbitration + * Configuration Register (EATDQAC) */ + + struct + { + __IOM uint32_t TDQA0 : 4; /*!< [3..0] TDQA0 */ + __IOM uint32_t TDQA1 : 4; /*!< [7..4] TDQA1 */ + __IOM uint32_t TDQA2 : 4; /*!< [11..8] TDQA2 */ + __IOM uint32_t TDQA3 : 4; /*!< [15..12] TDQA3 */ + __IOM uint32_t TDQA4 : 4; /*!< [19..16] TDQA4 */ + __IOM uint32_t TDQA5 : 4; /*!< [23..20] TDQA5 */ + __IOM uint32_t TDQA6 : 4; /*!< [27..24] TDQA6 */ + __IOM uint32_t TDQA7 : 4; /*!< [31..28] TDQA7 */ + } EATDQAC_b; + }; + + union + { + __IOM uint32_t EATPEC; /*!< (@ 0x00000020) Ethernet Agent TX Pre-Emption Configuration Register + * (EATPEC) */ + + struct + { + __IOM uint32_t TTQ0 : 1; /*!< [0..0] TTQ0 */ + __IOM uint32_t TTQ1 : 1; /*!< [1..1] TTQ1 */ + __IOM uint32_t TTQ2 : 1; /*!< [2..2] TTQ2 */ + __IOM uint32_t TTQ3 : 1; /*!< [3..3] TTQ3 */ + __IOM uint32_t TTQ4 : 1; /*!< [4..4] TTQ4 */ + __IOM uint32_t TTQ5 : 1; /*!< [5..5] TTQ5 */ + __IOM uint32_t TTQ6 : 1; /*!< [6..6] TTQ6 */ + __IOM uint32_t TTQ7 : 1; /*!< [7..7] TTQ7 */ + __IOM uint32_t TTQ8 : 1; /*!< [8..8] TTQ8 */ + __IOM uint32_t TTQ9 : 1; /*!< [9..9] TTQ9 */ + uint32_t : 6; + __IOM uint32_t AFS : 2; /*!< [17..16] AFS */ + uint32_t : 14; + } EATPEC_b; + }; + __IM uint32_t RESERVED1[7]; + + union + { + __IOM uint32_t EATMFSC0; /*!< (@ 0x00000040) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC0_b; + }; + + union + { + __IOM uint32_t EATMFSC1; /*!< (@ 0x00000044) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC1_b; + }; + + union + { + __IOM uint32_t EATMFSC2; /*!< (@ 0x00000048) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC2_b; + }; + + union + { + __IOM uint32_t EATMFSC3; /*!< (@ 0x0000004C) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC3_b; + }; + + union + { + __IOM uint32_t EATMFSC4; /*!< (@ 0x00000050) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC4_b; + }; + + union + { + __IOM uint32_t EATMFSC5; /*!< (@ 0x00000054) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC5_b; + }; + + union + { + __IOM uint32_t EATMFSC6; /*!< (@ 0x00000058) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC6_b; + }; + + union + { + __IOM uint32_t EATMFSC7; /*!< (@ 0x0000005C) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC7_b; + }; + + union + { + __IOM uint32_t EATDQDC0; /*!< (@ 0x00000060) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC0_b; + }; + + union + { + __IOM uint32_t EATDQDC1; /*!< (@ 0x00000064) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC1_b; + }; + + union + { + __IOM uint32_t EATDQDC2; /*!< (@ 0x00000068) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC2_b; + }; + + union + { + __IOM uint32_t EATDQDC3; /*!< (@ 0x0000006C) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC3_b; + }; + + union + { + __IOM uint32_t EATDQDC4; /*!< (@ 0x00000070) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC4_b; + }; + + union + { + __IOM uint32_t EATDQDC5; /*!< (@ 0x00000074) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC5_b; + }; + + union + { + __IOM uint32_t EATDQDC6; /*!< (@ 0x00000078) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC6_b; + }; + + union + { + __IOM uint32_t EATDQDC7; /*!< (@ 0x0000007C) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC7_b; + }; + + union + { + __IOM uint32_t EATDQM0; /*!< (@ 0x00000080) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM0_b; + }; + + union + { + __IOM uint32_t EATDQM1; /*!< (@ 0x00000084) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM1_b; + }; + + union + { + __IOM uint32_t EATDQM2; /*!< (@ 0x00000088) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM2_b; + }; + + union + { + __IOM uint32_t EATDQM3; /*!< (@ 0x0000008C) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM3_b; + }; + + union + { + __IOM uint32_t EATDQM4; /*!< (@ 0x00000090) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM4_b; + }; + + union + { + __IOM uint32_t EATDQM5; /*!< (@ 0x00000094) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM5_b; + }; + + union + { + __IOM uint32_t EATDQM6; /*!< (@ 0x00000098) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM6_b; + }; + + union + { + __IOM uint32_t EATDQM7; /*!< (@ 0x0000009C) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM7_b; + }; + + union + { + __IOM uint32_t EATDQMLM0; /*!< (@ 0x000000A0) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM0_b; + }; + + union + { + __IOM uint32_t EATDQMLM1; /*!< (@ 0x000000A4) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM1_b; + }; + + union + { + __IOM uint32_t EATDQMLM2; /*!< (@ 0x000000A8) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM2_b; + }; + + union + { + __IOM uint32_t EATDQMLM3; /*!< (@ 0x000000AC) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM3_b; + }; + + union + { + __IOM uint32_t EATDQMLM4; /*!< (@ 0x000000B0) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM4_b; + }; + + union + { + __IOM uint32_t EATDQMLM5; /*!< (@ 0x000000B4) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM5_b; + }; + + union + { + __IOM uint32_t EATDQMLM6; /*!< (@ 0x000000B8) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM6_b; + }; + + union + { + __IOM uint32_t EATDQMLM7; /*!< (@ 0x000000BC) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM7_b; + }; + __IM uint32_t RESERVED2[16]; + + union + { + __IOM uint32_t EACTQC; /*!< (@ 0x00000100) Ethernet Agent Cut-Through Queue Configuration + * Register (EACTQC) */ + + struct + { + __IOM uint32_t CTQD : 16; /*!< [15..0] CTQD */ + uint32_t : 16; + } EACTQC_b; + }; + + union + { + __IOM uint32_t EACTDQDC; /*!< (@ 0x00000104) Ethernet Agent Cut-Through Descriptor Queue Depth + * Configuration Register (EACTDQDC) */ + + struct + { + __IOM uint32_t CTDQD : 4; /*!< [3..0] CTDQD */ + uint32_t : 28; + } EACTDQDC_b; + }; + + union + { + __IOM uint32_t EACTDQM; /*!< (@ 0x00000108) Ethernet Agent Cut-Through Descriptor Queue Monitoring + * Register (EACTDQM) */ + + struct + { + __IOM uint32_t CTQDN : 10; /*!< [9..0] CTQDN */ + uint32_t : 22; + } EACTDQM_b; + }; + + union + { + __IOM uint32_t EACTDQMLM; /*!< (@ 0x0000010C) Ethernet Agent Cut-Through Descriptor Queue Max + * Level Monitoring Register (EACTDQMLM) */ + + struct + { + __IOM uint32_t CTDMLQ : 4; /*!< [3..0] CTDMLQ */ + uint32_t : 28; + } EACTDQMLM_b; + }; + __IM uint32_t RESERVED3[8]; + + union + { + __IOM uint32_t EAVCC; /*!< (@ 0x00000130) Ethernet Agent VLAN Control Configuration Register + * (EAVCC) */ + + struct + { + __IOM uint32_t VIM : 1; /*!< [0..0] VIM */ + uint32_t : 15; + __IOM uint32_t VEM : 3; /*!< [18..16] VEM */ + uint32_t : 13; + } EAVCC_b; + }; + + union + { + __IOM uint32_t EAVTC; /*!< (@ 0x00000134) Ethernet Agent VLAN TAG Configuration Register + * (EAVTC) */ + + struct + { + __IOM uint32_t CTV : 12; /*!< [11..0] CTV */ + __IOM uint32_t CTP : 3; /*!< [14..12] CTP */ + __IOM uint32_t CTD : 1; /*!< [15..15] CTD */ + __IOM uint32_t STV : 12; /*!< [27..16] STV */ + __IOM uint32_t STP : 3; /*!< [30..28] STP */ + __IOM uint32_t STD : 1; /*!< [31..31] STD */ + } EAVTC_b; + }; + + union + { + __IOM uint32_t EARTFC; /*!< (@ 0x00000138) Ethernet Agent Reception TAG Filtering Configuration + * Register (EARTFC) */ + + struct + { + __IOM uint32_t NT : 1; /*!< [0..0] NT */ + __IOM uint32_t RT : 1; /*!< [1..1] RT */ + __IOM uint32_t CST : 1; /*!< [2..2] CST */ + __IOM uint32_t CSRT : 1; /*!< [3..3] CSRT */ + __IOM uint32_t CT : 1; /*!< [4..4] CT */ + __IOM uint32_t CRT : 1; /*!< [5..5] CRT */ + __IOM uint32_t SCT : 1; /*!< [6..6] SCT */ + __IOM uint32_t SCRT : 1; /*!< [7..7] SCRT */ + __IOM uint32_t UT : 1; /*!< [8..8] UT */ + uint32_t : 23; + } EARTFC_b; + }; + __IM uint32_t RESERVED4[49]; + + union + { + __IOM uint32_t EACAEC; /*!< (@ 0x00000200) Ethernet Agent CBS Admin Enable Configuration + * Register (EACAEC) */ + + struct + { + __IOM uint32_t CE0 : 1; /*!< [0..0] CE0 */ + __IOM uint32_t CE1 : 1; /*!< [1..1] CE1 */ + __IOM uint32_t CE2 : 1; /*!< [2..2] CE2 */ + __IOM uint32_t CE3 : 1; /*!< [3..3] CE3 */ + __IOM uint32_t CE4 : 1; /*!< [4..4] CE4 */ + __IOM uint32_t CE5 : 1; /*!< [5..5] CE5 */ + __IOM uint32_t CE6 : 1; /*!< [6..6] CE6 */ + __IOM uint32_t CE7 : 1; /*!< [7..7] CE7 */ + uint32_t : 24; + } EACAEC_b; + }; + + union + { + __IOM uint32_t EACC; /*!< (@ 0x00000204) Ethernet Agent CBS Configuration Register (EACC) */ + + struct + { + __IOM uint32_t CC0 : 1; /*!< [0..0] CC0 */ + __IOM uint32_t CC1 : 1; /*!< [1..1] CC1 */ + __IOM uint32_t CC2 : 1; /*!< [2..2] CC2 */ + __IOM uint32_t CC3 : 1; /*!< [3..3] CC3 */ + __IOM uint32_t CC4 : 1; /*!< [4..4] CC4 */ + __IOM uint32_t CC5 : 1; /*!< [5..5] CC5 */ + __IOM uint32_t CC6 : 1; /*!< [6..6] CC6 */ + __IOM uint32_t CC7 : 1; /*!< [7..7] CC7 */ + uint32_t : 24; + } EACC_b; + }; + __IM uint32_t RESERVED5[6]; + + union + { + __IOM uint32_t EACAIVC0; /*!< (@ 0x00000220) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC0_b; + }; + + union + { + __IOM uint32_t EACAIVC1; /*!< (@ 0x00000224) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC1_b; + }; + + union + { + __IOM uint32_t EACAIVC2; /*!< (@ 0x00000228) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC2_b; + }; + + union + { + __IOM uint32_t EACAIVC3; /*!< (@ 0x0000022C) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC3_b; + }; + + union + { + __IOM uint32_t EACAIVC4; /*!< (@ 0x00000230) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC4_b; + }; + + union + { + __IOM uint32_t EACAIVC5; /*!< (@ 0x00000234) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC5_b; + }; + + union + { + __IOM uint32_t EACAIVC6; /*!< (@ 0x00000238) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC6_b; + }; + + union + { + __IOM uint32_t EACAIVC7; /*!< (@ 0x0000023C) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC7_b; + }; + + union + { + __IOM uint32_t EACAULC0; /*!< (@ 0x00000240) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC0_b; + }; + + union + { + __IOM uint32_t EACAULC1; /*!< (@ 0x00000244) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC1_b; + }; + + union + { + __IOM uint32_t EACAULC2; /*!< (@ 0x00000248) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC2_b; + }; + + union + { + __IOM uint32_t EACAULC3; /*!< (@ 0x0000024C) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC3_b; + }; + + union + { + __IOM uint32_t EACAULC4; /*!< (@ 0x00000250) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC4_b; + }; + + union + { + __IOM uint32_t EACAULC5; /*!< (@ 0x00000254) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC5_b; + }; + + union + { + __IOM uint32_t EACAULC6; /*!< (@ 0x00000258) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC6_b; + }; + + union + { + __IOM uint32_t EACAULC7; /*!< (@ 0x0000025C) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC7_b; + }; + + union + { + __IOM uint32_t EACOEM; /*!< (@ 0x00000260) Ethernet Agent CBS Oper Enable Monitoring Register + * (EACOEM) */ + + struct + { + __IOM uint32_t CE0 : 1; /*!< [0..0] CE0 */ + __IOM uint32_t CE1 : 1; /*!< [1..1] CE1 */ + __IOM uint32_t CE2 : 1; /*!< [2..2] CE2 */ + __IOM uint32_t CE3 : 1; /*!< [3..3] CE3 */ + __IOM uint32_t CE4 : 1; /*!< [4..4] CE4 */ + __IOM uint32_t CE5 : 1; /*!< [5..5] CE5 */ + __IOM uint32_t CE6 : 1; /*!< [6..6] CE6 */ + __IOM uint32_t CE7 : 1; /*!< [7..7] CE7 */ + uint32_t : 24; + } EACOEM_b; + }; + __IM uint32_t RESERVED6[7]; + + union + { + __IOM uint32_t EACOIVM0; /*!< (@ 0x00000280) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM0_b; + }; + + union + { + __IOM uint32_t EACOIVM1; /*!< (@ 0x00000284) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM1_b; + }; + + union + { + __IOM uint32_t EACOIVM2; /*!< (@ 0x00000288) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM2_b; + }; + + union + { + __IOM uint32_t EACOIVM3; /*!< (@ 0x0000028C) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM3_b; + }; + + union + { + __IOM uint32_t EACOIVM4; /*!< (@ 0x00000290) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM4_b; + }; + + union + { + __IOM uint32_t EACOIVM5; /*!< (@ 0x00000294) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM5_b; + }; + + union + { + __IOM uint32_t EACOIVM6; /*!< (@ 0x00000298) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM6_b; + }; + + union + { + __IOM uint32_t EACOIVM7; /*!< (@ 0x0000029C) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM7_b; + }; + + union + { + __IOM uint32_t EACOULM0; /*!< (@ 0x000002A0) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM0_b; + }; + + union + { + __IOM uint32_t EACOULM1; /*!< (@ 0x000002A4) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM1_b; + }; + + union + { + __IOM uint32_t EACOULM2; /*!< (@ 0x000002A8) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM2_b; + }; + + union + { + __IOM uint32_t EACOULM3; /*!< (@ 0x000002AC) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM3_b; + }; + + union + { + __IOM uint32_t EACOULM4; /*!< (@ 0x000002B0) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM4_b; + }; + + union + { + __IOM uint32_t EACOULM5; /*!< (@ 0x000002B4) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM5_b; + }; + + union + { + __IOM uint32_t EACOULM6; /*!< (@ 0x000002B8) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM6_b; + }; + + union + { + __IOM uint32_t EACOULM7; /*!< (@ 0x000002BC) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM7_b; + }; + + union + { + __IOM uint32_t EACGSM; /*!< (@ 0x000002C0) Ethernet Agent CBS Gate State Monitoring Register + * (EACGSM) */ + + struct + { + __IOM uint32_t CGS0 : 1; /*!< [0..0] CGS0 */ + __IOM uint32_t CGS1 : 1; /*!< [1..1] CGS1 */ + __IOM uint32_t CGS2 : 1; /*!< [2..2] CGS2 */ + __IOM uint32_t CGS3 : 1; /*!< [3..3] CGS3 */ + __IOM uint32_t CGS4 : 1; /*!< [4..4] CGS4 */ + __IOM uint32_t CGS5 : 1; /*!< [5..5] CGS5 */ + __IOM uint32_t CGS6 : 1; /*!< [6..6] CGS6 */ + __IOM uint32_t CGS7 : 1; /*!< [7..7] CGS7 */ + uint32_t : 24; + } EACGSM_b; + }; + __IM uint32_t RESERVED7[15]; + + union + { + __IOM uint32_t EATASC; /*!< (@ 0x00000300) Ethernet Agent TAS Configuration Register (EATASC) */ + + struct + { + __IOM uint32_t TASE : 1; /*!< [0..0] TASE */ + __IOM uint32_t TASCC : 1; /*!< [1..1] TASCC */ + __IOM uint32_t TASCI : 1; /*!< [2..2] TASCI */ + uint32_t : 5; + __IOM uint32_t TASTS : 1; /*!< [8..8] TASTS */ + uint32_t : 7; + __IOM uint32_t TASCA : 8; /*!< [23..16] TASCA */ + uint32_t : 8; + } EATASC_b; + }; + + union + { + __IOM uint32_t EATASIGSC; /*!< (@ 0x00000304) Ethernet Agent TAS Initial Gate State Configuration + * Register (EATASIGSC) */ + + struct + { + __IOM uint32_t TASIGS0 : 1; /*!< [0..0] TASIGS0 */ + __IOM uint32_t TASIGS1 : 1; /*!< [1..1] TASIGS1 */ + __IOM uint32_t TASIGS2 : 1; /*!< [2..2] TASIGS2 */ + __IOM uint32_t TASIGS3 : 1; /*!< [3..3] TASIGS3 */ + __IOM uint32_t TASIGS4 : 1; /*!< [4..4] TASIGS4 */ + __IOM uint32_t TASIGS5 : 1; /*!< [5..5] TASIGS5 */ + __IOM uint32_t TASIGS6 : 1; /*!< [6..6] TASIGS6 */ + __IOM uint32_t TASIGS7 : 1; /*!< [7..7] TASIGS7 */ + __IOM uint32_t TASCTIGS : 1; /*!< [8..8] TASCTIGS */ + uint32_t : 23; + } EATASIGSC_b; + }; + __IM uint32_t RESERVED8[6]; + + union + { + __IOM uint32_t EATASENC0; /*!< (@ 0x00000320) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC0_b; + }; + + union + { + __IOM uint32_t EATASENC1; /*!< (@ 0x00000324) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC1_b; + }; + + union + { + __IOM uint32_t EATASENC2; /*!< (@ 0x00000328) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC2_b; + }; + + union + { + __IOM uint32_t EATASENC3; /*!< (@ 0x0000032C) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC3_b; + }; + + union + { + __IOM uint32_t EATASENC4; /*!< (@ 0x00000330) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC4_b; + }; + + union + { + __IOM uint32_t EATASENC5; /*!< (@ 0x00000334) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC5_b; + }; + + union + { + __IOM uint32_t EATASENC6; /*!< (@ 0x00000338) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC6_b; + }; + + union + { + __IOM uint32_t EATASENC7; /*!< (@ 0x0000033C) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC7_b; + }; + + union + { + __IOM uint32_t EATASCTENC; /*!< (@ 0x00000340) Ethernet Agent TAS Cut-Through Entry Number Configuration + * Register (EATASCTENC) */ + + struct + { + __IOM uint32_t TASCTAEN : 9; /*!< [8..0] TASCTAEN */ + uint32_t : 23; + } EATASCTENC_b; + }; + __IM uint32_t RESERVED9[7]; + + union + { + __IOM uint32_t EATASENM0; /*!< (@ 0x00000360) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM0_b; + }; + + union + { + __IOM uint32_t EATASENM1; /*!< (@ 0x00000364) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM1_b; + }; + + union + { + __IOM uint32_t EATASENM2; /*!< (@ 0x00000368) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM2_b; + }; + + union + { + __IOM uint32_t EATASENM3; /*!< (@ 0x0000036C) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM3_b; + }; + + union + { + __IOM uint32_t EATASENM4; /*!< (@ 0x00000370) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM4_b; + }; + + union + { + __IOM uint32_t EATASENM5; /*!< (@ 0x00000374) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM5_b; + }; + + union + { + __IOM uint32_t EATASENM6; /*!< (@ 0x00000378) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM6_b; + }; + + union + { + __IOM uint32_t EATASENM7; /*!< (@ 0x0000037C) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM7_b; + }; + + union + { + __IOM uint32_t EATASCTENM; /*!< (@ 0x00000380) Ethernet Agent TAS Cut-Through Entry Number Monitoring + * Register (EATASCTENM) */ + + struct + { + __IOM uint32_t TASCTOEN : 9; /*!< [8..0] TASCTOEN */ + uint32_t : 23; + } EATASCTENM_b; + }; + __IM uint32_t RESERVED10[7]; + + union + { + __IOM uint32_t EATASCSTC0; /*!< (@ 0x000003A0) Ethernet Agent TAS Cycle Start Time Configuration + * Register 0 (EATASCSTC0) */ + + struct + { + __IOM uint32_t TASACSTP0 : 32; /*!< [31..0] TASACSTP0 */ + } EATASCSTC0_b; + }; + + union + { + __IOM uint32_t EATASCSTC1; /*!< (@ 0x000003A4) Ethernet Agent TAS Cycle Start Time Configuration + * Register 1 (EATASCSTC1) */ + + struct + { + __IOM uint32_t TASACSTP1 : 32; /*!< [31..0] TASACSTP1 */ + } EATASCSTC1_b; + }; + + union + { + __IOM uint32_t EATASCSTM0; /*!< (@ 0x000003A8) Ethernet Agent TAS Cycle Start Time Monitoring + * Register 0 (EATASCSTM0) */ + + struct + { + __IOM uint32_t TASOCSTP0 : 32; /*!< [31..0] TASOCSTP0 */ + } EATASCSTM0_b; + }; + + union + { + __IOM uint32_t EATASCSTM1; /*!< (@ 0x000003AC) Ethernet Agent TAS Cycle Start Time Monitoring + * Register 1 (EATASCSTM1) */ + + struct + { + __IOM uint32_t TASOCSTP1 : 32; /*!< [31..0] TASOCSTP1 */ + } EATASCSTM1_b; + }; + + union + { + __IOM uint32_t EATASCTC; /*!< (@ 0x000003B0) Ethernet Agent TAS Cycle Time Configuration Register + * (EATASCTC) */ + + struct + { + __IOM uint32_t TASACT : 32; /*!< [31..0] TASACT */ + } EATASCTC_b; + }; + + union + { + __IOM uint32_t EATASCTM; /*!< (@ 0x000003B4) Ethernet Agent TAS Cycle Time Monitoring Register + * (EATASCTM) */ + + struct + { + __IOM uint32_t TASOCT : 32; /*!< [31..0] TASOCT */ + } EATASCTM_b; + }; + __IM uint32_t RESERVED11[2]; + + union + { + __IOM uint32_t EATASGL0; /*!< (@ 0x000003C0) Ethernet Agent TAS Gate Learn Register 0 (EATASGL0) */ + + struct + { + __IOM uint32_t TASGAL : 8; /*!< [7..0] TASGAL */ + uint32_t : 24; + } EATASGL0_b; + }; + + union + { + __IOM uint32_t EATASGL1; /*!< (@ 0x000003C4) Ethernet Agent TAS Gate Learn Register 1 (EATASGL1) */ + + struct + { + __IOM uint32_t TASGTL : 28; /*!< [27..0] TASGTL */ + __IOM uint32_t TASGSL : 1; /*!< [28..28] TASGSL */ + uint32_t : 3; + } EATASGL1_b; + }; + + union + { + __IOM uint32_t EATASGLR; /*!< (@ 0x000003C8) Ethernet Agent TAS Gate Learn Result Register + * (EATASGLR) */ + + struct + { + uint32_t : 31; + __IOM uint32_t GL : 1; /*!< [31..31] GL */ + } EATASGLR_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t EATASGR; /*!< (@ 0x000003D0) Ethernet Agent TAS Gate Read Register (EATASGR) */ + + struct + { + __IOM uint32_t TASGAR : 8; /*!< [7..0] TASGAR */ + uint32_t : 24; + } EATASGR_b; + }; + + union + { + __IOM uint32_t EATASGRR; /*!< (@ 0x000003D4) Ethernet Agent TAS Gate Read Result Register + * (EATASGRR) */ + + struct + { + __IOM uint32_t TASGTR : 28; /*!< [27..0] TASGTR */ + __IOM uint32_t TASGSR : 1; /*!< [28..28] TASGSR */ + __IOM uint32_t TASREF : 1; /*!< [29..29] TASREF */ + uint32_t : 1; + __IOM uint32_t GR : 1; /*!< [31..31] GR */ + } EATASGRR_b; + }; + __IM uint32_t RESERVED13[2]; + + union + { + __IOM uint32_t EATASHCC; /*!< (@ 0x000003E0) Ethernet Agent TAS Hardware Calibration Configuration + * Register (EATASHCC) */ + + struct + { + __IOM uint32_t TASJ : 16; /*!< [15..0] TASJ */ + uint32_t : 16; + } EATASHCC_b; + }; + + union + { + __IOM uint32_t EATASRIRM; /*!< (@ 0x000003E4) Ethernet Agent TAS RAM Initialization Register + * Monitoring Register (EATASRIRM) */ + + struct + { + __IOM uint32_t TASRIOG : 1; /*!< [0..0] TASRIOG */ + __IOM uint32_t TASRR : 1; /*!< [1..1] TASRR */ + uint32_t : 30; + } EATASRIRM_b; + }; + + union + { + __IOM uint32_t EATASSM; /*!< (@ 0x000003E8) Ethernet Agent TAS Status Monitoring Register + * (EATASSM) */ + + struct + { + __IOM uint32_t TASGS0 : 1; /*!< [0..0] TASGS0 */ + __IOM uint32_t TASGS1 : 1; /*!< [1..1] TASGS1 */ + __IOM uint32_t TASGS2 : 1; /*!< [2..2] TASGS2 */ + __IOM uint32_t TASGS3 : 1; /*!< [3..3] TASGS3 */ + __IOM uint32_t TASGS4 : 1; /*!< [4..4] TASGS4 */ + __IOM uint32_t TASGS5 : 1; /*!< [5..5] TASGS5 */ + __IOM uint32_t TASGS6 : 1; /*!< [6..6] TASGS6 */ + __IOM uint32_t TASGS7 : 1; /*!< [7..7] TASGS7 */ + __IOM uint32_t TASCTGS : 1; /*!< [8..8] TASCTGS */ + uint32_t : 7; + __IOM uint32_t TASSO : 1; /*!< [16..16] TASSO */ + uint32_t : 15; + } EATASSM_b; + }; + __IM uint32_t RESERVED14[5]; + + union + { + __IOM uint32_t EAUSMFSECN; /*!< (@ 0x00000400) Ethernet Agent Switch Minimum Frame Size Error + * Counter Register (EAUSMFSECN) */ + + struct + { + __IOM uint32_t USMFSEN : 16; /*!< [15..0] USMFSEN */ + uint32_t : 16; + } EAUSMFSECN_b; + }; + + union + { + __IOM uint32_t EATFECN; /*!< (@ 0x00000404) Ethernet Agent TAG Filtering Error Counter Register + * (EATFECN) */ + + struct + { + __IOM uint32_t TFEN : 16; /*!< [15..0] TFEN */ + uint32_t : 16; + } EATFECN_b; + }; + + union + { + __IOM uint32_t EAFSECN; /*!< (@ 0x00000408) Ethernet Agent Frame Size Error Counter Register + * (EAFSECN) */ + + struct + { + __IOM uint32_t FSEN : 16; /*!< [15..0] FSEN */ + uint32_t : 16; + } EAFSECN_b; + }; + + union + { + __IOM uint32_t EADQOECN; /*!< (@ 0x0000040C) Ethernet Agent Descriptor Queue Overflow Error + * Counter Register (EADQOECN) */ + + struct + { + __IOM uint32_t DQOEN : 16; /*!< [15..0] DQOEN */ + uint32_t : 16; + } EADQOECN_b; + }; + + union + { + __IOM uint32_t EADQSECN; /*!< (@ 0x00000410) Ethernet Agent Descriptor Queue Security Error + * Counter Register (EADQSECN) */ + + struct + { + __IOM uint32_t DQSEN : 16; /*!< [15..0] DQSEN */ + uint32_t : 16; + } EADQSECN_b; + }; + __IM uint32_t RESERVED15[59]; + + union + { + __IOM uint32_t EAEIS0; /*!< (@ 0x00000500) Ethernet Agent Error Interrupt Status Register + * 0 (EAEIS0) */ + + struct + { + __IOM uint32_t DECCES : 1; /*!< [0..0] DECCES */ + __IOM uint32_t TECCES : 1; /*!< [1..1] TECCES */ + __IOM uint32_t PECCES : 1; /*!< [2..2] PECCES */ + __IOM uint32_t DSECCES : 1; /*!< [3..3] DSECCES */ + __IOM uint32_t L23UECCES : 1; /*!< [4..4] L23UECCES */ + __IOM uint32_t USMFSES : 1; /*!< [5..5] USMFSES */ + __IOM uint32_t TFES : 1; /*!< [6..6] TFES */ + uint32_t : 1; + __IOM uint32_t FSES0 : 1; /*!< [8..8] FSES0 */ + __IOM uint32_t FSES1 : 1; /*!< [9..9] FSES1 */ + __IOM uint32_t FSES2 : 1; /*!< [10..10] FSES2 */ + __IOM uint32_t FSES3 : 1; /*!< [11..11] FSES3 */ + __IOM uint32_t FSES4 : 1; /*!< [12..12] FSES4 */ + __IOM uint32_t FSES5 : 1; /*!< [13..13] FSES5 */ + __IOM uint32_t FSES6 : 1; /*!< [14..14] FSES6 */ + __IOM uint32_t FSES7 : 1; /*!< [15..15] FSES7 */ + __IOM uint32_t TASGEES0 : 1; /*!< [16..16] TASGEES0 */ + __IOM uint32_t TASGEES1 : 1; /*!< [17..17] TASGEES1 */ + __IOM uint32_t TASGEES2 : 1; /*!< [18..18] TASGEES2 */ + __IOM uint32_t TASGEES3 : 1; /*!< [19..19] TASGEES3 */ + __IOM uint32_t TASGEES4 : 1; /*!< [20..20] TASGEES4 */ + __IOM uint32_t TASGEES5 : 1; /*!< [21..21] TASGEES5 */ + __IOM uint32_t TASGEES6 : 1; /*!< [22..22] TASGEES6 */ + __IOM uint32_t TASGEES7 : 1; /*!< [23..23] TASGEES7 */ + __IOM uint32_t TASCTGEES : 1; /*!< [24..24] TASCTGEES */ + uint32_t : 7; + } EAEIS0_b; + }; + + union + { + __IOM uint32_t EAEIE0; /*!< (@ 0x00000504) Ethernet Agent Error Interrupt Enable Register + * 0 (EAEIE0) */ + + struct + { + __IOM uint32_t DECCEE : 1; /*!< [0..0] DECCEE */ + __IOM uint32_t TECCEE : 1; /*!< [1..1] TECCEE */ + __IOM uint32_t PECCEE : 1; /*!< [2..2] PECCEE */ + __IOM uint32_t DSECCEE : 1; /*!< [3..3] DSECCEE */ + __IOM uint32_t L23UECCEE : 1; /*!< [4..4] L23UECCEE */ + __IOM uint32_t USMFSEE : 1; /*!< [5..5] USMFSEE */ + __IOM uint32_t TFEE : 1; /*!< [6..6] TFEE */ + uint32_t : 1; + __IOM uint32_t FSEE0 : 1; /*!< [8..8] FSEE0 */ + __IOM uint32_t FSEE1 : 1; /*!< [9..9] FSEE1 */ + __IOM uint32_t FSEE2 : 1; /*!< [10..10] FSEE2 */ + __IOM uint32_t FSEE3 : 1; /*!< [11..11] FSEE3 */ + __IOM uint32_t FSEE4 : 1; /*!< [12..12] FSEE4 */ + __IOM uint32_t FSEE5 : 1; /*!< [13..13] FSEE5 */ + __IOM uint32_t FSEE6 : 1; /*!< [14..14] FSEE6 */ + __IOM uint32_t FSEE7 : 1; /*!< [15..15] FSEE7 */ + __IOM uint32_t TASGEEE0 : 1; /*!< [16..16] TASGEEE0 */ + __IOM uint32_t TASGEEE1 : 1; /*!< [17..17] TASGEEE1 */ + __IOM uint32_t TASGEEE2 : 1; /*!< [18..18] TASGEEE2 */ + __IOM uint32_t TASGEEE3 : 1; /*!< [19..19] TASGEEE3 */ + __IOM uint32_t TASGEEE4 : 1; /*!< [20..20] TASGEEE4 */ + __IOM uint32_t TASGEEE5 : 1; /*!< [21..21] TASGEEE5 */ + __IOM uint32_t TASGEEE6 : 1; /*!< [22..22] TASGEEE6 */ + __IOM uint32_t TASGEEE7 : 1; /*!< [23..23] TASGEEE7 */ + __IOM uint32_t TASCTGEEE : 1; /*!< [24..24] TASCTGEEE */ + uint32_t : 7; + } EAEIE0_b; + }; + + union + { + __IOM uint32_t EAEID0; /*!< (@ 0x00000508) Ethernet Agent Error Interrupt Disable Register + * 0 (EAEID0) */ + + struct + { + __IOM uint32_t DECCED : 1; /*!< [0..0] DECCED */ + __IOM uint32_t TECCED : 1; /*!< [1..1] TECCED */ + __IOM uint32_t PECCED : 1; /*!< [2..2] PECCED */ + __IOM uint32_t DSECCED : 1; /*!< [3..3] DSECCED */ + __IOM uint32_t L23UECCED : 1; /*!< [4..4] L23UECCED */ + __IOM uint32_t USMFSED : 1; /*!< [5..5] USMFSED */ + __IOM uint32_t TFED : 1; /*!< [6..6] TFED */ + uint32_t : 1; + __IOM uint32_t FSED0 : 1; /*!< [8..8] FSED0 */ + __IOM uint32_t FSED1 : 1; /*!< [9..9] FSED1 */ + __IOM uint32_t FSED2 : 1; /*!< [10..10] FSED2 */ + __IOM uint32_t FSED3 : 1; /*!< [11..11] FSED3 */ + __IOM uint32_t FSED4 : 1; /*!< [12..12] FSED4 */ + __IOM uint32_t FSED5 : 1; /*!< [13..13] FSED5 */ + __IOM uint32_t FSED6 : 1; /*!< [14..14] FSED6 */ + __IOM uint32_t FSED7 : 1; /*!< [15..15] FSED7 */ + __IOM uint32_t TASGEED0 : 1; /*!< [16..16] TASGEED0 */ + __IOM uint32_t TASGEED1 : 1; /*!< [17..17] TASGEED1 */ + __IOM uint32_t TASGEED2 : 1; /*!< [18..18] TASGEED2 */ + __IOM uint32_t TASGEED3 : 1; /*!< [19..19] TASGEED3 */ + __IOM uint32_t TASGEED4 : 1; /*!< [20..20] TASGEED4 */ + __IOM uint32_t TASGEED5 : 1; /*!< [21..21] TASGEED5 */ + __IOM uint32_t TASGEED6 : 1; /*!< [22..22] TASGEED6 */ + __IOM uint32_t TASGEED7 : 1; /*!< [23..23] TASGEED7 */ + __IOM uint32_t TASCTGEED : 1; /*!< [24..24] TASCTGEED */ + uint32_t : 7; + } EAEID0_b; + }; + __IM uint32_t RESERVED16; + + union + { + __IOM uint32_t EAEIS1; /*!< (@ 0x00000510) Ethernet Agent Error Interrupt Status Register + * 1 (EAEIS1) */ + + struct + { + __IOM uint32_t CULES0 : 1; /*!< [0..0] CULES0 */ + __IOM uint32_t CULES1 : 1; /*!< [1..1] CULES1 */ + __IOM uint32_t CULES2 : 1; /*!< [2..2] CULES2 */ + __IOM uint32_t CULES3 : 1; /*!< [3..3] CULES3 */ + __IOM uint32_t CULES4 : 1; /*!< [4..4] CULES4 */ + __IOM uint32_t CULES5 : 1; /*!< [5..5] CULES5 */ + __IOM uint32_t CULES6 : 1; /*!< [6..6] CULES6 */ + __IOM uint32_t CULES7 : 1; /*!< [7..7] CULES7 */ + uint32_t : 8; + __IOM uint32_t TASGES0 : 1; /*!< [16..16] TASGES0 */ + __IOM uint32_t TASGES1 : 1; /*!< [17..17] TASGES1 */ + __IOM uint32_t TASGES2 : 1; /*!< [18..18] TASGES2 */ + __IOM uint32_t TASGES3 : 1; /*!< [19..19] TASGES3 */ + __IOM uint32_t TASGES4 : 1; /*!< [20..20] TASGES4 */ + __IOM uint32_t TASGES5 : 1; /*!< [21..21] TASGES5 */ + __IOM uint32_t TASGES6 : 1; /*!< [22..22] TASGES6 */ + __IOM uint32_t TASGES7 : 1; /*!< [23..23] TASGES7 */ + __IOM uint32_t TASCTGES : 1; /*!< [24..24] TASCTGES */ + uint32_t : 7; + } EAEIS1_b; + }; + + union + { + __IOM uint32_t EAEIE1; /*!< (@ 0x00000514) Ethernet Agent Error Interrupt Enable Register + * 1 (EAEIE1) */ + + struct + { + __IOM uint32_t CULEE0 : 1; /*!< [0..0] CULEE0 */ + __IOM uint32_t CULEE1 : 1; /*!< [1..1] CULEE1 */ + __IOM uint32_t CULEE2 : 1; /*!< [2..2] CULEE2 */ + __IOM uint32_t CULEE3 : 1; /*!< [3..3] CULEE3 */ + __IOM uint32_t CULEE4 : 1; /*!< [4..4] CULEE4 */ + __IOM uint32_t CULEE5 : 1; /*!< [5..5] CULEE5 */ + __IOM uint32_t CULEE6 : 1; /*!< [6..6] CULEE6 */ + __IOM uint32_t CULEE7 : 1; /*!< [7..7] CULEE7 */ + uint32_t : 8; + __IOM uint32_t TASGEE0 : 1; /*!< [16..16] TASGEE0 */ + __IOM uint32_t TASGEE1 : 1; /*!< [17..17] TASGEE1 */ + __IOM uint32_t TASGEE2 : 1; /*!< [18..18] TASGEE2 */ + __IOM uint32_t TASGEE3 : 1; /*!< [19..19] TASGEE3 */ + __IOM uint32_t TASGEE4 : 1; /*!< [20..20] TASGEE4 */ + __IOM uint32_t TASGEE5 : 1; /*!< [21..21] TASGEE5 */ + __IOM uint32_t TASGEE6 : 1; /*!< [22..22] TASGEE6 */ + __IOM uint32_t TASGEE7 : 1; /*!< [23..23] TASGEE7 */ + __IOM uint32_t TASCTGEE : 1; /*!< [24..24] TASCTGEE */ + uint32_t : 7; + } EAEIE1_b; + }; + + union + { + __IOM uint32_t EAEID1; /*!< (@ 0x00000518) Ethernet Agent Error Interrupt Disable Register + * 1 (EAEID1) */ + + struct + { + __IOM uint32_t CULED0 : 1; /*!< [0..0] CULED0 */ + __IOM uint32_t CULED1 : 1; /*!< [1..1] CULED1 */ + __IOM uint32_t CULED2 : 1; /*!< [2..2] CULED2 */ + __IOM uint32_t CULED3 : 1; /*!< [3..3] CULED3 */ + __IOM uint32_t CULED4 : 1; /*!< [4..4] CULED4 */ + __IOM uint32_t CULED5 : 1; /*!< [5..5] CULED5 */ + __IOM uint32_t CULED6 : 1; /*!< [6..6] CULED6 */ + __IOM uint32_t CULED7 : 1; /*!< [7..7] CULED7 */ + uint32_t : 8; + __IOM uint32_t TASGED0 : 1; /*!< [16..16] TASGED0 */ + __IOM uint32_t TASGED1 : 1; /*!< [17..17] TASGED1 */ + __IOM uint32_t TASGED2 : 1; /*!< [18..18] TASGED2 */ + __IOM uint32_t TASGED3 : 1; /*!< [19..19] TASGED3 */ + __IOM uint32_t TASGED4 : 1; /*!< [20..20] TASGED4 */ + __IOM uint32_t TASGED5 : 1; /*!< [21..21] TASGED5 */ + __IOM uint32_t TASGED6 : 1; /*!< [22..22] TASGED6 */ + __IOM uint32_t TASGED7 : 1; /*!< [23..23] TASGED7 */ + __IOM uint32_t TASCTGED : 1; /*!< [24..24] TASCTGED */ + uint32_t : 7; + } EAEID1_b; + }; + __IM uint32_t RESERVED17; + + union + { + __IOM uint32_t EAEIS2; /*!< (@ 0x00000520) Ethernet Agent Error Interrupt Status Register + * 2 (EAEIS2) */ + + struct + { + __IOM uint32_t DQOES0 : 1; /*!< [0..0] DQOES0 */ + __IOM uint32_t DQOES1 : 1; /*!< [1..1] DQOES1 */ + __IOM uint32_t DQOES2 : 1; /*!< [2..2] DQOES2 */ + __IOM uint32_t DQOES3 : 1; /*!< [3..3] DQOES3 */ + __IOM uint32_t DQOES4 : 1; /*!< [4..4] DQOES4 */ + __IOM uint32_t DQOES5 : 1; /*!< [5..5] DQOES5 */ + __IOM uint32_t DQOES6 : 1; /*!< [6..6] DQOES6 */ + __IOM uint32_t DQOES7 : 1; /*!< [7..7] DQOES7 */ + __IOM uint32_t CTDQOES : 1; /*!< [8..8] CTDQOES */ + uint32_t : 7; + __IOM uint32_t DQSES0 : 1; /*!< [16..16] DQSES0 */ + __IOM uint32_t DQSES1 : 1; /*!< [17..17] DQSES1 */ + __IOM uint32_t DQSES2 : 1; /*!< [18..18] DQSES2 */ + __IOM uint32_t DQSES3 : 1; /*!< [19..19] DQSES3 */ + __IOM uint32_t DQSES4 : 1; /*!< [20..20] DQSES4 */ + __IOM uint32_t DQSES5 : 1; /*!< [21..21] DQSES5 */ + __IOM uint32_t DQSES6 : 1; /*!< [22..22] DQSES6 */ + __IOM uint32_t DQSES7 : 1; /*!< [23..23] DQSES7 */ + uint32_t : 8; + } EAEIS2_b; + }; + + union + { + __IOM uint32_t EAEIE2; /*!< (@ 0x00000524) Ethernet Agent Error Interrupt Enable Register + * 2 (EAEIE2) */ + + struct + { + __IOM uint32_t DQOEE0 : 1; /*!< [0..0] DQOEE0 */ + __IOM uint32_t DQOEE1 : 1; /*!< [1..1] DQOEE1 */ + __IOM uint32_t DQOEE2 : 1; /*!< [2..2] DQOEE2 */ + __IOM uint32_t DQOEE3 : 1; /*!< [3..3] DQOEE3 */ + __IOM uint32_t DQOEE4 : 1; /*!< [4..4] DQOEE4 */ + __IOM uint32_t DQOEE5 : 1; /*!< [5..5] DQOEE5 */ + __IOM uint32_t DQOEE6 : 1; /*!< [6..6] DQOEE6 */ + __IOM uint32_t DQOEE7 : 1; /*!< [7..7] DQOEE7 */ + __IOM uint32_t CTDQOEE : 1; /*!< [8..8] CTDQOEE */ + uint32_t : 7; + __IOM uint32_t DQSEE0 : 1; /*!< [16..16] DQSEE0 */ + __IOM uint32_t DQSEE1 : 1; /*!< [17..17] DQSEE1 */ + __IOM uint32_t DQSEE2 : 1; /*!< [18..18] DQSEE2 */ + __IOM uint32_t DQSEE3 : 1; /*!< [19..19] DQSEE3 */ + __IOM uint32_t DQSEE4 : 1; /*!< [20..20] DQSEE4 */ + __IOM uint32_t DQSEE5 : 1; /*!< [21..21] DQSEE5 */ + __IOM uint32_t DQSEE6 : 1; /*!< [22..22] DQSEE6 */ + __IOM uint32_t DQSEE7 : 1; /*!< [23..23] DQSEE7 */ + uint32_t : 8; + } EAEIE2_b; + }; + + union + { + __IOM uint32_t EAEID2; /*!< (@ 0x00000528) Ethernet Agent Error Interrupt Disable Register + * 2 (EAEID2) */ + + struct + { + __IOM uint32_t DQOED0 : 1; /*!< [0..0] DQOED0 */ + __IOM uint32_t DQOED1 : 1; /*!< [1..1] DQOED1 */ + __IOM uint32_t DQOED2 : 1; /*!< [2..2] DQOED2 */ + __IOM uint32_t DQOED3 : 1; /*!< [3..3] DQOED3 */ + __IOM uint32_t DQOED4 : 1; /*!< [4..4] DQOED4 */ + __IOM uint32_t DQOED5 : 1; /*!< [5..5] DQOED5 */ + __IOM uint32_t DQOED6 : 1; /*!< [6..6] DQOED6 */ + __IOM uint32_t DQOED7 : 1; /*!< [7..7] DQOED7 */ + __IOM uint32_t CTDQOED : 1; /*!< [8..8] CTDQOED */ + uint32_t : 7; + __IOM uint32_t DQSED0 : 1; /*!< [16..16] DQSED0 */ + __IOM uint32_t DQSED1 : 1; /*!< [17..17] DQSED1 */ + __IOM uint32_t DQSED2 : 1; /*!< [18..18] DQSED2 */ + __IOM uint32_t DQSED3 : 1; /*!< [19..19] DQSED3 */ + __IOM uint32_t DQSED4 : 1; /*!< [20..20] DQSED4 */ + __IOM uint32_t DQSED5 : 1; /*!< [21..21] DQSED5 */ + __IOM uint32_t DQSED6 : 1; /*!< [22..22] DQSED6 */ + __IOM uint32_t DQSED7 : 1; /*!< [23..23] DQSED7 */ + uint32_t : 8; + } EAEID2_b; + }; + __IM uint32_t RESERVED18[21]; + + union + { + __IOM uint32_t EASCR; /*!< (@ 0x00000580) Ethernet Agent Security Configuration Register + * (EASCR) */ + + struct + { + __IOM uint32_t MRSL : 1; /*!< [0..0] MRSL */ + __IOM uint32_t TRSL : 1; /*!< [1..1] TRSL */ + __IOM uint32_t MCRSL : 1; /*!< [2..2] MCRSL */ + __IOM uint32_t TGRSL : 1; /*!< [3..3] TGRSL */ + __IOM uint32_t TASRSL : 1; /*!< [4..4] TASRSL */ + __IOM uint32_t EIRSL : 1; /*!< [5..5] EIRSL */ + __IOM uint32_t CRSL : 1; /*!< [6..6] CRSL */ + uint32_t : 9; + __IOM uint32_t DQRSL0 : 1; /*!< [16..16] DQRSL0 */ + __IOM uint32_t DQRSL1 : 1; /*!< [17..17] DQRSL1 */ + __IOM uint32_t DQRSL2 : 1; /*!< [18..18] DQRSL2 */ + __IOM uint32_t DQRSL3 : 1; /*!< [19..19] DQRSL3 */ + __IOM uint32_t DQRSL4 : 1; /*!< [20..20] DQRSL4 */ + __IOM uint32_t DQRSL5 : 1; /*!< [21..21] DQRSL5 */ + __IOM uint32_t DQRSL6 : 1; /*!< [22..22] DQRSL6 */ + __IOM uint32_t DQRSL7 : 1; /*!< [23..23] DQRSL7 */ + uint32_t : 8; + } EASCR_b; + }; +} R_ETHA0_Type; /*!< Size = 1412 (0x584) */ + +/* =========================================================================================================================== */ +/* ================ R_GPTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Generic PTP Timer (R_GPTP) + */ + +typedef struct /*!< (@ 0x403E0000) R_GPTP Structure */ +{ + union + { + __IM uint32_t PTPIPV; /*!< (@ 0x00000000) IP Version Register */ + + struct + { + __IM uint32_t IPV : 32; /*!< [31..0] IP Version */ + } PTPIPV_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t PTPTMEC; /*!< (@ 0x00000010) Timer Enable Configuration Register */ + + struct + { + __IOM uint32_t TE : 2; /*!< [1..0] Timer Enable */ + uint32_t : 30; + } PTPTMEC_b; + }; + + union + { + __IOM uint32_t PTPTMDC; /*!< (@ 0x00000014) Timer Disable Configuration Register */ + + struct + { + __OM uint32_t TD : 2; /*!< [1..0] Timer Disable */ + uint32_t : 30; + } PTPTMDC_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t PTPTIVC0; /*!< (@ 0x00000020) Timer Increment Value Configuration Register + * 0 */ + + struct + { + __IOM uint32_t TIV : 32; /*!< [31..0] Timer Increment Value */ + } PTPTIVC0_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t PTPTOVCL0; /*!< (@ 0x00000030) Timer Offset Value Configuration Register L0 */ + + struct + { + __IOM uint32_t TOVL : 30; /*!< [29..0] Timer Offset Value Lower Part */ + uint32_t : 2; + } PTPTOVCL0_b; + }; + + union + { + __IOM uint32_t PTPTOVCM0; /*!< (@ 0x00000034) Timer Offset Value Configuration Register M0 */ + + struct + { + __IOM uint32_t TOVM : 32; /*!< [31..0] Timer Offset Value Middle Part */ + } PTPTOVCM0_b; + }; + + union + { + __IOM uint32_t PTPTOVCU0; /*!< (@ 0x00000038) Timer Offset Value Configuration Register U0 */ + + struct + { + __IOM uint32_t TOVU : 16; /*!< [15..0] Timer Offset Value Upper Part */ + uint32_t : 16; + } PTPTOVCU0_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IM uint32_t PTPAVTPTML0; /*!< (@ 0x00000040) AVTP Timer Monitoring Register L0 */ + + struct + { + __IM uint32_t AVTPL : 32; /*!< [31..0] AVTP Timer Value Lower Part */ + } PTPAVTPTML0_b; + }; + + union + { + __IM uint32_t PTPAVTPTMU0; /*!< (@ 0x00000044) AVTP Timer Monitoring Register U0 */ + + struct + { + __IM uint32_t AVTPU : 32; /*!< [31..0] AVTP Timer Value Upper Part */ + } PTPAVTPTMU0_b; + }; + __IM uint32_t RESERVED4[2]; + + union + { + __IM uint32_t PTPGPTPTML0; /*!< (@ 0x00000050) GPTP Timer Monitoring Register L0 */ + + struct + { + __IM uint32_t GPTPL : 30; /*!< [29..0] GPTP Timer Value Lower Part */ + uint32_t : 2; + } PTPGPTPTML0_b; + }; + + union + { + __IM uint32_t PTPGPTPTMM0; /*!< (@ 0x00000054) GPTP Timer Monitoring Register M0 */ + + struct + { + __IM uint32_t GPTPM : 32; /*!< [31..0] GPTP Timer Value Middle Part */ + } PTPGPTPTMM0_b; + }; + + union + { + __IM uint32_t PTPGPTPTMU0; /*!< (@ 0x00000058) GPTP Timer Monitoring Register U0 */ + + struct + { + __IM uint32_t GPTPU : 16; /*!< [15..0] GPTP Timer Value Upper Part */ + uint32_t : 16; + } PTPGPTPTMU0_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t PTPTIVC1; /*!< (@ 0x00000060) Timer Increment Value Configuration Register + * 1 */ + + struct + { + __IOM uint32_t TIV : 32; /*!< [31..0] Timer Increment Value */ + } PTPTIVC1_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t PTPTOVCL1; /*!< (@ 0x00000070) Timer Offset Value Configuration Register L1 */ + + struct + { + __IOM uint32_t TOVL : 30; /*!< [29..0] Timer Offset Value Lower Part */ + uint32_t : 2; + } PTPTOVCL1_b; + }; + + union + { + __IOM uint32_t PTPTOVCM1; /*!< (@ 0x00000074) Timer Offset Value Configuration Register M1 */ + + struct + { + __IOM uint32_t TOVM : 32; /*!< [31..0] Timer Offset Value Middle Part */ + } PTPTOVCM1_b; + }; + + union + { + __IOM uint32_t PTPTOVCU1; /*!< (@ 0x00000078) Timer Offset Value Configuration Register U1 */ + + struct + { + __IOM uint32_t TOVU : 16; /*!< [15..0] Timer Offset Value Upper Part */ + uint32_t : 16; + } PTPTOVCU1_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IM uint32_t PTPAVTPTML1; /*!< (@ 0x00000080) AVTP Timer Monitoring Register L1 */ + + struct + { + __IM uint32_t AVTPL : 32; /*!< [31..0] AVTP Timer Value Lower Part */ + } PTPAVTPTML1_b; + }; + + union + { + __IM uint32_t PTPAVTPTMU1; /*!< (@ 0x00000084) AVTP Timer Monitoring Register U1 */ + + struct + { + __IM uint32_t AVTPU : 32; /*!< [31..0] AVTP Timer Value Upper Part */ + } PTPAVTPTMU1_b; + }; + __IM uint32_t RESERVED8[2]; + + union + { + __IM uint32_t PTPGPTPTML1; /*!< (@ 0x00000090) GPTP Timer Monitoring Register L1 */ + + struct + { + __IM uint32_t GPTPL : 30; /*!< [29..0] GPTP Timer Value Lower Part */ + uint32_t : 2; + } PTPGPTPTML1_b; + }; + + union + { + __IM uint32_t PTPGPTPTMM1; /*!< (@ 0x00000094) GPTP Timer Monitoring Register M1 */ + + struct + { + __IM uint32_t GPTPM : 32; /*!< [31..0] GPTP Timer Value Middle Part */ + } PTPGPTPTMM1_b; + }; + + union + { + __IM uint32_t PTPGPTPTMU1; /*!< (@ 0x00000098) GPTP Timer Monitoring Register U1 */ + + struct + { + __IM uint32_t GPTPU : 16; /*!< [15..0] GPTP Timer Value Upper Part */ + uint32_t : 16; + } PTPGPTPTMU1_b; + }; + __IM uint32_t RESERVED9[89]; + + union + { + __IOM uint32_t PTPMCCC0; /*!< (@ 0x00000200) Media Clock Capture Configuration Register 0 */ + + struct + { + __IOM uint32_t MCPEE : 1; /*!< [0..0] Media Clock Capture Positive Edge Enable */ + __IOM uint32_t MCNEE : 1; /*!< [1..1] Media Clock Capture Negative Edge Enable */ + __IOM uint32_t MCTTS : 1; /*!< [2..2] Media Clock Capture Timer Type Select */ + __IOM uint32_t MCTNS : 1; /*!< [3..3] Media Clock Capture Timer Number Select */ + uint32_t : 12; + __IOM uint32_t MCCR : 1; /*!< [16..16] Media Clock Capture Request */ + uint32_t : 15; + } PTPMCCC0_b; + }; + + union + { + __IM uint32_t PTPMCCML0; /*!< (@ 0x00000204) Media Clock Capture Monitoring Register L0 */ + + struct + { + __IM uint32_t MCCTVL : 32; /*!< [31..0] Media Clock Captured Timer Value Lower Part */ + } PTPMCCML0_b; + }; + + union + { + __IM uint32_t PTPMCCMM0; /*!< (@ 0x00000208) Media Clock Capture Monitoring Register M0 */ + + struct + { + __IM uint32_t MCCTVM : 32; /*!< [31..0] Media Clock Captured Timer Value Middle Part */ + } PTPMCCMM0_b; + }; + + union + { + __IM uint32_t PTPMCCMU0; /*!< (@ 0x0000020C) Media Clock Capture Monitoring Register U0 */ + + struct + { + __IM uint32_t MCCTVU : 16; /*!< [15..0] Media Clock Captured Timer Value Upper Part */ + __IM uint32_t MCPEC : 1; /*!< [16..16] Media Clock Positive Edge Captured */ + __IM uint32_t MCNEC : 1; /*!< [17..17] Media Clock Negative Edge Captured */ + __IM uint32_t MCSWC : 1; /*!< [18..18] Media Clock SoftWare Captured */ + uint32_t : 5; + __IM uint32_t MCCN : 2; /*!< [25..24] Media Clock Capture Number */ + uint32_t : 6; + } PTPMCCMU0_b; + }; + + union + { + __IOM uint32_t PTPMCCC1; /*!< (@ 0x00000210) Media Clock Capture Configuration Register 1 */ + + struct + { + __IOM uint32_t MCPEE : 1; /*!< [0..0] Media Clock Capture Positive Edge Enable */ + __IOM uint32_t MCNEE : 1; /*!< [1..1] Media Clock Capture Negative Edge Enable */ + __IOM uint32_t MCTTS : 1; /*!< [2..2] Media Clock Capture Timer Type Select */ + __IOM uint32_t MCTNS : 1; /*!< [3..3] Media Clock Capture Timer Number Select */ + uint32_t : 12; + __IOM uint32_t MCCR : 1; /*!< [16..16] Media Clock Capture Request */ + uint32_t : 15; + } PTPMCCC1_b; + }; + + union + { + __IM uint32_t PTPMCCML1; /*!< (@ 0x00000214) Media Clock Capture Monitoring Register L1 */ + + struct + { + __IM uint32_t MCCTVL : 32; /*!< [31..0] Media Clock Captured Timer Value Lower Part */ + } PTPMCCML1_b; + }; + + union + { + __IM uint32_t PTPMCCMM1; /*!< (@ 0x00000218) Media Clock Capture Monitoring Register M1 */ + + struct + { + __IM uint32_t MCCTVM : 32; /*!< [31..0] Media Clock Captured Timer Value Middle Part */ + } PTPMCCMM1_b; + }; + + union + { + __IM uint32_t PTPMCCMU1; /*!< (@ 0x0000021C) Media Clock Capture Monitoring Register U1 */ + + struct + { + __IM uint32_t MCCTVU : 16; /*!< [15..0] Media Clock Captured Timer Value Upper Part */ + __IM uint32_t MCPEC : 1; /*!< [16..16] Media Clock Positive Edge Captured */ + __IM uint32_t MCNEC : 1; /*!< [17..17] Media Clock Negative Edge Captured */ + __IM uint32_t MCSWC : 1; /*!< [18..18] Media Clock SoftWare Captured */ + uint32_t : 5; + __IM uint32_t MCCN : 2; /*!< [25..24] Media Clock Capture Number */ + uint32_t : 6; + } PTPMCCMU1_b; + }; + __IM uint32_t RESERVED10[56]; + + union + { + __IOM uint32_t PTPMCRC0; /*!< (@ 0x00000300) Media Clock Recovery Configuration Register 0 */ + + struct + { + __IOM uint32_t MRTTS : 1; /*!< [0..0] Media Clock Recovery Timer Type Select */ + __IOM uint32_t MRAMS : 1; /*!< [1..1] Media Clock Recovery AVTP Mode Select */ + __IOM uint32_t MRTNS : 1; /*!< [2..2] Media Clock Recovery Timer Number Select */ + uint32_t : 13; + __IOM uint32_t MRPL : 16; /*!< [31..16] Media Clock Recovery Pulse Length */ + } PTPMCRC0_b; + }; + + union + { + __IOM uint32_t PTPMCRTCL0; /*!< (@ 0x00000304) Media Clock Recovery Time Configuration Register + * L0 */ + + struct + { + __IOM uint32_t MRTVL : 32; /*!< [31..0] Media Clock Recovery Timer Value Lower Part */ + } PTPMCRTCL0_b; + }; + + union + { + __IOM uint32_t PTPMCRTCM0; /*!< (@ 0x00000308) Media Clock Recovery Time Configuration Register + * M0 */ + + struct + { + __IOM uint32_t MRTVM : 32; /*!< [31..0] Media Clock Recovery Timer Value Middle Part */ + } PTPMCRTCM0_b; + }; + + union + { + __IOM uint32_t PTPMCRTCU0; /*!< (@ 0x0000030C) Media Clock Recovery Time Configuration Register + * U0 */ + + struct + { + __IOM uint32_t MRTVU : 16; /*!< [15..0] Media Clock Recovery Timer Value Upper Part */ + __IOM uint32_t MRTT : 2; /*!< [17..16] Media Clock Recovery Trigger Type */ + __IM uint32_t MCRN : 3; /*!< [20..18] Media Clock Recovery Number */ + uint32_t : 10; + __IM uint32_t MRBCR : 1; /*!< [31..31] Media Clock Recovery Buffer Clear Request */ + } PTPMCRTCU0_b; + }; + + union + { + __IOM uint32_t PTPMCRC1; /*!< (@ 0x00000310) Media Clock Recovery Configuration Register 1 */ + + struct + { + __IOM uint32_t MRTTS : 1; /*!< [0..0] Media Clock Recovery Timer Type Select */ + __IOM uint32_t MRAMS : 1; /*!< [1..1] Media Clock Recovery AVTP Mode Select */ + __IOM uint32_t MRTNS : 1; /*!< [2..2] Media Clock Recovery Timer Number Select */ + uint32_t : 13; + __IOM uint32_t MRPL : 16; /*!< [31..16] Media Clock Recovery Pulse Length */ + } PTPMCRC1_b; + }; + + union + { + __IOM uint32_t PTPMCRTCL1; /*!< (@ 0x00000314) Media Clock Recovery Time Configuration Register + * L1 */ + + struct + { + __IOM uint32_t MRTVL : 32; /*!< [31..0] Media Clock Recovery Timer Value Lower Part */ + } PTPMCRTCL1_b; + }; + + union + { + __IOM uint32_t PTPMCRTCM1; /*!< (@ 0x00000318) Media Clock Recovery Time Configuration Register + * M1 */ + + struct + { + __IOM uint32_t MRTVM : 32; /*!< [31..0] Media Clock Recovery Timer Value Middle Part */ + } PTPMCRTCM1_b; + }; + + union + { + __IOM uint32_t PTPMCRTCU1; /*!< (@ 0x0000031C) Media Clock Recovery Time Configuration Register + * U1 */ + + struct + { + __IOM uint32_t MRTVU : 16; /*!< [15..0] Media Clock Recovery Timer Value Upper Part */ + __IOM uint32_t MRTT : 2; /*!< [17..16] Media Clock Recovery Trigger Type */ + __IM uint32_t MCRN : 3; /*!< [20..18] Media Clock Recovery Number */ + uint32_t : 10; + __IM uint32_t MRBCR : 1; /*!< [31..31] Media Clock Recovery Buffer Clear Request */ + } PTPMCRTCU1_b; + }; + __IM uint32_t RESERVED11[56]; + + union + { + __IOM uint32_t PTPMCPC0; /*!< (@ 0x00000400) Media Clock Pin Configuration Register 0 */ + + struct + { + __IOM uint32_t PE : 1; /*!< [0..0] Pin Enable */ + __IOM uint32_t MRS : 1; /*!< [1..1] Media Clock Recovery Select */ + uint32_t : 30; + } PTPMCPC0_b; + }; + + union + { + __IOM uint32_t PTPMCPC1; /*!< (@ 0x00000404) Media Clock Pin Configuration Register 1 */ + + struct + { + __IOM uint32_t PE : 1; /*!< [0..0] Pin Enable */ + __IOM uint32_t MRS : 1; /*!< [1..1] Media Clock Recovery Select */ + uint32_t : 30; + } PTPMCPC1_b; + }; + __IM uint32_t RESERVED12[62]; + + union + { + __IOM uint32_t PTPCCC00; /*!< (@ 0x00000500) Cyclic Compare Configuration Register 00 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC00_b; + }; + + union + { + __IOM uint32_t PTPCCC10; /*!< (@ 0x00000504) Cyclic Compare Configuration Register 10 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC10_b; + }; + + union + { + __IOM uint32_t PTPCCC01; /*!< (@ 0x00000508) Cyclic Compare Configuration Register 01 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC01_b; + }; + + union + { + __IOM uint32_t PTPCCC11; /*!< (@ 0x0000050C) Cyclic Compare Configuration Register 11 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC11_b; + }; + + union + { + __IOM uint32_t PTPCCC02; /*!< (@ 0x00000510) Cyclic Compare Configuration Register 02 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC02_b; + }; + + union + { + __IOM uint32_t PTPCCC12; /*!< (@ 0x00000514) Cyclic Compare Configuration Register 12 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC12_b; + }; + + union + { + __IOM uint32_t PTPCCC03; /*!< (@ 0x00000518) Cyclic Compare Configuration Register 03 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC03_b; + }; + + union + { + __IOM uint32_t PTPCCC13; /*!< (@ 0x0000051C) Cyclic Compare Configuration Register 13 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC13_b; + }; + + union + { + __IOM uint32_t PTPCCC04; /*!< (@ 0x00000520) Cyclic Compare Configuration Register 04 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC04_b; + }; + + union + { + __IOM uint32_t PTPCCC14; /*!< (@ 0x00000524) Cyclic Compare Configuration Register 14 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC14_b; + }; + + union + { + __IOM uint32_t PTPCCC05; /*!< (@ 0x00000528) Cyclic Compare Configuration Register 05 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC05_b; + }; + + union + { + __IOM uint32_t PTPCCC15; /*!< (@ 0x0000052C) Cyclic Compare Configuration Register 15 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC15_b; + }; + + union + { + __IOM uint32_t PTPCCC06; /*!< (@ 0x00000530) Cyclic Compare Configuration Register 06 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC06_b; + }; + + union + { + __IOM uint32_t PTPCCC16; /*!< (@ 0x00000534) Cyclic Compare Configuration Register 16 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC16_b; + }; + + union + { + __IOM uint32_t PTPCCC07; /*!< (@ 0x00000538) Cyclic Compare Configuration Register 07 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC07_b; + }; + + union + { + __IOM uint32_t PTPCCC17; /*!< (@ 0x0000053C) Cyclic Compare Configuration Register 17 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC17_b; + }; + __IM uint32_t RESERVED13[112]; + + union + { + __IOM uint32_t PTPIS0; /*!< (@ 0x00000700) Interrupt Status Register 0 */ + + struct + { + __IOM uint32_t MCCS : 2; /*!< [1..0] Media Clock Capture Status */ + uint32_t : 14; + __IOM uint32_t MCCOES : 2; /*!< [17..16] Media Clock Capture Overflow Error Status */ + uint32_t : 14; + } PTPIS0_b; + }; + + union + { + __IOM uint32_t PTPIE0; /*!< (@ 0x00000704) Interrupt Enable Register 0 */ + + struct + { + __IOM uint32_t MCCE : 2; /*!< [1..0] Media Clock Capture Enable */ + uint32_t : 14; + __IOM uint32_t MCCOEE : 2; /*!< [17..16] Media Clock Capture Overflow Error Enable */ + uint32_t : 14; + } PTPIE0_b; + }; + + union + { + __IM uint32_t PTPID0; /*!< (@ 0x00000708) Interrupt Disable Register 0 */ + + struct + { + __IM uint32_t MCCD : 2; /*!< [1..0] Media Clock Capture Disable */ + uint32_t : 14; + __IM uint32_t MCCOED : 2; /*!< [17..16] Media Clock Capture Overflow Error Disable */ + uint32_t : 14; + } PTPID0_b; + }; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t PTPIS1; /*!< (@ 0x00000710) Interrupt Status Register 1 */ + + struct + { + __IOM uint32_t MCRMS : 2; /*!< [1..0] Media Clock Recovery Match Status */ + uint32_t : 30; + } PTPIS1_b; + }; + + union + { + __IOM uint32_t PTPIE1; /*!< (@ 0x00000714) Interrupt Enable Register 1 */ + + struct + { + __IOM uint32_t MCRME : 2; /*!< [1..0] Media Clock Recovery Match Enable */ + uint32_t : 30; + } PTPIE1_b; + }; + + union + { + __IM uint32_t PTPID1; /*!< (@ 0x00000718) Interrupt Disable Register 1 */ + + struct + { + __IM uint32_t MCRMD : 2; /*!< [1..0] Media Clock Recovery Match Disable */ + uint32_t : 30; + } PTPID1_b; + }; + __IM uint32_t RESERVED15[25]; + + union + { + __IOM uint32_t PTPSCR0; /*!< (@ 0x00000780) Security Configuration Register 0 */ + + struct + { + __IOM uint32_t TRSL : 2; /*!< [1..0] TRSL */ + uint32_t : 14; + __IOM uint32_t MCRSL : 2; /*!< [17..16] MCRSL */ + uint32_t : 14; + } PTPSCR0_b; + }; + + union + { + __IOM uint32_t PTPSCR1; /*!< (@ 0x00000784) Security Configuration Register 1 */ + + struct + { + __IOM uint32_t MRRSL : 2; /*!< [1..0] MRRSL */ + uint32_t : 14; + __IOM uint32_t MRRRSL : 2; /*!< [17..16] MRRRSL */ + uint32_t : 14; + } PTPSCR1_b; + }; + + union + { + __IOM uint32_t PTPSCR2; /*!< (@ 0x00000788) Security Configuration Register 2 */ + + struct + { + __IOM uint32_t CCRSL : 2; /*!< [1..0] CCRSL */ + uint32_t : 14; + __IOM uint32_t VRSL : 1; /*!< [16..16] VRSL */ + uint32_t : 15; + } PTPSCR2_b; + }; + __IM uint32_t RESERVED16[541]; + + union + { + __IOM uint32_t POTCFGR; /*!< (@ 0x00001000) Pulse Output Timer Configuration Register */ + + struct + { + __IOM uint32_t REFSEL : 1; /*!< [0..0] Reference Timer Select */ + uint32_t : 31; + } POTCFGR_b; + }; + + union + { + __IOM uint32_t POTCR0; /*!< (@ 0x00001004) Pulse Output Timer Control Register 0 */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] Pulse Output Enable */ + uint32_t : 31; + } POTCR0_b; + }; + __IOM uint32_t POTSTRU0; /*!< (@ 0x00001008) Pulse Output Start Time Setting Register U0 */ + __IOM uint32_t POTSTRM0; /*!< (@ 0x0000100C) Pulse Output Start Time Setting Register M0 */ + __IOM uint32_t POTSTRL0; /*!< (@ 0x00001010) Pulse Output Start Time Setting Register L0 */ + __IOM uint32_t POTPERU0; /*!< (@ 0x00001014) Period Setting Register U0 */ + __IOM uint32_t POTPERM0; /*!< (@ 0x00001018) Period Setting Register M0 */ + __IOM uint32_t POTPERL0; /*!< (@ 0x0000101C) Period Setting Register L0 */ + __IOM uint32_t POTPWR0; /*!< (@ 0x00001020) Pulse Width Setting Register 0 */ + __IM uint32_t RESERVED17; + __IM uint32_t POTCPRU0; /*!< (@ 0x00001028) Time Capture Register U0 */ + __IM uint32_t POTCPRM0; /*!< (@ 0x0000102C) Time Capture Register M0 */ + __IM uint32_t POTCPRL0; /*!< (@ 0x00001030) Time Capture Register L0 */ + + union + { + __IOM uint32_t POTCR1; /*!< (@ 0x00001034) Pulse Output Timer Control Register 1 */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] Pulse Output Enable */ + uint32_t : 31; + } POTCR1_b; + }; + __IOM uint32_t POTSTRU1; /*!< (@ 0x00001038) Pulse Output Start Time Setting Register U1 */ + __IOM uint32_t POTSTRM1; /*!< (@ 0x0000103C) Pulse Output Start Time Setting Register M1 */ + __IOM uint32_t POTSTRL1; /*!< (@ 0x00001040) Pulse Output Start Time Setting Register L1 */ + __IOM uint32_t POTPERU1; /*!< (@ 0x00001044) Period Setting Register U1 */ + __IOM uint32_t POTPERM1; /*!< (@ 0x00001048) Period Setting Register M1 */ + __IOM uint32_t POTPERL1; /*!< (@ 0x0000104C) Period Setting Register L1 */ + __IOM uint32_t POTPWR1; /*!< (@ 0x00001050) Pulse Width Setting Register 1 */ + __IM uint32_t RESERVED18; + __IM uint32_t POTCPRU1; /*!< (@ 0x00001058) Time Capture Register U1 */ + __IM uint32_t POTCPRM1; /*!< (@ 0x0000105C) Time Capture Register M1 */ + __IM uint32_t POTCPRL1; /*!< (@ 0x00001060) Time Capture Register L1 */ + + union + { + __IOM uint32_t POTCR2; /*!< (@ 0x00001064) Pulse Output Timer Control Register 2 */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] Pulse Output Enable */ + uint32_t : 31; + } POTCR2_b; + }; + __IOM uint32_t POTSTRU2; /*!< (@ 0x00001068) Pulse Output Start Time Setting Register U2 */ + __IOM uint32_t POTSTRM2; /*!< (@ 0x0000106C) Pulse Output Start Time Setting Register M2 */ + __IOM uint32_t POTSTRL2; /*!< (@ 0x00001070) Pulse Output Start Time Setting Register L2 */ + __IOM uint32_t POTPERU2; /*!< (@ 0x00001074) Period Setting Register U2 */ + __IOM uint32_t POTPERM2; /*!< (@ 0x00001078) Period Setting Register M2 */ + __IOM uint32_t POTPERL2; /*!< (@ 0x0000107C) Period Setting Register L2 */ + __IOM uint32_t POTPWR2; /*!< (@ 0x00001080) Pulse Width Setting Register 2 */ + __IM uint32_t RESERVED19; + __IM uint32_t POTCPRU2; /*!< (@ 0x00001088) Time Capture Register U2 */ + __IM uint32_t POTCPRM2; /*!< (@ 0x0000108C) Time Capture Register M2 */ + __IM uint32_t POTCPRL2; /*!< (@ 0x00001090) Time Capture Register L2 */ + + union + { + __IOM uint32_t POTCR3; /*!< (@ 0x00001094) Pulse Output Timer Control Register 3 */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] Pulse Output Enable */ + uint32_t : 31; + } POTCR3_b; + }; + __IOM uint32_t POTSTRU3; /*!< (@ 0x00001098) Pulse Output Start Time Setting Register U3 */ + __IOM uint32_t POTSTRM3; /*!< (@ 0x0000109C) Pulse Output Start Time Setting Register M3 */ + __IOM uint32_t POTSTRL3; /*!< (@ 0x000010A0) Pulse Output Start Time Setting Register L3 */ + __IOM uint32_t POTPERU3; /*!< (@ 0x000010A4) Period Setting Register U3 */ + __IOM uint32_t POTPERM3; /*!< (@ 0x000010A8) Period Setting Register M3 */ + __IOM uint32_t POTPERL3; /*!< (@ 0x000010AC) Period Setting Register L3 */ + __IOM uint32_t POTPWR3; /*!< (@ 0x000010B0) Pulse Width Setting Register 3 */ + __IM uint32_t RESERVED20; + __IM uint32_t POTCPRU3; /*!< (@ 0x000010B8) Time Capture Register U3 */ + __IM uint32_t POTCPRM3; /*!< (@ 0x000010BC) Time Capture Register M3 */ + __IM uint32_t POTCPRL3; /*!< (@ 0x000010C0) Time Capture Register L3 */ +} R_GPTP_Type; /*!< Size = 4292 (0x10c4) */ + +/* =========================================================================================================================== */ +/* ================ R_GWCA0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Gateway CPU Agent (R_GWCA0) + */ + +typedef struct /*!< (@ 0x403CE000) R_GWCA0 Structure */ +{ + union + { + __IOM uint32_t GWMC; /*!< (@ 0x00000000) GWCA Mode Configuration Register (GWMC) */ + + struct + { + __IOM uint32_t OPC : 2; /*!< [1..0] OPC */ + uint32_t : 30; + } GWMC_b; + }; + + union + { + __IOM uint32_t GWMS; /*!< (@ 0x00000004) GWCA Mode Status Register (GWMS) */ + + struct + { + __IOM uint32_t OPS : 2; /*!< [1..0] OPS */ + uint32_t : 30; + } GWMS_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t GWIRC; /*!< (@ 0x00000010) GWCA IPV Remapping Configuration Register [802.1Q] + * (GWIRC) */ + + struct + { + __IOM uint32_t IPVR0 : 3; /*!< [2..0] IPVR0 */ + uint32_t : 1; + __IOM uint32_t IPVR1 : 3; /*!< [6..4] IPVR1 */ + uint32_t : 1; + __IOM uint32_t IPVR2 : 3; /*!< [10..8] IPVR2 */ + uint32_t : 1; + __IOM uint32_t IPVR3 : 3; /*!< [14..12] IPVR3 */ + uint32_t : 1; + __IOM uint32_t IPVR4 : 3; /*!< [18..16] IPVR4 */ + uint32_t : 1; + __IOM uint32_t IPVR5 : 3; /*!< [22..20] IPVR5 */ + uint32_t : 1; + __IOM uint32_t IPVR6 : 3; /*!< [26..24] IPVR6 */ + uint32_t : 1; + __IOM uint32_t IPVR7 : 3; /*!< [30..28] IPVR7 */ + uint32_t : 1; + } GWIRC_b; + }; + + union + { + __IOM uint32_t GWRDQSC; /*!< (@ 0x00000014) GWCA RX Descriptor Queue Security Configuration + * Register (GWRDQSC) */ + + struct + { + __IOM uint32_t RDQSL0 : 1; /*!< [0..0] RDQSL0 */ + __IOM uint32_t RDQSL1 : 1; /*!< [1..1] RDQSL1 */ + __IOM uint32_t RDQSL2 : 1; /*!< [2..2] RDQSL2 */ + __IOM uint32_t RDQSL3 : 1; /*!< [3..3] RDQSL3 */ + __IOM uint32_t RDQSL4 : 1; /*!< [4..4] RDQSL4 */ + __IOM uint32_t RDQSL5 : 1; /*!< [5..5] RDQSL5 */ + __IOM uint32_t RDQSL6 : 1; /*!< [6..6] RDQSL6 */ + __IOM uint32_t RDQSL7 : 1; /*!< [7..7] RDQSL7 */ + uint32_t : 24; + } GWRDQSC_b; + }; + + union + { + __IOM uint32_t GWRDQC; /*!< (@ 0x00000018) GWCA RX Descriptor Queue Control Register (GWRDQC) */ + + struct + { + __IOM uint32_t RDQD0 : 1; /*!< [0..0] RDQD0 */ + __IOM uint32_t RDQD1 : 1; /*!< [1..1] RDQD1 */ + __IOM uint32_t RDQD2 : 1; /*!< [2..2] RDQD2 */ + __IOM uint32_t RDQD3 : 1; /*!< [3..3] RDQD3 */ + __IOM uint32_t RDQD4 : 1; /*!< [4..4] RDQD4 */ + __IOM uint32_t RDQD5 : 1; /*!< [5..5] RDQD5 */ + __IOM uint32_t RDQD6 : 1; /*!< [6..6] RDQD6 */ + __IOM uint32_t RDQD7 : 1; /*!< [7..7] RDQD7 */ + uint32_t : 8; + __IOM uint32_t RDQP0 : 1; /*!< [16..16] RDQP0 */ + __IOM uint32_t RDQP1 : 1; /*!< [17..17] RDQP1 */ + __IOM uint32_t RDQP2 : 1; /*!< [18..18] RDQP2 */ + __IOM uint32_t RDQP3 : 1; /*!< [19..19] RDQP3 */ + __IOM uint32_t RDQP4 : 1; /*!< [20..20] RDQP4 */ + __IOM uint32_t RDQP5 : 1; /*!< [21..21] RDQP5 */ + __IOM uint32_t RDQP6 : 1; /*!< [22..22] RDQP6 */ + __IOM uint32_t RDQP7 : 1; /*!< [23..23] RDQP7 */ + uint32_t : 8; + } GWRDQC_b; + }; + + union + { + __IOM uint32_t GWRDQAC; /*!< (@ 0x0000001C) GWCA RX Descriptor Queue Arbitration Control + * Register (GWRDQAC) */ + + struct + { + __IOM uint32_t RDQA0 : 4; /*!< [3..0] RDQA0 */ + __IOM uint32_t RDQA1 : 4; /*!< [7..4] RDQA1 */ + __IOM uint32_t RDQA2 : 4; /*!< [11..8] RDQA2 */ + __IOM uint32_t RDQA3 : 4; /*!< [15..12] RDQA3 */ + __IOM uint32_t RDQA4 : 4; /*!< [19..16] RDQA4 */ + __IOM uint32_t RDQA5 : 4; /*!< [23..20] RDQA5 */ + __IOM uint32_t RDQA6 : 4; /*!< [27..24] RDQA6 */ + __IOM uint32_t RDQA7 : 4; /*!< [31..28] RDQA7 */ + } GWRDQAC_b; + }; + + union + { + __IOM uint32_t GWRGC; /*!< (@ 0x00000020) GWCA RX General Configuration Register (GWRGC) */ + + struct + { + __IOM uint32_t RCPT : 1; /*!< [0..0] RCPT */ + uint32_t : 31; + } GWRGC_b; + }; + __IM uint32_t RESERVED1[7]; + + union + { + __IOM uint32_t GWRMFSC0; /*!< (@ 0x00000040) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC0_b; + }; + + union + { + __IOM uint32_t GWRMFSC1; /*!< (@ 0x00000044) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC1_b; + }; + + union + { + __IOM uint32_t GWRMFSC2; /*!< (@ 0x00000048) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC2_b; + }; + + union + { + __IOM uint32_t GWRMFSC3; /*!< (@ 0x0000004C) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC3_b; + }; + + union + { + __IOM uint32_t GWRMFSC4; /*!< (@ 0x00000050) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC4_b; + }; + + union + { + __IOM uint32_t GWRMFSC5; /*!< (@ 0x00000054) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC5_b; + }; + + union + { + __IOM uint32_t GWRMFSC6; /*!< (@ 0x00000058) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC6_b; + }; + + union + { + __IOM uint32_t GWRMFSC7; /*!< (@ 0x0000005C) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC7_b; + }; + + union + { + __IOM uint32_t GWRDQDC0; /*!< (@ 0x00000060) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC0_b; + }; + + union + { + __IOM uint32_t GWRDQDC1; /*!< (@ 0x00000064) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC1_b; + }; + + union + { + __IOM uint32_t GWRDQDC2; /*!< (@ 0x00000068) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC2_b; + }; + + union + { + __IOM uint32_t GWRDQDC3; /*!< (@ 0x0000006C) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC3_b; + }; + + union + { + __IOM uint32_t GWRDQDC4; /*!< (@ 0x00000070) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC4_b; + }; + + union + { + __IOM uint32_t GWRDQDC5; /*!< (@ 0x00000074) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC5_b; + }; + + union + { + __IOM uint32_t GWRDQDC6; /*!< (@ 0x00000078) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC6_b; + }; + + union + { + __IOM uint32_t GWRDQDC7; /*!< (@ 0x0000007C) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC7_b; + }; + + union + { + __IOM uint32_t GWRDQM0; /*!< (@ 0x00000080) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM0_b; + }; + + union + { + __IOM uint32_t GWRDQM1; /*!< (@ 0x00000084) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM1_b; + }; + + union + { + __IOM uint32_t GWRDQM2; /*!< (@ 0x00000088) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM2_b; + }; + + union + { + __IOM uint32_t GWRDQM3; /*!< (@ 0x0000008C) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM3_b; + }; + + union + { + __IOM uint32_t GWRDQM4; /*!< (@ 0x00000090) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM4_b; + }; + + union + { + __IOM uint32_t GWRDQM5; /*!< (@ 0x00000094) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM5_b; + }; + + union + { + __IOM uint32_t GWRDQM6; /*!< (@ 0x00000098) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM6_b; + }; + + union + { + __IOM uint32_t GWRDQM7; /*!< (@ 0x0000009C) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM7_b; + }; + + union + { + __IOM uint32_t GWRDQMLM0; /*!< (@ 0x000000A0) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM0_b; + }; + + union + { + __IOM uint32_t GWRDQMLM1; /*!< (@ 0x000000A4) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM1_b; + }; + + union + { + __IOM uint32_t GWRDQMLM2; /*!< (@ 0x000000A8) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM2_b; + }; + + union + { + __IOM uint32_t GWRDQMLM3; /*!< (@ 0x000000AC) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM3_b; + }; + + union + { + __IOM uint32_t GWRDQMLM4; /*!< (@ 0x000000B0) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM4_b; + }; + + union + { + __IOM uint32_t GWRDQMLM5; /*!< (@ 0x000000B4) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM5_b; + }; + + union + { + __IOM uint32_t GWRDQMLM6; /*!< (@ 0x000000B8) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM6_b; + }; + + union + { + __IOM uint32_t GWRDQMLM7; /*!< (@ 0x000000BC) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM7_b; + }; + __IM uint32_t RESERVED2[16]; + + union + { + __IOM uint32_t GWMTIRM; /*!< (@ 0x00000100) GWCA Multicast Table Initialization Register + * Monitoring Register (GWMTIRM) */ + + struct + { + __IOM uint32_t MTIOG : 1; /*!< [0..0] MTIOG */ + __IOM uint32_t MTR : 1; /*!< [1..1] MTR */ + uint32_t : 30; + } GWMTIRM_b; + }; + + union + { + __IOM uint32_t GWMSTLS; /*!< (@ 0x00000104) GWCA Multicast Table Learning Setting Register + * (GWMSTLS) */ + + struct + { + __IOM uint32_t MNRCNL : 7; /*!< [6..0] MNRCNL */ + uint32_t : 1; + __IOM uint32_t MNL : 3; /*!< [10..8] MNL */ + uint32_t : 5; + __IOM uint32_t MSENL : 7; /*!< [22..16] MSENL */ + uint32_t : 9; + } GWMSTLS_b; + }; + + union + { + __IOM uint32_t GWMSTLR; /*!< (@ 0x00000108) GWCA Multicast Table Learning Result Register + * (GWMSTLR) */ + + struct + { + __IOM uint32_t MTLF : 1; /*!< [0..0] MTLF */ + uint32_t : 30; + __IOM uint32_t MTL : 1; /*!< [31..31] MTL */ + } GWMSTLR_b; + }; + + union + { + __IOM uint32_t GWMSTSS; /*!< (@ 0x0000010C) GWCA Multicast Table Searching Setting Register + * (GWMSTSS) */ + + struct + { + __IOM uint32_t MSENS : 7; /*!< [6..0] MSENS */ + uint32_t : 25; + } GWMSTSS_b; + }; + + union + { + __IOM uint32_t GWMSTSR; /*!< (@ 0x00000110) GWCA Multicast Table Searching Result Register + * (GWMSTSR) */ + + struct + { + __IOM uint32_t MNRCNR : 7; /*!< [6..0] MNRCNR */ + uint32_t : 1; + __IOM uint32_t MNR : 3; /*!< [10..8] MNR */ + uint32_t : 5; + __IOM uint32_t MTSEF : 1; /*!< [16..16] MTSEF */ + uint32_t : 14; + __IOM uint32_t MTS : 1; /*!< [31..31] MTS */ + } GWMSTSR_b; + }; + __IM uint32_t RESERVED3[3]; + + union + { + __IOM uint32_t GWMAC0; /*!< (@ 0x00000120) GWCA MAC Address Configuration Register 0 (GWMAC0) */ + + struct + { + __IOM uint32_t MAUP : 16; /*!< [15..0] MAUP */ + uint32_t : 16; + } GWMAC0_b; + }; + + union + { + __IOM uint32_t GWMAC1; /*!< (@ 0x00000124) GWCA MAC Address Configuration Register 1 (GWMAC1) */ + + struct + { + __IOM uint32_t MADP : 32; /*!< [31..0] MADP */ + } GWMAC1_b; + }; + __IM uint32_t RESERVED4[2]; + + union + { + __IOM uint32_t GWVCC; /*!< (@ 0x00000130) GWCA VLAN Control Configuration Register (GWVCC) */ + + struct + { + __IOM uint32_t VIM : 1; /*!< [0..0] VIM */ + uint32_t : 7; + __IOM uint32_t CTVUM : 1; /*!< [8..8] CTVUM */ + uint32_t : 7; + __IOM uint32_t VEM : 3; /*!< [18..16] VEM */ + uint32_t : 13; + } GWVCC_b; + }; + + union + { + __IOM uint32_t GWVTC; /*!< (@ 0x00000134) GWCA VLAN TAG Configuration Register (GWVTC) */ + + struct + { + __IOM uint32_t CTV : 12; /*!< [11..0] CTV */ + __IOM uint32_t CTP : 3; /*!< [14..12] CTP */ + __IOM uint32_t CTD : 1; /*!< [15..15] CTD */ + __IOM uint32_t STV : 12; /*!< [27..16] STV */ + __IOM uint32_t STP : 3; /*!< [30..28] STP */ + __IOM uint32_t STD : 1; /*!< [31..31] STD */ + } GWVTC_b; + }; + + union + { + __IOM uint32_t GWTTFC; /*!< (@ 0x00000138) GWCA Transmission TAG Filtering Configuration + * Register (GWTTFC) */ + + struct + { + __IOM uint32_t NT : 1; /*!< [0..0] NT */ + __IOM uint32_t RT : 1; /*!< [1..1] RT */ + __IOM uint32_t CST : 1; /*!< [2..2] CST */ + __IOM uint32_t CSRT : 1; /*!< [3..3] CSRT */ + __IOM uint32_t CT : 1; /*!< [4..4] CT */ + __IOM uint32_t CRT : 1; /*!< [5..5] CRT */ + __IOM uint32_t SCT : 1; /*!< [6..6] SCT */ + __IOM uint32_t SCRT : 1; /*!< [7..7] SCRT */ + __IOM uint32_t UT : 1; /*!< [8..8] UT */ + uint32_t : 23; + } GWTTFC_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t GWTDCAC00; /*!< (@ 0x00000140) GWCA Timestamp Descriptor Chain Address Configuration + * Register 0s (GWTDCAC0s) (s = 0, 1) */ + + struct + { + __IOM uint32_t TSCCAUP : 8; /*!< [7..0] TSCCAUP */ + uint32_t : 24; + } GWTDCAC00_b; + }; + + union + { + __IOM uint32_t GWTDCAC10; /*!< (@ 0x00000144) GWCA Timestamp Descriptor Chain Address Configuration + * Register 1s (GWTDCAC1s) (s = 0, 1) */ + + struct + { + __IOM uint32_t TSCCADP : 32; /*!< [31..0] TSCCADP */ + } GWTDCAC10_b; + }; + + union + { + __IOM uint32_t GWTDCAC01; /*!< (@ 0x00000148) GWCA Timestamp Descriptor Chain Address Configuration + * Register 0s (GWTDCAC0s) (s = 0, 1) */ + + struct + { + __IOM uint32_t TSCCAUP : 8; /*!< [7..0] TSCCAUP */ + uint32_t : 24; + } GWTDCAC01_b; + }; + + union + { + __IOM uint32_t GWTDCAC11; /*!< (@ 0x0000014C) GWCA Timestamp Descriptor Chain Address Configuration + * Register 1s (GWTDCAC1s) (s = 0, 1) */ + + struct + { + __IOM uint32_t TSCCADP : 32; /*!< [31..0] TSCCADP */ + } GWTDCAC11_b; + }; + __IM uint32_t RESERVED6[4]; + + union + { + __IOM uint32_t GWTSDCC0; /*!< (@ 0x00000160) GWCA Timestamp Descriptor Chain Configuration + * Register s (GWTSDCCs) (s = 0, 1) */ + + struct + { + __IOM uint32_t TE : 1; /*!< [0..0] TE */ + __IOM uint32_t DCS : 2; /*!< [2..1] DCS */ + uint32_t : 5; + __IOM uint32_t OSID : 3; /*!< [10..8] OSID */ + uint32_t : 21; + } GWTSDCC0_b; + }; + + union + { + __IOM uint32_t GWTSDCC1; /*!< (@ 0x00000164) GWCA Timestamp Descriptor Chain Configuration + * Register s (GWTSDCCs) (s = 0, 1) */ + + struct + { + __IOM uint32_t TE : 1; /*!< [0..0] TE */ + __IOM uint32_t DCS : 2; /*!< [2..1] DCS */ + uint32_t : 5; + __IOM uint32_t OSID : 3; /*!< [10..8] OSID */ + uint32_t : 21; + } GWTSDCC1_b; + }; + __IM uint32_t RESERVED7[6]; + + union + { + __IOM uint32_t GWTSNM; /*!< (@ 0x00000180) GWCA Timestamp Number Monitoring Register (GWTSNM) */ + + struct + { + __IOM uint32_t TNTR : 8; /*!< [7..0] TNTR */ + uint32_t : 24; + } GWTSNM_b; + }; + + union + { + __IOM uint32_t GWTSMNM; /*!< (@ 0x00000184) GWCA Timestamp Maximum Number Monitoring Register + * (GWTSMNM) */ + + struct + { + __IOM uint32_t TMNTR : 8; /*!< [7..0] TMNTR */ + uint32_t : 24; + } GWTSMNM_b; + }; + __IM uint32_t RESERVED8[2]; + + union + { + __IOM uint32_t GWAC; /*!< (@ 0x00000190) GWCA AXI Control Register (GWAC) */ + + struct + { + __IOM uint32_t AMPR : 1; /*!< [0..0] AMPR */ + __IOM uint32_t AMP : 1; /*!< [1..1] AMP */ + uint32_t : 30; + } GWAC_b; + }; + + union + { + __IOM uint32_t GWDCBAC0; /*!< (@ 0x00000194) GWCA Descriptor Chain Base Address Configuration + * Register 0 (GWDCBAC0) */ + + struct + { + __IOM uint32_t DCBAUP : 8; /*!< [7..0] DCBAUP */ + uint32_t : 24; + } GWDCBAC0_b; + }; + + union + { + __IOM uint32_t GWDCBAC1; /*!< (@ 0x00000198) GWCA Descriptor Chain Base Address Configuration + * Register 1 (GWDCBAC1) */ + + struct + { + __IOM uint32_t DCBADP : 32; /*!< [31..0] DCBADP */ + } GWDCBAC1_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t GWMDNC; /*!< (@ 0x000001A0) GWCA Maximum Descriptor Number Configuration + * Register (GWMDNC) */ + + struct + { + __IOM uint32_t RXDMN : 5; /*!< [4..0] RXDMN */ + uint32_t : 3; + __IOM uint32_t TXDMN : 5; /*!< [12..8] TXDMN */ + uint32_t : 3; + __IOM uint32_t TSDMN : 2; /*!< [17..16] TSDMN */ + uint32_t : 14; + } GWMDNC_b; + }; + __IM uint32_t RESERVED10[23]; + __IOM uint32_t GWTRC0; /*!< (@ 0x00000200) GWCA Transmission Request Configuration Register + * i (GWTRCi) (i = 0, 1) */ + __IOM uint32_t GWTRC1; /*!< (@ 0x00000204) GWCA Transmission Request Configuration Register + * i (GWTRCi) (i = 0, 1) */ + __IM uint32_t RESERVED11[62]; + + union + { + __IOM uint32_t GWTPC0; /*!< (@ 0x00000300) GWCA Transmission Pause Configuration Register + * p (GWTPCp) (p = 0, 1) */ + + struct + { + __IOM uint32_t PPPL0 : 1; /*!< [0..0] PPPL0 */ + __IOM uint32_t PPPL1 : 1; /*!< [1..1] PPPL1 */ + __IOM uint32_t PPPL2 : 1; /*!< [2..2] PPPL2 */ + __IOM uint32_t PPPL3 : 1; /*!< [3..3] PPPL3 */ + __IOM uint32_t PPPL4 : 1; /*!< [4..4] PPPL4 */ + __IOM uint32_t PPPL5 : 1; /*!< [5..5] PPPL5 */ + __IOM uint32_t PPPL6 : 1; /*!< [6..6] PPPL6 */ + __IOM uint32_t PPPL7 : 1; /*!< [7..7] PPPL7 */ + __IOM uint32_t PPPL8 : 1; /*!< [8..8] PPPL8 */ + uint32_t : 23; + } GWTPC0_b; + }; + + union + { + __IOM uint32_t GWTPC1; /*!< (@ 0x00000304) GWCA Transmission Pause Configuration Register + * p (GWTPCp) (p = 0, 1) */ + + struct + { + __IOM uint32_t PPPL0 : 1; /*!< [0..0] PPPL0 */ + __IOM uint32_t PPPL1 : 1; /*!< [1..1] PPPL1 */ + __IOM uint32_t PPPL2 : 1; /*!< [2..2] PPPL2 */ + __IOM uint32_t PPPL3 : 1; /*!< [3..3] PPPL3 */ + __IOM uint32_t PPPL4 : 1; /*!< [4..4] PPPL4 */ + __IOM uint32_t PPPL5 : 1; /*!< [5..5] PPPL5 */ + __IOM uint32_t PPPL6 : 1; /*!< [6..6] PPPL6 */ + __IOM uint32_t PPPL7 : 1; /*!< [7..7] PPPL7 */ + __IOM uint32_t PPPL8 : 1; /*!< [8..8] PPPL8 */ + uint32_t : 23; + } GWTPC1_b; + }; + __IM uint32_t RESERVED12[30]; + + union + { + __IOM uint32_t GWARIRM; /*!< (@ 0x00000380) GWCA AXI RAM Initialization Register Monitoring + * Register (GWARIRM) */ + + struct + { + __IOM uint32_t ARIOG : 1; /*!< [0..0] ARIOG */ + __IOM uint32_t ARR : 1; /*!< [1..1] ARR */ + uint32_t : 30; + } GWARIRM_b; + }; + __IM uint32_t RESERVED13[31]; + + union + { + __IOM uint32_t GWDCC0; /*!< (@ 0x00000400) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC0_b; + }; + + union + { + __IOM uint32_t GWDCC1; /*!< (@ 0x00000404) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC1_b; + }; + + union + { + __IOM uint32_t GWDCC2; /*!< (@ 0x00000408) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC2_b; + }; + + union + { + __IOM uint32_t GWDCC3; /*!< (@ 0x0000040C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC3_b; + }; + + union + { + __IOM uint32_t GWDCC4; /*!< (@ 0x00000410) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC4_b; + }; + + union + { + __IOM uint32_t GWDCC5; /*!< (@ 0x00000414) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC5_b; + }; + + union + { + __IOM uint32_t GWDCC6; /*!< (@ 0x00000418) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC6_b; + }; + + union + { + __IOM uint32_t GWDCC7; /*!< (@ 0x0000041C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC7_b; + }; + + union + { + __IOM uint32_t GWDCC8; /*!< (@ 0x00000420) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC8_b; + }; + + union + { + __IOM uint32_t GWDCC9; /*!< (@ 0x00000424) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC9_b; + }; + + union + { + __IOM uint32_t GWDCC10; /*!< (@ 0x00000428) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC10_b; + }; + + union + { + __IOM uint32_t GWDCC11; /*!< (@ 0x0000042C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC11_b; + }; + + union + { + __IOM uint32_t GWDCC12; /*!< (@ 0x00000430) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC12_b; + }; + + union + { + __IOM uint32_t GWDCC13; /*!< (@ 0x00000434) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC13_b; + }; + + union + { + __IOM uint32_t GWDCC14; /*!< (@ 0x00000438) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC14_b; + }; + + union + { + __IOM uint32_t GWDCC15; /*!< (@ 0x0000043C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC15_b; + }; + + union + { + __IOM uint32_t GWDCC16; /*!< (@ 0x00000440) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC16_b; + }; + + union + { + __IOM uint32_t GWDCC17; /*!< (@ 0x00000444) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC17_b; + }; + + union + { + __IOM uint32_t GWDCC18; /*!< (@ 0x00000448) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC18_b; + }; + + union + { + __IOM uint32_t GWDCC19; /*!< (@ 0x0000044C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC19_b; + }; + + union + { + __IOM uint32_t GWDCC20; /*!< (@ 0x00000450) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC20_b; + }; + + union + { + __IOM uint32_t GWDCC21; /*!< (@ 0x00000454) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC21_b; + }; + + union + { + __IOM uint32_t GWDCC22; /*!< (@ 0x00000458) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC22_b; + }; + + union + { + __IOM uint32_t GWDCC23; /*!< (@ 0x0000045C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC23_b; + }; + + union + { + __IOM uint32_t GWDCC24; /*!< (@ 0x00000460) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC24_b; + }; + + union + { + __IOM uint32_t GWDCC25; /*!< (@ 0x00000464) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC25_b; + }; + + union + { + __IOM uint32_t GWDCC26; /*!< (@ 0x00000468) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC26_b; + }; + + union + { + __IOM uint32_t GWDCC27; /*!< (@ 0x0000046C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC27_b; + }; + + union + { + __IOM uint32_t GWDCC28; /*!< (@ 0x00000470) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC28_b; + }; + + union + { + __IOM uint32_t GWDCC29; /*!< (@ 0x00000474) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC29_b; + }; + + union + { + __IOM uint32_t GWDCC30; /*!< (@ 0x00000478) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC30_b; + }; + + union + { + __IOM uint32_t GWDCC31; /*!< (@ 0x0000047C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC31_b; + }; + + union + { + __IOM uint32_t GWDCC32; /*!< (@ 0x00000480) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC32_b; + }; + + union + { + __IOM uint32_t GWDCC33; /*!< (@ 0x00000484) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC33_b; + }; + + union + { + __IOM uint32_t GWDCC34; /*!< (@ 0x00000488) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC34_b; + }; + + union + { + __IOM uint32_t GWDCC35; /*!< (@ 0x0000048C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC35_b; + }; + + union + { + __IOM uint32_t GWDCC36; /*!< (@ 0x00000490) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC36_b; + }; + + union + { + __IOM uint32_t GWDCC37; /*!< (@ 0x00000494) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC37_b; + }; + + union + { + __IOM uint32_t GWDCC38; /*!< (@ 0x00000498) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC38_b; + }; + + union + { + __IOM uint32_t GWDCC39; /*!< (@ 0x0000049C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC39_b; + }; + + union + { + __IOM uint32_t GWDCC40; /*!< (@ 0x000004A0) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC40_b; + }; + + union + { + __IOM uint32_t GWDCC41; /*!< (@ 0x000004A4) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC41_b; + }; + + union + { + __IOM uint32_t GWDCC42; /*!< (@ 0x000004A8) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC42_b; + }; + + union + { + __IOM uint32_t GWDCC43; /*!< (@ 0x000004AC) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC43_b; + }; + + union + { + __IOM uint32_t GWDCC44; /*!< (@ 0x000004B0) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC44_b; + }; + + union + { + __IOM uint32_t GWDCC45; /*!< (@ 0x000004B4) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC45_b; + }; + + union + { + __IOM uint32_t GWDCC46; /*!< (@ 0x000004B8) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC46_b; + }; + + union + { + __IOM uint32_t GWDCC47; /*!< (@ 0x000004BC) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC47_b; + }; + + union + { + __IOM uint32_t GWDCC48; /*!< (@ 0x000004C0) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC48_b; + }; + + union + { + __IOM uint32_t GWDCC49; /*!< (@ 0x000004C4) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC49_b; + }; + + union + { + __IOM uint32_t GWDCC50; /*!< (@ 0x000004C8) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC50_b; + }; + + union + { + __IOM uint32_t GWDCC51; /*!< (@ 0x000004CC) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC51_b; + }; + + union + { + __IOM uint32_t GWDCC52; /*!< (@ 0x000004D0) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC52_b; + }; + + union + { + __IOM uint32_t GWDCC53; /*!< (@ 0x000004D4) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC53_b; + }; + + union + { + __IOM uint32_t GWDCC54; /*!< (@ 0x000004D8) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC54_b; + }; + + union + { + __IOM uint32_t GWDCC55; /*!< (@ 0x000004DC) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC55_b; + }; + + union + { + __IOM uint32_t GWDCC56; /*!< (@ 0x000004E0) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC56_b; + }; + + union + { + __IOM uint32_t GWDCC57; /*!< (@ 0x000004E4) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC57_b; + }; + + union + { + __IOM uint32_t GWDCC58; /*!< (@ 0x000004E8) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC58_b; + }; + + union + { + __IOM uint32_t GWDCC59; /*!< (@ 0x000004EC) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC59_b; + }; + + union + { + __IOM uint32_t GWDCC60; /*!< (@ 0x000004F0) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC60_b; + }; + + union + { + __IOM uint32_t GWDCC61; /*!< (@ 0x000004F4) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC61_b; + }; + + union + { + __IOM uint32_t GWDCC62; /*!< (@ 0x000004F8) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC62_b; + }; + + union + { + __IOM uint32_t GWDCC63; /*!< (@ 0x000004FC) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC63_b; + }; + __IM uint32_t RESERVED14[192]; + + union + { + __IOM uint32_t GWAARSS; /*!< (@ 0x00000800) GWCA AXI Address RAM Searching Setting Register + * (GWAARSS) */ + + struct + { + __IOM uint32_t AARA : 7; /*!< [6..0] AARA */ + uint32_t : 25; + } GWAARSS_b; + }; + + union + { + __IOM uint32_t GWAARSR0; /*!< (@ 0x00000804) GWCA AXI Address RAM Searching Result Register + * 0 (GWAARSR0) */ + + struct + { + __IOM uint32_t ACARU : 8; /*!< [7..0] ACARU */ + uint32_t : 8; + __IOM uint32_t AARSEF : 1; /*!< [16..16] AARSEF */ + __IOM uint32_t AARSSF : 1; /*!< [17..17] AARSSF */ + uint32_t : 13; + __IOM uint32_t AARS : 1; /*!< [31..31] AARS */ + } GWAARSR0_b; + }; + + union + { + __IOM uint32_t GWAARSR1; /*!< (@ 0x00000808) GWCA AXI Address RAM Searching Result Register + * 1 (GWAARSR1) */ + + struct + { + __IOM uint32_t ACARD : 32; /*!< [31..0] ACARD */ + } GWAARSR1_b; + }; + __IM uint32_t RESERVED15[13]; + + union + { + __IOM uint32_t GWIDAUAS0; /*!< (@ 0x00000840) GWCA Incremental Data Area Used Area Size Register + * i (GWIDAUASi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAUAS : 24; /*!< [23..0] IDAUAS */ + uint32_t : 8; + } GWIDAUAS0_b; + }; + + union + { + __IOM uint32_t GWIDAUAS1; /*!< (@ 0x00000844) GWCA Incremental Data Area Used Area Size Register + * i (GWIDAUASi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAUAS : 24; /*!< [23..0] IDAUAS */ + uint32_t : 8; + } GWIDAUAS1_b; + }; + + union + { + __IOM uint32_t GWIDAUAS2; /*!< (@ 0x00000848) GWCA Incremental Data Area Used Area Size Register + * i (GWIDAUASi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAUAS : 24; /*!< [23..0] IDAUAS */ + uint32_t : 8; + } GWIDAUAS2_b; + }; + + union + { + __IOM uint32_t GWIDAUAS3; /*!< (@ 0x0000084C) GWCA Incremental Data Area Used Area Size Register + * i (GWIDAUASi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAUAS : 24; /*!< [23..0] IDAUAS */ + uint32_t : 8; + } GWIDAUAS3_b; + }; + __IM uint32_t RESERVED16[12]; + + union + { + __IOM uint32_t GWIDASM0; /*!< (@ 0x00000880) GWCA Incremental Data Area Size Monitoring Register + * i (GWIDASMi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAS : 24; /*!< [23..0] IDAS */ + uint32_t : 8; + } GWIDASM0_b; + }; + + union + { + __IOM uint32_t GWIDASM1; /*!< (@ 0x00000884) GWCA Incremental Data Area Size Monitoring Register + * i (GWIDASMi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAS : 24; /*!< [23..0] IDAS */ + uint32_t : 8; + } GWIDASM1_b; + }; + + union + { + __IOM uint32_t GWIDASM2; /*!< (@ 0x00000888) GWCA Incremental Data Area Size Monitoring Register + * i (GWIDASMi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAS : 24; /*!< [23..0] IDAS */ + uint32_t : 8; + } GWIDASM2_b; + }; + + union + { + __IOM uint32_t GWIDASM3; /*!< (@ 0x0000088C) GWCA Incremental Data Area Size Monitoring Register + * i (GWIDASMi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAS : 24; /*!< [23..0] IDAS */ + uint32_t : 8; + } GWIDASM3_b; + }; + __IM uint32_t RESERVED17[28]; + + union + { + __IOM uint32_t GWIDASAM00; /*!< (@ 0x00000900) GWCA Incremental Data Area Start Address Monitoring + * Register 0i (GWIDASAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAU : 8; /*!< [7..0] IDASAU */ + uint32_t : 24; + } GWIDASAM00_b; + }; + + union + { + __IOM uint32_t GWIDASAM10; /*!< (@ 0x00000904) GWCA Incremental Data Area Start Address Monitoring + * Register 1i (GWIDASAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAL : 32; /*!< [31..0] IDASAL */ + } GWIDASAM10_b; + }; + + union + { + __IOM uint32_t GWIDASAM01; /*!< (@ 0x00000908) GWCA Incremental Data Area Start Address Monitoring + * Register 0i (GWIDASAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAU : 8; /*!< [7..0] IDASAU */ + uint32_t : 24; + } GWIDASAM01_b; + }; + + union + { + __IOM uint32_t GWIDASAM11; /*!< (@ 0x0000090C) GWCA Incremental Data Area Start Address Monitoring + * Register 1i (GWIDASAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAL : 32; /*!< [31..0] IDASAL */ + } GWIDASAM11_b; + }; + + union + { + __IOM uint32_t GWIDASAM02; /*!< (@ 0x00000910) GWCA Incremental Data Area Start Address Monitoring + * Register 0i (GWIDASAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAU : 8; /*!< [7..0] IDASAU */ + uint32_t : 24; + } GWIDASAM02_b; + }; + + union + { + __IOM uint32_t GWIDASAM12; /*!< (@ 0x00000914) GWCA Incremental Data Area Start Address Monitoring + * Register 1i (GWIDASAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAL : 32; /*!< [31..0] IDASAL */ + } GWIDASAM12_b; + }; + + union + { + __IOM uint32_t GWIDASAM03; /*!< (@ 0x00000918) GWCA Incremental Data Area Start Address Monitoring + * Register 0i (GWIDASAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAU : 8; /*!< [7..0] IDASAU */ + uint32_t : 24; + } GWIDASAM03_b; + }; + + union + { + __IOM uint32_t GWIDASAM13; /*!< (@ 0x0000091C) GWCA Incremental Data Area Start Address Monitoring + * Register 1i (GWIDASAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAL : 32; /*!< [31..0] IDASAL */ + } GWIDASAM13_b; + }; + __IM uint32_t RESERVED18[24]; + + union + { + __IOM uint32_t GWIDACAM00; /*!< (@ 0x00000980) GWCA Incremental Data Area Current Address Monitoring + * Register 0i (GWIDACAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAU : 8; /*!< [7..0] IDACAU */ + uint32_t : 24; + } GWIDACAM00_b; + }; + + union + { + __IOM uint32_t GWIDACAM10; /*!< (@ 0x00000984) GWCA Incremental Data Area Current Address Monitoring + * Register 1i (GWIDACAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAL : 32; /*!< [31..0] IDACAL */ + } GWIDACAM10_b; + }; + + union + { + __IOM uint32_t GWIDACAM01; /*!< (@ 0x00000988) GWCA Incremental Data Area Current Address Monitoring + * Register 0i (GWIDACAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAU : 8; /*!< [7..0] IDACAU */ + uint32_t : 24; + } GWIDACAM01_b; + }; + + union + { + __IOM uint32_t GWIDACAM11; /*!< (@ 0x0000098C) GWCA Incremental Data Area Current Address Monitoring + * Register 1i (GWIDACAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAL : 32; /*!< [31..0] IDACAL */ + } GWIDACAM11_b; + }; + + union + { + __IOM uint32_t GWIDACAM02; /*!< (@ 0x00000990) GWCA Incremental Data Area Current Address Monitoring + * Register 0i (GWIDACAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAU : 8; /*!< [7..0] IDACAU */ + uint32_t : 24; + } GWIDACAM02_b; + }; + + union + { + __IOM uint32_t GWIDACAM12; /*!< (@ 0x00000994) GWCA Incremental Data Area Current Address Monitoring + * Register 1i (GWIDACAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAL : 32; /*!< [31..0] IDACAL */ + } GWIDACAM12_b; + }; + + union + { + __IOM uint32_t GWIDACAM03; /*!< (@ 0x00000998) GWCA Incremental Data Area Current Address Monitoring + * Register 0i (GWIDACAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAU : 8; /*!< [7..0] IDACAU */ + uint32_t : 24; + } GWIDACAM03_b; + }; + + union + { + __IOM uint32_t GWIDACAM13; /*!< (@ 0x0000099C) GWCA Incremental Data Area Current Address Monitoring + * Register 1i (GWIDACAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAL : 32; /*!< [31..0] IDACAL */ + } GWIDACAM13_b; + }; + __IM uint32_t RESERVED19[24]; + + union + { + __IOM uint32_t GWGRLC; /*!< (@ 0x00000A00) GWCA Global Rate Limiter Configuration Register + * (GWGRLC) */ + + struct + { + __IOM uint32_t GRLIV : 16; /*!< [15..0] GRLIV */ + __IOM uint32_t GRLE : 1; /*!< [16..16] GRLE */ + __IOM uint32_t GRLULRS : 1; /*!< [17..17] GRLULRS */ + uint32_t : 14; + } GWGRLC_b; + }; + + union + { + __IOM uint32_t GWGRLULC; /*!< (@ 0x00000A04) GWCA Global Rate Limiter Upper Limit Configuration + * Register (GWGRLULC) */ + + struct + { + __IOM uint32_t GRLUL : 24; /*!< [23..0] GRLUL */ + uint32_t : 8; + } GWGRLULC_b; + }; + __IM uint32_t RESERVED20[30]; + + union + { + __IOM uint32_t GWRLC0; /*!< (@ 0x00000A80) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC0_b; + }; + + union + { + __IOM uint32_t GWRLULC0; /*!< (@ 0x00000A84) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC0_b; + }; + + union + { + __IOM uint32_t GWRLC1; /*!< (@ 0x00000A88) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC1_b; + }; + + union + { + __IOM uint32_t GWRLULC1; /*!< (@ 0x00000A8C) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC1_b; + }; + + union + { + __IOM uint32_t GWRLC2; /*!< (@ 0x00000A90) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC2_b; + }; + + union + { + __IOM uint32_t GWRLULC2; /*!< (@ 0x00000A94) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC2_b; + }; + + union + { + __IOM uint32_t GWRLC3; /*!< (@ 0x00000A98) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC3_b; + }; + + union + { + __IOM uint32_t GWRLULC3; /*!< (@ 0x00000A9C) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC3_b; + }; + + union + { + __IOM uint32_t GWRLC4; /*!< (@ 0x00000AA0) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC4_b; + }; + + union + { + __IOM uint32_t GWRLULC4; /*!< (@ 0x00000AA4) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC4_b; + }; + + union + { + __IOM uint32_t GWRLC5; /*!< (@ 0x00000AA8) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC5_b; + }; + + union + { + __IOM uint32_t GWRLULC5; /*!< (@ 0x00000AAC) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC5_b; + }; + + union + { + __IOM uint32_t GWRLC6; /*!< (@ 0x00000AB0) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC6_b; + }; + + union + { + __IOM uint32_t GWRLULC6; /*!< (@ 0x00000AB4) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC6_b; + }; + + union + { + __IOM uint32_t GWRLC7; /*!< (@ 0x00000AB8) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC7_b; + }; + + union + { + __IOM uint32_t GWRLULC7; /*!< (@ 0x00000ABC) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC7_b; + }; + __IM uint32_t RESERVED21[48]; + + union + { + __IOM uint32_t GWIDPC; /*!< (@ 0x00000B80) GWCA Interrupt Delay Prescaler Configuration + * Register (GWIDPC) */ + + struct + { + __IOM uint32_t IDPV : 10; /*!< [9..0] IDPV */ + uint32_t : 22; + } GWIDPC_b; + }; + __IM uint32_t RESERVED22[31]; + + union + { + __IOM uint32_t GWIDC0; /*!< (@ 0x00000C00) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC0_b; + }; + + union + { + __IOM uint32_t GWIDC1; /*!< (@ 0x00000C04) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC1_b; + }; + + union + { + __IOM uint32_t GWIDC2; /*!< (@ 0x00000C08) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC2_b; + }; + + union + { + __IOM uint32_t GWIDC3; /*!< (@ 0x00000C0C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC3_b; + }; + + union + { + __IOM uint32_t GWIDC4; /*!< (@ 0x00000C10) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC4_b; + }; + + union + { + __IOM uint32_t GWIDC5; /*!< (@ 0x00000C14) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC5_b; + }; + + union + { + __IOM uint32_t GWIDC6; /*!< (@ 0x00000C18) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC6_b; + }; + + union + { + __IOM uint32_t GWIDC7; /*!< (@ 0x00000C1C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC7_b; + }; + + union + { + __IOM uint32_t GWIDC8; /*!< (@ 0x00000C20) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC8_b; + }; + + union + { + __IOM uint32_t GWIDC9; /*!< (@ 0x00000C24) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC9_b; + }; + + union + { + __IOM uint32_t GWIDC10; /*!< (@ 0x00000C28) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC10_b; + }; + + union + { + __IOM uint32_t GWIDC11; /*!< (@ 0x00000C2C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC11_b; + }; + + union + { + __IOM uint32_t GWIDC12; /*!< (@ 0x00000C30) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC12_b; + }; + + union + { + __IOM uint32_t GWIDC13; /*!< (@ 0x00000C34) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC13_b; + }; + + union + { + __IOM uint32_t GWIDC14; /*!< (@ 0x00000C38) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC14_b; + }; + + union + { + __IOM uint32_t GWIDC15; /*!< (@ 0x00000C3C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC15_b; + }; + + union + { + __IOM uint32_t GWIDC16; /*!< (@ 0x00000C40) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC16_b; + }; + + union + { + __IOM uint32_t GWIDC17; /*!< (@ 0x00000C44) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC17_b; + }; + + union + { + __IOM uint32_t GWIDC18; /*!< (@ 0x00000C48) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC18_b; + }; + + union + { + __IOM uint32_t GWIDC19; /*!< (@ 0x00000C4C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC19_b; + }; + + union + { + __IOM uint32_t GWIDC20; /*!< (@ 0x00000C50) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC20_b; + }; + + union + { + __IOM uint32_t GWIDC21; /*!< (@ 0x00000C54) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC21_b; + }; + + union + { + __IOM uint32_t GWIDC22; /*!< (@ 0x00000C58) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC22_b; + }; + + union + { + __IOM uint32_t GWIDC23; /*!< (@ 0x00000C5C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC23_b; + }; + + union + { + __IOM uint32_t GWIDC24; /*!< (@ 0x00000C60) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC24_b; + }; + + union + { + __IOM uint32_t GWIDC25; /*!< (@ 0x00000C64) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC25_b; + }; + + union + { + __IOM uint32_t GWIDC26; /*!< (@ 0x00000C68) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC26_b; + }; + + union + { + __IOM uint32_t GWIDC27; /*!< (@ 0x00000C6C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC27_b; + }; + + union + { + __IOM uint32_t GWIDC28; /*!< (@ 0x00000C70) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC28_b; + }; + + union + { + __IOM uint32_t GWIDC29; /*!< (@ 0x00000C74) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC29_b; + }; + + union + { + __IOM uint32_t GWIDC30; /*!< (@ 0x00000C78) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC30_b; + }; + + union + { + __IOM uint32_t GWIDC31; /*!< (@ 0x00000C7C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC31_b; + }; + + union + { + __IOM uint32_t GWIDC32; /*!< (@ 0x00000C80) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC32_b; + }; + + union + { + __IOM uint32_t GWIDC33; /*!< (@ 0x00000C84) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC33_b; + }; + + union + { + __IOM uint32_t GWIDC34; /*!< (@ 0x00000C88) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC34_b; + }; + + union + { + __IOM uint32_t GWIDC35; /*!< (@ 0x00000C8C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC35_b; + }; + + union + { + __IOM uint32_t GWIDC36; /*!< (@ 0x00000C90) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC36_b; + }; + + union + { + __IOM uint32_t GWIDC37; /*!< (@ 0x00000C94) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC37_b; + }; + + union + { + __IOM uint32_t GWIDC38; /*!< (@ 0x00000C98) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC38_b; + }; + + union + { + __IOM uint32_t GWIDC39; /*!< (@ 0x00000C9C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC39_b; + }; + + union + { + __IOM uint32_t GWIDC40; /*!< (@ 0x00000CA0) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC40_b; + }; + + union + { + __IOM uint32_t GWIDC41; /*!< (@ 0x00000CA4) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC41_b; + }; + + union + { + __IOM uint32_t GWIDC42; /*!< (@ 0x00000CA8) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC42_b; + }; + + union + { + __IOM uint32_t GWIDC43; /*!< (@ 0x00000CAC) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC43_b; + }; + + union + { + __IOM uint32_t GWIDC44; /*!< (@ 0x00000CB0) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC44_b; + }; + + union + { + __IOM uint32_t GWIDC45; /*!< (@ 0x00000CB4) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC45_b; + }; + + union + { + __IOM uint32_t GWIDC46; /*!< (@ 0x00000CB8) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC46_b; + }; + + union + { + __IOM uint32_t GWIDC47; /*!< (@ 0x00000CBC) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC47_b; + }; + + union + { + __IOM uint32_t GWIDC48; /*!< (@ 0x00000CC0) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC48_b; + }; + + union + { + __IOM uint32_t GWIDC49; /*!< (@ 0x00000CC4) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC49_b; + }; + + union + { + __IOM uint32_t GWIDC50; /*!< (@ 0x00000CC8) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC50_b; + }; + + union + { + __IOM uint32_t GWIDC51; /*!< (@ 0x00000CCC) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC51_b; + }; + + union + { + __IOM uint32_t GWIDC52; /*!< (@ 0x00000CD0) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC52_b; + }; + + union + { + __IOM uint32_t GWIDC53; /*!< (@ 0x00000CD4) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC53_b; + }; + + union + { + __IOM uint32_t GWIDC54; /*!< (@ 0x00000CD8) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC54_b; + }; + + union + { + __IOM uint32_t GWIDC55; /*!< (@ 0x00000CDC) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC55_b; + }; + + union + { + __IOM uint32_t GWIDC56; /*!< (@ 0x00000CE0) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC56_b; + }; + + union + { + __IOM uint32_t GWIDC57; /*!< (@ 0x00000CE4) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC57_b; + }; + + union + { + __IOM uint32_t GWIDC58; /*!< (@ 0x00000CE8) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC58_b; + }; + + union + { + __IOM uint32_t GWIDC59; /*!< (@ 0x00000CEC) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC59_b; + }; + + union + { + __IOM uint32_t GWIDC60; /*!< (@ 0x00000CF0) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC60_b; + }; + + union + { + __IOM uint32_t GWIDC61; /*!< (@ 0x00000CF4) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC61_b; + }; + + union + { + __IOM uint32_t GWIDC62; /*!< (@ 0x00000CF8) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC62_b; + }; + + union + { + __IOM uint32_t GWIDC63; /*!< (@ 0x00000CFC) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC63_b; + }; + + union + { + __IOM uint32_t GWIDC64; /*!< (@ 0x00000D00) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC64_b; + }; + __IM uint32_t RESERVED23[191]; + + union + { + __IOM uint32_t GWRDCN; /*!< (@ 0x00001000) GWCA Received Data Counter Register (GWRDCN) */ + + struct + { + __IOM uint32_t RDN : 32; /*!< [31..0] RDN */ + } GWRDCN_b; + }; + + union + { + __IOM uint32_t GWTDCN; /*!< (@ 0x00001004) GWCA Transmitted Data Counter Register (GWTDCN) */ + + struct + { + __IOM uint32_t TDN : 32; /*!< [31..0] TDN */ + } GWTDCN_b; + }; + + union + { + __IOM uint32_t GWTSCN; /*!< (@ 0x00001008) GWCA Timestamp Counter Register (GWTSCN) */ + + struct + { + __IOM uint32_t TN : 32; /*!< [31..0] TN */ + } GWTSCN_b; + }; + + union + { + __IOM uint32_t GWTSOVFECN; /*!< (@ 0x0000100C) GWCA Timestamp Overflow Error Counter Register + * (GWTSOVFECN) */ + + struct + { + __IOM uint32_t TSOVFEN : 16; /*!< [15..0] TSOVFEN */ + uint32_t : 16; + } GWTSOVFECN_b; + }; + + union + { + __IOM uint32_t GWUSMFSECN; /*!< (@ 0x00001010) GWCA Under Switch Minimum Frame Size Error Counter + * Register (GWUSMFSECN) */ + + struct + { + __IOM uint32_t USMFSEN : 16; /*!< [15..0] USMFSEN */ + uint32_t : 16; + } GWUSMFSECN_b; + }; + + union + { + __IOM uint32_t GWTFECN; /*!< (@ 0x00001014) GWCA TAG Filtering Error Counter Register (GWTFECN) */ + + struct + { + __IOM uint32_t TFEN : 16; /*!< [15..0] TFEN */ + uint32_t : 16; + } GWTFECN_b; + }; + + union + { + __IOM uint32_t GWSEQECN; /*!< (@ 0x00001018) GWCA Sequence Error Counter Register (GWSEQECN) */ + + struct + { + __IOM uint32_t SEQEN : 16; /*!< [15..0] SEQEN */ + uint32_t : 16; + } GWSEQECN_b; + }; + __IM uint32_t RESERVED24; + + union + { + __IOM uint32_t GWTXDNECN; /*!< (@ 0x00001020) GWCA TX Descriptor Number Error Counter Register + * (GWTXDNECN) */ + + struct + { + __IOM uint32_t TXDNEN : 16; /*!< [15..0] TXDNEN */ + uint32_t : 16; + } GWTXDNECN_b; + }; + + union + { + __IOM uint32_t GWFSECN; /*!< (@ 0x00001024) GWCA Frame Size Error Counter Register (GWFSECN) */ + + struct + { + __IOM uint32_t FSEN : 16; /*!< [15..0] FSEN */ + uint32_t : 16; + } GWFSECN_b; + }; + + union + { + __IOM uint32_t GWTDFECN; /*!< (@ 0x00001028) GWCA Timestamp Descriptor Full Error Counter + * Register (GWTDFECN) */ + + struct + { + __IOM uint32_t TDFEN : 16; /*!< [15..0] TDFEN */ + uint32_t : 16; + } GWTDFECN_b; + }; + + union + { + __IOM uint32_t GWTSDNECN; /*!< (@ 0x0000102C) GWCA Timestamp Descriptor Number Error Counter + * Register (GWTSDNECN) */ + + struct + { + __IOM uint32_t TSDNEN : 16; /*!< [15..0] TSDNEN */ + uint32_t : 16; + } GWTSDNECN_b; + }; + + union + { + __IOM uint32_t GWDQOECN; /*!< (@ 0x00001030) GWCA Descriptor Queue Overflow Error Counter + * Register (GWDQOECN) */ + + struct + { + __IOM uint32_t DQOEN : 16; /*!< [15..0] DQOEN */ + uint32_t : 16; + } GWDQOECN_b; + }; + + union + { + __IOM uint32_t GWDQSECN; /*!< (@ 0x00001034) GWCA Descriptor Queue Security Error Counter + * Register (GWDQSECN) */ + + struct + { + __IOM uint32_t DQSEN : 16; /*!< [15..0] DQSEN */ + uint32_t : 16; + } GWDQSECN_b; + }; + + union + { + __IOM uint32_t GWDFECN; /*!< (@ 0x00001038) GWCA Descriptor Full Error Counter Register (GWDFECN) */ + + struct + { + __IOM uint32_t DFEN : 16; /*!< [15..0] DFEN */ + uint32_t : 16; + } GWDFECN_b; + }; + + union + { + __IOM uint32_t GWDSECN; /*!< (@ 0x0000103C) GWCA Descriptor Security Error Counter Register + * (GWDSECN) */ + + struct + { + __IOM uint32_t DSEN : 16; /*!< [15..0] DSEN */ + uint32_t : 16; + } GWDSECN_b; + }; + + union + { + __IOM uint32_t GWDSZECN; /*!< (@ 0x00001040) GWCA Data Size Error Counter Register (GWDSZECN) */ + + struct + { + __IOM uint32_t DSZEN : 16; /*!< [15..0] DSZEN */ + uint32_t : 16; + } GWDSZECN_b; + }; + + union + { + __IOM uint32_t GWDCTECN; /*!< (@ 0x00001044) GWCA Descriptor Chain Type Error Counter Register + * (GWDCTECN) */ + + struct + { + __IOM uint32_t DCTEN : 16; /*!< [15..0] DCTEN */ + uint32_t : 16; + } GWDCTECN_b; + }; + + union + { + __IOM uint32_t GWRXDNECN; /*!< (@ 0x00001048) GWCA RX Descriptor Number Error Counter Register + * (GWRXDNECN) */ + + struct + { + __IOM uint32_t RXDNEN : 16; /*!< [15..0] RXDNEN */ + uint32_t : 16; + } GWRXDNECN_b; + }; + __IM uint32_t RESERVED25[45]; + __IOM uint32_t GWDIS0; /*!< (@ 0x00001100) GWCA Data Interrupt Status Register i (GWDISi) + * (i = 0, 1) */ + __IOM uint32_t GWDIE0; /*!< (@ 0x00001104) GWCA Data Interrupt Enable Register i (GWDIEi) + * (i = 0, 1) */ + __IOM uint32_t GWDID0; /*!< (@ 0x00001108) GWCA Data Interrupt Disable Register i (GWDIDi) + * (i = 0, 1) */ + __IOM uint32_t GWDIDS0; /*!< (@ 0x0000110C) GWCA Data Interrupt Delayed Status Register i + * (GWDIDSi) (i = 0, 1) */ + __IOM uint32_t GWDIS1; /*!< (@ 0x00001110) GWCA Data Interrupt Status Register i (GWDISi) + * (i = 0, 1) */ + __IOM uint32_t GWDIE1; /*!< (@ 0x00001114) GWCA Data Interrupt Enable Register i (GWDIEi) + * (i = 0, 1) */ + __IOM uint32_t GWDID1; /*!< (@ 0x00001118) GWCA Data Interrupt Disable Register i (GWDIDi) + * (i = 0, 1) */ + __IOM uint32_t GWDIDS1; /*!< (@ 0x0000111C) GWCA Data Interrupt Delayed Status Register i + * (GWDIDSi) (i = 0, 1) */ + __IM uint32_t RESERVED26[24]; + + union + { + __IOM uint32_t GWTSDIS; /*!< (@ 0x00001180) GWCA Timestamp Data Interrupt Status Register + * (GWTSDIS) */ + + struct + { + __IOM uint32_t TSDIS0 : 1; /*!< [0..0] TSDIS0 */ + __IOM uint32_t TSDIS1 : 1; /*!< [1..1] TSDIS1 */ + uint32_t : 30; + } GWTSDIS_b; + }; + + union + { + __IOM uint32_t GWTSDIE; /*!< (@ 0x00001184) GWCA Timestamp Data Interrupt Enable Register + * (GWTSDIE) */ + + struct + { + __IOM uint32_t TSDIE0 : 1; /*!< [0..0] TSDIE0 */ + __IOM uint32_t TSDIE1 : 1; /*!< [1..1] TSDIE1 */ + uint32_t : 30; + } GWTSDIE_b; + }; + + union + { + __IOM uint32_t GWTSDID; /*!< (@ 0x00001188) GWCA Timestamp Data Interrupt Disable Register + * (GWTSDID) */ + + struct + { + __IOM uint32_t TSDID0 : 1; /*!< [0..0] TSDID0 */ + __IOM uint32_t TSDID1 : 1; /*!< [1..1] TSDID1 */ + uint32_t : 30; + } GWTSDID_b; + }; + __IM uint32_t RESERVED27; + + union + { + __IOM uint32_t GWEIS0; /*!< (@ 0x00001190) GWCA Error Interrupt Status Register 0 (GWEIS0) */ + + struct + { + __IOM uint32_t AES : 1; /*!< [0..0] AES */ + __IOM uint32_t DECCES : 1; /*!< [1..1] DECCES */ + __IOM uint32_t TECCES : 1; /*!< [2..2] TECCES */ + __IOM uint32_t PECCES : 1; /*!< [3..3] PECCES */ + __IOM uint32_t DSECCES : 1; /*!< [4..4] DSECCES */ + __IOM uint32_t MECCES : 1; /*!< [5..5] MECCES */ + __IOM uint32_t AECCES : 1; /*!< [6..6] AECCES */ + __IOM uint32_t TSECCES : 1; /*!< [7..7] TSECCES */ + __IOM uint32_t L23UECCES : 1; /*!< [8..8] L23UECCES */ + __IOM uint32_t TSOVFES : 1; /*!< [9..9] TSOVFES */ + __IOM uint32_t USMFSES : 1; /*!< [10..10] USMFSES */ + __IOM uint32_t TFES : 1; /*!< [11..11] TFES */ + __IOM uint32_t SEQES : 1; /*!< [12..12] SEQES */ + uint32_t : 1; + __IOM uint32_t TXDNES : 1; /*!< [14..14] TXDNES */ + __IOM uint32_t TSHES : 1; /*!< [15..15] TSHES */ + __IOM uint32_t FSES0 : 1; /*!< [16..16] FSES0 */ + __IOM uint32_t FSES1 : 1; /*!< [17..17] FSES1 */ + __IOM uint32_t FSES2 : 1; /*!< [18..18] FSES2 */ + __IOM uint32_t FSES3 : 1; /*!< [19..19] FSES3 */ + __IOM uint32_t FSES4 : 1; /*!< [20..20] FSES4 */ + __IOM uint32_t FSES5 : 1; /*!< [21..21] FSES5 */ + __IOM uint32_t FSES6 : 1; /*!< [22..22] FSES6 */ + __IOM uint32_t FSES7 : 1; /*!< [23..23] FSES7 */ + __IOM uint32_t TDFES0 : 1; /*!< [24..24] TDFES0 */ + __IOM uint32_t TDFES1 : 1; /*!< [25..25] TDFES1 */ + uint32_t : 2; + __IOM uint32_t TSDNES0 : 1; /*!< [28..28] TSDNES0 */ + __IOM uint32_t TSDNES1 : 1; /*!< [29..29] TSDNES1 */ + uint32_t : 2; + } GWEIS0_b; + }; + + union + { + __IOM uint32_t GWEIE0; /*!< (@ 0x00001194) GWCA Error Interrupt Enable Register 0 (GWEIE0) */ + + struct + { + __IOM uint32_t AEE : 1; /*!< [0..0] AEE */ + __IOM uint32_t DECCEE : 1; /*!< [1..1] DECCEE */ + __IOM uint32_t TECCEE : 1; /*!< [2..2] TECCEE */ + __IOM uint32_t PECCEE : 1; /*!< [3..3] PECCEE */ + __IOM uint32_t DSECCEE : 1; /*!< [4..4] DSECCEE */ + __IOM uint32_t MECCEE : 1; /*!< [5..5] MECCEE */ + __IOM uint32_t AECCEE : 1; /*!< [6..6] AECCEE */ + __IOM uint32_t TSECCEE : 1; /*!< [7..7] TSECCEE */ + __IOM uint32_t L23UECCEE : 1; /*!< [8..8] L23UECCEE */ + __IOM uint32_t TSOVFEE : 1; /*!< [9..9] TSOVFEE */ + __IOM uint32_t USMFSEE : 1; /*!< [10..10] USMFSEE */ + __IOM uint32_t TFEE : 1; /*!< [11..11] TFEE */ + __IOM uint32_t SEQEE : 1; /*!< [12..12] SEQEE */ + uint32_t : 1; + __IOM uint32_t TXDNEE : 1; /*!< [14..14] TXDNEE */ + __IOM uint32_t TSHEE : 1; /*!< [15..15] TSHEE */ + __IOM uint32_t FSEE0 : 1; /*!< [16..16] FSEE0 */ + __IOM uint32_t FSEE1 : 1; /*!< [17..17] FSEE1 */ + __IOM uint32_t FSEE2 : 1; /*!< [18..18] FSEE2 */ + __IOM uint32_t FSEE3 : 1; /*!< [19..19] FSEE3 */ + __IOM uint32_t FSEE4 : 1; /*!< [20..20] FSEE4 */ + __IOM uint32_t FSEE5 : 1; /*!< [21..21] FSEE5 */ + __IOM uint32_t FSEE6 : 1; /*!< [22..22] FSEE6 */ + __IOM uint32_t FSEE7 : 1; /*!< [23..23] FSEE7 */ + __IOM uint32_t TDFEE0 : 1; /*!< [24..24] TDFEE0 */ + __IOM uint32_t TDFEE1 : 1; /*!< [25..25] TDFEE1 */ + uint32_t : 2; + __IOM uint32_t TSDNEE0 : 1; /*!< [28..28] TSDNEE0 */ + __IOM uint32_t TSDNEE1 : 1; /*!< [29..29] TSDNEE1 */ + uint32_t : 2; + } GWEIE0_b; + }; + + union + { + __IOM uint32_t GWEID0; /*!< (@ 0x00001198) GWCA Error Interrupt Disable Register 0 (GWEID0) */ + + struct + { + __IOM uint32_t AED : 1; /*!< [0..0] AED */ + __IOM uint32_t TECCED : 1; /*!< [1..1] TECCED */ + __IOM uint32_t DECCED : 1; /*!< [2..2] DECCED */ + __IOM uint32_t PECCED : 1; /*!< [3..3] PECCED */ + __IOM uint32_t DSECCED : 1; /*!< [4..4] DSECCED */ + __IOM uint32_t MECCED : 1; /*!< [5..5] MECCED */ + __IOM uint32_t AECCED : 1; /*!< [6..6] AECCED */ + __IOM uint32_t TSECCED : 1; /*!< [7..7] TSECCED */ + __IOM uint32_t L23UECCED : 1; /*!< [8..8] L23UECCED */ + __IOM uint32_t TSOVFED : 1; /*!< [9..9] TSOVFED */ + __IOM uint32_t USMFSED : 1; /*!< [10..10] USMFSED */ + __IOM uint32_t TFED : 1; /*!< [11..11] TFED */ + __IOM uint32_t SEQED : 1; /*!< [12..12] SEQED */ + __IOM uint32_t IIPED : 1; /*!< [13..13] IIPED */ + __IOM uint32_t TXDNED : 1; /*!< [14..14] TXDNED */ + __IOM uint32_t TSHED : 1; /*!< [15..15] TSHED */ + __IOM uint32_t FSED0 : 1; /*!< [16..16] FSED0 */ + __IOM uint32_t FSED1 : 1; /*!< [17..17] FSED1 */ + __IOM uint32_t FSED2 : 1; /*!< [18..18] FSED2 */ + __IOM uint32_t FSED3 : 1; /*!< [19..19] FSED3 */ + __IOM uint32_t FSED4 : 1; /*!< [20..20] FSED4 */ + __IOM uint32_t FSED5 : 1; /*!< [21..21] FSED5 */ + __IOM uint32_t FSED6 : 1; /*!< [22..22] FSED6 */ + __IOM uint32_t FSED7 : 1; /*!< [23..23] FSED7 */ + __IOM uint32_t TDFED0 : 1; /*!< [24..24] TDFED0 */ + __IOM uint32_t TDFED1 : 1; /*!< [25..25] TDFED1 */ + uint32_t : 2; + __IOM uint32_t TSDNED0 : 1; /*!< [28..28] TSDNED0 */ + __IOM uint32_t TSDNED1 : 1; /*!< [29..29] TSDNED1 */ + uint32_t : 2; + } GWEID0_b; + }; + __IM uint32_t RESERVED28; + + union + { + __IOM uint32_t GWEIS1; /*!< (@ 0x000011A0) GWCA Error Interrupt Status Register 1 (GWEIS1) */ + + struct + { + __IOM uint32_t DQOES0 : 1; /*!< [0..0] DQOES0 */ + __IOM uint32_t DQOES1 : 1; /*!< [1..1] DQOES1 */ + __IOM uint32_t DQOES2 : 1; /*!< [2..2] DQOES2 */ + __IOM uint32_t DQOES3 : 1; /*!< [3..3] DQOES3 */ + __IOM uint32_t DQOES4 : 1; /*!< [4..4] DQOES4 */ + __IOM uint32_t DQOES5 : 1; /*!< [5..5] DQOES5 */ + __IOM uint32_t DQOES6 : 1; /*!< [6..6] DQOES6 */ + __IOM uint32_t DQOES7 : 1; /*!< [7..7] DQOES7 */ + uint32_t : 8; + __IOM uint32_t DQSES0 : 1; /*!< [16..16] DQSES0 */ + __IOM uint32_t DQSES1 : 1; /*!< [17..17] DQSES1 */ + __IOM uint32_t DQSES2 : 1; /*!< [18..18] DQSES2 */ + __IOM uint32_t DQSES3 : 1; /*!< [19..19] DQSES3 */ + __IOM uint32_t DQSES4 : 1; /*!< [20..20] DQSES4 */ + __IOM uint32_t DQSES5 : 1; /*!< [21..21] DQSES5 */ + __IOM uint32_t DQSES6 : 1; /*!< [22..22] DQSES6 */ + __IOM uint32_t DQSES7 : 1; /*!< [23..23] DQSES7 */ + uint32_t : 8; + } GWEIS1_b; + }; + + union + { + __IOM uint32_t GWEIE1; /*!< (@ 0x000011A4) GWCA Error Interrupt Enable Register 1 (GWEIE1) */ + + struct + { + __IOM uint32_t DQOEE0 : 1; /*!< [0..0] DQOEE0 */ + __IOM uint32_t DQOEE1 : 1; /*!< [1..1] DQOEE1 */ + __IOM uint32_t DQOEE2 : 1; /*!< [2..2] DQOEE2 */ + __IOM uint32_t DQOEE3 : 1; /*!< [3..3] DQOEE3 */ + __IOM uint32_t DQOEE4 : 1; /*!< [4..4] DQOEE4 */ + __IOM uint32_t DQOEE5 : 1; /*!< [5..5] DQOEE5 */ + __IOM uint32_t DQOEE6 : 1; /*!< [6..6] DQOEE6 */ + __IOM uint32_t DQOEE7 : 1; /*!< [7..7] DQOEE7 */ + uint32_t : 8; + __IOM uint32_t DQSEE0 : 1; /*!< [16..16] DQSEE0 */ + __IOM uint32_t DQSEE1 : 1; /*!< [17..17] DQSEE1 */ + __IOM uint32_t DQSEE2 : 1; /*!< [18..18] DQSEE2 */ + __IOM uint32_t DQSEE3 : 1; /*!< [19..19] DQSEE3 */ + __IOM uint32_t DQSEE4 : 1; /*!< [20..20] DQSEE4 */ + __IOM uint32_t DQSEE5 : 1; /*!< [21..21] DQSEE5 */ + __IOM uint32_t DQSEE6 : 1; /*!< [22..22] DQSEE6 */ + __IOM uint32_t DQSEE7 : 1; /*!< [23..23] DQSEE7 */ + uint32_t : 8; + } GWEIE1_b; + }; + + union + { + __IOM uint32_t GWEID1; /*!< (@ 0x000011A8) GWCA Error Interrupt Disable Register 1 (GWEID1) */ + + struct + { + __IOM uint32_t DQOED0 : 1; /*!< [0..0] DQOED0 */ + __IOM uint32_t DQOED1 : 1; /*!< [1..1] DQOED1 */ + __IOM uint32_t DQOED2 : 1; /*!< [2..2] DQOED2 */ + __IOM uint32_t DQOED3 : 1; /*!< [3..3] DQOED3 */ + __IOM uint32_t DQOED4 : 1; /*!< [4..4] DQOED4 */ + __IOM uint32_t DQOED5 : 1; /*!< [5..5] DQOED5 */ + __IOM uint32_t DQOED6 : 1; /*!< [6..6] DQOED6 */ + __IOM uint32_t DQOED7 : 1; /*!< [7..7] DQOED7 */ + uint32_t : 8; + __IOM uint32_t DQSED0 : 1; /*!< [16..16] DQSED0 */ + __IOM uint32_t DQSED1 : 1; /*!< [17..17] DQSED1 */ + __IOM uint32_t DQSED2 : 1; /*!< [18..18] DQSED2 */ + __IOM uint32_t DQSED3 : 1; /*!< [19..19] DQSED3 */ + __IOM uint32_t DQSED4 : 1; /*!< [20..20] DQSED4 */ + __IOM uint32_t DQSED5 : 1; /*!< [21..21] DQSED5 */ + __IOM uint32_t DQSED6 : 1; /*!< [22..22] DQSED6 */ + __IOM uint32_t DQSED7 : 1; /*!< [23..23] DQSED7 */ + uint32_t : 8; + } GWEID1_b; + }; + __IM uint32_t RESERVED29[21]; + __IOM uint32_t GWEIS20; /*!< (@ 0x00001200) GWCA Error Interrupt Status Register 2i (GWEIS2i) + * (i = 0, 1) */ + __IOM uint32_t GWEIE20; /*!< (@ 0x00001204) GWCA Error Interrupt Enable Register 2i (GWEIE2i) + * (i = 0, 1) */ + __IOM uint32_t GWEID20; /*!< (@ 0x00001208) GWCA Error Interrupt Disable Register 2i (GWEID2i) + * (i = 0, 1) */ + __IM uint32_t RESERVED30; + __IOM uint32_t GWEIS21; /*!< (@ 0x00001210) GWCA Error Interrupt Status Register 2i (GWEIS2i) + * (i = 0, 1) */ + __IOM uint32_t GWEIE21; /*!< (@ 0x00001214) GWCA Error Interrupt Enable Register 2i (GWEIE2i) + * (i = 0, 1) */ + __IOM uint32_t GWEID21; /*!< (@ 0x00001218) GWCA Error Interrupt Disable Register 2i (GWEID2i) + * (i = 0, 1) */ + __IM uint32_t RESERVED31[25]; + + union + { + __IOM uint32_t GWEIS3; /*!< (@ 0x00001280) GWCA Error Interrupt Status Register 3 (GWEIS3) */ + + struct + { + __IOM uint32_t IAOES0 : 1; /*!< [0..0] IAOES0 */ + __IOM uint32_t IAOES1 : 1; /*!< [1..1] IAOES1 */ + __IOM uint32_t IAOES2 : 1; /*!< [2..2] IAOES2 */ + __IOM uint32_t IAOES3 : 1; /*!< [3..3] IAOES3 */ + __IOM uint32_t IAOES4 : 1; /*!< [4..4] IAOES4 */ + uint32_t : 27; + } GWEIS3_b; + }; + + union + { + __IOM uint32_t GWEIE3; /*!< (@ 0x00001284) GWCA Error Interrupt Enable Register 3 (GWEIE3) */ + + struct + { + __IOM uint32_t IAOEE0 : 1; /*!< [0..0] IAOEE0 */ + __IOM uint32_t IAOEE1 : 1; /*!< [1..1] IAOEE1 */ + __IOM uint32_t IAOEE2 : 1; /*!< [2..2] IAOEE2 */ + __IOM uint32_t IAOEE3 : 1; /*!< [3..3] IAOEE3 */ + __IOM uint32_t IAOEE4 : 1; /*!< [4..4] IAOEE4 */ + uint32_t : 27; + } GWEIE3_b; + }; + + union + { + __IOM uint32_t GWEID3; /*!< (@ 0x00001288) GWCA Error Interrupt Disable Register 3 (GWEID3) */ + + struct + { + __IOM uint32_t IAOED0 : 1; /*!< [0..0] IAOED0 */ + __IOM uint32_t IAOED1 : 1; /*!< [1..1] IAOED1 */ + __IOM uint32_t IAOED2 : 1; /*!< [2..2] IAOED2 */ + __IOM uint32_t IAOED3 : 1; /*!< [3..3] IAOED3 */ + __IOM uint32_t IAOED4 : 1; /*!< [4..4] IAOED4 */ + uint32_t : 27; + } GWEID3_b; + }; + __IM uint32_t RESERVED32; + + union + { + __IOM uint32_t GWEIS4; /*!< (@ 0x00001290) GWCA Error Interrupt Status Register 4 (GWEIS4) */ + + struct + { + __IOM uint32_t DSSES : 1; /*!< [0..0] DSSES */ + __IOM uint32_t DSSEIOS : 1; /*!< [1..1] DSSEIOS */ + uint32_t : 6; + __IOM uint32_t DSSECN : 6; /*!< [13..8] DSSECN */ + uint32_t : 2; + __IOM uint32_t DSES : 1; /*!< [16..16] DSES */ + __IOM uint32_t DSEIOS : 1; /*!< [17..17] DSEIOS */ + uint32_t : 6; + __IOM uint32_t DSECN : 6; /*!< [29..24] DSECN */ + uint32_t : 2; + } GWEIS4_b; + }; + + union + { + __IOM uint32_t GWEIE4; /*!< (@ 0x00001294) GWCA Error Interrupt Enable Register 4 (GWEIE4) */ + + struct + { + __IOM uint32_t DSSEE : 1; /*!< [0..0] DSSEE */ + __IOM uint32_t DSSEIOE : 1; /*!< [1..1] DSSEIOE */ + uint32_t : 14; + __IOM uint32_t DSEE : 1; /*!< [16..16] DSEE */ + __IOM uint32_t DSEIOE : 1; /*!< [17..17] DSEIOE */ + uint32_t : 14; + } GWEIE4_b; + }; + + union + { + __IOM uint32_t GWEID4; /*!< (@ 0x00001298) GWCA Error Interrupt Disable Register 4 (GWEID4) */ + + struct + { + __IOM uint32_t DSSED : 1; /*!< [0..0] DSSED */ + __IOM uint32_t DSSEIOD : 1; /*!< [1..1] DSSEIOD */ + uint32_t : 14; + __IOM uint32_t DSED : 1; /*!< [16..16] DSED */ + __IOM uint32_t DSEIOD : 1; /*!< [17..17] DSEIOD */ + uint32_t : 14; + } GWEID4_b; + }; + __IM uint32_t RESERVED33; + + union + { + __IOM uint32_t GWEIS5; /*!< (@ 0x000012A0) GWCA Error Interrupt Status Register 5 (GWEIS5) */ + + struct + { + __IOM uint32_t DCTES : 1; /*!< [0..0] DCTES */ + __IOM uint32_t DCTEIOS : 1; /*!< [1..1] DCTEIOS */ + uint32_t : 6; + __IOM uint32_t DCTECN : 6; /*!< [13..8] DCTECN */ + uint32_t : 2; + __IOM uint32_t RXDNES : 1; /*!< [16..16] RXDNES */ + __IOM uint32_t RXDNEIOS : 1; /*!< [17..17] RXDNEIOS */ + uint32_t : 14; + } GWEIS5_b; + }; + + union + { + __IOM uint32_t GWEIE5; /*!< (@ 0x000012A4) GWCA Error Interrupt Enable Register 5 (GWEIE5) */ + + struct + { + __IOM uint32_t DCTEE : 1; /*!< [0..0] DCTEE */ + __IOM uint32_t DCTEIOE : 1; /*!< [1..1] DCTEIOE */ + uint32_t : 14; + __IOM uint32_t RXDNEE : 1; /*!< [16..16] RXDNEE */ + __IOM uint32_t RXDNEIOE : 1; /*!< [17..17] RXDNEIOE */ + uint32_t : 14; + } GWEIE5_b; + }; + + union + { + __IOM uint32_t GWEID5; /*!< (@ 0x000012A8) GWCA Error Interrupt Disable Register 5 (GWEID5) */ + + struct + { + __IOM uint32_t DCTED : 1; /*!< [0..0] DCTED */ + __IOM uint32_t DCTEIOD : 1; /*!< [1..1] DCTEIOD */ + uint32_t : 13; + __IOM uint32_t RXDNED : 1; /*!< [15..15] RXDNED */ + __IOM uint32_t RXDNEIOD : 1; /*!< [16..16] RXDNEIOD */ + uint32_t : 15; + } GWEID5_b; + }; +} R_GWCA0_Type; /*!< Size = 4780 (0x12ac) */ + +/* =========================================================================================================================== */ +/* ================ R_IPC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Inter-Processor Communication (R_IPC) + */ + +typedef struct /*!< (@ 0x40020000) R_IPC Structure */ +{ + union + { + __IOM uint32_t IPCSEM[16]; /*!< (@ 0x00000000) Semaphore Registers */ + + struct + { + __IOM uint32_t LOCK : 1; /*!< [0..0] Indicates the shared resource is locked */ + uint32_t : 31; + } IPCSEM_b[16]; + }; + __IM uint32_t RESERVED[16]; + __IOM R_IPC_IPCNMI_Type IPC0NMI; /*!< (@ 0x00000080) Inter-Processor NMI Registers */ + __IOM R_IPC_IPCNMI_Type IPC1NMI; /*!< (@ 0x00000090) Inter-Processor NMI Registers */ + __IM uint32_t RESERVED1[8]; + __IOM R_IPC_IPC_Type IPC0; /*!< (@ 0x000000C0) Inter-Processor Registers */ + __IOM R_IPC_IPC_Type IPC1; /*!< (@ 0x00000100) Inter-Processor Registers */ +} R_IPC_Type; /*!< Size = 320 (0x140) */ + +/* =========================================================================================================================== */ +/* ================ R_MFWD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Message Forwarding Engine (R_MFWD) + */ + +typedef struct /*!< (@ 0x403C0000) R_MFWD Structure */ +{ + union + { + __IOM uint32_t FWGC; /*!< (@ 0x00000000) General Configuration Register */ + + struct + { + __IOM uint32_t SVM : 2; /*!< [1..0] Switch VLAN Mode */ + uint32_t : 30; + } FWGC_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t FWTTC0; /*!< (@ 0x00000010) TAG TPID Configuration Register 0 */ + + struct + { + __IOM uint32_t CTT : 16; /*!< [15..0] C-TAG TPID */ + __IOM uint32_t STT : 16; /*!< [31..16] S-TAG TPID */ + } FWTTC0_b; + }; + + union + { + __IOM uint32_t FWTTC1; /*!< (@ 0x00000014) TAG TPID Configuration Register 1 */ + + struct + { + __IOM uint32_t RTT : 16; /*!< [15..0] R-TAG TPID */ + uint32_t : 16; + } FWTTC1_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t FWCEPTC; /*!< (@ 0x00000020) CPU Exceptional Path Target Configuration Register */ + + struct + { + __IOM uint32_t EPCSD : 7; /*!< [6..0] Exceptional Path CPU Sub Destination */ + uint32_t : 5; + __IOM uint32_t EPIPV : 3; /*!< [14..12] Exceptional Path Internal Priority Value */ + uint32_t : 1; + __IOM uint32_t EPCS : 2; /*!< [17..16] Exceptional Path CPU Select */ + uint32_t : 6; + __IOM uint32_t EPSL : 1; /*!< [24..24] Exceptional Path Security Level */ + uint32_t : 7; + } FWCEPTC_b; + }; + + union + { + __IOM uint32_t FWCEPRC0; /*!< (@ 0x00000024) CPU Exceptional Path Reason Configuration Register + * 0 */ + + struct + { + __IOM uint32_t EPHYEEF : 1; /*!< [0..0] Ethernet PHY Error Exceptional Forwarding */ + __IOM uint32_t EPCRCEEF : 1; /*!< [1..1] Ethernet PCH CRC Error Exceptional Forwarding */ + __IOM uint32_t ENIBEEF : 1; /*!< [2..2] Ethernet Nibble Error Exceptional Forwarding */ + __IOM uint32_t EFCSEEF : 1; /*!< [3..3] Ethernet FCS Error Exceptional Forwarding */ + __IOM uint32_t EFFMEEF : 1; /*!< [4..4] Ethernet Final Fragment Missing Error Exceptional Forwarding */ + __IOM uint32_t ECFSEEF : 1; /*!< [5..5] Ethernet C-Fragment SMD Error Exceptional Forwarding */ + __IOM uint32_t ECFFCEEF : 1; /*!< [6..6] Ethernet C-Fragment FRAG_COUNT Error Exceptional Forwarding */ + __IOM uint32_t ERFFEF : 1; /*!< [7..7] Ethernet RMAC Frame Filtered Exceptional Forwarding */ + __IOM uint32_t ERPOOEF : 1; /*!< [8..8] Ethernet Reception Partially Out of Operation Exceptional + * Forwarding */ + __IOM uint32_t EBOEEF : 1; /*!< [9..9] Ethernet Buffer Overflow Error Exceptional Forwarding */ + __IOM uint32_t EUEEF : 1; /*!< [10..10] Ethernet Undersize Error Exceptional Forwarding */ + __IOM uint32_t EOEEF : 1; /*!< [11..11] Ethernet Oversize Error Exceptional Forwarding */ + __IOM uint32_t ETFEF : 1; /*!< [12..12] Ethernet TAG Filtering Exceptional Forwarding */ + uint32_t : 3; + __IOM uint32_t GAREEEF : 1; /*!< [16..16] GWCA AXI RAM ECC Error Exceptional Forwarding */ + __IOM uint32_t GAXEEF : 1; /*!< [17..17] GWCA AXI Error Exceptional Forwarding */ + __IOM uint32_t GSEQEEF : 1; /*!< [18..18] GWCA Sequence Error Exceptional Forwarding */ + uint32_t : 1; + __IOM uint32_t GTFEF : 1; /*!< [20..20] GWCA TAG Filtering Exceptional Forwarding */ + __IOM uint32_t GDNEEF : 1; /*!< [21..21] GWCA Descriptor Number Error Exceptional Forwarding */ + uint32_t : 2; + __IOM uint32_t DDEEF : 1; /*!< [24..24] Direct Descriptor Error Exceptional Forwarding */ + uint32_t : 1; + __IOM uint32_t DDFSFEF : 1; /*!< [26..26] Direct Descriptor Format Security Filtering Exceptional + * Forwarding */ + uint32_t : 5; + } FWCEPRC0_b; + }; + + union + { + __IOM uint32_t FWCEPRC1; /*!< (@ 0x00000028) CPU Exceptional Path Reason Configuration Register + * 1 */ + + struct + { + __IOM uint32_t FMSDUFEF : 1; /*!< [0..0] MSDU Filtering Exceptional Forwarding */ + uint32_t : 1; + __IOM uint32_t FMTRFEF : 1; /*!< [2..2] Meter Filtering Exceptional Forwarding */ + uint32_t : 5; + __IOM uint32_t FIFFEF : 1; /*!< [8..8] Individual FRER Filtering Exceptional Forwarding */ + __IOM uint32_t FSFFEF : 1; /*!< [9..9] Sequence FRER Filtering Exceptional Forwarding */ + uint32_t : 22; + } FWCEPRC1_b; + }; + + union + { + __IOM uint32_t FWCEPRC2; /*!< (@ 0x0000002C) CPU Exceptional Path Reason Configuration Register + * 2 */ + + struct + { + __IOM uint32_t FLTHUFEF : 1; /*!< [0..0] Layer 3 Unknown Filtering Exceptional Forwarding */ + uint32_t : 2; + __IOM uint32_t FDMACUFEF : 1; /*!< [3..3] Destination MAC Unknown Filtering Exceptional Forwarding */ + __IOM uint32_t FSMACUFEF : 1; /*!< [4..4] Source MAC Unknown Filtering Exceptional Forwarding */ + __IOM uint32_t FVLANUFEF : 1; /*!< [5..5] VLAN Unknown Filtering Exceptional Forwarding */ + uint32_t : 2; + __IOM uint32_t FDDNTFEF : 1; /*!< [8..8] Direct Descriptor No Target Filtering Exceptional Forwarding */ + __IOM uint32_t FLTHNTFEF : 1; /*!< [9..9] Layer 3 No Target Filtering Exceptional Forwarding */ + uint32_t : 1; + __IOM uint32_t FLTWNTFEF : 1; /*!< [11..11] Layer 2 No Target Filtering Exceptional Forwarding */ + __IOM uint32_t FPBNTFEF : 1; /*!< [12..12] Port Based No Target Filtering Exceptional Forwarding */ + uint32_t : 3; + __IOM uint32_t FLTHSLFEF : 1; /*!< [16..16] Layer 3 Source Lock Filtering Exceptional Forwarding */ + uint32_t : 2; + __IOM uint32_t FDMACSLFEF : 1; /*!< [19..19] Destination MAC Source Lock Filtering Exceptional Forwarding */ + __IOM uint32_t FSMACSLFEF : 1; /*!< [20..20] Source MAC Source Lock Filtering Exceptional Forwarding */ + __IOM uint32_t FVLANSLFEF : 1; /*!< [21..21] VLAN Source Lock Filtering Exceptional Forwarding */ + uint32_t : 4; + __IOM uint32_t FWMFEF : 1; /*!< [26..26] Watermark Filtering Exceptional Forwarding */ + uint32_t : 5; + } FWCEPRC2_b; + }; + + union + { + __IOM uint32_t FWCLPTC; /*!< (@ 0x00000030) CPU Learning Path Target Configuration Register */ + + struct + { + __IOM uint32_t LPCSD : 7; /*!< [6..0] Learning Path CPU Sub Destination */ + uint32_t : 5; + __IOM uint32_t LPIPV : 3; /*!< [14..12] Learning Path Internal Priority Value */ + uint32_t : 1; + __IOM uint32_t LPCS : 2; /*!< [17..16] Learning Path CPU Select */ + uint32_t : 6; + __IOM uint32_t LPSL : 1; /*!< [24..24] Learning Path Security Level */ + uint32_t : 7; + } FWCLPTC_b; + }; + + union + { + __IOM uint32_t FWCLPRC; /*!< (@ 0x00000034) CPU Learning Path Reason Configuration Register */ + + struct + { + __IOM uint32_t USIDLF : 1; /*!< [0..0] Unknown Stream ID Learning Forwarding */ + uint32_t : 3; + __IOM uint32_t UDMACLF : 1; /*!< [4..4] Unknown Destination MAC Learning Forwarding */ + __IOM uint32_t USMACLF : 1; /*!< [5..5] Unknown Source MAC Learning Forwarding */ + __IOM uint32_t UPSMACLF : 1; /*!< [6..6] Unknown Port for Source MAC Learning Forwarding */ + __IOM uint32_t UVLANLF : 1; /*!< [7..7] Unknown VLAN Learning Forwarding */ + uint32_t : 24; + } FWCLPRC_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t FWCMPTC; /*!< (@ 0x00000040) CPU Mirroring Path Target Configuration Register */ + + struct + { + __IOM uint32_t CMPCSD : 7; /*!< [6..0] CPU Mirroring Path CPU Sub Destination */ + uint32_t : 5; + __IOM uint32_t CMPIPV : 3; /*!< [14..12] CPU Mirroring Path Internal Priority Value */ + __IOM uint32_t CMPIPU : 1; /*!< [15..15] CPU Mirroring Path Internal Priority Update */ + __IOM uint32_t CMPCS : 2; /*!< [17..16] CPU Mirroring Path CPU Select */ + uint32_t : 6; + __IOM uint32_t CMPSL : 1; /*!< [24..24] CPU Mirroring Path Security Level */ + uint32_t : 7; + } FWCMPTC_b; + }; + + union + { + __IOM uint32_t FWEMPTC; /*!< (@ 0x00000044) Ethernet Mirroring Path Target Configuration + * Register */ + + struct + { + uint32_t : 12; + __IOM uint32_t EMPIPV : 3; /*!< [14..12] Ethernet Mirroring Path Internal Priority Value */ + __IOM uint32_t EMPIPU : 1; /*!< [15..15] Ethernet Mirroring Path Internal Priority Update */ + __IOM uint32_t EMPPS : 2; /*!< [17..16] Ethernet Mirroring Path CPU Select */ + uint32_t : 6; + __IOM uint32_t EMPSL : 1; /*!< [24..24] Ethernet Mirroring Path Security Level */ + uint32_t : 7; + } FWEMPTC_b; + }; + __IM uint32_t RESERVED3[2]; + + union + { + __IOM uint32_t FWSDMPTC; /*!< (@ 0x00000050) Source-Destination Mirroring Path Target Configuration + * Register */ + + struct + { + __IOM uint32_t SDMPCSD : 7; /*!< [6..0] Source-Destination Mirroring Path CPU Sub Destination */ + uint32_t : 5; + __IOM uint32_t SDMPIPV : 3; /*!< [14..12] Source-Destination Mirroring Path Internal Priority + * Value */ + __IOM uint32_t SDMPIPU : 1; /*!< [15..15] Source-Destination Mirroring Path Internal Priority + * Update */ + __IOM uint32_t SDMPPS : 2; /*!< [17..16] Source-Destination Mirroring Path CPU Select */ + uint32_t : 6; + __IOM uint32_t SDMPSL : 1; /*!< [24..24] Source-Destination Mirroring Path Security Level */ + uint32_t : 7; + } FWSDMPTC_b; + }; + + union + { + __IOM uint32_t FWSDMPVC; /*!< (@ 0x00000054) Source-Destination Mirroring Path Vector Configuration + * Register */ + + struct + { + __IOM uint32_t SDMDV : 7; /*!< [6..0] Source-Destination Mirroring Destination Vector */ + uint32_t : 9; + __IOM uint32_t SDMSV : 7; /*!< [22..16] Source-Destination Mirroring Source Vector */ + uint32_t : 9; + } FWSDMPVC_b; + }; + __IM uint32_t RESERVED4[10]; + + union + { + __IOM uint32_t FWLBWMC0; /*!< (@ 0x00000080) Level Based Watermark Configuration Register + * 0 */ + + struct + { + __IOM uint32_t WMCLPR : 16; /*!< [15..0] Watermark Critical Level Priority Rejected */ + __IOM uint32_t WMFLPR : 16; /*!< [31..16] Watermark Flush Level Priority Rejected */ + } FWLBWMC0_b; + }; + + union + { + __IOM uint32_t FWLBWMC1; /*!< (@ 0x00000084) Level Based Watermark Configuration Register + * 1 */ + + struct + { + __IOM uint32_t WMCLPR : 16; /*!< [15..0] Watermark Critical Level Priority Rejected */ + __IOM uint32_t WMFLPR : 16; /*!< [31..16] Watermark Flush Level Priority Rejected */ + } FWLBWMC1_b; + }; + + union + { + __IOM uint32_t FWLBWMC2; /*!< (@ 0x00000088) Level Based Watermark Configuration Register + * 2 */ + + struct + { + __IOM uint32_t WMCLPR : 16; /*!< [15..0] Watermark Critical Level Priority Rejected */ + __IOM uint32_t WMFLPR : 16; /*!< [31..16] Watermark Flush Level Priority Rejected */ + } FWLBWMC2_b; + }; + __IM uint32_t RESERVED5[29]; + + union + { + __IOM uint32_t FWPC00; /*!< (@ 0x00000100) Port Configuration Register 00 */ + + struct + { + __IOM uint32_t LTHTA : 1; /*!< [0..0] L3 Table Active */ + __IOM uint32_t LTHRUS : 1; /*!< [1..1] L3 Reject Unknown Streams */ + __IOM uint32_t LTHRUSS : 1; /*!< [2..2] L3 Reject Unknown Secure Streams */ + __IOM uint32_t IP4UE : 1; /*!< [3..3] IPv4 UDP Enabled */ + __IOM uint32_t IP4TE : 1; /*!< [4..4] IPv4 TCP Enabled */ + __IOM uint32_t IP4OE : 1; /*!< [5..5] IPv4 Other Enabled */ + __IOM uint32_t IP6UE : 1; /*!< [6..6] IPv6 UDP Enabled */ + __IOM uint32_t IP6TE : 1; /*!< [7..7] IPv6 TCP Enabled */ + __IOM uint32_t IP6OE : 1; /*!< [8..8] IPv6 Other Enabled */ + __IOM uint32_t L2SE : 1; /*!< [9..9] L2 Stream Enable */ + uint32_t : 10; + __IOM uint32_t MACDSA : 1; /*!< [20..20] MAC Destination Search Active */ + __IOM uint32_t MACRUDA : 1; /*!< [21..21] MAC Reject Unknown Destination Addresses */ + __IOM uint32_t MACRUDSA : 1; /*!< [22..22] MAC Reject Unknown Destination Secure Addresses */ + __IOM uint32_t MACSSA : 1; /*!< [23..23] MAC Source Search Active */ + __IOM uint32_t MACRUSA : 1; /*!< [24..24] MAC Reject Unknown Source Addresses */ + __IOM uint32_t MACRUSSA : 1; /*!< [25..25] MAC Reject Unknown Source Secure Addresses */ + __IOM uint32_t MACHLA : 1; /*!< [26..26] MAC Hardware Learning Active */ + __IOM uint32_t MACHMA : 1; /*!< [27..27] MAC Hardware Migration Active */ + __IOM uint32_t VLANSA : 1; /*!< [28..28] VLAN Search Active */ + __IOM uint32_t VLANRU : 1; /*!< [29..29] VLAN Reject Unknown */ + __IOM uint32_t VLANRUS : 1; /*!< [30..30] VLAN Reject Unknown Secure */ + uint32_t : 1; + } FWPC00_b; + }; + + union + { + __IOM uint32_t FWPC10; /*!< (@ 0x00000104) Port Configuration Register 10 */ + + struct + { + __IOM uint32_t DDE : 1; /*!< [0..0] Direct Descriptor Enable */ + __IOM uint32_t DDSL : 1; /*!< [1..1] Direct Descriptor Security Level */ + uint32_t : 14; + __IOM uint32_t LTHFM : 7; /*!< [22..16] Layer 3 Forwarding Mask */ + uint32_t : 9; + } FWPC10_b; + }; + + union + { + __IOM uint32_t FWPC20; /*!< (@ 0x00000108) Port Configuration Register 20 */ + + struct + { + uint32_t : 16; + __IOM uint32_t LTWFM : 7; /*!< [22..16] Layer 2 Forwarding Mask */ + uint32_t : 9; + } FWPC20_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t FWPC01; /*!< (@ 0x00000110) Port Configuration Register 01 */ + + struct + { + __IOM uint32_t LTHTA : 1; /*!< [0..0] L3 Table Active */ + __IOM uint32_t LTHRUS : 1; /*!< [1..1] L3 Reject Unknown Streams */ + __IOM uint32_t LTHRUSS : 1; /*!< [2..2] L3 Reject Unknown Secure Streams */ + __IOM uint32_t IP4UE : 1; /*!< [3..3] IPv4 UDP Enabled */ + __IOM uint32_t IP4TE : 1; /*!< [4..4] IPv4 TCP Enabled */ + __IOM uint32_t IP4OE : 1; /*!< [5..5] IPv4 Other Enabled */ + __IOM uint32_t IP6UE : 1; /*!< [6..6] IPv6 UDP Enabled */ + __IOM uint32_t IP6TE : 1; /*!< [7..7] IPv6 TCP Enabled */ + __IOM uint32_t IP6OE : 1; /*!< [8..8] IPv6 Other Enabled */ + __IOM uint32_t L2SE : 1; /*!< [9..9] L2 Stream Enable */ + uint32_t : 10; + __IOM uint32_t MACDSA : 1; /*!< [20..20] MAC Destination Search Active */ + __IOM uint32_t MACRUDA : 1; /*!< [21..21] MAC Reject Unknown Destination Addresses */ + __IOM uint32_t MACRUDSA : 1; /*!< [22..22] MAC Reject Unknown Destination Secure Addresses */ + __IOM uint32_t MACSSA : 1; /*!< [23..23] MAC Source Search Active */ + __IOM uint32_t MACRUSA : 1; /*!< [24..24] MAC Reject Unknown Source Addresses */ + __IOM uint32_t MACRUSSA : 1; /*!< [25..25] MAC Reject Unknown Source Secure Addresses */ + __IOM uint32_t MACHLA : 1; /*!< [26..26] MAC Hardware Learning Active */ + __IOM uint32_t MACHMA : 1; /*!< [27..27] MAC Hardware Migration Active */ + __IOM uint32_t VLANSA : 1; /*!< [28..28] VLAN Search Active */ + __IOM uint32_t VLANRU : 1; /*!< [29..29] VLAN Reject Unknown */ + __IOM uint32_t VLANRUS : 1; /*!< [30..30] VLAN Reject Unknown Secure */ + uint32_t : 1; + } FWPC01_b; + }; + + union + { + __IOM uint32_t FWPC11; /*!< (@ 0x00000114) Port Configuration Register 11 */ + + struct + { + __IOM uint32_t DDE : 1; /*!< [0..0] Direct Descriptor Enable */ + __IOM uint32_t DDSL : 1; /*!< [1..1] Direct Descriptor Security Level */ + uint32_t : 14; + __IOM uint32_t LTHFM : 7; /*!< [22..16] Layer 3 Forwarding Mask */ + uint32_t : 9; + } FWPC11_b; + }; + + union + { + __IOM uint32_t FWPC21; /*!< (@ 0x00000118) Port Configuration Register 21 */ + + struct + { + uint32_t : 16; + __IOM uint32_t LTWFM : 7; /*!< [22..16] Layer 2 Forwarding Mask */ + uint32_t : 9; + } FWPC21_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t FWPC02; /*!< (@ 0x00000120) Port Configuration Register 02 */ + + struct + { + __IOM uint32_t LTHTA : 1; /*!< [0..0] L3 Table Active */ + __IOM uint32_t LTHRUS : 1; /*!< [1..1] L3 Reject Unknown Streams */ + __IOM uint32_t LTHRUSS : 1; /*!< [2..2] L3 Reject Unknown Secure Streams */ + __IOM uint32_t IP4UE : 1; /*!< [3..3] IPv4 UDP Enabled */ + __IOM uint32_t IP4TE : 1; /*!< [4..4] IPv4 TCP Enabled */ + __IOM uint32_t IP4OE : 1; /*!< [5..5] IPv4 Other Enabled */ + __IOM uint32_t IP6UE : 1; /*!< [6..6] IPv6 UDP Enabled */ + __IOM uint32_t IP6TE : 1; /*!< [7..7] IPv6 TCP Enabled */ + __IOM uint32_t IP6OE : 1; /*!< [8..8] IPv6 Other Enabled */ + __IOM uint32_t L2SE : 1; /*!< [9..9] L2 Stream Enable */ + uint32_t : 10; + __IOM uint32_t MACDSA : 1; /*!< [20..20] MAC Destination Search Active */ + __IOM uint32_t MACRUDA : 1; /*!< [21..21] MAC Reject Unknown Destination Addresses */ + __IOM uint32_t MACRUDSA : 1; /*!< [22..22] MAC Reject Unknown Destination Secure Addresses */ + __IOM uint32_t MACSSA : 1; /*!< [23..23] MAC Source Search Active */ + __IOM uint32_t MACRUSA : 1; /*!< [24..24] MAC Reject Unknown Source Addresses */ + __IOM uint32_t MACRUSSA : 1; /*!< [25..25] MAC Reject Unknown Source Secure Addresses */ + __IOM uint32_t MACHLA : 1; /*!< [26..26] MAC Hardware Learning Active */ + __IOM uint32_t MACHMA : 1; /*!< [27..27] MAC Hardware Migration Active */ + __IOM uint32_t VLANSA : 1; /*!< [28..28] VLAN Search Active */ + __IOM uint32_t VLANRU : 1; /*!< [29..29] VLAN Reject Unknown */ + __IOM uint32_t VLANRUS : 1; /*!< [30..30] VLAN Reject Unknown Secure */ + uint32_t : 1; + } FWPC02_b; + }; + + union + { + __IOM uint32_t FWPC12; /*!< (@ 0x00000124) Port Configuration Register 12 */ + + struct + { + __IOM uint32_t DDE : 1; /*!< [0..0] Direct Descriptor Enable */ + __IOM uint32_t DDSL : 1; /*!< [1..1] Direct Descriptor Security Level */ + uint32_t : 14; + __IOM uint32_t LTHFM : 7; /*!< [22..16] Layer 3 Forwarding Mask */ + uint32_t : 9; + } FWPC12_b; + }; + + union + { + __IOM uint32_t FWPC22; /*!< (@ 0x00000128) Port Configuration Register 22 */ + + struct + { + uint32_t : 16; + __IOM uint32_t LTWFM : 7; /*!< [22..16] Layer 2 Forwarding Mask */ + uint32_t : 9; + } FWPC22_b; + }; + __IM uint32_t RESERVED8[181]; + + union + { + __IOM uint32_t FWCTGC00; /*!< (@ 0x00000400) Cut-Through General Configuration Register 00 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC00_b; + }; + + union + { + __IOM uint32_t FWCTGC10; /*!< (@ 0x00000404) Cut-Through General Configuration Register 10 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC10_b; + }; + + union + { + __IOM uint32_t FWCTTC00; /*!< (@ 0x00000408) Cut-Through Target Configuration Register 00 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC00_b; + }; + + union + { + __IOM uint32_t FWCTTC10; /*!< (@ 0x0000040C) Cut-Through Target Configuration Register 10 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC10_b; + }; + + union + { + __IOM uint32_t FWCTTC200; /*!< (@ 0x00000410) Cut-Through Target Configuration Register 200 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC200_b; + }; + __IM uint32_t RESERVED9[3]; + + union + { + __IOM uint32_t FWCTSC00; /*!< (@ 0x00000420) Cut-Through Separation Configuration Register + * 00 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC00_b; + }; + + union + { + __IOM uint32_t FWCTSC10; /*!< (@ 0x00000424) Cut-Through Separation Configuration Register + * 10 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC10_b; + }; + + union + { + __IOM uint32_t FWCTSC20; /*!< (@ 0x00000428) Cut-Through Separation Configuration Register + * 20 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC20_b; + }; + + union + { + __IOM uint32_t FWCTSC30; /*!< (@ 0x0000042C) Cut-Through Separation Configuration Register + * 30 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC30_b; + }; + + union + { + __IOM uint32_t FWCTSC40; /*!< (@ 0x00000430) Cut-Through Separation Configuration Register + * 40 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC40_b; + }; + __IM uint32_t RESERVED10[3]; + + union + { + __IOM uint32_t FWCTGC01; /*!< (@ 0x00000440) Cut-Through General Configuration Register 01 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC01_b; + }; + + union + { + __IOM uint32_t FWCTGC11; /*!< (@ 0x00000444) Cut-Through General Configuration Register 11 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC11_b; + }; + + union + { + __IOM uint32_t FWCTTC01; /*!< (@ 0x00000448) Cut-Through Target Configuration Register 01 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC01_b; + }; + + union + { + __IOM uint32_t FWCTTC11; /*!< (@ 0x0000044C) Cut-Through Target Configuration Register 11 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC11_b; + }; + + union + { + __IOM uint32_t FWCTTC201; /*!< (@ 0x00000450) Cut-Through Target Configuration Register 201 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC201_b; + }; + __IM uint32_t RESERVED11[3]; + + union + { + __IOM uint32_t FWCTSC01; /*!< (@ 0x00000460) Cut-Through Separation Configuration Register + * 01 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC01_b; + }; + + union + { + __IOM uint32_t FWCTSC11; /*!< (@ 0x00000464) Cut-Through Separation Configuration Register + * 11 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC11_b; + }; + + union + { + __IOM uint32_t FWCTSC21; /*!< (@ 0x00000468) Cut-Through Separation Configuration Register + * 21 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC21_b; + }; + + union + { + __IOM uint32_t FWCTSC31; /*!< (@ 0x0000046C) Cut-Through Separation Configuration Register + * 31 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC31_b; + }; + + union + { + __IOM uint32_t FWCTSC41; /*!< (@ 0x00000470) Cut-Through Separation Configuration Register + * 41 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC41_b; + }; + __IM uint32_t RESERVED12[3]; + + union + { + __IOM uint32_t FWCTGC02; /*!< (@ 0x00000480) Cut-Through General Configuration Register 02 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC02_b; + }; + + union + { + __IOM uint32_t FWCTGC12; /*!< (@ 0x00000484) Cut-Through General Configuration Register 12 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC12_b; + }; + + union + { + __IOM uint32_t FWCTTC02; /*!< (@ 0x00000488) Cut-Through Target Configuration Register 02 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC02_b; + }; + + union + { + __IOM uint32_t FWCTTC12; /*!< (@ 0x0000048C) Cut-Through Target Configuration Register 12 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC12_b; + }; + + union + { + __IOM uint32_t FWCTTC202; /*!< (@ 0x00000490) Cut-Through Target Configuration Register 202 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC202_b; + }; + __IM uint32_t RESERVED13[3]; + + union + { + __IOM uint32_t FWCTSC02; /*!< (@ 0x000004A0) Cut-Through Separation Configuration Register + * 02 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC02_b; + }; + + union + { + __IOM uint32_t FWCTSC12; /*!< (@ 0x000004A4) Cut-Through Separation Configuration Register + * 12 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC12_b; + }; + + union + { + __IOM uint32_t FWCTSC22; /*!< (@ 0x000004A8) Cut-Through Separation Configuration Register + * 22 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC22_b; + }; + + union + { + __IOM uint32_t FWCTSC32; /*!< (@ 0x000004AC) Cut-Through Separation Configuration Register + * 32 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC32_b; + }; + + union + { + __IOM uint32_t FWCTSC42; /*!< (@ 0x000004B0) Cut-Through Separation Configuration Register + * 42 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC42_b; + }; + __IM uint32_t RESERVED14[3]; + + union + { + __IOM uint32_t FWCTGC03; /*!< (@ 0x000004C0) Cut-Through General Configuration Register 03 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC03_b; + }; + + union + { + __IOM uint32_t FWCTGC13; /*!< (@ 0x000004C4) Cut-Through General Configuration Register 13 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC13_b; + }; + + union + { + __IOM uint32_t FWCTTC03; /*!< (@ 0x000004C8) Cut-Through Target Configuration Register 03 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC03_b; + }; + + union + { + __IOM uint32_t FWCTTC13; /*!< (@ 0x000004CC) Cut-Through Target Configuration Register 13 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC13_b; + }; + + union + { + __IOM uint32_t FWCTTC203; /*!< (@ 0x000004D0) Cut-Through Target Configuration Register 203 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC203_b; + }; + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint32_t FWCTSC03; /*!< (@ 0x000004E0) Cut-Through Separation Configuration Register + * 03 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC03_b; + }; + + union + { + __IOM uint32_t FWCTSC13; /*!< (@ 0x000004E4) Cut-Through Separation Configuration Register + * 13 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC13_b; + }; + + union + { + __IOM uint32_t FWCTSC23; /*!< (@ 0x000004E8) Cut-Through Separation Configuration Register + * 23 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC23_b; + }; + + union + { + __IOM uint32_t FWCTSC33; /*!< (@ 0x000004EC) Cut-Through Separation Configuration Register + * 33 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC33_b; + }; + + union + { + __IOM uint32_t FWCTSC43; /*!< (@ 0x000004F0) Cut-Through Separation Configuration Register + * 43 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC43_b; + }; + __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint32_t FWCTGC04; /*!< (@ 0x00000500) Cut-Through General Configuration Register 04 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC04_b; + }; + + union + { + __IOM uint32_t FWCTGC14; /*!< (@ 0x00000504) Cut-Through General Configuration Register 14 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC14_b; + }; + + union + { + __IOM uint32_t FWCTTC04; /*!< (@ 0x00000508) Cut-Through Target Configuration Register 04 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC04_b; + }; + + union + { + __IOM uint32_t FWCTTC14; /*!< (@ 0x0000050C) Cut-Through Target Configuration Register 14 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC14_b; + }; + + union + { + __IOM uint32_t FWCTTC204; /*!< (@ 0x00000510) Cut-Through Target Configuration Register 204 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC204_b; + }; + __IM uint32_t RESERVED17[3]; + + union + { + __IOM uint32_t FWCTSC04; /*!< (@ 0x00000520) Cut-Through Separation Configuration Register + * 04 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC04_b; + }; + + union + { + __IOM uint32_t FWCTSC14; /*!< (@ 0x00000524) Cut-Through Separation Configuration Register + * 14 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC14_b; + }; + + union + { + __IOM uint32_t FWCTSC24; /*!< (@ 0x00000528) Cut-Through Separation Configuration Register + * 24 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC24_b; + }; + + union + { + __IOM uint32_t FWCTSC34; /*!< (@ 0x0000052C) Cut-Through Separation Configuration Register + * 34 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC34_b; + }; + + union + { + __IOM uint32_t FWCTSC44; /*!< (@ 0x00000530) Cut-Through Separation Configuration Register + * 44 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC44_b; + }; + __IM uint32_t RESERVED18[3]; + + union + { + __IOM uint32_t FWCTGC05; /*!< (@ 0x00000540) Cut-Through General Configuration Register 05 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC05_b; + }; + + union + { + __IOM uint32_t FWCTGC15; /*!< (@ 0x00000544) Cut-Through General Configuration Register 15 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC15_b; + }; + + union + { + __IOM uint32_t FWCTTC05; /*!< (@ 0x00000548) Cut-Through Target Configuration Register 05 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC05_b; + }; + + union + { + __IOM uint32_t FWCTTC15; /*!< (@ 0x0000054C) Cut-Through Target Configuration Register 15 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC15_b; + }; + + union + { + __IOM uint32_t FWCTTC205; /*!< (@ 0x00000550) Cut-Through Target Configuration Register 205 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC205_b; + }; + __IM uint32_t RESERVED19[3]; + + union + { + __IOM uint32_t FWCTSC05; /*!< (@ 0x00000560) Cut-Through Separation Configuration Register + * 05 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC05_b; + }; + + union + { + __IOM uint32_t FWCTSC15; /*!< (@ 0x00000564) Cut-Through Separation Configuration Register + * 15 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC15_b; + }; + + union + { + __IOM uint32_t FWCTSC25; /*!< (@ 0x00000568) Cut-Through Separation Configuration Register + * 25 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC25_b; + }; + + union + { + __IOM uint32_t FWCTSC35; /*!< (@ 0x0000056C) Cut-Through Separation Configuration Register + * 35 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC35_b; + }; + + union + { + __IOM uint32_t FWCTSC45; /*!< (@ 0x00000570) Cut-Through Separation Configuration Register + * 45 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC45_b; + }; + __IM uint32_t RESERVED20[3]; + + union + { + __IOM uint32_t FWCTGC06; /*!< (@ 0x00000580) Cut-Through General Configuration Register 06 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC06_b; + }; + + union + { + __IOM uint32_t FWCTGC16; /*!< (@ 0x00000584) Cut-Through General Configuration Register 16 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC16_b; + }; + + union + { + __IOM uint32_t FWCTTC06; /*!< (@ 0x00000588) Cut-Through Target Configuration Register 06 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC06_b; + }; + + union + { + __IOM uint32_t FWCTTC16; /*!< (@ 0x0000058C) Cut-Through Target Configuration Register 16 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC16_b; + }; + + union + { + __IOM uint32_t FWCTTC206; /*!< (@ 0x00000590) Cut-Through Target Configuration Register 206 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC206_b; + }; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t FWCTSC06; /*!< (@ 0x000005A0) Cut-Through Separation Configuration Register + * 06 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC06_b; + }; + + union + { + __IOM uint32_t FWCTSC16; /*!< (@ 0x000005A4) Cut-Through Separation Configuration Register + * 16 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC16_b; + }; + + union + { + __IOM uint32_t FWCTSC26; /*!< (@ 0x000005A8) Cut-Through Separation Configuration Register + * 26 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC26_b; + }; + + union + { + __IOM uint32_t FWCTSC36; /*!< (@ 0x000005AC) Cut-Through Separation Configuration Register + * 36 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC36_b; + }; + + union + { + __IOM uint32_t FWCTSC46; /*!< (@ 0x000005B0) Cut-Through Separation Configuration Register + * 46 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC46_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint32_t FWCTGC07; /*!< (@ 0x000005C0) Cut-Through General Configuration Register 07 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC07_b; + }; + + union + { + __IOM uint32_t FWCTGC17; /*!< (@ 0x000005C4) Cut-Through General Configuration Register 17 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC17_b; + }; + + union + { + __IOM uint32_t FWCTTC07; /*!< (@ 0x000005C8) Cut-Through Target Configuration Register 07 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC07_b; + }; + + union + { + __IOM uint32_t FWCTTC17; /*!< (@ 0x000005CC) Cut-Through Target Configuration Register 17 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC17_b; + }; + + union + { + __IOM uint32_t FWCTTC207; /*!< (@ 0x000005D0) Cut-Through Target Configuration Register 207 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC207_b; + }; + __IM uint32_t RESERVED23[3]; + + union + { + __IOM uint32_t FWCTSC07; /*!< (@ 0x000005E0) Cut-Through Separation Configuration Register + * 07 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC07_b; + }; + + union + { + __IOM uint32_t FWCTSC17; /*!< (@ 0x000005E4) Cut-Through Separation Configuration Register + * 17 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC17_b; + }; + + union + { + __IOM uint32_t FWCTSC27; /*!< (@ 0x000005E8) Cut-Through Separation Configuration Register + * 27 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC27_b; + }; + + union + { + __IOM uint32_t FWCTSC37; /*!< (@ 0x000005EC) Cut-Through Separation Configuration Register + * 37 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC37_b; + }; + + union + { + __IOM uint32_t FWCTSC47; /*!< (@ 0x000005F0) Cut-Through Separation Configuration Register + * 47 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC47_b; + }; + __IM uint32_t RESERVED24[643]; + + union + { + __IOM uint32_t FWTWBFC0; /*!< (@ 0x00001000) Two-Byte Filter Configuration Register 0 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC0_b; + }; + + union + { + __IOM uint32_t FWTWBFVC0; /*!< (@ 0x00001004) Two-Byte Filter Value Configuration Register + * 0 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC0_b; + }; + __IM uint32_t RESERVED25[2]; + + union + { + __IOM uint32_t FWTWBFC1; /*!< (@ 0x00001010) Two-Byte Filter Configuration Register 1 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC1_b; + }; + + union + { + __IOM uint32_t FWTWBFVC1; /*!< (@ 0x00001014) Two-Byte Filter Value Configuration Register + * 1 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC1_b; + }; + __IM uint32_t RESERVED26[2]; + + union + { + __IOM uint32_t FWTWBFC2; /*!< (@ 0x00001020) Two-Byte Filter Configuration Register 2 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC2_b; + }; + + union + { + __IOM uint32_t FWTWBFVC2; /*!< (@ 0x00001024) Two-Byte Filter Value Configuration Register + * 2 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC2_b; + }; + __IM uint32_t RESERVED27[2]; + + union + { + __IOM uint32_t FWTWBFC3; /*!< (@ 0x00001030) Two-Byte Filter Configuration Register 3 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC3_b; + }; + + union + { + __IOM uint32_t FWTWBFVC3; /*!< (@ 0x00001034) Two-Byte Filter Value Configuration Register + * 3 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC3_b; + }; + __IM uint32_t RESERVED28[2]; + + union + { + __IOM uint32_t FWTWBFC4; /*!< (@ 0x00001040) Two-Byte Filter Configuration Register 4 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC4_b; + }; + + union + { + __IOM uint32_t FWTWBFVC4; /*!< (@ 0x00001044) Two-Byte Filter Value Configuration Register + * 4 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC4_b; + }; + __IM uint32_t RESERVED29[2]; + + union + { + __IOM uint32_t FWTWBFC5; /*!< (@ 0x00001050) Two-Byte Filter Configuration Register 5 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC5_b; + }; + + union + { + __IOM uint32_t FWTWBFVC5; /*!< (@ 0x00001054) Two-Byte Filter Value Configuration Register + * 5 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC5_b; + }; + __IM uint32_t RESERVED30[2]; + + union + { + __IOM uint32_t FWTWBFC6; /*!< (@ 0x00001060) Two-Byte Filter Configuration Register 6 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC6_b; + }; + + union + { + __IOM uint32_t FWTWBFVC6; /*!< (@ 0x00001064) Two-Byte Filter Value Configuration Register + * 6 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC6_b; + }; + __IM uint32_t RESERVED31[2]; + + union + { + __IOM uint32_t FWTWBFC7; /*!< (@ 0x00001070) Two-Byte Filter Configuration Register 7 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC7_b; + }; + + union + { + __IOM uint32_t FWTWBFVC7; /*!< (@ 0x00001074) Two-Byte Filter Value Configuration Register + * 7 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC7_b; + }; + __IM uint32_t RESERVED32[2]; + + union + { + __IOM uint32_t FWTWBFC8; /*!< (@ 0x00001080) Two-Byte Filter Configuration Register 8 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC8_b; + }; + + union + { + __IOM uint32_t FWTWBFVC8; /*!< (@ 0x00001084) Two-Byte Filter Value Configuration Register + * 8 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC8_b; + }; + __IM uint32_t RESERVED33[2]; + + union + { + __IOM uint32_t FWTWBFC9; /*!< (@ 0x00001090) Two-Byte Filter Configuration Register 9 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC9_b; + }; + + union + { + __IOM uint32_t FWTWBFVC9; /*!< (@ 0x00001094) Two-Byte Filter Value Configuration Register + * 9 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC9_b; + }; + __IM uint32_t RESERVED34[2]; + + union + { + __IOM uint32_t FWTWBFC10; /*!< (@ 0x000010A0) Two-Byte Filter Configuration Register 10 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC10_b; + }; + + union + { + __IOM uint32_t FWTWBFVC10; /*!< (@ 0x000010A4) Two-Byte Filter Value Configuration Register + * 10 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC10_b; + }; + __IM uint32_t RESERVED35[2]; + + union + { + __IOM uint32_t FWTWBFC11; /*!< (@ 0x000010B0) Two-Byte Filter Configuration Register 11 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC11_b; + }; + + union + { + __IOM uint32_t FWTWBFVC11; /*!< (@ 0x000010B4) Two-Byte Filter Value Configuration Register + * 11 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC11_b; + }; + __IM uint32_t RESERVED36[2]; + + union + { + __IOM uint32_t FWTWBFC12; /*!< (@ 0x000010C0) Two-Byte Filter Configuration Register 12 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC12_b; + }; + + union + { + __IOM uint32_t FWTWBFVC12; /*!< (@ 0x000010C4) Two-Byte Filter Value Configuration Register + * 12 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC12_b; + }; + __IM uint32_t RESERVED37[2]; + + union + { + __IOM uint32_t FWTWBFC13; /*!< (@ 0x000010D0) Two-Byte Filter Configuration Register 13 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC13_b; + }; + + union + { + __IOM uint32_t FWTWBFVC13; /*!< (@ 0x000010D4) Two-Byte Filter Value Configuration Register + * 13 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC13_b; + }; + __IM uint32_t RESERVED38[2]; + + union + { + __IOM uint32_t FWTWBFC14; /*!< (@ 0x000010E0) Two-Byte Filter Configuration Register 14 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC14_b; + }; + + union + { + __IOM uint32_t FWTWBFVC14; /*!< (@ 0x000010E4) Two-Byte Filter Value Configuration Register + * 14 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC14_b; + }; + __IM uint32_t RESERVED39[2]; + + union + { + __IOM uint32_t FWTWBFC15; /*!< (@ 0x000010F0) Two-Byte Filter Configuration Register 15 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC15_b; + }; + + union + { + __IOM uint32_t FWTWBFVC15; /*!< (@ 0x000010F4) Two-Byte Filter Value Configuration Register + * 15 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC15_b; + }; + __IM uint32_t RESERVED40[194]; + + union + { + __IOM uint32_t FWTHBFC0; /*!< (@ 0x00001400) Three-Byte Filter Configuration Register 0 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC0_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C0; /*!< (@ 0x00001404) Three-Byte Filter Value 0 Configuration Register + * 0 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C0_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C0; /*!< (@ 0x00001408) Three-Byte Filter Value 1 Configuration Register + * 0 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C0_b; + }; + __IM uint32_t RESERVED41; + + union + { + __IOM uint32_t FWTHBFC1; /*!< (@ 0x00001410) Three-Byte Filter Configuration Register 1 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC1_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C1; /*!< (@ 0x00001414) Three-Byte Filter Value 0 Configuration Register + * 1 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C1_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C1; /*!< (@ 0x00001418) Three-Byte Filter Value 1 Configuration Register + * 1 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C1_b; + }; + __IM uint32_t RESERVED42; + + union + { + __IOM uint32_t FWTHBFC2; /*!< (@ 0x00001420) Three-Byte Filter Configuration Register 2 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC2_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C2; /*!< (@ 0x00001424) Three-Byte Filter Value 0 Configuration Register + * 2 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C2_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C2; /*!< (@ 0x00001428) Three-Byte Filter Value 1 Configuration Register + * 2 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C2_b; + }; + __IM uint32_t RESERVED43; + + union + { + __IOM uint32_t FWTHBFC3; /*!< (@ 0x00001430) Three-Byte Filter Configuration Register 3 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC3_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C3; /*!< (@ 0x00001434) Three-Byte Filter Value 0 Configuration Register + * 3 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C3_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C3; /*!< (@ 0x00001438) Three-Byte Filter Value 1 Configuration Register + * 3 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C3_b; + }; + __IM uint32_t RESERVED44; + + union + { + __IOM uint32_t FWTHBFC4; /*!< (@ 0x00001440) Three-Byte Filter Configuration Register 4 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC4_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C4; /*!< (@ 0x00001444) Three-Byte Filter Value 0 Configuration Register + * 4 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C4_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C4; /*!< (@ 0x00001448) Three-Byte Filter Value 1 Configuration Register + * 4 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C4_b; + }; + __IM uint32_t RESERVED45; + + union + { + __IOM uint32_t FWTHBFC5; /*!< (@ 0x00001450) Three-Byte Filter Configuration Register 5 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC5_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C5; /*!< (@ 0x00001454) Three-Byte Filter Value 0 Configuration Register + * 5 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C5_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C5; /*!< (@ 0x00001458) Three-Byte Filter Value 1 Configuration Register + * 5 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C5_b; + }; + __IM uint32_t RESERVED46; + + union + { + __IOM uint32_t FWTHBFC6; /*!< (@ 0x00001460) Three-Byte Filter Configuration Register 6 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC6_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C6; /*!< (@ 0x00001464) Three-Byte Filter Value 0 Configuration Register + * 6 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C6_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C6; /*!< (@ 0x00001468) Three-Byte Filter Value 1 Configuration Register + * 6 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C6_b; + }; + __IM uint32_t RESERVED47; + + union + { + __IOM uint32_t FWTHBFC7; /*!< (@ 0x00001470) Three-Byte Filter Configuration Register 7 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC7_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C7; /*!< (@ 0x00001474) Three-Byte Filter Value 0 Configuration Register + * 7 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C7_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C7; /*!< (@ 0x00001478) Three-Byte Filter Value 1 Configuration Register + * 7 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C7_b; + }; + __IM uint32_t RESERVED48; + + union + { + __IOM uint32_t FWTHBFC8; /*!< (@ 0x00001480) Three-Byte Filter Configuration Register 8 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC8_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C8; /*!< (@ 0x00001484) Three-Byte Filter Value 0 Configuration Register + * 8 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C8_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C8; /*!< (@ 0x00001488) Three-Byte Filter Value 1 Configuration Register + * 8 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C8_b; + }; + __IM uint32_t RESERVED49; + + union + { + __IOM uint32_t FWTHBFC9; /*!< (@ 0x00001490) Three-Byte Filter Configuration Register 9 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC9_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C9; /*!< (@ 0x00001494) Three-Byte Filter Value 0 Configuration Register + * 9 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C9_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C9; /*!< (@ 0x00001498) Three-Byte Filter Value 1 Configuration Register + * 9 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C9_b; + }; + __IM uint32_t RESERVED50; + + union + { + __IOM uint32_t FWTHBFC10; /*!< (@ 0x000014A0) Three-Byte Filter Configuration Register 10 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC10_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C10; /*!< (@ 0x000014A4) Three-Byte Filter Value 0 Configuration Register + * 10 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C10_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C10; /*!< (@ 0x000014A8) Three-Byte Filter Value 1 Configuration Register + * 10 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C10_b; + }; + __IM uint32_t RESERVED51; + + union + { + __IOM uint32_t FWTHBFC11; /*!< (@ 0x000014B0) Three-Byte Filter Configuration Register 11 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC11_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C11; /*!< (@ 0x000014B4) Three-Byte Filter Value 0 Configuration Register + * 11 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C11_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C11; /*!< (@ 0x000014B8) Three-Byte Filter Value 1 Configuration Register + * 11 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C11_b; + }; + __IM uint32_t RESERVED52; + + union + { + __IOM uint32_t FWTHBFC12; /*!< (@ 0x000014C0) Three-Byte Filter Configuration Register 12 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC12_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C12; /*!< (@ 0x000014C4) Three-Byte Filter Value 0 Configuration Register + * 12 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C12_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C12; /*!< (@ 0x000014C8) Three-Byte Filter Value 1 Configuration Register + * 12 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C12_b; + }; + __IM uint32_t RESERVED53; + + union + { + __IOM uint32_t FWTHBFC13; /*!< (@ 0x000014D0) Three-Byte Filter Configuration Register 13 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC13_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C13; /*!< (@ 0x000014D4) Three-Byte Filter Value 0 Configuration Register + * 13 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C13_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C13; /*!< (@ 0x000014D8) Three-Byte Filter Value 1 Configuration Register + * 13 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C13_b; + }; + __IM uint32_t RESERVED54; + + union + { + __IOM uint32_t FWTHBFC14; /*!< (@ 0x000014E0) Three-Byte Filter Configuration Register 14 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC14_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C14; /*!< (@ 0x000014E4) Three-Byte Filter Value 0 Configuration Register + * 14 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C14_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C14; /*!< (@ 0x000014E8) Three-Byte Filter Value 1 Configuration Register + * 14 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C14_b; + }; + __IM uint32_t RESERVED55; + + union + { + __IOM uint32_t FWTHBFC15; /*!< (@ 0x000014F0) Three-Byte Filter Configuration Register 15 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC15_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C15; /*!< (@ 0x000014F4) Three-Byte Filter Value 0 Configuration Register + * 15 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C15_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C15; /*!< (@ 0x000014F8) Three-Byte Filter Value 1 Configuration Register + * 15 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C15_b; + }; + __IM uint32_t RESERVED56[193]; + + union + { + __IOM uint32_t FWFOBFC0; /*!< (@ 0x00001800) Four-Byte Filter Configuration Register 0 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC0_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C0; /*!< (@ 0x00001804) Four-Byte Filter Value 0 Configuration Register + * 0 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C0_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C0; /*!< (@ 0x00001808) Four-Byte Filter Value 1 Configuration Register + * 0 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C0_b; + }; + __IM uint32_t RESERVED57; + + union + { + __IOM uint32_t FWFOBFC1; /*!< (@ 0x00001810) Four-Byte Filter Configuration Register 1 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC1_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C1; /*!< (@ 0x00001814) Four-Byte Filter Value 0 Configuration Register + * 1 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C1_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C1; /*!< (@ 0x00001818) Four-Byte Filter Value 1 Configuration Register + * 1 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C1_b; + }; + __IM uint32_t RESERVED58; + + union + { + __IOM uint32_t FWFOBFC2; /*!< (@ 0x00001820) Four-Byte Filter Configuration Register 2 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC2_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C2; /*!< (@ 0x00001824) Four-Byte Filter Value 0 Configuration Register + * 2 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C2_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C2; /*!< (@ 0x00001828) Four-Byte Filter Value 1 Configuration Register + * 2 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C2_b; + }; + __IM uint32_t RESERVED59; + + union + { + __IOM uint32_t FWFOBFC3; /*!< (@ 0x00001830) Four-Byte Filter Configuration Register 3 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC3_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C3; /*!< (@ 0x00001834) Four-Byte Filter Value 0 Configuration Register + * 3 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C3_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C3; /*!< (@ 0x00001838) Four-Byte Filter Value 1 Configuration Register + * 3 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C3_b; + }; + __IM uint32_t RESERVED60; + + union + { + __IOM uint32_t FWFOBFC4; /*!< (@ 0x00001840) Four-Byte Filter Configuration Register 4 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC4_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C4; /*!< (@ 0x00001844) Four-Byte Filter Value 0 Configuration Register + * 4 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C4_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C4; /*!< (@ 0x00001848) Four-Byte Filter Value 1 Configuration Register + * 4 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C4_b; + }; + __IM uint32_t RESERVED61; + + union + { + __IOM uint32_t FWFOBFC5; /*!< (@ 0x00001850) Four-Byte Filter Configuration Register 5 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC5_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C5; /*!< (@ 0x00001854) Four-Byte Filter Value 0 Configuration Register + * 5 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C5_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C5; /*!< (@ 0x00001858) Four-Byte Filter Value 1 Configuration Register + * 5 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C5_b; + }; + __IM uint32_t RESERVED62; + + union + { + __IOM uint32_t FWFOBFC6; /*!< (@ 0x00001860) Four-Byte Filter Configuration Register 6 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC6_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C6; /*!< (@ 0x00001864) Four-Byte Filter Value 0 Configuration Register + * 6 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C6_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C6; /*!< (@ 0x00001868) Four-Byte Filter Value 1 Configuration Register + * 6 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C6_b; + }; + __IM uint32_t RESERVED63; + + union + { + __IOM uint32_t FWFOBFC7; /*!< (@ 0x00001870) Four-Byte Filter Configuration Register 7 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC7_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C7; /*!< (@ 0x00001874) Four-Byte Filter Value 0 Configuration Register + * 7 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C7_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C7; /*!< (@ 0x00001878) Four-Byte Filter Value 1 Configuration Register + * 7 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C7_b; + }; + __IM uint32_t RESERVED64; + + union + { + __IOM uint32_t FWFOBFC8; /*!< (@ 0x00001880) Four-Byte Filter Configuration Register 8 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC8_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C8; /*!< (@ 0x00001884) Four-Byte Filter Value 0 Configuration Register + * 8 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C8_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C8; /*!< (@ 0x00001888) Four-Byte Filter Value 1 Configuration Register + * 8 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C8_b; + }; + __IM uint32_t RESERVED65; + + union + { + __IOM uint32_t FWFOBFC9; /*!< (@ 0x00001890) Four-Byte Filter Configuration Register 9 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC9_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C9; /*!< (@ 0x00001894) Four-Byte Filter Value 0 Configuration Register + * 9 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C9_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C9; /*!< (@ 0x00001898) Four-Byte Filter Value 1 Configuration Register + * 9 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C9_b; + }; + __IM uint32_t RESERVED66; + + union + { + __IOM uint32_t FWFOBFC10; /*!< (@ 0x000018A0) Four-Byte Filter Configuration Register 10 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC10_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C10; /*!< (@ 0x000018A4) Four-Byte Filter Value 0 Configuration Register + * 10 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C10_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C10; /*!< (@ 0x000018A8) Four-Byte Filter Value 1 Configuration Register + * 10 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C10_b; + }; + __IM uint32_t RESERVED67; + + union + { + __IOM uint32_t FWFOBFC11; /*!< (@ 0x000018B0) Four-Byte Filter Configuration Register 11 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC11_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C11; /*!< (@ 0x000018B4) Four-Byte Filter Value 0 Configuration Register + * 11 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C11_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C11; /*!< (@ 0x000018B8) Four-Byte Filter Value 1 Configuration Register + * 11 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C11_b; + }; + __IM uint32_t RESERVED68; + + union + { + __IOM uint32_t FWFOBFC12; /*!< (@ 0x000018C0) Four-Byte Filter Configuration Register 12 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC12_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C12; /*!< (@ 0x000018C4) Four-Byte Filter Value 0 Configuration Register + * 12 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C12_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C12; /*!< (@ 0x000018C8) Four-Byte Filter Value 1 Configuration Register + * 12 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C12_b; + }; + __IM uint32_t RESERVED69; + + union + { + __IOM uint32_t FWFOBFC13; /*!< (@ 0x000018D0) Four-Byte Filter Configuration Register 13 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC13_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C13; /*!< (@ 0x000018D4) Four-Byte Filter Value 0 Configuration Register + * 13 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C13_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C13; /*!< (@ 0x000018D8) Four-Byte Filter Value 1 Configuration Register + * 13 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C13_b; + }; + __IM uint32_t RESERVED70; + + union + { + __IOM uint32_t FWFOBFC14; /*!< (@ 0x000018E0) Four-Byte Filter Configuration Register 14 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC14_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C14; /*!< (@ 0x000018E4) Four-Byte Filter Value 0 Configuration Register + * 14 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C14_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C14; /*!< (@ 0x000018E8) Four-Byte Filter Value 1 Configuration Register + * 14 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C14_b; + }; + __IM uint32_t RESERVED71; + + union + { + __IOM uint32_t FWFOBFC15; /*!< (@ 0x000018F0) Four-Byte Filter Configuration Register 15 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC15_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C15; /*!< (@ 0x000018F4) Four-Byte Filter Value 0 Configuration Register + * 15 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C15_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C15; /*!< (@ 0x000018F8) Four-Byte Filter Value 1 Configuration Register + * 15 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C15_b; + }; + __IM uint32_t RESERVED72[193]; + + union + { + __IOM uint32_t FWRFC0; /*!< (@ 0x00001C00) Range Filter Configuration Register 0 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RFM : 1; /*!< [8..8] Range Filtering Mode */ + uint32_t : 7; + __IOM uint32_t RFOV : 8; /*!< [23..16] Range Filter Offset Value */ + uint32_t : 8; + } FWRFC0_b; + }; + + union + { + __IOM uint32_t FWRFVC0; /*!< (@ 0x00001C04) Range Filter Value Configuration Register 0 */ + + struct + { + __IOM uint32_t RFSV0 : 8; /*!< [7..0] Range Filter Start Value 0 */ + __IOM uint32_t RFSV1 : 8; /*!< [15..8] Range Filter Start Value 1 */ + __IOM uint32_t RFRV : 4; /*!< [19..16] Range Filter Range Value */ + uint32_t : 12; + } FWRFVC0_b; + }; + __IM uint32_t RESERVED73[2]; + + union + { + __IOM uint32_t FWRFC1; /*!< (@ 0x00001C10) Range Filter Configuration Register 1 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RFM : 1; /*!< [8..8] Range Filtering Mode */ + uint32_t : 7; + __IOM uint32_t RFOV : 8; /*!< [23..16] Range Filter Offset Value */ + uint32_t : 8; + } FWRFC1_b; + }; + + union + { + __IOM uint32_t FWRFVC1; /*!< (@ 0x00001C14) Range Filter Value Configuration Register 1 */ + + struct + { + __IOM uint32_t RFSV0 : 8; /*!< [7..0] Range Filter Start Value 0 */ + __IOM uint32_t RFSV1 : 8; /*!< [15..8] Range Filter Start Value 1 */ + __IOM uint32_t RFRV : 4; /*!< [19..16] Range Filter Range Value */ + uint32_t : 12; + } FWRFVC1_b; + }; + __IM uint32_t RESERVED74[250]; + + union + { + __IOM uint32_t FWCFC0; /*!< (@ 0x00002000) Cascade Filter Configuration Register 0 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC0_b; + }; + + union + { + __IOM uint32_t FWCFMC00; /*!< (@ 0x00002004) Cascade Filter Mapping Configuration Register + * 00 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC00_b; + }; + + union + { + __IOM uint32_t FWCFMC01; /*!< (@ 0x00002008) Cascade Filter Mapping Configuration Register + * 01 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC01_b; + }; + + union + { + __IOM uint32_t FWCFMC02; /*!< (@ 0x0000200C) Cascade Filter Mapping Configuration Register + * 02 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC02_b; + }; + + union + { + __IOM uint32_t FWCFMC03; /*!< (@ 0x00002010) Cascade Filter Mapping Configuration Register + * 03 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC03_b; + }; + + union + { + __IOM uint32_t FWCFMC04; /*!< (@ 0x00002014) Cascade Filter Mapping Configuration Register + * 04 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC04_b; + }; + + union + { + __IOM uint32_t FWCFMC05; /*!< (@ 0x00002018) Cascade Filter Mapping Configuration Register + * 05 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC05_b; + }; + + union + { + __IOM uint32_t FWCFMC06; /*!< (@ 0x0000201C) Cascade Filter Mapping Configuration Register + * 06 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC06_b; + }; + __IM uint32_t RESERVED75[8]; + + union + { + __IOM uint32_t FWCFC1; /*!< (@ 0x00002040) Cascade Filter Configuration Register 1 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC1_b; + }; + + union + { + __IOM uint32_t FWCFMC10; /*!< (@ 0x00002044) Cascade Filter Mapping Configuration Register + * 10 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC10_b; + }; + + union + { + __IOM uint32_t FWCFMC11; /*!< (@ 0x00002048) Cascade Filter Mapping Configuration Register + * 11 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC11_b; + }; + + union + { + __IOM uint32_t FWCFMC12; /*!< (@ 0x0000204C) Cascade Filter Mapping Configuration Register + * 12 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC12_b; + }; + + union + { + __IOM uint32_t FWCFMC13; /*!< (@ 0x00002050) Cascade Filter Mapping Configuration Register + * 13 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC13_b; + }; + + union + { + __IOM uint32_t FWCFMC14; /*!< (@ 0x00002054) Cascade Filter Mapping Configuration Register + * 14 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC14_b; + }; + + union + { + __IOM uint32_t FWCFMC15; /*!< (@ 0x00002058) Cascade Filter Mapping Configuration Register + * 15 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC15_b; + }; + + union + { + __IOM uint32_t FWCFMC16; /*!< (@ 0x0000205C) Cascade Filter Mapping Configuration Register + * 16 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC16_b; + }; + __IM uint32_t RESERVED76[8]; + + union + { + __IOM uint32_t FWCFC2; /*!< (@ 0x00002080) Cascade Filter Configuration Register 2 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC2_b; + }; + + union + { + __IOM uint32_t FWCFMC20; /*!< (@ 0x00002084) Cascade Filter Mapping Configuration Register + * 20 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC20_b; + }; + + union + { + __IOM uint32_t FWCFMC21; /*!< (@ 0x00002088) Cascade Filter Mapping Configuration Register + * 21 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC21_b; + }; + + union + { + __IOM uint32_t FWCFMC22; /*!< (@ 0x0000208C) Cascade Filter Mapping Configuration Register + * 22 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC22_b; + }; + + union + { + __IOM uint32_t FWCFMC23; /*!< (@ 0x00002090) Cascade Filter Mapping Configuration Register + * 23 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC23_b; + }; + + union + { + __IOM uint32_t FWCFMC24; /*!< (@ 0x00002094) Cascade Filter Mapping Configuration Register + * 24 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC24_b; + }; + + union + { + __IOM uint32_t FWCFMC25; /*!< (@ 0x00002098) Cascade Filter Mapping Configuration Register + * 25 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC25_b; + }; + + union + { + __IOM uint32_t FWCFMC26; /*!< (@ 0x0000209C) Cascade Filter Mapping Configuration Register + * 26 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC26_b; + }; + __IM uint32_t RESERVED77[8]; + + union + { + __IOM uint32_t FWCFC3; /*!< (@ 0x000020C0) Cascade Filter Configuration Register 3 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC3_b; + }; + + union + { + __IOM uint32_t FWCFMC30; /*!< (@ 0x000020C4) Cascade Filter Mapping Configuration Register + * 30 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC30_b; + }; + + union + { + __IOM uint32_t FWCFMC31; /*!< (@ 0x000020C8) Cascade Filter Mapping Configuration Register + * 31 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC31_b; + }; + + union + { + __IOM uint32_t FWCFMC32; /*!< (@ 0x000020CC) Cascade Filter Mapping Configuration Register + * 32 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC32_b; + }; + + union + { + __IOM uint32_t FWCFMC33; /*!< (@ 0x000020D0) Cascade Filter Mapping Configuration Register + * 33 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC33_b; + }; + + union + { + __IOM uint32_t FWCFMC34; /*!< (@ 0x000020D4) Cascade Filter Mapping Configuration Register + * 34 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC34_b; + }; + + union + { + __IOM uint32_t FWCFMC35; /*!< (@ 0x000020D8) Cascade Filter Mapping Configuration Register + * 35 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC35_b; + }; + + union + { + __IOM uint32_t FWCFMC36; /*!< (@ 0x000020DC) Cascade Filter Mapping Configuration Register + * 36 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC36_b; + }; + __IM uint32_t RESERVED78[8]; + + union + { + __IOM uint32_t FWCFC4; /*!< (@ 0x00002100) Cascade Filter Configuration Register 4 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC4_b; + }; + + union + { + __IOM uint32_t FWCFMC40; /*!< (@ 0x00002104) Cascade Filter Mapping Configuration Register + * 40 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC40_b; + }; + + union + { + __IOM uint32_t FWCFMC41; /*!< (@ 0x00002108) Cascade Filter Mapping Configuration Register + * 41 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC41_b; + }; + + union + { + __IOM uint32_t FWCFMC42; /*!< (@ 0x0000210C) Cascade Filter Mapping Configuration Register + * 42 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC42_b; + }; + + union + { + __IOM uint32_t FWCFMC43; /*!< (@ 0x00002110) Cascade Filter Mapping Configuration Register + * 43 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC43_b; + }; + + union + { + __IOM uint32_t FWCFMC44; /*!< (@ 0x00002114) Cascade Filter Mapping Configuration Register + * 44 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC44_b; + }; + + union + { + __IOM uint32_t FWCFMC45; /*!< (@ 0x00002118) Cascade Filter Mapping Configuration Register + * 45 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC45_b; + }; + + union + { + __IOM uint32_t FWCFMC46; /*!< (@ 0x0000211C) Cascade Filter Mapping Configuration Register + * 46 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC46_b; + }; + __IM uint32_t RESERVED79[8]; + + union + { + __IOM uint32_t FWCFC5; /*!< (@ 0x00002140) Cascade Filter Configuration Register 5 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC5_b; + }; + + union + { + __IOM uint32_t FWCFMC50; /*!< (@ 0x00002144) Cascade Filter Mapping Configuration Register + * 50 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC50_b; + }; + + union + { + __IOM uint32_t FWCFMC51; /*!< (@ 0x00002148) Cascade Filter Mapping Configuration Register + * 51 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC51_b; + }; + + union + { + __IOM uint32_t FWCFMC52; /*!< (@ 0x0000214C) Cascade Filter Mapping Configuration Register + * 52 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC52_b; + }; + + union + { + __IOM uint32_t FWCFMC53; /*!< (@ 0x00002150) Cascade Filter Mapping Configuration Register + * 53 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC53_b; + }; + + union + { + __IOM uint32_t FWCFMC54; /*!< (@ 0x00002154) Cascade Filter Mapping Configuration Register + * 54 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC54_b; + }; + + union + { + __IOM uint32_t FWCFMC55; /*!< (@ 0x00002158) Cascade Filter Mapping Configuration Register + * 55 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC55_b; + }; + + union + { + __IOM uint32_t FWCFMC56; /*!< (@ 0x0000215C) Cascade Filter Mapping Configuration Register + * 56 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC56_b; + }; + __IM uint32_t RESERVED80[8]; + + union + { + __IOM uint32_t FWCFC6; /*!< (@ 0x00002180) Cascade Filter Configuration Register 6 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC6_b; + }; + + union + { + __IOM uint32_t FWCFMC60; /*!< (@ 0x00002184) Cascade Filter Mapping Configuration Register + * 60 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC60_b; + }; + + union + { + __IOM uint32_t FWCFMC61; /*!< (@ 0x00002188) Cascade Filter Mapping Configuration Register + * 61 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC61_b; + }; + + union + { + __IOM uint32_t FWCFMC62; /*!< (@ 0x0000218C) Cascade Filter Mapping Configuration Register + * 62 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC62_b; + }; + + union + { + __IOM uint32_t FWCFMC63; /*!< (@ 0x00002190) Cascade Filter Mapping Configuration Register + * 63 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC63_b; + }; + + union + { + __IOM uint32_t FWCFMC64; /*!< (@ 0x00002194) Cascade Filter Mapping Configuration Register + * 64 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC64_b; + }; + + union + { + __IOM uint32_t FWCFMC65; /*!< (@ 0x00002198) Cascade Filter Mapping Configuration Register + * 65 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC65_b; + }; + + union + { + __IOM uint32_t FWCFMC66; /*!< (@ 0x0000219C) Cascade Filter Mapping Configuration Register + * 66 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC66_b; + }; + __IM uint32_t RESERVED81[8]; + + union + { + __IOM uint32_t FWCFC7; /*!< (@ 0x000021C0) Cascade Filter Configuration Register 7 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC7_b; + }; + + union + { + __IOM uint32_t FWCFMC70; /*!< (@ 0x000021C4) Cascade Filter Mapping Configuration Register + * 70 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC70_b; + }; + + union + { + __IOM uint32_t FWCFMC71; /*!< (@ 0x000021C8) Cascade Filter Mapping Configuration Register + * 71 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC71_b; + }; + + union + { + __IOM uint32_t FWCFMC72; /*!< (@ 0x000021CC) Cascade Filter Mapping Configuration Register + * 72 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC72_b; + }; + + union + { + __IOM uint32_t FWCFMC73; /*!< (@ 0x000021D0) Cascade Filter Mapping Configuration Register + * 73 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC73_b; + }; + + union + { + __IOM uint32_t FWCFMC74; /*!< (@ 0x000021D4) Cascade Filter Mapping Configuration Register + * 74 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC74_b; + }; + + union + { + __IOM uint32_t FWCFMC75; /*!< (@ 0x000021D8) Cascade Filter Mapping Configuration Register + * 75 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC75_b; + }; + + union + { + __IOM uint32_t FWCFMC76; /*!< (@ 0x000021DC) Cascade Filter Mapping Configuration Register + * 76 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC76_b; + }; + __IM uint32_t RESERVED82[8]; + + union + { + __IOM uint32_t FWCFC8; /*!< (@ 0x00002200) Cascade Filter Configuration Register 8 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC8_b; + }; + + union + { + __IOM uint32_t FWCFMC80; /*!< (@ 0x00002204) Cascade Filter Mapping Configuration Register + * 80 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC80_b; + }; + + union + { + __IOM uint32_t FWCFMC81; /*!< (@ 0x00002208) Cascade Filter Mapping Configuration Register + * 81 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC81_b; + }; + + union + { + __IOM uint32_t FWCFMC82; /*!< (@ 0x0000220C) Cascade Filter Mapping Configuration Register + * 82 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC82_b; + }; + + union + { + __IOM uint32_t FWCFMC83; /*!< (@ 0x00002210) Cascade Filter Mapping Configuration Register + * 83 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC83_b; + }; + + union + { + __IOM uint32_t FWCFMC84; /*!< (@ 0x00002214) Cascade Filter Mapping Configuration Register + * 84 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC84_b; + }; + + union + { + __IOM uint32_t FWCFMC85; /*!< (@ 0x00002218) Cascade Filter Mapping Configuration Register + * 85 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC85_b; + }; + + union + { + __IOM uint32_t FWCFMC86; /*!< (@ 0x0000221C) Cascade Filter Mapping Configuration Register + * 86 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC86_b; + }; + __IM uint32_t RESERVED83[8]; + + union + { + __IOM uint32_t FWCFC9; /*!< (@ 0x00002240) Cascade Filter Configuration Register 9 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC9_b; + }; + + union + { + __IOM uint32_t FWCFMC90; /*!< (@ 0x00002244) Cascade Filter Mapping Configuration Register + * 90 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC90_b; + }; + + union + { + __IOM uint32_t FWCFMC91; /*!< (@ 0x00002248) Cascade Filter Mapping Configuration Register + * 91 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC91_b; + }; + + union + { + __IOM uint32_t FWCFMC92; /*!< (@ 0x0000224C) Cascade Filter Mapping Configuration Register + * 92 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC92_b; + }; + + union + { + __IOM uint32_t FWCFMC93; /*!< (@ 0x00002250) Cascade Filter Mapping Configuration Register + * 93 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC93_b; + }; + + union + { + __IOM uint32_t FWCFMC94; /*!< (@ 0x00002254) Cascade Filter Mapping Configuration Register + * 94 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC94_b; + }; + + union + { + __IOM uint32_t FWCFMC95; /*!< (@ 0x00002258) Cascade Filter Mapping Configuration Register + * 95 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC95_b; + }; + + union + { + __IOM uint32_t FWCFMC96; /*!< (@ 0x0000225C) Cascade Filter Mapping Configuration Register + * 96 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC96_b; + }; + __IM uint32_t RESERVED84[8]; + + union + { + __IOM uint32_t FWCFC10; /*!< (@ 0x00002280) Cascade Filter Configuration Register 10 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC10_b; + }; + + union + { + __IOM uint32_t FWCFMC100; /*!< (@ 0x00002284) Cascade Filter Mapping Configuration Register + * 100 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC100_b; + }; + + union + { + __IOM uint32_t FWCFMC101; /*!< (@ 0x00002288) Cascade Filter Mapping Configuration Register + * 101 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC101_b; + }; + + union + { + __IOM uint32_t FWCFMC102; /*!< (@ 0x0000228C) Cascade Filter Mapping Configuration Register + * 102 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC102_b; + }; + + union + { + __IOM uint32_t FWCFMC103; /*!< (@ 0x00002290) Cascade Filter Mapping Configuration Register + * 103 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC103_b; + }; + + union + { + __IOM uint32_t FWCFMC104; /*!< (@ 0x00002294) Cascade Filter Mapping Configuration Register + * 104 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC104_b; + }; + + union + { + __IOM uint32_t FWCFMC105; /*!< (@ 0x00002298) Cascade Filter Mapping Configuration Register + * 105 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC105_b; + }; + + union + { + __IOM uint32_t FWCFMC106; /*!< (@ 0x0000229C) Cascade Filter Mapping Configuration Register + * 106 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC106_b; + }; + __IM uint32_t RESERVED85[8]; + + union + { + __IOM uint32_t FWCFC11; /*!< (@ 0x000022C0) Cascade Filter Configuration Register 11 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC11_b; + }; + + union + { + __IOM uint32_t FWCFMC110; /*!< (@ 0x000022C4) Cascade Filter Mapping Configuration Register + * 110 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC110_b; + }; + + union + { + __IOM uint32_t FWCFMC111; /*!< (@ 0x000022C8) Cascade Filter Mapping Configuration Register + * 111 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC111_b; + }; + + union + { + __IOM uint32_t FWCFMC112; /*!< (@ 0x000022CC) Cascade Filter Mapping Configuration Register + * 112 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC112_b; + }; + + union + { + __IOM uint32_t FWCFMC113; /*!< (@ 0x000022D0) Cascade Filter Mapping Configuration Register + * 113 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC113_b; + }; + + union + { + __IOM uint32_t FWCFMC114; /*!< (@ 0x000022D4) Cascade Filter Mapping Configuration Register + * 114 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC114_b; + }; + + union + { + __IOM uint32_t FWCFMC115; /*!< (@ 0x000022D8) Cascade Filter Mapping Configuration Register + * 115 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC115_b; + }; + + union + { + __IOM uint32_t FWCFMC116; /*!< (@ 0x000022DC) Cascade Filter Mapping Configuration Register + * 116 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC116_b; + }; + __IM uint32_t RESERVED86[8]; + + union + { + __IOM uint32_t FWCFC12; /*!< (@ 0x00002300) Cascade Filter Configuration Register 12 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC12_b; + }; + + union + { + __IOM uint32_t FWCFMC120; /*!< (@ 0x00002304) Cascade Filter Mapping Configuration Register + * 120 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC120_b; + }; + + union + { + __IOM uint32_t FWCFMC121; /*!< (@ 0x00002308) Cascade Filter Mapping Configuration Register + * 121 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC121_b; + }; + + union + { + __IOM uint32_t FWCFMC122; /*!< (@ 0x0000230C) Cascade Filter Mapping Configuration Register + * 122 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC122_b; + }; + + union + { + __IOM uint32_t FWCFMC123; /*!< (@ 0x00002310) Cascade Filter Mapping Configuration Register + * 123 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC123_b; + }; + + union + { + __IOM uint32_t FWCFMC124; /*!< (@ 0x00002314) Cascade Filter Mapping Configuration Register + * 124 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC124_b; + }; + + union + { + __IOM uint32_t FWCFMC125; /*!< (@ 0x00002318) Cascade Filter Mapping Configuration Register + * 125 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC125_b; + }; + + union + { + __IOM uint32_t FWCFMC126; /*!< (@ 0x0000231C) Cascade Filter Mapping Configuration Register + * 126 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC126_b; + }; + __IM uint32_t RESERVED87[8]; + + union + { + __IOM uint32_t FWCFC13; /*!< (@ 0x00002340) Cascade Filter Configuration Register 13 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC13_b; + }; + + union + { + __IOM uint32_t FWCFMC130; /*!< (@ 0x00002344) Cascade Filter Mapping Configuration Register + * 130 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC130_b; + }; + + union + { + __IOM uint32_t FWCFMC131; /*!< (@ 0x00002348) Cascade Filter Mapping Configuration Register + * 131 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC131_b; + }; + + union + { + __IOM uint32_t FWCFMC132; /*!< (@ 0x0000234C) Cascade Filter Mapping Configuration Register + * 132 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC132_b; + }; + + union + { + __IOM uint32_t FWCFMC133; /*!< (@ 0x00002350) Cascade Filter Mapping Configuration Register + * 133 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC133_b; + }; + + union + { + __IOM uint32_t FWCFMC134; /*!< (@ 0x00002354) Cascade Filter Mapping Configuration Register + * 134 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC134_b; + }; + + union + { + __IOM uint32_t FWCFMC135; /*!< (@ 0x00002358) Cascade Filter Mapping Configuration Register + * 135 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC135_b; + }; + + union + { + __IOM uint32_t FWCFMC136; /*!< (@ 0x0000235C) Cascade Filter Mapping Configuration Register + * 136 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC136_b; + }; + __IM uint32_t RESERVED88[8]; + + union + { + __IOM uint32_t FWCFC14; /*!< (@ 0x00002380) Cascade Filter Configuration Register 14 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC14_b; + }; + + union + { + __IOM uint32_t FWCFMC140; /*!< (@ 0x00002384) Cascade Filter Mapping Configuration Register + * 140 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC140_b; + }; + + union + { + __IOM uint32_t FWCFMC141; /*!< (@ 0x00002388) Cascade Filter Mapping Configuration Register + * 141 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC141_b; + }; + + union + { + __IOM uint32_t FWCFMC142; /*!< (@ 0x0000238C) Cascade Filter Mapping Configuration Register + * 142 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC142_b; + }; + + union + { + __IOM uint32_t FWCFMC143; /*!< (@ 0x00002390) Cascade Filter Mapping Configuration Register + * 143 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC143_b; + }; + + union + { + __IOM uint32_t FWCFMC144; /*!< (@ 0x00002394) Cascade Filter Mapping Configuration Register + * 144 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC144_b; + }; + + union + { + __IOM uint32_t FWCFMC145; /*!< (@ 0x00002398) Cascade Filter Mapping Configuration Register + * 145 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC145_b; + }; + + union + { + __IOM uint32_t FWCFMC146; /*!< (@ 0x0000239C) Cascade Filter Mapping Configuration Register + * 146 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC146_b; + }; + __IM uint32_t RESERVED89[8]; + + union + { + __IOM uint32_t FWCFC15; /*!< (@ 0x000023C0) Cascade Filter Configuration Register 15 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC15_b; + }; + + union + { + __IOM uint32_t FWCFMC150; /*!< (@ 0x000023C4) Cascade Filter Mapping Configuration Register + * 150 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC150_b; + }; + + union + { + __IOM uint32_t FWCFMC151; /*!< (@ 0x000023C8) Cascade Filter Mapping Configuration Register + * 151 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC151_b; + }; + + union + { + __IOM uint32_t FWCFMC152; /*!< (@ 0x000023CC) Cascade Filter Mapping Configuration Register + * 152 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC152_b; + }; + + union + { + __IOM uint32_t FWCFMC153; /*!< (@ 0x000023D0) Cascade Filter Mapping Configuration Register + * 153 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC153_b; + }; + + union + { + __IOM uint32_t FWCFMC154; /*!< (@ 0x000023D4) Cascade Filter Mapping Configuration Register + * 154 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC154_b; + }; + + union + { + __IOM uint32_t FWCFMC155; /*!< (@ 0x000023D8) Cascade Filter Mapping Configuration Register + * 155 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC155_b; + }; + + union + { + __IOM uint32_t FWCFMC156; /*!< (@ 0x000023DC) Cascade Filter Mapping Configuration Register + * 156 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC156_b; + }; + __IM uint32_t RESERVED90[1802]; + + union + { + __IOM uint32_t FWIP4SC; /*!< (@ 0x00004008) IPv4 Stream Configuration Register */ + + struct + { + __IOM uint32_t IP4IMDH : 1; /*!< [0..0] IPv4 Include MAC Destination in Hash */ + __IOM uint32_t IP4IMSH : 1; /*!< [1..1] IPv4 Include MAC Source in Hash */ + __IOM uint32_t IP4ISVH : 1; /*!< [2..2] IPv4 Include S-TAG VLAN ID in Hash */ + __IOM uint32_t IP4ISPH : 1; /*!< [3..3] IPv4 Include S-TAG PCP in Hash */ + __IOM uint32_t IP4ISDH : 1; /*!< [4..4] IPv4 Include S-TAG DEI in Hash */ + __IOM uint32_t IP4ICVH : 1; /*!< [5..5] IPv4 Include C-TAG VLAN ID in Hash */ + __IOM uint32_t IP4ICPH : 1; /*!< [6..6] IPv4 Include C-TAG PCP in Hash */ + __IOM uint32_t IP4ICDH : 1; /*!< [7..7] IPv4 Include C-TAG DEI in Hash */ + __IOM uint32_t IP4IISH : 1; /*!< [8..8] IPv4 Include IP Source in Hash */ + __IOM uint32_t IP4IIDH : 1; /*!< [9..9] IPv4 Include IP Destination in Hash */ + __IOM uint32_t IP4IPH : 1; /*!< [10..10] IPv4 Include Protocol in Hash */ + __IOM uint32_t IP4ISPTH : 1; /*!< [11..11] IPv4 Include Source Port in Hash */ + __IOM uint32_t IP4IDPTH : 1; /*!< [12..12] IPv4 Include Destination Port in Hash */ + uint32_t : 3; + __IOM uint32_t IP4ISVS : 1; /*!< [16..16] IPv4 Include S-TAG VLAN ID in Stream */ + __IOM uint32_t IP4ISPS : 1; /*!< [17..17] IPv4 Include S-TAG PCP in Stream */ + __IOM uint32_t IP4ISDS : 1; /*!< [18..18] IPv4 Include S-TAG DEI in Stream */ + __IOM uint32_t IP4ICVS : 1; /*!< [19..19] IPv4 Include C-TAG VLAN ID in Stream */ + __IOM uint32_t IP4ICPS : 1; /*!< [20..20] IPv4 Include C-TAG PCP in Stream */ + __IOM uint32_t IP4ICDS : 1; /*!< [21..21] IPv4 Include C-TAG DEI in Stream */ + __IOM uint32_t IP4IISS : 1; /*!< [22..22] IPv4 Include IP Source in Stream */ + __IOM uint32_t IP4IIDS : 1; /*!< [23..23] IPv4 Include IP Destination in Stream */ + __IOM uint32_t IP4IDPTS : 1; /*!< [24..24] IPv4 Include Destination Port in Stream */ + uint32_t : 7; + } FWIP4SC_b; + }; + __IM uint32_t RESERVED91[3]; + + union + { + __IOM uint32_t FWIP6SC; /*!< (@ 0x00004018) IPv6 Stream Configuration Register */ + + struct + { + __IOM uint32_t IP6IMDH : 1; /*!< [0..0] IPv6 Include MAC Destination in Hash */ + __IOM uint32_t IP6IMSH : 1; /*!< [1..1] IPv6 Include MAC Source in Hash */ + __IOM uint32_t IP6ISVH : 1; /*!< [2..2] IPv6 Include S-TAG VLAN ID in Hash */ + __IOM uint32_t IP6ISPH : 1; /*!< [3..3] IPv6 Include S-TAG PCP in Hash */ + __IOM uint32_t IP6ISDH : 1; /*!< [4..4] IPv6 Include S-TAG DEI in Hash */ + __IOM uint32_t IP6ICVH : 1; /*!< [5..5] IPv6 Include C-TAG VLAN ID in Hash */ + __IOM uint32_t IP6ICPH : 1; /*!< [6..6] IPv6 Include C-TAG PCP in Hash */ + __IOM uint32_t IP6ICDH : 1; /*!< [7..7] IPv6 Include C-TAG DEI in Hash */ + __IOM uint32_t IP6IISH : 1; /*!< [8..8] IPv6 Include IP Source in Hash */ + __IOM uint32_t IP6IIDH : 1; /*!< [9..9] IPv6 Include IP Destination in Hash */ + __IOM uint32_t IP6IPH : 1; /*!< [10..10] IPv6 Include Protocol in Hash */ + __IOM uint32_t IP6ISPTH : 1; /*!< [11..11] IPv6 Include Source Port in Hash */ + __IOM uint32_t IP6IDPTH : 1; /*!< [12..12] IPv6 Include Destination Port in Hash */ + uint32_t : 3; + __IOM uint32_t IP6ISVS : 1; /*!< [16..16] IPv6 Include S-TAG VLAN ID in Stream */ + __IOM uint32_t IP6ISPS : 1; /*!< [17..17] IPv6 Include S-TAG PCP in Stream */ + __IOM uint32_t IP6ISDS : 1; /*!< [18..18] IPv6 Include S-TAG DEI in Stream */ + __IOM uint32_t IP6ICVS : 1; /*!< [19..19] IPv6 Include C-TAG VLAN ID in Stream */ + __IOM uint32_t IP6ICPS : 1; /*!< [20..20] IPv6 Include C-TAG PCP in Stream */ + __IOM uint32_t IP6ICDS : 1; /*!< [21..21] IPv6 Include C-TAG DEI in Stream */ + __IOM uint32_t IP6II0S : 1; /*!< [22..22] IPv6 Include IP 0 in Stream */ + __IOM uint32_t IP6II1S : 1; /*!< [23..23] IPv6 Include IP 1 in Stream */ + __IOM uint32_t IP6IDPTS : 1; /*!< [24..24] IPv6 Include Destination Port in Stream */ + uint32_t : 7; + } FWIP6SC_b; + }; + + union + { + __IOM uint32_t FWIP6OC; /*!< (@ 0x0000401C) IPv6 Offset Configuration Register */ + + struct + { + __IOM uint32_t IP6IPOM0 : 1; /*!< [0..0] IPv6 IP Offset mode 0 */ + uint32_t : 3; + __IOM uint32_t IP6IPO0 : 4; /*!< [7..4] IPv6 IP Offset 0 */ + uint32_t : 8; + __IOM uint32_t IP6IPOM1 : 1; /*!< [16..16] IPv6 IP Offset mode 1 */ + uint32_t : 3; + __IOM uint32_t IP6IPO1 : 4; /*!< [23..20] IPv6 IP Offset 1 */ + uint32_t : 8; + } FWIP6OC_b; + }; + + union + { + __IOM uint32_t FWL2SC; /*!< (@ 0x00004020) Layer 2 Stream Configuration Register */ + + struct + { + __IOM uint32_t L2IMDS : 1; /*!< [0..0] Layer 2 Include MAC Destination in Stream */ + __IOM uint32_t L2IMSS : 1; /*!< [1..1] Layer 2 Include MAC Source in Stream */ + __IOM uint32_t L2ISVS : 1; /*!< [2..2] Layer 2 Include S-TAG VLAN ID in Stream */ + __IOM uint32_t L2ISPS : 1; /*!< [3..3] Layer 2 Include S-TAG PCP ID in Stream */ + __IOM uint32_t L2ISDS : 1; /*!< [4..4] Layer 2 Include S-TAG DEI in Stream */ + __IOM uint32_t L2ICVS : 1; /*!< [5..5] Layer 2 Include C-TAG VLAN ID in Stream */ + __IOM uint32_t L2ICPS : 1; /*!< [6..6] Layer 2 Include C-TAG PCP ID in Stream */ + __IOM uint32_t L2ICDS : 1; /*!< [7..7] Layer 2 Include C-TAG DEI in Stream */ + uint32_t : 24; + } FWL2SC_b; + }; + __IM uint32_t RESERVED92[3]; + + union + { + __IOM uint32_t FWSFHEC; /*!< (@ 0x00004030) Stream Filter Hash Equation Configuration Register */ + + struct + { + __IOM uint32_t IP4HE : 16; /*!< [15..0] Stream Filter Hash Equation */ + __IOM uint32_t IP6HE : 16; /*!< [31..16] Stream Filter Hash Equation */ + } FWSFHEC_b; + }; + __IM uint32_t RESERVED93[3]; + + union + { + __IOM uint32_t FWSHCR0; /*!< (@ 0x00004040) Software Hash Calculation Request Register 0 */ + + struct + { + __IOM uint32_t SHCMDP0 : 32; /*!< [31..0] Software Hash Calculation MAC Destination Part 0 */ + } FWSHCR0_b; + }; + + union + { + __IOM uint32_t FWSHCR1; /*!< (@ 0x00004044) Software Hash Calculation Request Register 1 */ + + struct + { + __IOM uint32_t SHCMSP0 : 16; /*!< [15..0] Software Hash Calculation MAC Source Part 0 */ + __IOM uint32_t SHCMDP1 : 16; /*!< [31..16] Software Hash Calculation MAC Destination Part 1 */ + } FWSHCR1_b; + }; + + union + { + __IOM uint32_t FWSHCR2; /*!< (@ 0x00004048) Software Hash Calculation Request Register 2 */ + + struct + { + __IOM uint32_t SHCMSP1 : 32; /*!< [31..0] Software Hash Calculation MAC Source Part 1 */ + } FWSHCR2_b; + }; + + union + { + __IOM uint32_t FWSHCR3; /*!< (@ 0x0000404C) Software Hash Calculation Request Register 3 */ + + struct + { + __IOM uint32_t SHCCV : 12; /*!< [11..0] Software Hash Calculation C-TAG VLAN */ + __IOM uint32_t SHCCD : 1; /*!< [12..12] Software Hash Calculation C-TAG DEI */ + __IOM uint32_t SHCCP : 3; /*!< [15..13] Software Hash Calculation C-TAG PCP */ + __IOM uint32_t SHCSV : 12; /*!< [27..16] Software Hash Calculation S-TAG VLANs */ + __IOM uint32_t SHCSD : 1; /*!< [28..28] Software Hash Calculation S-TAG DEI */ + __IOM uint32_t SHCSP : 3; /*!< [31..29] Software Hash Calculation S-TAG PCP */ + } FWSHCR3_b; + }; + + union + { + __IOM uint32_t FWSHCR4; /*!< (@ 0x00004050) Software Hash Calculation Request Register 4 */ + + struct + { + __IOM uint32_t SHCP : 8; /*!< [7..0] Software Hash Calculation Protocol (NextHeader for IPv6) */ + uint32_t : 8; + __IOM uint32_t SHCFF : 1; /*!< [16..16] Software Hash Calculation Frame Format */ + uint32_t : 15; + } FWSHCR4_b; + }; + + union + { + __IOM uint32_t FWSHCR5; /*!< (@ 0x00004054) Software Hash Calculation Request Register 5 */ + + struct + { + __IOM uint32_t SHCISP0 : 32; /*!< [31..0] Software Hash Calculation IP Source Part 0 */ + } FWSHCR5_b; + }; + + union + { + __IOM uint32_t FWSHCR6; /*!< (@ 0x00004058) Software Hash Calculation Request Register 6 */ + + struct + { + __IOM uint32_t SHCISP1 : 32; /*!< [31..0] Software Hash Calculation IP Source Part 1 */ + } FWSHCR6_b; + }; + + union + { + __IOM uint32_t FWSHCR7; /*!< (@ 0x0000405C) Software Hash Calculation Request Register 7 */ + + struct + { + __IOM uint32_t SHCISP2 : 32; /*!< [31..0] Software Hash Calculation IP Source Part 2 */ + } FWSHCR7_b; + }; + + union + { + __IOM uint32_t FWSHCR8; /*!< (@ 0x00004060) Software Hash Calculation Request Register 8 */ + + struct + { + __IOM uint32_t SHCISP3 : 32; /*!< [31..0] Software Hash Calculation IP Source Part 3 */ + } FWSHCR8_b; + }; + + union + { + __IOM uint32_t FWSHCR9; /*!< (@ 0x00004064) Software Hash Calculation Request Register 9 */ + + struct + { + __IOM uint32_t SHCIDP0 : 32; /*!< [31..0] Software Hash Calculation IP Destination Part 0 */ + } FWSHCR9_b; + }; + + union + { + __IOM uint32_t FWSHCR10; /*!< (@ 0x00004068) Software Hash Calculation Request Register 10 */ + + struct + { + __IOM uint32_t SHCIDP1 : 32; /*!< [31..0] Software Hash Calculation IP Destination Part 1 */ + } FWSHCR10_b; + }; + + union + { + __IOM uint32_t FWSHCR11; /*!< (@ 0x0000406C) Software Hash Calculation Request Register 11 */ + + struct + { + __IOM uint32_t SHCIDP2 : 32; /*!< [31..0] Software Hash Calculation IP Destination Part 2 */ + } FWSHCR11_b; + }; + + union + { + __IOM uint32_t FWSHCR12; /*!< (@ 0x00004070) Software Hash Calculation Request Register 12 */ + + struct + { + __IOM uint32_t SHCIDP3 : 32; /*!< [31..0] Software Hash Calculation IP Destination Part 3 */ + } FWSHCR12_b; + }; + + union + { + __IOM uint32_t FWSHCR13; /*!< (@ 0x00004074) Software Hash Calculation Request Register 13 */ + + struct + { + __IOM uint32_t SHCDP : 16; /*!< [15..0] Software Hash Calculation Destination Port */ + __IOM uint32_t SHCSP : 16; /*!< [31..16] Software Hash Calculation Source Port */ + } FWSHCR13_b; + }; + + union + { + __IM uint32_t FWSHCRR; /*!< (@ 0x00004078) Software Hash Calculation Request Result Register */ + + struct + { + __IM uint32_t SHCR : 16; /*!< [15..0] Software Hash Calculation Result */ + uint32_t : 15; + __IM uint32_t SHC : 1; /*!< [31..31] Software Hash Calculation */ + } FWSHCRR_b; + }; + __IM uint32_t RESERVED94[5]; + + union + { + __IOM uint32_t FWLTHHEC; /*!< (@ 0x00004090) L3 Hash Entry Configuration Register */ + + struct + { + __IOM uint32_t LTHHMC : 10; /*!< [9..0] L3 Hash Maximum Collision */ + uint32_t : 6; + __IOM uint32_t LTHHMUE : 11; /*!< [26..16] L3 Hash Maximum Unsecure Entry */ + uint32_t : 5; + } FWLTHHEC_b; + }; + + union + { + __IOM uint32_t FWLTHHC; /*!< (@ 0x00004094) L3 Hash Configuration Register */ + + struct + { + __IOM uint32_t LTHHE : 10; /*!< [9..0] L3 Hash Equation */ + uint32_t : 22; + } FWLTHHC_b; + }; + __IM uint32_t RESERVED95[2]; + + union + { + __IOM uint32_t FWLTHTL0; /*!< (@ 0x000040A0) L3 Table Learn Register 0 */ + + struct + { + __IOM uint32_t LTHSLP0 : 3; /*!< [2..0] L3 Stream Learn Part 0 */ + uint32_t : 5; + __IOM uint32_t LTHSLL : 1; /*!< [8..8] L3 Security Level Learn */ + uint32_t : 7; + __IOM uint32_t LTHED : 1; /*!< [16..16] L3 Entry Delete */ + uint32_t : 15; + } FWLTHTL0_b; + }; + + union + { + __IOM uint32_t FWLTHTL1; /*!< (@ 0x000040A4) L3 Table Learn Register 1 */ + + struct + { + __IOM uint32_t LTHSLP1 : 32; /*!< [31..0] L3 Stream Learn Part 1 */ + } FWLTHTL1_b; + }; + + union + { + __IOM uint32_t FWLTHTL2; /*!< (@ 0x000040A8) L3 Table Learn Register 2 */ + + struct + { + __IOM uint32_t LTHSLP2 : 32; /*!< [31..0] L3 Stream Learn Part 2 */ + } FWLTHTL2_b; + }; + + union + { + __IOM uint32_t FWLTHTL3; /*!< (@ 0x000040AC) L3 Table Learn Register 3 */ + + struct + { + __IOM uint32_t LTHSLP3 : 32; /*!< [31..0] L3 Stream Learn Part 3 */ + } FWLTHTL3_b; + }; + + union + { + __IOM uint32_t FWLTHTL4; /*!< (@ 0x000040B0) L3 Table Learn Register 4 */ + + struct + { + __IOM uint32_t LTHSLP4 : 32; /*!< [31..0] L3 Stream Learn Part 4 */ + } FWLTHTL4_b; + }; + + union + { + __IOM uint32_t FWLTHTL5; /*!< (@ 0x000040B4) L3 Table Learn Register 5 */ + + struct + { + uint32_t : 16; + __IOM uint32_t LTHMSDUNL : 4; /*!< [19..16] L3 MSDU Number Learn */ + uint32_t : 11; + __IOM uint32_t LTHMSDUVL : 1; /*!< [31..31] L3 MSDU Valid Learn */ + } FWLTHTL5_b; + }; + + union + { + __IOM uint32_t FWLTHTL6; /*!< (@ 0x000040B8) L3 Table Learn Register 6 */ + + struct + { + __IOM uint32_t LTHFRERNL : 7; /*!< [6..0] L3 FRER Number Learn */ + uint32_t : 8; + __IOM uint32_t LTHFRERVL : 1; /*!< [15..15] L3 FRER Valid Learn */ + __IOM uint32_t LTHMTRNL : 5; /*!< [20..16] L3 MeTeR Number Learn */ + uint32_t : 10; + __IOM uint32_t LTHMTRVL : 1; /*!< [31..31] L3 MeTeR Valid Learn */ + } FWLTHTL6_b; + }; + + union + { + __IOM uint32_t FWLTHTL7; /*!< (@ 0x000040BC) L3 Table Learn Register 7 */ + + struct + { + __IOM uint32_t LTHRNL : 8; /*!< [7..0] L3 Routing Number Learn */ + uint32_t : 7; + __IOM uint32_t LTHRVL : 1; /*!< [15..15] L3 Routing Valid Learn */ + __IOM uint32_t LTHSLVL : 7; /*!< [22..16] L3 Source Lock Vector Learn */ + uint32_t : 9; + } FWLTHTL7_b; + }; + + union + { + __IOM uint32_t FWLTHTL80; /*!< (@ 0x000040C0) L3 Table Learn Register 80 */ + + struct + { + __IOM uint32_t LTHCSDL : 7; /*!< [6..0] L3 CPU Sub-Destination Learn */ + uint32_t : 25; + } FWLTHTL80_b; + }; + __IM uint32_t RESERVED96[3]; + + union + { + __IOM uint32_t FWLTHTL9; /*!< (@ 0x000040D0) L3 Table Learn Register 9 */ + + struct + { + __IOM uint32_t LTHDVL : 7; /*!< [6..0] L3 Destination Vector Learn */ + uint32_t : 9; + __IOM uint32_t LTHIPVL : 3; /*!< [18..16] L3 Internal Priority Value Learn */ + __IOM uint32_t LTHIPUL : 1; /*!< [19..19] L3 Internal Priority Update Learn */ + __IOM uint32_t LTHEMEL : 1; /*!< [20..20] L3 Ethernet Mirroring Enable Learn */ + __IOM uint32_t LTHCMEL : 1; /*!< [21..21] L3 CPU Mirroring Enable Learn */ + uint32_t : 10; + } FWLTHTL9_b; + }; + + union + { + __IM uint32_t FWLTHTLR; /*!< (@ 0x000040D4) L3 Table Learn Result Register */ + + struct + { + __IM uint32_t LTHLF : 1; /*!< [0..0] L3 Learn Fail */ + __IM uint32_t LTHLSF : 1; /*!< [1..1] L3 Learn Security Fail */ + __IM uint32_t LTHLEF : 1; /*!< [2..2] L3 Learn ECC Fail */ + __IM uint32_t LTHLO : 1; /*!< [3..3] L3 Learn Overwrite */ + uint32_t : 12; + __IM uint32_t LTHLCN : 10; /*!< [25..16] L3 Learn Collision Number */ + uint32_t : 5; + __IM uint32_t LTHTL : 1; /*!< [31..31] L3 Table Learn */ + } FWLTHTLR_b; + }; + __IM uint32_t RESERVED97[2]; + + union + { + __IOM uint32_t FWLTHTIM; /*!< (@ 0x000040E0) L3 Table Initialization Monitoring Register */ + + struct + { + __IOM uint32_t LTHTIOG : 1; /*!< [0..0] L3 Table Initialization Ongoing */ + __IM uint32_t LTHTR : 1; /*!< [1..1] L3 Table Ready */ + uint32_t : 30; + } FWLTHTIM_b; + }; + + union + { + __IM uint32_t FWLTHTEM; /*!< (@ 0x000040E4) L3 Table Entry Monitoring Register */ + + struct + { + __IM uint32_t LTHTEN : 11; /*!< [10..0] L3 Table Entry Number */ + uint32_t : 5; + __IM uint32_t LTHTUEN : 11; /*!< [26..16] L3 Table Unsecure Entry Number */ + uint32_t : 5; + } FWLTHTEM_b; + }; + __IM uint32_t RESERVED98[6]; + + union + { + __IOM uint32_t FWLTHTS0; /*!< (@ 0x00004100) L3 Table Search Register 0 */ + + struct + { + __IOM uint32_t LTHSSP0 : 3; /*!< [2..0] L3 Stream Search Part 0 */ + uint32_t : 21; + __IOM uint32_t LTHSSPFS : 1; /*!< [24..24] L3 Stream Search Perfect Filter Select */ + uint32_t : 7; + } FWLTHTS0_b; + }; + + union + { + __IOM uint32_t FWLTHTS1; /*!< (@ 0x00004104) L3 Table Search Register 1 */ + + struct + { + __IOM uint32_t LTHSSP1 : 32; /*!< [31..0] L3 Stream Search Part 1 */ + } FWLTHTS1_b; + }; + + union + { + __IOM uint32_t FWLTHTS2; /*!< (@ 0x00004108) L3 Table Search Register 2 */ + + struct + { + __IOM uint32_t LTHSSP2 : 32; /*!< [31..0] L3 Stream Search Part 2 */ + } FWLTHTS2_b; + }; + + union + { + __IOM uint32_t FWLTHTS3; /*!< (@ 0x0000410C) L3 Table Search Register 3 */ + + struct + { + __IOM uint32_t LTHSSP3 : 32; /*!< [31..0] L3 Stream Search Part 3 */ + } FWLTHTS3_b; + }; + + union + { + __IOM uint32_t FWLTHTS4; /*!< (@ 0x00004110) L3 Table Search Register 4 */ + + struct + { + __IOM uint32_t LTHSSP4 : 32; /*!< [31..0] L3 Stream Search Part 4 */ + } FWLTHTS4_b; + }; + __IM uint32_t RESERVED99[3]; + + union + { + __IOM uint32_t FWLTHTSR0; /*!< (@ 0x00004120) L3 Table Search Result Register 0 */ + + struct + { + __IOM uint32_t LTHSEF : 1; /*!< [0..0] L3 Search ECC Fail */ + __IM uint32_t LTHSNF : 1; /*!< [1..1] L3 Search Not found */ + uint32_t : 6; + __IM uint32_t LTHSLS : 1; /*!< [8..8] L3 Security Level Search */ + uint32_t : 7; + __IM uint32_t LTHSCN : 10; /*!< [25..16] L3 Search Collision Number */ + uint32_t : 5; + __IM uint32_t LTHTS : 1; /*!< [31..31] L3 Table Search */ + } FWLTHTSR0_b; + }; + + union + { + __IM uint32_t FWLTHTSR1; /*!< (@ 0x00004124) L3 Table Search Result Register 1 */ + + struct + { + uint32_t : 16; + __IM uint32_t LTHMSDUNS : 4; /*!< [19..16] L3 MSDU Number Search */ + uint32_t : 11; + __IM uint32_t LTHMSDUVS : 1; /*!< [31..31] L3 MSDU Valid Search */ + } FWLTHTSR1_b; + }; + + union + { + __IM uint32_t FWLTHTSR2; /*!< (@ 0x00004128) L3 Table Search Result Register 2 */ + + struct + { + __IM uint32_t LTHFRERNS : 6; /*!< [5..0] L3 FRER Number Search */ + uint32_t : 9; + __IM uint32_t LTHFRERVS : 1; /*!< [15..15] L3 FRER Valid Search */ + __IM uint32_t LTHMTRNS : 5; /*!< [20..16] L3 MeTeR Number Search */ + uint32_t : 10; + __IM uint32_t LTHMTRVS : 1; /*!< [31..31] L3 MeTeR Valid Search */ + } FWLTHTSR2_b; + }; + + union + { + __IM uint32_t FWLTHTSR3; /*!< (@ 0x0000412C) L3 Table Search Result Register 3 */ + + struct + { + __IM uint32_t LTHRNS : 8; /*!< [7..0] L3 Routing Number Search */ + uint32_t : 7; + __IM uint32_t LTHRVS : 1; /*!< [15..15] L3 Routing Valid Search */ + __IM uint32_t LTHSLVS : 7; /*!< [22..16] L3 Source Lock Vector Search */ + uint32_t : 9; + } FWLTHTSR3_b; + }; + + union + { + __IM uint32_t FWLTHTSR40; /*!< (@ 0x00004130) L3 Table Search Result Register 40 */ + + struct + { + __IM uint32_t LTHCSDS : 7; /*!< [6..0] L3 CPU Sub-Destination Search */ + uint32_t : 25; + } FWLTHTSR40_b; + }; + __IM uint32_t RESERVED100[3]; + + union + { + __IM uint32_t FWLTHTSR5; /*!< (@ 0x00004140) L3 Table Search Result Register 5 */ + + struct + { + __IM uint32_t LTHDVS : 7; /*!< [6..0] L3 Destination Vector Search */ + uint32_t : 9; + __IM uint32_t LTHIPVS : 3; /*!< [18..16] L3 Internal Priority Value Search */ + __IM uint32_t LTHIPUS : 1; /*!< [19..19] L3 Internal Priority Update Search */ + __IM uint32_t LTHEMES : 1; /*!< [20..20] L3 Ethernet Mirroring Enable Search */ + __IM uint32_t LTHCMES : 1; /*!< [21..21] L3 CPU Mirroring Enable Search */ + uint32_t : 10; + } FWLTHTSR5_b; + }; + __IM uint32_t RESERVED101[3]; + + union + { + __IOM uint32_t FWLTHTR; /*!< (@ 0x00004150) L3 Table Read Register */ + + struct + { + __IOM uint32_t LTHAR : 10; /*!< [9..0] L3 Address Read */ + uint32_t : 22; + } FWLTHTR_b; + }; + + union + { + __IM uint32_t FWLTHTRR0; /*!< (@ 0x00004154) L3 Table Read Result Register 0 */ + + struct + { + __IM uint32_t LTHREF : 1; /*!< [0..0] L3 Read ECC Fail */ + __IM uint32_t LTHEVR : 1; /*!< [1..1] L3 Entry Valid Read */ + uint32_t : 29; + __IM uint32_t LTHTR : 1; /*!< [31..31] L3 Table Read */ + } FWLTHTRR0_b; + }; + + union + { + __IM uint32_t FWLTHTRR1; /*!< (@ 0x00004158) L3 Table Read Result Register 1 */ + + struct + { + __IM uint32_t LTHSRP0 : 3; /*!< [2..0] L3 Stream Read Part 0 */ + uint32_t : 5; + __IM uint32_t LTHSLR : 1; /*!< [8..8] L3 Security Level Read */ + uint32_t : 23; + } FWLTHTRR1_b; + }; + + union + { + __IM uint32_t FWLTHTRR2; /*!< (@ 0x0000415C) L3 Table Read Result Register 2 */ + + struct + { + __IM uint32_t LTHSRP1 : 32; /*!< [31..0] L3 Stream Read Part 1 */ + } FWLTHTRR2_b; + }; + + union + { + __IM uint32_t FWLTHTRR3; /*!< (@ 0x00004160) L3 Table Read Result Register 3 */ + + struct + { + __IM uint32_t LTHSRP2 : 32; /*!< [31..0] L3 Stream Read Part 2 */ + } FWLTHTRR3_b; + }; + + union + { + __IM uint32_t FWLTHTRR4; /*!< (@ 0x00004164) L3 Table Read Result Register 4 */ + + struct + { + __IM uint32_t LTHSRP3 : 32; /*!< [31..0] L3 Stream Read Part 3 */ + } FWLTHTRR4_b; + }; + + union + { + __IM uint32_t FWLTHTRR5; /*!< (@ 0x00004168) L3 Table Read Result Register 5 */ + + struct + { + __IM uint32_t LTHSRP4 : 32; /*!< [31..0] L3 Stream Read Part 4 */ + } FWLTHTRR5_b; + }; + + union + { + __IM uint32_t FWLTHTRR6; /*!< (@ 0x0000416C) L3 Table Read Result Register 6 */ + + struct + { + uint32_t : 16; + __IM uint32_t LTHMSDUNR : 4; /*!< [19..16] L3 MSDU Number Read */ + uint32_t : 11; + __IM uint32_t LTHMSDUVR : 1; /*!< [31..31] L3 MSDU Valid Read */ + } FWLTHTRR6_b; + }; + + union + { + __IM uint32_t FWLTHTRR7; /*!< (@ 0x00004170) L3 Table Read Result Register 7 */ + + struct + { + __IM uint32_t LTHFRERNR : 6; /*!< [5..0] L3 FRER Number Read */ + uint32_t : 9; + __IM uint32_t LTHFRERVR : 1; /*!< [15..15] L3 FRER Valid Read */ + __IM uint32_t LTHMTRNR : 5; /*!< [20..16] L3 MeTeR Number Read */ + uint32_t : 10; + __IM uint32_t LTHMTRVR : 1; /*!< [31..31] L3 MeTeR Valid Read */ + } FWLTHTRR7_b; + }; + + union + { + __IM uint32_t FWLTHTRR8; /*!< (@ 0x00004174) L3 Table Read Result Register 8 */ + + struct + { + __IM uint32_t LTHRNR : 8; /*!< [7..0] L3 Routing Number Read */ + uint32_t : 7; + __IM uint32_t LTHRVR : 1; /*!< [15..15] L3 Routing Valid Read */ + __IM uint32_t LTHSLVR : 7; /*!< [22..16] L3 Source Lock Vector Read */ + uint32_t : 9; + } FWLTHTRR8_b; + }; + __IM uint32_t RESERVED102[2]; + + union + { + __IM uint32_t FWLTHTRR90; /*!< (@ 0x00004180) L3 Table Read Result Register 90 */ + + struct + { + __IM uint32_t LTHCSDR : 7; /*!< [6..0] L3 CPU Sub-Destination Read */ + uint32_t : 25; + } FWLTHTRR90_b; + }; + __IM uint32_t RESERVED103[3]; + + union + { + __IM uint32_t FWLTHTRR10; /*!< (@ 0x00004190) L3 Table Read Result Register 10 */ + + struct + { + __IM uint32_t LTHDVR : 7; /*!< [6..0] L3 Destination Vector Read */ + uint32_t : 9; + __IM uint32_t LTHIPVR : 3; /*!< [18..16] L3 Internal Priority Value Read */ + __IM uint32_t LTHIPUR : 1; /*!< [19..19] L3 Internal Priority Update Read */ + __IM uint32_t LTHEMER : 1; /*!< [20..20] L3 Ethernet Mirroring Enable Read */ + __IM uint32_t LTHCMER : 1; /*!< [21..21] L3 CPU Mirroring Enable Read */ + uint32_t : 10; + } FWLTHTRR10_b; + }; + __IM uint32_t RESERVED104[291]; + + union + { + __IOM uint32_t FWMACHEC; /*!< (@ 0x00004620) MAC Hash Entry Configuration Register */ + + struct + { + __IOM uint32_t MACHMC : 11; /*!< [10..0] MAC Hash Maximum Collision */ + uint32_t : 5; + __IOM uint32_t MACHMUE : 12; /*!< [27..16] MAC Hash Maximum Unsecure Entry */ + uint32_t : 4; + } FWMACHEC_b; + }; + + union + { + __IOM uint32_t FWMACHC; /*!< (@ 0x00004624) MAC Hash Configuration Register */ + + struct + { + __IOM uint32_t MACHE : 11; /*!< [10..0] MAC Hash Equation */ + uint32_t : 21; + } FWMACHC_b; + }; + __IM uint32_t RESERVED105[2]; + + union + { + __IOM uint32_t FWMACTL0; /*!< (@ 0x00004630) MAC Table Learn Register 0 */ + + struct + { + uint32_t : 8; + __IOM uint32_t MACSLL : 1; /*!< [8..8] MAC Security Level Learn */ + __IOM uint32_t MACDEL : 1; /*!< [9..9] MAC Dynamic Entry Limit */ + __IOM uint32_t MACHLDL : 1; /*!< [10..10] MAC Hardware Learning Disable Learn */ + uint32_t : 5; + __IOM uint32_t MACED : 1; /*!< [16..16] MAC Entry Delete */ + uint32_t : 15; + } FWMACTL0_b; + }; + + union + { + __IOM uint32_t FWMACTL1; /*!< (@ 0x00004634) MAC Table Learn Register 1 */ + + struct + { + __IOM uint32_t MACMALP0 : 16; /*!< [15..0] MAC MAC address Learn Part 0 */ + uint32_t : 16; + } FWMACTL1_b; + }; + + union + { + __IOM uint32_t FWMACTL2; /*!< (@ 0x00004638) MAC Table Learn Register 2 */ + + struct + { + __IOM uint32_t MACMALP1 : 32; /*!< [31..0] MAC MAC address Learn Part 1 */ + } FWMACTL2_b; + }; + + union + { + __IOM uint32_t FWMACTL3; /*!< (@ 0x0000463C) MAC Table Learn Register 3 */ + + struct + { + __IOM uint32_t MACSSLVL : 7; /*!< [6..0] MAC Source Source Lock Vector Learn */ + uint32_t : 9; + __IOM uint32_t MACDSLVL : 7; /*!< [22..16] MAC Destination Source Lock Vector Learn */ + uint32_t : 9; + } FWMACTL3_b; + }; + + union + { + __IOM uint32_t FWMACTL40; /*!< (@ 0x00004640) MAC Table Learn Register 40 */ + + struct + { + __IOM uint32_t MACCSDL : 7; /*!< [6..0] MAC CPU Sub-Destination Learn */ + uint32_t : 25; + } FWMACTL40_b; + }; + __IM uint32_t RESERVED106[3]; + + union + { + __IOM uint32_t FWMACTL5; /*!< (@ 0x00004650) MAC Table Learn Register 5 */ + + struct + { + __IOM uint32_t MACDVL : 7; /*!< [6..0] MAC Destination Vector Learn */ + uint32_t : 9; + __IOM uint32_t MACIPVL : 3; /*!< [18..16] MAC Internal Priority Value Learn */ + __IOM uint32_t MACIPUL : 1; /*!< [19..19] MAC Internal Priority Update Learn */ + __IOM uint32_t MACEMEL : 1; /*!< [20..20] MAC Ethernet Mirroring Enable Learn */ + __IOM uint32_t MACCMEL : 1; /*!< [21..21] MAC CPU Mirroring Enable Learn */ + uint32_t : 10; + } FWMACTL5_b; + }; + + union + { + __IM uint32_t FWMACTLR; /*!< (@ 0x00004654) MAC Table Learn Result Register */ + + struct + { + __IM uint32_t MACLF : 1; /*!< [0..0] MAC Learn Fail */ + __IM uint32_t MACLSF : 1; /*!< [1..1] MAC Learn Security Fail */ + __IM uint32_t MACLEF : 1; /*!< [2..2] MAC Learn ECC Fail */ + __IM uint32_t MACLO : 1; /*!< [3..3] MAC Learn Overwrite */ + uint32_t : 12; + __IM uint32_t MACLCN : 10; /*!< [25..16] MAC Learn Collision Number */ + uint32_t : 5; + __IM uint32_t MACTL : 1; /*!< [31..31] MAC Table Learn */ + } FWMACTLR_b; + }; + __IM uint32_t RESERVED107[2]; + + union + { + __IOM uint32_t FWMACTIM; /*!< (@ 0x00004660) MAC Table Initialization Monitoring Register */ + + struct + { + __IOM uint32_t MACTIOG : 1; /*!< [0..0] MAC Table Initialization Ongoing */ + __IM uint32_t MACTR : 1; /*!< [1..1] MAC Table Ready */ + uint32_t : 30; + } FWMACTIM_b; + }; + + union + { + __IM uint32_t FWMACTEM; /*!< (@ 0x00004664) MAC Table Entry Monitoring Register */ + + struct + { + __IM uint32_t MACTEN : 11; /*!< [10..0] MAC Table Entry Number */ + uint32_t : 5; + __IM uint32_t MACTUEN : 11; /*!< [26..16] MAC Table Unsecure Entry Number */ + uint32_t : 5; + } FWMACTEM_b; + }; + __IM uint32_t RESERVED108[2]; + + union + { + __IOM uint32_t FWMACTS0; /*!< (@ 0x00004670) MAC Table Search Register 0 */ + + struct + { + __IOM uint32_t MACMASP0 : 16; /*!< [15..0] MAC MAC Address Search Part 0 */ + uint32_t : 16; + } FWMACTS0_b; + }; + + union + { + __IOM uint32_t FWMACTS1; /*!< (@ 0x00004674) MAC Table Search Register 1 */ + + struct + { + __IOM uint32_t MACMASP1 : 32; /*!< [31..0] MAC MAC Address Search Part 1 */ + } FWMACTS1_b; + }; + + union + { + __IOM uint32_t FWMACTSR0; /*!< (@ 0x00004678) MAC Table Search Result Register 0 */ + + struct + { + __IOM uint32_t MACSEF : 1; /*!< [0..0] MAC Search ECC Fail */ + __IM uint32_t MACSNF : 1; /*!< [1..1] MAC Search Not found */ + uint32_t : 6; + __IM uint32_t MACSLS : 1; /*!< [8..8] MAC Security Level Search */ + __IM uint32_t MACDES : 1; /*!< [9..9] MAC Dynamic Entry Search */ + __IM uint32_t MACHLDS : 1; /*!< [10..10] MAC Hardware Learning Disable Search */ + uint32_t : 5; + __IM uint32_t MACSCN : 10; /*!< [25..16] MAC Search Collision Number */ + uint32_t : 5; + __IM uint32_t MACTS : 1; /*!< [31..31] MAC Table Search */ + } FWMACTSR0_b; + }; + + union + { + __IM uint32_t FWMACTSR1; /*!< (@ 0x0000467C) MAC Table Search Result Register 1 */ + + struct + { + __IM uint32_t MACSSLVS : 7; /*!< [6..0] MAC Source Source Lock Vector Search */ + uint32_t : 9; + __IM uint32_t MACDSLVS : 7; /*!< [22..16] MAC Destination Source Lock Vector Search */ + uint32_t : 9; + } FWMACTSR1_b; + }; + + union + { + __IM uint32_t FWMACTSR20; /*!< (@ 0x00004680) MAC Table Search Result Register 20 */ + + struct + { + __IM uint32_t MACCSDS : 7; /*!< [6..0] MAC CPU Sub-Destination Search */ + uint32_t : 25; + } FWMACTSR20_b; + }; + __IM uint32_t RESERVED109[3]; + + union + { + __IM uint32_t FWMACTSR3; /*!< (@ 0x00004690) MAC Table Search Result Register 3 */ + + struct + { + __IM uint32_t MACDVS : 7; /*!< [6..0] MAC Destination Vector Search */ + uint32_t : 9; + __IM uint32_t MACIPVS : 3; /*!< [18..16] MAC Internal Priority Value Search */ + __IM uint32_t MACIPUS : 1; /*!< [19..19] MAC Internal Priority Update Search */ + __IM uint32_t MACEMES : 1; /*!< [20..20] MAC Ethernet Mirroring Enable Search */ + __IM uint32_t MACCMES : 1; /*!< [21..21] MAC CPU Mirroring Enable Search */ + uint32_t : 10; + } FWMACTSR3_b; + }; + __IM uint32_t RESERVED110[3]; + + union + { + __IOM uint32_t FWMACTR; /*!< (@ 0x000046A0) MAC Table Read Register */ + + struct + { + __IOM uint32_t MACAR : 10; /*!< [9..0] MAC Address Read */ + uint32_t : 22; + } FWMACTR_b; + }; + + union + { + __IM uint32_t FWMACTRR0; /*!< (@ 0x000046A4) MAC Table Read Result Register 0 */ + + struct + { + __IM uint32_t MACEVR : 1; /*!< [0..0] MAC Entry Valid Read */ + __IM uint32_t MACREF : 1; /*!< [1..1] MAC Read ECC Fail */ + uint32_t : 29; + __IM uint32_t MACTR : 1; /*!< [31..31] MAC Table Read */ + } FWMACTRR0_b; + }; + + union + { + __IM uint32_t FWMACTRR1; /*!< (@ 0x000046A8) MAC Table Read Result Register 1 */ + + struct + { + uint32_t : 8; + __IM uint32_t MACSLR : 1; /*!< [8..8] MAC Security Level Read */ + __IM uint32_t MACDER : 1; /*!< [9..9] MAC Dynamic Entry Read */ + __IM uint32_t MACHLDR : 1; /*!< [10..10] MAC Hardware Learn Disable Read */ + __IM uint32_t MACABR : 1; /*!< [11..11] MAC Aging Bit Read */ + uint32_t : 20; + } FWMACTRR1_b; + }; + + union + { + __IM uint32_t FWMACTRR2; /*!< (@ 0x000046AC) MAC Table Read Result Register 2 */ + + struct + { + __IM uint32_t MACMARP0 : 16; /*!< [15..0] MAC MAC address Read Part 0 */ + uint32_t : 16; + } FWMACTRR2_b; + }; + + union + { + __IM uint32_t FWMACTRR3; /*!< (@ 0x000046B0) MAC Table Read Result Register 3 */ + + struct + { + __IM uint32_t MACMARP1 : 32; /*!< [31..0] MAC MAC address Read Part 1 */ + } FWMACTRR3_b; + }; + + union + { + __IM uint32_t FWMACTRR4; /*!< (@ 0x000046B4) MAC Table Read Result Register 4 */ + + struct + { + __IM uint32_t MACSSLVR : 7; /*!< [6..0] MAC Source Source Lock Vector Read */ + uint32_t : 9; + __IM uint32_t MACDSLVR : 7; /*!< [22..16] MAC Destination Source Lock Vector Read */ + uint32_t : 9; + } FWMACTRR4_b; + }; + __IM uint32_t RESERVED111[2]; + + union + { + __IM uint32_t FWMACTRR50; /*!< (@ 0x000046C0) MAC Table Read Result Register 50 */ + + struct + { + __IM uint32_t MACCSDR : 7; /*!< [6..0] MAC CPU Sub-Destination Read */ + uint32_t : 25; + } FWMACTRR50_b; + }; + __IM uint32_t RESERVED112[3]; + + union + { + __IM uint32_t FWMACTRR6; /*!< (@ 0x000046D0) MAC Table Read Result Register 6 */ + + struct + { + __IM uint32_t MACDVR : 7; /*!< [6..0] MAC Destination Vector Read */ + uint32_t : 9; + __IM uint32_t MACIPVR : 3; /*!< [18..16] MAC Internal Priority Value Read */ + __IM uint32_t MACIPUR : 1; /*!< [19..19] MAC Internal Priority Update Read */ + __IM uint32_t MACEMER : 1; /*!< [20..20] MAC Ethernet Mirroring Enable Read */ + __IM uint32_t MACCMER : 1; /*!< [21..21] MAC CPU Mirroring Enable Read */ + uint32_t : 10; + } FWMACTRR6_b; + }; + __IM uint32_t RESERVED113[107]; + + union + { + __IOM uint32_t FWMACAGUSPC; /*!< (@ 0x00004880) MAC Aging US Prescaler Configuration Register */ + + struct + { + __IOM uint32_t MACAGUSP : 10; /*!< [9..0] MAC Aging US prescaler */ + uint32_t : 22; + } FWMACAGUSPC_b; + }; + + union + { + __IOM uint32_t FWMACAGC; /*!< (@ 0x00004884) MAC Aging Configuration Register */ + + struct + { + __IOM uint32_t MACAGT : 16; /*!< [15..0] MAC Aging Time */ + __IOM uint32_t MACAGE : 1; /*!< [16..16] MAC Aging Enable */ + __IOM uint32_t MACAGSL : 1; /*!< [17..17] MAC Aging Security Level */ + __IOM uint32_t MACAGPM : 1; /*!< [18..18] MAC Aging Polling Mode */ + uint32_t : 5; + __IM uint32_t MACDES : 1; /*!< [24..24] MAC Dynamic Entry Suppression */ + uint32_t : 3; + __IM uint32_t MACAGOG : 1; /*!< [28..28] MAC Aging OnGoing */ + __IM uint32_t MACDESOG : 1; /*!< [29..29] MAC Dynamic Entry Suppression OnGoing */ + uint32_t : 2; + } FWMACAGC_b; + }; + + union + { + __IM uint32_t FWMACAGM0; /*!< (@ 0x00004888) MAC Aging Monitoring Register 0 */ + + struct + { + __IM uint32_t AGMACAP0 : 16; /*!< [15..0] Aged MAC Address Part 0 */ + uint32_t : 16; + } FWMACAGM0_b; + }; + + union + { + __IM uint32_t FWMACAGM1; /*!< (@ 0x0000488C) MAC Aging Monitoring Register 1 */ + + struct + { + __IM uint32_t AGMACAP1 : 32; /*!< [31..0] Aged MAC Address Part 1 */ + } FWMACAGM1_b; + }; + __IM uint32_t RESERVED114[28]; + + union + { + __IOM uint32_t FWVLANTEC; /*!< (@ 0x00004900) VLAN Table Entry Configuration Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t VLANTMUE : 13; /*!< [28..16] VLAN Table Maximum Unsecure Entry */ + uint32_t : 3; + } FWVLANTEC_b; + }; + __IM uint32_t RESERVED115[3]; + + union + { + __IOM uint32_t FWVLANTL0; /*!< (@ 0x00004910) VLAN Table Learn Register 0 */ + + struct + { + uint32_t : 8; + __IOM uint32_t VLANSLL : 1; /*!< [8..8] VLAN Security Level Learn */ + uint32_t : 1; + __IOM uint32_t VLANHLDL : 1; /*!< [10..10] VLAN Hardware Learning Disable Learn */ + uint32_t : 5; + __IOM uint32_t VLANED : 1; /*!< [16..16] VLAN Entry Delete */ + uint32_t : 15; + } FWVLANTL0_b; + }; + + union + { + __IOM uint32_t FWVLANTL1; /*!< (@ 0x00004914) VLAN Table Learn Register 1 */ + + struct + { + __IOM uint32_t VLANVIDL : 12; /*!< [11..0] VLAN VID Learn */ + uint32_t : 20; + } FWVLANTL1_b; + }; + + union + { + __IOM uint32_t FWVLANTL2; /*!< (@ 0x00004918) VLAN Table Learn Register 2 */ + + struct + { + __IOM uint32_t VLANSLVL : 7; /*!< [6..0] VLAN Source Lock Vector Learn */ + uint32_t : 25; + } FWVLANTL2_b; + }; + __IM uint32_t RESERVED116; + + union + { + __IOM uint32_t FWVLANTL30; /*!< (@ 0x00004920) VLAN Table Learn Register 30 */ + + struct + { + __IOM uint32_t VLANCSDL : 7; /*!< [6..0] VLAN CPU Sub-Destination Learn */ + uint32_t : 25; + } FWVLANTL30_b; + }; + __IM uint32_t RESERVED117[3]; + + union + { + __IOM uint32_t FWVLANTL4; /*!< (@ 0x00004930) VLAN Table Learn Register 4 */ + + struct + { + __IOM uint32_t VLANDVL : 7; /*!< [6..0] VLAN Destination Vector Learn */ + uint32_t : 9; + __IOM uint32_t VLANIPVL : 3; /*!< [18..16] VLAN Internal Priority Value Learn */ + __IOM uint32_t VLANIPUL : 1; /*!< [19..19] VLAN Internal Priority Update Learn */ + __IOM uint32_t VLANEMEL : 1; /*!< [20..20] VLAN Ethernet Mirroring Enable Learn */ + __IOM uint32_t VLANCMEL : 1; /*!< [21..21] VLAN CPU Mirroring Enable Learn */ + uint32_t : 10; + } FWVLANTL4_b; + }; + + union + { + __IM uint32_t FWVLANTLR; /*!< (@ 0x00004934) VLAN Table Learn Result Register */ + + struct + { + __IM uint32_t VLANLF : 1; /*!< [0..0] VLAN Learn Fail */ + __IM uint32_t VLANLSF : 1; /*!< [1..1] VLAN Learn Security Fail */ + __IM uint32_t VLANLEF : 1; /*!< [2..2] VLAN Learn ECC Fail */ + __IM uint32_t VLANLO : 1; /*!< [3..3] VLAN Learn Overwrite */ + uint32_t : 27; + __IM uint32_t VLANTL : 1; /*!< [31..31] VLAN Table Learn */ + } FWVLANTLR_b; + }; + __IM uint32_t RESERVED118[2]; + + union + { + __IOM uint32_t FWVLANTIM; /*!< (@ 0x00004940) VLAN Table Initialization Monitoring Register */ + + struct + { + __IOM uint32_t VLANTIOG : 1; /*!< [0..0] VLAN Table Initialization Ongoing */ + __IM uint32_t VLANTR : 1; /*!< [1..1] VLAN Table Ready */ + uint32_t : 30; + } FWVLANTIM_b; + }; + + union + { + __IM uint32_t FWVLANTEM; /*!< (@ 0x00004944) VLAN Table Entry Monitoring Register */ + + struct + { + __IM uint32_t VLANTEN : 13; /*!< [12..0] VLAN Table Entry Number */ + uint32_t : 3; + __IM uint32_t VLANTUEN : 13; /*!< [28..16] VLAN Table Unsecure Entry Number */ + uint32_t : 3; + } FWVLANTEM_b; + }; + __IM uint32_t RESERVED119[2]; + + union + { + __IOM uint32_t FWVLANTS; /*!< (@ 0x00004950) VLAN Table Search Register */ + + struct + { + __IOM uint32_t VLANVIDS : 12; /*!< [11..0] VLAN VID Search */ + uint32_t : 20; + } FWVLANTS_b; + }; + + union + { + __IM uint32_t FWVLANTSR0; /*!< (@ 0x00004954) VLAN Table Search Result Register 0 */ + + struct + { + __IM uint32_t VLANSEF : 1; /*!< [0..0] VLAN Search ECC Fail */ + __IM uint32_t VLANSNF : 1; /*!< [1..1] VLAN Search Not found */ + uint32_t : 6; + __IM uint32_t VLANSLS : 1; /*!< [8..8] VLAN Security Level Search */ + uint32_t : 1; + __IM uint32_t VLANHLDS : 1; /*!< [10..10] VLAN Hardware Learning Disable Search */ + uint32_t : 20; + __IM uint32_t VLANTS : 1; /*!< [31..31] VLAN Table Search */ + } FWVLANTSR0_b; + }; + + union + { + __IM uint32_t FWVLANTSR1; /*!< (@ 0x00004958) VLAN Table Search Result Register 1 */ + + struct + { + __IM uint32_t VLANSLVS : 7; /*!< [6..0] VLAN Source Lock Vector Search */ + uint32_t : 25; + } FWVLANTSR1_b; + }; + __IM uint32_t RESERVED120; + + union + { + __IM uint32_t FWVLANTSR20; /*!< (@ 0x00004960) VLAN Table Search Result Register 20 */ + + struct + { + __IM uint32_t VLANCSDS : 7; /*!< [6..0] VLAN CPU Sub-Destination Search */ + uint32_t : 25; + } FWVLANTSR20_b; + }; + __IM uint32_t RESERVED121[3]; + + union + { + __IM uint32_t FWVLANTSR3; /*!< (@ 0x00004970) VLAN Table Search Result Register 3 */ + + struct + { + __IM uint32_t VLANDVS : 7; /*!< [6..0] VLAN Destination Vector Search */ + uint32_t : 9; + __IM uint32_t VLANIPVS : 3; /*!< [18..16] VLAN Internal Priority Value Search */ + __IM uint32_t VLANIPUS : 1; /*!< [19..19] VLAN Internal Priority Update Search */ + __IM uint32_t VLANEMES : 1; /*!< [20..20] VLAN Ethernet Mirroring Enable Search */ + __IM uint32_t VLANCMES : 1; /*!< [21..21] VLAN CPU Mirroring Enable Search */ + uint32_t : 10; + } FWVLANTSR3_b; + }; + __IM uint32_t RESERVED122[35]; + + union + { + __IOM uint32_t FWPBFC0; /*!< (@ 0x00004A00) Port Based Forwarding Configuration Register + * 0 */ + + struct + { + __IOM uint32_t PBDV : 7; /*!< [6..0] Port Based Destination Vector */ + uint32_t : 9; + __IOM uint32_t PBIPV : 3; /*!< [18..16] Port Based Internal Priority Value */ + __IOM uint32_t PBIPU : 1; /*!< [19..19] Port Based Internal Priority Update */ + __IOM uint32_t PBEME : 1; /*!< [20..20] Port Based Ethernet Mirroring Enabled */ + __IOM uint32_t PBCME : 1; /*!< [21..21] Port Based CPU Mirroring Enabled */ + __IOM uint32_t PBSL : 1; /*!< [22..22] Port Based Security Level */ + __IOM uint32_t IP4PDE : 1; /*!< [23..23] IPv4 Priority Decode Enable */ + __IOM uint32_t IP4PDM : 1; /*!< [24..24] IPv4 Priority Decode Mode */ + __IOM uint32_t IP6PDE : 1; /*!< [25..25] IPv6 Priority Decode Enable */ + __IOM uint32_t FAIFP : 1; /*!< [26..26] Force All Input Frame Priority Enable */ + uint32_t : 5; + } FWPBFC0_b; + }; + + union + { + __IOM uint32_t FWPBFCSDC00; /*!< (@ 0x00004A04) Port Based Forwarding CSD Configuration Register + * 00 */ + + struct + { + __IOM uint32_t PBCSD : 7; /*!< [6..0] Port Based CPU Sub Destination */ + uint32_t : 25; + } FWPBFCSDC00_b; + }; + __IM uint32_t RESERVED123[2]; + + union + { + __IOM uint32_t FWPBFC1; /*!< (@ 0x00004A10) Port Based Forwarding Configuration Register + * 1 */ + + struct + { + __IOM uint32_t PBDV : 7; /*!< [6..0] Port Based Destination Vector */ + uint32_t : 9; + __IOM uint32_t PBIPV : 3; /*!< [18..16] Port Based Internal Priority Value */ + __IOM uint32_t PBIPU : 1; /*!< [19..19] Port Based Internal Priority Update */ + __IOM uint32_t PBEME : 1; /*!< [20..20] Port Based Ethernet Mirroring Enabled */ + __IOM uint32_t PBCME : 1; /*!< [21..21] Port Based CPU Mirroring Enabled */ + __IOM uint32_t PBSL : 1; /*!< [22..22] Port Based Security Level */ + __IOM uint32_t IP4PDE : 1; /*!< [23..23] IPv4 Priority Decode Enable */ + __IOM uint32_t IP4PDM : 1; /*!< [24..24] IPv4 Priority Decode Mode */ + __IOM uint32_t IP6PDE : 1; /*!< [25..25] IPv6 Priority Decode Enable */ + __IOM uint32_t FAIFP : 1; /*!< [26..26] Force All Input Frame Priority Enable */ + uint32_t : 5; + } FWPBFC1_b; + }; + + union + { + __IOM uint32_t FWPBFCSDC01; /*!< (@ 0x00004A14) Port Based Forwarding CSD Configuration Register + * 01 */ + + struct + { + __IOM uint32_t PBCSD : 7; /*!< [6..0] Port Based CPU Sub Destination */ + uint32_t : 25; + } FWPBFCSDC01_b; + }; + __IM uint32_t RESERVED124[2]; + + union + { + __IOM uint32_t FWPBFC2; /*!< (@ 0x00004A20) Port Based Forwarding Configuration Register + * 2 */ + + struct + { + __IOM uint32_t PBDV : 7; /*!< [6..0] Port Based Destination Vector */ + uint32_t : 9; + __IOM uint32_t PBIPV : 3; /*!< [18..16] Port Based Internal Priority Value */ + __IOM uint32_t PBIPU : 1; /*!< [19..19] Port Based Internal Priority Update */ + __IOM uint32_t PBEME : 1; /*!< [20..20] Port Based Ethernet Mirroring Enabled */ + __IOM uint32_t PBCME : 1; /*!< [21..21] Port Based CPU Mirroring Enabled */ + __IOM uint32_t PBSL : 1; /*!< [22..22] Port Based Security Level */ + __IOM uint32_t IP4PDE : 1; /*!< [23..23] IPv4 Priority Decode Enable */ + __IOM uint32_t IP4PDM : 1; /*!< [24..24] IPv4 Priority Decode Mode */ + __IOM uint32_t IP6PDE : 1; /*!< [25..25] IPv6 Priority Decode Enable */ + __IOM uint32_t FAIFP : 1; /*!< [26..26] Force All Input Frame Priority Enable */ + uint32_t : 5; + } FWPBFC2_b; + }; + + union + { + __IOM uint32_t FWPBFCSDC02; /*!< (@ 0x00004A24) Port Based Forwarding CSD Configuration Register + * 02 */ + + struct + { + __IOM uint32_t PBCSD : 7; /*!< [6..0] Port Based CPU Sub Destination */ + uint32_t : 25; + } FWPBFCSDC02_b; + }; + __IM uint32_t RESERVED125[246]; + + union + { + __IOM uint32_t FWL23URL0; /*!< (@ 0x00004E00) Layer 2/Layer 3 Update Rule Learn Register 0 */ + + struct + { + __IOM uint32_t L23URNL : 8; /*!< [7..0] Layer 2/Layer 3 Update Routing Number Learn */ + uint32_t : 8; + __IOM uint32_t L23URPVL : 7; /*!< [22..16] Layer 2/Layer 3 Update Routing Port Valid Learn */ + uint32_t : 9; + } FWL23URL0_b; + }; + + union + { + __IOM uint32_t FWL23URL1; /*!< (@ 0x00004E04) Layer 2/Layer 3 Update Rule Learn Register 1 */ + + struct + { + __IOM uint32_t L23UMDALP0 : 16; /*!< [15..0] Layer 2/Layer 3 Update MAC Destination Address Learn + * Part 0 */ + __IOM uint32_t L23UTTLUL : 1; /*!< [16..16] Layer 2/Layer 3 Update Time To Live Update Learn */ + __IOM uint32_t L23UMDAUL : 1; /*!< [17..17] Layer 2/Layer 3 Update MAC Destination Address Update + * Learn */ + __IOM uint32_t L23UMSAUL : 1; /*!< [18..18] Layer 2/Layer 3 Update MAC Source Address Update Learn */ + __IOM uint32_t L23UCVIDUL : 1; /*!< [19..19] Layer 2/Layer 3 Update C-TAG VID Update Learn */ + __IOM uint32_t L23UCPCPUL : 1; /*!< [20..20] Layer 2/Layer 3 Update C-TAG PCP Update Learn */ + __IOM uint32_t L23UCDEIUL : 1; /*!< [21..21] Layer 2/Layer 3 Update C-TAG DEI Update Learn */ + __IOM uint32_t L23USVIDUL : 1; /*!< [22..22] Layer 2/Layer 3 Update S-TAG VID Update Learn */ + __IOM uint32_t L23USPCPUL : 1; /*!< [23..23] Layer 2/Layer 3 Update S-TAG PCP Update Learn */ + __IOM uint32_t L23USDEIUL : 1; /*!< [24..24] Layer 2/Layer 3 Update S-TAG DEI Update Learn */ + __IOM uint32_t L23URTUL : 2; /*!< [26..25] Layer 2/Layer 3 Update R-TAG Update Learn */ + uint32_t : 5; + } FWL23URL1_b; + }; + + union + { + __IOM uint32_t FWL23URL2; /*!< (@ 0x00004E08) Layer 2/Layer 3 Update Rule Learn Register 2 */ + + struct + { + __IOM uint32_t L23UMDALP1 : 32; /*!< [31..0] Layer 2/Layer 3 Update MAC Destination Address Learn + * Part 1 */ + } FWL23URL2_b; + }; + + union + { + __IOM uint32_t FWL23URL3; /*!< (@ 0x00004E0C) Layer 2/Layer 3 Update Rule Learn Register 3 */ + + struct + { + __IOM uint32_t L23UCVIDL : 12; /*!< [11..0] Layer 2/Layer 3 Update C-TAG VID Learn */ + __IOM uint32_t L23UCPCPL : 3; /*!< [14..12] Layer 2/Layer 3 Update C-TAG PCP Learn */ + __IOM uint32_t L23UCDEIL : 1; /*!< [15..15] Layer 2/Layer 3 Update C-TAG DEI Learn */ + __IOM uint32_t L23USVIDL : 12; /*!< [27..16] Layer 2/Layer 3 Update S-TAG VID Learn */ + __IOM uint32_t L23USPCPL : 3; /*!< [30..28] Layer 2/Layer 3 Update S-TAG PCP Learn */ + __IOM uint32_t L23USDEIL : 1; /*!< [31..31] Layer 2/Layer 3 Update S-TAG DEI Learn */ + } FWL23URL3_b; + }; + + union + { + __IM uint32_t FWL23URLR; /*!< (@ 0x00004E10) Layer 2/Layer 3 Update Rule Learn Result Register */ + + struct + { + __IM uint32_t L23ULF : 1; /*!< [0..0] Layer 2/Layer 3 Update Learn Fail */ + uint32_t : 30; + __IM uint32_t L23URL : 1; /*!< [31..31] Layer 2/Layer 3 Update Rule Learn */ + } FWL23URLR_b; + }; + __IM uint32_t RESERVED126[3]; + + union + { + __IOM uint32_t FWL23UTIM; /*!< (@ 0x00004E20) Layer 2/Layer 3 Update Table Initialization Monitoring + * Register */ + + struct + { + __IOM uint32_t L23UTIOG : 1; /*!< [0..0] Layer 2/Layer 3 Update Table Initialization Ongoing */ + __IM uint32_t L23UTR : 1; /*!< [1..1] Layer 2/Layer 3 Update Table Ready */ + uint32_t : 30; + } FWL23UTIM_b; + }; + __IM uint32_t RESERVED127[3]; + + union + { + __IOM uint32_t FWL23URR; /*!< (@ 0x00004E30) Layer 2/Layer 3 Update Rule Read Register */ + + struct + { + __IOM uint32_t L23RNR : 8; /*!< [7..0] Layer 2/Layer 3 Routing Number Read */ + uint32_t : 24; + } FWL23URR_b; + }; + + union + { + __IM uint32_t FWL23URRR0; /*!< (@ 0x00004E34) Layer 2/Layer 3 Update Rule Read Result Register + * 0 */ + + struct + { + __IM uint32_t L23URPVR : 7; /*!< [6..0] Layer 2/Layer 3 Update Routing Port Valid Read */ + uint32_t : 9; + __IM uint32_t L23UREF : 1; /*!< [16..16] Layer 2/Layer 3 Update Read ECC Fail */ + uint32_t : 14; + __IM uint32_t L23URR : 1; /*!< [31..31] Layer 2/Layer 3 Update Rule Read */ + } FWL23URRR0_b; + }; + + union + { + __IM uint32_t FWL23URRR1; /*!< (@ 0x00004E38) Layer 2/Layer 3 Update Rule Read Result Register + * 1 */ + + struct + { + __IM uint32_t L23UMDARP0 : 16; /*!< [15..0] Layer 2/Layer 3 MAC Destination Address Read Part 0 */ + __IM uint32_t L23UTTLUR : 1; /*!< [16..16] Layer 2/Layer 3 Time To Live Update Read */ + __IM uint32_t L23UMDAUR : 1; /*!< [17..17] Layer 2/Layer 3 MAC Destination Address Update Read */ + __IM uint32_t L23UMSAUR : 1; /*!< [18..18] Layer 2/Layer 3 MAC Source Address Update Read */ + __IM uint32_t L23UCVIDUR : 1; /*!< [19..19] Layer 2/Layer 3 C-TAG VID Update Read */ + __IM uint32_t L23UCPCPUR : 1; /*!< [20..20] Layer 2/Layer 3 C-TAG PCP Update Read */ + __IM uint32_t L23UCDEIUR : 1; /*!< [21..21] Layer 2/Layer 3 C-TAG DEI Update Read */ + __IM uint32_t L23USVIDUR : 1; /*!< [22..22] Layer 2/Layer 3 S-TAG VID Update Read */ + __IM uint32_t L23USPCPUR : 1; /*!< [23..23] Layer 2/Layer 3 S-TAG PCP Update Read */ + __IM uint32_t L23USDEIUR : 1; /*!< [24..24] Layer 2/Layer 3 S-TAG DEI Update Read */ + __IM uint32_t L23URTUR : 2; /*!< [26..25] Layer 2/Layer 3 R-TAG Update Read */ + uint32_t : 5; + } FWL23URRR1_b; + }; + + union + { + __IM uint32_t FWL23URRR2; /*!< (@ 0x00004E3C) Layer 2/Layer 3 Update Rule Read Result Register + * 2 */ + + struct + { + __IM uint32_t L23UMDARP1 : 32; /*!< [31..0] Layer 2/Layer 3 MAC Destination Address Read Part 1 */ + } FWL23URRR2_b; + }; + + union + { + __IM uint32_t FWL23URRR3; /*!< (@ 0x00004E40) Layer 2/Layer 3 Update Rule Read Result Register + * 3 */ + + struct + { + __IM uint32_t L23UCVIDR : 12; /*!< [11..0] Layer 2/Layer 3 Update MAC C-TAG VID Read */ + __IM uint32_t L23UCPCPR : 3; /*!< [14..12] Layer 2/Layer 3 Update MAC C-TAG PCP Read */ + __IM uint32_t L23UCDEIR : 1; /*!< [15..15] Layer 2/Layer 3 Update MAC C-TAG DEI Read */ + __IM uint32_t L23USVIDR : 12; /*!< [27..16] Layer 2/Layer 3 Update MAC S-TAG VID Read */ + __IM uint32_t L23USPCPR : 3; /*!< [30..28] Layer 2/Layer 3 Update MAC S-TAG PCP Read */ + __IM uint32_t L23USDEIR : 1; /*!< [31..31] Layer 2/Layer 3 Update MAC S-TAG DEI Read */ + } FWL23URRR3_b; + }; + __IM uint32_t RESERVED128[47]; + + union + { + __IOM uint32_t FWL23URMC0; /*!< (@ 0x00004F00) Layer 2/Layer 3 Update ReMapping Configuration + * Register 0 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC0_b; + }; + + union + { + __IOM uint32_t FWL23URMC1; /*!< (@ 0x00004F04) Layer 2/Layer 3 Update ReMapping Configuration + * Register 1 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC1_b; + }; + + union + { + __IOM uint32_t FWL23URMC2; /*!< (@ 0x00004F08) Layer 2/Layer 3 Update ReMapping Configuration + * Register 2 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC2_b; + }; + + union + { + __IOM uint32_t FWL23URMC3; /*!< (@ 0x00004F0C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 3 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC3_b; + }; + + union + { + __IOM uint32_t FWL23URMC4; /*!< (@ 0x00004F10) Layer 2/Layer 3 Update ReMapping Configuration + * Register 4 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC4_b; + }; + + union + { + __IOM uint32_t FWL23URMC5; /*!< (@ 0x00004F14) Layer 2/Layer 3 Update ReMapping Configuration + * Register 5 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC5_b; + }; + + union + { + __IOM uint32_t FWL23URMC6; /*!< (@ 0x00004F18) Layer 2/Layer 3 Update ReMapping Configuration + * Register 6 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC6_b; + }; + + union + { + __IOM uint32_t FWL23URMC7; /*!< (@ 0x00004F1C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 7 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC7_b; + }; + + union + { + __IOM uint32_t FWL23URMC8; /*!< (@ 0x00004F20) Layer 2/Layer 3 Update ReMapping Configuration + * Register 8 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC8_b; + }; + + union + { + __IOM uint32_t FWL23URMC9; /*!< (@ 0x00004F24) Layer 2/Layer 3 Update ReMapping Configuration + * Register 9 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC9_b; + }; + + union + { + __IOM uint32_t FWL23URMC10; /*!< (@ 0x00004F28) Layer 2/Layer 3 Update ReMapping Configuration + * Register 10 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC10_b; + }; + + union + { + __IOM uint32_t FWL23URMC11; /*!< (@ 0x00004F2C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 11 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC11_b; + }; + + union + { + __IOM uint32_t FWL23URMC12; /*!< (@ 0x00004F30) Layer 2/Layer 3 Update ReMapping Configuration + * Register 12 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC12_b; + }; + + union + { + __IOM uint32_t FWL23URMC13; /*!< (@ 0x00004F34) Layer 2/Layer 3 Update ReMapping Configuration + * Register 13 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC13_b; + }; + + union + { + __IOM uint32_t FWL23URMC14; /*!< (@ 0x00004F38) Layer 2/Layer 3 Update ReMapping Configuration + * Register 14 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC14_b; + }; + + union + { + __IOM uint32_t FWL23URMC15; /*!< (@ 0x00004F3C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 15 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC15_b; + }; + + union + { + __IOM uint32_t FWL23URMC16; /*!< (@ 0x00004F40) Layer 2/Layer 3 Update ReMapping Configuration + * Register 16 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC16_b; + }; + + union + { + __IOM uint32_t FWL23URMC17; /*!< (@ 0x00004F44) Layer 2/Layer 3 Update ReMapping Configuration + * Register 17 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC17_b; + }; + + union + { + __IOM uint32_t FWL23URMC18; /*!< (@ 0x00004F48) Layer 2/Layer 3 Update ReMapping Configuration + * Register 18 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC18_b; + }; + + union + { + __IOM uint32_t FWL23URMC19; /*!< (@ 0x00004F4C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 19 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC19_b; + }; + + union + { + __IOM uint32_t FWL23URMC20; /*!< (@ 0x00004F50) Layer 2/Layer 3 Update ReMapping Configuration + * Register 20 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC20_b; + }; + + union + { + __IOM uint32_t FWL23URMC21; /*!< (@ 0x00004F54) Layer 2/Layer 3 Update ReMapping Configuration + * Register 21 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC21_b; + }; + + union + { + __IOM uint32_t FWL23URMC22; /*!< (@ 0x00004F58) Layer 2/Layer 3 Update ReMapping Configuration + * Register 22 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC22_b; + }; + + union + { + __IOM uint32_t FWL23URMC23; /*!< (@ 0x00004F5C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 23 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC23_b; + }; + + union + { + __IOM uint32_t FWL23URMC24; /*!< (@ 0x00004F60) Layer 2/Layer 3 Update ReMapping Configuration + * Register 24 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC24_b; + }; + + union + { + __IOM uint32_t FWL23URMC25; /*!< (@ 0x00004F64) Layer 2/Layer 3 Update ReMapping Configuration + * Register 25 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC25_b; + }; + + union + { + __IOM uint32_t FWL23URMC26; /*!< (@ 0x00004F68) Layer 2/Layer 3 Update ReMapping Configuration + * Register 26 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC26_b; + }; + + union + { + __IOM uint32_t FWL23URMC27; /*!< (@ 0x00004F6C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 27 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC27_b; + }; + + union + { + __IOM uint32_t FWL23URMC28; /*!< (@ 0x00004F70) Layer 2/Layer 3 Update ReMapping Configuration + * Register 28 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC28_b; + }; + + union + { + __IOM uint32_t FWL23URMC29; /*!< (@ 0x00004F74) Layer 2/Layer 3 Update ReMapping Configuration + * Register 29 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC29_b; + }; + + union + { + __IOM uint32_t FWL23URMC30; /*!< (@ 0x00004F78) Layer 2/Layer 3 Update ReMapping Configuration + * Register 30 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC30_b; + }; + + union + { + __IOM uint32_t FWL23URMC31; /*!< (@ 0x00004F7C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 31 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC31_b; + }; + __IM uint32_t RESERVED129[32]; + + union + { + __IOM uint32_t FWPMFGC0; /*!< (@ 0x00005000) PSFP MSDU Filter Global Configuration Register + * 0 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC0_b; + }; + + union + { + __IOM uint32_t FWPMFGC1; /*!< (@ 0x00005004) PSFP MSDU Filter Global Configuration Register + * 1 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC1_b; + }; + + union + { + __IOM uint32_t FWPMFGC2; /*!< (@ 0x00005008) PSFP MSDU Filter Global Configuration Register + * 2 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC2_b; + }; + + union + { + __IOM uint32_t FWPMFGC3; /*!< (@ 0x0000500C) PSFP MSDU Filter Global Configuration Register + * 3 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC3_b; + }; + + union + { + __IOM uint32_t FWPMFGC4; /*!< (@ 0x00005010) PSFP MSDU Filter Global Configuration Register + * 4 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC4_b; + }; + + union + { + __IOM uint32_t FWPMFGC5; /*!< (@ 0x00005014) PSFP MSDU Filter Global Configuration Register + * 5 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC5_b; + }; + + union + { + __IOM uint32_t FWPMFGC6; /*!< (@ 0x00005018) PSFP MSDU Filter Global Configuration Register + * 6 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC6_b; + }; + + union + { + __IOM uint32_t FWPMFGC7; /*!< (@ 0x0000501C) PSFP MSDU Filter Global Configuration Register + * 7 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC7_b; + }; + + union + { + __IOM uint32_t FWPMFGC8; /*!< (@ 0x00005020) PSFP MSDU Filter Global Configuration Register + * 8 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC8_b; + }; + + union + { + __IOM uint32_t FWPMFGC9; /*!< (@ 0x00005024) PSFP MSDU Filter Global Configuration Register + * 9 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC9_b; + }; + + union + { + __IOM uint32_t FWPMFGC10; /*!< (@ 0x00005028) PSFP MSDU Filter Global Configuration Register + * 10 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC10_b; + }; + + union + { + __IOM uint32_t FWPMFGC11; /*!< (@ 0x0000502C) PSFP MSDU Filter Global Configuration Register + * 11 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC11_b; + }; + + union + { + __IOM uint32_t FWPMFGC12; /*!< (@ 0x00005030) PSFP MSDU Filter Global Configuration Register + * 12 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC12_b; + }; + + union + { + __IOM uint32_t FWPMFGC13; /*!< (@ 0x00005034) PSFP MSDU Filter Global Configuration Register + * 13 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC13_b; + }; + + union + { + __IOM uint32_t FWPMFGC14; /*!< (@ 0x00005038) PSFP MSDU Filter Global Configuration Register + * 14 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC14_b; + }; + + union + { + __IOM uint32_t FWPMFGC15; /*!< (@ 0x0000503C) PSFP MSDU Filter Global Configuration Register + * 15 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC15_b; + }; + __IM uint32_t RESERVED130[368]; + + union + { + __IOM uint32_t FWPMTRFC0; /*!< (@ 0x00005600) PSFP Meter Filter Configuration Register 0 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC0_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC0; /*!< (@ 0x00005604) PSFP Meter CBS Configuration Register 0 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC0_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC0; /*!< (@ 0x00005608) PSFP Meter CIR Configuration Register 0 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC0_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC0; /*!< (@ 0x0000560C) PSFP Meter EBS Configuration Register 0 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC0_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC0; /*!< (@ 0x00005610) PSFP Meter EIR Configuration Register 0 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC0_b; + }; + + union + { + __IM uint32_t FWPMTRFM0; /*!< (@ 0x00005614) PSFP Meter Filter Monitoring Register 0 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM0_b; + }; + __IM uint32_t RESERVED131[2]; + + union + { + __IOM uint32_t FWPMTRFC1; /*!< (@ 0x00005620) PSFP Meter Filter Configuration Register 1 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC1_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC1; /*!< (@ 0x00005624) PSFP Meter CBS Configuration Register 1 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC1_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC1; /*!< (@ 0x00005628) PSFP Meter CIR Configuration Register 1 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC1_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC1; /*!< (@ 0x0000562C) PSFP Meter EBS Configuration Register 1 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC1_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC1; /*!< (@ 0x00005630) PSFP Meter EIR Configuration Register 1 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC1_b; + }; + + union + { + __IM uint32_t FWPMTRFM1; /*!< (@ 0x00005634) PSFP Meter Filter Monitoring Register 1 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM1_b; + }; + __IM uint32_t RESERVED132[2]; + + union + { + __IOM uint32_t FWPMTRFC2; /*!< (@ 0x00005640) PSFP Meter Filter Configuration Register 2 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC2_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC2; /*!< (@ 0x00005644) PSFP Meter CBS Configuration Register 2 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC2_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC2; /*!< (@ 0x00005648) PSFP Meter CIR Configuration Register 2 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC2_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC2; /*!< (@ 0x0000564C) PSFP Meter EBS Configuration Register 2 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC2_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC2; /*!< (@ 0x00005650) PSFP Meter EIR Configuration Register 2 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC2_b; + }; + + union + { + __IM uint32_t FWPMTRFM2; /*!< (@ 0x00005654) PSFP Meter Filter Monitoring Register 2 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM2_b; + }; + __IM uint32_t RESERVED133[2]; + + union + { + __IOM uint32_t FWPMTRFC3; /*!< (@ 0x00005660) PSFP Meter Filter Configuration Register 3 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC3_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC3; /*!< (@ 0x00005664) PSFP Meter CBS Configuration Register 3 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC3_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC3; /*!< (@ 0x00005668) PSFP Meter CIR Configuration Register 3 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC3_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC3; /*!< (@ 0x0000566C) PSFP Meter EBS Configuration Register 3 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC3_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC3; /*!< (@ 0x00005670) PSFP Meter EIR Configuration Register 3 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC3_b; + }; + + union + { + __IM uint32_t FWPMTRFM3; /*!< (@ 0x00005674) PSFP Meter Filter Monitoring Register 3 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM3_b; + }; + __IM uint32_t RESERVED134[2]; + + union + { + __IOM uint32_t FWPMTRFC4; /*!< (@ 0x00005680) PSFP Meter Filter Configuration Register 4 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC4_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC4; /*!< (@ 0x00005684) PSFP Meter CBS Configuration Register 4 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC4_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC4; /*!< (@ 0x00005688) PSFP Meter CIR Configuration Register 4 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC4_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC4; /*!< (@ 0x0000568C) PSFP Meter EBS Configuration Register 4 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC4_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC4; /*!< (@ 0x00005690) PSFP Meter EIR Configuration Register 4 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC4_b; + }; + + union + { + __IM uint32_t FWPMTRFM4; /*!< (@ 0x00005694) PSFP Meter Filter Monitoring Register 4 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM4_b; + }; + __IM uint32_t RESERVED135[2]; + + union + { + __IOM uint32_t FWPMTRFC5; /*!< (@ 0x000056A0) PSFP Meter Filter Configuration Register 5 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC5_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC5; /*!< (@ 0x000056A4) PSFP Meter CBS Configuration Register 5 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC5_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC5; /*!< (@ 0x000056A8) PSFP Meter CIR Configuration Register 5 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC5_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC5; /*!< (@ 0x000056AC) PSFP Meter EBS Configuration Register 5 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC5_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC5; /*!< (@ 0x000056B0) PSFP Meter EIR Configuration Register 5 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC5_b; + }; + + union + { + __IM uint32_t FWPMTRFM5; /*!< (@ 0x000056B4) PSFP Meter Filter Monitoring Register 5 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM5_b; + }; + __IM uint32_t RESERVED136[2]; + + union + { + __IOM uint32_t FWPMTRFC6; /*!< (@ 0x000056C0) PSFP Meter Filter Configuration Register 6 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC6_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC6; /*!< (@ 0x000056C4) PSFP Meter CBS Configuration Register 6 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC6_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC6; /*!< (@ 0x000056C8) PSFP Meter CIR Configuration Register 6 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC6_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC6; /*!< (@ 0x000056CC) PSFP Meter EBS Configuration Register 6 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC6_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC6; /*!< (@ 0x000056D0) PSFP Meter EIR Configuration Register 6 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC6_b; + }; + + union + { + __IM uint32_t FWPMTRFM6; /*!< (@ 0x000056D4) PSFP Meter Filter Monitoring Register 6 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM6_b; + }; + __IM uint32_t RESERVED137[2]; + + union + { + __IOM uint32_t FWPMTRFC7; /*!< (@ 0x000056E0) PSFP Meter Filter Configuration Register 7 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC7_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC7; /*!< (@ 0x000056E4) PSFP Meter CBS Configuration Register 7 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC7_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC7; /*!< (@ 0x000056E8) PSFP Meter CIR Configuration Register 7 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC7_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC7; /*!< (@ 0x000056EC) PSFP Meter EBS Configuration Register 7 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC7_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC7; /*!< (@ 0x000056F0) PSFP Meter EIR Configuration Register 7 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC7_b; + }; + + union + { + __IM uint32_t FWPMTRFM7; /*!< (@ 0x000056F4) PSFP Meter Filter Monitoring Register 7 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM7_b; + }; + __IM uint32_t RESERVED138[2]; + + union + { + __IOM uint32_t FWPMTRFC8; /*!< (@ 0x00005700) PSFP Meter Filter Configuration Register 8 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC8_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC8; /*!< (@ 0x00005704) PSFP Meter CBS Configuration Register 8 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC8_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC8; /*!< (@ 0x00005708) PSFP Meter CIR Configuration Register 8 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC8_b; + }; + __IM uint32_t RESERVED139[2]; + + union + { + __IM uint32_t FWPMTRFM8; /*!< (@ 0x00005714) PSFP Meter Filter Monitoring Register 8 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM8_b; + }; + __IM uint32_t RESERVED140[2]; + + union + { + __IOM uint32_t FWPMTRFC9; /*!< (@ 0x00005720) PSFP Meter Filter Configuration Register 9 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC9_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC9; /*!< (@ 0x00005724) PSFP Meter CBS Configuration Register 9 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC9_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC9; /*!< (@ 0x00005728) PSFP Meter CIR Configuration Register 9 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC9_b; + }; + __IM uint32_t RESERVED141[2]; + + union + { + __IM uint32_t FWPMTRFM9; /*!< (@ 0x00005734) PSFP Meter Filter Monitoring Register 9 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM9_b; + }; + __IM uint32_t RESERVED142[2]; + + union + { + __IOM uint32_t FWPMTRFC10; /*!< (@ 0x00005740) PSFP Meter Filter Configuration Register 10 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC10_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC10; /*!< (@ 0x00005744) PSFP Meter CBS Configuration Register 10 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC10_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC10; /*!< (@ 0x00005748) PSFP Meter CIR Configuration Register 10 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC10_b; + }; + __IM uint32_t RESERVED143[2]; + + union + { + __IM uint32_t FWPMTRFM10; /*!< (@ 0x00005754) PSFP Meter Filter Monitoring Register 10 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM10_b; + }; + __IM uint32_t RESERVED144[2]; + + union + { + __IOM uint32_t FWPMTRFC11; /*!< (@ 0x00005760) PSFP Meter Filter Configuration Register 11 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC11_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC11; /*!< (@ 0x00005764) PSFP Meter CBS Configuration Register 11 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC11_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC11; /*!< (@ 0x00005768) PSFP Meter CIR Configuration Register 11 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC11_b; + }; + __IM uint32_t RESERVED145[2]; + + union + { + __IM uint32_t FWPMTRFM11; /*!< (@ 0x00005774) PSFP Meter Filter Monitoring Register 11 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM11_b; + }; + __IM uint32_t RESERVED146[2]; + + union + { + __IOM uint32_t FWPMTRFC12; /*!< (@ 0x00005780) PSFP Meter Filter Configuration Register 12 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC12_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC12; /*!< (@ 0x00005784) PSFP Meter CBS Configuration Register 12 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC12_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC12; /*!< (@ 0x00005788) PSFP Meter CIR Configuration Register 12 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC12_b; + }; + __IM uint32_t RESERVED147[2]; + + union + { + __IM uint32_t FWPMTRFM12; /*!< (@ 0x00005794) PSFP Meter Filter Monitoring Register 12 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM12_b; + }; + __IM uint32_t RESERVED148[2]; + + union + { + __IOM uint32_t FWPMTRFC13; /*!< (@ 0x000057A0) PSFP Meter Filter Configuration Register 13 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC13_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC13; /*!< (@ 0x000057A4) PSFP Meter CBS Configuration Register 13 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC13_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC13; /*!< (@ 0x000057A8) PSFP Meter CIR Configuration Register 13 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC13_b; + }; + __IM uint32_t RESERVED149[2]; + + union + { + __IM uint32_t FWPMTRFM13; /*!< (@ 0x000057B4) PSFP Meter Filter Monitoring Register 13 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM13_b; + }; + __IM uint32_t RESERVED150[2]; + + union + { + __IOM uint32_t FWPMTRFC14; /*!< (@ 0x000057C0) PSFP Meter Filter Configuration Register 14 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC14_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC14; /*!< (@ 0x000057C4) PSFP Meter CBS Configuration Register 14 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC14_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC14; /*!< (@ 0x000057C8) PSFP Meter CIR Configuration Register 14 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC14_b; + }; + __IM uint32_t RESERVED151[2]; + + union + { + __IM uint32_t FWPMTRFM14; /*!< (@ 0x000057D4) PSFP Meter Filter Monitoring Register 14 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM14_b; + }; + __IM uint32_t RESERVED152[2]; + + union + { + __IOM uint32_t FWPMTRFC15; /*!< (@ 0x000057E0) PSFP Meter Filter Configuration Register 15 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC15_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC15; /*!< (@ 0x000057E4) PSFP Meter CBS Configuration Register 15 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC15_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC15; /*!< (@ 0x000057E8) PSFP Meter CIR Configuration Register 15 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC15_b; + }; + __IM uint32_t RESERVED153[2]; + + union + { + __IM uint32_t FWPMTRFM15; /*!< (@ 0x000057F4) PSFP Meter Filter Monitoring Register 15 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM15_b; + }; + __IM uint32_t RESERVED154[2]; + + union + { + __IOM uint32_t FWPMTRFC16; /*!< (@ 0x00005800) PSFP Meter Filter Configuration Register 16 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC16_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC16; /*!< (@ 0x00005804) PSFP Meter CBS Configuration Register 16 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC16_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC16; /*!< (@ 0x00005808) PSFP Meter CIR Configuration Register 16 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC16_b; + }; + __IM uint32_t RESERVED155[2]; + + union + { + __IM uint32_t FWPMTRFM16; /*!< (@ 0x00005814) PSFP Meter Filter Monitoring Register 16 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM16_b; + }; + __IM uint32_t RESERVED156[2]; + + union + { + __IOM uint32_t FWPMTRFC17; /*!< (@ 0x00005820) PSFP Meter Filter Configuration Register 17 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC17_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC17; /*!< (@ 0x00005824) PSFP Meter CBS Configuration Register 17 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC17_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC17; /*!< (@ 0x00005828) PSFP Meter CIR Configuration Register 17 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC17_b; + }; + __IM uint32_t RESERVED157[2]; + + union + { + __IM uint32_t FWPMTRFM17; /*!< (@ 0x00005834) PSFP Meter Filter Monitoring Register 17 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM17_b; + }; + __IM uint32_t RESERVED158[2]; + + union + { + __IOM uint32_t FWPMTRFC18; /*!< (@ 0x00005840) PSFP Meter Filter Configuration Register 18 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC18_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC18; /*!< (@ 0x00005844) PSFP Meter CBS Configuration Register 18 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC18_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC18; /*!< (@ 0x00005848) PSFP Meter CIR Configuration Register 18 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC18_b; + }; + __IM uint32_t RESERVED159[2]; + + union + { + __IM uint32_t FWPMTRFM18; /*!< (@ 0x00005854) PSFP Meter Filter Monitoring Register 18 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM18_b; + }; + __IM uint32_t RESERVED160[2]; + + union + { + __IOM uint32_t FWPMTRFC19; /*!< (@ 0x00005860) PSFP Meter Filter Configuration Register 19 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC19_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC19; /*!< (@ 0x00005864) PSFP Meter CBS Configuration Register 19 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC19_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC19; /*!< (@ 0x00005868) PSFP Meter CIR Configuration Register 19 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC19_b; + }; + __IM uint32_t RESERVED161[2]; + + union + { + __IM uint32_t FWPMTRFM19; /*!< (@ 0x00005874) PSFP Meter Filter Monitoring Register 19 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM19_b; + }; + __IM uint32_t RESERVED162[2]; + + union + { + __IOM uint32_t FWPMTRFC20; /*!< (@ 0x00005880) PSFP Meter Filter Configuration Register 20 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC20_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC20; /*!< (@ 0x00005884) PSFP Meter CBS Configuration Register 20 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC20_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC20; /*!< (@ 0x00005888) PSFP Meter CIR Configuration Register 20 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC20_b; + }; + __IM uint32_t RESERVED163[2]; + + union + { + __IM uint32_t FWPMTRFM20; /*!< (@ 0x00005894) PSFP Meter Filter Monitoring Register 20 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM20_b; + }; + __IM uint32_t RESERVED164[2]; + + union + { + __IOM uint32_t FWPMTRFC21; /*!< (@ 0x000058A0) PSFP Meter Filter Configuration Register 21 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC21_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC21; /*!< (@ 0x000058A4) PSFP Meter CBS Configuration Register 21 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC21_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC21; /*!< (@ 0x000058A8) PSFP Meter CIR Configuration Register 21 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC21_b; + }; + __IM uint32_t RESERVED165[2]; + + union + { + __IM uint32_t FWPMTRFM21; /*!< (@ 0x000058B4) PSFP Meter Filter Monitoring Register 21 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM21_b; + }; + __IM uint32_t RESERVED166[2]; + + union + { + __IOM uint32_t FWPMTRFC22; /*!< (@ 0x000058C0) PSFP Meter Filter Configuration Register 22 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC22_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC22; /*!< (@ 0x000058C4) PSFP Meter CBS Configuration Register 22 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC22_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC22; /*!< (@ 0x000058C8) PSFP Meter CIR Configuration Register 22 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC22_b; + }; + __IM uint32_t RESERVED167[2]; + + union + { + __IM uint32_t FWPMTRFM22; /*!< (@ 0x000058D4) PSFP Meter Filter Monitoring Register 22 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM22_b; + }; + __IM uint32_t RESERVED168[2]; + + union + { + __IOM uint32_t FWPMTRFC23; /*!< (@ 0x000058E0) PSFP Meter Filter Configuration Register 23 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC23_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC23; /*!< (@ 0x000058E4) PSFP Meter CBS Configuration Register 23 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC23_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC23; /*!< (@ 0x000058E8) PSFP Meter CIR Configuration Register 23 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC23_b; + }; + __IM uint32_t RESERVED169[2]; + + union + { + __IM uint32_t FWPMTRFM23; /*!< (@ 0x000058F4) PSFP Meter Filter Monitoring Register 23 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM23_b; + }; + __IM uint32_t RESERVED170[2]; + + union + { + __IOM uint32_t FWPMTRFC24; /*!< (@ 0x00005900) PSFP Meter Filter Configuration Register 24 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC24_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC24; /*!< (@ 0x00005904) PSFP Meter CBS Configuration Register 24 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC24_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC24; /*!< (@ 0x00005908) PSFP Meter CIR Configuration Register 24 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC24_b; + }; + __IM uint32_t RESERVED171[2]; + + union + { + __IM uint32_t FWPMTRFM24; /*!< (@ 0x00005914) PSFP Meter Filter Monitoring Register 24 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM24_b; + }; + __IM uint32_t RESERVED172[2]; + + union + { + __IOM uint32_t FWPMTRFC25; /*!< (@ 0x00005920) PSFP Meter Filter Configuration Register 25 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC25_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC25; /*!< (@ 0x00005924) PSFP Meter CBS Configuration Register 25 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC25_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC25; /*!< (@ 0x00005928) PSFP Meter CIR Configuration Register 25 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC25_b; + }; + __IM uint32_t RESERVED173[2]; + + union + { + __IM uint32_t FWPMTRFM25; /*!< (@ 0x00005934) PSFP Meter Filter Monitoring Register 25 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM25_b; + }; + __IM uint32_t RESERVED174[2]; + + union + { + __IOM uint32_t FWPMTRFC26; /*!< (@ 0x00005940) PSFP Meter Filter Configuration Register 26 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC26_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC26; /*!< (@ 0x00005944) PSFP Meter CBS Configuration Register 26 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC26_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC26; /*!< (@ 0x00005948) PSFP Meter CIR Configuration Register 26 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC26_b; + }; + __IM uint32_t RESERVED175[2]; + + union + { + __IM uint32_t FWPMTRFM26; /*!< (@ 0x00005954) PSFP Meter Filter Monitoring Register 26 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM26_b; + }; + __IM uint32_t RESERVED176[2]; + + union + { + __IOM uint32_t FWPMTRFC27; /*!< (@ 0x00005960) PSFP Meter Filter Configuration Register 27 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC27_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC27; /*!< (@ 0x00005964) PSFP Meter CBS Configuration Register 27 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC27_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC27; /*!< (@ 0x00005968) PSFP Meter CIR Configuration Register 27 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC27_b; + }; + __IM uint32_t RESERVED177[2]; + + union + { + __IM uint32_t FWPMTRFM27; /*!< (@ 0x00005974) PSFP Meter Filter Monitoring Register 27 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM27_b; + }; + __IM uint32_t RESERVED178[2]; + + union + { + __IOM uint32_t FWPMTRFC28; /*!< (@ 0x00005980) PSFP Meter Filter Configuration Register 28 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC28_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC28; /*!< (@ 0x00005984) PSFP Meter CBS Configuration Register 28 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC28_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC28; /*!< (@ 0x00005988) PSFP Meter CIR Configuration Register 28 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC28_b; + }; + __IM uint32_t RESERVED179[2]; + + union + { + __IM uint32_t FWPMTRFM28; /*!< (@ 0x00005994) PSFP Meter Filter Monitoring Register 28 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM28_b; + }; + __IM uint32_t RESERVED180[2]; + + union + { + __IOM uint32_t FWPMTRFC29; /*!< (@ 0x000059A0) PSFP Meter Filter Configuration Register 29 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC29_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC29; /*!< (@ 0x000059A4) PSFP Meter CBS Configuration Register 29 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC29_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC29; /*!< (@ 0x000059A8) PSFP Meter CIR Configuration Register 29 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC29_b; + }; + __IM uint32_t RESERVED181[2]; + + union + { + __IM uint32_t FWPMTRFM29; /*!< (@ 0x000059B4) PSFP Meter Filter Monitoring Register 29 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM29_b; + }; + __IM uint32_t RESERVED182[2]; + + union + { + __IOM uint32_t FWPMTRFC30; /*!< (@ 0x000059C0) PSFP Meter Filter Configuration Register 30 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC30_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC30; /*!< (@ 0x000059C4) PSFP Meter CBS Configuration Register 30 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC30_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC30; /*!< (@ 0x000059C8) PSFP Meter CIR Configuration Register 30 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC30_b; + }; + __IM uint32_t RESERVED183[2]; + + union + { + __IM uint32_t FWPMTRFM30; /*!< (@ 0x000059D4) PSFP Meter Filter Monitoring Register 30 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM30_b; + }; + __IM uint32_t RESERVED184[2]; + + union + { + __IOM uint32_t FWPMTRFC31; /*!< (@ 0x000059E0) PSFP Meter Filter Configuration Register 31 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC31_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC31; /*!< (@ 0x000059E4) PSFP Meter CBS Configuration Register 31 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC31_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC31; /*!< (@ 0x000059E8) PSFP Meter CIR Configuration Register 31 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC31_b; + }; + __IM uint32_t RESERVED185[2]; + + union + { + __IM uint32_t FWPMTRFM31; /*!< (@ 0x000059F4) PSFP Meter Filter Monitoring Register 31 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM31_b; + }; + __IM uint32_t RESERVED186[386]; + + union + { + __IOM uint32_t FWFTL0; /*!< (@ 0x00006000) FRER Table Learn Register 0 */ + + struct + { + __IOM uint32_t FEAL : 7; /*!< [6..0] FRER Entry Address Learn */ + uint32_t : 9; + __IOM uint32_t FSRPL : 7; /*!< [22..16] FRER Sequence Recovery Pointer Learn */ + uint32_t : 9; + } FWFTL0_b; + }; + + union + { + __IOM uint32_t FWFTL1; /*!< (@ 0x00006004) FRER Table Learn Register 1 */ + + struct + { + __IOM uint32_t FSHLL : 4; /*!< [3..0] FRER Sequence History Length Learn */ + uint32_t : 4; + __IOM uint32_t FTNSL : 1; /*!< [8..8] FRER Take No Sequence Learn */ + __IOM uint32_t FSRPVL : 1; /*!< [9..9] FRER Sequence Recovery Pointer Valid Learn */ + uint32_t : 6; + __IOM uint32_t FSRRTL : 10; /*!< [25..16] FRER Sequence Recovery Remaining Ticks Learn */ + uint32_t : 6; + } FWFTL1_b; + }; + + union + { + __IM uint32_t FWFTLR; /*!< (@ 0x00006008) FRER Table Learn Result Register */ + + struct + { + __IM uint32_t FLF : 1; /*!< [0..0] FRER Learn Fail */ + uint32_t : 30; + __IM uint32_t FTL : 1; /*!< [31..31] FRER Table Learn */ + } FWFTLR_b; + }; + __IM uint32_t RESERVED187; + + union + { + __IOM uint32_t FWFTOC; /*!< (@ 0x00006010) FRER Timeout Configuration Register */ + + struct + { + __IOM uint32_t TOT : 16; /*!< [15..0] Timeout Time (ms) */ + __IOM uint32_t TOCE : 1; /*!< [16..16] Timeout Check Enable */ + __IOM uint32_t TOOG : 1; /*!< [17..17] Timeout Ongoing */ + uint32_t : 14; + } FWFTOC_b; + }; + + union + { + __IOM uint32_t FWFTOPC; /*!< (@ 0x00006014) FRER Timeout Prescaler Configuration Register + * 0 */ + + struct + { + __IOM uint32_t USP : 10; /*!< [9..0] Microsecond Prescaler */ + uint32_t : 22; + } FWFTOPC_b; + }; + __IM uint32_t RESERVED188[2]; + + union + { + __IOM uint32_t FWFTIM; /*!< (@ 0x00006020) FRER Table Initialization Monitoring Register */ + + struct + { + __IOM uint32_t FTIOG : 1; /*!< [0..0] FRER Table Initialization Ongoing */ + __IM uint32_t FTR : 1; /*!< [1..1] FRER Table Ready */ + uint32_t : 30; + } FWFTIM_b; + }; + __IM uint32_t RESERVED189[3]; + + union + { + __IOM uint32_t FWFTR; /*!< (@ 0x00006030) FRER Table Read Register */ + + struct + { + __IOM uint32_t FEAR : 7; /*!< [6..0] FRER Entry Address Read */ + uint32_t : 25; + } FWFTR_b; + }; + + union + { + __IM uint32_t FWFTRR0; /*!< (@ 0x00006034) FRER Table Read Result Register 0 */ + + struct + { + __IM uint32_t FSHLR : 4; /*!< [3..0] FRER Sequence History Length Read */ + uint32_t : 4; + __IM uint32_t FTNSR : 1; /*!< [8..8] FRER Take No Sequence Read */ + __IM uint32_t FSRPVR : 1; /*!< [9..9] FRER Sequence Recovery Pointer Valid Read */ + uint32_t : 6; + __IM uint32_t FSRRTR : 10; /*!< [25..16] FRER Set Recovery Remaining Ticks Read */ + uint32_t : 4; + __IM uint32_t FTREF : 1; /*!< [30..30] FRER Table Read ECC Fail */ + __IM uint32_t FTR : 1; /*!< [31..31] FRER Table Read */ + } FWFTRR0_b; + }; + + union + { + __IM uint32_t FWFTRR1; /*!< (@ 0x00006038) FRER Table Read Result Register 1 */ + + struct + { + __IM uint32_t FSHR : 15; /*!< [14..0] FRER Sequence History Read */ + uint32_t : 1; + __IM uint32_t FSRPR : 7; /*!< [22..16] FRER Sequence Recovery Pointer Read */ + uint32_t : 9; + } FWFTRR1_b; + }; + + union + { + __IM uint32_t FWFTRR2; /*!< (@ 0x0000603C) FRER Table Read Result Register 2 */ + + struct + { + __IM uint32_t FRSNR : 16; /*!< [15..0] FRER Recovery Sequence Number Read */ + __IM uint32_t FRRTR : 10; /*!< [25..16] FRER Recovery Remaining Ticks Read */ + uint32_t : 6; + } FWFTRR2_b; + }; + __IM uint32_t RESERVED190[48]; + + union + { + __IOM uint32_t FWSEQNGC0; /*!< (@ 0x00006100) Sequence Number Generation Configuration Register + * 0 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC0_b; + }; + + union + { + __IM uint32_t FWSEQNGM0; /*!< (@ 0x00006104) Sequence Number Generation Monitoring Register + * 0 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM0_b; + }; + + union + { + __IOM uint32_t FWSEQNGC1; /*!< (@ 0x00006108) Sequence Number Generation Configuration Register + * 1 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC1_b; + }; + + union + { + __IM uint32_t FWSEQNGM1; /*!< (@ 0x0000610C) Sequence Number Generation Monitoring Register + * 1 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM1_b; + }; + + union + { + __IOM uint32_t FWSEQNGC2; /*!< (@ 0x00006110) Sequence Number Generation Configuration Register + * 2 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC2_b; + }; + + union + { + __IM uint32_t FWSEQNGM2; /*!< (@ 0x00006114) Sequence Number Generation Monitoring Register + * 2 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM2_b; + }; + + union + { + __IOM uint32_t FWSEQNGC3; /*!< (@ 0x00006118) Sequence Number Generation Configuration Register + * 3 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC3_b; + }; + + union + { + __IM uint32_t FWSEQNGM3; /*!< (@ 0x0000611C) Sequence Number Generation Monitoring Register + * 3 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM3_b; + }; + + union + { + __IOM uint32_t FWSEQNGC4; /*!< (@ 0x00006120) Sequence Number Generation Configuration Register + * 4 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC4_b; + }; + + union + { + __IM uint32_t FWSEQNGM4; /*!< (@ 0x00006124) Sequence Number Generation Monitoring Register + * 4 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM4_b; + }; + + union + { + __IOM uint32_t FWSEQNGC5; /*!< (@ 0x00006128) Sequence Number Generation Configuration Register + * 5 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC5_b; + }; + + union + { + __IM uint32_t FWSEQNGM5; /*!< (@ 0x0000612C) Sequence Number Generation Monitoring Register + * 5 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM5_b; + }; + + union + { + __IOM uint32_t FWSEQNGC6; /*!< (@ 0x00006130) Sequence Number Generation Configuration Register + * 6 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC6_b; + }; + + union + { + __IM uint32_t FWSEQNGM6; /*!< (@ 0x00006134) Sequence Number Generation Monitoring Register + * 6 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM6_b; + }; + + union + { + __IOM uint32_t FWSEQNGC7; /*!< (@ 0x00006138) Sequence Number Generation Configuration Register + * 7 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC7_b; + }; + + union + { + __IM uint32_t FWSEQNGM7; /*!< (@ 0x0000613C) Sequence Number Generation Monitoring Register + * 7 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM7_b; + }; + + union + { + __IOM uint32_t FWSEQNGC8; /*!< (@ 0x00006140) Sequence Number Generation Configuration Register + * 8 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC8_b; + }; + + union + { + __IM uint32_t FWSEQNGM8; /*!< (@ 0x00006144) Sequence Number Generation Monitoring Register + * 8 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM8_b; + }; + + union + { + __IOM uint32_t FWSEQNGC9; /*!< (@ 0x00006148) Sequence Number Generation Configuration Register + * 9 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC9_b; + }; + + union + { + __IM uint32_t FWSEQNGM9; /*!< (@ 0x0000614C) Sequence Number Generation Monitoring Register + * 9 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM9_b; + }; + + union + { + __IOM uint32_t FWSEQNGC10; /*!< (@ 0x00006150) Sequence Number Generation Configuration Register + * 10 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC10_b; + }; + + union + { + __IM uint32_t FWSEQNGM10; /*!< (@ 0x00006154) Sequence Number Generation Monitoring Register + * 10 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM10_b; + }; + + union + { + __IOM uint32_t FWSEQNGC11; /*!< (@ 0x00006158) Sequence Number Generation Configuration Register + * 11 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC11_b; + }; + + union + { + __IM uint32_t FWSEQNGM11; /*!< (@ 0x0000615C) Sequence Number Generation Monitoring Register + * 11 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM11_b; + }; + + union + { + __IOM uint32_t FWSEQNGC12; /*!< (@ 0x00006160) Sequence Number Generation Configuration Register + * 12 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC12_b; + }; + + union + { + __IM uint32_t FWSEQNGM12; /*!< (@ 0x00006164) Sequence Number Generation Monitoring Register + * 12 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM12_b; + }; + + union + { + __IOM uint32_t FWSEQNGC13; /*!< (@ 0x00006168) Sequence Number Generation Configuration Register + * 13 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC13_b; + }; + + union + { + __IM uint32_t FWSEQNGM13; /*!< (@ 0x0000616C) Sequence Number Generation Monitoring Register + * 13 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM13_b; + }; + + union + { + __IOM uint32_t FWSEQNGC14; /*!< (@ 0x00006170) Sequence Number Generation Configuration Register + * 14 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC14_b; + }; + + union + { + __IM uint32_t FWSEQNGM14; /*!< (@ 0x00006174) Sequence Number Generation Monitoring Register + * 14 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM14_b; + }; + + union + { + __IOM uint32_t FWSEQNGC15; /*!< (@ 0x00006178) Sequence Number Generation Configuration Register + * 15 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC15_b; + }; + + union + { + __IM uint32_t FWSEQNGM15; /*!< (@ 0x0000617C) Sequence Number Generation Monitoring Register + * 15 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM15_b; + }; + + union + { + __IOM uint32_t FWSEQNGC16; /*!< (@ 0x00006180) Sequence Number Generation Configuration Register + * 16 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC16_b; + }; + + union + { + __IM uint32_t FWSEQNGM16; /*!< (@ 0x00006184) Sequence Number Generation Monitoring Register + * 16 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM16_b; + }; + + union + { + __IOM uint32_t FWSEQNGC17; /*!< (@ 0x00006188) Sequence Number Generation Configuration Register + * 17 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC17_b; + }; + + union + { + __IM uint32_t FWSEQNGM17; /*!< (@ 0x0000618C) Sequence Number Generation Monitoring Register + * 17 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM17_b; + }; + + union + { + __IOM uint32_t FWSEQNGC18; /*!< (@ 0x00006190) Sequence Number Generation Configuration Register + * 18 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC18_b; + }; + + union + { + __IM uint32_t FWSEQNGM18; /*!< (@ 0x00006194) Sequence Number Generation Monitoring Register + * 18 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM18_b; + }; + + union + { + __IOM uint32_t FWSEQNGC19; /*!< (@ 0x00006198) Sequence Number Generation Configuration Register + * 19 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC19_b; + }; + + union + { + __IM uint32_t FWSEQNGM19; /*!< (@ 0x0000619C) Sequence Number Generation Monitoring Register + * 19 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM19_b; + }; + + union + { + __IOM uint32_t FWSEQNGC20; /*!< (@ 0x000061A0) Sequence Number Generation Configuration Register + * 20 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC20_b; + }; + + union + { + __IM uint32_t FWSEQNGM20; /*!< (@ 0x000061A4) Sequence Number Generation Monitoring Register + * 20 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM20_b; + }; + + union + { + __IOM uint32_t FWSEQNGC21; /*!< (@ 0x000061A8) Sequence Number Generation Configuration Register + * 21 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC21_b; + }; + + union + { + __IM uint32_t FWSEQNGM21; /*!< (@ 0x000061AC) Sequence Number Generation Monitoring Register + * 21 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM21_b; + }; + + union + { + __IOM uint32_t FWSEQNGC22; /*!< (@ 0x000061B0) Sequence Number Generation Configuration Register + * 22 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC22_b; + }; + + union + { + __IM uint32_t FWSEQNGM22; /*!< (@ 0x000061B4) Sequence Number Generation Monitoring Register + * 22 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM22_b; + }; + + union + { + __IOM uint32_t FWSEQNGC23; /*!< (@ 0x000061B8) Sequence Number Generation Configuration Register + * 23 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC23_b; + }; + + union + { + __IM uint32_t FWSEQNGM23; /*!< (@ 0x000061BC) Sequence Number Generation Monitoring Register + * 23 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM23_b; + }; + + union + { + __IOM uint32_t FWSEQNGC24; /*!< (@ 0x000061C0) Sequence Number Generation Configuration Register + * 24 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC24_b; + }; + + union + { + __IM uint32_t FWSEQNGM24; /*!< (@ 0x000061C4) Sequence Number Generation Monitoring Register + * 24 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM24_b; + }; + + union + { + __IOM uint32_t FWSEQNGC25; /*!< (@ 0x000061C8) Sequence Number Generation Configuration Register + * 25 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC25_b; + }; + + union + { + __IM uint32_t FWSEQNGM25; /*!< (@ 0x000061CC) Sequence Number Generation Monitoring Register + * 25 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM25_b; + }; + + union + { + __IOM uint32_t FWSEQNGC26; /*!< (@ 0x000061D0) Sequence Number Generation Configuration Register + * 26 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC26_b; + }; + + union + { + __IM uint32_t FWSEQNGM26; /*!< (@ 0x000061D4) Sequence Number Generation Monitoring Register + * 26 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM26_b; + }; + + union + { + __IOM uint32_t FWSEQNGC27; /*!< (@ 0x000061D8) Sequence Number Generation Configuration Register + * 27 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC27_b; + }; + + union + { + __IM uint32_t FWSEQNGM27; /*!< (@ 0x000061DC) Sequence Number Generation Monitoring Register + * 27 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM27_b; + }; + + union + { + __IOM uint32_t FWSEQNGC28; /*!< (@ 0x000061E0) Sequence Number Generation Configuration Register + * 28 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC28_b; + }; + + union + { + __IM uint32_t FWSEQNGM28; /*!< (@ 0x000061E4) Sequence Number Generation Monitoring Register + * 28 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM28_b; + }; + + union + { + __IOM uint32_t FWSEQNGC29; /*!< (@ 0x000061E8) Sequence Number Generation Configuration Register + * 29 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC29_b; + }; + + union + { + __IM uint32_t FWSEQNGM29; /*!< (@ 0x000061EC) Sequence Number Generation Monitoring Register + * 29 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM29_b; + }; + + union + { + __IOM uint32_t FWSEQNGC30; /*!< (@ 0x000061F0) Sequence Number Generation Configuration Register + * 30 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC30_b; + }; + + union + { + __IM uint32_t FWSEQNGM30; /*!< (@ 0x000061F4) Sequence Number Generation Monitoring Register + * 30 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM30_b; + }; + + union + { + __IOM uint32_t FWSEQNGC31; /*!< (@ 0x000061F8) Sequence Number Generation Configuration Register + * 31 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC31_b; + }; + + union + { + __IM uint32_t FWSEQNGM31; /*!< (@ 0x000061FC) Sequence Number Generation Monitoring Register + * 31 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM31_b; + }; + + union + { + __OM uint32_t FWSEQNRC; /*!< (@ 0x00006200) Sequence Number Reset Configuration Register */ + + struct + { + __OM uint32_t SEQNR : 32; /*!< [31..0] Sequence Number Generation Reset */ + } FWSEQNRC_b; + }; + __IM uint32_t RESERVED191[63]; + + union + { + __IM uint32_t FWCTFDCN0; /*!< (@ 0x00006300) Cut-Through Forwarded Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t CTFDN : 32; /*!< [31..0] Cut-Through Forwarded Descriptor Number */ + } FWCTFDCN0_b; + }; + + union + { + __IM uint32_t FWLTHFDCN0; /*!< (@ 0x00006304) Layer 3 Forwarded Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t LTHFDN : 32; /*!< [31..0] Layer 3 Forwarded Descriptor Number */ + } FWLTHFDCN0_b; + }; + __IM uint32_t RESERVED192; + + union + { + __IM uint32_t FWLTWFDCN0; /*!< (@ 0x0000630C) Layer 2 Forwarded Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t LTWFDN : 32; /*!< [31..0] Layer 2 Forwarded Descriptor Number */ + } FWLTWFDCN0_b; + }; + + union + { + __IM uint32_t FWPBFDCN0; /*!< (@ 0x00006310) Port Based Forwarded Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t PBFDN : 32; /*!< [31..0] Port Based Forwarded Descriptor Number */ + } FWPBFDCN0_b; + }; + + union + { + __IM uint32_t FWMHLCN0; /*!< (@ 0x00006314) MAC Hardware Learn Counter Register 0 */ + + struct + { + __IM uint32_t MHLN : 32; /*!< [31..0] MAC Hardware Learn Number */ + } FWMHLCN0_b; + }; + __IM uint32_t RESERVED193[2]; + + union + { + __IM uint32_t FWCTFDCN1; /*!< (@ 0x00006320) Cut-Through Forwarded Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t CTFDN : 32; /*!< [31..0] Cut-Through Forwarded Descriptor Number */ + } FWCTFDCN1_b; + }; + + union + { + __IM uint32_t FWLTHFDCN1; /*!< (@ 0x00006324) Layer 3 Forwarded Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t LTHFDN : 32; /*!< [31..0] Layer 3 Forwarded Descriptor Number */ + } FWLTHFDCN1_b; + }; + __IM uint32_t RESERVED194; + + union + { + __IM uint32_t FWLTWFDCN1; /*!< (@ 0x0000632C) Layer 2 Forwarded Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t LTWFDN : 32; /*!< [31..0] Layer 2 Forwarded Descriptor Number */ + } FWLTWFDCN1_b; + }; + + union + { + __IM uint32_t FWPBFDCN1; /*!< (@ 0x00006330) Port Based Forwarded Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t PBFDN : 32; /*!< [31..0] Port Based Forwarded Descriptor Number */ + } FWPBFDCN1_b; + }; + + union + { + __IM uint32_t FWMHLCN1; /*!< (@ 0x00006334) MAC Hardware Learn Counter Register 1 */ + + struct + { + __IM uint32_t MHLN : 32; /*!< [31..0] MAC Hardware Learn Number */ + } FWMHLCN1_b; + }; + __IM uint32_t RESERVED195[2]; + + union + { + __IM uint32_t FWDDFDCN0; /*!< (@ 0x00006340) Direct Descriptor Forwarded Descriptor Counter + * Register 0 */ + + struct + { + __IM uint32_t DDFDN : 32; /*!< [31..0] Direct Descriptor Forwarded Descriptor Number */ + } FWDDFDCN0_b; + }; + + union + { + __IM uint32_t FWLTHFDCN2; /*!< (@ 0x00006344) Layer 3 Forwarded Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t LTHFDN : 32; /*!< [31..0] Layer 3 Forwarded Descriptor Number */ + } FWLTHFDCN2_b; + }; + __IM uint32_t RESERVED196; + + union + { + __IM uint32_t FWLTWFDCN2; /*!< (@ 0x0000634C) Layer 2 Forwarded Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t LTWFDN : 32; /*!< [31..0] Layer 2 Forwarded Descriptor Number */ + } FWLTWFDCN2_b; + }; + + union + { + __IM uint32_t FWPBFDCN2; /*!< (@ 0x00006350) Port Based Forwarded Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t PBFDN : 32; /*!< [31..0] Port Based Forwarded Descriptor Number */ + } FWPBFDCN2_b; + }; + + union + { + __IM uint32_t FWMHLCN2; /*!< (@ 0x00006354) MAC Hardware Learn Counter Register 2 */ + + struct + { + __IM uint32_t MHLN : 32; /*!< [31..0] MAC Hardware Learn Number */ + } FWMHLCN2_b; + }; + __IM uint32_t RESERVED197[107]; + + union + { + __IM uint32_t FWWMRDCN0; /*!< (@ 0x00006504) Watermark Rejected Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t WMRDN : 16; /*!< [15..0] Watermark rejected Descriptor Number */ + uint32_t : 16; + } FWWMRDCN0_b; + }; + + union + { + __IM uint32_t FWCTRDCN0; /*!< (@ 0x00006508) Cut-Through Rejected Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t CTRDN : 16; /*!< [15..0] Cut-through rejected Descriptor Number */ + uint32_t : 16; + } FWCTRDCN0_b; + }; + + union + { + __IM uint32_t FWLTHRDCN0; /*!< (@ 0x0000650C) Layer 3 Rejected Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t LTHRDN : 16; /*!< [15..0] Layer 3 rejected Descriptor Number */ + uint32_t : 16; + } FWLTHRDCN0_b; + }; + __IM uint32_t RESERVED198; + + union + { + __IM uint32_t FWLTWRDCN0; /*!< (@ 0x00006514) Layer 2 Rejected Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t LTWRDN : 16; /*!< [15..0] Layer 2 rejected Descriptor Number */ + uint32_t : 16; + } FWLTWRDCN0_b; + }; + + union + { + __IM uint32_t FWPBRDCN0; /*!< (@ 0x00006518) Port Based Rejected Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t PBRDN : 16; /*!< [15..0] Port Based rejected Descriptor Number */ + uint32_t : 16; + } FWPBRDCN0_b; + }; + __IM uint32_t RESERVED199[2]; + + union + { + __IM uint32_t FWWMRDCN1; /*!< (@ 0x00006524) Watermark Rejected Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t WMRDN : 16; /*!< [15..0] Watermark rejected Descriptor Number */ + uint32_t : 16; + } FWWMRDCN1_b; + }; + + union + { + __IM uint32_t FWCTRDCN1; /*!< (@ 0x00006528) Cut-Through Rejected Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t CTRDN : 16; /*!< [15..0] Cut-through rejected Descriptor Number */ + uint32_t : 16; + } FWCTRDCN1_b; + }; + + union + { + __IM uint32_t FWLTHRDCN1; /*!< (@ 0x0000652C) Layer 3 Rejected Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t LTHRDN : 16; /*!< [15..0] Layer 3 rejected Descriptor Number */ + uint32_t : 16; + } FWLTHRDCN1_b; + }; + __IM uint32_t RESERVED200; + + union + { + __IM uint32_t FWLTWRDCN1; /*!< (@ 0x00006534) Layer 2 Rejected Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t LTWRDN : 16; /*!< [15..0] Layer 2 rejected Descriptor Number */ + uint32_t : 16; + } FWLTWRDCN1_b; + }; + + union + { + __IM uint32_t FWPBRDCN1; /*!< (@ 0x00006538) Port Based Rejected Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t PBRDN : 16; /*!< [15..0] Port Based rejected Descriptor Number */ + uint32_t : 16; + } FWPBRDCN1_b; + }; + __IM uint32_t RESERVED201[2]; + + union + { + __IM uint32_t FWWMRDCN2; /*!< (@ 0x00006544) Watermark Rejected Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t WMRDN : 16; /*!< [15..0] Watermark rejected Descriptor Number */ + uint32_t : 16; + } FWWMRDCN2_b; + }; + + union + { + __IM uint32_t FWDDRDCN0; /*!< (@ 0x00006548) Direct Descriptor Rejected Descriptor Counter + * Register 0 */ + + struct + { + __IM uint32_t DDRDN : 16; /*!< [15..0] Direct Descriptor rejected Descriptor Number */ + uint32_t : 16; + } FWDDRDCN0_b; + }; + + union + { + __IM uint32_t FWLTHRDCN2; /*!< (@ 0x0000654C) Layer 3 Rejected Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t LTHRDN : 16; /*!< [15..0] Layer 3 rejected Descriptor Number */ + uint32_t : 16; + } FWLTHRDCN2_b; + }; + __IM uint32_t RESERVED202; + + union + { + __IM uint32_t FWLTWRDCN2; /*!< (@ 0x00006554) Layer 2 Rejected Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t LTWRDN : 16; /*!< [15..0] Layer 2 rejected Descriptor Number */ + uint32_t : 16; + } FWLTWRDCN2_b; + }; + + union + { + __IM uint32_t FWPBRDCN2; /*!< (@ 0x00006558) Port Based Rejected Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t PBRDN : 16; /*!< [15..0] Port Based rejected Descriptor Number */ + uint32_t : 16; + } FWPBRDCN2_b; + }; + __IM uint32_t RESERVED203[105]; + + union + { + __IM uint32_t FWPMFDCN0; /*!< (@ 0x00006700) PSFP MSDU Filtered Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN0_b; + }; + + union + { + __IM uint32_t FWPMFDCN1; /*!< (@ 0x00006704) PSFP MSDU Filtered Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN1_b; + }; + + union + { + __IM uint32_t FWPMFDCN2; /*!< (@ 0x00006708) PSFP MSDU Filtered Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN2_b; + }; + + union + { + __IM uint32_t FWPMFDCN3; /*!< (@ 0x0000670C) PSFP MSDU Filtered Descriptor Counter Register + * 3 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN3_b; + }; + + union + { + __IM uint32_t FWPMFDCN4; /*!< (@ 0x00006710) PSFP MSDU Filtered Descriptor Counter Register + * 4 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN4_b; + }; + + union + { + __IM uint32_t FWPMFDCN5; /*!< (@ 0x00006714) PSFP MSDU Filtered Descriptor Counter Register + * 5 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN5_b; + }; + + union + { + __IM uint32_t FWPMFDCN6; /*!< (@ 0x00006718) PSFP MSDU Filtered Descriptor Counter Register + * 6 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN6_b; + }; + + union + { + __IM uint32_t FWPMFDCN7; /*!< (@ 0x0000671C) PSFP MSDU Filtered Descriptor Counter Register + * 7 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN7_b; + }; + + union + { + __IM uint32_t FWPMFDCN8; /*!< (@ 0x00006720) PSFP MSDU Filtered Descriptor Counter Register + * 8 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN8_b; + }; + + union + { + __IM uint32_t FWPMFDCN9; /*!< (@ 0x00006724) PSFP MSDU Filtered Descriptor Counter Register + * 9 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN9_b; + }; + + union + { + __IM uint32_t FWPMFDCN10; /*!< (@ 0x00006728) PSFP MSDU Filtered Descriptor Counter Register + * 10 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN10_b; + }; + + union + { + __IM uint32_t FWPMFDCN11; /*!< (@ 0x0000672C) PSFP MSDU Filtered Descriptor Counter Register + * 11 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN11_b; + }; + + union + { + __IM uint32_t FWPMFDCN12; /*!< (@ 0x00006730) PSFP MSDU Filtered Descriptor Counter Register + * 12 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN12_b; + }; + + union + { + __IM uint32_t FWPMFDCN13; /*!< (@ 0x00006734) PSFP MSDU Filtered Descriptor Counter Register + * 13 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN13_b; + }; + + union + { + __IM uint32_t FWPMFDCN14; /*!< (@ 0x00006738) PSFP MSDU Filtered Descriptor Counter Register + * 14 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN14_b; + }; + + union + { + __IM uint32_t FWPMFDCN15; /*!< (@ 0x0000673C) PSFP MSDU Filtered Descriptor Counter Register + * 15 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN15_b; + }; + __IM uint32_t RESERVED204[48]; + + union + { + __IM uint32_t FWPMGDCN0; /*!< (@ 0x00006800) PSFP Meter Green Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN0_b; + }; + + union + { + __IM uint32_t FWPMYDCN0; /*!< (@ 0x00006804) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN0_b; + }; + + union + { + __IM uint32_t FWPMRDCN0; /*!< (@ 0x00006808) PSFP Meter Red Descriptor Counter Register 0 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN0_b; + }; + __IM uint32_t RESERVED205; + + union + { + __IM uint32_t FWPMGDCN1; /*!< (@ 0x00006810) PSFP Meter Green Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN1_b; + }; + + union + { + __IM uint32_t FWPMYDCN1; /*!< (@ 0x00006814) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN1_b; + }; + + union + { + __IM uint32_t FWPMRDCN1; /*!< (@ 0x00006818) PSFP Meter Red Descriptor Counter Register 1 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN1_b; + }; + __IM uint32_t RESERVED206; + + union + { + __IM uint32_t FWPMGDCN2; /*!< (@ 0x00006820) PSFP Meter Green Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN2_b; + }; + + union + { + __IM uint32_t FWPMYDCN2; /*!< (@ 0x00006824) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN2_b; + }; + + union + { + __IM uint32_t FWPMRDCN2; /*!< (@ 0x00006828) PSFP Meter Red Descriptor Counter Register 2 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN2_b; + }; + __IM uint32_t RESERVED207; + + union + { + __IM uint32_t FWPMGDCN3; /*!< (@ 0x00006830) PSFP Meter Green Descriptor Counter Register + * 3 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN3_b; + }; + + union + { + __IM uint32_t FWPMYDCN3; /*!< (@ 0x00006834) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN3_b; + }; + + union + { + __IM uint32_t FWPMRDCN3; /*!< (@ 0x00006838) PSFP Meter Red Descriptor Counter Register 3 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN3_b; + }; + __IM uint32_t RESERVED208; + + union + { + __IM uint32_t FWPMGDCN4; /*!< (@ 0x00006840) PSFP Meter Green Descriptor Counter Register + * 4 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN4_b; + }; + + union + { + __IM uint32_t FWPMYDCN4; /*!< (@ 0x00006844) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN4_b; + }; + + union + { + __IM uint32_t FWPMRDCN4; /*!< (@ 0x00006848) PSFP Meter Red Descriptor Counter Register 4 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN4_b; + }; + __IM uint32_t RESERVED209; + + union + { + __IM uint32_t FWPMGDCN5; /*!< (@ 0x00006850) PSFP Meter Green Descriptor Counter Register + * 5 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN5_b; + }; + + union + { + __IM uint32_t FWPMYDCN5; /*!< (@ 0x00006854) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN5_b; + }; + + union + { + __IM uint32_t FWPMRDCN5; /*!< (@ 0x00006858) PSFP Meter Red Descriptor Counter Register 5 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN5_b; + }; + __IM uint32_t RESERVED210; + + union + { + __IM uint32_t FWPMGDCN6; /*!< (@ 0x00006860) PSFP Meter Green Descriptor Counter Register + * 6 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN6_b; + }; + + union + { + __IM uint32_t FWPMYDCN6; /*!< (@ 0x00006864) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN6_b; + }; + + union + { + __IM uint32_t FWPMRDCN6; /*!< (@ 0x00006868) PSFP Meter Red Descriptor Counter Register 6 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN6_b; + }; + __IM uint32_t RESERVED211; + + union + { + __IM uint32_t FWPMGDCN7; /*!< (@ 0x00006870) PSFP Meter Green Descriptor Counter Register + * 7 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN7_b; + }; + + union + { + __IM uint32_t FWPMYDCN7; /*!< (@ 0x00006874) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN7_b; + }; + + union + { + __IM uint32_t FWPMRDCN7; /*!< (@ 0x00006878) PSFP Meter Red Descriptor Counter Register 7 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN7_b; + }; + __IM uint32_t RESERVED212; + + union + { + __IM uint32_t FWPMGDCN8; /*!< (@ 0x00006880) PSFP Meter Green Descriptor Counter Register + * 8 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN8_b; + }; + __IM uint32_t RESERVED213; + + union + { + __IM uint32_t FWPMRDCN8; /*!< (@ 0x00006888) PSFP Meter Red Descriptor Counter Register 8 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN8_b; + }; + __IM uint32_t RESERVED214; + + union + { + __IM uint32_t FWPMGDCN9; /*!< (@ 0x00006890) PSFP Meter Green Descriptor Counter Register + * 9 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN9_b; + }; + __IM uint32_t RESERVED215; + + union + { + __IM uint32_t FWPMRDCN9; /*!< (@ 0x00006898) PSFP Meter Red Descriptor Counter Register 9 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN9_b; + }; + __IM uint32_t RESERVED216; + + union + { + __IM uint32_t FWPMGDCN10; /*!< (@ 0x000068A0) PSFP Meter Green Descriptor Counter Register + * 10 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN10_b; + }; + __IM uint32_t RESERVED217; + + union + { + __IM uint32_t FWPMRDCN10; /*!< (@ 0x000068A8) PSFP Meter Red Descriptor Counter Register 10 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN10_b; + }; + __IM uint32_t RESERVED218; + + union + { + __IM uint32_t FWPMGDCN11; /*!< (@ 0x000068B0) PSFP Meter Green Descriptor Counter Register + * 11 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN11_b; + }; + __IM uint32_t RESERVED219; + + union + { + __IM uint32_t FWPMRDCN11; /*!< (@ 0x000068B8) PSFP Meter Red Descriptor Counter Register 11 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN11_b; + }; + __IM uint32_t RESERVED220; + + union + { + __IM uint32_t FWPMGDCN12; /*!< (@ 0x000068C0) PSFP Meter Green Descriptor Counter Register + * 12 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN12_b; + }; + __IM uint32_t RESERVED221; + + union + { + __IM uint32_t FWPMRDCN12; /*!< (@ 0x000068C8) PSFP Meter Red Descriptor Counter Register 12 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN12_b; + }; + __IM uint32_t RESERVED222; + + union + { + __IM uint32_t FWPMGDCN13; /*!< (@ 0x000068D0) PSFP Meter Green Descriptor Counter Register + * 13 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN13_b; + }; + __IM uint32_t RESERVED223; + + union + { + __IM uint32_t FWPMRDCN13; /*!< (@ 0x000068D8) PSFP Meter Red Descriptor Counter Register 13 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN13_b; + }; + __IM uint32_t RESERVED224; + + union + { + __IM uint32_t FWPMGDCN14; /*!< (@ 0x000068E0) PSFP Meter Green Descriptor Counter Register + * 14 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN14_b; + }; + __IM uint32_t RESERVED225; + + union + { + __IM uint32_t FWPMRDCN14; /*!< (@ 0x000068E8) PSFP Meter Red Descriptor Counter Register 14 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN14_b; + }; + __IM uint32_t RESERVED226; + + union + { + __IM uint32_t FWPMGDCN15; /*!< (@ 0x000068F0) PSFP Meter Green Descriptor Counter Register + * 15 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN15_b; + }; + __IM uint32_t RESERVED227; + + union + { + __IM uint32_t FWPMRDCN15; /*!< (@ 0x000068F8) PSFP Meter Red Descriptor Counter Register 15 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN15_b; + }; + __IM uint32_t RESERVED228; + + union + { + __IM uint32_t FWPMGDCN16; /*!< (@ 0x00006900) PSFP Meter Green Descriptor Counter Register + * 16 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN16_b; + }; + __IM uint32_t RESERVED229; + + union + { + __IM uint32_t FWPMRDCN16; /*!< (@ 0x00006908) PSFP Meter Red Descriptor Counter Register 16 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN16_b; + }; + __IM uint32_t RESERVED230; + + union + { + __IM uint32_t FWPMGDCN17; /*!< (@ 0x00006910) PSFP Meter Green Descriptor Counter Register + * 17 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN17_b; + }; + __IM uint32_t RESERVED231; + + union + { + __IM uint32_t FWPMRDCN17; /*!< (@ 0x00006918) PSFP Meter Red Descriptor Counter Register 17 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN17_b; + }; + __IM uint32_t RESERVED232; + + union + { + __IM uint32_t FWPMGDCN18; /*!< (@ 0x00006920) PSFP Meter Green Descriptor Counter Register + * 18 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN18_b; + }; + __IM uint32_t RESERVED233; + + union + { + __IM uint32_t FWPMRDCN18; /*!< (@ 0x00006928) PSFP Meter Red Descriptor Counter Register 18 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN18_b; + }; + __IM uint32_t RESERVED234; + + union + { + __IM uint32_t FWPMGDCN19; /*!< (@ 0x00006930) PSFP Meter Green Descriptor Counter Register + * 19 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN19_b; + }; + __IM uint32_t RESERVED235; + + union + { + __IM uint32_t FWPMRDCN19; /*!< (@ 0x00006938) PSFP Meter Red Descriptor Counter Register 19 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN19_b; + }; + __IM uint32_t RESERVED236; + + union + { + __IM uint32_t FWPMGDCN20; /*!< (@ 0x00006940) PSFP Meter Green Descriptor Counter Register + * 20 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN20_b; + }; + __IM uint32_t RESERVED237; + + union + { + __IM uint32_t FWPMRDCN20; /*!< (@ 0x00006948) PSFP Meter Red Descriptor Counter Register 20 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN20_b; + }; + __IM uint32_t RESERVED238; + + union + { + __IM uint32_t FWPMGDCN21; /*!< (@ 0x00006950) PSFP Meter Green Descriptor Counter Register + * 21 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN21_b; + }; + __IM uint32_t RESERVED239; + + union + { + __IM uint32_t FWPMRDCN21; /*!< (@ 0x00006958) PSFP Meter Red Descriptor Counter Register 21 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN21_b; + }; + __IM uint32_t RESERVED240; + + union + { + __IM uint32_t FWPMGDCN22; /*!< (@ 0x00006960) PSFP Meter Green Descriptor Counter Register + * 22 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN22_b; + }; + __IM uint32_t RESERVED241; + + union + { + __IM uint32_t FWPMRDCN22; /*!< (@ 0x00006968) PSFP Meter Red Descriptor Counter Register 22 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN22_b; + }; + __IM uint32_t RESERVED242; + + union + { + __IM uint32_t FWPMGDCN23; /*!< (@ 0x00006970) PSFP Meter Green Descriptor Counter Register + * 23 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN23_b; + }; + __IM uint32_t RESERVED243; + + union + { + __IM uint32_t FWPMRDCN23; /*!< (@ 0x00006978) PSFP Meter Red Descriptor Counter Register 23 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN23_b; + }; + __IM uint32_t RESERVED244; + + union + { + __IM uint32_t FWPMGDCN24; /*!< (@ 0x00006980) PSFP Meter Green Descriptor Counter Register + * 24 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN24_b; + }; + __IM uint32_t RESERVED245; + + union + { + __IM uint32_t FWPMRDCN24; /*!< (@ 0x00006988) PSFP Meter Red Descriptor Counter Register 24 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN24_b; + }; + __IM uint32_t RESERVED246; + + union + { + __IM uint32_t FWPMGDCN25; /*!< (@ 0x00006990) PSFP Meter Green Descriptor Counter Register + * 25 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN25_b; + }; + __IM uint32_t RESERVED247; + + union + { + __IM uint32_t FWPMRDCN25; /*!< (@ 0x00006998) PSFP Meter Red Descriptor Counter Register 25 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN25_b; + }; + __IM uint32_t RESERVED248; + + union + { + __IM uint32_t FWPMGDCN26; /*!< (@ 0x000069A0) PSFP Meter Green Descriptor Counter Register + * 26 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN26_b; + }; + __IM uint32_t RESERVED249; + + union + { + __IM uint32_t FWPMRDCN26; /*!< (@ 0x000069A8) PSFP Meter Red Descriptor Counter Register 26 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN26_b; + }; + __IM uint32_t RESERVED250; + + union + { + __IM uint32_t FWPMGDCN27; /*!< (@ 0x000069B0) PSFP Meter Green Descriptor Counter Register + * 27 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN27_b; + }; + __IM uint32_t RESERVED251; + + union + { + __IM uint32_t FWPMRDCN27; /*!< (@ 0x000069B8) PSFP Meter Red Descriptor Counter Register 27 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN27_b; + }; + __IM uint32_t RESERVED252; + + union + { + __IM uint32_t FWPMGDCN28; /*!< (@ 0x000069C0) PSFP Meter Green Descriptor Counter Register + * 28 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN28_b; + }; + __IM uint32_t RESERVED253; + + union + { + __IM uint32_t FWPMRDCN28; /*!< (@ 0x000069C8) PSFP Meter Red Descriptor Counter Register 28 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN28_b; + }; + __IM uint32_t RESERVED254; + + union + { + __IM uint32_t FWPMGDCN29; /*!< (@ 0x000069D0) PSFP Meter Green Descriptor Counter Register + * 29 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN29_b; + }; + __IM uint32_t RESERVED255; + + union + { + __IM uint32_t FWPMRDCN29; /*!< (@ 0x000069D8) PSFP Meter Red Descriptor Counter Register 29 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN29_b; + }; + __IM uint32_t RESERVED256; + + union + { + __IM uint32_t FWPMGDCN30; /*!< (@ 0x000069E0) PSFP Meter Green Descriptor Counter Register + * 30 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN30_b; + }; + __IM uint32_t RESERVED257; + + union + { + __IM uint32_t FWPMRDCN30; /*!< (@ 0x000069E8) PSFP Meter Red Descriptor Counter Register 30 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN30_b; + }; + __IM uint32_t RESERVED258; + + union + { + __IM uint32_t FWPMGDCN31; /*!< (@ 0x000069F0) PSFP Meter Green Descriptor Counter Register + * 31 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN31_b; + }; + __IM uint32_t RESERVED259; + + union + { + __IM uint32_t FWPMRDCN31; /*!< (@ 0x000069F8) PSFP Meter Red Descriptor Counter Register 31 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN31_b; + }; + __IM uint32_t RESERVED260; + + union + { + __IM uint32_t FWFRPPCN0; /*!< (@ 0x00006A00) FRER Passed Packet Counter Register 0 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN0_b; + }; + + union + { + __IM uint32_t FWFRDPCN0; /*!< (@ 0x00006A04) FRER Discarded Packet Counter Register 0 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN0_b; + }; + + union + { + __IM uint32_t FWFRPPCN1; /*!< (@ 0x00006A08) FRER Passed Packet Counter Register 1 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN1_b; + }; + + union + { + __IM uint32_t FWFRDPCN1; /*!< (@ 0x00006A0C) FRER Discarded Packet Counter Register 1 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN1_b; + }; + + union + { + __IM uint32_t FWFRPPCN2; /*!< (@ 0x00006A10) FRER Passed Packet Counter Register 2 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN2_b; + }; + + union + { + __IM uint32_t FWFRDPCN2; /*!< (@ 0x00006A14) FRER Discarded Packet Counter Register 2 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN2_b; + }; + + union + { + __IM uint32_t FWFRPPCN3; /*!< (@ 0x00006A18) FRER Passed Packet Counter Register 3 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN3_b; + }; + + union + { + __IM uint32_t FWFRDPCN3; /*!< (@ 0x00006A1C) FRER Discarded Packet Counter Register 3 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN3_b; + }; + + union + { + __IM uint32_t FWFRPPCN4; /*!< (@ 0x00006A20) FRER Passed Packet Counter Register 4 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN4_b; + }; + + union + { + __IM uint32_t FWFRDPCN4; /*!< (@ 0x00006A24) FRER Discarded Packet Counter Register 4 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN4_b; + }; + + union + { + __IM uint32_t FWFRPPCN5; /*!< (@ 0x00006A28) FRER Passed Packet Counter Register 5 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN5_b; + }; + + union + { + __IM uint32_t FWFRDPCN5; /*!< (@ 0x00006A2C) FRER Discarded Packet Counter Register 5 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN5_b; + }; + + union + { + __IM uint32_t FWFRPPCN6; /*!< (@ 0x00006A30) FRER Passed Packet Counter Register 6 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN6_b; + }; + + union + { + __IM uint32_t FWFRDPCN6; /*!< (@ 0x00006A34) FRER Discarded Packet Counter Register 6 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN6_b; + }; + + union + { + __IM uint32_t FWFRPPCN7; /*!< (@ 0x00006A38) FRER Passed Packet Counter Register 7 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN7_b; + }; + + union + { + __IM uint32_t FWFRDPCN7; /*!< (@ 0x00006A3C) FRER Discarded Packet Counter Register 7 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN7_b; + }; + + union + { + __IM uint32_t FWFRPPCN8; /*!< (@ 0x00006A40) FRER Passed Packet Counter Register 8 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN8_b; + }; + + union + { + __IM uint32_t FWFRDPCN8; /*!< (@ 0x00006A44) FRER Discarded Packet Counter Register 8 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN8_b; + }; + + union + { + __IM uint32_t FWFRPPCN9; /*!< (@ 0x00006A48) FRER Passed Packet Counter Register 9 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN9_b; + }; + + union + { + __IM uint32_t FWFRDPCN9; /*!< (@ 0x00006A4C) FRER Discarded Packet Counter Register 9 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN9_b; + }; + + union + { + __IM uint32_t FWFRPPCN10; /*!< (@ 0x00006A50) FRER Passed Packet Counter Register 10 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN10_b; + }; + + union + { + __IM uint32_t FWFRDPCN10; /*!< (@ 0x00006A54) FRER Discarded Packet Counter Register 10 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN10_b; + }; + + union + { + __IM uint32_t FWFRPPCN11; /*!< (@ 0x00006A58) FRER Passed Packet Counter Register 11 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN11_b; + }; + + union + { + __IM uint32_t FWFRDPCN11; /*!< (@ 0x00006A5C) FRER Discarded Packet Counter Register 11 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN11_b; + }; + + union + { + __IM uint32_t FWFRPPCN12; /*!< (@ 0x00006A60) FRER Passed Packet Counter Register 12 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN12_b; + }; + + union + { + __IM uint32_t FWFRDPCN12; /*!< (@ 0x00006A64) FRER Discarded Packet Counter Register 12 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN12_b; + }; + + union + { + __IM uint32_t FWFRPPCN13; /*!< (@ 0x00006A68) FRER Passed Packet Counter Register 13 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN13_b; + }; + + union + { + __IM uint32_t FWFRDPCN13; /*!< (@ 0x00006A6C) FRER Discarded Packet Counter Register 13 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN13_b; + }; + + union + { + __IM uint32_t FWFRPPCN14; /*!< (@ 0x00006A70) FRER Passed Packet Counter Register 14 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN14_b; + }; + + union + { + __IM uint32_t FWFRDPCN14; /*!< (@ 0x00006A74) FRER Discarded Packet Counter Register 14 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN14_b; + }; + + union + { + __IM uint32_t FWFRPPCN15; /*!< (@ 0x00006A78) FRER Passed Packet Counter Register 15 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN15_b; + }; + + union + { + __IM uint32_t FWFRDPCN15; /*!< (@ 0x00006A7C) FRER Discarded Packet Counter Register 15 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN15_b; + }; + + union + { + __IM uint32_t FWFRPPCN16; /*!< (@ 0x00006A80) FRER Passed Packet Counter Register 16 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN16_b; + }; + + union + { + __IM uint32_t FWFRDPCN16; /*!< (@ 0x00006A84) FRER Discarded Packet Counter Register 16 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN16_b; + }; + + union + { + __IM uint32_t FWFRPPCN17; /*!< (@ 0x00006A88) FRER Passed Packet Counter Register 17 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN17_b; + }; + + union + { + __IM uint32_t FWFRDPCN17; /*!< (@ 0x00006A8C) FRER Discarded Packet Counter Register 17 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN17_b; + }; + + union + { + __IM uint32_t FWFRPPCN18; /*!< (@ 0x00006A90) FRER Passed Packet Counter Register 18 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN18_b; + }; + + union + { + __IM uint32_t FWFRDPCN18; /*!< (@ 0x00006A94) FRER Discarded Packet Counter Register 18 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN18_b; + }; + + union + { + __IM uint32_t FWFRPPCN19; /*!< (@ 0x00006A98) FRER Passed Packet Counter Register 19 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN19_b; + }; + + union + { + __IM uint32_t FWFRDPCN19; /*!< (@ 0x00006A9C) FRER Discarded Packet Counter Register 19 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN19_b; + }; + + union + { + __IM uint32_t FWFRPPCN20; /*!< (@ 0x00006AA0) FRER Passed Packet Counter Register 20 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN20_b; + }; + + union + { + __IM uint32_t FWFRDPCN20; /*!< (@ 0x00006AA4) FRER Discarded Packet Counter Register 20 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN20_b; + }; + + union + { + __IM uint32_t FWFRPPCN21; /*!< (@ 0x00006AA8) FRER Passed Packet Counter Register 21 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN21_b; + }; + + union + { + __IM uint32_t FWFRDPCN21; /*!< (@ 0x00006AAC) FRER Discarded Packet Counter Register 21 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN21_b; + }; + + union + { + __IM uint32_t FWFRPPCN22; /*!< (@ 0x00006AB0) FRER Passed Packet Counter Register 22 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN22_b; + }; + + union + { + __IM uint32_t FWFRDPCN22; /*!< (@ 0x00006AB4) FRER Discarded Packet Counter Register 22 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN22_b; + }; + + union + { + __IM uint32_t FWFRPPCN23; /*!< (@ 0x00006AB8) FRER Passed Packet Counter Register 23 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN23_b; + }; + + union + { + __IM uint32_t FWFRDPCN23; /*!< (@ 0x00006ABC) FRER Discarded Packet Counter Register 23 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN23_b; + }; + + union + { + __IM uint32_t FWFRPPCN24; /*!< (@ 0x00006AC0) FRER Passed Packet Counter Register 24 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN24_b; + }; + + union + { + __IM uint32_t FWFRDPCN24; /*!< (@ 0x00006AC4) FRER Discarded Packet Counter Register 24 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN24_b; + }; + + union + { + __IM uint32_t FWFRPPCN25; /*!< (@ 0x00006AC8) FRER Passed Packet Counter Register 25 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN25_b; + }; + + union + { + __IM uint32_t FWFRDPCN25; /*!< (@ 0x00006ACC) FRER Discarded Packet Counter Register 25 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN25_b; + }; + + union + { + __IM uint32_t FWFRPPCN26; /*!< (@ 0x00006AD0) FRER Passed Packet Counter Register 26 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN26_b; + }; + + union + { + __IM uint32_t FWFRDPCN26; /*!< (@ 0x00006AD4) FRER Discarded Packet Counter Register 26 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN26_b; + }; + + union + { + __IM uint32_t FWFRPPCN27; /*!< (@ 0x00006AD8) FRER Passed Packet Counter Register 27 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN27_b; + }; + + union + { + __IM uint32_t FWFRDPCN27; /*!< (@ 0x00006ADC) FRER Discarded Packet Counter Register 27 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN27_b; + }; + + union + { + __IM uint32_t FWFRPPCN28; /*!< (@ 0x00006AE0) FRER Passed Packet Counter Register 28 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN28_b; + }; + + union + { + __IM uint32_t FWFRDPCN28; /*!< (@ 0x00006AE4) FRER Discarded Packet Counter Register 28 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN28_b; + }; + + union + { + __IM uint32_t FWFRPPCN29; /*!< (@ 0x00006AE8) FRER Passed Packet Counter Register 29 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN29_b; + }; + + union + { + __IM uint32_t FWFRDPCN29; /*!< (@ 0x00006AEC) FRER Discarded Packet Counter Register 29 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN29_b; + }; + + union + { + __IM uint32_t FWFRPPCN30; /*!< (@ 0x00006AF0) FRER Passed Packet Counter Register 30 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN30_b; + }; + + union + { + __IM uint32_t FWFRDPCN30; /*!< (@ 0x00006AF4) FRER Discarded Packet Counter Register 30 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN30_b; + }; + + union + { + __IM uint32_t FWFRPPCN31; /*!< (@ 0x00006AF8) FRER Passed Packet Counter Register 31 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN31_b; + }; + + union + { + __IM uint32_t FWFRDPCN31; /*!< (@ 0x00006AFC) FRER Discarded Packet Counter Register 31 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN31_b; + }; + + union + { + __IM uint32_t FWFRPPCN32; /*!< (@ 0x00006B00) FRER Passed Packet Counter Register 32 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN32_b; + }; + + union + { + __IM uint32_t FWFRDPCN32; /*!< (@ 0x00006B04) FRER Discarded Packet Counter Register 32 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN32_b; + }; + + union + { + __IM uint32_t FWFRPPCN33; /*!< (@ 0x00006B08) FRER Passed Packet Counter Register 33 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN33_b; + }; + + union + { + __IM uint32_t FWFRDPCN33; /*!< (@ 0x00006B0C) FRER Discarded Packet Counter Register 33 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN33_b; + }; + + union + { + __IM uint32_t FWFRPPCN34; /*!< (@ 0x00006B10) FRER Passed Packet Counter Register 34 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN34_b; + }; + + union + { + __IM uint32_t FWFRDPCN34; /*!< (@ 0x00006B14) FRER Discarded Packet Counter Register 34 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN34_b; + }; + + union + { + __IM uint32_t FWFRPPCN35; /*!< (@ 0x00006B18) FRER Passed Packet Counter Register 35 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN35_b; + }; + + union + { + __IM uint32_t FWFRDPCN35; /*!< (@ 0x00006B1C) FRER Discarded Packet Counter Register 35 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN35_b; + }; + + union + { + __IM uint32_t FWFRPPCN36; /*!< (@ 0x00006B20) FRER Passed Packet Counter Register 36 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN36_b; + }; + + union + { + __IM uint32_t FWFRDPCN36; /*!< (@ 0x00006B24) FRER Discarded Packet Counter Register 36 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN36_b; + }; + + union + { + __IM uint32_t FWFRPPCN37; /*!< (@ 0x00006B28) FRER Passed Packet Counter Register 37 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN37_b; + }; + + union + { + __IM uint32_t FWFRDPCN37; /*!< (@ 0x00006B2C) FRER Discarded Packet Counter Register 37 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN37_b; + }; + + union + { + __IM uint32_t FWFRPPCN38; /*!< (@ 0x00006B30) FRER Passed Packet Counter Register 38 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN38_b; + }; + + union + { + __IM uint32_t FWFRDPCN38; /*!< (@ 0x00006B34) FRER Discarded Packet Counter Register 38 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN38_b; + }; + + union + { + __IM uint32_t FWFRPPCN39; /*!< (@ 0x00006B38) FRER Passed Packet Counter Register 39 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN39_b; + }; + + union + { + __IM uint32_t FWFRDPCN39; /*!< (@ 0x00006B3C) FRER Discarded Packet Counter Register 39 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN39_b; + }; + + union + { + __IM uint32_t FWFRPPCN40; /*!< (@ 0x00006B40) FRER Passed Packet Counter Register 40 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN40_b; + }; + + union + { + __IM uint32_t FWFRDPCN40; /*!< (@ 0x00006B44) FRER Discarded Packet Counter Register 40 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN40_b; + }; + + union + { + __IM uint32_t FWFRPPCN41; /*!< (@ 0x00006B48) FRER Passed Packet Counter Register 41 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN41_b; + }; + + union + { + __IM uint32_t FWFRDPCN41; /*!< (@ 0x00006B4C) FRER Discarded Packet Counter Register 41 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN41_b; + }; + + union + { + __IM uint32_t FWFRPPCN42; /*!< (@ 0x00006B50) FRER Passed Packet Counter Register 42 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN42_b; + }; + + union + { + __IM uint32_t FWFRDPCN42; /*!< (@ 0x00006B54) FRER Discarded Packet Counter Register 42 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN42_b; + }; + + union + { + __IM uint32_t FWFRPPCN43; /*!< (@ 0x00006B58) FRER Passed Packet Counter Register 43 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN43_b; + }; + + union + { + __IM uint32_t FWFRDPCN43; /*!< (@ 0x00006B5C) FRER Discarded Packet Counter Register 43 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN43_b; + }; + + union + { + __IM uint32_t FWFRPPCN44; /*!< (@ 0x00006B60) FRER Passed Packet Counter Register 44 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN44_b; + }; + + union + { + __IM uint32_t FWFRDPCN44; /*!< (@ 0x00006B64) FRER Discarded Packet Counter Register 44 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN44_b; + }; + + union + { + __IM uint32_t FWFRPPCN45; /*!< (@ 0x00006B68) FRER Passed Packet Counter Register 45 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN45_b; + }; + + union + { + __IM uint32_t FWFRDPCN45; /*!< (@ 0x00006B6C) FRER Discarded Packet Counter Register 45 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN45_b; + }; + + union + { + __IM uint32_t FWFRPPCN46; /*!< (@ 0x00006B70) FRER Passed Packet Counter Register 46 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN46_b; + }; + + union + { + __IM uint32_t FWFRDPCN46; /*!< (@ 0x00006B74) FRER Discarded Packet Counter Register 46 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN46_b; + }; + + union + { + __IM uint32_t FWFRPPCN47; /*!< (@ 0x00006B78) FRER Passed Packet Counter Register 47 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN47_b; + }; + + union + { + __IM uint32_t FWFRDPCN47; /*!< (@ 0x00006B7C) FRER Discarded Packet Counter Register 47 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN47_b; + }; + + union + { + __IM uint32_t FWFRPPCN48; /*!< (@ 0x00006B80) FRER Passed Packet Counter Register 48 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN48_b; + }; + + union + { + __IM uint32_t FWFRDPCN48; /*!< (@ 0x00006B84) FRER Discarded Packet Counter Register 48 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN48_b; + }; + + union + { + __IM uint32_t FWFRPPCN49; /*!< (@ 0x00006B88) FRER Passed Packet Counter Register 49 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN49_b; + }; + + union + { + __IM uint32_t FWFRDPCN49; /*!< (@ 0x00006B8C) FRER Discarded Packet Counter Register 49 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN49_b; + }; + + union + { + __IM uint32_t FWFRPPCN50; /*!< (@ 0x00006B90) FRER Passed Packet Counter Register 50 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN50_b; + }; + + union + { + __IM uint32_t FWFRDPCN50; /*!< (@ 0x00006B94) FRER Discarded Packet Counter Register 50 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN50_b; + }; + + union + { + __IM uint32_t FWFRPPCN51; /*!< (@ 0x00006B98) FRER Passed Packet Counter Register 51 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN51_b; + }; + + union + { + __IM uint32_t FWFRDPCN51; /*!< (@ 0x00006B9C) FRER Discarded Packet Counter Register 51 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN51_b; + }; + + union + { + __IM uint32_t FWFRPPCN52; /*!< (@ 0x00006BA0) FRER Passed Packet Counter Register 52 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN52_b; + }; + + union + { + __IM uint32_t FWFRDPCN52; /*!< (@ 0x00006BA4) FRER Discarded Packet Counter Register 52 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN52_b; + }; + + union + { + __IM uint32_t FWFRPPCN53; /*!< (@ 0x00006BA8) FRER Passed Packet Counter Register 53 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN53_b; + }; + + union + { + __IM uint32_t FWFRDPCN53; /*!< (@ 0x00006BAC) FRER Discarded Packet Counter Register 53 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN53_b; + }; + + union + { + __IM uint32_t FWFRPPCN54; /*!< (@ 0x00006BB0) FRER Passed Packet Counter Register 54 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN54_b; + }; + + union + { + __IM uint32_t FWFRDPCN54; /*!< (@ 0x00006BB4) FRER Discarded Packet Counter Register 54 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN54_b; + }; + + union + { + __IM uint32_t FWFRPPCN55; /*!< (@ 0x00006BB8) FRER Passed Packet Counter Register 55 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN55_b; + }; + + union + { + __IM uint32_t FWFRDPCN55; /*!< (@ 0x00006BBC) FRER Discarded Packet Counter Register 55 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN55_b; + }; + + union + { + __IM uint32_t FWFRPPCN56; /*!< (@ 0x00006BC0) FRER Passed Packet Counter Register 56 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN56_b; + }; + + union + { + __IM uint32_t FWFRDPCN56; /*!< (@ 0x00006BC4) FRER Discarded Packet Counter Register 56 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN56_b; + }; + + union + { + __IM uint32_t FWFRPPCN57; /*!< (@ 0x00006BC8) FRER Passed Packet Counter Register 57 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN57_b; + }; + + union + { + __IM uint32_t FWFRDPCN57; /*!< (@ 0x00006BCC) FRER Discarded Packet Counter Register 57 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN57_b; + }; + + union + { + __IM uint32_t FWFRPPCN58; /*!< (@ 0x00006BD0) FRER Passed Packet Counter Register 58 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN58_b; + }; + + union + { + __IM uint32_t FWFRDPCN58; /*!< (@ 0x00006BD4) FRER Discarded Packet Counter Register 58 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN58_b; + }; + + union + { + __IM uint32_t FWFRPPCN59; /*!< (@ 0x00006BD8) FRER Passed Packet Counter Register 59 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN59_b; + }; + + union + { + __IM uint32_t FWFRDPCN59; /*!< (@ 0x00006BDC) FRER Discarded Packet Counter Register 59 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN59_b; + }; + + union + { + __IM uint32_t FWFRPPCN60; /*!< (@ 0x00006BE0) FRER Passed Packet Counter Register 60 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN60_b; + }; + + union + { + __IM uint32_t FWFRDPCN60; /*!< (@ 0x00006BE4) FRER Discarded Packet Counter Register 60 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN60_b; + }; + + union + { + __IM uint32_t FWFRPPCN61; /*!< (@ 0x00006BE8) FRER Passed Packet Counter Register 61 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN61_b; + }; + + union + { + __IM uint32_t FWFRDPCN61; /*!< (@ 0x00006BEC) FRER Discarded Packet Counter Register 61 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN61_b; + }; + + union + { + __IM uint32_t FWFRPPCN62; /*!< (@ 0x00006BF0) FRER Passed Packet Counter Register 62 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN62_b; + }; + + union + { + __IM uint32_t FWFRDPCN62; /*!< (@ 0x00006BF4) FRER Discarded Packet Counter Register 62 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN62_b; + }; + + union + { + __IM uint32_t FWFRPPCN63; /*!< (@ 0x00006BF8) FRER Passed Packet Counter Register 63 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN63_b; + }; + + union + { + __IM uint32_t FWFRDPCN63; /*!< (@ 0x00006BFC) FRER Discarded Packet Counter Register 63 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN63_b; + }; + + union + { + __IM uint32_t FWFRPPCN64; /*!< (@ 0x00006C00) FRER Passed Packet Counter Register 64 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN64_b; + }; + + union + { + __IM uint32_t FWFRDPCN64; /*!< (@ 0x00006C04) FRER Discarded Packet Counter Register 64 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN64_b; + }; + + union + { + __IM uint32_t FWFRPPCN65; /*!< (@ 0x00006C08) FRER Passed Packet Counter Register 65 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN65_b; + }; + + union + { + __IM uint32_t FWFRDPCN65; /*!< (@ 0x00006C0C) FRER Discarded Packet Counter Register 65 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN65_b; + }; + + union + { + __IM uint32_t FWFRPPCN66; /*!< (@ 0x00006C10) FRER Passed Packet Counter Register 66 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN66_b; + }; + + union + { + __IM uint32_t FWFRDPCN66; /*!< (@ 0x00006C14) FRER Discarded Packet Counter Register 66 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN66_b; + }; + + union + { + __IM uint32_t FWFRPPCN67; /*!< (@ 0x00006C18) FRER Passed Packet Counter Register 67 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN67_b; + }; + + union + { + __IM uint32_t FWFRDPCN67; /*!< (@ 0x00006C1C) FRER Discarded Packet Counter Register 67 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN67_b; + }; + + union + { + __IM uint32_t FWFRPPCN68; /*!< (@ 0x00006C20) FRER Passed Packet Counter Register 68 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN68_b; + }; + + union + { + __IM uint32_t FWFRDPCN68; /*!< (@ 0x00006C24) FRER Discarded Packet Counter Register 68 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN68_b; + }; + + union + { + __IM uint32_t FWFRPPCN69; /*!< (@ 0x00006C28) FRER Passed Packet Counter Register 69 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN69_b; + }; + + union + { + __IM uint32_t FWFRDPCN69; /*!< (@ 0x00006C2C) FRER Discarded Packet Counter Register 69 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN69_b; + }; + + union + { + __IM uint32_t FWFRPPCN70; /*!< (@ 0x00006C30) FRER Passed Packet Counter Register 70 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN70_b; + }; + + union + { + __IM uint32_t FWFRDPCN70; /*!< (@ 0x00006C34) FRER Discarded Packet Counter Register 70 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN70_b; + }; + + union + { + __IM uint32_t FWFRPPCN71; /*!< (@ 0x00006C38) FRER Passed Packet Counter Register 71 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN71_b; + }; + + union + { + __IM uint32_t FWFRDPCN71; /*!< (@ 0x00006C3C) FRER Discarded Packet Counter Register 71 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN71_b; + }; + + union + { + __IM uint32_t FWFRPPCN72; /*!< (@ 0x00006C40) FRER Passed Packet Counter Register 72 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN72_b; + }; + + union + { + __IM uint32_t FWFRDPCN72; /*!< (@ 0x00006C44) FRER Discarded Packet Counter Register 72 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN72_b; + }; + + union + { + __IM uint32_t FWFRPPCN73; /*!< (@ 0x00006C48) FRER Passed Packet Counter Register 73 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN73_b; + }; + + union + { + __IM uint32_t FWFRDPCN73; /*!< (@ 0x00006C4C) FRER Discarded Packet Counter Register 73 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN73_b; + }; + + union + { + __IM uint32_t FWFRPPCN74; /*!< (@ 0x00006C50) FRER Passed Packet Counter Register 74 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN74_b; + }; + + union + { + __IM uint32_t FWFRDPCN74; /*!< (@ 0x00006C54) FRER Discarded Packet Counter Register 74 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN74_b; + }; + + union + { + __IM uint32_t FWFRPPCN75; /*!< (@ 0x00006C58) FRER Passed Packet Counter Register 75 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN75_b; + }; + + union + { + __IM uint32_t FWFRDPCN75; /*!< (@ 0x00006C5C) FRER Discarded Packet Counter Register 75 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN75_b; + }; + + union + { + __IM uint32_t FWFRPPCN76; /*!< (@ 0x00006C60) FRER Passed Packet Counter Register 76 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN76_b; + }; + + union + { + __IM uint32_t FWFRDPCN76; /*!< (@ 0x00006C64) FRER Discarded Packet Counter Register 76 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN76_b; + }; + + union + { + __IM uint32_t FWFRPPCN77; /*!< (@ 0x00006C68) FRER Passed Packet Counter Register 77 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN77_b; + }; + + union + { + __IM uint32_t FWFRDPCN77; /*!< (@ 0x00006C6C) FRER Discarded Packet Counter Register 77 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN77_b; + }; + + union + { + __IM uint32_t FWFRPPCN78; /*!< (@ 0x00006C70) FRER Passed Packet Counter Register 78 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN78_b; + }; + + union + { + __IM uint32_t FWFRDPCN78; /*!< (@ 0x00006C74) FRER Discarded Packet Counter Register 78 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN78_b; + }; + + union + { + __IM uint32_t FWFRPPCN79; /*!< (@ 0x00006C78) FRER Passed Packet Counter Register 79 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN79_b; + }; + + union + { + __IM uint32_t FWFRDPCN79; /*!< (@ 0x00006C7C) FRER Discarded Packet Counter Register 79 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN79_b; + }; + + union + { + __IM uint32_t FWFRPPCN80; /*!< (@ 0x00006C80) FRER Passed Packet Counter Register 80 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN80_b; + }; + + union + { + __IM uint32_t FWFRDPCN80; /*!< (@ 0x00006C84) FRER Discarded Packet Counter Register 80 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN80_b; + }; + + union + { + __IM uint32_t FWFRPPCN81; /*!< (@ 0x00006C88) FRER Passed Packet Counter Register 81 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN81_b; + }; + + union + { + __IM uint32_t FWFRDPCN81; /*!< (@ 0x00006C8C) FRER Discarded Packet Counter Register 81 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN81_b; + }; + + union + { + __IM uint32_t FWFRPPCN82; /*!< (@ 0x00006C90) FRER Passed Packet Counter Register 82 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN82_b; + }; + + union + { + __IM uint32_t FWFRDPCN82; /*!< (@ 0x00006C94) FRER Discarded Packet Counter Register 82 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN82_b; + }; + + union + { + __IM uint32_t FWFRPPCN83; /*!< (@ 0x00006C98) FRER Passed Packet Counter Register 83 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN83_b; + }; + + union + { + __IM uint32_t FWFRDPCN83; /*!< (@ 0x00006C9C) FRER Discarded Packet Counter Register 83 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN83_b; + }; + + union + { + __IM uint32_t FWFRPPCN84; /*!< (@ 0x00006CA0) FRER Passed Packet Counter Register 84 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN84_b; + }; + + union + { + __IM uint32_t FWFRDPCN84; /*!< (@ 0x00006CA4) FRER Discarded Packet Counter Register 84 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN84_b; + }; + + union + { + __IM uint32_t FWFRPPCN85; /*!< (@ 0x00006CA8) FRER Passed Packet Counter Register 85 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN85_b; + }; + + union + { + __IM uint32_t FWFRDPCN85; /*!< (@ 0x00006CAC) FRER Discarded Packet Counter Register 85 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN85_b; + }; + + union + { + __IM uint32_t FWFRPPCN86; /*!< (@ 0x00006CB0) FRER Passed Packet Counter Register 86 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN86_b; + }; + + union + { + __IM uint32_t FWFRDPCN86; /*!< (@ 0x00006CB4) FRER Discarded Packet Counter Register 86 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN86_b; + }; + + union + { + __IM uint32_t FWFRPPCN87; /*!< (@ 0x00006CB8) FRER Passed Packet Counter Register 87 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN87_b; + }; + + union + { + __IM uint32_t FWFRDPCN87; /*!< (@ 0x00006CBC) FRER Discarded Packet Counter Register 87 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN87_b; + }; + + union + { + __IM uint32_t FWFRPPCN88; /*!< (@ 0x00006CC0) FRER Passed Packet Counter Register 88 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN88_b; + }; + + union + { + __IM uint32_t FWFRDPCN88; /*!< (@ 0x00006CC4) FRER Discarded Packet Counter Register 88 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN88_b; + }; + + union + { + __IM uint32_t FWFRPPCN89; /*!< (@ 0x00006CC8) FRER Passed Packet Counter Register 89 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN89_b; + }; + + union + { + __IM uint32_t FWFRDPCN89; /*!< (@ 0x00006CCC) FRER Discarded Packet Counter Register 89 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN89_b; + }; + + union + { + __IM uint32_t FWFRPPCN90; /*!< (@ 0x00006CD0) FRER Passed Packet Counter Register 90 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN90_b; + }; + + union + { + __IM uint32_t FWFRDPCN90; /*!< (@ 0x00006CD4) FRER Discarded Packet Counter Register 90 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN90_b; + }; + + union + { + __IM uint32_t FWFRPPCN91; /*!< (@ 0x00006CD8) FRER Passed Packet Counter Register 91 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN91_b; + }; + + union + { + __IM uint32_t FWFRDPCN91; /*!< (@ 0x00006CDC) FRER Discarded Packet Counter Register 91 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN91_b; + }; + + union + { + __IM uint32_t FWFRPPCN92; /*!< (@ 0x00006CE0) FRER Passed Packet Counter Register 92 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN92_b; + }; + + union + { + __IM uint32_t FWFRDPCN92; /*!< (@ 0x00006CE4) FRER Discarded Packet Counter Register 92 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN92_b; + }; + + union + { + __IM uint32_t FWFRPPCN93; /*!< (@ 0x00006CE8) FRER Passed Packet Counter Register 93 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN93_b; + }; + + union + { + __IM uint32_t FWFRDPCN93; /*!< (@ 0x00006CEC) FRER Discarded Packet Counter Register 93 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN93_b; + }; + + union + { + __IM uint32_t FWFRPPCN94; /*!< (@ 0x00006CF0) FRER Passed Packet Counter Register 94 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN94_b; + }; + + union + { + __IM uint32_t FWFRDPCN94; /*!< (@ 0x00006CF4) FRER Discarded Packet Counter Register 94 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN94_b; + }; + + union + { + __IM uint32_t FWFRPPCN95; /*!< (@ 0x00006CF8) FRER Passed Packet Counter Register 95 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN95_b; + }; + + union + { + __IM uint32_t FWFRDPCN95; /*!< (@ 0x00006CFC) FRER Discarded Packet Counter Register 95 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN95_b; + }; + + union + { + __IM uint32_t FWFRPPCN96; /*!< (@ 0x00006D00) FRER Passed Packet Counter Register 96 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN96_b; + }; + + union + { + __IM uint32_t FWFRDPCN96; /*!< (@ 0x00006D04) FRER Discarded Packet Counter Register 96 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN96_b; + }; + + union + { + __IM uint32_t FWFRPPCN97; /*!< (@ 0x00006D08) FRER Passed Packet Counter Register 97 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN97_b; + }; + + union + { + __IM uint32_t FWFRDPCN97; /*!< (@ 0x00006D0C) FRER Discarded Packet Counter Register 97 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN97_b; + }; + + union + { + __IM uint32_t FWFRPPCN98; /*!< (@ 0x00006D10) FRER Passed Packet Counter Register 98 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN98_b; + }; + + union + { + __IM uint32_t FWFRDPCN98; /*!< (@ 0x00006D14) FRER Discarded Packet Counter Register 98 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN98_b; + }; + + union + { + __IM uint32_t FWFRPPCN99; /*!< (@ 0x00006D18) FRER Passed Packet Counter Register 99 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN99_b; + }; + + union + { + __IM uint32_t FWFRDPCN99; /*!< (@ 0x00006D1C) FRER Discarded Packet Counter Register 99 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN99_b; + }; + + union + { + __IM uint32_t FWFRPPCN100; /*!< (@ 0x00006D20) FRER Passed Packet Counter Register 100 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN100_b; + }; + + union + { + __IM uint32_t FWFRDPCN100; /*!< (@ 0x00006D24) FRER Discarded Packet Counter Register 100 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN100_b; + }; + + union + { + __IM uint32_t FWFRPPCN101; /*!< (@ 0x00006D28) FRER Passed Packet Counter Register 101 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN101_b; + }; + + union + { + __IM uint32_t FWFRDPCN101; /*!< (@ 0x00006D2C) FRER Discarded Packet Counter Register 101 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN101_b; + }; + + union + { + __IM uint32_t FWFRPPCN102; /*!< (@ 0x00006D30) FRER Passed Packet Counter Register 102 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN102_b; + }; + + union + { + __IM uint32_t FWFRDPCN102; /*!< (@ 0x00006D34) FRER Discarded Packet Counter Register 102 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN102_b; + }; + + union + { + __IM uint32_t FWFRPPCN103; /*!< (@ 0x00006D38) FRER Passed Packet Counter Register 103 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN103_b; + }; + + union + { + __IM uint32_t FWFRDPCN103; /*!< (@ 0x00006D3C) FRER Discarded Packet Counter Register 103 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN103_b; + }; + + union + { + __IM uint32_t FWFRPPCN104; /*!< (@ 0x00006D40) FRER Passed Packet Counter Register 104 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN104_b; + }; + + union + { + __IM uint32_t FWFRDPCN104; /*!< (@ 0x00006D44) FRER Discarded Packet Counter Register 104 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN104_b; + }; + + union + { + __IM uint32_t FWFRPPCN105; /*!< (@ 0x00006D48) FRER Passed Packet Counter Register 105 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN105_b; + }; + + union + { + __IM uint32_t FWFRDPCN105; /*!< (@ 0x00006D4C) FRER Discarded Packet Counter Register 105 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN105_b; + }; + + union + { + __IM uint32_t FWFRPPCN106; /*!< (@ 0x00006D50) FRER Passed Packet Counter Register 106 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN106_b; + }; + + union + { + __IM uint32_t FWFRDPCN106; /*!< (@ 0x00006D54) FRER Discarded Packet Counter Register 106 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN106_b; + }; + + union + { + __IM uint32_t FWFRPPCN107; /*!< (@ 0x00006D58) FRER Passed Packet Counter Register 107 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN107_b; + }; + + union + { + __IM uint32_t FWFRDPCN107; /*!< (@ 0x00006D5C) FRER Discarded Packet Counter Register 107 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN107_b; + }; + + union + { + __IM uint32_t FWFRPPCN108; /*!< (@ 0x00006D60) FRER Passed Packet Counter Register 108 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN108_b; + }; + + union + { + __IM uint32_t FWFRDPCN108; /*!< (@ 0x00006D64) FRER Discarded Packet Counter Register 108 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN108_b; + }; + + union + { + __IM uint32_t FWFRPPCN109; /*!< (@ 0x00006D68) FRER Passed Packet Counter Register 109 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN109_b; + }; + + union + { + __IM uint32_t FWFRDPCN109; /*!< (@ 0x00006D6C) FRER Discarded Packet Counter Register 109 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN109_b; + }; + + union + { + __IM uint32_t FWFRPPCN110; /*!< (@ 0x00006D70) FRER Passed Packet Counter Register 110 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN110_b; + }; + + union + { + __IM uint32_t FWFRDPCN110; /*!< (@ 0x00006D74) FRER Discarded Packet Counter Register 110 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN110_b; + }; + + union + { + __IM uint32_t FWFRPPCN111; /*!< (@ 0x00006D78) FRER Passed Packet Counter Register 111 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN111_b; + }; + + union + { + __IM uint32_t FWFRDPCN111; /*!< (@ 0x00006D7C) FRER Discarded Packet Counter Register 111 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN111_b; + }; + + union + { + __IM uint32_t FWFRPPCN112; /*!< (@ 0x00006D80) FRER Passed Packet Counter Register 112 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN112_b; + }; + + union + { + __IM uint32_t FWFRDPCN112; /*!< (@ 0x00006D84) FRER Discarded Packet Counter Register 112 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN112_b; + }; + + union + { + __IM uint32_t FWFRPPCN113; /*!< (@ 0x00006D88) FRER Passed Packet Counter Register 113 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN113_b; + }; + + union + { + __IM uint32_t FWFRDPCN113; /*!< (@ 0x00006D8C) FRER Discarded Packet Counter Register 113 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN113_b; + }; + + union + { + __IM uint32_t FWFRPPCN114; /*!< (@ 0x00006D90) FRER Passed Packet Counter Register 114 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN114_b; + }; + + union + { + __IM uint32_t FWFRDPCN114; /*!< (@ 0x00006D94) FRER Discarded Packet Counter Register 114 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN114_b; + }; + + union + { + __IM uint32_t FWFRPPCN115; /*!< (@ 0x00006D98) FRER Passed Packet Counter Register 115 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN115_b; + }; + + union + { + __IM uint32_t FWFRDPCN115; /*!< (@ 0x00006D9C) FRER Discarded Packet Counter Register 115 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN115_b; + }; + + union + { + __IM uint32_t FWFRPPCN116; /*!< (@ 0x00006DA0) FRER Passed Packet Counter Register 116 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN116_b; + }; + + union + { + __IM uint32_t FWFRDPCN116; /*!< (@ 0x00006DA4) FRER Discarded Packet Counter Register 116 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN116_b; + }; + + union + { + __IM uint32_t FWFRPPCN117; /*!< (@ 0x00006DA8) FRER Passed Packet Counter Register 117 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN117_b; + }; + + union + { + __IM uint32_t FWFRDPCN117; /*!< (@ 0x00006DAC) FRER Discarded Packet Counter Register 117 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN117_b; + }; + + union + { + __IM uint32_t FWFRPPCN118; /*!< (@ 0x00006DB0) FRER Passed Packet Counter Register 118 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN118_b; + }; + + union + { + __IM uint32_t FWFRDPCN118; /*!< (@ 0x00006DB4) FRER Discarded Packet Counter Register 118 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN118_b; + }; + + union + { + __IM uint32_t FWFRPPCN119; /*!< (@ 0x00006DB8) FRER Passed Packet Counter Register 119 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN119_b; + }; + + union + { + __IM uint32_t FWFRDPCN119; /*!< (@ 0x00006DBC) FRER Discarded Packet Counter Register 119 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN119_b; + }; + + union + { + __IM uint32_t FWFRPPCN120; /*!< (@ 0x00006DC0) FRER Passed Packet Counter Register 120 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN120_b; + }; + + union + { + __IM uint32_t FWFRDPCN120; /*!< (@ 0x00006DC4) FRER Discarded Packet Counter Register 120 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN120_b; + }; + + union + { + __IM uint32_t FWFRPPCN121; /*!< (@ 0x00006DC8) FRER Passed Packet Counter Register 121 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN121_b; + }; + + union + { + __IM uint32_t FWFRDPCN121; /*!< (@ 0x00006DCC) FRER Discarded Packet Counter Register 121 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN121_b; + }; + + union + { + __IM uint32_t FWFRPPCN122; /*!< (@ 0x00006DD0) FRER Passed Packet Counter Register 122 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN122_b; + }; + + union + { + __IM uint32_t FWFRDPCN122; /*!< (@ 0x00006DD4) FRER Discarded Packet Counter Register 122 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN122_b; + }; + + union + { + __IM uint32_t FWFRPPCN123; /*!< (@ 0x00006DD8) FRER Passed Packet Counter Register 123 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN123_b; + }; + + union + { + __IM uint32_t FWFRDPCN123; /*!< (@ 0x00006DDC) FRER Discarded Packet Counter Register 123 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN123_b; + }; + + union + { + __IM uint32_t FWFRPPCN124; /*!< (@ 0x00006DE0) FRER Passed Packet Counter Register 124 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN124_b; + }; + + union + { + __IM uint32_t FWFRDPCN124; /*!< (@ 0x00006DE4) FRER Discarded Packet Counter Register 124 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN124_b; + }; + + union + { + __IM uint32_t FWFRPPCN125; /*!< (@ 0x00006DE8) FRER Passed Packet Counter Register 125 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN125_b; + }; + + union + { + __IM uint32_t FWFRDPCN125; /*!< (@ 0x00006DEC) FRER Discarded Packet Counter Register 125 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN125_b; + }; + + union + { + __IM uint32_t FWFRPPCN126; /*!< (@ 0x00006DF0) FRER Passed Packet Counter Register 126 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN126_b; + }; + + union + { + __IM uint32_t FWFRDPCN126; /*!< (@ 0x00006DF4) FRER Discarded Packet Counter Register 126 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN126_b; + }; + + union + { + __IM uint32_t FWFRPPCN127; /*!< (@ 0x00006DF8) FRER Passed Packet Counter Register 127 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN127_b; + }; + + union + { + __IM uint32_t FWFRDPCN127; /*!< (@ 0x00006DFC) FRER Discarded Packet Counter Register 127 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN127_b; + }; + __IM uint32_t RESERVED261[704]; + + union + { + __IOM uint32_t FWEIS00; /*!< (@ 0x00007900) Error Interrupt Status Register 00 */ + + struct + { + __IOM uint32_t LTHSPFS : 1; /*!< [0..0] Layer 3 Source Port Filtering Status */ + uint32_t : 1; + __IOM uint32_t LTHNTFS : 1; /*!< [2..2] Layer 3 No Target Filtering Status */ + __IOM uint32_t LTHUFS : 1; /*!< [3..3] Layer 3 Unknown Filtering Status */ + uint32_t : 6; + __IOM uint32_t LTWDSPFS : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Status */ + __IOM uint32_t LTWSSPFS : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Status */ + __IOM uint32_t LTWVSPFS : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Status */ + __IOM uint32_t LTWNTFS : 1; /*!< [13..13] Layer 2 No Target Filtering Status */ + __IOM uint32_t LTWSUFS : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Status */ + __IOM uint32_t LTWDUFS : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Status */ + __IOM uint32_t LTWVUFS : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Status */ + __IOM uint32_t PBNTFS : 1; /*!< [17..17] Port Based No Target Filtering Status */ + __IOM uint32_t SMHLFS : 1; /*!< [18..18] Source MAC Hardware Learning Fail Status */ + __IOM uint32_t SMHMFS : 1; /*!< [19..19] Source MAC Hardware Migration Fail Status */ + uint32_t : 2; + __IOM uint32_t WMCFS : 1; /*!< [22..22] Watermark Critical Filtering Status */ + __IOM uint32_t WMFFS : 1; /*!< [23..23] Watermark Flush Filtering Status */ + __IOM uint32_t WMISFS : 1; /*!< [24..24] Watermark IPV Secure Filtering Status */ + __IOM uint32_t WMIUFS : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Status */ + __IOM uint32_t DDES : 1; /*!< [26..26] Direct Descriptor Error Status i */ + uint32_t : 1; + __IOM uint32_t DDSES : 1; /*!< [28..28] Direct Descriptor Security Error Status */ + __IOM uint32_t DDNTFS : 1; /*!< [29..29] Direct Descriptor No Target Filtering Status */ + uint32_t : 2; + } FWEIS00_b; + }; + + union + { + __IOM uint32_t FWEIE00; /*!< (@ 0x00007904) Error Interrupt Enable Register 00 */ + + struct + { + __IOM uint32_t LTHSPFE : 1; /*!< [0..0] Layer 3 Source Port Filtering Enable */ + uint32_t : 1; + __IOM uint32_t LTHNTFE : 1; /*!< [2..2] Layer 3 No Target Filtering Enable */ + __IOM uint32_t LTHUFE : 1; /*!< [3..3] Layer 3 Unknown Filtering Enable */ + uint32_t : 6; + __IOM uint32_t LTWDSPFE : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Enable */ + __IOM uint32_t LTWSSPFE : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Enable */ + __IOM uint32_t LTWVSPFE : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Enable */ + __IOM uint32_t LTWNTFE : 1; /*!< [13..13] Layer 2 No Target Filtering Enable */ + __IOM uint32_t LTWSUFE : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Enable */ + __IOM uint32_t LTWDUFE : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Enable */ + __IOM uint32_t LTWVUFE : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Enable */ + __IOM uint32_t PBNTFE : 1; /*!< [17..17] Port Based No Target Filtering Enable */ + __IOM uint32_t SMHLFE : 1; /*!< [18..18] Source MAC Hardware Learning Fail Enable */ + __IOM uint32_t SMHMFE : 1; /*!< [19..19] Source MAC Hardware Migration Fail Enable */ + uint32_t : 2; + __IOM uint32_t WMCFE : 1; /*!< [22..22] Watermark Critical Filtering Enable */ + __IOM uint32_t WMFFE : 1; /*!< [23..23] Watermark Flush Filtering Enable */ + __IOM uint32_t WMISFE : 1; /*!< [24..24] Watermark IPV Secure Filtering Enable */ + __IOM uint32_t WMIUFE : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Enable */ + __IOM uint32_t DDEE : 1; /*!< [26..26] Direct Descriptor Error Enable */ + __IOM uint32_t DDFEE : 1; /*!< [27..27] Direct Descriptor Format Error Enable */ + __IOM uint32_t DDSEE : 1; /*!< [28..28] Direct Descriptor Security Error Enable */ + __IOM uint32_t DDNTFE : 1; /*!< [29..29] Direct Descriptor No Target Filtering Enable */ + uint32_t : 2; + } FWEIE00_b; + }; + + union + { + __IOM uint32_t FWEID00; /*!< (@ 0x00007908) Error Interrupt Disable Register 00 */ + + struct + { + __IOM uint32_t LTHSPFD : 1; /*!< [0..0] Layer 3 Source Port Filtering Disable */ + uint32_t : 1; + __IOM uint32_t LTHNTFD : 1; /*!< [2..2] Layer 3 No Target Filtering Disable */ + __IOM uint32_t LTHUFD : 1; /*!< [3..3] Layer 3 Unknown Filtering Disable */ + uint32_t : 6; + __IOM uint32_t LTWDSPFD : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Disable */ + __IOM uint32_t LTWSSPFD : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Disable */ + __IOM uint32_t LTWVSPFD : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Disable */ + __IOM uint32_t LTWNTFD : 1; /*!< [13..13] Layer 2 No Target Filtering Disable */ + __IOM uint32_t LTWSUFD : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Disable */ + __IOM uint32_t LTWDUFD : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Disable */ + __IOM uint32_t LTWVUFD : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Disable */ + __IOM uint32_t PBNTFD : 1; /*!< [17..17] Port Based No Target Filtering Disable */ + __IOM uint32_t SMHLFD : 1; /*!< [18..18] Source MAC Hardware Learning Fail Disable */ + __IOM uint32_t SMHMFD : 1; /*!< [19..19] Source MAC Hardware Migration Fail Disable */ + uint32_t : 2; + __IOM uint32_t WMCFD : 1; /*!< [22..22] Watermark Critical Filtering Disable */ + __IOM uint32_t WMFFD : 1; /*!< [23..23] Watermark Flush Filtering Disable */ + __IOM uint32_t WMISFD : 1; /*!< [24..24] Watermark IPV Secure Filtering Disable */ + __IOM uint32_t WMIUFD : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Disable */ + __IOM uint32_t DDED : 1; /*!< [26..26] Direct Descriptor Error Disable */ + __IOM uint32_t DDFED : 1; /*!< [27..27] Direct Descriptor Format Error Disable */ + __IOM uint32_t DDSED : 1; /*!< [28..28] Direct Descriptor Security Error Disable */ + __IOM uint32_t DDNTFD : 1; /*!< [29..29] Direct Descriptor No Target Filtering Disable */ + uint32_t : 2; + } FWEID00_b; + }; + __IM uint32_t RESERVED262; + + union + { + __IOM uint32_t FWEIS01; /*!< (@ 0x00007910) Error Interrupt Status Register 01 */ + + struct + { + __IOM uint32_t LTHSPFS : 1; /*!< [0..0] Layer 3 Source Port Filtering Status */ + uint32_t : 1; + __IOM uint32_t LTHNTFS : 1; /*!< [2..2] Layer 3 No Target Filtering Status */ + __IOM uint32_t LTHUFS : 1; /*!< [3..3] Layer 3 Unknown Filtering Status */ + uint32_t : 6; + __IOM uint32_t LTWDSPFS : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Status */ + __IOM uint32_t LTWSSPFS : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Status */ + __IOM uint32_t LTWVSPFS : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Status */ + __IOM uint32_t LTWNTFS : 1; /*!< [13..13] Layer 2 No Target Filtering Status */ + __IOM uint32_t LTWSUFS : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Status */ + __IOM uint32_t LTWDUFS : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Status */ + __IOM uint32_t LTWVUFS : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Status */ + __IOM uint32_t PBNTFS : 1; /*!< [17..17] Port Based No Target Filtering Status */ + __IOM uint32_t SMHLFS : 1; /*!< [18..18] Source MAC Hardware Learning Fail Status */ + __IOM uint32_t SMHMFS : 1; /*!< [19..19] Source MAC Hardware Migration Fail Status */ + uint32_t : 2; + __IOM uint32_t WMCFS : 1; /*!< [22..22] Watermark Critical Filtering Status */ + __IOM uint32_t WMFFS : 1; /*!< [23..23] Watermark Flush Filtering Status */ + __IOM uint32_t WMISFS : 1; /*!< [24..24] Watermark IPV Secure Filtering Status */ + __IOM uint32_t WMIUFS : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Status */ + __IOM uint32_t DDES : 1; /*!< [26..26] Direct Descriptor Error Status i */ + uint32_t : 1; + __IOM uint32_t DDSES : 1; /*!< [28..28] Direct Descriptor Security Error Status */ + __IOM uint32_t DDNTFS : 1; /*!< [29..29] Direct Descriptor No Target Filtering Status */ + uint32_t : 2; + } FWEIS01_b; + }; + + union + { + __IOM uint32_t FWEIE01; /*!< (@ 0x00007914) Error Interrupt Enable Register 01 */ + + struct + { + __IOM uint32_t LTHSPFE : 1; /*!< [0..0] Layer 3 Source Port Filtering Enable */ + uint32_t : 1; + __IOM uint32_t LTHNTFE : 1; /*!< [2..2] Layer 3 No Target Filtering Enable */ + __IOM uint32_t LTHUFE : 1; /*!< [3..3] Layer 3 Unknown Filtering Enable */ + uint32_t : 6; + __IOM uint32_t LTWDSPFE : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Enable */ + __IOM uint32_t LTWSSPFE : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Enable */ + __IOM uint32_t LTWVSPFE : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Enable */ + __IOM uint32_t LTWNTFE : 1; /*!< [13..13] Layer 2 No Target Filtering Enable */ + __IOM uint32_t LTWSUFE : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Enable */ + __IOM uint32_t LTWDUFE : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Enable */ + __IOM uint32_t LTWVUFE : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Enable */ + __IOM uint32_t PBNTFE : 1; /*!< [17..17] Port Based No Target Filtering Enable */ + __IOM uint32_t SMHLFE : 1; /*!< [18..18] Source MAC Hardware Learning Fail Enable */ + __IOM uint32_t SMHMFE : 1; /*!< [19..19] Source MAC Hardware Migration Fail Enable */ + uint32_t : 2; + __IOM uint32_t WMCFE : 1; /*!< [22..22] Watermark Critical Filtering Enable */ + __IOM uint32_t WMFFE : 1; /*!< [23..23] Watermark Flush Filtering Enable */ + __IOM uint32_t WMISFE : 1; /*!< [24..24] Watermark IPV Secure Filtering Enable */ + __IOM uint32_t WMIUFE : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Enable */ + __IOM uint32_t DDEE : 1; /*!< [26..26] Direct Descriptor Error Enable */ + __IOM uint32_t DDFEE : 1; /*!< [27..27] Direct Descriptor Format Error Enable */ + __IOM uint32_t DDSEE : 1; /*!< [28..28] Direct Descriptor Security Error Enable */ + __IOM uint32_t DDNTFE : 1; /*!< [29..29] Direct Descriptor No Target Filtering Enable */ + uint32_t : 2; + } FWEIE01_b; + }; + + union + { + __IOM uint32_t FWEID01; /*!< (@ 0x00007918) Error Interrupt Disable Register 01 */ + + struct + { + __IOM uint32_t LTHSPFD : 1; /*!< [0..0] Layer 3 Source Port Filtering Disable */ + uint32_t : 1; + __IOM uint32_t LTHNTFD : 1; /*!< [2..2] Layer 3 No Target Filtering Disable */ + __IOM uint32_t LTHUFD : 1; /*!< [3..3] Layer 3 Unknown Filtering Disable */ + uint32_t : 6; + __IOM uint32_t LTWDSPFD : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Disable */ + __IOM uint32_t LTWSSPFD : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Disable */ + __IOM uint32_t LTWVSPFD : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Disable */ + __IOM uint32_t LTWNTFD : 1; /*!< [13..13] Layer 2 No Target Filtering Disable */ + __IOM uint32_t LTWSUFD : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Disable */ + __IOM uint32_t LTWDUFD : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Disable */ + __IOM uint32_t LTWVUFD : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Disable */ + __IOM uint32_t PBNTFD : 1; /*!< [17..17] Port Based No Target Filtering Disable */ + __IOM uint32_t SMHLFD : 1; /*!< [18..18] Source MAC Hardware Learning Fail Disable */ + __IOM uint32_t SMHMFD : 1; /*!< [19..19] Source MAC Hardware Migration Fail Disable */ + uint32_t : 2; + __IOM uint32_t WMCFD : 1; /*!< [22..22] Watermark Critical Filtering Disable */ + __IOM uint32_t WMFFD : 1; /*!< [23..23] Watermark Flush Filtering Disable */ + __IOM uint32_t WMISFD : 1; /*!< [24..24] Watermark IPV Secure Filtering Disable */ + __IOM uint32_t WMIUFD : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Disable */ + __IOM uint32_t DDED : 1; /*!< [26..26] Direct Descriptor Error Disable */ + __IOM uint32_t DDFED : 1; /*!< [27..27] Direct Descriptor Format Error Disable */ + __IOM uint32_t DDSED : 1; /*!< [28..28] Direct Descriptor Security Error Disable */ + __IOM uint32_t DDNTFD : 1; /*!< [29..29] Direct Descriptor No Target Filtering Disable */ + uint32_t : 2; + } FWEID01_b; + }; + __IM uint32_t RESERVED263; + + union + { + __IOM uint32_t FWEIS02; /*!< (@ 0x00007920) Error Interrupt Status Register 02 */ + + struct + { + __IOM uint32_t LTHSPFS : 1; /*!< [0..0] Layer 3 Source Port Filtering Status */ + uint32_t : 1; + __IOM uint32_t LTHNTFS : 1; /*!< [2..2] Layer 3 No Target Filtering Status */ + __IOM uint32_t LTHUFS : 1; /*!< [3..3] Layer 3 Unknown Filtering Status */ + uint32_t : 6; + __IOM uint32_t LTWDSPFS : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Status */ + __IOM uint32_t LTWSSPFS : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Status */ + __IOM uint32_t LTWVSPFS : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Status */ + __IOM uint32_t LTWNTFS : 1; /*!< [13..13] Layer 2 No Target Filtering Status */ + __IOM uint32_t LTWSUFS : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Status */ + __IOM uint32_t LTWDUFS : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Status */ + __IOM uint32_t LTWVUFS : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Status */ + __IOM uint32_t PBNTFS : 1; /*!< [17..17] Port Based No Target Filtering Status */ + __IOM uint32_t SMHLFS : 1; /*!< [18..18] Source MAC Hardware Learning Fail Status */ + __IOM uint32_t SMHMFS : 1; /*!< [19..19] Source MAC Hardware Migration Fail Status */ + uint32_t : 2; + __IOM uint32_t WMCFS : 1; /*!< [22..22] Watermark Critical Filtering Status */ + __IOM uint32_t WMFFS : 1; /*!< [23..23] Watermark Flush Filtering Status */ + __IOM uint32_t WMISFS : 1; /*!< [24..24] Watermark IPV Secure Filtering Status */ + __IOM uint32_t WMIUFS : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Status */ + __IOM uint32_t DDES : 1; /*!< [26..26] Direct Descriptor Error Status i */ + uint32_t : 1; + __IOM uint32_t DDSES : 1; /*!< [28..28] Direct Descriptor Security Error Status */ + __IOM uint32_t DDNTFS : 1; /*!< [29..29] Direct Descriptor No Target Filtering Status */ + uint32_t : 2; + } FWEIS02_b; + }; + + union + { + __IOM uint32_t FWEIE02; /*!< (@ 0x00007924) Error Interrupt Enable Register 02 */ + + struct + { + __IOM uint32_t LTHSPFE : 1; /*!< [0..0] Layer 3 Source Port Filtering Enable */ + uint32_t : 1; + __IOM uint32_t LTHNTFE : 1; /*!< [2..2] Layer 3 No Target Filtering Enable */ + __IOM uint32_t LTHUFE : 1; /*!< [3..3] Layer 3 Unknown Filtering Enable */ + uint32_t : 6; + __IOM uint32_t LTWDSPFE : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Enable */ + __IOM uint32_t LTWSSPFE : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Enable */ + __IOM uint32_t LTWVSPFE : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Enable */ + __IOM uint32_t LTWNTFE : 1; /*!< [13..13] Layer 2 No Target Filtering Enable */ + __IOM uint32_t LTWSUFE : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Enable */ + __IOM uint32_t LTWDUFE : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Enable */ + __IOM uint32_t LTWVUFE : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Enable */ + __IOM uint32_t PBNTFE : 1; /*!< [17..17] Port Based No Target Filtering Enable */ + __IOM uint32_t SMHLFE : 1; /*!< [18..18] Source MAC Hardware Learning Fail Enable */ + __IOM uint32_t SMHMFE : 1; /*!< [19..19] Source MAC Hardware Migration Fail Enable */ + uint32_t : 2; + __IOM uint32_t WMCFE : 1; /*!< [22..22] Watermark Critical Filtering Enable */ + __IOM uint32_t WMFFE : 1; /*!< [23..23] Watermark Flush Filtering Enable */ + __IOM uint32_t WMISFE : 1; /*!< [24..24] Watermark IPV Secure Filtering Enable */ + __IOM uint32_t WMIUFE : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Enable */ + __IOM uint32_t DDEE : 1; /*!< [26..26] Direct Descriptor Error Enable */ + __IOM uint32_t DDFEE : 1; /*!< [27..27] Direct Descriptor Format Error Enable */ + __IOM uint32_t DDSEE : 1; /*!< [28..28] Direct Descriptor Security Error Enable */ + __IOM uint32_t DDNTFE : 1; /*!< [29..29] Direct Descriptor No Target Filtering Enable */ + uint32_t : 2; + } FWEIE02_b; + }; + + union + { + __IOM uint32_t FWEID02; /*!< (@ 0x00007928) Error Interrupt Disable Register 02 */ + + struct + { + __IOM uint32_t LTHSPFD : 1; /*!< [0..0] Layer 3 Source Port Filtering Disable */ + uint32_t : 1; + __IOM uint32_t LTHNTFD : 1; /*!< [2..2] Layer 3 No Target Filtering Disable */ + __IOM uint32_t LTHUFD : 1; /*!< [3..3] Layer 3 Unknown Filtering Disable */ + uint32_t : 6; + __IOM uint32_t LTWDSPFD : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Disable */ + __IOM uint32_t LTWSSPFD : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Disable */ + __IOM uint32_t LTWVSPFD : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Disable */ + __IOM uint32_t LTWNTFD : 1; /*!< [13..13] Layer 2 No Target Filtering Disable */ + __IOM uint32_t LTWSUFD : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Disable */ + __IOM uint32_t LTWDUFD : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Disable */ + __IOM uint32_t LTWVUFD : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Disable */ + __IOM uint32_t PBNTFD : 1; /*!< [17..17] Port Based No Target Filtering Disable */ + __IOM uint32_t SMHLFD : 1; /*!< [18..18] Source MAC Hardware Learning Fail Disable */ + __IOM uint32_t SMHMFD : 1; /*!< [19..19] Source MAC Hardware Migration Fail Disable */ + uint32_t : 2; + __IOM uint32_t WMCFD : 1; /*!< [22..22] Watermark Critical Filtering Disable */ + __IOM uint32_t WMFFD : 1; /*!< [23..23] Watermark Flush Filtering Disable */ + __IOM uint32_t WMISFD : 1; /*!< [24..24] Watermark IPV Secure Filtering Disable */ + __IOM uint32_t WMIUFD : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Disable */ + __IOM uint32_t DDED : 1; /*!< [26..26] Direct Descriptor Error Disable */ + __IOM uint32_t DDFED : 1; /*!< [27..27] Direct Descriptor Format Error Disable */ + __IOM uint32_t DDSED : 1; /*!< [28..28] Direct Descriptor Security Error Disable */ + __IOM uint32_t DDNTFD : 1; /*!< [29..29] Direct Descriptor No Target Filtering Disable */ + uint32_t : 2; + } FWEID02_b; + }; + __IM uint32_t RESERVED264[53]; + + union + { + __IOM uint32_t FWEIS1; /*!< (@ 0x00007A00) Error Interrupt Status Register 1 */ + + struct + { + __IOM uint32_t LTHTEES : 1; /*!< [0..0] L3 Table ECC Error Status */ + __IOM uint32_t LTHTSES : 1; /*!< [1..1] L3 Table Security Error Status */ + uint32_t : 2; + __IOM uint32_t MACTEES : 1; /*!< [4..4] MAC Table ECC Error Status */ + __IOM uint32_t MACTSES : 1; /*!< [5..5] MAC Table Security Error Status */ + __IOM uint32_t VLANTEES : 1; /*!< [6..6] VLAN Table ECC Error Status */ + __IOM uint32_t VLANTSES : 1; /*!< [7..7] VLAN Table Security Error Status */ + __IOM uint32_t L23UEES : 1; /*!< [8..8] Layer 2/Layer 3 Update ECC Error Status */ + uint32_t : 7; + __IOM uint32_t AREES : 1; /*!< [16..16] ATS RAM ECC Error Status */ + uint32_t : 15; + } FWEIS1_b; + }; + + union + { + __IOM uint32_t FWEIE1; /*!< (@ 0x00007A04) Error Interrupt Enable Register 1 */ + + struct + { + __IOM uint32_t LTHTEEE : 1; /*!< [0..0] L3 Table ECC Error Enable */ + __IOM uint32_t LTHTSEE : 1; /*!< [1..1] L3 Table Security Error Enable */ + uint32_t : 2; + __IOM uint32_t MACTEEE : 1; /*!< [4..4] MAC Table ECC Error Enable */ + __IOM uint32_t MACTSEE : 1; /*!< [5..5] MAC Table Security Error Enable */ + __IOM uint32_t VLANTEEE : 1; /*!< [6..6] VLAN Table ECC Error Enable */ + __IOM uint32_t VLANTSEE : 1; /*!< [7..7] VLAN Table Security Error Enable */ + __IOM uint32_t L23UEEE : 1; /*!< [8..8] Layer 2/Layer 3 Update ECC Error Enable */ + uint32_t : 7; + __IOM uint32_t AREEE : 1; /*!< [16..16] ATS RAM ECC Error Enable */ + uint32_t : 15; + } FWEIE1_b; + }; + + union + { + __IOM uint32_t FWEID1; /*!< (@ 0x00007A08) Error Interrupt Disable Register 1 */ + + struct + { + __IOM uint32_t LTHTEED : 1; /*!< [0..0] L3 Table ECC Error Disable */ + __IOM uint32_t LTHTSED : 1; /*!< [1..1] L3 Table Security Error Disable */ + uint32_t : 2; + __IOM uint32_t MACTEED : 1; /*!< [4..4] MAC Table ECC Error Disable */ + __IOM uint32_t MACTSED : 1; /*!< [5..5] MAC Table Security Error Disable */ + __IOM uint32_t VLANTEED : 1; /*!< [6..6] VLAN Table ECC Error Disable */ + __IOM uint32_t VLANTSED : 1; /*!< [7..7] VLAN Table Security Error Disable */ + __IOM uint32_t L23UEED : 1; /*!< [8..8] Layer 2/Layer 3 Update ECC Error Disable */ + uint32_t : 7; + __IOM uint32_t AREED : 1; /*!< [16..16] ATS RAM ECC Error Disable */ + uint32_t : 15; + } FWEID1_b; + }; + __IM uint32_t RESERVED265; + + union + { + __IOM uint32_t FWEIS2; /*!< (@ 0x00007A10) Error Interrupt Status Register 2 */ + + struct + { + __IOM uint32_t PMFS : 16; /*!< [15..0] PSFP MSDU Filtering Status */ + uint32_t : 16; + } FWEIS2_b; + }; + + union + { + __IOM uint32_t FWEIE2; /*!< (@ 0x00007A14) Error Interrupt Enable Register 2 */ + + struct + { + __IOM uint32_t PMFE : 16; /*!< [15..0] PSFP MSDU Filtering Enable */ + uint32_t : 16; + } FWEIE2_b; + }; + + union + { + __IOM uint32_t FWEID2; /*!< (@ 0x00007A18) Error Interrupt Disable Register 2 */ + + struct + { + __IOM uint32_t PMFD : 16; /*!< [15..0] PSFP MSDU Filtering Disable */ + uint32_t : 16; + } FWEID2_b; + }; + __IM uint32_t RESERVED266[9]; + + union + { + __IOM uint32_t FWEIS5; /*!< (@ 0x00007A40) Error Interrupt Status Register 5 */ + + struct + { + __IOM uint32_t PMRFS : 32; /*!< [31..0] PSFP Meter Filtering Status */ + } FWEIS5_b; + }; + + union + { + __IOM uint32_t FWEIE5; /*!< (@ 0x00007A44) Error Interrupt Enable Register 5 */ + + struct + { + __IOM uint32_t PMRFE : 32; /*!< [31..0] PSFP Meter Filtering Enable */ + } FWEIE5_b; + }; + + union + { + __IOM uint32_t FWEID5; /*!< (@ 0x00007A48) Error Interrupt Disable Register 5 */ + + struct + { + __IOM uint32_t PMRFD : 32; /*!< [31..0] PSFP Meter Filtering Disable */ + } FWEID5_b; + }; + __IM uint32_t RESERVED267; + + union + { + __IOM uint32_t FWEIS60; /*!< (@ 0x00007A50) Error Interrupt Status Register 60 */ + + struct + { + __IOM uint32_t FFS : 32; /*!< [31..0] FRER Filtering Status */ + } FWEIS60_b; + }; + + union + { + __IOM uint32_t FWEIE60; /*!< (@ 0x00007A54) Error Interrupt Enable Register 60 */ + + struct + { + __IOM uint32_t FFE : 32; /*!< [31..0] FRER Filtering Enable */ + } FWEIE60_b; + }; + + union + { + __IOM uint32_t FWEID60; /*!< (@ 0x00007A58) Error Interrupt Disable Register 60 */ + + struct + { + __IOM uint32_t FFD : 32; /*!< [31..0] FRER Filtering Disable */ + } FWEID60_b; + }; + __IM uint32_t RESERVED268; + + union + { + __IOM uint32_t FWEIS61; /*!< (@ 0x00007A60) Error Interrupt Status Register 61 */ + + struct + { + __IOM uint32_t FFS : 32; /*!< [31..0] FRER Filtering Status */ + } FWEIS61_b; + }; + + union + { + __IOM uint32_t FWEIE61; /*!< (@ 0x00007A64) Error Interrupt Enable Register 61 */ + + struct + { + __IOM uint32_t FFE : 32; /*!< [31..0] FRER Filtering Enable */ + } FWEIE61_b; + }; + + union + { + __IOM uint32_t FWEID61; /*!< (@ 0x00007A68) Error Interrupt Disable Register 61 */ + + struct + { + __IOM uint32_t FFD : 32; /*!< [31..0] FRER Filtering Disable */ + } FWEID61_b; + }; + __IM uint32_t RESERVED269; + + union + { + __IOM uint32_t FWEIS62; /*!< (@ 0x00007A70) Error Interrupt Status Register 62 */ + + struct + { + __IOM uint32_t FFS : 32; /*!< [31..0] FRER Filtering Status */ + } FWEIS62_b; + }; + + union + { + __IOM uint32_t FWEIE62; /*!< (@ 0x00007A74) Error Interrupt Enable Register 62 */ + + struct + { + __IOM uint32_t FFE : 32; /*!< [31..0] FRER Filtering Enable */ + } FWEIE62_b; + }; + + union + { + __IOM uint32_t FWEID62; /*!< (@ 0x00007A78) Error Interrupt Disable Register 62 */ + + struct + { + __IOM uint32_t FFD : 32; /*!< [31..0] FRER Filtering Disable */ + } FWEID62_b; + }; + __IM uint32_t RESERVED270; + + union + { + __IOM uint32_t FWEIS63; /*!< (@ 0x00007A80) Error Interrupt Status Register 63 */ + + struct + { + __IOM uint32_t FFS : 32; /*!< [31..0] FRER Filtering Status */ + } FWEIS63_b; + }; + + union + { + __IOM uint32_t FWEIE63; /*!< (@ 0x00007A84) Error Interrupt Enable Register 63 */ + + struct + { + __IOM uint32_t FFE : 32; /*!< [31..0] FRER Filtering Enable */ + } FWEIE63_b; + }; + + union + { + __IOM uint32_t FWEID63; /*!< (@ 0x00007A88) Error Interrupt Disable Register 63 */ + + struct + { + __IOM uint32_t FFD : 32; /*!< [31..0] FRER Filtering Disable */ + } FWEID63_b; + }; + __IM uint32_t RESERVED271; + + union + { + __IOM uint32_t FWEIS70; /*!< (@ 0x00007A90) Error Interrupt Status Register 70 */ + + struct + { + __IOM uint32_t FOORS : 32; /*!< [31..0] FRER Out Of Range Status */ + } FWEIS70_b; + }; + + union + { + __IOM uint32_t FWEIE70; /*!< (@ 0x00007A94) Error Interrupt Enable Register 70 */ + + struct + { + __IOM uint32_t FOORE : 32; /*!< [31..0] FRER Out Of Range Enable */ + } FWEIE70_b; + }; + + union + { + __IOM uint32_t FWEID70; /*!< (@ 0x00007A98) Error Interrupt Disable Register 70 */ + + struct + { + __IOM uint32_t FOORD : 32; /*!< [31..0] FRER Out Of Range Disable */ + } FWEID70_b; + }; + __IM uint32_t RESERVED272; + + union + { + __IOM uint32_t FWEIS71; /*!< (@ 0x00007AA0) Error Interrupt Status Register 71 */ + + struct + { + __IOM uint32_t FOORS : 32; /*!< [31..0] FRER Out Of Range Status */ + } FWEIS71_b; + }; + + union + { + __IOM uint32_t FWEIE71; /*!< (@ 0x00007AA4) Error Interrupt Enable Register 71 */ + + struct + { + __IOM uint32_t FOORE : 32; /*!< [31..0] FRER Out Of Range Enable */ + } FWEIE71_b; + }; + + union + { + __IOM uint32_t FWEID71; /*!< (@ 0x00007AA8) Error Interrupt Disable Register 71 */ + + struct + { + __IOM uint32_t FOORD : 32; /*!< [31..0] FRER Out Of Range Disable */ + } FWEID71_b; + }; + __IM uint32_t RESERVED273; + + union + { + __IOM uint32_t FWEIS72; /*!< (@ 0x00007AB0) Error Interrupt Status Register 72 */ + + struct + { + __IOM uint32_t FOORS : 32; /*!< [31..0] FRER Out Of Range Status */ + } FWEIS72_b; + }; + + union + { + __IOM uint32_t FWEIE72; /*!< (@ 0x00007AB4) Error Interrupt Enable Register 72 */ + + struct + { + __IOM uint32_t FOORE : 32; /*!< [31..0] FRER Out Of Range Enable */ + } FWEIE72_b; + }; + + union + { + __IOM uint32_t FWEID72; /*!< (@ 0x00007AB8) Error Interrupt Disable Register 72 */ + + struct + { + __IOM uint32_t FOORD : 32; /*!< [31..0] FRER Out Of Range Disable */ + } FWEID72_b; + }; + __IM uint32_t RESERVED274; + + union + { + __IOM uint32_t FWEIS73; /*!< (@ 0x00007AC0) Error Interrupt Status Register 73 */ + + struct + { + __IOM uint32_t FOORS : 32; /*!< [31..0] FRER Out Of Range Status */ + } FWEIS73_b; + }; + + union + { + __IOM uint32_t FWEIE73; /*!< (@ 0x00007AC4) Error Interrupt Enable Register 73 */ + + struct + { + __IOM uint32_t FOORE : 32; /*!< [31..0] FRER Out Of Range Enable */ + } FWEIE73_b; + }; + + union + { + __IOM uint32_t FWEID73; /*!< (@ 0x00007AC8) Error Interrupt Disable Register 73 */ + + struct + { + __IOM uint32_t FOORD : 32; /*!< [31..0] FRER Out Of Range Disable */ + } FWEID73_b; + }; + __IM uint32_t RESERVED275; + + union + { + __IOM uint32_t FWEIS80; /*!< (@ 0x00007AD0) Error Interrupt Status Register 80 */ + + struct + { + __IOM uint32_t TOS : 32; /*!< [31..0] Timeout Status */ + } FWEIS80_b; + }; + + union + { + __IOM uint32_t FWEIE80; /*!< (@ 0x00007AD4) Error Interrupt Enable Register 80 */ + + struct + { + __IOM uint32_t TOE : 32; /*!< [31..0] Timeout Enable */ + } FWEIE80_b; + }; + + union + { + __IOM uint32_t FWEID80; /*!< (@ 0x00007AD8) Error Interrupt Disable Register 80 */ + + struct + { + __IOM uint32_t TOD : 32; /*!< [31..0] Timeout Disable */ + } FWEID80_b; + }; + __IM uint32_t RESERVED276; + + union + { + __IOM uint32_t FWEIS81; /*!< (@ 0x00007AE0) Error Interrupt Status Register 81 */ + + struct + { + __IOM uint32_t TOS : 32; /*!< [31..0] Timeout Status */ + } FWEIS81_b; + }; + + union + { + __IOM uint32_t FWEIE81; /*!< (@ 0x00007AE4) Error Interrupt Enable Register 81 */ + + struct + { + __IOM uint32_t TOE : 32; /*!< [31..0] Timeout Enable */ + } FWEIE81_b; + }; + + union + { + __IOM uint32_t FWEID81; /*!< (@ 0x00007AE8) Error Interrupt Disable Register 81 */ + + struct + { + __IOM uint32_t TOD : 32; /*!< [31..0] Timeout Disable */ + } FWEID81_b; + }; + __IM uint32_t RESERVED277; + + union + { + __IOM uint32_t FWEIS82; /*!< (@ 0x00007AF0) Error Interrupt Status Register 82 */ + + struct + { + __IOM uint32_t TOS : 32; /*!< [31..0] Timeout Status */ + } FWEIS82_b; + }; + + union + { + __IOM uint32_t FWEIE82; /*!< (@ 0x00007AF4) Error Interrupt Enable Register 82 */ + + struct + { + __IOM uint32_t TOE : 32; /*!< [31..0] Timeout Enable */ + } FWEIE82_b; + }; + + union + { + __IOM uint32_t FWEID82; /*!< (@ 0x00007AF8) Error Interrupt Disable Register 82 */ + + struct + { + __IOM uint32_t TOD : 32; /*!< [31..0] Timeout Disable */ + } FWEID82_b; + }; + __IM uint32_t RESERVED278; + + union + { + __IOM uint32_t FWEIS83; /*!< (@ 0x00007B00) Error Interrupt Status Register 83 */ + + struct + { + __IOM uint32_t TOS : 32; /*!< [31..0] Timeout Status */ + } FWEIS83_b; + }; + + union + { + __IOM uint32_t FWEIE83; /*!< (@ 0x00007B04) Error Interrupt Enable Register 83 */ + + struct + { + __IOM uint32_t TOE : 32; /*!< [31..0] Timeout Enable */ + } FWEIE83_b; + }; + + union + { + __IOM uint32_t FWEID83; /*!< (@ 0x00007B08) Error Interrupt Disable Register 83 */ + + struct + { + __IOM uint32_t TOD : 32; /*!< [31..0] Timeout Disable */ + } FWEID83_b; + }; + __IM uint32_t RESERVED279[61]; + + union + { + __IOM uint32_t FWMIS0; /*!< (@ 0x00007C00) Monitoring Interrupt Status Register 0 */ + + struct + { + __IOM uint32_t LTHTFS : 1; /*!< [0..0] L3 Table Full Status */ + uint32_t : 1; + __IOM uint32_t MACTFS : 1; /*!< [2..2] MAC Table Full Status */ + __IOM uint32_t VLANTFS : 1; /*!< [3..3] VLAN Table Full Status */ + uint32_t : 13; + __IOM uint32_t MACADAS : 1; /*!< [17..17] MAC Address Deleted Aging Status */ + uint32_t : 14; + } FWMIS0_b; + }; + + union + { + __IOM uint32_t FWMIE0; /*!< (@ 0x00007C04) Monitoring Interrupt Enable Register 0 */ + + struct + { + __IOM uint32_t LTHTFE : 1; /*!< [0..0] L3 Table Full Enable */ + uint32_t : 1; + __IOM uint32_t MACTFE : 1; /*!< [2..2] MAC Table Full Enable */ + __IOM uint32_t VLANTFE : 1; /*!< [3..3] VLAN Table Full Enable */ + uint32_t : 13; + __IOM uint32_t MACADAE : 1; /*!< [17..17] MAC Address Deleted Aging Enable */ + uint32_t : 14; + } FWMIE0_b; + }; + + union + { + __IOM uint32_t FWMID0; /*!< (@ 0x00007C08) Monitoring Interrupt Disable Register 0 */ + + struct + { + __IOM uint32_t LTHTFD : 1; /*!< [0..0] L3 Table Full Disable */ + uint32_t : 1; + __IOM uint32_t MACTFD : 1; /*!< [2..2] MAC Table Full Disable */ + __IOM uint32_t VLANTFD : 1; /*!< [3..3] VLAN Table Full Disable */ + uint32_t : 13; + __IOM uint32_t MACADAD : 1; /*!< [17..17] MAC Address Deleted Aging Disable */ + uint32_t : 14; + } FWMID0_b; + }; +} R_MFWD_Type; /*!< Size = 31756 (0x7c0c) */ + +/* =========================================================================================================================== */ +/* ================ R_MIPI_DSI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DSI Link (R_MIPI_DSI) + */ + +typedef struct /*!< (@ 0x40346000) R_MIPI_DSI Structure */ +{ + union + { + __IM uint32_t ISR; /*!< (@ 0x00000000) Interrupt Status Register */ + + struct + { + __IM uint32_t SQ0 : 1; /*!< [0..0] Sequence Channel-0 Interrupt Flag */ + uint32_t : 3; + __IM uint32_t SQ1 : 1; /*!< [4..4] Sequence Channel-1 Interrupt Flag */ + uint32_t : 3; + __IM uint32_t VM : 1; /*!< [8..8] Video Mode Interrupt Flag */ + uint32_t : 3; + __IM uint32_t RCV : 1; /*!< [12..12] Receive Interrupt Flag */ + uint32_t : 3; + __IM uint32_t FERR : 1; /*!< [16..16] Fatal Error Interrupt Flag */ + uint32_t : 3; + __IM uint32_t PPI : 1; /*!< [20..20] PPI Interrupt Flag */ + uint32_t : 11; + } ISR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IM uint32_t LINKSR; /*!< (@ 0x00000010) Link Status Register */ + + struct + { + __IM uint32_t SQ0RUN : 1; /*!< [0..0] Sequence Channel-0 Running Flag */ + uint32_t : 3; + __IM uint32_t SQ1RUN : 1; /*!< [4..4] Sequence Channel-1 Running Flag */ + uint32_t : 3; + __IM uint32_t VRUN : 1; /*!< [8..8] Video Mode Operation Running Flag */ + uint32_t : 3; + __IM uint32_t HSBUSY : 1; /*!< [12..12] HS Operation Busy Flag */ + __IM uint32_t LPBUSY : 1; /*!< [13..13] LP Operation Busy Flag */ + uint32_t : 18; + } LINKSR_b; + }; + __IM uint32_t RESERVED1[59]; + + union + { + __IOM uint32_t TXSETR; /*!< (@ 0x00000100) Transmit Set Register */ + + struct + { + __IOM uint32_t NUMLANE : 2; /*!< [1..0] Number of Lane */ + uint32_t : 6; + __IOM uint32_t CLEN : 1; /*!< [8..8] Clock Lane Enable */ + __IOM uint32_t DLEN : 1; /*!< [9..9] Data Lane Enable */ + uint32_t : 22; + } TXSETR_b; + }; + + union + { + __IOM uint32_t HSCLKSETR; /*!< (@ 0x00000104) HS Clock Set Register */ + + struct + { + __IOM uint32_t HSCLST : 1; /*!< [0..0] HS Clock Start */ + __IOM uint32_t HSCLMD : 1; /*!< [1..1] HS Clock Running Mode */ + uint32_t : 30; + } HSCLKSETR_b; + }; + + union + { + __IOM uint32_t ULPSSETR; /*!< (@ 0x00000108) ULPS Set Register */ + + struct + { + __IOM uint32_t WKUP : 8; /*!< [7..0] ULPS Wakeup Period */ + uint32_t : 24; + } ULPSSETR_b; + }; + + union + { + __OM uint32_t ULPSCR; /*!< (@ 0x0000010C) ULPS Control Register */ + + struct + { + uint32_t : 24; + __OM uint32_t CLENT : 1; /*!< [24..24] CL ULPS Enter */ + __OM uint32_t CLEXIT : 1; /*!< [25..25] CL ULPS Exit */ + uint32_t : 2; + __OM uint32_t DLENT : 1; /*!< [28..28] DL ULPS Enter */ + __OM uint32_t DLEXIT : 1; /*!< [29..29] DL ULPS Exit */ + uint32_t : 2; + } ULPSCR_b; + }; + + union + { + __IOM uint32_t RSTCR; /*!< (@ 0x00000110) Reset Control Register */ + + struct + { + __IOM uint32_t SWRST : 1; /*!< [0..0] Software Reset */ + uint32_t : 15; + __IOM uint32_t FTXSTP : 1; /*!< [16..16] Force Tx Stop Mode */ + uint32_t : 15; + } RSTCR_b; + }; + + union + { + __IM uint32_t RSTSR; /*!< (@ 0x00000114) Reset Status Register */ + + struct + { + __IM uint32_t RSTHS : 1; /*!< [0..0] HS Software Reset Status */ + __IM uint32_t RSTLP : 1; /*!< [1..1] LP Software Reset Status */ + __IM uint32_t RSTAPB : 1; /*!< [2..2] APB Software Reset Status */ + __IM uint32_t RSTAXI : 1; /*!< [3..3] AXI Software Reset Status */ + __IM uint32_t RSTV : 1; /*!< [4..4] Video Software Reset Status */ + uint32_t : 3; + __IM uint32_t DL0STP : 1; /*!< [8..8] Data Lane-0 Stop Status */ + __IM uint32_t DL1STP : 1; /*!< [9..9] Data Lane-1 Stop Status */ + uint32_t : 5; + __IM uint32_t DL0DIR : 1; /*!< [15..15] Data Lane-0 Direction */ + uint32_t : 16; + } RSTSR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t DSISETR; /*!< (@ 0x00000120) DSI Set Register */ + + struct + { + __IOM uint32_t MRPSZ : 16; /*!< [15..0] Maximum Return Packet Size */ + __IOM uint32_t ECCEN : 1; /*!< [16..16] ECC Check Enable */ + uint32_t : 3; + __IOM uint32_t VC0CRCEN : 1; /*!< [20..20] VC-0 CRC Check Enable */ + __IOM uint32_t VC1CRCEN : 1; /*!< [21..21] VC-1 CRC Check Enable */ + __IOM uint32_t VC2CRCEN : 1; /*!< [22..22] VC-2 CRC Check Enable */ + __IOM uint32_t VC3CRCEN : 1; /*!< [23..23] VC-3 CRC Check Enable */ + uint32_t : 5; + __IOM uint32_t SCREN : 1; /*!< [29..29] Data Scramble Enable */ + __IOM uint32_t EXTEMD : 1; /*!< [30..30] External Tearing Effect Detection Sense Select */ + __IOM uint32_t EOTPEN : 1; /*!< [31..31] HS Transfer EoTp Enable */ + } DSISETR_b; + }; + __IM uint32_t RESERVED3[15]; + + union + { + __IOM uint32_t TXPPD0R; /*!< (@ 0x00000160) Transmit Packet Payload Data 0 Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Payload Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Payload Data 1 */ + __IOM uint32_t DATA2 : 8; /*!< [23..16] Payload Data 2 */ + __IOM uint32_t DATA3 : 8; /*!< [31..24] Payload Data 3 */ + } TXPPD0R_b; + }; + + union + { + __IOM uint32_t TXPPD1R; /*!< (@ 0x00000164) Transmit Packet Payload Data 1 Register */ + + struct + { + __IOM uint32_t DATA4 : 8; /*!< [7..0] Payload Data 4 */ + __IOM uint32_t DATA5 : 8; /*!< [15..8] Payload Data 5 */ + __IOM uint32_t DATA6 : 8; /*!< [23..16] Payload Data 6 */ + __IOM uint32_t DATA7 : 8; /*!< [31..24] Payload Data 7 */ + } TXPPD1R_b; + }; + + union + { + __IOM uint32_t TXPPD2R; /*!< (@ 0x00000168) Transmit Packet Payload Data 2 Register */ + + struct + { + __IOM uint32_t DATA8 : 8; /*!< [7..0] Payload Data 8 */ + __IOM uint32_t DATA9 : 8; /*!< [15..8] Payload Data 9 */ + __IOM uint32_t DATA10 : 8; /*!< [23..16] Payload Data 10 */ + __IOM uint32_t DATA11 : 8; /*!< [31..24] Payload Data 11 */ + } TXPPD2R_b; + }; + + union + { + __IOM uint32_t TXPPD3R; /*!< (@ 0x0000016C) Transmit Packet Payload Data 3 Register */ + + struct + { + __IOM uint32_t DATA12 : 8; /*!< [7..0] Payload Data 12 */ + __IOM uint32_t DATA13 : 8; /*!< [15..8] Payload Data 13 */ + __IOM uint32_t DATA14 : 8; /*!< [23..16] Payload Data 14 */ + __IOM uint32_t DATA15 : 8; /*!< [31..24] Payload Data 15 */ + } TXPPD3R_b; + }; + __IM uint32_t RESERVED4[36]; + + union + { + __IM uint32_t RXSR; /*!< (@ 0x00000200) Receive Status Register */ + + struct + { + __IM uint32_t BTAREND : 1; /*!< [0..0] BTA Request End Interrupt Flag */ + __IM uint32_t LRXHTO : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Flag */ + __IM uint32_t TATO : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Flag */ + uint32_t : 5; + __IM uint32_t RXRESP : 1; /*!< [8..8] Response Packet Receive Interrupt Flag */ + uint32_t : 1; + __IM uint32_t RXEOTP : 1; /*!< [10..10] EoTp Receive Interrupt Flag */ + uint32_t : 2; + __IM uint32_t RXTE : 1; /*!< [13..13] Tearing Effect Trigger Receive Interrupt Flag */ + __IM uint32_t RXACK : 1; /*!< [14..14] ACK Trigger Receive Interrupt Flag */ + __IM uint32_t EXTEDET : 1; /*!< [15..15] External Tearing Effect Detect Interrupt Flag */ + __IM uint32_t MLFERR : 1; /*!< [16..16] Malform Error Interrupt Flag */ + __IM uint32_t ECCERRM : 1; /*!< [17..17] Multi Bit ECC Error Interrupt Flag */ + __IM uint32_t UNEXERR : 1; /*!< [18..18] Unexpected Packet Error Interrupt Flag */ + uint32_t : 1; + __IM uint32_t WCERR : 1; /*!< [20..20] Word Count Error Interrupt Flag */ + __IM uint32_t CRCERR : 1; /*!< [21..21] CRC Error Interrupt Flag */ + __IM uint32_t IBERR : 1; /*!< [22..22] Internal Bus Error Interrupt Flag */ + __IM uint32_t RXOVFERR : 1; /*!< [23..23] Receive Buffer Overflow Error Interrupt Flag */ + __IM uint32_t PRTOERR : 1; /*!< [24..24] Peripheral Response Timeout Error Interrupt Flag */ + __IM uint32_t NORESERR : 1; /*!< [25..25] No Response Error Interrupt Flag */ + __IM uint32_t RSIZEERR : 1; /*!< [26..26] Return Packet Size Error Interrupt Flag */ + uint32_t : 1; + __IM uint32_t ECCERRS : 1; /*!< [28..28] Single Bit ECC Error Interrupt Flag */ + uint32_t : 1; + __IM uint32_t RXAKE : 1; /*!< [30..30] Acknowledge and Error Report Receive Interrupt Flag */ + uint32_t : 1; + } RXSR_b; + }; + + union + { + __IOM uint32_t RXSCR; /*!< (@ 0x00000204) Receive Status Clear Register */ + + struct + { + __IOM uint32_t BTAREND : 1; /*!< [0..0] BTA Request End Interrupt Flag Clear */ + __IOM uint32_t LRXHTO : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Flag Clear */ + __IOM uint32_t TATO : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Flag Clear */ + uint32_t : 5; + __IOM uint32_t RXRESP : 1; /*!< [8..8] Response Packet Receive Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t RXEOTP : 1; /*!< [10..10] EoTp Receive Interrupt Flag Clear */ + uint32_t : 2; + __IOM uint32_t RXTE : 1; /*!< [13..13] Tearing Effect Trigger Receive Interrupt Flag Clear */ + __IOM uint32_t RXACK : 1; /*!< [14..14] ACK Trigger Receive Interrupt Flag Clear */ + __IOM uint32_t EXTEDET : 1; /*!< [15..15] External Tearing Effect Detect Interrupt Flag Clear */ + __IOM uint32_t MLFERR : 1; /*!< [16..16] Malform Error Interrupt Flag Clear */ + __IOM uint32_t ECCERRM : 1; /*!< [17..17] Multi Bit ECC Error Interrupt Flag Clear */ + __IOM uint32_t UNEXERR : 1; /*!< [18..18] Unexpected Packet Error Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t WCERR : 1; /*!< [20..20] Word Count Error Interrupt Flag Clear */ + __IOM uint32_t CRCERR : 1; /*!< [21..21] CRC Error Interrupt Flag Clear */ + __IOM uint32_t IBERR : 1; /*!< [22..22] Internal Bus Error Interrupt Flag Clear */ + __IOM uint32_t RXOVFERR : 1; /*!< [23..23] Receive Buffer Overflow Error Interrupt Flag Clear */ + __IOM uint32_t PRTOERR : 1; /*!< [24..24] Peripheral Response Timeout Error Interrupt Flag Clear */ + __IOM uint32_t NORESERR : 1; /*!< [25..25] No Response Error Interrupt Flag Clear */ + __IOM uint32_t RSIZEERR : 1; /*!< [26..26] Return Packet Size Error Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t ECCERRS : 1; /*!< [28..28] Single Bit ECC Error Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t RXAKE : 1; /*!< [30..30] Acknowledge and Error Report Receive Interrupt Flag + * Clear */ + uint32_t : 1; + } RXSCR_b; + }; + + union + { + __IOM uint32_t RXIER; /*!< (@ 0x00000208) Receive Interrupt Enable Register */ + + struct + { + __IOM uint32_t BTAREND : 1; /*!< [0..0] BTA Request End Interrupt Enable */ + __IOM uint32_t LRXHTO : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Enable */ + __IOM uint32_t TATO : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Enable */ + uint32_t : 5; + __IOM uint32_t RXRESP : 1; /*!< [8..8] Response Packet Receive Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t RXEOTP : 1; /*!< [10..10] EoTp Receive Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t RXTE : 1; /*!< [13..13] Tearing Effect Trigger Receive Interrupt Enable */ + __IOM uint32_t RXACK : 1; /*!< [14..14] ACK Trigger Receive Interrupt Enable */ + __IOM uint32_t EXTEDET : 1; /*!< [15..15] External Tearing Effect Detect Interrupt Enable */ + __IOM uint32_t MLFERR : 1; /*!< [16..16] Malform Error Interrupt Enable */ + __IOM uint32_t ECCERRM : 1; /*!< [17..17] Multi Bit ECC Error Interrupt Enable */ + __IOM uint32_t UNEXERR : 1; /*!< [18..18] Unexpected Packet Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t WCERR : 1; /*!< [20..20] Word Count Error Interrupt Enable */ + __IOM uint32_t CRCERR : 1; /*!< [21..21] CRC Error Interrupt Enable */ + __IOM uint32_t IBERR : 1; /*!< [22..22] Internal Bus Error Interrupt Enable */ + __IOM uint32_t RXOVFERR : 1; /*!< [23..23] Receive Buffer Overflow Error Interrupt Enable */ + __IOM uint32_t PRTOERR : 1; /*!< [24..24] Peripheral Response Timeout Error Interrupt Enable */ + __IOM uint32_t NORESERR : 1; /*!< [25..25] No Response Error Interrupt Enable */ + __IOM uint32_t RSIZEERR : 1; /*!< [26..26] Return Packet Size Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t ECCERRS : 1; /*!< [28..28] Single Bit ECC Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t RXAKE : 1; /*!< [30..30] Acknowledge and Error Report Receive Interrupt Enable */ + uint32_t : 1; + } RXIER_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t PRESPTOBTASETR; /*!< (@ 0x00000210) Peripheral Response Timeout BTA Set Register */ + + struct + { + __IOM uint32_t PRTBTA : 32; /*!< [31..0] Peripheral Response Timeout Count */ + } PRESPTOBTASETR_b; + }; + + union + { + __IOM uint32_t PRESPTOLPSETR; /*!< (@ 0x00000214) Peripheral Response Timeout LP Set Register */ + + struct + { + __IOM uint32_t LPWTO : 16; /*!< [15..0] LPDT WRITE Request Timeout */ + __IOM uint32_t LPRTO : 16; /*!< [31..16] LPDT READ Request Timeout */ + } PRESPTOLPSETR_b; + }; + + union + { + __IOM uint32_t PRESPTOHSSETR; /*!< (@ 0x00000218) Peripheral Response Timeout HS Set Register */ + + struct + { + __IOM uint32_t HSWTO : 16; /*!< [15..0] HS WRITE Request Timeout */ + __IOM uint32_t HSRTO : 16; /*!< [31..16] HS READ Request Timeout */ + } PRESPTOHSSETR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IM uint32_t AKEPLATIR; /*!< (@ 0x00000220) Acknowledge and Error Report Packet Parameter + * Latest Info Register */ + + struct + { + __IM uint32_t EREP : 16; /*!< [15..0] Error Report */ + __IM uint32_t VC : 4; /*!< [19..16] Virtual Channel ID */ + uint32_t : 12; + } AKEPLATIR_b; + }; + + union + { + __IM uint32_t AKEPACMSR; /*!< (@ 0x00000224) Acknowledge and Error Report Packet Parameter + * Accumulate Status Register */ + + struct + { + __IM uint32_t AEREP : 16; /*!< [15..0] Accumulated Error Report */ + __IM uint32_t AVC : 4; /*!< [19..16] Virtual Channel ID */ + uint32_t : 12; + } AKEPACMSR_b; + }; + + union + { + __IOM uint32_t AKEPSCR; /*!< (@ 0x00000228) Acknowledge and Error Report Packet Parameter + * Status Clear Register */ + + struct + { + __IOM uint32_t AEREP : 16; /*!< [15..0] Accumulated Error Report Clear */ + __IM uint32_t AVC : 4; /*!< [19..16] Virtual Channel ID */ + uint32_t : 12; + } AKEPSCR_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IM uint32_t RXRSSR; /*!< (@ 0x00000230) Receive Result Saved Status Register */ + + struct + { + __IM uint32_t SLT0VLD : 1; /*!< [0..0] Slot-0 Valid Flag */ + __IM uint32_t SLT1VLD : 1; /*!< [1..1] Slot-1 Valid Flag */ + __IM uint32_t SLT2VLD : 1; /*!< [2..2] Slot-2 Valid Flag */ + __IM uint32_t SLT3VLD : 1; /*!< [3..3] Slot-3 Valid Flag */ + uint32_t : 28; + } RXRSSR_b; + }; + + union + { + __IOM uint32_t RXRSSCR; /*!< (@ 0x00000234) Receive Result Saved Status Clear Register */ + + struct + { + __IOM uint32_t SLT0VLD : 1; /*!< [0..0] Slot-0 Valid Flag Clear */ + __IOM uint32_t SLT1VLD : 1; /*!< [1..1] Slot-1 Valid Flag Clear */ + __IOM uint32_t SLT2VLD : 1; /*!< [2..2] Slot-2 Valid Flag Clear */ + __IOM uint32_t SLT3VLD : 1; /*!< [3..3] Slot-3 Valid Flag Clear */ + uint32_t : 28; + } RXRSSCR_b; + }; + + union + { + __IM uint32_t RXRINFOOWSR; /*!< (@ 0x00000238) Receive Result Info Overwrite Status Register */ + + struct + { + __IM uint32_t SL0OW : 1; /*!< [0..0] Slot-0 Information Overwrite Flag */ + __IM uint32_t SL1OW : 1; /*!< [1..1] Slot-1 Information Overwrite Flag */ + __IM uint32_t SL2OW : 1; /*!< [2..2] Slot-2 Information Overwrite Flag */ + __IM uint32_t SL3OW : 1; /*!< [3..3] Slot-3 Information Overwrite Flag */ + uint32_t : 28; + } RXRINFOOWSR_b; + }; + + union + { + __IOM uint32_t RXRINFOOWSCR; /*!< (@ 0x0000023C) Receive Result Info Overwrite Status Clear Register */ + + struct + { + __IOM uint32_t SL0OW : 1; /*!< [0..0] Slot-0 Information Overwrite Flag Clear */ + __IOM uint32_t SL1OW : 1; /*!< [1..1] Slot-1 Information Overwrite Flag Clear */ + __IOM uint32_t SL2OW : 1; /*!< [2..2] Slot-2 Information Overwrite Flag Clear */ + __IOM uint32_t SL3OW : 1; /*!< [3..3] Slot-3 Information Overwrite Flag Clear */ + uint32_t : 28; + } RXRINFOOWSCR_b; + }; + + union + { + union + { + __IM uint32_t RXRSS0R; /*!< (@ 0x00000240) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IM uint32_t FMT : 1; /*!< [24..24] Packet Format */ + __IM uint32_t RXSUC : 1; /*!< [25..25] Receive Success */ + __IM uint32_t RXFERR : 1; /*!< [26..26] Fatal Error */ + __IM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail */ + __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail */ + __IM uint32_t RXCERR : 1; /*!< [29..29] Receive Correctable Error */ + __IM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet */ + __IM uint32_t INFOOW : 1; /*!< [31..31] Information Overwrite */ + } RXRSS0R_b; + }; + + struct + { + union + { + union + { + __IM uint16_t RXRSS0R_L; /*!< (@ 0x00000240) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } RXRSS0R_L_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS0R_LL; /*!< (@ 0x00000240) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } RXRSS0R_LL_b; + }; + + union + { + __IM uint8_t RXRSS0R_LH; /*!< (@ 0x00000241) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } RXRSS0R_LH_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RXRSS0R_H; /*!< (@ 0x00000242) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IM uint16_t FMT : 1; /*!< [8..8] Packet Format */ + __IM uint16_t RXSUC : 1; /*!< [9..9] Receive Success */ + __IM uint16_t RXFERR : 1; /*!< [10..10] Fatal Error */ + __IM uint16_t RXFAIL : 1; /*!< [11..11] Receive Fail */ + __IM uint16_t RXPFAIL : 1; /*!< [12..12] Receive Packet Data Fail */ + __IM uint16_t RXCERR : 1; /*!< [13..13] Receive Correctable Error */ + __IM uint16_t RXAKE : 1; /*!< [14..14] Receive Acknowledge and Error Report Packet */ + __IM uint16_t INFOOW : 1; /*!< [15..15] Information Overwrite */ + } RXRSS0R_H_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS0R_HL; /*!< (@ 0x00000242) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } RXRSS0R_HL_b; + }; + + union + { + __IM uint8_t RXRSS0R_HH; /*!< (@ 0x00000243) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint8_t FMT : 1; /*!< [0..0] Packet Format */ + __IM uint8_t RXSUC : 1; /*!< [1..1] Receive Success */ + __IM uint8_t RXFERR : 1; /*!< [2..2] Fatal Error */ + __IM uint8_t RXFAIL : 1; /*!< [3..3] Receive Fail */ + __IM uint8_t RXPFAIL : 1; /*!< [4..4] Receive Packet Data Fail */ + __IM uint8_t RXCERR : 1; /*!< [5..5] Receive Correctable Error */ + __IM uint8_t RXAKE : 1; /*!< [6..6] Receive Acknowledge and Error Report Packet */ + __IM uint8_t INFOOW : 1; /*!< [7..7] Information Overwrite */ + } RXRSS0R_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IM uint32_t RXRSS1R; /*!< (@ 0x00000244) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IM uint32_t FMT : 1; /*!< [24..24] Packet Format */ + __IM uint32_t RXSUC : 1; /*!< [25..25] Receive Success */ + __IM uint32_t RXFERR : 1; /*!< [26..26] Fatal Error */ + __IM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail */ + __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail */ + __IM uint32_t RXCERR : 1; /*!< [29..29] Receive Correctable Error */ + __IM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet */ + __IM uint32_t INFOOW : 1; /*!< [31..31] Information Overwrite */ + } RXRSS1R_b; + }; + + struct + { + union + { + union + { + __IM uint16_t RXRSS1R_L; /*!< (@ 0x00000244) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } RXRSS1R_L_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS1R_LL; /*!< (@ 0x00000244) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } RXRSS1R_LL_b; + }; + + union + { + __IM uint8_t RXRSS1R_LH; /*!< (@ 0x00000245) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } RXRSS1R_LH_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RXRSS1R_H; /*!< (@ 0x00000246) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IM uint16_t FMT : 1; /*!< [8..8] Packet Format */ + __IM uint16_t RXSUC : 1; /*!< [9..9] Receive Success */ + __IM uint16_t RXFERR : 1; /*!< [10..10] Fatal Error */ + __IM uint16_t RXFAIL : 1; /*!< [11..11] Receive Fail */ + __IM uint16_t RXPFAIL : 1; /*!< [12..12] Receive Packet Data Fail */ + __IM uint16_t RXCERR : 1; /*!< [13..13] Receive Correctable Error */ + __IM uint16_t RXAKE : 1; /*!< [14..14] Receive Acknowledge and Error Report Packet */ + __IM uint16_t INFOOW : 1; /*!< [15..15] Information Overwrite */ + } RXRSS1R_H_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS1R_HL; /*!< (@ 0x00000246) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } RXRSS1R_HL_b; + }; + + union + { + __IM uint8_t RXRSS1R_HH; /*!< (@ 0x00000247) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint8_t FMT : 1; /*!< [0..0] Packet Format */ + __IM uint8_t RXSUC : 1; /*!< [1..1] Receive Success */ + __IM uint8_t RXFERR : 1; /*!< [2..2] Fatal Error */ + __IM uint8_t RXFAIL : 1; /*!< [3..3] Receive Fail */ + __IM uint8_t RXPFAIL : 1; /*!< [4..4] Receive Packet Data Fail */ + __IM uint8_t RXCERR : 1; /*!< [5..5] Receive Correctable Error */ + __IM uint8_t RXAKE : 1; /*!< [6..6] Receive Acknowledge and Error Report Packet */ + __IM uint8_t INFOOW : 1; /*!< [7..7] Information Overwrite */ + } RXRSS1R_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IM uint32_t RXRSS2R; /*!< (@ 0x00000248) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IM uint32_t FMT : 1; /*!< [24..24] Packet Format */ + __IM uint32_t RXSUC : 1; /*!< [25..25] Receive Success */ + __IM uint32_t RXFERR : 1; /*!< [26..26] Fatal Error */ + __IM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail */ + __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail */ + __IM uint32_t RXCERR : 1; /*!< [29..29] Receive Correctable Error */ + __IM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet */ + __IM uint32_t INFOOW : 1; /*!< [31..31] Information Overwrite */ + } RXRSS2R_b; + }; + + struct + { + union + { + union + { + __IM uint16_t RXRSS2R_L; /*!< (@ 0x00000248) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } RXRSS2R_L_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS2R_LL; /*!< (@ 0x00000248) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } RXRSS2R_LL_b; + }; + + union + { + __IM uint8_t RXRSS2R_LH; /*!< (@ 0x00000249) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } RXRSS2R_LH_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RXRSS2R_H; /*!< (@ 0x0000024A) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IM uint16_t FMT : 1; /*!< [8..8] Packet Format */ + __IM uint16_t RXSUC : 1; /*!< [9..9] Receive Success */ + __IM uint16_t RXFERR : 1; /*!< [10..10] Fatal Error */ + __IM uint16_t RXFAIL : 1; /*!< [11..11] Receive Fail */ + __IM uint16_t RXPFAIL : 1; /*!< [12..12] Receive Packet Data Fail */ + __IM uint16_t RXCERR : 1; /*!< [13..13] Receive Correctable Error */ + __IM uint16_t RXAKE : 1; /*!< [14..14] Receive Acknowledge and Error Report Packet */ + __IM uint16_t INFOOW : 1; /*!< [15..15] Information Overwrite */ + } RXRSS2R_H_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS2R_HL; /*!< (@ 0x0000024A) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } RXRSS2R_HL_b; + }; + + union + { + __IM uint8_t RXRSS2R_HH; /*!< (@ 0x0000024B) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint8_t FMT : 1; /*!< [0..0] Packet Format */ + __IM uint8_t RXSUC : 1; /*!< [1..1] Receive Success */ + __IM uint8_t RXFERR : 1; /*!< [2..2] Fatal Error */ + __IM uint8_t RXFAIL : 1; /*!< [3..3] Receive Fail */ + __IM uint8_t RXPFAIL : 1; /*!< [4..4] Receive Packet Data Fail */ + __IM uint8_t RXCERR : 1; /*!< [5..5] Receive Correctable Error */ + __IM uint8_t RXAKE : 1; /*!< [6..6] Receive Acknowledge and Error Report Packet */ + __IM uint8_t INFOOW : 1; /*!< [7..7] Information Overwrite */ + } RXRSS2R_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IM uint32_t RXRSS3R; /*!< (@ 0x0000024C) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IM uint32_t FMT : 1; /*!< [24..24] Packet Format */ + __IM uint32_t RXSUC : 1; /*!< [25..25] Receive Success */ + __IM uint32_t RXFERR : 1; /*!< [26..26] Fatal Error */ + __IM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail */ + __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail */ + __IM uint32_t RXCERR : 1; /*!< [29..29] Receive Correctable Error */ + __IM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet */ + __IM uint32_t INFOOW : 1; /*!< [31..31] Information Overwrite */ + } RXRSS3R_b; + }; + + struct + { + union + { + union + { + __IM uint16_t RXRSS3R_L; /*!< (@ 0x0000024C) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } RXRSS3R_L_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS3R_LL; /*!< (@ 0x0000024C) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } RXRSS3R_LL_b; + }; + + union + { + __IM uint8_t RXRSS3R_LH; /*!< (@ 0x0000024D) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } RXRSS3R_LH_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RXRSS3R_H; /*!< (@ 0x0000024E) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IM uint16_t FMT : 1; /*!< [8..8] Packet Format */ + __IM uint16_t RXSUC : 1; /*!< [9..9] Receive Success */ + __IM uint16_t RXFERR : 1; /*!< [10..10] Fatal Error */ + __IM uint16_t RXFAIL : 1; /*!< [11..11] Receive Fail */ + __IM uint16_t RXPFAIL : 1; /*!< [12..12] Receive Packet Data Fail */ + __IM uint16_t RXCERR : 1; /*!< [13..13] Receive Correctable Error */ + __IM uint16_t RXAKE : 1; /*!< [14..14] Receive Acknowledge and Error Report Packet */ + __IM uint16_t INFOOW : 1; /*!< [15..15] Information Overwrite */ + } RXRSS3R_H_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS3R_HL; /*!< (@ 0x0000024E) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } RXRSS3R_HL_b; + }; + + union + { + __IM uint8_t RXRSS3R_HH; /*!< (@ 0x0000024F) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint8_t FMT : 1; /*!< [0..0] Packet Format */ + __IM uint8_t RXSUC : 1; /*!< [1..1] Receive Success */ + __IM uint8_t RXFERR : 1; /*!< [2..2] Fatal Error */ + __IM uint8_t RXFAIL : 1; /*!< [3..3] Receive Fail */ + __IM uint8_t RXPFAIL : 1; /*!< [4..4] Receive Packet Data Fail */ + __IM uint8_t RXCERR : 1; /*!< [5..5] Receive Correctable Error */ + __IM uint8_t RXAKE : 1; /*!< [6..6] Receive Acknowledge and Error Report Packet */ + __IM uint8_t INFOOW : 1; /*!< [7..7] Information Overwrite */ + } RXRSS3R_HH_b; + }; + }; + }; + }; + }; + __IM uint32_t RESERVED8[28]; + + union + { + __IM uint32_t RXPPD0R; /*!< (@ 0x000002C0) Receive Packet Payload Data 0 Register */ + + struct + { + __IM uint32_t DATA0 : 8; /*!< [7..0] Payload Data 0 */ + __IM uint32_t DATA1 : 8; /*!< [15..8] Payload Data 1 */ + __IM uint32_t DATA2 : 8; /*!< [23..16] Payload Data 2 */ + __IM uint32_t DATA3 : 8; /*!< [31..24] Payload Data 3 */ + } RXPPD0R_b; + }; + + union + { + __IM uint32_t RXPPD1R; /*!< (@ 0x000002C4) Receive Packet Payload Data 1 Register */ + + struct + { + __IM uint32_t DATA4 : 8; /*!< [7..0] Payload Data 0 */ + __IM uint32_t DATA5 : 8; /*!< [15..8] Payload Data 1 */ + __IM uint32_t DATA6 : 8; /*!< [23..16] Payload Data 2 */ + __IM uint32_t DATA7 : 8; /*!< [31..24] Payload Data 3 */ + } RXPPD1R_b; + }; + + union + { + __IM uint32_t RXPPD2R; /*!< (@ 0x000002C8) Receive Packet Payload Data 2 Register */ + + struct + { + __IM uint32_t DATA8 : 8; /*!< [7..0] Payload Data 8 */ + __IM uint32_t DATA9 : 8; /*!< [15..8] Payload Data 9 */ + __IM uint32_t DATA10 : 8; /*!< [23..16] Payload Data 10 */ + __IM uint32_t DATA11 : 8; /*!< [31..24] Payload Data 11 */ + } RXPPD2R_b; + }; + + union + { + __IM uint32_t RXPPD3R; /*!< (@ 0x000002CC) Receive Packet Payload Data 3 Register */ + + struct + { + __IM uint32_t DATA12 : 8; /*!< [7..0] Payload Data 12 */ + __IM uint32_t DATA13 : 8; /*!< [15..8] Payload Data 13 */ + __IM uint32_t DATA14 : 8; /*!< [23..16] Payload Data 14 */ + __IM uint32_t DATA15 : 8; /*!< [31..24] Payload Data 15 */ + } RXPPD3R_b; + }; + __IM uint32_t RESERVED9[4]; + + union + { + __IOM uint32_t HSTXTOSETR; /*!< (@ 0x000002E0) HS TX Timeout Set Register */ + + struct + { + __IOM uint32_t HTXTO : 32; /*!< [31..0] HS TX Timeout Count */ + } HSTXTOSETR_b; + }; + + union + { + __IOM uint32_t LRXHTOSETR; /*!< (@ 0x000002E4) LRX-H Timeout Set Register */ + + struct + { + __IOM uint32_t LRXHTO : 32; /*!< [31..0] LP-RX Host Processor Timeout */ + } LRXHTOSETR_b; + }; + + union + { + __IOM uint32_t TATOSETR; /*!< (@ 0x000002E8) TA Timeout Set Register */ + + struct + { + __IOM uint32_t TATO : 32; /*!< [31..0] Turnaround Acknowledge Timeout */ + } TATOSETR_b; + }; + __IM uint32_t RESERVED10[5]; + + union + { + __IM uint32_t FERRSR; /*!< (@ 0x00000300) Fatal Error Status Register */ + + struct + { + __IM uint32_t HTXTO : 1; /*!< [0..0] HS TX Timeout Interrupt Flag */ + __IM uint32_t LRXHTO : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Flag */ + __IM uint32_t TATO : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Flag */ + uint32_t : 13; + __IM uint32_t ESCENT : 1; /*!< [16..16] Escape mode Entry Error Interrupt Flag */ + __IM uint32_t SYNCESC : 1; /*!< [17..17] LPDT Sync Error Interrupt Flag */ + __IM uint32_t CTRL : 1; /*!< [18..18] Control Error Interrupt Flag */ + __IM uint32_t CLP0 : 1; /*!< [19..19] LP0 Contention Error Interrupt Flag */ + __IM uint32_t CLP1 : 1; /*!< [20..20] LP1 Contention Error Interrupt Flag */ + uint32_t : 6; + __IM uint32_t CLP0S : 1; /*!< [27..27] LP0 Contention Error Status */ + __IM uint32_t CLP1S : 1; /*!< [28..28] LP1 Contention Error Status */ + uint32_t : 3; + } FERRSR_b; + }; + + union + { + __IOM uint32_t FERRSCR; /*!< (@ 0x00000304) Fatal Error Status Clear Register */ + + struct + { + __IOM uint32_t HTXTO : 1; /*!< [0..0] HS TX Timeout Interrupt Flag Clear */ + __IOM uint32_t LRXHTO : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Flag Clear */ + __IOM uint32_t TATO : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Flag Clear */ + uint32_t : 13; + __IOM uint32_t ESCENT : 1; /*!< [16..16] Escape mode Entry Error Interrupt Flag Clear */ + __IOM uint32_t SYNCESC : 1; /*!< [17..17] LPDT Sync Error Interrupt Flag Clear */ + __IOM uint32_t CTRL : 1; /*!< [18..18] Control Error Interrupt Flag Clear */ + __IOM uint32_t CLP0 : 1; /*!< [19..19] LP0 Contention Error Interrupt Flag Clear */ + __IOM uint32_t CLP1 : 1; /*!< [20..20] LP1 Contention Error Interrupt Flag Clear */ + uint32_t : 11; + } FERRSCR_b; + }; + + union + { + __IOM uint32_t FERRIER; /*!< (@ 0x00000308) Fatal Error Interrupt Enable Register */ + + struct + { + __IOM uint32_t HTXTO : 1; /*!< [0..0] HS TX Timeout Interrupt Enable */ + __IOM uint32_t LRXHTO : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Enable */ + __IOM uint32_t TATO : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Enable */ + uint32_t : 13; + __IOM uint32_t ESCENT : 1; /*!< [16..16] Escape mode Entry Error Interrupt Enable */ + __IOM uint32_t SYNCESC : 1; /*!< [17..17] LPDT Sync Error Interrupt Enable */ + __IOM uint32_t CTRL : 1; /*!< [18..18] Control Error Interrupt Enable */ + __IOM uint32_t CLP0 : 1; /*!< [19..19] LP0 Contention Error Interrupt Enable */ + __IOM uint32_t CLP1 : 1; /*!< [20..20] LP1 Contention Error Interrupt Enable */ + uint32_t : 11; + } FERRIER_b; + }; + __IM uint32_t RESERVED11[2]; + + union + { + __IOM uint32_t CLSTPTSETR; /*!< (@ 0x00000314) Clock Lane Stop Time Set Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t CLKSTPT : 10; /*!< [11..2] Clock Stop Time */ + uint32_t : 4; + __IOM uint32_t CLKBFHT : 8; /*!< [23..16] Clock Beforehand Time */ + __IOM uint32_t CLKKPT : 8; /*!< [31..24] Clock Keep Time */ + } CLSTPTSETR_b; + }; + + union + { + __IOM uint32_t LPTRNSTSETR; /*!< (@ 0x00000318) LP Transition Time Set Register */ + + struct + { + __IOM uint32_t GOLPBKT : 10; /*!< [9..0] Go LP and Back Time */ + uint32_t : 22; + } LPTRNSTSETR_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IM uint32_t PLSR; /*!< (@ 0x00000320) Physical Lane Status Register */ + + struct + { + __IM uint32_t CLUAN : 1; /*!< [0..0] Clock Lane UlpsActiveNot Status */ + __IM uint32_t CLSTP : 1; /*!< [1..1] Clock Lane Stop Status */ + __IM uint32_t DL0RLE : 1; /*!< [2..2] Data Lane-0 RxLpdtEsc Status */ + __IM uint32_t DL0RUE : 1; /*!< [3..3] Data Lane-0 RxUlpsEsc Status */ + __IM uint32_t DL0UAN : 1; /*!< [4..4] Data Lane-0 UlpsActiveNot Status */ + __IM uint32_t DL1UAN : 1; /*!< [5..5] Data Lane-1 UlpsActiveNot Status */ + uint32_t : 2; + __IM uint32_t DL0STP : 1; /*!< [8..8] Data Lane-0 Stop Status */ + __IM uint32_t DL1STP : 1; /*!< [9..9] Data Lane-1 Stop Status */ + uint32_t : 2; + __IM uint32_t DL0RX2TX : 1; /*!< [12..12] Data Lane-0 RX to TX Transition Interrupt Flag */ + __IM uint32_t DL0TX2RX : 1; /*!< [13..13] Data Lane-0 TX to RX Transition Interrupt Flag */ + uint32_t : 1; + __IM uint32_t DL0DIR : 1; /*!< [15..15] Data Lane-0 Direction */ + uint32_t : 8; + __IM uint32_t CLULPENT : 1; /*!< [24..24] Clock Lane ULPS Enter Interrupt Flag */ + __IM uint32_t CLULPEXT : 1; /*!< [25..25] Clock Lane ULPS Exit Interrupt Flag */ + __IM uint32_t CLLP2HS : 1; /*!< [26..26] Clock Lane LP to HS Transition Interrupt Flag */ + __IM uint32_t CLHS2LP : 1; /*!< [27..27] Clock Lane HS to LP Transition Interrupt Flag */ + __IM uint32_t DLULPENT : 1; /*!< [28..28] Data Lane ULPS Enter Interrupt Flag */ + __IM uint32_t DLULPEXT : 1; /*!< [29..29] Data Lane ULPS Exit Interrupt Flag */ + uint32_t : 2; + } PLSR_b; + }; + + union + { + __IOM uint32_t PLSCR; /*!< (@ 0x00000324) Physical Lane Status Clear Register */ + + struct + { + uint32_t : 12; + __IOM uint32_t DL0RX2TX : 1; /*!< [12..12] Data Lane-0 RX to TX Transition Interrupt Flag Clear */ + __IOM uint32_t DL0TX2RX : 1; /*!< [13..13] Data Lane-0 TX to RX Transition Interrupt Flag Clear */ + uint32_t : 10; + __IOM uint32_t CLULPENT : 1; /*!< [24..24] Clock Lane ULPS Enter Interrupt Flag Clear */ + __IOM uint32_t CLULPEXT : 1; /*!< [25..25] Clock Lane ULPS Exit Interrupt Flag Clear */ + __IOM uint32_t CLLP2HS : 1; /*!< [26..26] Clock Lane LP to HS Transition Interrupt Flag Clear */ + __IOM uint32_t CLHS2LP : 1; /*!< [27..27] Clock Lane HS to LP Transition Interrupt Flag Clear */ + __IOM uint32_t DLULPENT : 1; /*!< [28..28] Data Lane ULPS Enter Interrupt Flag Clear */ + __IOM uint32_t DLULPEXT : 1; /*!< [29..29] Data Lane ULPS Exit Interrupt Flag Clear */ + uint32_t : 2; + } PLSCR_b; + }; + + union + { + __IOM uint32_t PLIER; /*!< (@ 0x00000328) Physical Lane Interrupt Enable Register */ + + struct + { + uint32_t : 12; + __IOM uint32_t DL0RX2TX : 1; /*!< [12..12] Data Lane-0 RX to TX Transition Interrupt Enable */ + __IOM uint32_t DL0TX2RX : 1; /*!< [13..13] Data Lane-0 TX to RX Transition Interrupt Enable */ + uint32_t : 10; + __IOM uint32_t CLULPENT : 1; /*!< [24..24] Clock Lane ULPS Enter Interrupt Enable */ + __IOM uint32_t CLULPEXT : 1; /*!< [25..25] Clock Lane ULPS Exit Interrupt Enable */ + __IOM uint32_t CLLP2HS : 1; /*!< [26..26] Clock Lane LP to HS Transition Interrupt Enable */ + __IOM uint32_t CLHS2LP : 1; /*!< [27..27] Clock Lane HS to LP Transition Interrupt Enable */ + __IOM uint32_t DLULPENT : 1; /*!< [28..28] Data Lane ULPS Enter Interrupt Enable */ + __IOM uint32_t DLULPEXT : 1; /*!< [29..29] Data Lane ULPS Exit Interrupt Enable */ + uint32_t : 2; + } PLIER_b; + }; + __IM uint32_t RESERVED13[53]; + + union + { + __IOM uint32_t VMSET0R; /*!< (@ 0x00000400) Video Mode Set 0 Register */ + + struct + { + __OM uint32_t VSTART : 1; /*!< [0..0] Video Mode Operation Start */ + __OM uint32_t VSTOP : 1; /*!< [1..1] Video Mode Operation Stop */ + uint32_t : 6; + __IOM uint32_t HSANOLP : 1; /*!< [8..8] HSA period No LP */ + __IOM uint32_t HBPNOLP : 1; /*!< [9..9] HBP period No LP */ + __IOM uint32_t HFPNOLP : 1; /*!< [10..10] HFP period No LP */ + uint32_t : 21; + } VMSET0R_b; + }; + + union + { + __IOM uint32_t VMSET1R; /*!< (@ 0x00000404) Video Mode Set 1 Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t DLY : 12; /*!< [13..2] Delay Value */ + uint32_t : 18; + } VMSET1R_b; + }; + __IM uint32_t RESERVED14[2]; + + union + { + __IM uint32_t VMSR; /*!< (@ 0x00000410) Video Mode Status Register */ + + struct + { + __IM uint32_t START : 1; /*!< [0..0] Video Mode Operation Start Interrupt Flag */ + __IM uint32_t STOP : 1; /*!< [1..1] Video Mode Operation Stop Interrupt Flag */ + __IM uint32_t RUNNING : 1; /*!< [2..2] Video Mode Operation Running Status */ + __IM uint32_t VIRDY : 1; /*!< [3..3] Video Mode Operation Ready Interrupt Flag */ + uint32_t : 16; + __IM uint32_t TIMERR : 1; /*!< [20..20] Timing Error Interrupt Flag */ + uint32_t : 1; + __IM uint32_t VBUFUDF : 1; /*!< [22..22] Video Buffer Underflow Error Interrupt Flag */ + __IM uint32_t VBUFOVF : 1; /*!< [23..23] Video Buffer Overflow Error Interrupt Flag */ + uint32_t : 8; + } VMSR_b; + }; + + union + { + __IOM uint32_t VMSCR; /*!< (@ 0x00000414) Video Mode Status Clear Register */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] Video Mode Operation Start Interrupt Flag Clear */ + __IOM uint32_t STOP : 1; /*!< [1..1] Video Mode Operation Stop Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t VIRDY : 1; /*!< [3..3] Video Mode Operation Ready Interrupt Flag Clear */ + uint32_t : 16; + __IOM uint32_t TIMERR : 1; /*!< [20..20] Timing Error Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t VBUFUDF : 1; /*!< [22..22] Video Buffer Underflow Error Interrupt Flag Clear */ + __IOM uint32_t VBUFOVF : 1; /*!< [23..23] Video Buffer Overflow Error Interrupt Flag Clear */ + uint32_t : 8; + } VMSCR_b; + }; + + union + { + __IOM uint32_t VMIER; /*!< (@ 0x00000418) Video Mode Interrupt Enable Register */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] Video Mode Operation Start Interrupt Enable */ + __IOM uint32_t STOP : 1; /*!< [1..1] Video Mode Operation Stop Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t VIRDY : 1; /*!< [3..3] Video Mode Operation Ready Interrupt Enable */ + uint32_t : 16; + __IOM uint32_t TIMERR : 1; /*!< [20..20] Timing Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t VBUFUDF : 1; /*!< [22..22] Video Buffer Underflow Error Interrupt Enable */ + __IOM uint32_t VBUFOVF : 1; /*!< [23..23] Video Buffer Overflow Error Interrupt Enable */ + uint32_t : 8; + } VMIER_b; + }; + __IM uint32_t RESERVED15; + + union + { + __IOM uint32_t VMPPSETR; /*!< (@ 0x00000420) Video Mode Pixel Packet Set Register */ + + struct + { + uint32_t : 15; + __IOM uint32_t TXESYNC : 1; /*!< [15..15] Transmit End of Sync Pulse */ + __IOM uint32_t DT : 6; /*!< [21..16] Video Mode Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Video Mode Virtual Channel */ + uint32_t : 8; + } VMPPSETR_b; + }; + __IM uint32_t RESERVED16; + + union + { + __IOM uint32_t VMVSSETR; /*!< (@ 0x00000428) Video Mode Vertical Size Set Register */ + + struct + { + __IOM uint32_t VSA : 12; /*!< [11..0] VSA Lines */ + uint32_t : 3; + __IOM uint32_t VSPOL : 1; /*!< [15..15] VSYNC Polarity */ + __IOM uint32_t VACT : 15; /*!< [30..16] Vertical Active Lines */ + uint32_t : 1; + } VMVSSETR_b; + }; + + union + { + __IOM uint32_t VMVPSETR; /*!< (@ 0x0000042C) Video Mode Vertical Porch Set Register */ + + struct + { + __IOM uint32_t VBP : 13; /*!< [12..0] VBP Lines */ + uint32_t : 3; + __IOM uint32_t VFP : 13; /*!< [28..16] VFP Lines */ + uint32_t : 3; + } VMVPSETR_b; + }; + + union + { + __IOM uint32_t VMHSSETR; /*!< (@ 0x00000430) Video Mode Horizontal Size Set Register */ + + struct + { + __IOM uint32_t HSA : 12; /*!< [11..0] HSA Pixels */ + uint32_t : 3; + __IOM uint32_t HSPOL : 1; /*!< [15..15] HSYNC Polarity */ + __IOM uint32_t HACT : 15; /*!< [30..16] HACT Pixels */ + uint32_t : 1; + } VMHSSETR_b; + }; + + union + { + __IOM uint32_t VMHPSETR; /*!< (@ 0x00000434) Video Mode Horizontal Porch Set Register */ + + struct + { + __IOM uint32_t HBP : 13; /*!< [12..0] HBP Pixels */ + uint32_t : 3; + __IOM uint32_t HFP : 13; /*!< [28..16] HFP Pixels */ + uint32_t : 3; + } VMHPSETR_b; + }; + __IM uint32_t RESERVED17[98]; + + union + { + __IOM uint32_t SQCH0SET0R; /*!< (@ 0x000005C0) Sequence Channel 0 Set 0 Register */ + + struct + { + __OM uint32_t START : 1; /*!< [0..0] Sequence Operation Start */ + uint32_t : 31; + } SQCH0SET0R_b; + }; + __IM uint32_t RESERVED18[3]; + + union + { + __IM uint32_t SQCH0SR; /*!< (@ 0x000005D0) Sequence Channel 0 Status Register */ + + struct + { + uint32_t : 2; + __IM uint32_t RUNNING : 1; /*!< [2..2] Sequence Operation Running Status */ + uint32_t : 1; + __IM uint32_t AACTFIN : 1; /*!< [4..4] All Actions Finish Interrupt Flag */ + uint32_t : 3; + __IM uint32_t ADESFIN : 1; /*!< [8..8] All-Descriptors Finish Interrupt Flag */ + uint32_t : 7; + __IM uint32_t DABORT : 1; /*!< [16..16] Descriptor Abort Interrupt Flag */ + uint32_t : 2; + __IM uint32_t SIZEERR : 1; /*!< [19..19] Packet Size Error Interrupt Flag */ + uint32_t : 4; + __IM uint32_t TXIBERR : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Flag */ + uint32_t : 1; + __IM uint32_t RXFERR : 1; /*!< [26..26] Receive Fatal Error Interrupt Flag */ + __IM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail Interrupt Flag */ + __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Flag */ + __IM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Flag */ + __IM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt + * Flag */ + uint32_t : 1; + } SQCH0SR_b; + }; + + union + { + __IOM uint32_t SQCH0SCR; /*!< (@ 0x000005D4) Sequence Channel 0 Status Clear Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t AACTFIN : 1; /*!< [4..4] All Actions Finish Interrupt Flag Clear */ + uint32_t : 3; + __IOM uint32_t ADESFIN : 1; /*!< [8..8] All-Descriptors Finish Interrupt Flag Clear */ + uint32_t : 7; + __IOM uint32_t DABORT : 1; /*!< [16..16] Descriptor Abort Interrupt Flag Clear */ + uint32_t : 2; + __IOM uint32_t SIZEERR : 1; /*!< [19..19] Packet Size Error Interrupt Flag Clear */ + uint32_t : 4; + __IOM uint32_t TXIBERR : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t RXFERR : 1; /*!< [26..26] Receive Fatal Error Interrupt Flag Clear */ + __IOM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail Interrupt Flag Clear */ + __IOM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Flag Clear */ + __IOM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Flag Clear */ + __IOM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt + * Flag Clear */ + uint32_t : 1; + } SQCH0SCR_b; + }; + + union + { + __IOM uint32_t SQCH0IER; /*!< (@ 0x000005D8) Sequence Channel 0 Interrupt Enable Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t AACTFIN : 1; /*!< [4..4] All Actions Finish Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t ADESFIN : 1; /*!< [8..8] All-Descriptors Finish Interrupt Enable */ + uint32_t : 7; + __IOM uint32_t DABORT : 1; /*!< [16..16] Descriptor Abort Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SIZEERR : 1; /*!< [19..19] Packet Size Error Interrupt Enable */ + uint32_t : 4; + __IOM uint32_t TXIBERR : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t RXFERR : 1; /*!< [26..26] Receive Fatal Error Interrupt Enable */ + __IOM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail Interrupt Enable */ + __IOM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Enable */ + __IOM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Enable */ + __IOM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt + * Enable */ + uint32_t : 1; + } SQCH0IER_b; + }; + __IM uint32_t RESERVED19[9]; + + union + { + __IOM uint32_t SQCH1SET0R; /*!< (@ 0x00000600) Sequence Channel 1 Set 0 Register */ + + struct + { + __OM uint32_t START : 1; /*!< [0..0] Sequence Operation Start */ + uint32_t : 31; + } SQCH1SET0R_b; + }; + __IM uint32_t RESERVED20[3]; + + union + { + __IM uint32_t SQCH1SR; /*!< (@ 0x00000610) Sequence Channel 1 Status Register */ + + struct + { + uint32_t : 2; + __IM uint32_t RUNNING : 1; /*!< [2..2] Sequence Operation Running Status */ + uint32_t : 1; + __IM uint32_t AACTFIN : 1; /*!< [4..4] All Actions Finish Interrupt Flag */ + uint32_t : 3; + __IM uint32_t ADESFIN : 1; /*!< [8..8] All-Descriptors Finish Interrupt Flag */ + uint32_t : 7; + __IM uint32_t DABORT : 1; /*!< [16..16] Descriptor Abort Interrupt Flag */ + uint32_t : 2; + __IM uint32_t SIZEERR : 1; /*!< [19..19] Packet Size Error Interrupt Flag */ + uint32_t : 4; + __IM uint32_t TXIBERR : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Flag */ + uint32_t : 1; + __IM uint32_t RXFERR : 1; /*!< [26..26] Receive Fatal Error Interrupt Flag */ + __IM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail Interrupt Flag */ + __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Flag */ + __IM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Flag */ + __IM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt + * Flag */ + uint32_t : 1; + } SQCH1SR_b; + }; + + union + { + __IOM uint32_t SQCH1SCR; /*!< (@ 0x00000614) Sequence Channel 1 Status Clear Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t AACTFIN : 1; /*!< [4..4] All Actions Finish Interrupt Flag Clear */ + uint32_t : 3; + __IOM uint32_t ADESFIN : 1; /*!< [8..8] All-Descriptors Finish Interrupt Flag Clear */ + uint32_t : 7; + __IOM uint32_t DABORT : 1; /*!< [16..16] Descriptor Abort Interrupt Flag Clear */ + uint32_t : 2; + __IOM uint32_t SIZEERR : 1; /*!< [19..19] Packet Size Error Interrupt Flag Clear */ + uint32_t : 4; + __IOM uint32_t TXIBERR : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t RXFERR : 1; /*!< [26..26] Receive Fatal Error Interrupt Flag Clear */ + __IOM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail Interrupt Flag Clear */ + __IOM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Flag Clear */ + __IOM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Flag Clear */ + __IOM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt + * Flag Clear */ + uint32_t : 1; + } SQCH1SCR_b; + }; + + union + { + __IOM uint32_t SQCH1IER; /*!< (@ 0x00000618) Sequence Channel 1 Interrupt Enable Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t AACTFIN : 1; /*!< [4..4] All Actions Finish Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t ADESFIN : 1; /*!< [8..8] All-Descriptors Finish Interrupt Enable */ + uint32_t : 7; + __IOM uint32_t DABORT : 1; /*!< [16..16] Descriptor Abort Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SIZEERR : 1; /*!< [19..19] Packet Size Error Interrupt Enable */ + uint32_t : 4; + __IOM uint32_t TXIBERR : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t RXFERR : 1; /*!< [26..26] Receive Fatal Error Interrupt Enable */ + __IOM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail Interrupt Enable */ + __IOM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Enable */ + __IOM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Enable */ + __IOM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt + * Enable */ + uint32_t : 1; + } SQCH1IER_b; + }; + __IM uint32_t RESERVED21[89]; + + union + { + union + { + __IOM uint32_t SQCH0DSC0AR; /*!< (@ 0x00000780) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC0AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC0AR_L; /*!< (@ 0x00000780) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC0AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC0AR_LL; /*!< (@ 0x00000780) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC0AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC0AR_LH; /*!< (@ 0x00000781) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC0AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC0AR_H; /*!< (@ 0x00000782) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC0AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC0AR_HL; /*!< (@ 0x00000782) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC0AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC0AR_HH; /*!< (@ 0x00000783) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC0AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC0BR; /*!< (@ 0x00000784) Sequence Channel 0 Descriptor-0 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC0BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC0CR; /*!< (@ 0x00000788) Sequence Channel 0 Descriptor-0 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC0CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC0CR_L; /*!< (@ 0x00000788) Sequence Channel 0 Descriptor-0 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC0CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC0CR_LL; /*!< (@ 0x00000788) Sequence Channel 0 Descriptor-0 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC0CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC0CR_H; /*!< (@ 0x0000078A) Sequence Channel 0 Descriptor-0 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC0CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC0CR_HL; /*!< (@ 0x0000078A) Sequence Channel 0 Descriptor-0 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC0CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC0CR_HH; /*!< (@ 0x0000078B) Sequence Channel 0 Descriptor-0 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC0CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC0DR; /*!< (@ 0x0000078C) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC0DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC0DR_L; /*!< (@ 0x0000078C) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC0DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC0DR_LL; /*!< (@ 0x0000078C) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC0DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC0DR_LH; /*!< (@ 0x0000078D) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC0DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC0DR_H; /*!< (@ 0x0000078E) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC0DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC0DR_HL; /*!< (@ 0x0000078E) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC0DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC0DR_HH; /*!< (@ 0x0000078F) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC0DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC1AR; /*!< (@ 0x00000790) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC1AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC1AR_L; /*!< (@ 0x00000790) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC1AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC1AR_LL; /*!< (@ 0x00000790) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC1AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC1AR_LH; /*!< (@ 0x00000791) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC1AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC1AR_H; /*!< (@ 0x00000792) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC1AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC1AR_HL; /*!< (@ 0x00000792) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC1AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC1AR_HH; /*!< (@ 0x00000793) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC1AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC1BR; /*!< (@ 0x00000794) Sequence Channel 0 Descriptor-1 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC1BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC1CR; /*!< (@ 0x00000798) Sequence Channel 0 Descriptor-1 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC1CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC1CR_L; /*!< (@ 0x00000798) Sequence Channel 0 Descriptor-1 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC1CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC1CR_LL; /*!< (@ 0x00000798) Sequence Channel 0 Descriptor-1 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC1CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC1CR_H; /*!< (@ 0x0000079A) Sequence Channel 0 Descriptor-1 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC1CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC1CR_HL; /*!< (@ 0x0000079A) Sequence Channel 0 Descriptor-1 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC1CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC1CR_HH; /*!< (@ 0x0000079B) Sequence Channel 0 Descriptor-1 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC1CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC1DR; /*!< (@ 0x0000079C) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC1DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC1DR_L; /*!< (@ 0x0000079C) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC1DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC1DR_LL; /*!< (@ 0x0000079C) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC1DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC1DR_LH; /*!< (@ 0x0000079D) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC1DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC1DR_H; /*!< (@ 0x0000079E) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC1DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC1DR_HL; /*!< (@ 0x0000079E) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC1DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC1DR_HH; /*!< (@ 0x0000079F) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC1DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC2AR; /*!< (@ 0x000007A0) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC2AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC2AR_L; /*!< (@ 0x000007A0) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC2AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC2AR_LL; /*!< (@ 0x000007A0) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC2AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC2AR_LH; /*!< (@ 0x000007A1) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC2AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC2AR_H; /*!< (@ 0x000007A2) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC2AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC2AR_HL; /*!< (@ 0x000007A2) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC2AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC2AR_HH; /*!< (@ 0x000007A3) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC2AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC2BR; /*!< (@ 0x000007A4) Sequence Channel 0 Descriptor-2 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC2BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC2CR; /*!< (@ 0x000007A8) Sequence Channel 0 Descriptor-2 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC2CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC2CR_L; /*!< (@ 0x000007A8) Sequence Channel 0 Descriptor-2 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC2CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC2CR_LL; /*!< (@ 0x000007A8) Sequence Channel 0 Descriptor-2 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC2CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC2CR_H; /*!< (@ 0x000007AA) Sequence Channel 0 Descriptor-2 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC2CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC2CR_HL; /*!< (@ 0x000007AA) Sequence Channel 0 Descriptor-2 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC2CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC2CR_HH; /*!< (@ 0x000007AB) Sequence Channel 0 Descriptor-2 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC2CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC2DR; /*!< (@ 0x000007AC) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC2DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC2DR_L; /*!< (@ 0x000007AC) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC2DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC2DR_LL; /*!< (@ 0x000007AC) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC2DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC2DR_LH; /*!< (@ 0x000007AD) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC2DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC2DR_H; /*!< (@ 0x000007AE) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC2DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC2DR_HL; /*!< (@ 0x000007AE) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC2DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC2DR_HH; /*!< (@ 0x000007AF) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC2DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC3AR; /*!< (@ 0x000007B0) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC3AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC3AR_L; /*!< (@ 0x000007B0) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC3AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC3AR_LL; /*!< (@ 0x000007B0) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC3AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC3AR_LH; /*!< (@ 0x000007B1) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC3AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC3AR_H; /*!< (@ 0x000007B2) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC3AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC3AR_HL; /*!< (@ 0x000007B2) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC3AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC3AR_HH; /*!< (@ 0x000007B3) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC3AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC3BR; /*!< (@ 0x000007B4) Sequence Channel 0 Descriptor-3 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC3BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC3CR; /*!< (@ 0x000007B8) Sequence Channel 0 Descriptor-3 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC3CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC3CR_L; /*!< (@ 0x000007B8) Sequence Channel 0 Descriptor-3 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC3CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC3CR_LL; /*!< (@ 0x000007B8) Sequence Channel 0 Descriptor-3 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC3CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC3CR_H; /*!< (@ 0x000007BA) Sequence Channel 0 Descriptor-3 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC3CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC3CR_HL; /*!< (@ 0x000007BA) Sequence Channel 0 Descriptor-3 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC3CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC3CR_HH; /*!< (@ 0x000007BB) Sequence Channel 0 Descriptor-3 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC3CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC3DR; /*!< (@ 0x000007BC) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC3DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC3DR_L; /*!< (@ 0x000007BC) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC3DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC3DR_LL; /*!< (@ 0x000007BC) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC3DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC3DR_LH; /*!< (@ 0x000007BD) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC3DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC3DR_H; /*!< (@ 0x000007BE) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC3DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC3DR_HL; /*!< (@ 0x000007BE) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC3DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC3DR_HH; /*!< (@ 0x000007BF) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC3DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC4AR; /*!< (@ 0x000007C0) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC4AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC4AR_L; /*!< (@ 0x000007C0) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC4AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC4AR_LL; /*!< (@ 0x000007C0) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC4AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC4AR_LH; /*!< (@ 0x000007C1) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC4AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC4AR_H; /*!< (@ 0x000007C2) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC4AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC4AR_HL; /*!< (@ 0x000007C2) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC4AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC4AR_HH; /*!< (@ 0x000007C3) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC4AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC4BR; /*!< (@ 0x000007C4) Sequence Channel 0 Descriptor-4 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC4BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC4CR; /*!< (@ 0x000007C8) Sequence Channel 0 Descriptor-4 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC4CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC4CR_L; /*!< (@ 0x000007C8) Sequence Channel 0 Descriptor-4 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC4CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC4CR_LL; /*!< (@ 0x000007C8) Sequence Channel 0 Descriptor-4 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC4CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC4CR_H; /*!< (@ 0x000007CA) Sequence Channel 0 Descriptor-4 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC4CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC4CR_HL; /*!< (@ 0x000007CA) Sequence Channel 0 Descriptor-4 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC4CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC4CR_HH; /*!< (@ 0x000007CB) Sequence Channel 0 Descriptor-4 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC4CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC4DR; /*!< (@ 0x000007CC) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC4DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC4DR_L; /*!< (@ 0x000007CC) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC4DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC4DR_LL; /*!< (@ 0x000007CC) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC4DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC4DR_LH; /*!< (@ 0x000007CD) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC4DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC4DR_H; /*!< (@ 0x000007CE) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC4DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC4DR_HL; /*!< (@ 0x000007CE) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC4DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC4DR_HH; /*!< (@ 0x000007CF) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC4DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC5AR; /*!< (@ 0x000007D0) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC5AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC5AR_L; /*!< (@ 0x000007D0) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC5AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC5AR_LL; /*!< (@ 0x000007D0) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC5AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC5AR_LH; /*!< (@ 0x000007D1) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC5AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC5AR_H; /*!< (@ 0x000007D2) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC5AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC5AR_HL; /*!< (@ 0x000007D2) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC5AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC5AR_HH; /*!< (@ 0x000007D3) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC5AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC5BR; /*!< (@ 0x000007D4) Sequence Channel 0 Descriptor-5 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC5BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC5CR; /*!< (@ 0x000007D8) Sequence Channel 0 Descriptor-5 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC5CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC5CR_L; /*!< (@ 0x000007D8) Sequence Channel 0 Descriptor-5 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC5CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC5CR_LL; /*!< (@ 0x000007D8) Sequence Channel 0 Descriptor-5 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC5CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC5CR_H; /*!< (@ 0x000007DA) Sequence Channel 0 Descriptor-5 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC5CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC5CR_HL; /*!< (@ 0x000007DA) Sequence Channel 0 Descriptor-5 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC5CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC5CR_HH; /*!< (@ 0x000007DB) Sequence Channel 0 Descriptor-5 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC5CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC5DR; /*!< (@ 0x000007DC) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC5DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC5DR_L; /*!< (@ 0x000007DC) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC5DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC5DR_LL; /*!< (@ 0x000007DC) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC5DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC5DR_LH; /*!< (@ 0x000007DD) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC5DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC5DR_H; /*!< (@ 0x000007DE) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC5DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC5DR_HL; /*!< (@ 0x000007DE) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC5DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC5DR_HH; /*!< (@ 0x000007DF) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC5DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC6AR; /*!< (@ 0x000007E0) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC6AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC6AR_L; /*!< (@ 0x000007E0) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC6AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC6AR_LL; /*!< (@ 0x000007E0) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC6AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC6AR_LH; /*!< (@ 0x000007E1) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC6AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC6AR_H; /*!< (@ 0x000007E2) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC6AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC6AR_HL; /*!< (@ 0x000007E2) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC6AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC6AR_HH; /*!< (@ 0x000007E3) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC6AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC6BR; /*!< (@ 0x000007E4) Sequence Channel 0 Descriptor-6 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC6BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC6CR; /*!< (@ 0x000007E8) Sequence Channel 0 Descriptor-6 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC6CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC6CR_L; /*!< (@ 0x000007E8) Sequence Channel 0 Descriptor-6 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC6CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC6CR_LL; /*!< (@ 0x000007E8) Sequence Channel 0 Descriptor-6 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC6CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC6CR_H; /*!< (@ 0x000007EA) Sequence Channel 0 Descriptor-6 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC6CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC6CR_HL; /*!< (@ 0x000007EA) Sequence Channel 0 Descriptor-6 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC6CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC6CR_HH; /*!< (@ 0x000007EB) Sequence Channel 0 Descriptor-6 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC6CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC6DR; /*!< (@ 0x000007EC) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC6DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC6DR_L; /*!< (@ 0x000007EC) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC6DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC6DR_LL; /*!< (@ 0x000007EC) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC6DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC6DR_LH; /*!< (@ 0x000007ED) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC6DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC6DR_H; /*!< (@ 0x000007EE) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC6DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC6DR_HL; /*!< (@ 0x000007EE) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC6DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC6DR_HH; /*!< (@ 0x000007EF) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC6DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC7AR; /*!< (@ 0x000007F0) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC7AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC7AR_L; /*!< (@ 0x000007F0) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC7AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC7AR_LL; /*!< (@ 0x000007F0) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC7AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC7AR_LH; /*!< (@ 0x000007F1) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC7AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC7AR_H; /*!< (@ 0x000007F2) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC7AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC7AR_HL; /*!< (@ 0x000007F2) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC7AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC7AR_HH; /*!< (@ 0x000007F3) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC7AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC7BR; /*!< (@ 0x000007F4) Sequence Channel 0 Descriptor-7 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC7BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC7CR; /*!< (@ 0x000007F8) Sequence Channel 0 Descriptor-7 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC7CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC7CR_L; /*!< (@ 0x000007F8) Sequence Channel 0 Descriptor-7 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC7CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC7CR_LL; /*!< (@ 0x000007F8) Sequence Channel 0 Descriptor-7 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC7CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC7CR_H; /*!< (@ 0x000007FA) Sequence Channel 0 Descriptor-7 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC7CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC7CR_HL; /*!< (@ 0x000007FA) Sequence Channel 0 Descriptor-7 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC7CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC7CR_HH; /*!< (@ 0x000007FB) Sequence Channel 0 Descriptor-7 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC7CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC7DR; /*!< (@ 0x000007FC) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC7DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC7DR_L; /*!< (@ 0x000007FC) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC7DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC7DR_LL; /*!< (@ 0x000007FC) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC7DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC7DR_LH; /*!< (@ 0x000007FD) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC7DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC7DR_H; /*!< (@ 0x000007FE) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC7DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC7DR_HL; /*!< (@ 0x000007FE) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC7DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC7DR_HH; /*!< (@ 0x000007FF) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC7DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC0AR; /*!< (@ 0x00000800) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC0AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC0AR_L; /*!< (@ 0x00000800) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC0AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC0AR_LL; /*!< (@ 0x00000800) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC0AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC0AR_LH; /*!< (@ 0x00000801) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC0AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC0AR_H; /*!< (@ 0x00000802) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC0AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC0AR_HL; /*!< (@ 0x00000802) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC0AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC0AR_HH; /*!< (@ 0x00000803) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC0AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC0BR; /*!< (@ 0x00000804) Sequence Channel 1 Descriptor-0 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC0BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC0CR; /*!< (@ 0x00000808) Sequence Channel 1 Descriptor-0 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC0CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC0CR_L; /*!< (@ 0x00000808) Sequence Channel 1 Descriptor-0 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC0CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC0CR_LL; /*!< (@ 0x00000808) Sequence Channel 1 Descriptor-0 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC0CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC0CR_H; /*!< (@ 0x0000080A) Sequence Channel 1 Descriptor-0 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC0CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC0CR_HL; /*!< (@ 0x0000080A) Sequence Channel 1 Descriptor-0 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC0CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC0CR_HH; /*!< (@ 0x0000080B) Sequence Channel 1 Descriptor-0 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC0CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC0DR; /*!< (@ 0x0000080C) Sequence Channel 1 Descriptor-0 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC0DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC0DR_L; /*!< (@ 0x0000080C) Sequence Channel 1 Descriptor-0 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC0DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC0DR_LL; /*!< (@ 0x0000080C) Sequence Channel 1 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC0DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC0DR_LH; /*!< (@ 0x0000080D) Sequence Channel 1 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC0DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC0DR_HL; /*!< (@ 0x0000080E) Sequence Channel 1 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC0DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC0DR_HH; /*!< (@ 0x0000080F) Sequence Channel 1 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC0DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC1AR; /*!< (@ 0x00000810) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC1AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC1AR_L; /*!< (@ 0x00000810) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC1AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC1AR_LL; /*!< (@ 0x00000810) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC1AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC1AR_LH; /*!< (@ 0x00000811) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC1AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC1AR_H; /*!< (@ 0x00000812) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC1AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC1AR_HL; /*!< (@ 0x00000812) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC1AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC1AR_HH; /*!< (@ 0x00000813) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC1AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC1BR; /*!< (@ 0x00000814) Sequence Channel 1 Descriptor-1 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC1BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC1CR; /*!< (@ 0x00000818) Sequence Channel 1 Descriptor-1 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC1CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC1CR_L; /*!< (@ 0x00000818) Sequence Channel 1 Descriptor-1 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC1CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC1CR_LL; /*!< (@ 0x00000818) Sequence Channel 1 Descriptor-1 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC1CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC1CR_H; /*!< (@ 0x0000081A) Sequence Channel 1 Descriptor-1 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC1CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC1CR_HL; /*!< (@ 0x0000081A) Sequence Channel 1 Descriptor-1 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC1CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC1CR_HH; /*!< (@ 0x0000081B) Sequence Channel 1 Descriptor-1 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC1CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC1DR; /*!< (@ 0x0000081C) Sequence Channel 1 Descriptor-1 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC1DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC1DR_L; /*!< (@ 0x0000081C) Sequence Channel 1 Descriptor-1 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC1DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC1DR_LL; /*!< (@ 0x0000081C) Sequence Channel 1 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC1DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC1DR_LH; /*!< (@ 0x0000081D) Sequence Channel 1 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC1DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC1DR_HL; /*!< (@ 0x0000081E) Sequence Channel 1 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC1DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC1DR_HH; /*!< (@ 0x0000081F) Sequence Channel 1 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC1DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC2AR; /*!< (@ 0x00000820) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC2AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC2AR_L; /*!< (@ 0x00000820) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC2AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC2AR_LL; /*!< (@ 0x00000820) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC2AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC2AR_LH; /*!< (@ 0x00000821) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC2AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC2AR_H; /*!< (@ 0x00000822) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC2AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC2AR_HL; /*!< (@ 0x00000822) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC2AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC2AR_HH; /*!< (@ 0x00000823) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC2AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC2BR; /*!< (@ 0x00000824) Sequence Channel 1 Descriptor-2 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC2BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC2CR; /*!< (@ 0x00000828) Sequence Channel 1 Descriptor-2 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC2CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC2CR_L; /*!< (@ 0x00000828) Sequence Channel 1 Descriptor-2 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC2CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC2CR_LL; /*!< (@ 0x00000828) Sequence Channel 1 Descriptor-2 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC2CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC2CR_H; /*!< (@ 0x0000082A) Sequence Channel 1 Descriptor-2 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC2CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC2CR_HL; /*!< (@ 0x0000082A) Sequence Channel 1 Descriptor-2 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC2CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC2CR_HH; /*!< (@ 0x0000082B) Sequence Channel 1 Descriptor-2 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC2CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC2DR; /*!< (@ 0x0000082C) Sequence Channel 1 Descriptor-2 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC2DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC2DR_L; /*!< (@ 0x0000082C) Sequence Channel 1 Descriptor-2 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC2DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC2DR_LL; /*!< (@ 0x0000082C) Sequence Channel 1 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC2DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC2DR_LH; /*!< (@ 0x0000082D) Sequence Channel 1 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC2DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC2DR_HL; /*!< (@ 0x0000082E) Sequence Channel 1 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC2DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC2DR_HH; /*!< (@ 0x0000082F) Sequence Channel 1 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC2DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC3AR; /*!< (@ 0x00000830) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC3AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC3AR_L; /*!< (@ 0x00000830) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC3AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC3AR_LL; /*!< (@ 0x00000830) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC3AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC3AR_LH; /*!< (@ 0x00000831) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC3AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC3AR_H; /*!< (@ 0x00000832) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC3AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC3AR_HL; /*!< (@ 0x00000832) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC3AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC3AR_HH; /*!< (@ 0x00000833) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC3AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC3BR; /*!< (@ 0x00000834) Sequence Channel 1 Descriptor-3 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC3BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC3CR; /*!< (@ 0x00000838) Sequence Channel 1 Descriptor-3 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC3CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC3CR_L; /*!< (@ 0x00000838) Sequence Channel 1 Descriptor-3 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC3CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC3CR_LL; /*!< (@ 0x00000838) Sequence Channel 1 Descriptor-3 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC3CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC3CR_H; /*!< (@ 0x0000083A) Sequence Channel 1 Descriptor-3 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC3CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC3CR_HL; /*!< (@ 0x0000083A) Sequence Channel 1 Descriptor-3 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC3CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC3CR_HH; /*!< (@ 0x0000083B) Sequence Channel 1 Descriptor-3 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC3CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC3DR; /*!< (@ 0x0000083C) Sequence Channel 1 Descriptor-3 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC3DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC3DR_L; /*!< (@ 0x0000083C) Sequence Channel 1 Descriptor-3 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC3DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC3DR_LL; /*!< (@ 0x0000083C) Sequence Channel 1 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC3DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC3DR_LH; /*!< (@ 0x0000083D) Sequence Channel 1 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC3DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC3DR_HL; /*!< (@ 0x0000083E) Sequence Channel 1 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC3DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC3DR_HH; /*!< (@ 0x0000083F) Sequence Channel 1 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC3DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC4AR; /*!< (@ 0x00000840) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC4AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC4AR_L; /*!< (@ 0x00000840) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC4AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC4AR_LL; /*!< (@ 0x00000840) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC4AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC4AR_LH; /*!< (@ 0x00000841) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC4AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC4AR_H; /*!< (@ 0x00000842) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC4AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC4AR_HL; /*!< (@ 0x00000842) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC4AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC4AR_HH; /*!< (@ 0x00000843) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC4AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC4BR; /*!< (@ 0x00000844) Sequence Channel 1 Descriptor-4 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC4BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC4CR; /*!< (@ 0x00000848) Sequence Channel 1 Descriptor-4 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC4CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC4CR_L; /*!< (@ 0x00000848) Sequence Channel 1 Descriptor-4 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC4CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC4CR_LL; /*!< (@ 0x00000848) Sequence Channel 1 Descriptor-4 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC4CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC4CR_H; /*!< (@ 0x0000084A) Sequence Channel 1 Descriptor-4 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC4CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC4CR_HL; /*!< (@ 0x0000084A) Sequence Channel 1 Descriptor-4 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC4CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC4CR_HH; /*!< (@ 0x0000084B) Sequence Channel 1 Descriptor-4 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC4CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC4DR; /*!< (@ 0x0000084C) Sequence Channel 1 Descriptor-4 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC4DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC4DR_L; /*!< (@ 0x0000084C) Sequence Channel 1 Descriptor-4 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC4DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC4DR_LL; /*!< (@ 0x0000084C) Sequence Channel 1 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC4DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC4DR_LH; /*!< (@ 0x0000084D) Sequence Channel 1 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC4DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC4DR_HL; /*!< (@ 0x0000084E) Sequence Channel 1 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC4DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC4DR_HH; /*!< (@ 0x0000084F) Sequence Channel 1 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC4DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC5AR; /*!< (@ 0x00000850) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC5AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC5AR_L; /*!< (@ 0x00000850) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC5AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC5AR_LL; /*!< (@ 0x00000850) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC5AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC5AR_LH; /*!< (@ 0x00000851) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC5AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC5AR_H; /*!< (@ 0x00000852) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC5AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC5AR_HL; /*!< (@ 0x00000852) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC5AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC5AR_HH; /*!< (@ 0x00000853) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC5AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC5BR; /*!< (@ 0x00000854) Sequence Channel 1 Descriptor-5 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC5BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC5CR; /*!< (@ 0x00000858) Sequence Channel 1 Descriptor-5 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC5CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC5CR_L; /*!< (@ 0x00000858) Sequence Channel 1 Descriptor-5 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC5CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC5CR_LL; /*!< (@ 0x00000858) Sequence Channel 1 Descriptor-5 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC5CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC5CR_H; /*!< (@ 0x0000085A) Sequence Channel 1 Descriptor-5 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC5CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC5CR_HL; /*!< (@ 0x0000085A) Sequence Channel 1 Descriptor-5 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC5CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC5CR_HH; /*!< (@ 0x0000085B) Sequence Channel 1 Descriptor-5 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC5CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC5DR; /*!< (@ 0x0000085C) Sequence Channel 1 Descriptor-5 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC5DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC5DR_L; /*!< (@ 0x0000085C) Sequence Channel 1 Descriptor-5 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC5DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC5DR_LL; /*!< (@ 0x0000085C) Sequence Channel 1 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC5DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC5DR_LH; /*!< (@ 0x0000085D) Sequence Channel 1 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC5DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC5DR_HL; /*!< (@ 0x0000085E) Sequence Channel 1 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC5DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC5DR_HH; /*!< (@ 0x0000085F) Sequence Channel 1 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC5DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC6AR; /*!< (@ 0x00000860) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC6AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC6AR_L; /*!< (@ 0x00000860) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC6AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC6AR_LL; /*!< (@ 0x00000860) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC6AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC6AR_LH; /*!< (@ 0x00000861) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC6AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC6AR_H; /*!< (@ 0x00000862) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC6AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC6AR_HL; /*!< (@ 0x00000862) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC6AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC6AR_HH; /*!< (@ 0x00000863) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC6AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC6BR; /*!< (@ 0x00000864) Sequence Channel 1 Descriptor-6 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC6BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC6CR; /*!< (@ 0x00000868) Sequence Channel 1 Descriptor-6 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC6CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC6CR_L; /*!< (@ 0x00000868) Sequence Channel 1 Descriptor-6 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC6CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC6CR_LL; /*!< (@ 0x00000868) Sequence Channel 1 Descriptor-6 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC6CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC6CR_H; /*!< (@ 0x0000086A) Sequence Channel 1 Descriptor-6 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC6CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC6CR_HL; /*!< (@ 0x0000086A) Sequence Channel 1 Descriptor-6 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC6CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC6CR_HH; /*!< (@ 0x0000086B) Sequence Channel 1 Descriptor-6 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC6CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC6DR; /*!< (@ 0x0000086C) Sequence Channel 1 Descriptor-6 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC6DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC6DR_L; /*!< (@ 0x0000086C) Sequence Channel 1 Descriptor-6 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC6DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC6DR_LL; /*!< (@ 0x0000086C) Sequence Channel 1 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC6DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC6DR_LH; /*!< (@ 0x0000086D) Sequence Channel 1 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC6DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC6DR_HL; /*!< (@ 0x0000086E) Sequence Channel 1 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC6DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC6DR_HH; /*!< (@ 0x0000086F) Sequence Channel 1 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC6DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC7AR; /*!< (@ 0x00000870) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC7AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC7AR_L; /*!< (@ 0x00000870) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC7AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC7AR_LL; /*!< (@ 0x00000870) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC7AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC7AR_LH; /*!< (@ 0x00000871) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC7AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC7AR_H; /*!< (@ 0x00000872) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC7AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC7AR_HL; /*!< (@ 0x00000872) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC7AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC7AR_HH; /*!< (@ 0x00000873) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC7AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC7BR; /*!< (@ 0x00000874) Sequence Channel 1 Descriptor-7 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC7BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC7CR; /*!< (@ 0x00000878) Sequence Channel 1 Descriptor-7 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC7CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC7CR_L; /*!< (@ 0x00000878) Sequence Channel 1 Descriptor-7 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC7CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC7CR_LL; /*!< (@ 0x00000878) Sequence Channel 1 Descriptor-7 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC7CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC7CR_H; /*!< (@ 0x0000087A) Sequence Channel 1 Descriptor-7 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC7CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC7CR_HL; /*!< (@ 0x0000087A) Sequence Channel 1 Descriptor-7 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC7CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC7CR_HH; /*!< (@ 0x0000087B) Sequence Channel 1 Descriptor-7 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC7CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC7DR; /*!< (@ 0x0000087C) Sequence Channel 1 Descriptor-7 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC7DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC7DR_L; /*!< (@ 0x0000087C) Sequence Channel 1 Descriptor-7 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC7DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC7DR_LL; /*!< (@ 0x0000087C) Sequence Channel 1 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC7DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC7DR_LH; /*!< (@ 0x0000087D) Sequence Channel 1 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC7DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC7DR_HL; /*!< (@ 0x0000087E) Sequence Channel 1 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC7DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC7DR_HH; /*!< (@ 0x0000087F) Sequence Channel 1 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC7DR_HH_b; + }; + }; + }; +} R_MIPI_DSI_Type; /*!< Size = 2176 (0x880) */ + +/* =========================================================================================================================== */ +/* ================ R_MRMS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief MRAM Control (R_MRMS) + */ + +typedef struct /*!< (@ 0x4013C000) R_MRMS Structure */ +{ + union + { + __IOM uint8_t MRCPFB; /*!< (@ 0x00000000) Code MRAM Pre-Fetch Buffer Enable Register */ + + struct + { + __IOM uint8_t MPFBEN : 1; /*!< [0..0] MRAM Pre-Fetch Buffer enable. */ + uint8_t : 7; + } MRCPFB_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t MRCFREQ; /*!< (@ 0x00000004) Code MRAM Frequency Notifications Register */ + + struct + { + __IOM uint32_t MRCMHZ : 10; /*!< [9..0] Setting the operating frequency in the order of MHz */ + uint32_t : 14; + __IOM uint32_t KEY : 8; /*!< [31..24] Key Code */ + } MRCFREQ_b; + }; + + union + { + __IOM uint32_t MREFREQ; /*!< (@ 0x00000008) Extra MRAM Frequency Notifications Register */ + + struct + { + __IOM uint32_t MREMHZ : 8; /*!< [7..0] Setting the operating frequency in the order of MHz */ + uint32_t : 16; + __IOM uint32_t KEY : 8; /*!< [31..24] Key Code */ + } MREFREQ_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint16_t MRCDECC; /*!< (@ 0x00000010) Code MRAM ECC Decoder Control Register */ + + struct + { + __IOM uint16_t DECDISC : 1; /*!< [0..0] MRC ECC Decoder disable */ + __IOM uint16_t ECCSELC : 1; /*!< [1..1] MRC ECC Data select */ + uint16_t : 6; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MRCDECC_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t MRCRAEINT; /*!< (@ 0x00000014) Code MRAM Read Access Error Interrupt Enable + * Register */ + + struct + { + __IOM uint8_t INTENBDC : 1; /*!< [0..0] MRC DEC error interrupt enable. */ + __IOM uint8_t INTENBTC : 1; /*!< [1..1] MRC TED error interrupt enable. */ + uint8_t : 6; + } MRCRAEINT_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + + union + { + __IOM uint8_t MRCRAES; /*!< (@ 0x00000018) Code MRAM Read Access Error Status Register */ + + struct + { + __IOM uint8_t DECERRC : 1; /*!< [0..0] MRC DEC error detected. */ + __IOM uint8_t TEDERRC : 1; /*!< [1..1] MRC TED error detected. */ + uint8_t : 6; + } MRCRAES_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IM uint32_t MRCRTEA; /*!< (@ 0x0000001C) Code MRAM TED Error Address Register */ + + struct + { + uint32_t : 5; + __IM uint32_t MRCRTEA : 27; /*!< [31..5] MRC read access TED error Address. */ + } MRCRTEA_b; + }; + + union + { + __IM uint32_t MRCRDEA; /*!< (@ 0x00000020) Code MRAM DEC Error Address Register */ + + struct + { + uint32_t : 5; + __IM uint32_t MRCRDEA : 27; /*!< [31..5] MRC read access DEC error Address. */ + } MRCRDEA_b; + }; + __IM uint32_t RESERVED8[4]; + + union + { + __IOM uint8_t MRERAINT; /*!< (@ 0x00000034) Extra MRAM Read Access Error Interrupt Enable + * Register */ + + struct + { + __IOM uint8_t INTENBDE : 1; /*!< [0..0] MRE DEC error interrupt enable. */ + __IOM uint8_t INTENBTE : 1; /*!< [1..1] MRE TED error interrupt enable. */ + uint8_t : 6; + } MRERAINT_b; + }; + __IM uint8_t RESERVED9; + __IM uint16_t RESERVED10; + + union + { + __IOM uint8_t MRERAES; /*!< (@ 0x00000038) Extra MRAM Read Access Error Status Register */ + + struct + { + __IOM uint8_t DECERRE : 1; /*!< [0..0] MRE DEC error detected. */ + __IOM uint8_t TEDERRE : 1; /*!< [1..1] MRE TED error detected. */ + uint8_t : 6; + } MRERAES_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IM uint32_t MRERTEA; /*!< (@ 0x0000003C) Extra MRAM TED Error Address Register */ + + struct + { + uint32_t : 4; + __IM uint32_t MRERTEA : 28; /*!< [31..4] MRE read access TED error Address. */ + } MRERTEA_b; + }; + + union + { + __IM uint32_t MRERDEA; /*!< (@ 0x00000040) Extra MRAM DEC Error Address Register */ + + struct + { + uint32_t : 4; + __IM uint32_t MRERDEA : 28; /*!< [31..4] MRE read access DEC error Address. */ + } MRERDEA_b; + }; + __IM uint32_t RESERVED13[47]; + + union + { + __IOM uint16_t MSAR; /*!< (@ 0x00000100) MRAM Security Attribution Register */ + + struct + { + __IOM uint16_t MREECCSA : 1; /*!< [0..0] Extra MRAM ECC Register Security Attribution */ + __IOM uint16_t MREFREQSA : 1; /*!< [1..1] MREFREQ register Security Attribution */ + __IOM uint16_t MRCECCSA : 1; /*!< [2..2] Code MRAM ECC Register Security Attribution */ + __IOM uint16_t MRCFREQSA : 1; /*!< [3..3] MRCFREQ register Security Attribution */ + __IOM uint16_t MPFBENSA : 1; /*!< [4..4] MRCPFB register Security Attribution */ + uint16_t : 4; + __IOM uint16_t MACICMISA : 1; /*!< [9..9] MACI Command Issuing Security Attribution */ + __IOM uint16_t MACICMRSA : 1; /*!< [10..10] MACI Command Registers Security Attribution */ + __IOM uint16_t MACITRSA : 1; /*!< [11..11] MACI Transfer Security Attribution */ + uint16_t : 1; + __IOM uint16_t MRCPSA : 1; /*!< [13..13] Code MRAM Program Register Security Attribution */ + __IOM uint16_t MREPSEQSA : 1; /*!< [14..14] EPSEQ Area Register Security Attribution */ + __IOM uint16_t MRCPSEQSA : 1; /*!< [15..15] CPSEQ Area Register Security Attribution */ + } MSAR_b; + }; + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[191]; + + union + { + __IM uint8_t MREZS; /*!< (@ 0x00000400) Extra MRAM Zeroization Status Register */ + + struct + { + __IM uint8_t WHUKZF : 1; /*!< [0..0] W-HUK Zero Flag Status. */ + __IM uint8_t WHUKEXE : 1; /*!< [1..1] W-HUK Zeroization Executing Status */ + uint8_t : 6; + } MREZS_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint16_t MREZC; /*!< (@ 0x00000404) Extra MRAM Zeroization Control Register */ + + struct + { + __IOM uint16_t WHUKZE : 3; /*!< [2..0] W-KUK zeroization execute. */ + uint16_t : 5; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MREZC_b; + }; + __IM uint16_t RESERVED18; + __IM uint32_t RESERVED19[1794]; + + union + { + __IOM uint8_t MASTAT; /*!< (@ 0x00002010) Extra MRAM Access Status Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t MREAE : 1; /*!< [3..3] Extra MRAM Access Error */ + __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ + uint8_t : 3; + } MASTAT_b; + }; + __IM uint8_t RESERVED20; + __IM uint16_t RESERVED21; + + union + { + __IOM uint8_t MPAEINT; /*!< (@ 0x00002014) Extra MRAM Access Error Interrupt Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t MREAEIE : 1; /*!< [3..3] MRE Access Error Interrupt Enable */ + __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ + uint8_t : 3; + } MPAEINT_b; + }; + __IM uint8_t RESERVED22; + __IM uint16_t RESERVED23; + + union + { + __IOM uint8_t MRDYIE; /*!< (@ 0x00002018) Extra MRAM Ready Interrupt Enable Register */ + + struct + { + __IOM uint8_t MRDYIE : 1; /*!< [0..0] MRDY Interrupt Enable */ + uint8_t : 7; + } MRDYIE_b; + }; + __IM uint8_t RESERVED24; + __IM uint16_t RESERVED25; + __IM uint32_t RESERVED26[5]; + + union + { + __IOM uint32_t MSADDR; /*!< (@ 0x00002030) MACI Command Start Address Register */ + + struct + { + __IOM uint32_t MSADDR : 32; /*!< [31..0] Start Address for MACI Command Processing */ + } MSADDR_b; + }; + __IM uint32_t RESERVED27[5]; + + union + { + __IOM uint8_t MCNTSELR; /*!< (@ 0x00002048) MRAM Counter Select Register */ + + struct + { + __IOM uint8_t CNTSEL : 3; /*!< [2..0] Counter Select */ + uint8_t : 5; + } MCNTSELR_b; + }; + __IM uint8_t RESERVED28; + __IM uint16_t RESERVED29; + + union + { + __IM uint32_t MCNTDTR0; /*!< (@ 0x0000204C) MRAM Counter Data Register 0 */ + + struct + { + __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data */ + } MCNTDTR0_b; + }; + + union + { + __IM uint32_t MCNTDTR1; /*!< (@ 0x00002050) MRAM Counter Data Register 1 */ + + struct + { + __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data */ + } MCNTDTR1_b; + }; + __IM uint32_t RESERVED30[3]; + + union + { + __IOM uint16_t MCTRCNTR; /*!< (@ 0x00002060) MRAM Configuration Update Transfer Control Register */ + + struct + { + __IOM uint16_t TRTRG : 1; /*!< [0..0] Transfer Start Trigger */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MCTRCNTR_b; + }; + __IM uint16_t RESERVED31; + + union + { + __IOM uint8_t MCTRLSR; /*!< (@ 0x00002064) MRAM Configuration Update Transfer List Select + * Register */ + + struct + { + __IOM uint8_t TRLIST : 3; /*!< [2..0] Configuration Update Transfer List */ + uint8_t : 5; + } MCTRLSR_b; + }; + __IM uint8_t RESERVED32; + __IM uint16_t RESERVED33; + __IM uint32_t RESERVED34; + + union + { + __IM uint8_t MCTRSTATR; /*!< (@ 0x0000206C) MRAM Configuration Update Transfer Status Register */ + + struct + { + __IM uint8_t TRBUSY : 1; /*!< [0..0] Transfer Busy Status */ + uint8_t : 1; + __IM uint8_t TRMD : 1; /*!< [2..2] Transfer Mode Setting Status */ + uint8_t : 5; + } MCTRSTATR_b; + }; + __IM uint8_t RESERVED35; + __IM uint16_t RESERVED36; + __IM uint32_t RESERVED37[4]; + + union + { + __IM uint32_t MSTATR; /*!< (@ 0x00002080) Extra MRAM Status Register */ + + struct + { + uint32_t : 5; + __IM uint32_t CFGSETERR : 1; /*!< [5..5] Configuration Set Error Flag */ + uint32_t : 6; + __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ + uint32_t : 1; + __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Error */ + __IM uint32_t MRDY : 1; /*!< [15..15] MRE Ready */ + uint32_t : 3; + __IM uint32_t TZFERR : 1; /*!< [19..19] TrustZone Filter Error */ + __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ + __IM uint32_t SECERR : 1; /*!< [21..21] Security Error */ + uint32_t : 1; + __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ + uint32_t : 8; + } MSTATR_b; + }; + + union + { + __IOM uint16_t MENTRYR; /*!< (@ 0x00002084) Extra MRAM Program Mode Entry Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t MENTRY : 1; /*!< [7..7] Extra MRAM Mode Entry */ + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MENTRYR_b; + }; + __IM uint16_t RESERVED38; + __IM uint32_t RESERVED39; + + union + { + __IOM uint16_t MSUINITR; /*!< (@ 0x0000208C) Extra MRAM Sequencer Set-Up Initialization Register */ + + struct + { + __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MSUINITR_b; + }; + __IM uint16_t RESERVED40; + __IM uint32_t RESERVED41[4]; + + union + { + __IM uint16_t MCMDR; /*!< (@ 0x000020A0) MACI Command Register */ + + struct + { + __IM uint16_t PCMDR : 8; /*!< [7..0] Pre-command Flag */ + __IM uint16_t CMDR : 8; /*!< [15..8] Command Flag */ + } MCMDR_b; + }; + __IM uint16_t RESERVED42; + __IM uint32_t RESERVED43[14]; + + union + { + __IM uint32_t MSUASMON; /*!< (@ 0x000020DC) MRAM Start-Up Area Select Monitor Register */ + + struct + { + uint32_t : 15; + __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programing to set the Start-Up Area + * Select setting */ + uint32_t : 13; + __IM uint32_t BTSIZE : 2; /*!< [30..29] Size of Start-Up area select for Boot Swap */ + __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ + } MSUASMON_b; + }; + __IM uint32_t RESERVED44[2]; + + union + { + __IOM uint16_t MSUACR; /*!< (@ 0x000020E8) MRAM Start-Up Area Control Register */ + + struct + { + __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select */ + uint16_t : 6; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MSUACR_b; + }; + __IM uint16_t RESERVED45; + __IM uint32_t RESERVED46[453]; + + union + { + __IOM uint8_t MRPSC; /*!< (@ 0x00002800) MRAM Program Speed Control Register */ + + struct + { + __IOM uint8_t MHSPEN : 1; /*!< [0..0] MRAM high speed program mode enable. */ + uint8_t : 7; + } MRPSC_b; + }; + __IM uint8_t RESERVED47; + __IM uint16_t RESERVED48; + __IM uint32_t RESERVED49[511]; + + union + { + __IOM uint16_t MRCPC0; /*!< (@ 0x00003000) Code MRAM Program Control Register */ + + struct + { + __IOM uint16_t MRCPNEN : 1; /*!< [0..0] Code MRAM Program Enable for Non-secure */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MRCPC0_b; + }; + __IM uint16_t RESERVED50; + + union + { + __IOM uint16_t MRCPC1; /*!< (@ 0x00003004) Code MRAM Program Control for Secure Register */ + + struct + { + __IOM uint16_t MRCPSEN : 1; /*!< [0..0] Code MRAM Program Enable for Secure */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MRCPC1_b; + }; + __IM uint16_t RESERVED51; + + union + { + __IOM uint16_t MRCBPROT0; /*!< (@ 0x00003008) Code MRAM Block Protection Register */ + + struct + { + __IOM uint16_t BPCN0 : 1; /*!< [0..0] Code MRAM Block Protection Cancel for Non-secure */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MRCBPROT0_b; + }; + __IM uint16_t RESERVED52; + + union + { + __IOM uint16_t MRCBPROT1; /*!< (@ 0x0000300C) Code MRAM Block Protection for Secure Register */ + + struct + { + __IOM uint16_t BPCN1 : 1; /*!< [0..0] Code MRAM Block Protection Cancel for Secure */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MRCBPROT1_b; + }; + __IM uint16_t RESERVED53; + + union + { + __IOM uint8_t MRCPS; /*!< (@ 0x00003010) Code MRAM Program Status Register */ + + struct + { + __IOM uint8_t PRGERRC : 1; /*!< [0..0] Programming Error */ + __IOM uint8_t ECCERRC : 1; /*!< [1..1] ECC Error */ + uint8_t : 3; + __IM uint8_t ABUFEMP : 1; /*!< [5..5] Address Buffer Empty */ + __IM uint8_t ABUFFULL : 1; /*!< [6..6] Address Buffer Full */ + __IM uint8_t PRGBSYC : 1; /*!< [7..7] Code MRAM Program Busy */ + } MRCPS_b; + }; + __IM uint8_t RESERVED54; + __IM uint16_t RESERVED55; + + union + { + __IOM uint8_t MRCPAEINT; /*!< (@ 0x00003014) Code MRAM Program Access Error Interrupt Enable + * Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t MRCAEIE : 1; /*!< [7..7] Code MRAM Program Access Error Interrupt Enable */ + } MRCPAEINT_b; + }; + __IM uint8_t RESERVED56; + __IM uint16_t RESERVED57; + + union + { + __IM uint32_t MRCPEA; /*!< (@ 0x00003018) Code MRAM Program Error Address Register */ + + struct + { + uint32_t : 5; + __IM uint32_t MCPEA : 27; /*!< [31..5] Code MRAM Program Error Address */ + } MRCPEA_b; + }; + __IM uint32_t RESERVED58[5]; + + union + { + __IOM uint16_t MRCFLR; /*!< (@ 0x00003030) Code MRAM Flush Register */ + + struct + { + __IOM uint16_t MRCFL : 1; /*!< [0..0] Flush Write Data Buffer for code MRAM */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MRCFLR_b; + }; + __IM uint16_t RESERVED59; + __IM uint32_t RESERVED60[500]; + + union + { + __IOM uint16_t MRCEECC; /*!< (@ 0x00003804) Code MRAM ECC Encoder Control Register */ + + struct + { + __IOM uint16_t ECCBYPC : 1; /*!< [0..0] Code MRAM ECC encoder outputs bypass enable */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MRCEECC_b; + }; + __IM uint16_t RESERVED61; +} R_MRMS_Type; /*!< Size = 14344 (0x3808) */ + +/* =========================================================================================================================== */ +/* ================ R_NPU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Neural Processing Unit (R_NPU) + */ + +typedef struct /*!< (@ 0x40140000) R_NPU Structure */ +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) ID register */ + + struct + { + __IM uint32_t version_status : 4; /*!< [3..0] This is the version of the product */ + __IM uint32_t version_minor : 4; /*!< [7..4] This is the n for the P-part of an RnPn release number */ + __IM uint32_t version_major : 4; /*!< [11..8] This is the n for the R-part of an RnPn release number */ + __IM uint32_t product_major : 4; /*!< [15..12] This is the X-part of the ML00X product number */ + __IM uint32_t arch_patch_rev : 4; /*!< [19..16] This is the patch number of the architecture version + * a.b */ + __IM uint32_t arch_minor_rev : 8; /*!< [27..20] This is the minor architecture version number, b in + * the architecture version a.b */ + __IM uint32_t arch_major_rev : 4; /*!< [31..28] This is the major architecture version number, a in + * the architecture version a.b */ + } ID_b; + }; + + union + { + __IM uint32_t STATUS; /*!< (@ 0x00000004) Register describes the current operating status + * of the NPU */ + + struct + { + __IM uint32_t state : 1; /*!< [0..0] NPU state; 0 = Stopped, 1 = Running */ + __IM uint32_t irq_raised : 1; /*!< [1..1] Raw IRQ status: 0 = IRQ not raised, 1 = IRQ raised. IRQ + * is cleared using command register bit 1. */ + __IM uint32_t bus_status : 1; /*!< [2..2] 0=OK, 1=Bus abort detected and processing halted (the + * NPU has reached IDLE state and does not start to process + * any more commands/AXI transactions). Can only be cleared + * by a reset. */ + __IM uint32_t reset_status : 1; /*!< [3..3] Reset is ongoing and only this register can be read (other + * registers read as 0 and writes are ignored). A value of + * 0 means the NPU is not being reset and can be accessed + * as normal. */ + __IM uint32_t cmd_parse_error : 1; /*!< [4..4] 0=No error, 1=Command-stream parsing error detected. + * Can only be cleared by a reset. */ + __IM uint32_t cmd_end_reached : 1; /*!< [5..5] 0=Not reached, 1=Reached. Cleared by writing QBASE or + * QSIZE when the NPU is in stopped state. */ + __IM uint32_t pmu_irq_raised : 1; /*!< [6..6] 0=No PMU IRQ, 1=PMU IRQ raised. Cleared by using command + * register bit 1 */ + uint32_t : 1; + __IM uint32_t ecc_fault : 1; /*!< [8..8] ECC state for internal RAMs: 0=no fault, 1=ECC fault + * signalled. Can only be cleared by reset. */ + uint32_t : 2; + __IM uint32_t faulting_interface : 1; /*!< [11..11] Faulting interface on bus abort. 0=AXI-M0, 1=AXI-M1 */ + __IM uint32_t faulting_channel : 4; /*!< [15..12] Faulting channel on a bus abort. Read: 0=Cmd, 1=IFM, + * 2=Weights, 3=Scale+Bias, 4=Mem2Mem; Write: 8=OFM, 9=Mem2Mem */ + __IM uint32_t irq_history_mask : 16; /*!< [31..16] IRQ History mask */ + } STATUS_b; + }; + + union + { + __IOM uint32_t CMD; /*!< (@ 0x00000008) Command register, reads as last written command */ + + struct + { + __IOM uint32_t transition_to_running_state : 1; /*!< [0..0] Write 1 to transition the NPU to running state. Writing + * 0 has no effect */ + __IOM uint32_t clear_irq : 1; /*!< [1..1] Write 1 to clear the IRQ status in the STATUS register. + * Writing 0 has no effect */ + __IOM uint32_t clock_q_enable : 1; /*!< [2..2] Write 1 to this bit to enable clock off using the Clock + * Q-interface and enable the main clock gate */ + __IOM uint32_t power_q_enable : 1; /*!< [3..3] Write 1 to this bit to enable power off using the Power + * Q-interface */ + uint32_t : 12; + __IOM uint32_t clear_irq_history : 16; /*!< [31..16] Clears the IRQ history mask */ + } CMD_b; + }; + + union + { + __IOM uint32_t RESET; /*!< (@ 0x0000000C) Request Reset and new security mode */ + + struct + { + __IOM uint32_t pending_CPL : 1; /*!< [0..0] Current privilege level: 0=User, 1=Privileged */ + __IOM uint32_t pending_CSL : 1; /*!< [1..1] Current security level: 0=Secure, 1=Non secure */ + uint32_t : 30; + } RESET_b; + }; + + union + { + __IOM uint32_t QBASE0; /*!< (@ 0x00000010) Base address of Command-queue bits[31:0]. The + * address is 4-byte-aligned */ + + struct + { + __IOM uint32_t QBASE0 : 32; /*!< [31..0] The 4-byte-aligned lower bytes of the base address value + * for the command stream */ + } QBASE0_b; + }; + + union + { + __IOM uint32_t QBASE1; /*!< (@ 0x00000014) Address extension bits[47:32] for queue base */ + + struct + { + __IOM uint32_t QBASE1 : 32; /*!< [31..0] The 4-byte-aligned upper bytes of the base address value + * for the command stream */ + } QBASE1_b; + }; + + union + { + __IM uint32_t QREAD; /*!< (@ 0x00000018) Read offset in the command stream in bytes. Multiples + * of 4 in the range 0-16 MB */ + + struct + { + __IM uint32_t QREAD : 32; /*!< [31..0] The read offset of the current command under execution */ + } QREAD_b; + }; + + union + { + __IOM uint32_t QCONFIG; /*!< (@ 0x0000001C) AXI configuration for the command stream in the + * range 0-3. Same encoding as for REGIONCFG */ + + struct + { + __IOM uint32_t QCONFIG : 32; /*!< [31..0] AXI configuration for the command stream in the range + * 0-3 */ + } QCONFIG_b; + }; + + union + { + __IOM uint32_t QSIZE; /*!< (@ 0x00000020) Size of the command stream in bytes. Multiples + * of 4 in the range 0-16 MB */ + + struct + { + __IOM uint32_t QSIZE : 32; /*!< [31..0] Size of the next command stream to be executed by the + * NPU */ + } QSIZE_b; + }; + + union + { + __IM uint32_t PROT; /*!< (@ 0x00000024) Protection level configured for the NPU when + * acting as an AXI master */ + + struct + { + __IM uint32_t active_CPL : 1; /*!< [0..0] Current privilege level: 0=User, 1=Privileged */ + __IM uint32_t active_CSL : 1; /*!< [1..1] Current security level: 0=Secure, 1=Non-secure */ + uint32_t : 30; + } PROT_b; + }; + + union + { + __IM uint32_t CONFIG; /*!< (@ 0x00000028) RTL configuration */ + + struct + { + __IM uint32_t macs_per_cc : 4; /*!< [3..0] The log2(macs/clock cycle). Valid encoding range is 5-8 + * for 32-256 MACs/clock cycle. */ + __IM uint32_t cmd_stream_version : 4; /*!< [7..4] Command-stream version accepted by this NPU. */ + __IM uint32_t shram_size : 8; /*!< [15..8] Size in KB of SHRAM in the range 8-48. */ + uint32_t : 11; + __IM uint32_t custom_dma : 1; /*!< [27..27] Custom DMA configuration */ + __IM uint32_t product : 4; /*!< [31..28] Product configuration */ + } CONFIG_b; + }; + + union + { + __IOM uint32_t LOCK; /*!< (@ 0x0000002C) Lock register. This register is designed for + * driver use and does not affect NPU functionality */ + + struct + { + __IOM uint32_t LOCK : 32; /*!< [31..0] 32-bit value for the LOCK configuration */ + } LOCK_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t REGIONCFG; /*!< (@ 0x0000003C) Base pointer configuration. Bits[2*k+1:2*k] give + * the memory type for REGION[k] */ + + struct + { + __IOM uint32_t region0 : 2; /*!< [1..0] Bits for the Region0 configuration */ + __IOM uint32_t region1 : 2; /*!< [3..2] Bits for the Region1 configuration */ + __IOM uint32_t region2 : 2; /*!< [5..4] Bits for the Region2 configuration */ + __IOM uint32_t region3 : 2; /*!< [7..6] Bits for the Region3 configuration */ + __IOM uint32_t region4 : 2; /*!< [9..8] Bits for the Region4 configuration */ + __IOM uint32_t region5 : 2; /*!< [11..10] Bits for the Region5 configuration */ + __IOM uint32_t region6 : 2; /*!< [13..12] Bits for the Region6 configuration */ + __IOM uint32_t region7 : 2; /*!< [15..14] Bits for the Region7 configuration */ + uint32_t : 16; + } REGIONCFG_b; + }; + + union + { + __IOM uint32_t AXI_LIMIT0; /*!< (@ 0x00000040) AXI limits for port 0 counter 0 */ + + struct + { + __IOM uint32_t max_beats : 2; /*!< [1..0] Burst-split alignment: 0=64 bytes, 1=128 bytes, 2=256 + * bytes, 3=reserved */ + uint32_t : 2; + __IOM uint32_t memtype : 4; /*!< [7..4] Memtype */ + uint32_t : 8; + __IOM uint32_t max_outstanding_read_m1 : 8; /*!< [23..16] Maximum number of outstanding AXI read transactions + * - 1 in range 0-31 */ + __IOM uint32_t max_outstanding_write_m1 : 8; /*!< [31..24] Maximum number of outstanding AXI write transactions + * - 1 in range 0-15 */ + } AXI_LIMIT0_b; + }; + + union + { + __IOM uint32_t AXI_LIMIT1; /*!< (@ 0x00000044) AXI limits for port 0 counter 1 */ + + struct + { + __IOM uint32_t max_beats : 2; /*!< [1..0] Burst-split alignment: 0=64 bytes, 1=128 bytes, 2=256 + * bytes, 3=reserved */ + uint32_t : 2; + __IOM uint32_t memtype : 4; /*!< [7..4] Memtype */ + uint32_t : 8; + __IOM uint32_t max_outstanding_read_m1 : 8; /*!< [23..16] Maximum number of outstanding AXI read transactions + * - 1 in range 0-31 */ + __IOM uint32_t max_outstanding_write_m1 : 8; /*!< [31..24] Maximum number of outstanding AXI write transactions + * - 1 in range 0-15 */ + } AXI_LIMIT1_b; + }; + + union + { + __IOM uint32_t AXI_LIMIT2; /*!< (@ 0x00000048) AXI limits for port 1 counter 2 */ + + struct + { + __IOM uint32_t max_beats : 2; /*!< [1..0] Burst-split alignment: 0=64 bytes, 1=128 bytes, 2=256 + * bytes, 3=reserved */ + uint32_t : 2; + __IOM uint32_t memtype : 4; /*!< [7..4] Memtype */ + uint32_t : 8; + __IOM uint32_t max_outstanding_read_m1 : 8; /*!< [23..16] Maximum number of outstanding AXI read transactions + * - 1 in range 0-31 */ + __IOM uint32_t max_outstanding_write_m1 : 8; /*!< [31..24] Maximum number of outstanding AXI write transactions + * - 1 in range 0-15 */ + } AXI_LIMIT2_b; + }; + + union + { + __IOM uint32_t AXI_LIMIT3; /*!< (@ 0x0000004C) AXI limits for port 1 counter 3 */ + + struct + { + __IOM uint32_t max_beats : 2; /*!< [1..0] Burst-split alignment: 0=64 bytes, 1=128 bytes, 2=256 + * bytes, 3=reserved */ + uint32_t : 2; + __IOM uint32_t memtype : 4; /*!< [7..4] Memtype */ + uint32_t : 8; + __IOM uint32_t max_outstanding_read_m1 : 8; /*!< [23..16] Maximum number of outstanding AXI read transactions + * - 1 in range 0-31 */ + __IOM uint32_t max_outstanding_write_m1 : 8; /*!< [31..24] Maximum number of outstanding AXI write transactions + * - 1 in range 0-15 */ + } AXI_LIMIT3_b; + }; + __IM uint32_t RESERVED1[12]; + + union + { + __IOM uint32_t BASEP0; /*!< (@ 0x00000080) Lower 32 bits of the Base pointer for region + * index 0 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP0_b; + }; + + union + { + __IOM uint32_t BASEP1; /*!< (@ 0x00000084) Upper 32 bits of the Base pointer for region + * index 0 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP1_b; + }; + + union + { + __IOM uint32_t BASEP2; /*!< (@ 0x00000088) Lower 32 bits of the Base pointer for region + * index 1 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP2_b; + }; + + union + { + __IOM uint32_t BASEP3; /*!< (@ 0x0000008C) Upper 32 bits of the Base pointer for region + * index 1 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP3_b; + }; + + union + { + __IOM uint32_t BASEP4; /*!< (@ 0x00000090) Lower 32 bits of the Base pointer for region + * index 2 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP4_b; + }; + + union + { + __IOM uint32_t BASEP5; /*!< (@ 0x00000094) Upper 32 bits of the Base pointer for region + * index 2 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP5_b; + }; + + union + { + __IOM uint32_t BASEP6; /*!< (@ 0x00000098) Lower 32 bits of the Base pointer for region + * index 3 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP6_b; + }; + + union + { + __IOM uint32_t BASEP7; /*!< (@ 0x0000009C) Upper 32 bits of the Base pointer for region + * index 3 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP7_b; + }; + + union + { + __IOM uint32_t BASEP8; /*!< (@ 0x000000A0) Lower 32 bits of the Base pointer for region + * index 4 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP8_b; + }; + + union + { + __IOM uint32_t BASEP9; /*!< (@ 0x000000A4) Upper 32 bits of the Base pointer for region + * index 4 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP9_b; + }; + + union + { + __IOM uint32_t BASEP10; /*!< (@ 0x000000A8) Lower 32 bits of the Base pointer for region + * index 5 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP10_b; + }; + + union + { + __IOM uint32_t BASEP11; /*!< (@ 0x000000AC) Upper 32 bits of the Base pointer for region + * index 5 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP11_b; + }; + + union + { + __IOM uint32_t BASEP12; /*!< (@ 0x000000B0) Lower 32 bits of the Base pointer for region + * index 6 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP12_b; + }; + + union + { + __IOM uint32_t BASEP13; /*!< (@ 0x000000B4) Upper 32 bits of the Base pointer for region + * index 6 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP13_b; + }; + + union + { + __IOM uint32_t BASEP14; /*!< (@ 0x000000B8) Lower 32 bits of the Base pointer for region + * index 7 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP14_b; + }; + + union + { + __IOM uint32_t BASEP15; /*!< (@ 0x000000BC) Upper 32 bits of the Base pointer for region + * index 7 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP15_b; + }; + __IM uint32_t RESERVED2[48]; + + union + { + __IOM uint32_t PMCR; /*!< (@ 0x00000180) PMU master control register */ + + struct + { + __IOM uint32_t cnt_en : 1; /*!< [0..0] Enable counter */ + __IOM uint32_t event_cnt_rst : 1; /*!< [1..1] Reset event counter */ + __IOM uint32_t cycle_cnt_rst : 1; /*!< [2..2] Reset cycle counter */ + __IOM uint32_t mask_en : 1; /*!< [3..3] PMU can be enabled/disabled by command stream operationNPU_OP_PMU_MASK */ + uint32_t : 7; + __IOM uint32_t num_event_cnt : 5; /*!< [15..11] Number of event counters available for performance + * measurement */ + uint32_t : 16; + } PMCR_b; + }; + + union + { + __IOM uint32_t PMCNTENSET; /*!< (@ 0x00000184) Count-enable set register */ + + struct + { + __IOM uint32_t EVENT_CNT_0 : 1; /*!< [0..0] Event-counter enable bit for PMU_EVCNTR0 */ + __IOM uint32_t EVENT_CNT_1 : 1; /*!< [1..1] Event-counter enable bit for PMU_EVCNTR1 */ + __IOM uint32_t EVENT_CNT_2 : 1; /*!< [2..2] Event-counter enable bit for PMU_EVCNTR2 */ + __IOM uint32_t EVENT_CNT_3 : 1; /*!< [3..3] Event-counter enable bit for PMU_EVCNTR3 */ + uint32_t : 27; + __IOM uint32_t CYCLE_CNT : 1; /*!< [31..31] PMCCNTR enable bit */ + } PMCNTENSET_b; + }; + + union + { + __IOM uint32_t PMCNTENCLR; /*!< (@ 0x00000188) Count-enable clear register */ + + struct + { + __IOM uint32_t EVENT_CNT_0 : 1; /*!< [0..0] Event-counter disable bit for PMU_EVCNTR0 */ + __IOM uint32_t EVENT_CNT_1 : 1; /*!< [1..1] Event-counter disable bit for PMU_EVCNTR1 */ + __IOM uint32_t EVENT_CNT_2 : 1; /*!< [2..2] Event-counter disable bit for PMU_EVCNTR2 */ + __IOM uint32_t EVENT_CNT_3 : 1; /*!< [3..3] Event-counter disable bit for PMU_EVCNTR3 */ + uint32_t : 27; + __IOM uint32_t CYCLE_CNT : 1; /*!< [31..31] PMCCNTR disable bit */ + } PMCNTENCLR_b; + }; + + union + { + __IOM uint32_t PMOVSSET; /*!< (@ 0x0000018C) Overflow-flag status set register */ + + struct + { + __IOM uint32_t EVENT_CNT_0_OVF : 1; /*!< [0..0] Event-counter overflow set bit for PMU_EVCNTR0 */ + __IOM uint32_t EVENT_CNT_1_OVF : 1; /*!< [1..1] Event-counter overflow set bit for PMU_EVCNTR1 */ + __IOM uint32_t EVENT_CNT_2_OVF : 1; /*!< [2..2] Event-counter overflow set bit for PMU_EVCNTR2 */ + __IOM uint32_t EVENT_CNT_3_OVF : 1; /*!< [3..3] Event-counter overflow set bit for PMU_EVCNTR3 */ + uint32_t : 27; + __IOM uint32_t CYCLE_CNT_OVF : 1; /*!< [31..31] PMCCNTR overflow set bit */ + } PMOVSSET_b; + }; + + union + { + __IOM uint32_t PMOVSCLR; /*!< (@ 0x00000190) Overflow-flag status clear register */ + + struct + { + __IOM uint32_t EVENT_CNT_0_OVF : 1; /*!< [0..0] Event-counter overflow clear bit for PMU_EVCNTR0 */ + __IOM uint32_t EVENT_CNT_1_OVF : 1; /*!< [1..1] Event-counter overflow clear bit for PMU_EVCNTR1 */ + __IOM uint32_t EVENT_CNT_2_OVF : 1; /*!< [2..2] Event-counter overflow clear bit for PMU_EVCNTR2 */ + __IOM uint32_t EVENT_CNT_3_OVF : 1; /*!< [3..3] Event-counter overflow clear bit for PMU_EVCNTR3 */ + uint32_t : 27; + __IOM uint32_t CYCLE_CNT_OVF : 1; /*!< [31..31] PMCCNTR overflow clear bit */ + } PMOVSCLR_b; + }; + + union + { + __IOM uint32_t PMINTSET; /*!< (@ 0x00000194) Interrupt-enable set register */ + + struct + { + __IOM uint32_t EVENT_CNT_0_INT : 1; /*!< [0..0] Event-counter overflow interrupt-request enable bit for + * PMU_EVCNTR0 */ + __IOM uint32_t EVENT_CNT_1_INT : 1; /*!< [1..1] Event-counter overflow interrupt-request enable bit for + * PMU_EVCNTR1 */ + __IOM uint32_t EVENT_CNT_2_INT : 1; /*!< [2..2] Event-counter overflow interrupt-request enable bit for + * PMU_EVCNTR2 */ + __IOM uint32_t EVENT_CNT_3_INT : 1; /*!< [3..3] Event-counter overflow interrupt-request enable bit for + * PMU_EVCNTR3 */ + uint32_t : 27; + __IOM uint32_t CYCLE_CNT_INT : 1; /*!< [31..31] PMCCNTR overflow interrupt-request enable bit */ + } PMINTSET_b; + }; + + union + { + __IOM uint32_t PMINTCLR; /*!< (@ 0x00000198) Interrupt-enable clear register */ + + struct + { + __IOM uint32_t EVENT_CNT_0_INT : 1; /*!< [0..0] Event-counter overflow interrupt-request disable bit + * for PMU_EVCNTR0 */ + __IOM uint32_t EVENT_CNT_1_INT : 1; /*!< [1..1] Event-counter overflow interrupt-request disable bit + * for PMU_EVCNTR1 */ + __IOM uint32_t EVENT_CNT_2_INT : 1; /*!< [2..2] Event-counter overflow interrupt-request disable bit + * for PMU_EVCNTR2 */ + __IOM uint32_t EVENT_CNT_3_INT : 1; /*!< [3..3] Event-counter overflow interrupt-request disable bit + * for PMU_EVCNTR3 */ + uint32_t : 27; + __IOM uint32_t CYCLE_CNT_INT : 1; /*!< [31..31] PMCCNTR overflow interrupt-request disable bit */ + } PMINTCLR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t PMCCNTR_LO; /*!< (@ 0x000001A0) Performance-monitor cycle count low register */ + + struct + { + __IOM uint32_t CYCLE_CNT_LO : 32; /*!< [31..0] Cycle count low */ + } PMCCNTR_LO_b; + }; + + union + { + __IOM uint32_t PMCCNTR_HI; /*!< (@ 0x000001A4) Performance-monitor cycle count high register */ + + struct + { + __IOM uint32_t CYCLE_CNT_HI : 32; /*!< [31..0] Cycle count high */ + } PMCCNTR_HI_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t PMCAXI_CHAN; /*!< (@ 0x000001AC) Set which AXI channel monitor */ + + struct + { + __IOM uint32_t CH_SEL : 4; /*!< [3..0] Specify the type of traffic for bandwidth or latency + * measurements (Read: 0=command traffic, 1=IFM traffic, 2=Weight + * traffic, 3=Scale+Bias, 4=Mem2Mem traffic - read direction; + * Write: 8=OFM traffic, 9=Mem2Mem traffic - write direction) */ + uint32_t : 4; + __IOM uint32_t AXI_CNT_SEL : 2; /*!< [9..8] Select AXI counter to monitor for latency measurements + * (0=AXI0 counter0, 1=AXI0 counter1, 2=AXI1 counter 2, 3=AXI1 + * counter3) */ + __IOM uint32_t BW_CH_SEL_EN : 1; /*!< [10..10] Enable bandwidth channel selector: 0=AXI bw events + * measured for all channels, 1=AXI bw events measured for + * channel specified by CH_SEL */ + uint32_t : 21; + } PMCAXI_CHAN_b; + }; + __IM uint32_t RESERVED5[84]; + + union + { + __IOM uint32_t PMU_EVCNTR0; /*!< (@ 0x00000300) Performance-monitor event counters 0 */ + + struct + { + __IOM uint32_t PMEVCNTR : 32; /*!< [31..0] Performance-monitor event counters. */ + } PMU_EVCNTR0_b; + }; + + union + { + __IOM uint32_t PMU_EVCNTR1; /*!< (@ 0x00000304) Performance-monitor event counters 1 */ + + struct + { + __IOM uint32_t PMEVCNTR : 32; /*!< [31..0] Performance-monitor event counters. */ + } PMU_EVCNTR1_b; + }; + + union + { + __IOM uint32_t PMU_EVCNTR2; /*!< (@ 0x00000308) Performance-monitor event counters 2 */ + + struct + { + __IOM uint32_t PMEVCNTR : 32; /*!< [31..0] Performance-monitor event counters. */ + } PMU_EVCNTR2_b; + }; + + union + { + __IOM uint32_t PMU_EVCNTR3; /*!< (@ 0x0000030C) Performance-monitor event counters 3 */ + + struct + { + __IOM uint32_t PMEVCNTR : 32; /*!< [31..0] Performance-monitor event counters. */ + } PMU_EVCNTR3_b; + }; + __IM uint32_t RESERVED6[28]; + + union + { + __IOM uint32_t PMU_EVTYPER0; /*!< (@ 0x00000380) Performance-monitor event-type control counters + * 0 */ + + struct + { + __IOM uint32_t EV_TYPE : 32; /*!< [31..0] Event type. */ + } PMU_EVTYPER0_b; + }; + + union + { + __IOM uint32_t PMU_EVTYPER1; /*!< (@ 0x00000384) Performance-monitor event-type control counters + * 1 */ + + struct + { + __IOM uint32_t EV_TYPE : 32; /*!< [31..0] Event type. */ + } PMU_EVTYPER1_b; + }; + + union + { + __IOM uint32_t PMU_EVTYPER2; /*!< (@ 0x00000388) Performance-monitor event-type control counters + * 2 */ + + struct + { + __IOM uint32_t EV_TYPE : 32; /*!< [31..0] Event type. */ + } PMU_EVTYPER2_b; + }; + + union + { + __IOM uint32_t PMU_EVTYPER3; /*!< (@ 0x0000038C) Performance-monitor event-type control counters + * 3 */ + + struct + { + __IOM uint32_t EV_TYPE : 32; /*!< [31..0] Event type. */ + } PMU_EVTYPER3_b; + }; + __IM uint32_t RESERVED7[784]; + + union + { + __IM uint32_t PID4; /*!< (@ 0x00000FD0) Peripheral ID byte 4 (Arm=code 4) */ + + struct + { + __IM uint32_t PID4 : 32; /*!< [31..0] Byte 4 of the Peripheral ID (Lower 8 bits valid) */ + } PID4_b; + }; + + union + { + __IM uint32_t PID5; /*!< (@ 0x00000FD4) Peripheral ID byte 5 (reserved) */ + + struct + { + __IM uint32_t PID5 : 32; /*!< [31..0] Byte 5 of the Peripheral ID (Lower 8 bits valid) */ + } PID5_b; + }; + + union + { + __IM uint32_t PID6; /*!< (@ 0x00000FD8) Peripheral ID byte 6 (reserved) */ + + struct + { + __IM uint32_t PID6 : 32; /*!< [31..0] Byte 6 of the Peripheral ID (Lower 8 bits valid) */ + } PID6_b; + }; + + union + { + __IM uint32_t PID7; /*!< (@ 0x00000FDC) Peripheral ID byte 7 (reserved) */ + + struct + { + __IM uint32_t PID7 : 32; /*!< [31..0] Byte 7 of the Peripheral ID (Lower 8 bits valid) */ + } PID7_b; + }; + + union + { + __IM uint32_t PID0; /*!< (@ 0x00000FE0) Peripheral ID byte 0. This is bits[7:0] of the + * part number. */ + + struct + { + __IM uint32_t PID0 : 32; /*!< [31..0] Byte 0 of the Peripheral ID (Lower 8 bits valid) */ + } PID0_b; + }; + + union + { + __IM uint32_t PID1; /*!< (@ 0x00000FE4) Peripheral ID byte 1. This is bits[11:8] of the + * part number in bits[3:0], and bits[3:0] + * of the Arm ID in bits[7:4]. */ + + struct + { + __IM uint32_t PID1 : 32; /*!< [31..0] Byte 1 of the Peripheral ID (Lower 8 bits valid) */ + } PID1_b; + }; + + union + { + __IM uint32_t PID2; /*!< (@ 0x00000FE8) Peripheral ID byte 2. This is bits[6:4] of the + * Arm ID in bits[2:0], and bit 3 indicates + * format B. */ + + struct + { + __IM uint32_t PID2 : 32; /*!< [31..0] Byte 2 of the Peripheral ID (Lower 8 bits valid) */ + } PID2_b; + }; + + union + { + __IM uint32_t PID3; /*!< (@ 0x00000FEC) Peripheral ID byte 3. */ + + struct + { + __IM uint32_t PID3 : 32; /*!< [31..0] Byte 3 of the Peripheral ID (Lower 8 bits valid) */ + } PID3_b; + }; + + union + { + __IM uint32_t CID0; /*!< (@ 0x00000FF0) Component ID byte 0. */ + + struct + { + __IM uint32_t CID0 : 32; /*!< [31..0] Byte 0 of the Component ID (Lower 8 bits valid) */ + } CID0_b; + }; + + union + { + __IM uint32_t CID1; /*!< (@ 0x00000FF4) Component ID byte 1. */ + + struct + { + __IM uint32_t CID1 : 32; /*!< [31..0] Byte 1 of the Component ID (Lower 8 bits valid) */ + } CID1_b; + }; + + union + { + __IM uint32_t CID2; /*!< (@ 0x00000FF8) Component ID byte 2. */ + + struct + { + __IM uint32_t CID2 : 32; /*!< [31..0] Byte 2 of the Component ID (Lower 8 bits valid) */ + } CID2_b; + }; + + union + { + __IM uint32_t CID3; /*!< (@ 0x00000FFC) Component ID byte 3. */ + + struct + { + __IM uint32_t CID3 : 32; /*!< [31..0] Byte 3 of the Component ID (Lower 8 bits valid) */ + } CID3_b; + }; +} R_NPU_Type; /*!< Size = 4096 (0x1000) */ + +/* =========================================================================================================================== */ +/* ================ R_PDM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Pulse Density Modulator Interface (R_PDM) + */ + +typedef struct /*!< (@ 0x40256000) R_PDM Structure */ +{ + union + { + __OM uint32_t PDCSTRTR; /*!< (@ 0x00000000) Channel Software Start Trigger Register */ + + struct + { + __OM uint32_t STRTRG0 : 1; /*!< [0..0] Channel 0 start trigger */ + __OM uint32_t STRTRG1 : 1; /*!< [1..1] Channel 1 start trigger */ + __OM uint32_t STRTRG2 : 1; /*!< [2..2] Channel 2 start trigger */ + uint32_t : 29; + } PDCSTRTR_b; + }; + + union + { + __OM uint32_t PDCSTPTR; /*!< (@ 0x00000004) Channel Software Stop Trigger Register */ + + struct + { + __OM uint32_t STPTRG0 : 1; /*!< [0..0] Channel 0 stop trigger */ + __OM uint32_t STPTRG1 : 1; /*!< [1..1] Channel 1 stop trigger */ + __OM uint32_t STPTRG2 : 1; /*!< [2..2] Channel 2 stop trigger */ + uint32_t : 29; + } PDCSTPTR_b; + }; + + union + { + __OM uint32_t PDCCHGTR; /*!< (@ 0x00000008) Channel Software Change Trigger Register */ + + struct + { + __OM uint32_t CHGTRG0 : 1; /*!< [0..0] Channel 0 change trigger */ + __OM uint32_t CHGTRG1 : 1; /*!< [1..1] Channel 1 change trigger */ + __OM uint32_t CHGTRG2 : 1; /*!< [2..2] Channel 2 change trigger */ + uint32_t : 29; + } PDCCHGTR_b; + }; + + union + { + __IOM uint32_t PDCICR; /*!< (@ 0x0000000C) Channel Interrupt Control Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t ISDE0 : 1; /*!< [8..8] Channel 0 sound detection interrupt enable bit */ + __IOM uint32_t ISDE1 : 1; /*!< [9..9] Channel 1 sound detection interrupt enable bit */ + __IOM uint32_t ISDE2 : 1; /*!< [10..10] Channel 2 sound detection interrupt enable bit */ + uint32_t : 5; + __IOM uint32_t IDRE0 : 1; /*!< [16..16] Channel 0 data reception interrupt enable bit */ + __IOM uint32_t IDRE1 : 1; /*!< [17..17] Channel 1 data reception interrupt enable bit */ + __IOM uint32_t IDRE2 : 1; /*!< [18..18] Channel 2 data reception interrupt enable bit */ + uint32_t : 5; + __IOM uint32_t IEDE0 : 1; /*!< [24..24] Channel 0 error detection interrupt enable bit */ + __IOM uint32_t IEDE1 : 1; /*!< [25..25] Channel 1 error detection interrupt enable bit */ + __IOM uint32_t IEDE2 : 1; /*!< [26..26] Channel 2 error detection interrupt enable bit */ + uint32_t : 5; + } PDCICR_b; + }; + + union + { + __IM uint32_t PDCSR; /*!< (@ 0x00000010) Channel Status Register */ + + struct + { + __IM uint32_t STATE0 : 1; /*!< [0..0] Channel 0 state */ + __IM uint32_t STATE1 : 1; /*!< [1..1] Channel 1 state */ + __IM uint32_t STATE2 : 1; /*!< [2..2] Channel 2 state */ + uint32_t : 5; + __IM uint32_t SDF0 : 1; /*!< [8..8] Channel 0 sound detection flag */ + __IM uint32_t SDF1 : 1; /*!< [9..9] Channel 1 sound detection flag */ + __IM uint32_t SDF2 : 1; /*!< [10..10] Channel 2 sound detection flag */ + uint32_t : 5; + __IM uint32_t DRF0 : 1; /*!< [16..16] Channel 0 data reception flag */ + __IM uint32_t DRF1 : 1; /*!< [17..17] Channel 1 data reception flag */ + __IM uint32_t DRF2 : 1; /*!< [18..18] Channel 2 data reception flag */ + uint32_t : 5; + __IM uint32_t EDF0 : 1; /*!< [24..24] Channel 0 error detection flag */ + __IM uint32_t EDF1 : 1; /*!< [25..25] Channel 1 error detection flag */ + __IM uint32_t EDF2 : 1; /*!< [26..26] Channel 2 error detection flag */ + uint32_t : 5; + } PDCSR_b; + }; + + union + { + __OM uint32_t PDCSCR; /*!< (@ 0x00000014) Channel Status Clear Register */ + + struct + { + uint32_t : 8; + __OM uint32_t SDFC0 : 1; /*!< [8..8] Channel 0 sound detection flag clear */ + __OM uint32_t SDFC1 : 1; /*!< [9..9] Channel 1 sound detection flag clear */ + __OM uint32_t SDFC2 : 1; /*!< [10..10] Channel 2 sound detection flag clear */ + uint32_t : 21; + } PDCSCR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t PDCSDCR; /*!< (@ 0x00000020) Channel Sound Detection Control Register */ + + struct + { + __IOM uint32_t SDE0 : 1; /*!< [0..0] Channel 0 sound detection enable bit */ + __IOM uint32_t SDE1 : 1; /*!< [1..1] Channel 1 sound detection enable bit */ + __IOM uint32_t SDE2 : 1; /*!< [2..2] Channel 2 sound detection enable bit */ + uint32_t : 29; + } PDCSDCR_b; + }; + + union + { + __IOM uint32_t PDCDRCR; /*!< (@ 0x00000024) Channel Data Read Control Register */ + + struct + { + __IOM uint32_t DATRE0 : 1; /*!< [0..0] Channel 0 data read enable bit */ + __IOM uint32_t DATRE1 : 1; /*!< [1..1] Channel 1 data read enable bit */ + __IOM uint32_t DATRE2 : 1; /*!< [2..2] Channel 2 data read enable bit */ + uint32_t : 29; + } PDCDRCR_b; + }; + + union + { + __OM uint32_t PDCDCR; /*!< (@ 0x00000028) Channel Data Clear Register */ + + struct + { + __OM uint32_t DATC0 : 1; /*!< [0..0] Channel 0 data clear */ + __OM uint32_t DATC1 : 1; /*!< [1..1] Channel 1 data clear */ + __OM uint32_t DATC2 : 1; /*!< [2..2] Channel 2 data clear */ + uint32_t : 29; + } PDCDCR_b; + }; + __IM uint32_t RESERVED1[21]; + + union + { + __IM uint32_t PDVR; /*!< (@ 0x00000080) Version Register */ + + struct + { + __IM uint32_t VER : 12; /*!< [11..0] Version */ + uint32_t : 20; + } PDVR_b; + }; + __IM uint32_t RESERVED2[31]; + __IOM R_PDM_CH_Type CH[3]; /*!< (@ 0x00000100) PDM Channel-Specific Registers */ +} R_PDM_Type; /*!< Size = 1024 (0x400) */ + +/* =========================================================================================================================== */ +/* ================ R_RMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet MAC (R_RMAC0) + */ + +typedef struct /*!< (@ 0x403CB000) R_RMAC0 Structure */ +{ + union + { + __IOM uint32_t MPSM; /*!< (@ 0x00000000) MAC PHY Station Management Register (MPSM) */ + + struct + { + __IOM uint32_t PSME : 1; /*!< [0..0] PSME */ + uint32_t : 1; + __IOM uint32_t MFF : 1; /*!< [2..2] MFF */ + __IOM uint32_t PDA : 5; /*!< [7..3] PDA */ + __IOM uint32_t PRA : 5; /*!< [12..8] PRA */ + __IOM uint32_t POP : 2; /*!< [14..13] POP */ + uint32_t : 1; + __IOM uint32_t PRD : 16; /*!< [31..16] PRD */ + } MPSM_b; + }; + + union + { + __IOM uint32_t MPIC; /*!< (@ 0x00000004) MAC PHY Interfaces Configuration Register (MPIC) */ + + struct + { + __IOM uint32_t PIS : 3; /*!< [2..0] PIS */ + __IOM uint32_t LSC : 3; /*!< [5..3] LSC */ + uint32_t : 2; + __IOM uint32_t PIP : 1; /*!< [8..8] PIP */ + __IOM uint32_t PIPP : 1; /*!< [9..9] PIPP */ + __IOM uint32_t PLSPP : 1; /*!< [10..10] PLSPP */ + uint32_t : 5; + __IOM uint32_t PSMCS : 7; /*!< [22..16] PSMCS */ + __IOM uint32_t PSMDP : 1; /*!< [23..23] PSMDP */ + __IOM uint32_t PSMHT : 3; /*!< [26..24] PSMHT */ + uint32_t : 1; + __IOM uint32_t PSMCT : 3; /*!< [30..28] PSMCT */ + uint32_t : 1; + } MPIC_b; + }; + + union + { + __IOM uint32_t MPIM; /*!< (@ 0x00000008) MAC PHY Interfaces Monitoring Register (MPIM) */ + + struct + { + __IOM uint32_t PLS : 1; /*!< [0..0] PLS */ + __IOM uint32_t LPIA : 1; /*!< [1..1] LPIA */ + uint32_t : 30; + } MPIM_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t MIOC; /*!< (@ 0x00000010) RMAC IO Configuration Registers Register (MIOC) */ + + struct + { + __IOM uint32_t MIOC : 32; /*!< [31..0] MIOC */ + } MIOC_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t MTFFC; /*!< (@ 0x00000020) MAC Transmission Frame Format Configuration Register + * (MTFFC) */ + + struct + { + __IOM uint32_t DPAD : 1; /*!< [0..0] DPAD */ + __IOM uint32_t FCM : 1; /*!< [1..1] FCM */ + uint32_t : 30; + } MTFFC_b; + }; + + union + { + __IOM uint32_t MTPFC; /*!< (@ 0x00000024) MAC Transmission Pause or PFC Frame Configuration + * Register (MTPFC) */ + + struct + { + __IOM uint32_t PT : 16; /*!< [15..0] PT */ + __IOM uint32_t PFRT : 8; /*!< [23..16] PFRT */ + uint32_t : 2; + __IOM uint32_t PFM : 1; /*!< [26..26] PFM */ + __IOM uint32_t PFRLV : 5; /*!< [31..27] PFRLV */ + } MTPFC_b; + }; + + union + { + __IOM uint32_t MTPFC2; /*!< (@ 0x00000028) MAC Transmission Pause or PFC Frame configuration2 + * Register (MTPFC2) */ + + struct + { + __IOM uint32_t PFCTTZ : 2; /*!< [1..0] PFCTTZ */ + uint32_t : 6; + __IOM uint32_t MPFCFR0 : 1; /*!< [8..8] MPFCFR0 */ + __IOM uint32_t MPFCFR1 : 1; /*!< [9..9] MPFCFR1 */ + uint32_t : 6; + __IOM uint32_t PFTTZ : 1; /*!< [16..16] PFTTZ */ + __IOM uint32_t MPFR : 1; /*!< [17..17] MPFR */ + uint32_t : 14; + } MTPFC2_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t MTPFC30; /*!< (@ 0x00000030) MAC Transmission Pause or PFC Frame Configuration + * Register 3 (MTPFC3t) (t = 0, 1) */ + + struct + { + __IOM uint32_t PFCPG : 8; /*!< [7..0] PFCPG */ + uint32_t : 24; + } MTPFC30_b; + }; + + union + { + __IOM uint32_t MTPFC31; /*!< (@ 0x00000034) MAC Transmission Pause or PFC Frame Configuration + * Register 3 (MTPFC3t) (t = 0, 1) */ + + struct + { + __IOM uint32_t PFCPG : 8; /*!< [7..0] PFCPG */ + uint32_t : 24; + } MTPFC31_b; + }; + __IM uint32_t RESERVED3[6]; + + union + { + __IOM uint32_t MTATC0; /*!< (@ 0x00000050) MAC Transmission Automatic Timestamp Configuration + * Register (MTATCt) (t = 0, 1) */ + + struct + { + __IOM uint32_t TRTP : 8; /*!< [7..0] TRTP */ + __IOM uint32_t TRTL : 3; /*!< [10..8] TRTL */ + uint32_t : 21; + } MTATC0_b; + }; + + union + { + __IOM uint32_t MTATC1; /*!< (@ 0x00000054) MAC Transmission Automatic Timestamp Configuration + * Register (MTATCt) (t = 0, 1) */ + + struct + { + __IOM uint32_t TRTP : 8; /*!< [7..0] TRTP */ + __IOM uint32_t TRTL : 3; /*!< [10..8] TRTL */ + uint32_t : 21; + } MTATC1_b; + }; + __IM uint32_t RESERVED4[2]; + + union + { + __IOM uint32_t MTIM; /*!< (@ 0x00000060) MAC Transmission Interfaces Monitoring Register + * (MTIM) */ + + struct + { + __IOM uint32_t TS : 1; /*!< [0..0] TS */ + uint32_t : 31; + } MTIM_b; + }; + __IM uint32_t RESERVED5[7]; + + union + { + __IOM uint32_t MRGC; /*!< (@ 0x00000080) MAC Reception General Configuration Register + * (MRGC) */ + + struct + { + __IOM uint32_t RCPT : 1; /*!< [0..0] RCPT */ + __IOM uint32_t PFRC : 1; /*!< [1..1] PFRC */ + __IOM uint32_t PFRTZ : 1; /*!< [2..2] PFRTZ */ + __IOM uint32_t MPDE : 1; /*!< [3..3] MPDE */ + __IOM uint32_t RFCFE : 1; /*!< [4..4] RFCFE */ + uint32_t : 11; + __IOM uint32_t PFCRC : 8; /*!< [23..16] PFCRC */ + uint32_t : 8; + } MRGC_b; + }; + + union + { + __IOM uint32_t MRMAC0; /*!< (@ 0x00000084) MAC Reception MAC Address Configuration Register + * 0 (MRMAC0) */ + + struct + { + __IOM uint32_t MAU : 16; /*!< [15..0] MAU */ + uint32_t : 16; + } MRMAC0_b; + }; + + union + { + __IOM uint32_t MRMAC1; /*!< (@ 0x00000088) MAC Reception MAC Address Configuration Register + * 1 (MRMAC1) */ + + struct + { + __IOM uint32_t MAL : 32; /*!< [31..0] MAL */ + } MRMAC1_b; + }; + + union + { + __IOM uint32_t MRAFC; /*!< (@ 0x0000008C) MAC Reception Address Filter Configuration Register + * (MRAFC) */ + + struct + { + __IOM uint32_t UCENE : 1; /*!< [0..0] UCENE */ + __IOM uint32_t MCENE : 1; /*!< [1..1] MCENE */ + __IOM uint32_t BCENE : 1; /*!< [2..2] BCENE */ + __IOM uint32_t MSTENE : 1; /*!< [3..3] MSTENE */ + __IOM uint32_t BSTENE : 1; /*!< [4..4] BSTENE */ + __IOM uint32_t MCACE : 1; /*!< [5..5] MCACE */ + __IOM uint32_t BCACE : 1; /*!< [6..6] BCACE */ + __IOM uint32_t NDAREE : 1; /*!< [7..7] NDAREE */ + __IOM uint32_t SDSFREE : 1; /*!< [8..8] SDSFREE */ + __IOM uint32_t NSAREE : 1; /*!< [9..9] NSAREE */ + __IOM uint32_t MSAREE : 1; /*!< [10..10] MSAREE */ + uint32_t : 5; + __IOM uint32_t UCENP : 1; /*!< [16..16] UCENP */ + __IOM uint32_t MCENP : 1; /*!< [17..17] MCENP */ + __IOM uint32_t BCENP : 1; /*!< [18..18] BCENP */ + __IOM uint32_t MSTENP : 1; /*!< [19..19] MSTENP */ + __IOM uint32_t BSTENP : 1; /*!< [20..20] BSTENP */ + __IOM uint32_t MCACP : 1; /*!< [21..21] MCACP */ + __IOM uint32_t BCACP : 1; /*!< [22..22] BCACP */ + __IOM uint32_t NDAREP : 1; /*!< [23..23] NDAREP */ + __IOM uint32_t SDSFREP : 1; /*!< [24..24] SDSFREP */ + __IOM uint32_t NSAREP : 1; /*!< [25..25] NSAREP */ + __IOM uint32_t MSAREP : 1; /*!< [26..26] MSAREP */ + uint32_t : 5; + } MRAFC_b; + }; + + union + { + __IOM uint32_t MRSCE; /*!< (@ 0x00000090) MAC Reception Storm Configuration for e-Frames + * Register (MRSCE) */ + + struct + { + __IOM uint32_t CMFE : 16; /*!< [15..0] CMFE */ + __IOM uint32_t CBFE : 16; /*!< [31..16] CBFE */ + } MRSCE_b; + }; + + union + { + __IOM uint32_t MRSCP; /*!< (@ 0x00000094) MAC Reception Storm Configuration for p-Frames + * Register (MRSCP) */ + + struct + { + __IOM uint32_t CMFP : 16; /*!< [15..0] CMFP */ + __IOM uint32_t CBFP : 16; /*!< [31..16] CBFP */ + } MRSCP_b; + }; + + union + { + __IOM uint32_t MRSCC; /*!< (@ 0x00000098) MAC Reception Storm Counter Configuration Register + * (MRSCC) */ + + struct + { + __IOM uint32_t MSCCE : 1; /*!< [0..0] MSCCE */ + __IOM uint32_t BSCCE : 1; /*!< [1..1] BSCCE */ + uint32_t : 14; + __IOM uint32_t MSCCP : 1; /*!< [16..16] MSCCP */ + __IOM uint32_t BSCCP : 1; /*!< [17..17] BSCCP */ + uint32_t : 14; + } MRSCC_b; + }; + + union + { + __IOM uint32_t MRFSCE; /*!< (@ 0x0000009C) MAC Reception Frame Size Configuration for e-Frames + * Register (MRFSCE) */ + + struct + { + __IOM uint32_t EMXS : 16; /*!< [15..0] EMXS */ + __IOM uint32_t EMNS : 16; /*!< [31..16] EMNS */ + } MRFSCE_b; + }; + + union + { + __IOM uint32_t MRFSCP; /*!< (@ 0x000000A0) MAC Reception Frame Size Configuration for p-Frames + * Register (MRFSCP) */ + + struct + { + __IOM uint32_t PMXS : 16; /*!< [15..0] PMXS */ + __IOM uint32_t PMNS : 16; /*!< [31..16] PMNS */ + } MRFSCP_b; + }; + + union + { + __IOM uint32_t MTRC; /*!< (@ 0x000000A4) MAC Timestamp Reception Configuration Register + * (MTRC) */ + + struct + { + __IOM uint32_t TRHFME0 : 1; /*!< [0..0] TRHFME0 */ + __IOM uint32_t TRHFME1 : 1; /*!< [1..1] TRHFME1 */ + uint32_t : 22; + __IOM uint32_t TRDDE : 1; /*!< [24..24] TRDDE */ + __IOM uint32_t TRDDP : 1; /*!< [25..25] TRDDP */ + __IOM uint32_t TCTSE : 1; /*!< [26..26] TCTSE */ + __IOM uint32_t TCTSP : 1; /*!< [27..27] TCTSP */ + __IOM uint32_t DTN : 1; /*!< [28..28] DTN */ + uint32_t : 3; + } MTRC_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t MRPFM; /*!< (@ 0x000000AC) MAC Reception Pause or PFC Frame Monitoring Register + * (MRPFM) */ + + struct + { + __IOM uint32_t PTCA : 1; /*!< [0..0] PTCA */ + uint32_t : 15; + __IOM uint32_t PFCTCA : 8; /*!< [23..16] PFCTCA */ + uint32_t : 8; + } MRPFM_b; + }; + __IM uint32_t RESERVED7[20]; + + union + { + __IOM uint32_t MPFC0; /*!< (@ 0x00000100) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC0_b; + }; + + union + { + __IOM uint32_t MPFC1; /*!< (@ 0x00000104) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC1_b; + }; + + union + { + __IOM uint32_t MPFC2; /*!< (@ 0x00000108) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC2_b; + }; + + union + { + __IOM uint32_t MPFC3; /*!< (@ 0x0000010C) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC3_b; + }; + + union + { + __IOM uint32_t MPFC4; /*!< (@ 0x00000110) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC4_b; + }; + + union + { + __IOM uint32_t MPFC5; /*!< (@ 0x00000114) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC5_b; + }; + + union + { + __IOM uint32_t MPFC6; /*!< (@ 0x00000118) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC6_b; + }; + + union + { + __IOM uint32_t MPFC7; /*!< (@ 0x0000011C) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC7_b; + }; + + union + { + __IOM uint32_t MPFC8; /*!< (@ 0x00000120) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC8_b; + }; + + union + { + __IOM uint32_t MPFC9; /*!< (@ 0x00000124) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC9_b; + }; + + union + { + __IOM uint32_t MPFC10; /*!< (@ 0x00000128) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC10_b; + }; + + union + { + __IOM uint32_t MPFC11; /*!< (@ 0x0000012C) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC11_b; + }; + + union + { + __IOM uint32_t MPFC12; /*!< (@ 0x00000130) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC12_b; + }; + + union + { + __IOM uint32_t MPFC13; /*!< (@ 0x00000134) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC13_b; + }; + + union + { + __IOM uint32_t MPFC14; /*!< (@ 0x00000138) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC14_b; + }; + + union + { + __IOM uint32_t MPFC15; /*!< (@ 0x0000013C) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC15_b; + }; + __IM uint32_t RESERVED8[16]; + + union + { + __IOM uint32_t MLVC; /*!< (@ 0x00000180) MAC Link Verification Configuration Register + * (MLVC) */ + + struct + { + __IOM uint32_t LVT : 7; /*!< [6..0] LVT */ + uint32_t : 1; + __IOM uint32_t PASE : 1; /*!< [8..8] PASE */ + uint32_t : 7; + __IOM uint32_t PLV : 1; /*!< [16..16] PLV */ + uint32_t : 15; + } MLVC_b; + }; + + union + { + __IOM uint32_t MEEEC; /*!< (@ 0x00000184) MAC Energy Efficient Ethernet Configuration Register + * (MEEEC) */ + + struct + { + __IOM uint32_t LPITR : 1; /*!< [0..0] LPITR */ + uint32_t : 31; + } MEEEC_b; + }; + + union + { + __IOM uint32_t MLBC; /*!< (@ 0x00000188) MAC Loopback Configuration Register (MLBC) */ + + struct + { + __IOM uint32_t LBME : 1; /*!< [0..0] LBME */ + uint32_t : 31; + } MLBC_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t MXGMIIC; /*!< (@ 0x00000190) XGMII Configuration Register (MXGMIIC) */ + + struct + { + __IOM uint32_t LFS_TXRFS : 1; /*!< [0..0] LFS_TXRFS */ + __IOM uint32_t LFS_TXIDLE : 1; /*!< [1..1] LFS_TXIDLE */ + uint32_t : 30; + } MXGMIIC_b; + }; + + union + { + __IOM uint32_t MPCH; /*!< (@ 0x00000194) XGMII PCH Configuration Register (MPCH) */ + + struct + { + __IOM uint32_t TXPCH_M : 1; /*!< [0..0] TXPCH_M */ + uint32_t : 1; + __IOM uint32_t TXPCH_ETYPE : 2; /*!< [3..2] TXPCH_ETYPE */ + __IOM uint32_t TXPCH_PID : 4; /*!< [7..4] TXPCH_PID */ + __IOM uint32_t IETPTE : 1; /*!< [8..8] IETPTE */ + __IOM uint32_t CTPTE : 1; /*!< [9..9] CTPTE */ + __IOM uint32_t IETRIOD : 1; /*!< [10..10] IETRIOD */ + __IOM uint32_t CTRIOD : 1; /*!< [11..11] CTRIOD */ + uint32_t : 4; + __IOM uint32_t RXPCH_TSM : 1; /*!< [16..16] RXPCH_TSM */ + __IOM uint32_t RPHCRCD : 1; /*!< [17..17] RPHCRCD */ + uint32_t : 14; + } MPCH_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t MANM; /*!< (@ 0x0000019C) Auto-Negotiation Message Register (MANM) */ + + struct + { + __IOM uint32_t RX_AN_MES : 16; /*!< [15..0] RX_AN_MES */ + uint32_t : 16; + } MANM_b; + }; + __IM uint32_t RESERVED11[24]; + + union + { + __IOM uint32_t MEIS; /*!< (@ 0x00000200) MAC Error Interrupt Status Register (MEIS) */ + + struct + { + __IOM uint32_t TSLS : 1; /*!< [0..0] TSLS */ + __IOM uint32_t TIES : 1; /*!< [1..1] TIES */ + __IOM uint32_t PRES : 1; /*!< [2..2] PRES */ + __IOM uint32_t PFRROS : 1; /*!< [3..3] PFRROS */ + __IOM uint32_t FCDS : 1; /*!< [4..4] FCDS */ + __IOM uint32_t TCES : 1; /*!< [5..5] TCES */ + __IOM uint32_t TBCIS : 1; /*!< [6..6] TBCIS */ + __IOM uint32_t BFES : 1; /*!< [7..7] BFES */ + __IOM uint32_t FCES : 1; /*!< [8..8] FCES */ + __IOM uint32_t REOES : 1; /*!< [9..9] REOES */ + __IOM uint32_t RPOES : 1; /*!< [10..10] RPOES */ + __IOM uint32_t RPCRES : 1; /*!< [11..11] RPCRES */ + __IOM uint32_t CTLES0 : 1; /*!< [12..12] CTLES0 */ + __IOM uint32_t CTLES1 : 1; /*!< [13..13] CTLES1 */ + uint32_t : 6; + __IOM uint32_t PDES : 1; /*!< [20..20] PDES */ + __IOM uint32_t PNAES : 1; /*!< [21..21] PNAES */ + __IOM uint32_t FCMCES : 1; /*!< [22..22] FCMCES */ + __IOM uint32_t FFMES : 1; /*!< [23..23] FFMES */ + __IOM uint32_t CFCES : 1; /*!< [24..24] CFCES */ + __IOM uint32_t FRCES : 1; /*!< [25..25] FRCES */ + __IOM uint32_t RPOOMS : 1; /*!< [26..26] RPOOMS */ + __IOM uint32_t FFS : 1; /*!< [27..27] FFS */ + __IOM uint32_t FUES : 1; /*!< [28..28] FUES */ + __IOM uint32_t FOES : 1; /*!< [29..29] FOES */ + uint32_t : 2; + } MEIS_b; + }; + + union + { + __IOM uint32_t MEIE; /*!< (@ 0x00000204) MAC Error Interrupt Enable Register (MEIE) */ + + struct + { + __IOM uint32_t TSLE : 1; /*!< [0..0] TSLE */ + __IOM uint32_t TIEE : 1; /*!< [1..1] TIEE */ + __IOM uint32_t PMSEE : 1; /*!< [2..2] PMSEE */ + __IOM uint32_t PFRROE : 1; /*!< [3..3] PFRROE */ + __IOM uint32_t FCDE : 1; /*!< [4..4] FCDE */ + __IOM uint32_t TCEE : 1; /*!< [5..5] TCEE */ + __IOM uint32_t TBCIE : 1; /*!< [6..6] TBCIE */ + __IOM uint32_t BFEE : 1; /*!< [7..7] BFEE */ + __IOM uint32_t FCEE : 1; /*!< [8..8] FCEE */ + __IOM uint32_t REOEE : 1; /*!< [9..9] REOEE */ + __IOM uint32_t RPOEE : 1; /*!< [10..10] RPOEE */ + __IOM uint32_t RPCREE : 1; /*!< [11..11] RPCREE */ + __IOM uint32_t CTLEE0 : 1; /*!< [12..12] CTLEE0 */ + __IOM uint32_t CTLEE1 : 1; /*!< [13..13] CTLEE1 */ + uint32_t : 6; + __IOM uint32_t PDEE : 1; /*!< [20..20] PDEE */ + __IOM uint32_t PNAEE : 1; /*!< [21..21] PNAEE */ + __IOM uint32_t FCMCEE : 1; /*!< [22..22] FCMCEE */ + __IOM uint32_t FFMEE : 1; /*!< [23..23] FFMEE */ + __IOM uint32_t CFCEE : 1; /*!< [24..24] CFCEE */ + __IOM uint32_t FRCEE : 1; /*!< [25..25] FRCEE */ + __IOM uint32_t RPOOME : 1; /*!< [26..26] RPOOME */ + __IOM uint32_t FFE : 1; /*!< [27..27] FFE */ + __IOM uint32_t FUEE : 1; /*!< [28..28] FUEE */ + __IOM uint32_t FOEE : 1; /*!< [29..29] FOEE */ + uint32_t : 2; + } MEIE_b; + }; + + union + { + __IOM uint32_t MEID; /*!< (@ 0x00000208) MAC Error Interrupt Disable Register (MEID) */ + + struct + { + __IOM uint32_t TSLD : 1; /*!< [0..0] TSLD */ + __IOM uint32_t TIED : 1; /*!< [1..1] TIED */ + __IOM uint32_t PRED : 1; /*!< [2..2] PRED */ + __IOM uint32_t PFRROD : 1; /*!< [3..3] PFRROD */ + __IOM uint32_t FCDD : 1; /*!< [4..4] FCDD */ + __IOM uint32_t TCED : 1; /*!< [5..5] TCED */ + __IOM uint32_t TBCID : 1; /*!< [6..6] TBCID */ + __IOM uint32_t BFED : 1; /*!< [7..7] BFED */ + __IOM uint32_t FCED : 1; /*!< [8..8] FCED */ + __IOM uint32_t REOED : 1; /*!< [9..9] REOED */ + __IOM uint32_t RPOED : 1; /*!< [10..10] RPOED */ + __IOM uint32_t RPCRED : 1; /*!< [11..11] RPCRED */ + __IOM uint32_t CTLED0 : 1; /*!< [12..12] CTLED0 */ + __IOM uint32_t CTLED1 : 1; /*!< [13..13] CTLED1 */ + uint32_t : 6; + __IOM uint32_t PDED : 1; /*!< [20..20] PDED */ + __IOM uint32_t PNAED : 1; /*!< [21..21] PNAED */ + __IOM uint32_t FCMCED : 1; /*!< [22..22] FCMCED */ + __IOM uint32_t FFMED : 1; /*!< [23..23] FFMED */ + __IOM uint32_t CFCED : 1; /*!< [24..24] CFCED */ + __IOM uint32_t FRCED : 1; /*!< [25..25] FRCED */ + __IOM uint32_t RPOOMD : 1; /*!< [26..26] RPOOMD */ + __IOM uint32_t FFD : 1; /*!< [27..27] FFD */ + __IOM uint32_t FUED : 1; /*!< [28..28] FUED */ + __IOM uint32_t FOED : 1; /*!< [29..29] FOED */ + uint32_t : 2; + } MEID_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t MMIS0; /*!< (@ 0x00000210) MAC Monitoring Interrupt Status Register 0 (MMIS0) */ + + struct + { + __IOM uint32_t PLSCS : 1; /*!< [0..0] PLSCS */ + __IOM uint32_t PIDS : 1; /*!< [1..1] PIDS */ + __IOM uint32_t LVSS : 1; /*!< [2..2] LVSS */ + __IOM uint32_t LVFS : 1; /*!< [3..3] LVFS */ + __IOM uint32_t VFRS : 1; /*!< [4..4] VFRS */ + uint32_t : 1; + __IOM uint32_t ANDETS : 1; /*!< [6..6] ANDETS */ + uint32_t : 1; + __IOM uint32_t XLFDS : 1; /*!< [8..8] XLFDS */ + __IOM uint32_t XLFES : 1; /*!< [9..9] XLFES */ + __IOM uint32_t XLFSDS : 1; /*!< [10..10] XLFSDS */ + __IOM uint32_t XRFSDS : 1; /*!< [11..11] XRFSDS */ + __IOM uint32_t XLISDS : 1; /*!< [12..12] XLISDS */ + uint32_t : 19; + } MMIS0_b; + }; + + union + { + __IOM uint32_t MMIE0; /*!< (@ 0x00000214) MAC Monitoring Interrupt Enable Register 0 (MMIE0) */ + + struct + { + __IOM uint32_t PLSCE : 1; /*!< [0..0] PLSCE */ + __IOM uint32_t PIDE : 1; /*!< [1..1] PIDE */ + __IOM uint32_t LVSE : 1; /*!< [2..2] LVSE */ + __IOM uint32_t LVFE : 1; /*!< [3..3] LVFE */ + __IOM uint32_t VFRE : 1; /*!< [4..4] VFRE */ + uint32_t : 1; + __IOM uint32_t ANDETE : 1; /*!< [6..6] ANDETE */ + uint32_t : 1; + __IOM uint32_t XLFDE : 1; /*!< [8..8] XLFDE */ + __IOM uint32_t XLFEE : 1; /*!< [9..9] XLFEE */ + __IOM uint32_t XLFSDE : 1; /*!< [10..10] XLFSDE */ + __IOM uint32_t XRFSDE : 1; /*!< [11..11] XRFSDE */ + __IOM uint32_t XLISDE : 1; /*!< [12..12] XLISDE */ + uint32_t : 19; + } MMIE0_b; + }; + + union + { + __IOM uint32_t MMID0; /*!< (@ 0x00000218) MAC Monitoring Interrupt Disable Register 0 (MMID0) */ + + struct + { + __IOM uint32_t PLSCD : 1; /*!< [0..0] PLSCD */ + __IOM uint32_t PIDD : 1; /*!< [1..1] PIDD */ + __IOM uint32_t LVSD : 1; /*!< [2..2] LVSD */ + __IOM uint32_t LVFD : 1; /*!< [3..3] LVFD */ + __IOM uint32_t VFRD : 1; /*!< [4..4] VFRD */ + uint32_t : 1; + __IOM uint32_t ANDETD : 1; /*!< [6..6] ANDETD */ + uint32_t : 1; + __IOM uint32_t XLFDD : 1; /*!< [8..8] XLFDD */ + __IOM uint32_t XLFED : 1; /*!< [9..9] XLFED */ + __IOM uint32_t XLFSDD : 1; /*!< [10..10] XLFSDD */ + __IOM uint32_t XRFSDD : 1; /*!< [11..11] XRFSDD */ + __IOM uint32_t XLISDD : 1; /*!< [12..12] XLISDD */ + uint32_t : 19; + } MMID0_b; + }; + __IM uint32_t RESERVED13; + + union + { + __IOM uint32_t MMIS1; /*!< (@ 0x00000220) MAC Monitoring Interrupt Status Register 1 (MMIS1) */ + + struct + { + __IOM uint32_t PRACS : 1; /*!< [0..0] PRACS */ + __IOM uint32_t PWACS : 1; /*!< [1..1] PWACS */ + __IOM uint32_t PAACS : 1; /*!< [2..2] PAACS */ + __IOM uint32_t PPRACS : 1; /*!< [3..3] PPRACS */ + uint32_t : 28; + } MMIS1_b; + }; + + union + { + __IOM uint32_t MMIE1; /*!< (@ 0x00000224) MAC Monitoring Interrupt Enable Register 1 (MMIE1) */ + + struct + { + __IOM uint32_t PRACE : 1; /*!< [0..0] PRACE */ + __IOM uint32_t PWACE : 1; /*!< [1..1] PWACE */ + __IOM uint32_t PAACE : 1; /*!< [2..2] PAACE */ + __IOM uint32_t PPRACE : 1; /*!< [3..3] PPRACE */ + uint32_t : 28; + } MMIE1_b; + }; + + union + { + __IOM uint32_t MMID1; /*!< (@ 0x00000228) MAC Monitoring Interrupt Disable Register 1 (MMID1) */ + + struct + { + __IOM uint32_t PRACD : 1; /*!< [0..0] PRACD */ + __IOM uint32_t PWACD : 1; /*!< [1..1] PWACD */ + __IOM uint32_t PAACD : 1; /*!< [2..2] PAACD */ + __IOM uint32_t PPRACD : 1; /*!< [3..3] PPRACD */ + uint32_t : 28; + } MMID1_b; + }; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t MMIS2; /*!< (@ 0x00000230) MAC Monitoring Interrupt Status Register 2 (MMIS2) */ + + struct + { + __IOM uint32_t MPDIS : 1; /*!< [0..0] MPDIS */ + __IOM uint32_t LPIAIS : 1; /*!< [1..1] LPIAIS */ + __IOM uint32_t LPIDIS : 1; /*!< [2..2] LPIDIS */ + uint32_t : 29; + } MMIS2_b; + }; + + union + { + __IOM uint32_t MMIE2; /*!< (@ 0x00000234) MAC Monitoring Interrupt Enable Register 2 (MMIE2) */ + + struct + { + __IOM uint32_t MPDIE : 1; /*!< [0..0] MPDIE */ + __IOM uint32_t LPIAIE : 1; /*!< [1..1] LPIAIE */ + __IOM uint32_t LPIDIE : 1; /*!< [2..2] LPIDIE */ + uint32_t : 29; + } MMIE2_b; + }; + + union + { + __IOM uint32_t MMID2; /*!< (@ 0x00000238) MAC Monitoring Interrupt Disable Register 2 (MMID2) */ + + struct + { + __IOM uint32_t MPDID : 1; /*!< [0..0] MPDID */ + __IOM uint32_t LPIAID : 1; /*!< [1..1] LPIAID */ + __IOM uint32_t LPIDID : 1; /*!< [2..2] LPIDID */ + uint32_t : 29; + } MMID2_b; + }; + __IM uint32_t RESERVED15[49]; + + union + { + __IOM uint32_t MMPFTCT; /*!< (@ 0x00000300) MAC Manual Pause Frame Transmit Counter Register + * (MMPFTCT) */ + + struct + { + __IOM uint32_t MPFTC : 16; /*!< [15..0] MPFTC */ + uint32_t : 16; + } MMPFTCT_b; + }; + + union + { + __IOM uint32_t MAPFTCT; /*!< (@ 0x00000304) MAC Automatic Pause Frame Transmit Counter Register + * (MAPFTCT) */ + + struct + { + __IOM uint32_t APFTC : 16; /*!< [15..0] APFTC */ + uint32_t : 16; + } MAPFTCT_b; + }; + + union + { + __IOM uint32_t MPFRCT; /*!< (@ 0x00000308) MAC Pause Frame Receive Counter Register (MPFRCT) */ + + struct + { + __IOM uint32_t PFRC : 16; /*!< [15..0] PFRC */ + uint32_t : 16; + } MPFRCT_b; + }; + + union + { + __IOM uint32_t MFCICT; /*!< (@ 0x0000030C) MAC False Carrier Indication Counter Register + * (MFCICT) */ + + struct + { + __IOM uint32_t FCIC : 16; /*!< [15..0] FCIC */ + uint32_t : 16; + } MFCICT_b; + }; + + union + { + __IOM uint32_t MEEECT; /*!< (@ 0x00000310) MAC Energy Efficient Ethernet Counter Register + * (MEEECT) */ + + struct + { + __IOM uint32_t EEERC : 16; /*!< [15..0] EEERC */ + uint32_t : 16; + } MEEECT_b; + }; + __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint32_t MMPCFTCT0; /*!< (@ 0x00000320) MAC Manual PFC Frame Transmit Counter Register + * (MMPCFTCTt) (t = 0, 1) */ + + struct + { + __IOM uint32_t MPCFCTC : 16; /*!< [15..0] MPCFCTC */ + uint32_t : 16; + } MMPCFTCT0_b; + }; + + union + { + __IOM uint32_t MMPCFTCT1; /*!< (@ 0x00000324) MAC Manual PFC Frame Transmit Counter Register + * (MMPCFTCTt) (t = 0, 1) */ + + struct + { + __IOM uint32_t MPCFCTC : 16; /*!< [15..0] MPCFCTC */ + uint32_t : 16; + } MMPCFTCT1_b; + }; + __IM uint32_t RESERVED17[2]; + + union + { + __IOM uint32_t MAPCFTCT0; /*!< (@ 0x00000330) MAC Automatic PFC Frame Transmit Counter Register + * (MAPCFTCTt) (t = 0, 1) */ + + struct + { + __IOM uint32_t APCFCTC : 16; /*!< [15..0] APCFCTC */ + uint32_t : 16; + } MAPCFTCT0_b; + }; + + union + { + __IOM uint32_t MAPCFTCT1; /*!< (@ 0x00000334) MAC Automatic PFC Frame Transmit Counter Register + * (MAPCFTCTt) (t = 0, 1) */ + + struct + { + __IOM uint32_t APCFCTC : 16; /*!< [15..0] APCFCTC */ + uint32_t : 16; + } MAPCFTCT1_b; + }; + __IM uint32_t RESERVED18[2]; + + union + { + __IOM uint32_t MPCFRCT0; /*!< (@ 0x00000340) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT0_b; + }; + + union + { + __IOM uint32_t MPCFRCT1; /*!< (@ 0x00000344) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT1_b; + }; + + union + { + __IOM uint32_t MPCFRCT2; /*!< (@ 0x00000348) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT2_b; + }; + + union + { + __IOM uint32_t MPCFRCT3; /*!< (@ 0x0000034C) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT3_b; + }; + + union + { + __IOM uint32_t MPCFRCT4; /*!< (@ 0x00000350) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT4_b; + }; + + union + { + __IOM uint32_t MPCFRCT5; /*!< (@ 0x00000354) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT5_b; + }; + + union + { + __IOM uint32_t MPCFRCT6; /*!< (@ 0x00000358) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT6_b; + }; + + union + { + __IOM uint32_t MPCFRCT7; /*!< (@ 0x0000035C) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT7_b; + }; + + union + { + __IOM uint32_t MROVFC; /*!< (@ 0x00000360) Receive Overflow Counter Register (MROVFC) */ + + struct + { + __IOM uint32_t ROVFC : 32; /*!< [31..0] ROVFC */ + } MROVFC_b; + }; + + union + { + __IOM uint32_t MRHCRCEC; /*!< (@ 0x00000364) Reception Header-CRC(PCH CRC) Error Counter Register + * (MRHCRCEC) */ + + struct + { + __IOM uint32_t RHCRCEC : 16; /*!< [15..0] RHCRCEC */ + uint32_t : 16; + } MRHCRCEC_b; + }; + __IM uint32_t RESERVED19[40]; + + union + { + __IOM uint32_t MRGFCE; /*!< (@ 0x00000408) RMAC Received Good Frame Counter E-Frames Register + * (MRGFCE) */ + + struct + { + __IOM uint32_t RGFNE : 32; /*!< [31..0] RGFNE */ + } MRGFCE_b; + }; + + union + { + __IOM uint32_t MRGFCP; /*!< (@ 0x0000040C) RMAC Received Good Frame Counter P-Frames Register + * (MRGFCP) */ + + struct + { + __IOM uint32_t RGFNP : 32; /*!< [31..0] RGFNP */ + } MRGFCP_b; + }; + + union + { + __IOM uint32_t MRBFC; /*!< (@ 0x00000410) Register (MRBFC) */ + + struct + { + __IOM uint32_t RBFN : 32; /*!< [31..0] RBFN */ + } MRBFC_b; + }; + + union + { + __IOM uint32_t MRMFC; /*!< (@ 0x00000414) RMAC Received Good Multicast Frame Counter Register + * (MRMFC) */ + + struct + { + __IOM uint32_t RMFN : 32; /*!< [31..0] RMFN */ + } MRMFC_b; + }; + + union + { + __IOM uint32_t MRUFC; /*!< (@ 0x00000418) RMAC Received Good Unicast Frame Counter Register + * (MRUFC) */ + + struct + { + __IOM uint32_t RUFN : 32; /*!< [31..0] RUFN */ + } MRUFC_b; + }; + + union + { + __IOM uint32_t MRPEFC; /*!< (@ 0x0000041C) Register (MRPEFC) */ + + struct + { + __IOM uint32_t RPEFN : 16; /*!< [15..0] RPEFN */ + uint32_t : 16; + } MRPEFC_b; + }; + + union + { + __IOM uint32_t MRNEFC; /*!< (@ 0x00000420) Register (MRNEFC) */ + + struct + { + __IOM uint32_t RNEFN : 16; /*!< [15..0] RNEFN */ + uint32_t : 16; + } MRNEFC_b; + }; + + union + { + __IOM uint32_t MRFMEFC; /*!< (@ 0x00000424) Register (MRFMEFC) */ + + struct + { + __IOM uint32_t RFMEFN : 32; /*!< [31..0] RFMEFN */ + } MRFMEFC_b; + }; + + union + { + __IOM uint32_t MRFFMEFC; /*!< (@ 0x00000428) Register (MRFFMEFC) */ + + struct + { + __IOM uint32_t RFFMEFN : 16; /*!< [15..0] RFFMEFN */ + uint32_t : 16; + } MRFFMEFC_b; + }; + + union + { + __IOM uint32_t MRCFCEFC; /*!< (@ 0x0000042C) Register (MRCFCEFC) */ + + struct + { + __IOM uint32_t RCFCEFN : 16; /*!< [15..0] RCFCEFN */ + uint32_t : 16; + } MRCFCEFC_b; + }; + + union + { + __IOM uint32_t MRFCEFC; /*!< (@ 0x00000430) Register (MRFCEFC) */ + + struct + { + __IOM uint32_t RFCEFN : 16; /*!< [15..0] RFCEFN */ + uint32_t : 16; + } MRFCEFC_b; + }; + + union + { + __IOM uint32_t MRRCFEFC; /*!< (@ 0x00000434) Register (MRRCFEFC) */ + + struct + { + __IOM uint32_t RRCFEFN : 16; /*!< [15..0] RRCFEFN */ + uint32_t : 16; + } MRRCFEFC_b; + }; + + union + { + __IOM uint32_t MRFC; /*!< (@ 0x00000438) Register (MRFC) */ + + struct + { + __IOM uint32_t RFN : 32; /*!< [31..0] RFN */ + } MRFC_b; + }; + + union + { + __IOM uint32_t MRGUEFC; /*!< (@ 0x0000043C) RMAC Received Good Undersize Error Frame Count + * Register (MRGUEFC) */ + + struct + { + __IOM uint32_t RUEFN : 32; /*!< [31..0] RUEFN */ + } MRGUEFC_b; + }; + + union + { + __IOM uint32_t MRBUEFC; /*!< (@ 0x00000440) RMAC Received bad Undersize Error Frame Count + * Register (MRBUEFC) */ + + struct + { + __IOM uint32_t RUEFN : 32; /*!< [31..0] RUEFN */ + } MRBUEFC_b; + }; + + union + { + __IOM uint32_t MRGOEFC; /*!< (@ 0x00000444) Register (MRGOEFC) */ + + struct + { + __IOM uint32_t RGOEFN : 32; /*!< [31..0] RGOEFN */ + } MRGOEFC_b; + }; + + union + { + __IOM uint32_t MRBOEFC; /*!< (@ 0x00000448) Register (MRBOEFC) */ + + struct + { + __IOM uint32_t RBOEFN : 32; /*!< [31..0] RBOEFN */ + } MRBOEFC_b; + }; + + union + { + __IOM uint32_t MRXBCEU; /*!< (@ 0x0000044C) Register (MRXBCEU) */ + + struct + { + __IOM uint32_t RBNEU : 32; /*!< [31..0] RBNEU */ + } MRXBCEU_b; + }; + + union + { + __IOM uint32_t MRXBCEL; /*!< (@ 0x00000450) Register (MRXBCEL) */ + + struct + { + __IOM uint32_t RBNEL : 32; /*!< [31..0] RBNEL */ + } MRXBCEL_b; + }; + + union + { + __IOM uint32_t MRXBCPU; /*!< (@ 0x00000454) Register (MRXBCPU) */ + + struct + { + __IOM uint32_t RBNPU : 32; /*!< [31..0] RBNPU */ + } MRXBCPU_b; + }; + + union + { + __IOM uint32_t MRXBCPL; /*!< (@ 0x00000458) Register (MRXBCPL) */ + + struct + { + __IOM uint32_t RBNPL : 32; /*!< [31..0] RBNPL */ + } MRXBCPL_b; + }; + __IM uint32_t RESERVED20[43]; + + union + { + __IOM uint32_t MTGFCE; /*!< (@ 0x00000508) RMAC Transmitted Good Frame Counter E-Frames + * Register (MTGFCE) */ + + struct + { + __IOM uint32_t TGFNE : 32; /*!< [31..0] TGFNE */ + } MTGFCE_b; + }; + + union + { + __IOM uint32_t MTGFCP; /*!< (@ 0x0000050C) RMAC Transmitted Good Frame Counter P-Frames + * Register (MTGFCP) */ + + struct + { + __IOM uint32_t TGFNP : 32; /*!< [31..0] TGFNP */ + } MTGFCP_b; + }; + + union + { + __IOM uint32_t MTBFC; /*!< (@ 0x00000510) Register (MTBFC) */ + + struct + { + __IOM uint32_t TBFN : 32; /*!< [31..0] TBFN */ + } MTBFC_b; + }; + + union + { + __IOM uint32_t MTMFC; /*!< (@ 0x00000514) RMAC Transmitted Multicast Frame Counter Register + * (MTMFC) */ + + struct + { + __IOM uint32_t TMFN : 32; /*!< [31..0] TMFN */ + } MTMFC_b; + }; + + union + { + __IOM uint32_t MTUFC; /*!< (@ 0x00000518) Register (MTUFC) */ + + struct + { + __IOM uint32_t TUFN : 32; /*!< [31..0] TUFN */ + } MTUFC_b; + }; + + union + { + __IOM uint32_t MTEFC; /*!< (@ 0x0000051C) Register (MTEFC) */ + + struct + { + __IOM uint32_t TEFN : 16; /*!< [15..0] TEFN */ + uint32_t : 16; + } MTEFC_b; + }; + + union + { + __IOM uint32_t MTXBCEU; /*!< (@ 0x00000520) Register (MTXBCEU) */ + + struct + { + __IOM uint32_t TBNEU : 32; /*!< [31..0] TBNEU */ + } MTXBCEU_b; + }; + + union + { + __IOM uint32_t MTXBCEL; /*!< (@ 0x00000524) Register (MTXBCEL) */ + + struct + { + __IOM uint32_t TBNEL : 32; /*!< [31..0] TBNEL */ + } MTXBCEL_b; + }; + + union + { + __IOM uint32_t MTXBCPU; /*!< (@ 0x00000528) RMAC Transmitted Byte Counter P-Frames Upper + * Side Register (MTXBCPU) */ + + struct + { + __IOM uint32_t TBNPU : 32; /*!< [31..0] TBNPU */ + } MTXBCPU_b; + }; + + union + { + __IOM uint32_t MTXBCPL; /*!< (@ 0x0000052C) RMAC Transmitted Byte Counter P-Frames Lower + * Side Register (MTXBCPL) */ + + struct + { + __IOM uint32_t TBNPL : 32; /*!< [31..0] TBNPL */ + } MTXBCPL_b; + }; +} R_RMAC0_Type; /*!< Size = 1328 (0x530) */ + +/* =========================================================================================================================== */ +/* ================ R_TCM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Tightly Coupled Memory (R_TCM) + */ + +typedef struct /*!< (@ 0x4001C800) R_TCM Structure */ +{ + union + { + __IOM uint16_t TCMPRCR_S; /*!< (@ 0x00000000) TCM Protection Control Register for Secure */ + + struct + { + __IOM uint16_t PR : 1; /*!< [0..0] Register Write Control */ + uint16_t : 7; + __IOM uint16_t KW : 8; /*!< [15..8] Write Key Code */ + } TCMPRCR_S_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TCMPRCR_NS; /*!< (@ 0x00000004) TCM Protection Control Register for Non-Secure */ + + struct + { + __IOM uint16_t PR : 1; /*!< [0..0] Register Write Control */ + uint16_t : 7; + __IOM uint16_t KW : 8; /*!< [15..8] Write Key Code */ + } TCMPRCR_NS_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint8_t TCMCRC; /*!< (@ 0x00000010) TCM Control Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after ECC error detection */ + uint8_t : 1; + __IOM uint8_t ECCMOD : 2; /*!< [3..2] ECC Operating Mode Select */ + __IOM uint8_t E1STSEN : 1; /*!< [4..4] ECC 1-Bit Error Information Update Enable */ + uint8_t : 2; + __IOM uint8_t TSTBYP : 1; /*!< [7..7] ECC Test Enable / ECC Bypass Select */ + } TCMCRC_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t TCMCRS; /*!< (@ 0x00000014) TCM Control Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after ECC error detection */ + uint8_t : 1; + __IOM uint8_t ECCMOD : 2; /*!< [3..2] ECC Operating Mode Select */ + __IOM uint8_t E1STSEN : 1; /*!< [4..4] ECC 1-Bit Error Information Update Enable */ + uint8_t : 2; + __IOM uint8_t TSTBYP : 1; /*!< [7..7] ECC Test Enable / ECC Bypass Select */ + } TCMCRS_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[10]; + + union + { + __IOM uint16_t TCMESR; /*!< (@ 0x00000040) TCM Error Status Register */ + + struct + { + __IOM uint16_t ERRC0 : 1; /*!< [0..0] C-TCM 1-bit ECC Error Status */ + __IOM uint16_t ERRC1 : 1; /*!< [1..1] C-TCM 2-bit ECC Error Status */ + __IOM uint16_t ERRS0 : 1; /*!< [2..2] S-TCM 1-bit ECC Error Status */ + __IOM uint16_t ERRS1 : 1; /*!< [3..3] S-TCM 2-bit ECC Error Status */ + uint16_t : 12; + } TCMESR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9; + + union + { + __IOM uint16_t TCMESCLR; /*!< (@ 0x00000048) TCM Error Status Clear Register */ + + struct + { + __IOM uint16_t CLRC0 : 1; /*!< [0..0] TCM 1-bit ECC Error Status Clear */ + __IOM uint16_t CLRC1 : 1; /*!< [1..1] TCM 2-bit ECC Error Status Clear */ + __IOM uint16_t CLRS0 : 1; /*!< [2..2] S-TCM 1-bit ECC Error Status Clear */ + __IOM uint16_t CLRS1 : 1; /*!< [3..3] S-TCM 2-bit ECC Error Status Clear */ + uint16_t : 12; + } TCMESCLR_b; + }; + __IM uint16_t RESERVED10; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t TCMEARC0; /*!< (@ 0x00000050) TCM Error Address Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t EAR : 16; /*!< [17..2] When an SRAM error occurs, it stores an error address */ + uint32_t : 14; + } TCMEARC0_b; + }; + + union + { + __IOM uint32_t TCMEARC1; /*!< (@ 0x00000054) TCM Error Address Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t EAR : 16; /*!< [17..2] When an SRAM error occurs, it stores an error address */ + uint32_t : 14; + } TCMEARC1_b; + }; + + union + { + __IOM uint32_t TCMEARS0; /*!< (@ 0x00000058) TCM Error Address Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t EAR : 16; /*!< [17..2] When an SRAM error occurs, it stores an error address */ + uint32_t : 14; + } TCMEARS0_b; + }; + + union + { + __IOM uint32_t TCMEARS1; /*!< (@ 0x0000005C) TCM Error Address Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t EAR : 16; /*!< [17..2] When an SRAM error occurs, it stores an error address */ + uint32_t : 14; + } TCMEARS1_b; + }; +} R_TCM_Type; /*!< Size = 96 (0x60) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #if defined(_RA_TZ_NONSECURE) + #define BASE_NS_OFFSET (BSP_FEATURE_TZ_NS_OFFSET) + #else + #define BASE_NS_OFFSET 0U + #endif + + #define R_ACMPHS0_BASE (0x40236000UL + BASE_NS_OFFSET) + #define R_ACMPHS1_BASE (0x40236100UL + BASE_NS_OFFSET) + #define R_ACMPHS2_BASE (0x40236200UL + BASE_NS_OFFSET) + #define R_ACMPHS3_BASE (0x40236300UL + BASE_NS_OFFSET) + #define R_ACMPHS4_BASE (0x40236400UL + BASE_NS_OFFSET) + #define R_ACMPHS5_BASE (0x40236500UL + BASE_NS_OFFSET) + #define R_PSCU_BASE (0x40204000UL + BASE_NS_OFFSET) + #define R_BUS_BASE (0x40003000UL + BASE_NS_OFFSET) + #define R_CAC_BASE (0x40202400UL + BASE_NS_OFFSET) + #define R_CANFD_BASE (0x40380000UL + BASE_NS_OFFSET) + #define R_CANFD1_BASE (0x40382000UL + BASE_NS_OFFSET) + #define R_CRC_BASE (0x40310000UL + BASE_NS_OFFSET) + #define R_DAC_B0_BASE (0x40233000UL + BASE_NS_OFFSET) + #define R_DAC_B1_BASE (0x40233100UL + BASE_NS_OFFSET) + #define R_DEBUG_BASE (0x4001B000UL + BASE_NS_OFFSET) + #define R_DMA_BASE (0x4000A800UL + BASE_NS_OFFSET) + #define R_DMAC0_BASE (0x4000A000UL + BASE_NS_OFFSET) + #define R_DMAC1_BASE (0x4000A040UL + BASE_NS_OFFSET) + #define R_DMAC2_BASE (0x4000A080UL + BASE_NS_OFFSET) + #define R_DMAC3_BASE (0x4000A0C0UL + BASE_NS_OFFSET) + #define R_DMAC4_BASE (0x4000A100UL + BASE_NS_OFFSET) + #define R_DMAC5_BASE (0x4000A140UL + BASE_NS_OFFSET) + #define R_DMAC6_BASE (0x4000A180UL + BASE_NS_OFFSET) + #define R_DMAC7_BASE (0x4000A1C0UL + BASE_NS_OFFSET) + #define R_DOC_BASE (0x40311000UL + BASE_NS_OFFSET) + #define R_DRW_BASE (0x40444000UL + BASE_NS_OFFSET) + #define R_DTC_BASE (0x4000AC00UL + BASE_NS_OFFSET) + #define R_ELC_BASE (0x40201000UL + BASE_NS_OFFSET) + #define R_ETHERC_EDMAC_BASE (0x40354000UL + BASE_NS_OFFSET) + #define R_GLCDC_BASE (0x40342000UL + BASE_NS_OFFSET) + #define R_GPT0_BASE (0x40322000UL + BASE_NS_OFFSET) + #define R_GPT1_BASE (0x40322100UL + BASE_NS_OFFSET) + #define R_GPT2_BASE (0x40322200UL + BASE_NS_OFFSET) + #define R_GPT3_BASE (0x40322300UL + BASE_NS_OFFSET) + #define R_GPT4_BASE (0x40322400UL + BASE_NS_OFFSET) + #define R_GPT5_BASE (0x40322500UL + BASE_NS_OFFSET) + #define R_GPT6_BASE (0x40322600UL + BASE_NS_OFFSET) + #define R_GPT7_BASE (0x40322700UL + BASE_NS_OFFSET) + #define R_GPT8_BASE (0x40322800UL + BASE_NS_OFFSET) + #define R_GPT9_BASE (0x40322900UL + BASE_NS_OFFSET) + #define R_GPT10_BASE (0x40322A00UL + BASE_NS_OFFSET) + #define R_GPT11_BASE (0x40322B00UL + BASE_NS_OFFSET) + #define R_GPT12_BASE (0x40322C00UL + BASE_NS_OFFSET) + #define R_GPT13_BASE (0x40322D00UL + BASE_NS_OFFSET) + #define R_GPT_GTCLK_BASE (0x40323F10UL + BASE_NS_OFFSET) + #define R_GPT_ODC_BASE (0x40324000UL + BASE_NS_OFFSET) + #define R_GPT_OPS_BASE (0x40323F00UL + BASE_NS_OFFSET) + #define R_GPT_POEG0_BASE (0x40212000UL + BASE_NS_OFFSET) + #define R_GPT_POEG1_BASE (0x40212100UL + BASE_NS_OFFSET) + #define R_GPT_POEG2_BASE (0x40212200UL + BASE_NS_OFFSET) + #define R_GPT_POEG3_BASE (0x40212300UL + BASE_NS_OFFSET) + #define R_ICU_BASE (0x40006000UL + BASE_NS_OFFSET) + #define R_IIC0_BASE (0x4025E000UL + BASE_NS_OFFSET) + #define R_IIC1_BASE (0x4025E100UL + BASE_NS_OFFSET) + #define R_IIC2_BASE (0x4025E200UL + BASE_NS_OFFSET) + #define R_IWDT_BASE (0x40202200UL + BASE_NS_OFFSET) + #define R_I3C0_BASE (0x4035F000UL + BASE_NS_OFFSET) + #define R_I3C1_BASE (0x4035F100UL + BASE_NS_OFFSET) + #define R_MPU_MMPU_BASE (0x40000000UL + BASE_NS_OFFSET) + #define R_MPU_SPMON_BASE (0x40000D00UL + BASE_NS_OFFSET) + #define R_MSTP_BASE (0x40203000UL + BASE_NS_OFFSET) + #define R_PORT0_BASE (0x40400000UL + BASE_NS_OFFSET) + #define R_PORT1_BASE (0x40400020UL + BASE_NS_OFFSET) + #define R_PORT2_BASE (0x40400040UL + BASE_NS_OFFSET) + #define R_PORT3_BASE (0x40400060UL + BASE_NS_OFFSET) + #define R_PORT4_BASE (0x40400080UL + BASE_NS_OFFSET) + #define R_PORT5_BASE (0x404000A0UL + BASE_NS_OFFSET) + #define R_PORT6_BASE (0x404000C0UL + BASE_NS_OFFSET) + #define R_PORT7_BASE (0x404000E0UL + BASE_NS_OFFSET) + #define R_PORT8_BASE (0x40400100UL + BASE_NS_OFFSET) + #define R_PORT9_BASE (0x40400120UL + BASE_NS_OFFSET) + #define R_PORT10_BASE (0x40400140UL + BASE_NS_OFFSET) + #define R_PORT11_BASE (0x40400160UL + BASE_NS_OFFSET) + #define R_PORT12_BASE (0x40400180UL + BASE_NS_OFFSET) + #define R_PORT13_BASE (0x404001A0UL + BASE_NS_OFFSET) + #define R_PORT14_BASE (0x404001C0UL + BASE_NS_OFFSET) + #define R_PFS_BASE (0x40400800UL + BASE_NS_OFFSET) + #define R_PMISC_BASE (0x40400D00UL + BASE_NS_OFFSET) + #define R_RTC_BASE (0x40202000UL + BASE_NS_OFFSET) + #define R_SCI0_BASE (0x40358000UL + BASE_NS_OFFSET) + #define R_SCI1_BASE (0x40358100UL + BASE_NS_OFFSET) + #define R_SCI2_BASE (0x40358200UL + BASE_NS_OFFSET) + #define R_SCI3_BASE (0x40358300UL + BASE_NS_OFFSET) + #define R_SCI4_BASE (0x40358400UL + BASE_NS_OFFSET) + #define R_SCI5_BASE (0x40358500UL + BASE_NS_OFFSET) + #define R_SCI6_BASE (0x40358600UL + BASE_NS_OFFSET) + #define R_SCI7_BASE (0x40358700UL + BASE_NS_OFFSET) + #define R_SCI8_BASE (0x40358800UL + BASE_NS_OFFSET) + #define R_SCI9_BASE (0x40358900UL + BASE_NS_OFFSET) + #define R_SDHI0_BASE (0x40252000UL + BASE_NS_OFFSET) + #define R_SDHI1_BASE (0x40252400UL + BASE_NS_OFFSET) + #define R_SPI0_BASE (0x4035C000UL + BASE_NS_OFFSET) + #define R_SPI1_BASE (0x4035C100UL + BASE_NS_OFFSET) + #define R_SPI2_BASE (0x40072200UL + BASE_NS_OFFSET) + #define R_SRAM_BASE (0x40002000UL + BASE_NS_OFFSET) + #define R_SSI0_BASE (0x4025D000UL + BASE_NS_OFFSET) + #define R_SSI1_BASE (0x4025D100UL + BASE_NS_OFFSET) + #define R_SYSTEM_BASE (0x4001E000UL + BASE_NS_OFFSET) + #define R_TSN_CAL_BASE (0x02C1EDA0UL + BASE_NS_OFFSET) + #define R_TSN_CTRL_BASE (0x40235000UL + BASE_NS_OFFSET) + #define R_USB_FS0_BASE (0x40250000UL + BASE_NS_OFFSET) + #define R_VIN_BASE (0x40347400UL + BASE_NS_OFFSET) + #define R_WDT_BASE (0x40202600UL + BASE_NS_OFFSET) + #define R_CACHE_BASE (0x4001C000UL + BASE_NS_OFFSET) + #define R_CPSCU_BASE (0x40008000UL + BASE_NS_OFFSET) + #define R_ADC_B0_BASE (0x40338000UL + BASE_NS_OFFSET) + #define R_DOC_B_BASE (0x40311000UL + BASE_NS_OFFSET) + #define R_SCI_B0_BASE (0x40358000UL + BASE_NS_OFFSET) + #define R_SCI_B1_BASE (0x40358100UL + BASE_NS_OFFSET) + #define R_SCI_B2_BASE (0x40358200UL + BASE_NS_OFFSET) + #define R_SCI_B3_BASE (0x40358300UL + BASE_NS_OFFSET) + #define R_SCI_B4_BASE (0x40358400UL + BASE_NS_OFFSET) + #define R_SCI_B9_BASE (0x40358900UL + BASE_NS_OFFSET) + #define R_SPI_B0_BASE (0x4035C000UL + BASE_NS_OFFSET) + #define R_SPI_B1_BASE (0x4035C100UL + BASE_NS_OFFSET) + #define R_USB_HS0_BASE (0x40351000UL + BASE_NS_OFFSET) + #define R_XSPI0_BASE (0x40268000UL + BASE_NS_OFFSET) + #define R_XSPI1_BASE (0x40268400UL + BASE_NS_OFFSET) + #define R_MIPI_PHY_BASE (0x40346C00UL + BASE_NS_OFFSET) + #define R_MIPI_CSI_BASE (0x40347000UL + BASE_NS_OFFSET) + #define R_CEU_BASE (0x40348000UL + BASE_NS_OFFSET) + #define R_ULPT0_BASE (0x40220000UL + BASE_NS_OFFSET) + #define R_ULPT1_BASE (0x40220100UL + BASE_NS_OFFSET) + #define R_DEBUG_OCD_BASE (0x40011000UL + BASE_NS_OFFSET) + #define R_DOTF_BASE (0x40268800UL + BASE_NS_OFFSET) + #define R_AGTX0_BASE (0x40221000UL + BASE_NS_OFFSET) + #define R_AGTX1_BASE (0x40221100UL + BASE_NS_OFFSET) + #define R_AGTX2_BASE (0x40221200UL + BASE_NS_OFFSET) + #define R_AGTX3_BASE (0x40221300UL + BASE_NS_OFFSET) + #define R_AGTX4_BASE (0x40221400UL + BASE_NS_OFFSET) + #define R_AGTX5_BASE (0x40221500UL + BASE_NS_OFFSET) + #define R_AGTX6_BASE (0x40221600UL + BASE_NS_OFFSET) + #define R_AGTX7_BASE (0x40221700UL + BASE_NS_OFFSET) + #define R_AGTX8_BASE (0x40221800UL + BASE_NS_OFFSET) + #define R_AGTX9_BASE (0x40221900UL + BASE_NS_OFFSET) + #define R_COMA_BASE (0x403C9000UL + BASE_NS_OFFSET) + #define R_CPU_CTRL_BASE (0x4000F000UL + BASE_NS_OFFSET) + #define R_DOTF1_BASE (0x40268900UL + BASE_NS_OFFSET) + #define R_ECCMB0_BASE (0x4036F200UL + BASE_NS_OFFSET) + #define R_ECCMB1_BASE (0x4036F300UL + BASE_NS_OFFSET) + #define R_ESWM_BASE (0x403C8000UL + BASE_NS_OFFSET) + #define R_ETHA0_BASE (0x403CA000UL + BASE_NS_OFFSET) + #define R_ETHA1_BASE (0x403CC000UL + BASE_NS_OFFSET) + #define R_GPTP_BASE (0x403E0000UL + BASE_NS_OFFSET) + #define R_GWCA0_BASE (0x403CE000UL + BASE_NS_OFFSET) + #define R_IPC_BASE (0x40020000UL + BASE_NS_OFFSET) + #define R_MFWD_BASE (0x403C0000UL + BASE_NS_OFFSET) + #define R_MIPI_DSI_BASE (0x40346000UL + BASE_NS_OFFSET) + #define R_MRMS_BASE (0x4013C000UL + BASE_NS_OFFSET) + #define R_NPU_BASE (0x40140000UL + BASE_NS_OFFSET) + #define R_PDM_BASE (0x40256000UL + BASE_NS_OFFSET) + #define R_RMAC0_BASE (0x403CB000UL + BASE_NS_OFFSET) + #define R_RMAC1_BASE (0x403CD000UL + BASE_NS_OFFSET) + #define R_SCI_B5_BASE (0x40358500UL + BASE_NS_OFFSET) + #define R_SCI_B6_BASE (0x40358600UL + BASE_NS_OFFSET) + #define R_SCI_B7_BASE (0x40358700UL + BASE_NS_OFFSET) + #define R_SCI_B8_BASE (0x40358800UL + BASE_NS_OFFSET) + #define R_TCM_BASE (0x4001C800UL + BASE_NS_OFFSET) + #define R_WDT1_BASE (0x40202700UL + BASE_NS_OFFSET) + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_ACMPHS0 ((R_ACMPHS0_Type *) R_ACMPHS0_BASE) + #define R_ACMPHS1 ((R_ACMPHS0_Type *) R_ACMPHS1_BASE) + #define R_ACMPHS2 ((R_ACMPHS0_Type *) R_ACMPHS2_BASE) + #define R_ACMPHS3 ((R_ACMPHS0_Type *) R_ACMPHS3_BASE) + #define R_ACMPHS4 ((R_ACMPHS0_Type *) R_ACMPHS4_BASE) + #define R_ACMPHS5 ((R_ACMPHS0_Type *) R_ACMPHS5_BASE) + #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE) + #define R_CANFD0 ((R_CANFD_Type *) R_CANFD_BASE) + #define R_CANFD1 ((R_CANFD_Type *) R_CANFD1_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #define R_DAC_B0 ((R_DAC_B0_Type *) R_DAC_B0_BASE) + #define R_DAC_B1 ((R_DAC_B0_Type *) R_DAC_B1_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DMA ((R_DMA_Type *) R_DMA_BASE) + #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) + #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) + #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) + #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) + #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) + #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) + #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) + #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_DRW ((R_DRW_Type *) R_DRW_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE) + #define R_GLCDC ((R_GLCDC_Type *) R_GLCDC_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_GPT_GTCLK ((R_GPT_GTCLK_Type *) R_GPT_GTCLK_BASE) + #define R_GPT_ODC ((R_GPT_ODC_Type *) R_GPT_ODC_BASE) + #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE) + #define R_I3C1 ((R_I3C0_Type *) R_I3C1_BASE) + #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) + #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) + #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) + #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) + #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE) + #define R_SDHI1 ((R_SDHI0_Type *) R_SDHI1_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SPI2 ((R_SPI0_Type *) R_SPI2_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) + #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) + #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) + #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) + #define R_VIN ((R_VIN_Type *) R_VIN_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + #define R_CACHE ((R_CACHE_Type *) R_CACHE_BASE) + #define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE) + #define R_ADC_B ((R_ADC_B0_Type *) R_ADC_B0_BASE) + #define R_DOC_B ((R_DOC_B_Type *) R_DOC_B_BASE) + #define R_SCI_B0 ((R_SCI_B0_Type *) R_SCI_B0_BASE) + #define R_SCI_B1 ((R_SCI_B0_Type *) R_SCI_B1_BASE) + #define R_SCI_B2 ((R_SCI_B0_Type *) R_SCI_B2_BASE) + #define R_SCI_B3 ((R_SCI_B0_Type *) R_SCI_B3_BASE) + #define R_SCI_B4 ((R_SCI_B0_Type *) R_SCI_B4_BASE) + #define R_SCI_B9 ((R_SCI_B0_Type *) R_SCI_B9_BASE) + #define R_SPI_B0 ((R_SPI_B0_Type *) R_SPI_B0_BASE) + #define R_SPI_B1 ((R_SPI_B0_Type *) R_SPI_B1_BASE) + #define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE) + #define R_XSPI0 ((R_XSPI0_Type *) R_XSPI0_BASE) + #define R_XSPI1 ((R_XSPI0_Type *) R_XSPI1_BASE) + #define R_MIPI_PHY ((R_MIPI_PHY_Type *) R_MIPI_PHY_BASE) + #define R_MIPI_CSI ((R_MIPI_CSI_Type *) R_MIPI_CSI_BASE) + #define R_CEU ((R_CEU_Type *) R_CEU_BASE) + #define R_ULPT0 ((R_ULPT0_Type *) R_ULPT0_BASE) + #define R_ULPT1 ((R_ULPT0_Type *) R_ULPT1_BASE) + #define R_DEBUG_OCD ((R_DEBUG_OCD_Type *) R_DEBUG_OCD_BASE) + #define R_DOTF ((R_DOTF_Type *) R_DOTF_BASE) + #define R_AGT0 ((R_AGTX0_Type *) R_AGTX0_BASE) + #define R_AGT1 ((R_AGTX0_Type *) R_AGTX1_BASE) + #define R_AGT2 ((R_AGTX0_Type *) R_AGTX2_BASE) + #define R_AGT3 ((R_AGTX0_Type *) R_AGTX3_BASE) + #define R_AGT4 ((R_AGTX0_Type *) R_AGTX4_BASE) + #define R_AGT5 ((R_AGTX0_Type *) R_AGTX5_BASE) + #define R_AGT6 ((R_AGTX0_Type *) R_AGTX6_BASE) + #define R_AGT7 ((R_AGTX0_Type *) R_AGTX7_BASE) + #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) + #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) + #define R_COMA ((R_COMA_Type *) R_COMA_BASE) + #define R_CPU_CTRL ((R_CPU_CTRL_Type *) R_CPU_CTRL_BASE) + #define R_DOTF1 ((R_DOTF_Type *) R_DOTF1_BASE) + #define R_ECCMB0 ((R_ECCMB0_Type *) R_ECCMB0_BASE) + #define R_ECCMB1 ((R_ECCMB0_Type *) R_ECCMB1_BASE) + #define R_ESWM ((R_ESWM_Type *) R_ESWM_BASE) + #define R_ETHA0 ((R_ETHA0_Type *) R_ETHA0_BASE) + #define R_ETHA1 ((R_ETHA0_Type *) R_ETHA1_BASE) + #define R_GPTP ((R_GPTP_Type *) R_GPTP_BASE) + #define R_GWCA0 ((R_GWCA0_Type *) R_GWCA0_BASE) + #define R_IPC ((R_IPC_Type *) R_IPC_BASE) + #define R_MFWD ((R_MFWD_Type *) R_MFWD_BASE) + #define R_MIPI_DSI ((R_MIPI_DSI_Type *) R_MIPI_DSI_BASE) + #define R_MRMS ((R_MRMS_Type *) R_MRMS_BASE) + #define R_NPU ((R_NPU_Type *) R_NPU_BASE) + #define R_PDM ((R_PDM_Type *) R_PDM_BASE) + #define R_RMAC0 ((R_RMAC0_Type *) R_RMAC0_BASE) + #define R_RMAC1 ((R_RMAC0_Type *) R_RMAC1_BASE) + #define R_SCI_B5 ((R_SCI_B0_Type *) R_SCI_B5_BASE) + #define R_SCI_B6 ((R_SCI_B0_Type *) R_SCI_B6_BASE) + #define R_SCI_B7 ((R_SCI_B0_Type *) R_SCI_B7_BASE) + #define R_SCI_B8 ((R_SCI_B0_Type *) R_SCI_B8_BASE) + #define R_TCM ((R_TCM_Type *) R_TCM_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ SDRAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SDCCR ========================================================= */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCMOD ========================================================= */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDAMOD ========================================================= */ + #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDSELF ========================================================= */ + #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ + #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDRFCR ========================================================= */ + #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ + #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ +/* ======================================================== SDRFEN ========================================================= */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SDICR ========================================================= */ + #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ + #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SDIR ========================================================== */ + #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ + #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ + #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ + #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ +/* ========================================================= SDADR ========================================================= */ + #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ + #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ +/* ========================================================= SDTR ========================================================== */ + #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ + #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ + #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ + #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ + #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ + #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ +/* ========================================================= SDMOD ========================================================= */ + #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ + #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ +/* ========================================================= SDSR ========================================================== */ + #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ + #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ + #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ + #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU1TCMBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ + #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ + #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CFDC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= NCFG ========================================================== */ + #define R_CANFD_CFDC_NCFG_NBRP_Pos (0UL) /*!< NBRP (Bit 0) */ + #define R_CANFD_CFDC_NCFG_NBRP_Msk (0x3ffUL) /*!< NBRP (Bitfield-Mask: 0x3ff) */ + #define R_CANFD_CFDC_NCFG_NSJW_Pos (10UL) /*!< NSJW (Bit 10) */ + #define R_CANFD_CFDC_NCFG_NSJW_Msk (0x1fc00UL) /*!< NSJW (Bitfield-Mask: 0x7f) */ + #define R_CANFD_CFDC_NCFG_NTSEG1_Pos (17UL) /*!< NTSEG1 (Bit 17) */ + #define R_CANFD_CFDC_NCFG_NTSEG1_Msk (0x1fe0000UL) /*!< NTSEG1 (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC_NCFG_NTSEG2_Pos (25UL) /*!< NTSEG2 (Bit 25) */ + #define R_CANFD_CFDC_NCFG_NTSEG2_Msk (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f) */ +/* ========================================================== CTR ========================================================== */ + #define R_CANFD_CFDC_CTR_CHMDC_Pos (0UL) /*!< CHMDC (Bit 0) */ + #define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_CSLPR_Pos (2UL) /*!< CSLPR (Bit 2) */ + #define R_CANFD_CFDC_CTR_CSLPR_Msk (0x4UL) /*!< CSLPR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_RTBO_Pos (3UL) /*!< RTBO (Bit 3) */ + #define R_CANFD_CFDC_CTR_RTBO_Msk (0x8UL) /*!< RTBO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BEIE_Pos (8UL) /*!< BEIE (Bit 8) */ + #define R_CANFD_CFDC_CTR_BEIE_Msk (0x100UL) /*!< BEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EWIE_Pos (9UL) /*!< EWIE (Bit 9) */ + #define R_CANFD_CFDC_CTR_EWIE_Msk (0x200UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EPIE_Pos (10UL) /*!< EPIE (Bit 10) */ + #define R_CANFD_CFDC_CTR_EPIE_Msk (0x400UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BOEIE_Pos (11UL) /*!< BOEIE (Bit 11) */ + #define R_CANFD_CFDC_CTR_BOEIE_Msk (0x800UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BORIE_Pos (12UL) /*!< BORIE (Bit 12) */ + #define R_CANFD_CFDC_CTR_BORIE_Msk (0x1000UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_OLIE_Pos (13UL) /*!< OLIE (Bit 13) */ + #define R_CANFD_CFDC_CTR_OLIE_Msk (0x2000UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BLIE_Pos (14UL) /*!< BLIE (Bit 14) */ + #define R_CANFD_CFDC_CTR_BLIE_Msk (0x4000UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_ALIE_Pos (15UL) /*!< ALIE (Bit 15) */ + #define R_CANFD_CFDC_CTR_ALIE_Msk (0x8000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TAIE_Pos (16UL) /*!< TAIE (Bit 16) */ + #define R_CANFD_CFDC_CTR_TAIE_Msk (0x10000UL) /*!< TAIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EOCOIE_Pos (17UL) /*!< EOCOIE (Bit 17) */ + #define R_CANFD_CFDC_CTR_EOCOIE_Msk (0x20000UL) /*!< EOCOIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_SOCOIE_Pos (18UL) /*!< SOCOIE (Bit 18) */ + #define R_CANFD_CFDC_CTR_SOCOIE_Msk (0x40000UL) /*!< SOCOIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TDCVFIE_Pos (19UL) /*!< TDCVFIE (Bit 19) */ + #define R_CANFD_CFDC_CTR_TDCVFIE_Msk (0x80000UL) /*!< TDCVFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BOM_Pos (21UL) /*!< BOM (Bit 21) */ + #define R_CANFD_CFDC_CTR_BOM_Msk (0x600000UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_ERRD_Pos (23UL) /*!< ERRD (Bit 23) */ + #define R_CANFD_CFDC_CTR_ERRD_Msk (0x800000UL) /*!< ERRD (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_CTME_Pos (24UL) /*!< CTME (Bit 24) */ + #define R_CANFD_CFDC_CTR_CTME_Msk (0x1000000UL) /*!< CTME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_CTMS_Pos (25UL) /*!< CTMS (Bit 25) */ + #define R_CANFD_CFDC_CTR_CTMS_Msk (0x6000000UL) /*!< CTMS (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_CRCT_Pos (30UL) /*!< CRCT (Bit 30) */ + #define R_CANFD_CFDC_CTR_CRCT_Msk (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_ROM_Pos (31UL) /*!< ROM (Bit 31) */ + #define R_CANFD_CFDC_CTR_ROM_Msk (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01) */ +/* ========================================================== STS ========================================================== */ + #define R_CANFD_CFDC_STS_CRSTSTS_Pos (0UL) /*!< CRSTSTS (Bit 0) */ + #define R_CANFD_CFDC_STS_CRSTSTS_Msk (0x1UL) /*!< CRSTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_CHLTSTS_Pos (1UL) /*!< CHLTSTS (Bit 1) */ + #define R_CANFD_CFDC_STS_CHLTSTS_Msk (0x2UL) /*!< CHLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_CSLPSTS_Pos (2UL) /*!< CSLPSTS (Bit 2) */ + #define R_CANFD_CFDC_STS_CSLPSTS_Msk (0x4UL) /*!< CSLPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_EPSTS_Pos (3UL) /*!< EPSTS (Bit 3) */ + #define R_CANFD_CFDC_STS_EPSTS_Msk (0x8UL) /*!< EPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_BOSTS_Pos (4UL) /*!< BOSTS (Bit 4) */ + #define R_CANFD_CFDC_STS_BOSTS_Msk (0x10UL) /*!< BOSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_TRMSTS_Pos (5UL) /*!< TRMSTS (Bit 5) */ + #define R_CANFD_CFDC_STS_TRMSTS_Msk (0x20UL) /*!< TRMSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_RECSTS_Pos (6UL) /*!< RECSTS (Bit 6) */ + #define R_CANFD_CFDC_STS_RECSTS_Msk (0x40UL) /*!< RECSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_COMSTS_Pos (7UL) /*!< COMSTS (Bit 7) */ + #define R_CANFD_CFDC_STS_COMSTS_Msk (0x80UL) /*!< COMSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_ESIF_Pos (8UL) /*!< ESIF (Bit 8) */ + #define R_CANFD_CFDC_STS_ESIF_Msk (0x100UL) /*!< ESIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_REC_Pos (16UL) /*!< REC (Bit 16) */ + #define R_CANFD_CFDC_STS_REC_Msk (0xff0000UL) /*!< REC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC_STS_TEC_Pos (24UL) /*!< TEC (Bit 24) */ + #define R_CANFD_CFDC_STS_TEC_Msk (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff) */ +/* ========================================================= ERFL ========================================================== */ + #define R_CANFD_CFDC_ERFL_BEF_Pos (0UL) /*!< BEF (Bit 0) */ + #define R_CANFD_CFDC_ERFL_BEF_Msk (0x1UL) /*!< BEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_EWF_Pos (1UL) /*!< EWF (Bit 1) */ + #define R_CANFD_CFDC_ERFL_EWF_Msk (0x2UL) /*!< EWF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_EPF_Pos (2UL) /*!< EPF (Bit 2) */ + #define R_CANFD_CFDC_ERFL_EPF_Msk (0x4UL) /*!< EPF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BOEF_Pos (3UL) /*!< BOEF (Bit 3) */ + #define R_CANFD_CFDC_ERFL_BOEF_Msk (0x8UL) /*!< BOEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BORF_Pos (4UL) /*!< BORF (Bit 4) */ + #define R_CANFD_CFDC_ERFL_BORF_Msk (0x10UL) /*!< BORF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_OVLF_Pos (5UL) /*!< OVLF (Bit 5) */ + #define R_CANFD_CFDC_ERFL_OVLF_Msk (0x20UL) /*!< OVLF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BLF_Pos (6UL) /*!< BLF (Bit 6) */ + #define R_CANFD_CFDC_ERFL_BLF_Msk (0x40UL) /*!< BLF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_ALF_Pos (7UL) /*!< ALF (Bit 7) */ + #define R_CANFD_CFDC_ERFL_ALF_Msk (0x80UL) /*!< ALF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_SERR_Pos (8UL) /*!< SERR (Bit 8) */ + #define R_CANFD_CFDC_ERFL_SERR_Msk (0x100UL) /*!< SERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_FERR_Pos (9UL) /*!< FERR (Bit 9) */ + #define R_CANFD_CFDC_ERFL_FERR_Msk (0x200UL) /*!< FERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_AERR_Pos (10UL) /*!< AERR (Bit 10) */ + #define R_CANFD_CFDC_ERFL_AERR_Msk (0x400UL) /*!< AERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_CERR_Pos (11UL) /*!< CERR (Bit 11) */ + #define R_CANFD_CFDC_ERFL_CERR_Msk (0x800UL) /*!< CERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_B1ERR_Pos (12UL) /*!< B1ERR (Bit 12) */ + #define R_CANFD_CFDC_ERFL_B1ERR_Msk (0x1000UL) /*!< B1ERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_B0ERR_Pos (13UL) /*!< B0ERR (Bit 13) */ + #define R_CANFD_CFDC_ERFL_B0ERR_Msk (0x2000UL) /*!< B0ERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_ADERR_Pos (14UL) /*!< ADERR (Bit 14) */ + #define R_CANFD_CFDC_ERFL_ADERR_Msk (0x4000UL) /*!< ADERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_CRCREG_Pos (16UL) /*!< CRCREG (Bit 16) */ + #define R_CANFD_CFDC_ERFL_CRCREG_Msk (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff) */ + +/* =========================================================================================================================== */ +/* ================ CFDC2 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DCFG ========================================================== */ + #define R_CANFD_CFDC2_DCFG_DBRP_Pos (0UL) /*!< DBRP (Bit 0) */ + #define R_CANFD_CFDC2_DCFG_DBRP_Msk (0xffUL) /*!< DBRP (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos (8UL) /*!< DTSEG1 (Bit 8) */ + #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk (0x1f00UL) /*!< DTSEG1 (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos (16UL) /*!< DTSEG2 (Bit 16) */ + #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk (0xf0000UL) /*!< DTSEG2 (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDC2_DCFG_DSJW_Pos (24UL) /*!< DSJW (Bit 24) */ + #define R_CANFD_CFDC2_DCFG_DSJW_Msk (0xf000000UL) /*!< DSJW (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCFG ========================================================= */ + #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos (0UL) /*!< EOCCFG (Bit 0) */ + #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk (0x7UL) /*!< EOCCFG (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos (8UL) /*!< TDCOC (Bit 8) */ + #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk (0x100UL) /*!< TDCOC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_TDCE_Pos (9UL) /*!< TDCE (Bit 9) */ + #define R_CANFD_CFDC2_FDCFG_TDCE_Msk (0x200UL) /*!< TDCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_ESIC_Pos (10UL) /*!< ESIC (Bit 10) */ + #define R_CANFD_CFDC2_FDCFG_ESIC_Msk (0x400UL) /*!< ESIC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_TDCO_Pos (16UL) /*!< TDCO (Bit 16) */ + #define R_CANFD_CFDC2_FDCFG_TDCO_Msk (0xff0000UL) /*!< TDCO (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDCFG_FDOE_Pos (28UL) /*!< FDOE (Bit 28) */ + #define R_CANFD_CFDC2_FDCFG_FDOE_Msk (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_REFE_Pos (29UL) /*!< REFE (Bit 29) */ + #define R_CANFD_CFDC2_FDCFG_REFE_Msk (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_CLOE_Pos (30UL) /*!< CLOE (Bit 30) */ + #define R_CANFD_CFDC2_FDCFG_CLOE_Msk (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01) */ +/* ========================================================= FDCTR ========================================================= */ + #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos (0UL) /*!< EOCCLR (Bit 0) */ + #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk (0x1UL) /*!< EOCCLR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos (1UL) /*!< SOCCLR (Bit 1) */ + #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk (0x2UL) /*!< SOCCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDC2_FDSTS_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ + #define R_CANFD_CFDC2_FDSTS_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDSTS_EOCO_Pos (8UL) /*!< EOCO (Bit 8) */ + #define R_CANFD_CFDC2_FDSTS_EOCO_Msk (0x100UL) /*!< EOCO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_SOCO_Pos (9UL) /*!< SOCO (Bit 9) */ + #define R_CANFD_CFDC2_FDSTS_SOCO_Msk (0x200UL) /*!< SOCO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos (15UL) /*!< TDCVF (Bit 15) */ + #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk (0x8000UL) /*!< TDCVF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_EOC_Pos (16UL) /*!< EOC (Bit 16) */ + #define R_CANFD_CFDC2_FDSTS_EOC_Msk (0xff0000UL) /*!< EOC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDSTS_SOC_Pos (24UL) /*!< SOC (Bit 24) */ + #define R_CANFD_CFDC2_FDSTS_SOC_Msk (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff) */ +/* ========================================================= FDCRC ========================================================= */ + #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos (0UL) /*!< CRCREG (Bit 0) */ + #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk (0x1fffffUL) /*!< CRCREG (Bitfield-Mask: 0x1fffff) */ + #define R_CANFD_CFDC2_FDCRC_SCNT_Pos (24UL) /*!< SCNT (Bit 24) */ + #define R_CANFD_CFDC2_FDCRC_SCNT_Msk (0xf000000UL) /*!< SCNT (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ CFDGAFL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDGAFL_ID_GAFLID_Pos (0UL) /*!< GAFLID (Bit 0) */ + #define R_CANFD_CFDGAFL_ID_GAFLID_Msk (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos (29UL) /*!< GAFLLB (Bit 29) */ + #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos (30UL) /*!< GAFLRTR (Bit 30) */ + #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos (31UL) /*!< GAFLIDE (Bit 31) */ + #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01) */ +/* =========================================================== M =========================================================== */ + #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos (0UL) /*!< GAFLIDM (Bit 0) */ + #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos (29UL) /*!< GAFLIFL1 (Bit 29) */ + #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos (30UL) /*!< GAFLRTRM (Bit 30) */ + #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos (31UL) /*!< GAFLIDEM (Bit 31) */ + #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01) */ +/* ========================================================== P0 =========================================================== */ + #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos (0UL) /*!< GAFLDLC (Bit 0) */ + #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk (0xfUL) /*!< GAFLDLC (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos (7UL) /*!< GAFLIFL0 (Bit 7) */ + #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk (0x80UL) /*!< GAFLIFL0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos (8UL) /*!< GAFLRMDP (Bit 8) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk (0x1f00UL) /*!< GAFLRMDP (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos (15UL) /*!< GAFLRMV (Bit 15) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk (0x8000UL) /*!< GAFLRMV (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos (16UL) /*!< GAFLPTR (Bit 16) */ + #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== P1 =========================================================== */ + #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos (0UL) /*!< GAFLFDP (Bit 0) */ + #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk (0x1ffUL) /*!< GAFLFDP (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ CFDTHL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ACC0 ========================================================== */ + #define R_CANFD_CFDTHL_ACC0_BT_Pos (0UL) /*!< BT (Bit 0) */ + #define R_CANFD_CFDTHL_ACC0_BT_Msk (0x7UL) /*!< BT (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTHL_ACC0_BN_Pos (3UL) /*!< BN (Bit 3) */ + #define R_CANFD_CFDTHL_ACC0_BN_Msk (0x3f8UL) /*!< BN (Bitfield-Mask: 0x7f) */ + #define R_CANFD_CFDTHL_ACC0_TMTS_Pos (16UL) /*!< TMTS (Bit 16) */ + #define R_CANFD_CFDTHL_ACC0_TMTS_Msk (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff) */ +/* ========================================================= ACC1 ========================================================== */ + #define R_CANFD_CFDTHL_ACC1_TID_Pos (0UL) /*!< TID (Bit 0) */ + #define R_CANFD_CFDTHL_ACC1_TID_Msk (0xffffUL) /*!< TID (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDTHL_ACC1_TIFL_Pos (16UL) /*!< TIFL (Bit 16) */ + #define R_CANFD_CFDTHL_ACC1_TIFL_Msk (0x30000UL) /*!< TIFL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CFDRF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDRF_ID_RFID_Pos (0UL) /*!< RFID (Bit 0) */ + #define R_CANFD_CFDRF_ID_RFID_Msk (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDRF_ID_RFRTR_Pos (30UL) /*!< RFRTR (Bit 30) */ + #define R_CANFD_CFDRF_ID_RFRTR_Msk (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_ID_RFIDE_Pos (31UL) /*!< RFIDE (Bit 31) */ + #define R_CANFD_CFDRF_ID_RFIDE_Msk (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDRF_PTR_RFTS_Pos (0UL) /*!< RFTS (Bit 0) */ + #define R_CANFD_CFDRF_PTR_RFTS_Msk (0xffffUL) /*!< RFTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDRF_PTR_RFDLC_Pos (28UL) /*!< RFDLC (Bit 28) */ + #define R_CANFD_CFDRF_PTR_RFDLC_Msk (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDRF_FDSTS_RFESI_Pos (0UL) /*!< RFESI (Bit 0) */ + #define R_CANFD_CFDRF_FDSTS_RFESI_Msk (0x1UL) /*!< RFESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos (1UL) /*!< RFBRS (Bit 1) */ + #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk (0x2UL) /*!< RFBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos (2UL) /*!< RFFDF (Bit 2) */ + #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk (0x4UL) /*!< RFFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos (8UL) /*!< RFIFL (Bit 8) */ + #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk (0x300UL) /*!< RFIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDRF_FDSTS_RFPTR_Pos (16UL) /*!< RFPTR (Bit 16) */ + #define R_CANFD_CFDRF_FDSTS_RFPTR_Msk (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDRF_DF_RFDB_Pos (0UL) /*!< RFDB (Bit 0) */ + #define R_CANFD_CFDRF_DF_RFDB_Msk (0xffUL) /*!< RFDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDCF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */ + #define R_CANFD_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDCF_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDCF_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */ + #define R_CANFD_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */ + #define R_CANFD_CFDCF_ID_CFIDE_Msk (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDCF_PTR_CFTS_Pos (0UL) /*!< CFTS (Bit 0) */ + #define R_CANFD_CFDCF_PTR_CFTS_Msk (0xffffUL) /*!< CFTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDCF_PTR_CFDLC_Pos (28UL) /*!< CFDLC (Bit 28) */ + #define R_CANFD_CFDCF_PTR_CFDLC_Msk (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDCF_FDSTS_CFESI_Pos (0UL) /*!< CFESI (Bit 0) */ + #define R_CANFD_CFDCF_FDSTS_CFESI_Msk (0x1UL) /*!< CFESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFBRS_Pos (1UL) /*!< CFBRS (Bit 1) */ + #define R_CANFD_CFDCF_FDSTS_CFBRS_Msk (0x2UL) /*!< CFBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFFDF_Pos (2UL) /*!< CFFDF (Bit 2) */ + #define R_CANFD_CFDCF_FDSTS_CFFDF_Msk (0x4UL) /*!< CFFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFIFL_Pos (8UL) /*!< CFIFL (Bit 8) */ + #define R_CANFD_CFDCF_FDSTS_CFIFL_Msk (0x300UL) /*!< CFIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDCF_FDSTS_CFPTR_Pos (16UL) /*!< CFPTR (Bit 16) */ + #define R_CANFD_CFDCF_FDSTS_CFPTR_Msk (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDCF_DF_CFDB_Pos (0UL) /*!< CFDB (Bit 0) */ + #define R_CANFD_CFDCF_DF_CFDB_Msk (0xffUL) /*!< CFDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDTM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */ + #define R_CANFD_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDTM_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDTM_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */ + #define R_CANFD_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */ + #define R_CANFD_CFDTM_ID_TMIDE_Msk (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDTM_PTR_TMTS_Pos (0UL) /*!< TMTS (Bit 0) */ + #define R_CANFD_CFDTM_PTR_TMTS_Msk (0xffffUL) /*!< TMTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDTM_PTR_TMDLC_Pos (28UL) /*!< TMDLC (Bit 28) */ + #define R_CANFD_CFDTM_PTR_TMDLC_Msk (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCTR ========================================================= */ + #define R_CANFD_CFDTM_FDCTR_TMESI_Pos (0UL) /*!< TMESI (Bit 0) */ + #define R_CANFD_CFDTM_FDCTR_TMESI_Msk (0x1UL) /*!< TMESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos (1UL) /*!< TMBRS (Bit 1) */ + #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk (0x2UL) /*!< TMBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos (2UL) /*!< TMFDF (Bit 2) */ + #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk (0x4UL) /*!< TMFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos (8UL) /*!< TMIFL (Bit 8) */ + #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk (0x300UL) /*!< TMIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos (16UL) /*!< TMPTR (Bit 16) */ + #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDTM_DF_TMDB_Pos (0UL) /*!< TMDB (Bit 0) */ + #define R_CANFD_CFDTM_DF_TMDB_Msk (0xffUL) /*!< TMDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ RM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDRM_RM_ID_RMID_Pos (0UL) /*!< RMID (Bit 0) */ + #define R_CANFD_CFDRM_RM_ID_RMID_Msk (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDRM_RM_ID_RMRTR_Pos (30UL) /*!< RMRTR (Bit 30) */ + #define R_CANFD_CFDRM_RM_ID_RMRTR_Msk (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_ID_RMIDE_Pos (31UL) /*!< RMIDE (Bit 31) */ + #define R_CANFD_CFDRM_RM_ID_RMIDE_Msk (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDRM_RM_PTR_RMTS_Pos (0UL) /*!< RMTS (Bit 0) */ + #define R_CANFD_CFDRM_RM_PTR_RMTS_Msk (0xffffUL) /*!< RMTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDRM_RM_PTR_RMDLC_Pos (28UL) /*!< RMDLC (Bit 28) */ + #define R_CANFD_CFDRM_RM_PTR_RMDLC_Msk (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Pos (0UL) /*!< RMESI (Bit 0) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Msk (0x1UL) /*!< RMESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Pos (1UL) /*!< RMBRS (Bit 1) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Msk (0x2UL) /*!< RMBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Pos (2UL) /*!< RMFDF (Bit 2) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Msk (0x4UL) /*!< RMFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Pos (8UL) /*!< RMIFL (Bit 8) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Msk (0x300UL) /*!< RMIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Pos (16UL) /*!< RMPTR (Bit 16) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Msk (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDRM_RM_DF_RMDB_Pos (0UL) /*!< RMDB (Bit 0) */ + #define R_CANFD_CFDRM_RM_DF_RMDB_Msk (0xffUL) /*!< RMDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDRM ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ ELSEGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ + #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ + #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ + #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELSR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== HA =========================================================== */ + #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ + #define R_ELC_ELSR_HA_ELS_Msk (0x3ffUL) /*!< ELS (Bitfield-Mask: 0x3ff) */ + +/* =========================================================================================================================== */ +/* ================ BG ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EN =========================================================== */ + #define R_GLCDC_BG_EN_SWRST_Pos (16UL) /*!< SWRST (Bit 16) */ + #define R_GLCDC_BG_EN_SWRST_Msk (0x10000UL) /*!< SWRST (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_EN_VEN_Pos (8UL) /*!< VEN (Bit 8) */ + #define R_GLCDC_BG_EN_VEN_Msk (0x100UL) /*!< VEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_EN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_GLCDC_BG_EN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= PERI ========================================================== */ + #define R_GLCDC_BG_PERI_FV_Pos (16UL) /*!< FV (Bit 16) */ + #define R_GLCDC_BG_PERI_FV_Msk (0x7ff0000UL) /*!< FV (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_BG_PERI_FH_Pos (0UL) /*!< FH (Bit 0) */ + #define R_GLCDC_BG_PERI_FH_Msk (0x7ffUL) /*!< FH (Bitfield-Mask: 0x7ff) */ +/* ========================================================= SYNC ========================================================== */ + #define R_GLCDC_BG_SYNC_VP_Pos (16UL) /*!< VP (Bit 16) */ + #define R_GLCDC_BG_SYNC_VP_Msk (0xf0000UL) /*!< VP (Bitfield-Mask: 0x0f) */ + #define R_GLCDC_BG_SYNC_HP_Pos (0UL) /*!< HP (Bit 0) */ + #define R_GLCDC_BG_SYNC_HP_Msk (0xfUL) /*!< HP (Bitfield-Mask: 0x0f) */ +/* ========================================================= VSIZE ========================================================= */ + #define R_GLCDC_BG_VSIZE_VP_Pos (16UL) /*!< VP (Bit 16) */ + #define R_GLCDC_BG_VSIZE_VP_Msk (0x7ff0000UL) /*!< VP (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_BG_VSIZE_VW_Pos (0UL) /*!< VW (Bit 0) */ + #define R_GLCDC_BG_VSIZE_VW_Msk (0x7ffUL) /*!< VW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= HSIZE ========================================================= */ + #define R_GLCDC_BG_HSIZE_HP_Pos (16UL) /*!< HP (Bit 16) */ + #define R_GLCDC_BG_HSIZE_HP_Msk (0x7ff0000UL) /*!< HP (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_BG_HSIZE_HW_Pos (0UL) /*!< HW (Bit 0) */ + #define R_GLCDC_BG_HSIZE_HW_Msk (0x7ffUL) /*!< HW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== BGC ========================================================== */ + #define R_GLCDC_BG_BGC_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_BG_BGC_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_BG_BGC_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_BG_BGC_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_BG_BGC_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_BG_BGC_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ========================================================== MON ========================================================== */ + #define R_GLCDC_BG_MON_SWRST_Pos (16UL) /*!< SWRST (Bit 16) */ + #define R_GLCDC_BG_MON_SWRST_Msk (0x10000UL) /*!< SWRST (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_MON_VEN_Pos (8UL) /*!< VEN (Bit 8) */ + #define R_GLCDC_BG_MON_VEN_Msk (0x100UL) /*!< VEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_MON_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_GLCDC_BG_MON_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ GR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== VEN ========================================================== */ + #define R_GLCDC_GR_VEN_PVEN_Pos (0UL) /*!< PVEN (Bit 0) */ + #define R_GLCDC_GR_VEN_PVEN_Msk (0x1UL) /*!< PVEN (Bitfield-Mask: 0x01) */ +/* ========================================================= FLMRD ========================================================= */ + #define R_GLCDC_GR_FLMRD_RENB_Pos (0UL) /*!< RENB (Bit 0) */ + #define R_GLCDC_GR_FLMRD_RENB_Msk (0x1UL) /*!< RENB (Bitfield-Mask: 0x01) */ +/* ========================================================= FLM1 ========================================================== */ + #define R_GLCDC_GR_FLM1_BSTMD_Pos (0UL) /*!< BSTMD (Bit 0) */ + #define R_GLCDC_GR_FLM1_BSTMD_Msk (0x3UL) /*!< BSTMD (Bitfield-Mask: 0x03) */ +/* ========================================================= FLM2 ========================================================== */ + #define R_GLCDC_GR_FLM2_BASE_Pos (0UL) /*!< BASE (Bit 0) */ + #define R_GLCDC_GR_FLM2_BASE_Msk (0xffffffffUL) /*!< BASE (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= FLM3 ========================================================== */ + #define R_GLCDC_GR_FLM3_LNOFF_Pos (16UL) /*!< LNOFF (Bit 16) */ + #define R_GLCDC_GR_FLM3_LNOFF_Msk (0xffff0000UL) /*!< LNOFF (Bitfield-Mask: 0xffff) */ +/* ========================================================= FLM5 ========================================================== */ + #define R_GLCDC_GR_FLM5_LNNUM_Pos (16UL) /*!< LNNUM (Bit 16) */ + #define R_GLCDC_GR_FLM5_LNNUM_Msk (0x7ff0000UL) /*!< LNNUM (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_FLM5_DATANUM_Pos (0UL) /*!< DATANUM (Bit 0) */ + #define R_GLCDC_GR_FLM5_DATANUM_Msk (0xffffUL) /*!< DATANUM (Bitfield-Mask: 0xffff) */ +/* ========================================================= FLM6 ========================================================== */ + #define R_GLCDC_GR_FLM6_FORMAT_Pos (28UL) /*!< FORMAT (Bit 28) */ + #define R_GLCDC_GR_FLM6_FORMAT_Msk (0x70000000UL) /*!< FORMAT (Bitfield-Mask: 0x07) */ +/* ========================================================== AB1 ========================================================== */ + #define R_GLCDC_GR_AB1_ARCON_Pos (12UL) /*!< ARCON (Bit 12) */ + #define R_GLCDC_GR_AB1_ARCON_Msk (0x1000UL) /*!< ARCON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_AB1_ARCDISPON_Pos (8UL) /*!< ARCDISPON (Bit 8) */ + #define R_GLCDC_GR_AB1_ARCDISPON_Msk (0x100UL) /*!< ARCDISPON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_AB1_GRCDISPON_Pos (4UL) /*!< GRCDISPON (Bit 4) */ + #define R_GLCDC_GR_AB1_GRCDISPON_Msk (0x10UL) /*!< GRCDISPON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_AB1_DISPSEL_Pos (0UL) /*!< DISPSEL (Bit 0) */ + #define R_GLCDC_GR_AB1_DISPSEL_Msk (0x3UL) /*!< DISPSEL (Bitfield-Mask: 0x03) */ +/* ========================================================== AB2 ========================================================== */ + #define R_GLCDC_GR_AB2_GRCVS_Pos (16UL) /*!< GRCVS (Bit 16) */ + #define R_GLCDC_GR_AB2_GRCVS_Msk (0x7ff0000UL) /*!< GRCVS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB2_GRCVW_Pos (0UL) /*!< GRCVW (Bit 0) */ + #define R_GLCDC_GR_AB2_GRCVW_Msk (0x7ffUL) /*!< GRCVW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB3 ========================================================== */ + #define R_GLCDC_GR_AB3_GRCHS_Pos (16UL) /*!< GRCHS (Bit 16) */ + #define R_GLCDC_GR_AB3_GRCHS_Msk (0x7ff0000UL) /*!< GRCHS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB3_GRCHW_Pos (0UL) /*!< GRCHW (Bit 0) */ + #define R_GLCDC_GR_AB3_GRCHW_Msk (0x7ffUL) /*!< GRCHW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB4 ========================================================== */ + #define R_GLCDC_GR_AB4_ARCVS_Pos (16UL) /*!< ARCVS (Bit 16) */ + #define R_GLCDC_GR_AB4_ARCVS_Msk (0x7ff0000UL) /*!< ARCVS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB4_ARCVW_Pos (0UL) /*!< ARCVW (Bit 0) */ + #define R_GLCDC_GR_AB4_ARCVW_Msk (0x7ffUL) /*!< ARCVW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB5 ========================================================== */ + #define R_GLCDC_GR_AB5_ARCHS_Pos (16UL) /*!< ARCHS (Bit 16) */ + #define R_GLCDC_GR_AB5_ARCHS_Msk (0x7ff0000UL) /*!< ARCHS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB5_ARCHW_Pos (0UL) /*!< ARCHW (Bit 0) */ + #define R_GLCDC_GR_AB5_ARCHW_Msk (0x7ffUL) /*!< ARCHW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB6 ========================================================== */ + #define R_GLCDC_GR_AB6_ARCCOEF_Pos (16UL) /*!< ARCCOEF (Bit 16) */ + #define R_GLCDC_GR_AB6_ARCCOEF_Msk (0x1ff0000UL) /*!< ARCCOEF (Bitfield-Mask: 0x1ff) */ + #define R_GLCDC_GR_AB6_ARCRATE_Pos (0UL) /*!< ARCRATE (Bit 0) */ + #define R_GLCDC_GR_AB6_ARCRATE_Msk (0xffUL) /*!< ARCRATE (Bitfield-Mask: 0xff) */ +/* ========================================================== AB7 ========================================================== */ + #define R_GLCDC_GR_AB7_ARCDEF_Pos (16UL) /*!< ARCDEF (Bit 16) */ + #define R_GLCDC_GR_AB7_ARCDEF_Msk (0xff0000UL) /*!< ARCDEF (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB7_CKON_Pos (0UL) /*!< CKON (Bit 0) */ + #define R_GLCDC_GR_AB7_CKON_Msk (0x1UL) /*!< CKON (Bitfield-Mask: 0x01) */ +/* ========================================================== AB8 ========================================================== */ + #define R_GLCDC_GR_AB8_CKKG_Pos (16UL) /*!< CKKG (Bit 16) */ + #define R_GLCDC_GR_AB8_CKKG_Msk (0xff0000UL) /*!< CKKG (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB8_CKKB_Pos (8UL) /*!< CKKB (Bit 8) */ + #define R_GLCDC_GR_AB8_CKKB_Msk (0xff00UL) /*!< CKKB (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB8_CKKR_Pos (0UL) /*!< CKKR (Bit 0) */ + #define R_GLCDC_GR_AB8_CKKR_Msk (0xffUL) /*!< CKKR (Bitfield-Mask: 0xff) */ +/* ========================================================== AB9 ========================================================== */ + #define R_GLCDC_GR_AB9_CKA_Pos (24UL) /*!< CKA (Bit 24) */ + #define R_GLCDC_GR_AB9_CKA_Msk (0xff000000UL) /*!< CKA (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB9_CKG_Pos (16UL) /*!< CKG (Bit 16) */ + #define R_GLCDC_GR_AB9_CKG_Msk (0xff0000UL) /*!< CKG (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB9_CKB_Pos (8UL) /*!< CKB (Bit 8) */ + #define R_GLCDC_GR_AB9_CKB_Msk (0xff00UL) /*!< CKB (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB9_CKR_Pos (0UL) /*!< CKR (Bit 0) */ + #define R_GLCDC_GR_AB9_CKR_Msk (0xffUL) /*!< CKR (Bitfield-Mask: 0xff) */ +/* ========================================================= BASE ========================================================== */ + #define R_GLCDC_GR_BASE_G_Pos (16UL) /*!< G (Bit 16) */ + #define R_GLCDC_GR_BASE_G_Msk (0xff0000UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_BASE_B_Pos (8UL) /*!< B (Bit 8) */ + #define R_GLCDC_GR_BASE_B_Msk (0xff00UL) /*!< B (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_BASE_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_GLCDC_GR_BASE_R_Msk (0xffUL) /*!< R (Bitfield-Mask: 0xff) */ +/* ======================================================== CLUTINT ======================================================== */ + #define R_GLCDC_GR_CLUTINT_SEL_Pos (16UL) /*!< SEL (Bit 16) */ + #define R_GLCDC_GR_CLUTINT_SEL_Msk (0x10000UL) /*!< SEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_CLUTINT_LINE_Pos (0UL) /*!< LINE (Bit 0) */ + #define R_GLCDC_GR_CLUTINT_LINE_Msk (0x7ffUL) /*!< LINE (Bitfield-Mask: 0x7ff) */ +/* ========================================================== MON ========================================================== */ + #define R_GLCDC_GR_MON_UNDFLST_Pos (16UL) /*!< UNDFLST (Bit 16) */ + #define R_GLCDC_GR_MON_UNDFLST_Msk (0x10000UL) /*!< UNDFLST (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_MON_ARCST_Pos (0UL) /*!< ARCST (Bit 0) */ + #define R_GLCDC_GR_MON_ARCST_Msk (0x1UL) /*!< ARCST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ GAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= LATCH ========================================================= */ + #define R_GLCDC_GAM_LATCH_VEN_Pos (0UL) /*!< VEN (Bit 0) */ + #define R_GLCDC_GAM_LATCH_VEN_Msk (0x1UL) /*!< VEN (Bitfield-Mask: 0x01) */ +/* ======================================================== GAM_SW ========================================================= */ + #define R_GLCDC_GAM_GAM_SW_GAMON_Pos (0UL) /*!< GAMON (Bit 0) */ + #define R_GLCDC_GAM_GAM_SW_GAMON_Msk (0x1UL) /*!< GAMON (Bitfield-Mask: 0x01) */ +/* ========================================================== LUT ========================================================== */ + #define R_GLCDC_GAM_LUT___Pos (0UL) /*!< _ (Bit 0) */ + #define R_GLCDC_GAM_LUT___Msk (0x7ffUL) /*!< _ (Bitfield-Mask: 0x7ff) */ +/* ========================================================= AREA ========================================================== */ + #define R_GLCDC_GAM_AREA___Pos (0UL) /*!< _ (Bit 0) */ + #define R_GLCDC_GAM_AREA___Msk (0x3ffUL) /*!< _ (Bitfield-Mask: 0x3ff) */ + +/* =========================================================================================================================== */ +/* ================ OUT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== VLATCH ========================================================= */ + #define R_GLCDC_OUT_VLATCH_VEN_Pos (0UL) /*!< VEN (Bit 0) */ + #define R_GLCDC_OUT_VLATCH_VEN_Msk (0x1UL) /*!< VEN (Bitfield-Mask: 0x01) */ +/* ========================================================== SET ========================================================== */ + #define R_GLCDC_OUT_SET_ENDIANON_Pos (28UL) /*!< ENDIANON (Bit 28) */ + #define R_GLCDC_OUT_SET_ENDIANON_Msk (0x10000000UL) /*!< ENDIANON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_SET_SWAPON_Pos (24UL) /*!< SWAPON (Bit 24) */ + #define R_GLCDC_OUT_SET_SWAPON_Msk (0x1000000UL) /*!< SWAPON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_SET_FORMAT_Pos (12UL) /*!< FORMAT (Bit 12) */ + #define R_GLCDC_OUT_SET_FORMAT_Msk (0x3000UL) /*!< FORMAT (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_SET_FRQSEL_Pos (8UL) /*!< FRQSEL (Bit 8) */ + #define R_GLCDC_OUT_SET_FRQSEL_Msk (0x300UL) /*!< FRQSEL (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_SET_DIRSEL_Pos (4UL) /*!< DIRSEL (Bit 4) */ + #define R_GLCDC_OUT_SET_DIRSEL_Msk (0x10UL) /*!< DIRSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_SET_PHASE_Pos (0UL) /*!< PHASE (Bit 0) */ + #define R_GLCDC_OUT_SET_PHASE_Msk (0x3UL) /*!< PHASE (Bitfield-Mask: 0x03) */ +/* ======================================================== BRIGHT1 ======================================================== */ + #define R_GLCDC_OUT_BRIGHT1_BRTG_Pos (0UL) /*!< BRTG (Bit 0) */ + #define R_GLCDC_OUT_BRIGHT1_BRTG_Msk (0x3ffUL) /*!< BRTG (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BRIGHT2 ======================================================== */ + #define R_GLCDC_OUT_BRIGHT2_BRTB_Pos (16UL) /*!< BRTB (Bit 16) */ + #define R_GLCDC_OUT_BRIGHT2_BRTB_Msk (0x3ff0000UL) /*!< BRTB (Bitfield-Mask: 0x3ff) */ + #define R_GLCDC_OUT_BRIGHT2_BRTR_Pos (0UL) /*!< BRTR (Bit 0) */ + #define R_GLCDC_OUT_BRIGHT2_BRTR_Msk (0x3ffUL) /*!< BRTR (Bitfield-Mask: 0x3ff) */ +/* ======================================================= CONTRAST ======================================================== */ + #define R_GLCDC_OUT_CONTRAST_CONTG_Pos (16UL) /*!< CONTG (Bit 16) */ + #define R_GLCDC_OUT_CONTRAST_CONTG_Msk (0xff0000UL) /*!< CONTG (Bitfield-Mask: 0xff) */ + #define R_GLCDC_OUT_CONTRAST_CONTB_Pos (8UL) /*!< CONTB (Bit 8) */ + #define R_GLCDC_OUT_CONTRAST_CONTB_Msk (0xff00UL) /*!< CONTB (Bitfield-Mask: 0xff) */ + #define R_GLCDC_OUT_CONTRAST_CONTR_Pos (0UL) /*!< CONTR (Bit 0) */ + #define R_GLCDC_OUT_CONTRAST_CONTR_Msk (0xffUL) /*!< CONTR (Bitfield-Mask: 0xff) */ +/* ========================================================= PDTHA ========================================================= */ + #define R_GLCDC_OUT_PDTHA_SEL_Pos (20UL) /*!< SEL (Bit 20) */ + #define R_GLCDC_OUT_PDTHA_SEL_Msk (0x300000UL) /*!< SEL (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_FORM_Pos (16UL) /*!< FORM (Bit 16) */ + #define R_GLCDC_OUT_PDTHA_FORM_Msk (0x30000UL) /*!< FORM (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PA_Pos (12UL) /*!< PA (Bit 12) */ + #define R_GLCDC_OUT_PDTHA_PA_Msk (0x3000UL) /*!< PA (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PB_Pos (8UL) /*!< PB (Bit 8) */ + #define R_GLCDC_OUT_PDTHA_PB_Msk (0x300UL) /*!< PB (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PC_Pos (4UL) /*!< PC (Bit 4) */ + #define R_GLCDC_OUT_PDTHA_PC_Msk (0x30UL) /*!< PC (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PD_Pos (0UL) /*!< PD (Bit 0) */ + #define R_GLCDC_OUT_PDTHA_PD_Msk (0x3UL) /*!< PD (Bitfield-Mask: 0x03) */ +/* ======================================================= CLKPHASE ======================================================== */ + #define R_GLCDC_OUT_CLKPHASE_FRONTGAM_Pos (12UL) /*!< FRONTGAM (Bit 12) */ + #define R_GLCDC_OUT_CLKPHASE_FRONTGAM_Msk (0x1000UL) /*!< FRONTGAM (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_LCDEDGE_Pos (8UL) /*!< LCDEDGE (Bit 8) */ + #define R_GLCDC_OUT_CLKPHASE_LCDEDGE_Msk (0x100UL) /*!< LCDEDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON0EDGE_Pos (6UL) /*!< TCON0EDGE (Bit 6) */ + #define R_GLCDC_OUT_CLKPHASE_TCON0EDGE_Msk (0x40UL) /*!< TCON0EDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON1EDGE_Pos (5UL) /*!< TCON1EDGE (Bit 5) */ + #define R_GLCDC_OUT_CLKPHASE_TCON1EDGE_Msk (0x20UL) /*!< TCON1EDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON2EDGE_Pos (4UL) /*!< TCON2EDGE (Bit 4) */ + #define R_GLCDC_OUT_CLKPHASE_TCON2EDGE_Msk (0x10UL) /*!< TCON2EDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON3EDGE_Pos (3UL) /*!< TCON3EDGE (Bit 3) */ + #define R_GLCDC_OUT_CLKPHASE_TCON3EDGE_Msk (0x8UL) /*!< TCON3EDGE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ TCON ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TIM ========================================================== */ + #define R_GLCDC_TCON_TIM_HALF_Pos (16UL) /*!< HALF (Bit 16) */ + #define R_GLCDC_TCON_TIM_HALF_Msk (0x7ff0000UL) /*!< HALF (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_TIM_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */ + #define R_GLCDC_TCON_TIM_OFFSET_Msk (0x7ffUL) /*!< OFFSET (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STVA1 ========================================================= */ + #define R_GLCDC_TCON_STVA1_VS_Pos (16UL) /*!< VS (Bit 16) */ + #define R_GLCDC_TCON_STVA1_VS_Msk (0x7ff0000UL) /*!< VS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STVA1_VW_Pos (0UL) /*!< VW (Bit 0) */ + #define R_GLCDC_TCON_STVA1_VW_Msk (0x7ffUL) /*!< VW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STVB1 ========================================================= */ + #define R_GLCDC_TCON_STVB1_VS_Pos (16UL) /*!< VS (Bit 16) */ + #define R_GLCDC_TCON_STVB1_VS_Msk (0x7ff0000UL) /*!< VS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STVB1_VW_Pos (0UL) /*!< VW (Bit 0) */ + #define R_GLCDC_TCON_STVB1_VW_Msk (0x7ffUL) /*!< VW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STVA2 ========================================================= */ + #define R_GLCDC_TCON_STVA2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STVA2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STVA2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STVA2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================= STVB2 ========================================================= */ + #define R_GLCDC_TCON_STVB2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STVB2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STVB2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STVB2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================= STHA1 ========================================================= */ + #define R_GLCDC_TCON_STHA1_HS_Pos (16UL) /*!< HS (Bit 16) */ + #define R_GLCDC_TCON_STHA1_HS_Msk (0x7ff0000UL) /*!< HS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STHA1_HW_Pos (0UL) /*!< HW (Bit 0) */ + #define R_GLCDC_TCON_STHA1_HW_Msk (0x7ffUL) /*!< HW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STHB1 ========================================================= */ + #define R_GLCDC_TCON_STHB1_HS_Pos (16UL) /*!< HS (Bit 16) */ + #define R_GLCDC_TCON_STHB1_HS_Msk (0x7ff0000UL) /*!< HS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STHB1_HW_Pos (0UL) /*!< HW (Bit 0) */ + #define R_GLCDC_TCON_STHB1_HW_Msk (0x7ffUL) /*!< HW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STHA2 ========================================================= */ + #define R_GLCDC_TCON_STHA2_HSSEL_Pos (8UL) /*!< HSSEL (Bit 8) */ + #define R_GLCDC_TCON_STHA2_HSSEL_Msk (0x100UL) /*!< HSSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHA2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STHA2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHA2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STHA2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================= STHB2 ========================================================= */ + #define R_GLCDC_TCON_STHB2_HSSEL_Pos (8UL) /*!< HSSEL (Bit 8) */ + #define R_GLCDC_TCON_STHB2_HSSEL_Msk (0x100UL) /*!< HSSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHB2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STHB2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHB2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STHB2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================== DE =========================================================== */ + #define R_GLCDC_TCON_DE_INV_Pos (0UL) /*!< INV (Bit 0) */ + #define R_GLCDC_TCON_DE_INV_Msk (0x1UL) /*!< INV (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SYSCNT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DTCTEN ========================================================= */ + #define R_GLCDC_SYSCNT_DTCTEN_L2UNDFDTC_Pos (2UL) /*!< L2UNDFDTC (Bit 2) */ + #define R_GLCDC_SYSCNT_DTCTEN_L2UNDFDTC_Msk (0x4UL) /*!< L2UNDFDTC (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_DTCTEN_L1UNDFDTC_Pos (1UL) /*!< L1UNDFDTC (Bit 1) */ + #define R_GLCDC_SYSCNT_DTCTEN_L1UNDFDTC_Msk (0x2UL) /*!< L1UNDFDTC (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_DTCTEN_VPOSDTC_Pos (0UL) /*!< VPOSDTC (Bit 0) */ + #define R_GLCDC_SYSCNT_DTCTEN_VPOSDTC_Msk (0x1UL) /*!< VPOSDTC (Bitfield-Mask: 0x01) */ +/* ========================================================= INTEN ========================================================= */ + #define R_GLCDC_SYSCNT_INTEN_L2UNDFINTEN_Pos (2UL) /*!< L2UNDFINTEN (Bit 2) */ + #define R_GLCDC_SYSCNT_INTEN_L2UNDFINTEN_Msk (0x4UL) /*!< L2UNDFINTEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_INTEN_L1UNDFINTEN_Pos (1UL) /*!< L1UNDFINTEN (Bit 1) */ + #define R_GLCDC_SYSCNT_INTEN_L1UNDFINTEN_Msk (0x2UL) /*!< L1UNDFINTEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_INTEN_VPOSINTEN_Pos (0UL) /*!< VPOSINTEN (Bit 0) */ + #define R_GLCDC_SYSCNT_INTEN_VPOSINTEN_Msk (0x1UL) /*!< VPOSINTEN (Bitfield-Mask: 0x01) */ +/* ========================================================= STCLR ========================================================= */ + #define R_GLCDC_SYSCNT_STCLR_L2UNDFCLR_Pos (2UL) /*!< L2UNDFCLR (Bit 2) */ + #define R_GLCDC_SYSCNT_STCLR_L2UNDFCLR_Msk (0x4UL) /*!< L2UNDFCLR (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STCLR_L1UNDFCLR_Pos (1UL) /*!< L1UNDFCLR (Bit 1) */ + #define R_GLCDC_SYSCNT_STCLR_L1UNDFCLR_Msk (0x2UL) /*!< L1UNDFCLR (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STCLR_VPOSCLR_Pos (0UL) /*!< VPOSCLR (Bit 0) */ + #define R_GLCDC_SYSCNT_STCLR_VPOSCLR_Msk (0x1UL) /*!< VPOSCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= STMON ========================================================= */ + #define R_GLCDC_SYSCNT_STMON_L2UNDF_Pos (2UL) /*!< L2UNDF (Bit 2) */ + #define R_GLCDC_SYSCNT_STMON_L2UNDF_Msk (0x4UL) /*!< L2UNDF (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STMON_L1UNDF_Pos (1UL) /*!< L1UNDF (Bit 1) */ + #define R_GLCDC_SYSCNT_STMON_L1UNDF_Msk (0x2UL) /*!< L1UNDF (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STMON_VPOS_Pos (0UL) /*!< VPOS (Bit 0) */ + #define R_GLCDC_SYSCNT_STMON_VPOS_Msk (0x1UL) /*!< VPOS (Bitfield-Mask: 0x01) */ +/* ======================================================= PANEL_CLK ======================================================= */ + #define R_GLCDC_SYSCNT_PANEL_CLK_VER_Pos (16UL) /*!< VER (Bit 16) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_VER_Msk (0xffff0000UL) /*!< VER (Bitfield-Mask: 0xffff) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_PIXSEL_Pos (12UL) /*!< PIXSEL (Bit 12) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_PIXSEL_Msk (0x1000UL) /*!< PIXSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKSEL_Pos (8UL) /*!< CLKSEL (Bit 8) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKSEL_Msk (0x100UL) /*!< CLKSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKEN_Pos (6UL) /*!< CLKEN (Bit 6) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKEN_Msk (0x40UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_DCDR_Pos (0UL) /*!< DCDR (Bit 0) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_DCDR_Msk (0x3fUL) /*!< DCDR (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ GTDLYR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== A =========================================================== */ + #define R_GPT_ODC_GTDLYR_A_DLY_Pos (0UL) /*!< DLY (Bit 0) */ + #define R_GPT_ODC_GTDLYR_A_DLY_Msk (0x7fUL) /*!< DLY (Bitfield-Mask: 0x7f) */ +/* =========================================================== B =========================================================== */ + #define R_GPT_ODC_GTDLYR_B_DLY_Pos (0UL) /*!< DLY (Bit 0) */ + #define R_GPT_ODC_GTDLYR_B_DLY_Msk (0x7fUL) /*!< DLY (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ + #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ + #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ + #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ REGION ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos (3UL) /*!< PP (Bit 3) */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk (0x8UL) /*!< PP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* =========================================================== S =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ +/* =========================================================== E =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ GROUP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EN =========================================================== */ + #define R_MPU_MMPU_GROUP_EN_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_EN_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================= ENPT ========================================================== */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== RPT ========================================================== */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== RPT_SEC ======================================================== */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== CTL ========================================================== */ + #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ + #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== SA =========================================================== */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== EA =========================================================== */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ PIN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PmnPFS_BY ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ +/* ======================================================= PmnPFS_HA ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ +/* ======================================================== PmnPFS ========================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ PMSAR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PMSAR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ RTCCR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RTCCR ========================================================= */ + #define R_RTC_RTCCR_RTCCR_TCEN_Pos (7UL) /*!< TCEN (Bit 7) */ + #define R_RTC_RTCCR_RTCCR_TCEN_Msk (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ + #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ + #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RSEC ========================================================== */ + #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ + #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMIN ========================================================== */ + #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ + #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ +/* ========================================================== RHR ========================================================== */ + #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ + #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RDAY ========================================================== */ + #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ + #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMON ========================================================== */ + #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_HS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_HS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_HS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_HS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_HS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ CMCFGCS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CMCFG0 ========================================================= */ + #define R_XSPI0_CMCFGCS_CMCFG0_FFMT_Pos (0UL) /*!< FFMT (Bit 0) */ + #define R_XSPI0_CMCFGCS_CMCFG0_FFMT_Msk (0x3UL) /*!< FFMT (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDSIZE_Pos (2UL) /*!< ADDSIZE (Bit 2) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDSIZE_Msk (0xcUL) /*!< ADDSIZE (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CMCFGCS_CMCFG0_WPBSTMD_Pos (4UL) /*!< WPBSTMD (Bit 4) */ + #define R_XSPI0_CMCFGCS_CMCFG0_WPBSTMD_Msk (0x10UL) /*!< WPBSTMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ARYAMD_Pos (5UL) /*!< ARYAMD (Bit 5) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ARYAMD_Msk (0x20UL) /*!< ARYAMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDRPEN_Pos (16UL) /*!< ADDRPEN (Bit 16) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDRPEN_Msk (0xff0000UL) /*!< ADDRPEN (Bitfield-Mask: 0xff) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDRPCD_Pos (24UL) /*!< ADDRPCD (Bit 24) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDRPCD_Msk (0xff000000UL) /*!< ADDRPCD (Bitfield-Mask: 0xff) */ +/* ======================================================== CMCFG1 ========================================================= */ + #define R_XSPI0_CMCFGCS_CMCFG1_RDCMD_Pos (0UL) /*!< RDCMD (Bit 0) */ + #define R_XSPI0_CMCFGCS_CMCFG1_RDCMD_Msk (0xffffUL) /*!< RDCMD (Bitfield-Mask: 0xffff) */ + #define R_XSPI0_CMCFGCS_CMCFG1_RDLATE_Pos (16UL) /*!< RDLATE (Bit 16) */ + #define R_XSPI0_CMCFGCS_CMCFG1_RDLATE_Msk (0x1f0000UL) /*!< RDLATE (Bitfield-Mask: 0x1f) */ +/* ======================================================== CMCFG2 ========================================================= */ + #define R_XSPI0_CMCFGCS_CMCFG2_WRCMD_Pos (0UL) /*!< WRCMD (Bit 0) */ + #define R_XSPI0_CMCFGCS_CMCFG2_WRCMD_Msk (0xffffUL) /*!< WRCMD (Bitfield-Mask: 0xffff) */ + #define R_XSPI0_CMCFGCS_CMCFG2_WRLATE_Pos (16UL) /*!< WRLATE (Bit 16) */ + #define R_XSPI0_CMCFGCS_CMCFG2_WRLATE_Msk (0x1f0000UL) /*!< WRLATE (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ CDBUF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CDT ========================================================== */ + #define R_XSPI0_CDBUF_CDT_CMDSIZE_Pos (0UL) /*!< CMDSIZE (Bit 0) */ + #define R_XSPI0_CDBUF_CDT_CMDSIZE_Msk (0x3UL) /*!< CMDSIZE (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CDBUF_CDT_ADDSIZE_Pos (2UL) /*!< ADDSIZE (Bit 2) */ + #define R_XSPI0_CDBUF_CDT_ADDSIZE_Msk (0x1cUL) /*!< ADDSIZE (Bitfield-Mask: 0x07) */ + #define R_XSPI0_CDBUF_CDT_DATASIZE_Pos (5UL) /*!< DATASIZE (Bit 5) */ + #define R_XSPI0_CDBUF_CDT_DATASIZE_Msk (0x1e0UL) /*!< DATASIZE (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_CDBUF_CDT_LATE_Pos (9UL) /*!< LATE (Bit 9) */ + #define R_XSPI0_CDBUF_CDT_LATE_Msk (0x3e00UL) /*!< LATE (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CDBUF_CDT_TRTYPE_Pos (15UL) /*!< TRTYPE (Bit 15) */ + #define R_XSPI0_CDBUF_CDT_TRTYPE_Msk (0x8000UL) /*!< TRTYPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDBUF_CDT_CMD_Pos (16UL) /*!< CMD (Bit 16) */ + #define R_XSPI0_CDBUF_CDT_CMD_Msk (0xffff0000UL) /*!< CMD (Bitfield-Mask: 0xffff) */ +/* ========================================================== CDA ========================================================== */ + #define R_XSPI0_CDBUF_CDA_ADD_Pos (0UL) /*!< ADD (Bit 0) */ + #define R_XSPI0_CDBUF_CDA_ADD_Msk (0xffffffffUL) /*!< ADD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDD0 ========================================================== */ + #define R_XSPI0_CDBUF_CDD0_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_XSPI0_CDBUF_CDD0_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDD1 ========================================================== */ + #define R_XSPI0_CDBUF_CDD1_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_XSPI0_CDBUF_CDD1_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CCCTLCS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CCCTL0 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL0_CAEN_Pos (0UL) /*!< CAEN (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CAEN_Msk (0x1UL) /*!< CAEN (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CANOWR_Pos (1UL) /*!< CANOWR (Bit 1) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CANOWR_Msk (0x2UL) /*!< CANOWR (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CAITV_Pos (8UL) /*!< CAITV (Bit 8) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CAITV_Msk (0x1f00UL) /*!< CAITV (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CASFTSTA_Pos (16UL) /*!< CASFTSTA (Bit 16) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CASFTSTA_Msk (0x1f0000UL) /*!< CASFTSTA (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CASFTEND_Pos (24UL) /*!< CASFTEND (Bit 24) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CASFTEND_Msk (0x1f000000UL) /*!< CASFTEND (Bitfield-Mask: 0x1f) */ +/* ======================================================== CCCTL1 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL1_CACMDSIZE_Pos (0UL) /*!< CACMDSIZE (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CACMDSIZE_Msk (0x3UL) /*!< CACMDSIZE (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CAADDSIZE_Pos (2UL) /*!< CAADDSIZE (Bit 2) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CAADDSIZE_Msk (0x1cUL) /*!< CAADDSIZE (Bitfield-Mask: 0x07) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CADATASIZE_Pos (5UL) /*!< CADATASIZE (Bit 5) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CADATASIZE_Msk (0x1e0UL) /*!< CADATASIZE (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CAWRLATE_Pos (16UL) /*!< CAWRLATE (Bit 16) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CAWRLATE_Msk (0x1f0000UL) /*!< CAWRLATE (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CARDLATE_Pos (24UL) /*!< CARDLATE (Bit 24) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CARDLATE_Msk (0x1f000000UL) /*!< CARDLATE (Bitfield-Mask: 0x1f) */ +/* ======================================================== CCCTL2 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL2_CAWRCMD_Pos (0UL) /*!< CAWRCMD (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL2_CAWRCMD_Msk (0xffffUL) /*!< CAWRCMD (Bitfield-Mask: 0xffff) */ + #define R_XSPI0_CCCTLCS_CCCTL2_CARDCMD_Pos (16UL) /*!< CARDCMD (Bit 16) */ + #define R_XSPI0_CCCTLCS_CCCTL2_CARDCMD_Msk (0xffff0000UL) /*!< CARDCMD (Bitfield-Mask: 0xffff) */ +/* ======================================================== CCCTL3 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL3_CAADD_Pos (0UL) /*!< CAADD (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL3_CAADD_Msk (0xffffffffUL) /*!< CAADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL4 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL4_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL4_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL5 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL5_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL5_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL6 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL6_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL6_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL7 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL7_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL7_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= AGTCR ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTMR1 ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTMR2 ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ +/* ===================================================== AGTIOSEL_ALT ====================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ +/* ======================================================== AGTIOC ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTISR ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTCMSR ======================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ +/* ======================================================= AGTIOSEL ======================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ AGT16 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGTX0_AGT16_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGTX0_AGT16_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ AGT32 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGTX0_AGT32_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGTX0_AGT32_AGT_AGT_Msk (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CABPPPFLC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== LEVEL0 ========================================================= */ + #define R_COMA_CABPPPFLC_LEVEL0_PPDL_Pos (0UL) /*!< PPDL (Bit 0) */ + #define R_COMA_CABPPPFLC_LEVEL0_PPDL_Msk (0x3ffUL) /*!< PPDL (Bitfield-Mask: 0x3ff) */ + #define R_COMA_CABPPPFLC_LEVEL0_PPAL_Pos (16UL) /*!< PPAL (Bit 16) */ + #define R_COMA_CABPPPFLC_LEVEL0_PPAL_Msk (0x3ff0000UL) /*!< PPAL (Bitfield-Mask: 0x3ff) */ +/* ======================================================== LEVEL1 ========================================================= */ + #define R_COMA_CABPPPFLC_LEVEL1_PPDL_Pos (0UL) /*!< PPDL (Bit 0) */ + #define R_COMA_CABPPPFLC_LEVEL1_PPDL_Msk (0x3ffUL) /*!< PPDL (Bitfield-Mask: 0x3ff) */ + #define R_COMA_CABPPPFLC_LEVEL1_PPAL_Pos (16UL) /*!< PPAL (Bit 16) */ + #define R_COMA_CABPPPFLC_LEVEL1_PPAL_Msk (0x3ff0000UL) /*!< PPAL (Bitfield-Mask: 0x3ff) */ + +/* =========================================================================================================================== */ +/* ================ IPCNMI ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== STA ========================================================== */ + #define R_IPC_IPCNMI_STA_NMI_Pos (0UL) /*!< NMI (Bit 0) */ + #define R_IPC_IPCNMI_STA_NMI_Msk (0x1UL) /*!< NMI (Bitfield-Mask: 0x01) */ +/* ========================================================== SET ========================================================== */ + #define R_IPC_IPCNMI_SET_SET_Pos (0UL) /*!< SET (Bit 0) */ + #define R_IPC_IPCNMI_SET_SET_Msk (0x1UL) /*!< SET (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_IPC_IPCNMI_CLR_CLR_Pos (0UL) /*!< CLR (Bit 0) */ + #define R_IPC_IPCNMI_CLR_CLR_Msk (0x1UL) /*!< CLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ CH ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== STA ========================================================== */ + #define R_IPC_IPC_CH_STA_IRQ_Pos (0UL) /*!< IRQ (Bit 0) */ + #define R_IPC_IPC_CH_STA_IRQ_Msk (0x1UL) /*!< IRQ (Bitfield-Mask: 0x01) */ + #define R_IPC_IPC_CH_STA_RDY_Pos (16UL) /*!< RDY (Bit 16) */ + #define R_IPC_IPC_CH_STA_RDY_Msk (0x10000UL) /*!< RDY (Bitfield-Mask: 0x01) */ + #define R_IPC_IPC_CH_STA_FULL_Pos (17UL) /*!< FULL (Bit 17) */ + #define R_IPC_IPC_CH_STA_FULL_Msk (0x20000UL) /*!< FULL (Bitfield-Mask: 0x01) */ + #define R_IPC_IPC_CH_STA_RERR_Pos (24UL) /*!< RERR (Bit 24) */ + #define R_IPC_IPC_CH_STA_RERR_Msk (0x1000000UL) /*!< RERR (Bitfield-Mask: 0x01) */ + #define R_IPC_IPC_CH_STA_FERR_Pos (25UL) /*!< FERR (Bit 25) */ + #define R_IPC_IPC_CH_STA_FERR_Msk (0x2000000UL) /*!< FERR (Bitfield-Mask: 0x01) */ +/* ========================================================== SET ========================================================== */ + #define R_IPC_IPC_CH_SET_SET_Pos (0UL) /*!< SET (Bit 0) */ + #define R_IPC_IPC_CH_SET_SET_Msk (0x1UL) /*!< SET (Bitfield-Mask: 0x01) */ +/* ========================================================== TXD ========================================================== */ + #define R_IPC_IPC_CH_TXD_TXD_Pos (0UL) /*!< TXD (Bit 0) */ + #define R_IPC_IPC_CH_TXD_TXD_Msk (0xffffffffUL) /*!< TXD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RXD ========================================================== */ + #define R_IPC_IPC_CH_RXD_RXD_Pos (0UL) /*!< RXD (Bit 0) */ + #define R_IPC_IPC_CH_RXD_RXD_Msk (0xffffffffUL) /*!< RXD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== CLR ========================================================== */ + #define R_IPC_IPC_CH_CLR_CLR_Pos (0UL) /*!< CLR (Bit 0) */ + #define R_IPC_IPC_CH_CLR_CLR_Msk (0x1UL) /*!< CLR (Bitfield-Mask: 0x01) */ + #define R_IPC_IPC_CH_CLR_RST_Pos (16UL) /*!< RST (Bit 16) */ + #define R_IPC_IPC_CH_CLR_RST_Msk (0x10000UL) /*!< RST (Bitfield-Mask: 0x01) */ + #define R_IPC_IPC_CH_CLR_RCLR_Pos (24UL) /*!< RCLR (Bit 24) */ + #define R_IPC_IPC_CH_CLR_RCLR_Msk (0x1000000UL) /*!< RCLR (Bitfield-Mask: 0x01) */ + #define R_IPC_IPC_CH_CLR_FCLR_Pos (25UL) /*!< FCLR (Bit 25) */ + #define R_IPC_IPC_CH_CLR_FCLR_Msk (0x2000000UL) /*!< FCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ IPC ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ CH ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PDSTRTR ======================================================== */ + #define R_PDM_CH_PDSTRTR_STRTRG_Pos (0UL) /*!< STRTRG (Bit 0) */ + #define R_PDM_CH_PDSTRTR_STRTRG_Msk (0x1UL) /*!< STRTRG (Bitfield-Mask: 0x01) */ +/* ======================================================== PDSTPTR ======================================================== */ + #define R_PDM_CH_PDSTPTR_STPTRG_Pos (0UL) /*!< STPTRG (Bit 0) */ + #define R_PDM_CH_PDSTPTR_STPTRG_Msk (0x1UL) /*!< STPTRG (Bitfield-Mask: 0x01) */ +/* ======================================================== PDCHGTR ======================================================== */ + #define R_PDM_CH_PDCHGTR_CHGTRG_Pos (0UL) /*!< CHGTRG (Bit 0) */ + #define R_PDM_CH_PDCHGTR_CHGTRG_Msk (0x1UL) /*!< CHGTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= PDICR ========================================================= */ + #define R_PDM_CH_PDICR_ISDE_Pos (1UL) /*!< ISDE (Bit 1) */ + #define R_PDM_CH_PDICR_ISDE_Msk (0x2UL) /*!< ISDE (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDICR_IDRE_Pos (2UL) /*!< IDRE (Bit 2) */ + #define R_PDM_CH_PDICR_IDRE_Msk (0x4UL) /*!< IDRE (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDICR_IEDE_Pos (16UL) /*!< IEDE (Bit 16) */ + #define R_PDM_CH_PDICR_IEDE_Msk (0x10000UL) /*!< IEDE (Bitfield-Mask: 0x01) */ +/* ======================================================== PDSDCR ========================================================= */ + #define R_PDM_CH_PDSDCR_SDE_Pos (1UL) /*!< SDE (Bit 1) */ + #define R_PDM_CH_PDSDCR_SDE_Msk (0x2UL) /*!< SDE (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSDCR_SCDE_Pos (16UL) /*!< SCDE (Bit 16) */ + #define R_PDM_CH_PDSDCR_SCDE_Msk (0x10000UL) /*!< SCDE (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSDCR_OVLDE_Pos (17UL) /*!< OVLDE (Bit 17) */ + #define R_PDM_CH_PDSDCR_OVLDE_Msk (0x20000UL) /*!< OVLDE (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSDCR_OVUDE_Pos (18UL) /*!< OVUDE (Bit 18) */ + #define R_PDM_CH_PDSDCR_OVUDE_Msk (0x40000UL) /*!< OVUDE (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSDCR_BFOWDE_Pos (27UL) /*!< BFOWDE (Bit 27) */ + #define R_PDM_CH_PDSDCR_BFOWDE_Msk (0x8000000UL) /*!< BFOWDE (Bitfield-Mask: 0x01) */ +/* ========================================================= PDSR ========================================================== */ + #define R_PDM_CH_PDSR_STATE_Pos (0UL) /*!< STATE (Bit 0) */ + #define R_PDM_CH_PDSR_STATE_Msk (0x1UL) /*!< STATE (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSR_SDF_Pos (1UL) /*!< SDF (Bit 1) */ + #define R_PDM_CH_PDSR_SDF_Msk (0x2UL) /*!< SDF (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSR_DRF_Pos (2UL) /*!< DRF (Bit 2) */ + #define R_PDM_CH_PDSR_DRF_Msk (0x4UL) /*!< DRF (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSR_SCDF_Pos (16UL) /*!< SCDF (Bit 16) */ + #define R_PDM_CH_PDSR_SCDF_Msk (0x10000UL) /*!< SCDF (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSR_OVLDF_Pos (17UL) /*!< OVLDF (Bit 17) */ + #define R_PDM_CH_PDSR_OVLDF_Msk (0x20000UL) /*!< OVLDF (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSR_OVUDF_Pos (18UL) /*!< OVUDF (Bit 18) */ + #define R_PDM_CH_PDSR_OVUDF_Msk (0x40000UL) /*!< OVUDF (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSR_BFOWDF_Pos (27UL) /*!< BFOWDF (Bit 27) */ + #define R_PDM_CH_PDSR_BFOWDF_Msk (0x8000000UL) /*!< BFOWDF (Bitfield-Mask: 0x01) */ +/* ========================================================= PDSCR ========================================================= */ + #define R_PDM_CH_PDSCR_SDFC_Pos (1UL) /*!< SDFC (Bit 1) */ + #define R_PDM_CH_PDSCR_SDFC_Msk (0x2UL) /*!< SDFC (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSCR_SCDFC_Pos (16UL) /*!< SCDFC (Bit 16) */ + #define R_PDM_CH_PDSCR_SCDFC_Msk (0x10000UL) /*!< SCDFC (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSCR_OVLDFC_Pos (17UL) /*!< OVLDFC (Bit 17) */ + #define R_PDM_CH_PDSCR_OVLDFC_Msk (0x20000UL) /*!< OVLDFC (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSCR_OVUDFC_Pos (18UL) /*!< OVUDFC (Bit 18) */ + #define R_PDM_CH_PDSCR_OVUDFC_Msk (0x40000UL) /*!< OVUDFC (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSCR_BFOWDFC_Pos (27UL) /*!< BFOWDFC (Bit 27) */ + #define R_PDM_CH_PDSCR_BFOWDFC_Msk (0x8000000UL) /*!< BFOWDFC (Bitfield-Mask: 0x01) */ +/* ======================================================== PDMDSR ========================================================= */ + #define R_PDM_CH_PDMDSR_INPSEL_Pos (0UL) /*!< INPSEL (Bit 0) */ + #define R_PDM_CH_PDMDSR_INPSEL_Msk (0x1UL) /*!< INPSEL (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDMDSR_SFMD_Pos (4UL) /*!< SFMD (Bit 4) */ + #define R_PDM_CH_PDMDSR_SFMD_Msk (0x70UL) /*!< SFMD (Bitfield-Mask: 0x07) */ + #define R_PDM_CH_PDMDSR_HFIS_Pos (8UL) /*!< HFIS (Bit 8) */ + #define R_PDM_CH_PDMDSR_HFIS_Msk (0x300UL) /*!< HFIS (Bitfield-Mask: 0x03) */ + #define R_PDM_CH_PDMDSR_CFIS_Pos (12UL) /*!< CFIS (Bit 12) */ + #define R_PDM_CH_PDMDSR_CFIS_Msk (0x3000UL) /*!< CFIS (Bitfield-Mask: 0x03) */ + #define R_PDM_CH_PDMDSR_LFIS_Pos (16UL) /*!< LFIS (Bit 16) */ + #define R_PDM_CH_PDMDSR_LFIS_Msk (0x30000UL) /*!< LFIS (Bitfield-Mask: 0x03) */ + #define R_PDM_CH_PDMDSR_SDMAMD_Pos (24UL) /*!< SDMAMD (Bit 24) */ + #define R_PDM_CH_PDMDSR_SDMAMD_Msk (0x3000000UL) /*!< SDMAMD (Bitfield-Mask: 0x03) */ + #define R_PDM_CH_PDMDSR_DBIS_Pos (28UL) /*!< DBIS (Bit 28) */ + #define R_PDM_CH_PDMDSR_DBIS_Msk (0xf0000000UL) /*!< DBIS (Bitfield-Mask: 0x0f) */ +/* ======================================================== PDSFCR ========================================================= */ + #define R_PDM_CH_PDSFCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_PDM_CH_PDSFCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ + #define R_PDM_CH_PDSFCR_SINCDEC_Pos (16UL) /*!< SINCDEC (Bit 16) */ + #define R_PDM_CH_PDSFCR_SINCDEC_Msk (0xff0000UL) /*!< SINCDEC (Bitfield-Mask: 0xff) */ + #define R_PDM_CH_PDSFCR_SINCRNG_Pos (24UL) /*!< SINCRNG (Bit 24) */ + #define R_PDM_CH_PDSFCR_SINCRNG_Msk (0x1f000000UL) /*!< SINCRNG (Bitfield-Mask: 0x1f) */ +/* ======================================================= PDHFCS0R ======================================================== */ + #define R_PDM_CH_PDHFCS0R_HFS0_Pos (0UL) /*!< HFS0 (Bit 0) */ + #define R_PDM_CH_PDHFCS0R_HFS0_Msk (0xffffUL) /*!< HFS0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= PDHFCK1R ======================================================== */ + #define R_PDM_CH_PDHFCK1R_HFK1_Pos (0UL) /*!< HFK1 (Bit 0) */ + #define R_PDM_CH_PDHFCK1R_HFK1_Msk (0xffffUL) /*!< HFK1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== PDHFCHR ======================================================== */ + #define R_PDM_CH_PDHFCHR_HFHn_Pos (0UL) /*!< HFHn (Bit 0) */ + #define R_PDM_CH_PDHFCHR_HFHn_Msk (0xffffUL) /*!< HFHn (Bitfield-Mask: 0xffff) */ +/* ======================================================== PDCFCHR ======================================================== */ + #define R_PDM_CH_PDCFCHR_CFHn_Pos (0UL) /*!< CFHn (Bit 0) */ + #define R_PDM_CH_PDCFCHR_CFHn_Msk (0x1fffUL) /*!< CFHn (Bitfield-Mask: 0x1fff) */ +/* ====================================================== PDLFCH010R ======================================================= */ + #define R_PDM_CH_PDLFCH010R_LFH010_Pos (0UL) /*!< LFH010 (Bit 0) */ + #define R_PDM_CH_PDLFCH010R_LFH010_Msk (0x1fffUL) /*!< LFH010 (Bitfield-Mask: 0x1fff) */ +/* ======================================================= PDLFCH1R ======================================================== */ + #define R_PDM_CH_PDLFCH1R_LFH1n_Pos (0UL) /*!< LFH1n (Bit 0) */ + #define R_PDM_CH_PDLFCH1R_LFH1n_Msk (0x1fffUL) /*!< LFH1n (Bitfield-Mask: 0x1fff) */ +/* ======================================================== PDSDLTR ======================================================== */ + #define R_PDM_CH_PDSDLTR_SDETL_Pos (0UL) /*!< SDETL (Bit 0) */ + #define R_PDM_CH_PDSDLTR_SDETL_Msk (0xfffffUL) /*!< SDETL (Bitfield-Mask: 0xfffff) */ +/* ======================================================== PDSDUTR ======================================================== */ + #define R_PDM_CH_PDSDUTR_SDETU_Pos (0UL) /*!< SDETU (Bit 0) */ + #define R_PDM_CH_PDSDUTR_SDETU_Msk (0xfffffUL) /*!< SDETU (Bitfield-Mask: 0xfffff) */ +/* ======================================================== PDDBCR ========================================================= */ + #define R_PDM_CH_PDDBCR_DATRITHR_Pos (0UL) /*!< DATRITHR (Bit 0) */ + #define R_PDM_CH_PDDBCR_DATRITHR_Msk (0x7UL) /*!< DATRITHR (Bitfield-Mask: 0x07) */ +/* ======================================================== PDSCTSR ======================================================== */ + #define R_PDM_CH_PDSCTSR_SCDL_Pos (0UL) /*!< SCDL (Bit 0) */ + #define R_PDM_CH_PDSCTSR_SCDL_Msk (0x1fffUL) /*!< SCDL (Bitfield-Mask: 0x1fff) */ + #define R_PDM_CH_PDSCTSR_SCDH_Pos (16UL) /*!< SCDH (Bit 16) */ + #define R_PDM_CH_PDSCTSR_SCDH_Msk (0x1fff0000UL) /*!< SCDH (Bitfield-Mask: 0x1fff) */ +/* ======================================================== PDOVLTR ======================================================== */ + #define R_PDM_CH_PDOVLTR_OVDL_Pos (0UL) /*!< OVDL (Bit 0) */ + #define R_PDM_CH_PDOVLTR_OVDL_Msk (0xfffffUL) /*!< OVDL (Bitfield-Mask: 0xfffff) */ +/* ======================================================== PDOVUTR ======================================================== */ + #define R_PDM_CH_PDOVUTR_OVDU_Pos (0UL) /*!< OVDU (Bit 0) */ + #define R_PDM_CH_PDOVUTR_OVDU_Msk (0xfffffUL) /*!< OVDU (Bitfield-Mask: 0xfffff) */ +/* ======================================================== PDDRCR ========================================================= */ + #define R_PDM_CH_PDDRCR_DATRE_Pos (0UL) /*!< DATRE (Bit 0) */ + #define R_PDM_CH_PDDRCR_DATRE_Msk (0x1UL) /*!< DATRE (Bitfield-Mask: 0x01) */ +/* ========================================================= PDDCR ========================================================= */ + #define R_PDM_CH_PDDCR_DATC_Pos (0UL) /*!< DATC (Bit 0) */ + #define R_PDM_CH_PDDCR_DATC_Msk (0x1UL) /*!< DATC (Bitfield-Mask: 0x01) */ +/* ========================================================= PDDRR ========================================================= */ + #define R_PDM_CH_PDDRR_DAT_Pos (0UL) /*!< DAT (Bit 0) */ + #define R_PDM_CH_PDDRR_DAT_Msk (0xfffffUL) /*!< DAT (Bitfield-Mask: 0xfffff) */ +/* ========================================================= PDDSR ========================================================= */ + #define R_PDM_CH_PDDSR_DATNUM_Pos (0UL) /*!< DATNUM (Bit 0) */ + #define R_PDM_CH_PDDSR_DATNUM_Msk (0xffUL) /*!< DATNUM (Bitfield-Mask: 0xff) */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CMPCTL ========================================================= */ + #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ + #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ + #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ + #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ + #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ +/* ======================================================== CMPSEL0 ======================================================== */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== CMPSEL1 ======================================================== */ + #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ +/* ======================================================== CMPMON ========================================================= */ + #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ + #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ +/* ========================================================= CPIOC ========================================================= */ + #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ + #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ + #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPINTCTL ======================================================== */ + #define R_ACMPHS0_CPINTCTL_MSKE_Pos (0UL) /*!< MSKE (Bit 0) */ + #define R_ACMPHS0_CPINTCTL_MSKE_Msk (0x1UL) /*!< MSKE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPMSKCTL ======================================================== */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Pos (0UL) /*!< MSKSEL (Bit 0) */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Msk (0x7UL) /*!< MSKSEL (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PSARB ========================================================= */ + #define R_PSCU_PSARB_PSARB_Pos (0UL) /*!< PSARB (Bit 0) */ + #define R_PSCU_PSARB_PSARB_Msk (0x1UL) /*!< PSARB (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARC ========================================================= */ + #define R_PSCU_PSARC_PSARC_Pos (0UL) /*!< PSARC (Bit 0) */ + #define R_PSCU_PSARC_PSARC_Msk (0x1UL) /*!< PSARC (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARD ========================================================= */ + #define R_PSCU_PSARD_PSARD_Pos (0UL) /*!< PSARD (Bit 0) */ + #define R_PSCU_PSARD_PSARD_Msk (0x1UL) /*!< PSARD (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARE ========================================================= */ + #define R_PSCU_PSARE_PSARE_Pos (0UL) /*!< PSARE (Bit 0) */ + #define R_PSCU_PSARE_PSARE_Msk (0x1UL) /*!< PSARE (Bitfield-Mask: 0x01) */ +/* ========================================================= MSSAR ========================================================= */ + #define R_PSCU_MSSAR_MSSAR_Pos (0UL) /*!< MSSAR (Bit 0) */ + #define R_PSCU_MSSAR_MSSAR_Msk (0x1UL) /*!< MSSAR (Bitfield-Mask: 0x01) */ +/* ========================================================= PPARB ========================================================= */ + #define R_PSCU_PPARB_PPARB_Pos (0UL) /*!< PPARB (Bit 0) */ + #define R_PSCU_PPARB_PPARB_Msk (0x1UL) /*!< PPARB (Bitfield-Mask: 0x01) */ +/* ========================================================= PPARC ========================================================= */ + #define R_PSCU_PPARC_PPARC_Pos (0UL) /*!< PPARC (Bit 0) */ + #define R_PSCU_PPARC_PPARC_Msk (0x1UL) /*!< PPARC (Bitfield-Mask: 0x01) */ +/* ========================================================= PPARD ========================================================= */ + #define R_PSCU_PPARD_PPARD_Pos (0UL) /*!< PPARD (Bit 0) */ + #define R_PSCU_PPARD_PPARD_Msk (0x1UL) /*!< PPARD (Bitfield-Mask: 0x01) */ +/* ========================================================= PPARE ========================================================= */ + #define R_PSCU_PPARE_PPARE_Pos (0UL) /*!< PPARE (Bit 0) */ + #define R_PSCU_PPARE_PPARE_Msk (0x1UL) /*!< PPARE (Bitfield-Mask: 0x01) */ +/* ========================================================= MSPAR ========================================================= */ + #define R_PSCU_MSPAR_MSPAR_Pos (0UL) /*!< MSPAR (Bit 0) */ + #define R_PSCU_MSPAR_MSPAR_Msk (0x1UL) /*!< MSPAR (Bitfield-Mask: 0x01) */ +/* ======================================================= CFSAMONA ======================================================== */ + #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ + #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ +/* ======================================================== DLMMON ========================================================= */ + #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */ + #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFSAMON ======================================================== */ + #define R_PSCU_SFSAMON_SFS_Pos (15UL) /*!< SFS (Bit 15) */ + #define R_PSCU_SFSAMON_SFS_Msk (0xff8000UL) /*!< SFS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CACR0 ========================================================= */ + #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ + #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR1 ========================================================= */ + #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ + #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ + #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ + #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR2 ========================================================= */ + #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ + #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ + #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ + #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ + #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ +/* ========================================================= CAICR ========================================================= */ + #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ + #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ + #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ + #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ + #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ + #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ + #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CASTR ========================================================= */ + #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ + #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ + #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ + #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ +/* ======================================================== CAULVR ========================================================= */ + #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ + #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CALLVR ========================================================= */ + #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ + #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CACNTBR ======================================================== */ + #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ + #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CANFD0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CFDGCFG ======================================================== */ + #define R_CANFD_CFDGCFG_TPRI_Pos (0UL) /*!< TPRI (Bit 0) */ + #define R_CANFD_CFDGCFG_TPRI_Msk (0x1UL) /*!< TPRI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DCE_Pos (1UL) /*!< DCE (Bit 1) */ + #define R_CANFD_CFDGCFG_DCE_Msk (0x2UL) /*!< DCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DRE_Pos (2UL) /*!< DRE (Bit 2) */ + #define R_CANFD_CFDGCFG_DRE_Msk (0x4UL) /*!< DRE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_MME_Pos (3UL) /*!< MME (Bit 3) */ + #define R_CANFD_CFDGCFG_MME_Msk (0x8UL) /*!< MME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DCS_Pos (4UL) /*!< DCS (Bit 4) */ + #define R_CANFD_CFDGCFG_DCS_Msk (0x10UL) /*!< DCS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_CMPOC_Pos (5UL) /*!< CMPOC (Bit 5) */ + #define R_CANFD_CFDGCFG_CMPOC_Msk (0x20UL) /*!< CMPOC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_TSP_Pos (8UL) /*!< TSP (Bit 8) */ + #define R_CANFD_CFDGCFG_TSP_Msk (0xf00UL) /*!< TSP (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGCFG_TSSS_Pos (12UL) /*!< TSSS (Bit 12) */ + #define R_CANFD_CFDGCFG_TSSS_Msk (0x1000UL) /*!< TSSS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_ITRCP_Pos (16UL) /*!< ITRCP (Bit 16) */ + #define R_CANFD_CFDGCFG_ITRCP_Msk (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff) */ +/* ======================================================== CFDGCTR ======================================================== */ + #define R_CANFD_CFDGCTR_GMDC_Pos (0UL) /*!< GMDC (Bit 0) */ + #define R_CANFD_CFDGCTR_GMDC_Msk (0x3UL) /*!< GMDC (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDGCTR_GSLPR_Pos (2UL) /*!< GSLPR (Bit 2) */ + #define R_CANFD_CFDGCTR_GSLPR_Msk (0x4UL) /*!< GSLPR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_DEIE_Pos (8UL) /*!< DEIE (Bit 8) */ + #define R_CANFD_CFDGCTR_DEIE_Msk (0x100UL) /*!< DEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_MEIE_Pos (9UL) /*!< MEIE (Bit 9) */ + #define R_CANFD_CFDGCTR_MEIE_Msk (0x200UL) /*!< MEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_THLEIE_Pos (10UL) /*!< THLEIE (Bit 10) */ + #define R_CANFD_CFDGCTR_THLEIE_Msk (0x400UL) /*!< THLEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_CMPOFIE_Pos (11UL) /*!< CMPOFIE (Bit 11) */ + #define R_CANFD_CFDGCTR_CMPOFIE_Msk (0x800UL) /*!< CMPOFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_TSRST_Pos (16UL) /*!< TSRST (Bit 16) */ + #define R_CANFD_CFDGCTR_TSRST_Msk (0x10000UL) /*!< TSRST (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGSTS ======================================================== */ + #define R_CANFD_CFDGSTS_GRSTSTS_Pos (0UL) /*!< GRSTSTS (Bit 0) */ + #define R_CANFD_CFDGSTS_GRSTSTS_Msk (0x1UL) /*!< GRSTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GHLTSTS_Pos (1UL) /*!< GHLTSTS (Bit 1) */ + #define R_CANFD_CFDGSTS_GHLTSTS_Msk (0x2UL) /*!< GHLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GSLPSTS_Pos (2UL) /*!< GSLPSTS (Bit 2) */ + #define R_CANFD_CFDGSTS_GSLPSTS_Msk (0x4UL) /*!< GSLPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GRAMINIT_Pos (3UL) /*!< GRAMINIT (Bit 3) */ + #define R_CANFD_CFDGSTS_GRAMINIT_Msk (0x8UL) /*!< GRAMINIT (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGERFL ======================================================== */ + #define R_CANFD_CFDGERFL_DEF_Pos (0UL) /*!< DEF (Bit 0) */ + #define R_CANFD_CFDGERFL_DEF_Msk (0x1UL) /*!< DEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_MES_Pos (1UL) /*!< MES (Bit 1) */ + #define R_CANFD_CFDGERFL_MES_Msk (0x2UL) /*!< MES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_THLES_Pos (2UL) /*!< THLES (Bit 2) */ + #define R_CANFD_CFDGERFL_THLES_Msk (0x4UL) /*!< THLES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_CMPOF_Pos (3UL) /*!< CMPOF (Bit 3) */ + #define R_CANFD_CFDGERFL_CMPOF_Msk (0x8UL) /*!< CMPOF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_EEF0_Pos (16UL) /*!< EEF0 (Bit 16) */ + #define R_CANFD_CFDGERFL_EEF0_Msk (0x10000UL) /*!< EEF0 (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGTSC ======================================================== */ + #define R_CANFD_CFDGTSC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CANFD_CFDGTSC_TS_Msk (0xffffUL) /*!< TS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CFDGAFLECTR ====================================================== */ + #define R_CANFD_CFDGAFLECTR_AFLPN_Pos (0UL) /*!< AFLPN (Bit 0) */ + #define R_CANFD_CFDGAFLECTR_AFLPN_Msk (0xfUL) /*!< AFLPN (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos (8UL) /*!< AFLDAE (Bit 8) */ + #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk (0x100UL) /*!< AFLDAE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGAFLCFG0 ====================================================== */ + #define R_CANFD_CFDGAFLCFG0_RNC1_Pos (0UL) /*!< RNC1 (Bit 0) */ + #define R_CANFD_CFDGAFLCFG0_RNC1_Msk (0x1ffUL) /*!< RNC1 (Bitfield-Mask: 0x1ff) */ + #define R_CANFD_CFDGAFLCFG0_RNC0_Pos (16UL) /*!< RNC0 (Bit 16) */ + #define R_CANFD_CFDGAFLCFG0_RNC0_Msk (0x1ff0000UL) /*!< RNC0 (Bitfield-Mask: 0x1ff) */ +/* ======================================================== CFDRMNB ======================================================== */ + #define R_CANFD_CFDRMNB_NRXMB_Pos (0UL) /*!< NRXMB (Bit 0) */ + #define R_CANFD_CFDRMNB_NRXMB_Msk (0xffUL) /*!< NRXMB (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRMNB_RMPLS_Pos (8UL) /*!< RMPLS (Bit 8) */ + #define R_CANFD_CFDRMNB_RMPLS_Msk (0x700UL) /*!< RMPLS (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDRMND0 ======================================================== */ + #define R_CANFD_CFDRMND0_RMNSu_Pos (0UL) /*!< RMNSu (Bit 0) */ + #define R_CANFD_CFDRMND0_RMNSu_Msk (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CFDRMIEC ======================================================== */ + #define R_CANFD_CFDRMIEC_RMIE_Pos (0UL) /*!< RMIE (Bit 0) */ + #define R_CANFD_CFDRMIEC_RMIE_Msk (0xffffffffUL) /*!< RMIE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CFDRFCC ======================================================== */ + #define R_CANFD_CFDRFCC_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CANFD_CFDRFCC_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFIE_Pos (1UL) /*!< RFIE (Bit 1) */ + #define R_CANFD_CFDRFCC_RFIE_Msk (0x2UL) /*!< RFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFPLS_Pos (4UL) /*!< RFPLS (Bit 4) */ + #define R_CANFD_CFDRFCC_RFPLS_Msk (0x70UL) /*!< RFPLS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFDC_Pos (8UL) /*!< RFDC (Bit 8) */ + #define R_CANFD_CFDRFCC_RFDC_Msk (0x700UL) /*!< RFDC (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFIM_Pos (12UL) /*!< RFIM (Bit 12) */ + #define R_CANFD_CFDRFCC_RFIM_Msk (0x1000UL) /*!< RFIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFIGCV_Pos (13UL) /*!< RFIGCV (Bit 13) */ + #define R_CANFD_CFDRFCC_RFIGCV_Msk (0xe000UL) /*!< RFIGCV (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDRFSTS ======================================================== */ + #define R_CANFD_CFDRFSTS_RFEMP_Pos (0UL) /*!< RFEMP (Bit 0) */ + #define R_CANFD_CFDRFSTS_RFEMP_Msk (0x1UL) /*!< RFEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFFLL_Pos (1UL) /*!< RFFLL (Bit 1) */ + #define R_CANFD_CFDRFSTS_RFFLL_Msk (0x2UL) /*!< RFFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFMLT_Pos (2UL) /*!< RFMLT (Bit 2) */ + #define R_CANFD_CFDRFSTS_RFMLT_Msk (0x4UL) /*!< RFMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFIF_Pos (3UL) /*!< RFIF (Bit 3) */ + #define R_CANFD_CFDRFSTS_RFIF_Msk (0x8UL) /*!< RFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFMC_Pos (8UL) /*!< RFMC (Bit 8) */ + #define R_CANFD_CFDRFSTS_RFMC_Msk (0xff00UL) /*!< RFMC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDRFPCTR ======================================================= */ + #define R_CANFD_CFDRFPCTR_RFPC_Pos (0UL) /*!< RFPC (Bit 0) */ + #define R_CANFD_CFDRFPCTR_RFPC_Msk (0xffUL) /*!< RFPC (Bitfield-Mask: 0xff) */ +/* ======================================================== CFDCFCC ======================================================== */ + #define R_CANFD_CFDCFCC_CFE_Pos (0UL) /*!< CFE (Bit 0) */ + #define R_CANFD_CFDCFCC_CFE_Msk (0x1UL) /*!< CFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFRXIE_Pos (1UL) /*!< CFRXIE (Bit 1) */ + #define R_CANFD_CFDCFCC_CFRXIE_Msk (0x2UL) /*!< CFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFTXIE_Pos (2UL) /*!< CFTXIE (Bit 2) */ + #define R_CANFD_CFDCFCC_CFTXIE_Msk (0x4UL) /*!< CFTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFPLS_Pos (4UL) /*!< CFPLS (Bit 4) */ + #define R_CANFD_CFDCFCC_CFPLS_Msk (0x70UL) /*!< CFPLS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFM_Pos (8UL) /*!< CFM (Bit 8) */ + #define R_CANFD_CFDCFCC_CFM_Msk (0x300UL) /*!< CFM (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDCFCC_CFITSS_Pos (10UL) /*!< CFITSS (Bit 10) */ + #define R_CANFD_CFDCFCC_CFITSS_Msk (0x400UL) /*!< CFITSS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFITR_Pos (11UL) /*!< CFITR (Bit 11) */ + #define R_CANFD_CFDCFCC_CFITR_Msk (0x800UL) /*!< CFITR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFIM_Pos (12UL) /*!< CFIM (Bit 12) */ + #define R_CANFD_CFDCFCC_CFIM_Msk (0x1000UL) /*!< CFIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFIGCV_Pos (13UL) /*!< CFIGCV (Bit 13) */ + #define R_CANFD_CFDCFCC_CFIGCV_Msk (0xe000UL) /*!< CFIGCV (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFTML_Pos (16UL) /*!< CFTML (Bit 16) */ + #define R_CANFD_CFDCFCC_CFTML_Msk (0x1f0000UL) /*!< CFTML (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDCFCC_CFDC_Pos (21UL) /*!< CFDC (Bit 21) */ + #define R_CANFD_CFDCFCC_CFDC_Msk (0xe00000UL) /*!< CFDC (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFITT_Pos (24UL) /*!< CFITT (Bit 24) */ + #define R_CANFD_CFDCFCC_CFITT_Msk (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCFSTS ======================================================== */ + #define R_CANFD_CFDCFSTS_CFEMP_Pos (0UL) /*!< CFEMP (Bit 0) */ + #define R_CANFD_CFDCFSTS_CFEMP_Msk (0x1UL) /*!< CFEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFFLL_Pos (1UL) /*!< CFFLL (Bit 1) */ + #define R_CANFD_CFDCFSTS_CFFLL_Msk (0x2UL) /*!< CFFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMLT_Pos (2UL) /*!< CFMLT (Bit 2) */ + #define R_CANFD_CFDCFSTS_CFMLT_Msk (0x4UL) /*!< CFMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFRXIF_Pos (3UL) /*!< CFRXIF (Bit 3) */ + #define R_CANFD_CFDCFSTS_CFRXIF_Msk (0x8UL) /*!< CFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFTXIF_Pos (4UL) /*!< CFTXIF (Bit 4) */ + #define R_CANFD_CFDCFSTS_CFTXIF_Msk (0x10UL) /*!< CFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMC_Pos (8UL) /*!< CFMC (Bit 8) */ + #define R_CANFD_CFDCFSTS_CFMC_Msk (0xff00UL) /*!< CFMC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCFPCTR ======================================================= */ + #define R_CANFD_CFDCFPCTR_CFPC_Pos (0UL) /*!< CFPC (Bit 0) */ + #define R_CANFD_CFDCFPCTR_CFPC_Msk (0xffUL) /*!< CFPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDFESTS ======================================================== */ + #define R_CANFD_CFDFESTS_RFXEMP_Pos (0UL) /*!< RFXEMP (Bit 0) */ + #define R_CANFD_CFDFESTS_RFXEMP_Msk (0x3UL) /*!< RFXEMP (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDFESTS_CFXEMP_Pos (8UL) /*!< CFXEMP (Bit 8) */ + #define R_CANFD_CFDFESTS_CFXEMP_Msk (0x100UL) /*!< CFXEMP (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDFFSTS ======================================================== */ + #define R_CANFD_CFDFFSTS_RFXFLL_Pos (0UL) /*!< RFXFLL (Bit 0) */ + #define R_CANFD_CFDFFSTS_RFXFLL_Msk (0x3UL) /*!< RFXFLL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDFFSTS_CFXFLL_Pos (8UL) /*!< CFXFLL (Bit 8) */ + #define R_CANFD_CFDFFSTS_CFXFLL_Msk (0x100UL) /*!< CFXFLL (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDFMSTS ======================================================== */ + #define R_CANFD_CFDFMSTS_RFXMLT_Pos (0UL) /*!< RFXMLT (Bit 0) */ + #define R_CANFD_CFDFMSTS_RFXMLT_Msk (0x3UL) /*!< RFXMLT (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDFMSTS_CFXMLT_Pos (8UL) /*!< CFXMLT (Bit 8) */ + #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x100UL) /*!< CFXMLT (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDRFISTS ======================================================= */ + #define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */ + #define R_CANFD_CFDRFISTS_RFXIF_Msk (0x3UL) /*!< RFXIF (Bitfield-Mask: 0x03) */ +/* ======================================================== CFDTMC ========================================================= */ + #define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */ + #define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMC_TMTAR_Pos (1UL) /*!< TMTAR (Bit 1) */ + #define R_CANFD_CFDTMC_TMTAR_Msk (0x2UL) /*!< TMTAR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMC_TMOM_Pos (2UL) /*!< TMOM (Bit 2) */ + #define R_CANFD_CFDTMC_TMOM_Msk (0x4UL) /*!< TMOM (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTMSTS ======================================================== */ + #define R_CANFD_CFDTMSTS_TMTSTS_Pos (0UL) /*!< TMTSTS (Bit 0) */ + #define R_CANFD_CFDTMSTS_TMTSTS_Msk (0x1UL) /*!< TMTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMSTS_TMTRF_Pos (1UL) /*!< TMTRF (Bit 1) */ + #define R_CANFD_CFDTMSTS_TMTRF_Msk (0x6UL) /*!< TMTRF (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDTMSTS_TMTRM_Pos (3UL) /*!< TMTRM (Bit 3) */ + #define R_CANFD_CFDTMSTS_TMTRM_Msk (0x8UL) /*!< TMTRM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMSTS_TMTARM_Pos (4UL) /*!< TMTARM (Bit 4) */ + #define R_CANFD_CFDTMSTS_TMTARM_Msk (0x10UL) /*!< TMTARM (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTMTRSTS ======================================================= */ + #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Pos (0UL) /*!< CFDTMTRSTSg (Bit 0) */ + #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Msk (0xfUL) /*!< CFDTMTRSTSg (Bitfield-Mask: 0x0f) */ +/* ====================================================== CFDTMTARSTS ====================================================== */ + #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Pos (0UL) /*!< CFDTMTARSTSg (Bit 0) */ + #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Msk (0xfUL) /*!< CFDTMTARSTSg (Bitfield-Mask: 0x0f) */ +/* ====================================================== CFDTMTCSTS ======================================================= */ + #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Pos (0UL) /*!< CFDTMTCSTSg (Bit 0) */ + #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Msk (0xfUL) /*!< CFDTMTCSTSg (Bitfield-Mask: 0x0f) */ +/* ====================================================== CFDTMTASTS ======================================================= */ + #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Pos (0UL) /*!< CFDTMTASTSg (Bit 0) */ + #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Msk (0xfUL) /*!< CFDTMTASTSg (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFDTMIEC ======================================================== */ + #define R_CANFD_CFDTMIEC_TMIEg_Pos (0UL) /*!< TMIEg (Bit 0) */ + #define R_CANFD_CFDTMIEC_TMIEg_Msk (0xfUL) /*!< TMIEg (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFDTXQCC0 ======================================================= */ + #define R_CANFD_CFDTXQCC0_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC0_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC0_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC0_TXQDC_Msk (0x300UL) /*!< TXQDC (Bitfield-Mask: 0x03) */ +/* ====================================================== CFDTXQSTS0 ======================================================= */ + #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS0_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDTXQPCTR0 ====================================================== */ + #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTHLCC ======================================================== */ + #define R_CANFD_CFDTHLCC_THLE_Pos (0UL) /*!< THLE (Bit 0) */ + #define R_CANFD_CFDTHLCC_THLE_Msk (0x1UL) /*!< THLE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLIE_Pos (8UL) /*!< THLIE (Bit 8) */ + #define R_CANFD_CFDTHLCC_THLIE_Msk (0x100UL) /*!< THLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLIM_Pos (9UL) /*!< THLIM (Bit 9) */ + #define R_CANFD_CFDTHLCC_THLIM_Msk (0x200UL) /*!< THLIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLDTE_Pos (10UL) /*!< THLDTE (Bit 10) */ + #define R_CANFD_CFDTHLCC_THLDTE_Msk (0x400UL) /*!< THLDTE (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTHLSTS ======================================================= */ + #define R_CANFD_CFDTHLSTS_THLEMP_Pos (0UL) /*!< THLEMP (Bit 0) */ + #define R_CANFD_CFDTHLSTS_THLEMP_Msk (0x1UL) /*!< THLEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLFLL_Pos (1UL) /*!< THLFLL (Bit 1) */ + #define R_CANFD_CFDTHLSTS_THLFLL_Msk (0x2UL) /*!< THLFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLELT_Pos (2UL) /*!< THLELT (Bit 2) */ + #define R_CANFD_CFDTHLSTS_THLELT_Msk (0x4UL) /*!< THLELT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLIF_Pos (3UL) /*!< THLIF (Bit 3) */ + #define R_CANFD_CFDTHLSTS_THLIF_Msk (0x8UL) /*!< THLIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLMC_Pos (8UL) /*!< THLMC (Bit 8) */ + #define R_CANFD_CFDTHLSTS_THLMC_Msk (0x3f00UL) /*!< THLMC (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDTHLPCTR ======================================================= */ + #define R_CANFD_CFDTHLPCTR_THLPC_Pos (0UL) /*!< THLPC (Bit 0) */ + #define R_CANFD_CFDTHLPCTR_THLPC_Msk (0xffUL) /*!< THLPC (Bitfield-Mask: 0xff) */ +/* ===================================================== CFDGTINTSTS0 ====================================================== */ + #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos (0UL) /*!< TSIF0 (Bit 0) */ + #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk (0x1UL) /*!< TSIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos (1UL) /*!< TAIF0 (Bit 1) */ + #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk (0x2UL) /*!< TAIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos (2UL) /*!< TQIF0 (Bit 2) */ + #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk (0x4UL) /*!< TQIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos (3UL) /*!< CFTIF0 (Bit 3) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk (0x8UL) /*!< CFTIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_THIF0_Pos (4UL) /*!< THIF0 (Bit 4) */ + #define R_CANFD_CFDGTINTSTS0_THIF0_Msk (0x10UL) /*!< THIF0 (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGTSTCFG ======================================================= */ + #define R_CANFD_CFDGTSTCFG_RTMPS_Pos (16UL) /*!< RTMPS (Bit 16) */ + #define R_CANFD_CFDGTSTCFG_RTMPS_Msk (0x3ff0000UL) /*!< RTMPS (Bitfield-Mask: 0x3ff) */ +/* ====================================================== CFDGTSTCTR ======================================================= */ + #define R_CANFD_CFDGTSTCTR_RTME_Pos (2UL) /*!< RTME (Bit 2) */ + #define R_CANFD_CFDGTSTCTR_RTME_Msk (0x4UL) /*!< RTME (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGFDCFG ======================================================= */ + #define R_CANFD_CFDGFDCFG_RPED_Pos (0UL) /*!< RPED (Bit 0) */ + #define R_CANFD_CFDGFDCFG_RPED_Msk (0x1UL) /*!< RPED (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGFDCFG_TSCCFG_Pos (8UL) /*!< TSCCFG (Bit 8) */ + #define R_CANFD_CFDGFDCFG_TSCCFG_Msk (0x300UL) /*!< TSCCFG (Bitfield-Mask: 0x03) */ +/* ======================================================= CFDGLOCKK ======================================================= */ + #define R_CANFD_CFDGLOCKK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ + #define R_CANFD_CFDGLOCKK_LOCK_Msk (0xffffUL) /*!< LOCK (Bitfield-Mask: 0xffff) */ +/* ===================================================== CFDGAFLIGNENT ===================================================== */ + #define R_CANFD_CFDGAFLIGNENT_IRN_Pos (0UL) /*!< IRN (Bit 0) */ + #define R_CANFD_CFDGAFLIGNENT_IRN_Msk (0x1fUL) /*!< IRN (Bitfield-Mask: 0x1f) */ +/* ===================================================== CFDGAFLIGNCTR ===================================================== */ + #define R_CANFD_CFDGAFLIGNCTR_IREN_Pos (0UL) /*!< IREN (Bit 0) */ + #define R_CANFD_CFDGAFLIGNCTR_IREN_Msk (0x1UL) /*!< IREN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFLIGNCTR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CANFD_CFDGAFLIGNCTR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCDTCT ======================================================== */ + #define R_CANFD_CFDCDTCT_RFDMAE0_Pos (0UL) /*!< RFDMAE0 (Bit 0) */ + #define R_CANFD_CFDCDTCT_RFDMAE0_Msk (0x1UL) /*!< RFDMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE1_Pos (1UL) /*!< RFDMAE1 (Bit 1) */ + #define R_CANFD_CFDCDTCT_RFDMAE1_Msk (0x2UL) /*!< RFDMAE1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_CFDMAE0_Pos (8UL) /*!< CFDMAE0 (Bit 8) */ + #define R_CANFD_CFDCDTCT_CFDMAE0_Msk (0x100UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCDTSTS ======================================================= */ + #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos (0UL) /*!< RFDMASTS0 (Bit 0) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk (0x1UL) /*!< RFDMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos (1UL) /*!< RFDMASTS1 (Bit 1) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk (0x2UL) /*!< RFDMASTS1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos (8UL) /*!< CFDMASTS0 (Bit 8) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk (0x100UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGRSTC ======================================================== */ + #define R_CANFD_CFDGRSTC_SRST_Pos (0UL) /*!< SRST (Bit 0) */ + #define R_CANFD_CFDGRSTC_SRST_Msk (0x1UL) /*!< SRST (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGRSTC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CANFD_CFDGRSTC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDRPGACC ======================================================= */ + #define R_CANFD_CFDRPGACC_RDTA_Pos (0UL) /*!< RDTA (Bit 0) */ + #define R_CANFD_CFDRPGACC_RDTA_Msk (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ + #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ + #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ + #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ + #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDIR_BY ======================================================= */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCDOR ========================================================= */ + #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ + #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDOR_HA ======================================================= */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ +/* ======================================================= CRCDOR_BY ======================================================= */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCSAR ========================================================= */ + #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ + #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC_B0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DADR ========================================================== */ + #define R_DAC_B0_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ + #define R_DAC_B0_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DACR0 ========================================================= */ + #define R_DAC_B0_DACR0_DACEN_Pos (0UL) /*!< DACEN (Bit 0) */ + #define R_DAC_B0_DACR0_DACEN_Msk (0x1UL) /*!< DACEN (Bitfield-Mask: 0x01) */ + #define R_DAC_B0_DACR0_DAE_Pos (15UL) /*!< DAE (Bit 15) */ + #define R_DAC_B0_DACR0_DAE_Msk (0x8000UL) /*!< DAE (Bitfield-Mask: 0x01) */ + #define R_DAC_B0_DACR0_DAOUTDIS_Pos (31UL) /*!< DAOUTDIS (Bit 31) */ + #define R_DAC_B0_DACR0_DAOUTDIS_Msk (0x80000000UL) /*!< DAOUTDIS (Bitfield-Mask: 0x01) */ +/* ========================================================= DACR1 ========================================================= */ + #define R_DAC_B0_DACR1_DPSEL_Pos (16UL) /*!< DPSEL (Bit 16) */ + #define R_DAC_B0_DACR1_DPSEL_Msk (0x10000UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= DACR2 ========================================================= */ + #define R_DAC_B0_DACR2_OFSSEL_Pos (8UL) /*!< OFSSEL (Bit 8) */ + #define R_DAC_B0_DACR2_OFSSEL_Msk (0x100UL) /*!< OFSSEL (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DBGSTR ========================================================= */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGSTOPCR ======================================================= */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Pos (14UL) /*!< DBGSTOP_TIM (Bit 14) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Msk (0x4000UL) /*!< DBGSTOP_TIM (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Pos (15UL) /*!< DBGSTOP_SIR (Bit 15) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Msk (0x8000UL) /*!< DBGSTOP_SIR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT1_Pos (2UL) /*!< DBGSTOP_WDT1 (Bit 2) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT1_Msk (0x4UL) /*!< DBGSTOP_WDT1 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_NVMERR_Pos (26UL) /*!< DBGSTOP_NVMERR (Bit 26) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_NVMERR_Msk (0x4000000UL) /*!< DBGSTOP_NVMERR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CTERR0_Pos (28UL) /*!< DBGSTOP_CTERR0 (Bit 28) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CTERR0_Msk (0x10000000UL) /*!< DBGSTOP_CTERR0 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CTERR1_Pos (29UL) /*!< DBGSTOP_CTERR1 (Bit 29) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CTERR1_Msk (0x20000000UL) /*!< DBGSTOP_CTERR1 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGAUTH0 ======================================================== */ + #define R_DEBUG_DBGAUTH0_DBGEN0_Pos (0UL) /*!< DBGEN0 (Bit 0) */ + #define R_DEBUG_DBGAUTH0_DBGEN0_Msk (0x1UL) /*!< DBGEN0 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGAUTH0_DBGEN1_Pos (1UL) /*!< DBGEN1 (Bit 1) */ + #define R_DEBUG_DBGAUTH0_DBGEN1_Msk (0x2UL) /*!< DBGEN1 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGAUTH0_NIDEN0_Pos (4UL) /*!< NIDEN0 (Bit 4) */ + #define R_DEBUG_DBGAUTH0_NIDEN0_Msk (0x10UL) /*!< NIDEN0 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGAUTH0_NIDEN1_Pos (5UL) /*!< NIDEN1 (Bit 5) */ + #define R_DEBUG_DBGAUTH0_NIDEN1_Msk (0x20UL) /*!< NIDEN1 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGAUTH0_DEVICEEN_Pos (16UL) /*!< DEVICEEN (Bit 16) */ + #define R_DEBUG_DBGAUTH0_DEVICEEN_Msk (0x10000UL) /*!< DEVICEEN (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGAUTH0_SWDBG_Pos (31UL) /*!< SWDBG (Bit 31) */ + #define R_DEBUG_DBGAUTH0_SWDBG_Msk (0x80000000UL) /*!< SWDBG (Bitfield-Mask: 0x01) */ +/* ====================================================== CACHEDBGCR ======================================================= */ + #define R_DEBUG_CACHEDBGCR_L1RSTDIS_Pos (0UL) /*!< L1RSTDIS (Bit 0) */ + #define R_DEBUG_CACHEDBGCR_L1RSTDIS_Msk (0x1UL) /*!< L1RSTDIS (Bitfield-Mask: 0x01) */ +/* ======================================================= TRPORTCR ======================================================== */ + #define R_DEBUG_TRPORTCR_OE_Pos (0UL) /*!< OE (Bit 0) */ + #define R_DEBUG_TRPORTCR_OE_Msk (0x1UL) /*!< OE (Bitfield-Mask: 0x01) */ + #define R_DEBUG_TRPORTCR_DRV_Pos (2UL) /*!< DRV (Bit 2) */ + #define R_DEBUG_TRPORTCR_DRV_Msk (0xcUL) /*!< DRV (Bitfield-Mask: 0x03) */ + #define R_DEBUG_TRPORTCR_PORTSEL_Pos (8UL) /*!< PORTSEL (Bit 8) */ + #define R_DEBUG_TRPORTCR_PORTSEL_Msk (0x300UL) /*!< PORTSEL (Bitfield-Mask: 0x03) */ + #define R_DEBUG_TRPORTCR_SWOSEL_Pos (16UL) /*!< SWOSEL (Bit 16) */ + #define R_DEBUG_TRPORTCR_SWOSEL_Msk (0x10000UL) /*!< SWOSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== ALCTRL ========================================================= */ + #define R_DEBUG_ALCTRL_AL_Pos (0UL) /*!< AL (Bit 0) */ + #define R_DEBUG_ALCTRL_AL_Msk (0xffUL) /*!< AL (Bitfield-Mask: 0xff) */ + #define R_DEBUG_ALCTRL_FAILCNT_Pos (30UL) /*!< FAILCNT (Bit 30) */ + #define R_DEBUG_ALCTRL_FAILCNT_Msk (0xc0000000UL) /*!< FAILCNT (Bitfield-Mask: 0x03) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ +/* ======================================================= TRPORTSZ ======================================================== */ + #define R_DEBUG_TRPORTSZ_PORTSIZE_Pos (0UL) /*!< PORTSIZE (Bit 0) */ + #define R_DEBUG_TRPORTSZ_PORTSIZE_Msk (0xffffffffUL) /*!< PORTSIZE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DBGNVMCR ======================================================== */ + #define R_DEBUG_DBGNVMCR_NVMWE_Pos (0UL) /*!< NVMWE (Bit 0) */ + #define R_DEBUG_DBGNVMCR_NVMWE_Msk (0x1UL) /*!< NVMWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMAST ========================================================= */ + #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ + #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ +/* ======================================================== DMECHR ========================================================= */ + #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ + #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ + #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ + #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ + #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ + #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */ +/* ========================================================= DELSR ========================================================= */ + #define R_DMA_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMSAR ========================================================= */ + #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */ + #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMDAR ========================================================= */ + #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */ + #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCRA ========================================================= */ + #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */ + #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */ + #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */ + #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMCRB ========================================================= */ + #define R_DMAC0_DMCRB_DMCRBL_Pos (0UL) /*!< DMCRBL (Bit 0) */ + #define R_DMAC0_DMCRB_DMCRBL_Msk (0xffffUL) /*!< DMCRBL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMCRB_DMCRBH_Pos (16UL) /*!< DMCRBH (Bit 16) */ + #define R_DMAC0_DMCRB_DMCRBH_Msk (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMTMD ========================================================= */ + #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */ + #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */ + #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */ + #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */ + #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */ + #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */ +/* ========================================================= DMINT ========================================================= */ + #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */ + #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */ + #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */ + #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */ + #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */ + #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMAMD ========================================================= */ + #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */ + #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */ + #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */ + #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */ + #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */ + #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */ + #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */ +/* ========================================================= DMOFR ========================================================= */ + #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */ + #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCNT ========================================================= */ + #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */ + #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMREQ ========================================================= */ + #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */ + #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */ + #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSTS ========================================================= */ + #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */ + #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */ + #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSRR ========================================================= */ +/* ========================================================= DMDRR ========================================================= */ +/* ========================================================= DMSBS ========================================================= */ + #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */ + #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */ + #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMDBS ========================================================= */ + #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */ + #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */ + #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMBWR ========================================================= */ + #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */ + #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ +/* ========================================================= DODIR ========================================================= */ + #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ + #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DODSR ========================================================= */ + #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ + #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_DRW ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CONTROL ======================================================== */ + #define R_DRW_CONTROL_SPANSTORE_Pos (23UL) /*!< SPANSTORE (Bit 23) */ + #define R_DRW_CONTROL_SPANSTORE_Msk (0x800000UL) /*!< SPANSTORE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_SPANABORT_Pos (22UL) /*!< SPANABORT (Bit 22) */ + #define R_DRW_CONTROL_SPANABORT_Msk (0x400000UL) /*!< SPANABORT (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNIONCD_Pos (21UL) /*!< UNIONCD (Bit 21) */ + #define R_DRW_CONTROL_UNIONCD_Msk (0x200000UL) /*!< UNIONCD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNIONAB_Pos (20UL) /*!< UNIONAB (Bit 20) */ + #define R_DRW_CONTROL_UNIONAB_Msk (0x100000UL) /*!< UNIONAB (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNION56_Pos (19UL) /*!< UNION56 (Bit 19) */ + #define R_DRW_CONTROL_UNION56_Msk (0x80000UL) /*!< UNION56 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNION34_Pos (18UL) /*!< UNION34 (Bit 18) */ + #define R_DRW_CONTROL_UNION34_Msk (0x40000UL) /*!< UNION34 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNION12_Pos (17UL) /*!< UNION12 (Bit 17) */ + #define R_DRW_CONTROL_UNION12_Msk (0x20000UL) /*!< UNION12 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_BAND2ENABLE_Pos (16UL) /*!< BAND2ENABLE (Bit 16) */ + #define R_DRW_CONTROL_BAND2ENABLE_Msk (0x10000UL) /*!< BAND2ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_BAND1ENABLE_Pos (15UL) /*!< BAND1ENABLE (Bit 15) */ + #define R_DRW_CONTROL_BAND1ENABLE_Msk (0x8000UL) /*!< BAND1ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM6THRESHOLD_Pos (14UL) /*!< LIM6THRESHOLD (Bit 14) */ + #define R_DRW_CONTROL_LIM6THRESHOLD_Msk (0x4000UL) /*!< LIM6THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM5THRESHOLD_Pos (13UL) /*!< LIM5THRESHOLD (Bit 13) */ + #define R_DRW_CONTROL_LIM5THRESHOLD_Msk (0x2000UL) /*!< LIM5THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM4THRESHOLD_Pos (12UL) /*!< LIM4THRESHOLD (Bit 12) */ + #define R_DRW_CONTROL_LIM4THRESHOLD_Msk (0x1000UL) /*!< LIM4THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM3THRESHOLD_Pos (11UL) /*!< LIM3THRESHOLD (Bit 11) */ + #define R_DRW_CONTROL_LIM3THRESHOLD_Msk (0x800UL) /*!< LIM3THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM2THRESHOLD_Pos (10UL) /*!< LIM2THRESHOLD (Bit 10) */ + #define R_DRW_CONTROL_LIM2THRESHOLD_Msk (0x400UL) /*!< LIM2THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM1THRESHOLD_Pos (9UL) /*!< LIM1THRESHOLD (Bit 9) */ + #define R_DRW_CONTROL_LIM1THRESHOLD_Msk (0x200UL) /*!< LIM1THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_QUAD3ENABLE_Pos (8UL) /*!< QUAD3ENABLE (Bit 8) */ + #define R_DRW_CONTROL_QUAD3ENABLE_Msk (0x100UL) /*!< QUAD3ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_QUAD2ENABLE_Pos (7UL) /*!< QUAD2ENABLE (Bit 7) */ + #define R_DRW_CONTROL_QUAD2ENABLE_Msk (0x80UL) /*!< QUAD2ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_QUAD1ENABLE_Pos (6UL) /*!< QUAD1ENABLE (Bit 6) */ + #define R_DRW_CONTROL_QUAD1ENABLE_Msk (0x40UL) /*!< QUAD1ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM6ENABLE_Pos (5UL) /*!< LIM6ENABLE (Bit 5) */ + #define R_DRW_CONTROL_LIM6ENABLE_Msk (0x20UL) /*!< LIM6ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM5ENABLE_Pos (4UL) /*!< LIM5ENABLE (Bit 4) */ + #define R_DRW_CONTROL_LIM5ENABLE_Msk (0x10UL) /*!< LIM5ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM4ENABLE_Pos (3UL) /*!< LIM4ENABLE (Bit 3) */ + #define R_DRW_CONTROL_LIM4ENABLE_Msk (0x8UL) /*!< LIM4ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM3ENABLE_Pos (2UL) /*!< LIM3ENABLE (Bit 2) */ + #define R_DRW_CONTROL_LIM3ENABLE_Msk (0x4UL) /*!< LIM3ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM2ENABLE_Pos (1UL) /*!< LIM2ENABLE (Bit 1) */ + #define R_DRW_CONTROL_LIM2ENABLE_Msk (0x2UL) /*!< LIM2ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM1ENABLE_Pos (0UL) /*!< LIM1ENABLE (Bit 0) */ + #define R_DRW_CONTROL_LIM1ENABLE_Msk (0x1UL) /*!< LIM1ENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================= CONTROL2 ======================================================== */ + #define R_DRW_CONTROL2_RLEPIXELWIDTH_Pos (30UL) /*!< RLEPIXELWIDTH (Bit 30) */ + #define R_DRW_CONTROL2_RLEPIXELWIDTH_Msk (0xc0000000UL) /*!< RLEPIXELWIDTH (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_BDIA_Pos (29UL) /*!< BDIA (Bit 29) */ + #define R_DRW_CONTROL2_BDIA_Msk (0x20000000UL) /*!< BDIA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSIA_Pos (28UL) /*!< BSIA (Bit 28) */ + #define R_DRW_CONTROL2_BSIA_Msk (0x10000000UL) /*!< BSIA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_CLUTFORMAT_Pos (27UL) /*!< CLUTFORMAT (Bit 27) */ + #define R_DRW_CONTROL2_CLUTFORMAT_Msk (0x8000000UL) /*!< CLUTFORMAT (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_COLKEYENABLE_Pos (26UL) /*!< COLKEYENABLE (Bit 26) */ + #define R_DRW_CONTROL2_COLKEYENABLE_Msk (0x4000000UL) /*!< COLKEYENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_CLUTENABLE_Pos (25UL) /*!< CLUTENABLE (Bit 25) */ + #define R_DRW_CONTROL2_CLUTENABLE_Msk (0x2000000UL) /*!< CLUTENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_RLEENABLE_Pos (24UL) /*!< RLEENABLE (Bit 24) */ + #define R_DRW_CONTROL2_RLEENABLE_Msk (0x1000000UL) /*!< RLEENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_WRITEALPHA_Pos (22UL) /*!< WRITEALPHA (Bit 22) */ + #define R_DRW_CONTROL2_WRITEALPHA_Msk (0xc00000UL) /*!< WRITEALPHA (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_WRITEFORMAT10_Pos (20UL) /*!< WRITEFORMAT10 (Bit 20) */ + #define R_DRW_CONTROL2_WRITEFORMAT10_Msk (0x300000UL) /*!< WRITEFORMAT10 (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_READFORMAT10_Pos (18UL) /*!< READFORMAT10 (Bit 18) */ + #define R_DRW_CONTROL2_READFORMAT10_Msk (0xc0000UL) /*!< READFORMAT10 (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_TEXTUREFILTERY_Pos (17UL) /*!< TEXTUREFILTERY (Bit 17) */ + #define R_DRW_CONTROL2_TEXTUREFILTERY_Msk (0x20000UL) /*!< TEXTUREFILTERY (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTUREFILTERX_Pos (16UL) /*!< TEXTUREFILTERX (Bit 16) */ + #define R_DRW_CONTROL2_TEXTUREFILTERX_Msk (0x10000UL) /*!< TEXTUREFILTERX (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTURECLAMPY_Pos (15UL) /*!< TEXTURECLAMPY (Bit 15) */ + #define R_DRW_CONTROL2_TEXTURECLAMPY_Msk (0x8000UL) /*!< TEXTURECLAMPY (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTURECLAMPX_Pos (14UL) /*!< TEXTURECLAMPX (Bit 14) */ + #define R_DRW_CONTROL2_TEXTURECLAMPX_Msk (0x4000UL) /*!< TEXTURECLAMPX (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BC2_Pos (13UL) /*!< BC2 (Bit 13) */ + #define R_DRW_CONTROL2_BC2_Msk (0x2000UL) /*!< BC2 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BDI_Pos (12UL) /*!< BDI (Bit 12) */ + #define R_DRW_CONTROL2_BDI_Msk (0x1000UL) /*!< BDI (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSI_Pos (11UL) /*!< BSI (Bit 11) */ + #define R_DRW_CONTROL2_BSI_Msk (0x800UL) /*!< BSI (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BDF_Pos (10UL) /*!< BDF (Bit 10) */ + #define R_DRW_CONTROL2_BDF_Msk (0x400UL) /*!< BDF (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSF_Pos (9UL) /*!< BSF (Bit 9) */ + #define R_DRW_CONTROL2_BSF_Msk (0x200UL) /*!< BSF (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_WRITEFORMAT2_Pos (8UL) /*!< WRITEFORMAT2 (Bit 8) */ + #define R_DRW_CONTROL2_WRITEFORMAT2_Msk (0x100UL) /*!< WRITEFORMAT2 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BDFA_Pos (7UL) /*!< BDFA (Bit 7) */ + #define R_DRW_CONTROL2_BDFA_Msk (0x80UL) /*!< BDFA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSFA_Pos (6UL) /*!< BSFA (Bit 6) */ + #define R_DRW_CONTROL2_BSFA_Msk (0x40UL) /*!< BSFA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_READFORMAT32_Pos (4UL) /*!< READFORMAT32 (Bit 4) */ + #define R_DRW_CONTROL2_READFORMAT32_Msk (0x30UL) /*!< READFORMAT32 (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_USEACB_Pos (3UL) /*!< USEACB (Bit 3) */ + #define R_DRW_CONTROL2_USEACB_Msk (0x8UL) /*!< USEACB (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_PATTERNSOURCEL5_Pos (2UL) /*!< PATTERNSOURCEL5 (Bit 2) */ + #define R_DRW_CONTROL2_PATTERNSOURCEL5_Msk (0x4UL) /*!< PATTERNSOURCEL5 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTUREENABLE_Pos (1UL) /*!< TEXTUREENABLE (Bit 1) */ + #define R_DRW_CONTROL2_TEXTUREENABLE_Msk (0x2UL) /*!< TEXTUREENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_PATTERNENABLE_Pos (0UL) /*!< PATTERNENABLE (Bit 0) */ + #define R_DRW_CONTROL2_PATTERNENABLE_Msk (0x1UL) /*!< PATTERNENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================== IRQCTL ========================================================= */ + #define R_DRW_IRQCTL_BUSIRQCLR_Pos (5UL) /*!< BUSIRQCLR (Bit 5) */ + #define R_DRW_IRQCTL_BUSIRQCLR_Msk (0x20UL) /*!< BUSIRQCLR (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_BUSIRQEN_Pos (4UL) /*!< BUSIRQEN (Bit 4) */ + #define R_DRW_IRQCTL_BUSIRQEN_Msk (0x10UL) /*!< BUSIRQEN (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_DLISTIRQCLR_Pos (3UL) /*!< DLISTIRQCLR (Bit 3) */ + #define R_DRW_IRQCTL_DLISTIRQCLR_Msk (0x8UL) /*!< DLISTIRQCLR (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_ENUMIRQCLR_Pos (2UL) /*!< ENUMIRQCLR (Bit 2) */ + #define R_DRW_IRQCTL_ENUMIRQCLR_Msk (0x4UL) /*!< ENUMIRQCLR (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_DLISTIRQEN_Pos (1UL) /*!< DLISTIRQEN (Bit 1) */ + #define R_DRW_IRQCTL_DLISTIRQEN_Msk (0x2UL) /*!< DLISTIRQEN (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_ENUMIRQEN_Pos (0UL) /*!< ENUMIRQEN (Bit 0) */ + #define R_DRW_IRQCTL_ENUMIRQEN_Msk (0x1UL) /*!< ENUMIRQEN (Bitfield-Mask: 0x01) */ +/* ======================================================= CACHECTL ======================================================== */ + #define R_DRW_CACHECTL_CFLUSHTX_Pos (3UL) /*!< CFLUSHTX (Bit 3) */ + #define R_DRW_CACHECTL_CFLUSHTX_Msk (0x8UL) /*!< CFLUSHTX (Bitfield-Mask: 0x01) */ + #define R_DRW_CACHECTL_CENABLETX_Pos (2UL) /*!< CENABLETX (Bit 2) */ + #define R_DRW_CACHECTL_CENABLETX_Msk (0x4UL) /*!< CENABLETX (Bitfield-Mask: 0x01) */ + #define R_DRW_CACHECTL_CFLUSHFX_Pos (1UL) /*!< CFLUSHFX (Bit 1) */ + #define R_DRW_CACHECTL_CFLUSHFX_Msk (0x2UL) /*!< CFLUSHFX (Bitfield-Mask: 0x01) */ + #define R_DRW_CACHECTL_CENABLEFX_Pos (0UL) /*!< CENABLEFX (Bit 0) */ + #define R_DRW_CACHECTL_CENABLEFX_Msk (0x1UL) /*!< CENABLEFX (Bitfield-Mask: 0x01) */ +/* ======================================================== STATUS ========================================================= */ + #define R_DRW_STATUS_BUSERRMDL_Pos (10UL) /*!< BUSERRMDL (Bit 10) */ + #define R_DRW_STATUS_BUSERRMDL_Msk (0x400UL) /*!< BUSERRMDL (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSERRMTXMRL_Pos (9UL) /*!< BUSERRMTXMRL (Bit 9) */ + #define R_DRW_STATUS_BUSERRMTXMRL_Msk (0x200UL) /*!< BUSERRMTXMRL (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSERRMFB_Pos (8UL) /*!< BUSERRMFB (Bit 8) */ + #define R_DRW_STATUS_BUSERRMFB_Msk (0x100UL) /*!< BUSERRMFB (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSIRQ_Pos (6UL) /*!< BUSIRQ (Bit 6) */ + #define R_DRW_STATUS_BUSIRQ_Msk (0x40UL) /*!< BUSIRQ (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_DLISTIRQ_Pos (5UL) /*!< DLISTIRQ (Bit 5) */ + #define R_DRW_STATUS_DLISTIRQ_Msk (0x20UL) /*!< DLISTIRQ (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_ENUMIRQ_Pos (4UL) /*!< ENUMIRQ (Bit 4) */ + #define R_DRW_STATUS_ENUMIRQ_Msk (0x10UL) /*!< ENUMIRQ (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_DLISTACTIVE_Pos (3UL) /*!< DLISTACTIVE (Bit 3) */ + #define R_DRW_STATUS_DLISTACTIVE_Msk (0x8UL) /*!< DLISTACTIVE (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_CACHEDIRTY_Pos (2UL) /*!< CACHEDIRTY (Bit 2) */ + #define R_DRW_STATUS_CACHEDIRTY_Msk (0x4UL) /*!< CACHEDIRTY (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSYWRITE_Pos (1UL) /*!< BUSYWRITE (Bit 1) */ + #define R_DRW_STATUS_BUSYWRITE_Msk (0x2UL) /*!< BUSYWRITE (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSYENUM_Pos (0UL) /*!< BUSYENUM (Bit 0) */ + #define R_DRW_STATUS_BUSYENUM_Msk (0x1UL) /*!< BUSYENUM (Bitfield-Mask: 0x01) */ +/* ====================================================== HWREVISION ======================================================= */ + #define R_DRW_HWREVISION_ACBLEND_Pos (27UL) /*!< ACBLEND (Bit 27) */ + #define R_DRW_HWREVISION_ACBLEND_Msk (0x8000000UL) /*!< ACBLEND (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_COLORKEY_Pos (25UL) /*!< COLORKEY (Bit 25) */ + #define R_DRW_HWREVISION_COLORKEY_Msk (0x2000000UL) /*!< COLORKEY (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_TEXCLUT256_Pos (24UL) /*!< TEXCLUT256 (Bit 24) */ + #define R_DRW_HWREVISION_TEXCLUT256_Msk (0x1000000UL) /*!< TEXCLUT256 (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_RLEUNIT_Pos (23UL) /*!< RLEUNIT (Bit 23) */ + #define R_DRW_HWREVISION_RLEUNIT_Msk (0x800000UL) /*!< RLEUNIT (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_TEXCLU_Pos (21UL) /*!< TEXCLU (Bit 21) */ + #define R_DRW_HWREVISION_TEXCLU_Msk (0x200000UL) /*!< TEXCLU (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_PERFCOUNT_Pos (20UL) /*!< PERFCOUNT (Bit 20) */ + #define R_DRW_HWREVISION_PERFCOUNT_Msk (0x100000UL) /*!< PERFCOUNT (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_TXCACHE_Pos (19UL) /*!< TXCACHE (Bit 19) */ + #define R_DRW_HWREVISION_TXCACHE_Msk (0x80000UL) /*!< TXCACHE (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_FBCACHE_Pos (18UL) /*!< FBCACHE (Bit 18) */ + #define R_DRW_HWREVISION_FBCACHE_Msk (0x40000UL) /*!< FBCACHE (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_DLR_Pos (17UL) /*!< DLR (Bit 17) */ + #define R_DRW_HWREVISION_DLR_Msk (0x20000UL) /*!< DLR (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_REV_Pos (0UL) /*!< REV (Bit 0) */ + #define R_DRW_HWREVISION_REV_Msk (0xfffUL) /*!< REV (Bitfield-Mask: 0xfff) */ +/* ======================================================== COLOR1 ========================================================= */ + #define R_DRW_COLOR1_COLOR1A_Pos (24UL) /*!< COLOR1A (Bit 24) */ + #define R_DRW_COLOR1_COLOR1A_Msk (0xff000000UL) /*!< COLOR1A (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR1_COLOR1R_Pos (16UL) /*!< COLOR1R (Bit 16) */ + #define R_DRW_COLOR1_COLOR1R_Msk (0xff0000UL) /*!< COLOR1R (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR1_COLOR1G_Pos (8UL) /*!< COLOR1G (Bit 8) */ + #define R_DRW_COLOR1_COLOR1G_Msk (0xff00UL) /*!< COLOR1G (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR1_COLOR1B_Pos (0UL) /*!< COLOR1B (Bit 0) */ + #define R_DRW_COLOR1_COLOR1B_Msk (0xffUL) /*!< COLOR1B (Bitfield-Mask: 0xff) */ +/* ======================================================== COLOR2 ========================================================= */ + #define R_DRW_COLOR2_COLOR2A_Pos (24UL) /*!< COLOR2A (Bit 24) */ + #define R_DRW_COLOR2_COLOR2A_Msk (0xff000000UL) /*!< COLOR2A (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR2_COLOR2R_Pos (16UL) /*!< COLOR2R (Bit 16) */ + #define R_DRW_COLOR2_COLOR2R_Msk (0xff0000UL) /*!< COLOR2R (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR2_COLOR2G_Pos (8UL) /*!< COLOR2G (Bit 8) */ + #define R_DRW_COLOR2_COLOR2G_Msk (0xff00UL) /*!< COLOR2G (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR2_COLOR2B_Pos (0UL) /*!< COLOR2B (Bit 0) */ + #define R_DRW_COLOR2_COLOR2B_Msk (0xffUL) /*!< COLOR2B (Bitfield-Mask: 0xff) */ +/* ======================================================== PATTERN ======================================================== */ + #define R_DRW_PATTERN_PATTERN_Pos (0UL) /*!< PATTERN (Bit 0) */ + #define R_DRW_PATTERN_PATTERN_Msk (0xffUL) /*!< PATTERN (Bitfield-Mask: 0xff) */ +/* ======================================================== L1START ======================================================== */ + #define R_DRW_L1START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L1START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2START ======================================================== */ + #define R_DRW_L2START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L2START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L3START ======================================================== */ + #define R_DRW_L3START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L3START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L4START ======================================================== */ + #define R_DRW_L4START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L4START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L5START ======================================================== */ + #define R_DRW_L5START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L5START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L6START ======================================================== */ + #define R_DRW_L6START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L6START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L1XADD ========================================================= */ + #define R_DRW_L1XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L1XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2XADD ========================================================= */ + #define R_DRW_L2XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L2XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L3XADD ========================================================= */ + #define R_DRW_L3XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L3XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L4XADD ========================================================= */ + #define R_DRW_L4XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L4XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L5XADD ========================================================= */ + #define R_DRW_L5XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L5XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L6XADD ========================================================= */ + #define R_DRW_L6XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L6XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L1YADD ========================================================= */ + #define R_DRW_L1YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L1YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2YADD ========================================================= */ + #define R_DRW_L2YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L2YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L3YADD ========================================================= */ + #define R_DRW_L3YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L3YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L4YADD ========================================================= */ + #define R_DRW_L4YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L4YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L5YADD ========================================================= */ + #define R_DRW_L5YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L5YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L6YADD ========================================================= */ + #define R_DRW_L6YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L6YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L1BAND ========================================================= */ + #define R_DRW_L1BAND_LBAND_Pos (0UL) /*!< LBAND (Bit 0) */ + #define R_DRW_L1BAND_LBAND_Msk (0xffffffffUL) /*!< LBAND (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2BAND ========================================================= */ + #define R_DRW_L2BAND_LBAND_Pos (0UL) /*!< LBAND (Bit 0) */ + #define R_DRW_L2BAND_LBAND_Msk (0xffffffffUL) /*!< LBAND (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TEXORIGIN ======================================================= */ + #define R_DRW_TEXORIGIN_TEXORIGIN_Pos (0UL) /*!< TEXORIGIN (Bit 0) */ + #define R_DRW_TEXORIGIN_TEXORIGIN_Msk (0xffffffffUL) /*!< TEXORIGIN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TEXPITCH ======================================================== */ + #define R_DRW_TEXPITCH_TEXPITCH_Pos (0UL) /*!< TEXPITCH (Bit 0) */ + #define R_DRW_TEXPITCH_TEXPITCH_Msk (0xffffffffUL) /*!< TEXPITCH (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TEXMASK ======================================================== */ + #define R_DRW_TEXMASK_TEXVMASK_Pos (11UL) /*!< TEXVMASK (Bit 11) */ + #define R_DRW_TEXMASK_TEXVMASK_Msk (0xfffff800UL) /*!< TEXVMASK (Bitfield-Mask: 0x1fffff) */ + #define R_DRW_TEXMASK_TEXUMASK_Pos (0UL) /*!< TEXUMASK (Bit 0) */ + #define R_DRW_TEXMASK_TEXUMASK_Msk (0x7ffUL) /*!< TEXUMASK (Bitfield-Mask: 0x7ff) */ +/* ======================================================== LUSTART ======================================================== */ + #define R_DRW_LUSTART_LUSTART_Pos (0UL) /*!< LUSTART (Bit 0) */ + #define R_DRW_LUSTART_LUSTART_Msk (0xffffffffUL) /*!< LUSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LUXADD ========================================================= */ + #define R_DRW_LUXADD_LUXADD_Pos (0UL) /*!< LUXADD (Bit 0) */ + #define R_DRW_LUXADD_LUXADD_Msk (0xffffffffUL) /*!< LUXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LUYADD ========================================================= */ + #define R_DRW_LUYADD_LUYADD_Pos (0UL) /*!< LUYADD (Bit 0) */ + #define R_DRW_LUYADD_LUYADD_Msk (0xffffffffUL) /*!< LUYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= LVSTARTI ======================================================== */ + #define R_DRW_LVSTARTI_LVSTARTI_Pos (0UL) /*!< LVSTARTI (Bit 0) */ + #define R_DRW_LVSTARTI_LVSTARTI_Msk (0xffffffffUL) /*!< LVSTARTI (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= LVSTARTF ======================================================== */ + #define R_DRW_LVSTARTF_LVSTARTF_Pos (0UL) /*!< LVSTARTF (Bit 0) */ + #define R_DRW_LVSTARTF_LVSTARTF_Msk (0xffffUL) /*!< LVSTARTF (Bitfield-Mask: 0xffff) */ +/* ======================================================== LVXADDI ======================================================== */ + #define R_DRW_LVXADDI_LVXADDI_Pos (0UL) /*!< LVXADDI (Bit 0) */ + #define R_DRW_LVXADDI_LVXADDI_Msk (0xffffffffUL) /*!< LVXADDI (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LVYADDI ======================================================== */ + #define R_DRW_LVYADDI_LVYADDI_Pos (0UL) /*!< LVYADDI (Bit 0) */ + #define R_DRW_LVYADDI_LVYADDI_Msk (0xffffffffUL) /*!< LVYADDI (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= LVYXADDF ======================================================== */ + #define R_DRW_LVYXADDF_LVYADDF_Pos (16UL) /*!< LVYADDF (Bit 16) */ + #define R_DRW_LVYXADDF_LVYADDF_Msk (0xffff0000UL) /*!< LVYADDF (Bitfield-Mask: 0xffff) */ + #define R_DRW_LVYXADDF_LVXADDF_Pos (0UL) /*!< LVXADDF (Bit 0) */ + #define R_DRW_LVYXADDF_LVXADDF_Msk (0xffffUL) /*!< LVXADDF (Bitfield-Mask: 0xffff) */ +/* ======================================================= TEXCLADDR ======================================================= */ + #define R_DRW_TEXCLADDR_CLADDR_Pos (0UL) /*!< CLADDR (Bit 0) */ + #define R_DRW_TEXCLADDR_CLADDR_Msk (0xffUL) /*!< CLADDR (Bitfield-Mask: 0xff) */ +/* ======================================================= TEXCLDATA ======================================================= */ + #define R_DRW_TEXCLDATA_CLDATA_Pos (0UL) /*!< CLDATA (Bit 0) */ + #define R_DRW_TEXCLDATA_CLDATA_Msk (0xffffffffUL) /*!< CLDATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== TEXCLOFFSET ====================================================== */ + #define R_DRW_TEXCLOFFSET_CLOFFSET_Pos (0UL) /*!< CLOFFSET (Bit 0) */ + #define R_DRW_TEXCLOFFSET_CLOFFSET_Msk (0xffUL) /*!< CLOFFSET (Bitfield-Mask: 0xff) */ +/* ======================================================== COLKEY ========================================================= */ + #define R_DRW_COLKEY_COLKEYR_Pos (16UL) /*!< COLKEYR (Bit 16) */ + #define R_DRW_COLKEY_COLKEYR_Msk (0xff0000UL) /*!< COLKEYR (Bitfield-Mask: 0xff) */ + #define R_DRW_COLKEY_COLKEYG_Pos (8UL) /*!< COLKEYG (Bit 8) */ + #define R_DRW_COLKEY_COLKEYG_Msk (0xff00UL) /*!< COLKEYG (Bitfield-Mask: 0xff) */ + #define R_DRW_COLKEY_COLKEYB_Pos (0UL) /*!< COLKEYB (Bit 0) */ + #define R_DRW_COLKEY_COLKEYB_Msk (0xffUL) /*!< COLKEYB (Bitfield-Mask: 0xff) */ +/* ========================================================= SIZE ========================================================== */ + #define R_DRW_SIZE_SIZEY_Pos (16UL) /*!< SIZEY (Bit 16) */ + #define R_DRW_SIZE_SIZEY_Msk (0xffff0000UL) /*!< SIZEY (Bitfield-Mask: 0xffff) */ + #define R_DRW_SIZE_SIZEX_Pos (0UL) /*!< SIZEX (Bit 0) */ + #define R_DRW_SIZE_SIZEX_Msk (0xffffUL) /*!< SIZEX (Bitfield-Mask: 0xffff) */ +/* ========================================================= PITCH ========================================================= */ + #define R_DRW_PITCH_SSD_Pos (16UL) /*!< SSD (Bit 16) */ + #define R_DRW_PITCH_SSD_Msk (0xffff0000UL) /*!< SSD (Bitfield-Mask: 0xffff) */ + #define R_DRW_PITCH_PITCH_Pos (0UL) /*!< PITCH (Bit 0) */ + #define R_DRW_PITCH_PITCH_Msk (0xffffUL) /*!< PITCH (Bitfield-Mask: 0xffff) */ +/* ======================================================== ORIGIN ========================================================= */ + #define R_DRW_ORIGIN_ORIGIN_Pos (0UL) /*!< ORIGIN (Bit 0) */ + #define R_DRW_ORIGIN_ORIGIN_Msk (0xffffffffUL) /*!< ORIGIN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== DLISTSTART ======================================================= */ + #define R_DRW_DLISTSTART_DLISTSTART_Pos (0UL) /*!< DLISTSTART (Bit 0) */ + #define R_DRW_DLISTSTART_DLISTSTART_Msk (0xffffffffUL) /*!< DLISTSTART (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PERFTRIGGER ====================================================== */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER2_Pos (16UL) /*!< PERFTRIGGER2 (Bit 16) */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER2_Msk (0xffff0000UL) /*!< PERFTRIGGER2 (Bitfield-Mask: 0xffff) */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER1_Pos (0UL) /*!< PERFTRIGGER1 (Bit 0) */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER1_Msk (0xffffUL) /*!< PERFTRIGGER1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== PERFCOUNT1 ======================================================= */ + #define R_DRW_PERFCOUNT1_PERFCOUNT_Pos (0UL) /*!< PERFCOUNT (Bit 0) */ + #define R_DRW_PERFCOUNT1_PERFCOUNT_Msk (0xffffffffUL) /*!< PERFCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PERFCOUNT2 ======================================================= */ + #define R_DRW_PERFCOUNT2_PERFCOUNT_Pos (0UL) /*!< PERFCOUNT (Bit 0) */ + #define R_DRW_PERFCOUNT2_PERFCOUNT_Msk (0xffffffffUL) /*!< PERFCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DBWER ========================================================= */ + #define R_DRW_DBWER_BWE_Pos (2UL) /*!< BWE (Bit 2) */ + #define R_DRW_DBWER_BWE_Msk (0x4UL) /*!< BWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DTCCR ========================================================= */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCVBR ========================================================= */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ +/* ========================================================= DTCST ========================================================= */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSTS ========================================================= */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ +/* ======================================================= DTCCR_SEC ======================================================= */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTEVR ========================================================= */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELCR ========================================================== */ + #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ + #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARA ======================================================== */ + #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR_Pos (1UL) /*!< ELSEGR (Bit 1) */ + #define R_ELC_ELCSARA_ELSEGR_Msk (0x2UL) /*!< ELSEGR (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARB ======================================================== */ + #define R_ELC_ELCSARB_ELSR_Pos (0UL) /*!< ELSR (Bit 0) */ + #define R_ELC_ELCSARB_ELSR_Msk (0x1UL) /*!< ELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARC ======================================================== */ + #define R_ELC_ELCSARC_ELSR_Pos (0UL) /*!< ELSR (Bit 0) */ + #define R_ELC_ELCSARC_ELSR_Msk (0x1UL) /*!< ELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCPARA ======================================================== */ + #define R_ELC_ELCPARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCPARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCPARA_ELSEGR_Pos (1UL) /*!< ELSEGR (Bit 1) */ + #define R_ELC_ELCPARA_ELSEGR_Msk (0x2UL) /*!< ELSEGR (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCPARB ======================================================== */ + #define R_ELC_ELCPARB_ELSR_Pos (0UL) /*!< ELSR (Bit 0) */ + #define R_ELC_ELCPARB_ELSR_Msk (0x1UL) /*!< ELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCPARC ======================================================== */ + #define R_ELC_ELCPARC_ELSR_Pos (0UL) /*!< ELSR (Bit 0) */ + #define R_ELC_ELCPARC_ELSR_Msk (0x1UL) /*!< ELSR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EDMAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= EDMR ========================================================== */ + #define R_ETHERC_EDMAC_EDMR_DE_Pos (6UL) /*!< DE (Bit 6) */ + #define R_ETHERC_EDMAC_EDMR_DE_Msk (0x40UL) /*!< DE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EDMR_DL_Pos (4UL) /*!< DL (Bit 4) */ + #define R_ETHERC_EDMAC_EDMR_DL_Msk (0x30UL) /*!< DL (Bitfield-Mask: 0x03) */ + #define R_ETHERC_EDMAC_EDMR_SWR_Pos (0UL) /*!< SWR (Bit 0) */ + #define R_ETHERC_EDMAC_EDMR_SWR_Msk (0x1UL) /*!< SWR (Bitfield-Mask: 0x01) */ +/* ========================================================= EDTRR ========================================================= */ + #define R_ETHERC_EDMAC_EDTRR_TR_Pos (0UL) /*!< TR (Bit 0) */ + #define R_ETHERC_EDMAC_EDTRR_TR_Msk (0x1UL) /*!< TR (Bitfield-Mask: 0x01) */ +/* ========================================================= EDRRR ========================================================= */ + #define R_ETHERC_EDMAC_EDRRR_RR_Pos (0UL) /*!< RR (Bit 0) */ + #define R_ETHERC_EDMAC_EDRRR_RR_Msk (0x1UL) /*!< RR (Bitfield-Mask: 0x01) */ +/* ========================================================= TDLAR ========================================================= */ + #define R_ETHERC_EDMAC_TDLAR_TDLAR_Pos (0UL) /*!< TDLAR (Bit 0) */ + #define R_ETHERC_EDMAC_TDLAR_TDLAR_Msk (0xffffffffUL) /*!< TDLAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RDLAR ========================================================= */ + #define R_ETHERC_EDMAC_RDLAR_RDLAR_Pos (0UL) /*!< RDLAR (Bit 0) */ + #define R_ETHERC_EDMAC_RDLAR_RDLAR_Msk (0xffffffffUL) /*!< RDLAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= EESR ========================================================== */ + #define R_ETHERC_EDMAC_EESR_TWB_Pos (30UL) /*!< TWB (Bit 30) */ + #define R_ETHERC_EDMAC_EESR_TWB_Msk (0x40000000UL) /*!< TWB (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TABT_Pos (26UL) /*!< TABT (Bit 26) */ + #define R_ETHERC_EDMAC_EESR_TABT_Msk (0x4000000UL) /*!< TABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RABT_Pos (25UL) /*!< RABT (Bit 25) */ + #define R_ETHERC_EDMAC_EESR_RABT_Msk (0x2000000UL) /*!< RABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RFCOF_Pos (24UL) /*!< RFCOF (Bit 24) */ + #define R_ETHERC_EDMAC_EESR_RFCOF_Msk (0x1000000UL) /*!< RFCOF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_ADE_Pos (23UL) /*!< ADE (Bit 23) */ + #define R_ETHERC_EDMAC_EESR_ADE_Msk (0x800000UL) /*!< ADE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_ECI_Pos (22UL) /*!< ECI (Bit 22) */ + #define R_ETHERC_EDMAC_EESR_ECI_Msk (0x400000UL) /*!< ECI (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TC_Pos (21UL) /*!< TC (Bit 21) */ + #define R_ETHERC_EDMAC_EESR_TC_Msk (0x200000UL) /*!< TC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TDE_Pos (20UL) /*!< TDE (Bit 20) */ + #define R_ETHERC_EDMAC_EESR_TDE_Msk (0x100000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TFUF_Pos (19UL) /*!< TFUF (Bit 19) */ + #define R_ETHERC_EDMAC_EESR_TFUF_Msk (0x80000UL) /*!< TFUF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_FR_Pos (18UL) /*!< FR (Bit 18) */ + #define R_ETHERC_EDMAC_EESR_FR_Msk (0x40000UL) /*!< FR (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RDE_Pos (17UL) /*!< RDE (Bit 17) */ + #define R_ETHERC_EDMAC_EESR_RDE_Msk (0x20000UL) /*!< RDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RFOF_Pos (16UL) /*!< RFOF (Bit 16) */ + #define R_ETHERC_EDMAC_EESR_RFOF_Msk (0x10000UL) /*!< RFOF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CND_Pos (11UL) /*!< CND (Bit 11) */ + #define R_ETHERC_EDMAC_EESR_CND_Msk (0x800UL) /*!< CND (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_DLC_Pos (10UL) /*!< DLC (Bit 10) */ + #define R_ETHERC_EDMAC_EESR_DLC_Msk (0x400UL) /*!< DLC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CD_Pos (9UL) /*!< CD (Bit 9) */ + #define R_ETHERC_EDMAC_EESR_CD_Msk (0x200UL) /*!< CD (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TRO_Pos (8UL) /*!< TRO (Bit 8) */ + #define R_ETHERC_EDMAC_EESR_TRO_Msk (0x100UL) /*!< TRO (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RMAF_Pos (7UL) /*!< RMAF (Bit 7) */ + #define R_ETHERC_EDMAC_EESR_RMAF_Msk (0x80UL) /*!< RMAF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RRF_Pos (4UL) /*!< RRF (Bit 4) */ + #define R_ETHERC_EDMAC_EESR_RRF_Msk (0x10UL) /*!< RRF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RTLF_Pos (3UL) /*!< RTLF (Bit 3) */ + #define R_ETHERC_EDMAC_EESR_RTLF_Msk (0x8UL) /*!< RTLF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RTSF_Pos (2UL) /*!< RTSF (Bit 2) */ + #define R_ETHERC_EDMAC_EESR_RTSF_Msk (0x4UL) /*!< RTSF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_PRE_Pos (1UL) /*!< PRE (Bit 1) */ + #define R_ETHERC_EDMAC_EESR_PRE_Msk (0x2UL) /*!< PRE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CERF_Pos (0UL) /*!< CERF (Bit 0) */ + #define R_ETHERC_EDMAC_EESR_CERF_Msk (0x1UL) /*!< CERF (Bitfield-Mask: 0x01) */ +/* ======================================================== EESIPR ========================================================= */ + #define R_ETHERC_EDMAC_EESIPR_TWBIP_Pos (30UL) /*!< TWBIP (Bit 30) */ + #define R_ETHERC_EDMAC_EESIPR_TWBIP_Msk (0x40000000UL) /*!< TWBIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TABTIP_Pos (26UL) /*!< TABTIP (Bit 26) */ + #define R_ETHERC_EDMAC_EESIPR_TABTIP_Msk (0x4000000UL) /*!< TABTIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RABTIP_Pos (25UL) /*!< RABTIP (Bit 25) */ + #define R_ETHERC_EDMAC_EESIPR_RABTIP_Msk (0x2000000UL) /*!< RABTIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Pos (24UL) /*!< RFCOFIP (Bit 24) */ + #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Msk (0x1000000UL) /*!< RFCOFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_ADEIP_Pos (23UL) /*!< ADEIP (Bit 23) */ + #define R_ETHERC_EDMAC_EESIPR_ADEIP_Msk (0x800000UL) /*!< ADEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_ECIIP_Pos (22UL) /*!< ECIIP (Bit 22) */ + #define R_ETHERC_EDMAC_EESIPR_ECIIP_Msk (0x400000UL) /*!< ECIIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TCIP_Pos (21UL) /*!< TCIP (Bit 21) */ + #define R_ETHERC_EDMAC_EESIPR_TCIP_Msk (0x200000UL) /*!< TCIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TDEIP_Pos (20UL) /*!< TDEIP (Bit 20) */ + #define R_ETHERC_EDMAC_EESIPR_TDEIP_Msk (0x100000UL) /*!< TDEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Pos (19UL) /*!< TFUFIP (Bit 19) */ + #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Msk (0x80000UL) /*!< TFUFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_FRIP_Pos (18UL) /*!< FRIP (Bit 18) */ + #define R_ETHERC_EDMAC_EESIPR_FRIP_Msk (0x40000UL) /*!< FRIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RDEIP_Pos (17UL) /*!< RDEIP (Bit 17) */ + #define R_ETHERC_EDMAC_EESIPR_RDEIP_Msk (0x20000UL) /*!< RDEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Pos (16UL) /*!< RFOFIP (Bit 16) */ + #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Msk (0x10000UL) /*!< RFOFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CNDIP_Pos (11UL) /*!< CNDIP (Bit 11) */ + #define R_ETHERC_EDMAC_EESIPR_CNDIP_Msk (0x800UL) /*!< CNDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_DLCIP_Pos (10UL) /*!< DLCIP (Bit 10) */ + #define R_ETHERC_EDMAC_EESIPR_DLCIP_Msk (0x400UL) /*!< DLCIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CDIP_Pos (9UL) /*!< CDIP (Bit 9) */ + #define R_ETHERC_EDMAC_EESIPR_CDIP_Msk (0x200UL) /*!< CDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TROIP_Pos (8UL) /*!< TROIP (Bit 8) */ + #define R_ETHERC_EDMAC_EESIPR_TROIP_Msk (0x100UL) /*!< TROIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Pos (7UL) /*!< RMAFIP (Bit 7) */ + #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Msk (0x80UL) /*!< RMAFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RRFIP_Pos (4UL) /*!< RRFIP (Bit 4) */ + #define R_ETHERC_EDMAC_EESIPR_RRFIP_Msk (0x10UL) /*!< RRFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Pos (3UL) /*!< RTLFIP (Bit 3) */ + #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Msk (0x8UL) /*!< RTLFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Pos (2UL) /*!< RTSFIP (Bit 2) */ + #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Msk (0x4UL) /*!< RTSFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_PREIP_Pos (1UL) /*!< PREIP (Bit 1) */ + #define R_ETHERC_EDMAC_EESIPR_PREIP_Msk (0x2UL) /*!< PREIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CERFIP_Pos (0UL) /*!< CERFIP (Bit 0) */ + #define R_ETHERC_EDMAC_EESIPR_CERFIP_Msk (0x1UL) /*!< CERFIP (Bitfield-Mask: 0x01) */ +/* ======================================================== TRSCER ========================================================= */ + #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Pos (7UL) /*!< RMAFCE (Bit 7) */ + #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Msk (0x80UL) /*!< RMAFCE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_TRSCER_RRFCE_Pos (4UL) /*!< RRFCE (Bit 4) */ + #define R_ETHERC_EDMAC_TRSCER_RRFCE_Msk (0x10UL) /*!< RRFCE (Bitfield-Mask: 0x01) */ +/* ========================================================= RMFCR ========================================================= */ + #define R_ETHERC_EDMAC_RMFCR_MFC_Pos (0UL) /*!< MFC (Bit 0) */ + #define R_ETHERC_EDMAC_RMFCR_MFC_Msk (0xffffUL) /*!< MFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= TFTR ========================================================== */ + #define R_ETHERC_EDMAC_TFTR_TFT_Pos (0UL) /*!< TFT (Bit 0) */ + #define R_ETHERC_EDMAC_TFTR_TFT_Msk (0x7ffUL) /*!< TFT (Bitfield-Mask: 0x7ff) */ +/* ========================================================== FDR ========================================================== */ + #define R_ETHERC_EDMAC_FDR_TFD_Pos (8UL) /*!< TFD (Bit 8) */ + #define R_ETHERC_EDMAC_FDR_TFD_Msk (0x1f00UL) /*!< TFD (Bitfield-Mask: 0x1f) */ + #define R_ETHERC_EDMAC_FDR_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHERC_EDMAC_FDR_RFD_Msk (0x1fUL) /*!< RFD (Bitfield-Mask: 0x1f) */ +/* ========================================================= RMCR ========================================================== */ + #define R_ETHERC_EDMAC_RMCR_RNR_Pos (0UL) /*!< RNR (Bit 0) */ + #define R_ETHERC_EDMAC_RMCR_RNR_Msk (0x1UL) /*!< RNR (Bitfield-Mask: 0x01) */ +/* ========================================================= TFUCR ========================================================= */ + #define R_ETHERC_EDMAC_TFUCR_UNDER_Pos (0UL) /*!< UNDER (Bit 0) */ + #define R_ETHERC_EDMAC_TFUCR_UNDER_Msk (0xffffUL) /*!< UNDER (Bitfield-Mask: 0xffff) */ +/* ========================================================= RFOCR ========================================================= */ + #define R_ETHERC_EDMAC_RFOCR_OVER_Pos (0UL) /*!< OVER (Bit 0) */ + #define R_ETHERC_EDMAC_RFOCR_OVER_Msk (0xffffUL) /*!< OVER (Bitfield-Mask: 0xffff) */ +/* ========================================================= IOSR ========================================================== */ + #define R_ETHERC_EDMAC_IOSR_ELB_Pos (0UL) /*!< ELB (Bit 0) */ + #define R_ETHERC_EDMAC_IOSR_ELB_Msk (0x1UL) /*!< ELB (Bitfield-Mask: 0x01) */ +/* ========================================================= FCFTR ========================================================= */ + #define R_ETHERC_EDMAC_FCFTR_RFFO_Pos (16UL) /*!< RFFO (Bit 16) */ + #define R_ETHERC_EDMAC_FCFTR_RFFO_Msk (0x70000UL) /*!< RFFO (Bitfield-Mask: 0x07) */ + #define R_ETHERC_EDMAC_FCFTR_RFDO_Pos (0UL) /*!< RFDO (Bit 0) */ + #define R_ETHERC_EDMAC_FCFTR_RFDO_Msk (0x7UL) /*!< RFDO (Bitfield-Mask: 0x07) */ +/* ======================================================== RPADIR ========================================================= */ + #define R_ETHERC_EDMAC_RPADIR_PADS_Pos (16UL) /*!< PADS (Bit 16) */ + #define R_ETHERC_EDMAC_RPADIR_PADS_Msk (0x30000UL) /*!< PADS (Bitfield-Mask: 0x03) */ + #define R_ETHERC_EDMAC_RPADIR_PADR_Pos (0UL) /*!< PADR (Bit 0) */ + #define R_ETHERC_EDMAC_RPADIR_PADR_Msk (0x3fUL) /*!< PADR (Bitfield-Mask: 0x3f) */ +/* ========================================================= TRIMD ========================================================= */ + #define R_ETHERC_EDMAC_TRIMD_TIM_Pos (4UL) /*!< TIM (Bit 4) */ + #define R_ETHERC_EDMAC_TRIMD_TIM_Msk (0x10UL) /*!< TIM (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_TRIMD_TIS_Pos (0UL) /*!< TIS (Bit 0) */ + #define R_ETHERC_EDMAC_TRIMD_TIS_Msk (0x1UL) /*!< TIS (Bitfield-Mask: 0x01) */ +/* ========================================================= RBWAR ========================================================= */ + #define R_ETHERC_EDMAC_RBWAR_RBWAR_Pos (0UL) /*!< RBWAR (Bit 0) */ + #define R_ETHERC_EDMAC_RBWAR_RBWAR_Msk (0xffffffffUL) /*!< RBWAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RDFAR ========================================================= */ + #define R_ETHERC_EDMAC_RDFAR_RDFAR_Pos (0UL) /*!< RDFAR (Bit 0) */ + #define R_ETHERC_EDMAC_RDFAR_RDFAR_Msk (0xffffffffUL) /*!< RDFAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TBRAR ========================================================= */ + #define R_ETHERC_EDMAC_TBRAR_TBRAR_Pos (0UL) /*!< TBRAR (Bit 0) */ + #define R_ETHERC_EDMAC_TBRAR_TBRAR_Msk (0xffffffffUL) /*!< TBRAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TDFAR ========================================================= */ + #define R_ETHERC_EDMAC_TDFAR_TDFAR_Pos (0UL) /*!< TDFAR (Bit 0) */ + #define R_ETHERC_EDMAC_TDFAR_TDFAR_Msk (0xffffffffUL) /*!< TDFAR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_GLCDC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= GR1_CLUT0 ======================================================= */ + #define R_GLCDC_GR1_CLUT0_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR1_CLUT0_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT0_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR1_CLUT0_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT0_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR1_CLUT0_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT0_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR1_CLUT0_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ======================================================= GR1_CLUT1 ======================================================= */ + #define R_GLCDC_GR1_CLUT1_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR1_CLUT1_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT1_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR1_CLUT1_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT1_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR1_CLUT1_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT1_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR1_CLUT1_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ======================================================= GR2_CLUT0 ======================================================= */ + #define R_GLCDC_GR2_CLUT0_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR2_CLUT0_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT0_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR2_CLUT0_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT0_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR2_CLUT0_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT0_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR2_CLUT0_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ======================================================= GR2_CLUT1 ======================================================= */ + #define R_GLCDC_GR2_CLUT1_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR2_CLUT1_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT1_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR2_CLUT1_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT1_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR2_CLUT1_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT1_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR2_CLUT1_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ + #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ + #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ + #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ + #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ + #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ + #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ + #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ + #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ + #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ + #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ + #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ + #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ + #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ + #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ + #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ + #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ + #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ + #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ + #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ + #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ + #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ + #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ + #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ + #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ + #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ + #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ + #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ + #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ + #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ + #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ + #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ + #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ + #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ + #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ + #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ + #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ + #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ + #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ + #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ + #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ + #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ + #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ + #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ + #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ + #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ + #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ + #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ + #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ + #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ + #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ + #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ + #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ + #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ + #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ + #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ + #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ + #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ + #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ + #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ + #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ + #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ + #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ + #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ + #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ + #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ + #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ + #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ + #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ + #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ + #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ + #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ + #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ + #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ + #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ + #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ + #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ + #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ + #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ + #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ + #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ + #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ + #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ + #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ + #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT0_GTCR_CKEG_Pos (27UL) /*!< CKEG (Bit 27) */ + #define R_GPT0_GTCR_CKEG_Msk (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ + #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT0_GTCR_MD_Msk (0xf0000UL) /*!< MD (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_SSCEN_Pos (15UL) /*!< SSCEN (Bit 15) */ + #define R_GPT0_GTCR_SSCEN_Msk (0x8000UL) /*!< SSCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_CPSCD_Pos (12UL) /*!< CPSCD (Bit 12) */ + #define R_GPT0_GTCR_CPSCD_Msk (0x1000UL) /*!< CPSCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_SSCGRP_Pos (10UL) /*!< SSCGRP (Bit 10) */ + #define R_GPT0_GTCR_SSCGRP_Msk (0xc00UL) /*!< SSCGRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTCR_SCGTIOC_Pos (9UL) /*!< SCGTIOC (Bit 9) */ + #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ + #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ + #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ + #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ + #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ + #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ + #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_ADTRDEN_Pos (17UL) /*!< ADTRDEN (Bit 17) */ + #define R_GPT0_GTINTAD_ADTRDEN_Msk (0x20000UL) /*!< ADTRDEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_ADTRUEN_Pos (16UL) /*!< ADTRUEN (Bit 16) */ + #define R_GPT0_GTINTAD_ADTRUEN_Msk (0x10000UL) /*!< ADTRUEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCFPU_Pos (15UL) /*!< SCFPU (Bit 15) */ + #define R_GPT0_GTINTAD_SCFPU_Msk (0x8000UL) /*!< SCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCFPO_Pos (14UL) /*!< SCFPO (Bit 14) */ + #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ + #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ + #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ + #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ + #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ + #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ + #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ + #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ + #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ + #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_DBRTEC_Pos (8UL) /*!< DBRTEC (Bit 8) */ + #define R_GPT0_GTBER_DBRTEC_Msk (0x100UL) /*!< DBRTEC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ + #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ + #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTCCR ========================================================= */ + #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ + #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPR ========================================================== */ + #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ + #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPBR ========================================================= */ + #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ + #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTPDBR ========================================================= */ + #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ + #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRA ======================================================== */ + #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ + #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRB ======================================================== */ + #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ + #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRA ======================================================== */ + #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ + #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRB ======================================================== */ + #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ + #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRA ======================================================= */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRB ======================================================= */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ + #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDVD ========================================================= */ + #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ + #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBU ========================================================= */ + #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBD ========================================================= */ + #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ + #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTADSMR ======================================================== */ + #define R_GPT0_GTADSMR_ADSMS0_Pos (0UL) /*!< ADSMS0 (Bit 0) */ + #define R_GPT0_GTADSMR_ADSMS0_Msk (0x3UL) /*!< ADSMS0 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTADSMR_ADSMEN0_Pos (8UL) /*!< ADSMEN0 (Bit 8) */ + #define R_GPT0_GTADSMR_ADSMEN0_Msk (0x100UL) /*!< ADSMEN0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTADSMR_ADSMS1_Pos (16UL) /*!< ADSMS1 (Bit 16) */ + #define R_GPT0_GTADSMR_ADSMS1_Msk (0x30000UL) /*!< ADSMS1 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTADSMR_ADSMEN1_Pos (24UL) /*!< ADSMEN1 (Bit 24) */ + #define R_GPT0_GTADSMR_ADSMEN1_Msk (0x1000000UL) /*!< ADSMEN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTEITC ========================================================= */ + #define R_GPT0_GTEITC_EIVTC1_Pos (0UL) /*!< EIVTC1 (Bit 0) */ + #define R_GPT0_GTEITC_EIVTC1_Msk (0x3UL) /*!< EIVTC1 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTEITC_EIVTT1_Pos (4UL) /*!< EIVTT1 (Bit 4) */ + #define R_GPT0_GTEITC_EIVTT1_Msk (0xf0UL) /*!< EIVTT1 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT1_Pos (12UL) /*!< EITCNT1 (Bit 12) */ + #define R_GPT0_GTEITC_EITCNT1_Msk (0xf000UL) /*!< EITCNT1 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EIVTC2_Pos (16UL) /*!< EIVTC2 (Bit 16) */ + #define R_GPT0_GTEITC_EIVTC2_Msk (0x30000UL) /*!< EIVTC2 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTEITC_EIVTT2_Pos (20UL) /*!< EIVTT2 (Bit 20) */ + #define R_GPT0_GTEITC_EIVTT2_Msk (0xf00000UL) /*!< EIVTT2 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT2IV_Pos (24UL) /*!< EITCNT2IV (Bit 24) */ + #define R_GPT0_GTEITC_EITCNT2IV_Msk (0xf000000UL) /*!< EITCNT2IV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT2_Pos (28UL) /*!< EITCNT2 (Bit 28) */ + #define R_GPT0_GTEITC_EITCNT2_Msk (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f) */ +/* ======================================================= GTEITLI1 ======================================================== */ + #define R_GPT0_GTEITLI1_EITLA_Pos (0UL) /*!< EITLA (Bit 0) */ + #define R_GPT0_GTEITLI1_EITLA_Msk (0x7UL) /*!< EITLA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLB_Pos (4UL) /*!< EITLB (Bit 4) */ + #define R_GPT0_GTEITLI1_EITLB_Msk (0x70UL) /*!< EITLB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLC_Pos (8UL) /*!< EITLC (Bit 8) */ + #define R_GPT0_GTEITLI1_EITLC_Msk (0x700UL) /*!< EITLC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLD_Pos (12UL) /*!< EITLD (Bit 12) */ + #define R_GPT0_GTEITLI1_EITLD_Msk (0x7000UL) /*!< EITLD (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLE_Pos (16UL) /*!< EITLE (Bit 16) */ + #define R_GPT0_GTEITLI1_EITLE_Msk (0x70000UL) /*!< EITLE (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLF_Pos (20UL) /*!< EITLF (Bit 20) */ + #define R_GPT0_GTEITLI1_EITLF_Msk (0x700000UL) /*!< EITLF (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLV_Pos (24UL) /*!< EITLV (Bit 24) */ + #define R_GPT0_GTEITLI1_EITLV_Msk (0x7000000UL) /*!< EITLV (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLU_Pos (28UL) /*!< EITLU (Bit 28) */ + #define R_GPT0_GTEITLI1_EITLU_Msk (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07) */ +/* ======================================================= GTEITLI2 ======================================================== */ + #define R_GPT0_GTEITLI2_EADTAL_Pos (0UL) /*!< EADTAL (Bit 0) */ + #define R_GPT0_GTEITLI2_EADTAL_Msk (0x7UL) /*!< EADTAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI2_EADTBL_Pos (4UL) /*!< EADTBL (Bit 4) */ + #define R_GPT0_GTEITLI2_EADTBL_Msk (0x70UL) /*!< EADTBL (Bitfield-Mask: 0x07) */ +/* ======================================================== GTEITLB ======================================================== */ + #define R_GPT0_GTEITLB_EBTLCA_Pos (0UL) /*!< EBTLCA (Bit 0) */ + #define R_GPT0_GTEITLB_EBTLCA_Msk (0x7UL) /*!< EBTLCA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLCB_Pos (4UL) /*!< EBTLCB (Bit 4) */ + #define R_GPT0_GTEITLB_EBTLCB_Msk (0x70UL) /*!< EBTLCB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLPR_Pos (8UL) /*!< EBTLPR (Bit 8) */ + #define R_GPT0_GTEITLB_EBTLPR_Msk (0x700UL) /*!< EBTLPR (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLADA_Pos (16UL) /*!< EBTLADA (Bit 16) */ + #define R_GPT0_GTEITLB_EBTLADA_Msk (0x70000UL) /*!< EBTLADA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLADB_Pos (20UL) /*!< EBTLADB (Bit 20) */ + #define R_GPT0_GTEITLB_EBTLADB_Msk (0x700000UL) /*!< EBTLADB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLDVU_Pos (24UL) /*!< EBTLDVU (Bit 24) */ + #define R_GPT0_GTEITLB_EBTLDVU_Msk (0x7000000UL) /*!< EBTLDVU (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLDVD_Pos (28UL) /*!< EBTLDVD (Bit 28) */ + #define R_GPT0_GTEITLB_EBTLDVD_Msk (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07) */ +/* ======================================================== GTICLF ========================================================= */ + #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ + #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ + #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ + #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ + #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ + #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ +/* ========================================================= GTPC ========================================================== */ + #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ + #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ + #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ + #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ + #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ + #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ + #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDAE_Pos (2UL) /*!< SBDAE (Bit 2) */ + #define R_GPT0_GTSECR_SBDAE_Msk (0x4UL) /*!< SBDAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDDE_Pos (3UL) /*!< SBDDE (Bit 3) */ + #define R_GPT0_GTSECR_SBDDE_Msk (0x8UL) /*!< SBDDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDAD_Pos (10UL) /*!< SBDAD (Bit 10) */ + #define R_GPT0_GTSECR_SBDAD_Msk (0x400UL) /*!< SBDAD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDDD_Pos (11UL) /*!< SBDDD (Bit 11) */ + #define R_GPT0_GTSECR_SBDDD_Msk (0x800UL) /*!< SBDDD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ + #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SSCE_Pos (17UL) /*!< SSCE (Bit 17) */ + #define R_GPT0_GTSECR_SSCE_Msk (0x20000UL) /*!< SSCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ + #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SSCD_Pos (25UL) /*!< SSCD (Bit 25) */ + #define R_GPT0_GTSECR_SSCD_Msk (0x2000000UL) /*!< SSCD (Bitfield-Mask: 0x01) */ +/* ======================================================== GTBER2 ========================================================= */ + #define R_GPT0_GTBER2_CCTCA_Pos (0UL) /*!< CCTCA (Bit 0) */ + #define R_GPT0_GTBER2_CCTCA_Msk (0x1UL) /*!< CCTCA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTCB_Pos (1UL) /*!< CCTCB (Bit 1) */ + #define R_GPT0_GTBER2_CCTCB_Msk (0x2UL) /*!< CCTCB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTPR_Pos (2UL) /*!< CCTPR (Bit 2) */ + #define R_GPT0_GTBER2_CCTPR_Msk (0x4UL) /*!< CCTPR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTADA_Pos (3UL) /*!< CCTADA (Bit 3) */ + #define R_GPT0_GTBER2_CCTADA_Msk (0x8UL) /*!< CCTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTADB_Pos (4UL) /*!< CCTADB (Bit 4) */ + #define R_GPT0_GTBER2_CCTADB_Msk (0x10UL) /*!< CCTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTDV_Pos (5UL) /*!< CCTDV (Bit 5) */ + #define R_GPT0_GTBER2_CCTDV_Msk (0x20UL) /*!< CCTDV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CMTCA_Pos (8UL) /*!< CMTCA (Bit 8) */ + #define R_GPT0_GTBER2_CMTCA_Msk (0x300UL) /*!< CMTCA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_CMTCB_Pos (10UL) /*!< CMTCB (Bit 10) */ + #define R_GPT0_GTBER2_CMTCB_Msk (0xc00UL) /*!< CMTCB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_CMTADA_Pos (13UL) /*!< CMTADA (Bit 13) */ + #define R_GPT0_GTBER2_CMTADA_Msk (0x2000UL) /*!< CMTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CMTADB_Pos (14UL) /*!< CMTADB (Bit 14) */ + #define R_GPT0_GTBER2_CMTADB_Msk (0x4000UL) /*!< CMTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTCA_Pos (16UL) /*!< CPTCA (Bit 16) */ + #define R_GPT0_GTBER2_CPTCA_Msk (0x10000UL) /*!< CPTCA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTCB_Pos (17UL) /*!< CPTCB (Bit 17) */ + #define R_GPT0_GTBER2_CPTCB_Msk (0x20000UL) /*!< CPTCB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTPR_Pos (18UL) /*!< CPTPR (Bit 18) */ + #define R_GPT0_GTBER2_CPTPR_Msk (0x40000UL) /*!< CPTPR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTADA_Pos (19UL) /*!< CPTADA (Bit 19) */ + #define R_GPT0_GTBER2_CPTADA_Msk (0x80000UL) /*!< CPTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTADB_Pos (20UL) /*!< CPTADB (Bit 20) */ + #define R_GPT0_GTBER2_CPTADB_Msk (0x100000UL) /*!< CPTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTDV_Pos (21UL) /*!< CPTDV (Bit 21) */ + #define R_GPT0_GTBER2_CPTDV_Msk (0x200000UL) /*!< CPTDV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CP3DB_Pos (24UL) /*!< CP3DB (Bit 24) */ + #define R_GPT0_GTBER2_CP3DB_Msk (0x1000000UL) /*!< CP3DB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPBTD_Pos (25UL) /*!< CPBTD (Bit 25) */ + #define R_GPT0_GTBER2_CPBTD_Msk (0x2000000UL) /*!< CPBTD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_OLTTA_Pos (26UL) /*!< OLTTA (Bit 26) */ + #define R_GPT0_GTBER2_OLTTA_Msk (0xc000000UL) /*!< OLTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_OLTTB_Pos (28UL) /*!< OLTTB (Bit 28) */ + #define R_GPT0_GTBER2_OLTTB_Msk (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03) */ +/* ======================================================== GTOLBR ========================================================= */ + #define R_GPT0_GTOLBR_GTIOAB_Pos (0UL) /*!< GTIOAB (Bit 0) */ + #define R_GPT0_GTOLBR_GTIOAB_Msk (0x1fUL) /*!< GTIOAB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTOLBR_GTIOBB_Pos (16UL) /*!< GTIOBB (Bit 16) */ + #define R_GPT0_GTOLBR_GTIOBB_Msk (0x1f0000UL) /*!< GTIOBB (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTICCR ========================================================= */ + #define R_GPT0_GTICCR_ICAFA_Pos (0UL) /*!< ICAFA (Bit 0) */ + #define R_GPT0_GTICCR_ICAFA_Msk (0x1UL) /*!< ICAFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFB_Pos (1UL) /*!< ICAFB (Bit 1) */ + #define R_GPT0_GTICCR_ICAFB_Msk (0x2UL) /*!< ICAFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFC_Pos (2UL) /*!< ICAFC (Bit 2) */ + #define R_GPT0_GTICCR_ICAFC_Msk (0x4UL) /*!< ICAFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFD_Pos (3UL) /*!< ICAFD (Bit 3) */ + #define R_GPT0_GTICCR_ICAFD_Msk (0x8UL) /*!< ICAFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFE_Pos (4UL) /*!< ICAFE (Bit 4) */ + #define R_GPT0_GTICCR_ICAFE_Msk (0x10UL) /*!< ICAFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFF_Pos (5UL) /*!< ICAFF (Bit 5) */ + #define R_GPT0_GTICCR_ICAFF_Msk (0x20UL) /*!< ICAFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFPO_Pos (6UL) /*!< ICAFPO (Bit 6) */ + #define R_GPT0_GTICCR_ICAFPO_Msk (0x40UL) /*!< ICAFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFPU_Pos (7UL) /*!< ICAFPU (Bit 7) */ + #define R_GPT0_GTICCR_ICAFPU_Msk (0x80UL) /*!< ICAFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICACLK_Pos (8UL) /*!< ICACLK (Bit 8) */ + #define R_GPT0_GTICCR_ICACLK_Msk (0x100UL) /*!< ICACLK (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAGRP_Pos (14UL) /*!< ICAGRP (Bit 14) */ + #define R_GPT0_GTICCR_ICAGRP_Msk (0xc000UL) /*!< ICAGRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTICCR_ICBFA_Pos (16UL) /*!< ICBFA (Bit 16) */ + #define R_GPT0_GTICCR_ICBFA_Msk (0x10000UL) /*!< ICBFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFB_Pos (17UL) /*!< ICBFB (Bit 17) */ + #define R_GPT0_GTICCR_ICBFB_Msk (0x20000UL) /*!< ICBFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFC_Pos (18UL) /*!< ICBFC (Bit 18) */ + #define R_GPT0_GTICCR_ICBFC_Msk (0x40000UL) /*!< ICBFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFD_Pos (19UL) /*!< ICBFD (Bit 19) */ + #define R_GPT0_GTICCR_ICBFD_Msk (0x80000UL) /*!< ICBFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFE_Pos (20UL) /*!< ICBFE (Bit 20) */ + #define R_GPT0_GTICCR_ICBFE_Msk (0x100000UL) /*!< ICBFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFF_Pos (21UL) /*!< ICBFF (Bit 21) */ + #define R_GPT0_GTICCR_ICBFF_Msk (0x200000UL) /*!< ICBFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFPO_Pos (22UL) /*!< ICBFPO (Bit 22) */ + #define R_GPT0_GTICCR_ICBFPO_Msk (0x400000UL) /*!< ICBFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFPU_Pos (23UL) /*!< ICBFPU (Bit 23) */ + #define R_GPT0_GTICCR_ICBFPU_Msk (0x800000UL) /*!< ICBFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBCLK_Pos (24UL) /*!< ICBCLK (Bit 24) */ + #define R_GPT0_GTICCR_ICBCLK_Msk (0x1000000UL) /*!< ICBCLK (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBGRP_Pos (30UL) /*!< ICBGRP (Bit 30) */ + #define R_GPT0_GTICCR_ICBGRP_Msk (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_GTCLK ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== GTCLKCR ======================================================== */ + #define R_GPT_GTCLK_GTCLKCR_BPEN_Pos (0UL) /*!< BPEN (Bit 0) */ + #define R_GPT_GTCLK_GTCLKCR_BPEN_Msk (0x1UL) /*!< BPEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_ODC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= GTDLYCR1 ======================================================== */ + #define R_GPT_ODC_GTDLYCR1_FRANGE_Pos (8UL) /*!< FRANGE (Bit 8) */ + #define R_GPT_ODC_GTDLYCR1_FRANGE_Msk (0x300UL) /*!< FRANGE (Bitfield-Mask: 0x03) */ + #define R_GPT_ODC_GTDLYCR1_DLYRST_Pos (1UL) /*!< DLYRST (Bit 1) */ + #define R_GPT_ODC_GTDLYCR1_DLYRST_Msk (0x2UL) /*!< DLYRST (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR1_DLLEN_Pos (0UL) /*!< DLLEN (Bit 0) */ + #define R_GPT_ODC_GTDLYCR1_DLLEN_Msk (0x1UL) /*!< DLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================= GTDLYCR2 ======================================================== */ + #define R_GPT_ODC_GTDLYCR2_DLYDENB_Pos (12UL) /*!< DLYDENB (Bit 12) */ + #define R_GPT_ODC_GTDLYCR2_DLYDENB_Msk (0x1000UL) /*!< DLYDENB (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR2_DLYEN_Pos (8UL) /*!< DLYEN (Bit 8) */ + #define R_GPT_ODC_GTDLYCR2_DLYEN_Msk (0x100UL) /*!< DLYEN (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR2_DLYBS_Pos (0UL) /*!< DLYBS (Bit 0) */ + #define R_GPT_ODC_GTDLYCR2_DLYBS_Msk (0x1UL) /*!< DLYBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= OPSCR ========================================================= */ + #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */ + #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */ + #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */ + #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */ + #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */ + #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */ + #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */ + #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */ + #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */ + #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */ + #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */ + #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */ + #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */ + #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */ + #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= POEGG ========================================================= */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IRQCRa ========================================================= */ + #define R_ICU_IRQCRa_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCRa_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCRa_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCRa_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCRa_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCRa_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ +/* ========================================================= NMICR ========================================================= */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ +/* ======================================================== IRQCRb ========================================================= */ + #define R_ICU_IRQCRb_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCRb_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCRb_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCRb_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCRb_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCRb_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSELR ======================================================== */ + #define R_ICU_INTSELR_IS_Pos (0UL) /*!< IS (Bit 0) */ + #define R_ICU_INTSELR_IS_Msk (0x1UL) /*!< IS (Bitfield-Mask: 0x01) */ +/* ========================================================= NMIER ========================================================= */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_PVD1EN_Pos (2UL) /*!< PVD1EN (Bit 2) */ + #define R_ICU_NMIER_PVD1EN_Msk (0x4UL) /*!< PVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_PVD2EN_Pos (3UL) /*!< PVD2EN (Bit 3) */ + #define R_ICU_NMIER_PVD2EN_Msk (0x8UL) /*!< PVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_SOSTEN_Pos (5UL) /*!< SOSTEN (Bit 5) */ + #define R_ICU_NMIER_SOSTEN_Msk (0x20UL) /*!< SOSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSEN_Pos (12UL) /*!< BUSEN (Bit 12) */ + #define R_ICU_NMIER_BUSEN_Msk (0x1000UL) /*!< BUSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CMEN_Pos (13UL) /*!< CMEN (Bit 13) */ + #define R_ICU_NMIER_CMEN_Msk (0x2000UL) /*!< CMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LMEN_Pos (14UL) /*!< LMEN (Bit 14) */ + #define R_ICU_NMIER_LMEN_Msk (0x4000UL) /*!< LMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LUEN_Pos (15UL) /*!< LUEN (Bit 15) */ + #define R_ICU_NMIER_LUEN_Msk (0x8000UL) /*!< LUEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_FPUFLTEN_Pos (16UL) /*!< FPUFLTEN (Bit 16) */ + #define R_ICU_NMIER_FPUFLTEN_Msk (0x10000UL) /*!< FPUFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_MRCRDEN_Pos (17UL) /*!< MRCRDEN (Bit 17) */ + #define R_ICU_NMIER_MRCRDEN_Msk (0x20000UL) /*!< MRCRDEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_MRERDEN_Pos (18UL) /*!< MRERDEN (Bit 18) */ + #define R_ICU_NMIER_MRERDEN_Msk (0x40000UL) /*!< MRERDEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IPCEN_Pos (20UL) /*!< IPCEN (Bit 20) */ + #define R_ICU_NMIER_IPCEN_Msk (0x100000UL) /*!< IPCEN (Bitfield-Mask: 0x01) */ +/* ======================================================== NMICLR ========================================================= */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_PVD1CLR_Pos (2UL) /*!< PVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_PVD1CLR_Msk (0x4UL) /*!< PVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_PVD2CLR_Pos (3UL) /*!< PVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_PVD2CLR_Msk (0x8UL) /*!< PVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_SOSTCLR_Pos (5UL) /*!< SOSTCLR (Bit 5) */ + #define R_ICU_NMICLR_SOSTCLR_Msk (0x20UL) /*!< SOSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSCLR_Pos (12UL) /*!< BUSCLR (Bit 12) */ + #define R_ICU_NMICLR_BUSCLR_Msk (0x1000UL) /*!< BUSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CMCLR_Pos (13UL) /*!< CMCLR (Bit 13) */ + #define R_ICU_NMICLR_CMCLR_Msk (0x2000UL) /*!< CMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LMCLR_Pos (14UL) /*!< LMCLR (Bit 14) */ + #define R_ICU_NMICLR_LMCLR_Msk (0x4000UL) /*!< LMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LUCLR_Pos (15UL) /*!< LUCLR (Bit 15) */ + #define R_ICU_NMICLR_LUCLR_Msk (0x8000UL) /*!< LUCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_FPUFLTCLR_Pos (16UL) /*!< FPUFLTCLR (Bit 16) */ + #define R_ICU_NMICLR_FPUFLTCLR_Msk (0x10000UL) /*!< FPUFLTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_MRCRDCLR_Pos (17UL) /*!< MRCRDCLR (Bit 17) */ + #define R_ICU_NMICLR_MRCRDCLR_Msk (0x20000UL) /*!< MRCRDCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_MRERDCLR_Pos (18UL) /*!< MRERDCLR (Bit 18) */ + #define R_ICU_NMICLR_MRERDCLR_Msk (0x40000UL) /*!< MRERDCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IPCCLR_Pos (20UL) /*!< IPCCLR (Bit 20) */ + #define R_ICU_NMICLR_IPCCLR_Msk (0x100000UL) /*!< IPCCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= NMISR ========================================================= */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_PVD1ST_Pos (2UL) /*!< PVD1ST (Bit 2) */ + #define R_ICU_NMISR_PVD1ST_Msk (0x4UL) /*!< PVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_PVD2ST_Pos (3UL) /*!< PVD2ST (Bit 3) */ + #define R_ICU_NMISR_PVD2ST_Msk (0x8UL) /*!< PVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_SOSTST_Pos (5UL) /*!< SOSTST (Bit 5) */ + #define R_ICU_NMISR_SOSTST_Msk (0x20UL) /*!< SOSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSST_Pos (12UL) /*!< BUSST (Bit 12) */ + #define R_ICU_NMISR_BUSST_Msk (0x1000UL) /*!< BUSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CMST_Pos (13UL) /*!< CMST (Bit 13) */ + #define R_ICU_NMISR_CMST_Msk (0x2000UL) /*!< CMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LMST_Pos (14UL) /*!< LMST (Bit 14) */ + #define R_ICU_NMISR_LMST_Msk (0x4000UL) /*!< LMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LUST_Pos (15UL) /*!< LUST (Bit 15) */ + #define R_ICU_NMISR_LUST_Msk (0x8000UL) /*!< LUST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_FPUFLTST_Pos (16UL) /*!< FPUFLTST (Bit 16) */ + #define R_ICU_NMISR_FPUFLTST_Msk (0x10000UL) /*!< FPUFLTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_MRCRDST_Pos (17UL) /*!< MRCRDST (Bit 17) */ + #define R_ICU_NMISR_MRCRDST_Msk (0x20000UL) /*!< MRCRDST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_MRERDST_Pos (18UL) /*!< MRERDST (Bit 18) */ + #define R_ICU_NMISR_MRERDST_Msk (0x40000UL) /*!< MRERDST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IPCST_Pos (20UL) /*!< IPCST (Bit 20) */ + #define R_ICU_NMISR_IPCST_Msk (0x100000UL) /*!< IPCST (Bitfield-Mask: 0x01) */ +/* ========================================================= WUPEN ========================================================= */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_WUPEN_Pos (16UL) /*!< WUPEN (Bit 16) */ + #define R_ICU_WUPEN_WUPEN_Msk (0x10000UL) /*!< WUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN1 ========================================================= */ + #define R_ICU_WUPEN1_WUPEN_Pos (0UL) /*!< WUPEN (Bit 0) */ + #define R_ICU_WUPEN1_WUPEN_Msk (0x1UL) /*!< WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_IRQWUPEN_Pos (16UL) /*!< IRQWUPEN (Bit 16) */ + #define R_ICU_WUPEN1_IRQWUPEN_Msk (0x10000UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ +/* ===================================================== DSLPWUPIRQEN ====================================================== */ + #define R_ICU_DSLPWUPIRQEN_IRQ_Pos (0UL) /*!< IRQ (Bit 0) */ + #define R_ICU_DSLPWUPIRQEN_IRQ_Msk (0x1UL) /*!< IRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= DELSR ========================================================= */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x3ffUL) /*!< DELS (Bitfield-Mask: 0x3ff) */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ +/* ========================================================= IELSR ========================================================= */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x3ffUL) /*!< IELS (Bitfield-Mask: 0x3ff) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ + #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ + #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ + #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ +/* ========================================================= ICDRR ========================================================= */ + #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ + #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ +/* ========================================================= ICWUR ========================================================= */ + #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ + #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ + #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ + #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ + #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ + #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICWUR2 ========================================================= */ + #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ + #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ + #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ + #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IWDTRR ========================================================= */ + #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ + #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ +/* ======================================================== IWDTCR ========================================================= */ + #define R_IWDT_IWDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_IWDT_IWDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_IWDT_IWDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_IWDT_IWDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_IWDT_IWDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IWDT_IWDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_IWDT_IWDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_IWDT_IWDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ======================================================== IWDTSR ========================================================= */ + #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== IWDTRCR ======================================================== */ + #define R_IWDT_IWDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_IWDT_IWDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= IWDTCSTPR ======================================================= */ + #define R_IWDT_IWDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_IWDT_IWDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_I3C0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PRTS ========================================================== */ + #define R_I3C0_PRTS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */ + #define R_I3C0_PRTS_PRTMD_Msk (0x1UL) /*!< PRTMD (Bitfield-Mask: 0x01) */ +/* ========================================================= CECTL ========================================================= */ + #define R_I3C0_CECTL_CLKE_Pos (0UL) /*!< CLKE (Bit 0) */ + #define R_I3C0_CECTL_CLKE_Msk (0x1UL) /*!< CLKE (Bitfield-Mask: 0x01) */ +/* ========================================================= BCTL ========================================================== */ + #define R_I3C0_BCTL_INCBA_Pos (0UL) /*!< INCBA (Bit 0) */ + #define R_I3C0_BCTL_INCBA_Msk (0x1UL) /*!< INCBA (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_BMDS_Pos (7UL) /*!< BMDS (Bit 7) */ + #define R_I3C0_BCTL_BMDS_Msk (0x80UL) /*!< BMDS (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_HJACKCTL_Pos (8UL) /*!< HJACKCTL (Bit 8) */ + #define R_I3C0_BCTL_HJACKCTL_Msk (0x100UL) /*!< HJACKCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_ABT_Pos (29UL) /*!< ABT (Bit 29) */ + #define R_I3C0_BCTL_ABT_Msk (0x20000000UL) /*!< ABT (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_RSM_Pos (30UL) /*!< RSM (Bit 30) */ + #define R_I3C0_BCTL_RSM_Msk (0x40000000UL) /*!< RSM (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_BUSE_Pos (31UL) /*!< BUSE (Bit 31) */ + #define R_I3C0_BCTL_BUSE_Msk (0x80000000UL) /*!< BUSE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSDVAD ========================================================= */ + #define R_I3C0_MSDVAD_MDYAD_Pos (16UL) /*!< MDYAD (Bit 16) */ + #define R_I3C0_MSDVAD_MDYAD_Msk (0x7f0000UL) /*!< MDYAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_MSDVAD_MDYADV_Pos (31UL) /*!< MDYADV (Bit 31) */ + #define R_I3C0_MSDVAD_MDYADV_Msk (0x80000000UL) /*!< MDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTCTL ========================================================= */ + #define R_I3C0_RSTCTL_RI3CRST_Pos (0UL) /*!< RI3CRST (Bit 0) */ + #define R_I3C0_RSTCTL_RI3CRST_Msk (0x1UL) /*!< RI3CRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_CMDQRST_Pos (1UL) /*!< CMDQRST (Bit 1) */ + #define R_I3C0_RSTCTL_CMDQRST_Msk (0x2UL) /*!< CMDQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RSPQRST_Pos (2UL) /*!< RSPQRST (Bit 2) */ + #define R_I3C0_RSTCTL_RSPQRST_Msk (0x4UL) /*!< RSPQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_TDBRST_Pos (3UL) /*!< TDBRST (Bit 3) */ + #define R_I3C0_RSTCTL_TDBRST_Msk (0x8UL) /*!< TDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RDBRST_Pos (4UL) /*!< RDBRST (Bit 4) */ + #define R_I3C0_RSTCTL_RDBRST_Msk (0x10UL) /*!< RDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_IBIQRST_Pos (5UL) /*!< IBIQRST (Bit 5) */ + #define R_I3C0_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */ + #define R_I3C0_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HCMDQRST_Pos (9UL) /*!< HCMDQRST (Bit 9) */ + #define R_I3C0_RSTCTL_HCMDQRST_Msk (0x200UL) /*!< HCMDQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRSPQRST_Pos (10UL) /*!< HRSPQRST (Bit 10) */ + #define R_I3C0_RSTCTL_HRSPQRST_Msk (0x400UL) /*!< HRSPQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HTDBRST_Pos (11UL) /*!< HTDBRST (Bit 11) */ + #define R_I3C0_RSTCTL_HTDBRST_Msk (0x800UL) /*!< HTDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRDBRST_Pos (12UL) /*!< HRDBRST (Bit 12) */ + #define R_I3C0_RSTCTL_HRDBRST_Msk (0x1000UL) /*!< HRDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */ + #define R_I3C0_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */ +/* ========================================================= PRSST ========================================================= */ + #define R_I3C0_PRSST_CRMS_Pos (2UL) /*!< CRMS (Bit 2) */ + #define R_I3C0_PRSST_CRMS_Msk (0x4UL) /*!< CRMS (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSST_TRMD_Pos (4UL) /*!< TRMD (Bit 4) */ + #define R_I3C0_PRSST_TRMD_Msk (0x10UL) /*!< TRMD (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSST_PRSSTWP_Pos (7UL) /*!< PRSSTWP (Bit 7) */ + #define R_I3C0_PRSST_PRSSTWP_Msk (0x80UL) /*!< PRSSTWP (Bitfield-Mask: 0x01) */ +/* ========================================================= INST ========================================================== */ + #define R_I3C0_INST_INEF_Pos (10UL) /*!< INEF (Bit 10) */ + #define R_I3C0_INST_INEF_Msk (0x400UL) /*!< INEF (Bitfield-Mask: 0x01) */ +/* ========================================================= INSTE ========================================================= */ + #define R_I3C0_INSTE_INEE_Pos (10UL) /*!< INEE (Bit 10) */ + #define R_I3C0_INSTE_INEE_Msk (0x400UL) /*!< INEE (Bitfield-Mask: 0x01) */ +/* ========================================================= INIE ========================================================== */ + #define R_I3C0_INIE_INEIE_Pos (10UL) /*!< INEIE (Bit 10) */ + #define R_I3C0_INIE_INEIE_Msk (0x400UL) /*!< INEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== INSTFC ========================================================= */ + #define R_I3C0_INSTFC_INEFC_Pos (10UL) /*!< INEFC (Bit 10) */ + #define R_I3C0_INSTFC_INEFC_Msk (0x400UL) /*!< INEFC (Bitfield-Mask: 0x01) */ +/* ========================================================= DVCT ========================================================== */ + #define R_I3C0_DVCT_IDX_Pos (19UL) /*!< IDX (Bit 19) */ + #define R_I3C0_DVCT_IDX_Msk (0xf80000UL) /*!< IDX (Bitfield-Mask: 0x1f) */ +/* ======================================================== IBINCTL ======================================================== */ + #define R_I3C0_IBINCTL_NRHJCTL_Pos (0UL) /*!< NRHJCTL (Bit 0) */ + #define R_I3C0_IBINCTL_NRHJCTL_Msk (0x1UL) /*!< NRHJCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_IBINCTL_NRMRCTL_Pos (1UL) /*!< NRMRCTL (Bit 1) */ + #define R_I3C0_IBINCTL_NRMRCTL_Msk (0x2UL) /*!< NRMRCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_IBINCTL_NRSIRCTL_Pos (3UL) /*!< NRSIRCTL (Bit 3) */ + #define R_I3C0_IBINCTL_NRSIRCTL_Msk (0x8UL) /*!< NRSIRCTL (Bitfield-Mask: 0x01) */ +/* ========================================================= BFCTL ========================================================= */ + #define R_I3C0_BFCTL_MALE_Pos (0UL) /*!< MALE (Bit 0) */ + #define R_I3C0_BFCTL_MALE_Msk (0x1UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_NALE_Pos (1UL) /*!< NALE (Bit 1) */ + #define R_I3C0_BFCTL_NALE_Msk (0x2UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SALE_Pos (2UL) /*!< SALE (Bit 2) */ + #define R_I3C0_BFCTL_SALE_Msk (0x4UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SCSYNE_Pos (8UL) /*!< SCSYNE (Bit 8) */ + #define R_I3C0_BFCTL_SCSYNE_Msk (0x100UL) /*!< SCSYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SMBS_Pos (12UL) /*!< SMBS (Bit 12) */ + #define R_I3C0_BFCTL_SMBS_Msk (0x1000UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_FMPE_Pos (14UL) /*!< FMPE (Bit 14) */ + #define R_I3C0_BFCTL_FMPE_Msk (0x4000UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_HSME_Pos (15UL) /*!< HSME (Bit 15) */ + #define R_I3C0_BFCTL_HSME_Msk (0x8000UL) /*!< HSME (Bitfield-Mask: 0x01) */ +/* ========================================================= SVCTL ========================================================= */ + #define R_I3C0_SVCTL_GCAE_Pos (0UL) /*!< GCAE (Bit 0) */ + #define R_I3C0_SVCTL_GCAE_Msk (0x1UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_HSMCE_Pos (5UL) /*!< HSMCE (Bit 5) */ + #define R_I3C0_SVCTL_HSMCE_Msk (0x20UL) /*!< HSMCE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_DVIDE_Pos (6UL) /*!< DVIDE (Bit 6) */ + #define R_I3C0_SVCTL_DVIDE_Msk (0x40UL) /*!< DVIDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */ + #define R_I3C0_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */ + #define R_I3C0_SVCTL_SVAEn_Msk (0x70000UL) /*!< SVAEn (Bitfield-Mask: 0x07) */ +/* ======================================================= REFCKCTL ======================================================== */ + #define R_I3C0_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */ + #define R_I3C0_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */ +/* ========================================================= STDBR ========================================================= */ + #define R_I3C0_STDBR_SBRLO_Pos (0UL) /*!< SBRLO (Bit 0) */ + #define R_I3C0_STDBR_SBRLO_Msk (0xffUL) /*!< SBRLO (Bitfield-Mask: 0xff) */ + #define R_I3C0_STDBR_SBRHO_Pos (8UL) /*!< SBRHO (Bit 8) */ + #define R_I3C0_STDBR_SBRHO_Msk (0xff00UL) /*!< SBRHO (Bitfield-Mask: 0xff) */ + #define R_I3C0_STDBR_SBRLP_Pos (16UL) /*!< SBRLP (Bit 16) */ + #define R_I3C0_STDBR_SBRLP_Msk (0x3f0000UL) /*!< SBRLP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_STDBR_SBRHP_Pos (24UL) /*!< SBRHP (Bit 24) */ + #define R_I3C0_STDBR_SBRHP_Msk (0x3f000000UL) /*!< SBRHP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_STDBR_DSBRPO_Pos (31UL) /*!< DSBRPO (Bit 31) */ + #define R_I3C0_STDBR_DSBRPO_Msk (0x80000000UL) /*!< DSBRPO (Bitfield-Mask: 0x01) */ +/* ========================================================= EXTBR ========================================================= */ + #define R_I3C0_EXTBR_EBRLO_Pos (0UL) /*!< EBRLO (Bit 0) */ + #define R_I3C0_EXTBR_EBRLO_Msk (0xffUL) /*!< EBRLO (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXTBR_EBRHO_Pos (8UL) /*!< EBRHO (Bit 8) */ + #define R_I3C0_EXTBR_EBRHO_Msk (0xff00UL) /*!< EBRHO (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXTBR_EBRLP_Pos (16UL) /*!< EBRLP (Bit 16) */ + #define R_I3C0_EXTBR_EBRLP_Msk (0x3f0000UL) /*!< EBRLP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_EXTBR_EBRHP_Pos (24UL) /*!< EBRHP (Bit 24) */ + #define R_I3C0_EXTBR_EBRHP_Msk (0x3f000000UL) /*!< EBRHP (Bitfield-Mask: 0x3f) */ +/* ======================================================== BFRECDT ======================================================== */ + #define R_I3C0_BFRECDT_FRECYC_Pos (0UL) /*!< FRECYC (Bit 0) */ + #define R_I3C0_BFRECDT_FRECYC_Msk (0x1ffUL) /*!< FRECYC (Bitfield-Mask: 0x1ff) */ +/* ======================================================== BAVLCDT ======================================================== */ + #define R_I3C0_BAVLCDT_AVLCYC_Pos (0UL) /*!< AVLCYC (Bit 0) */ + #define R_I3C0_BAVLCDT_AVLCYC_Msk (0x1ffUL) /*!< AVLCYC (Bitfield-Mask: 0x1ff) */ +/* ======================================================== BIDLCDT ======================================================== */ + #define R_I3C0_BIDLCDT_IDLCYC_Pos (0UL) /*!< IDLCYC (Bit 0) */ + #define R_I3C0_BIDLCDT_IDLCYC_Msk (0x3ffffUL) /*!< IDLCYC (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== OUTCTL ========================================================= */ + #define R_I3C0_OUTCTL_SDOC_Pos (0UL) /*!< SDOC (Bit 0) */ + #define R_I3C0_OUTCTL_SDOC_Msk (0x1UL) /*!< SDOC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SCOC_Pos (1UL) /*!< SCOC (Bit 1) */ + #define R_I3C0_OUTCTL_SCOC_Msk (0x2UL) /*!< SCOC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SOCWP_Pos (2UL) /*!< SOCWP (Bit 2) */ + #define R_I3C0_OUTCTL_SOCWP_Msk (0x4UL) /*!< SOCWP (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_EXCYC_Pos (4UL) /*!< EXCYC (Bit 4) */ + #define R_I3C0_OUTCTL_EXCYC_Msk (0x10UL) /*!< EXCYC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SDOD_Pos (8UL) /*!< SDOD (Bit 8) */ + #define R_I3C0_OUTCTL_SDOD_Msk (0x700UL) /*!< SDOD (Bitfield-Mask: 0x07) */ + #define R_I3C0_OUTCTL_SDODCS_Pos (15UL) /*!< SDODCS (Bit 15) */ + #define R_I3C0_OUTCTL_SDODCS_Msk (0x8000UL) /*!< SDODCS (Bitfield-Mask: 0x01) */ +/* ========================================================= INCTL ========================================================= */ + #define R_I3C0_INCTL_DNFS_Pos (0UL) /*!< DNFS (Bit 0) */ + #define R_I3C0_INCTL_DNFS_Msk (0xfUL) /*!< DNFS (Bitfield-Mask: 0x0f) */ + #define R_I3C0_INCTL_DNFE_Pos (4UL) /*!< DNFE (Bit 4) */ + #define R_I3C0_INCTL_DNFE_Msk (0x10UL) /*!< DNFE (Bitfield-Mask: 0x01) */ +/* ======================================================== TMOCTL ========================================================= */ + #define R_I3C0_TMOCTL_TODTS_Pos (0UL) /*!< TODTS (Bit 0) */ + #define R_I3C0_TMOCTL_TODTS_Msk (0x3UL) /*!< TODTS (Bitfield-Mask: 0x03) */ + #define R_I3C0_TMOCTL_TOLCTL_Pos (4UL) /*!< TOLCTL (Bit 4) */ + #define R_I3C0_TMOCTL_TOLCTL_Msk (0x10UL) /*!< TOLCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_TMOCTL_TOHCTL_Pos (5UL) /*!< TOHCTL (Bit 5) */ + #define R_I3C0_TMOCTL_TOHCTL_Msk (0x20UL) /*!< TOHCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_TMOCTL_TOMDS_Pos (6UL) /*!< TOMDS (Bit 6) */ + #define R_I3C0_TMOCTL_TOMDS_Msk (0xc0UL) /*!< TOMDS (Bitfield-Mask: 0x03) */ +/* ========================================================= WUCTL ========================================================= */ + #define R_I3C0_WUCTL_WUACKS_Pos (0UL) /*!< WUACKS (Bit 0) */ + #define R_I3C0_WUCTL_WUACKS_Msk (0x1UL) /*!< WUACKS (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUANFS_Pos (4UL) /*!< WUANFS (Bit 4) */ + #define R_I3C0_WUCTL_WUANFS_Msk (0x10UL) /*!< WUANFS (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUFSYNE_Pos (6UL) /*!< WUFSYNE (Bit 6) */ + #define R_I3C0_WUCTL_WUFSYNE_Msk (0x40UL) /*!< WUFSYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUFE_Pos (7UL) /*!< WUFE (Bit 7) */ + #define R_I3C0_WUCTL_WUFE_Msk (0x80UL) /*!< WUFE (Bitfield-Mask: 0x01) */ +/* ======================================================== ACKCTL ========================================================= */ + #define R_I3C0_ACKCTL_ACKR_Pos (0UL) /*!< ACKR (Bit 0) */ + #define R_I3C0_ACKCTL_ACKR_Msk (0x1UL) /*!< ACKR (Bitfield-Mask: 0x01) */ + #define R_I3C0_ACKCTL_ACKT_Pos (1UL) /*!< ACKT (Bit 1) */ + #define R_I3C0_ACKCTL_ACKT_Msk (0x2UL) /*!< ACKT (Bitfield-Mask: 0x01) */ + #define R_I3C0_ACKCTL_ACKTWP_Pos (2UL) /*!< ACKTWP (Bit 2) */ + #define R_I3C0_ACKCTL_ACKTWP_Msk (0x4UL) /*!< ACKTWP (Bitfield-Mask: 0x01) */ +/* ======================================================= SCSTRCTL ======================================================== */ + #define R_I3C0_SCSTRCTL_ACKTWE_Pos (0UL) /*!< ACKTWE (Bit 0) */ + #define R_I3C0_SCSTRCTL_ACKTWE_Msk (0x1UL) /*!< ACKTWE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTRCTL_RWE_Pos (1UL) /*!< RWE (Bit 1) */ + #define R_I3C0_SCSTRCTL_RWE_Msk (0x2UL) /*!< RWE (Bitfield-Mask: 0x01) */ +/* ======================================================= SCSTLCTL ======================================================== */ + #define R_I3C0_SCSTLCTL_STLCYC_Pos (0UL) /*!< STLCYC (Bit 0) */ + #define R_I3C0_SCSTLCTL_STLCYC_Msk (0xffffUL) /*!< STLCYC (Bitfield-Mask: 0xffff) */ + #define R_I3C0_SCSTLCTL_AAPE_Pos (28UL) /*!< AAPE (Bit 28) */ + #define R_I3C0_SCSTLCTL_AAPE_Msk (0x10000000UL) /*!< AAPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_TRAPE_Pos (29UL) /*!< TRAPE (Bit 29) */ + #define R_I3C0_SCSTLCTL_TRAPE_Msk (0x20000000UL) /*!< TRAPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_PARPE_Pos (30UL) /*!< PARPE (Bit 30) */ + #define R_I3C0_SCSTLCTL_PARPE_Msk (0x40000000UL) /*!< PARPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_ACKPE_Pos (31UL) /*!< ACKPE (Bit 31) */ + #define R_I3C0_SCSTLCTL_ACKPE_Msk (0x80000000UL) /*!< ACKPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SVTDLG0 ======================================================== */ + #define R_I3C0_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */ + #define R_I3C0_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */ +/* ========================================================= STCTL ========================================================= */ + #define R_I3C0_STCTL_STOE_Pos (0UL) /*!< STOE (Bit 0) */ + #define R_I3C0_STCTL_STOE_Msk (0x1UL) /*!< STOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ATCTL ========================================================= */ + #define R_I3C0_ATCTL_ATTRGS_Pos (0UL) /*!< ATTRGS (Bit 0) */ + #define R_I3C0_ATCTL_ATTRGS_Msk (0x1UL) /*!< ATTRGS (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_MREFOE_Pos (1UL) /*!< MREFOE (Bit 1) */ + #define R_I3C0_ATCTL_MREFOE_Msk (0x2UL) /*!< MREFOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_AMEOE_Pos (2UL) /*!< AMEOE (Bit 2) */ + #define R_I3C0_ATCTL_AMEOE_Msk (0x4UL) /*!< AMEOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_CDIV_Pos (8UL) /*!< CDIV (Bit 8) */ + #define R_I3C0_ATCTL_CDIV_Msk (0xff00UL) /*!< CDIV (Bitfield-Mask: 0xff) */ +/* ========================================================= ATTRG ========================================================= */ + #define R_I3C0_ATTRG_ATSTRG_Pos (0UL) /*!< ATSTRG (Bit 0) */ + #define R_I3C0_ATTRG_ATSTRG_Msk (0x1UL) /*!< ATSTRG (Bitfield-Mask: 0x01) */ +/* ======================================================== ATCCNTE ======================================================== */ + #define R_I3C0_ATCCNTE_ATCE_Pos (0UL) /*!< ATCE (Bit 0) */ + #define R_I3C0_ATCCNTE_ATCE_Msk (0x1UL) /*!< ATCE (Bitfield-Mask: 0x01) */ +/* ======================================================== CNDCTL ========================================================= */ + #define R_I3C0_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */ + #define R_I3C0_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */ + #define R_I3C0_CNDCTL_SRCND_Pos (1UL) /*!< SRCND (Bit 1) */ + #define R_I3C0_CNDCTL_SRCND_Msk (0x2UL) /*!< SRCND (Bitfield-Mask: 0x01) */ + #define R_I3C0_CNDCTL_SPCND_Pos (2UL) /*!< SPCND (Bit 2) */ + #define R_I3C0_CNDCTL_SPCND_Msk (0x4UL) /*!< SPCND (Bitfield-Mask: 0x01) */ +/* ======================================================== NCMDQP ========================================================= */ +/* ======================================================== NRSPQP ========================================================= */ +/* ======================================================== NTDTBP0 ======================================================== */ +/* ======================================================== NIBIQP ========================================================= */ +/* ========================================================= NRSQP ========================================================= */ +/* ======================================================== HCMDQP ========================================================= */ + #define R_I3C0_HCMDQP_HCMDQP_Pos (0UL) /*!< HCMDQP (Bit 0) */ + #define R_I3C0_HCMDQP_HCMDQP_Msk (0xffffffffUL) /*!< HCMDQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HRSPQP ========================================================= */ + #define R_I3C0_HRSPQP_HRSPQP_Pos (0UL) /*!< HRSPQP (Bit 0) */ + #define R_I3C0_HRSPQP_HRSPQP_Msk (0xffffffffUL) /*!< HRSPQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HTDTBP ========================================================= */ + #define R_I3C0_HTDTBP_HTDTBP_Pos (0UL) /*!< HTDTBP (Bit 0) */ + #define R_I3C0_HTDTBP_HTDTBP_Msk (0xffffffffUL) /*!< HTDTBP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== NQTHCTL ======================================================== */ + #define R_I3C0_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ + #define R_I3C0_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ + #define R_I3C0_NQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_IBIDSSZ_Pos (16UL) /*!< IBIDSSZ (Bit 16) */ + #define R_I3C0_NQTHCTL_IBIDSSZ_Msk (0xff0000UL) /*!< IBIDSSZ (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_IBIQTH_Pos (24UL) /*!< IBIQTH (Bit 24) */ + #define R_I3C0_NQTHCTL_IBIQTH_Msk (0xff000000UL) /*!< IBIQTH (Bitfield-Mask: 0xff) */ +/* ======================================================= NTBTHCTL0 ======================================================= */ + #define R_I3C0_NTBTHCTL0_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ + #define R_I3C0_NTBTHCTL0_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ + #define R_I3C0_NTBTHCTL0_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ + #define R_I3C0_NTBTHCTL0_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ + #define R_I3C0_NTBTHCTL0_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ +/* ======================================================= NRQTHCTL ======================================================== */ + #define R_I3C0_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */ + #define R_I3C0_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */ +/* ======================================================== HQTHCTL ======================================================== */ + #define R_I3C0_HQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ + #define R_I3C0_HQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ + #define R_I3C0_HQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ +/* ======================================================= HTBTHCTL ======================================================== */ + #define R_I3C0_HTBTHCTL_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ + #define R_I3C0_HTBTHCTL_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ +/* ========================================================== BST ========================================================== */ + #define R_I3C0_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */ + #define R_I3C0_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_SPCNDDF_Pos (1UL) /*!< SPCNDDF (Bit 1) */ + #define R_I3C0_BST_SPCNDDF_Msk (0x2UL) /*!< SPCNDDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_HDREXDF_Pos (2UL) /*!< HDREXDF (Bit 2) */ + #define R_I3C0_BST_HDREXDF_Msk (0x4UL) /*!< HDREXDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_NACKDF_Pos (4UL) /*!< NACKDF (Bit 4) */ + #define R_I3C0_BST_NACKDF_Msk (0x10UL) /*!< NACKDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_TENDF_Pos (8UL) /*!< TENDF (Bit 8) */ + #define R_I3C0_BST_TENDF_Msk (0x100UL) /*!< TENDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_ALF_Pos (16UL) /*!< ALF (Bit 16) */ + #define R_I3C0_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */ + #define R_I3C0_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_WUCNDDF_Pos (24UL) /*!< WUCNDDF (Bit 24) */ + #define R_I3C0_BST_WUCNDDF_Msk (0x1000000UL) /*!< WUCNDDF (Bitfield-Mask: 0x01) */ +/* ========================================================= BSTE ========================================================== */ + #define R_I3C0_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */ + #define R_I3C0_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_SPCNDDE_Pos (1UL) /*!< SPCNDDE (Bit 1) */ + #define R_I3C0_BSTE_SPCNDDE_Msk (0x2UL) /*!< SPCNDDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_HDREXDE_Pos (2UL) /*!< HDREXDE (Bit 2) */ + #define R_I3C0_BSTE_HDREXDE_Msk (0x4UL) /*!< HDREXDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_NACKDE_Pos (4UL) /*!< NACKDE (Bit 4) */ + #define R_I3C0_BSTE_NACKDE_Msk (0x10UL) /*!< NACKDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_TENDE_Pos (8UL) /*!< TENDE (Bit 8) */ + #define R_I3C0_BSTE_TENDE_Msk (0x100UL) /*!< TENDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_ALE_Pos (16UL) /*!< ALE (Bit 16) */ + #define R_I3C0_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */ + #define R_I3C0_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_WUCNDDE_Pos (24UL) /*!< WUCNDDE (Bit 24) */ + #define R_I3C0_BSTE_WUCNDDE_Msk (0x1000000UL) /*!< WUCNDDE (Bitfield-Mask: 0x01) */ +/* ========================================================== BIE ========================================================== */ + #define R_I3C0_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */ + #define R_I3C0_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_SPCNDDIE_Pos (1UL) /*!< SPCNDDIE (Bit 1) */ + #define R_I3C0_BIE_SPCNDDIE_Msk (0x2UL) /*!< SPCNDDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_HDREXDIE_Pos (2UL) /*!< HDREXDIE (Bit 2) */ + #define R_I3C0_BIE_HDREXDIE_Msk (0x4UL) /*!< HDREXDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_NACKDIE_Pos (4UL) /*!< NACKDIE (Bit 4) */ + #define R_I3C0_BIE_NACKDIE_Msk (0x10UL) /*!< NACKDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_TENDIE_Pos (8UL) /*!< TENDIE (Bit 8) */ + #define R_I3C0_BIE_TENDIE_Msk (0x100UL) /*!< TENDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_ALIE_Pos (16UL) /*!< ALIE (Bit 16) */ + #define R_I3C0_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */ + #define R_I3C0_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_WUCNDDIE_Pos (24UL) /*!< WUCNDDIE (Bit 24) */ + #define R_I3C0_BIE_WUCNDDIE_Msk (0x1000000UL) /*!< WUCNDDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= BSTFC ========================================================= */ + #define R_I3C0_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */ + #define R_I3C0_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_SPCNDDFC_Pos (1UL) /*!< SPCNDDFC (Bit 1) */ + #define R_I3C0_BSTFC_SPCNDDFC_Msk (0x2UL) /*!< SPCNDDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_HDREXDFC_Pos (2UL) /*!< HDREXDFC (Bit 2) */ + #define R_I3C0_BSTFC_HDREXDFC_Msk (0x4UL) /*!< HDREXDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_NACKDFC_Pos (4UL) /*!< NACKDFC (Bit 4) */ + #define R_I3C0_BSTFC_NACKDFC_Msk (0x10UL) /*!< NACKDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_TENDFC_Pos (8UL) /*!< TENDFC (Bit 8) */ + #define R_I3C0_BSTFC_TENDFC_Msk (0x100UL) /*!< TENDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_ALFC_Pos (16UL) /*!< ALFC (Bit 16) */ + #define R_I3C0_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */ + #define R_I3C0_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_WUCNDDFC_Pos (24UL) /*!< WUCNDDFC (Bit 24) */ + #define R_I3C0_BSTFC_WUCNDDFC_Msk (0x1000000UL) /*!< WUCNDDFC (Bitfield-Mask: 0x01) */ +/* ========================================================= NTST ========================================================== */ + #define R_I3C0_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */ + #define R_I3C0_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RDBFF0_Pos (1UL) /*!< RDBFF0 (Bit 1) */ + #define R_I3C0_NTST_RDBFF0_Msk (0x2UL) /*!< RDBFF0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_IBIQEFF_Pos (2UL) /*!< IBIQEFF (Bit 2) */ + #define R_I3C0_NTST_IBIQEFF_Msk (0x4UL) /*!< IBIQEFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ + #define R_I3C0_NTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ + #define R_I3C0_NTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ + #define R_I3C0_NTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ + #define R_I3C0_NTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RSQFF_Pos (20UL) /*!< RSQFF (Bit 20) */ + #define R_I3C0_NTST_RSQFF_Msk (0x100000UL) /*!< RSQFF (Bitfield-Mask: 0x01) */ +/* ========================================================= NTSTE ========================================================= */ + #define R_I3C0_NTSTE_TDBEE0_Pos (0UL) /*!< TDBEE0 (Bit 0) */ + #define R_I3C0_NTSTE_TDBEE0_Msk (0x1UL) /*!< TDBEE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RDBFE0_Pos (1UL) /*!< RDBFE0 (Bit 1) */ + #define R_I3C0_NTSTE_RDBFE0_Msk (0x2UL) /*!< RDBFE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_IBIQEFE_Pos (2UL) /*!< IBIQEFE (Bit 2) */ + #define R_I3C0_NTSTE_IBIQEFE_Msk (0x4UL) /*!< IBIQEFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ + #define R_I3C0_NTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ + #define R_I3C0_NTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ + #define R_I3C0_NTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ + #define R_I3C0_NTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RSQFE_Pos (20UL) /*!< RSQFE (Bit 20) */ + #define R_I3C0_NTSTE_RSQFE_Msk (0x100000UL) /*!< RSQFE (Bitfield-Mask: 0x01) */ +/* ========================================================= NTIE ========================================================== */ + #define R_I3C0_NTIE_TDBEIE0_Pos (0UL) /*!< TDBEIE0 (Bit 0) */ + #define R_I3C0_NTIE_TDBEIE0_Msk (0x1UL) /*!< TDBEIE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RDBFIE0_Pos (1UL) /*!< RDBFIE0 (Bit 1) */ + #define R_I3C0_NTIE_RDBFIE0_Msk (0x2UL) /*!< RDBFIE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_IBIQEFIE_Pos (2UL) /*!< IBIQEFIE (Bit 2) */ + #define R_I3C0_NTIE_IBIQEFIE_Msk (0x4UL) /*!< IBIQEFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ + #define R_I3C0_NTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ + #define R_I3C0_NTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ + #define R_I3C0_NTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ + #define R_I3C0_NTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RSQFIE_Pos (20UL) /*!< RSQFIE (Bit 20) */ + #define R_I3C0_NTIE_RSQFIE_Msk (0x100000UL) /*!< RSQFIE (Bitfield-Mask: 0x01) */ +/* ======================================================== NTSTFC ========================================================= */ + #define R_I3C0_NTSTFC_TDBEFC0_Pos (0UL) /*!< TDBEFC0 (Bit 0) */ + #define R_I3C0_NTSTFC_TDBEFC0_Msk (0x1UL) /*!< TDBEFC0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RDBFFC0_Pos (1UL) /*!< RDBFFC0 (Bit 1) */ + #define R_I3C0_NTSTFC_RDBFFC0_Msk (0x2UL) /*!< RDBFFC0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_IBIQEFFC_Pos (2UL) /*!< IBIQEFFC (Bit 2) */ + #define R_I3C0_NTSTFC_IBIQEFFC_Msk (0x4UL) /*!< IBIQEFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ + #define R_I3C0_NTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ + #define R_I3C0_NTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ + #define R_I3C0_NTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ + #define R_I3C0_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */ + #define R_I3C0_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */ +/* ========================================================= HTST ========================================================== */ + #define R_I3C0_HTST_TDBEF_Pos (0UL) /*!< TDBEF (Bit 0) */ + #define R_I3C0_HTST_TDBEF_Msk (0x1UL) /*!< TDBEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RDBFF_Pos (1UL) /*!< RDBFF (Bit 1) */ + #define R_I3C0_HTST_RDBFF_Msk (0x2UL) /*!< RDBFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ + #define R_I3C0_HTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ + #define R_I3C0_HTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ + #define R_I3C0_HTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ + #define R_I3C0_HTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ +/* ========================================================= HTSTE ========================================================= */ + #define R_I3C0_HTSTE_TDBEE_Pos (0UL) /*!< TDBEE (Bit 0) */ + #define R_I3C0_HTSTE_TDBEE_Msk (0x1UL) /*!< TDBEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RDBFE_Pos (1UL) /*!< RDBFE (Bit 1) */ + #define R_I3C0_HTSTE_RDBFE_Msk (0x2UL) /*!< RDBFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ + #define R_I3C0_HTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ + #define R_I3C0_HTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ + #define R_I3C0_HTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ + #define R_I3C0_HTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ +/* ========================================================= HTIE ========================================================== */ + #define R_I3C0_HTIE_TDBEIE_Pos (0UL) /*!< TDBEIE (Bit 0) */ + #define R_I3C0_HTIE_TDBEIE_Msk (0x1UL) /*!< TDBEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RDBFIE_Pos (1UL) /*!< RDBFIE (Bit 1) */ + #define R_I3C0_HTIE_RDBFIE_Msk (0x2UL) /*!< RDBFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ + #define R_I3C0_HTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ + #define R_I3C0_HTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ + #define R_I3C0_HTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ + #define R_I3C0_HTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== HTSTFC ========================================================= */ + #define R_I3C0_HTSTFC_TDBEFC_Pos (0UL) /*!< TDBEFC (Bit 0) */ + #define R_I3C0_HTSTFC_TDBEFC_Msk (0x1UL) /*!< TDBEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RDBFFC_Pos (1UL) /*!< RDBFFC (Bit 1) */ + #define R_I3C0_HTSTFC_RDBFFC_Msk (0x2UL) /*!< RDBFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ + #define R_I3C0_HTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ + #define R_I3C0_HTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ + #define R_I3C0_HTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ + #define R_I3C0_HTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ +/* ========================================================= BCST ========================================================== */ + #define R_I3C0_BCST_BFREF_Pos (0UL) /*!< BFREF (Bit 0) */ + #define R_I3C0_BCST_BFREF_Msk (0x1UL) /*!< BFREF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCST_BAVLF_Pos (1UL) /*!< BAVLF (Bit 1) */ + #define R_I3C0_BCST_BAVLF_Msk (0x2UL) /*!< BAVLF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCST_BIDLF_Pos (2UL) /*!< BIDLF (Bit 2) */ + #define R_I3C0_BCST_BIDLF_Msk (0x4UL) /*!< BIDLF (Bitfield-Mask: 0x01) */ +/* ========================================================= SVST ========================================================== */ + #define R_I3C0_SVST_GCAF_Pos (0UL) /*!< GCAF (Bit 0) */ + #define R_I3C0_SVST_GCAF_Msk (0x1UL) /*!< GCAF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_HSMCF_Pos (5UL) /*!< HSMCF (Bit 5) */ + #define R_I3C0_SVST_HSMCF_Msk (0x20UL) /*!< HSMCF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_DVIDF_Pos (6UL) /*!< DVIDF (Bit 6) */ + #define R_I3C0_SVST_DVIDF_Msk (0x40UL) /*!< DVIDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */ + #define R_I3C0_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */ + #define R_I3C0_SVST_SVAFn_Msk (0x70000UL) /*!< SVAFn (Bitfield-Mask: 0x07) */ +/* ========================================================= WUST ========================================================== */ + #define R_I3C0_WUST_WUASYNF_Pos (0UL) /*!< WUASYNF (Bit 0) */ + #define R_I3C0_WUST_WUASYNF_Msk (0x1UL) /*!< WUASYNF (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCCPT ========================================================= */ + #define R_I3C0_MRCCPT_MRCCPT_Pos (0UL) /*!< MRCCPT (Bit 0) */ + #define R_I3C0_MRCCPT_MRCCPT_Msk (0xffffffffUL) /*!< MRCCPT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DATBAS0 ======================================================== */ + #define R_I3C0_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS0_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS0_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS0_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS0_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS0_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS0_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS0_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS0_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS0_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS0_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS1 ======================================================== */ + #define R_I3C0_DATBAS1_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS1_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS1_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS1_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS1_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS1_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS1_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS1_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS1_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS1_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS1_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS1_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS2 ======================================================== */ + #define R_I3C0_DATBAS2_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS2_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS2_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS2_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS2_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS2_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS2_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS2_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS2_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS2_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS2_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS2_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS3 ======================================================== */ + #define R_I3C0_DATBAS3_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS3_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS3_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS3_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS3_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS3_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS3_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS3_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS3_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS4 ======================================================== */ + #define R_I3C0_DATBAS4_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS4_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS4_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS4_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS4_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS4_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS4_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS4_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS4_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS4_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS4_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS5 ======================================================== */ + #define R_I3C0_DATBAS5_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS5_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS5_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS5_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS5_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS5_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS5_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS5_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS5_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS5_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS5_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS6 ======================================================== */ + #define R_I3C0_DATBAS6_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS6_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS6_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS6_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS6_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS6_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS6_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS6_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS6_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS6_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS6_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS7 ======================================================== */ + #define R_I3C0_DATBAS7_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS7_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS7_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS7_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS7_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS7_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS7_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS7_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS7_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS7_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS7_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================= EXDATBAS ======================================================== */ + #define R_I3C0_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */ + #define R_I3C0_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_EXDATBAS_EDDYAD_Pos (16UL) /*!< EDDYAD (Bit 16) */ + #define R_I3C0_EXDATBAS_EDDYAD_Msk (0xff0000UL) /*!< EDDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXDATBAS_EDNACK_Pos (29UL) /*!< EDNACK (Bit 29) */ + #define R_I3C0_EXDATBAS_EDNACK_Msk (0x60000000UL) /*!< EDNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_EXDATBAS_EDTYP_Pos (31UL) /*!< EDTYP (Bit 31) */ + #define R_I3C0_EXDATBAS_EDTYP_Msk (0x80000000UL) /*!< EDTYP (Bitfield-Mask: 0x01) */ +/* ======================================================= SDATBAS0 ======================================================== */ + #define R_I3C0_SDATBAS0_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS0_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS0_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS0_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS0_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS0_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS0_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS0_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================= SDATBAS1 ======================================================== */ + #define R_I3C0_SDATBAS1_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS1_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS1_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS1_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS1_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS1_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS1_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS1_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================= SDATBAS2 ======================================================== */ + #define R_I3C0_SDATBAS2_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS2_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS2_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS2_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS2_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS2_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS2_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS2_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================== MSDCT0 ========================================================= */ + #define R_I3C0_MSDCT0_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT0_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT0_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT0_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT0_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT1 ========================================================= */ + #define R_I3C0_MSDCT1_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT1_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT1_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT1_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT1_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT2 ========================================================= */ + #define R_I3C0_MSDCT2_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT2_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT2_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT2_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT2_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT3 ========================================================= */ + #define R_I3C0_MSDCT3_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT3_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT3_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT3_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT4 ========================================================= */ + #define R_I3C0_MSDCT4_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT4_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT4_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT4_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT4_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT4_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT4_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT4_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT5 ========================================================= */ + #define R_I3C0_MSDCT5_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT5_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT5_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT5_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT5_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT5_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT5_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT5_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT6 ========================================================= */ + #define R_I3C0_MSDCT6_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT6_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT6_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT6_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT6_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT6_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT6_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT6_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT7 ========================================================= */ + #define R_I3C0_MSDCT7_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT7_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT7_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT7_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT7_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT7_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT7_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT7_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ========================================================= SVDCT ========================================================= */ + #define R_I3C0_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ + #define R_I3C0_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ + #define R_I3C0_SVDCT_TBCR0_Pos (8UL) /*!< TBCR0 (Bit 8) */ + #define R_I3C0_SVDCT_TBCR0_Msk (0x100UL) /*!< TBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR1_Pos (9UL) /*!< TBCR1 (Bit 9) */ + #define R_I3C0_SVDCT_TBCR1_Msk (0x200UL) /*!< TBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR2_Pos (10UL) /*!< TBCR2 (Bit 10) */ + #define R_I3C0_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */ + #define R_I3C0_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR4_Pos (12UL) /*!< TBCR4 (Bit 12) */ + #define R_I3C0_SVDCT_TBCR4_Msk (0x1000UL) /*!< TBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR5_Pos (13UL) /*!< TBCR5 (Bit 13) */ + #define R_I3C0_SVDCT_TBCR5_Msk (0x2000UL) /*!< TBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */ + #define R_I3C0_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================= SDCTPIDL ======================================================== */ +/* ======================================================= SDCTPIDH ======================================================== */ +/* ======================================================== SVDVAD0 ======================================================== */ + #define R_I3C0_SVDVAD0_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD0_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD0_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD0_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD0_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD1 ======================================================== */ + #define R_I3C0_SVDVAD1_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD1_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD1_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD1_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD1_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD1_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD2 ======================================================== */ + #define R_I3C0_SVDVAD2_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD2_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD2_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD2_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD2_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD2_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== CSECMD ========================================================= */ + #define R_I3C0_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */ + #define R_I3C0_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CSECMD_MSRQE_Pos (1UL) /*!< MSRQE (Bit 1) */ + #define R_I3C0_CSECMD_MSRQE_Msk (0x2UL) /*!< MSRQE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CSECMD_HJEVE_Pos (3UL) /*!< HJEVE (Bit 3) */ + #define R_I3C0_CSECMD_HJEVE_Msk (0x8UL) /*!< HJEVE (Bitfield-Mask: 0x01) */ +/* ======================================================== CEACTST ======================================================== */ + #define R_I3C0_CEACTST_ACTST_Pos (0UL) /*!< ACTST (Bit 0) */ + #define R_I3C0_CEACTST_ACTST_Msk (0xfUL) /*!< ACTST (Bitfield-Mask: 0x0f) */ +/* ========================================================= CMWLG ========================================================= */ + #define R_I3C0_CMWLG_MWLG_Pos (0UL) /*!< MWLG (Bit 0) */ + #define R_I3C0_CMWLG_MWLG_Msk (0xffffUL) /*!< MWLG (Bitfield-Mask: 0xffff) */ +/* ========================================================= CMRLG ========================================================= */ + #define R_I3C0_CMRLG_MRLG_Pos (0UL) /*!< MRLG (Bit 0) */ + #define R_I3C0_CMRLG_MRLG_Msk (0xffffUL) /*!< MRLG (Bitfield-Mask: 0xffff) */ + #define R_I3C0_CMRLG_IBIPSZ_Pos (16UL) /*!< IBIPSZ (Bit 16) */ + #define R_I3C0_CMRLG_IBIPSZ_Msk (0xff0000UL) /*!< IBIPSZ (Bitfield-Mask: 0xff) */ +/* ======================================================== CETSTMD ======================================================== */ + #define R_I3C0_CETSTMD_TSTMD_Pos (0UL) /*!< TSTMD (Bit 0) */ + #define R_I3C0_CETSTMD_TSTMD_Msk (0xffUL) /*!< TSTMD (Bitfield-Mask: 0xff) */ +/* ======================================================== CGDVST ========================================================= */ + #define R_I3C0_CGDVST_PNDINT_Pos (0UL) /*!< PNDINT (Bit 0) */ + #define R_I3C0_CGDVST_PNDINT_Msk (0xfUL) /*!< PNDINT (Bitfield-Mask: 0x0f) */ + #define R_I3C0_CGDVST_PRTE_Pos (5UL) /*!< PRTE (Bit 5) */ + #define R_I3C0_CGDVST_PRTE_Msk (0x20UL) /*!< PRTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGDVST_ACTMD_Pos (6UL) /*!< ACTMD (Bit 6) */ + #define R_I3C0_CGDVST_ACTMD_Msk (0xc0UL) /*!< ACTMD (Bitfield-Mask: 0x03) */ + #define R_I3C0_CGDVST_VDRSV_Pos (8UL) /*!< VDRSV (Bit 8) */ + #define R_I3C0_CGDVST_VDRSV_Msk (0xff00UL) /*!< VDRSV (Bitfield-Mask: 0xff) */ +/* ======================================================== CMDSPW ========================================================= */ + #define R_I3C0_CMDSPW_MSWDR_Pos (0UL) /*!< MSWDR (Bit 0) */ + #define R_I3C0_CMDSPW_MSWDR_Msk (0x7UL) /*!< MSWDR (Bitfield-Mask: 0x07) */ +/* ======================================================== CMDSPR ========================================================= */ + #define R_I3C0_CMDSPR_MSRDR_Pos (0UL) /*!< MSRDR (Bit 0) */ + #define R_I3C0_CMDSPR_MSRDR_Msk (0x7UL) /*!< MSRDR (Bitfield-Mask: 0x07) */ + #define R_I3C0_CMDSPR_CDTTIM_Pos (3UL) /*!< CDTTIM (Bit 3) */ + #define R_I3C0_CMDSPR_CDTTIM_Msk (0x38UL) /*!< CDTTIM (Bitfield-Mask: 0x07) */ +/* ======================================================== CMDSPT ========================================================= */ + #define R_I3C0_CMDSPT_MRTTIM_Pos (0UL) /*!< MRTTIM (Bit 0) */ + #define R_I3C0_CMDSPT_MRTTIM_Msk (0xffffffUL) /*!< MRTTIM (Bitfield-Mask: 0xffffff) */ + #define R_I3C0_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */ + #define R_I3C0_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */ +/* ========================================================= CETSM ========================================================= */ + #define R_I3C0_CETSM_SPTSYN_Pos (0UL) /*!< SPTSYN (Bit 0) */ + #define R_I3C0_CETSM_SPTSYN_Msk (0x1UL) /*!< SPTSYN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN0_Pos (1UL) /*!< SPTASYN0 (Bit 1) */ + #define R_I3C0_CETSM_SPTASYN0_Msk (0x2UL) /*!< SPTASYN0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN1_Pos (2UL) /*!< SPTASYN1 (Bit 2) */ + #define R_I3C0_CETSM_SPTASYN1_Msk (0x4UL) /*!< SPTASYN1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */ + #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ + #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ + #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ========================================================= CETSS ========================================================= */ + #define R_I3C0_CETSS_SYNE_Pos (0UL) /*!< SYNE (Bit 0) */ + #define R_I3C0_CETSS_SYNE_Msk (0x1UL) /*!< SYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSS_ASYNE_Pos (1UL) /*!< ASYNE (Bit 1) */ + #define R_I3C0_CETSS_ASYNE_Msk (0x6UL) /*!< ASYNE (Bitfield-Mask: 0x03) */ + #define R_I3C0_CETSS_ICOVF_Pos (7UL) /*!< ICOVF (Bit 7) */ + #define R_I3C0_CETSS_ICOVF_Msk (0x80UL) /*!< ICOVF (Bitfield-Mask: 0x01) */ +/* ======================================================= CGHDRCAP ======================================================== */ + #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ + #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSPEN_Pos (1UL) /*!< TSPEN (Bit 1) */ + #define R_I3C0_CGHDRCAP_TSPEN_Msk (0x2UL) /*!< TSPEN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSLEN_Pos (2UL) /*!< TSLEN (Bit 2) */ + #define R_I3C0_CGHDRCAP_TSLEN_Msk (0x4UL) /*!< TSLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BITCNT ========================================================= */ + #define R_I3C0_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */ + #define R_I3C0_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */ + #define R_I3C0_BITCNT_BCNTWP_Pos (7UL) /*!< BCNTWP (Bit 7) */ + #define R_I3C0_BITCNT_BCNTWP_Msk (0x80UL) /*!< BCNTWP (Bitfield-Mask: 0x01) */ +/* ======================================================== NQSTLV ========================================================= */ + #define R_I3C0_NQSTLV_CMDQFLV_Pos (0UL) /*!< CMDQFLV (Bit 0) */ + #define R_I3C0_NQSTLV_CMDQFLV_Msk (0xffUL) /*!< CMDQFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ + #define R_I3C0_NQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_IBIQLV_Pos (16UL) /*!< IBIQLV (Bit 16) */ + #define R_I3C0_NQSTLV_IBIQLV_Msk (0xff0000UL) /*!< IBIQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_IBISCNT_Pos (24UL) /*!< IBISCNT (Bit 24) */ + #define R_I3C0_NQSTLV_IBISCNT_Msk (0x1f000000UL) /*!< IBISCNT (Bitfield-Mask: 0x1f) */ +/* ======================================================= NDBSTLV0 ======================================================== */ + #define R_I3C0_NDBSTLV0_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ + #define R_I3C0_NDBSTLV0_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NDBSTLV0_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ + #define R_I3C0_NDBSTLV0_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ +/* ======================================================= NRSQSTLV ======================================================== */ + #define R_I3C0_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */ + #define R_I3C0_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HQSTLV ========================================================= */ + #define R_I3C0_HQSTLV_CMDQLV_Pos (0UL) /*!< CMDQLV (Bit 0) */ + #define R_I3C0_HQSTLV_CMDQLV_Msk (0xffUL) /*!< CMDQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ + #define R_I3C0_HQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HDBSTLV ======================================================== */ + #define R_I3C0_HDBSTLV_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ + #define R_I3C0_HDBSTLV_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HDBSTLV_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ + #define R_I3C0_HDBSTLV_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ +/* ======================================================== PRSTDBG ======================================================== */ + #define R_I3C0_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */ + #define R_I3C0_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SDILV_Pos (1UL) /*!< SDILV (Bit 1) */ + #define R_I3C0_PRSTDBG_SDILV_Msk (0x2UL) /*!< SDILV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SCOLV_Pos (2UL) /*!< SCOLV (Bit 2) */ + #define R_I3C0_PRSTDBG_SCOLV_Msk (0x4UL) /*!< SCOLV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SDOLV_Pos (3UL) /*!< SDOLV (Bit 3) */ + #define R_I3C0_PRSTDBG_SDOLV_Msk (0x8UL) /*!< SDOLV (Bitfield-Mask: 0x01) */ +/* ======================================================= MSERRCNT ======================================================== */ + #define R_I3C0_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */ + #define R_I3C0_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */ +/* ======================================================== SC1CPT ========================================================= */ + #define R_I3C0_SC1CPT_SC1C_Pos (0UL) /*!< SC1C (Bit 0) */ + #define R_I3C0_SC1CPT_SC1C_Msk (0xffffUL) /*!< SC1C (Bitfield-Mask: 0xffff) */ +/* ======================================================== SC2CPT ========================================================= */ + #define R_I3C0_SC2CPT_SC2C_Pos (0UL) /*!< SC2C (Bit 0) */ + #define R_I3C0_SC2CPT_SC2C_Msk (0xffffUL) /*!< SC2C (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_MMPU_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_MMPU_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= OADPT ========================================================= */ + #define R_MPU_MMPU_OADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_OADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MSTPCRA ======================================================== */ + #define R_MSTP_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */ + #define R_MSTP_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_MSTP_MSTPCRB_MSTPB_Pos (0UL) /*!< MSTPB (Bit 0) */ + #define R_MSTP_MSTPCRB_MSTPB_Msk (0x1UL) /*!< MSTPB (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_MSTP_MSTPCRC_MSTPC_Pos (0UL) /*!< MSTPC (Bit 0) */ + #define R_MSTP_MSTPCRC_MSTPC_Msk (0x1UL) /*!< MSTPC (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_MSTP_MSTPCRD_MSTPD_Pos (0UL) /*!< MSTPD (Bit 0) */ + #define R_MSTP_MSTPCRD_MSTPD_Msk (0x1UL) /*!< MSTPD (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_MSTP_MSTPCRE_MSTPE_Pos (0UL) /*!< MSTPE (Bit 0) */ + #define R_MSTP_MSTPCRE_MSTPE_Msk (0x1UL) /*!< MSTPE (Bitfield-Mask: 0x01) */ +/* ======================================================= LSMRWDIS ======================================================== */ + #define R_MSTP_LSMRWDIS_RTCRWDIS_Pos (0UL) /*!< RTCRWDIS (Bit 0) */ + #define R_MSTP_LSMRWDIS_RTCRWDIS_Msk (0x1UL) /*!< RTCRWDIS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_WDTDIS_Pos (1UL) /*!< WDTDIS (Bit 1) */ + #define R_MSTP_LSMRWDIS_WDTDIS_Msk (0x2UL) /*!< WDTDIS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_IWDTIDS_Pos (2UL) /*!< IWDTIDS (Bit 2) */ + #define R_MSTP_LSMRWDIS_IWDTIDS_Msk (0x4UL) /*!< IWDTIDS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_WREN_Pos (7UL) /*!< WREN (Bit 7) */ + #define R_MSTP_LSMRWDIS_WREN_Msk (0x80UL) /*!< WREN (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_MSTP_LSMRWDIS_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PCNTR1 ========================================================= */ + #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ +/* ========================================================== PDR ========================================================== */ + #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ +/* ========================================================= PODR ========================================================== */ + #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR2 ========================================================= */ + #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PIDR ========================================================== */ + #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ +/* ========================================================= EIDR ========================================================== */ + #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ + #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR3 ========================================================= */ + #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ +/* ========================================================= POSR ========================================================== */ + #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ +/* ========================================================= PORR ========================================================== */ + #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ + #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR4 ========================================================= */ + #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EOSR ========================================================== */ + #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ +/* ========================================================= EORR ========================================================== */ + #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ + #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PFENET ========================================================= */ + #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ + #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPR ========================================================== */ + #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPRS ========================================================= */ + #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== R64CNT ========================================================= */ + #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ + #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ + #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ + #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ +/* ======================================================== RSECCNT ======================================================== */ + #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ + #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINCNT ======================================================== */ + #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ + #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ +/* ======================================================== RHRCNT ========================================================= */ + #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ + #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RWKCNT ========================================================= */ + #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================== RDAYCNT ======================================================== */ + #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RMONCNT ======================================================== */ + #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RYRCNT ========================================================= */ + #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT0AR ======================================================== */ + #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ + #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RSECAR ========================================================= */ + #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT1AR ======================================================== */ + #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ + #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINAR ========================================================= */ + #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT2AR ======================================================== */ + #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ + #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RHRAR ========================================================= */ + #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT3AR ======================================================== */ + #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ + #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RWKAR ========================================================= */ + #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================= BCNT0AER ======================================================== */ + #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYAR ========================================================= */ + #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT1AER ======================================================== */ + #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RMONAR ========================================================= */ + #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT2AER ======================================================== */ + #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RYRAR ========================================================= */ + #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT3AER ======================================================== */ + #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RYRAREN ======================================================== */ + #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR1 ========================================================== */ + #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ + #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ + #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ + #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ + #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ + #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ + #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR2 ========================================================== */ + #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ + #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ + #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ + #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ + #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ + #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ + #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ + #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR4 ========================================================== */ + #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ + #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ + #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRH ========================================================== */ + #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ + #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRL ========================================================== */ + #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= RADJ ========================================================== */ + #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ + #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ + #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ + #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ +/* ========================================================= RADJ2 ========================================================= */ + #define R_RTC_RADJ2_FADJ_Pos (5UL) /*!< FADJ (Bit 5) */ + #define R_RTC_RADJ2_FADJ_Msk (0xffe0UL) /*!< FADJ (Bitfield-Mask: 0x7ff) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SMR ========================================================== */ + #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ + #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ + #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ + #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ======================================================= SMR_SMCI ======================================================== */ + #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ + #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ + #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ + #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ + #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ========================================================== BRR ========================================================== */ + #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ + #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== SCR ========================================================== */ + #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ======================================================= SCR_SMCI ======================================================== */ + #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ + #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ +/* ========================================================== SSR ========================================================== */ + #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_FIFO ======================================================== */ + #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ + #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_MANC ======================================================== */ + #define R_SCI0_SSR_MANC_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_MANC_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_MANC_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_MANC_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_MANC_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_MANC_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_MANC_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MANC_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_MER_Pos (0UL) /*!< MER (Bit 0) */ + #define R_SCI0_SSR_MANC_MER_Msk (0x1UL) /*!< MER (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_SMCI ======================================================== */ + #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ + #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ +/* ========================================================= SCMR ========================================================== */ + #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ + #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ + #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ + #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ + #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ + #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SEMR ========================================================== */ + #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ + #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ + #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ + #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ + #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ + #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ + #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ + #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ + #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SNFR ========================================================== */ + #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ + #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ +/* ========================================================= SIMR1 ========================================================= */ + #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ + #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ + #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR2 ========================================================= */ + #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ + #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ + #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ + #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR3 ========================================================= */ + #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ + #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ + #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ + #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ + #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ + #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ +/* ========================================================= SPMR ========================================================== */ + #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ + #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ + #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ + #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ + #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ + #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ + #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ + #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TDRHL ========================================================= */ + #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ + #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FTDRHL ========================================================= */ + #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FTDRH ========================================================= */ + #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ + #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ + #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FTDRL ========================================================= */ + #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ + #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= RDRHL ========================================================= */ + #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ + #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRDRHL ========================================================= */ + #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ + #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ + #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ + #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ + #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ +/* ======================================================= TDRHL_MAN ======================================================= */ + #define R_SCI0_TDRHL_MAN_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_TDRHL_MAN_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI0_TDRHL_MAN_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_TDRHL_MAN_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_TDRHL_MAN_TSYNC_Pos (12UL) /*!< TSYNC (Bit 12) */ + #define R_SCI0_TDRHL_MAN_TSYNC_Msk (0x1000UL) /*!< TSYNC (Bitfield-Mask: 0x01) */ +/* ======================================================= RDRHL_MAN ======================================================= */ + #define R_SCI0_RDRHL_MAN_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_RDRHL_MAN_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI0_RDRHL_MAN_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_RDRHL_MAN_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_RDRHL_MAN_RSYNC_Pos (12UL) /*!< RSYNC (Bit 12) */ + #define R_SCI0_RDRHL_MAN_RSYNC_Msk (0x1000UL) /*!< RSYNC (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRH ========================================================= */ + #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ + #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ + #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRL ========================================================= */ + #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ + #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= MDDR ========================================================== */ + #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ + #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= DCCR ========================================================== */ + #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ + #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ + #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ + #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ + #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ + #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ + #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ + #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ + #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ + #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ + #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ + #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ + #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ + #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ + #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ +/* ========================================================== LSR ========================================================== */ + #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ + #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ + #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ +/* ========================================================== CDR ========================================================== */ + #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ +/* ========================================================= SPTR ========================================================== */ + #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ + #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ + #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ + #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ + #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ + #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ + #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ + #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ACTR ========================================================== */ + #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ + #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ + #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ + #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ + #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= ESMER ========================================================= */ + #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ + #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ + #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ + #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ + #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ + #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ + #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ + #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ + #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ + #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ + #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ + #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ +/* ========================================================== CR2 ========================================================== */ + #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ + #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ + #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ + #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ +/* ========================================================== CR3 ========================================================== */ + #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ + #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ +/* ========================================================== PCR ========================================================== */ + #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ + #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ + #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ + #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ + #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ + #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ + #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ + #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ + #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ + #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ + #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ + #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ + #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ + #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ + #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ + #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ +/* ========================================================= STCR ========================================================== */ + #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ + #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ + #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ + #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ + #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ + #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ + #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0DR ========================================================= */ +/* ========================================================= CF0CR ========================================================= */ + #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ + #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ + #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ + #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ + #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ + #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ + #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ + #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ + #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0RR ========================================================= */ +/* ======================================================== PCF1DR ========================================================= */ +/* ======================================================== SCF1DR ========================================================= */ +/* ========================================================= CF1CR ========================================================= */ + #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ + #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ + #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ + #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ + #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ + #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ + #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ + #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ + #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF1RR ========================================================= */ +/* ========================================================== TCR ========================================================== */ + #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ +/* ========================================================== TMR ========================================================== */ + #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ + #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ + #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ + #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ + #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ +/* ========================================================= TPRE ========================================================== */ +/* ========================================================= TCNT ========================================================== */ +/* ======================================================= SCIMSKEN ======================================================== */ + #define R_SCI0_SCIMSKEN_MSKEN_Pos (0UL) /*!< MSKEN (Bit 0) */ + #define R_SCI0_SCIMSKEN_MSKEN_Msk (0x1UL) /*!< MSKEN (Bitfield-Mask: 0x01) */ +/* ========================================================== MMR ========================================================== */ + #define R_SCI0_MMR_MANEN_Pos (7UL) /*!< MANEN (Bit 7) */ + #define R_SCI0_MMR_MANEN_Msk (0x80UL) /*!< MANEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_SBSEL_Pos (6UL) /*!< SBSEL (Bit 6) */ + #define R_SCI0_MMR_SBSEL_Msk (0x40UL) /*!< SBSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_SYNSEL_Pos (5UL) /*!< SYNSEL (Bit 5) */ + #define R_SCI0_MMR_SYNSEL_Msk (0x20UL) /*!< SYNSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_SYNVAL_Pos (4UL) /*!< SYNVAL (Bit 4) */ + #define R_SCI0_MMR_SYNVAL_Msk (0x10UL) /*!< SYNVAL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_ERTEN_Pos (2UL) /*!< ERTEN (Bit 2) */ + #define R_SCI0_MMR_ERTEN_Msk (0x4UL) /*!< ERTEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_TMPOL_Pos (1UL) /*!< TMPOL (Bit 1) */ + #define R_SCI0_MMR_TMPOL_Msk (0x2UL) /*!< TMPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_RMPOL_Pos (0UL) /*!< RMPOL (Bit 0) */ + #define R_SCI0_MMR_RMPOL_Msk (0x1UL) /*!< RMPOL (Bitfield-Mask: 0x01) */ +/* ========================================================= TMPR ========================================================== */ + #define R_SCI0_TMPR_TPLEN_Pos (0UL) /*!< TPLEN (Bit 0) */ + #define R_SCI0_TMPR_TPLEN_Msk (0xfUL) /*!< TPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI0_TMPR_TPPAT_Pos (4UL) /*!< TPPAT (Bit 4) */ + #define R_SCI0_TMPR_TPPAT_Msk (0x30UL) /*!< TPPAT (Bitfield-Mask: 0x03) */ +/* ========================================================= RMPR ========================================================== */ + #define R_SCI0_RMPR_RPLEN_Pos (0UL) /*!< RPLEN (Bit 0) */ + #define R_SCI0_RMPR_RPLEN_Msk (0xfUL) /*!< RPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI0_RMPR_RPPAT_Pos (4UL) /*!< RPPAT (Bit 4) */ + #define R_SCI0_RMPR_RPPAT_Msk (0x30UL) /*!< RPPAT (Bitfield-Mask: 0x03) */ +/* ========================================================= MESR ========================================================== */ + #define R_SCI0_MESR_PFER_Pos (0UL) /*!< PFER (Bit 0) */ + #define R_SCI0_MESR_PFER_Msk (0x1UL) /*!< PFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_MESR_SYER_Pos (1UL) /*!< SYER (Bit 1) */ + #define R_SCI0_MESR_SYER_Msk (0x2UL) /*!< SYER (Bitfield-Mask: 0x01) */ + #define R_SCI0_MESR_SBER_Pos (2UL) /*!< SBER (Bit 2) */ + #define R_SCI0_MESR_SBER_Msk (0x4UL) /*!< SBER (Bitfield-Mask: 0x01) */ +/* ========================================================= MECR ========================================================== */ + #define R_SCI0_MECR_PFEREN_Pos (0UL) /*!< PFEREN (Bit 0) */ + #define R_SCI0_MECR_PFEREN_Msk (0x1UL) /*!< PFEREN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MECR_SYEREN_Pos (1UL) /*!< SYEREN (Bit 1) */ + #define R_SCI0_MECR_SYEREN_Msk (0x2UL) /*!< SYEREN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MECR_SBEREN_Pos (2UL) /*!< SBEREN (Bit 2) */ + #define R_SCI0_MECR_SBEREN_Msk (0x4UL) /*!< SBEREN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SD_CMD ========================================================= */ + #define R_SDHI0_SD_CMD_CMD12AT_Pos (14UL) /*!< CMD12AT (Bit 14) */ + #define R_SDHI0_SD_CMD_CMD12AT_Msk (0xc000UL) /*!< CMD12AT (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_TRSTP_Pos (13UL) /*!< TRSTP (Bit 13) */ + #define R_SDHI0_SD_CMD_TRSTP_Msk (0x2000UL) /*!< TRSTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDRW_Pos (12UL) /*!< CMDRW (Bit 12) */ + #define R_SDHI0_SD_CMD_CMDRW_Msk (0x1000UL) /*!< CMDRW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDTP_Pos (11UL) /*!< CMDTP (Bit 11) */ + #define R_SDHI0_SD_CMD_CMDTP_Msk (0x800UL) /*!< CMDTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_RSPTP_Pos (8UL) /*!< RSPTP (Bit 8) */ + #define R_SDHI0_SD_CMD_RSPTP_Msk (0x700UL) /*!< RSPTP (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_CMD_ACMD_Pos (6UL) /*!< ACMD (Bit 6) */ + #define R_SDHI0_SD_CMD_ACMD_Msk (0xc0UL) /*!< ACMD (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_CMDIDX_Pos (0UL) /*!< CMDIDX (Bit 0) */ + #define R_SDHI0_SD_CMD_CMDIDX_Msk (0x3fUL) /*!< CMDIDX (Bitfield-Mask: 0x3f) */ +/* ======================================================== SD_ARG ========================================================= */ + #define R_SDHI0_SD_ARG_SD_ARG_Pos (0UL) /*!< SD_ARG (Bit 0) */ + #define R_SDHI0_SD_ARG_SD_ARG_Msk (0xffffffffUL) /*!< SD_ARG (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_ARG1 ======================================================== */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Pos (0UL) /*!< SD_ARG1 (Bit 0) */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Msk (0xffffUL) /*!< SD_ARG1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== SD_STOP ======================================================== */ + #define R_SDHI0_SD_STOP_SEC_Pos (8UL) /*!< SEC (Bit 8) */ + #define R_SDHI0_SD_STOP_SEC_Msk (0x100UL) /*!< SEC (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_STOP_STP_Pos (0UL) /*!< STP (Bit 0) */ + #define R_SDHI0_SD_STOP_STP_Msk (0x1UL) /*!< STP (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_SECCNT ======================================================= */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Pos (0UL) /*!< SD_SECCNT (Bit 0) */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Msk (0xffffffffUL) /*!< SD_SECCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SD_RSP10 ======================================================== */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Pos (0UL) /*!< SD_RSP10 (Bit 0) */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Msk (0xffffffffUL) /*!< SD_RSP10 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP1 ======================================================== */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Pos (0UL) /*!< SD_RSP1 (Bit 0) */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Msk (0xffffUL) /*!< SD_RSP1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP32 ======================================================== */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Pos (0UL) /*!< SD_RSP32 (Bit 0) */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Msk (0xffffffffUL) /*!< SD_RSP32 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP3 ======================================================== */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Pos (0UL) /*!< SD_RSP3 (Bit 0) */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Msk (0xffffUL) /*!< SD_RSP3 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP54 ======================================================== */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Pos (0UL) /*!< SD_RSP54 (Bit 0) */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Msk (0xffffffffUL) /*!< SD_RSP54 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP5 ======================================================== */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Pos (0UL) /*!< SD_RSP5 (Bit 0) */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Msk (0xffffUL) /*!< SD_RSP5 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP76 ======================================================== */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Pos (0UL) /*!< SD_RSP76 (Bit 0) */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Msk (0xffffffUL) /*!< SD_RSP76 (Bitfield-Mask: 0xffffff) */ +/* ======================================================== SD_RSP7 ======================================================== */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Pos (0UL) /*!< SD_RSP7 (Bit 0) */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Msk (0xffUL) /*!< SD_RSP7 (Bitfield-Mask: 0xff) */ +/* ======================================================= SD_INFO1 ======================================================== */ + #define R_SDHI0_SD_INFO1_SDD3MON_Pos (10UL) /*!< SDD3MON (Bit 10) */ + #define R_SDHI0_SD_INFO1_SDD3MON_Msk (0x400UL) /*!< SDD3MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Pos (9UL) /*!< SDD3IN (Bit 9) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Msk (0x200UL) /*!< SDD3IN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Pos (8UL) /*!< SDD3RM (Bit 8) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Msk (0x100UL) /*!< SDD3RM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Pos (7UL) /*!< SDWPMON (Bit 7) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Msk (0x80UL) /*!< SDWPMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Pos (5UL) /*!< SDCDMON (Bit 5) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Msk (0x20UL) /*!< SDCDMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Pos (4UL) /*!< SDCDIN (Bit 4) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Msk (0x10UL) /*!< SDCDIN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Pos (3UL) /*!< SDCDRM (Bit 3) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Msk (0x8UL) /*!< SDCDRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_ACEND_Pos (2UL) /*!< ACEND (Bit 2) */ + #define R_SDHI0_SD_INFO1_ACEND_Msk (0x4UL) /*!< ACEND (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_RSPEND_Pos (0UL) /*!< RSPEND (Bit 0) */ + #define R_SDHI0_SD_INFO1_RSPEND_Msk (0x1UL) /*!< RSPEND (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_INFO2 ======================================================== */ + #define R_SDHI0_SD_INFO2_ILA_Pos (15UL) /*!< ILA (Bit 15) */ + #define R_SDHI0_SD_INFO2_ILA_Msk (0x8000UL) /*!< ILA (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CBSY_Pos (14UL) /*!< CBSY (Bit 14) */ + #define R_SDHI0_SD_INFO2_CBSY_Msk (0x4000UL) /*!< CBSY (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Pos (13UL) /*!< SD_CLK_CTRLEN (Bit 13) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Msk (0x2000UL) /*!< SD_CLK_CTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BWE_Pos (9UL) /*!< BWE (Bit 9) */ + #define R_SDHI0_SD_INFO2_BWE_Msk (0x200UL) /*!< BWE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BRE_Pos (8UL) /*!< BRE (Bit 8) */ + #define R_SDHI0_SD_INFO2_BRE_Msk (0x100UL) /*!< BRE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Pos (7UL) /*!< SDD0MON (Bit 7) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Msk (0x80UL) /*!< SDD0MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_RSPTO_Pos (6UL) /*!< RSPTO (Bit 6) */ + #define R_SDHI0_SD_INFO2_RSPTO_Msk (0x40UL) /*!< RSPTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILR_Pos (5UL) /*!< ILR (Bit 5) */ + #define R_SDHI0_SD_INFO2_ILR_Msk (0x20UL) /*!< ILR (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILW_Pos (4UL) /*!< ILW (Bit 4) */ + #define R_SDHI0_SD_INFO2_ILW_Msk (0x10UL) /*!< ILW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_DTO_Pos (3UL) /*!< DTO (Bit 3) */ + #define R_SDHI0_SD_INFO2_DTO_Msk (0x8UL) /*!< DTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ENDE_Pos (2UL) /*!< ENDE (Bit 2) */ + #define R_SDHI0_SD_INFO2_ENDE_Msk (0x4UL) /*!< ENDE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CRCE_Pos (1UL) /*!< CRCE (Bit 1) */ + #define R_SDHI0_SD_INFO2_CRCE_Msk (0x2UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CMDE_Pos (0UL) /*!< CMDE (Bit 0) */ + #define R_SDHI0_SD_INFO2_CMDE_Msk (0x1UL) /*!< CMDE (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO1_MASK ===================================================== */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Pos (9UL) /*!< SDD3INM (Bit 9) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Msk (0x200UL) /*!< SDD3INM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Pos (8UL) /*!< SDD3RMM (Bit 8) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Msk (0x100UL) /*!< SDD3RMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Pos (4UL) /*!< SDCDINM (Bit 4) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Msk (0x10UL) /*!< SDCDINM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Pos (3UL) /*!< SDCDRMM (Bit 3) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Msk (0x8UL) /*!< SDCDRMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Pos (2UL) /*!< ACENDM (Bit 2) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Msk (0x4UL) /*!< ACENDM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Pos (0UL) /*!< RSPENDM (Bit 0) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Msk (0x1UL) /*!< RSPENDM (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO2_MASK ===================================================== */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Pos (15UL) /*!< ILAM (Bit 15) */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Msk (0x8000UL) /*!< ILAM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Pos (9UL) /*!< BWEM (Bit 9) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Msk (0x200UL) /*!< BWEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Pos (8UL) /*!< BREM (Bit 8) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Msk (0x100UL) /*!< BREM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Pos (6UL) /*!< RSPTOM (Bit 6) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Msk (0x40UL) /*!< RSPTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Pos (5UL) /*!< ILRM (Bit 5) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Msk (0x20UL) /*!< ILRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Pos (4UL) /*!< ILWM (Bit 4) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Msk (0x10UL) /*!< ILWM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Pos (3UL) /*!< DTOM (Bit 3) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Msk (0x8UL) /*!< DTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Pos (2UL) /*!< ENDEM (Bit 2) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Msk (0x4UL) /*!< ENDEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Pos (1UL) /*!< CRCEM (Bit 1) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Msk (0x2UL) /*!< CRCEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Pos (0UL) /*!< CMDEM (Bit 0) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Msk (0x1UL) /*!< CMDEM (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_CLK_CTRL ====================================================== */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Pos (9UL) /*!< CLKCTRLEN (Bit 9) */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Msk (0x200UL) /*!< CLKCTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Pos (8UL) /*!< CLKEN (Bit 8) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Msk (0x100UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Msk (0xffUL) /*!< CLKSEL (Bitfield-Mask: 0xff) */ +/* ======================================================== SD_SIZE ======================================================== */ + #define R_SDHI0_SD_SIZE_LEN_Pos (0UL) /*!< LEN (Bit 0) */ + #define R_SDHI0_SD_SIZE_LEN_Msk (0x3ffUL) /*!< LEN (Bitfield-Mask: 0x3ff) */ +/* ======================================================= SD_OPTION ======================================================= */ + #define R_SDHI0_SD_OPTION_WIDTH_Pos (15UL) /*!< WIDTH (Bit 15) */ + #define R_SDHI0_SD_OPTION_WIDTH_Msk (0x8000UL) /*!< WIDTH (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Pos (13UL) /*!< WIDTH8 (Bit 13) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Msk (0x2000UL) /*!< WIDTH8 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Pos (8UL) /*!< TOUTMASK (Bit 8) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Msk (0x100UL) /*!< TOUTMASK (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOP_Pos (4UL) /*!< TOP (Bit 4) */ + #define R_SDHI0_SD_OPTION_TOP_Msk (0xf0UL) /*!< TOP (Bitfield-Mask: 0x0f) */ + #define R_SDHI0_SD_OPTION_CTOP_Pos (0UL) /*!< CTOP (Bit 0) */ + #define R_SDHI0_SD_OPTION_CTOP_Msk (0xfUL) /*!< CTOP (Bitfield-Mask: 0x0f) */ +/* ====================================================== SD_ERR_STS1 ====================================================== */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Pos (12UL) /*!< CRCTK (Bit 12) */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Msk (0x7000UL) /*!< CRCTK (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Pos (11UL) /*!< CRCTKE (Bit 11) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Msk (0x800UL) /*!< CRCTKE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Pos (10UL) /*!< RDCRCE (Bit 10) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Msk (0x400UL) /*!< RDCRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Pos (9UL) /*!< RSPCRCE1 (Bit 9) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Msk (0x200UL) /*!< RSPCRCE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Pos (8UL) /*!< RSPCRCE0 (Bit 8) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Msk (0x100UL) /*!< RSPCRCE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Pos (5UL) /*!< CRCLENE (Bit 5) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Msk (0x20UL) /*!< CRCLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Pos (4UL) /*!< RDLENE (Bit 4) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Msk (0x10UL) /*!< RDLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Pos (3UL) /*!< RSPLENE1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Msk (0x8UL) /*!< RSPLENE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Pos (2UL) /*!< RSPLENE0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Msk (0x4UL) /*!< RSPLENE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Pos (1UL) /*!< CMDE1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Msk (0x2UL) /*!< CMDE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Pos (0UL) /*!< CMDE0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Msk (0x1UL) /*!< CMDE0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_ERR_STS2 ====================================================== */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Pos (6UL) /*!< CRCBSYTO (Bit 6) */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Msk (0x40UL) /*!< CRCBSYTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Pos (5UL) /*!< CRCTO (Bit 5) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Msk (0x20UL) /*!< CRCTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Pos (4UL) /*!< RDTO (Bit 4) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Msk (0x10UL) /*!< RDTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Pos (3UL) /*!< BSYTO1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Msk (0x8UL) /*!< BSYTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Pos (2UL) /*!< BSYTO0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Msk (0x4UL) /*!< BSYTO0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Pos (1UL) /*!< RSPTO1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Msk (0x2UL) /*!< RSPTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Pos (0UL) /*!< RSPTO0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Msk (0x1UL) /*!< RSPTO0 (Bitfield-Mask: 0x01) */ +/* ======================================================== SD_BUF0 ======================================================== */ + #define R_SDHI0_SD_BUF0_SD_BUF_Pos (0UL) /*!< SD_BUF (Bit 0) */ + #define R_SDHI0_SD_BUF0_SD_BUF_Msk (0xffffffffUL) /*!< SD_BUF (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SDIO_MODE ======================================================= */ + #define R_SDHI0_SDIO_MODE_C52PUB_Pos (9UL) /*!< C52PUB (Bit 9) */ + #define R_SDHI0_SDIO_MODE_C52PUB_Msk (0x200UL) /*!< C52PUB (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_IOABT_Pos (8UL) /*!< IOABT (Bit 8) */ + #define R_SDHI0_SDIO_MODE_IOABT_Msk (0x100UL) /*!< IOABT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Pos (2UL) /*!< RWREQ (Bit 2) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Msk (0x4UL) /*!< RWREQ (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_INTEN_Pos (0UL) /*!< INTEN (Bit 0) */ + #define R_SDHI0_SDIO_MODE_INTEN_Msk (0x1UL) /*!< INTEN (Bitfield-Mask: 0x01) */ +/* ====================================================== SDIO_INFO1 ======================================================= */ + #define R_SDHI0_SDIO_INFO1_EXWT_Pos (15UL) /*!< EXWT (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_EXWT_Msk (0x8000UL) /*!< EXWT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos (14UL) /*!< EXPUB52 (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk (0x4000UL) /*!< EXPUB52 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos (0UL) /*!< IOIRQ (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk (0x1UL) /*!< IOIRQ (Bitfield-Mask: 0x01) */ +/* ==================================================== SDIO_INFO1_MASK ==================================================== */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Pos (15UL) /*!< EXWTM (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Msk (0x8000UL) /*!< EXWTM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Pos (14UL) /*!< EXPUB52M (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Msk (0x4000UL) /*!< EXPUB52M (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Pos (0UL) /*!< IOIRQM (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Msk (0x1UL) /*!< IOIRQM (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_DMAEN ======================================================== */ + #define R_SDHI0_SD_DMAEN_DMAEN_Pos (1UL) /*!< DMAEN (Bit 1) */ + #define R_SDHI0_SD_DMAEN_DMAEN_Msk (0x2UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ +/* ======================================================= SOFT_RST ======================================================== */ + #define R_SDHI0_SOFT_RST_SDRST_Pos (0UL) /*!< SDRST (Bit 0) */ + #define R_SDHI0_SOFT_RST_SDRST_Msk (0x1UL) /*!< SDRST (Bitfield-Mask: 0x01) */ +/* ======================================================= SDIF_MODE ======================================================= */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos (8UL) /*!< NOCHKCR (Bit 8) */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk (0x100UL) /*!< NOCHKCR (Bitfield-Mask: 0x01) */ +/* ======================================================= EXT_SWAP ======================================================== */ + #define R_SDHI0_EXT_SWAP_BRSWP_Pos (7UL) /*!< BRSWP (Bit 7) */ + #define R_SDHI0_EXT_SWAP_BRSWP_Msk (0x80UL) /*!< BRSWP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Pos (6UL) /*!< BWSWP (Bit 6) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Msk (0x40UL) /*!< BWSWP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ + #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ + #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ + #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ + #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ + #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ + #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ + #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ + #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ + #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ + #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ + #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ + #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ + #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ + #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ + #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ + #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ + #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ + #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ + #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ + #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ + #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ + #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ + #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ + #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ + #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPR ========================================================== */ + #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ + #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ + #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ + #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= SRAMPRCR ======================================================== */ + #define R_SRAM_SRAMPRCR_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_SRAM_SRAMPRCR_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR_KW_Pos (8UL) /*!< KW (Bit 8) */ + #define R_SRAM_SRAMPRCR_KW_Msk (0xff00UL) /*!< KW (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMPRCR_NS ====================================================== */ + #define R_SRAM_SRAMPRCR_NS_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_SRAM_SRAMPRCR_NS_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR_NS_KW_Pos (8UL) /*!< KW (Bit 8) */ + #define R_SRAM_SRAMPRCR_NS_KW_Msk (0xff00UL) /*!< KW (Bitfield-Mask: 0xff) */ +/* ======================================================= SRAMWTSC ======================================================== */ + #define R_SRAM_SRAMWTSC_WTEN_Pos (0UL) /*!< WTEN (Bit 0) */ + #define R_SRAM_SRAMWTSC_WTEN_Msk (0x1UL) /*!< WTEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMCR0 ======================================================== */ + #define R_SRAM_SRAMCR0_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_SRAMCR0_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR0_ECCMOD_Pos (2UL) /*!< ECCMOD (Bit 2) */ + #define R_SRAM_SRAMCR0_ECCMOD_Msk (0xcUL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ + #define R_SRAM_SRAMCR0_E1STSEN_Pos (4UL) /*!< E1STSEN (Bit 4) */ + #define R_SRAM_SRAMCR0_E1STSEN_Msk (0x10UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR0_TSTBYP_Pos (7UL) /*!< TSTBYP (Bit 7) */ + #define R_SRAM_SRAMCR0_TSTBYP_Msk (0x80UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMCR1 ======================================================== */ + #define R_SRAM_SRAMCR1_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_SRAMCR1_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR1_ECCMOD_Pos (2UL) /*!< ECCMOD (Bit 2) */ + #define R_SRAM_SRAMCR1_ECCMOD_Msk (0xcUL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ + #define R_SRAM_SRAMCR1_E1STSEN_Pos (4UL) /*!< E1STSEN (Bit 4) */ + #define R_SRAM_SRAMCR1_E1STSEN_Msk (0x10UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR1_TSTBYP_Pos (7UL) /*!< TSTBYP (Bit 7) */ + #define R_SRAM_SRAMCR1_TSTBYP_Msk (0x80UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMCR2 ======================================================== */ + #define R_SRAM_SRAMCR2_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_SRAMCR2_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR2_ECCMOD_Pos (2UL) /*!< ECCMOD (Bit 2) */ + #define R_SRAM_SRAMCR2_ECCMOD_Msk (0xcUL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ + #define R_SRAM_SRAMCR2_E1STSEN_Pos (4UL) /*!< E1STSEN (Bit 4) */ + #define R_SRAM_SRAMCR2_E1STSEN_Msk (0x10UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR2_TSTBYP_Pos (7UL) /*!< TSTBYP (Bit 7) */ + #define R_SRAM_SRAMCR2_TSTBYP_Msk (0x80UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMCR3 ======================================================== */ + #define R_SRAM_SRAMCR3_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_SRAMCR3_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR3_ECCMOD_Pos (2UL) /*!< ECCMOD (Bit 2) */ + #define R_SRAM_SRAMCR3_ECCMOD_Msk (0xcUL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ + #define R_SRAM_SRAMCR3_E1STSEN_Pos (4UL) /*!< E1STSEN (Bit 4) */ + #define R_SRAM_SRAMCR3_E1STSEN_Msk (0x10UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR3_TSTBYP_Pos (7UL) /*!< TSTBYP (Bit 7) */ + #define R_SRAM_SRAMCR3_TSTBYP_Msk (0x80UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ====================================================== SRAMECCRGN0 ====================================================== */ + #define R_SRAM_SRAMECCRGN0_ECCRGN_Pos (0UL) /*!< ECCRGN (Bit 0) */ + #define R_SRAM_SRAMECCRGN0_ECCRGN_Msk (0x7UL) /*!< ECCRGN (Bitfield-Mask: 0x07) */ +/* ====================================================== SRAMECCRGN1 ====================================================== */ + #define R_SRAM_SRAMECCRGN1_ECCRGN_Pos (0UL) /*!< ECCRGN (Bit 0) */ + #define R_SRAM_SRAMECCRGN1_ECCRGN_Msk (0x7UL) /*!< ECCRGN (Bitfield-Mask: 0x07) */ +/* ====================================================== SRAMECCRGN2 ====================================================== */ + #define R_SRAM_SRAMECCRGN2_ECCRGN_Pos (0UL) /*!< ECCRGN (Bit 0) */ + #define R_SRAM_SRAMECCRGN2_ECCRGN_Msk (0x7UL) /*!< ECCRGN (Bitfield-Mask: 0x07) */ +/* ====================================================== SRAMECCRGN3 ====================================================== */ + #define R_SRAM_SRAMECCRGN3_ECCRGN_Pos (0UL) /*!< ECCRGN (Bit 0) */ + #define R_SRAM_SRAMECCRGN3_ECCRGN_Msk (0x7UL) /*!< ECCRGN (Bitfield-Mask: 0x07) */ +/* ======================================================== SRAMESR ======================================================== */ + #define R_SRAM_SRAMESR_ERR0_Pos (0UL) /*!< ERR0 (Bit 0) */ + #define R_SRAM_SRAMESR_ERR0_Msk (0x1UL) /*!< ERR0 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMESR_ERR1_Pos (1UL) /*!< ERR1 (Bit 1) */ + #define R_SRAM_SRAMESR_ERR1_Msk (0x2UL) /*!< ERR1 (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMESCLR ======================================================= */ + #define R_SRAM_SRAMESCLR_CLR0_Pos (0UL) /*!< CLR0 (Bit 0) */ + #define R_SRAM_SRAMESCLR_CLR0_Msk (0x1UL) /*!< CLR0 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMESCLR_CLR1_Pos (1UL) /*!< CLR1 (Bit 1) */ + #define R_SRAM_SRAMESCLR_CLR1_Msk (0x2UL) /*!< CLR1 (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMEAR00 ======================================================= */ + #define R_SRAM_SRAMEAR00_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR00_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRAMEAR10 ======================================================= */ + #define R_SRAM_SRAMEAR10_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR10_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRAMEAR20 ======================================================= */ + #define R_SRAM_SRAMEAR20_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR20_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRAMEAR30 ======================================================= */ + #define R_SRAM_SRAMEAR30_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR30_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRAMEAR01 ======================================================= */ + #define R_SRAM_SRAMEAR01_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR01_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRAMEAR11 ======================================================= */ + #define R_SRAM_SRAMEAR11_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR11_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRAMEAR21 ======================================================= */ + #define R_SRAM_SRAMEAR21_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR21_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRAMEAR31 ======================================================= */ + #define R_SRAM_SRAMEAR31_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR31_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SSICR ========================================================= */ + #define R_SSI0_SSICR_CKS_Pos (30UL) /*!< CKS (Bit 30) */ + #define R_SSI0_SSICR_CKS_Msk (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TUIEN_Pos (29UL) /*!< TUIEN (Bit 29) */ + #define R_SSI0_SSICR_TUIEN_Msk (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TOIEN_Pos (28UL) /*!< TOIEN (Bit 28) */ + #define R_SSI0_SSICR_TOIEN_Msk (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_RUIEN_Pos (27UL) /*!< RUIEN (Bit 27) */ + #define R_SSI0_SSICR_RUIEN_Msk (0x8000000UL) /*!< RUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_ROIEN_Pos (26UL) /*!< ROIEN (Bit 26) */ + #define R_SSI0_SSICR_ROIEN_Msk (0x4000000UL) /*!< ROIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_IIEN_Pos (25UL) /*!< IIEN (Bit 25) */ + #define R_SSI0_SSICR_IIEN_Msk (0x2000000UL) /*!< IIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_FRM_Pos (22UL) /*!< FRM (Bit 22) */ + #define R_SSI0_SSICR_FRM_Msk (0xc00000UL) /*!< FRM (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSICR_DWL_Pos (19UL) /*!< DWL (Bit 19) */ + #define R_SSI0_SSICR_DWL_Msk (0x380000UL) /*!< DWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_SWL_Pos (16UL) /*!< SWL (Bit 16) */ + #define R_SSI0_SSICR_SWL_Msk (0x70000UL) /*!< SWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_MST_Pos (14UL) /*!< MST (Bit 14) */ + #define R_SSI0_SSICR_MST_Msk (0x4000UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_BCKP_Pos (13UL) /*!< BCKP (Bit 13) */ + #define R_SSI0_SSICR_BCKP_Msk (0x2000UL) /*!< BCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_LRCKP_Pos (12UL) /*!< LRCKP (Bit 12) */ + #define R_SSI0_SSICR_LRCKP_Msk (0x1000UL) /*!< LRCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SPDP_Pos (11UL) /*!< SPDP (Bit 11) */ + #define R_SSI0_SSICR_SPDP_Msk (0x800UL) /*!< SPDP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SDTA_Pos (10UL) /*!< SDTA (Bit 10) */ + #define R_SSI0_SSICR_SDTA_Msk (0x400UL) /*!< SDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_PDTA_Pos (9UL) /*!< PDTA (Bit 9) */ + #define R_SSI0_SSICR_PDTA_Msk (0x200UL) /*!< PDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_DEL_Pos (8UL) /*!< DEL (Bit 8) */ + #define R_SSI0_SSICR_DEL_Msk (0x100UL) /*!< DEL (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_CKDV_Pos (4UL) /*!< CKDV (Bit 4) */ + #define R_SSI0_SSICR_CKDV_Msk (0xf0UL) /*!< CKDV (Bitfield-Mask: 0x0f) */ + #define R_SSI0_SSICR_MUEN_Pos (3UL) /*!< MUEN (Bit 3) */ + #define R_SSI0_SSICR_MUEN_Msk (0x8UL) /*!< MUEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TEN_Pos (1UL) /*!< TEN (Bit 1) */ + #define R_SSI0_SSICR_TEN_Msk (0x2UL) /*!< TEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_REN_Pos (0UL) /*!< REN (Bit 0) */ + #define R_SSI0_SSICR_REN_Msk (0x1UL) /*!< REN (Bitfield-Mask: 0x01) */ +/* ========================================================= SSISR ========================================================= */ + #define R_SSI0_SSISR_TUIRQ_Pos (29UL) /*!< TUIRQ (Bit 29) */ + #define R_SSI0_SSISR_TUIRQ_Msk (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TOIRQ_Pos (28UL) /*!< TOIRQ (Bit 28) */ + #define R_SSI0_SSISR_TOIRQ_Msk (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RUIRQ_Pos (27UL) /*!< RUIRQ (Bit 27) */ + #define R_SSI0_SSISR_RUIRQ_Msk (0x8000000UL) /*!< RUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_ROIRQ_Pos (26UL) /*!< ROIRQ (Bit 26) */ + #define R_SSI0_SSISR_ROIRQ_Msk (0x4000000UL) /*!< ROIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IIRQ_Pos (25UL) /*!< IIRQ (Bit 25) */ + #define R_SSI0_SSISR_IIRQ_Msk (0x2000000UL) /*!< IIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TCHNO_Pos (5UL) /*!< TCHNO (Bit 5) */ + #define R_SSI0_SSISR_TCHNO_Msk (0x60UL) /*!< TCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_TSWNO_Pos (4UL) /*!< TSWNO (Bit 4) */ + #define R_SSI0_SSISR_TSWNO_Msk (0x10UL) /*!< TSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RCHNO_Pos (2UL) /*!< RCHNO (Bit 2) */ + #define R_SSI0_SSISR_RCHNO_Msk (0xcUL) /*!< RCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_RSWNO_Pos (1UL) /*!< RSWNO (Bit 1) */ + #define R_SSI0_SSISR_RSWNO_Msk (0x2UL) /*!< RSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IDST_Pos (0UL) /*!< IDST (Bit 0) */ + #define R_SSI0_SSISR_IDST_Msk (0x1UL) /*!< IDST (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFCR ========================================================= */ + #define R_SSI0_SSIFCR_AUCKE_Pos (31UL) /*!< AUCKE (Bit 31) */ + #define R_SSI0_SSIFCR_AUCKE_Msk (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_SSIRST_Pos (16UL) /*!< SSIRST (Bit 16) */ + #define R_SSI0_SSIFCR_SSIRST_Msk (0x10000UL) /*!< SSIRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TTRG_Pos (6UL) /*!< TTRG (Bit 6) */ + #define R_SSI0_SSIFCR_TTRG_Msk (0xc0UL) /*!< TTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_RTRG_Pos (4UL) /*!< RTRG (Bit 4) */ + #define R_SSI0_SSIFCR_RTRG_Msk (0x30UL) /*!< RTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_TIE_Pos (3UL) /*!< TIE (Bit 3) */ + #define R_SSI0_SSIFCR_TIE_Msk (0x8UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RIE_Pos (2UL) /*!< RIE (Bit 2) */ + #define R_SSI0_SSIFCR_RIE_Msk (0x4UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TFRST_Pos (1UL) /*!< TFRST (Bit 1) */ + #define R_SSI0_SSIFCR_TFRST_Msk (0x2UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RFRST_Pos (0UL) /*!< RFRST (Bit 0) */ + #define R_SSI0_SSIFCR_RFRST_Msk (0x1UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_BSW_Pos (11UL) /*!< BSW (Bit 11) */ + #define R_SSI0_SSIFCR_BSW_Msk (0x800UL) /*!< BSW (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFSR ========================================================= */ + #define R_SSI0_SSIFSR_TDC_Pos (24UL) /*!< TDC (Bit 24) */ + #define R_SSI0_SSIFSR_TDC_Msk (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_TDE_Pos (16UL) /*!< TDE (Bit 16) */ + #define R_SSI0_SSIFSR_TDE_Msk (0x10000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFSR_RDC_Pos (8UL) /*!< RDC (Bit 8) */ + #define R_SSI0_SSIFSR_RDC_Msk (0x3f00UL) /*!< RDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_RDF_Pos (0UL) /*!< RDF (Bit 0) */ + #define R_SSI0_SSIFSR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFTDR ======================================================== */ + #define R_SSI0_SSIFTDR_SSIFTDR_Pos (0UL) /*!< SSIFTDR (Bit 0) */ + #define R_SSI0_SSIFTDR_SSIFTDR_Msk (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFTDR16 ======================================================= */ +/* ======================================================= SSIFTDR8 ======================================================== */ +/* ======================================================== SSIFRDR ======================================================== */ + #define R_SSI0_SSIFRDR_SSIFRDR_Pos (0UL) /*!< SSIFRDR (Bit 0) */ + #define R_SSI0_SSIFRDR_SSIFRDR_Msk (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFRDR16 ======================================================= */ +/* ======================================================= SSIFRDR8 ======================================================== */ +/* ======================================================== SSIOFR ========================================================= */ + #define R_SSI0_SSIOFR_BCKASTP_Pos (9UL) /*!< BCKASTP (Bit 9) */ + #define R_SSI0_SSIOFR_BCKASTP_Msk (0x200UL) /*!< BCKASTP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_LRCONT_Pos (8UL) /*!< LRCONT (Bit 8) */ + #define R_SSI0_SSIOFR_LRCONT_Msk (0x100UL) /*!< LRCONT (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_OMOD_Pos (0UL) /*!< OMOD (Bit 0) */ + #define R_SSI0_SSIOFR_OMOD_Msk (0x3UL) /*!< OMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== SSISCR ========================================================= */ + #define R_SSI0_SSISCR_TDES_Pos (8UL) /*!< TDES (Bit 8) */ + #define R_SSI0_SSISCR_TDES_Msk (0x1f00UL) /*!< TDES (Bitfield-Mask: 0x1f) */ + #define R_SSI0_SSISCR_RDFS_Pos (0UL) /*!< RDFS (Bit 0) */ + #define R_SSI0_SSISCR_RDFS_Msk (0x1fUL) /*!< RDFS (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SBYCR ========================================================= */ + #define R_SYSTEM_SBYCR_OPE_Pos (6UL) /*!< OPE (Bit 6) */ + #define R_SYSTEM_SBYCR_OPE_Msk (0x40UL) /*!< OPE (Bitfield-Mask: 0x01) */ +/* ========================================================= SSCR2 ========================================================= */ + #define R_SYSTEM_SSCR2_SS2FSR_Pos (0UL) /*!< SS2FSR (Bit 0) */ + #define R_SYSTEM_SSCR2_SS2FSR_Msk (0x1UL) /*!< SS2FSR (Bitfield-Mask: 0x01) */ +/* ========================================================= MRSCR ========================================================= */ + #define R_SYSTEM_MRSCR_MRSWCF_Pos (0UL) /*!< MRSWCF (Bit 0) */ + #define R_SYSTEM_MRSCR_MRSWCF_Msk (0x1UL) /*!< MRSWCF (Bitfield-Mask: 0x01) */ +/* ========================================================= VSCR ========================================================== */ + #define R_SYSTEM_VSCR_VSCM_Pos (0UL) /*!< VSCM (Bit 0) */ + #define R_SYSTEM_VSCR_VSCM_Msk (0x7UL) /*!< VSCM (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_VSCR_VSCMTSF_Pos (4UL) /*!< VSCMTSF (Bit 4) */ + #define R_SYSTEM_VSCR_VSCMTSF_Msk (0x10UL) /*!< VSCMTSF (Bitfield-Mask: 0x01) */ +/* ======================================================== SRMONR ========================================================= */ + #define R_SYSTEM_SRMONR_MON_Pos (0UL) /*!< MON (Bit 0) */ + #define R_SYSTEM_SRMONR_MON_Msk (0x3UL) /*!< MON (Bitfield-Mask: 0x03) */ +/* ======================================================= SCKDIVCR ======================================================== */ + #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0xfUL) /*!< PCKD (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0xf0UL) /*!< PCKC (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0xf00UL) /*!< PCKB (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0xf000UL) /*!< PCKA (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ + #define R_SYSTEM_SCKDIVCR_BCK_Msk (0xf0000UL) /*!< BCK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_PCKE_Pos (20UL) /*!< PCKE (Bit 20) */ + #define R_SYSTEM_SCKDIVCR_PCKE_Msk (0xf00000UL) /*!< PCKE (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ + #define R_SYSTEM_SCKDIVCR_ICK_Msk (0xf000000UL) /*!< ICK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ + #define R_SYSTEM_SCKDIVCR_FCK_Msk (0xf0000000UL) /*!< FCK (Bitfield-Mask: 0x0f) */ +/* ======================================================= SCKDIVCR2 ======================================================= */ + #define R_SYSTEM_SCKDIVCR2_CPUCK_Pos (0UL) /*!< CPUCK (Bit 0) */ + #define R_SYSTEM_SCKDIVCR2_CPUCK_Msk (0xfUL) /*!< CPUCK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR2_CPUCK1_Pos (4UL) /*!< CPUCK1 (Bit 4) */ + #define R_SYSTEM_SCKDIVCR2_CPUCK1_Msk (0xf0UL) /*!< CPUCK1 (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR2_NPUCK_Pos (8UL) /*!< NPUCK (Bit 8) */ + #define R_SYSTEM_SCKDIVCR2_NPUCK_Msk (0xf00UL) /*!< NPUCK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR2_MRICK_Pos (12UL) /*!< MRICK (Bit 12) */ + #define R_SYSTEM_SCKDIVCR2_MRICK_Msk (0xf000UL) /*!< MRICK (Bitfield-Mask: 0x0f) */ +/* ======================================================== SCKSCR ========================================================= */ + #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ +/* ========================================================= PLLCR ========================================================= */ + #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= BCKCR ========================================================= */ + #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BCKCR_EBCKASEL_Pos (7UL) /*!< EBCKASEL (Bit 7) */ + #define R_SYSTEM_BCKCR_EBCKASEL_Msk (0x80UL) /*!< EBCKASEL (Bitfield-Mask: 0x01) */ +/* ======================================================== MEMWAIT ======================================================== */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCCR ========================================================= */ + #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ + #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR ========================================================= */ + #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ + #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOCOCR ========================================================= */ + #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ + #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR1 ========================================================= */ + #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ + #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR2 ========================================================= */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ +/* ========================================================= OSCSF ========================================================= */ + #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ + #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ + #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ + #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ + #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ +/* ========================================================= CKOCR ========================================================= */ + #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ + #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ + #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ + #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== TRCKCR ========================================================= */ + #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ + #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_TRCKCR_TRCKSEL_Pos (4UL) /*!< TRCKSEL (Bit 4) */ + #define R_SYSTEM_TRCKCR_TRCKSEL_Msk (0x10UL) /*!< TRCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDCR ========================================================= */ + #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ + #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDSR ========================================================= */ + #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ + #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ +/* ======================================================== OSCMONR ======================================================== */ + #define R_SYSTEM_OSCMONR_MOCOMON_Pos (1UL) /*!< MOCOMON (Bit 1) */ + #define R_SYSTEM_OSCMONR_MOCOMON_Msk (0x2UL) /*!< MOCOMON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCMONR_LOCOMON_Pos (2UL) /*!< LOCOMON (Bit 2) */ + #define R_SYSTEM_OSCMONR_LOCOMON_Msk (0x4UL) /*!< LOCOMON (Bitfield-Mask: 0x01) */ +/* ======================================================== PLL2CR ========================================================= */ + #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR2 ======================================================== */ + #define R_SYSTEM_PLLCCR2_PLODIVP_Pos (0UL) /*!< PLODIVP (Bit 0) */ + #define R_SYSTEM_PLLCCR2_PLODIVP_Msk (0xfUL) /*!< PLODIVP (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_PLLCCR2_PLODIVQ_Pos (4UL) /*!< PLODIVQ (Bit 4) */ + #define R_SYSTEM_PLLCCR2_PLODIVQ_Msk (0xf0UL) /*!< PLODIVQ (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_PLLCCR2_PLODIVR_Pos (8UL) /*!< PLODIVR (Bit 8) */ + #define R_SYSTEM_PLLCCR2_PLODIVR_Msk (0xf00UL) /*!< PLODIVR (Bitfield-Mask: 0x0f) */ +/* ========================================================= LPOPT ========================================================= */ + #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */ + #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */ + #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PLL2CCR2 ======================================================== */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos (0UL) /*!< PL2ODIVP (Bit 0) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk (0xfUL) /*!< PL2ODIVP (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos (4UL) /*!< PL2ODIVQ (Bit 4) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk (0xf0UL) /*!< PL2ODIVQ (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos (8UL) /*!< PL2ODIVR (Bit 8) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk (0xf00UL) /*!< PL2ODIVR (Bitfield-Mask: 0x0f) */ +/* ======================================================= SLCDSCKCR ======================================================= */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== EBCKOCR ======================================================== */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCKOCR ======================================================== */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ +/* ====================================================== SCICKDIVCR ======================================================= */ + #define R_SYSTEM_SCICKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_SCICKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== SCICKCR ======================================================== */ + #define R_SYSTEM_SCICKCR_SCICKSEL_Pos (0UL) /*!< SCICKSEL (Bit 0) */ + #define R_SYSTEM_SCICKCR_SCICKSEL_Msk (0xfUL) /*!< SCICKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCICKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_SCICKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SCICKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_SCICKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== SPICKDIVCR ======================================================= */ + #define R_SYSTEM_SPICKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_SPICKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== SPICKCR ======================================================== */ + #define R_SYSTEM_SPICKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SPICKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SPICKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_SPICKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SPICKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_SPICKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCCKDIVCR ======================================================= */ + #define R_SYSTEM_ADCCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_ADCCKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCCKCR ======================================================== */ + #define R_SYSTEM_ADCCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_ADCCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_ADCCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_ADCCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_ADCCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_ADCCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== GPTCKDIVCR ======================================================= */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0xfUL) /*!< GPTCKDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== GPTCKCR ======================================================== */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0xfUL) /*!< GPTCKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== LCDCKDIVCR ======================================================= */ + #define R_SYSTEM_LCDCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_LCDCKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== LCDCKCR ======================================================== */ + #define R_SYSTEM_LCDCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_LCDCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_LCDCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_LCDCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LCDCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_LCDCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= MOCOUTCR ======================================================== */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================= HOCOUTCR ======================================================== */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ +/* ====================================================== USBCKDIVCR ======================================================= */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0xfUL) /*!< USBCKDIV (Bitfield-Mask: 0x0f) */ +/* ====================================================== OCTACKDIVCR ====================================================== */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0xfUL) /*!< OCTACKDIV (Bitfield-Mask: 0x0f) */ +/* ===================================================== CANFDCKDIVCR ====================================================== */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0xfUL) /*!< CANFDCKDIV (Bitfield-Mask: 0x0f) */ +/* ===================================================== USB60CKDIVCR ====================================================== */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0xfUL) /*!< USB60CKDIV (Bitfield-Mask: 0x0f) */ +/* ====================================================== I3CCKDIVCR ======================================================= */ + #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos (0UL) /*!< I3CCKDIV (Bit 0) */ + #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk (0xfUL) /*!< I3CCKDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== USBCKCR ======================================================== */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0xfUL) /*!< USBCKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= OCTACKCR ======================================================== */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0xfUL) /*!< OCTACKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= CANFDCKCR ======================================================= */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0xfUL) /*!< CANFDCKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= USB60CKCR ======================================================= */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== I3CCKCR ======================================================== */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0xfUL) /*!< I3CCKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCSCR ======================================================== */ + #define R_SYSTEM_MOSCSCR_MOSCSOKP_Pos (0UL) /*!< MOSCSOKP (Bit 0) */ + #define R_SYSTEM_MOSCSCR_MOSCSOKP_Msk (0x1UL) /*!< MOSCSOKP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOSCR ======================================================== */ + #define R_SYSTEM_HOCOSCR_HOSCSOKP_Pos (0UL) /*!< HOSCSOKP (Bit 0) */ + #define R_SYSTEM_HOCOSCR_HOSCSOKP_Msk (0x1UL) /*!< HOSCSOKP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOCOSCR ======================================================== */ + #define R_SYSTEM_MOCOSCR_MOCOSOKP_Pos (0UL) /*!< MOCOSOKP (Bit 0) */ + #define R_SYSTEM_MOCOSCR_MOCOSOKP_Msk (0x1UL) /*!< MOCOSOKP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLSTOP ========================================================= */ + #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ +/* ========================================================= PSMCR ========================================================= */ + #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ + #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ +/* ========================================================= OPCCR ========================================================= */ + #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ + #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ +/* ======================================================= MOSCWTCR ======================================================== */ + #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ +/* ======================================================= HOCOWTCR ======================================================== */ + #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ +/* ======================================================== SOPCCR ========================================================= */ + #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ + #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR ========================================================= */ + #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCCR_PLLMULNF_Pos (6UL) /*!< PLLMULNF (Bit 6) */ + #define R_SYSTEM_PLLCCR_PLLMULNF_Msk (0xc0UL) /*!< PLLMULNF (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x1ff00UL) /*!< PLLMUL (Bitfield-Mask: 0x1ff) */ +/* ======================================================== RSTSR1 ========================================================= */ + #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ + #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ + #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CLURF_Pos (4UL) /*!< CLURF (Bit 4) */ + #define R_SYSTEM_RSTSR1_CLURF_Msk (0x10UL) /*!< CLURF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_LM0RF_Pos (5UL) /*!< LM0RF (Bit 5) */ + #define R_SYSTEM_RSTSR1_LM0RF_Msk (0x20UL) /*!< LM0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CMRF_Pos (14UL) /*!< CMRF (Bit 14) */ + #define R_SYSTEM_RSTSR1_CMRF_Msk (0x4000UL) /*!< CMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDT1RF_Pos (17UL) /*!< WDT1RF (Bit 17) */ + #define R_SYSTEM_RSTSR1_WDT1RF_Msk (0x20000UL) /*!< WDT1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CLU1RF_Pos (20UL) /*!< CLU1RF (Bit 20) */ + #define R_SYSTEM_RSTSR1_CLU1RF_Msk (0x100000UL) /*!< CLU1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_LM1RF_Pos (21UL) /*!< LM1RF (Bit 21) */ + #define R_SYSTEM_RSTSR1_LM1RF_Msk (0x200000UL) /*!< LM1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_NWRF_Pos (22UL) /*!< NWRF (Bit 22) */ + #define R_SYSTEM_RSTSR1_NWRF_Msk (0x400000UL) /*!< NWRF (Bitfield-Mask: 0x01) */ +/* ======================================================== PLL2CCR ======================================================== */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CCR_PLL2MULNF_Pos (6UL) /*!< PLL2MULNF (Bit 6) */ + #define R_SYSTEM_PLL2CCR_PLL2MULNF_Msk (0xc0UL) /*!< PLL2MULNF (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x1ff00UL) /*!< PLL2MUL (Bitfield-Mask: 0x1ff) */ +/* ======================================================== SYRACCR ======================================================== */ + #define R_SYSTEM_SYRACCR_BUSY_Pos (0UL) /*!< BUSY (Bit 0) */ + #define R_SYSTEM_SYRACCR_BUSY_Msk (0x1UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +/* ====================================================== USBCKCR_ALT ====================================================== */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= SDADCCKCR ======================================================= */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================= BCKADIVCR ======================================================= */ + #define R_SYSTEM_BCKADIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_BCKADIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ====================================================== ESWCKDIVCR ======================================================= */ + #define R_SYSTEM_ESWCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_ESWCKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ====================================================== ESWPCKDIVCR ====================================================== */ + #define R_SYSTEM_ESWPCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_ESWPCKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ====================================================== ESCCKDIVCR ======================================================= */ + #define R_SYSTEM_ESCCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_ESCCKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ====================================================== ETHPCKDIVCR ====================================================== */ + #define R_SYSTEM_ETHPCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_ETHPCKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCKACR ========================================================= */ + #define R_SYSTEM_BCKACR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_BCKACR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_BCKACR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_BCKACR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BCKACR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_BCKACR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== ESWCKCR ======================================================== */ + #define R_SYSTEM_ESWCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_ESWCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_ESWCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_ESWCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_ESWCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_ESWCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= ESWPCKCR ======================================================== */ + #define R_SYSTEM_ESWPCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_ESWPCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_ESWPCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_ESWPCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_ESWPCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_ESWPCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== ESCCKCR ======================================================== */ + #define R_SYSTEM_ESCCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_ESCCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_ESCCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_ESCCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_ESCCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_ESCCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= ETHPCKCR ======================================================== */ + #define R_SYSTEM_ETHPCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_ETHPCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_ETHPCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_ETHPCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_ETHPCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_ETHPCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR1 ======================================================== */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR1 ======================================================== */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD3CR1 ======================================================== */ + #define R_SYSTEM_LVD3CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD3CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD3CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD3CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD4CR1 ======================================================== */ + #define R_SYSTEM_LVD4CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD4CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD4CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD4CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD5CR1 ======================================================== */ + #define R_SYSTEM_LVD5CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD5CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD5CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD5CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1SR ========================================================= */ + #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2SR ========================================================= */ + #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD3SR ========================================================= */ + #define R_SYSTEM_LVD3SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD3SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD3SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD3SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ +/* ======================================================= CRVSYSCR ======================================================== */ + #define R_SYSTEM_CRVSYSCR_CRVEN_Pos (0UL) /*!< CRVEN (Bit 0) */ + #define R_SYSTEM_CRVSYSCR_CRVEN_Msk (0x1UL) /*!< CRVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== CPUDSCR ======================================================== */ + #define R_SYSTEM_CPUDSCR_PGD_Pos (0UL) /*!< PGD (Bit 0) */ + #define R_SYSTEM_CPUDSCR_PGD_Msk (0x1UL) /*!< PGD (Bitfield-Mask: 0x01) */ +/* ======================================================== PDCTRGD ======================================================== */ + #define R_SYSTEM_PDCTRGD_PDDE_Pos (0UL) /*!< PDDE (Bit 0) */ + #define R_SYSTEM_PDCTRGD_PDDE_Msk (0x1UL) /*!< PDDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PDCTRGD_PDCSF_Pos (6UL) /*!< PDCSF (Bit 6) */ + #define R_SYSTEM_PDCTRGD_PDCSF_Msk (0x40UL) /*!< PDCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PDCTRGD_PDPGSF_Pos (7UL) /*!< PDPGSF (Bit 7) */ + #define R_SYSTEM_PDCTRGD_PDPGSF_Msk (0x80UL) /*!< PDPGSF (Bitfield-Mask: 0x01) */ +/* ======================================================= PDCTRNPU ======================================================== */ + #define R_SYSTEM_PDCTRNPU_PDDE_Pos (0UL) /*!< PDDE (Bit 0) */ + #define R_SYSTEM_PDCTRNPU_PDDE_Msk (0x1UL) /*!< PDDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PDCTRNPU_PDCSF_Pos (6UL) /*!< PDCSF (Bit 6) */ + #define R_SYSTEM_PDCTRNPU_PDCSF_Msk (0x40UL) /*!< PDCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PDCTRNPU_PDPGSF_Pos (7UL) /*!< PDPGSF (Bit 7) */ + #define R_SYSTEM_PDCTRNPU_PDPGSF_Msk (0x80UL) /*!< PDPGSF (Bitfield-Mask: 0x01) */ +/* ======================================================= PDCTRESWM ======================================================= */ + #define R_SYSTEM_PDCTRESWM_PDDE_Pos (0UL) /*!< PDDE (Bit 0) */ + #define R_SYSTEM_PDCTRESWM_PDDE_Msk (0x1UL) /*!< PDDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PDCTRESWM_PDCSF_Pos (6UL) /*!< PDCSF (Bit 6) */ + #define R_SYSTEM_PDCTRESWM_PDCSF_Msk (0x40UL) /*!< PDCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PDCTRESWM_PDPGSF_Pos (7UL) /*!< PDPGSF (Bit 7) */ + #define R_SYSTEM_PDCTRESWM_PDPGSF_Msk (0x80UL) /*!< PDPGSF (Bitfield-Mask: 0x01) */ +/* ======================================================= PDRAMSCR0 ======================================================= */ + #define R_SYSTEM_PDRAMSCR0_RKEEP_Pos (0UL) /*!< RKEEP (Bit 0) */ + #define R_SYSTEM_PDRAMSCR0_RKEEP_Msk (0x1UL) /*!< RKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================= PDRAMSCR1 ======================================================= */ + #define R_SYSTEM_PDRAMSCR1_RKEEP_Pos (0UL) /*!< RKEEP (Bit 0) */ + #define R_SYSTEM_PDRAMSCR1_RKEEP_Msk (0x1UL) /*!< RKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================= VBRSABAR ======================================================== */ + #define R_SYSTEM_VBRSABAR_SABA_Pos (0UL) /*!< SABA (Bit 0) */ + #define R_SYSTEM_VBRSABAR_SABA_Msk (0xffffUL) /*!< SABA (Bitfield-Mask: 0xffff) */ +/* ======================================================= VBRPABARS ======================================================= */ + #define R_SYSTEM_VBRPABARS_PABAS_Pos (0UL) /*!< PABAS (Bit 0) */ + #define R_SYSTEM_VBRPABARS_PABAS_Msk (0xffffUL) /*!< PABAS (Bitfield-Mask: 0xffff) */ +/* ====================================================== VBRPABARNS ======================================================= */ + #define R_SYSTEM_VBRPABARNS_PABANS_Pos (0UL) /*!< PABANS (Bit 0) */ + #define R_SYSTEM_VBRPABARNS_PABANS_Msk (0xffffUL) /*!< PABANS (Bitfield-Mask: 0xffff) */ +/* ======================================================== CGFSAR ========================================================= */ + #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ + #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSAR ========================================================= */ + #define R_SYSTEM_RSTSAR_NONSEC_Pos (0UL) /*!< NONSEC (Bit 0) */ + #define R_SYSTEM_RSTSAR_NONSEC_Msk (0x1UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ +/* ======================================================== LPMSAR ========================================================= */ + #define R_SYSTEM_LPMSAR_NONSEC_Pos (0UL) /*!< NONSEC (Bit 0) */ + #define R_SYSTEM_LPMSAR_NONSEC_Msk (0x1UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDSAR ========================================================= */ + #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== BBFSAR ========================================================= */ + #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC3_Pos (3UL) /*!< NONSEC3 (Bit 3) */ + #define R_SYSTEM_BBFSAR_NONSEC3_Msk (0x8UL) /*!< NONSEC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ + #define R_SYSTEM_BBFSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC5_Pos (5UL) /*!< NONSEC5 (Bit 5) */ + #define R_SYSTEM_BBFSAR_NONSEC5_Msk (0x20UL) /*!< NONSEC5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC6_Pos (6UL) /*!< NONSEC6 (Bit 6) */ + #define R_SYSTEM_BBFSAR_NONSEC6_Msk (0x40UL) /*!< NONSEC6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC7_Pos (7UL) /*!< NONSEC7 (Bit 7) */ + #define R_SYSTEM_BBFSAR_NONSEC7_Msk (0x80UL) /*!< NONSEC7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ + #define R_SYSTEM_BBFSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ +/* ======================================================== PGCSAR ========================================================= */ + #define R_SYSTEM_PGCSAR_NONSEC_Pos (0UL) /*!< NONSEC (Bit 0) */ + #define R_SYSTEM_PGCSAR_NONSEC_Msk (0x1UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR ========================================================= */ + #define R_SYSTEM_DPFSAR_DPFSA_Pos (0UL) /*!< DPFSA (Bit 0) */ + #define R_SYSTEM_DPFSAR_DPFSA_Msk (0x1UL) /*!< DPFSA (Bitfield-Mask: 0x01) */ +/* ======================================================== RSCSAR ========================================================= */ + #define R_SYSTEM_RSCSAR_RSCSA_Pos (0UL) /*!< RSCSA (Bit 0) */ + #define R_SYSTEM_RSCSAR_RSCSA_Msk (0x1UL) /*!< RSCSA (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR1 ======================================================== */ + #define R_SYSTEM_DPFSAR1_DPFSA_Pos (0UL) /*!< DPFSA (Bit 0) */ + #define R_SYSTEM_DPFSAR1_DPFSA_Msk (0x1UL) /*!< DPFSA (Bitfield-Mask: 0x01) */ +/* ========================================================= PRCR ========================================================== */ + #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC5_Pos (5UL) /*!< PRC5 (Bit 5) */ + #define R_SYSTEM_PRCR_PRC5_Msk (0x20UL) /*!< PRC5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== PRCR_NS ======================================================== */ + #define R_SYSTEM_PRCR_NS_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_NS_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_NS_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_NS_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_NS_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_NS_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_NS_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_NS_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_NS_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_NS_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= LOCOUTCR ======================================================== */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================== STCONR ========================================================= */ + #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ + #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ +/* ======================================================== FWEPROR ======================================================== */ + #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ + #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ +/* ======================================================= VBATTMONR ======================================================= */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTCR1 ========================================================= */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== DCDCCTL ======================================================== */ + #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ + #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ + #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ +/* ======================================================== VCCSEL ========================================================= */ + #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ + #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SOMRG ========================================================= */ + #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ + #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ +/* ======================================================== VBTCR2 ========================================================= */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ +/* ========================================================= VBTSR ========================================================= */ + #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ + #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTCMPCR ======================================================== */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTLVDICR ======================================================= */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTWCTLR ======================================================== */ + #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ + #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH0OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH1OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH2OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTOCTLR ======================================================== */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWTER ======================================================== */ + #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ + #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ + #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ + #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWEGR ======================================================== */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWFR ========================================================= */ + #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ + #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ + #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ + #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSBYCR ======================================================== */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_DPSBYCR_DCSSMODE_Pos (2UL) /*!< DCSSMODE (Bit 2) */ + #define R_SYSTEM_DPSBYCR_DCSSMODE_Msk (0xcUL) /*!< DCSSMODE (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER0 ======================================================== */ + #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER1 ======================================================== */ + #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER2 ======================================================== */ + #define R_SYSTEM_DPSIER2_DPVD1IE_Pos (0UL) /*!< DPVD1IE (Bit 0) */ + #define R_SYSTEM_DPSIER2_DPVD1IE_Msk (0x1UL) /*!< DPVD1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DPVD2IE_Pos (1UL) /*!< DPVD2IE (Bit 1) */ + #define R_SYSTEM_DPSIER2_DPVD2IE_Msk (0x2UL) /*!< DPVD2IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCIIE_Pos (2UL) /*!< DRTCIIE (Bit 2) */ + #define R_SYSTEM_DPSIER2_DRTCIIE_Msk (0x4UL) /*!< DRTCIIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ + #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DPVD3IE_Pos (5UL) /*!< DPVD3IE (Bit 5) */ + #define R_SYSTEM_DPSIER2_DPVD3IE_Msk (0x20UL) /*!< DPVD3IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER3 ======================================================== */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DULPT0IE_Pos (2UL) /*!< DULPT0IE (Bit 2) */ + #define R_SYSTEM_DPSIER3_DULPT0IE_Msk (0x4UL) /*!< DULPT0IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DULPT1IE_Pos (3UL) /*!< DULPT1IE (Bit 3) */ + #define R_SYSTEM_DPSIER3_DULPT1IE_Msk (0x8UL) /*!< DULPT1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DIWDTIE_Pos (5UL) /*!< DIWDTIE (Bit 5) */ + #define R_SYSTEM_DPSIER3_DIWDTIE_Msk (0x20UL) /*!< DIWDTIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DSOSTDIE_Pos (6UL) /*!< DSOSTDIE (Bit 6) */ + #define R_SYSTEM_DPSIER3_DSOSTDIE_Msk (0x40UL) /*!< DSOSTDIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DVBATTADIE_Pos (7UL) /*!< DVBATTADIE (Bit 7) */ + #define R_SYSTEM_DPSIER3_DVBATTADIE_Msk (0x80UL) /*!< DVBATTADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR0 ======================================================== */ + #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR1 ======================================================== */ + #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR2 ======================================================== */ + #define R_SYSTEM_DPSIFR2_DPVD1IF_Pos (0UL) /*!< DPVD1IF (Bit 0) */ + #define R_SYSTEM_DPSIFR2_DPVD1IF_Msk (0x1UL) /*!< DPVD1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DPVD2IF_Pos (1UL) /*!< DPVD2IF (Bit 1) */ + #define R_SYSTEM_DPSIFR2_DPVD2IF_Msk (0x2UL) /*!< DPVD2IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCIIF_Pos (2UL) /*!< DRTCIIF (Bit 2) */ + #define R_SYSTEM_DPSIFR2_DRTCIIF_Msk (0x4UL) /*!< DRTCIIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DPVD3IF_Pos (5UL) /*!< DPVD3IF (Bit 5) */ + #define R_SYSTEM_DPSIFR2_DPVD3IF_Msk (0x20UL) /*!< DPVD3IF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR3 ======================================================== */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DULPT0IF_Pos (2UL) /*!< DULPT0IF (Bit 2) */ + #define R_SYSTEM_DPSIFR3_DULPT0IF_Msk (0x4UL) /*!< DULPT0IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DULPT1IF_Pos (3UL) /*!< DULPT1IF (Bit 3) */ + #define R_SYSTEM_DPSIFR3_DULPT1IF_Msk (0x8UL) /*!< DULPT1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DIWDTIF_Pos (5UL) /*!< DIWDTIF (Bit 5) */ + #define R_SYSTEM_DPSIFR3_DIWDTIF_Msk (0x20UL) /*!< DIWDTIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DSOSTDIF_Pos (6UL) /*!< DSOSTDIF (Bit 6) */ + #define R_SYSTEM_DPSIFR3_DSOSTDIF_Msk (0x40UL) /*!< DSOSTDIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DVBATTADIF_Pos (7UL) /*!< DVBATTADIF (Bit 7) */ + #define R_SYSTEM_DPSIFR3_DVBATTADIF_Msk (0x80UL) /*!< DVBATTADIF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR0 ======================================================== */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR1 ======================================================== */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR2 ======================================================== */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD3IEG_Pos (5UL) /*!< DLVD3IEG (Bit 5) */ + #define R_SYSTEM_DPSIEGR2_DLVD3IEG_Msk (0x20UL) /*!< DLVD3IEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR3 ======================================================== */ + #define R_SYSTEM_DPSIEGR3_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR3_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================== SYOCDCR ======================================================== */ + #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ + #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD4RF_Pos (5UL) /*!< LVD4RF (Bit 5) */ + #define R_SYSTEM_RSTSR0_LVD4RF_Msk (0x20UL) /*!< LVD4RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD5RF_Pos (6UL) /*!< LVD5RF (Bit 6) */ + #define R_SYSTEM_RSTSR0_LVD5RF_Msk (0x40UL) /*!< LVD5RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR2 ========================================================= */ + #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ + #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR3 ========================================================= */ + #define R_SYSTEM_RSTSR3_CVMRF_Pos (0UL) /*!< CVMRF (Bit 0) */ + #define R_SYSTEM_RSTSR3_CVMRF_Msk (0x1UL) /*!< CVMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR3_OCPRF_Pos (4UL) /*!< OCPRF (Bit 4) */ + #define R_SYSTEM_RSTSR3_OCPRF_Msk (0x10UL) /*!< OCPRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR3_TEMPRF_Pos (7UL) /*!< TEMPRF (Bit 7) */ + #define R_SYSTEM_RSTSR3_TEMPRF_Msk (0x80UL) /*!< TEMPRF (Bitfield-Mask: 0x01) */ +/* ========================================================= MOMCR ========================================================= */ + #define R_SYSTEM_MOMCR_MODRV0_Pos (1UL) /*!< MODRV0 (Bit 1) */ + #define R_SYSTEM_MOMCR_MODRV0_Msk (0xeUL) /*!< MODRV0 (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ + #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD1CMPCR ======================================================= */ + #define R_SYSTEM_LVD1CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD1CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD1CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD1CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD2CMPCR ======================================================= */ + #define R_SYSTEM_LVD2CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD2CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD2CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD2CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD3CMPCR ======================================================= */ + #define R_SYSTEM_LVD3CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD3CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD3CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD3CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD4CMPCR ======================================================= */ + #define R_SYSTEM_LVD4CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD4CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD4CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD4CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD5CMPCR ======================================================= */ + #define R_SYSTEM_LVD5CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD5CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD5CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD5CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR0 ======================================================== */ + #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR0 ======================================================== */ + #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD3CR0 ======================================================== */ + #define R_SYSTEM_LVD3CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD3CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD3CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD3CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD3CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD3CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD3CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD3CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD3CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD3CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD3CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD3CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD4CR0 ======================================================== */ + #define R_SYSTEM_LVD4CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD4CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD4CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD4CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD4CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD4CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD4CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD4CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD4CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD4CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD4CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD4CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD5CR0 ======================================================== */ + #define R_SYSTEM_LVD5CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD5CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD5CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD5CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD5CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD5CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD5CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD5CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD5CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD5CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD5CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD5CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBATTMNSELR ====================================================== */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTBPCR1 ======================================================== */ + #define R_SYSTEM_VBTBPCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTBPCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSCR ========================================================= */ + #define R_SYSTEM_LPSCR_LPMD_Pos (0UL) /*!< LPMD (Bit 0) */ + #define R_SYSTEM_LPSCR_LPMD_Msk (0xfUL) /*!< LPMD (Bitfield-Mask: 0x0f) */ +/* ========================================================= SSCR1 ========================================================= */ + #define R_SYSTEM_SSCR1_SS2FR_Pos (0UL) /*!< SS2FR (Bit 0) */ + #define R_SYSTEM_SSCR1_SS2FR_Msk (0x1UL) /*!< SS2FR (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SSCR1_SS2LP_Pos (2UL) /*!< SS2LP (Bit 2) */ + #define R_SYSTEM_SSCR1_SS2LP_Msk (0xcUL) /*!< SS2LP (Bitfield-Mask: 0x03) */ +/* ========================================================= SVSCR ========================================================= */ + #define R_SYSTEM_SVSCR_SVSCM_Pos (0UL) /*!< SVSCM (Bit 0) */ + #define R_SYSTEM_SVSCR_SVSCM_Msk (0x7UL) /*!< SVSCM (Bitfield-Mask: 0x07) */ +/* ========================================================= LVOCR ========================================================= */ + #define R_SYSTEM_LVOCR_LVO0E_Pos (0UL) /*!< LVO0E (Bit 0) */ + #define R_SYSTEM_LVOCR_LVO0E_Msk (0x1UL) /*!< LVO0E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVOCR_LVO1E_Pos (1UL) /*!< LVO1E (Bit 1) */ + #define R_SYSTEM_LVOCR_LVO1E_Msk (0x2UL) /*!< LVO1E (Bitfield-Mask: 0x01) */ +/* ========================================================= MWMCR ========================================================= */ + #define R_SYSTEM_MWMCR_MWM_Pos (0UL) /*!< MWM (Bit 0) */ + #define R_SYSTEM_MWMCR_MWM_Msk (0x3UL) /*!< MWM (Bitfield-Mask: 0x03) */ +/* ======================================================= SYRSTMSK0 ======================================================= */ + #define R_SYSTEM_SYRSTMSK0_IWDTMASK_Pos (0UL) /*!< IWDTMASK (Bit 0) */ + #define R_SYSTEM_SYRSTMSK0_IWDTMASK_Msk (0x1UL) /*!< IWDTMASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_WDT0MASK_Pos (1UL) /*!< WDT0MASK (Bit 1) */ + #define R_SYSTEM_SYRSTMSK0_WDT0MASK_Msk (0x2UL) /*!< WDT0MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_SWMASK_Pos (2UL) /*!< SWMASK (Bit 2) */ + #define R_SYSTEM_SYRSTMSK0_SWMASK_Msk (0x4UL) /*!< SWMASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_CLU0MASK_Pos (4UL) /*!< CLU0MASK (Bit 4) */ + #define R_SYSTEM_SYRSTMSK0_CLU0MASK_Msk (0x10UL) /*!< CLU0MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_LM0MASK_Pos (5UL) /*!< LM0MASK (Bit 5) */ + #define R_SYSTEM_SYRSTMSK0_LM0MASK_Msk (0x20UL) /*!< LM0MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_CMMASK_Pos (6UL) /*!< CMMASK (Bit 6) */ + #define R_SYSTEM_SYRSTMSK0_CMMASK_Msk (0x40UL) /*!< CMMASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_BUSMASK_Pos (7UL) /*!< BUSMASK (Bit 7) */ + #define R_SYSTEM_SYRSTMSK0_BUSMASK_Msk (0x80UL) /*!< BUSMASK (Bitfield-Mask: 0x01) */ +/* ======================================================= SYRSTMSK1 ======================================================= */ + #define R_SYSTEM_SYRSTMSK1_WDT1MASK_Pos (1UL) /*!< WDT1MASK (Bit 1) */ + #define R_SYSTEM_SYRSTMSK1_WDT1MASK_Msk (0x2UL) /*!< WDT1MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK1_CLU1MASK_Pos (4UL) /*!< CLU1MASK (Bit 4) */ + #define R_SYSTEM_SYRSTMSK1_CLU1MASK_Msk (0x10UL) /*!< CLU1MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK1_LM1MASK_Pos (5UL) /*!< LM1MASK (Bit 5) */ + #define R_SYSTEM_SYRSTMSK1_LM1MASK_Msk (0x20UL) /*!< LM1MASK (Bitfield-Mask: 0x01) */ +/* ======================================================= SYRSTMSK2 ======================================================= */ + #define R_SYSTEM_SYRSTMSK2_PVD1MASK_Pos (0UL) /*!< PVD1MASK (Bit 0) */ + #define R_SYSTEM_SYRSTMSK2_PVD1MASK_Msk (0x1UL) /*!< PVD1MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK2_PVD2MASK_Pos (1UL) /*!< PVD2MASK (Bit 1) */ + #define R_SYSTEM_SYRSTMSK2_PVD2MASK_Msk (0x2UL) /*!< PVD2MASK (Bitfield-Mask: 0x01) */ +/* ======================================================== TEMPRCR ======================================================== */ + #define R_SYSTEM_TEMPRCR_TEMPREN_Pos (0UL) /*!< TEMPREN (Bit 0) */ + #define R_SYSTEM_TEMPRCR_TEMPREN_Msk (0x1UL) /*!< TEMPREN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TEMPRCR_TSNEN_Pos (1UL) /*!< TSNEN (Bit 1) */ + #define R_SYSTEM_TEMPRCR_TSNEN_Msk (0x2UL) /*!< TSNEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TEMPRCR_CMPEN_Pos (2UL) /*!< CMPEN (Bit 2) */ + #define R_SYSTEM_TEMPRCR_CMPEN_Msk (0x4UL) /*!< CMPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TEMPRCR_TSNKEEP_Pos (3UL) /*!< TSNKEEP (Bit 3) */ + #define R_SYSTEM_TEMPRCR_TSNKEEP_Msk (0x8UL) /*!< TSNKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================== TEMPRLR ======================================================== */ + #define R_SYSTEM_TEMPRLR_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ + #define R_SYSTEM_TEMPRLR_LOCK_Msk (0x1UL) /*!< LOCK (Bitfield-Mask: 0x01) */ +/* ======================================================== LDOSCR ========================================================= */ + #define R_SYSTEM_LDOSCR_LDOSTP_Pos (0UL) /*!< LDOSTP (Bit 0) */ + #define R_SYSTEM_LDOSCR_LDOSTP_Msk (0x1UL) /*!< LDOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= PLL1LDOCR ======================================================= */ + #define R_SYSTEM_PLL1LDOCR_LDOSTP_Pos (0UL) /*!< LDOSTP (Bit 0) */ + #define R_SYSTEM_PLL1LDOCR_LDOSTP_Msk (0x1UL) /*!< LDOSTP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL1LDOCR_SKEEP_Pos (1UL) /*!< SKEEP (Bit 1) */ + #define R_SYSTEM_PLL1LDOCR_SKEEP_Msk (0x2UL) /*!< SKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================= PLL2LDOCR ======================================================= */ + #define R_SYSTEM_PLL2LDOCR_LDOSTP_Pos (0UL) /*!< LDOSTP (Bit 0) */ + #define R_SYSTEM_PLL2LDOCR_LDOSTP_Msk (0x1UL) /*!< LDOSTP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2LDOCR_SKEEP_Pos (1UL) /*!< SKEEP (Bit 1) */ + #define R_SYSTEM_PLL2LDOCR_SKEEP_Msk (0x2UL) /*!< SKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================= HOCOLDOCR ======================================================= */ + #define R_SYSTEM_HOCOLDOCR_LDOSTP_Pos (0UL) /*!< LDOSTP (Bit 0) */ + #define R_SYSTEM_HOCOLDOCR_LDOSTP_Msk (0x1UL) /*!< LDOSTP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_HOCOLDOCR_SKEEP_Pos (1UL) /*!< SKEEP (Bit 1) */ + #define R_SYSTEM_HOCOLDOCR_SKEEP_Msk (0x2UL) /*!< SKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOMCR2 ========================================================= */ + #define R_SYSTEM_MOMCR2_MOMODE_Pos (0UL) /*!< MOMODE (Bit 0) */ + #define R_SYSTEM_MOMCR2_MOMODE_Msk (0x1UL) /*!< MOMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1FCR ======================================================== */ + #define R_SYSTEM_LVD1FCR_RHSEL_Pos (0UL) /*!< RHSEL (Bit 0) */ + #define R_SYSTEM_LVD1FCR_RHSEL_Msk (0x1UL) /*!< RHSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2FCR ======================================================== */ + #define R_SYSTEM_LVD2FCR_RHSEL_Pos (0UL) /*!< RHSEL (Bit 0) */ + #define R_SYSTEM_LVD2FCR_RHSEL_Msk (0x1UL) /*!< RHSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD3FCR ======================================================== */ + #define R_SYSTEM_LVD3FCR_RHSEL_Pos (0UL) /*!< RHSEL (Bit 0) */ + #define R_SYSTEM_LVD3FCR_RHSEL_Msk (0x1UL) /*!< RHSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD4FCR ======================================================== */ + #define R_SYSTEM_LVD4FCR_RHSEL_Pos (0UL) /*!< RHSEL (Bit 0) */ + #define R_SYSTEM_LVD4FCR_RHSEL_Msk (0x1UL) /*!< RHSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD5FCR ======================================================== */ + #define R_SYSTEM_LVD5FCR_RHSEL_Pos (0UL) /*!< RHSEL (Bit 0) */ + #define R_SYSTEM_LVD5FCR_RHSEL_Msk (0x1UL) /*!< RHSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= PVDLR ========================================================= */ + #define R_SYSTEM_PVDLR_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ + #define R_SYSTEM_PVDLR_LOCK_Msk (0x1UL) /*!< LOCK (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER4 ======================================================== */ + #define R_SYSTEM_DPSIER4_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER4_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER5 ======================================================== */ + #define R_SYSTEM_DPSIER5_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER5_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR4 ======================================================== */ + #define R_SYSTEM_DPSIFR4_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR4_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR5 ======================================================== */ + #define R_SYSTEM_DPSIFR5_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR5_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR4 ======================================================== */ + #define R_SYSTEM_DPSIEGR4_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR4_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTSWMON ======================================================== */ + #define R_SYSTEM_VBTSWMON_VLVLMON_Pos (0UL) /*!< VLVLMON (Bit 0) */ + #define R_SYSTEM_VBTSWMON_VLVLMON_Msk (0x7UL) /*!< VLVLMON (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_VBTSWMON_VDETEMON_Pos (4UL) /*!< VDETEMON (Bit 4) */ + #define R_SYSTEM_VBTSWMON_VDETEMON_Msk (0x10UL) /*!< VDETEMON (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTSWSCR ======================================================== */ + #define R_SYSTEM_VBTSWSCR_VBTSWE_Pos (0UL) /*!< VBTSWE (Bit 0) */ + #define R_SYSTEM_VBTSWSCR_VBTSWE_Msk (0x1UL) /*!< VBTSWE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSCCR ========================================================= */ + #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ + #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= SOMCR ========================================================= */ + #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ + #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_SOMCR_SOSEL_Pos (6UL) /*!< SOSEL (Bit 6) */ + #define R_SYSTEM_SOMCR_SOSEL_Msk (0x40UL) /*!< SOSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSTDCR ======================================================== */ + #define R_SYSTEM_SOSTDCR_SOSTDIE_Pos (0UL) /*!< SOSTDIE (Bit 0) */ + #define R_SYSTEM_SOSTDCR_SOSTDIE_Msk (0x1UL) /*!< SOSTDIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOSTDCR_SOSTDE_Pos (7UL) /*!< SOSTDE (Bit 7) */ + #define R_SYSTEM_SOSTDCR_SOSTDE_Msk (0x80UL) /*!< SOSTDE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSTDSR ======================================================== */ + #define R_SYSTEM_SOSTDSR_SOSTDF_Pos (0UL) /*!< SOSTDF (Bit 0) */ + #define R_SYSTEM_SOSTDSR_SOSTDF_Msk (0x1UL) /*!< SOSTDF (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBER ========================================================= */ + #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ + #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTBPCR2 ======================================================== */ + #define R_SYSTEM_VBTBPCR2_VDETLVL_Pos (0UL) /*!< VDETLVL (Bit 0) */ + #define R_SYSTEM_VBTBPCR2_VDETLVL_Msk (0x7UL) /*!< VDETLVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_VBTBPCR2_VDETE_Pos (4UL) /*!< VDETE (Bit 4) */ + #define R_SYSTEM_VBTBPCR2_VDETE_Msk (0x10UL) /*!< VDETE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBPSR ======================================================== */ + #define R_SYSTEM_VBTBPSR_VBPORF_Pos (0UL) /*!< VBPORF (Bit 0) */ + #define R_SYSTEM_VBTBPSR_VBPORF_Msk (0x1UL) /*!< VBPORF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTBPSR_VBPORM_Pos (4UL) /*!< VBPORM (Bit 4) */ + #define R_SYSTEM_VBTBPSR_VBPORM_Msk (0x10UL) /*!< VBPORM (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTBPSR_BPWSWM_Pos (5UL) /*!< BPWSWM (Bit 5) */ + #define R_SYSTEM_VBTBPSR_BPWSWM_Msk (0x20UL) /*!< BPWSWM (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTADSR ======================================================== */ + #define R_SYSTEM_VBTADSR_VBTADF0_Pos (0UL) /*!< VBTADF0 (Bit 0) */ + #define R_SYSTEM_VBTADSR_VBTADF0_Msk (0x1UL) /*!< VBTADF0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADSR_VBTADF1_Pos (1UL) /*!< VBTADF1 (Bit 1) */ + #define R_SYSTEM_VBTADSR_VBTADF1_Msk (0x2UL) /*!< VBTADF1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADSR_VBTADF2_Pos (2UL) /*!< VBTADF2 (Bit 2) */ + #define R_SYSTEM_VBTADSR_VBTADF2_Msk (0x4UL) /*!< VBTADF2 (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTADCR1 ======================================================== */ + #define R_SYSTEM_VBTADCR1_VBTADIE0_Pos (0UL) /*!< VBTADIE0 (Bit 0) */ + #define R_SYSTEM_VBTADCR1_VBTADIE0_Msk (0x1UL) /*!< VBTADIE0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADIE1_Pos (1UL) /*!< VBTADIE1 (Bit 1) */ + #define R_SYSTEM_VBTADCR1_VBTADIE1_Msk (0x2UL) /*!< VBTADIE1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADIE2_Pos (2UL) /*!< VBTADIE2 (Bit 2) */ + #define R_SYSTEM_VBTADCR1_VBTADIE2_Msk (0x4UL) /*!< VBTADIE2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE0_Pos (4UL) /*!< VBTADCLE0 (Bit 4) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE0_Msk (0x10UL) /*!< VBTADCLE0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE1_Pos (5UL) /*!< VBTADCLE1 (Bit 5) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE1_Msk (0x20UL) /*!< VBTADCLE1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE2_Pos (6UL) /*!< VBTADCLE2 (Bit 6) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE2_Msk (0x40UL) /*!< VBTADCLE2 (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTADCR2 ======================================================== */ + #define R_SYSTEM_VBTADCR2_VBRTCES0_Pos (0UL) /*!< VBRTCES0 (Bit 0) */ + #define R_SYSTEM_VBTADCR2_VBRTCES0_Msk (0x1UL) /*!< VBRTCES0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR2_VBRTCES1_Pos (1UL) /*!< VBRTCES1 (Bit 1) */ + #define R_SYSTEM_VBTADCR2_VBRTCES1_Msk (0x2UL) /*!< VBRTCES1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR2_VBRTCES2_Pos (2UL) /*!< VBRTCES2 (Bit 2) */ + #define R_SYSTEM_VBTADCR2_VBRTCES2_Msk (0x4UL) /*!< VBRTCES2 (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR ======================================================== */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR2 ======================================================= */ + #define R_SYSTEM_VBTICTLR2_VCH0NCE_Pos (0UL) /*!< VCH0NCE (Bit 0) */ + #define R_SYSTEM_VBTICTLR2_VCH0NCE_Msk (0x1UL) /*!< VCH0NCE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH1NCE_Pos (1UL) /*!< VCH1NCE (Bit 1) */ + #define R_SYSTEM_VBTICTLR2_VCH1NCE_Msk (0x2UL) /*!< VCH1NCE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH2NCE_Pos (2UL) /*!< VCH2NCE (Bit 2) */ + #define R_SYSTEM_VBTICTLR2_VCH2NCE_Msk (0x4UL) /*!< VCH2NCE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH0EG_Pos (4UL) /*!< VCH0EG (Bit 4) */ + #define R_SYSTEM_VBTICTLR2_VCH0EG_Msk (0x10UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH1EG_Pos (5UL) /*!< VCH1EG (Bit 5) */ + #define R_SYSTEM_VBTICTLR2_VCH1EG_Msk (0x20UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH2EG_Pos (6UL) /*!< VCH2EG (Bit 6) */ + #define R_SYSTEM_VBTICTLR2_VCH2EG_Msk (0x40UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTIMONR ======================================================== */ + #define R_SYSTEM_VBTIMONR_VCH0MON_Pos (0UL) /*!< VCH0MON (Bit 0) */ + #define R_SYSTEM_VBTIMONR_VCH0MON_Msk (0x1UL) /*!< VCH0MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTIMONR_VCH1MON_Pos (1UL) /*!< VCH1MON (Bit 1) */ + #define R_SYSTEM_VBTIMONR_VCH1MON_Msk (0x2UL) /*!< VCH1MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTIMONR_VCH2MON_Pos (2UL) /*!< VCH2MON (Bit 2) */ + #define R_SYSTEM_VBTIMONR_VCH2MON_Msk (0x4UL) /*!< VCH2MON (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTNCWCR ======================================================== */ + #define R_SYSTEM_VBTNCWCR_VINCW_Pos (0UL) /*!< VINCW (Bit 0) */ + #define R_SYSTEM_VBTNCWCR_VINCW_Msk (0x7UL) /*!< VINCW (Bitfield-Mask: 0x07) */ +/* ======================================================= VBTADCR3 ======================================================== */ + #define R_SYSTEM_VBTADCR3_VBTADZE0_Pos (0UL) /*!< VBTADZE0 (Bit 0) */ + #define R_SYSTEM_VBTADCR3_VBTADZE0_Msk (0x1UL) /*!< VBTADZE0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR3_VBTADZE1_Pos (1UL) /*!< VBTADZE1 (Bit 1) */ + #define R_SYSTEM_VBTADCR3_VBTADZE1_Msk (0x2UL) /*!< VBTADZE1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR3_VBTADZE2_Pos (2UL) /*!< VBTADZE2 (Bit 2) */ + #define R_SYSTEM_VBTADCR3_VBTADZE2_Msk (0x4UL) /*!< VBTADZE2 (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBKR ========================================================= */ + #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCDR ========================================================= */ + #define R_TSN_CAL_TSCDR_TSCDR_Pos (0UL) /*!< TSCDR (Bit 0) */ + #define R_TSN_CAL_TSCDR_TSCDR_Msk (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCR ========================================================== */ + #define R_TSN_CTRL_TSCR_TSEN_Pos (7UL) /*!< TSEN (Bit 7) */ + #define R_TSN_CTRL_TSCR_TSEN_Msk (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01) */ + #define R_TSN_CTRL_TSCR_TSOE_Pos (4UL) /*!< TSOE (Bit 4) */ + #define R_TSN_CTRL_TSCR_TSOE_Msk (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */ + #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */ + #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ========================================================= CFIFO ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== DVCHGR ========================================================= */ + #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ + #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ + #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ + #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ====================================================== USBBCCTRL0 ======================================================= */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */ +/* ======================================================== UCKSEL ========================================================= */ + #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */ + #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */ +/* ========================================================= USBMC ========================================================= */ + #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */ + #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */ + #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSLEW ======================================================== */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR0R_FS ======================================================= */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR1R_FS ======================================================= */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_VIN ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MC =========================================================== */ + #define R_VIN_MC_ME_Pos (0UL) /*!< ME (Bit 0) */ + #define R_VIN_MC_ME_Msk (0x1UL) /*!< ME (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_BPS_Pos (1UL) /*!< BPS (Bit 1) */ + #define R_VIN_MC_BPS_Msk (0x2UL) /*!< BPS (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_IM_Pos (3UL) /*!< IM (Bit 3) */ + #define R_VIN_MC_IM_Msk (0x18UL) /*!< IM (Bitfield-Mask: 0x03) */ + #define R_VIN_MC_EN_Pos (6UL) /*!< EN (Bit 6) */ + #define R_VIN_MC_EN_Msk (0x40UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_DC_Pos (14UL) /*!< DC (Bit 14) */ + #define R_VIN_MC_DC_Msk (0xc000UL) /*!< DC (Bitfield-Mask: 0x03) */ + #define R_VIN_MC_INF_Pos (16UL) /*!< INF (Bit 16) */ + #define R_VIN_MC_INF_Msk (0x70000UL) /*!< INF (Bitfield-Mask: 0x07) */ + #define R_VIN_MC_LUTE_Pos (20UL) /*!< LUTE (Bit 20) */ + #define R_VIN_MC_LUTE_Msk (0x100000UL) /*!< LUTE (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_ST_Pos (22UL) /*!< ST (Bit 22) */ + #define R_VIN_MC_ST_Msk (0x400000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_DC2_Pos (24UL) /*!< DC2 (Bit 24) */ + #define R_VIN_MC_DC2_Msk (0x1000000UL) /*!< DC2 (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_YUV444_Pos (25UL) /*!< YUV444 (Bit 25) */ + #define R_VIN_MC_YUV444_Msk (0x2000000UL) /*!< YUV444 (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_SCLE_Pos (26UL) /*!< SCLE (Bit 26) */ + #define R_VIN_MC_SCLE_Msk (0x4000000UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_CLP_Pos (28UL) /*!< CLP (Bit 28) */ + #define R_VIN_MC_CLP_Msk (0x30000000UL) /*!< CLP (Bitfield-Mask: 0x03) */ +/* ========================================================== MS =========================================================== */ + #define R_VIN_MS_CA_Pos (0UL) /*!< CA (Bit 0) */ + #define R_VIN_MS_CA_Msk (0x1UL) /*!< CA (Bitfield-Mask: 0x01) */ + #define R_VIN_MS_AV_Pos (1UL) /*!< AV (Bit 1) */ + #define R_VIN_MS_AV_Msk (0x2UL) /*!< AV (Bitfield-Mask: 0x01) */ + #define R_VIN_MS_FS_Pos (2UL) /*!< FS (Bit 2) */ + #define R_VIN_MS_FS_Msk (0x4UL) /*!< FS (Bitfield-Mask: 0x01) */ + #define R_VIN_MS_FBS_Pos (3UL) /*!< FBS (Bit 3) */ + #define R_VIN_MS_FBS_Msk (0x18UL) /*!< FBS (Bitfield-Mask: 0x03) */ + #define R_VIN_MS_MA_Pos (16UL) /*!< MA (Bit 16) */ + #define R_VIN_MS_MA_Msk (0x10000UL) /*!< MA (Bitfield-Mask: 0x01) */ + #define R_VIN_MS_FMS_Pos (19UL) /*!< FMS (Bit 19) */ + #define R_VIN_MS_FMS_Msk (0x180000UL) /*!< FMS (Bitfield-Mask: 0x03) */ +/* ========================================================== FC =========================================================== */ + #define R_VIN_FC_CC_Pos (1UL) /*!< CC (Bit 1) */ + #define R_VIN_FC_CC_Msk (0x2UL) /*!< CC (Bitfield-Mask: 0x01) */ +/* ========================================================= SLPRC ========================================================= */ + #define R_VIN_SLPRC_SLPRC_Pos (0UL) /*!< SLPRC (Bit 0) */ + #define R_VIN_SLPRC_SLPRC_Msk (0xfffUL) /*!< SLPRC (Bitfield-Mask: 0xfff) */ +/* ========================================================= ELPRC ========================================================= */ + #define R_VIN_ELPRC_ELPRC_Pos (0UL) /*!< ELPRC (Bit 0) */ + #define R_VIN_ELPRC_ELPRC_Msk (0xfffUL) /*!< ELPRC (Bitfield-Mask: 0xfff) */ +/* ========================================================= SPPRC ========================================================= */ + #define R_VIN_SPPRC_SPPRC_Pos (0UL) /*!< SPPRC (Bit 0) */ + #define R_VIN_SPPRC_SPPRC_Msk (0xfffUL) /*!< SPPRC (Bitfield-Mask: 0xfff) */ +/* ========================================================= EPPRC ========================================================= */ + #define R_VIN_EPPRC_EPPRC_Pos (0UL) /*!< EPPRC (Bit 0) */ + #define R_VIN_EPPRC_EPPRC_Msk (0xfffUL) /*!< EPPRC (Bitfield-Mask: 0xfff) */ +/* ======================================================= CSI_IFMD ======================================================== */ + #define R_VIN_CSI_IFMD_VC_SEL_Pos (0UL) /*!< VC_SEL (Bit 0) */ + #define R_VIN_CSI_IFMD_VC_SEL_Msk (0xfUL) /*!< VC_SEL (Bitfield-Mask: 0x0f) */ + #define R_VIN_CSI_IFMD_DT_Pos (8UL) /*!< DT (Bit 8) */ + #define R_VIN_CSI_IFMD_DT_Msk (0x3f00UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_VIN_CSI_IFMD_DES0_Pos (25UL) /*!< DES0 (Bit 25) */ + #define R_VIN_CSI_IFMD_DES0_Msk (0x2000000UL) /*!< DES0 (Bitfield-Mask: 0x01) */ +/* ======================================================== CSIFLD ========================================================= */ + #define R_VIN_CSIFLD_FLD_EN_Pos (0UL) /*!< FLD_EN (Bit 0) */ + #define R_VIN_CSIFLD_FLD_EN_Msk (0x1UL) /*!< FLD_EN (Bitfield-Mask: 0x01) */ + #define R_VIN_CSIFLD_FLD_SEL_Pos (4UL) /*!< FLD_SEL (Bit 4) */ + #define R_VIN_CSIFLD_FLD_SEL_Msk (0x30UL) /*!< FLD_SEL (Bitfield-Mask: 0x03) */ + #define R_VIN_CSIFLD_FLD_NUM_Pos (16UL) /*!< FLD_NUM (Bit 16) */ + #define R_VIN_CSIFLD_FLD_NUM_Msk (0x10000UL) /*!< FLD_NUM (Bitfield-Mask: 0x01) */ +/* ========================================================== IS =========================================================== */ + #define R_VIN_IS_IS_Pos (0UL) /*!< IS (Bit 0) */ + #define R_VIN_IS_IS_Msk (0x1fffUL) /*!< IS (Bitfield-Mask: 0x1fff) */ +/* ========================================================== MB1 ========================================================== */ + #define R_VIN_MB1_MB1_Pos (7UL) /*!< MB1 (Bit 7) */ + #define R_VIN_MB1_MB1_Msk (0xffffff80UL) /*!< MB1 (Bitfield-Mask: 0x1ffffff) */ +/* ========================================================== MB2 ========================================================== */ + #define R_VIN_MB2_MB2_Pos (7UL) /*!< MB2 (Bit 7) */ + #define R_VIN_MB2_MB2_Msk (0xffffff80UL) /*!< MB2 (Bitfield-Mask: 0x1ffffff) */ +/* ========================================================== MB3 ========================================================== */ + #define R_VIN_MB3_MB3_Pos (7UL) /*!< MB3 (Bit 7) */ + #define R_VIN_MB3_MB3_Msk (0xffffff80UL) /*!< MB3 (Bitfield-Mask: 0x1ffffff) */ +/* ========================================================== LC =========================================================== */ + #define R_VIN_LC_LC_Pos (0UL) /*!< LC (Bit 0) */ + #define R_VIN_LC_LC_Msk (0xfffUL) /*!< LC (Bitfield-Mask: 0xfff) */ +/* ========================================================== IE =========================================================== */ + #define R_VIN_IE_FOE_Pos (0UL) /*!< FOE (Bit 0) */ + #define R_VIN_IE_FOE_Msk (0x1UL) /*!< FOE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_EFE_Pos (1UL) /*!< EFE (Bit 1) */ + #define R_VIN_IE_EFE_Msk (0x2UL) /*!< EFE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_SIE_Pos (2UL) /*!< SIE (Bit 2) */ + #define R_VIN_IE_SIE_Msk (0x4UL) /*!< SIE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_FIE_Pos (4UL) /*!< FIE (Bit 4) */ + #define R_VIN_IE_FIE_Msk (0x10UL) /*!< FIE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_FME_Pos (5UL) /*!< FME (Bit 5) */ + #define R_VIN_IE_FME_Msk (0x20UL) /*!< FME (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_PRCLIPHEE_Pos (8UL) /*!< PRCLIPHEE (Bit 8) */ + #define R_VIN_IE_PRCLIPHEE_Msk (0x100UL) /*!< PRCLIPHEE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_PRCLIPVEE_Pos (9UL) /*!< PRCLIPVEE (Bit 9) */ + #define R_VIN_IE_PRCLIPVEE_Msk (0x200UL) /*!< PRCLIPVEE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_ROE_Pos (14UL) /*!< ROE (Bit 14) */ + #define R_VIN_IE_ROE_Msk (0x4000UL) /*!< ROE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_AREE_Pos (15UL) /*!< AREE (Bit 15) */ + #define R_VIN_IE_AREE_Msk (0x8000UL) /*!< AREE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_VRE_Pos (16UL) /*!< VRE (Bit 16) */ + #define R_VIN_IE_VRE_Msk (0x10000UL) /*!< VRE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_VFE_Pos (17UL) /*!< VFE (Bit 17) */ + #define R_VIN_IE_VFE_Msk (0x20000UL) /*!< VFE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_FIE2_Pos (31UL) /*!< FIE2 (Bit 31) */ + #define R_VIN_IE_FIE2_Msk (0x80000000UL) /*!< FIE2 (Bitfield-Mask: 0x01) */ +/* ========================================================= INTS ========================================================== */ + #define R_VIN_INTS_FOS_Pos (0UL) /*!< FOS (Bit 0) */ + #define R_VIN_INTS_FOS_Msk (0x1UL) /*!< FOS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_EFS_Pos (1UL) /*!< EFS (Bit 1) */ + #define R_VIN_INTS_EFS_Msk (0x2UL) /*!< EFS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_SIS_Pos (2UL) /*!< SIS (Bit 2) */ + #define R_VIN_INTS_SIS_Msk (0x4UL) /*!< SIS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_FIS_Pos (4UL) /*!< FIS (Bit 4) */ + #define R_VIN_INTS_FIS_Msk (0x10UL) /*!< FIS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_FMS_Pos (5UL) /*!< FMS (Bit 5) */ + #define R_VIN_INTS_FMS_Msk (0x20UL) /*!< FMS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_PRCLIPHES_Pos (8UL) /*!< PRCLIPHES (Bit 8) */ + #define R_VIN_INTS_PRCLIPHES_Msk (0x100UL) /*!< PRCLIPHES (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_PRCLIPVES_Pos (9UL) /*!< PRCLIPVES (Bit 9) */ + #define R_VIN_INTS_PRCLIPVES_Msk (0x200UL) /*!< PRCLIPVES (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_ROS_Pos (14UL) /*!< ROS (Bit 14) */ + #define R_VIN_INTS_ROS_Msk (0x4000UL) /*!< ROS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_ARES_Pos (15UL) /*!< ARES (Bit 15) */ + #define R_VIN_INTS_ARES_Msk (0x8000UL) /*!< ARES (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_VRS_Pos (16UL) /*!< VRS (Bit 16) */ + #define R_VIN_INTS_VRS_Msk (0x10000UL) /*!< VRS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_VFS_Pos (17UL) /*!< VFS (Bit 17) */ + #define R_VIN_INTS_VFS_Msk (0x20000UL) /*!< VFS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_FIS2_Pos (31UL) /*!< FIS2 (Bit 31) */ + #define R_VIN_INTS_FIS2_Msk (0x80000000UL) /*!< FIS2 (Bitfield-Mask: 0x01) */ +/* ========================================================== SI =========================================================== */ + #define R_VIN_SI_SI_Pos (0UL) /*!< SI (Bit 0) */ + #define R_VIN_SI_SI_Msk (0xfffUL) /*!< SI (Bitfield-Mask: 0xfff) */ +/* ======================================================== MTCSTOP ======================================================== */ + #define R_VIN_MTCSTOP_STOPREQ_Pos (0UL) /*!< STOPREQ (Bit 0) */ + #define R_VIN_MTCSTOP_STOPREQ_Msk (0x1UL) /*!< STOPREQ (Bitfield-Mask: 0x01) */ + #define R_VIN_MTCSTOP_STOPACK_Pos (1UL) /*!< STOPACK (Bit 1) */ + #define R_VIN_MTCSTOP_STOPACK_Msk (0x2UL) /*!< STOPACK (Bitfield-Mask: 0x01) */ + #define R_VIN_MTCSTOP_OUTSTAND_Pos (16UL) /*!< OUTSTAND (Bit 16) */ + #define R_VIN_MTCSTOP_OUTSTAND_Msk (0x3f0000UL) /*!< OUTSTAND (Bitfield-Mask: 0x3f) */ +/* ========================================================== DMR ========================================================== */ + #define R_VIN_DMR_DTMD_Pos (0UL) /*!< DTMD (Bit 0) */ + #define R_VIN_DMR_DTMD_Msk (0x3UL) /*!< DTMD (Bitfield-Mask: 0x03) */ + #define R_VIN_DMR_ABIT_Pos (2UL) /*!< ABIT (Bit 2) */ + #define R_VIN_DMR_ABIT_Msk (0x4UL) /*!< ABIT (Bitfield-Mask: 0x01) */ + #define R_VIN_DMR_BPSM_Pos (4UL) /*!< BPSM (Bit 4) */ + #define R_VIN_DMR_BPSM_Msk (0x10UL) /*!< BPSM (Bitfield-Mask: 0x01) */ + #define R_VIN_DMR_EXRGB_Pos (8UL) /*!< EXRGB (Bit 8) */ + #define R_VIN_DMR_EXRGB_Msk (0x100UL) /*!< EXRGB (Bitfield-Mask: 0x01) */ + #define R_VIN_DMR_YC_THR_Pos (11UL) /*!< YC_THR (Bit 11) */ + #define R_VIN_DMR_YC_THR_Msk (0x800UL) /*!< YC_THR (Bitfield-Mask: 0x01) */ + #define R_VIN_DMR_YMODE_Pos (12UL) /*!< YMODE (Bit 12) */ + #define R_VIN_DMR_YMODE_Msk (0x7000UL) /*!< YMODE (Bitfield-Mask: 0x07) */ + #define R_VIN_DMR_A8BIT_Pos (24UL) /*!< A8BIT (Bit 24) */ + #define R_VIN_DMR_A8BIT_Msk (0xff000000UL) /*!< A8BIT (Bitfield-Mask: 0xff) */ +/* ========================================================= UVAOF ========================================================= */ + #define R_VIN_UVAOF_UVAOF_Pos (7UL) /*!< UVAOF (Bit 7) */ + #define R_VIN_UVAOF_UVAOF_Msk (0xffffff80UL) /*!< UVAOF (Bitfield-Mask: 0x1ffffff) */ +/* ========================================================= CSCE1 ========================================================= */ + #define R_VIN_CSCE1_YMUL2_Pos (0UL) /*!< YMUL2 (Bit 0) */ + #define R_VIN_CSCE1_YMUL2_Msk (0x3fffUL) /*!< YMUL2 (Bitfield-Mask: 0x3fff) */ + #define R_VIN_CSCE1_ROUND_Pos (16UL) /*!< ROUND (Bit 16) */ + #define R_VIN_CSCE1_ROUND_Msk (0x10000UL) /*!< ROUND (Bitfield-Mask: 0x01) */ +/* ========================================================= CSCE2 ========================================================= */ + #define R_VIN_CSCE2_CSUB2_Pos (0UL) /*!< CSUB2 (Bit 0) */ + #define R_VIN_CSCE2_CSUB2_Msk (0xfffUL) /*!< CSUB2 (Bitfield-Mask: 0xfff) */ + #define R_VIN_CSCE2_YSUB2_Pos (16UL) /*!< YSUB2 (Bit 16) */ + #define R_VIN_CSCE2_YSUB2_Msk (0xfff0000UL) /*!< YSUB2 (Bitfield-Mask: 0xfff) */ +/* ========================================================= CSCE3 ========================================================= */ + #define R_VIN_CSCE3_GCRMUL2_Pos (0UL) /*!< GCRMUL2 (Bit 0) */ + #define R_VIN_CSCE3_GCRMUL2_Msk (0x3fffUL) /*!< GCRMUL2 (Bitfield-Mask: 0x3fff) */ + #define R_VIN_CSCE3_RCRMUL2_Pos (16UL) /*!< RCRMUL2 (Bit 16) */ + #define R_VIN_CSCE3_RCRMUL2_Msk (0x3fff0000UL) /*!< RCRMUL2 (Bitfield-Mask: 0x3fff) */ +/* ========================================================= CSCE4 ========================================================= */ + #define R_VIN_CSCE4_BCBMUL2_Pos (0UL) /*!< BCBMUL2 (Bit 0) */ + #define R_VIN_CSCE4_BCBMUL2_Msk (0x3fffUL) /*!< BCBMUL2 (Bitfield-Mask: 0x3fff) */ + #define R_VIN_CSCE4_GCBMUL2_Pos (16UL) /*!< GCBMUL2 (Bit 16) */ + #define R_VIN_CSCE4_GCBMUL2_Msk (0x3fff0000UL) /*!< GCBMUL2 (Bitfield-Mask: 0x3fff) */ +/* ======================================================= UDS_CTRL ======================================================== */ + #define R_VIN_UDS_CTRL_NE_BCB_Pos (16UL) /*!< NE_BCB (Bit 16) */ + #define R_VIN_UDS_CTRL_NE_BCB_Msk (0x10000UL) /*!< NE_BCB (Bitfield-Mask: 0x01) */ + #define R_VIN_UDS_CTRL_NE_GY_Pos (17UL) /*!< NE_GY (Bit 17) */ + #define R_VIN_UDS_CTRL_NE_GY_Msk (0x20000UL) /*!< NE_GY (Bitfield-Mask: 0x01) */ + #define R_VIN_UDS_CTRL_NE_RCR_Pos (18UL) /*!< NE_RCR (Bit 18) */ + #define R_VIN_UDS_CTRL_NE_RCR_Msk (0x40000UL) /*!< NE_RCR (Bitfield-Mask: 0x01) */ + #define R_VIN_UDS_CTRL_BC_Pos (20UL) /*!< BC (Bit 20) */ + #define R_VIN_UDS_CTRL_BC_Msk (0x100000UL) /*!< BC (Bitfield-Mask: 0x01) */ + #define R_VIN_UDS_CTRL_BLADV_Pos (28UL) /*!< BLADV (Bit 28) */ + #define R_VIN_UDS_CTRL_BLADV_Msk (0x10000000UL) /*!< BLADV (Bitfield-Mask: 0x01) */ + #define R_VIN_UDS_CTRL_AMD_Pos (30UL) /*!< AMD (Bit 30) */ + #define R_VIN_UDS_CTRL_AMD_Msk (0x40000000UL) /*!< AMD (Bitfield-Mask: 0x01) */ +/* ======================================================= UDS_SCALE ======================================================= */ + #define R_VIN_UDS_SCALE_VFRAC_Pos (0UL) /*!< VFRAC (Bit 0) */ + #define R_VIN_UDS_SCALE_VFRAC_Msk (0xfffUL) /*!< VFRAC (Bitfield-Mask: 0xfff) */ + #define R_VIN_UDS_SCALE_VMANT_Pos (12UL) /*!< VMANT (Bit 12) */ + #define R_VIN_UDS_SCALE_VMANT_Msk (0xf000UL) /*!< VMANT (Bitfield-Mask: 0x0f) */ + #define R_VIN_UDS_SCALE_HFRAC_Pos (16UL) /*!< HFRAC (Bit 16) */ + #define R_VIN_UDS_SCALE_HFRAC_Msk (0xfff0000UL) /*!< HFRAC (Bitfield-Mask: 0xfff) */ + #define R_VIN_UDS_SCALE_HMANT_Pos (28UL) /*!< HMANT (Bit 28) */ + #define R_VIN_UDS_SCALE_HMANT_Msk (0xf0000000UL) /*!< HMANT (Bitfield-Mask: 0x0f) */ +/* ==================================================== UDS_PASS_BWIDTH ==================================================== */ + #define R_VIN_UDS_PASS_BWIDTH_BWIDTH_V_Pos (0UL) /*!< BWIDTH_V (Bit 0) */ + #define R_VIN_UDS_PASS_BWIDTH_BWIDTH_V_Msk (0x7fUL) /*!< BWIDTH_V (Bitfield-Mask: 0x7f) */ + #define R_VIN_UDS_PASS_BWIDTH_BWIDTH_H_Pos (16UL) /*!< BWIDTH_H (Bit 16) */ + #define R_VIN_UDS_PASS_BWIDTH_BWIDTH_H_Msk (0x7f0000UL) /*!< BWIDTH_H (Bitfield-Mask: 0x7f) */ +/* ===================================================== UDS_CLIP_SIZE ===================================================== */ + #define R_VIN_UDS_CLIP_SIZE_CL_VSIZE_Pos (0UL) /*!< CL_VSIZE (Bit 0) */ + #define R_VIN_UDS_CLIP_SIZE_CL_VSIZE_Msk (0xfffUL) /*!< CL_VSIZE (Bitfield-Mask: 0xfff) */ + #define R_VIN_UDS_CLIP_SIZE_CL_HSIZE_Pos (16UL) /*!< CL_HSIZE (Bit 16) */ + #define R_VIN_UDS_CLIP_SIZE_CL_HSIZE_Msk (0xfff0000UL) /*!< CL_HSIZE (Bitfield-Mask: 0xfff) */ +/* ========================================================= LUTP ========================================================== */ + #define R_VIN_LUTP_LTCRPR_Pos (0UL) /*!< LTCRPR (Bit 0) */ + #define R_VIN_LUTP_LTCRPR_Msk (0x3ffUL) /*!< LTCRPR (Bitfield-Mask: 0x3ff) */ + #define R_VIN_LUTP_LTCBPR_Pos (10UL) /*!< LTCBPR (Bit 10) */ + #define R_VIN_LUTP_LTCBPR_Msk (0xffc00UL) /*!< LTCBPR (Bitfield-Mask: 0x3ff) */ + #define R_VIN_LUTP_LTYPR_Pos (20UL) /*!< LTYPR (Bit 20) */ + #define R_VIN_LUTP_LTYPR_Msk (0x3ff00000UL) /*!< LTYPR (Bitfield-Mask: 0x3ff) */ +/* ========================================================= LUTD ========================================================== */ + #define R_VIN_LUTD_LTCRDT_Pos (0UL) /*!< LTCRDT (Bit 0) */ + #define R_VIN_LUTD_LTCRDT_Msk (0xffUL) /*!< LTCRDT (Bitfield-Mask: 0xff) */ + #define R_VIN_LUTD_LTCBDT_Pos (8UL) /*!< LTCBDT (Bit 8) */ + #define R_VIN_LUTD_LTCBDT_Msk (0xff00UL) /*!< LTCBDT (Bitfield-Mask: 0xff) */ + #define R_VIN_LUTD_LTYDT_Pos (16UL) /*!< LTYDT (Bit 16) */ + #define R_VIN_LUTD_LTYDT_Msk (0xff0000UL) /*!< LTYDT (Bitfield-Mask: 0xff) */ +/* ========================================================= YCCR1 ========================================================= */ + #define R_VIN_YCCR1_YCLRP_Pos (0UL) /*!< YCLRP (Bit 0) */ + #define R_VIN_YCCR1_YCLRP_Msk (0x1fffUL) /*!< YCLRP (Bitfield-Mask: 0x1fff) */ +/* ========================================================= YCCR2 ========================================================= */ + #define R_VIN_YCCR2_YCLGP_Pos (0UL) /*!< YCLGP (Bit 0) */ + #define R_VIN_YCCR2_YCLGP_Msk (0x1fffUL) /*!< YCLGP (Bitfield-Mask: 0x1fff) */ + #define R_VIN_YCCR2_YCLBP_Pos (16UL) /*!< YCLBP (Bit 16) */ + #define R_VIN_YCCR2_YCLBP_Msk (0x1fff0000UL) /*!< YCLBP (Bitfield-Mask: 0x1fff) */ +/* ========================================================= YCCR3 ========================================================= */ + #define R_VIN_YCCR3_YCLAP_Pos (0UL) /*!< YCLAP (Bit 0) */ + #define R_VIN_YCCR3_YCLAP_Msk (0xfffUL) /*!< YCLAP (Bitfield-Mask: 0xfff) */ + #define R_VIN_YCCR3_YCLHEN_Pos (23UL) /*!< YCLHEN (Bit 23) */ + #define R_VIN_YCCR3_YCLHEN_Msk (0x800000UL) /*!< YCLHEN (Bitfield-Mask: 0x01) */ + #define R_VIN_YCCR3_YCLSFT_Pos (24UL) /*!< YCLSFT (Bit 24) */ + #define R_VIN_YCCR3_YCLSFT_Msk (0x1f000000UL) /*!< YCLSFT (Bitfield-Mask: 0x1f) */ +/* ======================================================== CBCCR1 ========================================================= */ + #define R_VIN_CBCCR1_CBCLRP_Pos (0UL) /*!< CBCLRP (Bit 0) */ + #define R_VIN_CBCCR1_CBCLRP_Msk (0x1fffUL) /*!< CBCLRP (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CBCCR2 ========================================================= */ + #define R_VIN_CBCCR2_CBCLGP_Pos (0UL) /*!< CBCLGP (Bit 0) */ + #define R_VIN_CBCCR2_CBCLGP_Msk (0x1fffUL) /*!< CBCLGP (Bitfield-Mask: 0x1fff) */ + #define R_VIN_CBCCR2_CBCLBP_Pos (16UL) /*!< CBCLBP (Bit 16) */ + #define R_VIN_CBCCR2_CBCLBP_Msk (0x1fff0000UL) /*!< CBCLBP (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CBCCR3 ========================================================= */ + #define R_VIN_CBCCR3_CBCLAP_Pos (0UL) /*!< CBCLAP (Bit 0) */ + #define R_VIN_CBCCR3_CBCLAP_Msk (0xfffUL) /*!< CBCLAP (Bitfield-Mask: 0xfff) */ + #define R_VIN_CBCCR3_CBCLHEN_Pos (23UL) /*!< CBCLHEN (Bit 23) */ + #define R_VIN_CBCCR3_CBCLHEN_Msk (0x800000UL) /*!< CBCLHEN (Bitfield-Mask: 0x01) */ + #define R_VIN_CBCCR3_CBCLSFT_Pos (24UL) /*!< CBCLSFT (Bit 24) */ + #define R_VIN_CBCCR3_CBCLSFT_Msk (0x1f000000UL) /*!< CBCLSFT (Bitfield-Mask: 0x1f) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_VIN_CRCCR1_CRCLRP_Pos (0UL) /*!< CRCLRP (Bit 0) */ + #define R_VIN_CRCCR1_CRCLRP_Msk (0x1fffUL) /*!< CRCLRP (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CRCCR2 ========================================================= */ + #define R_VIN_CRCCR2_CRCLGP_Pos (0UL) /*!< CRCLGP (Bit 0) */ + #define R_VIN_CRCCR2_CRCLGP_Msk (0x1fffUL) /*!< CRCLGP (Bitfield-Mask: 0x1fff) */ + #define R_VIN_CRCCR2_CRCLBP_Pos (16UL) /*!< CRCLBP (Bit 16) */ + #define R_VIN_CRCCR2_CRCLBP_Msk (0x1fff0000UL) /*!< CRCLBP (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CRCCR3 ========================================================= */ + #define R_VIN_CRCCR3_CRCLAP_Pos (0UL) /*!< CRCLAP (Bit 0) */ + #define R_VIN_CRCCR3_CRCLAP_Msk (0xfffUL) /*!< CRCLAP (Bitfield-Mask: 0xfff) */ + #define R_VIN_CRCCR3_CRCLHEN_Pos (23UL) /*!< CRCLHEN (Bit 23) */ + #define R_VIN_CRCCR3_CRCLHEN_Msk (0x800000UL) /*!< CRCLHEN (Bitfield-Mask: 0x01) */ + #define R_VIN_CRCCR3_CRCLSFT_Pos (24UL) /*!< CRCLSFT (Bit 24) */ + #define R_VIN_CRCCR3_CRCLSFT_Msk (0x1f000000UL) /*!< CRCLSFT (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ + #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ + #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= WDTCSTPR ======================================================== */ + #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CACHE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CCACTL ========================================================= */ + #define R_CACHE_CCACTL_ENC_Pos (0UL) /*!< ENC (Bit 0) */ + #define R_CACHE_CCACTL_ENC_Msk (0x1UL) /*!< ENC (Bitfield-Mask: 0x01) */ + #define R_CACHE_CCACTL_FC_Pos (8UL) /*!< FC (Bit 8) */ + #define R_CACHE_CCACTL_FC_Msk (0x100UL) /*!< FC (Bitfield-Mask: 0x01) */ + #define R_CACHE_CCACTL_WB_Pos (9UL) /*!< WB (Bit 9) */ + #define R_CACHE_CCACTL_WB_Msk (0x200UL) /*!< WB (Bitfield-Mask: 0x01) */ +/* ======================================================== CCAFCT ========================================================= */ + #define R_CACHE_CCAFCT_FC_Pos (0UL) /*!< FC (Bit 0) */ + #define R_CACHE_CCAFCT_FC_Msk (0x1UL) /*!< FC (Bitfield-Mask: 0x01) */ + #define R_CACHE_CCAFCT_WB_Pos (1UL) /*!< WB (Bit 1) */ + #define R_CACHE_CCAFCT_WB_Msk (0x2UL) /*!< WB (Bitfield-Mask: 0x01) */ +/* ======================================================== CCAWTA ========================================================= */ + #define R_CACHE_CCAWTA_WT_Pos (0UL) /*!< WT (Bit 0) */ + #define R_CACHE_CCAWTA_WT_Msk (0x1UL) /*!< WT (Bitfield-Mask: 0x01) */ + #define R_CACHE_CCAWTA_WA_Pos (1UL) /*!< WA (Bit 1) */ + #define R_CACHE_CCAWTA_WA_Msk (0x2UL) /*!< WA (Bitfield-Mask: 0x01) */ +/* ======================================================== CCAEDST ======================================================== */ + #define R_CACHE_CCAEDST_ESD0_Pos (0UL) /*!< ESD0 (Bit 0) */ + #define R_CACHE_CCAEDST_ESD0_Msk (0x1UL) /*!< ESD0 (Bitfield-Mask: 0x01) */ + #define R_CACHE_CCAEDST_ESD1_Pos (1UL) /*!< ESD1 (Bit 1) */ + #define R_CACHE_CCAEDST_ESD1_Msk (0x2UL) /*!< ESD1 (Bitfield-Mask: 0x01) */ + #define R_CACHE_CCAEDST_ESTC_Pos (2UL) /*!< ESTC (Bit 2) */ + #define R_CACHE_CCAEDST_ESTC_Msk (0x4UL) /*!< ESTC (Bitfield-Mask: 0x01) */ + #define R_CACHE_CCAEDST_ESTD_Pos (3UL) /*!< ESTD (Bit 3) */ + #define R_CACHE_CCAEDST_ESTD_Msk (0x8UL) /*!< ESTD (Bitfield-Mask: 0x01) */ + #define R_CACHE_CCAEDST_EST2_Pos (4UL) /*!< EST2 (Bit 4) */ + #define R_CACHE_CCAEDST_EST2_Msk (0x10UL) /*!< EST2 (Bitfield-Mask: 0x01) */ +/* ======================================================== CCATAA ========================================================= */ + #define R_CACHE_CCATAA_OFFSET_Pos (2UL) /*!< OFFSET (Bit 2) */ + #define R_CACHE_CCATAA_OFFSET_Msk (0x1cUL) /*!< OFFSET (Bitfield-Mask: 0x07) */ + #define R_CACHE_CCATAA_ENTRY_Pos (5UL) /*!< ENTRY (Bit 5) */ + #define R_CACHE_CCATAA_ENTRY_Msk (0xfe0UL) /*!< ENTRY (Bitfield-Mask: 0x7f) */ + #define R_CACHE_CCATAA_TARGET_Pos (16UL) /*!< TARGET (Bit 16) */ + #define R_CACHE_CCATAA_TARGET_Msk (0x70000UL) /*!< TARGET (Bitfield-Mask: 0x07) */ + #define R_CACHE_CCATAA_RW_Pos (23UL) /*!< RW (Bit 23) */ + #define R_CACHE_CCATAA_RW_Msk (0x800000UL) /*!< RW (Bitfield-Mask: 0x01) */ + #define R_CACHE_CCATAA_WAY_Pos (30UL) /*!< WAY (Bit 30) */ + #define R_CACHE_CCATAA_WAY_Msk (0xc0000000UL) /*!< WAY (Bitfield-Mask: 0x03) */ +/* ======================================================== CCATAD ========================================================= */ + #define R_CACHE_CCATAD_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_CACHE_CCATAD_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCACTL ========================================================= */ + #define R_CACHE_SCACTL_ENS_Pos (0UL) /*!< ENS (Bit 0) */ + #define R_CACHE_SCACTL_ENS_Msk (0x1UL) /*!< ENS (Bitfield-Mask: 0x01) */ + #define R_CACHE_SCACTL_FS_Pos (8UL) /*!< FS (Bit 8) */ + #define R_CACHE_SCACTL_FS_Msk (0x100UL) /*!< FS (Bitfield-Mask: 0x01) */ + #define R_CACHE_SCACTL_WB_Pos (9UL) /*!< WB (Bit 9) */ + #define R_CACHE_SCACTL_WB_Msk (0x200UL) /*!< WB (Bitfield-Mask: 0x01) */ +/* ======================================================== SCAFCT ========================================================= */ + #define R_CACHE_SCAFCT_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_CACHE_SCAFCT_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + #define R_CACHE_SCAFCT_WB_Pos (1UL) /*!< WB (Bit 1) */ + #define R_CACHE_SCAFCT_WB_Msk (0x2UL) /*!< WB (Bitfield-Mask: 0x01) */ +/* ======================================================== SCAWTA ========================================================= */ + #define R_CACHE_SCAWTA_WT_Pos (0UL) /*!< WT (Bit 0) */ + #define R_CACHE_SCAWTA_WT_Msk (0x1UL) /*!< WT (Bitfield-Mask: 0x01) */ + #define R_CACHE_SCAWTA_WA_Pos (1UL) /*!< WA (Bit 1) */ + #define R_CACHE_SCAWTA_WA_Msk (0x2UL) /*!< WA (Bitfield-Mask: 0x01) */ +/* ======================================================== SCAEDST ======================================================== */ + #define R_CACHE_SCAEDST_ESD0_Pos (0UL) /*!< ESD0 (Bit 0) */ + #define R_CACHE_SCAEDST_ESD0_Msk (0x1UL) /*!< ESD0 (Bitfield-Mask: 0x01) */ + #define R_CACHE_SCAEDST_ESD1_Pos (1UL) /*!< ESD1 (Bit 1) */ + #define R_CACHE_SCAEDST_ESD1_Msk (0x2UL) /*!< ESD1 (Bitfield-Mask: 0x01) */ + #define R_CACHE_SCAEDST_ESTC_Pos (2UL) /*!< ESTC (Bit 2) */ + #define R_CACHE_SCAEDST_ESTC_Msk (0x4UL) /*!< ESTC (Bitfield-Mask: 0x01) */ + #define R_CACHE_SCAEDST_ESTD_Pos (3UL) /*!< ESTD (Bit 3) */ + #define R_CACHE_SCAEDST_ESTD_Msk (0x8UL) /*!< ESTD (Bitfield-Mask: 0x01) */ + #define R_CACHE_SCAEDST_EST2_Pos (4UL) /*!< EST2 (Bit 4) */ + #define R_CACHE_SCAEDST_EST2_Msk (0x10UL) /*!< EST2 (Bitfield-Mask: 0x01) */ +/* ======================================================== SCATAA ========================================================= */ + #define R_CACHE_SCATAA_OFFSET_Pos (2UL) /*!< OFFSET (Bit 2) */ + #define R_CACHE_SCATAA_OFFSET_Msk (0x1cUL) /*!< OFFSET (Bitfield-Mask: 0x07) */ + #define R_CACHE_SCATAA_ENTRY_Pos (5UL) /*!< ENTRY (Bit 5) */ + #define R_CACHE_SCATAA_ENTRY_Msk (0xfe0UL) /*!< ENTRY (Bitfield-Mask: 0x7f) */ + #define R_CACHE_SCATAA_TARGET_Pos (16UL) /*!< TARGET (Bit 16) */ + #define R_CACHE_SCATAA_TARGET_Msk (0x70000UL) /*!< TARGET (Bitfield-Mask: 0x07) */ + #define R_CACHE_SCATAA_RW_Pos (23UL) /*!< RW (Bit 23) */ + #define R_CACHE_SCATAA_RW_Msk (0x800000UL) /*!< RW (Bitfield-Mask: 0x01) */ + #define R_CACHE_SCATAA_WAY_Pos (30UL) /*!< WAY (Bit 30) */ + #define R_CACHE_SCATAA_WAY_Msk (0xc0000000UL) /*!< WAY (Bitfield-Mask: 0x03) */ +/* ======================================================== SCATAD ========================================================= */ + #define R_CACHE_SCATAD_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_CACHE_SCATAD_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CAPOAD ========================================================= */ + #define R_CACHE_CAPOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_CACHE_CAPOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_CACHE_CAPOAD_ECCMOD1_Pos (3UL) /*!< ECCMOD1 (Bit 3) */ + #define R_CACHE_CAPOAD_ECCMOD1_Msk (0x8UL) /*!< ECCMOD1 (Bitfield-Mask: 0x01) */ + #define R_CACHE_CAPOAD_E1STSEN_Pos (4UL) /*!< E1STSEN (Bit 4) */ + #define R_CACHE_CAPOAD_E1STSEN_Msk (0x10UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ +/* ======================================================== CAPRCR ========================================================= */ + #define R_CACHE_CAPRCR_PRCR_Pos (0UL) /*!< PRCR (Bit 0) */ + #define R_CACHE_CAPRCR_PRCR_Msk (0x1UL) /*!< PRCR (Bitfield-Mask: 0x01) */ + #define R_CACHE_CAPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_CACHE_CAPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CSAR ========================================================== */ + #define R_CPSCU_CSAR_CACHESA_Pos (0UL) /*!< CACHESA (Bit 0) */ + #define R_CPSCU_CSAR_CACHESA_Msk (0x1UL) /*!< CACHESA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHELSA_Pos (1UL) /*!< CACHELSA (Bit 1) */ + #define R_CPSCU_CSAR_CACHELSA_Msk (0x2UL) /*!< CACHELSA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHEESA_Pos (2UL) /*!< CACHEESA (Bit 2) */ + #define R_CPSCU_CSAR_CACHEESA_Msk (0x4UL) /*!< CACHEESA (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMSAR ======================================================== */ + #define R_CPSCU_SRAMSAR_SRAMSA_Pos (0UL) /*!< SRAMSA (Bit 0) */ + #define R_CPSCU_SRAMSAR_SRAMSA_Msk (0x1UL) /*!< SRAMSA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMWTSA_Pos (8UL) /*!< SRAMWTSA (Bit 8) */ + #define R_CPSCU_SRAMSAR_SRAMWTSA_Msk (0x100UL) /*!< SRAMWTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= STBRAMSAR ======================================================= */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos (0UL) /*!< NSBSTBR (Bit 0) */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk (0xfUL) /*!< NSBSTBR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DTCSAR ========================================================= */ + #define R_CPSCU_DTCSAR_DTCSTSA_Pos (0UL) /*!< DTCSTSA (Bit 0) */ + #define R_CPSCU_DTCSAR_DTCSTSA_Msk (0x1UL) /*!< DTCSTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== DMACSAR ======================================================== */ + #define R_CPSCU_DMACSAR_DMASTSA_Pos (0UL) /*!< DMASTSA (Bit 0) */ + #define R_CPSCU_DMACSAR_DMASTSA_Msk (0x1UL) /*!< DMASTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARA ======================================================== */ + #define R_CPSCU_ICUSARA_SAIRQCR_Pos (0UL) /*!< SAIRQCR (Bit 0) */ + #define R_CPSCU_ICUSARA_SAIRQCR_Msk (0x1UL) /*!< SAIRQCR (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARB ======================================================== */ + #define R_CPSCU_ICUSARB_SANMI_Pos (0UL) /*!< SANMI (Bit 0) */ + #define R_CPSCU_ICUSARB_SANMI_Msk (0x1UL) /*!< SANMI (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARC ======================================================== */ + #define R_CPSCU_ICUSARC_SADMACn_Pos (0UL) /*!< SADMACn (Bit 0) */ + #define R_CPSCU_ICUSARC_SADMACn_Msk (0xffUL) /*!< SADMACn (Bitfield-Mask: 0xff) */ +/* ======================================================== ICUSARD ======================================================== */ + #define R_CPSCU_ICUSARD_SASELSR0_Pos (0UL) /*!< SASELSR0 (Bit 0) */ + #define R_CPSCU_ICUSARD_SASELSR0_Msk (0x1UL) /*!< SASELSR0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARE ======================================================== */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos (16UL) /*!< SAIWDTWUP (Bit 16) */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk (0x10000UL) /*!< SAIWDTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Pos (18UL) /*!< SALVD1WUP (Bit 18) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Msk (0x40000UL) /*!< SALVD1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Pos (19UL) /*!< SALVD2WUP (Bit 19) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos (20UL) /*!< SAVBATTWUP (Bit 20) */ + #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk (0x100000UL) /*!< SAVBATTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk (0x2000000UL) /*!< SARTCPRDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos (27UL) /*!< SAUSBFS0WUP (Bit 27) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk (0x8000000UL) /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos (28UL) /*!< SAAGT1UDWUP (Bit 28) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos (29UL) /*!< SAAGT1CAWUP (Bit 29) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos (30UL) /*!< SAAGT1CBWUP (Bit 30) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos (31UL) /*!< SAIIC0WUP (Bit 31) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARF ======================================================== */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos (0UL) /*!< SAAGT3UDWUP (Bit 0) */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk (0x1UL) /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos (1UL) /*!< SAAGT3CAWUP (Bit 1) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk (0x2UL) /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos (2UL) /*!< SAAGT3CBWUP (Bit 2) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos (3UL) /*!< SACOMPHS0WUP (Bit 3) */ + #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk (0x8UL) /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Pos (7UL) /*!< SASOSCWUP (Bit 7) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Msk (0x80UL) /*!< SASOSCWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos (8UL) /*!< SAULP0UWUP (Bit 8) */ + #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk (0x100UL) /*!< SAULP0UWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos (9UL) /*!< SAULP0AWUP (Bit 9) */ + #define R_CPSCU_ICUSARF_SAULP0AWUP_Msk (0x200UL) /*!< SAULP0AWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP0BWUP_Pos (10UL) /*!< SAULP0BWUP (Bit 10) */ + #define R_CPSCU_ICUSARF_SAULP0BWUP_Msk (0x400UL) /*!< SAULP0BWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAI3CWUP_Pos (11UL) /*!< SAI3CWUP (Bit 11) */ + #define R_CPSCU_ICUSARF_SAI3CWUP_Msk (0x800UL) /*!< SAI3CWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP1UWUP_Pos (12UL) /*!< SAULP1UWUP (Bit 12) */ + #define R_CPSCU_ICUSARF_SAULP1UWUP_Msk (0x1000UL) /*!< SAULP1UWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP1AWUP_Pos (13UL) /*!< SAULP1AWUP (Bit 13) */ + #define R_CPSCU_ICUSARF_SAULP1AWUP_Msk (0x2000UL) /*!< SAULP1AWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP1BWUP_Pos (14UL) /*!< SAULP1BWUP (Bit 14) */ + #define R_CPSCU_ICUSARF_SAULP1BWUP_Msk (0x4000UL) /*!< SAULP1BWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAPDMWUP_Pos (15UL) /*!< SAPDMWUP (Bit 15) */ + #define R_CPSCU_ICUSARF_SAPDMWUP_Msk (0x8000UL) /*!< SAPDMWUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARG ======================================================== */ + #define R_CPSCU_ICUSARG_SAIELSR_Pos (0UL) /*!< SAIELSR (Bit 0) */ + #define R_CPSCU_ICUSARG_SAIELSR_Msk (0x1UL) /*!< SAIELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARH ======================================================== */ + #define R_CPSCU_ICUSARH_SAIELSR_Pos (0UL) /*!< SAIELSR (Bit 0) */ + #define R_CPSCU_ICUSARH_SAIELSR_Msk (0x1UL) /*!< SAIELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARI ======================================================== */ + #define R_CPSCU_ICUSARI_SAIELSR_Pos (0UL) /*!< SAIELSR (Bit 0) */ + #define R_CPSCU_ICUSARI_SAIELSR_Msk (0x1UL) /*!< SAIELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARJ ======================================================== */ + #define R_CPSCU_ICUSARJ_SAIELSR_Pos (0UL) /*!< SAIELSR (Bit 0) */ + #define R_CPSCU_ICUSARJ_SAIELSR_Msk (0x1UL) /*!< SAIELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARK ======================================================== */ + #define R_CPSCU_ICUSARK_SAIELSR_Pos (0UL) /*!< SAIELSR (Bit 0) */ + #define R_CPSCU_ICUSARK_SAIELSR_Msk (0x1UL) /*!< SAIELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARL ======================================================== */ + #define R_CPSCU_ICUSARL_SAIELSR_Pos (0UL) /*!< SAIELSR (Bit 0) */ + #define R_CPSCU_ICUSARL_SAIELSR_Msk (0x1UL) /*!< SAIELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARA ======================================================== */ + #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ + #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARB ======================================================== */ + #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ + #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARC ======================================================== */ + #define R_CPSCU_BUSSARC_BUSSC0_Pos (0UL) /*!< BUSSC0 (Bit 0) */ + #define R_CPSCU_BUSSARC_BUSSC0_Msk (0x1UL) /*!< BUSSC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSPARC ======================================================== */ + #define R_CPSCU_BUSPARC_BUSPA0_Pos (0UL) /*!< BUSPA0 (Bit 0) */ + #define R_CPSCU_BUSPARC_BUSPA0_Msk (0x1UL) /*!< BUSPA0 (Bitfield-Mask: 0x01) */ +/* ========================================================= NMISR ========================================================= */ + #define R_CPSCU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_CPSCU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_CPSCU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_PVD1ST_Pos (2UL) /*!< PVD1ST (Bit 2) */ + #define R_CPSCU_NMISR_PVD1ST_Msk (0x4UL) /*!< PVD1ST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_PVD2ST_Pos (3UL) /*!< PVD2ST (Bit 3) */ + #define R_CPSCU_NMISR_PVD2ST_Msk (0x8UL) /*!< PVD2ST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_SOSTST_Pos (5UL) /*!< SOSTST (Bit 5) */ + #define R_CPSCU_NMISR_SOSTST_Msk (0x20UL) /*!< SOSTST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_CPSCU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_CPSCU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_BUSST_Pos (12UL) /*!< BUSST (Bit 12) */ + #define R_CPSCU_NMISR_BUSST_Msk (0x1000UL) /*!< BUSST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_CMST_Pos (13UL) /*!< CMST (Bit 13) */ + #define R_CPSCU_NMISR_CMST_Msk (0x2000UL) /*!< CMST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_LMST_Pos (14UL) /*!< LMST (Bit 14) */ + #define R_CPSCU_NMISR_LMST_Msk (0x4000UL) /*!< LMST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_LUST_Pos (15UL) /*!< LUST (Bit 15) */ + #define R_CPSCU_NMISR_LUST_Msk (0x8000UL) /*!< LUST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_FPUEXCST_Pos (16UL) /*!< FPUEXCST (Bit 16) */ + #define R_CPSCU_NMISR_FPUEXCST_Msk (0x10000UL) /*!< FPUEXCST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_MRCRDST_Pos (17UL) /*!< MRCRDST (Bit 17) */ + #define R_CPSCU_NMISR_MRCRDST_Msk (0x20000UL) /*!< MRCRDST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_MRERDST_Pos (18UL) /*!< MRERDST (Bit 18) */ + #define R_CPSCU_NMISR_MRERDST_Msk (0x40000UL) /*!< MRERDST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_IPCST_Pos (20UL) /*!< IPCST (Bit 20) */ + #define R_CPSCU_NMISR_IPCST_Msk (0x100000UL) /*!< IPCST (Bitfield-Mask: 0x01) */ +/* ======================================================= MMPUSARA ======================================================== */ + #define R_CPSCU_MMPUSARA_MMPUASA_Pos (0UL) /*!< MMPUASA (Bit 0) */ + #define R_CPSCU_MMPUSARA_MMPUASA_Msk (0x1UL) /*!< MMPUASA (Bitfield-Mask: 0x01) */ +/* ======================================================= MMPUSARB ======================================================== */ + #define R_CPSCU_MMPUSARB_MMPUBSA_Pos (0UL) /*!< MMPUBSA (Bit 0) */ + #define R_CPSCU_MMPUSARB_MMPUBSA_Msk (0x1UL) /*!< MMPUBSA (Bitfield-Mask: 0x01) */ +/* ======================================================== CPUSAR ========================================================= */ + #define R_CPSCU_CPUSAR_CPUSA_Pos (0UL) /*!< CPUSA (Bit 0) */ + #define R_CPSCU_CPUSAR_CPUSA_Msk (0x1UL) /*!< CPUSA (Bitfield-Mask: 0x01) */ +/* ======================================================= DEBUGSAR ======================================================== */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Pos (0UL) /*!< DBGSA0 (Bit 0) */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Msk (0x1UL) /*!< DBGSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DMACCHSAR ======================================================= */ + #define R_CPSCU_DMACCHSAR_SADMAC0_Pos (0UL) /*!< SADMAC0 (Bit 0) */ + #define R_CPSCU_DMACCHSAR_SADMAC0_Msk (0x1UL) /*!< SADMAC0 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_DMACCHSAR_SADMAC1_Pos (16UL) /*!< SADMAC1 (Bit 16) */ + #define R_CPSCU_DMACCHSAR_SADMAC1_Msk (0x10000UL) /*!< SADMAC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== CPUDSAR ======================================================== */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DMACCHPAR ======================================================= */ + #define R_CPSCU_DMACCHPAR_PADMAC0_Pos (0UL) /*!< PADMAC0 (Bit 0) */ + #define R_CPSCU_DMACCHPAR_PADMAC0_Msk (0x1UL) /*!< PADMAC0 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_DMACCHPAR_PADMAC1_Pos (16UL) /*!< PADMAC1 (Bit 16) */ + #define R_CPSCU_DMACCHPAR_PADMAC1_Msk (0x10000UL) /*!< PADMAC1 (Bitfield-Mask: 0x01) */ +/* ====================================================== SRAMSABAR0 ======================================================= */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMSABAR1 ======================================================= */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMSABAR2 ======================================================= */ + #define R_CPSCU_SRAMSABAR2_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR2_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMSABAR3 ======================================================= */ + #define R_CPSCU_SRAMSABAR3_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR3_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ======================================================= CACHESAR ======================================================== */ + #define R_CPSCU_CACHESAR_CACHESA_Pos (0UL) /*!< CACHESA (Bit 0) */ + #define R_CPSCU_CACHESAR_CACHESA_Msk (0x1UL) /*!< CACHESA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CACHESAR_CACHEESA_Pos (2UL) /*!< CACHEESA (Bit 2) */ + #define R_CPSCU_CACHESAR_CACHEESA_Msk (0x4UL) /*!< CACHEESA (Bitfield-Mask: 0x01) */ +/* ======================================================== TCMSAR ========================================================= */ + #define R_CPSCU_TCMSAR_TCMSA_Pos (0UL) /*!< TCMSA (Bit 0) */ + #define R_CPSCU_TCMSAR_TCMSA_Msk (0x1UL) /*!< TCMSA (Bitfield-Mask: 0x01) */ +/* ======================================================= TCMSABARC ======================================================= */ + #define R_CPSCU_TCMSABARC_TCMSABA_Pos (13UL) /*!< TCMSABA (Bit 13) */ + #define R_CPSCU_TCMSABARC_TCMSABA_Msk (0x7e000UL) /*!< TCMSABA (Bitfield-Mask: 0x3f) */ +/* ======================================================= TCMSABARS ======================================================= */ + #define R_CPSCU_TCMSABARS_TCMSABA_Pos (13UL) /*!< TCMSABA (Bit 13) */ + #define R_CPSCU_TCMSABARS_TCMSABA_Msk (0x7e000UL) /*!< TCMSABA (Bitfield-Mask: 0x3f) */ +/* ======================================================= SRAMESAR ======================================================== */ + #define R_CPSCU_SRAMESAR_SRAMESA_Pos (0UL) /*!< SRAMESA (Bit 0) */ + #define R_CPSCU_SRAMESAR_SRAMESA_Msk (0x1UL) /*!< SRAMESA (Bitfield-Mask: 0x01) */ +/* ======================================================== TEVTRCR ======================================================== */ + #define R_CPSCU_TEVTRCR_TEVTE_Pos (0UL) /*!< TEVTE (Bit 0) */ + #define R_CPSCU_TEVTRCR_TEVTE_Msk (0x1UL) /*!< TEVTE (Bitfield-Mask: 0x01) */ + #define R_CPSCU_TEVTRCR_TEVTEICU_Pos (1UL) /*!< TEVTEICU (Bit 1) */ + #define R_CPSCU_TEVTRCR_TEVTEICU_Msk (0x2UL) /*!< TEVTEICU (Bitfield-Mask: 0x01) */ +/* ======================================================== IPCSAR ========================================================= */ + #define R_CPSCU_IPCSAR_SAIPCSEM_Pos (0UL) /*!< SAIPCSEM (Bit 0) */ + #define R_CPSCU_IPCSAR_SAIPCSEM_Msk (0x1UL) /*!< SAIPCSEM (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCSAR_SAIPCNMI_Pos (8UL) /*!< SAIPCNMI (Bit 8) */ + #define R_CPSCU_IPCSAR_SAIPCNMI_Msk (0x100UL) /*!< SAIPCNMI (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCSAR_SAIPCIR0_Pos (16UL) /*!< SAIPCIR0 (Bit 16) */ + #define R_CPSCU_IPCSAR_SAIPCIR0_Msk (0x10000UL) /*!< SAIPCIR0 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCSAR_SAIPCIR1_Pos (17UL) /*!< SAIPCIR1 (Bit 17) */ + #define R_CPSCU_IPCSAR_SAIPCIR1_Msk (0x20000UL) /*!< SAIPCIR1 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCSAR_SAIPCIR2_Pos (18UL) /*!< SAIPCIR2 (Bit 18) */ + #define R_CPSCU_IPCSAR_SAIPCIR2_Msk (0x40000UL) /*!< SAIPCIR2 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCSAR_SAIPCIR3_Pos (19UL) /*!< SAIPCIR3 (Bit 19) */ + #define R_CPSCU_IPCSAR_SAIPCIR3_Msk (0x80000UL) /*!< SAIPCIR3 (Bitfield-Mask: 0x01) */ +/* ======================================================== IPCPAR ========================================================= */ + #define R_CPSCU_IPCPAR_PAIPCSEM_Pos (0UL) /*!< PAIPCSEM (Bit 0) */ + #define R_CPSCU_IPCPAR_PAIPCSEM_Msk (0x1UL) /*!< PAIPCSEM (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCPAR_PAIPCNMI_Pos (8UL) /*!< PAIPCNMI (Bit 8) */ + #define R_CPSCU_IPCPAR_PAIPCNMI_Msk (0x100UL) /*!< PAIPCNMI (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCPAR_PAIPCIR0_Pos (16UL) /*!< PAIPCIR0 (Bit 16) */ + #define R_CPSCU_IPCPAR_PAIPCIR0_Msk (0x10000UL) /*!< PAIPCIR0 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCPAR_PAIPCIR1_Pos (17UL) /*!< PAIPCIR1 (Bit 17) */ + #define R_CPSCU_IPCPAR_PAIPCIR1_Msk (0x20000UL) /*!< PAIPCIR1 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCPAR_PAIPCIR2_Pos (18UL) /*!< PAIPCIR2 (Bit 18) */ + #define R_CPSCU_IPCPAR_PAIPCIR2_Msk (0x40000UL) /*!< PAIPCIR2 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCPAR_PAIPCIR3_Pos (19UL) /*!< PAIPCIR3 (Bit 19) */ + #define R_CPSCU_IPCPAR_PAIPCIR3_Msk (0x80000UL) /*!< PAIPCIR3 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC_B0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= ADCLKENR ======================================================== */ + #define R_ADC_B0_ADCLKENR_CLKEN_Pos (0UL) /*!< CLKEN (Bit 0) */ + #define R_ADC_B0_ADCLKENR_CLKEN_Msk (0x1UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCLKSR ======================================================== */ + #define R_ADC_B0_ADCLKSR_CLKSR_Pos (0UL) /*!< CLKSR (Bit 0) */ + #define R_ADC_B0_ADCLKSR_CLKSR_Msk (0x1UL) /*!< CLKSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCLKCR ======================================================== */ + #define R_ADC_B0_ADCLKCR_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ + #define R_ADC_B0_ADCLKCR_CLKSEL_Msk (0x3UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCLKCR_DIVR_Pos (16UL) /*!< DIVR (Bit 16) */ + #define R_ADC_B0_ADCLKCR_DIVR_Msk (0x70000UL) /*!< DIVR (Bitfield-Mask: 0x07) */ +/* ======================================================== ADSYCR ========================================================= */ + #define R_ADC_B0_ADSYCR_ADSYCYC_Pos (0UL) /*!< ADSYCYC (Bit 0) */ + #define R_ADC_B0_ADSYCR_ADSYCYC_Msk (0x7ffUL) /*!< ADSYCYC (Bitfield-Mask: 0x7ff) */ + #define R_ADC_B0_ADSYCR_ADSYDIS0_Pos (16UL) /*!< ADSYDIS0 (Bit 16) */ + #define R_ADC_B0_ADSYCR_ADSYDIS0_Msk (0x10000UL) /*!< ADSYDIS0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSYCR_ADSYDIS1_Pos (17UL) /*!< ADSYDIS1 (Bit 17) */ + #define R_ADC_B0_ADSYCR_ADSYDIS1_Msk (0x20000UL) /*!< ADSYDIS1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADERINTCR ======================================================= */ + #define R_ADC_B0_ADERINTCR_ADEIE0_Pos (0UL) /*!< ADEIE0 (Bit 0) */ + #define R_ADC_B0_ADERINTCR_ADEIE0_Msk (0x1UL) /*!< ADEIE0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADERINTCR_ADEIE1_Pos (1UL) /*!< ADEIE1 (Bit 1) */ + #define R_ADC_B0_ADERINTCR_ADEIE1_Msk (0x2UL) /*!< ADEIE1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADOVFINTCR ======================================================= */ + #define R_ADC_B0_ADOVFINTCR_ADOVFIE0_Pos (0UL) /*!< ADOVFIE0 (Bit 0) */ + #define R_ADC_B0_ADOVFINTCR_ADOVFIE0_Msk (0x1UL) /*!< ADOVFIE0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFINTCR_ADOVFIE1_Pos (1UL) /*!< ADOVFIE1 (Bit 1) */ + #define R_ADC_B0_ADOVFINTCR_ADOVFIE1_Msk (0x2UL) /*!< ADOVFIE1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCALINTCR ======================================================= */ + #define R_ADC_B0_ADCALINTCR_CALENDIE0_Pos (16UL) /*!< CALENDIE0 (Bit 16) */ + #define R_ADC_B0_ADCALINTCR_CALENDIE0_Msk (0x10000UL) /*!< CALENDIE0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCALINTCR_CALENDIE1_Pos (17UL) /*!< CALENDIE1 (Bit 17) */ + #define R_ADC_B0_ADCALINTCR_CALENDIE1_Msk (0x20000UL) /*!< CALENDIE1 (Bitfield-Mask: 0x01) */ +/* ========================================================= ADMDR ========================================================= */ + #define R_ADC_B0_ADMDR_ADMD0_Pos (0UL) /*!< ADMD0 (Bit 0) */ + #define R_ADC_B0_ADMDR_ADMD0_Msk (0xfUL) /*!< ADMD0 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADMDR_ADMD1_Pos (8UL) /*!< ADMD1 (Bit 8) */ + #define R_ADC_B0_ADMDR_ADMD1_Msk (0xf00UL) /*!< ADMD1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC_B0_ADGSPCR_PGS0_Pos (0UL) /*!< PGS0 (Bit 0) */ + #define R_ADC_B0_ADGSPCR_PGS0_Msk (0x1UL) /*!< PGS0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_RSCN0_Pos (1UL) /*!< RSCN0 (Bit 1) */ + #define R_ADC_B0_ADGSPCR_RSCN0_Msk (0x2UL) /*!< RSCN0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_LGRRS0_Pos (2UL) /*!< LGRRS0 (Bit 2) */ + #define R_ADC_B0_ADGSPCR_LGRRS0_Msk (0x4UL) /*!< LGRRS0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_GRP0_Pos (3UL) /*!< GRP0 (Bit 3) */ + #define R_ADC_B0_ADGSPCR_GRP0_Msk (0x8UL) /*!< GRP0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_PGS1_Pos (8UL) /*!< PGS1 (Bit 8) */ + #define R_ADC_B0_ADGSPCR_PGS1_Msk (0x100UL) /*!< PGS1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_RSCN1_Pos (9UL) /*!< RSCN1 (Bit 9) */ + #define R_ADC_B0_ADGSPCR_RSCN1_Msk (0x200UL) /*!< RSCN1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_LGRRS1_Pos (10UL) /*!< LGRRS1 (Bit 10) */ + #define R_ADC_B0_ADGSPCR_LGRRS1_Msk (0x400UL) /*!< LGRRS1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_GRP1_Pos (11UL) /*!< GRP1 (Bit 11) */ + #define R_ADC_B0_ADGSPCR_GRP1_Msk (0x800UL) /*!< GRP1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSGER ========================================================= */ + #define R_ADC_B0_ADSGER_SGREn_Pos (0UL) /*!< SGREn (Bit 0) */ + #define R_ADC_B0_ADSGER_SGREn_Msk (0x1ffUL) /*!< SGREn (Bitfield-Mask: 0x1ff) */ +/* ======================================================== ADSGCR0 ======================================================== */ + #define R_ADC_B0_ADSGCR0_SGADS0_Pos (0UL) /*!< SGADS0 (Bit 0) */ + #define R_ADC_B0_ADSGCR0_SGADS0_Msk (0x3UL) /*!< SGADS0 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADSGCR0_SGADS1_Pos (8UL) /*!< SGADS1 (Bit 8) */ + #define R_ADC_B0_ADSGCR0_SGADS1_Msk (0x300UL) /*!< SGADS1 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADSGCR0_SGADS2_Pos (16UL) /*!< SGADS2 (Bit 16) */ + #define R_ADC_B0_ADSGCR0_SGADS2_Msk (0x30000UL) /*!< SGADS2 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADSGCR0_SGADS3_Pos (24UL) /*!< SGADS3 (Bit 24) */ + #define R_ADC_B0_ADSGCR0_SGADS3_Msk (0x3000000UL) /*!< SGADS3 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADSGCR1 ======================================================== */ + #define R_ADC_B0_ADSGCR1_SGADS4_Pos (0UL) /*!< SGADS4 (Bit 0) */ + #define R_ADC_B0_ADSGCR1_SGADS4_Msk (0x3UL) /*!< SGADS4 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADSGCR1_SGADS5_Pos (8UL) /*!< SGADS5 (Bit 8) */ + #define R_ADC_B0_ADSGCR1_SGADS5_Msk (0x300UL) /*!< SGADS5 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADSGCR1_SGADS6_Pos (16UL) /*!< SGADS6 (Bit 16) */ + #define R_ADC_B0_ADSGCR1_SGADS6_Msk (0x30000UL) /*!< SGADS6 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADSGCR1_SGADS7_Pos (24UL) /*!< SGADS7 (Bit 24) */ + #define R_ADC_B0_ADSGCR1_SGADS7_Msk (0x3000000UL) /*!< SGADS7 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADSGCR2 ======================================================== */ + #define R_ADC_B0_ADSGCR2_SGADS8_Pos (0UL) /*!< SGADS8 (Bit 0) */ + #define R_ADC_B0_ADSGCR2_SGADS8_Msk (0x3UL) /*!< SGADS8 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADINTCR ======================================================== */ + #define R_ADC_B0_ADINTCR_ADIEn_Pos (0UL) /*!< ADIEn (Bit 0) */ + #define R_ADC_B0_ADINTCR_ADIEn_Msk (0x1ffUL) /*!< ADIEn (Bitfield-Mask: 0x1ff) */ +/* ======================================================= ADTRGEXT0 ======================================================= */ + #define R_ADC_B0_ADTRGEXT0_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT0_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT0_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT0_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT1 ======================================================= */ + #define R_ADC_B0_ADTRGEXT1_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT1_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT1_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT1_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT2 ======================================================= */ + #define R_ADC_B0_ADTRGEXT2_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT2_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT2_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT2_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT3 ======================================================= */ + #define R_ADC_B0_ADTRGEXT3_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT3_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT3_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT3_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT4 ======================================================= */ + #define R_ADC_B0_ADTRGEXT4_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT4_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT4_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT4_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT5 ======================================================= */ + #define R_ADC_B0_ADTRGEXT5_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT5_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT5_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT5_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT6 ======================================================= */ + #define R_ADC_B0_ADTRGEXT6_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT6_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT6_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT6_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT7 ======================================================= */ + #define R_ADC_B0_ADTRGEXT7_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT7_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT7_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT7_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT8 ======================================================= */ + #define R_ADC_B0_ADTRGEXT8_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT8_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT8_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT8_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGELC0 ======================================================= */ + #define R_ADC_B0_ADTRGELC0_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC0_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC1 ======================================================= */ + #define R_ADC_B0_ADTRGELC1_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC1_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC2 ======================================================= */ + #define R_ADC_B0_ADTRGELC2_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC2_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC3 ======================================================= */ + #define R_ADC_B0_ADTRGELC3_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC3_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC4 ======================================================= */ + #define R_ADC_B0_ADTRGELC4_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC4_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC5 ======================================================= */ + #define R_ADC_B0_ADTRGELC5_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC5_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC6 ======================================================= */ + #define R_ADC_B0_ADTRGELC6_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC6_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC7 ======================================================= */ + #define R_ADC_B0_ADTRGELC7_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC7_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC8 ======================================================= */ + #define R_ADC_B0_ADTRGELC8_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC8_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGGPT0 ======================================================= */ + #define R_ADC_B0_ADTRGGPT0_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT0_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT0_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT0_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT1 ======================================================= */ + #define R_ADC_B0_ADTRGGPT1_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT1_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT1_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT1_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT2 ======================================================= */ + #define R_ADC_B0_ADTRGGPT2_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT2_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT2_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT2_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT3 ======================================================= */ + #define R_ADC_B0_ADTRGGPT3_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT3_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT3_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT3_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT4 ======================================================= */ + #define R_ADC_B0_ADTRGGPT4_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT4_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT4_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT4_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT5 ======================================================= */ + #define R_ADC_B0_ADTRGGPT5_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT5_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT5_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT5_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT6 ======================================================= */ + #define R_ADC_B0_ADTRGGPT6_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT6_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT6_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT6_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT7 ======================================================= */ + #define R_ADC_B0_ADTRGGPT7_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT7_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT7_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT7_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT8 ======================================================= */ + #define R_ADC_B0_ADTRGGPT8_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT8_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT8_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT8_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGDLR0 ======================================================= */ + #define R_ADC_B0_ADTRGDLR0_TRGDLY0_Pos (0UL) /*!< TRGDLY0 (Bit 0) */ + #define R_ADC_B0_ADTRGDLR0_TRGDLY0_Msk (0xffUL) /*!< TRGDLY0 (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADTRGDLR0_TRGDLY1_Pos (16UL) /*!< TRGDLY1 (Bit 16) */ + #define R_ADC_B0_ADTRGDLR0_TRGDLY1_Msk (0xff0000UL) /*!< TRGDLY1 (Bitfield-Mask: 0xff) */ +/* ======================================================= ADTRGDLR1 ======================================================= */ + #define R_ADC_B0_ADTRGDLR1_TRGDLY2_Pos (0UL) /*!< TRGDLY2 (Bit 0) */ + #define R_ADC_B0_ADTRGDLR1_TRGDLY2_Msk (0xffUL) /*!< TRGDLY2 (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADTRGDLR1_TRGDLY3_Pos (16UL) /*!< TRGDLY3 (Bit 16) */ + #define R_ADC_B0_ADTRGDLR1_TRGDLY3_Msk (0xff0000UL) /*!< TRGDLY3 (Bitfield-Mask: 0xff) */ +/* ======================================================= ADTRGDLR2 ======================================================= */ + #define R_ADC_B0_ADTRGDLR2_TRGDLY4_Pos (0UL) /*!< TRGDLY4 (Bit 0) */ + #define R_ADC_B0_ADTRGDLR2_TRGDLY4_Msk (0xffUL) /*!< TRGDLY4 (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADTRGDLR2_TRGDLY5_Pos (16UL) /*!< TRGDLY5 (Bit 16) */ + #define R_ADC_B0_ADTRGDLR2_TRGDLY5_Msk (0xff0000UL) /*!< TRGDLY5 (Bitfield-Mask: 0xff) */ +/* ======================================================= ADTRGDLR3 ======================================================= */ + #define R_ADC_B0_ADTRGDLR3_TRGDLY6_Pos (0UL) /*!< TRGDLY6 (Bit 0) */ + #define R_ADC_B0_ADTRGDLR3_TRGDLY6_Msk (0xffUL) /*!< TRGDLY6 (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADTRGDLR3_TRGDLY7_Pos (16UL) /*!< TRGDLY7 (Bit 16) */ + #define R_ADC_B0_ADTRGDLR3_TRGDLY7_Msk (0xff0000UL) /*!< TRGDLY7 (Bitfield-Mask: 0xff) */ +/* ======================================================= ADTRGDLR4 ======================================================= */ + #define R_ADC_B0_ADTRGDLR4_TRGDLY8_Pos (0UL) /*!< TRGDLY8 (Bit 0) */ + #define R_ADC_B0_ADTRGDLR4_TRGDLY8_Msk (0xffUL) /*!< TRGDLY8 (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR0 ======================================================== */ + #define R_ADC_B0_ADSGDCR0_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR0_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR0_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR0_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR0_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR0_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR0_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR0_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR0_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR0_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR1 ======================================================== */ + #define R_ADC_B0_ADSGDCR1_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR1_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR1_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR1_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR1_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR1_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR1_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR1_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR1_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR1_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR2 ======================================================== */ + #define R_ADC_B0_ADSGDCR2_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR2_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR2_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR2_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR2_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR2_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR2_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR2_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR2_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR2_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR3 ======================================================== */ + #define R_ADC_B0_ADSGDCR3_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR3_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR3_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR3_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR3_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR3_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR3_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR3_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR3_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR3_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR4 ======================================================== */ + #define R_ADC_B0_ADSGDCR4_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR4_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR4_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR4_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR4_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR4_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR4_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR4_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR4_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR4_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR5 ======================================================== */ + #define R_ADC_B0_ADSGDCR5_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR5_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR5_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR5_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR5_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR5_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR5_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR5_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR5_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR5_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR6 ======================================================== */ + #define R_ADC_B0_ADSGDCR6_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR6_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR6_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR6_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR6_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR6_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR6_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR6_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR6_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR6_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR7 ======================================================== */ + #define R_ADC_B0_ADSGDCR7_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR7_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR7_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR7_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR7_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR7_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR7_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR7_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR7_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR7_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR8 ======================================================== */ + #define R_ADC_B0_ADSGDCR8_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR8_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR8_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR8_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR8_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR8_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR8_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR8_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR8_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR8_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTR0 ======================================================== */ + #define R_ADC_B0_ADSSTR0_SST0_Pos (0UL) /*!< SST0 (Bit 0) */ + #define R_ADC_B0_ADSSTR0_SST0_Msk (0x3ffUL) /*!< SST0 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR0_SST1_Pos (16UL) /*!< SST1 (Bit 16) */ + #define R_ADC_B0_ADSSTR0_SST1_Msk (0x3ff0000UL) /*!< SST1 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR1 ======================================================== */ + #define R_ADC_B0_ADSSTR1_SST2_Pos (0UL) /*!< SST2 (Bit 0) */ + #define R_ADC_B0_ADSSTR1_SST2_Msk (0x3ffUL) /*!< SST2 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR1_SST3_Pos (16UL) /*!< SST3 (Bit 16) */ + #define R_ADC_B0_ADSSTR1_SST3_Msk (0x3ff0000UL) /*!< SST3 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR2 ======================================================== */ + #define R_ADC_B0_ADSSTR2_SST4_Pos (0UL) /*!< SST4 (Bit 0) */ + #define R_ADC_B0_ADSSTR2_SST4_Msk (0x3ffUL) /*!< SST4 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR2_SST5_Pos (16UL) /*!< SST5 (Bit 16) */ + #define R_ADC_B0_ADSSTR2_SST5_Msk (0x3ff0000UL) /*!< SST5 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR3 ======================================================== */ + #define R_ADC_B0_ADSSTR3_SST6_Pos (0UL) /*!< SST6 (Bit 0) */ + #define R_ADC_B0_ADSSTR3_SST6_Msk (0x3ffUL) /*!< SST6 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR3_SST7_Pos (16UL) /*!< SST7 (Bit 16) */ + #define R_ADC_B0_ADSSTR3_SST7_Msk (0x3ff0000UL) /*!< SST7 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR4 ======================================================== */ + #define R_ADC_B0_ADSSTR4_SST8_Pos (0UL) /*!< SST8 (Bit 0) */ + #define R_ADC_B0_ADSSTR4_SST8_Msk (0x3ffUL) /*!< SST8 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR4_SST9_Pos (16UL) /*!< SST9 (Bit 16) */ + #define R_ADC_B0_ADSSTR4_SST9_Msk (0x3ff0000UL) /*!< SST9 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR5 ======================================================== */ + #define R_ADC_B0_ADSSTR5_SST10_Pos (0UL) /*!< SST10 (Bit 0) */ + #define R_ADC_B0_ADSSTR5_SST10_Msk (0x3ffUL) /*!< SST10 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR5_SST11_Pos (16UL) /*!< SST11 (Bit 16) */ + #define R_ADC_B0_ADSSTR5_SST11_Msk (0x3ff0000UL) /*!< SST11 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR6 ======================================================== */ + #define R_ADC_B0_ADSSTR6_SST12_Pos (0UL) /*!< SST12 (Bit 0) */ + #define R_ADC_B0_ADSSTR6_SST12_Msk (0x3ffUL) /*!< SST12 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR6_SST13_Pos (16UL) /*!< SST13 (Bit 16) */ + #define R_ADC_B0_ADSSTR6_SST13_Msk (0x3ff0000UL) /*!< SST13 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR7 ======================================================== */ + #define R_ADC_B0_ADSSTR7_SST14_Pos (0UL) /*!< SST14 (Bit 0) */ + #define R_ADC_B0_ADSSTR7_SST14_Msk (0x3ffUL) /*!< SST14 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR7_SST15_Pos (16UL) /*!< SST15 (Bit 16) */ + #define R_ADC_B0_ADSSTR7_SST15_Msk (0x3ff0000UL) /*!< SST15 (Bitfield-Mask: 0x3ff) */ +/* ======================================================= ADCNVSTR ======================================================== */ + #define R_ADC_B0_ADCNVSTR_CST0_Pos (0UL) /*!< CST0 (Bit 0) */ + #define R_ADC_B0_ADCNVSTR_CST0_Msk (0x3fUL) /*!< CST0 (Bitfield-Mask: 0x3f) */ + #define R_ADC_B0_ADCNVSTR_CST1_Pos (8UL) /*!< CST1 (Bit 8) */ + #define R_ADC_B0_ADCNVSTR_CST1_Msk (0x3f00UL) /*!< CST1 (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADCALSTCR ======================================================= */ + #define R_ADC_B0_ADCALSTCR_CALADSST_Pos (0UL) /*!< CALADSST (Bit 0) */ + #define R_ADC_B0_ADCALSTCR_CALADSST_Msk (0x3ffUL) /*!< CALADSST (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADCALSTCR_CALADCST_Pos (16UL) /*!< CALADCST (Bit 16) */ + #define R_ADC_B0_ADCALSTCR_CALADCST_Msk (0x3f0000UL) /*!< CALADCST (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADSHCR0 ======================================================== */ + #define R_ADC_B0_ADSHCR0_SHEN_Pos (0UL) /*!< SHEN (Bit 0) */ + #define R_ADC_B0_ADSHCR0_SHEN_Msk (0x1UL) /*!< SHEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSHCR0_SHMD_Pos (16UL) /*!< SHMD (Bit 16) */ + #define R_ADC_B0_ADSHCR0_SHMD_Msk (0x10000UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSHSTR0 ======================================================== */ + #define R_ADC_B0_ADSHSTR0_SHSST_Pos (0UL) /*!< SHSST (Bit 0) */ + #define R_ADC_B0_ADSHSTR0_SHSST_Msk (0xffUL) /*!< SHSST (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADSHSTR0_SHHST_Pos (16UL) /*!< SHHST (Bit 16) */ + #define R_ADC_B0_ADSHSTR0_SHHST_Msk (0x70000UL) /*!< SHHST (Bitfield-Mask: 0x07) */ +/* ======================================================== ADSHCR1 ======================================================== */ + #define R_ADC_B0_ADSHCR1_SHEN_Pos (0UL) /*!< SHEN (Bit 0) */ + #define R_ADC_B0_ADSHCR1_SHEN_Msk (0x1UL) /*!< SHEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSHCR1_SHMD_Pos (16UL) /*!< SHMD (Bit 16) */ + #define R_ADC_B0_ADSHCR1_SHMD_Msk (0x10000UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSHSTR1 ======================================================== */ + #define R_ADC_B0_ADSHSTR1_SHSST_Pos (0UL) /*!< SHSST (Bit 0) */ + #define R_ADC_B0_ADSHSTR1_SHSST_Msk (0xffUL) /*!< SHSST (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADSHSTR1_SHHST_Pos (16UL) /*!< SHHST (Bit 16) */ + #define R_ADC_B0_ADSHSTR1_SHHST_Msk (0x70000UL) /*!< SHHST (Bitfield-Mask: 0x07) */ +/* ======================================================= ADCALSHCR ======================================================= */ + #define R_ADC_B0_ADCALSHCR_CALSHSST_Pos (0UL) /*!< CALSHSST (Bit 0) */ + #define R_ADC_B0_ADCALSHCR_CALSHSST_Msk (0xffUL) /*!< CALSHSST (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADCALSHCR_CALSHHST_Pos (16UL) /*!< CALSHHST (Bit 16) */ + #define R_ADC_B0_ADCALSHCR_CALSHHST_Msk (0x70000UL) /*!< CALSHHST (Bitfield-Mask: 0x07) */ +/* ======================================================== ADREFCR ======================================================== */ + #define R_ADC_B0_ADREFCR_VDE_Pos (0UL) /*!< VDE (Bit 0) */ + #define R_ADC_B0_ADREFCR_VDE_Msk (0x1UL) /*!< VDE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADDFSR0 ======================================================== */ + #define R_ADC_B0_ADDFSR0_DFSEL0_Pos (0UL) /*!< DFSEL0 (Bit 0) */ + #define R_ADC_B0_ADDFSR0_DFSEL0_Msk (0x3UL) /*!< DFSEL0 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDFSR0_DFSEL1_Pos (8UL) /*!< DFSEL1 (Bit 8) */ + #define R_ADC_B0_ADDFSR0_DFSEL1_Msk (0x300UL) /*!< DFSEL1 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDFSR0_DFSEL2_Pos (16UL) /*!< DFSEL2 (Bit 16) */ + #define R_ADC_B0_ADDFSR0_DFSEL2_Msk (0x30000UL) /*!< DFSEL2 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDFSR0_DFSEL3_Pos (24UL) /*!< DFSEL3 (Bit 24) */ + #define R_ADC_B0_ADDFSR0_DFSEL3_Msk (0x3000000UL) /*!< DFSEL3 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADDFSR1 ======================================================== */ + #define R_ADC_B0_ADDFSR1_DFSEL0_Pos (0UL) /*!< DFSEL0 (Bit 0) */ + #define R_ADC_B0_ADDFSR1_DFSEL0_Msk (0x3UL) /*!< DFSEL0 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDFSR1_DFSEL1_Pos (8UL) /*!< DFSEL1 (Bit 8) */ + #define R_ADC_B0_ADDFSR1_DFSEL1_Msk (0x300UL) /*!< DFSEL1 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDFSR1_DFSEL2_Pos (16UL) /*!< DFSEL2 (Bit 16) */ + #define R_ADC_B0_ADDFSR1_DFSEL2_Msk (0x30000UL) /*!< DFSEL2 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDFSR1_DFSEL3_Pos (24UL) /*!< DFSEL3 (Bit 24) */ + #define R_ADC_B0_ADDFSR1_DFSEL3_Msk (0x3000000UL) /*!< DFSEL3 (Bitfield-Mask: 0x03) */ +/* ======================================================= ADUOFTR0 ======================================================== */ + #define R_ADC_B0_ADUOFTR0_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR0_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR1 ======================================================== */ + #define R_ADC_B0_ADUOFTR1_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR1_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR2 ======================================================== */ + #define R_ADC_B0_ADUOFTR2_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR2_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR3 ======================================================== */ + #define R_ADC_B0_ADUOFTR3_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR3_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR4 ======================================================== */ + #define R_ADC_B0_ADUOFTR4_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR4_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR5 ======================================================== */ + #define R_ADC_B0_ADUOFTR5_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR5_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR6 ======================================================== */ + #define R_ADC_B0_ADUOFTR6_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR6_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR7 ======================================================== */ + #define R_ADC_B0_ADUOFTR7_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR7_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADUGTR0 ======================================================== */ + #define R_ADC_B0_ADUGTR0_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR0_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR0_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR0_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ======================================================== ADUGTR1 ======================================================== */ + #define R_ADC_B0_ADUGTR1_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR1_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR1_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR1_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ======================================================== ADUGTR2 ======================================================== */ + #define R_ADC_B0_ADUGTR2_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR2_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR2_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR2_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ======================================================== ADUGTR3 ======================================================== */ + #define R_ADC_B0_ADUGTR3_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR3_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR3_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR3_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ======================================================== ADUGTR4 ======================================================== */ + #define R_ADC_B0_ADUGTR4_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR4_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR4_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR4_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ======================================================== ADUGTR5 ======================================================== */ + #define R_ADC_B0_ADUGTR5_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR5_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR5_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR5_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ======================================================== ADUGTR6 ======================================================== */ + #define R_ADC_B0_ADUGTR6_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR6_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR6_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR6_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ======================================================== ADUGTR7 ======================================================== */ + #define R_ADC_B0_ADUGTR7_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR7_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR7_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR7_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ====================================================== ADLIMINTCR ======================================================= */ + #define R_ADC_B0_ADLIMINTCR_LIMIEn_Pos (0UL) /*!< LIMIEn (Bit 0) */ + #define R_ADC_B0_ADLIMINTCR_LIMIEn_Msk (0x1ffUL) /*!< LIMIEn (Bitfield-Mask: 0x1ff) */ +/* ======================================================= ADLIMTR0 ======================================================== */ + #define R_ADC_B0_ADLIMTR0_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR0_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR0_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR0_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR1 ======================================================== */ + #define R_ADC_B0_ADLIMTR1_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR1_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR1_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR1_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR2 ======================================================== */ + #define R_ADC_B0_ADLIMTR2_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR2_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR2_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR2_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR3 ======================================================== */ + #define R_ADC_B0_ADLIMTR3_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR3_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR3_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR3_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR4 ======================================================== */ + #define R_ADC_B0_ADLIMTR4_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR4_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR4_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR4_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR5 ======================================================== */ + #define R_ADC_B0_ADLIMTR5_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR5_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR5_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR5_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR6 ======================================================== */ + #define R_ADC_B0_ADLIMTR6_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR6_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR6_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR6_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR7 ======================================================== */ + #define R_ADC_B0_ADLIMTR7_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR7_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR7_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR7_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPENR ======================================================== */ + #define R_ADC_B0_ADCMPENR_CMPENn_Pos (0UL) /*!< CMPENn (Bit 0) */ + #define R_ADC_B0_ADCMPENR_CMPENn_Msk (0xffUL) /*!< CMPENn (Bitfield-Mask: 0xff) */ +/* ====================================================== ADCMPINTCR ======================================================= */ + #define R_ADC_B0_ADCMPINTCR_CMPIEn_Pos (0UL) /*!< CMPIEn (Bit 0) */ + #define R_ADC_B0_ADCMPINTCR_CMPIEn_Msk (0xfUL) /*!< CMPIEn (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCCMPCR0 ======================================================= */ + #define R_ADC_B0_ADCCMPCR0_CCMPCND_Pos (0UL) /*!< CCMPCND (Bit 0) */ + #define R_ADC_B0_ADCCMPCR0_CCMPCND_Msk (0x3UL) /*!< CCMPCND (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCCMPCR0_CCMPTBLm_Pos (16UL) /*!< CCMPTBLm (Bit 16) */ + #define R_ADC_B0_ADCCMPCR0_CCMPTBLm_Msk (0xff0000UL) /*!< CCMPTBLm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADCCMPCR1 ======================================================= */ + #define R_ADC_B0_ADCCMPCR1_CCMPCND_Pos (0UL) /*!< CCMPCND (Bit 0) */ + #define R_ADC_B0_ADCCMPCR1_CCMPCND_Msk (0x3UL) /*!< CCMPCND (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCCMPCR1_CCMPTBLm_Pos (16UL) /*!< CCMPTBLm (Bit 16) */ + #define R_ADC_B0_ADCCMPCR1_CCMPTBLm_Msk (0xff0000UL) /*!< CCMPTBLm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADCMPMDR0 ======================================================= */ + #define R_ADC_B0_ADCMPMDR0_CMPMD0_Pos (0UL) /*!< CMPMD0 (Bit 0) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD0_Msk (0x3UL) /*!< CMPMD0 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD1_Pos (8UL) /*!< CMPMD1 (Bit 8) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD1_Msk (0x300UL) /*!< CMPMD1 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD2_Pos (16UL) /*!< CMPMD2 (Bit 16) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD2_Msk (0x30000UL) /*!< CMPMD2 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD3_Pos (24UL) /*!< CMPMD3 (Bit 24) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD3_Msk (0x3000000UL) /*!< CMPMD3 (Bitfield-Mask: 0x03) */ +/* ======================================================= ADCMPMDR1 ======================================================= */ + #define R_ADC_B0_ADCMPMDR1_CMPMD4_Pos (0UL) /*!< CMPMD4 (Bit 0) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD4_Msk (0x3UL) /*!< CMPMD4 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD5_Pos (8UL) /*!< CMPMD5 (Bit 8) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD5_Msk (0x300UL) /*!< CMPMD5 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD6_Pos (16UL) /*!< CMPMD6 (Bit 16) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD6_Msk (0x30000UL) /*!< CMPMD6 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD7_Pos (24UL) /*!< CMPMD7 (Bit 24) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD7_Msk (0x3000000UL) /*!< CMPMD7 (Bitfield-Mask: 0x03) */ +/* ======================================================= ADCMPTBR0 ======================================================= */ + #define R_ADC_B0_ADCMPTBR0_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR0_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR0_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR0_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR1 ======================================================= */ + #define R_ADC_B0_ADCMPTBR1_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR1_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR1_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR1_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR2 ======================================================= */ + #define R_ADC_B0_ADCMPTBR2_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR2_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR2_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR2_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR3 ======================================================= */ + #define R_ADC_B0_ADCMPTBR3_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR3_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR3_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR3_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR4 ======================================================= */ + #define R_ADC_B0_ADCMPTBR4_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR4_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR4_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR4_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR5 ======================================================= */ + #define R_ADC_B0_ADCMPTBR5_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR5_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR5_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR5_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR6 ======================================================= */ + #define R_ADC_B0_ADCMPTBR6_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR6_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR6_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR6_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR7 ======================================================= */ + #define R_ADC_B0_ADCMPTBR7_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR7_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR7_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR7_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADFIFOCR ======================================================== */ + #define R_ADC_B0_ADFIFOCR_FIFOEN0_Pos (0UL) /*!< FIFOEN0 (Bit 0) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN0_Msk (0x1UL) /*!< FIFOEN0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN1_Pos (1UL) /*!< FIFOEN1 (Bit 1) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN1_Msk (0x2UL) /*!< FIFOEN1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN2_Pos (2UL) /*!< FIFOEN2 (Bit 2) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN2_Msk (0x4UL) /*!< FIFOEN2 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN3_Pos (3UL) /*!< FIFOEN3 (Bit 3) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN3_Msk (0x8UL) /*!< FIFOEN3 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN4_Pos (4UL) /*!< FIFOEN4 (Bit 4) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN4_Msk (0x10UL) /*!< FIFOEN4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN5_Pos (5UL) /*!< FIFOEN5 (Bit 5) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN5_Msk (0x20UL) /*!< FIFOEN5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN6_Pos (6UL) /*!< FIFOEN6 (Bit 6) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN6_Msk (0x40UL) /*!< FIFOEN6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN7_Pos (7UL) /*!< FIFOEN7 (Bit 7) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN7_Msk (0x80UL) /*!< FIFOEN7 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN8_Pos (8UL) /*!< FIFOEN8 (Bit 8) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN8_Msk (0x100UL) /*!< FIFOEN8 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADFIFOINTCR ====================================================== */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE0_Pos (0UL) /*!< FIFOIE0 (Bit 0) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE0_Msk (0x1UL) /*!< FIFOIE0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE1_Pos (1UL) /*!< FIFOIE1 (Bit 1) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE1_Msk (0x2UL) /*!< FIFOIE1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE2_Pos (2UL) /*!< FIFOIE2 (Bit 2) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE2_Msk (0x4UL) /*!< FIFOIE2 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE3_Pos (3UL) /*!< FIFOIE3 (Bit 3) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE3_Msk (0x8UL) /*!< FIFOIE3 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE4_Pos (4UL) /*!< FIFOIE4 (Bit 4) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE4_Msk (0x10UL) /*!< FIFOIE4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE5_Pos (5UL) /*!< FIFOIE5 (Bit 5) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE5_Msk (0x20UL) /*!< FIFOIE5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE6_Pos (6UL) /*!< FIFOIE6 (Bit 6) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE6_Msk (0x40UL) /*!< FIFOIE6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE7_Pos (7UL) /*!< FIFOIE7 (Bit 7) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE7_Msk (0x80UL) /*!< FIFOIE7 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE8_Pos (8UL) /*!< FIFOIE8 (Bit 8) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE8_Msk (0x100UL) /*!< FIFOIE8 (Bitfield-Mask: 0x01) */ +/* ===================================================== ADFIFOINTLR0 ====================================================== */ + #define R_ADC_B0_ADFIFOINTLR0_FIFOILV0_Pos (0UL) /*!< FIFOILV0 (Bit 0) */ + #define R_ADC_B0_ADFIFOINTLR0_FIFOILV0_Msk (0xfUL) /*!< FIFOILV0 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOINTLR0_FIFOILV1_Pos (16UL) /*!< FIFOILV1 (Bit 16) */ + #define R_ADC_B0_ADFIFOINTLR0_FIFOILV1_Msk (0xf0000UL) /*!< FIFOILV1 (Bitfield-Mask: 0x0f) */ +/* ===================================================== ADFIFOINTLR1 ====================================================== */ + #define R_ADC_B0_ADFIFOINTLR1_FIFOILV2_Pos (0UL) /*!< FIFOILV2 (Bit 0) */ + #define R_ADC_B0_ADFIFOINTLR1_FIFOILV2_Msk (0xfUL) /*!< FIFOILV2 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOINTLR1_FIFOILV3_Pos (16UL) /*!< FIFOILV3 (Bit 16) */ + #define R_ADC_B0_ADFIFOINTLR1_FIFOILV3_Msk (0xf0000UL) /*!< FIFOILV3 (Bitfield-Mask: 0x0f) */ +/* ===================================================== ADFIFOINTLR2 ====================================================== */ + #define R_ADC_B0_ADFIFOINTLR2_FIFOILV4_Pos (0UL) /*!< FIFOILV4 (Bit 0) */ + #define R_ADC_B0_ADFIFOINTLR2_FIFOILV4_Msk (0xfUL) /*!< FIFOILV4 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOINTLR2_FIFOILV5_Pos (16UL) /*!< FIFOILV5 (Bit 16) */ + #define R_ADC_B0_ADFIFOINTLR2_FIFOILV5_Msk (0xf0000UL) /*!< FIFOILV5 (Bitfield-Mask: 0x0f) */ +/* ===================================================== ADFIFOINTLR3 ====================================================== */ + #define R_ADC_B0_ADFIFOINTLR3_FIFOILV6_Pos (0UL) /*!< FIFOILV6 (Bit 0) */ + #define R_ADC_B0_ADFIFOINTLR3_FIFOILV6_Msk (0xfUL) /*!< FIFOILV6 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOINTLR3_FIFOILV7_Pos (16UL) /*!< FIFOILV7 (Bit 16) */ + #define R_ADC_B0_ADFIFOINTLR3_FIFOILV7_Msk (0xf0000UL) /*!< FIFOILV7 (Bitfield-Mask: 0x0f) */ +/* ===================================================== ADFIFOINTLR4 ====================================================== */ + #define R_ADC_B0_ADFIFOINTLR4_FIFOILV8_Pos (0UL) /*!< FIFOILV8 (Bit 0) */ + #define R_ADC_B0_ADFIFOINTLR4_FIFOILV8_Msk (0xfUL) /*!< FIFOILV8 (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR0 ======================================================== */ + #define R_ADC_B0_ADCHCR0_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR0_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR0_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR0_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR0_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR0_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR0_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR0_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR1 ======================================================== */ + #define R_ADC_B0_ADCHCR1_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR1_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR1_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR1_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR1_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR1_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR1_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR1_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR2 ======================================================== */ + #define R_ADC_B0_ADCHCR2_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR2_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR2_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR2_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR2_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR2_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR2_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR2_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR3 ======================================================== */ + #define R_ADC_B0_ADCHCR3_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR3_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR3_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR3_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR3_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR3_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR3_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR3_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR4 ======================================================== */ + #define R_ADC_B0_ADCHCR4_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR4_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR4_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR4_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR4_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR4_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR4_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR4_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR5 ======================================================== */ + #define R_ADC_B0_ADCHCR5_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR5_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR5_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR5_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR5_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR5_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR5_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR5_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR6 ======================================================== */ + #define R_ADC_B0_ADCHCR6_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR6_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR6_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR6_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR6_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR6_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR6_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR6_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR7 ======================================================== */ + #define R_ADC_B0_ADCHCR7_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR7_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR7_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR7_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR7_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR7_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR7_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR7_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR8 ======================================================== */ + #define R_ADC_B0_ADCHCR8_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR8_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR8_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR8_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR8_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR8_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR8_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR8_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR9 ======================================================== */ + #define R_ADC_B0_ADCHCR9_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR9_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR9_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR9_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR9_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR9_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR9_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR9_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR10 ======================================================== */ + #define R_ADC_B0_ADCHCR10_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR10_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR10_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR10_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR10_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR10_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR10_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR10_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR11 ======================================================== */ + #define R_ADC_B0_ADCHCR11_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR11_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR11_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR11_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR11_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR11_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR11_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR11_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR12 ======================================================== */ + #define R_ADC_B0_ADCHCR12_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR12_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR12_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR12_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR12_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR12_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR12_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR12_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR13 ======================================================== */ + #define R_ADC_B0_ADCHCR13_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR13_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR13_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR13_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR13_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR13_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR13_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR13_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR14 ======================================================== */ + #define R_ADC_B0_ADCHCR14_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR14_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR14_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR14_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR14_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR14_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR14_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR14_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR15 ======================================================== */ + #define R_ADC_B0_ADCHCR15_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR15_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR15_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR15_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR15_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR15_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR15_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR15_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR16 ======================================================== */ + #define R_ADC_B0_ADCHCR16_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR16_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR16_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR16_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR16_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR16_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR16_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR16_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR17 ======================================================== */ + #define R_ADC_B0_ADCHCR17_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR17_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR17_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR17_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR17_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR17_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR17_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR17_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR18 ======================================================== */ + #define R_ADC_B0_ADCHCR18_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR18_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR18_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR18_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR18_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR18_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR18_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR18_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR19 ======================================================== */ + #define R_ADC_B0_ADCHCR19_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR19_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR19_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR19_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR19_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR19_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR19_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR19_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR20 ======================================================== */ + #define R_ADC_B0_ADCHCR20_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR20_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR20_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR20_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR20_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR20_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR20_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR20_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR21 ======================================================== */ + #define R_ADC_B0_ADCHCR21_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR21_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR21_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR21_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR21_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR21_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR21_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR21_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR22 ======================================================== */ + #define R_ADC_B0_ADCHCR22_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR22_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR22_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR22_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR22_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR22_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR22_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR22_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR23 ======================================================== */ + #define R_ADC_B0_ADCHCR23_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR23_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR23_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR23_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR23_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR23_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR23_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR23_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR24 ======================================================== */ + #define R_ADC_B0_ADCHCR24_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR24_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR24_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR24_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR24_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR24_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR24_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR24_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR25 ======================================================== */ + #define R_ADC_B0_ADCHCR25_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR25_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR25_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR25_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR25_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR25_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR25_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR25_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR26 ======================================================== */ + #define R_ADC_B0_ADCHCR26_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR26_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR26_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR26_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR26_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR26_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR26_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR26_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR27 ======================================================== */ + #define R_ADC_B0_ADCHCR27_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR27_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR27_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR27_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR27_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR27_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR27_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR27_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR28 ======================================================== */ + #define R_ADC_B0_ADCHCR28_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR28_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR28_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR28_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR28_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR28_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR28_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR28_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR29 ======================================================== */ + #define R_ADC_B0_ADCHCR29_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR29_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR29_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR29_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR29_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR29_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR29_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR29_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR30 ======================================================== */ + #define R_ADC_B0_ADCHCR30_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR30_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR30_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR30_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR30_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR30_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR30_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR30_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR31 ======================================================== */ + #define R_ADC_B0_ADCHCR31_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR31_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR31_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR31_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR31_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR31_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR31_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR31_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR32 ======================================================== */ + #define R_ADC_B0_ADCHCR32_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR32_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR32_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR32_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR32_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR32_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR32_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR32_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA0 ======================================================= */ + #define R_ADC_B0_ADDOPCRA0_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA0_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA0_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA0_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA0_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA0_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA1 ======================================================= */ + #define R_ADC_B0_ADDOPCRA1_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA1_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA1_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA1_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA1_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA1_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA2 ======================================================= */ + #define R_ADC_B0_ADDOPCRA2_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA2_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA2_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA2_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA2_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA2_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA3 ======================================================= */ + #define R_ADC_B0_ADDOPCRA3_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA3_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA3_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA3_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA3_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA3_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA4 ======================================================= */ + #define R_ADC_B0_ADDOPCRA4_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA4_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA4_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA4_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA4_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA4_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA5 ======================================================= */ + #define R_ADC_B0_ADDOPCRA5_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA5_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA5_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA5_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA5_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA5_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA6 ======================================================= */ + #define R_ADC_B0_ADDOPCRA6_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA6_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA6_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA6_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA6_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA6_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA7 ======================================================= */ + #define R_ADC_B0_ADDOPCRA7_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA7_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA7_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA7_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA7_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA7_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA8 ======================================================= */ + #define R_ADC_B0_ADDOPCRA8_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA8_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA8_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA8_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA8_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA8_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA9 ======================================================= */ + #define R_ADC_B0_ADDOPCRA9_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA9_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA9_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA9_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA9_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA9_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA10 ======================================================= */ + #define R_ADC_B0_ADDOPCRA10_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA10_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA10_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA10_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA10_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA10_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA11 ======================================================= */ + #define R_ADC_B0_ADDOPCRA11_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA11_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA11_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA11_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA11_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA11_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA12 ======================================================= */ + #define R_ADC_B0_ADDOPCRA12_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA12_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA12_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA12_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA12_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA12_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA13 ======================================================= */ + #define R_ADC_B0_ADDOPCRA13_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA13_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA13_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA13_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA13_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA13_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA14 ======================================================= */ + #define R_ADC_B0_ADDOPCRA14_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA14_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA14_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA14_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA14_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA14_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA15 ======================================================= */ + #define R_ADC_B0_ADDOPCRA15_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA15_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA15_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA15_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA15_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA15_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA16 ======================================================= */ + #define R_ADC_B0_ADDOPCRA16_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA16_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA16_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA16_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA16_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA16_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA17 ======================================================= */ + #define R_ADC_B0_ADDOPCRA17_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA17_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA17_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA17_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA17_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA17_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA18 ======================================================= */ + #define R_ADC_B0_ADDOPCRA18_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA18_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA18_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA18_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA18_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA18_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA19 ======================================================= */ + #define R_ADC_B0_ADDOPCRA19_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA19_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA19_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA19_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA19_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA19_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA20 ======================================================= */ + #define R_ADC_B0_ADDOPCRA20_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA20_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA20_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA20_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA20_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA20_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA21 ======================================================= */ + #define R_ADC_B0_ADDOPCRA21_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA21_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA21_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA21_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA21_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA21_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA22 ======================================================= */ + #define R_ADC_B0_ADDOPCRA22_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA22_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA22_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA22_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA22_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA22_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA23 ======================================================= */ + #define R_ADC_B0_ADDOPCRA23_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA23_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA23_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA23_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA23_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA23_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA24 ======================================================= */ + #define R_ADC_B0_ADDOPCRA24_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA24_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA24_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA24_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA24_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA24_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA25 ======================================================= */ + #define R_ADC_B0_ADDOPCRA25_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA25_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA25_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA25_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA25_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA25_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA26 ======================================================= */ + #define R_ADC_B0_ADDOPCRA26_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA26_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA26_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA26_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA26_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA26_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA27 ======================================================= */ + #define R_ADC_B0_ADDOPCRA27_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA27_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA27_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA27_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA27_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA27_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA28 ======================================================= */ + #define R_ADC_B0_ADDOPCRA28_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA28_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA28_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA28_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA28_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA28_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA29 ======================================================= */ + #define R_ADC_B0_ADDOPCRA29_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA29_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA29_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA29_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA29_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA29_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA30 ======================================================= */ + #define R_ADC_B0_ADDOPCRA30_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA30_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA30_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA30_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA30_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA30_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA31 ======================================================= */ + #define R_ADC_B0_ADDOPCRA31_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA31_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA31_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA31_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA31_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA31_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA32 ======================================================= */ + #define R_ADC_B0_ADDOPCRA32_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA32_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA32_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA32_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA32_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA32_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRB0 ======================================================= */ + #define R_ADC_B0_ADDOPCRB0_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB0_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB0_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB0_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB0_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB0_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB1 ======================================================= */ + #define R_ADC_B0_ADDOPCRB1_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB1_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB1_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB1_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB1_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB1_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB2 ======================================================= */ + #define R_ADC_B0_ADDOPCRB2_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB2_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB2_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB2_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB2_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB2_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB3 ======================================================= */ + #define R_ADC_B0_ADDOPCRB3_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB3_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB3_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB3_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB3_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB3_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB4 ======================================================= */ + #define R_ADC_B0_ADDOPCRB4_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB4_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB4_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB4_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB4_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB4_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB5 ======================================================= */ + #define R_ADC_B0_ADDOPCRB5_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB5_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB5_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB5_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB5_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB5_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB6 ======================================================= */ + #define R_ADC_B0_ADDOPCRB6_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB6_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB6_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB6_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB6_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB6_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB7 ======================================================= */ + #define R_ADC_B0_ADDOPCRB7_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB7_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB7_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB7_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB7_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB7_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB8 ======================================================= */ + #define R_ADC_B0_ADDOPCRB8_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB8_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB8_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB8_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB8_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB8_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB9 ======================================================= */ + #define R_ADC_B0_ADDOPCRB9_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB9_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB9_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB9_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB9_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB9_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB10 ======================================================= */ + #define R_ADC_B0_ADDOPCRB10_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB10_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB10_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB10_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB10_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB10_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB11 ======================================================= */ + #define R_ADC_B0_ADDOPCRB11_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB11_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB11_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB11_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB11_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB11_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB12 ======================================================= */ + #define R_ADC_B0_ADDOPCRB12_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB12_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB12_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB12_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB12_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB12_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB13 ======================================================= */ + #define R_ADC_B0_ADDOPCRB13_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB13_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB13_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB13_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB13_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB13_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB14 ======================================================= */ + #define R_ADC_B0_ADDOPCRB14_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB14_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB14_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB14_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB14_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB14_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB15 ======================================================= */ + #define R_ADC_B0_ADDOPCRB15_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB15_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB15_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB15_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB15_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB15_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB16 ======================================================= */ + #define R_ADC_B0_ADDOPCRB16_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB16_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB16_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB16_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB16_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB16_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB17 ======================================================= */ + #define R_ADC_B0_ADDOPCRB17_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB17_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB17_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB17_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB17_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB17_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB18 ======================================================= */ + #define R_ADC_B0_ADDOPCRB18_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB18_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB18_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB18_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB18_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB18_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB19 ======================================================= */ + #define R_ADC_B0_ADDOPCRB19_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB19_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB19_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB19_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB19_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB19_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB20 ======================================================= */ + #define R_ADC_B0_ADDOPCRB20_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB20_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB20_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB20_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB20_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB20_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB21 ======================================================= */ + #define R_ADC_B0_ADDOPCRB21_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB21_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB21_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB21_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB21_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB21_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB22 ======================================================= */ + #define R_ADC_B0_ADDOPCRB22_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB22_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB22_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB22_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB22_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB22_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB23 ======================================================= */ + #define R_ADC_B0_ADDOPCRB23_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB23_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB23_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB23_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB23_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB23_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB24 ======================================================= */ + #define R_ADC_B0_ADDOPCRB24_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB24_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB24_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB24_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB24_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB24_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB25 ======================================================= */ + #define R_ADC_B0_ADDOPCRB25_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB25_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB25_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB25_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB25_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB25_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB26 ======================================================= */ + #define R_ADC_B0_ADDOPCRB26_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB26_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB26_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB26_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB26_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB26_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB27 ======================================================= */ + #define R_ADC_B0_ADDOPCRB27_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB27_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB27_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB27_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB27_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB27_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB28 ======================================================= */ + #define R_ADC_B0_ADDOPCRB28_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB28_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB28_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB28_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB28_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB28_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB29 ======================================================= */ + #define R_ADC_B0_ADDOPCRB29_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB29_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB29_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB29_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB29_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB29_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB30 ======================================================= */ + #define R_ADC_B0_ADDOPCRB30_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB30_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB30_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB30_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB30_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB30_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB31 ======================================================= */ + #define R_ADC_B0_ADDOPCRB31_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB31_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB31_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB31_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB31_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB31_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB32 ======================================================= */ + #define R_ADC_B0_ADDOPCRB32_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB32_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB32_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB32_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB32_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB32_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRC0 ======================================================= */ + #define R_ADC_B0_ADDOPCRC0_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC0_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC0_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC0_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC0_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC0_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC1 ======================================================= */ + #define R_ADC_B0_ADDOPCRC1_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC1_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC1_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC1_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC1_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC1_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC2 ======================================================= */ + #define R_ADC_B0_ADDOPCRC2_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC2_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC2_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC2_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC2_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC2_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC3 ======================================================= */ + #define R_ADC_B0_ADDOPCRC3_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC3_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC3_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC3_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC3_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC3_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC4 ======================================================= */ + #define R_ADC_B0_ADDOPCRC4_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC4_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC4_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC4_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC4_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC4_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC5 ======================================================= */ + #define R_ADC_B0_ADDOPCRC5_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC5_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC5_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC5_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC5_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC5_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC6 ======================================================= */ + #define R_ADC_B0_ADDOPCRC6_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC6_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC6_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC6_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC6_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC6_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC7 ======================================================= */ + #define R_ADC_B0_ADDOPCRC7_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC7_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC7_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC7_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC7_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC7_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC8 ======================================================= */ + #define R_ADC_B0_ADDOPCRC8_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC8_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC8_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC8_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC8_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC8_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC9 ======================================================= */ + #define R_ADC_B0_ADDOPCRC9_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC9_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC9_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC9_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC9_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC9_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC10 ======================================================= */ + #define R_ADC_B0_ADDOPCRC10_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC10_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC10_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC10_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC10_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC10_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC11 ======================================================= */ + #define R_ADC_B0_ADDOPCRC11_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC11_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC11_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC11_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC11_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC11_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC12 ======================================================= */ + #define R_ADC_B0_ADDOPCRC12_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC12_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC12_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC12_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC12_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC12_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC13 ======================================================= */ + #define R_ADC_B0_ADDOPCRC13_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC13_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC13_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC13_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC13_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC13_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC14 ======================================================= */ + #define R_ADC_B0_ADDOPCRC14_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC14_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC14_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC14_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC14_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC14_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC15 ======================================================= */ + #define R_ADC_B0_ADDOPCRC15_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC15_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC15_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC15_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC15_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC15_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC16 ======================================================= */ + #define R_ADC_B0_ADDOPCRC16_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC16_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC16_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC16_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC16_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC16_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC17 ======================================================= */ + #define R_ADC_B0_ADDOPCRC17_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC17_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC17_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC17_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC17_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC17_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC18 ======================================================= */ + #define R_ADC_B0_ADDOPCRC18_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC18_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC18_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC18_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC18_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC18_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC19 ======================================================= */ + #define R_ADC_B0_ADDOPCRC19_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC19_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC19_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC19_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC19_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC19_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC20 ======================================================= */ + #define R_ADC_B0_ADDOPCRC20_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC20_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC20_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC20_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC20_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC20_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC21 ======================================================= */ + #define R_ADC_B0_ADDOPCRC21_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC21_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC21_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC21_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC21_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC21_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC22 ======================================================= */ + #define R_ADC_B0_ADDOPCRC22_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC22_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC22_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC22_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC22_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC22_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC23 ======================================================= */ + #define R_ADC_B0_ADDOPCRC23_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC23_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC23_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC23_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC23_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC23_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC24 ======================================================= */ + #define R_ADC_B0_ADDOPCRC24_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC24_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC24_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC24_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC24_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC24_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC25 ======================================================= */ + #define R_ADC_B0_ADDOPCRC25_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC25_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC25_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC25_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC25_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC25_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC26 ======================================================= */ + #define R_ADC_B0_ADDOPCRC26_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC26_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC26_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC26_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC26_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC26_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC27 ======================================================= */ + #define R_ADC_B0_ADDOPCRC27_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC27_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC27_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC27_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC27_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC27_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC28 ======================================================= */ + #define R_ADC_B0_ADDOPCRC28_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC28_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC28_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC28_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC28_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC28_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC29 ======================================================= */ + #define R_ADC_B0_ADDOPCRC29_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC29_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC29_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC29_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC29_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC29_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC30 ======================================================= */ + #define R_ADC_B0_ADDOPCRC30_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC30_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC30_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC30_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC30_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC30_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC31 ======================================================= */ + #define R_ADC_B0_ADDOPCRC31_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC31_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC31_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC31_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC31_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC31_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC32 ======================================================= */ + #define R_ADC_B0_ADDOPCRC32_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC32_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC32_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC32_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC32_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC32_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCALSTR ======================================================== */ + #define R_ADC_B0_ADCALSTR_ADCALST0_Pos (0UL) /*!< ADCALST0 (Bit 0) */ + #define R_ADC_B0_ADCALSTR_ADCALST0_Msk (0x7UL) /*!< ADCALST0 (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADCALSTR_ADCALST1_Pos (8UL) /*!< ADCALST1 (Bit 8) */ + #define R_ADC_B0_ADCALSTR_ADCALST1_Msk (0x700UL) /*!< ADCALST1 (Bitfield-Mask: 0x07) */ +/* ======================================================= ADTRGENR ======================================================== */ + #define R_ADC_B0_ADTRGENR_STTRGENn_Pos (0UL) /*!< STTRGENn (Bit 0) */ + #define R_ADC_B0_ADTRGENR_STTRGENn_Msk (0x1ffUL) /*!< STTRGENn (Bitfield-Mask: 0x1ff) */ +/* ======================================================== ADSYSTR ======================================================== */ + #define R_ADC_B0_ADSYSTR_ADSYSTn_Pos (0UL) /*!< ADSYSTn (Bit 0) */ + #define R_ADC_B0_ADSYSTR_ADSYSTn_Msk (0x1ffUL) /*!< ADSYSTn (Bitfield-Mask: 0x1ff) */ +/* ========================================================= ADSTR ========================================================= */ + #define R_ADC_B0_ADSTR_ADST_Pos (0UL) /*!< ADST (Bit 0) */ + #define R_ADC_B0_ADSTR_ADST_Msk (0x1UL) /*!< ADST (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTOPR ======================================================== */ + #define R_ADC_B0_ADSTOPR_ADSTOP0_Pos (0UL) /*!< ADSTOP0 (Bit 0) */ + #define R_ADC_B0_ADSTOPR_ADSTOP0_Msk (0x1UL) /*!< ADSTOP0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSTOPR_ADSTOP1_Pos (8UL) /*!< ADSTOP1 (Bit 8) */ + #define R_ADC_B0_ADSTOPR_ADSTOP1_Msk (0x100UL) /*!< ADSTOP1 (Bitfield-Mask: 0x01) */ +/* ========================================================= ADSR ========================================================== */ + #define R_ADC_B0_ADSR_ADACT0_Pos (0UL) /*!< ADACT0 (Bit 0) */ + #define R_ADC_B0_ADSR_ADACT0_Msk (0x1UL) /*!< ADACT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSR_ADACT1_Pos (1UL) /*!< ADACT1 (Bit 1) */ + #define R_ADC_B0_ADSR_ADACT1_Msk (0x2UL) /*!< ADACT1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSR_CALACT0_Pos (16UL) /*!< CALACT0 (Bit 16) */ + #define R_ADC_B0_ADSR_CALACT0_Msk (0x10000UL) /*!< CALACT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSR_CALACT1_Pos (17UL) /*!< CALACT1 (Bit 17) */ + #define R_ADC_B0_ADSR_CALACT1_Msk (0x20000UL) /*!< CALACT1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGRSR ========================================================= */ + #define R_ADC_B0_ADGRSR_ACTGRn_Pos (0UL) /*!< ACTGRn (Bit 0) */ + #define R_ADC_B0_ADGRSR_ACTGRn_Msk (0x1ffUL) /*!< ACTGRn (Bitfield-Mask: 0x1ff) */ +/* ======================================================== ADERSR ========================================================= */ + #define R_ADC_B0_ADERSR_ADERF0_Pos (0UL) /*!< ADERF0 (Bit 0) */ + #define R_ADC_B0_ADERSR_ADERF0_Msk (0x1UL) /*!< ADERF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADERSR_ADERF1_Pos (1UL) /*!< ADERF1 (Bit 1) */ + #define R_ADC_B0_ADERSR_ADERF1_Msk (0x2UL) /*!< ADERF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ADERSCR ======================================================== */ + #define R_ADC_B0_ADERSCR_ADERCLR0_Pos (0UL) /*!< ADERCLR0 (Bit 0) */ + #define R_ADC_B0_ADERSCR_ADERCLR0_Msk (0x1UL) /*!< ADERCLR0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADERSCR_ADERCLR1_Pos (1UL) /*!< ADERCLR1 (Bit 1) */ + #define R_ADC_B0_ADERSCR_ADERCLR1_Msk (0x2UL) /*!< ADERCLR1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCALENDSR ======================================================= */ + #define R_ADC_B0_ADCALENDSR_CALENDF0_Pos (0UL) /*!< CALENDF0 (Bit 0) */ + #define R_ADC_B0_ADCALENDSR_CALENDF0_Msk (0x1UL) /*!< CALENDF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCALENDSR_CALENDF1_Pos (1UL) /*!< CALENDF1 (Bit 1) */ + #define R_ADC_B0_ADCALENDSR_CALENDF1_Msk (0x2UL) /*!< CALENDF1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCALENDSCR ====================================================== */ + #define R_ADC_B0_ADCALENDSCR_CALENDC0_Pos (0UL) /*!< CALENDC0 (Bit 0) */ + #define R_ADC_B0_ADCALENDSCR_CALENDC0_Msk (0x1UL) /*!< CALENDC0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCALENDSCR_CALENDC1_Pos (1UL) /*!< CALENDC1 (Bit 1) */ + #define R_ADC_B0_ADCALENDSCR_CALENDC1_Msk (0x2UL) /*!< CALENDC1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADOVFERSR ======================================================= */ + #define R_ADC_B0_ADOVFERSR_ADOVFEF0_Pos (0UL) /*!< ADOVFEF0 (Bit 0) */ + #define R_ADC_B0_ADOVFERSR_ADOVFEF0_Msk (0x1UL) /*!< ADOVFEF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFERSR_ADOVFEF1_Pos (1UL) /*!< ADOVFEF1 (Bit 1) */ + #define R_ADC_B0_ADOVFERSR_ADOVFEF1_Msk (0x2UL) /*!< ADOVFEF1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADOVFCHSR0 ======================================================= */ + #define R_ADC_B0_ADOVFCHSR0_OVFCHFn_Pos (0UL) /*!< OVFCHFn (Bit 0) */ + #define R_ADC_B0_ADOVFCHSR0_OVFCHFn_Msk (0x7fffffUL) /*!< OVFCHFn (Bitfield-Mask: 0x7fffff) */ +/* ======================================================= ADOVFEXSR ======================================================= */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF0_Pos (0UL) /*!< OVFEXF0 (Bit 0) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF0_Msk (0x1UL) /*!< OVFEXF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF1_Pos (1UL) /*!< OVFEXF1 (Bit 1) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF1_Msk (0x2UL) /*!< OVFEXF1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF4_Pos (4UL) /*!< OVFEXF4 (Bit 4) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF4_Msk (0x10UL) /*!< OVFEXF4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF5_Pos (5UL) /*!< OVFEXF5 (Bit 5) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF5_Msk (0x20UL) /*!< OVFEXF5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF6_Pos (6UL) /*!< OVFEXF6 (Bit 6) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF6_Msk (0x40UL) /*!< OVFEXF6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF8_Pos (8UL) /*!< OVFEXF8 (Bit 8) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF8_Msk (0x100UL) /*!< OVFEXF8 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF9_Pos (9UL) /*!< OVFEXF9 (Bit 9) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF9_Msk (0x200UL) /*!< OVFEXF9 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF16_Pos (16UL) /*!< OVFEXF16 (Bit 16) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF16_Msk (0x10000UL) /*!< OVFEXF16 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF17_Pos (17UL) /*!< OVFEXF17 (Bit 17) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF17_Msk (0x20000UL) /*!< OVFEXF17 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF18_Pos (18UL) /*!< OVFEXF18 (Bit 18) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF18_Msk (0x40000UL) /*!< OVFEXF18 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF20_Pos (20UL) /*!< OVFEXF20 (Bit 20) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF20_Msk (0x100000UL) /*!< OVFEXF20 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF21_Pos (21UL) /*!< OVFEXF21 (Bit 21) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF21_Msk (0x200000UL) /*!< OVFEXF21 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF22_Pos (22UL) /*!< OVFEXF22 (Bit 22) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF22_Msk (0x400000UL) /*!< OVFEXF22 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADOVFERSCR ======================================================= */ + #define R_ADC_B0_ADOVFERSCR_ADOVFEC0_Pos (0UL) /*!< ADOVFEC0 (Bit 0) */ + #define R_ADC_B0_ADOVFERSCR_ADOVFEC0_Msk (0x1UL) /*!< ADOVFEC0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFERSCR_ADOVFEC1_Pos (1UL) /*!< ADOVFEC1 (Bit 1) */ + #define R_ADC_B0_ADOVFERSCR_ADOVFEC1_Msk (0x2UL) /*!< ADOVFEC1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADOVFCHSCR0 ====================================================== */ + #define R_ADC_B0_ADOVFCHSCR0_OVFCHCn_Pos (0UL) /*!< OVFCHCn (Bit 0) */ + #define R_ADC_B0_ADOVFCHSCR0_OVFCHCn_Msk (0x7fffffUL) /*!< OVFCHCn (Bitfield-Mask: 0x7fffff) */ +/* ====================================================== ADOVFEXSCR ======================================================= */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC0_Pos (0UL) /*!< OVFEXC0 (Bit 0) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC0_Msk (0x1UL) /*!< OVFEXC0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC1_Pos (1UL) /*!< OVFEXC1 (Bit 1) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC1_Msk (0x2UL) /*!< OVFEXC1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC4_Pos (4UL) /*!< OVFEXC4 (Bit 4) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC4_Msk (0x10UL) /*!< OVFEXC4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC5_Pos (5UL) /*!< OVFEXC5 (Bit 5) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC5_Msk (0x20UL) /*!< OVFEXC5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC6_Pos (6UL) /*!< OVFEXC6 (Bit 6) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC6_Msk (0x40UL) /*!< OVFEXC6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC8_Pos (8UL) /*!< OVFEXC8 (Bit 8) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC8_Msk (0x100UL) /*!< OVFEXC8 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC9_Pos (9UL) /*!< OVFEXC9 (Bit 9) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC9_Msk (0x200UL) /*!< OVFEXC9 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC16_Pos (16UL) /*!< OVFEXC16 (Bit 16) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC16_Msk (0x10000UL) /*!< OVFEXC16 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC17_Pos (17UL) /*!< OVFEXC17 (Bit 17) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC17_Msk (0x20000UL) /*!< OVFEXC17 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC18_Pos (18UL) /*!< OVFEXC18 (Bit 18) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC18_Msk (0x40000UL) /*!< OVFEXC18 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC20_Pos (20UL) /*!< OVFEXC20 (Bit 20) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC20_Msk (0x100000UL) /*!< OVFEXC20 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC21_Pos (21UL) /*!< OVFEXC21 (Bit 21) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC21_Msk (0x200000UL) /*!< OVFEXC21 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC22_Pos (22UL) /*!< OVFEXC22 (Bit 22) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC22_Msk (0x400000UL) /*!< OVFEXC22 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFOSR0 ======================================================= */ + #define R_ADC_B0_ADFIFOSR0_FIFOST0_Pos (0UL) /*!< FIFOST0 (Bit 0) */ + #define R_ADC_B0_ADFIFOSR0_FIFOST0_Msk (0xfUL) /*!< FIFOST0 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOSR0_FIFOST1_Pos (16UL) /*!< FIFOST1 (Bit 16) */ + #define R_ADC_B0_ADFIFOSR0_FIFOST1_Msk (0xf0000UL) /*!< FIFOST1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADFIFOSR1 ======================================================= */ + #define R_ADC_B0_ADFIFOSR1_FIFOST2_Pos (0UL) /*!< FIFOST2 (Bit 0) */ + #define R_ADC_B0_ADFIFOSR1_FIFOST2_Msk (0xfUL) /*!< FIFOST2 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOSR1_FIFOST3_Pos (16UL) /*!< FIFOST3 (Bit 16) */ + #define R_ADC_B0_ADFIFOSR1_FIFOST3_Msk (0xf0000UL) /*!< FIFOST3 (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADFIFOSR2 ======================================================= */ + #define R_ADC_B0_ADFIFOSR2_FIFOST4_Pos (0UL) /*!< FIFOST4 (Bit 0) */ + #define R_ADC_B0_ADFIFOSR2_FIFOST4_Msk (0xfUL) /*!< FIFOST4 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOSR2_FIFOST5_Pos (16UL) /*!< FIFOST5 (Bit 16) */ + #define R_ADC_B0_ADFIFOSR2_FIFOST5_Msk (0xf0000UL) /*!< FIFOST5 (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADFIFOSR3 ======================================================= */ + #define R_ADC_B0_ADFIFOSR3_FIFOST6_Pos (0UL) /*!< FIFOST6 (Bit 0) */ + #define R_ADC_B0_ADFIFOSR3_FIFOST6_Msk (0xfUL) /*!< FIFOST6 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOSR3_FIFOST7_Pos (16UL) /*!< FIFOST7 (Bit 16) */ + #define R_ADC_B0_ADFIFOSR3_FIFOST7_Msk (0xf0000UL) /*!< FIFOST7 (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADFIFOSR4 ======================================================= */ + #define R_ADC_B0_ADFIFOSR4_FIFOST8_Pos (0UL) /*!< FIFOST8 (Bit 0) */ + #define R_ADC_B0_ADFIFOSR4_FIFOST8_Msk (0xfUL) /*!< FIFOST8 (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADFIFODCR ======================================================= */ + #define R_ADC_B0_ADFIFODCR_FIFODCn_Pos (0UL) /*!< FIFODCn (Bit 0) */ + #define R_ADC_B0_ADFIFODCR_FIFODCn_Msk (0x1ffUL) /*!< FIFODCn (Bitfield-Mask: 0x1ff) */ +/* ====================================================== ADFIFOERSR ======================================================= */ + #define R_ADC_B0_ADFIFOERSR_FIFOOVFn_Pos (0UL) /*!< FIFOOVFn (Bit 0) */ + #define R_ADC_B0_ADFIFOERSR_FIFOOVFn_Msk (0x1ffUL) /*!< FIFOOVFn (Bitfield-Mask: 0x1ff) */ + #define R_ADC_B0_ADFIFOERSR_FIFOFLFn_Pos (16UL) /*!< FIFOFLFn (Bit 16) */ + #define R_ADC_B0_ADFIFOERSR_FIFOFLFn_Msk (0x1ff0000UL) /*!< FIFOFLFn (Bitfield-Mask: 0x1ff) */ +/* ====================================================== ADFIFOERSCR ====================================================== */ + #define R_ADC_B0_ADFIFOERSCR_FIFOOVFCn_Pos (0UL) /*!< FIFOOVFCn (Bit 0) */ + #define R_ADC_B0_ADFIFOERSCR_FIFOOVFCn_Msk (0x1ffUL) /*!< FIFOOVFCn (Bitfield-Mask: 0x1ff) */ + #define R_ADC_B0_ADFIFOERSCR_FIFOFLCn_Pos (16UL) /*!< FIFOFLCn (Bit 16) */ + #define R_ADC_B0_ADFIFOERSCR_FIFOFLCn_Msk (0x1ff0000UL) /*!< FIFOFLCn (Bitfield-Mask: 0x1ff) */ +/* ======================================================= ADCMPTBSR ======================================================= */ + #define R_ADC_B0_ADCMPTBSR_CMPTBFn_Pos (0UL) /*!< CMPTBFn (Bit 0) */ + #define R_ADC_B0_ADCMPTBSR_CMPTBFn_Msk (0xffUL) /*!< CMPTBFn (Bitfield-Mask: 0xff) */ +/* ====================================================== ADCMPTBSCR ======================================================= */ + #define R_ADC_B0_ADCMPTBSCR_CMPTBCn_Pos (0UL) /*!< CMPTBCn (Bit 0) */ + #define R_ADC_B0_ADCMPTBSCR_CMPTBCn_Msk (0xffUL) /*!< CMPTBCn (Bitfield-Mask: 0xff) */ +/* ====================================================== ADCMPCHSR0 ======================================================= */ + #define R_ADC_B0_ADCMPCHSR0_CMPCHFn_Pos (0UL) /*!< CMPCHFn (Bit 0) */ + #define R_ADC_B0_ADCMPCHSR0_CMPCHFn_Msk (0x7fffffUL) /*!< CMPCHFn (Bitfield-Mask: 0x7fffff) */ +/* ======================================================= ADCMPEXSR ======================================================= */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF0_Pos (0UL) /*!< CMPEXF0 (Bit 0) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF0_Msk (0x1UL) /*!< CMPEXF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF1_Pos (1UL) /*!< CMPEXF1 (Bit 1) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF1_Msk (0x2UL) /*!< CMPEXF1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF4_Pos (4UL) /*!< CMPEXF4 (Bit 4) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF4_Msk (0x10UL) /*!< CMPEXF4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF5_Pos (5UL) /*!< CMPEXF5 (Bit 5) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF5_Msk (0x20UL) /*!< CMPEXF5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF6_Pos (6UL) /*!< CMPEXF6 (Bit 6) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF6_Msk (0x40UL) /*!< CMPEXF6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF8_Pos (8UL) /*!< CMPEXF8 (Bit 8) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF8_Msk (0x100UL) /*!< CMPEXF8 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF9_Pos (9UL) /*!< CMPEXF9 (Bit 9) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF9_Msk (0x200UL) /*!< CMPEXF9 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF16_Pos (16UL) /*!< CMPEXF16 (Bit 16) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF16_Msk (0x10000UL) /*!< CMPEXF16 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF17_Pos (17UL) /*!< CMPEXF17 (Bit 17) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF17_Msk (0x20000UL) /*!< CMPEXF17 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF18_Pos (18UL) /*!< CMPEXF18 (Bit 18) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF18_Msk (0x40000UL) /*!< CMPEXF18 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF20_Pos (20UL) /*!< CMPEXF20 (Bit 20) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF20_Msk (0x100000UL) /*!< CMPEXF20 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF21_Pos (21UL) /*!< CMPEXF21 (Bit 21) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF21_Msk (0x200000UL) /*!< CMPEXF21 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF22_Pos (22UL) /*!< CMPEXF22 (Bit 22) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF22_Msk (0x400000UL) /*!< CMPEXF22 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCMPCHSCR0 ====================================================== */ + #define R_ADC_B0_ADCMPCHSCR0_CMPCHCn_Pos (0UL) /*!< CMPCHCn (Bit 0) */ + #define R_ADC_B0_ADCMPCHSCR0_CMPCHCn_Msk (0x7fffffUL) /*!< CMPCHCn (Bitfield-Mask: 0x7fffff) */ +/* ====================================================== ADCMPEXSCR ======================================================= */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC0_Pos (0UL) /*!< CMPEXC0 (Bit 0) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC0_Msk (0x1UL) /*!< CMPEXC0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC1_Pos (1UL) /*!< CMPEXC1 (Bit 1) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC1_Msk (0x2UL) /*!< CMPEXC1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC4_Pos (4UL) /*!< CMPEXC4 (Bit 4) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC4_Msk (0x10UL) /*!< CMPEXC4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC5_Pos (5UL) /*!< CMPEXC5 (Bit 5) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC5_Msk (0x20UL) /*!< CMPEXC5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC6_Pos (6UL) /*!< CMPEXC6 (Bit 6) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC6_Msk (0x40UL) /*!< CMPEXC6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC8_Pos (8UL) /*!< CMPEXC8 (Bit 8) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC8_Msk (0x100UL) /*!< CMPEXC8 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC9_Pos (9UL) /*!< CMPEXC9 (Bit 9) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC9_Msk (0x200UL) /*!< CMPEXC9 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC16_Pos (16UL) /*!< CMPEXC16 (Bit 16) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC16_Msk (0x10000UL) /*!< CMPEXC16 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC17_Pos (17UL) /*!< CMPEXC17 (Bit 17) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC17_Msk (0x20000UL) /*!< CMPEXC17 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC18_Pos (18UL) /*!< CMPEXC18 (Bit 18) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC18_Msk (0x40000UL) /*!< CMPEXC18 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC20_Pos (20UL) /*!< CMPEXC20 (Bit 20) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC20_Msk (0x100000UL) /*!< CMPEXC20 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC21_Pos (21UL) /*!< CMPEXC21 (Bit 21) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC21_Msk (0x200000UL) /*!< CMPEXC21 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC22_Pos (22UL) /*!< CMPEXC22 (Bit 22) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC22_Msk (0x400000UL) /*!< CMPEXC22 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADLIMGRSR ======================================================= */ + #define R_ADC_B0_ADLIMGRSR_LIMGRFn_Pos (0UL) /*!< LIMGRFn (Bit 0) */ + #define R_ADC_B0_ADLIMGRSR_LIMGRFn_Msk (0x1ffUL) /*!< LIMGRFn (Bitfield-Mask: 0x1ff) */ +/* ====================================================== ADLIMCHSR0 ======================================================= */ + #define R_ADC_B0_ADLIMCHSR0_LIMCHFn_Pos (0UL) /*!< LIMCHFn (Bit 0) */ + #define R_ADC_B0_ADLIMCHSR0_LIMCHFn_Msk (0x7fffffUL) /*!< LIMCHFn (Bitfield-Mask: 0x7fffff) */ +/* ======================================================= ADLIMEXSR ======================================================= */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF0_Pos (0UL) /*!< LIMEXF0 (Bit 0) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF0_Msk (0x1UL) /*!< LIMEXF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF1_Pos (1UL) /*!< LIMEXF1 (Bit 1) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF1_Msk (0x2UL) /*!< LIMEXF1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF4_Pos (4UL) /*!< LIMEXF4 (Bit 4) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF4_Msk (0x10UL) /*!< LIMEXF4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF5_Pos (5UL) /*!< LIMEXF5 (Bit 5) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF5_Msk (0x20UL) /*!< LIMEXF5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF6_Pos (6UL) /*!< LIMEXF6 (Bit 6) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF6_Msk (0x40UL) /*!< LIMEXF6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF8_Pos (8UL) /*!< LIMEXF8 (Bit 8) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF8_Msk (0x100UL) /*!< LIMEXF8 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF9_Pos (9UL) /*!< LIMEXF9 (Bit 9) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF9_Msk (0x200UL) /*!< LIMEXF9 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF16_Pos (16UL) /*!< LIMEXF16 (Bit 16) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF16_Msk (0x10000UL) /*!< LIMEXF16 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF17_Pos (17UL) /*!< LIMEXF17 (Bit 17) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF17_Msk (0x20000UL) /*!< LIMEXF17 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF18_Pos (18UL) /*!< LIMEXF18 (Bit 18) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF18_Msk (0x40000UL) /*!< LIMEXF18 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF20_Pos (20UL) /*!< LIMEXF20 (Bit 20) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF20_Msk (0x100000UL) /*!< LIMEXF20 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF21_Pos (21UL) /*!< LIMEXF21 (Bit 21) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF21_Msk (0x200000UL) /*!< LIMEXF21 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF22_Pos (22UL) /*!< LIMEXF22 (Bit 22) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF22_Msk (0x400000UL) /*!< LIMEXF22 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADLIMGRSCR ======================================================= */ + #define R_ADC_B0_ADLIMGRSCR_LIMGRCn_Pos (0UL) /*!< LIMGRCn (Bit 0) */ + #define R_ADC_B0_ADLIMGRSCR_LIMGRCn_Msk (0x1ffUL) /*!< LIMGRCn (Bitfield-Mask: 0x1ff) */ +/* ====================================================== ADLIMCHSCR0 ====================================================== */ + #define R_ADC_B0_ADLIMCHSCR0_LIMCHCn_Pos (0UL) /*!< LIMCHCn (Bit 0) */ + #define R_ADC_B0_ADLIMCHSCR0_LIMCHCn_Msk (0x7fffffUL) /*!< LIMCHCn (Bitfield-Mask: 0x7fffff) */ +/* ====================================================== ADLIMEXSCR ======================================================= */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF0_Pos (0UL) /*!< LIMEXF0 (Bit 0) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF0_Msk (0x1UL) /*!< LIMEXF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF1_Pos (1UL) /*!< LIMEXF1 (Bit 1) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF1_Msk (0x2UL) /*!< LIMEXF1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF4_Pos (4UL) /*!< LIMEXF4 (Bit 4) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF4_Msk (0x10UL) /*!< LIMEXF4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF5_Pos (5UL) /*!< LIMEXF5 (Bit 5) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF5_Msk (0x20UL) /*!< LIMEXF5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF6_Pos (6UL) /*!< LIMEXF6 (Bit 6) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF6_Msk (0x40UL) /*!< LIMEXF6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF8_Pos (8UL) /*!< LIMEXF8 (Bit 8) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF8_Msk (0x100UL) /*!< LIMEXF8 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF9_Pos (9UL) /*!< LIMEXF9 (Bit 9) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF9_Msk (0x200UL) /*!< LIMEXF9 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF16_Pos (16UL) /*!< LIMEXF16 (Bit 16) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF16_Msk (0x10000UL) /*!< LIMEXF16 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF17_Pos (17UL) /*!< LIMEXF17 (Bit 17) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF17_Msk (0x20000UL) /*!< LIMEXF17 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF18_Pos (18UL) /*!< LIMEXF18 (Bit 18) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF18_Msk (0x40000UL) /*!< LIMEXF18 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF20_Pos (20UL) /*!< LIMEXF20 (Bit 20) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF20_Msk (0x100000UL) /*!< LIMEXF20 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF21_Pos (21UL) /*!< LIMEXF21 (Bit 21) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF21_Msk (0x200000UL) /*!< LIMEXF21 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF22_Pos (22UL) /*!< LIMEXF22 (Bit 22) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF22_Msk (0x400000UL) /*!< LIMEXF22 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADSCANENDSR ====================================================== */ + #define R_ADC_B0_ADSCANENDSR_SCENDFn_Pos (0UL) /*!< SCENDFn (Bit 0) */ + #define R_ADC_B0_ADSCANENDSR_SCENDFn_Msk (0x1ffUL) /*!< SCENDFn (Bitfield-Mask: 0x1ff) */ +/* ===================================================== ADSCANENDSCR ====================================================== */ + #define R_ADC_B0_ADSCANENDSCR_SCENDCn_Pos (0UL) /*!< SCENDCn (Bit 0) */ + #define R_ADC_B0_ADSCANENDSCR_SCENDCn_Msk (0x1ffUL) /*!< SCENDCn (Bitfield-Mask: 0x1ff) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC_B0_ADDR_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADDR_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADDR_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADDR_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADEXDR ========================================================= */ + #define R_ADC_B0_ADEXDR_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADEXDR_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADEXDR_DIAGSR_Pos (24UL) /*!< DIAGSR (Bit 24) */ + #define R_ADC_B0_ADEXDR_DIAGSR_Msk (0x7000000UL) /*!< DIAGSR (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADEXDR_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADEXDR_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR0 ======================================================= */ + #define R_ADC_B0_ADFIFODR0_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR0_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR0_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR0_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR0_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR0_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR1 ======================================================= */ + #define R_ADC_B0_ADFIFODR1_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR1_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR1_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR1_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR1_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR1_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR2 ======================================================= */ + #define R_ADC_B0_ADFIFODR2_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR2_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR2_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR2_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR2_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR2_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR3 ======================================================= */ + #define R_ADC_B0_ADFIFODR3_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR3_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR3_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR3_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR3_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR3_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR4 ======================================================= */ + #define R_ADC_B0_ADFIFODR4_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR4_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR4_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR4_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR4_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR4_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR5 ======================================================= */ + #define R_ADC_B0_ADFIFODR5_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR5_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR5_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR5_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR5_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR5_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR6 ======================================================= */ + #define R_ADC_B0_ADFIFODR6_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR6_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR6_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR6_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR6_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR6_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR7 ======================================================= */ + #define R_ADC_B0_ADFIFODR7_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR7_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR7_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR7_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR7_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR7_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR8 ======================================================= */ + #define R_ADC_B0_ADFIFODR8_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR8_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR8_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR8_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR8_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR8_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC_B ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_B_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_B_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ + #define R_DOC_B_DOCR_DOBW_Pos (3UL) /*!< DOBW (Bit 3) */ + #define R_DOC_B_DOCR_DOBW_Msk (0x8UL) /*!< DOBW (Bitfield-Mask: 0x01) */ + #define R_DOC_B_DOCR_DCSEL_Pos (4UL) /*!< DCSEL (Bit 4) */ + #define R_DOC_B_DOCR_DCSEL_Msk (0x70UL) /*!< DCSEL (Bitfield-Mask: 0x07) */ +/* ========================================================= DOSR ========================================================== */ + #define R_DOC_B_DOSR_DOPCF_Pos (0UL) /*!< DOPCF (Bit 0) */ + #define R_DOC_B_DOSR_DOPCF_Msk (0x1UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ +/* ========================================================= DOSCR ========================================================= */ + #define R_DOC_B_DOSCR_DOPCFCL_Pos (0UL) /*!< DOPCFCL (Bit 0) */ + #define R_DOC_B_DOSCR_DOPCFCL_Msk (0x1UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ +/* ========================================================= DODIR ========================================================= */ +/* ======================================================== DODSR0 ========================================================= */ +/* ======================================================== DODSR1 ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_SCI_B0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== RDR ========================================================== */ + #define R_SCI_B0_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI_B0_RDR_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI_B0_RDR_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI_B0_RDR_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI_B0_RDR_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_FPER_Pos (11UL) /*!< FPER (Bit 11) */ + #define R_SCI_B0_RDR_FPER_Msk (0x800UL) /*!< FPER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_FFER_Pos (12UL) /*!< FFER (Bit 12) */ + #define R_SCI_B0_RDR_FFER_Msk (0x1000UL) /*!< FFER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_ORER_Pos (24UL) /*!< ORER (Bit 24) */ + #define R_SCI_B0_RDR_ORER_Msk (0x1000000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_PER_Pos (27UL) /*!< PER (Bit 27) */ + #define R_SCI_B0_RDR_PER_Msk (0x8000000UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_FER_Pos (28UL) /*!< FER (Bit 28) */ + #define R_SCI_B0_RDR_FER_Msk (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01) */ +/* ======================================================== RDR_BY ========================================================= */ + #define R_SCI_B0_RDR_BY_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI_B0_RDR_BY_RDAT_Msk (0xffUL) /*!< RDAT (Bitfield-Mask: 0xff) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI_B0_TDR_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI_B0_TDR_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI_B0_TDR_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI_B0_TDR_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_TDR_TSYNC_Pos (12UL) /*!< TSYNC (Bit 12) */ + #define R_SCI_B0_TDR_TSYNC_Msk (0x1000UL) /*!< TSYNC (Bitfield-Mask: 0x01) */ +/* ======================================================== TDR_BY ========================================================= */ + #define R_SCI_B0_TDR_BY_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI_B0_TDR_BY_TDAT_Msk (0xffUL) /*!< TDAT (Bitfield-Mask: 0xff) */ +/* ========================================================= CCR0 ========================================================== */ + #define R_SCI_B0_CCR0_RE_Pos (0UL) /*!< RE (Bit 0) */ + #define R_SCI_B0_CCR0_RE_Msk (0x1UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_TE_Pos (4UL) /*!< TE (Bit 4) */ + #define R_SCI_B0_CCR0_TE_Msk (0x10UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_MPIE_Pos (8UL) /*!< MPIE (Bit 8) */ + #define R_SCI_B0_CCR0_MPIE_Msk (0x100UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_DCME_Pos (9UL) /*!< DCME (Bit 9) */ + #define R_SCI_B0_CCR0_DCME_Msk (0x200UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_IDSEL_Pos (10UL) /*!< IDSEL (Bit 10) */ + #define R_SCI_B0_CCR0_IDSEL_Msk (0x400UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_RIE_Pos (16UL) /*!< RIE (Bit 16) */ + #define R_SCI_B0_CCR0_RIE_Msk (0x10000UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_TIE_Pos (20UL) /*!< TIE (Bit 20) */ + #define R_SCI_B0_CCR0_TIE_Msk (0x100000UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_TEIE_Pos (21UL) /*!< TEIE (Bit 21) */ + #define R_SCI_B0_CCR0_TEIE_Msk (0x200000UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_SSE_Pos (24UL) /*!< SSE (Bit 24) */ + #define R_SCI_B0_CCR0_SSE_Msk (0x1000000UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR1 ========================================================== */ + #define R_SCI_B0_CCR1_CTSE_Pos (0UL) /*!< CTSE (Bit 0) */ + #define R_SCI_B0_CCR1_CTSE_Msk (0x1UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_CTSPEN_Pos (1UL) /*!< CTSPEN (Bit 1) */ + #define R_SCI_B0_CCR1_CTSPEN_Msk (0x2UL) /*!< CTSPEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SPB2DT_Pos (4UL) /*!< SPB2DT (Bit 4) */ + #define R_SCI_B0_CCR1_SPB2DT_Msk (0x10UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SPB2IO_Pos (5UL) /*!< SPB2IO (Bit 5) */ + #define R_SCI_B0_CCR1_SPB2IO_Msk (0x20UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_PE_Pos (8UL) /*!< PE (Bit 8) */ + #define R_SCI_B0_CCR1_PE_Msk (0x100UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_PM_Pos (9UL) /*!< PM (Bit 9) */ + #define R_SCI_B0_CCR1_PM_Msk (0x200UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_TINV_Pos (12UL) /*!< TINV (Bit 12) */ + #define R_SCI_B0_CCR1_TINV_Msk (0x1000UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_RINV_Pos (13UL) /*!< RINV (Bit 13) */ + #define R_SCI_B0_CCR1_RINV_Msk (0x2000UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SPLP_Pos (16UL) /*!< SPLP (Bit 16) */ + #define R_SCI_B0_CCR1_SPLP_Msk (0x10000UL) /*!< SPLP (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SHARPS_Pos (20UL) /*!< SHARPS (Bit 20) */ + #define R_SCI_B0_CCR1_SHARPS_Msk (0x100000UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_NFCS_Pos (24UL) /*!< NFCS (Bit 24) */ + #define R_SCI_B0_CCR1_NFCS_Msk (0x7000000UL) /*!< NFCS (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR1_NFEN_Pos (28UL) /*!< NFEN (Bit 28) */ + #define R_SCI_B0_CCR1_NFEN_Msk (0x10000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR2 ========================================================== */ + #define R_SCI_B0_CCR2_BCP_Pos (0UL) /*!< BCP (Bit 0) */ + #define R_SCI_B0_CCR2_BCP_Msk (0x7UL) /*!< BCP (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR2_BGDM_Pos (4UL) /*!< BGDM (Bit 4) */ + #define R_SCI_B0_CCR2_BGDM_Msk (0x10UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_ABCS_Pos (5UL) /*!< ABCS (Bit 5) */ + #define R_SCI_B0_CCR2_ABCS_Msk (0x20UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_ABCSE_Pos (6UL) /*!< ABCSE (Bit 6) */ + #define R_SCI_B0_CCR2_ABCSE_Msk (0x40UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_BRR_Pos (8UL) /*!< BRR (Bit 8) */ + #define R_SCI_B0_CCR2_BRR_Msk (0xff00UL) /*!< BRR (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_CCR2_BRME_Pos (16UL) /*!< BRME (Bit 16) */ + #define R_SCI_B0_CCR2_BRME_Msk (0x10000UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_CKS_Pos (20UL) /*!< CKS (Bit 20) */ + #define R_SCI_B0_CCR2_CKS_Msk (0x300000UL) /*!< CKS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_CCR2_MDDR_Pos (24UL) /*!< MDDR (Bit 24) */ + #define R_SCI_B0_CCR2_MDDR_Msk (0xff000000UL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= CCR3 ========================================================== */ + #define R_SCI_B0_CCR3_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SCI_B0_CCR3_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SCI_B0_CCR3_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_BPEN_Pos (7UL) /*!< BPEN (Bit 7) */ + #define R_SCI_B0_CCR3_BPEN_Msk (0x80UL) /*!< BPEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_CHR_Pos (8UL) /*!< CHR (Bit 8) */ + #define R_SCI_B0_CCR3_CHR_Msk (0x300UL) /*!< CHR (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_CCR3_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SCI_B0_CCR3_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_SINV_Pos (13UL) /*!< SINV (Bit 13) */ + #define R_SCI_B0_CCR3_SINV_Msk (0x2000UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_STP_Pos (14UL) /*!< STP (Bit 14) */ + #define R_SCI_B0_CCR3_STP_Msk (0x4000UL) /*!< STP (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_RXDESEL_Pos (15UL) /*!< RXDESEL (Bit 15) */ + #define R_SCI_B0_CCR3_RXDESEL_Msk (0x8000UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_MOD_Pos (16UL) /*!< MOD (Bit 16) */ + #define R_SCI_B0_CCR3_MOD_Msk (0x70000UL) /*!< MOD (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR3_MP_Pos (19UL) /*!< MP (Bit 19) */ + #define R_SCI_B0_CCR3_MP_Msk (0x80000UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_FM_Pos (20UL) /*!< FM (Bit 20) */ + #define R_SCI_B0_CCR3_FM_Msk (0x100000UL) /*!< FM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_DEN_Pos (21UL) /*!< DEN (Bit 21) */ + #define R_SCI_B0_CCR3_DEN_Msk (0x200000UL) /*!< DEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_CKE_Pos (24UL) /*!< CKE (Bit 24) */ + #define R_SCI_B0_CCR3_CKE_Msk (0x3000000UL) /*!< CKE (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_CCR3_GM_Pos (28UL) /*!< GM (Bit 28) */ + #define R_SCI_B0_CCR3_GM_Msk (0x10000000UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_BLK_Pos (29UL) /*!< BLK (Bit 29) */ + #define R_SCI_B0_CCR3_BLK_Msk (0x20000000UL) /*!< BLK (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR4 ========================================================== */ + #define R_SCI_B0_CCR4_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI_B0_CCR4_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ + #define R_SCI_B0_CCR4_ASEN_Pos (16UL) /*!< ASEN (Bit 16) */ + #define R_SCI_B0_CCR4_ASEN_Msk (0x10000UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR4_ATEN_Pos (17UL) /*!< ATEN (Bit 17) */ + #define R_SCI_B0_CCR4_ATEN_Msk (0x20000UL) /*!< ATEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR4_SCKSEL_Pos (19UL) /*!< SCKSEL (Bit 19) */ + #define R_SCI_B0_CCR4_SCKSEL_Msk (0x80000UL) /*!< SCKSEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR4_AST_Pos (24UL) /*!< AST (Bit 24) */ + #define R_SCI_B0_CCR4_AST_Msk (0x7000000UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR4_AJD_Pos (27UL) /*!< AJD (Bit 27) */ + #define R_SCI_B0_CCR4_AJD_Msk (0x8000000UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR4_ATT_Pos (28UL) /*!< ATT (Bit 28) */ + #define R_SCI_B0_CCR4_ATT_Msk (0x70000000UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR4_AET_Pos (31UL) /*!< AET (Bit 31) */ + #define R_SCI_B0_CCR4_AET_Msk (0x80000000UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= CESR ========================================================== */ + #define R_SCI_B0_CESR_RIST_Pos (0UL) /*!< RIST (Bit 0) */ + #define R_SCI_B0_CESR_RIST_Msk (0x1UL) /*!< RIST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CESR_TIST_Pos (4UL) /*!< TIST (Bit 4) */ + #define R_SCI_B0_CESR_TIST_Msk (0x10UL) /*!< TIST (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI_B0_ICR_IICDL_Pos (0UL) /*!< IICDL (Bit 0) */ + #define R_SCI_B0_ICR_IICDL_Msk (0x1fUL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_ICR_IICINTM_Pos (8UL) /*!< IICINTM (Bit 8) */ + #define R_SCI_B0_ICR_IICINTM_Msk (0x100UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICCSC_Pos (9UL) /*!< IICCSC (Bit 9) */ + #define R_SCI_B0_ICR_IICCSC_Msk (0x200UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICACKT_Pos (13UL) /*!< IICACKT (Bit 13) */ + #define R_SCI_B0_ICR_IICACKT_Msk (0x2000UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICSTAREQ_Pos (16UL) /*!< IICSTAREQ (Bit 16) */ + #define R_SCI_B0_ICR_IICSTAREQ_Msk (0x10000UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICRSTAREQ_Pos (17UL) /*!< IICRSTAREQ (Bit 17) */ + #define R_SCI_B0_ICR_IICRSTAREQ_Msk (0x20000UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICSTPREQ_Pos (18UL) /*!< IICSTPREQ (Bit 18) */ + #define R_SCI_B0_ICR_IICSTPREQ_Msk (0x40000UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICSDAS_Pos (20UL) /*!< IICSDAS (Bit 20) */ + #define R_SCI_B0_ICR_IICSDAS_Msk (0x300000UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_ICR_IICSCLS_Pos (22UL) /*!< IICSCLS (Bit 22) */ + #define R_SCI_B0_ICR_IICSCLS_Msk (0xc00000UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI_B0_FCR_DRES_Pos (0UL) /*!< DRES (Bit 0) */ + #define R_SCI_B0_FCR_DRES_Msk (0x1UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FCR_TTRG_Pos (8UL) /*!< TTRG (Bit 8) */ + #define R_SCI_B0_FCR_TTRG_Msk (0x1f00UL) /*!< TTRG (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_FCR_TFRST_Pos (15UL) /*!< TFRST (Bit 15) */ + #define R_SCI_B0_FCR_TFRST_Msk (0x8000UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FCR_RTRG_Pos (16UL) /*!< RTRG (Bit 16) */ + #define R_SCI_B0_FCR_RTRG_Msk (0x1f0000UL) /*!< RTRG (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_FCR_RFRST_Pos (23UL) /*!< RFRST (Bit 23) */ + #define R_SCI_B0_FCR_RFRST_Msk (0x800000UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FCR_RSTRG_Pos (24UL) /*!< RSTRG (Bit 24) */ + #define R_SCI_B0_FCR_RSTRG_Msk (0x1f000000UL) /*!< RSTRG (Bitfield-Mask: 0x1f) */ +/* ========================================================== MCR ========================================================== */ + #define R_SCI_B0_MCR_RMPOL_Pos (0UL) /*!< RMPOL (Bit 0) */ + #define R_SCI_B0_MCR_RMPOL_Msk (0x1UL) /*!< RMPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_TMPOL_Pos (1UL) /*!< TMPOL (Bit 1) */ + #define R_SCI_B0_MCR_TMPOL_Msk (0x2UL) /*!< TMPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_ERTEN_Pos (2UL) /*!< ERTEN (Bit 2) */ + #define R_SCI_B0_MCR_ERTEN_Msk (0x4UL) /*!< ERTEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SYNVAL_Pos (4UL) /*!< SYNVAL (Bit 4) */ + #define R_SCI_B0_MCR_SYNVAL_Msk (0x10UL) /*!< SYNVAL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SYNSEL_Pos (5UL) /*!< SYNSEL (Bit 5) */ + #define R_SCI_B0_MCR_SYNSEL_Msk (0x20UL) /*!< SYNSEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SBSEL_Pos (6UL) /*!< SBSEL (Bit 6) */ + #define R_SCI_B0_MCR_SBSEL_Msk (0x40UL) /*!< SBSEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_TPLEN_Pos (8UL) /*!< TPLEN (Bit 8) */ + #define R_SCI_B0_MCR_TPLEN_Msk (0xf00UL) /*!< TPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI_B0_MCR_TPPAT_Pos (12UL) /*!< TPPAT (Bit 12) */ + #define R_SCI_B0_MCR_TPPAT_Msk (0x3000UL) /*!< TPPAT (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_MCR_RPLEN_Pos (16UL) /*!< RPLEN (Bit 16) */ + #define R_SCI_B0_MCR_RPLEN_Msk (0xf0000UL) /*!< RPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI_B0_MCR_RPPAT_Pos (20UL) /*!< RPPAT (Bit 20) */ + #define R_SCI_B0_MCR_RPPAT_Msk (0x300000UL) /*!< RPPAT (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_MCR_PFEREN_Pos (24UL) /*!< PFEREN (Bit 24) */ + #define R_SCI_B0_MCR_PFEREN_Msk (0x1000000UL) /*!< PFEREN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SYEREN_Pos (25UL) /*!< SYEREN (Bit 25) */ + #define R_SCI_B0_MCR_SYEREN_Msk (0x2000000UL) /*!< SYEREN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SBEREN_Pos (26UL) /*!< SBEREN (Bit 26) */ + #define R_SCI_B0_MCR_SBEREN_Msk (0x4000000UL) /*!< SBEREN (Bitfield-Mask: 0x01) */ +/* ========================================================== DCR ========================================================== */ + #define R_SCI_B0_DCR_DEPOL_Pos (0UL) /*!< DEPOL (Bit 0) */ + #define R_SCI_B0_DCR_DEPOL_Msk (0x1UL) /*!< DEPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_DCR_DEAST_Pos (8UL) /*!< DEAST (Bit 8) */ + #define R_SCI_B0_DCR_DEAST_Msk (0x1f00UL) /*!< DEAST (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_DCR_DENGT_Pos (16UL) /*!< DENGT (Bit 16) */ + #define R_SCI_B0_DCR_DENGT_Msk (0x1f0000UL) /*!< DENGT (Bitfield-Mask: 0x1f) */ +/* ========================================================= XCR0 ========================================================== */ + #define R_SCI_B0_XCR0_TCSS_Pos (0UL) /*!< TCSS (Bit 0) */ + #define R_SCI_B0_XCR0_TCSS_Msk (0x3UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_XCR0_BFE_Pos (8UL) /*!< BFE (Bit 8) */ + #define R_SCI_B0_XCR0_BFE_Msk (0x100UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_CF0RE_Pos (9UL) /*!< CF0RE (Bit 9) */ + #define R_SCI_B0_XCR0_CF0RE_Msk (0x200UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_CF1DS_Pos (10UL) /*!< CF1DS (Bit 10) */ + #define R_SCI_B0_XCR0_CF1DS_Msk (0xc00UL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_XCR0_PIBE_Pos (12UL) /*!< PIBE (Bit 12) */ + #define R_SCI_B0_XCR0_PIBE_Msk (0x1000UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_PIBS_Pos (13UL) /*!< PIBS (Bit 13) */ + #define R_SCI_B0_XCR0_PIBS_Msk (0xe000UL) /*!< PIBS (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_XCR0_BFOIE_Pos (16UL) /*!< BFOIE (Bit 16) */ + #define R_SCI_B0_XCR0_BFOIE_Msk (0x10000UL) /*!< BFOIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_BCDIE_Pos (17UL) /*!< BCDIE (Bit 17) */ + #define R_SCI_B0_XCR0_BCDIE_Msk (0x20000UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_BFDIE_Pos (20UL) /*!< BFDIE (Bit 20) */ + #define R_SCI_B0_XCR0_BFDIE_Msk (0x100000UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_COFIE_Pos (21UL) /*!< COFIE (Bit 21) */ + #define R_SCI_B0_XCR0_COFIE_Msk (0x200000UL) /*!< COFIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_AEDIE_Pos (22UL) /*!< AEDIE (Bit 22) */ + #define R_SCI_B0_XCR0_AEDIE_Msk (0x400000UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_BCCS_Pos (24UL) /*!< BCCS (Bit 24) */ + #define R_SCI_B0_XCR0_BCCS_Msk (0x3000000UL) /*!< BCCS (Bitfield-Mask: 0x03) */ +/* ========================================================= XCR1 ========================================================== */ + #define R_SCI_B0_XCR1_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI_B0_XCR1_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR1_SDST_Pos (4UL) /*!< SDST (Bit 4) */ + #define R_SCI_B0_XCR1_SDST_Msk (0x10UL) /*!< SDST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR1_BMEN_Pos (5UL) /*!< BMEN (Bit 5) */ + #define R_SCI_B0_XCR1_BMEN_Msk (0x20UL) /*!< BMEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR1_PCF1D_Pos (8UL) /*!< PCF1D (Bit 8) */ + #define R_SCI_B0_XCR1_PCF1D_Msk (0xff00UL) /*!< PCF1D (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR1_SCF1D_Pos (16UL) /*!< SCF1D (Bit 16) */ + #define R_SCI_B0_XCR1_SCF1D_Msk (0xff0000UL) /*!< SCF1D (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR1_CF1CE_Pos (24UL) /*!< CF1CE (Bit 24) */ + #define R_SCI_B0_XCR1_CF1CE_Msk (0xff000000UL) /*!< CF1CE (Bitfield-Mask: 0xff) */ +/* ========================================================= XCR2 ========================================================== */ + #define R_SCI_B0_XCR2_CF0D_Pos (0UL) /*!< CF0D (Bit 0) */ + #define R_SCI_B0_XCR2_CF0D_Msk (0xffUL) /*!< CF0D (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR2_CF0CE_Pos (8UL) /*!< CF0CE (Bit 8) */ + #define R_SCI_B0_XCR2_CF0CE_Msk (0xff00UL) /*!< CF0CE (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR2_BFLW_Pos (16UL) /*!< BFLW (Bit 16) */ + #define R_SCI_B0_XCR2_BFLW_Msk (0xffff0000UL) /*!< BFLW (Bitfield-Mask: 0xffff) */ +/* ========================================================== CSR ========================================================== */ + #define R_SCI_B0_CSR_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI_B0_CSR_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_RXDMON_Pos (15UL) /*!< RXDMON (Bit 15) */ + #define R_SCI_B0_CSR_RXDMON_Msk (0x8000UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_DCMF_Pos (16UL) /*!< DCMF (Bit 16) */ + #define R_SCI_B0_CSR_DCMF_Msk (0x10000UL) /*!< DCMF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_DPER_Pos (17UL) /*!< DPER (Bit 17) */ + #define R_SCI_B0_CSR_DPER_Msk (0x20000UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_DFER_Pos (18UL) /*!< DFER (Bit 18) */ + #define R_SCI_B0_CSR_DFER_Msk (0x40000UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_ORER_Pos (24UL) /*!< ORER (Bit 24) */ + #define R_SCI_B0_CSR_ORER_Msk (0x1000000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_MFF_Pos (26UL) /*!< MFF (Bit 26) */ + #define R_SCI_B0_CSR_MFF_Msk (0x4000000UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_PER_Pos (27UL) /*!< PER (Bit 27) */ + #define R_SCI_B0_CSR_PER_Msk (0x8000000UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_FER_Pos (28UL) /*!< FER (Bit 28) */ + #define R_SCI_B0_CSR_FER_Msk (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_TDRE_Pos (29UL) /*!< TDRE (Bit 29) */ + #define R_SCI_B0_CSR_TDRE_Msk (0x20000000UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_TEND_Pos (30UL) /*!< TEND (Bit 30) */ + #define R_SCI_B0_CSR_TEND_Msk (0x40000000UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_RDRF_Pos (31UL) /*!< RDRF (Bit 31) */ + #define R_SCI_B0_CSR_RDRF_Msk (0x80000000UL) /*!< RDRF (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ + #define R_SCI_B0_ISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI_B0_ISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ISR_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI_B0_ISR_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ +/* ========================================================= FRSR ========================================================== */ + #define R_SCI_B0_FRSR_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI_B0_FRSR_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FRSR_R_Pos (8UL) /*!< R (Bit 8) */ + #define R_SCI_B0_FRSR_R_Msk (0x3f00UL) /*!< R (Bitfield-Mask: 0x3f) */ + #define R_SCI_B0_FRSR_PNUM_Pos (16UL) /*!< PNUM (Bit 16) */ + #define R_SCI_B0_FRSR_PNUM_Msk (0x3f0000UL) /*!< PNUM (Bitfield-Mask: 0x3f) */ + #define R_SCI_B0_FRSR_FNUM_Pos (24UL) /*!< FNUM (Bit 24) */ + #define R_SCI_B0_FRSR_FNUM_Msk (0x3f000000UL) /*!< FNUM (Bitfield-Mask: 0x3f) */ +/* ========================================================= FTSR ========================================================== */ + #define R_SCI_B0_FTSR_T_Pos (0UL) /*!< T (Bit 0) */ + #define R_SCI_B0_FTSR_T_Msk (0x3fUL) /*!< T (Bitfield-Mask: 0x3f) */ +/* ========================================================== MSR ========================================================== */ + #define R_SCI_B0_MSR_PFER_Pos (0UL) /*!< PFER (Bit 0) */ + #define R_SCI_B0_MSR_PFER_Msk (0x1UL) /*!< PFER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_SYER_Pos (1UL) /*!< SYER (Bit 1) */ + #define R_SCI_B0_MSR_SYER_Msk (0x2UL) /*!< SYER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_SBER_Pos (2UL) /*!< SBER (Bit 2) */ + #define R_SCI_B0_MSR_SBER_Msk (0x4UL) /*!< SBER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_MER_Pos (4UL) /*!< MER (Bit 4) */ + #define R_SCI_B0_MSR_MER_Msk (0x10UL) /*!< MER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_RSYNC_Pos (6UL) /*!< RSYNC (Bit 6) */ + #define R_SCI_B0_MSR_RSYNC_Msk (0x40UL) /*!< RSYNC (Bitfield-Mask: 0x01) */ +/* ========================================================= XSR0 ========================================================== */ + #define R_SCI_B0_XSR0_SFSF_Pos (0UL) /*!< SFSF (Bit 0) */ + #define R_SCI_B0_XSR0_SFSF_Msk (0x1UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_RXDSF_Pos (1UL) /*!< RXDSF (Bit 1) */ + #define R_SCI_B0_XSR0_RXDSF_Msk (0x2UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_BFOF_Pos (8UL) /*!< BFOF (Bit 8) */ + #define R_SCI_B0_XSR0_BFOF_Msk (0x100UL) /*!< BFOF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_BCDF_Pos (9UL) /*!< BCDF (Bit 9) */ + #define R_SCI_B0_XSR0_BCDF_Msk (0x200UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_BFDF_Pos (10UL) /*!< BFDF (Bit 10) */ + #define R_SCI_B0_XSR0_BFDF_Msk (0x400UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_CF0MF_Pos (11UL) /*!< CF0MF (Bit 11) */ + #define R_SCI_B0_XSR0_CF0MF_Msk (0x800UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_CF1MF_Pos (12UL) /*!< CF1MF (Bit 12) */ + #define R_SCI_B0_XSR0_CF1MF_Msk (0x1000UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_PIBDF_Pos (13UL) /*!< PIBDF (Bit 13) */ + #define R_SCI_B0_XSR0_PIBDF_Msk (0x2000UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_COF_Pos (14UL) /*!< COF (Bit 14) */ + #define R_SCI_B0_XSR0_COF_Msk (0x4000UL) /*!< COF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_AEDF_Pos (15UL) /*!< AEDF (Bit 15) */ + #define R_SCI_B0_XSR0_AEDF_Msk (0x8000UL) /*!< AEDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_CF0RD_Pos (16UL) /*!< CF0RD (Bit 16) */ + #define R_SCI_B0_XSR0_CF0RD_Msk (0xff0000UL) /*!< CF0RD (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XSR0_CF1RD_Pos (24UL) /*!< CF1RD (Bit 24) */ + #define R_SCI_B0_XSR0_CF1RD_Msk (0xff000000UL) /*!< CF1RD (Bitfield-Mask: 0xff) */ +/* ========================================================= XSR1 ========================================================== */ + #define R_SCI_B0_XSR1_TCNT_Pos (0UL) /*!< TCNT (Bit 0) */ + #define R_SCI_B0_XSR1_TCNT_Msk (0xffffUL) /*!< TCNT (Bitfield-Mask: 0xffff) */ +/* ========================================================= CFCLR ========================================================= */ + #define R_SCI_B0_CFCLR_ERSC_Pos (4UL) /*!< ERSC (Bit 4) */ + #define R_SCI_B0_CFCLR_ERSC_Msk (0x10UL) /*!< ERSC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_DCMFC_Pos (16UL) /*!< DCMFC (Bit 16) */ + #define R_SCI_B0_CFCLR_DCMFC_Msk (0x10000UL) /*!< DCMFC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_DPERC_Pos (17UL) /*!< DPERC (Bit 17) */ + #define R_SCI_B0_CFCLR_DPERC_Msk (0x20000UL) /*!< DPERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_DFERC_Pos (18UL) /*!< DFERC (Bit 18) */ + #define R_SCI_B0_CFCLR_DFERC_Msk (0x40000UL) /*!< DFERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_ORERC_Pos (24UL) /*!< ORERC (Bit 24) */ + #define R_SCI_B0_CFCLR_ORERC_Msk (0x1000000UL) /*!< ORERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_MFFC_Pos (26UL) /*!< MFFC (Bit 26) */ + #define R_SCI_B0_CFCLR_MFFC_Msk (0x4000000UL) /*!< MFFC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_PERC_Pos (27UL) /*!< PERC (Bit 27) */ + #define R_SCI_B0_CFCLR_PERC_Msk (0x8000000UL) /*!< PERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_FERC_Pos (28UL) /*!< FERC (Bit 28) */ + #define R_SCI_B0_CFCLR_FERC_Msk (0x10000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_TDREC_Pos (29UL) /*!< TDREC (Bit 29) */ + #define R_SCI_B0_CFCLR_TDREC_Msk (0x20000000UL) /*!< TDREC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_RDRFC_Pos (31UL) /*!< RDRFC (Bit 31) */ + #define R_SCI_B0_CFCLR_RDRFC_Msk (0x80000000UL) /*!< RDRFC (Bitfield-Mask: 0x01) */ +/* ======================================================== ICFCLR ========================================================= */ + #define R_SCI_B0_ICFCLR_IICSTIFC_Pos (3UL) /*!< IICSTIFC (Bit 3) */ + #define R_SCI_B0_ICFCLR_IICSTIFC_Msk (0x8UL) /*!< IICSTIFC (Bitfield-Mask: 0x01) */ +/* ========================================================= FFCLR ========================================================= */ + #define R_SCI_B0_FFCLR_DRC_Pos (0UL) /*!< DRC (Bit 0) */ + #define R_SCI_B0_FFCLR_DRC_Msk (0x1UL) /*!< DRC (Bitfield-Mask: 0x01) */ +/* ========================================================= MFCLR ========================================================= */ + #define R_SCI_B0_MFCLR_PFERC_Pos (0UL) /*!< PFERC (Bit 0) */ + #define R_SCI_B0_MFCLR_PFERC_Msk (0x1UL) /*!< PFERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MFCLR_SYERC_Pos (1UL) /*!< SYERC (Bit 1) */ + #define R_SCI_B0_MFCLR_SYERC_Msk (0x2UL) /*!< SYERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MFCLR_SBERC_Pos (2UL) /*!< SBERC (Bit 2) */ + #define R_SCI_B0_MFCLR_SBERC_Msk (0x4UL) /*!< SBERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MFCLR_MERC_Pos (4UL) /*!< MERC (Bit 4) */ + #define R_SCI_B0_MFCLR_MERC_Msk (0x10UL) /*!< MERC (Bitfield-Mask: 0x01) */ +/* ========================================================= XFCLR ========================================================= */ + #define R_SCI_B0_XFCLR_BFOC_Pos (8UL) /*!< BFOC (Bit 8) */ + #define R_SCI_B0_XFCLR_BFOC_Msk (0x100UL) /*!< BFOC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_BCDC_Pos (9UL) /*!< BCDC (Bit 9) */ + #define R_SCI_B0_XFCLR_BCDC_Msk (0x200UL) /*!< BCDC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_BFDC_Pos (10UL) /*!< BFDC (Bit 10) */ + #define R_SCI_B0_XFCLR_BFDC_Msk (0x400UL) /*!< BFDC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_CF0MC_Pos (11UL) /*!< CF0MC (Bit 11) */ + #define R_SCI_B0_XFCLR_CF0MC_Msk (0x800UL) /*!< CF0MC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_CF1MC_Pos (12UL) /*!< CF1MC (Bit 12) */ + #define R_SCI_B0_XFCLR_CF1MC_Msk (0x1000UL) /*!< CF1MC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_PIBDC_Pos (13UL) /*!< PIBDC (Bit 13) */ + #define R_SCI_B0_XFCLR_PIBDC_Msk (0x2000UL) /*!< PIBDC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_COFC_Pos (14UL) /*!< COFC (Bit 14) */ + #define R_SCI_B0_XFCLR_COFC_Msk (0x4000UL) /*!< COFC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_AEDC_Pos (15UL) /*!< AEDC (Bit 15) */ + #define R_SCI_B0_XFCLR_AEDC_Msk (0x8000UL) /*!< AEDC (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI_B0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDECR ========================================================= */ + #define R_SPI_B0_SPDECR_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI_B0_SPDECR_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPDECR_SLNDL_Pos (8UL) /*!< SLNDL (Bit 8) */ + #define R_SPI_B0_SPDECR_SLNDL_Msk (0x700UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPDECR_SPNDL_Pos (16UL) /*!< SPNDL (Bit 16) */ + #define R_SPI_B0_SPDECR_SPNDL_Msk (0x70000UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPDECR_ARST_Pos (24UL) /*!< ARST (Bit 24) */ + #define R_SPI_B0_SPDECR_ARST_Msk (0x7000000UL) /*!< ARST (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR ========================================================== */ + #define R_SPI_B0_SPCR_SPE_Pos (0UL) /*!< SPE (Bit 0) */ + #define R_SPI_B0_SPCR_SPE_Msk (0x1UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPSCKSEL_Pos (7UL) /*!< SPSCKSEL (Bit 7) */ + #define R_SPI_B0_SPCR_SPSCKSEL_Msk (0x80UL) /*!< SPSCKSEL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPPE_Pos (8UL) /*!< SPPE (Bit 8) */ + #define R_SPI_B0_SPCR_SPPE_Msk (0x100UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPOE_Pos (9UL) /*!< SPOE (Bit 9) */ + #define R_SPI_B0_SPCR_SPOE_Msk (0x200UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_PTE_Pos (11UL) /*!< PTE (Bit 11) */ + #define R_SPI_B0_SPCR_PTE_Msk (0x800UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SCKASE_Pos (12UL) /*!< SCKASE (Bit 12) */ + #define R_SPI_B0_SPCR_SCKASE_Msk (0x1000UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_BFDS_Pos (13UL) /*!< BFDS (Bit 13) */ + #define R_SPI_B0_SPCR_BFDS_Msk (0x2000UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_MODFEN_Pos (14UL) /*!< MODFEN (Bit 14) */ + #define R_SPI_B0_SPCR_MODFEN_Msk (0x4000UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPEIE_Pos (16UL) /*!< SPEIE (Bit 16) */ + #define R_SPI_B0_SPCR_SPEIE_Msk (0x10000UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPRIE_Pos (17UL) /*!< SPRIE (Bit 17) */ + #define R_SPI_B0_SPCR_SPRIE_Msk (0x20000UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPIIE_Pos (18UL) /*!< SPIIE (Bit 18) */ + #define R_SPI_B0_SPCR_SPIIE_Msk (0x40000UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPDRES_Pos (19UL) /*!< SPDRES (Bit 19) */ + #define R_SPI_B0_SPCR_SPDRES_Msk (0x80000UL) /*!< SPDRES (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPTIE_Pos (20UL) /*!< SPTIE (Bit 20) */ + #define R_SPI_B0_SPCR_SPTIE_Msk (0x100000UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_CENDIE_Pos (21UL) /*!< CENDIE (Bit 21) */ + #define R_SPI_B0_SPCR_CENDIE_Msk (0x200000UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPMS_Pos (24UL) /*!< SPMS (Bit 24) */ + #define R_SPI_B0_SPCR_SPMS_Msk (0x1000000UL) /*!< SPMS (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPFRF_Pos (25UL) /*!< SPFRF (Bit 25) */ + #define R_SPI_B0_SPCR_SPFRF_Msk (0x2000000UL) /*!< SPFRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_TXMD_Pos (28UL) /*!< TXMD (Bit 28) */ + #define R_SPI_B0_SPCR_TXMD_Msk (0x30000000UL) /*!< TXMD (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCR_MSTR_Pos (30UL) /*!< MSTR (Bit 30) */ + #define R_SPI_B0_SPCR_MSTR_Msk (0x40000000UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_BPEN_Pos (31UL) /*!< BPEN (Bit 31) */ + #define R_SPI_B0_SPCR_BPEN_Msk (0x80000000UL) /*!< BPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI_B0_SPCR2_RMFM_Pos (0UL) /*!< RMFM (Bit 0) */ + #define R_SPI_B0_SPCR2_RMFM_Msk (0x1fUL) /*!< RMFM (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCR2_RMEDTG_Pos (6UL) /*!< RMEDTG (Bit 6) */ + #define R_SPI_B0_SPCR2_RMEDTG_Msk (0x40UL) /*!< RMEDTG (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_RMSTTG_Pos (7UL) /*!< RMSTTG (Bit 7) */ + #define R_SPI_B0_SPCR2_RMSTTG_Msk (0x80UL) /*!< RMSTTG (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_SPDRC_Pos (8UL) /*!< SPDRC (Bit 8) */ + #define R_SPI_B0_SPCR2_SPDRC_Msk (0xff00UL) /*!< SPDRC (Bitfield-Mask: 0xff) */ + #define R_SPI_B0_SPCR2_SPLP_Pos (16UL) /*!< SPLP (Bit 16) */ + #define R_SPI_B0_SPCR2_SPLP_Msk (0x10000UL) /*!< SPLP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_SPLP2_Pos (17UL) /*!< SPLP2 (Bit 17) */ + #define R_SPI_B0_SPCR2_SPLP2_Msk (0x20000UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_MOIFV_Pos (20UL) /*!< MOIFV (Bit 20) */ + #define R_SPI_B0_SPCR2_MOIFV_Msk (0x100000UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_MOIFE_Pos (21UL) /*!< MOIFE (Bit 21) */ + #define R_SPI_B0_SPCR2_MOIFE_Msk (0x200000UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI_B0_SPCR3_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI_B0_SPCR3_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI_B0_SPCR3_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI_B0_SPCR3_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI_B0_SPCR3_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SPBR_Pos (8UL) /*!< SPBR (Bit 8) */ + #define R_SPI_B0_SPCR3_SPBR_Msk (0xff00UL) /*!< SPBR (Bitfield-Mask: 0xff) */ + #define R_SPI_B0_SPCR3_SPSLN_Pos (24UL) /*!< SPSLN (Bit 24) */ + #define R_SPI_B0_SPCR3_SPSLN_Msk (0x7000000UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD0 ========================================================= */ + #define R_SPI_B0_SPCMD0_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD0_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD0_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD0_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD0_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD0_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD0_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD0_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD0_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD0_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD0_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD0_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD0_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD1 ========================================================= */ + #define R_SPI_B0_SPCMD1_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD1_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD1_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD1_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD1_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD1_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD1_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD1_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD1_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD1_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD1_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD1_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD1_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD2 ========================================================= */ + #define R_SPI_B0_SPCMD2_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD2_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD2_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD2_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD2_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD2_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD2_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD2_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD2_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD2_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD2_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD2_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD2_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD3 ========================================================= */ + #define R_SPI_B0_SPCMD3_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD3_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD3_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD3_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD3_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD3_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD3_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD3_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD3_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD3_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD3_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD3_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD3_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD4 ========================================================= */ + #define R_SPI_B0_SPCMD4_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD4_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD4_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD4_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD4_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD4_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD4_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD4_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD4_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD4_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD4_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD4_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD4_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD5 ========================================================= */ + #define R_SPI_B0_SPCMD5_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD5_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD5_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD5_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD5_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD5_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD5_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD5_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD5_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD5_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD5_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD5_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD5_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD6 ========================================================= */ + #define R_SPI_B0_SPCMD6_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD6_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD6_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD6_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD6_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD6_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD6_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD6_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD6_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD6_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD6_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD6_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD6_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD7 ========================================================= */ + #define R_SPI_B0_SPCMD7_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD7_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD7_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD7_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD7_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD7_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD7_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD7_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD7_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD7_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD7_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD7_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD7_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI_B0_SPDCR_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI_B0_SPDCR_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPDCR_SPRDTD_Pos (3UL) /*!< SPRDTD (Bit 3) */ + #define R_SPI_B0_SPDCR_SPRDTD_Msk (0x8UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPDCR_SINV_Pos (4UL) /*!< SINV (Bit 4) */ + #define R_SPI_B0_SPDCR_SINV_Msk (0x10UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPDCR_SPFC_Pos (8UL) /*!< SPFC (Bit 8) */ + #define R_SPI_B0_SPDCR_SPFC_Msk (0x300UL) /*!< SPFC (Bitfield-Mask: 0x03) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI_B0_SPDCR2_RTRG_Pos (0UL) /*!< RTRG (Bit 0) */ + #define R_SPI_B0_SPDCR2_RTRG_Msk (0x3UL) /*!< RTRG (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPDCR2_TTRG_Pos (8UL) /*!< TTRG (Bit 8) */ + #define R_SPI_B0_SPDCR2_TTRG_Msk (0x300UL) /*!< TTRG (Bitfield-Mask: 0x03) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI_B0_SPSR_SPCP_Pos (8UL) /*!< SPCP (Bit 8) */ + #define R_SPI_B0_SPSR_SPCP_Msk (0x700UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPSR_SPECM_Pos (12UL) /*!< SPECM (Bit 12) */ + #define R_SPI_B0_SPSR_SPECM_Msk (0x7000UL) /*!< SPECM (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPSR_SPDRF_Pos (23UL) /*!< SPDRF (Bit 23) */ + #define R_SPI_B0_SPSR_SPDRF_Msk (0x800000UL) /*!< SPDRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_OVRF_Pos (24UL) /*!< OVRF (Bit 24) */ + #define R_SPI_B0_SPSR_OVRF_Msk (0x1000000UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_IDLNF_Pos (25UL) /*!< IDLNF (Bit 25) */ + #define R_SPI_B0_SPSR_IDLNF_Msk (0x2000000UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_MODF_Pos (26UL) /*!< MODF (Bit 26) */ + #define R_SPI_B0_SPSR_MODF_Msk (0x4000000UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_PERF_Pos (27UL) /*!< PERF (Bit 27) */ + #define R_SPI_B0_SPSR_PERF_Msk (0x8000000UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_UDRF_Pos (28UL) /*!< UDRF (Bit 28) */ + #define R_SPI_B0_SPSR_UDRF_Msk (0x10000000UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_SPTEF_Pos (29UL) /*!< SPTEF (Bit 29) */ + #define R_SPI_B0_SPSR_SPTEF_Msk (0x20000000UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_CENDF_Pos (30UL) /*!< CENDF (Bit 30) */ + #define R_SPI_B0_SPSR_CENDF_Msk (0x40000000UL) /*!< CENDF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_SPRF_Pos (31UL) /*!< SPRF (Bit 31) */ + #define R_SPI_B0_SPSR_SPRF_Msk (0x80000000UL) /*!< SPRF (Bitfield-Mask: 0x01) */ +/* ======================================================== SPTFSR ========================================================= */ + #define R_SPI_B0_SPTFSR_TFDN_Pos (0UL) /*!< TFDN (Bit 0) */ + #define R_SPI_B0_SPTFSR_TFDN_Msk (0x7UL) /*!< TFDN (Bitfield-Mask: 0x07) */ +/* ======================================================== SPRFSR ========================================================= */ + #define R_SPI_B0_SPRFSR_RFDN_Pos (0UL) /*!< RFDN (Bit 0) */ + #define R_SPI_B0_SPRFSR_RFDN_Msk (0x7UL) /*!< RFDN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPPSR ========================================================= */ + #define R_SPI_B0_SPPSR_SPEPS_Pos (0UL) /*!< SPEPS (Bit 0) */ + #define R_SPI_B0_SPPSR_SPEPS_Msk (0x1UL) /*!< SPEPS (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSRC ========================================================= */ + #define R_SPI_B0_SPSRC_SPDRFC_Pos (23UL) /*!< SPDRFC (Bit 23) */ + #define R_SPI_B0_SPSRC_SPDRFC_Msk (0x800000UL) /*!< SPDRFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_OVRFC_Pos (24UL) /*!< OVRFC (Bit 24) */ + #define R_SPI_B0_SPSRC_OVRFC_Msk (0x1000000UL) /*!< OVRFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_MODFC_Pos (26UL) /*!< MODFC (Bit 26) */ + #define R_SPI_B0_SPSRC_MODFC_Msk (0x4000000UL) /*!< MODFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_PERFC_Pos (27UL) /*!< PERFC (Bit 27) */ + #define R_SPI_B0_SPSRC_PERFC_Msk (0x8000000UL) /*!< PERFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_UDRFC_Pos (28UL) /*!< UDRFC (Bit 28) */ + #define R_SPI_B0_SPSRC_UDRFC_Msk (0x10000000UL) /*!< UDRFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_SPTEFC_Pos (29UL) /*!< SPTEFC (Bit 29) */ + #define R_SPI_B0_SPSRC_SPTEFC_Msk (0x20000000UL) /*!< SPTEFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_CENDFC_Pos (30UL) /*!< CENDFC (Bit 30) */ + #define R_SPI_B0_SPSRC_CENDFC_Msk (0x40000000UL) /*!< CENDFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_SPRFC_Pos (31UL) /*!< SPRFC (Bit 31) */ + #define R_SPI_B0_SPSRC_SPRFC_Msk (0x80000000UL) /*!< SPRFC (Bitfield-Mask: 0x01) */ +/* ========================================================= SPFCR ========================================================= */ + #define R_SPI_B0_SPFCR_SPFRST_Pos (0UL) /*!< SPFRST (Bit 0) */ + #define R_SPI_B0_SPFCR_SPFRST_Msk (0x1UL) /*!< SPFRST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_HS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_HS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_HS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_HSE_Pos (7UL) /*!< HSE (Bit 7) */ + #define R_USB_HS0_SYSCFG_HSE_Msk (0x80UL) /*!< HSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_HS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_HS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_HS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_HS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_HS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_HS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_HS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_HS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_HS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_HS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_HS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_HS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_HS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_HS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_HS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_HS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_HS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_HS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_HS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_HS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_HS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_HS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_HS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_HS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_HS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_HS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ========================================================= CFIFO ========================================================= */ + #define R_USB_HS0_CFIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_CFIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ + #define R_USB_HS0_D0FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_D0FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ + #define R_USB_HS0_D1FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_D1FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_HS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_HS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_HS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_HS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_HS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_HS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_HS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_HS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_HS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_HS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_HS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_HS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_HS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_HS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_HS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_HS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_HS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_HS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_HS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_HS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_HS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_HS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_HS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_HS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_HS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_L1RSMENDE_Pos (9UL) /*!< L1RSMENDE (Bit 9) */ + #define R_USB_HS0_INTENB1_L1RSMENDE_Msk (0x200UL) /*!< L1RSMENDE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_LPMENDE_Pos (8UL) /*!< LPMENDE (Bit 8) */ + #define R_USB_HS0_INTENB1_LPMENDE_Msk (0x100UL) /*!< LPMENDE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_HS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_HS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_HS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_HS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_HS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_HS0_BRDYENB_PIPEBRDYE_Msk (0x3ffUL) /*!< PIPEBRDYE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_HS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_HS0_NRDYENB_PIPENRDYE_Msk (0x3ffUL) /*!< PIPENRDYE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_HS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_HS0_BEMPENB_PIPEBEMPE_Msk (0x3ffUL) /*!< PIPEBEMPE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_HS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_HS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_HS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_HS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_HS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_HS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_HS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_HS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_HS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_HS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_HS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_HS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_HS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_HS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_HS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_HS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_HS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_HS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_HS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_HS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_HS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_HS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_HS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_HS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_HS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_HS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_HS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_HS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_HS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_HS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_HS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_HS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_HS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_HS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_HS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_HS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_HS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_HS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_HS0_BRDYSTS_PIPEBRDY_Msk (0x3ffUL) /*!< PIPEBRDY (Bitfield-Mask: 0x3ff) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_HS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_HS0_NRDYSTS_PIPENRDY_Msk (0x3ffUL) /*!< PIPENRDY (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_HS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_HS0_BEMPSTS_PIPEBEMP_Msk (0x3ffUL) /*!< PIPEBEMP (Bitfield-Mask: 0x3ff) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_HS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_HS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_HS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_HS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== UFRMNUM ======================================================== */ + #define R_USB_HS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_HS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ + #define R_USB_HS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_HS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_HS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_HS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_HS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_HS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_HS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_HS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_HS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_HS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_HS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_HS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_HS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_HS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_HS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_HS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_HS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_HS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_HS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_HS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_HS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_HS0_DCPCTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_HS0_DCPCTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_HS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_HS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_HS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_HS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_HS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PINGE_Pos (4UL) /*!< PINGE (Bit 4) */ + #define R_USB_HS0_DCPCTR_PINGE_Msk (0x10UL) /*!< PINGE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_HS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_HS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_HS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_HS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_HS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_HS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_HS0_PIPECFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_HS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_HS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_HS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPEBUF ======================================================== */ + #define R_USB_HS0_PIPEBUF_BUFSIZE_Pos (10UL) /*!< BUFSIZE (Bit 10) */ + #define R_USB_HS0_PIPEBUF_BUFSIZE_Msk (0x7c00UL) /*!< BUFSIZE (Bitfield-Mask: 0x1f) */ + #define R_USB_HS0_PIPEBUF_BUFNMB_Pos (0UL) /*!< BUFNMB (Bit 0) */ + #define R_USB_HS0_PIPEBUF_BUFNMB_Msk (0xffUL) /*!< BUFNMB (Bitfield-Mask: 0xff) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_HS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_HS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_HS0_PIPEMAXP_MXPS_Msk (0x7ffUL) /*!< MXPS (Bitfield-Mask: 0x7ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_HS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_HS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_HS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_HS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_HS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_HS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_HS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_HS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_HS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_HS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_HS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_HS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_HS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_HS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_HS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_HS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_HS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_HS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_HS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_HS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_HS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_HS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_HS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_HS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_HS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_HS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_HS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_HS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_HS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_HS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_HS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_HS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_HS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_HS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_HS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_HS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_HS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_HS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_HS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_HS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_HS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_HS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_HS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_HS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_HS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_HS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_HS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_HS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_HS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================= PHYTRIM1 ======================================================== */ + #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Pos (12UL) /*!< IMPOFFSET (Bit 12) */ + #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Msk (0x7000UL) /*!< IMPOFFSET (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_PHYTRIM1_HSIUP_Pos (8UL) /*!< HSIUP (Bit 8) */ + #define R_USB_HS0_PHYTRIM1_HSIUP_Msk (0xf00UL) /*!< HSIUP (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PHYTRIM1_PCOMPENB_Pos (7UL) /*!< PCOMPENB (Bit 7) */ + #define R_USB_HS0_PHYTRIM1_PCOMPENB_Msk (0x80UL) /*!< PCOMPENB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYTRIM1_DFALL_Pos (2UL) /*!< DFALL (Bit 2) */ + #define R_USB_HS0_PHYTRIM1_DFALL_Msk (0xcUL) /*!< DFALL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYTRIM1_DRISE_Pos (0UL) /*!< DRISE (Bit 0) */ + #define R_USB_HS0_PHYTRIM1_DRISE_Msk (0x3UL) /*!< DRISE (Bitfield-Mask: 0x03) */ +/* ======================================================= PHYTRIM2 ======================================================== */ + #define R_USB_HS0_PHYTRIM2_DIS_Pos (12UL) /*!< DIS (Bit 12) */ + #define R_USB_HS0_PHYTRIM2_DIS_Msk (0x7000UL) /*!< DIS (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_PHYTRIM2_PDR_Pos (8UL) /*!< PDR (Bit 8) */ + #define R_USB_HS0_PHYTRIM2_PDR_Msk (0x300UL) /*!< PDR (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYTRIM2_HSRXENMO_Pos (7UL) /*!< HSRXENMO (Bit 7) */ + #define R_USB_HS0_PHYTRIM2_HSRXENMO_Msk (0x80UL) /*!< HSRXENMO (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYTRIM2_SQU_Pos (0UL) /*!< SQU (Bit 0) */ + #define R_USB_HS0_PHYTRIM2_SQU_Msk (0xfUL) /*!< SQU (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_HS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_HS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_HS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_HS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_HS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_HS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_HS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_HS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_HS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_HS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_HS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_HS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_HS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_HS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_HS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_HS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_HS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_HS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_HS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_HS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_HS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_XSPI0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== WRAPCFG ======================================================== */ + #define R_XSPI0_WRAPCFG_CKSFTCS0_Pos (0UL) /*!< CKSFTCS0 (Bit 0) */ + #define R_XSPI0_WRAPCFG_CKSFTCS0_Msk (0x1fUL) /*!< CKSFTCS0 (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_WRAPCFG_DSSFTCS0_Pos (8UL) /*!< DSSFTCS0 (Bit 8) */ + #define R_XSPI0_WRAPCFG_DSSFTCS0_Msk (0x1f00UL) /*!< DSSFTCS0 (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_WRAPCFG_CKSFTCS1_Pos (16UL) /*!< CKSFTCS1 (Bit 16) */ + #define R_XSPI0_WRAPCFG_CKSFTCS1_Msk (0x1f0000UL) /*!< CKSFTCS1 (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_WRAPCFG_DSSFTCS1_Pos (24UL) /*!< DSSFTCS1 (Bit 24) */ + #define R_XSPI0_WRAPCFG_DSSFTCS1_Msk (0x1f000000UL) /*!< DSSFTCS1 (Bitfield-Mask: 0x1f) */ +/* ======================================================== COMCFG ========================================================= */ + #define R_XSPI0_COMCFG_ARBMD_Pos (0UL) /*!< ARBMD (Bit 0) */ + #define R_XSPI0_COMCFG_ARBMD_Msk (0x3UL) /*!< ARBMD (Bitfield-Mask: 0x03) */ + #define R_XSPI0_COMCFG_ECSINTOUTEN_Pos (4UL) /*!< ECSINTOUTEN (Bit 4) */ + #define R_XSPI0_COMCFG_ECSINTOUTEN_Msk (0x30UL) /*!< ECSINTOUTEN (Bitfield-Mask: 0x03) */ + #define R_XSPI0_COMCFG_OEASTEX_Pos (16UL) /*!< OEASTEX (Bit 16) */ + #define R_XSPI0_COMCFG_OEASTEX_Msk (0x10000UL) /*!< OEASTEX (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMCFG_OENEGEX_Pos (17UL) /*!< OENEGEX (Bit 17) */ + #define R_XSPI0_COMCFG_OENEGEX_Msk (0x20000UL) /*!< OENEGEX (Bitfield-Mask: 0x01) */ +/* ======================================================== BMCFGCH ======================================================== */ + #define R_XSPI0_BMCFGCH_WRMD_Pos (0UL) /*!< WRMD (Bit 0) */ + #define R_XSPI0_BMCFGCH_WRMD_Msk (0x1UL) /*!< WRMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCFGCH_MWRCOMB_Pos (7UL) /*!< MWRCOMB (Bit 7) */ + #define R_XSPI0_BMCFGCH_MWRCOMB_Msk (0x80UL) /*!< MWRCOMB (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCFGCH_MWRSIZE_Pos (8UL) /*!< MWRSIZE (Bit 8) */ + #define R_XSPI0_BMCFGCH_MWRSIZE_Msk (0xff00UL) /*!< MWRSIZE (Bitfield-Mask: 0xff) */ + #define R_XSPI0_BMCFGCH_PREEN_Pos (16UL) /*!< PREEN (Bit 16) */ + #define R_XSPI0_BMCFGCH_PREEN_Msk (0x10000UL) /*!< PREEN (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCFGCH_CMBTIM_Pos (24UL) /*!< CMBTIM (Bit 24) */ + #define R_XSPI0_BMCFGCH_CMBTIM_Msk (0xff000000UL) /*!< CMBTIM (Bitfield-Mask: 0xff) */ +/* ======================================================= LIOCFGCS ======================================================== */ + #define R_XSPI0_LIOCFGCS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */ + #define R_XSPI0_LIOCFGCS_PRTMD_Msk (0x3ffUL) /*!< PRTMD (Bitfield-Mask: 0x3ff) */ + #define R_XSPI0_LIOCFGCS_LATEMD_Pos (10UL) /*!< LATEMD (Bit 10) */ + #define R_XSPI0_LIOCFGCS_LATEMD_Msk (0x400UL) /*!< LATEMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_WRMSKMD_Pos (11UL) /*!< WRMSKMD (Bit 11) */ + #define R_XSPI0_LIOCFGCS_WRMSKMD_Msk (0x800UL) /*!< WRMSKMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_CSMIN_Pos (16UL) /*!< CSMIN (Bit 16) */ + #define R_XSPI0_LIOCFGCS_CSMIN_Msk (0xf0000UL) /*!< CSMIN (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_LIOCFGCS_CSASTEX_Pos (20UL) /*!< CSASTEX (Bit 20) */ + #define R_XSPI0_LIOCFGCS_CSASTEX_Msk (0x100000UL) /*!< CSASTEX (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_CSNEGEX_Pos (21UL) /*!< CSNEGEX (Bit 21) */ + #define R_XSPI0_LIOCFGCS_CSNEGEX_Msk (0x200000UL) /*!< CSNEGEX (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_SDRDRV_Pos (22UL) /*!< SDRDRV (Bit 22) */ + #define R_XSPI0_LIOCFGCS_SDRDRV_Msk (0x400000UL) /*!< SDRDRV (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_SDRSMPMD_Pos (23UL) /*!< SDRSMPMD (Bit 23) */ + #define R_XSPI0_LIOCFGCS_SDRSMPMD_Msk (0x800000UL) /*!< SDRSMPMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_SDRSMPSFT_Pos (24UL) /*!< SDRSMPSFT (Bit 24) */ + #define R_XSPI0_LIOCFGCS_SDRSMPSFT_Msk (0xf000000UL) /*!< SDRSMPSFT (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_LIOCFGCS_DDRSMPEX_Pos (28UL) /*!< DDRSMPEX (Bit 28) */ + #define R_XSPI0_LIOCFGCS_DDRSMPEX_Msk (0xf0000000UL) /*!< DDRSMPEX (Bitfield-Mask: 0x0f) */ +/* ======================================================== ABMCFG ========================================================= */ + #define R_XSPI0_ABMCFG_ODRMD_Pos (0UL) /*!< ODRMD (Bit 0) */ + #define R_XSPI0_ABMCFG_ODRMD_Msk (0x3UL) /*!< ODRMD (Bitfield-Mask: 0x03) */ + #define R_XSPI0_ABMCFG_CHSEL_Pos (16UL) /*!< CHSEL (Bit 16) */ + #define R_XSPI0_ABMCFG_CHSEL_Msk (0xffff0000UL) /*!< CHSEL (Bitfield-Mask: 0xffff) */ +/* ======================================================== BMCTL0 ========================================================= */ + #define R_XSPI0_BMCTL0_CH0CS0ACC_Pos (0UL) /*!< CH0CS0ACC (Bit 0) */ + #define R_XSPI0_BMCTL0_CH0CS0ACC_Msk (0x3UL) /*!< CH0CS0ACC (Bitfield-Mask: 0x03) */ + #define R_XSPI0_BMCTL0_CH0CS1ACC_Pos (2UL) /*!< CH0CS1ACC (Bit 2) */ + #define R_XSPI0_BMCTL0_CH0CS1ACC_Msk (0xcUL) /*!< CH0CS1ACC (Bitfield-Mask: 0x03) */ + #define R_XSPI0_BMCTL0_CH1CS0ACC_Pos (4UL) /*!< CH1CS0ACC (Bit 4) */ + #define R_XSPI0_BMCTL0_CH1CS0ACC_Msk (0x30UL) /*!< CH1CS0ACC (Bitfield-Mask: 0x03) */ + #define R_XSPI0_BMCTL0_CH1CS1ACC_Pos (6UL) /*!< CH1CS1ACC (Bit 6) */ + #define R_XSPI0_BMCTL0_CH1CS1ACC_Msk (0xc0UL) /*!< CH1CS1ACC (Bitfield-Mask: 0x03) */ +/* ======================================================== BMCTL1 ========================================================= */ + #define R_XSPI0_BMCTL1_MWRPUSHCH_Pos (8UL) /*!< MWRPUSHCH (Bit 8) */ + #define R_XSPI0_BMCTL1_MWRPUSHCH_Msk (0x100UL) /*!< MWRPUSHCH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCTL1_PBUFCLRCH_Pos (10UL) /*!< PBUFCLRCH (Bit 10) */ + #define R_XSPI0_BMCTL1_PBUFCLRCH_Msk (0x400UL) /*!< PBUFCLRCH (Bitfield-Mask: 0x01) */ +/* ======================================================== CMCTLCH ======================================================== */ + #define R_XSPI0_CMCTLCH_XIPENCODE_Pos (0UL) /*!< XIPENCODE (Bit 0) */ + #define R_XSPI0_CMCTLCH_XIPENCODE_Msk (0xffUL) /*!< XIPENCODE (Bitfield-Mask: 0xff) */ + #define R_XSPI0_CMCTLCH_XIPEXCODE_Pos (8UL) /*!< XIPEXCODE (Bit 8) */ + #define R_XSPI0_CMCTLCH_XIPEXCODE_Msk (0xff00UL) /*!< XIPEXCODE (Bitfield-Mask: 0xff) */ + #define R_XSPI0_CMCTLCH_XIPEN_Pos (16UL) /*!< XIPEN (Bit 16) */ + #define R_XSPI0_CMCTLCH_XIPEN_Msk (0x10000UL) /*!< XIPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== CDCTL0 ========================================================= */ + #define R_XSPI0_CDCTL0_TRREQ_Pos (0UL) /*!< TRREQ (Bit 0) */ + #define R_XSPI0_CDCTL0_TRREQ_Msk (0x1UL) /*!< TRREQ (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDCTL0_PERMD_Pos (1UL) /*!< PERMD (Bit 1) */ + #define R_XSPI0_CDCTL0_PERMD_Msk (0x2UL) /*!< PERMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDCTL0_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */ + #define R_XSPI0_CDCTL0_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDCTL0_TRNUM_Pos (4UL) /*!< TRNUM (Bit 4) */ + #define R_XSPI0_CDCTL0_TRNUM_Msk (0x30UL) /*!< TRNUM (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CDCTL0_PERITV_Pos (16UL) /*!< PERITV (Bit 16) */ + #define R_XSPI0_CDCTL0_PERITV_Msk (0x1f0000UL) /*!< PERITV (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CDCTL0_PERREP_Pos (24UL) /*!< PERREP (Bit 24) */ + #define R_XSPI0_CDCTL0_PERREP_Msk (0xf000000UL) /*!< PERREP (Bitfield-Mask: 0x0f) */ +/* ======================================================== CDCTL1 ========================================================= */ + #define R_XSPI0_CDCTL1_PEREXP_Pos (0UL) /*!< PEREXP (Bit 0) */ + #define R_XSPI0_CDCTL1_PEREXP_Msk (0xffffffffUL) /*!< PEREXP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDCTL2 ========================================================= */ + #define R_XSPI0_CDCTL2_PERMSK_Pos (0UL) /*!< PERMSK (Bit 0) */ + #define R_XSPI0_CDCTL2_PERMSK_Msk (0xffffffffUL) /*!< PERMSK (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LPCTL0 ========================================================= */ + #define R_XSPI0_LPCTL0_PATREQ_Pos (0UL) /*!< PATREQ (Bit 0) */ + #define R_XSPI0_LPCTL0_PATREQ_Msk (0x1UL) /*!< PATREQ (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL0_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */ + #define R_XSPI0_LPCTL0_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL0_XDPIN_Pos (4UL) /*!< XDPIN (Bit 4) */ + #define R_XSPI0_LPCTL0_XDPIN_Msk (0x30UL) /*!< XDPIN (Bitfield-Mask: 0x03) */ + #define R_XSPI0_LPCTL0_XD1LEN_Pos (16UL) /*!< XD1LEN (Bit 16) */ + #define R_XSPI0_LPCTL0_XD1LEN_Msk (0x1f0000UL) /*!< XD1LEN (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_LPCTL0_XD1VAL_Pos (23UL) /*!< XD1VAL (Bit 23) */ + #define R_XSPI0_LPCTL0_XD1VAL_Msk (0x800000UL) /*!< XD1VAL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL0_XD2LEN_Pos (24UL) /*!< XD2LEN (Bit 24) */ + #define R_XSPI0_LPCTL0_XD2LEN_Msk (0x1f000000UL) /*!< XD2LEN (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_LPCTL0_XD2VAL_Pos (31UL) /*!< XD2VAL (Bit 31) */ + #define R_XSPI0_LPCTL0_XD2VAL_Msk (0x80000000UL) /*!< XD2VAL (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTL1 ========================================================= */ + #define R_XSPI0_LPCTL1_PATREQ_Pos (0UL) /*!< PATREQ (Bit 0) */ + #define R_XSPI0_LPCTL1_PATREQ_Msk (0x3UL) /*!< PATREQ (Bitfield-Mask: 0x03) */ + #define R_XSPI0_LPCTL1_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */ + #define R_XSPI0_LPCTL1_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL1_RSTREP_Pos (4UL) /*!< RSTREP (Bit 4) */ + #define R_XSPI0_LPCTL1_RSTREP_Msk (0x30UL) /*!< RSTREP (Bitfield-Mask: 0x03) */ + #define R_XSPI0_LPCTL1_RSTWID_Pos (8UL) /*!< RSTWID (Bit 8) */ + #define R_XSPI0_LPCTL1_RSTWID_Msk (0x700UL) /*!< RSTWID (Bitfield-Mask: 0x07) */ + #define R_XSPI0_LPCTL1_RSTSU_Pos (12UL) /*!< RSTSU (Bit 12) */ + #define R_XSPI0_LPCTL1_RSTSU_Msk (0x7000UL) /*!< RSTSU (Bitfield-Mask: 0x07) */ +/* ======================================================== LIOCTL ========================================================= */ + #define R_XSPI0_LIOCTL_WPCS_Pos (0UL) /*!< WPCS (Bit 0) */ + #define R_XSPI0_LIOCTL_WPCS_Msk (0x1UL) /*!< WPCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCTL_RSTCS_Pos (16UL) /*!< RSTCS (Bit 16) */ + #define R_XSPI0_LIOCTL_RSTCS_Msk (0x10000UL) /*!< RSTCS (Bitfield-Mask: 0x01) */ +/* ======================================================== VERSTT ========================================================= */ + #define R_XSPI0_VERSTT_VER_Pos (0UL) /*!< VER (Bit 0) */ + #define R_XSPI0_VERSTT_VER_Msk (0xffffffffUL) /*!< VER (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== COMSTT ========================================================= */ + #define R_XSPI0_COMSTT_MEMACCCH_Pos (0UL) /*!< MEMACCCH (Bit 0) */ + #define R_XSPI0_COMSTT_MEMACCCH_Msk (0x1UL) /*!< MEMACCCH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_PBUFNECH_Pos (4UL) /*!< PBUFNECH (Bit 4) */ + #define R_XSPI0_COMSTT_PBUFNECH_Msk (0x10UL) /*!< PBUFNECH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_WRBUFNECH_Pos (6UL) /*!< WRBUFNECH (Bit 6) */ + #define R_XSPI0_COMSTT_WRBUFNECH_Msk (0x40UL) /*!< WRBUFNECH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_ECSCS_Pos (16UL) /*!< ECSCS (Bit 16) */ + #define R_XSPI0_COMSTT_ECSCS_Msk (0x10000UL) /*!< ECSCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_INTCS_Pos (17UL) /*!< INTCS (Bit 17) */ + #define R_XSPI0_COMSTT_INTCS_Msk (0x20000UL) /*!< INTCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_RSTOCS_Pos (18UL) /*!< RSTOCS (Bit 18) */ + #define R_XSPI0_COMSTT_RSTOCS_Msk (0x40000UL) /*!< RSTOCS (Bitfield-Mask: 0x01) */ +/* ======================================================== CASTTCS ======================================================== */ + #define R_XSPI0_CASTTCS_CASUC_Pos (0UL) /*!< CASUC (Bit 0) */ + #define R_XSPI0_CASTTCS_CASUC_Msk (0xffffffffUL) /*!< CASUC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= INTS ========================================================== */ + #define R_XSPI0_INTS_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ + #define R_XSPI0_INTS_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_PATCMP_Pos (1UL) /*!< PATCMP (Bit 1) */ + #define R_XSPI0_INTS_PATCMP_Msk (0x2UL) /*!< PATCMP (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_INICMP_Pos (2UL) /*!< INICMP (Bit 2) */ + #define R_XSPI0_INTS_INICMP_Msk (0x4UL) /*!< INICMP (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_PERTO_Pos (3UL) /*!< PERTO (Bit 3) */ + #define R_XSPI0_INTS_PERTO_Msk (0x8UL) /*!< PERTO (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_DSTOCS_Pos (4UL) /*!< DSTOCS (Bit 4) */ + #define R_XSPI0_INTS_DSTOCS_Msk (0x10UL) /*!< DSTOCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_ECSCS_Pos (8UL) /*!< ECSCS (Bit 8) */ + #define R_XSPI0_INTS_ECSCS_Msk (0x100UL) /*!< ECSCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_INTCS_Pos (12UL) /*!< INTCS (Bit 12) */ + #define R_XSPI0_INTS_INTCS_Msk (0x1000UL) /*!< INTCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_BRGOFCH_Pos (16UL) /*!< BRGOFCH (Bit 16) */ + #define R_XSPI0_INTS_BRGOFCH_Msk (0x10000UL) /*!< BRGOFCH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_BRGUFCH_Pos (18UL) /*!< BRGUFCH (Bit 18) */ + #define R_XSPI0_INTS_BRGUFCH_Msk (0x40000UL) /*!< BRGUFCH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_BUSERRCH_Pos (20UL) /*!< BUSERRCH (Bit 20) */ + #define R_XSPI0_INTS_BUSERRCH_Msk (0x100000UL) /*!< BUSERRCH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_CAFAILCS_Pos (28UL) /*!< CAFAILCS (Bit 28) */ + #define R_XSPI0_INTS_CAFAILCS_Msk (0x10000000UL) /*!< CAFAILCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_CASUCCS_Pos (30UL) /*!< CASUCCS (Bit 30) */ + #define R_XSPI0_INTS_CASUCCS_Msk (0x40000000UL) /*!< CASUCCS (Bitfield-Mask: 0x01) */ +/* ========================================================= INTC ========================================================== */ + #define R_XSPI0_INTC_CMDCMPC_Pos (0UL) /*!< CMDCMPC (Bit 0) */ + #define R_XSPI0_INTC_CMDCMPC_Msk (0x1UL) /*!< CMDCMPC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_PATCMPC_Pos (1UL) /*!< PATCMPC (Bit 1) */ + #define R_XSPI0_INTC_PATCMPC_Msk (0x2UL) /*!< PATCMPC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_INICMPC_Pos (2UL) /*!< INICMPC (Bit 2) */ + #define R_XSPI0_INTC_INICMPC_Msk (0x4UL) /*!< INICMPC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_PERTOC_Pos (3UL) /*!< PERTOC (Bit 3) */ + #define R_XSPI0_INTC_PERTOC_Msk (0x8UL) /*!< PERTOC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_DSTOCSC_Pos (4UL) /*!< DSTOCSC (Bit 4) */ + #define R_XSPI0_INTC_DSTOCSC_Msk (0x10UL) /*!< DSTOCSC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_ECSCSC_Pos (8UL) /*!< ECSCSC (Bit 8) */ + #define R_XSPI0_INTC_ECSCSC_Msk (0x100UL) /*!< ECSCSC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_INTCSC_Pos (12UL) /*!< INTCSC (Bit 12) */ + #define R_XSPI0_INTC_INTCSC_Msk (0x1000UL) /*!< INTCSC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_BRGOFCHC_Pos (16UL) /*!< BRGOFCHC (Bit 16) */ + #define R_XSPI0_INTC_BRGOFCHC_Msk (0x10000UL) /*!< BRGOFCHC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_BRGUFCHC_Pos (18UL) /*!< BRGUFCHC (Bit 18) */ + #define R_XSPI0_INTC_BRGUFCHC_Msk (0x40000UL) /*!< BRGUFCHC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_BUSERRCHC_Pos (20UL) /*!< BUSERRCHC (Bit 20) */ + #define R_XSPI0_INTC_BUSERRCHC_Msk (0x100000UL) /*!< BUSERRCHC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_CAFAILCSC_Pos (28UL) /*!< CAFAILCSC (Bit 28) */ + #define R_XSPI0_INTC_CAFAILCSC_Msk (0x10000000UL) /*!< CAFAILCSC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_CASUCCSC_Pos (30UL) /*!< CASUCCSC (Bit 30) */ + #define R_XSPI0_INTC_CASUCCSC_Msk (0x40000000UL) /*!< CASUCCSC (Bitfield-Mask: 0x01) */ +/* ========================================================= INTE ========================================================== */ + #define R_XSPI0_INTE_CMDCMPE_Pos (0UL) /*!< CMDCMPE (Bit 0) */ + #define R_XSPI0_INTE_CMDCMPE_Msk (0x1UL) /*!< CMDCMPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_PATCMPE_Pos (1UL) /*!< PATCMPE (Bit 1) */ + #define R_XSPI0_INTE_PATCMPE_Msk (0x2UL) /*!< PATCMPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_INICMPE_Pos (2UL) /*!< INICMPE (Bit 2) */ + #define R_XSPI0_INTE_INICMPE_Msk (0x4UL) /*!< INICMPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_PERTOE_Pos (3UL) /*!< PERTOE (Bit 3) */ + #define R_XSPI0_INTE_PERTOE_Msk (0x8UL) /*!< PERTOE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_DSTOCSE_Pos (4UL) /*!< DSTOCSE (Bit 4) */ + #define R_XSPI0_INTE_DSTOCSE_Msk (0x10UL) /*!< DSTOCSE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_ECSCSE_Pos (8UL) /*!< ECSCSE (Bit 8) */ + #define R_XSPI0_INTE_ECSCSE_Msk (0x100UL) /*!< ECSCSE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_INTCSE_Pos (12UL) /*!< INTCSE (Bit 12) */ + #define R_XSPI0_INTE_INTCSE_Msk (0x1000UL) /*!< INTCSE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_BRGOFCHE_Pos (16UL) /*!< BRGOFCHE (Bit 16) */ + #define R_XSPI0_INTE_BRGOFCHE_Msk (0x10000UL) /*!< BRGOFCHE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_BRGUFCHE_Pos (18UL) /*!< BRGUFCHE (Bit 18) */ + #define R_XSPI0_INTE_BRGUFCHE_Msk (0x40000UL) /*!< BRGUFCHE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_BUSERRCHE_Pos (20UL) /*!< BUSERRCHE (Bit 20) */ + #define R_XSPI0_INTE_BUSERRCHE_Msk (0x100000UL) /*!< BUSERRCHE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_CAFAILCSE_Pos (28UL) /*!< CAFAILCSE (Bit 28) */ + #define R_XSPI0_INTE_CAFAILCSE_Msk (0x10000000UL) /*!< CAFAILCSE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_CASUCCSE_Pos (30UL) /*!< CASUCCSE (Bit 30) */ + #define R_XSPI0_INTE_CASUCCSE_Msk (0x40000000UL) /*!< CASUCCSE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MIPI_PHY ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= DPHYREFCR ======================================================= */ + #define R_MIPI_PHY_DPHYREFCR_RFREQ_Pos (0UL) /*!< RFREQ (Bit 0) */ + #define R_MIPI_PHY_DPHYREFCR_RFREQ_Msk (0xffUL) /*!< RFREQ (Bitfield-Mask: 0xff) */ +/* ======================================================= DPHYPLFCR ======================================================= */ + #define R_MIPI_PHY_DPHYPLFCR_IDIV_Pos (0UL) /*!< IDIV (Bit 0) */ + #define R_MIPI_PHY_DPHYPLFCR_IDIV_Msk (0x3UL) /*!< IDIV (Bitfield-Mask: 0x03) */ + #define R_MIPI_PHY_DPHYPLFCR_NFMUL_Pos (8UL) /*!< NFMUL (Bit 8) */ + #define R_MIPI_PHY_DPHYPLFCR_NFMUL_Msk (0x300UL) /*!< NFMUL (Bitfield-Mask: 0x03) */ + #define R_MIPI_PHY_DPHYPLFCR_PMUL_Pos (12UL) /*!< PMUL (Bit 12) */ + #define R_MIPI_PHY_DPHYPLFCR_PMUL_Msk (0x3000UL) /*!< PMUL (Bitfield-Mask: 0x03) */ + #define R_MIPI_PHY_DPHYPLFCR_NMUL_Pos (16UL) /*!< NMUL (Bit 16) */ + #define R_MIPI_PHY_DPHYPLFCR_NMUL_Msk (0x1ff0000UL) /*!< NMUL (Bitfield-Mask: 0x1ff) */ +/* ======================================================= DPHYPLOCR ======================================================= */ + #define R_MIPI_PHY_DPHYPLOCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_MIPI_PHY_DPHYPLOCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= DPHYESCCR ======================================================= */ + #define R_MIPI_PHY_DPHYESCCR_ESCDIV_Pos (0UL) /*!< ESCDIV (Bit 0) */ + #define R_MIPI_PHY_DPHYESCCR_ESCDIV_Msk (0x1fUL) /*!< ESCDIV (Bitfield-Mask: 0x1f) */ +/* ======================================================= DPHYPWRCR ======================================================= */ + #define R_MIPI_PHY_DPHYPWRCR_PWRSEN_Pos (0UL) /*!< PWRSEN (Bit 0) */ + #define R_MIPI_PHY_DPHYPWRCR_PWRSEN_Msk (0x1UL) /*!< PWRSEN (Bitfield-Mask: 0x01) */ +/* ======================================================== DPHYSFR ======================================================== */ + #define R_MIPI_PHY_DPHYSFR_PWRSF_Pos (0UL) /*!< PWRSF (Bit 0) */ + #define R_MIPI_PHY_DPHYSFR_PWRSF_Msk (0x1UL) /*!< PWRSF (Bitfield-Mask: 0x01) */ + #define R_MIPI_PHY_DPHYSFR_PLLSF_Pos (8UL) /*!< PLLSF (Bit 8) */ + #define R_MIPI_PHY_DPHYSFR_PLLSF_Msk (0x100UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPHYOCR ======================================================== */ + #define R_MIPI_PHY_DPHYOCR_DPHYEN_Pos (0UL) /*!< DPHYEN (Bit 0) */ + #define R_MIPI_PHY_DPHYOCR_DPHYEN_Msk (0x1UL) /*!< DPHYEN (Bitfield-Mask: 0x01) */ +/* ======================================================= DPHYTIM1 ======================================================== */ + #define R_MIPI_PHY_DPHYTIM1_TINIT_Pos (0UL) /*!< TINIT (Bit 0) */ + #define R_MIPI_PHY_DPHYTIM1_TINIT_Msk (0x7ffffUL) /*!< TINIT (Bitfield-Mask: 0x7ffff) */ +/* ======================================================= DPHYTIM2 ======================================================== */ + #define R_MIPI_PHY_DPHYTIM2_TCLKPREP_Pos (0UL) /*!< TCLKPREP (Bit 0) */ + #define R_MIPI_PHY_DPHYTIM2_TCLKPREP_Msk (0xffUL) /*!< TCLKPREP (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM2_TCLKSETT_Pos (8UL) /*!< TCLKSETT (Bit 8) */ + #define R_MIPI_PHY_DPHYTIM2_TCLKSETT_Msk (0xff00UL) /*!< TCLKSETT (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM2_TCLKMISS_Pos (16UL) /*!< TCLKMISS (Bit 16) */ + #define R_MIPI_PHY_DPHYTIM2_TCLKMISS_Msk (0xff0000UL) /*!< TCLKMISS (Bitfield-Mask: 0xff) */ +/* ======================================================= DPHYTIM3 ======================================================== */ + #define R_MIPI_PHY_DPHYTIM3_THSPREP_Pos (0UL) /*!< THSPREP (Bit 0) */ + #define R_MIPI_PHY_DPHYTIM3_THSPREP_Msk (0xffUL) /*!< THSPREP (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM3_THSSETT_Pos (8UL) /*!< THSSETT (Bit 8) */ + #define R_MIPI_PHY_DPHYTIM3_THSSETT_Msk (0xff00UL) /*!< THSSETT (Bitfield-Mask: 0xff) */ +/* ======================================================= DPHYTIM4 ======================================================== */ + #define R_MIPI_PHY_DPHYTIM4_TCLKZERO_Pos (0UL) /*!< TCLKZERO (Bit 0) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKZERO_Msk (0xffUL) /*!< TCLKZERO (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKPRE_Pos (8UL) /*!< TCLKPRE (Bit 8) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKPRE_Msk (0xff00UL) /*!< TCLKPRE (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKPOST_Pos (16UL) /*!< TCLKPOST (Bit 16) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKPOST_Msk (0xff0000UL) /*!< TCLKPOST (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKTRL_Pos (24UL) /*!< TCLKTRL (Bit 24) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKTRL_Msk (0xff000000UL) /*!< TCLKTRL (Bitfield-Mask: 0xff) */ +/* ======================================================= DPHYTIM5 ======================================================== */ + #define R_MIPI_PHY_DPHYTIM5_THSZERO_Pos (0UL) /*!< THSZERO (Bit 0) */ + #define R_MIPI_PHY_DPHYTIM5_THSZERO_Msk (0xffUL) /*!< THSZERO (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM5_THSTRL_Pos (8UL) /*!< THSTRL (Bit 8) */ + #define R_MIPI_PHY_DPHYTIM5_THSTRL_Msk (0xff00UL) /*!< THSTRL (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM5_THSEXIT_Pos (16UL) /*!< THSEXIT (Bit 16) */ + #define R_MIPI_PHY_DPHYTIM5_THSEXIT_Msk (0xff0000UL) /*!< THSEXIT (Bitfield-Mask: 0xff) */ +/* ======================================================= DPHYTIM6 ======================================================== */ + #define R_MIPI_PHY_DPHYTIM6_TLPX_Pos (0UL) /*!< TLPX (Bit 0) */ + #define R_MIPI_PHY_DPHYTIM6_TLPX_Msk (0xffUL) /*!< TLPX (Bitfield-Mask: 0xff) */ +/* ======================================================== DPHYMDC ======================================================== */ + #define R_MIPI_PHY_DPHYMDC_MASTEREN_Pos (0UL) /*!< MASTEREN (Bit 0) */ + #define R_MIPI_PHY_DPHYMDC_MASTEREN_Msk (0x1UL) /*!< MASTEREN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MIPI_CSI ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MCG ========================================================== */ + #define R_MIPI_CSI_MCG_VER_Pos (0UL) /*!< VER (Bit 0) */ + #define R_MIPI_CSI_MCG_VER_Msk (0xfUL) /*!< VER (Bitfield-Mask: 0x0f) */ + #define R_MIPI_CSI_MCG_SDLN_Pos (8UL) /*!< SDLN (Bit 8) */ + #define R_MIPI_CSI_MCG_SDLN_Msk (0xf00UL) /*!< SDLN (Bitfield-Mask: 0x0f) */ + #define R_MIPI_CSI_MCG_GSNM_Pos (16UL) /*!< GSNM (Bit 16) */ + #define R_MIPI_CSI_MCG_GSNM_Msk (0xff0000UL) /*!< GSNM (Bitfield-Mask: 0xff) */ +/* ========================================================= MCT0 ========================================================== */ + #define R_MIPI_CSI_MCT0_VDLN_Pos (0UL) /*!< VDLN (Bit 0) */ + #define R_MIPI_CSI_MCT0_VDLN_Msk (0xfUL) /*!< VDLN (Bitfield-Mask: 0x0f) */ + #define R_MIPI_CSI_MCT0_ZLMD_Pos (16UL) /*!< ZLMD (Bit 16) */ + #define R_MIPI_CSI_MCT0_ZLMD_Msk (0x10000UL) /*!< ZLMD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MCT0_EDMD_Pos (17UL) /*!< EDMD (Bit 17) */ + #define R_MIPI_CSI_MCT0_EDMD_Msk (0x20000UL) /*!< EDMD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MCT0_RVMD_Pos (19UL) /*!< RVMD (Bit 19) */ + #define R_MIPI_CSI_MCT0_RVMD_Msk (0x80000UL) /*!< RVMD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MCT0_GRMD_Pos (20UL) /*!< GRMD (Bit 20) */ + #define R_MIPI_CSI_MCT0_GRMD_Msk (0x100000UL) /*!< GRMD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MCT0_ECCV13_Pos (24UL) /*!< ECCV13 (Bit 24) */ + #define R_MIPI_CSI_MCT0_ECCV13_Msk (0x1000000UL) /*!< ECCV13 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MCT0_LFSREN_Pos (25UL) /*!< LFSREN (Bit 25) */ + #define R_MIPI_CSI_MCT0_LFSREN_Msk (0x2000000UL) /*!< LFSREN (Bitfield-Mask: 0x01) */ +/* ========================================================= MCT2 ========================================================== */ + #define R_MIPI_CSI_MCT2_FRRCLK_Pos (0UL) /*!< FRRCLK (Bit 0) */ + #define R_MIPI_CSI_MCT2_FRRCLK_Msk (0x1ffUL) /*!< FRRCLK (Bitfield-Mask: 0x1ff) */ + #define R_MIPI_CSI_MCT2_FRRSKW_Pos (16UL) /*!< FRRSKW (Bit 16) */ + #define R_MIPI_CSI_MCT2_FRRSKW_Msk (0x1ff0000UL) /*!< FRRSKW (Bitfield-Mask: 0x1ff) */ +/* ========================================================= MCT3 ========================================================== */ + #define R_MIPI_CSI_MCT3_RXEN_Pos (0UL) /*!< RXEN (Bit 0) */ + #define R_MIPI_CSI_MCT3_RXEN_Msk (0x1UL) /*!< RXEN (Bitfield-Mask: 0x01) */ +/* ========================================================= RTCT ========================================================== */ + #define R_MIPI_CSI_RTCT_VSRST_Pos (0UL) /*!< VSRST (Bit 0) */ + #define R_MIPI_CSI_RTCT_VSRST_Msk (0x1UL) /*!< VSRST (Bitfield-Mask: 0x01) */ +/* ========================================================= RTST ========================================================== */ + #define R_MIPI_CSI_RTST_VSRSTS_Pos (0UL) /*!< VSRSTS (Bit 0) */ + #define R_MIPI_CSI_RTST_VSRSTS_Msk (0x1UL) /*!< VSRSTS (Bitfield-Mask: 0x01) */ +/* ========================================================= EPCT ========================================================== */ + #define R_MIPI_CSI_EPCT_SLP_Pos (0UL) /*!< SLP (Bit 0) */ + #define R_MIPI_CSI_EPCT_SLP_Msk (0x7fffUL) /*!< SLP (Bitfield-Mask: 0x7fff) */ + #define R_MIPI_CSI_EPCT_EPDOP_Pos (15UL) /*!< EPDOP (Bit 15) */ + #define R_MIPI_CSI_EPCT_EPDOP_Msk (0x8000UL) /*!< EPDOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_EPCT_SSP_Pos (16UL) /*!< SSP (Bit 16) */ + #define R_MIPI_CSI_EPCT_SSP_Msk (0x7fff0000UL) /*!< SSP (Bitfield-Mask: 0x7fff) */ + #define R_MIPI_CSI_EPCT_EPDEN_Pos (31UL) /*!< EPDEN (Bit 31) */ + #define R_MIPI_CSI_EPCT_EPDEN_Msk (0x80000000UL) /*!< EPDEN (Bitfield-Mask: 0x01) */ +/* ========================================================= EMCT ========================================================== */ + #define R_MIPI_CSI_EMCT_VLSIEN_Pos (4UL) /*!< VLSIEN (Bit 4) */ + #define R_MIPI_CSI_EMCT_VLSIEN_Msk (0x30UL) /*!< VLSIEN (Bitfield-Mask: 0x03) */ + #define R_MIPI_CSI_EMCT_EOTPEN_Pos (6UL) /*!< EOTPEN (Bit 6) */ + #define R_MIPI_CSI_EMCT_EOTPEN_Msk (0x40UL) /*!< EOTPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= MIST ========================================================== */ + #define R_MIPI_CSI_MIST_DL0S_Pos (0UL) /*!< DL0S (Bit 0) */ + #define R_MIPI_CSI_MIST_DL0S_Msk (0x1UL) /*!< DL0S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_DL1S_Pos (1UL) /*!< DL1S (Bit 1) */ + #define R_MIPI_CSI_MIST_DL1S_Msk (0x2UL) /*!< DL1S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_PMS_Pos (8UL) /*!< PMS (Bit 8) */ + #define R_MIPI_CSI_MIST_PMS_Msk (0x100UL) /*!< PMS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_GSTS_Pos (9UL) /*!< GSTS (Bit 9) */ + #define R_MIPI_CSI_MIST_GSTS_Msk (0x200UL) /*!< GSTS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_RXS_Pos (10UL) /*!< RXS (Bit 10) */ + #define R_MIPI_CSI_MIST_RXS_Msk (0x400UL) /*!< RXS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC0S_Pos (16UL) /*!< VC0S (Bit 16) */ + #define R_MIPI_CSI_MIST_VC0S_Msk (0x10000UL) /*!< VC0S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC1S_Pos (17UL) /*!< VC1S (Bit 17) */ + #define R_MIPI_CSI_MIST_VC1S_Msk (0x20000UL) /*!< VC1S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC2S_Pos (18UL) /*!< VC2S (Bit 18) */ + #define R_MIPI_CSI_MIST_VC2S_Msk (0x40000UL) /*!< VC2S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC3S_Pos (19UL) /*!< VC3S (Bit 19) */ + #define R_MIPI_CSI_MIST_VC3S_Msk (0x80000UL) /*!< VC3S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC4S_Pos (20UL) /*!< VC4S (Bit 20) */ + #define R_MIPI_CSI_MIST_VC4S_Msk (0x100000UL) /*!< VC4S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC5S_Pos (21UL) /*!< VC5S (Bit 21) */ + #define R_MIPI_CSI_MIST_VC5S_Msk (0x200000UL) /*!< VC5S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC6S_Pos (22UL) /*!< VC6S (Bit 22) */ + #define R_MIPI_CSI_MIST_VC6S_Msk (0x400000UL) /*!< VC6S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC7S_Pos (23UL) /*!< VC7S (Bit 23) */ + #define R_MIPI_CSI_MIST_VC7S_Msk (0x800000UL) /*!< VC7S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC8S_Pos (24UL) /*!< VC8S (Bit 24) */ + #define R_MIPI_CSI_MIST_VC8S_Msk (0x1000000UL) /*!< VC8S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC9S_Pos (25UL) /*!< VC9S (Bit 25) */ + #define R_MIPI_CSI_MIST_VC9S_Msk (0x2000000UL) /*!< VC9S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC10S_Pos (26UL) /*!< VC10S (Bit 26) */ + #define R_MIPI_CSI_MIST_VC10S_Msk (0x4000000UL) /*!< VC10S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC11S_Pos (27UL) /*!< VC11S (Bit 27) */ + #define R_MIPI_CSI_MIST_VC11S_Msk (0x8000000UL) /*!< VC11S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC12S_Pos (28UL) /*!< VC12S (Bit 28) */ + #define R_MIPI_CSI_MIST_VC12S_Msk (0x10000000UL) /*!< VC12S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC13S_Pos (29UL) /*!< VC13S (Bit 29) */ + #define R_MIPI_CSI_MIST_VC13S_Msk (0x20000000UL) /*!< VC13S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC14S_Pos (30UL) /*!< VC14S (Bit 30) */ + #define R_MIPI_CSI_MIST_VC14S_Msk (0x40000000UL) /*!< VC14S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC15S_Pos (31UL) /*!< VC15S (Bit 31) */ + #define R_MIPI_CSI_MIST_VC15S_Msk (0x80000000UL) /*!< VC15S (Bitfield-Mask: 0x01) */ +/* ========================================================= DTEL ========================================================== */ + #define R_MIPI_CSI_DTEL_DTEN_Pos (0UL) /*!< DTEN (Bit 0) */ + #define R_MIPI_CSI_DTEL_DTEN_Msk (0xffffffffUL) /*!< DTEN (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTEH ========================================================== */ + #define R_MIPI_CSI_DTEH_DTEN_Pos (0UL) /*!< DTEN (Bit 0) */ + #define R_MIPI_CSI_DTEH_DTEN_Msk (0xffffffffUL) /*!< DTEN (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RXST ========================================================== */ + #define R_MIPI_CSI_RXST_FRM0_Pos (0UL) /*!< FRM0 (Bit 0) */ + #define R_MIPI_CSI_RXST_FRM0_Msk (0x1UL) /*!< FRM0 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM1_Pos (1UL) /*!< FRM1 (Bit 1) */ + #define R_MIPI_CSI_RXST_FRM1_Msk (0x2UL) /*!< FRM1 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM2_Pos (2UL) /*!< FRM2 (Bit 2) */ + #define R_MIPI_CSI_RXST_FRM2_Msk (0x4UL) /*!< FRM2 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM3_Pos (3UL) /*!< FRM3 (Bit 3) */ + #define R_MIPI_CSI_RXST_FRM3_Msk (0x8UL) /*!< FRM3 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM4_Pos (4UL) /*!< FRM4 (Bit 4) */ + #define R_MIPI_CSI_RXST_FRM4_Msk (0x10UL) /*!< FRM4 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM5_Pos (5UL) /*!< FRM5 (Bit 5) */ + #define R_MIPI_CSI_RXST_FRM5_Msk (0x20UL) /*!< FRM5 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM6_Pos (6UL) /*!< FRM6 (Bit 6) */ + #define R_MIPI_CSI_RXST_FRM6_Msk (0x40UL) /*!< FRM6 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM7_Pos (7UL) /*!< FRM7 (Bit 7) */ + #define R_MIPI_CSI_RXST_FRM7_Msk (0x80UL) /*!< FRM7 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM8_Pos (8UL) /*!< FRM8 (Bit 8) */ + #define R_MIPI_CSI_RXST_FRM8_Msk (0x100UL) /*!< FRM8 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM9_Pos (9UL) /*!< FRM9 (Bit 9) */ + #define R_MIPI_CSI_RXST_FRM9_Msk (0x200UL) /*!< FRM9 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM10_Pos (10UL) /*!< FRM10 (Bit 10) */ + #define R_MIPI_CSI_RXST_FRM10_Msk (0x400UL) /*!< FRM10 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM11_Pos (11UL) /*!< FRM11 (Bit 11) */ + #define R_MIPI_CSI_RXST_FRM11_Msk (0x800UL) /*!< FRM11 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM12_Pos (12UL) /*!< FRM12 (Bit 12) */ + #define R_MIPI_CSI_RXST_FRM12_Msk (0x1000UL) /*!< FRM12 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM13_Pos (13UL) /*!< FRM13 (Bit 13) */ + #define R_MIPI_CSI_RXST_FRM13_Msk (0x2000UL) /*!< FRM13 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM14_Pos (14UL) /*!< FRM14 (Bit 14) */ + #define R_MIPI_CSI_RXST_FRM14_Msk (0x4000UL) /*!< FRM14 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM15_Pos (15UL) /*!< FRM15 (Bit 15) */ + #define R_MIPI_CSI_RXST_FRM15_Msk (0x8000UL) /*!< FRM15 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_RACT_Pos (16UL) /*!< RACT (Bit 16) */ + #define R_MIPI_CSI_RXST_RACT_Msk (0x10000UL) /*!< RACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_RACTDET_Pos (17UL) /*!< RACTDET (Bit 17) */ + #define R_MIPI_CSI_RXST_RACTDET_Msk (0x20000UL) /*!< RACTDET (Bitfield-Mask: 0x01) */ +/* ========================================================= RXSC ========================================================== */ + #define R_MIPI_CSI_RXSC_RACTDETC_Pos (17UL) /*!< RACTDETC (Bit 17) */ + #define R_MIPI_CSI_RXSC_RACTDETC_Msk (0x20000UL) /*!< RACTDETC (Bitfield-Mask: 0x01) */ +/* ========================================================= RXIE ========================================================== */ + #define R_MIPI_CSI_RXIE_RACTDETE_Pos (17UL) /*!< RACTDETE (Bit 17) */ + #define R_MIPI_CSI_RXIE_RACTDETE_Msk (0x20000UL) /*!< RACTDETE (Bitfield-Mask: 0x01) */ +/* ========================================================= DLST0 ========================================================= */ + #define R_MIPI_CSI_DLST0_ESH_Pos (0UL) /*!< ESH (Bit 0) */ + #define R_MIPI_CSI_DLST0_ESH_Msk (0x1UL) /*!< ESH (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST0_ESS_Pos (1UL) /*!< ESS (Bit 1) */ + #define R_MIPI_CSI_DLST0_ESS_Msk (0x2UL) /*!< ESS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST0_ECT_Pos (2UL) /*!< ECT (Bit 2) */ + #define R_MIPI_CSI_DLST0_ECT_Msk (0x4UL) /*!< ECT (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST0_EES_Pos (3UL) /*!< EES (Bit 3) */ + #define R_MIPI_CSI_DLST0_EES_Msk (0x8UL) /*!< EES (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST0_EUL_Pos (16UL) /*!< EUL (Bit 16) */ + #define R_MIPI_CSI_DLST0_EUL_Msk (0x10000UL) /*!< EUL (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST0_RUL_Pos (17UL) /*!< RUL (Bit 17) */ + #define R_MIPI_CSI_DLST0_RUL_Msk (0x20000UL) /*!< RUL (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST0_ULP_Pos (24UL) /*!< ULP (Bit 24) */ + #define R_MIPI_CSI_DLST0_ULP_Msk (0x1000000UL) /*!< ULP (Bitfield-Mask: 0x01) */ +/* ========================================================= DLST1 ========================================================= */ + #define R_MIPI_CSI_DLST1_ESH_Pos (0UL) /*!< ESH (Bit 0) */ + #define R_MIPI_CSI_DLST1_ESH_Msk (0x1UL) /*!< ESH (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST1_ESS_Pos (1UL) /*!< ESS (Bit 1) */ + #define R_MIPI_CSI_DLST1_ESS_Msk (0x2UL) /*!< ESS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST1_ECT_Pos (2UL) /*!< ECT (Bit 2) */ + #define R_MIPI_CSI_DLST1_ECT_Msk (0x4UL) /*!< ECT (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST1_EES_Pos (3UL) /*!< EES (Bit 3) */ + #define R_MIPI_CSI_DLST1_EES_Msk (0x8UL) /*!< EES (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST1_EUL_Pos (16UL) /*!< EUL (Bit 16) */ + #define R_MIPI_CSI_DLST1_EUL_Msk (0x10000UL) /*!< EUL (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST1_RUL_Pos (17UL) /*!< RUL (Bit 17) */ + #define R_MIPI_CSI_DLST1_RUL_Msk (0x20000UL) /*!< RUL (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST1_ULP_Pos (24UL) /*!< ULP (Bit 24) */ + #define R_MIPI_CSI_DLST1_ULP_Msk (0x1000000UL) /*!< ULP (Bitfield-Mask: 0x01) */ +/* ========================================================= DLSC0 ========================================================= */ + #define R_MIPI_CSI_DLSC0_ESHC_Pos (0UL) /*!< ESHC (Bit 0) */ + #define R_MIPI_CSI_DLSC0_ESHC_Msk (0x1UL) /*!< ESHC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC0_ESSC_Pos (1UL) /*!< ESSC (Bit 1) */ + #define R_MIPI_CSI_DLSC0_ESSC_Msk (0x2UL) /*!< ESSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC0_ECTC_Pos (2UL) /*!< ECTC (Bit 2) */ + #define R_MIPI_CSI_DLSC0_ECTC_Msk (0x4UL) /*!< ECTC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC0_EESC_Pos (3UL) /*!< EESC (Bit 3) */ + #define R_MIPI_CSI_DLSC0_EESC_Msk (0x8UL) /*!< EESC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC0_EULC_Pos (16UL) /*!< EULC (Bit 16) */ + #define R_MIPI_CSI_DLSC0_EULC_Msk (0x10000UL) /*!< EULC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC0_RULC_Pos (17UL) /*!< RULC (Bit 17) */ + #define R_MIPI_CSI_DLSC0_RULC_Msk (0x20000UL) /*!< RULC (Bitfield-Mask: 0x01) */ +/* ========================================================= DLSC1 ========================================================= */ + #define R_MIPI_CSI_DLSC1_ESHC_Pos (0UL) /*!< ESHC (Bit 0) */ + #define R_MIPI_CSI_DLSC1_ESHC_Msk (0x1UL) /*!< ESHC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC1_ESSC_Pos (1UL) /*!< ESSC (Bit 1) */ + #define R_MIPI_CSI_DLSC1_ESSC_Msk (0x2UL) /*!< ESSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC1_ECTC_Pos (2UL) /*!< ECTC (Bit 2) */ + #define R_MIPI_CSI_DLSC1_ECTC_Msk (0x4UL) /*!< ECTC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC1_EESC_Pos (3UL) /*!< EESC (Bit 3) */ + #define R_MIPI_CSI_DLSC1_EESC_Msk (0x8UL) /*!< EESC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC1_EULC_Pos (16UL) /*!< EULC (Bit 16) */ + #define R_MIPI_CSI_DLSC1_EULC_Msk (0x10000UL) /*!< EULC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC1_RULC_Pos (17UL) /*!< RULC (Bit 17) */ + #define R_MIPI_CSI_DLSC1_RULC_Msk (0x20000UL) /*!< RULC (Bitfield-Mask: 0x01) */ +/* ========================================================= DLIE0 ========================================================= */ + #define R_MIPI_CSI_DLIE0_ESHE_Pos (0UL) /*!< ESHE (Bit 0) */ + #define R_MIPI_CSI_DLIE0_ESHE_Msk (0x1UL) /*!< ESHE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE0_ESSE_Pos (1UL) /*!< ESSE (Bit 1) */ + #define R_MIPI_CSI_DLIE0_ESSE_Msk (0x2UL) /*!< ESSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE0_ECTE_Pos (2UL) /*!< ECTE (Bit 2) */ + #define R_MIPI_CSI_DLIE0_ECTE_Msk (0x4UL) /*!< ECTE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE0_EESE_Pos (3UL) /*!< EESE (Bit 3) */ + #define R_MIPI_CSI_DLIE0_EESE_Msk (0x8UL) /*!< EESE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE0_EULE_Pos (16UL) /*!< EULE (Bit 16) */ + #define R_MIPI_CSI_DLIE0_EULE_Msk (0x10000UL) /*!< EULE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE0_RULE_Pos (17UL) /*!< RULE (Bit 17) */ + #define R_MIPI_CSI_DLIE0_RULE_Msk (0x20000UL) /*!< RULE (Bitfield-Mask: 0x01) */ +/* ========================================================= DLIE1 ========================================================= */ + #define R_MIPI_CSI_DLIE1_ESHE_Pos (0UL) /*!< ESHE (Bit 0) */ + #define R_MIPI_CSI_DLIE1_ESHE_Msk (0x1UL) /*!< ESHE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE1_ESSE_Pos (1UL) /*!< ESSE (Bit 1) */ + #define R_MIPI_CSI_DLIE1_ESSE_Msk (0x2UL) /*!< ESSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE1_ECTE_Pos (2UL) /*!< ECTE (Bit 2) */ + #define R_MIPI_CSI_DLIE1_ECTE_Msk (0x4UL) /*!< ECTE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE1_EESE_Pos (3UL) /*!< EESE (Bit 3) */ + #define R_MIPI_CSI_DLIE1_EESE_Msk (0x8UL) /*!< EESE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE1_EULE_Pos (16UL) /*!< EULE (Bit 16) */ + #define R_MIPI_CSI_DLIE1_EULE_Msk (0x10000UL) /*!< EULE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE1_RULE_Pos (17UL) /*!< RULE (Bit 17) */ + #define R_MIPI_CSI_DLIE1_RULE_Msk (0x20000UL) /*!< RULE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST0 ========================================================= */ + #define R_MIPI_CSI_VCST0_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST0_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST0_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST0_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST0_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST0_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST0_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST0_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST0_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST0_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST0_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST0_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST0_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST0_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST0_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST0_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST1 ========================================================= */ + #define R_MIPI_CSI_VCST1_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST1_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST1_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST1_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST1_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST1_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST1_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST1_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST1_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST1_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST1_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST1_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST1_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST1_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST1_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST1_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST2 ========================================================= */ + #define R_MIPI_CSI_VCST2_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST2_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST2_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST2_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST2_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST2_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST2_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST2_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST2_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST2_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST2_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST2_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST2_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST2_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST2_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST2_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST3 ========================================================= */ + #define R_MIPI_CSI_VCST3_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST3_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST3_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST3_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST3_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST3_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST3_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST3_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST3_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST3_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST3_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST3_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST3_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST3_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST3_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST3_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST4 ========================================================= */ + #define R_MIPI_CSI_VCST4_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST4_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST4_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST4_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST4_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST4_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST4_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST4_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST4_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST4_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST4_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST4_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST4_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST4_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST4_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST4_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST5 ========================================================= */ + #define R_MIPI_CSI_VCST5_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST5_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST5_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST5_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST5_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST5_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST5_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST5_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST5_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST5_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST5_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST5_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST5_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST5_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST5_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST5_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST6 ========================================================= */ + #define R_MIPI_CSI_VCST6_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST6_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST6_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST6_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST6_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST6_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST6_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST6_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST6_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST6_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST6_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST6_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST6_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST6_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST6_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST6_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST7 ========================================================= */ + #define R_MIPI_CSI_VCST7_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST7_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST7_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST7_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST7_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST7_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST7_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST7_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST7_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST7_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST7_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST7_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST7_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST7_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST7_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST7_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST8 ========================================================= */ + #define R_MIPI_CSI_VCST8_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST8_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST8_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST8_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST8_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST8_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST8_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST8_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST8_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST8_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST8_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST8_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST8_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST8_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST8_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST8_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST9 ========================================================= */ + #define R_MIPI_CSI_VCST9_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST9_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST9_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST9_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST9_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST9_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST9_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST9_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST9_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST9_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST9_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST9_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST9_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST9_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST9_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST9_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ======================================================== VCST10 ========================================================= */ + #define R_MIPI_CSI_VCST10_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST10_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST10_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST10_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST10_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST10_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST10_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST10_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST10_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST10_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST10_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST10_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST10_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST10_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST10_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST10_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ======================================================== VCST11 ========================================================= */ + #define R_MIPI_CSI_VCST11_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST11_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST11_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST11_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST11_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST11_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST11_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST11_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST11_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST11_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST11_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST11_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST11_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST11_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST11_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST11_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ======================================================== VCST12 ========================================================= */ + #define R_MIPI_CSI_VCST12_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST12_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST12_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST12_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST12_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST12_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST12_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST12_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST12_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST12_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST12_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST12_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST12_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST12_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST12_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST12_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ======================================================== VCST13 ========================================================= */ + #define R_MIPI_CSI_VCST13_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST13_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST13_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST13_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST13_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST13_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST13_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST13_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST13_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST13_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST13_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST13_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST13_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST13_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST13_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST13_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ======================================================== VCST14 ========================================================= */ + #define R_MIPI_CSI_VCST14_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST14_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST14_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST14_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST14_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST14_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST14_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST14_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST14_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST14_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST14_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST14_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST14_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST14_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST14_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST14_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ======================================================== VCST15 ========================================================= */ + #define R_MIPI_CSI_VCST15_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST15_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST15_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST15_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST15_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST15_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST15_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST15_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST15_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST15_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST15_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST15_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST15_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST15_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST15_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST15_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC0 ========================================================= */ + #define R_MIPI_CSI_VCSC0_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC0_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC0_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC0_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC0_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC0_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC0_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC0_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC0_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC0_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC0_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC0_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC0_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC0_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC0_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC0_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC0_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC0_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC1 ========================================================= */ + #define R_MIPI_CSI_VCSC1_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC1_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC1_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC1_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC1_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC1_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC1_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC1_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC1_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC1_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC1_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC1_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC1_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC1_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC1_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC1_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC1_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC1_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC2 ========================================================= */ + #define R_MIPI_CSI_VCSC2_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC2_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC2_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC2_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC2_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC2_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC2_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC2_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC2_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC2_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC2_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC2_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC2_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC2_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC2_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC2_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC2_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC2_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC3 ========================================================= */ + #define R_MIPI_CSI_VCSC3_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC3_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC3_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC3_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC3_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC3_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC3_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC3_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC3_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC3_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC3_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC3_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC3_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC3_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC3_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC3_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC3_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC3_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC4 ========================================================= */ + #define R_MIPI_CSI_VCSC4_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC4_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC4_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC4_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC4_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC4_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC4_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC4_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC4_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC4_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC4_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC4_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC4_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC4_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC4_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC4_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC4_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC4_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC5 ========================================================= */ + #define R_MIPI_CSI_VCSC5_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC5_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC5_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC5_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC5_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC5_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC5_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC5_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC5_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC5_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC5_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC5_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC5_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC5_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC5_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC5_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC5_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC5_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC6 ========================================================= */ + #define R_MIPI_CSI_VCSC6_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC6_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC6_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC6_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC6_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC6_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC6_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC6_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC6_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC6_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC6_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC6_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC6_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC6_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC6_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC6_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC6_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC6_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC7 ========================================================= */ + #define R_MIPI_CSI_VCSC7_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC7_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC7_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC7_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC7_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC7_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC7_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC7_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC7_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC7_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC7_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC7_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC7_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC7_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC7_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC7_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC7_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC7_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC8 ========================================================= */ + #define R_MIPI_CSI_VCSC8_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC8_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC8_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC8_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC8_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC8_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC8_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC8_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC8_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC8_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC8_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC8_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC8_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC8_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC8_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC8_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC8_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC8_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC9 ========================================================= */ + #define R_MIPI_CSI_VCSC9_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC9_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC9_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC9_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC9_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC9_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC9_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC9_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC9_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC9_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC9_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC9_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC9_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC9_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC9_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC9_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC9_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC9_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ======================================================== VCSC10 ========================================================= */ + #define R_MIPI_CSI_VCSC10_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC10_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC10_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC10_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC10_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC10_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC10_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC10_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC10_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC10_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC10_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC10_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC10_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC10_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC10_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC10_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC10_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC10_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ======================================================== VCSC11 ========================================================= */ + #define R_MIPI_CSI_VCSC11_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC11_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC11_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC11_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC11_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC11_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC11_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC11_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC11_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC11_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC11_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC11_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC11_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC11_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC11_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC11_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC11_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC11_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ======================================================== VCSC12 ========================================================= */ + #define R_MIPI_CSI_VCSC12_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC12_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC12_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC12_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC12_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC12_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC12_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC12_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC12_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC12_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC12_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC12_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC12_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC12_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC12_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC12_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC12_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC12_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ======================================================== VCSC13 ========================================================= */ + #define R_MIPI_CSI_VCSC13_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC13_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC13_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC13_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC13_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC13_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC13_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC13_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC13_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC13_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC13_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC13_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC13_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC13_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC13_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC13_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC13_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC13_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ======================================================== VCSC14 ========================================================= */ + #define R_MIPI_CSI_VCSC14_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC14_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC14_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC14_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC14_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC14_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC14_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC14_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC14_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC14_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC14_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC14_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC14_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC14_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC14_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC14_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC14_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC14_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ======================================================== VCSC15 ========================================================= */ + #define R_MIPI_CSI_VCSC15_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC15_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC15_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC15_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC15_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC15_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC15_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC15_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC15_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC15_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC15_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC15_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC15_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC15_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC15_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC15_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC15_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC15_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE0 ========================================================= */ + #define R_MIPI_CSI_VCIE0_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE0_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE0_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE0_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE0_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE0_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE0_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE0_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE0_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE0_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE0_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE0_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE0_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE0_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE0_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE0_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE1 ========================================================= */ + #define R_MIPI_CSI_VCIE1_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE1_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE1_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE1_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE1_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE1_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE1_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE1_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE1_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE1_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE1_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE1_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE1_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE1_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE1_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE1_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE2 ========================================================= */ + #define R_MIPI_CSI_VCIE2_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE2_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE2_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE2_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE2_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE2_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE2_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE2_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE2_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE2_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE2_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE2_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE2_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE2_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE2_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE2_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE3 ========================================================= */ + #define R_MIPI_CSI_VCIE3_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE3_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE3_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE3_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE3_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE3_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE3_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE3_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE3_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE3_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE3_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE3_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE3_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE3_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE3_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE3_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE4 ========================================================= */ + #define R_MIPI_CSI_VCIE4_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE4_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE4_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE4_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE4_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE4_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE4_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE4_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE4_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE4_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE4_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE4_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE4_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE4_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE4_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE4_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE5 ========================================================= */ + #define R_MIPI_CSI_VCIE5_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE5_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE5_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE5_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE5_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE5_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE5_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE5_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE5_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE5_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE5_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE5_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE5_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE5_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE5_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE5_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE6 ========================================================= */ + #define R_MIPI_CSI_VCIE6_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE6_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE6_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE6_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE6_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE6_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE6_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE6_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE6_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE6_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE6_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE6_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE6_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE6_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE6_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE6_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE7 ========================================================= */ + #define R_MIPI_CSI_VCIE7_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE7_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE7_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE7_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE7_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE7_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE7_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE7_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE7_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE7_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE7_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE7_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE7_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE7_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE7_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE7_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE8 ========================================================= */ + #define R_MIPI_CSI_VCIE8_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE8_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE8_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE8_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE8_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE8_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE8_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE8_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE8_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE8_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE8_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE8_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE8_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE8_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE8_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE8_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE9 ========================================================= */ + #define R_MIPI_CSI_VCIE9_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE9_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE9_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE9_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE9_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE9_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE9_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE9_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE9_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE9_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE9_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE9_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE9_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE9_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE9_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE9_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ======================================================== VCIE10 ========================================================= */ + #define R_MIPI_CSI_VCIE10_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE10_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE10_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE10_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE10_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE10_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE10_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE10_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE10_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE10_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE10_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE10_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE10_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE10_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE10_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE10_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ======================================================== VCIE11 ========================================================= */ + #define R_MIPI_CSI_VCIE11_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE11_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE11_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE11_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE11_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE11_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE11_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE11_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE11_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE11_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE11_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE11_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE11_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE11_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE11_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE11_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ======================================================== VCIE12 ========================================================= */ + #define R_MIPI_CSI_VCIE12_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE12_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE12_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE12_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE12_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE12_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE12_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE12_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE12_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE12_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE12_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE12_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE12_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE12_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE12_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE12_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ======================================================== VCIE13 ========================================================= */ + #define R_MIPI_CSI_VCIE13_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE13_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE13_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE13_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE13_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE13_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE13_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE13_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE13_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE13_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE13_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE13_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE13_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE13_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE13_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE13_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ======================================================== VCIE14 ========================================================= */ + #define R_MIPI_CSI_VCIE14_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE14_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE14_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE14_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE14_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE14_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE14_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE14_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE14_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE14_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE14_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE14_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE14_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE14_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE14_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE14_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ======================================================== VCIE15 ========================================================= */ + #define R_MIPI_CSI_VCIE15_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE15_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE15_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE15_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE15_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE15_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE15_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE15_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE15_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE15_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE15_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE15_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE15_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE15_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE15_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE15_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= PMST ========================================================== */ + #define R_MIPI_CSI_PMST_DSX_Pos (0UL) /*!< DSX (Bit 0) */ + #define R_MIPI_CSI_PMST_DSX_Msk (0x1UL) /*!< DSX (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_DSN_Pos (1UL) /*!< DSN (Bit 1) */ + #define R_MIPI_CSI_PMST_DSN_Msk (0x2UL) /*!< DSN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_CSX_Pos (2UL) /*!< CSX (Bit 2) */ + #define R_MIPI_CSI_PMST_CSX_Msk (0x4UL) /*!< CSX (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_CSN_Pos (3UL) /*!< CSN (Bit 3) */ + #define R_MIPI_CSI_PMST_CSN_Msk (0x8UL) /*!< CSN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_DUX_Pos (4UL) /*!< DUX (Bit 4) */ + #define R_MIPI_CSI_PMST_DUX_Msk (0x10UL) /*!< DUX (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_DUN_Pos (5UL) /*!< DUN (Bit 5) */ + #define R_MIPI_CSI_PMST_DUN_Msk (0x20UL) /*!< DUN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_CUX_Pos (6UL) /*!< CUX (Bit 6) */ + #define R_MIPI_CSI_PMST_CUX_Msk (0x40UL) /*!< CUX (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_CUN_Pos (7UL) /*!< CUN (Bit 7) */ + #define R_MIPI_CSI_PMST_CUN_Msk (0x80UL) /*!< CUN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_CLSS_Pos (14UL) /*!< CLSS (Bit 14) */ + #define R_MIPI_CSI_PMST_CLSS_Msk (0x4000UL) /*!< CLSS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_CLUL_Pos (15UL) /*!< CLUL (Bit 15) */ + #define R_MIPI_CSI_PMST_CLUL_Msk (0x8000UL) /*!< CLUL (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_DLSS_Pos (16UL) /*!< DLSS (Bit 16) */ + #define R_MIPI_CSI_PMST_DLSS_Msk (0x30000UL) /*!< DLSS (Bitfield-Mask: 0x03) */ + #define R_MIPI_CSI_PMST_DLUL_Pos (24UL) /*!< DLUL (Bit 24) */ + #define R_MIPI_CSI_PMST_DLUL_Msk (0x3000000UL) /*!< DLUL (Bitfield-Mask: 0x03) */ +/* ========================================================= PMSC ========================================================== */ + #define R_MIPI_CSI_PMSC_DSXC_Pos (0UL) /*!< DSXC (Bit 0) */ + #define R_MIPI_CSI_PMSC_DSXC_Msk (0x1UL) /*!< DSXC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMSC_DSNC_Pos (1UL) /*!< DSNC (Bit 1) */ + #define R_MIPI_CSI_PMSC_DSNC_Msk (0x2UL) /*!< DSNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMSC_CSXC_Pos (2UL) /*!< CSXC (Bit 2) */ + #define R_MIPI_CSI_PMSC_CSXC_Msk (0x4UL) /*!< CSXC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMSC_CSNC_Pos (3UL) /*!< CSNC (Bit 3) */ + #define R_MIPI_CSI_PMSC_CSNC_Msk (0x8UL) /*!< CSNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMSC_DUXC_Pos (4UL) /*!< DUXC (Bit 4) */ + #define R_MIPI_CSI_PMSC_DUXC_Msk (0x10UL) /*!< DUXC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMSC_DUNC_Pos (5UL) /*!< DUNC (Bit 5) */ + #define R_MIPI_CSI_PMSC_DUNC_Msk (0x20UL) /*!< DUNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMSC_CUXC_Pos (6UL) /*!< CUXC (Bit 6) */ + #define R_MIPI_CSI_PMSC_CUXC_Msk (0x40UL) /*!< CUXC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMSC_CUNC_Pos (7UL) /*!< CUNC (Bit 7) */ + #define R_MIPI_CSI_PMSC_CUNC_Msk (0x80UL) /*!< CUNC (Bitfield-Mask: 0x01) */ +/* ========================================================= PMIE ========================================================== */ + #define R_MIPI_CSI_PMIE_DSXE_Pos (0UL) /*!< DSXE (Bit 0) */ + #define R_MIPI_CSI_PMIE_DSXE_Msk (0x1UL) /*!< DSXE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMIE_DSNE_Pos (1UL) /*!< DSNE (Bit 1) */ + #define R_MIPI_CSI_PMIE_DSNE_Msk (0x2UL) /*!< DSNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMIE_CSXE_Pos (2UL) /*!< CSXE (Bit 2) */ + #define R_MIPI_CSI_PMIE_CSXE_Msk (0x4UL) /*!< CSXE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMIE_CSNE_Pos (3UL) /*!< CSNE (Bit 3) */ + #define R_MIPI_CSI_PMIE_CSNE_Msk (0x8UL) /*!< CSNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMIE_DUXE_Pos (4UL) /*!< DUXE (Bit 4) */ + #define R_MIPI_CSI_PMIE_DUXE_Msk (0x10UL) /*!< DUXE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMIE_DUNE_Pos (5UL) /*!< DUNE (Bit 5) */ + #define R_MIPI_CSI_PMIE_DUNE_Msk (0x20UL) /*!< DUNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMIE_CUXE_Pos (6UL) /*!< CUXE (Bit 6) */ + #define R_MIPI_CSI_PMIE_CUXE_Msk (0x40UL) /*!< CUXE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMIE_CUNE_Pos (7UL) /*!< CUNE (Bit 7) */ + #define R_MIPI_CSI_PMIE_CUNE_Msk (0x80UL) /*!< CUNE (Bitfield-Mask: 0x01) */ +/* ========================================================= GSCT ========================================================== */ + #define R_MIPI_CSI_GSCT_SHTH_Pos (0UL) /*!< SHTH (Bit 0) */ + #define R_MIPI_CSI_GSCT_SHTH_Msk (0x7fUL) /*!< SHTH (Bitfield-Mask: 0x7f) */ + #define R_MIPI_CSI_GSCT_GFIF_Pos (16UL) /*!< GFIF (Bit 16) */ + #define R_MIPI_CSI_GSCT_GFIF_Msk (0x10000UL) /*!< GFIF (Bitfield-Mask: 0x01) */ +/* ========================================================= GSST ========================================================== */ + #define R_MIPI_CSI_GSST_GNE_Pos (0UL) /*!< GNE (Bit 0) */ + #define R_MIPI_CSI_GSST_GNE_Msk (0x1UL) /*!< GNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSST_GTH_Pos (1UL) /*!< GTH (Bit 1) */ + #define R_MIPI_CSI_GSST_GTH_Msk (0x2UL) /*!< GTH (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSST_GOV_Pos (4UL) /*!< GOV (Bit 4) */ + #define R_MIPI_CSI_GSST_GOV_Msk (0x10UL) /*!< GOV (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSST_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_MIPI_CSI_GSST_PNUM_Msk (0xff00UL) /*!< PNUM (Bitfield-Mask: 0xff) */ + #define R_MIPI_CSI_GSST_GCD_Pos (16UL) /*!< GCD (Bit 16) */ + #define R_MIPI_CSI_GSST_GCD_Msk (0x10000UL) /*!< GCD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSST_STRDS_Pos (17UL) /*!< STRDS (Bit 17) */ + #define R_MIPI_CSI_GSST_STRDS_Msk (0x20000UL) /*!< STRDS (Bitfield-Mask: 0x01) */ +/* ========================================================= GSSC ========================================================== */ + #define R_MIPI_CSI_GSSC_GOVC_Pos (4UL) /*!< GOVC (Bit 4) */ + #define R_MIPI_CSI_GSSC_GOVC_Msk (0x10UL) /*!< GOVC (Bitfield-Mask: 0x01) */ +/* ========================================================= GSIE ========================================================== */ + #define R_MIPI_CSI_GSIE_GNEE_Pos (0UL) /*!< GNEE (Bit 0) */ + #define R_MIPI_CSI_GSIE_GNEE_Msk (0x1UL) /*!< GNEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSIE_GTHE_Pos (1UL) /*!< GTHE (Bit 1) */ + #define R_MIPI_CSI_GSIE_GTHE_Msk (0x2UL) /*!< GTHE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSIE_GOVE_Pos (4UL) /*!< GOVE (Bit 4) */ + #define R_MIPI_CSI_GSIE_GOVE_Msk (0x10UL) /*!< GOVE (Bitfield-Mask: 0x01) */ +/* ========================================================= GSHT ========================================================== */ + #define R_MIPI_CSI_GSHT_SPDT_Pos (0UL) /*!< SPDT (Bit 0) */ + #define R_MIPI_CSI_GSHT_SPDT_Msk (0xffffUL) /*!< SPDT (Bitfield-Mask: 0xffff) */ + #define R_MIPI_CSI_GSHT_DTYP_Pos (16UL) /*!< DTYP (Bit 16) */ + #define R_MIPI_CSI_GSHT_DTYP_Msk (0x3f0000UL) /*!< DTYP (Bitfield-Mask: 0x3f) */ + #define R_MIPI_CSI_GSHT_SPVC_Pos (24UL) /*!< SPVC (Bit 24) */ + #define R_MIPI_CSI_GSHT_SPVC_Msk (0xf000000UL) /*!< SPVC (Bitfield-Mask: 0x0f) */ +/* ========================================================= GSIU ========================================================== */ + #define R_MIPI_CSI_GSIU_FINC_Pos (0UL) /*!< FINC (Bit 0) */ + #define R_MIPI_CSI_GSIU_FINC_Msk (0x1UL) /*!< FINC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSIU_GFCLR_Pos (8UL) /*!< GFCLR (Bit 8) */ + #define R_MIPI_CSI_GSIU_GFCLR_Msk (0x100UL) /*!< GFCLR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSIU_GFEN_Pos (16UL) /*!< GFEN (Bit 16) */ + #define R_MIPI_CSI_GSIU_GFEN_Msk (0x10000UL) /*!< GFEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CEU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CAPSR ========================================================= */ + #define R_CEU_CAPSR_CE_Pos (0UL) /*!< CE (Bit 0) */ + #define R_CEU_CAPSR_CE_Msk (0x1UL) /*!< CE (Bitfield-Mask: 0x01) */ + #define R_CEU_CAPSR_CPKIL_Pos (16UL) /*!< CPKIL (Bit 16) */ + #define R_CEU_CAPSR_CPKIL_Msk (0x10000UL) /*!< CPKIL (Bitfield-Mask: 0x01) */ +/* ========================================================= CAPCR ========================================================= */ + #define R_CEU_CAPCR_CTNCP_Pos (16UL) /*!< CTNCP (Bit 16) */ + #define R_CEU_CAPCR_CTNCP_Msk (0x10000UL) /*!< CTNCP (Bitfield-Mask: 0x01) */ + #define R_CEU_CAPCR_MTCM_Pos (20UL) /*!< MTCM (Bit 20) */ + #define R_CEU_CAPCR_MTCM_Msk (0x300000UL) /*!< MTCM (Bitfield-Mask: 0x03) */ + #define R_CEU_CAPCR_FDRP_Pos (24UL) /*!< FDRP (Bit 24) */ + #define R_CEU_CAPCR_FDRP_Msk (0xff000000UL) /*!< FDRP (Bitfield-Mask: 0xff) */ +/* ========================================================= CAMCR ========================================================= */ + #define R_CEU_CAMCR_HDPOL_Pos (0UL) /*!< HDPOL (Bit 0) */ + #define R_CEU_CAMCR_HDPOL_Msk (0x1UL) /*!< HDPOL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_VDPOL_Pos (1UL) /*!< VDPOL (Bit 1) */ + #define R_CEU_CAMCR_VDPOL_Msk (0x2UL) /*!< VDPOL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_JPG_Pos (4UL) /*!< JPG (Bit 4) */ + #define R_CEU_CAMCR_JPG_Msk (0x30UL) /*!< JPG (Bitfield-Mask: 0x03) */ + #define R_CEU_CAMCR_DTARY_Pos (8UL) /*!< DTARY (Bit 8) */ + #define R_CEU_CAMCR_DTARY_Msk (0x300UL) /*!< DTARY (Bitfield-Mask: 0x03) */ + #define R_CEU_CAMCR_DTIF_Pos (12UL) /*!< DTIF (Bit 12) */ + #define R_CEU_CAMCR_DTIF_Msk (0x1000UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_FLDPOL_Pos (16UL) /*!< FLDPOL (Bit 16) */ + #define R_CEU_CAMCR_FLDPOL_Msk (0x10000UL) /*!< FLDPOL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_DSEL_Pos (24UL) /*!< DSEL (Bit 24) */ + #define R_CEU_CAMCR_DSEL_Msk (0x1000000UL) /*!< DSEL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_FLDSEL_Pos (25UL) /*!< FLDSEL (Bit 25) */ + #define R_CEU_CAMCR_FLDSEL_Msk (0x2000000UL) /*!< FLDSEL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_HDSEL_Pos (26UL) /*!< HDSEL (Bit 26) */ + #define R_CEU_CAMCR_HDSEL_Msk (0x4000000UL) /*!< HDSEL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_VDSEL_Pos (27UL) /*!< VDSEL (Bit 27) */ + #define R_CEU_CAMCR_VDSEL_Msk (0x8000000UL) /*!< VDSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= CMCYR ========================================================= */ + #define R_CEU_CMCYR_HCYL_Pos (0UL) /*!< HCYL (Bit 0) */ + #define R_CEU_CMCYR_HCYL_Msk (0x3fffUL) /*!< HCYL (Bitfield-Mask: 0x3fff) */ + #define R_CEU_CMCYR_VCYL_Pos (16UL) /*!< VCYL (Bit 16) */ + #define R_CEU_CMCYR_VCYL_Msk (0x3fff0000UL) /*!< VCYL (Bitfield-Mask: 0x3fff) */ +/* ========================================================= CAMOR ========================================================= */ + #define R_CEU_CAMOR_HOFST_Pos (0UL) /*!< HOFST (Bit 0) */ + #define R_CEU_CAMOR_HOFST_Msk (0x1fffUL) /*!< HOFST (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAMOR_VOFST_Pos (16UL) /*!< VOFST (Bit 16) */ + #define R_CEU_CAMOR_VOFST_Msk (0xfff0000UL) /*!< VOFST (Bitfield-Mask: 0xfff) */ +/* ========================================================= CAPWR ========================================================= */ + #define R_CEU_CAPWR_HWDTH_Pos (0UL) /*!< HWDTH (Bit 0) */ + #define R_CEU_CAPWR_HWDTH_Msk (0x1fffUL) /*!< HWDTH (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAPWR_VWDTH_Pos (16UL) /*!< VWDTH (Bit 16) */ + #define R_CEU_CAPWR_VWDTH_Msk (0xfff0000UL) /*!< VWDTH (Bitfield-Mask: 0xfff) */ +/* ========================================================= CAIFR ========================================================= */ + #define R_CEU_CAIFR_FCI_Pos (0UL) /*!< FCI (Bit 0) */ + #define R_CEU_CAIFR_FCI_Msk (0x3UL) /*!< FCI (Bitfield-Mask: 0x03) */ + #define R_CEU_CAIFR_CIM_Pos (4UL) /*!< CIM (Bit 4) */ + #define R_CEU_CAIFR_CIM_Msk (0x10UL) /*!< CIM (Bitfield-Mask: 0x01) */ + #define R_CEU_CAIFR_IFS_Pos (8UL) /*!< IFS (Bit 8) */ + #define R_CEU_CAIFR_IFS_Msk (0x100UL) /*!< IFS (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCNTR ========================================================= */ + #define R_CEU_CRCNTR_RC_Pos (0UL) /*!< RC (Bit 0) */ + #define R_CEU_CRCNTR_RC_Msk (0x1UL) /*!< RC (Bitfield-Mask: 0x01) */ + #define R_CEU_CRCNTR_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_CEU_CRCNTR_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_CEU_CRCNTR_RVS_Pos (4UL) /*!< RVS (Bit 4) */ + #define R_CEU_CRCNTR_RVS_Msk (0x10UL) /*!< RVS (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCMPR ========================================================= */ + #define R_CEU_CRCMPR_RA_Pos (0UL) /*!< RA (Bit 0) */ + #define R_CEU_CRCMPR_RA_Msk (0x1UL) /*!< RA (Bitfield-Mask: 0x01) */ +/* ========================================================= CFLCR ========================================================= */ + #define R_CEU_CFLCR_HFRAC_Pos (0UL) /*!< HFRAC (Bit 0) */ + #define R_CEU_CFLCR_HFRAC_Msk (0xfffUL) /*!< HFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_HMANT_Pos (12UL) /*!< HMANT (Bit 12) */ + #define R_CEU_CFLCR_HMANT_Msk (0xf000UL) /*!< HMANT (Bitfield-Mask: 0x0f) */ + #define R_CEU_CFLCR_VFRAC_Pos (16UL) /*!< VFRAC (Bit 16) */ + #define R_CEU_CFLCR_VFRAC_Msk (0xfff0000UL) /*!< VFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_VMANT_Pos (28UL) /*!< VMANT (Bit 28) */ + #define R_CEU_CFLCR_VMANT_Msk (0xf0000000UL) /*!< VMANT (Bitfield-Mask: 0x0f) */ +/* ========================================================= CFSZR ========================================================= */ + #define R_CEU_CFSZR_HFCLP_Pos (0UL) /*!< HFCLP (Bit 0) */ + #define R_CEU_CFSZR_HFCLP_Msk (0xfffUL) /*!< HFCLP (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFSZR_VFCLP_Pos (16UL) /*!< VFCLP (Bit 16) */ + #define R_CEU_CFSZR_VFCLP_Msk (0xfff0000UL) /*!< VFCLP (Bitfield-Mask: 0xfff) */ +/* ========================================================= CDWDR ========================================================= */ + #define R_CEU_CDWDR_CHDW_Pos (0UL) /*!< CHDW (Bit 0) */ + #define R_CEU_CDWDR_CHDW_Msk (0x1fffUL) /*!< CHDW (Bitfield-Mask: 0x1fff) */ +/* ========================================================= CDAYR ========================================================= */ + #define R_CEU_CDAYR_CAYR_Pos (0UL) /*!< CAYR (Bit 0) */ + #define R_CEU_CDAYR_CAYR_Msk (0xffffffffUL) /*!< CAYR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDACR ========================================================= */ + #define R_CEU_CDACR_CACR_Pos (0UL) /*!< CACR (Bit 0) */ + #define R_CEU_CDACR_CACR_Msk (0xffffffffUL) /*!< CACR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDBYR ========================================================= */ + #define R_CEU_CDBYR_CBYR_Pos (0UL) /*!< CBYR (Bit 0) */ + #define R_CEU_CDBYR_CBYR_Msk (0xffffffffUL) /*!< CBYR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDBCR ========================================================= */ + #define R_CEU_CDBCR_CBCR_Pos (0UL) /*!< CBCR (Bit 0) */ + #define R_CEU_CDBCR_CBCR_Msk (0xffffffffUL) /*!< CBCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CBDSR ========================================================= */ + #define R_CEU_CBDSR_CBVS_Pos (0UL) /*!< CBVS (Bit 0) */ + #define R_CEU_CBDSR_CBVS_Msk (0x7fffffUL) /*!< CBVS (Bitfield-Mask: 0x7fffff) */ +/* ========================================================= CFWCR ========================================================= */ + #define R_CEU_CFWCR_FWE_Pos (0UL) /*!< FWE (Bit 0) */ + #define R_CEU_CFWCR_FWE_Msk (0x1UL) /*!< FWE (Bitfield-Mask: 0x01) */ + #define R_CEU_CFWCR_FWV_Pos (5UL) /*!< FWV (Bit 5) */ + #define R_CEU_CFWCR_FWV_Msk (0xffffffe0UL) /*!< FWV (Bitfield-Mask: 0x7ffffff) */ +/* ========================================================= CLFCR ========================================================= */ + #define R_CEU_CLFCR_LPF_Pos (0UL) /*!< LPF (Bit 0) */ + #define R_CEU_CLFCR_LPF_Msk (0x1UL) /*!< LPF (Bitfield-Mask: 0x01) */ +/* ========================================================= CDOCR ========================================================= */ + #define R_CEU_CDOCR_COBS_Pos (0UL) /*!< COBS (Bit 0) */ + #define R_CEU_CDOCR_COBS_Msk (0x1UL) /*!< COBS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_COWS_Pos (1UL) /*!< COWS (Bit 1) */ + #define R_CEU_CDOCR_COWS_Msk (0x2UL) /*!< COWS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_COLS_Pos (2UL) /*!< COLS (Bit 2) */ + #define R_CEU_CDOCR_COLS_Msk (0x4UL) /*!< COLS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_CDS_Pos (4UL) /*!< CDS (Bit 4) */ + #define R_CEU_CDOCR_CDS_Msk (0x10UL) /*!< CDS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_CBE_Pos (16UL) /*!< CBE (Bit 16) */ + #define R_CEU_CDOCR_CBE_Msk (0x10000UL) /*!< CBE (Bitfield-Mask: 0x01) */ +/* ========================================================= CEIER ========================================================= */ + #define R_CEU_CEIER_CPEIE_Pos (0UL) /*!< CPEIE (Bit 0) */ + #define R_CEU_CEIER_CPEIE_Msk (0x1UL) /*!< CPEIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CFEIE_Pos (1UL) /*!< CFEIE (Bit 1) */ + #define R_CEU_CEIER_CFEIE_Msk (0x2UL) /*!< CFEIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_IGRWIE_Pos (4UL) /*!< IGRWIE (Bit 4) */ + #define R_CEU_CEIER_IGRWIE_Msk (0x10UL) /*!< IGRWIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_HDIE_Pos (8UL) /*!< HDIE (Bit 8) */ + #define R_CEU_CEIER_HDIE_Msk (0x100UL) /*!< HDIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_VDIE_Pos (9UL) /*!< VDIE (Bit 9) */ + #define R_CEU_CEIER_VDIE_Msk (0x200UL) /*!< VDIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CPBE1IE_Pos (12UL) /*!< CPBE1IE (Bit 12) */ + #define R_CEU_CEIER_CPBE1IE_Msk (0x1000UL) /*!< CPBE1IE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CPBE2IE_Pos (13UL) /*!< CPBE2IE (Bit 13) */ + #define R_CEU_CEIER_CPBE2IE_Msk (0x2000UL) /*!< CPBE2IE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CPBE3IE_Pos (14UL) /*!< CPBE3IE (Bit 14) */ + #define R_CEU_CEIER_CPBE3IE_Msk (0x4000UL) /*!< CPBE3IE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CPBE4IE_Pos (15UL) /*!< CPBE4IE (Bit 15) */ + #define R_CEU_CEIER_CPBE4IE_Msk (0x8000UL) /*!< CPBE4IE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CDTOFIE_Pos (16UL) /*!< CDTOFIE (Bit 16) */ + #define R_CEU_CEIER_CDTOFIE_Msk (0x10000UL) /*!< CDTOFIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_IGHSIE_Pos (17UL) /*!< IGHSIE (Bit 17) */ + #define R_CEU_CEIER_IGHSIE_Msk (0x20000UL) /*!< IGHSIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_IGVSIE_Pos (18UL) /*!< IGVSIE (Bit 18) */ + #define R_CEU_CEIER_IGVSIE_Msk (0x40000UL) /*!< IGVSIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_VBPIE_Pos (20UL) /*!< VBPIE (Bit 20) */ + #define R_CEU_CEIER_VBPIE_Msk (0x100000UL) /*!< VBPIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_FWFIE_Pos (23UL) /*!< FWFIE (Bit 23) */ + #define R_CEU_CEIER_FWFIE_Msk (0x800000UL) /*!< FWFIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_NHDIE_Pos (24UL) /*!< NHDIE (Bit 24) */ + #define R_CEU_CEIER_NHDIE_Msk (0x1000000UL) /*!< NHDIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_NVDIE_Pos (25UL) /*!< NVDIE (Bit 25) */ + #define R_CEU_CEIER_NVDIE_Msk (0x2000000UL) /*!< NVDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CETCR ========================================================= */ + #define R_CEU_CETCR_CPE_Pos (0UL) /*!< CPE (Bit 0) */ + #define R_CEU_CETCR_CPE_Msk (0x1UL) /*!< CPE (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CFE_Pos (1UL) /*!< CFE (Bit 1) */ + #define R_CEU_CETCR_CFE_Msk (0x2UL) /*!< CFE (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_IGRW_Pos (4UL) /*!< IGRW (Bit 4) */ + #define R_CEU_CETCR_IGRW_Msk (0x10UL) /*!< IGRW (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_HD_Pos (8UL) /*!< HD (Bit 8) */ + #define R_CEU_CETCR_HD_Msk (0x100UL) /*!< HD (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_VD_Pos (9UL) /*!< VD (Bit 9) */ + #define R_CEU_CETCR_VD_Msk (0x200UL) /*!< VD (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CPBE1_Pos (12UL) /*!< CPBE1 (Bit 12) */ + #define R_CEU_CETCR_CPBE1_Msk (0x1000UL) /*!< CPBE1 (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CPBE2_Pos (13UL) /*!< CPBE2 (Bit 13) */ + #define R_CEU_CETCR_CPBE2_Msk (0x2000UL) /*!< CPBE2 (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CPBE3_Pos (14UL) /*!< CPBE3 (Bit 14) */ + #define R_CEU_CETCR_CPBE3_Msk (0x4000UL) /*!< CPBE3 (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CPBE4_Pos (15UL) /*!< CPBE4 (Bit 15) */ + #define R_CEU_CETCR_CPBE4_Msk (0x8000UL) /*!< CPBE4 (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CDTOF_Pos (16UL) /*!< CDTOF (Bit 16) */ + #define R_CEU_CETCR_CDTOF_Msk (0x10000UL) /*!< CDTOF (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_IGHS_Pos (17UL) /*!< IGHS (Bit 17) */ + #define R_CEU_CETCR_IGHS_Msk (0x20000UL) /*!< IGHS (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_IGVS_Pos (18UL) /*!< IGVS (Bit 18) */ + #define R_CEU_CETCR_IGVS_Msk (0x40000UL) /*!< IGVS (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_VBP_Pos (20UL) /*!< VBP (Bit 20) */ + #define R_CEU_CETCR_VBP_Msk (0x100000UL) /*!< VBP (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_FWF_Pos (23UL) /*!< FWF (Bit 23) */ + #define R_CEU_CETCR_FWF_Msk (0x800000UL) /*!< FWF (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_NHD_Pos (24UL) /*!< NHD (Bit 24) */ + #define R_CEU_CETCR_NHD_Msk (0x1000000UL) /*!< NHD (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_NVD_Pos (25UL) /*!< NVD (Bit 25) */ + #define R_CEU_CETCR_NVD_Msk (0x2000000UL) /*!< NVD (Bitfield-Mask: 0x01) */ +/* ========================================================= CSTSR ========================================================= */ + #define R_CEU_CSTSR_CPTON_Pos (0UL) /*!< CPTON (Bit 0) */ + #define R_CEU_CSTSR_CPTON_Msk (0x1UL) /*!< CPTON (Bitfield-Mask: 0x01) */ + #define R_CEU_CSTSR_CPFLD_Pos (16UL) /*!< CPFLD (Bit 16) */ + #define R_CEU_CSTSR_CPFLD_Msk (0x10000UL) /*!< CPFLD (Bitfield-Mask: 0x01) */ + #define R_CEU_CSTSR_CRST_Pos (24UL) /*!< CRST (Bit 24) */ + #define R_CEU_CSTSR_CRST_Msk (0x1000000UL) /*!< CRST (Bitfield-Mask: 0x01) */ +/* ========================================================= CDSSR ========================================================= */ + #define R_CEU_CDSSR_CDSS_Pos (0UL) /*!< CDSS (Bit 0) */ + #define R_CEU_CDSSR_CDSS_Msk (0xffffffffUL) /*!< CDSS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDAYR2 ========================================================= */ + #define R_CEU_CDAYR2_CAYR2_Pos (0UL) /*!< CAYR2 (Bit 0) */ + #define R_CEU_CDAYR2_CAYR2_Msk (0xffffffffUL) /*!< CAYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDACR2 ========================================================= */ + #define R_CEU_CDACR2_CACR2_Pos (0UL) /*!< CACR2 (Bit 0) */ + #define R_CEU_CDACR2_CACR2_Msk (0xffffffffUL) /*!< CACR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBYR2 ========================================================= */ + #define R_CEU_CDBYR2_CBYR2_Pos (0UL) /*!< CBYR2 (Bit 0) */ + #define R_CEU_CDBYR2_CBYR2_Msk (0xffffffffUL) /*!< CBYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBCR2 ========================================================= */ + #define R_CEU_CDBCR2_CBCR2_Pos (0UL) /*!< CBCR2 (Bit 0) */ + #define R_CEU_CDBCR2_CBCR2_Msk (0xffffffffUL) /*!< CBCR2 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== AXIBUSCTL2 ======================================================= */ + #define R_CEU_AXIBUSCTL2_AWCACHE_Pos (0UL) /*!< AWCACHE (Bit 0) */ + #define R_CEU_AXIBUSCTL2_AWCACHE_Msk (0xfUL) /*!< AWCACHE (Bitfield-Mask: 0x0f) */ +/* ======================================================== CAMOR_B ======================================================== */ + #define R_CEU_CAMOR_B_HOFST_Pos (0UL) /*!< HOFST (Bit 0) */ + #define R_CEU_CAMOR_B_HOFST_Msk (0x1fffUL) /*!< HOFST (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAMOR_B_VOFST_Pos (16UL) /*!< VOFST (Bit 16) */ + #define R_CEU_CAMOR_B_VOFST_Msk (0xfff0000UL) /*!< VOFST (Bitfield-Mask: 0xfff) */ +/* ======================================================== CAPWR_B ======================================================== */ + #define R_CEU_CAPWR_B_HWDTH_Pos (0UL) /*!< HWDTH (Bit 0) */ + #define R_CEU_CAPWR_B_HWDTH_Msk (0x1fffUL) /*!< HWDTH (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAPWR_B_VWDTH_Pos (16UL) /*!< VWDTH (Bit 16) */ + #define R_CEU_CAPWR_B_VWDTH_Msk (0xfff0000UL) /*!< VWDTH (Bitfield-Mask: 0xfff) */ +/* ======================================================== CFLCR_B ======================================================== */ + #define R_CEU_CFLCR_B_HFRAC_Pos (0UL) /*!< HFRAC (Bit 0) */ + #define R_CEU_CFLCR_B_HFRAC_Msk (0xfffUL) /*!< HFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_B_HMANT_Pos (12UL) /*!< HMANT (Bit 12) */ + #define R_CEU_CFLCR_B_HMANT_Msk (0xf000UL) /*!< HMANT (Bitfield-Mask: 0x0f) */ + #define R_CEU_CFLCR_B_VFRAC_Pos (16UL) /*!< VFRAC (Bit 16) */ + #define R_CEU_CFLCR_B_VFRAC_Msk (0xfff0000UL) /*!< VFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_B_VMANT_Pos (28UL) /*!< VMANT (Bit 28) */ + #define R_CEU_CFLCR_B_VMANT_Msk (0xf0000000UL) /*!< VMANT (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFSZR_B ======================================================== */ + #define R_CEU_CFSZR_B_HFCLP_Pos (0UL) /*!< HFCLP (Bit 0) */ + #define R_CEU_CFSZR_B_HFCLP_Msk (0xfffUL) /*!< HFCLP (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFSZR_B_VFCLP_Pos (16UL) /*!< VFCLP (Bit 16) */ + #define R_CEU_CFSZR_B_VFCLP_Msk (0xfff0000UL) /*!< VFCLP (Bitfield-Mask: 0xfff) */ +/* ======================================================== CDWDR_B ======================================================== */ + #define R_CEU_CDWDR_B_CHDW_Pos (0UL) /*!< CHDW (Bit 0) */ + #define R_CEU_CDWDR_B_CHDW_Msk (0x1fffUL) /*!< CHDW (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CDAYR_B ======================================================== */ + #define R_CEU_CDAYR_B_CAYR_Pos (0UL) /*!< CAYR (Bit 0) */ + #define R_CEU_CDAYR_B_CAYR_Msk (0xffffffffUL) /*!< CAYR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDACR_B ======================================================== */ + #define R_CEU_CDACR_B_CACR_Pos (0UL) /*!< CACR (Bit 0) */ + #define R_CEU_CDACR_B_CACR_Msk (0xffffffffUL) /*!< CACR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBYR_B ======================================================== */ + #define R_CEU_CDBYR_B_CBYR_Pos (0UL) /*!< CBYR (Bit 0) */ + #define R_CEU_CDBYR_B_CBYR_Msk (0xffffffffUL) /*!< CBYR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBCR_B ======================================================== */ + #define R_CEU_CDBCR_B_CBCR_Pos (0UL) /*!< CBCR (Bit 0) */ + #define R_CEU_CDBCR_B_CBCR_Msk (0xffffffffUL) /*!< CBCR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CBDSR_B ======================================================== */ + #define R_CEU_CBDSR_B_CBVS_Pos (0UL) /*!< CBVS (Bit 0) */ + #define R_CEU_CBDSR_B_CBVS_Msk (0x7fffffUL) /*!< CBVS (Bitfield-Mask: 0x7fffff) */ +/* ======================================================== CLFCR_B ======================================================== */ + #define R_CEU_CLFCR_B_LPF_Pos (0UL) /*!< LPF (Bit 0) */ + #define R_CEU_CLFCR_B_LPF_Msk (0x1UL) /*!< LPF (Bitfield-Mask: 0x01) */ +/* ======================================================== CDOCR_B ======================================================== */ + #define R_CEU_CDOCR_B_COBS_Pos (0UL) /*!< COBS (Bit 0) */ + #define R_CEU_CDOCR_B_COBS_Msk (0x1UL) /*!< COBS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_B_COWS_Pos (1UL) /*!< COWS (Bit 1) */ + #define R_CEU_CDOCR_B_COWS_Msk (0x2UL) /*!< COWS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_B_COLS_Pos (2UL) /*!< COLS (Bit 2) */ + #define R_CEU_CDOCR_B_COLS_Msk (0x4UL) /*!< COLS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_B_CDS_Pos (4UL) /*!< CDS (Bit 4) */ + #define R_CEU_CDOCR_B_CDS_Msk (0x10UL) /*!< CDS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_B_CBE_Pos (16UL) /*!< CBE (Bit 16) */ + #define R_CEU_CDOCR_B_CBE_Msk (0x10000UL) /*!< CBE (Bitfield-Mask: 0x01) */ +/* ======================================================= CDAYR2_B ======================================================== */ + #define R_CEU_CDAYR2_B_CAYR2_Pos (0UL) /*!< CAYR2 (Bit 0) */ + #define R_CEU_CDAYR2_B_CAYR2_Msk (0xffffffffUL) /*!< CAYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDACR2_B ======================================================== */ + #define R_CEU_CDACR2_B_CACR2_Pos (0UL) /*!< CACR2 (Bit 0) */ + #define R_CEU_CDACR2_B_CACR2_Msk (0xffffffffUL) /*!< CACR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDBYR2_B ======================================================== */ + #define R_CEU_CDBYR2_B_CBYR2_Pos (0UL) /*!< CBYR2 (Bit 0) */ + #define R_CEU_CDBYR2_B_CBYR2_Msk (0xffffffffUL) /*!< CBYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDBCR2_B ======================================================== */ + #define R_CEU_CDBCR2_B_CBCR2_Pos (0UL) /*!< CBCR2 (Bit 0) */ + #define R_CEU_CDBCR2_B_CBCR2_Msk (0xffffffffUL) /*!< CBCR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CAMOR_M ======================================================== */ + #define R_CEU_CAMOR_M_HOFST_Pos (0UL) /*!< HOFST (Bit 0) */ + #define R_CEU_CAMOR_M_HOFST_Msk (0x1fffUL) /*!< HOFST (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAMOR_M_VOFST_Pos (16UL) /*!< VOFST (Bit 16) */ + #define R_CEU_CAMOR_M_VOFST_Msk (0xfff0000UL) /*!< VOFST (Bitfield-Mask: 0xfff) */ +/* ======================================================== CAPWR_M ======================================================== */ + #define R_CEU_CAPWR_M_HWDTH_Pos (0UL) /*!< HWDTH (Bit 0) */ + #define R_CEU_CAPWR_M_HWDTH_Msk (0x1fffUL) /*!< HWDTH (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAPWR_M_VWDTH_Pos (16UL) /*!< VWDTH (Bit 16) */ + #define R_CEU_CAPWR_M_VWDTH_Msk (0xfff0000UL) /*!< VWDTH (Bitfield-Mask: 0xfff) */ +/* ======================================================== CFLCR_M ======================================================== */ + #define R_CEU_CFLCR_M_HFRAC_Pos (0UL) /*!< HFRAC (Bit 0) */ + #define R_CEU_CFLCR_M_HFRAC_Msk (0xfffUL) /*!< HFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_M_HMANT_Pos (12UL) /*!< HMANT (Bit 12) */ + #define R_CEU_CFLCR_M_HMANT_Msk (0xf000UL) /*!< HMANT (Bitfield-Mask: 0x0f) */ + #define R_CEU_CFLCR_M_VFRAC_Pos (16UL) /*!< VFRAC (Bit 16) */ + #define R_CEU_CFLCR_M_VFRAC_Msk (0xfff0000UL) /*!< VFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_M_VMANT_Pos (28UL) /*!< VMANT (Bit 28) */ + #define R_CEU_CFLCR_M_VMANT_Msk (0xf0000000UL) /*!< VMANT (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFSZR_M ======================================================== */ + #define R_CEU_CFSZR_M_HFCLP_Pos (0UL) /*!< HFCLP (Bit 0) */ + #define R_CEU_CFSZR_M_HFCLP_Msk (0xfffUL) /*!< HFCLP (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFSZR_M_VFCLP_Pos (16UL) /*!< VFCLP (Bit 16) */ + #define R_CEU_CFSZR_M_VFCLP_Msk (0xfff0000UL) /*!< VFCLP (Bitfield-Mask: 0xfff) */ +/* ======================================================== CDWDR_M ======================================================== */ + #define R_CEU_CDWDR_M_CHDW_Pos (0UL) /*!< CHDW (Bit 0) */ + #define R_CEU_CDWDR_M_CHDW_Msk (0x1fffUL) /*!< CHDW (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CDAYR_M ======================================================== */ + #define R_CEU_CDAYR_M_CAYR_Pos (0UL) /*!< CAYR (Bit 0) */ + #define R_CEU_CDAYR_M_CAYR_Msk (0xffffffffUL) /*!< CAYR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDACR_M ======================================================== */ + #define R_CEU_CDACR_M_CACR_Pos (0UL) /*!< CACR (Bit 0) */ + #define R_CEU_CDACR_M_CACR_Msk (0xffffffffUL) /*!< CACR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBYR_M ======================================================== */ + #define R_CEU_CDBYR_M_CBYR_Pos (0UL) /*!< CBYR (Bit 0) */ + #define R_CEU_CDBYR_M_CBYR_Msk (0xffffffffUL) /*!< CBYR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBCR_M ======================================================== */ + #define R_CEU_CDBCR_M_CBCR_Pos (0UL) /*!< CBCR (Bit 0) */ + #define R_CEU_CDBCR_M_CBCR_Msk (0xffffffffUL) /*!< CBCR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CBDSR_M ======================================================== */ + #define R_CEU_CBDSR_M_CBVS_Pos (0UL) /*!< CBVS (Bit 0) */ + #define R_CEU_CBDSR_M_CBVS_Msk (0x7fffffUL) /*!< CBVS (Bitfield-Mask: 0x7fffff) */ +/* ======================================================== CLFCR_M ======================================================== */ + #define R_CEU_CLFCR_M_LPF_Pos (0UL) /*!< LPF (Bit 0) */ + #define R_CEU_CLFCR_M_LPF_Msk (0x1UL) /*!< LPF (Bitfield-Mask: 0x01) */ +/* ======================================================== CDOCR_M ======================================================== */ + #define R_CEU_CDOCR_M_COBS_Pos (0UL) /*!< COBS (Bit 0) */ + #define R_CEU_CDOCR_M_COBS_Msk (0x1UL) /*!< COBS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_M_COWS_Pos (1UL) /*!< COWS (Bit 1) */ + #define R_CEU_CDOCR_M_COWS_Msk (0x2UL) /*!< COWS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_M_COLS_Pos (2UL) /*!< COLS (Bit 2) */ + #define R_CEU_CDOCR_M_COLS_Msk (0x4UL) /*!< COLS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_M_CDS_Pos (4UL) /*!< CDS (Bit 4) */ + #define R_CEU_CDOCR_M_CDS_Msk (0x10UL) /*!< CDS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_M_CBE_Pos (16UL) /*!< CBE (Bit 16) */ + #define R_CEU_CDOCR_M_CBE_Msk (0x10000UL) /*!< CBE (Bitfield-Mask: 0x01) */ +/* ======================================================= CDAYR2_M ======================================================== */ + #define R_CEU_CDAYR2_M_CAYR2_Pos (0UL) /*!< CAYR2 (Bit 0) */ + #define R_CEU_CDAYR2_M_CAYR2_Msk (0xffffffffUL) /*!< CAYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDACR2_M ======================================================== */ + #define R_CEU_CDACR2_M_CACR2_Pos (0UL) /*!< CACR2 (Bit 0) */ + #define R_CEU_CDACR2_M_CACR2_Msk (0xffffffffUL) /*!< CACR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDBYR2_M ======================================================== */ + #define R_CEU_CDBYR2_M_CBYR2_Pos (0UL) /*!< CBYR2 (Bit 0) */ + #define R_CEU_CDBYR2_M_CBYR2_Msk (0xffffffffUL) /*!< CBYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDBCR2_M ======================================================== */ + #define R_CEU_CDBCR2_M_CBCR2_Pos (0UL) /*!< CBCR2 (Bit 0) */ + #define R_CEU_CDBCR2_M_CBCR2_Msk (0xffffffffUL) /*!< CBCR2 (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_ULPT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== ULPTCNT ======================================================== */ + #define R_ULPT0_ULPTCNT_ULPTCNT_Pos (0UL) /*!< ULPTCNT (Bit 0) */ + #define R_ULPT0_ULPTCNT_ULPTCNT_Msk (0xffffffffUL) /*!< ULPTCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ULPTCMA ======================================================== */ + #define R_ULPT0_ULPTCMA_ULPTCMA_Pos (0UL) /*!< ULPTCMA (Bit 0) */ + #define R_ULPT0_ULPTCMA_ULPTCMA_Msk (0xffffffffUL) /*!< ULPTCMA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ULPTCMB ======================================================== */ + #define R_ULPT0_ULPTCMB_ULPTCMB_Pos (0UL) /*!< ULPTCMB (Bit 0) */ + #define R_ULPT0_ULPTCMB_ULPTCMB_Msk (0xffffffffUL) /*!< ULPTCMB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ULPTCR ========================================================= */ + #define R_ULPT0_ULPTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_ULPT0_ULPTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_ULPT0_ULPTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_ULPT0_ULPTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_ULPT0_ULPTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_ULPT0_ULPTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_ULPT0_ULPTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ +/* ======================================================== ULPTMR1 ======================================================== */ + #define R_ULPT0_ULPTMR1_TMOD1_Pos (1UL) /*!< TMOD1 (Bit 1) */ + #define R_ULPT0_ULPTMR1_TMOD1_Msk (0x2UL) /*!< TMOD1 (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_ULPT0_ULPTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR1_TCK1_Pos (5UL) /*!< TCK1 (Bit 5) */ + #define R_ULPT0_ULPTMR1_TCK1_Msk (0x20UL) /*!< TCK1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ULPTMR2 ======================================================== */ + #define R_ULPT0_ULPTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_ULPT0_ULPTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_ULPT0_ULPTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_ULPT0_ULPTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ +/* ======================================================== ULPTMR3 ======================================================== */ + #define R_ULPT0_ULPTMR3_TCNTCTL_Pos (0UL) /*!< TCNTCTL (Bit 0) */ + #define R_ULPT0_ULPTMR3_TCNTCTL_Msk (0x1UL) /*!< TCNTCTL (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR3_TEVPOL_Pos (1UL) /*!< TEVPOL (Bit 1) */ + #define R_ULPT0_ULPTMR3_TEVPOL_Msk (0x2UL) /*!< TEVPOL (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR3_TOPOL_Pos (2UL) /*!< TOPOL (Bit 2) */ + #define R_ULPT0_ULPTMR3_TOPOL_Msk (0x4UL) /*!< TOPOL (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR3_TEECTL_Pos (4UL) /*!< TEECTL (Bit 4) */ + #define R_ULPT0_ULPTMR3_TEECTL_Msk (0x30UL) /*!< TEECTL (Bitfield-Mask: 0x03) */ + #define R_ULPT0_ULPTMR3_TEEPOL_Pos (6UL) /*!< TEEPOL (Bit 6) */ + #define R_ULPT0_ULPTMR3_TEEPOL_Msk (0xc0UL) /*!< TEEPOL (Bitfield-Mask: 0x03) */ +/* ======================================================== ULPTIOC ======================================================== */ + #define R_ULPT0_ULPTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_ULPT0_ULPTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_ULPT0_ULPTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_ULPT0_ULPTIOC_TIOGT0_Pos (6UL) /*!< TIOGT0 (Bit 6) */ + #define R_ULPT0_ULPTIOC_TIOGT0_Msk (0x40UL) /*!< TIOGT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ULPTISR ======================================================== */ + #define R_ULPT0_ULPTISR_RCCPSEL2_Pos (2UL) /*!< RCCPSEL2 (Bit 2) */ + #define R_ULPT0_ULPTISR_RCCPSEL2_Msk (0x4UL) /*!< RCCPSEL2 (Bitfield-Mask: 0x01) */ +/* ======================================================= ULPTCMSR ======================================================== */ + #define R_ULPT0_ULPTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_ULPT0_ULPTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_ULPT0_ULPTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_ULPT0_ULPTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_ULPT0_ULPTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_ULPT0_ULPTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_ULPT0_ULPTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG_OCD ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== MCUERRSTAT ======================================================= */ + #define R_DEBUG_OCD_MCUERRSTAT_ZERO_Pos (0UL) /*!< ZERO (Bit 0) */ + #define R_DEBUG_OCD_MCUERRSTAT_ZERO_Msk (0x1UL) /*!< ZERO (Bitfield-Mask: 0x01) */ +/* ======================================================== MCUCTRL ======================================================== */ + #define R_DEBUG_OCD_MCUCTRL_EDBGRQ0_Pos (0UL) /*!< EDBGRQ0 (Bit 0) */ + #define R_DEBUG_OCD_MCUCTRL_EDBGRQ0_Msk (0x1UL) /*!< EDBGRQ0 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_OCD_MCUCTRL_EDBGRQ1_Pos (1UL) /*!< EDBGRQ1 (Bit 1) */ + #define R_DEBUG_OCD_MCUCTRL_EDBGRQ1_Msk (0x2UL) /*!< EDBGRQ1 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_OCD_MCUCTRL_DBIRQ0_Pos (8UL) /*!< DBIRQ0 (Bit 8) */ + #define R_DEBUG_OCD_MCUCTRL_DBIRQ0_Msk (0x100UL) /*!< DBIRQ0 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_OCD_MCUCTRL_DBIRQ1_Pos (9UL) /*!< DBIRQ1 (Bit 9) */ + #define R_DEBUG_OCD_MCUCTRL_DBIRQ1_Msk (0x200UL) /*!< DBIRQ1 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_OCD_MCUCTRL_CPUWAIT0_Pos (16UL) /*!< CPUWAIT0 (Bit 16) */ + #define R_DEBUG_OCD_MCUCTRL_CPUWAIT0_Msk (0x10000UL) /*!< CPUWAIT0 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_OCD_MCUCTRL_CPUWAIT1_Pos (17UL) /*!< CPUWAIT1 (Bit 17) */ + #define R_DEBUG_OCD_MCUCTRL_CPUWAIT1_Msk (0x20000UL) /*!< CPUWAIT1 (Bitfield-Mask: 0x01) */ +/* ========================================================= JBMDR ========================================================= */ + #define R_DEBUG_OCD_JBMDR_KEY_Pos (0UL) /*!< KEY (Bit 0) */ + #define R_DEBUG_OCD_JBMDR_KEY_Msk (0xffUL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================= JBRDR ========================================================= */ + #define R_DEBUG_OCD_JBRDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_DEBUG_OCD_JBRDR_RDAT_Msk (0xffffffffUL) /*!< RDAT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= JBTDR ========================================================= */ + #define R_DEBUG_OCD_JBTDR_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_DEBUG_OCD_JBTDR_TDAT_Msk (0xffffffffUL) /*!< TDAT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= JBSTR ========================================================= */ + #define R_DEBUG_OCD_JBSTR_RDF_Pos (0UL) /*!< RDF (Bit 0) */ + #define R_DEBUG_OCD_JBSTR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_DEBUG_OCD_JBSTR_TDE_Pos (1UL) /*!< TDE (Bit 1) */ + #define R_DEBUG_OCD_JBSTR_TDE_Msk (0x2UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= JBICR ========================================================= */ + #define R_DEBUG_OCD_JBICR_RDFIE_Pos (0UL) /*!< RDFIE (Bit 0) */ + #define R_DEBUG_OCD_JBICR_RDFIE_Msk (0x1UL) /*!< RDFIE (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTATM ======================================================= */ + #define R_DEBUG_OCD_FSBLSTATM_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_OCD_FSBLSTATM_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_OCD_FSBLSTATM_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_OCD_FSBLSTATM_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOTF ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== CONVAREAST ======================================================= */ + #define R_DOTF_CONVAREAST_CONVAREAST_Pos (12UL) /*!< CONVAREAST (Bit 12) */ + #define R_DOTF_CONVAREAST_CONVAREAST_Msk (0xfffff000UL) /*!< CONVAREAST (Bitfield-Mask: 0xfffff) */ +/* ======================================================= CONVAREAD ======================================================= */ + #define R_DOTF_CONVAREAD_CONVAREAD_Pos (12UL) /*!< CONVAREAD (Bit 12) */ + #define R_DOTF_CONVAREAD_CONVAREAD_Msk (0xfffff000UL) /*!< CONVAREAD (Bitfield-Mask: 0xfffff) */ +/* ========================================================= REG00 ========================================================= */ + #define R_DOTF_REG00_B09_Pos (9UL) /*!< B09 (Bit 9) */ + #define R_DOTF_REG00_B09_Msk (0x200UL) /*!< B09 (Bitfield-Mask: 0x01) */ + #define R_DOTF_REG00_B16_Pos (16UL) /*!< B16 (Bit 16) */ + #define R_DOTF_REG00_B16_Msk (0x10000UL) /*!< B16 (Bitfield-Mask: 0x01) */ + #define R_DOTF_REG00_B17_Pos (17UL) /*!< B17 (Bit 17) */ + #define R_DOTF_REG00_B17_Msk (0x20000UL) /*!< B17 (Bitfield-Mask: 0x01) */ + #define R_DOTF_REG00_B20_Pos (20UL) /*!< B20 (Bit 20) */ + #define R_DOTF_REG00_B20_Msk (0x100000UL) /*!< B20 (Bitfield-Mask: 0x01) */ + #define R_DOTF_REG00_B24_Pos (24UL) /*!< B24 (Bit 24) */ + #define R_DOTF_REG00_B24_Msk (0x3000000UL) /*!< B24 (Bitfield-Mask: 0x03) */ + #define R_DOTF_REG00_B28_Pos (28UL) /*!< B28 (Bit 28) */ + #define R_DOTF_REG00_B28_Msk (0x30000000UL) /*!< B28 (Bitfield-Mask: 0x03) */ +/* ========================================================= REG03 ========================================================= */ + #define R_DOTF_REG03_B00_Pos (0UL) /*!< B00 (Bit 0) */ + #define R_DOTF_REG03_B00_Msk (0xffffffffUL) /*!< B00 (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_AGTX0 ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_COMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RIPV ========================================================== */ + #define R_COMA_RIPV_TIPV_Pos (0UL) /*!< TIPV (Bit 0) */ + #define R_COMA_RIPV_TIPV_Msk (0xfUL) /*!< TIPV (Bitfield-Mask: 0x0f) */ + #define R_COMA_RIPV_GWIPV_Pos (4UL) /*!< GWIPV (Bit 4) */ + #define R_COMA_RIPV_GWIPV_Msk (0xf0UL) /*!< GWIPV (Bitfield-Mask: 0x0f) */ + #define R_COMA_RIPV_FWIPV_Pos (8UL) /*!< FWIPV (Bit 8) */ + #define R_COMA_RIPV_FWIPV_Msk (0xf00UL) /*!< FWIPV (Bitfield-Mask: 0x0f) */ + #define R_COMA_RIPV_EAIPV_Pos (12UL) /*!< EAIPV (Bit 12) */ + #define R_COMA_RIPV_EAIPV_Msk (0xf000UL) /*!< EAIPV (Bitfield-Mask: 0x0f) */ + #define R_COMA_RIPV_FBIPV_Pos (16UL) /*!< FBIPV (Bit 16) */ + #define R_COMA_RIPV_FBIPV_Msk (0xf0000UL) /*!< FBIPV (Bitfield-Mask: 0x0f) */ + #define R_COMA_RIPV_CAIPV_Pos (20UL) /*!< CAIPV (Bit 20) */ + #define R_COMA_RIPV_CAIPV_Msk (0xf00000UL) /*!< CAIPV (Bitfield-Mask: 0x0f) */ +/* ========================================================== RRC ========================================================== */ + #define R_COMA_RRC_RR_Pos (0UL) /*!< RR (Bit 0) */ + #define R_COMA_RRC_RR_Msk (0x1UL) /*!< RR (Bitfield-Mask: 0x01) */ +/* ========================================================= RCEC ========================================================== */ + #define R_COMA_RCEC_ACE_Pos (0UL) /*!< ACE (Bit 0) */ + #define R_COMA_RCEC_ACE_Msk (0x7fUL) /*!< ACE (Bitfield-Mask: 0x7f) */ + #define R_COMA_RCEC_RCE_Pos (16UL) /*!< RCE (Bit 16) */ + #define R_COMA_RCEC_RCE_Msk (0x10000UL) /*!< RCE (Bitfield-Mask: 0x01) */ +/* ========================================================= RCDC ========================================================== */ + #define R_COMA_RCDC_ACD_Pos (0UL) /*!< ACD (Bit 0) */ + #define R_COMA_RCDC_ACD_Msk (0x7fUL) /*!< ACD (Bitfield-Mask: 0x7f) */ + #define R_COMA_RCDC_RCD_Pos (16UL) /*!< RCD (Bit 16) */ + #define R_COMA_RCDC_RCD_Msk (0x10000UL) /*!< RCD (Bitfield-Mask: 0x01) */ +/* ======================================================= CABPIBWMC ======================================================= */ + #define R_COMA_CABPIBWMC_IBUWMPN_Pos (0UL) /*!< IBUWMPN (Bit 0) */ + #define R_COMA_CABPIBWMC_IBUWMPN_Msk (0x3ffUL) /*!< IBUWMPN (Bitfield-Mask: 0x3ff) */ + #define R_COMA_CABPIBWMC_IBSWMPN_Pos (16UL) /*!< IBSWMPN (Bit 16) */ + #define R_COMA_CABPIBWMC_IBSWMPN_Msk (0x3ff0000UL) /*!< IBSWMPN (Bitfield-Mask: 0x3ff) */ +/* ======================================================= CABPWMLC ======================================================== */ + #define R_COMA_CABPWMLC_WMFL_Pos (0UL) /*!< WMFL (Bit 0) */ + #define R_COMA_CABPWMLC_WMFL_Msk (0x1fffUL) /*!< WMFL (Bitfield-Mask: 0x1fff) */ + #define R_COMA_CABPWMLC_WMCL_Pos (16UL) /*!< WMCL (Bit 16) */ + #define R_COMA_CABPWMLC_WMCL_Msk (0x1fff0000UL) /*!< WMCL (Bitfield-Mask: 0x1fff) */ +/* ======================================================= CABPPFLC ======================================================== */ + #define R_COMA_CABPPFLC_PDL_Pos (0UL) /*!< PDL (Bit 0) */ + #define R_COMA_CABPPFLC_PDL_Msk (0x1fffUL) /*!< PDL (Bitfield-Mask: 0x1fff) */ + #define R_COMA_CABPPFLC_PAL_Pos (16UL) /*!< PAL (Bit 16) */ + #define R_COMA_CABPPFLC_PAL_Msk (0x1fff0000UL) /*!< PAL (Bitfield-Mask: 0x1fff) */ +/* ======================================================= CABPPWMLC ======================================================= */ + #define R_COMA_CABPPWMLC_PWMFL_Pos (0UL) /*!< PWMFL (Bit 0) */ + #define R_COMA_CABPPWMLC_PWMFL_Msk (0x1fffUL) /*!< PWMFL (Bitfield-Mask: 0x1fff) */ + #define R_COMA_CABPPWMLC_PWMCL_Pos (16UL) /*!< PWMCL (Bit 16) */ + #define R_COMA_CABPPWMLC_PWMCL_Msk (0x1fff0000UL) /*!< PWMCL (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CABPULC ======================================================== */ + #define R_COMA_CABPULC_MXNPN_Pos (0UL) /*!< MXNPN (Bit 0) */ + #define R_COMA_CABPULC_MXNPN_Msk (0x1fffUL) /*!< MXNPN (Bitfield-Mask: 0x1fff) */ + #define R_COMA_CABPULC_MNNPN_Pos (16UL) /*!< MNNPN (Bit 16) */ + #define R_COMA_CABPULC_MNNPN_Msk (0x1fff0000UL) /*!< MNNPN (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CABPIRM ======================================================== */ + #define R_COMA_CABPIRM_BPIOG_Pos (0UL) /*!< BPIOG (Bit 0) */ + #define R_COMA_CABPIRM_BPIOG_Msk (0x1UL) /*!< BPIOG (Bitfield-Mask: 0x01) */ + #define R_COMA_CABPIRM_BPR_Pos (1UL) /*!< BPR (Bit 1) */ + #define R_COMA_CABPIRM_BPR_Msk (0x2UL) /*!< BPR (Bitfield-Mask: 0x01) */ +/* ======================================================== CABPPCM ======================================================== */ + #define R_COMA_CABPPCM_RPC_Pos (0UL) /*!< RPC (Bit 0) */ + #define R_COMA_CABPPCM_RPC_Msk (0x1fffUL) /*!< RPC (Bitfield-Mask: 0x1fff) */ + #define R_COMA_CABPPCM_TPC_Pos (16UL) /*!< TPC (Bit 16) */ + #define R_COMA_CABPPCM_TPC_Msk (0x1fff0000UL) /*!< TPC (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CABPLCM ======================================================== */ + #define R_COMA_CABPLCM_LRC_Pos (0UL) /*!< LRC (Bit 0) */ + #define R_COMA_CABPLCM_LRC_Msk (0x1fffUL) /*!< LRC (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CABPCPM ======================================================== */ + #define R_COMA_CABPCPM_RPCP_Pos (0UL) /*!< RPCP (Bit 0) */ + #define R_COMA_CABPCPM_RPCP_Msk (0x1fffUL) /*!< RPCP (Bitfield-Mask: 0x1fff) */ +/* ======================================================= CABPMCPM ======================================================== */ + #define R_COMA_CABPMCPM_RPMCP_Pos (0UL) /*!< RPMCP (Bit 0) */ + #define R_COMA_CABPMCPM_RPMCP_Msk (0x1fffUL) /*!< RPMCP (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CARDNM ========================================================= */ + #define R_COMA_CARDNM_RDNRR_Pos (0UL) /*!< RDNRR (Bit 0) */ + #define R_COMA_CARDNM_RDNRR_Msk (0x1fffUL) /*!< RDNRR (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CARDMNM ======================================================== */ + #define R_COMA_CARDMNM_RDMNRR_Pos (0UL) /*!< RDMNRR (Bit 0) */ + #define R_COMA_CARDMNM_RDMNRR_Msk (0x1fffUL) /*!< RDMNRR (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CARDCN ========================================================= */ + #define R_COMA_CARDCN_RDN_Pos (0UL) /*!< RDN (Bit 0) */ + #define R_COMA_CARDCN_RDN_Msk (0xffffffffUL) /*!< RDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CAEIS0 ========================================================= */ + #define R_COMA_CAEIS0_PECCES_Pos (0UL) /*!< PECCES (Bit 0) */ + #define R_COMA_CAEIS0_PECCES_Msk (0x1UL) /*!< PECCES (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIS0_DSECCES_Pos (1UL) /*!< DSECCES (Bit 1) */ + #define R_COMA_CAEIS0_DSECCES_Msk (0x2UL) /*!< DSECCES (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIS0_BPECCES_Pos (2UL) /*!< BPECCES (Bit 2) */ + #define R_COMA_CAEIS0_BPECCES_Msk (0x4UL) /*!< BPECCES (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIS0_BPOPS_Pos (8UL) /*!< BPOPS (Bit 8) */ + #define R_COMA_CAEIS0_BPOPS_Msk (0x100UL) /*!< BPOPS (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIS0_WMCLOS_Pos (9UL) /*!< WMCLOS (Bit 9) */ + #define R_COMA_CAEIS0_WMCLOS_Msk (0x200UL) /*!< WMCLOS (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIS0_WMFLOS_Pos (10UL) /*!< WMFLOS (Bit 10) */ + #define R_COMA_CAEIS0_WMFLOS_Msk (0x400UL) /*!< WMFLOS (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIS0_EEIPLN_Pos (16UL) /*!< EEIPLN (Bit 16) */ + #define R_COMA_CAEIS0_EEIPLN_Msk (0xf0000UL) /*!< EEIPLN (Bitfield-Mask: 0x0f) */ +/* ======================================================== CAEIE0 ========================================================= */ + #define R_COMA_CAEIE0_PECCEE_Pos (0UL) /*!< PECCEE (Bit 0) */ + #define R_COMA_CAEIE0_PECCEE_Msk (0x1UL) /*!< PECCEE (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIE0_DSECCEE_Pos (1UL) /*!< DSECCEE (Bit 1) */ + #define R_COMA_CAEIE0_DSECCEE_Msk (0x2UL) /*!< DSECCEE (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIE0_BPECCEE_Pos (2UL) /*!< BPECCEE (Bit 2) */ + #define R_COMA_CAEIE0_BPECCEE_Msk (0x4UL) /*!< BPECCEE (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIE0_BPOPE_Pos (8UL) /*!< BPOPE (Bit 8) */ + #define R_COMA_CAEIE0_BPOPE_Msk (0x100UL) /*!< BPOPE (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIE0_WMCLOE_Pos (9UL) /*!< WMCLOE (Bit 9) */ + #define R_COMA_CAEIE0_WMCLOE_Msk (0x200UL) /*!< WMCLOE (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIE0_WMFLOE_Pos (10UL) /*!< WMFLOE (Bit 10) */ + #define R_COMA_CAEIE0_WMFLOE_Msk (0x400UL) /*!< WMFLOE (Bitfield-Mask: 0x01) */ +/* ======================================================== CAEID0 ========================================================= */ + #define R_COMA_CAEID0_PECCED_Pos (0UL) /*!< PECCED (Bit 0) */ + #define R_COMA_CAEID0_PECCED_Msk (0x1UL) /*!< PECCED (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEID0_DSECCED_Pos (1UL) /*!< DSECCED (Bit 1) */ + #define R_COMA_CAEID0_DSECCED_Msk (0x2UL) /*!< DSECCED (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEID0_BPECCED_Pos (2UL) /*!< BPECCED (Bit 2) */ + #define R_COMA_CAEID0_BPECCED_Msk (0x4UL) /*!< BPECCED (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEID0_BPOPD_Pos (8UL) /*!< BPOPD (Bit 8) */ + #define R_COMA_CAEID0_BPOPD_Msk (0x100UL) /*!< BPOPD (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEID0_WMCLOD_Pos (9UL) /*!< WMCLOD (Bit 9) */ + #define R_COMA_CAEID0_WMCLOD_Msk (0x200UL) /*!< WMCLOD (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEID0_WMFLOD_Pos (10UL) /*!< WMFLOD (Bit 10) */ + #define R_COMA_CAEID0_WMFLOD_Msk (0x400UL) /*!< WMFLOD (Bitfield-Mask: 0x01) */ +/* ======================================================== CAEIS1 ========================================================= */ + #define R_COMA_CAEIS1_PWMCLOS_Pos (0UL) /*!< PWMCLOS (Bit 0) */ + #define R_COMA_CAEIS1_PWMCLOS_Msk (0x7fUL) /*!< PWMCLOS (Bitfield-Mask: 0x7f) */ + #define R_COMA_CAEIS1_PWMFLOS_Pos (16UL) /*!< PWMFLOS (Bit 16) */ + #define R_COMA_CAEIS1_PWMFLOS_Msk (0x7f0000UL) /*!< PWMFLOS (Bitfield-Mask: 0x7f) */ +/* ======================================================== CAEIE1 ========================================================= */ + #define R_COMA_CAEIE1_PWMCLOE_Pos (0UL) /*!< PWMCLOE (Bit 0) */ + #define R_COMA_CAEIE1_PWMCLOE_Msk (0x7fUL) /*!< PWMCLOE (Bitfield-Mask: 0x7f) */ + #define R_COMA_CAEIE1_PWMFLOE_Pos (16UL) /*!< PWMFLOE (Bit 16) */ + #define R_COMA_CAEIE1_PWMFLOE_Msk (0x7f0000UL) /*!< PWMFLOE (Bitfield-Mask: 0x7f) */ +/* ======================================================== CAEID1 ========================================================= */ + #define R_COMA_CAEID1_PWMCLOD_Pos (0UL) /*!< PWMCLOD (Bit 0) */ + #define R_COMA_CAEID1_PWMCLOD_Msk (0x7fUL) /*!< PWMCLOD (Bitfield-Mask: 0x7f) */ + #define R_COMA_CAEID1_PWMFLOD_Pos (16UL) /*!< PWMFLOD (Bit 16) */ + #define R_COMA_CAEID1_PWMFLOD_Msk (0x7f0000UL) /*!< PWMFLOD (Bitfield-Mask: 0x7f) */ +/* ======================================================== CAMIS0 ========================================================= */ + #define R_COMA_CAMIS0_PFS_Pos (0UL) /*!< PFS (Bit 0) */ + #define R_COMA_CAMIS0_PFS_Msk (0x3UL) /*!< PFS (Bitfield-Mask: 0x03) */ +/* ======================================================== CAMIE0 ========================================================= */ + #define R_COMA_CAMIE0_PFE_Pos (0UL) /*!< PFE (Bit 0) */ + #define R_COMA_CAMIE0_PFE_Msk (0x3UL) /*!< PFE (Bitfield-Mask: 0x03) */ +/* ======================================================== CAMID0 ========================================================= */ + #define R_COMA_CAMID0_PFD_Pos (0UL) /*!< PFD (Bit 0) */ + #define R_COMA_CAMID0_PFD_Msk (0x3UL) /*!< PFD (Bitfield-Mask: 0x03) */ +/* ======================================================== CAMIS1 ========================================================= */ + #define R_COMA_CAMIS1_PPFS_Pos (0UL) /*!< PPFS (Bit 0) */ + #define R_COMA_CAMIS1_PPFS_Msk (0x3fffUL) /*!< PPFS (Bitfield-Mask: 0x3fff) */ +/* ======================================================== CAMIE1 ========================================================= */ + #define R_COMA_CAMIE1_PPFE_Pos (0UL) /*!< PPFE (Bit 0) */ + #define R_COMA_CAMIE1_PPFE_Msk (0x3fffUL) /*!< PPFE (Bitfield-Mask: 0x3fff) */ +/* ======================================================== CAMID1 ========================================================= */ + #define R_COMA_CAMID1_PPFD_Pos (0UL) /*!< PPFD (Bit 0) */ + #define R_COMA_CAMID1_PPFD_Msk (0x3fffUL) /*!< PPFD (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_CPU_CTRL ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== CPU0LCKUPCR ====================================================== */ + #define R_CPU_CTRL_CPU0LCKUPCR_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_CPU_CTRL_CPU0LCKUPCR_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ====================================================== CPU1LCKUPCR ====================================================== */ + #define R_CPU_CTRL_CPU1LCKUPCR_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_CPU_CTRL_CPU1LCKUPCR_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ===================================================== CPU0INITVTOR ====================================================== */ + #define R_CPU_CTRL_CPU0INITVTOR_CPUnINITVTOR_Pos (0UL) /*!< CPUnINITVTOR (Bit 0) */ + #define R_CPU_CTRL_CPU0INITVTOR_CPUnINITVTOR_Msk (0xffffffffUL) /*!< CPUnINITVTOR (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CPU1INITVTOR ====================================================== */ + #define R_CPU_CTRL_CPU1INITVTOR_CPUnINITVTOR_Pos (0UL) /*!< CPUnINITVTOR (Bit 0) */ + #define R_CPU_CTRL_CPU1INITVTOR_CPUnINITVTOR_Msk (0xffffffffUL) /*!< CPUnINITVTOR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== CPU0WAITCR ======================================================= */ + #define R_CPU_CTRL_CPU0WAITCR_CPUWAIT_Pos (0UL) /*!< CPUWAIT (Bit 0) */ + #define R_CPU_CTRL_CPU0WAITCR_CPUWAIT_Msk (0x1UL) /*!< CPUWAIT (Bitfield-Mask: 0x01) */ +/* ====================================================== CPU1WAITCR ======================================================= */ + #define R_CPU_CTRL_CPU1WAITCR_CPUWAIT_Pos (0UL) /*!< CPUWAIT (Bit 0) */ + #define R_CPU_CTRL_CPU1WAITCR_CPUWAIT_Msk (0x1UL) /*!< CPUWAIT (Bitfield-Mask: 0x01) */ +/* ====================================================== CPU0ACTCSR ======================================================= */ + #define R_CPU_CTRL_CPU0ACTCSR_ACTREQ_Pos (0UL) /*!< ACTREQ (Bit 0) */ + #define R_CPU_CTRL_CPU0ACTCSR_ACTREQ_Msk (0x1UL) /*!< ACTREQ (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0ACTCSR_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_CPU_CTRL_CPU0ACTCSR_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0ACTCSR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CPU_CTRL_CPU0ACTCSR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ====================================================== CPU1ACTCSR ======================================================= */ + #define R_CPU_CTRL_CPU1ACTCSR_ACTREQ_Pos (0UL) /*!< ACTREQ (Bit 0) */ + #define R_CPU_CTRL_CPU1ACTCSR_ACTREQ_Msk (0x1UL) /*!< ACTREQ (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1ACTCSR_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_CPU_CTRL_CPU1ACTCSR_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1ACTCSR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CPU_CTRL_CPU1ACTCSR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CPU0LMECR ======================================================= */ + #define R_CPU_CTRL_CPU0LMECR_SYRSTEN_Pos (0UL) /*!< SYRSTEN (Bit 0) */ + #define R_CPU_CTRL_CPU0LMECR_SYRSTEN_Msk (0x1UL) /*!< SYRSTEN (Bitfield-Mask: 0x01) */ +/* ======================================================== CPUIDR ========================================================= */ + #define R_CPU_CTRL_CPUIDR_CPUID_Pos (0UL) /*!< CPUID (Bit 0) */ + #define R_CPU_CTRL_CPUIDR_CPUID_Msk (0x1UL) /*!< CPUID (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0STATM ======================================================= */ + #define R_CPU_CTRL_CPU0STATM_SLEEPING_Pos (0UL) /*!< SLEEPING (Bit 0) */ + #define R_CPU_CTRL_CPU0STATM_SLEEPING_Msk (0x1UL) /*!< SLEEPING (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0STATM_SLEEPDEEP_Pos (1UL) /*!< SLEEPDEEP (Bit 1) */ + #define R_CPU_CTRL_CPU0STATM_SLEEPDEEP_Msk (0x2UL) /*!< SLEEPDEEP (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0STATM_SAHBSTP_Pos (4UL) /*!< SAHBSTP (Bit 4) */ + #define R_CPU_CTRL_CPU0STATM_SAHBSTP_Msk (0x10UL) /*!< SAHBSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU1STATM ======================================================= */ + #define R_CPU_CTRL_CPU1STATM_SLEEPING_Pos (0UL) /*!< SLEEPING (Bit 0) */ + #define R_CPU_CTRL_CPU1STATM_SLEEPING_Msk (0x1UL) /*!< SLEEPING (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1STATM_SLEEPDEEP_Pos (1UL) /*!< SLEEPDEEP (Bit 1) */ + #define R_CPU_CTRL_CPU1STATM_SLEEPDEEP_Msk (0x2UL) /*!< SLEEPDEEP (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1STATM_SAHBSTP_Pos (4UL) /*!< SAHBSTP (Bit 4) */ + #define R_CPU_CTRL_CPU1STATM_SAHBSTP_Msk (0x10UL) /*!< SAHBSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= SECEXTMON ======================================================= */ + #define R_CPU_CTRL_SECEXTMON_SECEXT_Pos (0UL) /*!< SECEXT (Bit 0) */ + #define R_CPU_CTRL_SECEXTMON_SECEXT_Msk (0x1UL) /*!< SECEXT (Bitfield-Mask: 0x01) */ +/* ======================================================== NSCPUCR ======================================================== */ + #define R_CPU_CTRL_NSCPUCR_RSTREQEN_Pos (0UL) /*!< RSTREQEN (Bit 0) */ + #define R_CPU_CTRL_NSCPUCR_RSTREQEN_Msk (0x1UL) /*!< RSTREQEN (Bitfield-Mask: 0x01) */ +/* ====================================================== CPU0LOCKCR ======================================================= */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKSVTAIR_Pos (0UL) /*!< LCKSVTAIR (Bit 0) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKSVTAIR_Msk (0x1UL) /*!< LCKSVTAIR (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKSMPU_Pos (1UL) /*!< LCKSMPU (Bit 1) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKSMPU_Msk (0x2UL) /*!< LCKSMPU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKSAU_Pos (2UL) /*!< LCKSAU (Bit 2) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKSAU_Msk (0x4UL) /*!< LCKSAU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKITGU_Pos (3UL) /*!< LCKITGU (Bit 3) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKITGU_Msk (0x8UL) /*!< LCKITGU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKDTGU_Pos (4UL) /*!< LCKDTGU (Bit 4) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKDTGU_Msk (0x10UL) /*!< LCKDTGU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKDCAIC_Pos (5UL) /*!< LCKDCAIC (Bit 5) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKDCAIC_Msk (0x20UL) /*!< LCKDCAIC (Bitfield-Mask: 0x01) */ +/* ====================================================== CPU1LOCKCR ======================================================= */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKSVTAIR_Pos (0UL) /*!< LCKSVTAIR (Bit 0) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKSVTAIR_Msk (0x1UL) /*!< LCKSVTAIR (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKSMPU_Pos (1UL) /*!< LCKSMPU (Bit 1) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKSMPU_Msk (0x2UL) /*!< LCKSMPU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKSAU_Pos (2UL) /*!< LCKSAU (Bit 2) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKSAU_Msk (0x4UL) /*!< LCKSAU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKITGU_Pos (3UL) /*!< LCKITGU (Bit 3) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKITGU_Msk (0x8UL) /*!< LCKITGU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKDTGU_Pos (4UL) /*!< LCKDTGU (Bit 4) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKDTGU_Msk (0x10UL) /*!< LCKDTGU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKDCAIC_Pos (5UL) /*!< LCKDCAIC (Bit 5) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKDCAIC_Msk (0x20UL) /*!< LCKDCAIC (Bitfield-Mask: 0x01) */ +/* ===================================================== CPU0LOCKCRNS ====================================================== */ + #define R_CPU_CTRL_CPU0LOCKCRNS_LCKNSVTOR_Pos (0UL) /*!< LCKNSVTOR (Bit 0) */ + #define R_CPU_CTRL_CPU0LOCKCRNS_LCKNSVTOR_Msk (0x1UL) /*!< LCKNSVTOR (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0LOCKCRNS_LCKNSMPU_Pos (1UL) /*!< LCKNSMPU (Bit 1) */ + #define R_CPU_CTRL_CPU0LOCKCRNS_LCKNSMPU_Msk (0x2UL) /*!< LCKNSMPU (Bitfield-Mask: 0x01) */ +/* ===================================================== CPU1LOCKCRNS ====================================================== */ + #define R_CPU_CTRL_CPU1LOCKCRNS_LCKNSVTOR_Pos (0UL) /*!< LCKNSVTOR (Bit 0) */ + #define R_CPU_CTRL_CPU1LOCKCRNS_LCKNSVTOR_Msk (0x1UL) /*!< LCKNSVTOR (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1LOCKCRNS_LCKNSMPU_Pos (1UL) /*!< LCKNSMPU (Bit 1) */ + #define R_CPU_CTRL_CPU1LOCKCRNS_LCKNSMPU_Msk (0x2UL) /*!< LCKNSMPU (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0CRPT ======================================================== */ + #define R_CPU_CTRL_CPU0CRPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_CPU_CTRL_CPU0CRPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0CRPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CPU_CTRL_CPU0CRPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CPU1CRPT ======================================================== */ + #define R_CPU_CTRL_CPU1CRPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_CPU_CTRL_CPU1CRPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1CRPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CPU_CTRL_CPU1CRPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= EC710CTL ======================================================== */ + #define R_ECCMB0_EC710CTL_ECEMF_Pos (0UL) /*!< ECEMF (Bit 0) */ + #define R_ECCMB0_EC710CTL_ECEMF_Msk (0x1UL) /*!< ECEMF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1F_Pos (1UL) /*!< ECER1F (Bit 1) */ + #define R_ECCMB0_EC710CTL_ECER1F_Msk (0x2UL) /*!< ECER1F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2F_Pos (2UL) /*!< ECER2F (Bit 2) */ + #define R_ECCMB0_EC710CTL_ECER2F_Msk (0x4UL) /*!< ECER2F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Pos (3UL) /*!< EC1EDIC (Bit 3) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Msk (0x8UL) /*!< EC1EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Pos (4UL) /*!< EC2EDIC (Bit 4) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Msk (0x10UL) /*!< EC2EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Pos (5UL) /*!< EC1ECP (Bit 5) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Msk (0x20UL) /*!< EC1ECP (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECERVF_Pos (6UL) /*!< ECERVF (Bit 6) */ + #define R_ECCMB0_EC710CTL_ECERVF_Msk (0x40UL) /*!< ECERVF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1C_Pos (9UL) /*!< ECER1C (Bit 9) */ + #define R_ECCMB0_EC710CTL_ECER1C_Msk (0x200UL) /*!< ECER1C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2C_Pos (10UL) /*!< ECER2C (Bit 10) */ + #define R_ECCMB0_EC710CTL_ECER2C_Msk (0x400UL) /*!< ECER2C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Pos (11UL) /*!< ECOVFF (Bit 11) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Msk (0x800UL) /*!< ECOVFF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EMCA_Pos (14UL) /*!< EMCA (Bit 14) */ + #define R_ECCMB0_EC710CTL_EMCA_Msk (0xc000UL) /*!< EMCA (Bitfield-Mask: 0x03) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Pos (16UL) /*!< ECSEDF0 (Bit 16) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Msk (0x10000UL) /*!< ECSEDF0 (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Pos (17UL) /*!< ECDEDF0 (Bit 17) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Msk (0x20000UL) /*!< ECDEDF0 (Bitfield-Mask: 0x01) */ +/* ======================================================= EC710TMC ======================================================== */ + #define R_ECCMB0_EC710TMC_ECDCS_Pos (1UL) /*!< ECDCS (Bit 1) */ + #define R_ECCMB0_EC710TMC_ECDCS_Msk (0x2UL) /*!< ECDCS (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Pos (7UL) /*!< ECTMCE (Bit 7) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Msk (0x80UL) /*!< ECTMCE (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ETMA_Pos (14UL) /*!< ETMA (Bit 14) */ + #define R_ECCMB0_EC710TMC_ETMA_Msk (0xc000UL) /*!< ETMA (Bitfield-Mask: 0x03) */ +/* ======================================================= EC710TED ======================================================== */ + #define R_ECCMB0_EC710TED_ECEDB_Pos (0UL) /*!< ECEDB (Bit 0) */ + #define R_ECCMB0_EC710TED_ECEDB_Msk (0xffffffffUL) /*!< ECEDB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EC710EAD0 ======================================================= */ + #define R_ECCMB0_EC710EAD0_ECEAD_Pos (0UL) /*!< ECEAD (Bit 0) */ + #define R_ECCMB0_EC710EAD0_ECEAD_Msk (0x3ffUL) /*!< ECEAD (Bitfield-Mask: 0x3ff) */ + +/* =========================================================================================================================== */ +/* ================ R_ESWM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= TPEMIMC0 ======================================================== */ + #define R_ESWM_TPEMIMC0_SEIM_Pos (0UL) /*!< SEIM (Bit 0) */ + #define R_ESWM_TPEMIMC0_SEIM_Msk (0x1UL) /*!< SEIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC0_SEIGM_Pos (1UL) /*!< SEIGM (Bit 1) */ + #define R_ESWM_TPEMIMC0_SEIGM_Msk (0x2UL) /*!< SEIGM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC0_SEICM_Pos (4UL) /*!< SEICM (Bit 4) */ + #define R_ESWM_TPEMIMC0_SEICM_Msk (0x70UL) /*!< SEICM (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC0_SSIM_Pos (16UL) /*!< SSIM (Bit 16) */ + #define R_ESWM_TPEMIMC0_SSIM_Msk (0x10000UL) /*!< SSIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC0_SSIGM_Pos (17UL) /*!< SSIGM (Bit 17) */ + #define R_ESWM_TPEMIMC0_SSIGM_Msk (0x20000UL) /*!< SSIGM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC0_SSICM_Pos (20UL) /*!< SSICM (Bit 20) */ + #define R_ESWM_TPEMIMC0_SSICM_Msk (0x700000UL) /*!< SSICM (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC1 ======================================================== */ + #define R_ESWM_TPEMIMC1_FEIM_Pos (0UL) /*!< FEIM (Bit 0) */ + #define R_ESWM_TPEMIMC1_FEIM_Msk (0x1UL) /*!< FEIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_FEIGM_Pos (1UL) /*!< FEIGM (Bit 1) */ + #define R_ESWM_TPEMIMC1_FEIGM_Msk (0x2UL) /*!< FEIGM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_FEICM_Pos (4UL) /*!< FEICM (Bit 4) */ + #define R_ESWM_TPEMIMC1_FEICM_Msk (0x70UL) /*!< FEICM (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC1_FSIM_Pos (8UL) /*!< FSIM (Bit 8) */ + #define R_ESWM_TPEMIMC1_FSIM_Msk (0x100UL) /*!< FSIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_FSIGM_Pos (9UL) /*!< FSIGM (Bit 9) */ + #define R_ESWM_TPEMIMC1_FSIGM_Msk (0x200UL) /*!< FSIGM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_FSICM_Pos (12UL) /*!< FSICM (Bit 12) */ + #define R_ESWM_TPEMIMC1_FSICM_Msk (0x7000UL) /*!< FSICM (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC1_CEIM_Pos (16UL) /*!< CEIM (Bit 16) */ + #define R_ESWM_TPEMIMC1_CEIM_Msk (0x10000UL) /*!< CEIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_CEIGM_Pos (17UL) /*!< CEIGM (Bit 17) */ + #define R_ESWM_TPEMIMC1_CEIGM_Msk (0x20000UL) /*!< CEIGM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_CEICM_Pos (20UL) /*!< CEICM (Bit 20) */ + #define R_ESWM_TPEMIMC1_CEICM_Msk (0x700000UL) /*!< CEICM (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC1_CSIM_Pos (24UL) /*!< CSIM (Bit 24) */ + #define R_ESWM_TPEMIMC1_CSIM_Msk (0x1000000UL) /*!< CSIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_CSIGM_Pos (25UL) /*!< CSIGM (Bit 25) */ + #define R_ESWM_TPEMIMC1_CSIGM_Msk (0x2000000UL) /*!< CSIGM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_CSICM_Pos (28UL) /*!< CSICM (Bit 28) */ + #define R_ESWM_TPEMIMC1_CSICM_Msk (0x70000000UL) /*!< CSICM (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC2 ======================================================== */ + #define R_ESWM_TPEMIMC2_GEIM0_Pos (0UL) /*!< GEIM0 (Bit 0) */ + #define R_ESWM_TPEMIMC2_GEIM0_Msk (0x1UL) /*!< GEIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC2_GEIGM0_Pos (1UL) /*!< GEIGM0 (Bit 1) */ + #define R_ESWM_TPEMIMC2_GEIGM0_Msk (0x2UL) /*!< GEIGM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC2_GEICM0_Pos (4UL) /*!< GEICM0 (Bit 4) */ + #define R_ESWM_TPEMIMC2_GEICM0_Msk (0x70UL) /*!< GEICM0 (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC2_GSIM0_Pos (8UL) /*!< GSIM0 (Bit 8) */ + #define R_ESWM_TPEMIMC2_GSIM0_Msk (0x100UL) /*!< GSIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC2_GSIGM0_Pos (9UL) /*!< GSIGM0 (Bit 9) */ + #define R_ESWM_TPEMIMC2_GSIGM0_Msk (0x200UL) /*!< GSIGM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC2_GSICM0_Pos (12UL) /*!< GSICM0 (Bit 12) */ + #define R_ESWM_TPEMIMC2_GSICM0_Msk (0x7000UL) /*!< GSICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC3 ======================================================== */ + #define R_ESWM_TPEMIMC3_EEIM0_Pos (0UL) /*!< EEIM0 (Bit 0) */ + #define R_ESWM_TPEMIMC3_EEIM0_Msk (0x1UL) /*!< EEIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC3_EEIGM0_Pos (1UL) /*!< EEIGM0 (Bit 1) */ + #define R_ESWM_TPEMIMC3_EEIGM0_Msk (0x2UL) /*!< EEIGM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC3_EEICM0_Pos (4UL) /*!< EEICM0 (Bit 4) */ + #define R_ESWM_TPEMIMC3_EEICM0_Msk (0x70UL) /*!< EEICM0 (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC3_ESIM0_Pos (8UL) /*!< ESIM0 (Bit 8) */ + #define R_ESWM_TPEMIMC3_ESIM0_Msk (0x100UL) /*!< ESIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC3_ESIGM0_Pos (9UL) /*!< ESIGM0 (Bit 9) */ + #define R_ESWM_TPEMIMC3_ESIGM0_Msk (0x200UL) /*!< ESIGM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC3_ESICM0_Pos (12UL) /*!< ESICM0 (Bit 12) */ + #define R_ESWM_TPEMIMC3_ESICM0_Msk (0x7000UL) /*!< ESICM0 (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC3_RSIM0_Pos (16UL) /*!< RSIM0 (Bit 16) */ + #define R_ESWM_TPEMIMC3_RSIM0_Msk (0x10000UL) /*!< RSIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC3_RSIGM0_Pos (17UL) /*!< RSIGM0 (Bit 17) */ + #define R_ESWM_TPEMIMC3_RSIGM0_Msk (0x20000UL) /*!< RSIGM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC3_RSICM0_Pos (20UL) /*!< RSICM0 (Bit 20) */ + #define R_ESWM_TPEMIMC3_RSICM0_Msk (0x700000UL) /*!< RSICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC4 ======================================================== */ + #define R_ESWM_TPEMIMC4_EEIM1_Pos (0UL) /*!< EEIM1 (Bit 0) */ + #define R_ESWM_TPEMIMC4_EEIM1_Msk (0x1UL) /*!< EEIM1 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC4_EEIGM1_Pos (1UL) /*!< EEIGM1 (Bit 1) */ + #define R_ESWM_TPEMIMC4_EEIGM1_Msk (0x2UL) /*!< EEIGM1 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC4_EEICM1_Pos (4UL) /*!< EEICM1 (Bit 4) */ + #define R_ESWM_TPEMIMC4_EEICM1_Msk (0x70UL) /*!< EEICM1 (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC4_ESIM1_Pos (8UL) /*!< ESIM1 (Bit 8) */ + #define R_ESWM_TPEMIMC4_ESIM1_Msk (0x100UL) /*!< ESIM1 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC4_ESIGM1_Pos (9UL) /*!< ESIGM1 (Bit 9) */ + #define R_ESWM_TPEMIMC4_ESIGM1_Msk (0x200UL) /*!< ESIGM1 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC4_ESICM1_Pos (12UL) /*!< ESICM1 (Bit 12) */ + #define R_ESWM_TPEMIMC4_ESICM1_Msk (0x7000UL) /*!< ESICM1 (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC4_RSIM1_Pos (16UL) /*!< RSIM1 (Bit 16) */ + #define R_ESWM_TPEMIMC4_RSIM1_Msk (0x10000UL) /*!< RSIM1 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC4_RSIGM1_Pos (17UL) /*!< RSIGM1 (Bit 17) */ + #define R_ESWM_TPEMIMC4_RSIGM1_Msk (0x20000UL) /*!< RSIGM1 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC4_RSICM1_Pos (20UL) /*!< RSICM1 (Bit 20) */ + #define R_ESWM_TPEMIMC4_RSICM1_Msk (0x700000UL) /*!< RSICM1 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC60 ======================================================= */ + #define R_ESWM_TPEMIMC60_GTSIM0_Pos (0UL) /*!< GTSIM0 (Bit 0) */ + #define R_ESWM_TPEMIMC60_GTSIM0_Msk (0x1UL) /*!< GTSIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC60_GTSICM0_Pos (1UL) /*!< GTSICM0 (Bit 1) */ + #define R_ESWM_TPEMIMC60_GTSICM0_Msk (0xeUL) /*!< GTSICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC61 ======================================================= */ + #define R_ESWM_TPEMIMC61_GTSIM0_Pos (0UL) /*!< GTSIM0 (Bit 0) */ + #define R_ESWM_TPEMIMC61_GTSIM0_Msk (0x1UL) /*!< GTSIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC61_GTSICM0_Pos (1UL) /*!< GTSICM0 (Bit 1) */ + #define R_ESWM_TPEMIMC61_GTSICM0_Msk (0xeUL) /*!< GTSICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC62 ======================================================= */ + #define R_ESWM_TPEMIMC62_GTSIM0_Pos (0UL) /*!< GTSIM0 (Bit 0) */ + #define R_ESWM_TPEMIMC62_GTSIM0_Msk (0x1UL) /*!< GTSIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC62_GTSICM0_Pos (1UL) /*!< GTSICM0 (Bit 1) */ + #define R_ESWM_TPEMIMC62_GTSICM0_Msk (0xeUL) /*!< GTSICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC63 ======================================================= */ + #define R_ESWM_TPEMIMC63_GTSIM0_Pos (0UL) /*!< GTSIM0 (Bit 0) */ + #define R_ESWM_TPEMIMC63_GTSIM0_Msk (0x1UL) /*!< GTSIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC63_GTSICM0_Pos (1UL) /*!< GTSICM0 (Bit 1) */ + #define R_ESWM_TPEMIMC63_GTSICM0_Msk (0xeUL) /*!< GTSICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC64 ======================================================= */ + #define R_ESWM_TPEMIMC64_GTSIM0_Pos (0UL) /*!< GTSIM0 (Bit 0) */ + #define R_ESWM_TPEMIMC64_GTSIM0_Msk (0x1UL) /*!< GTSIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC64_GTSICM0_Pos (1UL) /*!< GTSICM0 (Bit 1) */ + #define R_ESWM_TPEMIMC64_GTSICM0_Msk (0xeUL) /*!< GTSICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC70 ======================================================= */ + #define R_ESWM_TPEMIMC70_GDICM0_Pos (0UL) /*!< GDICM0 (Bit 0) */ + #define R_ESWM_TPEMIMC70_GDICM0_Msk (0x7UL) /*!< GDICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC71 ======================================================= */ + #define R_ESWM_TPEMIMC71_GDICM0_Pos (0UL) /*!< GDICM0 (Bit 0) */ + #define R_ESWM_TPEMIMC71_GDICM0_Msk (0x7UL) /*!< GDICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC72 ======================================================= */ + #define R_ESWM_TPEMIMC72_GDICM0_Pos (0UL) /*!< GDICM0 (Bit 0) */ + #define R_ESWM_TPEMIMC72_GDICM0_Msk (0x7UL) /*!< GDICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC73 ======================================================= */ + #define R_ESWM_TPEMIMC73_GDICM0_Pos (0UL) /*!< GDICM0 (Bit 0) */ + #define R_ESWM_TPEMIMC73_GDICM0_Msk (0x7UL) /*!< GDICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC74 ======================================================= */ + #define R_ESWM_TPEMIMC74_GDICM0_Pos (0UL) /*!< GDICM0 (Bit 0) */ + #define R_ESWM_TPEMIMC74_GDICM0_Msk (0x7UL) /*!< GDICM0 (Bitfield-Mask: 0x07) */ +/* ========================================================= TSIM ========================================================== */ + #define R_ESWM_TSIM_FIM_Pos (0UL) /*!< FIM (Bit 0) */ + #define R_ESWM_TSIM_FIM_Msk (0x1UL) /*!< FIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TSIM_CIM_Pos (1UL) /*!< CIM (Bit 1) */ + #define R_ESWM_TSIM_CIM_Msk (0x2UL) /*!< CIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TSIM_GIM_Pos (2UL) /*!< GIM (Bit 2) */ + #define R_ESWM_TSIM_GIM_Msk (0x4UL) /*!< GIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TSIM_EIM_Pos (4UL) /*!< EIM (Bit 4) */ + #define R_ESWM_TSIM_EIM_Msk (0x10UL) /*!< EIM (Bitfield-Mask: 0x01) */ +/* ========================================================= TFIM ========================================================== */ + #define R_ESWM_TFIM_FWEISIM_Pos (0UL) /*!< FWEISIM (Bit 0) */ + #define R_ESWM_TFIM_FWEISIM_Msk (0x1UL) /*!< FWEISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TFIM_FWMISIM0_Pos (9UL) /*!< FWMISIM0 (Bit 9) */ + #define R_ESWM_TFIM_FWMISIM0_Msk (0x200UL) /*!< FWMISIM0 (Bitfield-Mask: 0x01) */ +/* ========================================================= TCIM ========================================================== */ + #define R_ESWM_TCIM_RSSISIM_Pos (0UL) /*!< RSSISIM (Bit 0) */ + #define R_ESWM_TCIM_RSSISIM_Msk (0x1UL) /*!< RSSISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TCIM_CAEISIM_Pos (1UL) /*!< CAEISIM (Bit 1) */ + #define R_ESWM_TCIM_CAEISIM_Msk (0x2UL) /*!< CAEISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TCIM_CAMISIM_Pos (3UL) /*!< CAMISIM (Bit 3) */ + #define R_ESWM_TCIM_CAMISIM_Msk (0x8UL) /*!< CAMISIM (Bitfield-Mask: 0x01) */ +/* ========================================================= TGIM0 ========================================================= */ + #define R_ESWM_TGIM0_GWDISIM_Pos (0UL) /*!< GWDISIM (Bit 0) */ + #define R_ESWM_TGIM0_GWDISIM_Msk (0x1UL) /*!< GWDISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TGIM0_GWTSDISIM_Pos (1UL) /*!< GWTSDISIM (Bit 1) */ + #define R_ESWM_TGIM0_GWTSDISIM_Msk (0x2UL) /*!< GWTSDISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TGIM0_GWEISIM_Pos (2UL) /*!< GWEISIM (Bit 2) */ + #define R_ESWM_TGIM0_GWEISIM_Msk (0x4UL) /*!< GWEISIM (Bitfield-Mask: 0x01) */ +/* ========================================================= TEIM0 ========================================================= */ + #define R_ESWM_TEIM0_EAEISIM_Pos (0UL) /*!< EAEISIM (Bit 0) */ + #define R_ESWM_TEIM0_EAEISIM_Msk (0x1UL) /*!< EAEISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TEIM0_MEISIM_Pos (3UL) /*!< MEISIM (Bit 3) */ + #define R_ESWM_TEIM0_MEISIM_Msk (0x8UL) /*!< MEISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TEIM0_MMISIM_Pos (4UL) /*!< MMISIM (Bit 4) */ + #define R_ESWM_TEIM0_MMISIM_Msk (0x10UL) /*!< MMISIM (Bitfield-Mask: 0x01) */ +/* ========================================================= TEIM1 ========================================================= */ + #define R_ESWM_TEIM1_EAEISIM_Pos (0UL) /*!< EAEISIM (Bit 0) */ + #define R_ESWM_TEIM1_EAEISIM_Msk (0x1UL) /*!< EAEISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TEIM1_MEISIM_Pos (3UL) /*!< MEISIM (Bit 3) */ + #define R_ESWM_TEIM1_MEISIM_Msk (0x8UL) /*!< MEISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TEIM1_MMISIM_Pos (4UL) /*!< MMISIM (Bit 4) */ + #define R_ESWM_TEIM1_MMISIM_Msk (0x10UL) /*!< MMISIM (Bitfield-Mask: 0x01) */ +/* ========================================================= MIIRR ========================================================= */ + #define R_ESWM_MIIRR_RGRST_Pos (0UL) /*!< RGRST (Bit 0) */ + #define R_ESWM_MIIRR_RGRST_Msk (0x1UL) /*!< RGRST (Bitfield-Mask: 0x01) */ + #define R_ESWM_MIIRR_RMRST_Pos (8UL) /*!< RMRST (Bit 8) */ + #define R_ESWM_MIIRR_RMRST_Msk (0x100UL) /*!< RMRST (Bitfield-Mask: 0x01) */ +/* ======================================================== MIICR0 ========================================================= */ + #define R_ESWM_MIICR0_MIISEL_Pos (0UL) /*!< MIISEL (Bit 0) */ + #define R_ESWM_MIICR0_MIISEL_Msk (0x3UL) /*!< MIISEL (Bitfield-Mask: 0x03) */ + #define R_ESWM_MIICR0_DIVSTP_Pos (8UL) /*!< DIVSTP (Bit 8) */ + #define R_ESWM_MIICR0_DIVSTP_Msk (0x100UL) /*!< DIVSTP (Bitfield-Mask: 0x01) */ + #define R_ESWM_MIICR0_TXCIDE_Pos (12UL) /*!< TXCIDE (Bit 12) */ + #define R_ESWM_MIICR0_TXCIDE_Msk (0x1000UL) /*!< TXCIDE (Bitfield-Mask: 0x01) */ +/* ======================================================== MIICR1 ========================================================= */ + #define R_ESWM_MIICR1_MIISEL_Pos (0UL) /*!< MIISEL (Bit 0) */ + #define R_ESWM_MIICR1_MIISEL_Msk (0x3UL) /*!< MIISEL (Bitfield-Mask: 0x03) */ + #define R_ESWM_MIICR1_DIVSTP_Pos (8UL) /*!< DIVSTP (Bit 8) */ + #define R_ESWM_MIICR1_DIVSTP_Msk (0x100UL) /*!< DIVSTP (Bitfield-Mask: 0x01) */ + #define R_ESWM_MIICR1_TXCIDE_Pos (12UL) /*!< TXCIDE (Bit 12) */ + #define R_ESWM_MIICR1_TXCIDE_Msk (0x1000UL) /*!< TXCIDE (Bitfield-Mask: 0x01) */ +/* ======================================================== MCCESR ========================================================= */ + #define R_ESWM_MCCESR_MCCES_Pos (0UL) /*!< MCCES (Bit 0) */ + #define R_ESWM_MCCESR_MCCES_Msk (0x1UL) /*!< MCCES (Bitfield-Mask: 0x01) */ +/* ======================================================== TASSTSR ======================================================== */ + #define R_ESWM_TASSTSR_MSS_Pos (0UL) /*!< MSS (Bit 0) */ + #define R_ESWM_TASSTSR_MSS_Msk (0x1fUL) /*!< MSS (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHA0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= EAMC ========================================================== */ + #define R_ETHA0_EAMC_OPC_Pos (0UL) /*!< OPC (Bit 0) */ + #define R_ETHA0_EAMC_OPC_Msk (0x3UL) /*!< OPC (Bitfield-Mask: 0x03) */ +/* ========================================================= EAMS ========================================================== */ + #define R_ETHA0_EAMS_OPS_Pos (0UL) /*!< OPS (Bit 0) */ + #define R_ETHA0_EAMS_OPS_Msk (0x3UL) /*!< OPS (Bitfield-Mask: 0x03) */ +/* ========================================================= EAIRC ========================================================= */ + #define R_ETHA0_EAIRC_IPVR0_Pos (0UL) /*!< IPVR0 (Bit 0) */ + #define R_ETHA0_EAIRC_IPVR0_Msk (0x7UL) /*!< IPVR0 (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAIRC_IPVR1_Pos (4UL) /*!< IPVR1 (Bit 4) */ + #define R_ETHA0_EAIRC_IPVR1_Msk (0x70UL) /*!< IPVR1 (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAIRC_IPVR2_Pos (8UL) /*!< IPVR2 (Bit 8) */ + #define R_ETHA0_EAIRC_IPVR2_Msk (0x700UL) /*!< IPVR2 (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAIRC_IPVR3_Pos (12UL) /*!< IPVR3 (Bit 12) */ + #define R_ETHA0_EAIRC_IPVR3_Msk (0x7000UL) /*!< IPVR3 (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAIRC_IPVR4_Pos (16UL) /*!< IPVR4 (Bit 16) */ + #define R_ETHA0_EAIRC_IPVR4_Msk (0x70000UL) /*!< IPVR4 (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAIRC_IPVR5_Pos (20UL) /*!< IPVR5 (Bit 20) */ + #define R_ETHA0_EAIRC_IPVR5_Msk (0x700000UL) /*!< IPVR5 (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAIRC_IPVR6_Pos (24UL) /*!< IPVR6 (Bit 24) */ + #define R_ETHA0_EAIRC_IPVR6_Msk (0x7000000UL) /*!< IPVR6 (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAIRC_IPVR7_Pos (28UL) /*!< IPVR7 (Bit 28) */ + #define R_ETHA0_EAIRC_IPVR7_Msk (0x70000000UL) /*!< IPVR7 (Bitfield-Mask: 0x07) */ +/* ======================================================== EATDQSC ======================================================== */ + #define R_ETHA0_EATDQSC_TDQSL0_Pos (0UL) /*!< TDQSL0 (Bit 0) */ + #define R_ETHA0_EATDQSC_TDQSL0_Msk (0x1UL) /*!< TDQSL0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQSC_TDQSL1_Pos (1UL) /*!< TDQSL1 (Bit 1) */ + #define R_ETHA0_EATDQSC_TDQSL1_Msk (0x2UL) /*!< TDQSL1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQSC_TDQSL2_Pos (2UL) /*!< TDQSL2 (Bit 2) */ + #define R_ETHA0_EATDQSC_TDQSL2_Msk (0x4UL) /*!< TDQSL2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQSC_TDQSL3_Pos (3UL) /*!< TDQSL3 (Bit 3) */ + #define R_ETHA0_EATDQSC_TDQSL3_Msk (0x8UL) /*!< TDQSL3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQSC_TDQSL4_Pos (4UL) /*!< TDQSL4 (Bit 4) */ + #define R_ETHA0_EATDQSC_TDQSL4_Msk (0x10UL) /*!< TDQSL4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQSC_TDQSL5_Pos (5UL) /*!< TDQSL5 (Bit 5) */ + #define R_ETHA0_EATDQSC_TDQSL5_Msk (0x20UL) /*!< TDQSL5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQSC_TDQSL6_Pos (6UL) /*!< TDQSL6 (Bit 6) */ + #define R_ETHA0_EATDQSC_TDQSL6_Msk (0x40UL) /*!< TDQSL6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQSC_TDQSL7_Pos (7UL) /*!< TDQSL7 (Bit 7) */ + #define R_ETHA0_EATDQSC_TDQSL7_Msk (0x80UL) /*!< TDQSL7 (Bitfield-Mask: 0x01) */ +/* ======================================================== EATDQC ========================================================= */ + #define R_ETHA0_EATDQC_TDQD0_Pos (0UL) /*!< TDQD0 (Bit 0) */ + #define R_ETHA0_EATDQC_TDQD0_Msk (0x1UL) /*!< TDQD0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQD1_Pos (1UL) /*!< TDQD1 (Bit 1) */ + #define R_ETHA0_EATDQC_TDQD1_Msk (0x2UL) /*!< TDQD1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQD2_Pos (2UL) /*!< TDQD2 (Bit 2) */ + #define R_ETHA0_EATDQC_TDQD2_Msk (0x4UL) /*!< TDQD2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQD3_Pos (3UL) /*!< TDQD3 (Bit 3) */ + #define R_ETHA0_EATDQC_TDQD3_Msk (0x8UL) /*!< TDQD3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQD4_Pos (4UL) /*!< TDQD4 (Bit 4) */ + #define R_ETHA0_EATDQC_TDQD4_Msk (0x10UL) /*!< TDQD4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQD5_Pos (5UL) /*!< TDQD5 (Bit 5) */ + #define R_ETHA0_EATDQC_TDQD5_Msk (0x20UL) /*!< TDQD5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQD6_Pos (6UL) /*!< TDQD6 (Bit 6) */ + #define R_ETHA0_EATDQC_TDQD6_Msk (0x40UL) /*!< TDQD6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQD7_Pos (7UL) /*!< TDQD7 (Bit 7) */ + #define R_ETHA0_EATDQC_TDQD7_Msk (0x80UL) /*!< TDQD7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TCTDQD_Pos (8UL) /*!< TCTDQD (Bit 8) */ + #define R_ETHA0_EATDQC_TCTDQD_Msk (0x100UL) /*!< TCTDQD (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP0_Pos (16UL) /*!< TDQP0 (Bit 16) */ + #define R_ETHA0_EATDQC_TDQP0_Msk (0x10000UL) /*!< TDQP0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP1_Pos (17UL) /*!< TDQP1 (Bit 17) */ + #define R_ETHA0_EATDQC_TDQP1_Msk (0x20000UL) /*!< TDQP1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP2_Pos (18UL) /*!< TDQP2 (Bit 18) */ + #define R_ETHA0_EATDQC_TDQP2_Msk (0x40000UL) /*!< TDQP2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP3_Pos (19UL) /*!< TDQP3 (Bit 19) */ + #define R_ETHA0_EATDQC_TDQP3_Msk (0x80000UL) /*!< TDQP3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP4_Pos (20UL) /*!< TDQP4 (Bit 20) */ + #define R_ETHA0_EATDQC_TDQP4_Msk (0x100000UL) /*!< TDQP4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP5_Pos (21UL) /*!< TDQP5 (Bit 21) */ + #define R_ETHA0_EATDQC_TDQP5_Msk (0x200000UL) /*!< TDQP5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP6_Pos (22UL) /*!< TDQP6 (Bit 22) */ + #define R_ETHA0_EATDQC_TDQP6_Msk (0x400000UL) /*!< TDQP6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP7_Pos (23UL) /*!< TDQP7 (Bit 23) */ + #define R_ETHA0_EATDQC_TDQP7_Msk (0x800000UL) /*!< TDQP7 (Bitfield-Mask: 0x01) */ +/* ======================================================== EATDQAC ======================================================== */ + #define R_ETHA0_EATDQAC_TDQA0_Pos (0UL) /*!< TDQA0 (Bit 0) */ + #define R_ETHA0_EATDQAC_TDQA0_Msk (0xfUL) /*!< TDQA0 (Bitfield-Mask: 0x0f) */ + #define R_ETHA0_EATDQAC_TDQA1_Pos (4UL) /*!< TDQA1 (Bit 4) */ + #define R_ETHA0_EATDQAC_TDQA1_Msk (0xf0UL) /*!< TDQA1 (Bitfield-Mask: 0x0f) */ + #define R_ETHA0_EATDQAC_TDQA2_Pos (8UL) /*!< TDQA2 (Bit 8) */ + #define R_ETHA0_EATDQAC_TDQA2_Msk (0xf00UL) /*!< TDQA2 (Bitfield-Mask: 0x0f) */ + #define R_ETHA0_EATDQAC_TDQA3_Pos (12UL) /*!< TDQA3 (Bit 12) */ + #define R_ETHA0_EATDQAC_TDQA3_Msk (0xf000UL) /*!< TDQA3 (Bitfield-Mask: 0x0f) */ + #define R_ETHA0_EATDQAC_TDQA4_Pos (16UL) /*!< TDQA4 (Bit 16) */ + #define R_ETHA0_EATDQAC_TDQA4_Msk (0xf0000UL) /*!< TDQA4 (Bitfield-Mask: 0x0f) */ + #define R_ETHA0_EATDQAC_TDQA5_Pos (20UL) /*!< TDQA5 (Bit 20) */ + #define R_ETHA0_EATDQAC_TDQA5_Msk (0xf00000UL) /*!< TDQA5 (Bitfield-Mask: 0x0f) */ + #define R_ETHA0_EATDQAC_TDQA6_Pos (24UL) /*!< TDQA6 (Bit 24) */ + #define R_ETHA0_EATDQAC_TDQA6_Msk (0xf000000UL) /*!< TDQA6 (Bitfield-Mask: 0x0f) */ + #define R_ETHA0_EATDQAC_TDQA7_Pos (28UL) /*!< TDQA7 (Bit 28) */ + #define R_ETHA0_EATDQAC_TDQA7_Msk (0xf0000000UL) /*!< TDQA7 (Bitfield-Mask: 0x0f) */ +/* ======================================================== EATPEC ========================================================= */ + #define R_ETHA0_EATPEC_TTQ0_Pos (0UL) /*!< TTQ0 (Bit 0) */ + #define R_ETHA0_EATPEC_TTQ0_Msk (0x1UL) /*!< TTQ0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ1_Pos (1UL) /*!< TTQ1 (Bit 1) */ + #define R_ETHA0_EATPEC_TTQ1_Msk (0x2UL) /*!< TTQ1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ2_Pos (2UL) /*!< TTQ2 (Bit 2) */ + #define R_ETHA0_EATPEC_TTQ2_Msk (0x4UL) /*!< TTQ2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ3_Pos (3UL) /*!< TTQ3 (Bit 3) */ + #define R_ETHA0_EATPEC_TTQ3_Msk (0x8UL) /*!< TTQ3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ4_Pos (4UL) /*!< TTQ4 (Bit 4) */ + #define R_ETHA0_EATPEC_TTQ4_Msk (0x10UL) /*!< TTQ4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ5_Pos (5UL) /*!< TTQ5 (Bit 5) */ + #define R_ETHA0_EATPEC_TTQ5_Msk (0x20UL) /*!< TTQ5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ6_Pos (6UL) /*!< TTQ6 (Bit 6) */ + #define R_ETHA0_EATPEC_TTQ6_Msk (0x40UL) /*!< TTQ6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ7_Pos (7UL) /*!< TTQ7 (Bit 7) */ + #define R_ETHA0_EATPEC_TTQ7_Msk (0x80UL) /*!< TTQ7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ8_Pos (8UL) /*!< TTQ8 (Bit 8) */ + #define R_ETHA0_EATPEC_TTQ8_Msk (0x100UL) /*!< TTQ8 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ9_Pos (9UL) /*!< TTQ9 (Bit 9) */ + #define R_ETHA0_EATPEC_TTQ9_Msk (0x200UL) /*!< TTQ9 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_AFS_Pos (16UL) /*!< AFS (Bit 16) */ + #define R_ETHA0_EATPEC_AFS_Msk (0x30000UL) /*!< AFS (Bitfield-Mask: 0x03) */ +/* ======================================================= EATMFSC0 ======================================================== */ + #define R_ETHA0_EATMFSC0_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC0_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATMFSC1 ======================================================== */ + #define R_ETHA0_EATMFSC1_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC1_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATMFSC2 ======================================================== */ + #define R_ETHA0_EATMFSC2_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC2_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATMFSC3 ======================================================== */ + #define R_ETHA0_EATMFSC3_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC3_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATMFSC4 ======================================================== */ + #define R_ETHA0_EATMFSC4_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC4_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATMFSC5 ======================================================== */ + #define R_ETHA0_EATMFSC5_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC5_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATMFSC6 ======================================================== */ + #define R_ETHA0_EATMFSC6_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC6_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATMFSC7 ======================================================== */ + #define R_ETHA0_EATMFSC7_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC7_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATDQDC0 ======================================================== */ + #define R_ETHA0_EATDQDC0_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC0_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQDC1 ======================================================== */ + #define R_ETHA0_EATDQDC1_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC1_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQDC2 ======================================================== */ + #define R_ETHA0_EATDQDC2_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC2_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQDC3 ======================================================== */ + #define R_ETHA0_EATDQDC3_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC3_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQDC4 ======================================================== */ + #define R_ETHA0_EATDQDC4_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC4_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQDC5 ======================================================== */ + #define R_ETHA0_EATDQDC5_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC5_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQDC6 ======================================================== */ + #define R_ETHA0_EATDQDC6_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC6_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQDC7 ======================================================== */ + #define R_ETHA0_EATDQDC7_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC7_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM0 ======================================================== */ + #define R_ETHA0_EATDQM0_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM0_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM1 ======================================================== */ + #define R_ETHA0_EATDQM1_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM1_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM2 ======================================================== */ + #define R_ETHA0_EATDQM2_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM2_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM3 ======================================================== */ + #define R_ETHA0_EATDQM3_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM3_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM4 ======================================================== */ + #define R_ETHA0_EATDQM4_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM4_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM5 ======================================================== */ + #define R_ETHA0_EATDQM5_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM5_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM6 ======================================================== */ + #define R_ETHA0_EATDQM6_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM6_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM7 ======================================================== */ + #define R_ETHA0_EATDQM7_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM7_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM0 ======================================================= */ + #define R_ETHA0_EATDQMLM0_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM0_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM1 ======================================================= */ + #define R_ETHA0_EATDQMLM1_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM1_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM2 ======================================================= */ + #define R_ETHA0_EATDQMLM2_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM2_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM3 ======================================================= */ + #define R_ETHA0_EATDQMLM3_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM3_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM4 ======================================================= */ + #define R_ETHA0_EATDQMLM4_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM4_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM5 ======================================================= */ + #define R_ETHA0_EATDQMLM5_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM5_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM6 ======================================================= */ + #define R_ETHA0_EATDQMLM6_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM6_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM7 ======================================================= */ + #define R_ETHA0_EATDQMLM7_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM7_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EACTQC ========================================================= */ + #define R_ETHA0_EACTQC_CTQD_Pos (0UL) /*!< CTQD (Bit 0) */ + #define R_ETHA0_EACTQC_CTQD_Msk (0xffffUL) /*!< CTQD (Bitfield-Mask: 0xffff) */ +/* ======================================================= EACTDQDC ======================================================== */ + #define R_ETHA0_EACTDQDC_CTDQD_Pos (0UL) /*!< CTDQD (Bit 0) */ + #define R_ETHA0_EACTDQDC_CTDQD_Msk (0xfUL) /*!< CTDQD (Bitfield-Mask: 0x0f) */ +/* ======================================================== EACTDQM ======================================================== */ + #define R_ETHA0_EACTDQM_CTQDN_Pos (0UL) /*!< CTQDN (Bit 0) */ + #define R_ETHA0_EACTDQM_CTQDN_Msk (0x3ffUL) /*!< CTQDN (Bitfield-Mask: 0x3ff) */ +/* ======================================================= EACTDQMLM ======================================================= */ + #define R_ETHA0_EACTDQMLM_CTDMLQ_Pos (0UL) /*!< CTDMLQ (Bit 0) */ + #define R_ETHA0_EACTDQMLM_CTDMLQ_Msk (0xfUL) /*!< CTDMLQ (Bitfield-Mask: 0x0f) */ +/* ========================================================= EAVCC ========================================================= */ + #define R_ETHA0_EAVCC_VIM_Pos (0UL) /*!< VIM (Bit 0) */ + #define R_ETHA0_EAVCC_VIM_Msk (0x1UL) /*!< VIM (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAVCC_VEM_Pos (16UL) /*!< VEM (Bit 16) */ + #define R_ETHA0_EAVCC_VEM_Msk (0x70000UL) /*!< VEM (Bitfield-Mask: 0x07) */ +/* ========================================================= EAVTC ========================================================= */ + #define R_ETHA0_EAVTC_CTV_Pos (0UL) /*!< CTV (Bit 0) */ + #define R_ETHA0_EAVTC_CTV_Msk (0xfffUL) /*!< CTV (Bitfield-Mask: 0xfff) */ + #define R_ETHA0_EAVTC_CTP_Pos (12UL) /*!< CTP (Bit 12) */ + #define R_ETHA0_EAVTC_CTP_Msk (0x7000UL) /*!< CTP (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAVTC_CTD_Pos (15UL) /*!< CTD (Bit 15) */ + #define R_ETHA0_EAVTC_CTD_Msk (0x8000UL) /*!< CTD (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAVTC_STV_Pos (16UL) /*!< STV (Bit 16) */ + #define R_ETHA0_EAVTC_STV_Msk (0xfff0000UL) /*!< STV (Bitfield-Mask: 0xfff) */ + #define R_ETHA0_EAVTC_STP_Pos (28UL) /*!< STP (Bit 28) */ + #define R_ETHA0_EAVTC_STP_Msk (0x70000000UL) /*!< STP (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAVTC_STD_Pos (31UL) /*!< STD (Bit 31) */ + #define R_ETHA0_EAVTC_STD_Msk (0x80000000UL) /*!< STD (Bitfield-Mask: 0x01) */ +/* ======================================================== EARTFC ========================================================= */ + #define R_ETHA0_EARTFC_NT_Pos (0UL) /*!< NT (Bit 0) */ + #define R_ETHA0_EARTFC_NT_Msk (0x1UL) /*!< NT (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_RT_Pos (1UL) /*!< RT (Bit 1) */ + #define R_ETHA0_EARTFC_RT_Msk (0x2UL) /*!< RT (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_CST_Pos (2UL) /*!< CST (Bit 2) */ + #define R_ETHA0_EARTFC_CST_Msk (0x4UL) /*!< CST (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_CSRT_Pos (3UL) /*!< CSRT (Bit 3) */ + #define R_ETHA0_EARTFC_CSRT_Msk (0x8UL) /*!< CSRT (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_CT_Pos (4UL) /*!< CT (Bit 4) */ + #define R_ETHA0_EARTFC_CT_Msk (0x10UL) /*!< CT (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_CRT_Pos (5UL) /*!< CRT (Bit 5) */ + #define R_ETHA0_EARTFC_CRT_Msk (0x20UL) /*!< CRT (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_SCT_Pos (6UL) /*!< SCT (Bit 6) */ + #define R_ETHA0_EARTFC_SCT_Msk (0x40UL) /*!< SCT (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_SCRT_Pos (7UL) /*!< SCRT (Bit 7) */ + #define R_ETHA0_EARTFC_SCRT_Msk (0x80UL) /*!< SCRT (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_UT_Pos (8UL) /*!< UT (Bit 8) */ + #define R_ETHA0_EARTFC_UT_Msk (0x100UL) /*!< UT (Bitfield-Mask: 0x01) */ +/* ======================================================== EACAEC ========================================================= */ + #define R_ETHA0_EACAEC_CE0_Pos (0UL) /*!< CE0 (Bit 0) */ + #define R_ETHA0_EACAEC_CE0_Msk (0x1UL) /*!< CE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACAEC_CE1_Pos (1UL) /*!< CE1 (Bit 1) */ + #define R_ETHA0_EACAEC_CE1_Msk (0x2UL) /*!< CE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACAEC_CE2_Pos (2UL) /*!< CE2 (Bit 2) */ + #define R_ETHA0_EACAEC_CE2_Msk (0x4UL) /*!< CE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACAEC_CE3_Pos (3UL) /*!< CE3 (Bit 3) */ + #define R_ETHA0_EACAEC_CE3_Msk (0x8UL) /*!< CE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACAEC_CE4_Pos (4UL) /*!< CE4 (Bit 4) */ + #define R_ETHA0_EACAEC_CE4_Msk (0x10UL) /*!< CE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACAEC_CE5_Pos (5UL) /*!< CE5 (Bit 5) */ + #define R_ETHA0_EACAEC_CE5_Msk (0x20UL) /*!< CE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACAEC_CE6_Pos (6UL) /*!< CE6 (Bit 6) */ + #define R_ETHA0_EACAEC_CE6_Msk (0x40UL) /*!< CE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACAEC_CE7_Pos (7UL) /*!< CE7 (Bit 7) */ + #define R_ETHA0_EACAEC_CE7_Msk (0x80UL) /*!< CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= EACC ========================================================== */ + #define R_ETHA0_EACC_CC0_Pos (0UL) /*!< CC0 (Bit 0) */ + #define R_ETHA0_EACC_CC0_Msk (0x1UL) /*!< CC0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACC_CC1_Pos (1UL) /*!< CC1 (Bit 1) */ + #define R_ETHA0_EACC_CC1_Msk (0x2UL) /*!< CC1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACC_CC2_Pos (2UL) /*!< CC2 (Bit 2) */ + #define R_ETHA0_EACC_CC2_Msk (0x4UL) /*!< CC2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACC_CC3_Pos (3UL) /*!< CC3 (Bit 3) */ + #define R_ETHA0_EACC_CC3_Msk (0x8UL) /*!< CC3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACC_CC4_Pos (4UL) /*!< CC4 (Bit 4) */ + #define R_ETHA0_EACC_CC4_Msk (0x10UL) /*!< CC4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACC_CC5_Pos (5UL) /*!< CC5 (Bit 5) */ + #define R_ETHA0_EACC_CC5_Msk (0x20UL) /*!< CC5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACC_CC6_Pos (6UL) /*!< CC6 (Bit 6) */ + #define R_ETHA0_EACC_CC6_Msk (0x40UL) /*!< CC6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACC_CC7_Pos (7UL) /*!< CC7 (Bit 7) */ + #define R_ETHA0_EACC_CC7_Msk (0x80UL) /*!< CC7 (Bitfield-Mask: 0x01) */ +/* ======================================================= EACAIVC0 ======================================================== */ + #define R_ETHA0_EACAIVC0_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC0_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAIVC1 ======================================================== */ + #define R_ETHA0_EACAIVC1_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC1_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAIVC2 ======================================================== */ + #define R_ETHA0_EACAIVC2_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC2_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAIVC3 ======================================================== */ + #define R_ETHA0_EACAIVC3_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC3_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAIVC4 ======================================================== */ + #define R_ETHA0_EACAIVC4_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC4_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAIVC5 ======================================================== */ + #define R_ETHA0_EACAIVC5_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC5_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAIVC6 ======================================================== */ + #define R_ETHA0_EACAIVC6_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC6_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAIVC7 ======================================================== */ + #define R_ETHA0_EACAIVC7_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC7_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAULC0 ======================================================== */ + #define R_ETHA0_EACAULC0_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC0_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACAULC1 ======================================================== */ + #define R_ETHA0_EACAULC1_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC1_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACAULC2 ======================================================== */ + #define R_ETHA0_EACAULC2_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC2_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACAULC3 ======================================================== */ + #define R_ETHA0_EACAULC3_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC3_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACAULC4 ======================================================== */ + #define R_ETHA0_EACAULC4_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC4_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACAULC5 ======================================================== */ + #define R_ETHA0_EACAULC5_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC5_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACAULC6 ======================================================== */ + #define R_ETHA0_EACAULC6_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC6_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACAULC7 ======================================================== */ + #define R_ETHA0_EACAULC7_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC7_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================== EACOEM ========================================================= */ + #define R_ETHA0_EACOEM_CE0_Pos (0UL) /*!< CE0 (Bit 0) */ + #define R_ETHA0_EACOEM_CE0_Msk (0x1UL) /*!< CE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACOEM_CE1_Pos (1UL) /*!< CE1 (Bit 1) */ + #define R_ETHA0_EACOEM_CE1_Msk (0x2UL) /*!< CE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACOEM_CE2_Pos (2UL) /*!< CE2 (Bit 2) */ + #define R_ETHA0_EACOEM_CE2_Msk (0x4UL) /*!< CE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACOEM_CE3_Pos (3UL) /*!< CE3 (Bit 3) */ + #define R_ETHA0_EACOEM_CE3_Msk (0x8UL) /*!< CE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACOEM_CE4_Pos (4UL) /*!< CE4 (Bit 4) */ + #define R_ETHA0_EACOEM_CE4_Msk (0x10UL) /*!< CE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACOEM_CE5_Pos (5UL) /*!< CE5 (Bit 5) */ + #define R_ETHA0_EACOEM_CE5_Msk (0x20UL) /*!< CE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACOEM_CE6_Pos (6UL) /*!< CE6 (Bit 6) */ + #define R_ETHA0_EACOEM_CE6_Msk (0x40UL) /*!< CE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACOEM_CE7_Pos (7UL) /*!< CE7 (Bit 7) */ + #define R_ETHA0_EACOEM_CE7_Msk (0x80UL) /*!< CE7 (Bitfield-Mask: 0x01) */ +/* ======================================================= EACOIVM0 ======================================================== */ + #define R_ETHA0_EACOIVM0_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM0_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOIVM1 ======================================================== */ + #define R_ETHA0_EACOIVM1_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM1_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOIVM2 ======================================================== */ + #define R_ETHA0_EACOIVM2_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM2_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOIVM3 ======================================================== */ + #define R_ETHA0_EACOIVM3_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM3_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOIVM4 ======================================================== */ + #define R_ETHA0_EACOIVM4_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM4_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOIVM5 ======================================================== */ + #define R_ETHA0_EACOIVM5_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM5_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOIVM6 ======================================================== */ + #define R_ETHA0_EACOIVM6_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM6_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOIVM7 ======================================================== */ + #define R_ETHA0_EACOIVM7_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM7_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOULM0 ======================================================== */ + #define R_ETHA0_EACOULM0_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM0_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACOULM1 ======================================================== */ + #define R_ETHA0_EACOULM1_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM1_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACOULM2 ======================================================== */ + #define R_ETHA0_EACOULM2_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM2_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACOULM3 ======================================================== */ + #define R_ETHA0_EACOULM3_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM3_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACOULM4 ======================================================== */ + #define R_ETHA0_EACOULM4_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM4_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACOULM5 ======================================================== */ + #define R_ETHA0_EACOULM5_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM5_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACOULM6 ======================================================== */ + #define R_ETHA0_EACOULM6_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM6_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACOULM7 ======================================================== */ + #define R_ETHA0_EACOULM7_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM7_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================== EACGSM ========================================================= */ + #define R_ETHA0_EACGSM_CGS0_Pos (0UL) /*!< CGS0 (Bit 0) */ + #define R_ETHA0_EACGSM_CGS0_Msk (0x1UL) /*!< CGS0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACGSM_CGS1_Pos (1UL) /*!< CGS1 (Bit 1) */ + #define R_ETHA0_EACGSM_CGS1_Msk (0x2UL) /*!< CGS1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACGSM_CGS2_Pos (2UL) /*!< CGS2 (Bit 2) */ + #define R_ETHA0_EACGSM_CGS2_Msk (0x4UL) /*!< CGS2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACGSM_CGS3_Pos (3UL) /*!< CGS3 (Bit 3) */ + #define R_ETHA0_EACGSM_CGS3_Msk (0x8UL) /*!< CGS3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACGSM_CGS4_Pos (4UL) /*!< CGS4 (Bit 4) */ + #define R_ETHA0_EACGSM_CGS4_Msk (0x10UL) /*!< CGS4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACGSM_CGS5_Pos (5UL) /*!< CGS5 (Bit 5) */ + #define R_ETHA0_EACGSM_CGS5_Msk (0x20UL) /*!< CGS5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACGSM_CGS6_Pos (6UL) /*!< CGS6 (Bit 6) */ + #define R_ETHA0_EACGSM_CGS6_Msk (0x40UL) /*!< CGS6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACGSM_CGS7_Pos (7UL) /*!< CGS7 (Bit 7) */ + #define R_ETHA0_EACGSM_CGS7_Msk (0x80UL) /*!< CGS7 (Bitfield-Mask: 0x01) */ +/* ======================================================== EATASC ========================================================= */ + #define R_ETHA0_EATASC_TASE_Pos (0UL) /*!< TASE (Bit 0) */ + #define R_ETHA0_EATASC_TASE_Msk (0x1UL) /*!< TASE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASC_TASCC_Pos (1UL) /*!< TASCC (Bit 1) */ + #define R_ETHA0_EATASC_TASCC_Msk (0x2UL) /*!< TASCC (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASC_TASCI_Pos (2UL) /*!< TASCI (Bit 2) */ + #define R_ETHA0_EATASC_TASCI_Msk (0x4UL) /*!< TASCI (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASC_TASTS_Pos (8UL) /*!< TASTS (Bit 8) */ + #define R_ETHA0_EATASC_TASTS_Msk (0x100UL) /*!< TASTS (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASC_TASCA_Pos (16UL) /*!< TASCA (Bit 16) */ + #define R_ETHA0_EATASC_TASCA_Msk (0xff0000UL) /*!< TASCA (Bitfield-Mask: 0xff) */ +/* ======================================================= EATASIGSC ======================================================= */ + #define R_ETHA0_EATASIGSC_TASIGS0_Pos (0UL) /*!< TASIGS0 (Bit 0) */ + #define R_ETHA0_EATASIGSC_TASIGS0_Msk (0x1UL) /*!< TASIGS0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASIGS1_Pos (1UL) /*!< TASIGS1 (Bit 1) */ + #define R_ETHA0_EATASIGSC_TASIGS1_Msk (0x2UL) /*!< TASIGS1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASIGS2_Pos (2UL) /*!< TASIGS2 (Bit 2) */ + #define R_ETHA0_EATASIGSC_TASIGS2_Msk (0x4UL) /*!< TASIGS2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASIGS3_Pos (3UL) /*!< TASIGS3 (Bit 3) */ + #define R_ETHA0_EATASIGSC_TASIGS3_Msk (0x8UL) /*!< TASIGS3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASIGS4_Pos (4UL) /*!< TASIGS4 (Bit 4) */ + #define R_ETHA0_EATASIGSC_TASIGS4_Msk (0x10UL) /*!< TASIGS4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASIGS5_Pos (5UL) /*!< TASIGS5 (Bit 5) */ + #define R_ETHA0_EATASIGSC_TASIGS5_Msk (0x20UL) /*!< TASIGS5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASIGS6_Pos (6UL) /*!< TASIGS6 (Bit 6) */ + #define R_ETHA0_EATASIGSC_TASIGS6_Msk (0x40UL) /*!< TASIGS6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASIGS7_Pos (7UL) /*!< TASIGS7 (Bit 7) */ + #define R_ETHA0_EATASIGSC_TASIGS7_Msk (0x80UL) /*!< TASIGS7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASCTIGS_Pos (8UL) /*!< TASCTIGS (Bit 8) */ + #define R_ETHA0_EATASIGSC_TASCTIGS_Msk (0x100UL) /*!< TASCTIGS (Bitfield-Mask: 0x01) */ +/* ======================================================= EATASENC0 ======================================================= */ + #define R_ETHA0_EATASENC0_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC0_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENC1 ======================================================= */ + #define R_ETHA0_EATASENC1_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC1_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENC2 ======================================================= */ + #define R_ETHA0_EATASENC2_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC2_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENC3 ======================================================= */ + #define R_ETHA0_EATASENC3_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC3_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENC4 ======================================================= */ + #define R_ETHA0_EATASENC4_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC4_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENC5 ======================================================= */ + #define R_ETHA0_EATASENC5_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC5_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENC6 ======================================================= */ + #define R_ETHA0_EATASENC6_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC6_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENC7 ======================================================= */ + #define R_ETHA0_EATASENC7_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC7_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ====================================================== EATASCTENC ======================================================= */ + #define R_ETHA0_EATASCTENC_TASCTAEN_Pos (0UL) /*!< TASCTAEN (Bit 0) */ + #define R_ETHA0_EATASCTENC_TASCTAEN_Msk (0x1ffUL) /*!< TASCTAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM0 ======================================================= */ + #define R_ETHA0_EATASENM0_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM0_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM1 ======================================================= */ + #define R_ETHA0_EATASENM1_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM1_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM2 ======================================================= */ + #define R_ETHA0_EATASENM2_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM2_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM3 ======================================================= */ + #define R_ETHA0_EATASENM3_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM3_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM4 ======================================================= */ + #define R_ETHA0_EATASENM4_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM4_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM5 ======================================================= */ + #define R_ETHA0_EATASENM5_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM5_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM6 ======================================================= */ + #define R_ETHA0_EATASENM6_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM6_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM7 ======================================================= */ + #define R_ETHA0_EATASENM7_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM7_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ====================================================== EATASCTENM ======================================================= */ + #define R_ETHA0_EATASCTENM_TASCTOEN_Pos (0UL) /*!< TASCTOEN (Bit 0) */ + #define R_ETHA0_EATASCTENM_TASCTOEN_Msk (0x1ffUL) /*!< TASCTOEN (Bitfield-Mask: 0x1ff) */ +/* ====================================================== EATASCSTC0 ======================================================= */ + #define R_ETHA0_EATASCSTC0_TASACSTP0_Pos (0UL) /*!< TASACSTP0 (Bit 0) */ + #define R_ETHA0_EATASCSTC0_TASACSTP0_Msk (0xffffffffUL) /*!< TASACSTP0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== EATASCSTC1 ======================================================= */ + #define R_ETHA0_EATASCSTC1_TASACSTP1_Pos (0UL) /*!< TASACSTP1 (Bit 0) */ + #define R_ETHA0_EATASCSTC1_TASACSTP1_Msk (0xffffffffUL) /*!< TASACSTP1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== EATASCSTM0 ======================================================= */ + #define R_ETHA0_EATASCSTM0_TASOCSTP0_Pos (0UL) /*!< TASOCSTP0 (Bit 0) */ + #define R_ETHA0_EATASCSTM0_TASOCSTP0_Msk (0xffffffffUL) /*!< TASOCSTP0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== EATASCSTM1 ======================================================= */ + #define R_ETHA0_EATASCSTM1_TASOCSTP1_Pos (0UL) /*!< TASOCSTP1 (Bit 0) */ + #define R_ETHA0_EATASCSTM1_TASOCSTP1_Msk (0xffffffffUL) /*!< TASOCSTP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EATASCTC ======================================================== */ + #define R_ETHA0_EATASCTC_TASACT_Pos (0UL) /*!< TASACT (Bit 0) */ + #define R_ETHA0_EATASCTC_TASACT_Msk (0xffffffffUL) /*!< TASACT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EATASCTM ======================================================== */ + #define R_ETHA0_EATASCTM_TASOCT_Pos (0UL) /*!< TASOCT (Bit 0) */ + #define R_ETHA0_EATASCTM_TASOCT_Msk (0xffffffffUL) /*!< TASOCT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EATASGL0 ======================================================== */ + #define R_ETHA0_EATASGL0_TASGAL_Pos (0UL) /*!< TASGAL (Bit 0) */ + #define R_ETHA0_EATASGL0_TASGAL_Msk (0xffUL) /*!< TASGAL (Bitfield-Mask: 0xff) */ +/* ======================================================= EATASGL1 ======================================================== */ + #define R_ETHA0_EATASGL1_TASGTL_Pos (0UL) /*!< TASGTL (Bit 0) */ + #define R_ETHA0_EATASGL1_TASGTL_Msk (0xfffffffUL) /*!< TASGTL (Bitfield-Mask: 0xfffffff) */ + #define R_ETHA0_EATASGL1_TASGSL_Pos (28UL) /*!< TASGSL (Bit 28) */ + #define R_ETHA0_EATASGL1_TASGSL_Msk (0x10000000UL) /*!< TASGSL (Bitfield-Mask: 0x01) */ +/* ======================================================= EATASGLR ======================================================== */ + #define R_ETHA0_EATASGLR_GL_Pos (31UL) /*!< GL (Bit 31) */ + #define R_ETHA0_EATASGLR_GL_Msk (0x80000000UL) /*!< GL (Bitfield-Mask: 0x01) */ +/* ======================================================== EATASGR ======================================================== */ + #define R_ETHA0_EATASGR_TASGAR_Pos (0UL) /*!< TASGAR (Bit 0) */ + #define R_ETHA0_EATASGR_TASGAR_Msk (0xffUL) /*!< TASGAR (Bitfield-Mask: 0xff) */ +/* ======================================================= EATASGRR ======================================================== */ + #define R_ETHA0_EATASGRR_TASGTR_Pos (0UL) /*!< TASGTR (Bit 0) */ + #define R_ETHA0_EATASGRR_TASGTR_Msk (0xfffffffUL) /*!< TASGTR (Bitfield-Mask: 0xfffffff) */ + #define R_ETHA0_EATASGRR_TASGSR_Pos (28UL) /*!< TASGSR (Bit 28) */ + #define R_ETHA0_EATASGRR_TASGSR_Msk (0x10000000UL) /*!< TASGSR (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASGRR_TASREF_Pos (29UL) /*!< TASREF (Bit 29) */ + #define R_ETHA0_EATASGRR_TASREF_Msk (0x20000000UL) /*!< TASREF (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASGRR_GR_Pos (31UL) /*!< GR (Bit 31) */ + #define R_ETHA0_EATASGRR_GR_Msk (0x80000000UL) /*!< GR (Bitfield-Mask: 0x01) */ +/* ======================================================= EATASHCC ======================================================== */ + #define R_ETHA0_EATASHCC_TASJ_Pos (0UL) /*!< TASJ (Bit 0) */ + #define R_ETHA0_EATASHCC_TASJ_Msk (0xffffUL) /*!< TASJ (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATASRIRM ======================================================= */ + #define R_ETHA0_EATASRIRM_TASRIOG_Pos (0UL) /*!< TASRIOG (Bit 0) */ + #define R_ETHA0_EATASRIRM_TASRIOG_Msk (0x1UL) /*!< TASRIOG (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASRIRM_TASRR_Pos (1UL) /*!< TASRR (Bit 1) */ + #define R_ETHA0_EATASRIRM_TASRR_Msk (0x2UL) /*!< TASRR (Bitfield-Mask: 0x01) */ +/* ======================================================== EATASSM ======================================================== */ + #define R_ETHA0_EATASSM_TASGS0_Pos (0UL) /*!< TASGS0 (Bit 0) */ + #define R_ETHA0_EATASSM_TASGS0_Msk (0x1UL) /*!< TASGS0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASGS1_Pos (1UL) /*!< TASGS1 (Bit 1) */ + #define R_ETHA0_EATASSM_TASGS1_Msk (0x2UL) /*!< TASGS1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASGS2_Pos (2UL) /*!< TASGS2 (Bit 2) */ + #define R_ETHA0_EATASSM_TASGS2_Msk (0x4UL) /*!< TASGS2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASGS3_Pos (3UL) /*!< TASGS3 (Bit 3) */ + #define R_ETHA0_EATASSM_TASGS3_Msk (0x8UL) /*!< TASGS3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASGS4_Pos (4UL) /*!< TASGS4 (Bit 4) */ + #define R_ETHA0_EATASSM_TASGS4_Msk (0x10UL) /*!< TASGS4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASGS5_Pos (5UL) /*!< TASGS5 (Bit 5) */ + #define R_ETHA0_EATASSM_TASGS5_Msk (0x20UL) /*!< TASGS5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASGS6_Pos (6UL) /*!< TASGS6 (Bit 6) */ + #define R_ETHA0_EATASSM_TASGS6_Msk (0x40UL) /*!< TASGS6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASGS7_Pos (7UL) /*!< TASGS7 (Bit 7) */ + #define R_ETHA0_EATASSM_TASGS7_Msk (0x80UL) /*!< TASGS7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASCTGS_Pos (8UL) /*!< TASCTGS (Bit 8) */ + #define R_ETHA0_EATASSM_TASCTGS_Msk (0x100UL) /*!< TASCTGS (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASSO_Pos (16UL) /*!< TASSO (Bit 16) */ + #define R_ETHA0_EATASSM_TASSO_Msk (0x10000UL) /*!< TASSO (Bitfield-Mask: 0x01) */ +/* ====================================================== EAUSMFSECN ======================================================= */ + #define R_ETHA0_EAUSMFSECN_USMFSEN_Pos (0UL) /*!< USMFSEN (Bit 0) */ + #define R_ETHA0_EAUSMFSECN_USMFSEN_Msk (0xffffUL) /*!< USMFSEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== EATFECN ======================================================== */ + #define R_ETHA0_EATFECN_TFEN_Pos (0UL) /*!< TFEN (Bit 0) */ + #define R_ETHA0_EATFECN_TFEN_Msk (0xffffUL) /*!< TFEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== EAFSECN ======================================================== */ + #define R_ETHA0_EAFSECN_FSEN_Pos (0UL) /*!< FSEN (Bit 0) */ + #define R_ETHA0_EAFSECN_FSEN_Msk (0xffffUL) /*!< FSEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= EADQOECN ======================================================== */ + #define R_ETHA0_EADQOECN_DQOEN_Pos (0UL) /*!< DQOEN (Bit 0) */ + #define R_ETHA0_EADQOECN_DQOEN_Msk (0xffffUL) /*!< DQOEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= EADQSECN ======================================================== */ + #define R_ETHA0_EADQSECN_DQSEN_Pos (0UL) /*!< DQSEN (Bit 0) */ + #define R_ETHA0_EADQSECN_DQSEN_Msk (0xffffUL) /*!< DQSEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== EAEIS0 ========================================================= */ + #define R_ETHA0_EAEIS0_DECCES_Pos (0UL) /*!< DECCES (Bit 0) */ + #define R_ETHA0_EAEIS0_DECCES_Msk (0x1UL) /*!< DECCES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TECCES_Pos (1UL) /*!< TECCES (Bit 1) */ + #define R_ETHA0_EAEIS0_TECCES_Msk (0x2UL) /*!< TECCES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_PECCES_Pos (2UL) /*!< PECCES (Bit 2) */ + #define R_ETHA0_EAEIS0_PECCES_Msk (0x4UL) /*!< PECCES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_DSECCES_Pos (3UL) /*!< DSECCES (Bit 3) */ + #define R_ETHA0_EAEIS0_DSECCES_Msk (0x8UL) /*!< DSECCES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_L23UECCES_Pos (4UL) /*!< L23UECCES (Bit 4) */ + #define R_ETHA0_EAEIS0_L23UECCES_Msk (0x10UL) /*!< L23UECCES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_USMFSES_Pos (5UL) /*!< USMFSES (Bit 5) */ + #define R_ETHA0_EAEIS0_USMFSES_Msk (0x20UL) /*!< USMFSES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TFES_Pos (6UL) /*!< TFES (Bit 6) */ + #define R_ETHA0_EAEIS0_TFES_Msk (0x40UL) /*!< TFES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES0_Pos (8UL) /*!< FSES0 (Bit 8) */ + #define R_ETHA0_EAEIS0_FSES0_Msk (0x100UL) /*!< FSES0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES1_Pos (9UL) /*!< FSES1 (Bit 9) */ + #define R_ETHA0_EAEIS0_FSES1_Msk (0x200UL) /*!< FSES1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES2_Pos (10UL) /*!< FSES2 (Bit 10) */ + #define R_ETHA0_EAEIS0_FSES2_Msk (0x400UL) /*!< FSES2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES3_Pos (11UL) /*!< FSES3 (Bit 11) */ + #define R_ETHA0_EAEIS0_FSES3_Msk (0x800UL) /*!< FSES3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES4_Pos (12UL) /*!< FSES4 (Bit 12) */ + #define R_ETHA0_EAEIS0_FSES4_Msk (0x1000UL) /*!< FSES4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES5_Pos (13UL) /*!< FSES5 (Bit 13) */ + #define R_ETHA0_EAEIS0_FSES5_Msk (0x2000UL) /*!< FSES5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES6_Pos (14UL) /*!< FSES6 (Bit 14) */ + #define R_ETHA0_EAEIS0_FSES6_Msk (0x4000UL) /*!< FSES6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES7_Pos (15UL) /*!< FSES7 (Bit 15) */ + #define R_ETHA0_EAEIS0_FSES7_Msk (0x8000UL) /*!< FSES7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES0_Pos (16UL) /*!< TASGEES0 (Bit 16) */ + #define R_ETHA0_EAEIS0_TASGEES0_Msk (0x10000UL) /*!< TASGEES0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES1_Pos (17UL) /*!< TASGEES1 (Bit 17) */ + #define R_ETHA0_EAEIS0_TASGEES1_Msk (0x20000UL) /*!< TASGEES1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES2_Pos (18UL) /*!< TASGEES2 (Bit 18) */ + #define R_ETHA0_EAEIS0_TASGEES2_Msk (0x40000UL) /*!< TASGEES2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES3_Pos (19UL) /*!< TASGEES3 (Bit 19) */ + #define R_ETHA0_EAEIS0_TASGEES3_Msk (0x80000UL) /*!< TASGEES3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES4_Pos (20UL) /*!< TASGEES4 (Bit 20) */ + #define R_ETHA0_EAEIS0_TASGEES4_Msk (0x100000UL) /*!< TASGEES4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES5_Pos (21UL) /*!< TASGEES5 (Bit 21) */ + #define R_ETHA0_EAEIS0_TASGEES5_Msk (0x200000UL) /*!< TASGEES5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES6_Pos (22UL) /*!< TASGEES6 (Bit 22) */ + #define R_ETHA0_EAEIS0_TASGEES6_Msk (0x400000UL) /*!< TASGEES6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES7_Pos (23UL) /*!< TASGEES7 (Bit 23) */ + #define R_ETHA0_EAEIS0_TASGEES7_Msk (0x800000UL) /*!< TASGEES7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASCTGEES_Pos (24UL) /*!< TASCTGEES (Bit 24) */ + #define R_ETHA0_EAEIS0_TASCTGEES_Msk (0x1000000UL) /*!< TASCTGEES (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEIE0 ========================================================= */ + #define R_ETHA0_EAEIE0_DECCEE_Pos (0UL) /*!< DECCEE (Bit 0) */ + #define R_ETHA0_EAEIE0_DECCEE_Msk (0x1UL) /*!< DECCEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TECCEE_Pos (1UL) /*!< TECCEE (Bit 1) */ + #define R_ETHA0_EAEIE0_TECCEE_Msk (0x2UL) /*!< TECCEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_PECCEE_Pos (2UL) /*!< PECCEE (Bit 2) */ + #define R_ETHA0_EAEIE0_PECCEE_Msk (0x4UL) /*!< PECCEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_DSECCEE_Pos (3UL) /*!< DSECCEE (Bit 3) */ + #define R_ETHA0_EAEIE0_DSECCEE_Msk (0x8UL) /*!< DSECCEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_L23UECCEE_Pos (4UL) /*!< L23UECCEE (Bit 4) */ + #define R_ETHA0_EAEIE0_L23UECCEE_Msk (0x10UL) /*!< L23UECCEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_USMFSEE_Pos (5UL) /*!< USMFSEE (Bit 5) */ + #define R_ETHA0_EAEIE0_USMFSEE_Msk (0x20UL) /*!< USMFSEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TFEE_Pos (6UL) /*!< TFEE (Bit 6) */ + #define R_ETHA0_EAEIE0_TFEE_Msk (0x40UL) /*!< TFEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE0_Pos (8UL) /*!< FSEE0 (Bit 8) */ + #define R_ETHA0_EAEIE0_FSEE0_Msk (0x100UL) /*!< FSEE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE1_Pos (9UL) /*!< FSEE1 (Bit 9) */ + #define R_ETHA0_EAEIE0_FSEE1_Msk (0x200UL) /*!< FSEE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE2_Pos (10UL) /*!< FSEE2 (Bit 10) */ + #define R_ETHA0_EAEIE0_FSEE2_Msk (0x400UL) /*!< FSEE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE3_Pos (11UL) /*!< FSEE3 (Bit 11) */ + #define R_ETHA0_EAEIE0_FSEE3_Msk (0x800UL) /*!< FSEE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE4_Pos (12UL) /*!< FSEE4 (Bit 12) */ + #define R_ETHA0_EAEIE0_FSEE4_Msk (0x1000UL) /*!< FSEE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE5_Pos (13UL) /*!< FSEE5 (Bit 13) */ + #define R_ETHA0_EAEIE0_FSEE5_Msk (0x2000UL) /*!< FSEE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE6_Pos (14UL) /*!< FSEE6 (Bit 14) */ + #define R_ETHA0_EAEIE0_FSEE6_Msk (0x4000UL) /*!< FSEE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE7_Pos (15UL) /*!< FSEE7 (Bit 15) */ + #define R_ETHA0_EAEIE0_FSEE7_Msk (0x8000UL) /*!< FSEE7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE0_Pos (16UL) /*!< TASGEEE0 (Bit 16) */ + #define R_ETHA0_EAEIE0_TASGEEE0_Msk (0x10000UL) /*!< TASGEEE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE1_Pos (17UL) /*!< TASGEEE1 (Bit 17) */ + #define R_ETHA0_EAEIE0_TASGEEE1_Msk (0x20000UL) /*!< TASGEEE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE2_Pos (18UL) /*!< TASGEEE2 (Bit 18) */ + #define R_ETHA0_EAEIE0_TASGEEE2_Msk (0x40000UL) /*!< TASGEEE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE3_Pos (19UL) /*!< TASGEEE3 (Bit 19) */ + #define R_ETHA0_EAEIE0_TASGEEE3_Msk (0x80000UL) /*!< TASGEEE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE4_Pos (20UL) /*!< TASGEEE4 (Bit 20) */ + #define R_ETHA0_EAEIE0_TASGEEE4_Msk (0x100000UL) /*!< TASGEEE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE5_Pos (21UL) /*!< TASGEEE5 (Bit 21) */ + #define R_ETHA0_EAEIE0_TASGEEE5_Msk (0x200000UL) /*!< TASGEEE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE6_Pos (22UL) /*!< TASGEEE6 (Bit 22) */ + #define R_ETHA0_EAEIE0_TASGEEE6_Msk (0x400000UL) /*!< TASGEEE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE7_Pos (23UL) /*!< TASGEEE7 (Bit 23) */ + #define R_ETHA0_EAEIE0_TASGEEE7_Msk (0x800000UL) /*!< TASGEEE7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASCTGEEE_Pos (24UL) /*!< TASCTGEEE (Bit 24) */ + #define R_ETHA0_EAEIE0_TASCTGEEE_Msk (0x1000000UL) /*!< TASCTGEEE (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEID0 ========================================================= */ + #define R_ETHA0_EAEID0_DECCED_Pos (0UL) /*!< DECCED (Bit 0) */ + #define R_ETHA0_EAEID0_DECCED_Msk (0x1UL) /*!< DECCED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TECCED_Pos (1UL) /*!< TECCED (Bit 1) */ + #define R_ETHA0_EAEID0_TECCED_Msk (0x2UL) /*!< TECCED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_PECCED_Pos (2UL) /*!< PECCED (Bit 2) */ + #define R_ETHA0_EAEID0_PECCED_Msk (0x4UL) /*!< PECCED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_DSECCED_Pos (3UL) /*!< DSECCED (Bit 3) */ + #define R_ETHA0_EAEID0_DSECCED_Msk (0x8UL) /*!< DSECCED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_L23UECCED_Pos (4UL) /*!< L23UECCED (Bit 4) */ + #define R_ETHA0_EAEID0_L23UECCED_Msk (0x10UL) /*!< L23UECCED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_USMFSED_Pos (5UL) /*!< USMFSED (Bit 5) */ + #define R_ETHA0_EAEID0_USMFSED_Msk (0x20UL) /*!< USMFSED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TFED_Pos (6UL) /*!< TFED (Bit 6) */ + #define R_ETHA0_EAEID0_TFED_Msk (0x40UL) /*!< TFED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED0_Pos (8UL) /*!< FSED0 (Bit 8) */ + #define R_ETHA0_EAEID0_FSED0_Msk (0x100UL) /*!< FSED0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED1_Pos (9UL) /*!< FSED1 (Bit 9) */ + #define R_ETHA0_EAEID0_FSED1_Msk (0x200UL) /*!< FSED1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED2_Pos (10UL) /*!< FSED2 (Bit 10) */ + #define R_ETHA0_EAEID0_FSED2_Msk (0x400UL) /*!< FSED2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED3_Pos (11UL) /*!< FSED3 (Bit 11) */ + #define R_ETHA0_EAEID0_FSED3_Msk (0x800UL) /*!< FSED3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED4_Pos (12UL) /*!< FSED4 (Bit 12) */ + #define R_ETHA0_EAEID0_FSED4_Msk (0x1000UL) /*!< FSED4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED5_Pos (13UL) /*!< FSED5 (Bit 13) */ + #define R_ETHA0_EAEID0_FSED5_Msk (0x2000UL) /*!< FSED5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED6_Pos (14UL) /*!< FSED6 (Bit 14) */ + #define R_ETHA0_EAEID0_FSED6_Msk (0x4000UL) /*!< FSED6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED7_Pos (15UL) /*!< FSED7 (Bit 15) */ + #define R_ETHA0_EAEID0_FSED7_Msk (0x8000UL) /*!< FSED7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED0_Pos (16UL) /*!< TASGEED0 (Bit 16) */ + #define R_ETHA0_EAEID0_TASGEED0_Msk (0x10000UL) /*!< TASGEED0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED1_Pos (17UL) /*!< TASGEED1 (Bit 17) */ + #define R_ETHA0_EAEID0_TASGEED1_Msk (0x20000UL) /*!< TASGEED1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED2_Pos (18UL) /*!< TASGEED2 (Bit 18) */ + #define R_ETHA0_EAEID0_TASGEED2_Msk (0x40000UL) /*!< TASGEED2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED3_Pos (19UL) /*!< TASGEED3 (Bit 19) */ + #define R_ETHA0_EAEID0_TASGEED3_Msk (0x80000UL) /*!< TASGEED3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED4_Pos (20UL) /*!< TASGEED4 (Bit 20) */ + #define R_ETHA0_EAEID0_TASGEED4_Msk (0x100000UL) /*!< TASGEED4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED5_Pos (21UL) /*!< TASGEED5 (Bit 21) */ + #define R_ETHA0_EAEID0_TASGEED5_Msk (0x200000UL) /*!< TASGEED5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED6_Pos (22UL) /*!< TASGEED6 (Bit 22) */ + #define R_ETHA0_EAEID0_TASGEED6_Msk (0x400000UL) /*!< TASGEED6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED7_Pos (23UL) /*!< TASGEED7 (Bit 23) */ + #define R_ETHA0_EAEID0_TASGEED7_Msk (0x800000UL) /*!< TASGEED7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASCTGEED_Pos (24UL) /*!< TASCTGEED (Bit 24) */ + #define R_ETHA0_EAEID0_TASCTGEED_Msk (0x1000000UL) /*!< TASCTGEED (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEIS1 ========================================================= */ + #define R_ETHA0_EAEIS1_CULES0_Pos (0UL) /*!< CULES0 (Bit 0) */ + #define R_ETHA0_EAEIS1_CULES0_Msk (0x1UL) /*!< CULES0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_CULES1_Pos (1UL) /*!< CULES1 (Bit 1) */ + #define R_ETHA0_EAEIS1_CULES1_Msk (0x2UL) /*!< CULES1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_CULES2_Pos (2UL) /*!< CULES2 (Bit 2) */ + #define R_ETHA0_EAEIS1_CULES2_Msk (0x4UL) /*!< CULES2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_CULES3_Pos (3UL) /*!< CULES3 (Bit 3) */ + #define R_ETHA0_EAEIS1_CULES3_Msk (0x8UL) /*!< CULES3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_CULES4_Pos (4UL) /*!< CULES4 (Bit 4) */ + #define R_ETHA0_EAEIS1_CULES4_Msk (0x10UL) /*!< CULES4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_CULES5_Pos (5UL) /*!< CULES5 (Bit 5) */ + #define R_ETHA0_EAEIS1_CULES5_Msk (0x20UL) /*!< CULES5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_CULES6_Pos (6UL) /*!< CULES6 (Bit 6) */ + #define R_ETHA0_EAEIS1_CULES6_Msk (0x40UL) /*!< CULES6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_CULES7_Pos (7UL) /*!< CULES7 (Bit 7) */ + #define R_ETHA0_EAEIS1_CULES7_Msk (0x80UL) /*!< CULES7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES0_Pos (16UL) /*!< TASGES0 (Bit 16) */ + #define R_ETHA0_EAEIS1_TASGES0_Msk (0x10000UL) /*!< TASGES0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES1_Pos (17UL) /*!< TASGES1 (Bit 17) */ + #define R_ETHA0_EAEIS1_TASGES1_Msk (0x20000UL) /*!< TASGES1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES2_Pos (18UL) /*!< TASGES2 (Bit 18) */ + #define R_ETHA0_EAEIS1_TASGES2_Msk (0x40000UL) /*!< TASGES2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES3_Pos (19UL) /*!< TASGES3 (Bit 19) */ + #define R_ETHA0_EAEIS1_TASGES3_Msk (0x80000UL) /*!< TASGES3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES4_Pos (20UL) /*!< TASGES4 (Bit 20) */ + #define R_ETHA0_EAEIS1_TASGES4_Msk (0x100000UL) /*!< TASGES4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES5_Pos (21UL) /*!< TASGES5 (Bit 21) */ + #define R_ETHA0_EAEIS1_TASGES5_Msk (0x200000UL) /*!< TASGES5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES6_Pos (22UL) /*!< TASGES6 (Bit 22) */ + #define R_ETHA0_EAEIS1_TASGES6_Msk (0x400000UL) /*!< TASGES6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES7_Pos (23UL) /*!< TASGES7 (Bit 23) */ + #define R_ETHA0_EAEIS1_TASGES7_Msk (0x800000UL) /*!< TASGES7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASCTGES_Pos (24UL) /*!< TASCTGES (Bit 24) */ + #define R_ETHA0_EAEIS1_TASCTGES_Msk (0x1000000UL) /*!< TASCTGES (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEIE1 ========================================================= */ + #define R_ETHA0_EAEIE1_CULEE0_Pos (0UL) /*!< CULEE0 (Bit 0) */ + #define R_ETHA0_EAEIE1_CULEE0_Msk (0x1UL) /*!< CULEE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_CULEE1_Pos (1UL) /*!< CULEE1 (Bit 1) */ + #define R_ETHA0_EAEIE1_CULEE1_Msk (0x2UL) /*!< CULEE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_CULEE2_Pos (2UL) /*!< CULEE2 (Bit 2) */ + #define R_ETHA0_EAEIE1_CULEE2_Msk (0x4UL) /*!< CULEE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_CULEE3_Pos (3UL) /*!< CULEE3 (Bit 3) */ + #define R_ETHA0_EAEIE1_CULEE3_Msk (0x8UL) /*!< CULEE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_CULEE4_Pos (4UL) /*!< CULEE4 (Bit 4) */ + #define R_ETHA0_EAEIE1_CULEE4_Msk (0x10UL) /*!< CULEE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_CULEE5_Pos (5UL) /*!< CULEE5 (Bit 5) */ + #define R_ETHA0_EAEIE1_CULEE5_Msk (0x20UL) /*!< CULEE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_CULEE6_Pos (6UL) /*!< CULEE6 (Bit 6) */ + #define R_ETHA0_EAEIE1_CULEE6_Msk (0x40UL) /*!< CULEE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_CULEE7_Pos (7UL) /*!< CULEE7 (Bit 7) */ + #define R_ETHA0_EAEIE1_CULEE7_Msk (0x80UL) /*!< CULEE7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE0_Pos (16UL) /*!< TASGEE0 (Bit 16) */ + #define R_ETHA0_EAEIE1_TASGEE0_Msk (0x10000UL) /*!< TASGEE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE1_Pos (17UL) /*!< TASGEE1 (Bit 17) */ + #define R_ETHA0_EAEIE1_TASGEE1_Msk (0x20000UL) /*!< TASGEE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE2_Pos (18UL) /*!< TASGEE2 (Bit 18) */ + #define R_ETHA0_EAEIE1_TASGEE2_Msk (0x40000UL) /*!< TASGEE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE3_Pos (19UL) /*!< TASGEE3 (Bit 19) */ + #define R_ETHA0_EAEIE1_TASGEE3_Msk (0x80000UL) /*!< TASGEE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE4_Pos (20UL) /*!< TASGEE4 (Bit 20) */ + #define R_ETHA0_EAEIE1_TASGEE4_Msk (0x100000UL) /*!< TASGEE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE5_Pos (21UL) /*!< TASGEE5 (Bit 21) */ + #define R_ETHA0_EAEIE1_TASGEE5_Msk (0x200000UL) /*!< TASGEE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE6_Pos (22UL) /*!< TASGEE6 (Bit 22) */ + #define R_ETHA0_EAEIE1_TASGEE6_Msk (0x400000UL) /*!< TASGEE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE7_Pos (23UL) /*!< TASGEE7 (Bit 23) */ + #define R_ETHA0_EAEIE1_TASGEE7_Msk (0x800000UL) /*!< TASGEE7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASCTGEE_Pos (24UL) /*!< TASCTGEE (Bit 24) */ + #define R_ETHA0_EAEIE1_TASCTGEE_Msk (0x1000000UL) /*!< TASCTGEE (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEID1 ========================================================= */ + #define R_ETHA0_EAEID1_CULED0_Pos (0UL) /*!< CULED0 (Bit 0) */ + #define R_ETHA0_EAEID1_CULED0_Msk (0x1UL) /*!< CULED0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_CULED1_Pos (1UL) /*!< CULED1 (Bit 1) */ + #define R_ETHA0_EAEID1_CULED1_Msk (0x2UL) /*!< CULED1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_CULED2_Pos (2UL) /*!< CULED2 (Bit 2) */ + #define R_ETHA0_EAEID1_CULED2_Msk (0x4UL) /*!< CULED2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_CULED3_Pos (3UL) /*!< CULED3 (Bit 3) */ + #define R_ETHA0_EAEID1_CULED3_Msk (0x8UL) /*!< CULED3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_CULED4_Pos (4UL) /*!< CULED4 (Bit 4) */ + #define R_ETHA0_EAEID1_CULED4_Msk (0x10UL) /*!< CULED4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_CULED5_Pos (5UL) /*!< CULED5 (Bit 5) */ + #define R_ETHA0_EAEID1_CULED5_Msk (0x20UL) /*!< CULED5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_CULED6_Pos (6UL) /*!< CULED6 (Bit 6) */ + #define R_ETHA0_EAEID1_CULED6_Msk (0x40UL) /*!< CULED6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_CULED7_Pos (7UL) /*!< CULED7 (Bit 7) */ + #define R_ETHA0_EAEID1_CULED7_Msk (0x80UL) /*!< CULED7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED0_Pos (16UL) /*!< TASGED0 (Bit 16) */ + #define R_ETHA0_EAEID1_TASGED0_Msk (0x10000UL) /*!< TASGED0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED1_Pos (17UL) /*!< TASGED1 (Bit 17) */ + #define R_ETHA0_EAEID1_TASGED1_Msk (0x20000UL) /*!< TASGED1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED2_Pos (18UL) /*!< TASGED2 (Bit 18) */ + #define R_ETHA0_EAEID1_TASGED2_Msk (0x40000UL) /*!< TASGED2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED3_Pos (19UL) /*!< TASGED3 (Bit 19) */ + #define R_ETHA0_EAEID1_TASGED3_Msk (0x80000UL) /*!< TASGED3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED4_Pos (20UL) /*!< TASGED4 (Bit 20) */ + #define R_ETHA0_EAEID1_TASGED4_Msk (0x100000UL) /*!< TASGED4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED5_Pos (21UL) /*!< TASGED5 (Bit 21) */ + #define R_ETHA0_EAEID1_TASGED5_Msk (0x200000UL) /*!< TASGED5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED6_Pos (22UL) /*!< TASGED6 (Bit 22) */ + #define R_ETHA0_EAEID1_TASGED6_Msk (0x400000UL) /*!< TASGED6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED7_Pos (23UL) /*!< TASGED7 (Bit 23) */ + #define R_ETHA0_EAEID1_TASGED7_Msk (0x800000UL) /*!< TASGED7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASCTGED_Pos (24UL) /*!< TASCTGED (Bit 24) */ + #define R_ETHA0_EAEID1_TASCTGED_Msk (0x1000000UL) /*!< TASCTGED (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEIS2 ========================================================= */ + #define R_ETHA0_EAEIS2_DQOES0_Pos (0UL) /*!< DQOES0 (Bit 0) */ + #define R_ETHA0_EAEIS2_DQOES0_Msk (0x1UL) /*!< DQOES0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQOES1_Pos (1UL) /*!< DQOES1 (Bit 1) */ + #define R_ETHA0_EAEIS2_DQOES1_Msk (0x2UL) /*!< DQOES1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQOES2_Pos (2UL) /*!< DQOES2 (Bit 2) */ + #define R_ETHA0_EAEIS2_DQOES2_Msk (0x4UL) /*!< DQOES2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQOES3_Pos (3UL) /*!< DQOES3 (Bit 3) */ + #define R_ETHA0_EAEIS2_DQOES3_Msk (0x8UL) /*!< DQOES3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQOES4_Pos (4UL) /*!< DQOES4 (Bit 4) */ + #define R_ETHA0_EAEIS2_DQOES4_Msk (0x10UL) /*!< DQOES4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQOES5_Pos (5UL) /*!< DQOES5 (Bit 5) */ + #define R_ETHA0_EAEIS2_DQOES5_Msk (0x20UL) /*!< DQOES5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQOES6_Pos (6UL) /*!< DQOES6 (Bit 6) */ + #define R_ETHA0_EAEIS2_DQOES6_Msk (0x40UL) /*!< DQOES6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQOES7_Pos (7UL) /*!< DQOES7 (Bit 7) */ + #define R_ETHA0_EAEIS2_DQOES7_Msk (0x80UL) /*!< DQOES7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_CTDQOES_Pos (8UL) /*!< CTDQOES (Bit 8) */ + #define R_ETHA0_EAEIS2_CTDQOES_Msk (0x100UL) /*!< CTDQOES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES0_Pos (16UL) /*!< DQSES0 (Bit 16) */ + #define R_ETHA0_EAEIS2_DQSES0_Msk (0x10000UL) /*!< DQSES0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES1_Pos (17UL) /*!< DQSES1 (Bit 17) */ + #define R_ETHA0_EAEIS2_DQSES1_Msk (0x20000UL) /*!< DQSES1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES2_Pos (18UL) /*!< DQSES2 (Bit 18) */ + #define R_ETHA0_EAEIS2_DQSES2_Msk (0x40000UL) /*!< DQSES2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES3_Pos (19UL) /*!< DQSES3 (Bit 19) */ + #define R_ETHA0_EAEIS2_DQSES3_Msk (0x80000UL) /*!< DQSES3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES4_Pos (20UL) /*!< DQSES4 (Bit 20) */ + #define R_ETHA0_EAEIS2_DQSES4_Msk (0x100000UL) /*!< DQSES4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES5_Pos (21UL) /*!< DQSES5 (Bit 21) */ + #define R_ETHA0_EAEIS2_DQSES5_Msk (0x200000UL) /*!< DQSES5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES6_Pos (22UL) /*!< DQSES6 (Bit 22) */ + #define R_ETHA0_EAEIS2_DQSES6_Msk (0x400000UL) /*!< DQSES6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES7_Pos (23UL) /*!< DQSES7 (Bit 23) */ + #define R_ETHA0_EAEIS2_DQSES7_Msk (0x800000UL) /*!< DQSES7 (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEIE2 ========================================================= */ + #define R_ETHA0_EAEIE2_DQOEE0_Pos (0UL) /*!< DQOEE0 (Bit 0) */ + #define R_ETHA0_EAEIE2_DQOEE0_Msk (0x1UL) /*!< DQOEE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQOEE1_Pos (1UL) /*!< DQOEE1 (Bit 1) */ + #define R_ETHA0_EAEIE2_DQOEE1_Msk (0x2UL) /*!< DQOEE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQOEE2_Pos (2UL) /*!< DQOEE2 (Bit 2) */ + #define R_ETHA0_EAEIE2_DQOEE2_Msk (0x4UL) /*!< DQOEE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQOEE3_Pos (3UL) /*!< DQOEE3 (Bit 3) */ + #define R_ETHA0_EAEIE2_DQOEE3_Msk (0x8UL) /*!< DQOEE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQOEE4_Pos (4UL) /*!< DQOEE4 (Bit 4) */ + #define R_ETHA0_EAEIE2_DQOEE4_Msk (0x10UL) /*!< DQOEE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQOEE5_Pos (5UL) /*!< DQOEE5 (Bit 5) */ + #define R_ETHA0_EAEIE2_DQOEE5_Msk (0x20UL) /*!< DQOEE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQOEE6_Pos (6UL) /*!< DQOEE6 (Bit 6) */ + #define R_ETHA0_EAEIE2_DQOEE6_Msk (0x40UL) /*!< DQOEE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQOEE7_Pos (7UL) /*!< DQOEE7 (Bit 7) */ + #define R_ETHA0_EAEIE2_DQOEE7_Msk (0x80UL) /*!< DQOEE7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_CTDQOEE_Pos (8UL) /*!< CTDQOEE (Bit 8) */ + #define R_ETHA0_EAEIE2_CTDQOEE_Msk (0x100UL) /*!< CTDQOEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE0_Pos (16UL) /*!< DQSEE0 (Bit 16) */ + #define R_ETHA0_EAEIE2_DQSEE0_Msk (0x10000UL) /*!< DQSEE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE1_Pos (17UL) /*!< DQSEE1 (Bit 17) */ + #define R_ETHA0_EAEIE2_DQSEE1_Msk (0x20000UL) /*!< DQSEE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE2_Pos (18UL) /*!< DQSEE2 (Bit 18) */ + #define R_ETHA0_EAEIE2_DQSEE2_Msk (0x40000UL) /*!< DQSEE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE3_Pos (19UL) /*!< DQSEE3 (Bit 19) */ + #define R_ETHA0_EAEIE2_DQSEE3_Msk (0x80000UL) /*!< DQSEE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE4_Pos (20UL) /*!< DQSEE4 (Bit 20) */ + #define R_ETHA0_EAEIE2_DQSEE4_Msk (0x100000UL) /*!< DQSEE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE5_Pos (21UL) /*!< DQSEE5 (Bit 21) */ + #define R_ETHA0_EAEIE2_DQSEE5_Msk (0x200000UL) /*!< DQSEE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE6_Pos (22UL) /*!< DQSEE6 (Bit 22) */ + #define R_ETHA0_EAEIE2_DQSEE6_Msk (0x400000UL) /*!< DQSEE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE7_Pos (23UL) /*!< DQSEE7 (Bit 23) */ + #define R_ETHA0_EAEIE2_DQSEE7_Msk (0x800000UL) /*!< DQSEE7 (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEID2 ========================================================= */ + #define R_ETHA0_EAEID2_DQOED0_Pos (0UL) /*!< DQOED0 (Bit 0) */ + #define R_ETHA0_EAEID2_DQOED0_Msk (0x1UL) /*!< DQOED0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQOED1_Pos (1UL) /*!< DQOED1 (Bit 1) */ + #define R_ETHA0_EAEID2_DQOED1_Msk (0x2UL) /*!< DQOED1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQOED2_Pos (2UL) /*!< DQOED2 (Bit 2) */ + #define R_ETHA0_EAEID2_DQOED2_Msk (0x4UL) /*!< DQOED2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQOED3_Pos (3UL) /*!< DQOED3 (Bit 3) */ + #define R_ETHA0_EAEID2_DQOED3_Msk (0x8UL) /*!< DQOED3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQOED4_Pos (4UL) /*!< DQOED4 (Bit 4) */ + #define R_ETHA0_EAEID2_DQOED4_Msk (0x10UL) /*!< DQOED4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQOED5_Pos (5UL) /*!< DQOED5 (Bit 5) */ + #define R_ETHA0_EAEID2_DQOED5_Msk (0x20UL) /*!< DQOED5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQOED6_Pos (6UL) /*!< DQOED6 (Bit 6) */ + #define R_ETHA0_EAEID2_DQOED6_Msk (0x40UL) /*!< DQOED6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQOED7_Pos (7UL) /*!< DQOED7 (Bit 7) */ + #define R_ETHA0_EAEID2_DQOED7_Msk (0x80UL) /*!< DQOED7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_CTDQOED_Pos (8UL) /*!< CTDQOED (Bit 8) */ + #define R_ETHA0_EAEID2_CTDQOED_Msk (0x100UL) /*!< CTDQOED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED0_Pos (16UL) /*!< DQSED0 (Bit 16) */ + #define R_ETHA0_EAEID2_DQSED0_Msk (0x10000UL) /*!< DQSED0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED1_Pos (17UL) /*!< DQSED1 (Bit 17) */ + #define R_ETHA0_EAEID2_DQSED1_Msk (0x20000UL) /*!< DQSED1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED2_Pos (18UL) /*!< DQSED2 (Bit 18) */ + #define R_ETHA0_EAEID2_DQSED2_Msk (0x40000UL) /*!< DQSED2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED3_Pos (19UL) /*!< DQSED3 (Bit 19) */ + #define R_ETHA0_EAEID2_DQSED3_Msk (0x80000UL) /*!< DQSED3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED4_Pos (20UL) /*!< DQSED4 (Bit 20) */ + #define R_ETHA0_EAEID2_DQSED4_Msk (0x100000UL) /*!< DQSED4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED5_Pos (21UL) /*!< DQSED5 (Bit 21) */ + #define R_ETHA0_EAEID2_DQSED5_Msk (0x200000UL) /*!< DQSED5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED6_Pos (22UL) /*!< DQSED6 (Bit 22) */ + #define R_ETHA0_EAEID2_DQSED6_Msk (0x400000UL) /*!< DQSED6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED7_Pos (23UL) /*!< DQSED7 (Bit 23) */ + #define R_ETHA0_EAEID2_DQSED7_Msk (0x800000UL) /*!< DQSED7 (Bitfield-Mask: 0x01) */ +/* ========================================================= EASCR ========================================================= */ + #define R_ETHA0_EASCR_MRSL_Pos (0UL) /*!< MRSL (Bit 0) */ + #define R_ETHA0_EASCR_MRSL_Msk (0x1UL) /*!< MRSL (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_TRSL_Pos (1UL) /*!< TRSL (Bit 1) */ + #define R_ETHA0_EASCR_TRSL_Msk (0x2UL) /*!< TRSL (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_MCRSL_Pos (2UL) /*!< MCRSL (Bit 2) */ + #define R_ETHA0_EASCR_MCRSL_Msk (0x4UL) /*!< MCRSL (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_TGRSL_Pos (3UL) /*!< TGRSL (Bit 3) */ + #define R_ETHA0_EASCR_TGRSL_Msk (0x8UL) /*!< TGRSL (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_TASRSL_Pos (4UL) /*!< TASRSL (Bit 4) */ + #define R_ETHA0_EASCR_TASRSL_Msk (0x10UL) /*!< TASRSL (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_EIRSL_Pos (5UL) /*!< EIRSL (Bit 5) */ + #define R_ETHA0_EASCR_EIRSL_Msk (0x20UL) /*!< EIRSL (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_CRSL_Pos (6UL) /*!< CRSL (Bit 6) */ + #define R_ETHA0_EASCR_CRSL_Msk (0x40UL) /*!< CRSL (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL0_Pos (16UL) /*!< DQRSL0 (Bit 16) */ + #define R_ETHA0_EASCR_DQRSL0_Msk (0x10000UL) /*!< DQRSL0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL1_Pos (17UL) /*!< DQRSL1 (Bit 17) */ + #define R_ETHA0_EASCR_DQRSL1_Msk (0x20000UL) /*!< DQRSL1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL2_Pos (18UL) /*!< DQRSL2 (Bit 18) */ + #define R_ETHA0_EASCR_DQRSL2_Msk (0x40000UL) /*!< DQRSL2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL3_Pos (19UL) /*!< DQRSL3 (Bit 19) */ + #define R_ETHA0_EASCR_DQRSL3_Msk (0x80000UL) /*!< DQRSL3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL4_Pos (20UL) /*!< DQRSL4 (Bit 20) */ + #define R_ETHA0_EASCR_DQRSL4_Msk (0x100000UL) /*!< DQRSL4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL5_Pos (21UL) /*!< DQRSL5 (Bit 21) */ + #define R_ETHA0_EASCR_DQRSL5_Msk (0x200000UL) /*!< DQRSL5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL6_Pos (22UL) /*!< DQRSL6 (Bit 22) */ + #define R_ETHA0_EASCR_DQRSL6_Msk (0x400000UL) /*!< DQRSL6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL7_Pos (23UL) /*!< DQRSL7 (Bit 23) */ + #define R_ETHA0_EASCR_DQRSL7_Msk (0x800000UL) /*!< DQRSL7 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PTPIPV ========================================================= */ + #define R_GPTP_PTPIPV_IPV_Pos (0UL) /*!< IPV (Bit 0) */ + #define R_GPTP_PTPIPV_IPV_Msk (0xffffffffUL) /*!< IPV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== PTPTMEC ======================================================== */ + #define R_GPTP_PTPTMEC_TE_Pos (0UL) /*!< TE (Bit 0) */ + #define R_GPTP_PTPTMEC_TE_Msk (0x3UL) /*!< TE (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPTMDC ======================================================== */ + #define R_GPTP_PTPTMDC_TD_Pos (0UL) /*!< TD (Bit 0) */ + #define R_GPTP_PTPTMDC_TD_Msk (0x3UL) /*!< TD (Bitfield-Mask: 0x03) */ +/* ======================================================= PTPTIVC0 ======================================================== */ + #define R_GPTP_PTPTIVC0_TIV_Pos (0UL) /*!< TIV (Bit 0) */ + #define R_GPTP_PTPTIVC0_TIV_Msk (0xffffffffUL) /*!< TIV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPTIVC1 ======================================================== */ + #define R_GPTP_PTPTIVC1_TIV_Pos (0UL) /*!< TIV (Bit 0) */ + #define R_GPTP_PTPTIVC1_TIV_Msk (0xffffffffUL) /*!< TIV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPTOVCL0 ======================================================= */ + #define R_GPTP_PTPTOVCL0_TOVL_Pos (0UL) /*!< TOVL (Bit 0) */ + #define R_GPTP_PTPTOVCL0_TOVL_Msk (0x3fffffffUL) /*!< TOVL (Bitfield-Mask: 0x3fffffff) */ +/* ======================================================= PTPTOVCL1 ======================================================= */ + #define R_GPTP_PTPTOVCL1_TOVL_Pos (0UL) /*!< TOVL (Bit 0) */ + #define R_GPTP_PTPTOVCL1_TOVL_Msk (0x3fffffffUL) /*!< TOVL (Bitfield-Mask: 0x3fffffff) */ +/* ======================================================= PTPTOVCM0 ======================================================= */ + #define R_GPTP_PTPTOVCM0_TOVM_Pos (0UL) /*!< TOVM (Bit 0) */ + #define R_GPTP_PTPTOVCM0_TOVM_Msk (0xffffffffUL) /*!< TOVM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPTOVCM1 ======================================================= */ + #define R_GPTP_PTPTOVCM1_TOVM_Pos (0UL) /*!< TOVM (Bit 0) */ + #define R_GPTP_PTPTOVCM1_TOVM_Msk (0xffffffffUL) /*!< TOVM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPTOVCU0 ======================================================= */ + #define R_GPTP_PTPTOVCU0_TOVU_Pos (0UL) /*!< TOVU (Bit 0) */ + #define R_GPTP_PTPTOVCU0_TOVU_Msk (0xffffUL) /*!< TOVU (Bitfield-Mask: 0xffff) */ +/* ======================================================= PTPTOVCU1 ======================================================= */ + #define R_GPTP_PTPTOVCU1_TOVU_Pos (0UL) /*!< TOVU (Bit 0) */ + #define R_GPTP_PTPTOVCU1_TOVU_Msk (0xffffUL) /*!< TOVU (Bitfield-Mask: 0xffff) */ +/* ====================================================== PTPAVTPTML0 ====================================================== */ + #define R_GPTP_PTPAVTPTML0_AVTPL_Pos (0UL) /*!< AVTPL (Bit 0) */ + #define R_GPTP_PTPAVTPTML0_AVTPL_Msk (0xffffffffUL) /*!< AVTPL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPAVTPTML1 ====================================================== */ + #define R_GPTP_PTPAVTPTML1_AVTPL_Pos (0UL) /*!< AVTPL (Bit 0) */ + #define R_GPTP_PTPAVTPTML1_AVTPL_Msk (0xffffffffUL) /*!< AVTPL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPAVTPTMU0 ====================================================== */ + #define R_GPTP_PTPAVTPTMU0_AVTPU_Pos (0UL) /*!< AVTPU (Bit 0) */ + #define R_GPTP_PTPAVTPTMU0_AVTPU_Msk (0xffffffffUL) /*!< AVTPU (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPAVTPTMU1 ====================================================== */ + #define R_GPTP_PTPAVTPTMU1_AVTPU_Pos (0UL) /*!< AVTPU (Bit 0) */ + #define R_GPTP_PTPAVTPTMU1_AVTPU_Msk (0xffffffffUL) /*!< AVTPU (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPGPTPTML0 ====================================================== */ + #define R_GPTP_PTPGPTPTML0_GPTPL_Pos (0UL) /*!< GPTPL (Bit 0) */ + #define R_GPTP_PTPGPTPTML0_GPTPL_Msk (0x3fffffffUL) /*!< GPTPL (Bitfield-Mask: 0x3fffffff) */ +/* ====================================================== PTPGPTPTML1 ====================================================== */ + #define R_GPTP_PTPGPTPTML1_GPTPL_Pos (0UL) /*!< GPTPL (Bit 0) */ + #define R_GPTP_PTPGPTPTML1_GPTPL_Msk (0x3fffffffUL) /*!< GPTPL (Bitfield-Mask: 0x3fffffff) */ +/* ====================================================== PTPGPTPTMM0 ====================================================== */ + #define R_GPTP_PTPGPTPTMM0_GPTPM_Pos (0UL) /*!< GPTPM (Bit 0) */ + #define R_GPTP_PTPGPTPTMM0_GPTPM_Msk (0xffffffffUL) /*!< GPTPM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPGPTPTMM1 ====================================================== */ + #define R_GPTP_PTPGPTPTMM1_GPTPM_Pos (0UL) /*!< GPTPM (Bit 0) */ + #define R_GPTP_PTPGPTPTMM1_GPTPM_Msk (0xffffffffUL) /*!< GPTPM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPGPTPTMU0 ====================================================== */ + #define R_GPTP_PTPGPTPTMU0_GPTPU_Pos (0UL) /*!< GPTPU (Bit 0) */ + #define R_GPTP_PTPGPTPTMU0_GPTPU_Msk (0xffffUL) /*!< GPTPU (Bitfield-Mask: 0xffff) */ +/* ====================================================== PTPGPTPTMU1 ====================================================== */ + #define R_GPTP_PTPGPTPTMU1_GPTPU_Pos (0UL) /*!< GPTPU (Bit 0) */ + #define R_GPTP_PTPGPTPTMU1_GPTPU_Msk (0xffffUL) /*!< GPTPU (Bitfield-Mask: 0xffff) */ +/* ======================================================= PTPMCCC0 ======================================================== */ + #define R_GPTP_PTPMCCC0_MCPEE_Pos (0UL) /*!< MCPEE (Bit 0) */ + #define R_GPTP_PTPMCCC0_MCPEE_Msk (0x1UL) /*!< MCPEE (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC0_MCNEE_Pos (1UL) /*!< MCNEE (Bit 1) */ + #define R_GPTP_PTPMCCC0_MCNEE_Msk (0x2UL) /*!< MCNEE (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC0_MCTTS_Pos (2UL) /*!< MCTTS (Bit 2) */ + #define R_GPTP_PTPMCCC0_MCTTS_Msk (0x4UL) /*!< MCTTS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC0_MCTNS_Pos (3UL) /*!< MCTNS (Bit 3) */ + #define R_GPTP_PTPMCCC0_MCTNS_Msk (0x8UL) /*!< MCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC0_MCCR_Pos (16UL) /*!< MCCR (Bit 16) */ + #define R_GPTP_PTPMCCC0_MCCR_Msk (0x10000UL) /*!< MCCR (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPMCCC1 ======================================================== */ + #define R_GPTP_PTPMCCC1_MCPEE_Pos (0UL) /*!< MCPEE (Bit 0) */ + #define R_GPTP_PTPMCCC1_MCPEE_Msk (0x1UL) /*!< MCPEE (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC1_MCNEE_Pos (1UL) /*!< MCNEE (Bit 1) */ + #define R_GPTP_PTPMCCC1_MCNEE_Msk (0x2UL) /*!< MCNEE (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC1_MCTTS_Pos (2UL) /*!< MCTTS (Bit 2) */ + #define R_GPTP_PTPMCCC1_MCTTS_Msk (0x4UL) /*!< MCTTS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC1_MCTNS_Pos (3UL) /*!< MCTNS (Bit 3) */ + #define R_GPTP_PTPMCCC1_MCTNS_Msk (0x8UL) /*!< MCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC1_MCCR_Pos (16UL) /*!< MCCR (Bit 16) */ + #define R_GPTP_PTPMCCC1_MCCR_Msk (0x10000UL) /*!< MCCR (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPMCCML0 ======================================================= */ + #define R_GPTP_PTPMCCML0_MCCTVL_Pos (0UL) /*!< MCCTVL (Bit 0) */ + #define R_GPTP_PTPMCCML0_MCCTVL_Msk (0xffffffffUL) /*!< MCCTVL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPMCCML1 ======================================================= */ + #define R_GPTP_PTPMCCML1_MCCTVL_Pos (0UL) /*!< MCCTVL (Bit 0) */ + #define R_GPTP_PTPMCCML1_MCCTVL_Msk (0xffffffffUL) /*!< MCCTVL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPMCCMM0 ======================================================= */ + #define R_GPTP_PTPMCCMM0_MCCTVM_Pos (0UL) /*!< MCCTVM (Bit 0) */ + #define R_GPTP_PTPMCCMM0_MCCTVM_Msk (0xffffffffUL) /*!< MCCTVM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPMCCMM1 ======================================================= */ + #define R_GPTP_PTPMCCMM1_MCCTVM_Pos (0UL) /*!< MCCTVM (Bit 0) */ + #define R_GPTP_PTPMCCMM1_MCCTVM_Msk (0xffffffffUL) /*!< MCCTVM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPMCCMU0 ======================================================= */ + #define R_GPTP_PTPMCCMU0_MCCTVU_Pos (0UL) /*!< MCCTVU (Bit 0) */ + #define R_GPTP_PTPMCCMU0_MCCTVU_Msk (0xffffUL) /*!< MCCTVU (Bitfield-Mask: 0xffff) */ + #define R_GPTP_PTPMCCMU0_MCPEC_Pos (16UL) /*!< MCPEC (Bit 16) */ + #define R_GPTP_PTPMCCMU0_MCPEC_Msk (0x10000UL) /*!< MCPEC (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCMU0_MCNEC_Pos (17UL) /*!< MCNEC (Bit 17) */ + #define R_GPTP_PTPMCCMU0_MCNEC_Msk (0x20000UL) /*!< MCNEC (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCMU0_MCSWC_Pos (18UL) /*!< MCSWC (Bit 18) */ + #define R_GPTP_PTPMCCMU0_MCSWC_Msk (0x40000UL) /*!< MCSWC (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCMU0_MCCN_Pos (24UL) /*!< MCCN (Bit 24) */ + #define R_GPTP_PTPMCCMU0_MCCN_Msk (0x3000000UL) /*!< MCCN (Bitfield-Mask: 0x03) */ +/* ======================================================= PTPMCCMU1 ======================================================= */ + #define R_GPTP_PTPMCCMU1_MCCTVU_Pos (0UL) /*!< MCCTVU (Bit 0) */ + #define R_GPTP_PTPMCCMU1_MCCTVU_Msk (0xffffUL) /*!< MCCTVU (Bitfield-Mask: 0xffff) */ + #define R_GPTP_PTPMCCMU1_MCPEC_Pos (16UL) /*!< MCPEC (Bit 16) */ + #define R_GPTP_PTPMCCMU1_MCPEC_Msk (0x10000UL) /*!< MCPEC (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCMU1_MCNEC_Pos (17UL) /*!< MCNEC (Bit 17) */ + #define R_GPTP_PTPMCCMU1_MCNEC_Msk (0x20000UL) /*!< MCNEC (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCMU1_MCSWC_Pos (18UL) /*!< MCSWC (Bit 18) */ + #define R_GPTP_PTPMCCMU1_MCSWC_Msk (0x40000UL) /*!< MCSWC (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCMU1_MCCN_Pos (24UL) /*!< MCCN (Bit 24) */ + #define R_GPTP_PTPMCCMU1_MCCN_Msk (0x3000000UL) /*!< MCCN (Bitfield-Mask: 0x03) */ +/* ======================================================= PTPMCRC0 ======================================================== */ + #define R_GPTP_PTPMCRC0_MRTTS_Pos (0UL) /*!< MRTTS (Bit 0) */ + #define R_GPTP_PTPMCRC0_MRTTS_Msk (0x1UL) /*!< MRTTS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCRC0_MRAMS_Pos (1UL) /*!< MRAMS (Bit 1) */ + #define R_GPTP_PTPMCRC0_MRAMS_Msk (0x2UL) /*!< MRAMS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCRC0_MRTNS_Pos (2UL) /*!< MRTNS (Bit 2) */ + #define R_GPTP_PTPMCRC0_MRTNS_Msk (0x4UL) /*!< MRTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCRC0_MRPL_Pos (16UL) /*!< MRPL (Bit 16) */ + #define R_GPTP_PTPMCRC0_MRPL_Msk (0xffff0000UL) /*!< MRPL (Bitfield-Mask: 0xffff) */ +/* ======================================================= PTPMCRC1 ======================================================== */ + #define R_GPTP_PTPMCRC1_MRTTS_Pos (0UL) /*!< MRTTS (Bit 0) */ + #define R_GPTP_PTPMCRC1_MRTTS_Msk (0x1UL) /*!< MRTTS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCRC1_MRAMS_Pos (1UL) /*!< MRAMS (Bit 1) */ + #define R_GPTP_PTPMCRC1_MRAMS_Msk (0x2UL) /*!< MRAMS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCRC1_MRTNS_Pos (2UL) /*!< MRTNS (Bit 2) */ + #define R_GPTP_PTPMCRC1_MRTNS_Msk (0x4UL) /*!< MRTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCRC1_MRPL_Pos (16UL) /*!< MRPL (Bit 16) */ + #define R_GPTP_PTPMCRC1_MRPL_Msk (0xffff0000UL) /*!< MRPL (Bitfield-Mask: 0xffff) */ +/* ====================================================== PTPMCRTCL0 ======================================================= */ + #define R_GPTP_PTPMCRTCL0_MRTVL_Pos (0UL) /*!< MRTVL (Bit 0) */ + #define R_GPTP_PTPMCRTCL0_MRTVL_Msk (0xffffffffUL) /*!< MRTVL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPMCRTCL1 ======================================================= */ + #define R_GPTP_PTPMCRTCL1_MRTVL_Pos (0UL) /*!< MRTVL (Bit 0) */ + #define R_GPTP_PTPMCRTCL1_MRTVL_Msk (0xffffffffUL) /*!< MRTVL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPMCRTCM0 ======================================================= */ + #define R_GPTP_PTPMCRTCM0_MRTVM_Pos (0UL) /*!< MRTVM (Bit 0) */ + #define R_GPTP_PTPMCRTCM0_MRTVM_Msk (0xffffffffUL) /*!< MRTVM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPMCRTCM1 ======================================================= */ + #define R_GPTP_PTPMCRTCM1_MRTVM_Pos (0UL) /*!< MRTVM (Bit 0) */ + #define R_GPTP_PTPMCRTCM1_MRTVM_Msk (0xffffffffUL) /*!< MRTVM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPMCRTCU0 ======================================================= */ + #define R_GPTP_PTPMCRTCU0_MRTVU_Pos (0UL) /*!< MRTVU (Bit 0) */ + #define R_GPTP_PTPMCRTCU0_MRTVU_Msk (0xffffUL) /*!< MRTVU (Bitfield-Mask: 0xffff) */ + #define R_GPTP_PTPMCRTCU0_MRTT_Pos (16UL) /*!< MRTT (Bit 16) */ + #define R_GPTP_PTPMCRTCU0_MRTT_Msk (0x30000UL) /*!< MRTT (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPMCRTCU0_MCRN_Pos (18UL) /*!< MCRN (Bit 18) */ + #define R_GPTP_PTPMCRTCU0_MCRN_Msk (0x1c0000UL) /*!< MCRN (Bitfield-Mask: 0x07) */ + #define R_GPTP_PTPMCRTCU0_MRBCR_Pos (31UL) /*!< MRBCR (Bit 31) */ + #define R_GPTP_PTPMCRTCU0_MRBCR_Msk (0x80000000UL) /*!< MRBCR (Bitfield-Mask: 0x01) */ +/* ====================================================== PTPMCRTCU1 ======================================================= */ + #define R_GPTP_PTPMCRTCU1_MRTVU_Pos (0UL) /*!< MRTVU (Bit 0) */ + #define R_GPTP_PTPMCRTCU1_MRTVU_Msk (0xffffUL) /*!< MRTVU (Bitfield-Mask: 0xffff) */ + #define R_GPTP_PTPMCRTCU1_MRTT_Pos (16UL) /*!< MRTT (Bit 16) */ + #define R_GPTP_PTPMCRTCU1_MRTT_Msk (0x30000UL) /*!< MRTT (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPMCRTCU1_MCRN_Pos (18UL) /*!< MCRN (Bit 18) */ + #define R_GPTP_PTPMCRTCU1_MCRN_Msk (0x1c0000UL) /*!< MCRN (Bitfield-Mask: 0x07) */ + #define R_GPTP_PTPMCRTCU1_MRBCR_Pos (31UL) /*!< MRBCR (Bit 31) */ + #define R_GPTP_PTPMCRTCU1_MRBCR_Msk (0x80000000UL) /*!< MRBCR (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPMCPC0 ======================================================== */ + #define R_GPTP_PTPMCPC0_PE_Pos (0UL) /*!< PE (Bit 0) */ + #define R_GPTP_PTPMCPC0_PE_Msk (0x1UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCPC0_MRS_Pos (1UL) /*!< MRS (Bit 1) */ + #define R_GPTP_PTPMCPC0_MRS_Msk (0x2UL) /*!< MRS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPMCPC1 ======================================================== */ + #define R_GPTP_PTPMCPC1_PE_Pos (0UL) /*!< PE (Bit 0) */ + #define R_GPTP_PTPMCPC1_PE_Msk (0x1UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCPC1_MRS_Pos (1UL) /*!< MRS (Bit 1) */ + #define R_GPTP_PTPMCPC1_MRS_Msk (0x2UL) /*!< MRS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC00 ======================================================== */ + #define R_GPTP_PTPCCC00_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC00_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC00_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC00_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC01 ======================================================== */ + #define R_GPTP_PTPCCC01_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC01_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC01_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC01_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC02 ======================================================== */ + #define R_GPTP_PTPCCC02_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC02_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC02_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC02_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC03 ======================================================== */ + #define R_GPTP_PTPCCC03_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC03_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC03_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC03_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC04 ======================================================== */ + #define R_GPTP_PTPCCC04_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC04_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC04_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC04_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC05 ======================================================== */ + #define R_GPTP_PTPCCC05_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC05_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC05_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC05_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC06 ======================================================== */ + #define R_GPTP_PTPCCC06_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC06_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC06_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC06_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC07 ======================================================== */ + #define R_GPTP_PTPCCC07_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC07_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC07_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC07_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC10 ======================================================== */ + #define R_GPTP_PTPCCC10_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC10_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPCCC11 ======================================================== */ + #define R_GPTP_PTPCCC11_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC11_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPCCC12 ======================================================== */ + #define R_GPTP_PTPCCC12_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC12_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPCCC13 ======================================================== */ + #define R_GPTP_PTPCCC13_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC13_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPCCC14 ======================================================== */ + #define R_GPTP_PTPCCC14_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC14_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPCCC15 ======================================================== */ + #define R_GPTP_PTPCCC15_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC15_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPCCC16 ======================================================== */ + #define R_GPTP_PTPCCC16_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC16_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPCCC17 ======================================================== */ + #define R_GPTP_PTPCCC17_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC17_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== PTPIS0 ========================================================= */ + #define R_GPTP_PTPIS0_MCCS_Pos (0UL) /*!< MCCS (Bit 0) */ + #define R_GPTP_PTPIS0_MCCS_Msk (0x3UL) /*!< MCCS (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPIS0_MCCOES_Pos (16UL) /*!< MCCOES (Bit 16) */ + #define R_GPTP_PTPIS0_MCCOES_Msk (0x30000UL) /*!< MCCOES (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPIE0 ========================================================= */ + #define R_GPTP_PTPIE0_MCCE_Pos (0UL) /*!< MCCE (Bit 0) */ + #define R_GPTP_PTPIE0_MCCE_Msk (0x3UL) /*!< MCCE (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPIE0_MCCOEE_Pos (16UL) /*!< MCCOEE (Bit 16) */ + #define R_GPTP_PTPIE0_MCCOEE_Msk (0x30000UL) /*!< MCCOEE (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPID0 ========================================================= */ + #define R_GPTP_PTPID0_MCCD_Pos (0UL) /*!< MCCD (Bit 0) */ + #define R_GPTP_PTPID0_MCCD_Msk (0x3UL) /*!< MCCD (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPID0_MCCOED_Pos (16UL) /*!< MCCOED (Bit 16) */ + #define R_GPTP_PTPID0_MCCOED_Msk (0x30000UL) /*!< MCCOED (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPIS1 ========================================================= */ + #define R_GPTP_PTPIS1_MCRMS_Pos (0UL) /*!< MCRMS (Bit 0) */ + #define R_GPTP_PTPIS1_MCRMS_Msk (0x3UL) /*!< MCRMS (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPIE1 ========================================================= */ + #define R_GPTP_PTPIE1_MCRME_Pos (0UL) /*!< MCRME (Bit 0) */ + #define R_GPTP_PTPIE1_MCRME_Msk (0x3UL) /*!< MCRME (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPID1 ========================================================= */ + #define R_GPTP_PTPID1_MCRMD_Pos (0UL) /*!< MCRMD (Bit 0) */ + #define R_GPTP_PTPID1_MCRMD_Msk (0x3UL) /*!< MCRMD (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPSCR0 ======================================================== */ + #define R_GPTP_PTPSCR0_TRSL_Pos (0UL) /*!< TRSL (Bit 0) */ + #define R_GPTP_PTPSCR0_TRSL_Msk (0x3UL) /*!< TRSL (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPSCR0_MCRSL_Pos (16UL) /*!< MCRSL (Bit 16) */ + #define R_GPTP_PTPSCR0_MCRSL_Msk (0x30000UL) /*!< MCRSL (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPSCR1 ======================================================== */ + #define R_GPTP_PTPSCR1_MRRSL_Pos (0UL) /*!< MRRSL (Bit 0) */ + #define R_GPTP_PTPSCR1_MRRSL_Msk (0x3UL) /*!< MRRSL (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPSCR1_MRRRSL_Pos (16UL) /*!< MRRRSL (Bit 16) */ + #define R_GPTP_PTPSCR1_MRRRSL_Msk (0x30000UL) /*!< MRRRSL (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPSCR2 ======================================================== */ + #define R_GPTP_PTPSCR2_CCRSL_Pos (0UL) /*!< CCRSL (Bit 0) */ + #define R_GPTP_PTPSCR2_CCRSL_Msk (0x3UL) /*!< CCRSL (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPSCR2_VRSL_Pos (16UL) /*!< VRSL (Bit 16) */ + #define R_GPTP_PTPSCR2_VRSL_Msk (0x10000UL) /*!< VRSL (Bitfield-Mask: 0x01) */ +/* ======================================================== POTCFGR ======================================================== */ + #define R_GPTP_POTCFGR_REFSEL_Pos (0UL) /*!< REFSEL (Bit 0) */ + #define R_GPTP_POTCFGR_REFSEL_Msk (0x1UL) /*!< REFSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== POTCR0 ========================================================= */ + #define R_GPTP_POTCR0_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_GPTP_POTCR0_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ======================================================== POTCR1 ========================================================= */ + #define R_GPTP_POTCR1_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_GPTP_POTCR1_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ======================================================== POTCR2 ========================================================= */ + #define R_GPTP_POTCR2_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_GPTP_POTCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ======================================================== POTCR3 ========================================================= */ + #define R_GPTP_POTCR3_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_GPTP_POTCR3_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ======================================================= POTSTRU0 ======================================================== */ +/* ======================================================= POTSTRU1 ======================================================== */ +/* ======================================================= POTSTRU2 ======================================================== */ +/* ======================================================= POTSTRU3 ======================================================== */ +/* ======================================================= POTSTRM0 ======================================================== */ +/* ======================================================= POTSTRM1 ======================================================== */ +/* ======================================================= POTSTRM2 ======================================================== */ +/* ======================================================= POTSTRM3 ======================================================== */ +/* ======================================================= POTSTRL0 ======================================================== */ +/* ======================================================= POTSTRL1 ======================================================== */ +/* ======================================================= POTSTRL2 ======================================================== */ +/* ======================================================= POTSTRL3 ======================================================== */ +/* ======================================================= POTPERU0 ======================================================== */ +/* ======================================================= POTPERU1 ======================================================== */ +/* ======================================================= POTPERU2 ======================================================== */ +/* ======================================================= POTPERU3 ======================================================== */ +/* ======================================================= POTPERM0 ======================================================== */ +/* ======================================================= POTPERM1 ======================================================== */ +/* ======================================================= POTPERM2 ======================================================== */ +/* ======================================================= POTPERM3 ======================================================== */ +/* ======================================================= POTPERL0 ======================================================== */ +/* ======================================================= POTPERL1 ======================================================== */ +/* ======================================================= POTPERL2 ======================================================== */ +/* ======================================================= POTPERL3 ======================================================== */ +/* ======================================================== POTPWR0 ======================================================== */ +/* ======================================================== POTPWR1 ======================================================== */ +/* ======================================================== POTPWR2 ======================================================== */ +/* ======================================================== POTPWR3 ======================================================== */ +/* ======================================================= POTCPRU0 ======================================================== */ +/* ======================================================= POTCPRU1 ======================================================== */ +/* ======================================================= POTCPRU2 ======================================================== */ +/* ======================================================= POTCPRU3 ======================================================== */ +/* ======================================================= POTCPRM0 ======================================================== */ +/* ======================================================= POTCPRM1 ======================================================== */ +/* ======================================================= POTCPRM2 ======================================================== */ +/* ======================================================= POTCPRM3 ======================================================== */ +/* ======================================================= POTCPRL0 ======================================================== */ +/* ======================================================= POTCPRL1 ======================================================== */ +/* ======================================================= POTCPRL2 ======================================================== */ +/* ======================================================= POTCPRL3 ======================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_GWCA0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GWMC ========================================================== */ + #define R_GWCA0_GWMC_OPC_Pos (0UL) /*!< OPC (Bit 0) */ + #define R_GWCA0_GWMC_OPC_Msk (0x3UL) /*!< OPC (Bitfield-Mask: 0x03) */ +/* ========================================================= GWMS ========================================================== */ + #define R_GWCA0_GWMS_OPS_Pos (0UL) /*!< OPS (Bit 0) */ + #define R_GWCA0_GWMS_OPS_Msk (0x3UL) /*!< OPS (Bitfield-Mask: 0x03) */ +/* ========================================================= GWIRC ========================================================= */ + #define R_GWCA0_GWIRC_IPVR0_Pos (0UL) /*!< IPVR0 (Bit 0) */ + #define R_GWCA0_GWIRC_IPVR0_Msk (0x7UL) /*!< IPVR0 (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWIRC_IPVR1_Pos (4UL) /*!< IPVR1 (Bit 4) */ + #define R_GWCA0_GWIRC_IPVR1_Msk (0x70UL) /*!< IPVR1 (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWIRC_IPVR2_Pos (8UL) /*!< IPVR2 (Bit 8) */ + #define R_GWCA0_GWIRC_IPVR2_Msk (0x700UL) /*!< IPVR2 (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWIRC_IPVR3_Pos (12UL) /*!< IPVR3 (Bit 12) */ + #define R_GWCA0_GWIRC_IPVR3_Msk (0x7000UL) /*!< IPVR3 (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWIRC_IPVR4_Pos (16UL) /*!< IPVR4 (Bit 16) */ + #define R_GWCA0_GWIRC_IPVR4_Msk (0x70000UL) /*!< IPVR4 (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWIRC_IPVR5_Pos (20UL) /*!< IPVR5 (Bit 20) */ + #define R_GWCA0_GWIRC_IPVR5_Msk (0x700000UL) /*!< IPVR5 (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWIRC_IPVR6_Pos (24UL) /*!< IPVR6 (Bit 24) */ + #define R_GWCA0_GWIRC_IPVR6_Msk (0x7000000UL) /*!< IPVR6 (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWIRC_IPVR7_Pos (28UL) /*!< IPVR7 (Bit 28) */ + #define R_GWCA0_GWIRC_IPVR7_Msk (0x70000000UL) /*!< IPVR7 (Bitfield-Mask: 0x07) */ +/* ======================================================== GWRDQSC ======================================================== */ + #define R_GWCA0_GWRDQSC_RDQSL0_Pos (0UL) /*!< RDQSL0 (Bit 0) */ + #define R_GWCA0_GWRDQSC_RDQSL0_Msk (0x1UL) /*!< RDQSL0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQSC_RDQSL1_Pos (1UL) /*!< RDQSL1 (Bit 1) */ + #define R_GWCA0_GWRDQSC_RDQSL1_Msk (0x2UL) /*!< RDQSL1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQSC_RDQSL2_Pos (2UL) /*!< RDQSL2 (Bit 2) */ + #define R_GWCA0_GWRDQSC_RDQSL2_Msk (0x4UL) /*!< RDQSL2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQSC_RDQSL3_Pos (3UL) /*!< RDQSL3 (Bit 3) */ + #define R_GWCA0_GWRDQSC_RDQSL3_Msk (0x8UL) /*!< RDQSL3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQSC_RDQSL4_Pos (4UL) /*!< RDQSL4 (Bit 4) */ + #define R_GWCA0_GWRDQSC_RDQSL4_Msk (0x10UL) /*!< RDQSL4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQSC_RDQSL5_Pos (5UL) /*!< RDQSL5 (Bit 5) */ + #define R_GWCA0_GWRDQSC_RDQSL5_Msk (0x20UL) /*!< RDQSL5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQSC_RDQSL6_Pos (6UL) /*!< RDQSL6 (Bit 6) */ + #define R_GWCA0_GWRDQSC_RDQSL6_Msk (0x40UL) /*!< RDQSL6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQSC_RDQSL7_Pos (7UL) /*!< RDQSL7 (Bit 7) */ + #define R_GWCA0_GWRDQSC_RDQSL7_Msk (0x80UL) /*!< RDQSL7 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWRDQC ========================================================= */ + #define R_GWCA0_GWRDQC_RDQD0_Pos (0UL) /*!< RDQD0 (Bit 0) */ + #define R_GWCA0_GWRDQC_RDQD0_Msk (0x1UL) /*!< RDQD0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQD1_Pos (1UL) /*!< RDQD1 (Bit 1) */ + #define R_GWCA0_GWRDQC_RDQD1_Msk (0x2UL) /*!< RDQD1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQD2_Pos (2UL) /*!< RDQD2 (Bit 2) */ + #define R_GWCA0_GWRDQC_RDQD2_Msk (0x4UL) /*!< RDQD2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQD3_Pos (3UL) /*!< RDQD3 (Bit 3) */ + #define R_GWCA0_GWRDQC_RDQD3_Msk (0x8UL) /*!< RDQD3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQD4_Pos (4UL) /*!< RDQD4 (Bit 4) */ + #define R_GWCA0_GWRDQC_RDQD4_Msk (0x10UL) /*!< RDQD4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQD5_Pos (5UL) /*!< RDQD5 (Bit 5) */ + #define R_GWCA0_GWRDQC_RDQD5_Msk (0x20UL) /*!< RDQD5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQD6_Pos (6UL) /*!< RDQD6 (Bit 6) */ + #define R_GWCA0_GWRDQC_RDQD6_Msk (0x40UL) /*!< RDQD6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQD7_Pos (7UL) /*!< RDQD7 (Bit 7) */ + #define R_GWCA0_GWRDQC_RDQD7_Msk (0x80UL) /*!< RDQD7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP0_Pos (16UL) /*!< RDQP0 (Bit 16) */ + #define R_GWCA0_GWRDQC_RDQP0_Msk (0x10000UL) /*!< RDQP0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP1_Pos (17UL) /*!< RDQP1 (Bit 17) */ + #define R_GWCA0_GWRDQC_RDQP1_Msk (0x20000UL) /*!< RDQP1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP2_Pos (18UL) /*!< RDQP2 (Bit 18) */ + #define R_GWCA0_GWRDQC_RDQP2_Msk (0x40000UL) /*!< RDQP2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP3_Pos (19UL) /*!< RDQP3 (Bit 19) */ + #define R_GWCA0_GWRDQC_RDQP3_Msk (0x80000UL) /*!< RDQP3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP4_Pos (20UL) /*!< RDQP4 (Bit 20) */ + #define R_GWCA0_GWRDQC_RDQP4_Msk (0x100000UL) /*!< RDQP4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP5_Pos (21UL) /*!< RDQP5 (Bit 21) */ + #define R_GWCA0_GWRDQC_RDQP5_Msk (0x200000UL) /*!< RDQP5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP6_Pos (22UL) /*!< RDQP6 (Bit 22) */ + #define R_GWCA0_GWRDQC_RDQP6_Msk (0x400000UL) /*!< RDQP6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP7_Pos (23UL) /*!< RDQP7 (Bit 23) */ + #define R_GWCA0_GWRDQC_RDQP7_Msk (0x800000UL) /*!< RDQP7 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWRDQAC ======================================================== */ + #define R_GWCA0_GWRDQAC_RDQA0_Pos (0UL) /*!< RDQA0 (Bit 0) */ + #define R_GWCA0_GWRDQAC_RDQA0_Msk (0xfUL) /*!< RDQA0 (Bitfield-Mask: 0x0f) */ + #define R_GWCA0_GWRDQAC_RDQA1_Pos (4UL) /*!< RDQA1 (Bit 4) */ + #define R_GWCA0_GWRDQAC_RDQA1_Msk (0xf0UL) /*!< RDQA1 (Bitfield-Mask: 0x0f) */ + #define R_GWCA0_GWRDQAC_RDQA2_Pos (8UL) /*!< RDQA2 (Bit 8) */ + #define R_GWCA0_GWRDQAC_RDQA2_Msk (0xf00UL) /*!< RDQA2 (Bitfield-Mask: 0x0f) */ + #define R_GWCA0_GWRDQAC_RDQA3_Pos (12UL) /*!< RDQA3 (Bit 12) */ + #define R_GWCA0_GWRDQAC_RDQA3_Msk (0xf000UL) /*!< RDQA3 (Bitfield-Mask: 0x0f) */ + #define R_GWCA0_GWRDQAC_RDQA4_Pos (16UL) /*!< RDQA4 (Bit 16) */ + #define R_GWCA0_GWRDQAC_RDQA4_Msk (0xf0000UL) /*!< RDQA4 (Bitfield-Mask: 0x0f) */ + #define R_GWCA0_GWRDQAC_RDQA5_Pos (20UL) /*!< RDQA5 (Bit 20) */ + #define R_GWCA0_GWRDQAC_RDQA5_Msk (0xf00000UL) /*!< RDQA5 (Bitfield-Mask: 0x0f) */ + #define R_GWCA0_GWRDQAC_RDQA6_Pos (24UL) /*!< RDQA6 (Bit 24) */ + #define R_GWCA0_GWRDQAC_RDQA6_Msk (0xf000000UL) /*!< RDQA6 (Bitfield-Mask: 0x0f) */ + #define R_GWCA0_GWRDQAC_RDQA7_Pos (28UL) /*!< RDQA7 (Bit 28) */ + #define R_GWCA0_GWRDQAC_RDQA7_Msk (0xf0000000UL) /*!< RDQA7 (Bitfield-Mask: 0x0f) */ +/* ========================================================= GWRGC ========================================================= */ + #define R_GWCA0_GWRGC_RCPT_Pos (0UL) /*!< RCPT (Bit 0) */ + #define R_GWCA0_GWRGC_RCPT_Msk (0x1UL) /*!< RCPT (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRMFSC0 ======================================================== */ + #define R_GWCA0_GWRMFSC0_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC0_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRMFSC1 ======================================================== */ + #define R_GWCA0_GWRMFSC1_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC1_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRMFSC2 ======================================================== */ + #define R_GWCA0_GWRMFSC2_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC2_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRMFSC3 ======================================================== */ + #define R_GWCA0_GWRMFSC3_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC3_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRMFSC4 ======================================================== */ + #define R_GWCA0_GWRMFSC4_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC4_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRMFSC5 ======================================================== */ + #define R_GWCA0_GWRMFSC5_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC5_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRMFSC6 ======================================================== */ + #define R_GWCA0_GWRMFSC6_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC6_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRMFSC7 ======================================================== */ + #define R_GWCA0_GWRMFSC7_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC7_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRDQDC0 ======================================================== */ + #define R_GWCA0_GWRDQDC0_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC0_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQDC1 ======================================================== */ + #define R_GWCA0_GWRDQDC1_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC1_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQDC2 ======================================================== */ + #define R_GWCA0_GWRDQDC2_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC2_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQDC3 ======================================================== */ + #define R_GWCA0_GWRDQDC3_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC3_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQDC4 ======================================================== */ + #define R_GWCA0_GWRDQDC4_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC4_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQDC5 ======================================================== */ + #define R_GWCA0_GWRDQDC5_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC5_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQDC6 ======================================================== */ + #define R_GWCA0_GWRDQDC6_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC6_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQDC7 ======================================================== */ + #define R_GWCA0_GWRDQDC7_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC7_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM0 ======================================================== */ + #define R_GWCA0_GWRDQM0_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM0_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM1 ======================================================== */ + #define R_GWCA0_GWRDQM1_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM1_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM2 ======================================================== */ + #define R_GWCA0_GWRDQM2_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM2_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM3 ======================================================== */ + #define R_GWCA0_GWRDQM3_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM3_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM4 ======================================================== */ + #define R_GWCA0_GWRDQM4_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM4_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM5 ======================================================== */ + #define R_GWCA0_GWRDQM5_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM5_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM6 ======================================================== */ + #define R_GWCA0_GWRDQM6_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM6_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM7 ======================================================== */ + #define R_GWCA0_GWRDQM7_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM7_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM0 ======================================================= */ + #define R_GWCA0_GWRDQMLM0_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM0_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM1 ======================================================= */ + #define R_GWCA0_GWRDQMLM1_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM1_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM2 ======================================================= */ + #define R_GWCA0_GWRDQMLM2_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM2_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM3 ======================================================= */ + #define R_GWCA0_GWRDQMLM3_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM3_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM4 ======================================================= */ + #define R_GWCA0_GWRDQMLM4_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM4_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM5 ======================================================= */ + #define R_GWCA0_GWRDQMLM5_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM5_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM6 ======================================================= */ + #define R_GWCA0_GWRDQMLM6_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM6_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM7 ======================================================= */ + #define R_GWCA0_GWRDQMLM7_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM7_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWMTIRM ======================================================== */ + #define R_GWCA0_GWMTIRM_MTIOG_Pos (0UL) /*!< MTIOG (Bit 0) */ + #define R_GWCA0_GWMTIRM_MTIOG_Msk (0x1UL) /*!< MTIOG (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWMTIRM_MTR_Pos (1UL) /*!< MTR (Bit 1) */ + #define R_GWCA0_GWMTIRM_MTR_Msk (0x2UL) /*!< MTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GWMSTLS ======================================================== */ + #define R_GWCA0_GWMSTLS_MNRCNL_Pos (0UL) /*!< MNRCNL (Bit 0) */ + #define R_GWCA0_GWMSTLS_MNRCNL_Msk (0x7fUL) /*!< MNRCNL (Bitfield-Mask: 0x7f) */ + #define R_GWCA0_GWMSTLS_MNL_Pos (8UL) /*!< MNL (Bit 8) */ + #define R_GWCA0_GWMSTLS_MNL_Msk (0x700UL) /*!< MNL (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWMSTLS_MSENL_Pos (16UL) /*!< MSENL (Bit 16) */ + #define R_GWCA0_GWMSTLS_MSENL_Msk (0x7f0000UL) /*!< MSENL (Bitfield-Mask: 0x7f) */ +/* ======================================================== GWMSTLR ======================================================== */ + #define R_GWCA0_GWMSTLR_MTLF_Pos (0UL) /*!< MTLF (Bit 0) */ + #define R_GWCA0_GWMSTLR_MTLF_Msk (0x1UL) /*!< MTLF (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWMSTLR_MTL_Pos (31UL) /*!< MTL (Bit 31) */ + #define R_GWCA0_GWMSTLR_MTL_Msk (0x80000000UL) /*!< MTL (Bitfield-Mask: 0x01) */ +/* ======================================================== GWMSTSS ======================================================== */ + #define R_GWCA0_GWMSTSS_MSENS_Pos (0UL) /*!< MSENS (Bit 0) */ + #define R_GWCA0_GWMSTSS_MSENS_Msk (0x7fUL) /*!< MSENS (Bitfield-Mask: 0x7f) */ +/* ======================================================== GWMSTSR ======================================================== */ + #define R_GWCA0_GWMSTSR_MNRCNR_Pos (0UL) /*!< MNRCNR (Bit 0) */ + #define R_GWCA0_GWMSTSR_MNRCNR_Msk (0x7fUL) /*!< MNRCNR (Bitfield-Mask: 0x7f) */ + #define R_GWCA0_GWMSTSR_MNR_Pos (8UL) /*!< MNR (Bit 8) */ + #define R_GWCA0_GWMSTSR_MNR_Msk (0x700UL) /*!< MNR (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWMSTSR_MTSEF_Pos (16UL) /*!< MTSEF (Bit 16) */ + #define R_GWCA0_GWMSTSR_MTSEF_Msk (0x10000UL) /*!< MTSEF (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWMSTSR_MTS_Pos (31UL) /*!< MTS (Bit 31) */ + #define R_GWCA0_GWMSTSR_MTS_Msk (0x80000000UL) /*!< MTS (Bitfield-Mask: 0x01) */ +/* ======================================================== GWMAC0 ========================================================= */ + #define R_GWCA0_GWMAC0_MAUP_Pos (0UL) /*!< MAUP (Bit 0) */ + #define R_GWCA0_GWMAC0_MAUP_Msk (0xffffUL) /*!< MAUP (Bitfield-Mask: 0xffff) */ +/* ======================================================== GWMAC1 ========================================================= */ + #define R_GWCA0_GWMAC1_MADP_Pos (0UL) /*!< MADP (Bit 0) */ + #define R_GWCA0_GWMAC1_MADP_Msk (0xffffffffUL) /*!< MADP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GWVCC ========================================================= */ + #define R_GWCA0_GWVCC_VIM_Pos (0UL) /*!< VIM (Bit 0) */ + #define R_GWCA0_GWVCC_VIM_Msk (0x1UL) /*!< VIM (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWVCC_CTVUM_Pos (8UL) /*!< CTVUM (Bit 8) */ + #define R_GWCA0_GWVCC_CTVUM_Msk (0x100UL) /*!< CTVUM (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWVCC_VEM_Pos (16UL) /*!< VEM (Bit 16) */ + #define R_GWCA0_GWVCC_VEM_Msk (0x70000UL) /*!< VEM (Bitfield-Mask: 0x07) */ +/* ========================================================= GWVTC ========================================================= */ + #define R_GWCA0_GWVTC_CTV_Pos (0UL) /*!< CTV (Bit 0) */ + #define R_GWCA0_GWVTC_CTV_Msk (0xfffUL) /*!< CTV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWVTC_CTP_Pos (12UL) /*!< CTP (Bit 12) */ + #define R_GWCA0_GWVTC_CTP_Msk (0x7000UL) /*!< CTP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWVTC_CTD_Pos (15UL) /*!< CTD (Bit 15) */ + #define R_GWCA0_GWVTC_CTD_Msk (0x8000UL) /*!< CTD (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWVTC_STV_Pos (16UL) /*!< STV (Bit 16) */ + #define R_GWCA0_GWVTC_STV_Msk (0xfff0000UL) /*!< STV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWVTC_STP_Pos (28UL) /*!< STP (Bit 28) */ + #define R_GWCA0_GWVTC_STP_Msk (0x70000000UL) /*!< STP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWVTC_STD_Pos (31UL) /*!< STD (Bit 31) */ + #define R_GWCA0_GWVTC_STD_Msk (0x80000000UL) /*!< STD (Bitfield-Mask: 0x01) */ +/* ======================================================== GWTTFC ========================================================= */ + #define R_GWCA0_GWTTFC_NT_Pos (0UL) /*!< NT (Bit 0) */ + #define R_GWCA0_GWTTFC_NT_Msk (0x1UL) /*!< NT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_RT_Pos (1UL) /*!< RT (Bit 1) */ + #define R_GWCA0_GWTTFC_RT_Msk (0x2UL) /*!< RT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_CST_Pos (2UL) /*!< CST (Bit 2) */ + #define R_GWCA0_GWTTFC_CST_Msk (0x4UL) /*!< CST (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_CSRT_Pos (3UL) /*!< CSRT (Bit 3) */ + #define R_GWCA0_GWTTFC_CSRT_Msk (0x8UL) /*!< CSRT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_CT_Pos (4UL) /*!< CT (Bit 4) */ + #define R_GWCA0_GWTTFC_CT_Msk (0x10UL) /*!< CT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_CRT_Pos (5UL) /*!< CRT (Bit 5) */ + #define R_GWCA0_GWTTFC_CRT_Msk (0x20UL) /*!< CRT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_SCT_Pos (6UL) /*!< SCT (Bit 6) */ + #define R_GWCA0_GWTTFC_SCT_Msk (0x40UL) /*!< SCT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_SCRT_Pos (7UL) /*!< SCRT (Bit 7) */ + #define R_GWCA0_GWTTFC_SCRT_Msk (0x80UL) /*!< SCRT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_UT_Pos (8UL) /*!< UT (Bit 8) */ + #define R_GWCA0_GWTTFC_UT_Msk (0x100UL) /*!< UT (Bitfield-Mask: 0x01) */ +/* ======================================================= GWTDCAC00 ======================================================= */ + #define R_GWCA0_GWTDCAC00_TSCCAUP_Pos (0UL) /*!< TSCCAUP (Bit 0) */ + #define R_GWCA0_GWTDCAC00_TSCCAUP_Msk (0xffUL) /*!< TSCCAUP (Bitfield-Mask: 0xff) */ +/* ======================================================= GWTDCAC10 ======================================================= */ + #define R_GWCA0_GWTDCAC10_TSCCADP_Pos (0UL) /*!< TSCCADP (Bit 0) */ + #define R_GWCA0_GWTDCAC10_TSCCADP_Msk (0xffffffffUL) /*!< TSCCADP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GWTDCAC01 ======================================================= */ + #define R_GWCA0_GWTDCAC01_TSCCAUP_Pos (0UL) /*!< TSCCAUP (Bit 0) */ + #define R_GWCA0_GWTDCAC01_TSCCAUP_Msk (0xffUL) /*!< TSCCAUP (Bitfield-Mask: 0xff) */ +/* ======================================================= GWTDCAC11 ======================================================= */ + #define R_GWCA0_GWTDCAC11_TSCCADP_Pos (0UL) /*!< TSCCADP (Bit 0) */ + #define R_GWCA0_GWTDCAC11_TSCCADP_Msk (0xffffffffUL) /*!< TSCCADP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GWTSDCC0 ======================================================== */ + #define R_GWCA0_GWTSDCC0_TE_Pos (0UL) /*!< TE (Bit 0) */ + #define R_GWCA0_GWTSDCC0_TE_Msk (0x1UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTSDCC0_DCS_Pos (1UL) /*!< DCS (Bit 1) */ + #define R_GWCA0_GWTSDCC0_DCS_Msk (0x6UL) /*!< DCS (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWTSDCC0_OSID_Pos (8UL) /*!< OSID (Bit 8) */ + #define R_GWCA0_GWTSDCC0_OSID_Msk (0x700UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================= GWTSDCC1 ======================================================== */ + #define R_GWCA0_GWTSDCC1_TE_Pos (0UL) /*!< TE (Bit 0) */ + #define R_GWCA0_GWTSDCC1_TE_Msk (0x1UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTSDCC1_DCS_Pos (1UL) /*!< DCS (Bit 1) */ + #define R_GWCA0_GWTSDCC1_DCS_Msk (0x6UL) /*!< DCS (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWTSDCC1_OSID_Pos (8UL) /*!< OSID (Bit 8) */ + #define R_GWCA0_GWTSDCC1_OSID_Msk (0x700UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWTSNM ========================================================= */ + #define R_GWCA0_GWTSNM_TNTR_Pos (0UL) /*!< TNTR (Bit 0) */ + #define R_GWCA0_GWTSNM_TNTR_Msk (0xffUL) /*!< TNTR (Bitfield-Mask: 0xff) */ +/* ======================================================== GWTSMNM ======================================================== */ + #define R_GWCA0_GWTSMNM_TMNTR_Pos (0UL) /*!< TMNTR (Bit 0) */ + #define R_GWCA0_GWTSMNM_TMNTR_Msk (0xffUL) /*!< TMNTR (Bitfield-Mask: 0xff) */ +/* ========================================================= GWAC ========================================================== */ + #define R_GWCA0_GWAC_AMPR_Pos (0UL) /*!< AMPR (Bit 0) */ + #define R_GWCA0_GWAC_AMPR_Msk (0x1UL) /*!< AMPR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWAC_AMP_Pos (1UL) /*!< AMP (Bit 1) */ + #define R_GWCA0_GWAC_AMP_Msk (0x2UL) /*!< AMP (Bitfield-Mask: 0x01) */ +/* ======================================================= GWDCBAC0 ======================================================== */ + #define R_GWCA0_GWDCBAC0_DCBAUP_Pos (0UL) /*!< DCBAUP (Bit 0) */ + #define R_GWCA0_GWDCBAC0_DCBAUP_Msk (0xffUL) /*!< DCBAUP (Bitfield-Mask: 0xff) */ +/* ======================================================= GWDCBAC1 ======================================================== */ + #define R_GWCA0_GWDCBAC1_DCBADP_Pos (0UL) /*!< DCBADP (Bit 0) */ + #define R_GWCA0_GWDCBAC1_DCBADP_Msk (0xffffffffUL) /*!< DCBADP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GWMDNC ========================================================= */ + #define R_GWCA0_GWMDNC_RXDMN_Pos (0UL) /*!< RXDMN (Bit 0) */ + #define R_GWCA0_GWMDNC_RXDMN_Msk (0x1fUL) /*!< RXDMN (Bitfield-Mask: 0x1f) */ + #define R_GWCA0_GWMDNC_TXDMN_Pos (8UL) /*!< TXDMN (Bit 8) */ + #define R_GWCA0_GWMDNC_TXDMN_Msk (0x1f00UL) /*!< TXDMN (Bitfield-Mask: 0x1f) */ + #define R_GWCA0_GWMDNC_TSDMN_Pos (16UL) /*!< TSDMN (Bit 16) */ + #define R_GWCA0_GWMDNC_TSDMN_Msk (0x30000UL) /*!< TSDMN (Bitfield-Mask: 0x03) */ +/* ======================================================== GWTRC0 ========================================================= */ +/* ======================================================== GWTRC1 ========================================================= */ +/* ======================================================== GWTPC0 ========================================================= */ + #define R_GWCA0_GWTPC0_PPPL0_Pos (0UL) /*!< PPPL0 (Bit 0) */ + #define R_GWCA0_GWTPC0_PPPL0_Msk (0x1UL) /*!< PPPL0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL1_Pos (1UL) /*!< PPPL1 (Bit 1) */ + #define R_GWCA0_GWTPC0_PPPL1_Msk (0x2UL) /*!< PPPL1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL2_Pos (2UL) /*!< PPPL2 (Bit 2) */ + #define R_GWCA0_GWTPC0_PPPL2_Msk (0x4UL) /*!< PPPL2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL3_Pos (3UL) /*!< PPPL3 (Bit 3) */ + #define R_GWCA0_GWTPC0_PPPL3_Msk (0x8UL) /*!< PPPL3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL4_Pos (4UL) /*!< PPPL4 (Bit 4) */ + #define R_GWCA0_GWTPC0_PPPL4_Msk (0x10UL) /*!< PPPL4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL5_Pos (5UL) /*!< PPPL5 (Bit 5) */ + #define R_GWCA0_GWTPC0_PPPL5_Msk (0x20UL) /*!< PPPL5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL6_Pos (6UL) /*!< PPPL6 (Bit 6) */ + #define R_GWCA0_GWTPC0_PPPL6_Msk (0x40UL) /*!< PPPL6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL7_Pos (7UL) /*!< PPPL7 (Bit 7) */ + #define R_GWCA0_GWTPC0_PPPL7_Msk (0x80UL) /*!< PPPL7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL8_Pos (8UL) /*!< PPPL8 (Bit 8) */ + #define R_GWCA0_GWTPC0_PPPL8_Msk (0x100UL) /*!< PPPL8 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWTPC1 ========================================================= */ + #define R_GWCA0_GWTPC1_PPPL0_Pos (0UL) /*!< PPPL0 (Bit 0) */ + #define R_GWCA0_GWTPC1_PPPL0_Msk (0x1UL) /*!< PPPL0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL1_Pos (1UL) /*!< PPPL1 (Bit 1) */ + #define R_GWCA0_GWTPC1_PPPL1_Msk (0x2UL) /*!< PPPL1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL2_Pos (2UL) /*!< PPPL2 (Bit 2) */ + #define R_GWCA0_GWTPC1_PPPL2_Msk (0x4UL) /*!< PPPL2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL3_Pos (3UL) /*!< PPPL3 (Bit 3) */ + #define R_GWCA0_GWTPC1_PPPL3_Msk (0x8UL) /*!< PPPL3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL4_Pos (4UL) /*!< PPPL4 (Bit 4) */ + #define R_GWCA0_GWTPC1_PPPL4_Msk (0x10UL) /*!< PPPL4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL5_Pos (5UL) /*!< PPPL5 (Bit 5) */ + #define R_GWCA0_GWTPC1_PPPL5_Msk (0x20UL) /*!< PPPL5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL6_Pos (6UL) /*!< PPPL6 (Bit 6) */ + #define R_GWCA0_GWTPC1_PPPL6_Msk (0x40UL) /*!< PPPL6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL7_Pos (7UL) /*!< PPPL7 (Bit 7) */ + #define R_GWCA0_GWTPC1_PPPL7_Msk (0x80UL) /*!< PPPL7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL8_Pos (8UL) /*!< PPPL8 (Bit 8) */ + #define R_GWCA0_GWTPC1_PPPL8_Msk (0x100UL) /*!< PPPL8 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWARIRM ======================================================== */ + #define R_GWCA0_GWARIRM_ARIOG_Pos (0UL) /*!< ARIOG (Bit 0) */ + #define R_GWCA0_GWARIRM_ARIOG_Msk (0x1UL) /*!< ARIOG (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWARIRM_ARR_Pos (1UL) /*!< ARR (Bit 1) */ + #define R_GWCA0_GWARIRM_ARR_Msk (0x2UL) /*!< ARR (Bitfield-Mask: 0x01) */ +/* ======================================================== GWDCC0 ========================================================= */ + #define R_GWCA0_GWDCC0_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC0_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC0_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC0_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC0_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC0_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC0_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC0_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC0_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC0_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC0_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC0_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC0_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC0_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC0_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC0_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC1 ========================================================= */ + #define R_GWCA0_GWDCC1_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC1_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC1_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC1_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC1_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC1_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC1_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC1_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC1_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC1_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC1_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC1_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC1_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC1_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC1_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC1_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC2 ========================================================= */ + #define R_GWCA0_GWDCC2_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC2_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC2_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC2_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC2_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC2_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC2_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC2_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC2_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC2_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC2_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC2_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC2_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC2_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC2_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC2_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC3 ========================================================= */ + #define R_GWCA0_GWDCC3_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC3_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC3_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC3_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC3_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC3_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC3_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC3_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC3_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC3_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC3_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC3_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC3_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC3_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC3_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC3_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC4 ========================================================= */ + #define R_GWCA0_GWDCC4_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC4_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC4_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC4_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC4_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC4_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC4_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC4_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC4_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC4_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC4_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC4_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC4_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC4_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC4_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC4_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC5 ========================================================= */ + #define R_GWCA0_GWDCC5_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC5_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC5_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC5_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC5_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC5_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC5_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC5_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC5_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC5_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC5_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC5_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC5_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC5_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC5_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC5_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC6 ========================================================= */ + #define R_GWCA0_GWDCC6_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC6_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC6_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC6_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC6_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC6_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC6_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC6_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC6_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC6_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC6_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC6_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC6_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC6_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC6_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC6_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC7 ========================================================= */ + #define R_GWCA0_GWDCC7_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC7_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC7_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC7_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC7_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC7_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC7_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC7_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC7_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC7_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC7_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC7_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC7_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC7_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC7_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC7_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC8 ========================================================= */ + #define R_GWCA0_GWDCC8_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC8_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC8_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC8_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC8_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC8_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC8_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC8_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC8_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC8_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC8_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC8_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC8_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC8_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC8_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC8_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC9 ========================================================= */ + #define R_GWCA0_GWDCC9_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC9_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC9_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC9_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC9_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC9_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC9_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC9_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC9_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC9_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC9_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC9_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC9_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC9_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC9_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC9_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC10 ======================================================== */ + #define R_GWCA0_GWDCC10_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC10_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC10_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC10_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC10_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC10_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC10_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC10_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC10_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC10_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC10_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC10_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC10_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC10_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC10_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC10_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC11 ======================================================== */ + #define R_GWCA0_GWDCC11_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC11_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC11_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC11_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC11_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC11_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC11_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC11_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC11_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC11_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC11_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC11_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC11_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC11_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC11_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC11_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC12 ======================================================== */ + #define R_GWCA0_GWDCC12_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC12_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC12_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC12_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC12_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC12_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC12_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC12_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC12_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC12_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC12_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC12_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC12_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC12_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC12_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC12_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC13 ======================================================== */ + #define R_GWCA0_GWDCC13_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC13_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC13_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC13_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC13_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC13_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC13_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC13_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC13_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC13_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC13_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC13_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC13_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC13_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC13_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC13_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC14 ======================================================== */ + #define R_GWCA0_GWDCC14_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC14_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC14_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC14_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC14_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC14_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC14_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC14_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC14_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC14_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC14_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC14_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC14_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC14_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC14_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC14_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC15 ======================================================== */ + #define R_GWCA0_GWDCC15_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC15_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC15_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC15_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC15_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC15_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC15_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC15_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC15_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC15_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC15_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC15_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC15_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC15_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC15_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC15_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC16 ======================================================== */ + #define R_GWCA0_GWDCC16_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC16_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC16_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC16_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC16_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC16_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC16_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC16_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC16_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC16_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC16_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC16_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC16_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC16_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC16_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC16_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC17 ======================================================== */ + #define R_GWCA0_GWDCC17_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC17_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC17_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC17_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC17_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC17_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC17_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC17_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC17_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC17_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC17_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC17_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC17_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC17_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC17_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC17_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC18 ======================================================== */ + #define R_GWCA0_GWDCC18_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC18_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC18_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC18_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC18_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC18_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC18_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC18_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC18_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC18_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC18_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC18_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC18_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC18_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC18_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC18_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC19 ======================================================== */ + #define R_GWCA0_GWDCC19_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC19_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC19_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC19_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC19_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC19_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC19_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC19_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC19_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC19_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC19_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC19_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC19_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC19_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC19_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC19_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC20 ======================================================== */ + #define R_GWCA0_GWDCC20_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC20_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC20_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC20_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC20_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC20_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC20_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC20_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC20_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC20_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC20_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC20_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC20_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC20_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC20_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC20_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC21 ======================================================== */ + #define R_GWCA0_GWDCC21_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC21_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC21_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC21_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC21_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC21_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC21_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC21_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC21_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC21_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC21_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC21_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC21_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC21_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC21_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC21_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC22 ======================================================== */ + #define R_GWCA0_GWDCC22_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC22_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC22_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC22_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC22_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC22_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC22_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC22_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC22_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC22_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC22_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC22_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC22_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC22_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC22_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC22_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC23 ======================================================== */ + #define R_GWCA0_GWDCC23_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC23_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC23_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC23_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC23_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC23_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC23_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC23_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC23_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC23_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC23_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC23_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC23_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC23_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC23_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC23_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC24 ======================================================== */ + #define R_GWCA0_GWDCC24_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC24_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC24_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC24_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC24_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC24_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC24_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC24_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC24_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC24_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC24_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC24_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC24_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC24_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC24_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC24_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC25 ======================================================== */ + #define R_GWCA0_GWDCC25_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC25_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC25_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC25_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC25_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC25_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC25_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC25_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC25_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC25_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC25_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC25_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC25_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC25_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC25_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC25_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC26 ======================================================== */ + #define R_GWCA0_GWDCC26_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC26_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC26_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC26_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC26_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC26_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC26_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC26_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC26_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC26_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC26_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC26_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC26_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC26_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC26_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC26_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC27 ======================================================== */ + #define R_GWCA0_GWDCC27_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC27_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC27_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC27_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC27_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC27_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC27_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC27_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC27_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC27_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC27_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC27_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC27_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC27_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC27_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC27_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC28 ======================================================== */ + #define R_GWCA0_GWDCC28_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC28_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC28_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC28_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC28_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC28_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC28_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC28_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC28_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC28_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC28_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC28_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC28_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC28_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC28_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC28_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC29 ======================================================== */ + #define R_GWCA0_GWDCC29_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC29_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC29_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC29_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC29_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC29_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC29_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC29_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC29_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC29_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC29_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC29_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC29_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC29_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC29_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC29_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC30 ======================================================== */ + #define R_GWCA0_GWDCC30_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC30_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC30_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC30_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC30_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC30_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC30_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC30_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC30_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC30_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC30_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC30_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC30_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC30_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC30_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC30_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC31 ======================================================== */ + #define R_GWCA0_GWDCC31_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC31_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC31_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC31_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC31_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC31_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC31_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC31_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC31_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC31_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC31_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC31_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC31_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC31_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC31_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC31_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC32 ======================================================== */ + #define R_GWCA0_GWDCC32_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC32_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC32_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC32_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC32_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC32_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC32_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC32_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC32_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC32_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC32_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC32_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC32_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC32_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC32_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC32_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC33 ======================================================== */ + #define R_GWCA0_GWDCC33_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC33_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC33_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC33_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC33_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC33_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC33_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC33_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC33_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC33_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC33_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC33_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC33_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC33_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC33_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC33_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC34 ======================================================== */ + #define R_GWCA0_GWDCC34_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC34_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC34_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC34_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC34_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC34_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC34_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC34_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC34_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC34_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC34_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC34_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC34_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC34_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC34_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC34_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC35 ======================================================== */ + #define R_GWCA0_GWDCC35_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC35_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC35_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC35_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC35_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC35_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC35_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC35_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC35_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC35_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC35_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC35_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC35_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC35_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC35_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC35_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC36 ======================================================== */ + #define R_GWCA0_GWDCC36_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC36_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC36_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC36_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC36_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC36_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC36_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC36_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC36_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC36_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC36_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC36_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC36_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC36_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC36_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC36_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC37 ======================================================== */ + #define R_GWCA0_GWDCC37_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC37_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC37_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC37_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC37_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC37_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC37_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC37_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC37_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC37_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC37_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC37_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC37_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC37_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC37_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC37_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC38 ======================================================== */ + #define R_GWCA0_GWDCC38_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC38_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC38_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC38_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC38_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC38_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC38_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC38_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC38_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC38_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC38_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC38_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC38_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC38_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC38_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC38_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC39 ======================================================== */ + #define R_GWCA0_GWDCC39_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC39_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC39_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC39_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC39_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC39_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC39_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC39_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC39_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC39_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC39_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC39_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC39_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC39_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC39_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC39_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC40 ======================================================== */ + #define R_GWCA0_GWDCC40_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC40_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC40_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC40_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC40_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC40_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC40_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC40_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC40_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC40_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC40_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC40_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC40_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC40_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC40_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC40_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC41 ======================================================== */ + #define R_GWCA0_GWDCC41_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC41_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC41_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC41_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC41_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC41_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC41_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC41_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC41_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC41_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC41_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC41_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC41_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC41_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC41_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC41_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC42 ======================================================== */ + #define R_GWCA0_GWDCC42_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC42_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC42_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC42_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC42_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC42_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC42_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC42_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC42_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC42_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC42_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC42_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC42_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC42_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC42_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC42_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC43 ======================================================== */ + #define R_GWCA0_GWDCC43_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC43_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC43_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC43_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC43_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC43_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC43_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC43_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC43_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC43_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC43_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC43_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC43_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC43_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC43_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC43_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC44 ======================================================== */ + #define R_GWCA0_GWDCC44_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC44_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC44_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC44_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC44_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC44_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC44_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC44_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC44_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC44_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC44_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC44_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC44_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC44_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC44_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC44_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC45 ======================================================== */ + #define R_GWCA0_GWDCC45_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC45_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC45_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC45_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC45_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC45_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC45_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC45_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC45_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC45_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC45_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC45_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC45_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC45_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC45_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC45_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC46 ======================================================== */ + #define R_GWCA0_GWDCC46_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC46_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC46_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC46_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC46_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC46_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC46_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC46_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC46_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC46_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC46_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC46_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC46_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC46_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC46_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC46_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC47 ======================================================== */ + #define R_GWCA0_GWDCC47_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC47_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC47_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC47_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC47_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC47_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC47_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC47_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC47_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC47_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC47_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC47_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC47_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC47_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC47_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC47_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC48 ======================================================== */ + #define R_GWCA0_GWDCC48_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC48_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC48_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC48_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC48_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC48_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC48_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC48_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC48_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC48_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC48_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC48_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC48_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC48_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC48_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC48_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC49 ======================================================== */ + #define R_GWCA0_GWDCC49_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC49_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC49_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC49_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC49_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC49_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC49_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC49_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC49_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC49_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC49_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC49_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC49_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC49_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC49_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC49_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC50 ======================================================== */ + #define R_GWCA0_GWDCC50_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC50_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC50_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC50_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC50_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC50_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC50_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC50_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC50_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC50_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC50_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC50_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC50_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC50_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC50_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC50_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC51 ======================================================== */ + #define R_GWCA0_GWDCC51_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC51_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC51_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC51_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC51_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC51_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC51_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC51_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC51_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC51_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC51_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC51_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC51_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC51_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC51_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC51_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC52 ======================================================== */ + #define R_GWCA0_GWDCC52_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC52_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC52_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC52_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC52_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC52_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC52_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC52_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC52_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC52_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC52_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC52_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC52_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC52_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC52_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC52_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC53 ======================================================== */ + #define R_GWCA0_GWDCC53_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC53_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC53_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC53_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC53_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC53_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC53_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC53_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC53_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC53_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC53_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC53_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC53_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC53_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC53_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC53_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC54 ======================================================== */ + #define R_GWCA0_GWDCC54_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC54_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC54_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC54_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC54_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC54_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC54_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC54_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC54_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC54_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC54_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC54_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC54_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC54_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC54_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC54_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC55 ======================================================== */ + #define R_GWCA0_GWDCC55_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC55_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC55_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC55_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC55_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC55_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC55_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC55_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC55_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC55_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC55_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC55_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC55_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC55_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC55_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC55_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC56 ======================================================== */ + #define R_GWCA0_GWDCC56_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC56_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC56_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC56_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC56_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC56_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC56_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC56_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC56_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC56_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC56_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC56_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC56_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC56_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC56_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC56_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC57 ======================================================== */ + #define R_GWCA0_GWDCC57_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC57_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC57_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC57_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC57_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC57_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC57_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC57_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC57_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC57_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC57_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC57_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC57_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC57_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC57_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC57_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC58 ======================================================== */ + #define R_GWCA0_GWDCC58_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC58_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC58_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC58_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC58_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC58_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC58_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC58_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC58_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC58_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC58_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC58_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC58_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC58_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC58_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC58_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC59 ======================================================== */ + #define R_GWCA0_GWDCC59_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC59_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC59_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC59_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC59_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC59_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC59_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC59_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC59_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC59_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC59_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC59_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC59_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC59_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC59_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC59_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC60 ======================================================== */ + #define R_GWCA0_GWDCC60_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC60_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC60_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC60_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC60_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC60_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC60_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC60_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC60_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC60_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC60_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC60_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC60_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC60_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC60_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC60_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC61 ======================================================== */ + #define R_GWCA0_GWDCC61_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC61_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC61_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC61_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC61_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC61_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC61_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC61_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC61_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC61_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC61_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC61_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC61_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC61_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC61_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC61_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC62 ======================================================== */ + #define R_GWCA0_GWDCC62_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC62_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC62_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC62_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC62_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC62_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC62_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC62_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC62_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC62_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC62_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC62_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC62_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC62_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC62_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC62_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC63 ======================================================== */ + #define R_GWCA0_GWDCC63_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC63_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC63_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC63_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC63_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC63_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC63_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC63_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC63_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC63_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC63_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC63_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC63_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC63_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC63_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC63_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWAARSS ======================================================== */ + #define R_GWCA0_GWAARSS_AARA_Pos (0UL) /*!< AARA (Bit 0) */ + #define R_GWCA0_GWAARSS_AARA_Msk (0x7fUL) /*!< AARA (Bitfield-Mask: 0x7f) */ +/* ======================================================= GWAARSR0 ======================================================== */ + #define R_GWCA0_GWAARSR0_ACARU_Pos (0UL) /*!< ACARU (Bit 0) */ + #define R_GWCA0_GWAARSR0_ACARU_Msk (0xffUL) /*!< ACARU (Bitfield-Mask: 0xff) */ + #define R_GWCA0_GWAARSR0_AARSEF_Pos (16UL) /*!< AARSEF (Bit 16) */ + #define R_GWCA0_GWAARSR0_AARSEF_Msk (0x10000UL) /*!< AARSEF (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWAARSR0_AARSSF_Pos (17UL) /*!< AARSSF (Bit 17) */ + #define R_GWCA0_GWAARSR0_AARSSF_Msk (0x20000UL) /*!< AARSSF (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWAARSR0_AARS_Pos (31UL) /*!< AARS (Bit 31) */ + #define R_GWCA0_GWAARSR0_AARS_Msk (0x80000000UL) /*!< AARS (Bitfield-Mask: 0x01) */ +/* ======================================================= GWAARSR1 ======================================================== */ + #define R_GWCA0_GWAARSR1_ACARD_Pos (0UL) /*!< ACARD (Bit 0) */ + #define R_GWCA0_GWAARSR1_ACARD_Msk (0xffffffffUL) /*!< ACARD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GWIDAUAS0 ======================================================= */ + #define R_GWCA0_GWIDAUAS0_IDAUAS_Pos (0UL) /*!< IDAUAS (Bit 0) */ + #define R_GWCA0_GWIDAUAS0_IDAUAS_Msk (0xffffffUL) /*!< IDAUAS (Bitfield-Mask: 0xffffff) */ +/* ======================================================= GWIDAUAS1 ======================================================= */ + #define R_GWCA0_GWIDAUAS1_IDAUAS_Pos (0UL) /*!< IDAUAS (Bit 0) */ + #define R_GWCA0_GWIDAUAS1_IDAUAS_Msk (0xffffffUL) /*!< IDAUAS (Bitfield-Mask: 0xffffff) */ +/* ======================================================= GWIDAUAS2 ======================================================= */ + #define R_GWCA0_GWIDAUAS2_IDAUAS_Pos (0UL) /*!< IDAUAS (Bit 0) */ + #define R_GWCA0_GWIDAUAS2_IDAUAS_Msk (0xffffffUL) /*!< IDAUAS (Bitfield-Mask: 0xffffff) */ +/* ======================================================= GWIDAUAS3 ======================================================= */ + #define R_GWCA0_GWIDAUAS3_IDAUAS_Pos (0UL) /*!< IDAUAS (Bit 0) */ + #define R_GWCA0_GWIDAUAS3_IDAUAS_Msk (0xffffffUL) /*!< IDAUAS (Bitfield-Mask: 0xffffff) */ +/* ======================================================= GWIDASM0 ======================================================== */ + #define R_GWCA0_GWIDASM0_IDAS_Pos (0UL) /*!< IDAS (Bit 0) */ + #define R_GWCA0_GWIDASM0_IDAS_Msk (0xffffffUL) /*!< IDAS (Bitfield-Mask: 0xffffff) */ +/* ======================================================= GWIDASM1 ======================================================== */ + #define R_GWCA0_GWIDASM1_IDAS_Pos (0UL) /*!< IDAS (Bit 0) */ + #define R_GWCA0_GWIDASM1_IDAS_Msk (0xffffffUL) /*!< IDAS (Bitfield-Mask: 0xffffff) */ +/* ======================================================= GWIDASM2 ======================================================== */ + #define R_GWCA0_GWIDASM2_IDAS_Pos (0UL) /*!< IDAS (Bit 0) */ + #define R_GWCA0_GWIDASM2_IDAS_Msk (0xffffffUL) /*!< IDAS (Bitfield-Mask: 0xffffff) */ +/* ======================================================= GWIDASM3 ======================================================== */ + #define R_GWCA0_GWIDASM3_IDAS_Pos (0UL) /*!< IDAS (Bit 0) */ + #define R_GWCA0_GWIDASM3_IDAS_Msk (0xffffffUL) /*!< IDAS (Bitfield-Mask: 0xffffff) */ +/* ====================================================== GWIDASAM00 ======================================================= */ + #define R_GWCA0_GWIDASAM00_IDASAU_Pos (0UL) /*!< IDASAU (Bit 0) */ + #define R_GWCA0_GWIDASAM00_IDASAU_Msk (0xffUL) /*!< IDASAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDASAM10 ======================================================= */ + #define R_GWCA0_GWIDASAM10_IDASAL_Pos (0UL) /*!< IDASAL (Bit 0) */ + #define R_GWCA0_GWIDASAM10_IDASAL_Msk (0xffffffffUL) /*!< IDASAL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWIDASAM01 ======================================================= */ + #define R_GWCA0_GWIDASAM01_IDASAU_Pos (0UL) /*!< IDASAU (Bit 0) */ + #define R_GWCA0_GWIDASAM01_IDASAU_Msk (0xffUL) /*!< IDASAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDASAM11 ======================================================= */ + #define R_GWCA0_GWIDASAM11_IDASAL_Pos (0UL) /*!< IDASAL (Bit 0) */ + #define R_GWCA0_GWIDASAM11_IDASAL_Msk (0xffffffffUL) /*!< IDASAL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWIDASAM02 ======================================================= */ + #define R_GWCA0_GWIDASAM02_IDASAU_Pos (0UL) /*!< IDASAU (Bit 0) */ + #define R_GWCA0_GWIDASAM02_IDASAU_Msk (0xffUL) /*!< IDASAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDASAM12 ======================================================= */ + #define R_GWCA0_GWIDASAM12_IDASAL_Pos (0UL) /*!< IDASAL (Bit 0) */ + #define R_GWCA0_GWIDASAM12_IDASAL_Msk (0xffffffffUL) /*!< IDASAL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWIDASAM03 ======================================================= */ + #define R_GWCA0_GWIDASAM03_IDASAU_Pos (0UL) /*!< IDASAU (Bit 0) */ + #define R_GWCA0_GWIDASAM03_IDASAU_Msk (0xffUL) /*!< IDASAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDASAM13 ======================================================= */ + #define R_GWCA0_GWIDASAM13_IDASAL_Pos (0UL) /*!< IDASAL (Bit 0) */ + #define R_GWCA0_GWIDASAM13_IDASAL_Msk (0xffffffffUL) /*!< IDASAL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWIDACAM00 ======================================================= */ + #define R_GWCA0_GWIDACAM00_IDACAU_Pos (0UL) /*!< IDACAU (Bit 0) */ + #define R_GWCA0_GWIDACAM00_IDACAU_Msk (0xffUL) /*!< IDACAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDACAM10 ======================================================= */ + #define R_GWCA0_GWIDACAM10_IDACAL_Pos (0UL) /*!< IDACAL (Bit 0) */ + #define R_GWCA0_GWIDACAM10_IDACAL_Msk (0xffffffffUL) /*!< IDACAL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWIDACAM01 ======================================================= */ + #define R_GWCA0_GWIDACAM01_IDACAU_Pos (0UL) /*!< IDACAU (Bit 0) */ + #define R_GWCA0_GWIDACAM01_IDACAU_Msk (0xffUL) /*!< IDACAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDACAM11 ======================================================= */ + #define R_GWCA0_GWIDACAM11_IDACAL_Pos (0UL) /*!< IDACAL (Bit 0) */ + #define R_GWCA0_GWIDACAM11_IDACAL_Msk (0xffffffffUL) /*!< IDACAL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWIDACAM02 ======================================================= */ + #define R_GWCA0_GWIDACAM02_IDACAU_Pos (0UL) /*!< IDACAU (Bit 0) */ + #define R_GWCA0_GWIDACAM02_IDACAU_Msk (0xffUL) /*!< IDACAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDACAM12 ======================================================= */ + #define R_GWCA0_GWIDACAM12_IDACAL_Pos (0UL) /*!< IDACAL (Bit 0) */ + #define R_GWCA0_GWIDACAM12_IDACAL_Msk (0xffffffffUL) /*!< IDACAL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWIDACAM03 ======================================================= */ + #define R_GWCA0_GWIDACAM03_IDACAU_Pos (0UL) /*!< IDACAU (Bit 0) */ + #define R_GWCA0_GWIDACAM03_IDACAU_Msk (0xffUL) /*!< IDACAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDACAM13 ======================================================= */ + #define R_GWCA0_GWIDACAM13_IDACAL_Pos (0UL) /*!< IDACAL (Bit 0) */ + #define R_GWCA0_GWIDACAM13_IDACAL_Msk (0xffffffffUL) /*!< IDACAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GWGRLC ========================================================= */ + #define R_GWCA0_GWGRLC_GRLIV_Pos (0UL) /*!< GRLIV (Bit 0) */ + #define R_GWCA0_GWGRLC_GRLIV_Msk (0xffffUL) /*!< GRLIV (Bitfield-Mask: 0xffff) */ + #define R_GWCA0_GWGRLC_GRLE_Pos (16UL) /*!< GRLE (Bit 16) */ + #define R_GWCA0_GWGRLC_GRLE_Msk (0x10000UL) /*!< GRLE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWGRLC_GRLULRS_Pos (17UL) /*!< GRLULRS (Bit 17) */ + #define R_GWCA0_GWGRLC_GRLULRS_Msk (0x20000UL) /*!< GRLULRS (Bitfield-Mask: 0x01) */ +/* ======================================================= GWGRLULC ======================================================== */ + #define R_GWCA0_GWGRLULC_GRLUL_Pos (0UL) /*!< GRLUL (Bit 0) */ + #define R_GWCA0_GWGRLULC_GRLUL_Msk (0xffffffUL) /*!< GRLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC0 ========================================================= */ + #define R_GWCA0_GWRLC0_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC0_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC0_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC0_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC0 ======================================================== */ + #define R_GWCA0_GWRLULC0_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC0_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC1 ========================================================= */ + #define R_GWCA0_GWRLC1_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC1_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC1_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC1_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC1 ======================================================== */ + #define R_GWCA0_GWRLULC1_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC1_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC2 ========================================================= */ + #define R_GWCA0_GWRLC2_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC2_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC2_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC2_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC2 ======================================================== */ + #define R_GWCA0_GWRLULC2_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC2_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC3 ========================================================= */ + #define R_GWCA0_GWRLC3_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC3_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC3_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC3_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC3 ======================================================== */ + #define R_GWCA0_GWRLULC3_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC3_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC4 ========================================================= */ + #define R_GWCA0_GWRLC4_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC4_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC4_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC4_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC4 ======================================================== */ + #define R_GWCA0_GWRLULC4_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC4_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC5 ========================================================= */ + #define R_GWCA0_GWRLC5_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC5_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC5_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC5_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC5 ======================================================== */ + #define R_GWCA0_GWRLULC5_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC5_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC6 ========================================================= */ + #define R_GWCA0_GWRLC6_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC6_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC6_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC6_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC6 ======================================================== */ + #define R_GWCA0_GWRLULC6_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC6_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC7 ========================================================= */ + #define R_GWCA0_GWRLC7_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC7_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC7_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC7_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC7 ======================================================== */ + #define R_GWCA0_GWRLULC7_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC7_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWIDPC ========================================================= */ + #define R_GWCA0_GWIDPC_IDPV_Pos (0UL) /*!< IDPV (Bit 0) */ + #define R_GWCA0_GWIDPC_IDPV_Msk (0x3ffUL) /*!< IDPV (Bitfield-Mask: 0x3ff) */ +/* ======================================================== GWIDC0 ========================================================= */ + #define R_GWCA0_GWIDC0_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC0_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC1 ========================================================= */ + #define R_GWCA0_GWIDC1_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC1_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC2 ========================================================= */ + #define R_GWCA0_GWIDC2_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC2_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC3 ========================================================= */ + #define R_GWCA0_GWIDC3_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC3_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC4 ========================================================= */ + #define R_GWCA0_GWIDC4_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC4_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC5 ========================================================= */ + #define R_GWCA0_GWIDC5_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC5_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC6 ========================================================= */ + #define R_GWCA0_GWIDC6_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC6_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC7 ========================================================= */ + #define R_GWCA0_GWIDC7_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC7_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC8 ========================================================= */ + #define R_GWCA0_GWIDC8_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC8_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC9 ========================================================= */ + #define R_GWCA0_GWIDC9_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC9_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC10 ======================================================== */ + #define R_GWCA0_GWIDC10_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC10_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC11 ======================================================== */ + #define R_GWCA0_GWIDC11_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC11_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC12 ======================================================== */ + #define R_GWCA0_GWIDC12_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC12_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC13 ======================================================== */ + #define R_GWCA0_GWIDC13_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC13_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC14 ======================================================== */ + #define R_GWCA0_GWIDC14_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC14_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC15 ======================================================== */ + #define R_GWCA0_GWIDC15_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC15_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC16 ======================================================== */ + #define R_GWCA0_GWIDC16_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC16_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC17 ======================================================== */ + #define R_GWCA0_GWIDC17_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC17_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC18 ======================================================== */ + #define R_GWCA0_GWIDC18_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC18_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC19 ======================================================== */ + #define R_GWCA0_GWIDC19_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC19_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC20 ======================================================== */ + #define R_GWCA0_GWIDC20_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC20_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC21 ======================================================== */ + #define R_GWCA0_GWIDC21_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC21_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC22 ======================================================== */ + #define R_GWCA0_GWIDC22_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC22_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC23 ======================================================== */ + #define R_GWCA0_GWIDC23_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC23_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC24 ======================================================== */ + #define R_GWCA0_GWIDC24_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC24_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC25 ======================================================== */ + #define R_GWCA0_GWIDC25_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC25_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC26 ======================================================== */ + #define R_GWCA0_GWIDC26_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC26_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC27 ======================================================== */ + #define R_GWCA0_GWIDC27_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC27_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC28 ======================================================== */ + #define R_GWCA0_GWIDC28_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC28_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC29 ======================================================== */ + #define R_GWCA0_GWIDC29_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC29_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC30 ======================================================== */ + #define R_GWCA0_GWIDC30_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC30_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC31 ======================================================== */ + #define R_GWCA0_GWIDC31_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC31_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC32 ======================================================== */ + #define R_GWCA0_GWIDC32_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC32_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC33 ======================================================== */ + #define R_GWCA0_GWIDC33_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC33_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC34 ======================================================== */ + #define R_GWCA0_GWIDC34_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC34_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC35 ======================================================== */ + #define R_GWCA0_GWIDC35_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC35_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC36 ======================================================== */ + #define R_GWCA0_GWIDC36_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC36_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC37 ======================================================== */ + #define R_GWCA0_GWIDC37_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC37_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC38 ======================================================== */ + #define R_GWCA0_GWIDC38_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC38_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC39 ======================================================== */ + #define R_GWCA0_GWIDC39_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC39_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC40 ======================================================== */ + #define R_GWCA0_GWIDC40_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC40_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC41 ======================================================== */ + #define R_GWCA0_GWIDC41_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC41_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC42 ======================================================== */ + #define R_GWCA0_GWIDC42_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC42_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC43 ======================================================== */ + #define R_GWCA0_GWIDC43_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC43_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC44 ======================================================== */ + #define R_GWCA0_GWIDC44_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC44_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC45 ======================================================== */ + #define R_GWCA0_GWIDC45_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC45_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC46 ======================================================== */ + #define R_GWCA0_GWIDC46_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC46_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC47 ======================================================== */ + #define R_GWCA0_GWIDC47_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC47_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC48 ======================================================== */ + #define R_GWCA0_GWIDC48_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC48_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC49 ======================================================== */ + #define R_GWCA0_GWIDC49_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC49_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC50 ======================================================== */ + #define R_GWCA0_GWIDC50_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC50_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC51 ======================================================== */ + #define R_GWCA0_GWIDC51_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC51_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC52 ======================================================== */ + #define R_GWCA0_GWIDC52_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC52_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC53 ======================================================== */ + #define R_GWCA0_GWIDC53_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC53_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC54 ======================================================== */ + #define R_GWCA0_GWIDC54_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC54_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC55 ======================================================== */ + #define R_GWCA0_GWIDC55_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC55_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC56 ======================================================== */ + #define R_GWCA0_GWIDC56_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC56_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC57 ======================================================== */ + #define R_GWCA0_GWIDC57_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC57_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC58 ======================================================== */ + #define R_GWCA0_GWIDC58_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC58_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC59 ======================================================== */ + #define R_GWCA0_GWIDC59_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC59_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC60 ======================================================== */ + #define R_GWCA0_GWIDC60_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC60_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC61 ======================================================== */ + #define R_GWCA0_GWIDC61_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC61_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC62 ======================================================== */ + #define R_GWCA0_GWIDC62_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC62_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC63 ======================================================== */ + #define R_GWCA0_GWIDC63_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC63_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC64 ======================================================== */ + #define R_GWCA0_GWIDC64_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC64_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWRDCN ========================================================= */ + #define R_GWCA0_GWRDCN_RDN_Pos (0UL) /*!< RDN (Bit 0) */ + #define R_GWCA0_GWRDCN_RDN_Msk (0xffffffffUL) /*!< RDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GWTDCN ========================================================= */ + #define R_GWCA0_GWTDCN_TDN_Pos (0UL) /*!< TDN (Bit 0) */ + #define R_GWCA0_GWTDCN_TDN_Msk (0xffffffffUL) /*!< TDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GWTSCN ========================================================= */ + #define R_GWCA0_GWTSCN_TN_Pos (0UL) /*!< TN (Bit 0) */ + #define R_GWCA0_GWTSCN_TN_Msk (0xffffffffUL) /*!< TN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWTSOVFECN ======================================================= */ + #define R_GWCA0_GWTSOVFECN_TSOVFEN_Pos (0UL) /*!< TSOVFEN (Bit 0) */ + #define R_GWCA0_GWTSOVFECN_TSOVFEN_Msk (0xffffUL) /*!< TSOVFEN (Bitfield-Mask: 0xffff) */ +/* ====================================================== GWUSMFSECN ======================================================= */ + #define R_GWCA0_GWUSMFSECN_USMFSEN_Pos (0UL) /*!< USMFSEN (Bit 0) */ + #define R_GWCA0_GWUSMFSECN_USMFSEN_Msk (0xffffUL) /*!< USMFSEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== GWTFECN ======================================================== */ + #define R_GWCA0_GWTFECN_TFEN_Pos (0UL) /*!< TFEN (Bit 0) */ + #define R_GWCA0_GWTFECN_TFEN_Msk (0xffffUL) /*!< TFEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWSEQECN ======================================================== */ + #define R_GWCA0_GWSEQECN_SEQEN_Pos (0UL) /*!< SEQEN (Bit 0) */ + #define R_GWCA0_GWSEQECN_SEQEN_Msk (0xffffUL) /*!< SEQEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWTXDNECN ======================================================= */ + #define R_GWCA0_GWTXDNECN_TXDNEN_Pos (0UL) /*!< TXDNEN (Bit 0) */ + #define R_GWCA0_GWTXDNECN_TXDNEN_Msk (0xffffUL) /*!< TXDNEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== GWFSECN ======================================================== */ + #define R_GWCA0_GWFSECN_FSEN_Pos (0UL) /*!< FSEN (Bit 0) */ + #define R_GWCA0_GWFSECN_FSEN_Msk (0xffffUL) /*!< FSEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWTDFECN ======================================================== */ + #define R_GWCA0_GWTDFECN_TDFEN_Pos (0UL) /*!< TDFEN (Bit 0) */ + #define R_GWCA0_GWTDFECN_TDFEN_Msk (0xffffUL) /*!< TDFEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWTSDNECN ======================================================= */ + #define R_GWCA0_GWTSDNECN_TSDNEN_Pos (0UL) /*!< TSDNEN (Bit 0) */ + #define R_GWCA0_GWTSDNECN_TSDNEN_Msk (0xffffUL) /*!< TSDNEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWDQOECN ======================================================== */ + #define R_GWCA0_GWDQOECN_DQOEN_Pos (0UL) /*!< DQOEN (Bit 0) */ + #define R_GWCA0_GWDQOECN_DQOEN_Msk (0xffffUL) /*!< DQOEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWDQSECN ======================================================== */ + #define R_GWCA0_GWDQSECN_DQSEN_Pos (0UL) /*!< DQSEN (Bit 0) */ + #define R_GWCA0_GWDQSECN_DQSEN_Msk (0xffffUL) /*!< DQSEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== GWDFECN ======================================================== */ + #define R_GWCA0_GWDFECN_DFEN_Pos (0UL) /*!< DFEN (Bit 0) */ + #define R_GWCA0_GWDFECN_DFEN_Msk (0xffffUL) /*!< DFEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== GWDSECN ======================================================== */ + #define R_GWCA0_GWDSECN_DSEN_Pos (0UL) /*!< DSEN (Bit 0) */ + #define R_GWCA0_GWDSECN_DSEN_Msk (0xffffUL) /*!< DSEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWDSZECN ======================================================== */ + #define R_GWCA0_GWDSZECN_DSZEN_Pos (0UL) /*!< DSZEN (Bit 0) */ + #define R_GWCA0_GWDSZECN_DSZEN_Msk (0xffffUL) /*!< DSZEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWDCTECN ======================================================== */ + #define R_GWCA0_GWDCTECN_DCTEN_Pos (0UL) /*!< DCTEN (Bit 0) */ + #define R_GWCA0_GWDCTECN_DCTEN_Msk (0xffffUL) /*!< DCTEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRXDNECN ======================================================= */ + #define R_GWCA0_GWRXDNECN_RXDNEN_Pos (0UL) /*!< RXDNEN (Bit 0) */ + #define R_GWCA0_GWRXDNECN_RXDNEN_Msk (0xffffUL) /*!< RXDNEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== GWDIS0 ========================================================= */ +/* ======================================================== GWDIE0 ========================================================= */ +/* ======================================================== GWDID0 ========================================================= */ +/* ======================================================== GWDIDS0 ======================================================== */ +/* ======================================================== GWDIS1 ========================================================= */ +/* ======================================================== GWDIE1 ========================================================= */ +/* ======================================================== GWDID1 ========================================================= */ +/* ======================================================== GWDIDS1 ======================================================== */ +/* ======================================================== GWTSDIS ======================================================== */ + #define R_GWCA0_GWTSDIS_TSDIS0_Pos (0UL) /*!< TSDIS0 (Bit 0) */ + #define R_GWCA0_GWTSDIS_TSDIS0_Msk (0x1UL) /*!< TSDIS0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTSDIS_TSDIS1_Pos (1UL) /*!< TSDIS1 (Bit 1) */ + #define R_GWCA0_GWTSDIS_TSDIS1_Msk (0x2UL) /*!< TSDIS1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWTSDIE ======================================================== */ + #define R_GWCA0_GWTSDIE_TSDIE0_Pos (0UL) /*!< TSDIE0 (Bit 0) */ + #define R_GWCA0_GWTSDIE_TSDIE0_Msk (0x1UL) /*!< TSDIE0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTSDIE_TSDIE1_Pos (1UL) /*!< TSDIE1 (Bit 1) */ + #define R_GWCA0_GWTSDIE_TSDIE1_Msk (0x2UL) /*!< TSDIE1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWTSDID ======================================================== */ + #define R_GWCA0_GWTSDID_TSDID0_Pos (0UL) /*!< TSDID0 (Bit 0) */ + #define R_GWCA0_GWTSDID_TSDID0_Msk (0x1UL) /*!< TSDID0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTSDID_TSDID1_Pos (1UL) /*!< TSDID1 (Bit 1) */ + #define R_GWCA0_GWTSDID_TSDID1_Msk (0x2UL) /*!< TSDID1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIS0 ========================================================= */ + #define R_GWCA0_GWEIS0_AES_Pos (0UL) /*!< AES (Bit 0) */ + #define R_GWCA0_GWEIS0_AES_Msk (0x1UL) /*!< AES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_DECCES_Pos (1UL) /*!< DECCES (Bit 1) */ + #define R_GWCA0_GWEIS0_DECCES_Msk (0x2UL) /*!< DECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TECCES_Pos (2UL) /*!< TECCES (Bit 2) */ + #define R_GWCA0_GWEIS0_TECCES_Msk (0x4UL) /*!< TECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_PECCES_Pos (3UL) /*!< PECCES (Bit 3) */ + #define R_GWCA0_GWEIS0_PECCES_Msk (0x8UL) /*!< PECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_DSECCES_Pos (4UL) /*!< DSECCES (Bit 4) */ + #define R_GWCA0_GWEIS0_DSECCES_Msk (0x10UL) /*!< DSECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_MECCES_Pos (5UL) /*!< MECCES (Bit 5) */ + #define R_GWCA0_GWEIS0_MECCES_Msk (0x20UL) /*!< MECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_AECCES_Pos (6UL) /*!< AECCES (Bit 6) */ + #define R_GWCA0_GWEIS0_AECCES_Msk (0x40UL) /*!< AECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TSECCES_Pos (7UL) /*!< TSECCES (Bit 7) */ + #define R_GWCA0_GWEIS0_TSECCES_Msk (0x80UL) /*!< TSECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_L23UECCES_Pos (8UL) /*!< L23UECCES (Bit 8) */ + #define R_GWCA0_GWEIS0_L23UECCES_Msk (0x100UL) /*!< L23UECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TSOVFES_Pos (9UL) /*!< TSOVFES (Bit 9) */ + #define R_GWCA0_GWEIS0_TSOVFES_Msk (0x200UL) /*!< TSOVFES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_USMFSES_Pos (10UL) /*!< USMFSES (Bit 10) */ + #define R_GWCA0_GWEIS0_USMFSES_Msk (0x400UL) /*!< USMFSES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TFES_Pos (11UL) /*!< TFES (Bit 11) */ + #define R_GWCA0_GWEIS0_TFES_Msk (0x800UL) /*!< TFES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_SEQES_Pos (12UL) /*!< SEQES (Bit 12) */ + #define R_GWCA0_GWEIS0_SEQES_Msk (0x1000UL) /*!< SEQES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TXDNES_Pos (14UL) /*!< TXDNES (Bit 14) */ + #define R_GWCA0_GWEIS0_TXDNES_Msk (0x4000UL) /*!< TXDNES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TSHES_Pos (15UL) /*!< TSHES (Bit 15) */ + #define R_GWCA0_GWEIS0_TSHES_Msk (0x8000UL) /*!< TSHES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES0_Pos (16UL) /*!< FSES0 (Bit 16) */ + #define R_GWCA0_GWEIS0_FSES0_Msk (0x10000UL) /*!< FSES0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES1_Pos (17UL) /*!< FSES1 (Bit 17) */ + #define R_GWCA0_GWEIS0_FSES1_Msk (0x20000UL) /*!< FSES1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES2_Pos (18UL) /*!< FSES2 (Bit 18) */ + #define R_GWCA0_GWEIS0_FSES2_Msk (0x40000UL) /*!< FSES2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES3_Pos (19UL) /*!< FSES3 (Bit 19) */ + #define R_GWCA0_GWEIS0_FSES3_Msk (0x80000UL) /*!< FSES3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES4_Pos (20UL) /*!< FSES4 (Bit 20) */ + #define R_GWCA0_GWEIS0_FSES4_Msk (0x100000UL) /*!< FSES4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES5_Pos (21UL) /*!< FSES5 (Bit 21) */ + #define R_GWCA0_GWEIS0_FSES5_Msk (0x200000UL) /*!< FSES5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES6_Pos (22UL) /*!< FSES6 (Bit 22) */ + #define R_GWCA0_GWEIS0_FSES6_Msk (0x400000UL) /*!< FSES6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES7_Pos (23UL) /*!< FSES7 (Bit 23) */ + #define R_GWCA0_GWEIS0_FSES7_Msk (0x800000UL) /*!< FSES7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TDFES0_Pos (24UL) /*!< TDFES0 (Bit 24) */ + #define R_GWCA0_GWEIS0_TDFES0_Msk (0x1000000UL) /*!< TDFES0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TDFES1_Pos (25UL) /*!< TDFES1 (Bit 25) */ + #define R_GWCA0_GWEIS0_TDFES1_Msk (0x2000000UL) /*!< TDFES1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TSDNES0_Pos (28UL) /*!< TSDNES0 (Bit 28) */ + #define R_GWCA0_GWEIS0_TSDNES0_Msk (0x10000000UL) /*!< TSDNES0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TSDNES1_Pos (29UL) /*!< TSDNES1 (Bit 29) */ + #define R_GWCA0_GWEIS0_TSDNES1_Msk (0x20000000UL) /*!< TSDNES1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIE0 ========================================================= */ + #define R_GWCA0_GWEIE0_AEE_Pos (0UL) /*!< AEE (Bit 0) */ + #define R_GWCA0_GWEIE0_AEE_Msk (0x1UL) /*!< AEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_DECCEE_Pos (1UL) /*!< DECCEE (Bit 1) */ + #define R_GWCA0_GWEIE0_DECCEE_Msk (0x2UL) /*!< DECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TECCEE_Pos (2UL) /*!< TECCEE (Bit 2) */ + #define R_GWCA0_GWEIE0_TECCEE_Msk (0x4UL) /*!< TECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_PECCEE_Pos (3UL) /*!< PECCEE (Bit 3) */ + #define R_GWCA0_GWEIE0_PECCEE_Msk (0x8UL) /*!< PECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_DSECCEE_Pos (4UL) /*!< DSECCEE (Bit 4) */ + #define R_GWCA0_GWEIE0_DSECCEE_Msk (0x10UL) /*!< DSECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_MECCEE_Pos (5UL) /*!< MECCEE (Bit 5) */ + #define R_GWCA0_GWEIE0_MECCEE_Msk (0x20UL) /*!< MECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_AECCEE_Pos (6UL) /*!< AECCEE (Bit 6) */ + #define R_GWCA0_GWEIE0_AECCEE_Msk (0x40UL) /*!< AECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TSECCEE_Pos (7UL) /*!< TSECCEE (Bit 7) */ + #define R_GWCA0_GWEIE0_TSECCEE_Msk (0x80UL) /*!< TSECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_L23UECCEE_Pos (8UL) /*!< L23UECCEE (Bit 8) */ + #define R_GWCA0_GWEIE0_L23UECCEE_Msk (0x100UL) /*!< L23UECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TSOVFEE_Pos (9UL) /*!< TSOVFEE (Bit 9) */ + #define R_GWCA0_GWEIE0_TSOVFEE_Msk (0x200UL) /*!< TSOVFEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_USMFSEE_Pos (10UL) /*!< USMFSEE (Bit 10) */ + #define R_GWCA0_GWEIE0_USMFSEE_Msk (0x400UL) /*!< USMFSEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TFEE_Pos (11UL) /*!< TFEE (Bit 11) */ + #define R_GWCA0_GWEIE0_TFEE_Msk (0x800UL) /*!< TFEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_SEQEE_Pos (12UL) /*!< SEQEE (Bit 12) */ + #define R_GWCA0_GWEIE0_SEQEE_Msk (0x1000UL) /*!< SEQEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TXDNEE_Pos (14UL) /*!< TXDNEE (Bit 14) */ + #define R_GWCA0_GWEIE0_TXDNEE_Msk (0x4000UL) /*!< TXDNEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TSHEE_Pos (15UL) /*!< TSHEE (Bit 15) */ + #define R_GWCA0_GWEIE0_TSHEE_Msk (0x8000UL) /*!< TSHEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE0_Pos (16UL) /*!< FSEE0 (Bit 16) */ + #define R_GWCA0_GWEIE0_FSEE0_Msk (0x10000UL) /*!< FSEE0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE1_Pos (17UL) /*!< FSEE1 (Bit 17) */ + #define R_GWCA0_GWEIE0_FSEE1_Msk (0x20000UL) /*!< FSEE1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE2_Pos (18UL) /*!< FSEE2 (Bit 18) */ + #define R_GWCA0_GWEIE0_FSEE2_Msk (0x40000UL) /*!< FSEE2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE3_Pos (19UL) /*!< FSEE3 (Bit 19) */ + #define R_GWCA0_GWEIE0_FSEE3_Msk (0x80000UL) /*!< FSEE3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE4_Pos (20UL) /*!< FSEE4 (Bit 20) */ + #define R_GWCA0_GWEIE0_FSEE4_Msk (0x100000UL) /*!< FSEE4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE5_Pos (21UL) /*!< FSEE5 (Bit 21) */ + #define R_GWCA0_GWEIE0_FSEE5_Msk (0x200000UL) /*!< FSEE5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE6_Pos (22UL) /*!< FSEE6 (Bit 22) */ + #define R_GWCA0_GWEIE0_FSEE6_Msk (0x400000UL) /*!< FSEE6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE7_Pos (23UL) /*!< FSEE7 (Bit 23) */ + #define R_GWCA0_GWEIE0_FSEE7_Msk (0x800000UL) /*!< FSEE7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TDFEE0_Pos (24UL) /*!< TDFEE0 (Bit 24) */ + #define R_GWCA0_GWEIE0_TDFEE0_Msk (0x1000000UL) /*!< TDFEE0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TDFEE1_Pos (25UL) /*!< TDFEE1 (Bit 25) */ + #define R_GWCA0_GWEIE0_TDFEE1_Msk (0x2000000UL) /*!< TDFEE1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TSDNEE0_Pos (28UL) /*!< TSDNEE0 (Bit 28) */ + #define R_GWCA0_GWEIE0_TSDNEE0_Msk (0x10000000UL) /*!< TSDNEE0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TSDNEE1_Pos (29UL) /*!< TSDNEE1 (Bit 29) */ + #define R_GWCA0_GWEIE0_TSDNEE1_Msk (0x20000000UL) /*!< TSDNEE1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEID0 ========================================================= */ + #define R_GWCA0_GWEID0_AED_Pos (0UL) /*!< AED (Bit 0) */ + #define R_GWCA0_GWEID0_AED_Msk (0x1UL) /*!< AED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TECCED_Pos (1UL) /*!< TECCED (Bit 1) */ + #define R_GWCA0_GWEID0_TECCED_Msk (0x2UL) /*!< TECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_DECCED_Pos (2UL) /*!< DECCED (Bit 2) */ + #define R_GWCA0_GWEID0_DECCED_Msk (0x4UL) /*!< DECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_PECCED_Pos (3UL) /*!< PECCED (Bit 3) */ + #define R_GWCA0_GWEID0_PECCED_Msk (0x8UL) /*!< PECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_DSECCED_Pos (4UL) /*!< DSECCED (Bit 4) */ + #define R_GWCA0_GWEID0_DSECCED_Msk (0x10UL) /*!< DSECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_MECCED_Pos (5UL) /*!< MECCED (Bit 5) */ + #define R_GWCA0_GWEID0_MECCED_Msk (0x20UL) /*!< MECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_AECCED_Pos (6UL) /*!< AECCED (Bit 6) */ + #define R_GWCA0_GWEID0_AECCED_Msk (0x40UL) /*!< AECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TSECCED_Pos (7UL) /*!< TSECCED (Bit 7) */ + #define R_GWCA0_GWEID0_TSECCED_Msk (0x80UL) /*!< TSECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_L23UECCED_Pos (8UL) /*!< L23UECCED (Bit 8) */ + #define R_GWCA0_GWEID0_L23UECCED_Msk (0x100UL) /*!< L23UECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TSOVFED_Pos (9UL) /*!< TSOVFED (Bit 9) */ + #define R_GWCA0_GWEID0_TSOVFED_Msk (0x200UL) /*!< TSOVFED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_USMFSED_Pos (10UL) /*!< USMFSED (Bit 10) */ + #define R_GWCA0_GWEID0_USMFSED_Msk (0x400UL) /*!< USMFSED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TFED_Pos (11UL) /*!< TFED (Bit 11) */ + #define R_GWCA0_GWEID0_TFED_Msk (0x800UL) /*!< TFED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_SEQED_Pos (12UL) /*!< SEQED (Bit 12) */ + #define R_GWCA0_GWEID0_SEQED_Msk (0x1000UL) /*!< SEQED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_IIPED_Pos (13UL) /*!< IIPED (Bit 13) */ + #define R_GWCA0_GWEID0_IIPED_Msk (0x2000UL) /*!< IIPED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TXDNED_Pos (14UL) /*!< TXDNED (Bit 14) */ + #define R_GWCA0_GWEID0_TXDNED_Msk (0x4000UL) /*!< TXDNED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TSHED_Pos (15UL) /*!< TSHED (Bit 15) */ + #define R_GWCA0_GWEID0_TSHED_Msk (0x8000UL) /*!< TSHED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED0_Pos (16UL) /*!< FSED0 (Bit 16) */ + #define R_GWCA0_GWEID0_FSED0_Msk (0x10000UL) /*!< FSED0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED1_Pos (17UL) /*!< FSED1 (Bit 17) */ + #define R_GWCA0_GWEID0_FSED1_Msk (0x20000UL) /*!< FSED1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED2_Pos (18UL) /*!< FSED2 (Bit 18) */ + #define R_GWCA0_GWEID0_FSED2_Msk (0x40000UL) /*!< FSED2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED3_Pos (19UL) /*!< FSED3 (Bit 19) */ + #define R_GWCA0_GWEID0_FSED3_Msk (0x80000UL) /*!< FSED3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED4_Pos (20UL) /*!< FSED4 (Bit 20) */ + #define R_GWCA0_GWEID0_FSED4_Msk (0x100000UL) /*!< FSED4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED5_Pos (21UL) /*!< FSED5 (Bit 21) */ + #define R_GWCA0_GWEID0_FSED5_Msk (0x200000UL) /*!< FSED5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED6_Pos (22UL) /*!< FSED6 (Bit 22) */ + #define R_GWCA0_GWEID0_FSED6_Msk (0x400000UL) /*!< FSED6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED7_Pos (23UL) /*!< FSED7 (Bit 23) */ + #define R_GWCA0_GWEID0_FSED7_Msk (0x800000UL) /*!< FSED7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TDFED0_Pos (24UL) /*!< TDFED0 (Bit 24) */ + #define R_GWCA0_GWEID0_TDFED0_Msk (0x1000000UL) /*!< TDFED0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TDFED1_Pos (25UL) /*!< TDFED1 (Bit 25) */ + #define R_GWCA0_GWEID0_TDFED1_Msk (0x2000000UL) /*!< TDFED1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TSDNED0_Pos (28UL) /*!< TSDNED0 (Bit 28) */ + #define R_GWCA0_GWEID0_TSDNED0_Msk (0x10000000UL) /*!< TSDNED0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TSDNED1_Pos (29UL) /*!< TSDNED1 (Bit 29) */ + #define R_GWCA0_GWEID0_TSDNED1_Msk (0x20000000UL) /*!< TSDNED1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIS1 ========================================================= */ + #define R_GWCA0_GWEIS1_DQOES0_Pos (0UL) /*!< DQOES0 (Bit 0) */ + #define R_GWCA0_GWEIS1_DQOES0_Msk (0x1UL) /*!< DQOES0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQOES1_Pos (1UL) /*!< DQOES1 (Bit 1) */ + #define R_GWCA0_GWEIS1_DQOES1_Msk (0x2UL) /*!< DQOES1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQOES2_Pos (2UL) /*!< DQOES2 (Bit 2) */ + #define R_GWCA0_GWEIS1_DQOES2_Msk (0x4UL) /*!< DQOES2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQOES3_Pos (3UL) /*!< DQOES3 (Bit 3) */ + #define R_GWCA0_GWEIS1_DQOES3_Msk (0x8UL) /*!< DQOES3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQOES4_Pos (4UL) /*!< DQOES4 (Bit 4) */ + #define R_GWCA0_GWEIS1_DQOES4_Msk (0x10UL) /*!< DQOES4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQOES5_Pos (5UL) /*!< DQOES5 (Bit 5) */ + #define R_GWCA0_GWEIS1_DQOES5_Msk (0x20UL) /*!< DQOES5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQOES6_Pos (6UL) /*!< DQOES6 (Bit 6) */ + #define R_GWCA0_GWEIS1_DQOES6_Msk (0x40UL) /*!< DQOES6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQOES7_Pos (7UL) /*!< DQOES7 (Bit 7) */ + #define R_GWCA0_GWEIS1_DQOES7_Msk (0x80UL) /*!< DQOES7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES0_Pos (16UL) /*!< DQSES0 (Bit 16) */ + #define R_GWCA0_GWEIS1_DQSES0_Msk (0x10000UL) /*!< DQSES0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES1_Pos (17UL) /*!< DQSES1 (Bit 17) */ + #define R_GWCA0_GWEIS1_DQSES1_Msk (0x20000UL) /*!< DQSES1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES2_Pos (18UL) /*!< DQSES2 (Bit 18) */ + #define R_GWCA0_GWEIS1_DQSES2_Msk (0x40000UL) /*!< DQSES2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES3_Pos (19UL) /*!< DQSES3 (Bit 19) */ + #define R_GWCA0_GWEIS1_DQSES3_Msk (0x80000UL) /*!< DQSES3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES4_Pos (20UL) /*!< DQSES4 (Bit 20) */ + #define R_GWCA0_GWEIS1_DQSES4_Msk (0x100000UL) /*!< DQSES4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES5_Pos (21UL) /*!< DQSES5 (Bit 21) */ + #define R_GWCA0_GWEIS1_DQSES5_Msk (0x200000UL) /*!< DQSES5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES6_Pos (22UL) /*!< DQSES6 (Bit 22) */ + #define R_GWCA0_GWEIS1_DQSES6_Msk (0x400000UL) /*!< DQSES6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES7_Pos (23UL) /*!< DQSES7 (Bit 23) */ + #define R_GWCA0_GWEIS1_DQSES7_Msk (0x800000UL) /*!< DQSES7 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIE1 ========================================================= */ + #define R_GWCA0_GWEIE1_DQOEE0_Pos (0UL) /*!< DQOEE0 (Bit 0) */ + #define R_GWCA0_GWEIE1_DQOEE0_Msk (0x1UL) /*!< DQOEE0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQOEE1_Pos (1UL) /*!< DQOEE1 (Bit 1) */ + #define R_GWCA0_GWEIE1_DQOEE1_Msk (0x2UL) /*!< DQOEE1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQOEE2_Pos (2UL) /*!< DQOEE2 (Bit 2) */ + #define R_GWCA0_GWEIE1_DQOEE2_Msk (0x4UL) /*!< DQOEE2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQOEE3_Pos (3UL) /*!< DQOEE3 (Bit 3) */ + #define R_GWCA0_GWEIE1_DQOEE3_Msk (0x8UL) /*!< DQOEE3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQOEE4_Pos (4UL) /*!< DQOEE4 (Bit 4) */ + #define R_GWCA0_GWEIE1_DQOEE4_Msk (0x10UL) /*!< DQOEE4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQOEE5_Pos (5UL) /*!< DQOEE5 (Bit 5) */ + #define R_GWCA0_GWEIE1_DQOEE5_Msk (0x20UL) /*!< DQOEE5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQOEE6_Pos (6UL) /*!< DQOEE6 (Bit 6) */ + #define R_GWCA0_GWEIE1_DQOEE6_Msk (0x40UL) /*!< DQOEE6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQOEE7_Pos (7UL) /*!< DQOEE7 (Bit 7) */ + #define R_GWCA0_GWEIE1_DQOEE7_Msk (0x80UL) /*!< DQOEE7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE0_Pos (16UL) /*!< DQSEE0 (Bit 16) */ + #define R_GWCA0_GWEIE1_DQSEE0_Msk (0x10000UL) /*!< DQSEE0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE1_Pos (17UL) /*!< DQSEE1 (Bit 17) */ + #define R_GWCA0_GWEIE1_DQSEE1_Msk (0x20000UL) /*!< DQSEE1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE2_Pos (18UL) /*!< DQSEE2 (Bit 18) */ + #define R_GWCA0_GWEIE1_DQSEE2_Msk (0x40000UL) /*!< DQSEE2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE3_Pos (19UL) /*!< DQSEE3 (Bit 19) */ + #define R_GWCA0_GWEIE1_DQSEE3_Msk (0x80000UL) /*!< DQSEE3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE4_Pos (20UL) /*!< DQSEE4 (Bit 20) */ + #define R_GWCA0_GWEIE1_DQSEE4_Msk (0x100000UL) /*!< DQSEE4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE5_Pos (21UL) /*!< DQSEE5 (Bit 21) */ + #define R_GWCA0_GWEIE1_DQSEE5_Msk (0x200000UL) /*!< DQSEE5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE6_Pos (22UL) /*!< DQSEE6 (Bit 22) */ + #define R_GWCA0_GWEIE1_DQSEE6_Msk (0x400000UL) /*!< DQSEE6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE7_Pos (23UL) /*!< DQSEE7 (Bit 23) */ + #define R_GWCA0_GWEIE1_DQSEE7_Msk (0x800000UL) /*!< DQSEE7 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEID1 ========================================================= */ + #define R_GWCA0_GWEID1_DQOED0_Pos (0UL) /*!< DQOED0 (Bit 0) */ + #define R_GWCA0_GWEID1_DQOED0_Msk (0x1UL) /*!< DQOED0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQOED1_Pos (1UL) /*!< DQOED1 (Bit 1) */ + #define R_GWCA0_GWEID1_DQOED1_Msk (0x2UL) /*!< DQOED1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQOED2_Pos (2UL) /*!< DQOED2 (Bit 2) */ + #define R_GWCA0_GWEID1_DQOED2_Msk (0x4UL) /*!< DQOED2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQOED3_Pos (3UL) /*!< DQOED3 (Bit 3) */ + #define R_GWCA0_GWEID1_DQOED3_Msk (0x8UL) /*!< DQOED3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQOED4_Pos (4UL) /*!< DQOED4 (Bit 4) */ + #define R_GWCA0_GWEID1_DQOED4_Msk (0x10UL) /*!< DQOED4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQOED5_Pos (5UL) /*!< DQOED5 (Bit 5) */ + #define R_GWCA0_GWEID1_DQOED5_Msk (0x20UL) /*!< DQOED5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQOED6_Pos (6UL) /*!< DQOED6 (Bit 6) */ + #define R_GWCA0_GWEID1_DQOED6_Msk (0x40UL) /*!< DQOED6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQOED7_Pos (7UL) /*!< DQOED7 (Bit 7) */ + #define R_GWCA0_GWEID1_DQOED7_Msk (0x80UL) /*!< DQOED7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED0_Pos (16UL) /*!< DQSED0 (Bit 16) */ + #define R_GWCA0_GWEID1_DQSED0_Msk (0x10000UL) /*!< DQSED0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED1_Pos (17UL) /*!< DQSED1 (Bit 17) */ + #define R_GWCA0_GWEID1_DQSED1_Msk (0x20000UL) /*!< DQSED1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED2_Pos (18UL) /*!< DQSED2 (Bit 18) */ + #define R_GWCA0_GWEID1_DQSED2_Msk (0x40000UL) /*!< DQSED2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED3_Pos (19UL) /*!< DQSED3 (Bit 19) */ + #define R_GWCA0_GWEID1_DQSED3_Msk (0x80000UL) /*!< DQSED3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED4_Pos (20UL) /*!< DQSED4 (Bit 20) */ + #define R_GWCA0_GWEID1_DQSED4_Msk (0x100000UL) /*!< DQSED4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED5_Pos (21UL) /*!< DQSED5 (Bit 21) */ + #define R_GWCA0_GWEID1_DQSED5_Msk (0x200000UL) /*!< DQSED5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED6_Pos (22UL) /*!< DQSED6 (Bit 22) */ + #define R_GWCA0_GWEID1_DQSED6_Msk (0x400000UL) /*!< DQSED6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED7_Pos (23UL) /*!< DQSED7 (Bit 23) */ + #define R_GWCA0_GWEID1_DQSED7_Msk (0x800000UL) /*!< DQSED7 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIS20 ======================================================== */ +/* ======================================================== GWEIE20 ======================================================== */ +/* ======================================================== GWEID20 ======================================================== */ +/* ======================================================== GWEIS21 ======================================================== */ +/* ======================================================== GWEIE21 ======================================================== */ +/* ======================================================== GWEID21 ======================================================== */ +/* ======================================================== GWEIS3 ========================================================= */ + #define R_GWCA0_GWEIS3_IAOES0_Pos (0UL) /*!< IAOES0 (Bit 0) */ + #define R_GWCA0_GWEIS3_IAOES0_Msk (0x1UL) /*!< IAOES0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS3_IAOES1_Pos (1UL) /*!< IAOES1 (Bit 1) */ + #define R_GWCA0_GWEIS3_IAOES1_Msk (0x2UL) /*!< IAOES1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS3_IAOES2_Pos (2UL) /*!< IAOES2 (Bit 2) */ + #define R_GWCA0_GWEIS3_IAOES2_Msk (0x4UL) /*!< IAOES2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS3_IAOES3_Pos (3UL) /*!< IAOES3 (Bit 3) */ + #define R_GWCA0_GWEIS3_IAOES3_Msk (0x8UL) /*!< IAOES3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS3_IAOES4_Pos (4UL) /*!< IAOES4 (Bit 4) */ + #define R_GWCA0_GWEIS3_IAOES4_Msk (0x10UL) /*!< IAOES4 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIE3 ========================================================= */ + #define R_GWCA0_GWEIE3_IAOEE0_Pos (0UL) /*!< IAOEE0 (Bit 0) */ + #define R_GWCA0_GWEIE3_IAOEE0_Msk (0x1UL) /*!< IAOEE0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE3_IAOEE1_Pos (1UL) /*!< IAOEE1 (Bit 1) */ + #define R_GWCA0_GWEIE3_IAOEE1_Msk (0x2UL) /*!< IAOEE1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE3_IAOEE2_Pos (2UL) /*!< IAOEE2 (Bit 2) */ + #define R_GWCA0_GWEIE3_IAOEE2_Msk (0x4UL) /*!< IAOEE2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE3_IAOEE3_Pos (3UL) /*!< IAOEE3 (Bit 3) */ + #define R_GWCA0_GWEIE3_IAOEE3_Msk (0x8UL) /*!< IAOEE3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE3_IAOEE4_Pos (4UL) /*!< IAOEE4 (Bit 4) */ + #define R_GWCA0_GWEIE3_IAOEE4_Msk (0x10UL) /*!< IAOEE4 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEID3 ========================================================= */ + #define R_GWCA0_GWEID3_IAOED0_Pos (0UL) /*!< IAOED0 (Bit 0) */ + #define R_GWCA0_GWEID3_IAOED0_Msk (0x1UL) /*!< IAOED0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID3_IAOED1_Pos (1UL) /*!< IAOED1 (Bit 1) */ + #define R_GWCA0_GWEID3_IAOED1_Msk (0x2UL) /*!< IAOED1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID3_IAOED2_Pos (2UL) /*!< IAOED2 (Bit 2) */ + #define R_GWCA0_GWEID3_IAOED2_Msk (0x4UL) /*!< IAOED2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID3_IAOED3_Pos (3UL) /*!< IAOED3 (Bit 3) */ + #define R_GWCA0_GWEID3_IAOED3_Msk (0x8UL) /*!< IAOED3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID3_IAOED4_Pos (4UL) /*!< IAOED4 (Bit 4) */ + #define R_GWCA0_GWEID3_IAOED4_Msk (0x10UL) /*!< IAOED4 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIS4 ========================================================= */ + #define R_GWCA0_GWEIS4_DSSES_Pos (0UL) /*!< DSSES (Bit 0) */ + #define R_GWCA0_GWEIS4_DSSES_Msk (0x1UL) /*!< DSSES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS4_DSSEIOS_Pos (1UL) /*!< DSSEIOS (Bit 1) */ + #define R_GWCA0_GWEIS4_DSSEIOS_Msk (0x2UL) /*!< DSSEIOS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS4_DSSECN_Pos (8UL) /*!< DSSECN (Bit 8) */ + #define R_GWCA0_GWEIS4_DSSECN_Msk (0x3f00UL) /*!< DSSECN (Bitfield-Mask: 0x3f) */ + #define R_GWCA0_GWEIS4_DSES_Pos (16UL) /*!< DSES (Bit 16) */ + #define R_GWCA0_GWEIS4_DSES_Msk (0x10000UL) /*!< DSES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS4_DSEIOS_Pos (17UL) /*!< DSEIOS (Bit 17) */ + #define R_GWCA0_GWEIS4_DSEIOS_Msk (0x20000UL) /*!< DSEIOS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS4_DSECN_Pos (24UL) /*!< DSECN (Bit 24) */ + #define R_GWCA0_GWEIS4_DSECN_Msk (0x3f000000UL) /*!< DSECN (Bitfield-Mask: 0x3f) */ +/* ======================================================== GWEIE4 ========================================================= */ + #define R_GWCA0_GWEIE4_DSSEE_Pos (0UL) /*!< DSSEE (Bit 0) */ + #define R_GWCA0_GWEIE4_DSSEE_Msk (0x1UL) /*!< DSSEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE4_DSSEIOE_Pos (1UL) /*!< DSSEIOE (Bit 1) */ + #define R_GWCA0_GWEIE4_DSSEIOE_Msk (0x2UL) /*!< DSSEIOE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE4_DSEE_Pos (16UL) /*!< DSEE (Bit 16) */ + #define R_GWCA0_GWEIE4_DSEE_Msk (0x10000UL) /*!< DSEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE4_DSEIOE_Pos (17UL) /*!< DSEIOE (Bit 17) */ + #define R_GWCA0_GWEIE4_DSEIOE_Msk (0x20000UL) /*!< DSEIOE (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEID4 ========================================================= */ + #define R_GWCA0_GWEID4_DSSED_Pos (0UL) /*!< DSSED (Bit 0) */ + #define R_GWCA0_GWEID4_DSSED_Msk (0x1UL) /*!< DSSED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID4_DSSEIOD_Pos (1UL) /*!< DSSEIOD (Bit 1) */ + #define R_GWCA0_GWEID4_DSSEIOD_Msk (0x2UL) /*!< DSSEIOD (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID4_DSED_Pos (16UL) /*!< DSED (Bit 16) */ + #define R_GWCA0_GWEID4_DSED_Msk (0x10000UL) /*!< DSED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID4_DSEIOD_Pos (17UL) /*!< DSEIOD (Bit 17) */ + #define R_GWCA0_GWEID4_DSEIOD_Msk (0x20000UL) /*!< DSEIOD (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIS5 ========================================================= */ + #define R_GWCA0_GWEIS5_DCTES_Pos (0UL) /*!< DCTES (Bit 0) */ + #define R_GWCA0_GWEIS5_DCTES_Msk (0x1UL) /*!< DCTES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS5_DCTEIOS_Pos (1UL) /*!< DCTEIOS (Bit 1) */ + #define R_GWCA0_GWEIS5_DCTEIOS_Msk (0x2UL) /*!< DCTEIOS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS5_DCTECN_Pos (8UL) /*!< DCTECN (Bit 8) */ + #define R_GWCA0_GWEIS5_DCTECN_Msk (0x3f00UL) /*!< DCTECN (Bitfield-Mask: 0x3f) */ + #define R_GWCA0_GWEIS5_RXDNES_Pos (16UL) /*!< RXDNES (Bit 16) */ + #define R_GWCA0_GWEIS5_RXDNES_Msk (0x10000UL) /*!< RXDNES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS5_RXDNEIOS_Pos (17UL) /*!< RXDNEIOS (Bit 17) */ + #define R_GWCA0_GWEIS5_RXDNEIOS_Msk (0x20000UL) /*!< RXDNEIOS (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIE5 ========================================================= */ + #define R_GWCA0_GWEIE5_DCTEE_Pos (0UL) /*!< DCTEE (Bit 0) */ + #define R_GWCA0_GWEIE5_DCTEE_Msk (0x1UL) /*!< DCTEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE5_DCTEIOE_Pos (1UL) /*!< DCTEIOE (Bit 1) */ + #define R_GWCA0_GWEIE5_DCTEIOE_Msk (0x2UL) /*!< DCTEIOE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE5_RXDNEE_Pos (16UL) /*!< RXDNEE (Bit 16) */ + #define R_GWCA0_GWEIE5_RXDNEE_Msk (0x10000UL) /*!< RXDNEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE5_RXDNEIOE_Pos (17UL) /*!< RXDNEIOE (Bit 17) */ + #define R_GWCA0_GWEIE5_RXDNEIOE_Msk (0x20000UL) /*!< RXDNEIOE (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEID5 ========================================================= */ + #define R_GWCA0_GWEID5_DCTED_Pos (0UL) /*!< DCTED (Bit 0) */ + #define R_GWCA0_GWEID5_DCTED_Msk (0x1UL) /*!< DCTED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID5_DCTEIOD_Pos (1UL) /*!< DCTEIOD (Bit 1) */ + #define R_GWCA0_GWEID5_DCTEIOD_Msk (0x2UL) /*!< DCTEIOD (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID5_RXDNED_Pos (15UL) /*!< RXDNED (Bit 15) */ + #define R_GWCA0_GWEID5_RXDNED_Msk (0x8000UL) /*!< RXDNED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID5_RXDNEIOD_Pos (16UL) /*!< RXDNEIOD (Bit 16) */ + #define R_GWCA0_GWEID5_RXDNEIOD_Msk (0x10000UL) /*!< RXDNEIOD (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IPC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IPCSEM ========================================================= */ + #define R_IPC_IPCSEM_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ + #define R_IPC_IPCSEM_LOCK_Msk (0x1UL) /*!< LOCK (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MFWD ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FWGC ========================================================== */ + #define R_MFWD_FWGC_SVM_Pos (0UL) /*!< SVM (Bit 0) */ + #define R_MFWD_FWGC_SVM_Msk (0x3UL) /*!< SVM (Bitfield-Mask: 0x03) */ +/* ======================================================== FWTTC0 ========================================================= */ + #define R_MFWD_FWTTC0_CTT_Pos (0UL) /*!< CTT (Bit 0) */ + #define R_MFWD_FWTTC0_CTT_Msk (0xffffUL) /*!< CTT (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTTC0_STT_Pos (16UL) /*!< STT (Bit 16) */ + #define R_MFWD_FWTTC0_STT_Msk (0xffff0000UL) /*!< STT (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWTTC1 ========================================================= */ + #define R_MFWD_FWTTC1_RTT_Pos (0UL) /*!< RTT (Bit 0) */ + #define R_MFWD_FWTTC1_RTT_Msk (0xffffUL) /*!< RTT (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWCEPTC ======================================================== */ + #define R_MFWD_FWCEPTC_EPCSD_Pos (0UL) /*!< EPCSD (Bit 0) */ + #define R_MFWD_FWCEPTC_EPCSD_Msk (0x7fUL) /*!< EPCSD (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCEPTC_EPIPV_Pos (12UL) /*!< EPIPV (Bit 12) */ + #define R_MFWD_FWCEPTC_EPIPV_Msk (0x7000UL) /*!< EPIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCEPTC_EPCS_Pos (16UL) /*!< EPCS (Bit 16) */ + #define R_MFWD_FWCEPTC_EPCS_Msk (0x30000UL) /*!< EPCS (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCEPTC_EPSL_Pos (24UL) /*!< EPSL (Bit 24) */ + #define R_MFWD_FWCEPTC_EPSL_Msk (0x1000000UL) /*!< EPSL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCEPRC0 ======================================================== */ + #define R_MFWD_FWCEPRC0_EPHYEEF_Pos (0UL) /*!< EPHYEEF (Bit 0) */ + #define R_MFWD_FWCEPRC0_EPHYEEF_Msk (0x1UL) /*!< EPHYEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_EPCRCEEF_Pos (1UL) /*!< EPCRCEEF (Bit 1) */ + #define R_MFWD_FWCEPRC0_EPCRCEEF_Msk (0x2UL) /*!< EPCRCEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_ENIBEEF_Pos (2UL) /*!< ENIBEEF (Bit 2) */ + #define R_MFWD_FWCEPRC0_ENIBEEF_Msk (0x4UL) /*!< ENIBEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_EFCSEEF_Pos (3UL) /*!< EFCSEEF (Bit 3) */ + #define R_MFWD_FWCEPRC0_EFCSEEF_Msk (0x8UL) /*!< EFCSEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_EFFMEEF_Pos (4UL) /*!< EFFMEEF (Bit 4) */ + #define R_MFWD_FWCEPRC0_EFFMEEF_Msk (0x10UL) /*!< EFFMEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_ECFSEEF_Pos (5UL) /*!< ECFSEEF (Bit 5) */ + #define R_MFWD_FWCEPRC0_ECFSEEF_Msk (0x20UL) /*!< ECFSEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_ECFFCEEF_Pos (6UL) /*!< ECFFCEEF (Bit 6) */ + #define R_MFWD_FWCEPRC0_ECFFCEEF_Msk (0x40UL) /*!< ECFFCEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_ERFFEF_Pos (7UL) /*!< ERFFEF (Bit 7) */ + #define R_MFWD_FWCEPRC0_ERFFEF_Msk (0x80UL) /*!< ERFFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_ERPOOEF_Pos (8UL) /*!< ERPOOEF (Bit 8) */ + #define R_MFWD_FWCEPRC0_ERPOOEF_Msk (0x100UL) /*!< ERPOOEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_EBOEEF_Pos (9UL) /*!< EBOEEF (Bit 9) */ + #define R_MFWD_FWCEPRC0_EBOEEF_Msk (0x200UL) /*!< EBOEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_EUEEF_Pos (10UL) /*!< EUEEF (Bit 10) */ + #define R_MFWD_FWCEPRC0_EUEEF_Msk (0x400UL) /*!< EUEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_EOEEF_Pos (11UL) /*!< EOEEF (Bit 11) */ + #define R_MFWD_FWCEPRC0_EOEEF_Msk (0x800UL) /*!< EOEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_ETFEF_Pos (12UL) /*!< ETFEF (Bit 12) */ + #define R_MFWD_FWCEPRC0_ETFEF_Msk (0x1000UL) /*!< ETFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_GAREEEF_Pos (16UL) /*!< GAREEEF (Bit 16) */ + #define R_MFWD_FWCEPRC0_GAREEEF_Msk (0x10000UL) /*!< GAREEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_GAXEEF_Pos (17UL) /*!< GAXEEF (Bit 17) */ + #define R_MFWD_FWCEPRC0_GAXEEF_Msk (0x20000UL) /*!< GAXEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_GSEQEEF_Pos (18UL) /*!< GSEQEEF (Bit 18) */ + #define R_MFWD_FWCEPRC0_GSEQEEF_Msk (0x40000UL) /*!< GSEQEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_GTFEF_Pos (20UL) /*!< GTFEF (Bit 20) */ + #define R_MFWD_FWCEPRC0_GTFEF_Msk (0x100000UL) /*!< GTFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_GDNEEF_Pos (21UL) /*!< GDNEEF (Bit 21) */ + #define R_MFWD_FWCEPRC0_GDNEEF_Msk (0x200000UL) /*!< GDNEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_DDEEF_Pos (24UL) /*!< DDEEF (Bit 24) */ + #define R_MFWD_FWCEPRC0_DDEEF_Msk (0x1000000UL) /*!< DDEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_DDFSFEF_Pos (26UL) /*!< DDFSFEF (Bit 26) */ + #define R_MFWD_FWCEPRC0_DDFSFEF_Msk (0x4000000UL) /*!< DDFSFEF (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCEPRC1 ======================================================== */ + #define R_MFWD_FWCEPRC1_FMSDUFEF_Pos (0UL) /*!< FMSDUFEF (Bit 0) */ + #define R_MFWD_FWCEPRC1_FMSDUFEF_Msk (0x1UL) /*!< FMSDUFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC1_FMTRFEF_Pos (2UL) /*!< FMTRFEF (Bit 2) */ + #define R_MFWD_FWCEPRC1_FMTRFEF_Msk (0x4UL) /*!< FMTRFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC1_FIFFEF_Pos (8UL) /*!< FIFFEF (Bit 8) */ + #define R_MFWD_FWCEPRC1_FIFFEF_Msk (0x100UL) /*!< FIFFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC1_FSFFEF_Pos (9UL) /*!< FSFFEF (Bit 9) */ + #define R_MFWD_FWCEPRC1_FSFFEF_Msk (0x200UL) /*!< FSFFEF (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCEPRC2 ======================================================== */ + #define R_MFWD_FWCEPRC2_FLTHUFEF_Pos (0UL) /*!< FLTHUFEF (Bit 0) */ + #define R_MFWD_FWCEPRC2_FLTHUFEF_Msk (0x1UL) /*!< FLTHUFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FDMACUFEF_Pos (3UL) /*!< FDMACUFEF (Bit 3) */ + #define R_MFWD_FWCEPRC2_FDMACUFEF_Msk (0x8UL) /*!< FDMACUFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FSMACUFEF_Pos (4UL) /*!< FSMACUFEF (Bit 4) */ + #define R_MFWD_FWCEPRC2_FSMACUFEF_Msk (0x10UL) /*!< FSMACUFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FVLANUFEF_Pos (5UL) /*!< FVLANUFEF (Bit 5) */ + #define R_MFWD_FWCEPRC2_FVLANUFEF_Msk (0x20UL) /*!< FVLANUFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FDDNTFEF_Pos (8UL) /*!< FDDNTFEF (Bit 8) */ + #define R_MFWD_FWCEPRC2_FDDNTFEF_Msk (0x100UL) /*!< FDDNTFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FLTHNTFEF_Pos (9UL) /*!< FLTHNTFEF (Bit 9) */ + #define R_MFWD_FWCEPRC2_FLTHNTFEF_Msk (0x200UL) /*!< FLTHNTFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FLTWNTFEF_Pos (11UL) /*!< FLTWNTFEF (Bit 11) */ + #define R_MFWD_FWCEPRC2_FLTWNTFEF_Msk (0x800UL) /*!< FLTWNTFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FPBNTFEF_Pos (12UL) /*!< FPBNTFEF (Bit 12) */ + #define R_MFWD_FWCEPRC2_FPBNTFEF_Msk (0x1000UL) /*!< FPBNTFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FLTHSLFEF_Pos (16UL) /*!< FLTHSLFEF (Bit 16) */ + #define R_MFWD_FWCEPRC2_FLTHSLFEF_Msk (0x10000UL) /*!< FLTHSLFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FDMACSLFEF_Pos (19UL) /*!< FDMACSLFEF (Bit 19) */ + #define R_MFWD_FWCEPRC2_FDMACSLFEF_Msk (0x80000UL) /*!< FDMACSLFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FSMACSLFEF_Pos (20UL) /*!< FSMACSLFEF (Bit 20) */ + #define R_MFWD_FWCEPRC2_FSMACSLFEF_Msk (0x100000UL) /*!< FSMACSLFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FVLANSLFEF_Pos (21UL) /*!< FVLANSLFEF (Bit 21) */ + #define R_MFWD_FWCEPRC2_FVLANSLFEF_Msk (0x200000UL) /*!< FVLANSLFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FWMFEF_Pos (26UL) /*!< FWMFEF (Bit 26) */ + #define R_MFWD_FWCEPRC2_FWMFEF_Msk (0x4000000UL) /*!< FWMFEF (Bitfield-Mask: 0x01) */ +/* ======================================================== FWCLPTC ======================================================== */ + #define R_MFWD_FWCLPTC_LPCSD_Pos (0UL) /*!< LPCSD (Bit 0) */ + #define R_MFWD_FWCLPTC_LPCSD_Msk (0x7fUL) /*!< LPCSD (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCLPTC_LPIPV_Pos (12UL) /*!< LPIPV (Bit 12) */ + #define R_MFWD_FWCLPTC_LPIPV_Msk (0x7000UL) /*!< LPIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCLPTC_LPCS_Pos (16UL) /*!< LPCS (Bit 16) */ + #define R_MFWD_FWCLPTC_LPCS_Msk (0x30000UL) /*!< LPCS (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCLPTC_LPSL_Pos (24UL) /*!< LPSL (Bit 24) */ + #define R_MFWD_FWCLPTC_LPSL_Msk (0x1000000UL) /*!< LPSL (Bitfield-Mask: 0x01) */ +/* ======================================================== FWCLPRC ======================================================== */ + #define R_MFWD_FWCLPRC_USIDLF_Pos (0UL) /*!< USIDLF (Bit 0) */ + #define R_MFWD_FWCLPRC_USIDLF_Msk (0x1UL) /*!< USIDLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCLPRC_UDMACLF_Pos (4UL) /*!< UDMACLF (Bit 4) */ + #define R_MFWD_FWCLPRC_UDMACLF_Msk (0x10UL) /*!< UDMACLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCLPRC_USMACLF_Pos (5UL) /*!< USMACLF (Bit 5) */ + #define R_MFWD_FWCLPRC_USMACLF_Msk (0x20UL) /*!< USMACLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCLPRC_UPSMACLF_Pos (6UL) /*!< UPSMACLF (Bit 6) */ + #define R_MFWD_FWCLPRC_UPSMACLF_Msk (0x40UL) /*!< UPSMACLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCLPRC_UVLANLF_Pos (7UL) /*!< UVLANLF (Bit 7) */ + #define R_MFWD_FWCLPRC_UVLANLF_Msk (0x80UL) /*!< UVLANLF (Bitfield-Mask: 0x01) */ +/* ======================================================== FWCMPTC ======================================================== */ + #define R_MFWD_FWCMPTC_CMPCSD_Pos (0UL) /*!< CMPCSD (Bit 0) */ + #define R_MFWD_FWCMPTC_CMPCSD_Msk (0x7fUL) /*!< CMPCSD (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCMPTC_CMPIPV_Pos (12UL) /*!< CMPIPV (Bit 12) */ + #define R_MFWD_FWCMPTC_CMPIPV_Msk (0x7000UL) /*!< CMPIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCMPTC_CMPIPU_Pos (15UL) /*!< CMPIPU (Bit 15) */ + #define R_MFWD_FWCMPTC_CMPIPU_Msk (0x8000UL) /*!< CMPIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCMPTC_CMPCS_Pos (16UL) /*!< CMPCS (Bit 16) */ + #define R_MFWD_FWCMPTC_CMPCS_Msk (0x30000UL) /*!< CMPCS (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCMPTC_CMPSL_Pos (24UL) /*!< CMPSL (Bit 24) */ + #define R_MFWD_FWCMPTC_CMPSL_Msk (0x1000000UL) /*!< CMPSL (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEMPTC ======================================================== */ + #define R_MFWD_FWEMPTC_EMPIPV_Pos (12UL) /*!< EMPIPV (Bit 12) */ + #define R_MFWD_FWEMPTC_EMPIPV_Msk (0x7000UL) /*!< EMPIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWEMPTC_EMPIPU_Pos (15UL) /*!< EMPIPU (Bit 15) */ + #define R_MFWD_FWEMPTC_EMPIPU_Msk (0x8000UL) /*!< EMPIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEMPTC_EMPPS_Pos (16UL) /*!< EMPPS (Bit 16) */ + #define R_MFWD_FWEMPTC_EMPPS_Msk (0x30000UL) /*!< EMPPS (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWEMPTC_EMPSL_Pos (24UL) /*!< EMPSL (Bit 24) */ + #define R_MFWD_FWEMPTC_EMPSL_Msk (0x1000000UL) /*!< EMPSL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSDMPTC ======================================================== */ + #define R_MFWD_FWSDMPTC_SDMPCSD_Pos (0UL) /*!< SDMPCSD (Bit 0) */ + #define R_MFWD_FWSDMPTC_SDMPCSD_Msk (0x7fUL) /*!< SDMPCSD (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWSDMPTC_SDMPIPV_Pos (12UL) /*!< SDMPIPV (Bit 12) */ + #define R_MFWD_FWSDMPTC_SDMPIPV_Msk (0x7000UL) /*!< SDMPIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWSDMPTC_SDMPIPU_Pos (15UL) /*!< SDMPIPU (Bit 15) */ + #define R_MFWD_FWSDMPTC_SDMPIPU_Msk (0x8000UL) /*!< SDMPIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWSDMPTC_SDMPPS_Pos (16UL) /*!< SDMPPS (Bit 16) */ + #define R_MFWD_FWSDMPTC_SDMPPS_Msk (0x30000UL) /*!< SDMPPS (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWSDMPTC_SDMPSL_Pos (24UL) /*!< SDMPSL (Bit 24) */ + #define R_MFWD_FWSDMPTC_SDMPSL_Msk (0x1000000UL) /*!< SDMPSL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSDMPVC ======================================================== */ + #define R_MFWD_FWSDMPVC_SDMDV_Pos (0UL) /*!< SDMDV (Bit 0) */ + #define R_MFWD_FWSDMPVC_SDMDV_Msk (0x7fUL) /*!< SDMDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWSDMPVC_SDMSV_Pos (16UL) /*!< SDMSV (Bit 16) */ + #define R_MFWD_FWSDMPVC_SDMSV_Msk (0x7f0000UL) /*!< SDMSV (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWLBWMC0 ======================================================== */ + #define R_MFWD_FWLBWMC0_WMCLPR_Pos (0UL) /*!< WMCLPR (Bit 0) */ + #define R_MFWD_FWLBWMC0_WMCLPR_Msk (0xffffUL) /*!< WMCLPR (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWLBWMC0_WMFLPR_Pos (16UL) /*!< WMFLPR (Bit 16) */ + #define R_MFWD_FWLBWMC0_WMFLPR_Msk (0xffff0000UL) /*!< WMFLPR (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWLBWMC1 ======================================================== */ + #define R_MFWD_FWLBWMC1_WMCLPR_Pos (0UL) /*!< WMCLPR (Bit 0) */ + #define R_MFWD_FWLBWMC1_WMCLPR_Msk (0xffffUL) /*!< WMCLPR (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWLBWMC1_WMFLPR_Pos (16UL) /*!< WMFLPR (Bit 16) */ + #define R_MFWD_FWLBWMC1_WMFLPR_Msk (0xffff0000UL) /*!< WMFLPR (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWLBWMC2 ======================================================== */ + #define R_MFWD_FWLBWMC2_WMCLPR_Pos (0UL) /*!< WMCLPR (Bit 0) */ + #define R_MFWD_FWLBWMC2_WMCLPR_Msk (0xffffUL) /*!< WMCLPR (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWLBWMC2_WMFLPR_Pos (16UL) /*!< WMFLPR (Bit 16) */ + #define R_MFWD_FWLBWMC2_WMFLPR_Msk (0xffff0000UL) /*!< WMFLPR (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWPC00 ========================================================= */ + #define R_MFWD_FWPC00_LTHTA_Pos (0UL) /*!< LTHTA (Bit 0) */ + #define R_MFWD_FWPC00_LTHTA_Msk (0x1UL) /*!< LTHTA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_LTHRUS_Pos (1UL) /*!< LTHRUS (Bit 1) */ + #define R_MFWD_FWPC00_LTHRUS_Msk (0x2UL) /*!< LTHRUS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_LTHRUSS_Pos (2UL) /*!< LTHRUSS (Bit 2) */ + #define R_MFWD_FWPC00_LTHRUSS_Msk (0x4UL) /*!< LTHRUSS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_IP4UE_Pos (3UL) /*!< IP4UE (Bit 3) */ + #define R_MFWD_FWPC00_IP4UE_Msk (0x8UL) /*!< IP4UE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_IP4TE_Pos (4UL) /*!< IP4TE (Bit 4) */ + #define R_MFWD_FWPC00_IP4TE_Msk (0x10UL) /*!< IP4TE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_IP4OE_Pos (5UL) /*!< IP4OE (Bit 5) */ + #define R_MFWD_FWPC00_IP4OE_Msk (0x20UL) /*!< IP4OE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_IP6UE_Pos (6UL) /*!< IP6UE (Bit 6) */ + #define R_MFWD_FWPC00_IP6UE_Msk (0x40UL) /*!< IP6UE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_IP6TE_Pos (7UL) /*!< IP6TE (Bit 7) */ + #define R_MFWD_FWPC00_IP6TE_Msk (0x80UL) /*!< IP6TE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_IP6OE_Pos (8UL) /*!< IP6OE (Bit 8) */ + #define R_MFWD_FWPC00_IP6OE_Msk (0x100UL) /*!< IP6OE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_L2SE_Pos (9UL) /*!< L2SE (Bit 9) */ + #define R_MFWD_FWPC00_L2SE_Msk (0x200UL) /*!< L2SE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACDSA_Pos (20UL) /*!< MACDSA (Bit 20) */ + #define R_MFWD_FWPC00_MACDSA_Msk (0x100000UL) /*!< MACDSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACRUDA_Pos (21UL) /*!< MACRUDA (Bit 21) */ + #define R_MFWD_FWPC00_MACRUDA_Msk (0x200000UL) /*!< MACRUDA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACRUDSA_Pos (22UL) /*!< MACRUDSA (Bit 22) */ + #define R_MFWD_FWPC00_MACRUDSA_Msk (0x400000UL) /*!< MACRUDSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACSSA_Pos (23UL) /*!< MACSSA (Bit 23) */ + #define R_MFWD_FWPC00_MACSSA_Msk (0x800000UL) /*!< MACSSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACRUSA_Pos (24UL) /*!< MACRUSA (Bit 24) */ + #define R_MFWD_FWPC00_MACRUSA_Msk (0x1000000UL) /*!< MACRUSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACRUSSA_Pos (25UL) /*!< MACRUSSA (Bit 25) */ + #define R_MFWD_FWPC00_MACRUSSA_Msk (0x2000000UL) /*!< MACRUSSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACHLA_Pos (26UL) /*!< MACHLA (Bit 26) */ + #define R_MFWD_FWPC00_MACHLA_Msk (0x4000000UL) /*!< MACHLA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACHMA_Pos (27UL) /*!< MACHMA (Bit 27) */ + #define R_MFWD_FWPC00_MACHMA_Msk (0x8000000UL) /*!< MACHMA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_VLANSA_Pos (28UL) /*!< VLANSA (Bit 28) */ + #define R_MFWD_FWPC00_VLANSA_Msk (0x10000000UL) /*!< VLANSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_VLANRU_Pos (29UL) /*!< VLANRU (Bit 29) */ + #define R_MFWD_FWPC00_VLANRU_Msk (0x20000000UL) /*!< VLANRU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_VLANRUS_Pos (30UL) /*!< VLANRUS (Bit 30) */ + #define R_MFWD_FWPC00_VLANRUS_Msk (0x40000000UL) /*!< VLANRUS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWPC01 ========================================================= */ + #define R_MFWD_FWPC01_LTHTA_Pos (0UL) /*!< LTHTA (Bit 0) */ + #define R_MFWD_FWPC01_LTHTA_Msk (0x1UL) /*!< LTHTA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_LTHRUS_Pos (1UL) /*!< LTHRUS (Bit 1) */ + #define R_MFWD_FWPC01_LTHRUS_Msk (0x2UL) /*!< LTHRUS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_LTHRUSS_Pos (2UL) /*!< LTHRUSS (Bit 2) */ + #define R_MFWD_FWPC01_LTHRUSS_Msk (0x4UL) /*!< LTHRUSS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_IP4UE_Pos (3UL) /*!< IP4UE (Bit 3) */ + #define R_MFWD_FWPC01_IP4UE_Msk (0x8UL) /*!< IP4UE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_IP4TE_Pos (4UL) /*!< IP4TE (Bit 4) */ + #define R_MFWD_FWPC01_IP4TE_Msk (0x10UL) /*!< IP4TE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_IP4OE_Pos (5UL) /*!< IP4OE (Bit 5) */ + #define R_MFWD_FWPC01_IP4OE_Msk (0x20UL) /*!< IP4OE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_IP6UE_Pos (6UL) /*!< IP6UE (Bit 6) */ + #define R_MFWD_FWPC01_IP6UE_Msk (0x40UL) /*!< IP6UE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_IP6TE_Pos (7UL) /*!< IP6TE (Bit 7) */ + #define R_MFWD_FWPC01_IP6TE_Msk (0x80UL) /*!< IP6TE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_IP6OE_Pos (8UL) /*!< IP6OE (Bit 8) */ + #define R_MFWD_FWPC01_IP6OE_Msk (0x100UL) /*!< IP6OE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_L2SE_Pos (9UL) /*!< L2SE (Bit 9) */ + #define R_MFWD_FWPC01_L2SE_Msk (0x200UL) /*!< L2SE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACDSA_Pos (20UL) /*!< MACDSA (Bit 20) */ + #define R_MFWD_FWPC01_MACDSA_Msk (0x100000UL) /*!< MACDSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACRUDA_Pos (21UL) /*!< MACRUDA (Bit 21) */ + #define R_MFWD_FWPC01_MACRUDA_Msk (0x200000UL) /*!< MACRUDA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACRUDSA_Pos (22UL) /*!< MACRUDSA (Bit 22) */ + #define R_MFWD_FWPC01_MACRUDSA_Msk (0x400000UL) /*!< MACRUDSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACSSA_Pos (23UL) /*!< MACSSA (Bit 23) */ + #define R_MFWD_FWPC01_MACSSA_Msk (0x800000UL) /*!< MACSSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACRUSA_Pos (24UL) /*!< MACRUSA (Bit 24) */ + #define R_MFWD_FWPC01_MACRUSA_Msk (0x1000000UL) /*!< MACRUSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACRUSSA_Pos (25UL) /*!< MACRUSSA (Bit 25) */ + #define R_MFWD_FWPC01_MACRUSSA_Msk (0x2000000UL) /*!< MACRUSSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACHLA_Pos (26UL) /*!< MACHLA (Bit 26) */ + #define R_MFWD_FWPC01_MACHLA_Msk (0x4000000UL) /*!< MACHLA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACHMA_Pos (27UL) /*!< MACHMA (Bit 27) */ + #define R_MFWD_FWPC01_MACHMA_Msk (0x8000000UL) /*!< MACHMA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_VLANSA_Pos (28UL) /*!< VLANSA (Bit 28) */ + #define R_MFWD_FWPC01_VLANSA_Msk (0x10000000UL) /*!< VLANSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_VLANRU_Pos (29UL) /*!< VLANRU (Bit 29) */ + #define R_MFWD_FWPC01_VLANRU_Msk (0x20000000UL) /*!< VLANRU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_VLANRUS_Pos (30UL) /*!< VLANRUS (Bit 30) */ + #define R_MFWD_FWPC01_VLANRUS_Msk (0x40000000UL) /*!< VLANRUS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWPC02 ========================================================= */ + #define R_MFWD_FWPC02_LTHTA_Pos (0UL) /*!< LTHTA (Bit 0) */ + #define R_MFWD_FWPC02_LTHTA_Msk (0x1UL) /*!< LTHTA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_LTHRUS_Pos (1UL) /*!< LTHRUS (Bit 1) */ + #define R_MFWD_FWPC02_LTHRUS_Msk (0x2UL) /*!< LTHRUS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_LTHRUSS_Pos (2UL) /*!< LTHRUSS (Bit 2) */ + #define R_MFWD_FWPC02_LTHRUSS_Msk (0x4UL) /*!< LTHRUSS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_IP4UE_Pos (3UL) /*!< IP4UE (Bit 3) */ + #define R_MFWD_FWPC02_IP4UE_Msk (0x8UL) /*!< IP4UE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_IP4TE_Pos (4UL) /*!< IP4TE (Bit 4) */ + #define R_MFWD_FWPC02_IP4TE_Msk (0x10UL) /*!< IP4TE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_IP4OE_Pos (5UL) /*!< IP4OE (Bit 5) */ + #define R_MFWD_FWPC02_IP4OE_Msk (0x20UL) /*!< IP4OE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_IP6UE_Pos (6UL) /*!< IP6UE (Bit 6) */ + #define R_MFWD_FWPC02_IP6UE_Msk (0x40UL) /*!< IP6UE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_IP6TE_Pos (7UL) /*!< IP6TE (Bit 7) */ + #define R_MFWD_FWPC02_IP6TE_Msk (0x80UL) /*!< IP6TE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_IP6OE_Pos (8UL) /*!< IP6OE (Bit 8) */ + #define R_MFWD_FWPC02_IP6OE_Msk (0x100UL) /*!< IP6OE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_L2SE_Pos (9UL) /*!< L2SE (Bit 9) */ + #define R_MFWD_FWPC02_L2SE_Msk (0x200UL) /*!< L2SE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACDSA_Pos (20UL) /*!< MACDSA (Bit 20) */ + #define R_MFWD_FWPC02_MACDSA_Msk (0x100000UL) /*!< MACDSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACRUDA_Pos (21UL) /*!< MACRUDA (Bit 21) */ + #define R_MFWD_FWPC02_MACRUDA_Msk (0x200000UL) /*!< MACRUDA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACRUDSA_Pos (22UL) /*!< MACRUDSA (Bit 22) */ + #define R_MFWD_FWPC02_MACRUDSA_Msk (0x400000UL) /*!< MACRUDSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACSSA_Pos (23UL) /*!< MACSSA (Bit 23) */ + #define R_MFWD_FWPC02_MACSSA_Msk (0x800000UL) /*!< MACSSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACRUSA_Pos (24UL) /*!< MACRUSA (Bit 24) */ + #define R_MFWD_FWPC02_MACRUSA_Msk (0x1000000UL) /*!< MACRUSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACRUSSA_Pos (25UL) /*!< MACRUSSA (Bit 25) */ + #define R_MFWD_FWPC02_MACRUSSA_Msk (0x2000000UL) /*!< MACRUSSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACHLA_Pos (26UL) /*!< MACHLA (Bit 26) */ + #define R_MFWD_FWPC02_MACHLA_Msk (0x4000000UL) /*!< MACHLA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACHMA_Pos (27UL) /*!< MACHMA (Bit 27) */ + #define R_MFWD_FWPC02_MACHMA_Msk (0x8000000UL) /*!< MACHMA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_VLANSA_Pos (28UL) /*!< VLANSA (Bit 28) */ + #define R_MFWD_FWPC02_VLANSA_Msk (0x10000000UL) /*!< VLANSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_VLANRU_Pos (29UL) /*!< VLANRU (Bit 29) */ + #define R_MFWD_FWPC02_VLANRU_Msk (0x20000000UL) /*!< VLANRU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_VLANRUS_Pos (30UL) /*!< VLANRUS (Bit 30) */ + #define R_MFWD_FWPC02_VLANRUS_Msk (0x40000000UL) /*!< VLANRUS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWPC10 ========================================================= */ + #define R_MFWD_FWPC10_DDE_Pos (0UL) /*!< DDE (Bit 0) */ + #define R_MFWD_FWPC10_DDE_Msk (0x1UL) /*!< DDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC10_DDSL_Pos (1UL) /*!< DDSL (Bit 1) */ + #define R_MFWD_FWPC10_DDSL_Msk (0x2UL) /*!< DDSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC10_LTHFM_Pos (16UL) /*!< LTHFM (Bit 16) */ + #define R_MFWD_FWPC10_LTHFM_Msk (0x7f0000UL) /*!< LTHFM (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWPC11 ========================================================= */ + #define R_MFWD_FWPC11_DDE_Pos (0UL) /*!< DDE (Bit 0) */ + #define R_MFWD_FWPC11_DDE_Msk (0x1UL) /*!< DDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC11_DDSL_Pos (1UL) /*!< DDSL (Bit 1) */ + #define R_MFWD_FWPC11_DDSL_Msk (0x2UL) /*!< DDSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC11_LTHFM_Pos (16UL) /*!< LTHFM (Bit 16) */ + #define R_MFWD_FWPC11_LTHFM_Msk (0x7f0000UL) /*!< LTHFM (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWPC12 ========================================================= */ + #define R_MFWD_FWPC12_DDE_Pos (0UL) /*!< DDE (Bit 0) */ + #define R_MFWD_FWPC12_DDE_Msk (0x1UL) /*!< DDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC12_DDSL_Pos (1UL) /*!< DDSL (Bit 1) */ + #define R_MFWD_FWPC12_DDSL_Msk (0x2UL) /*!< DDSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC12_LTHFM_Pos (16UL) /*!< LTHFM (Bit 16) */ + #define R_MFWD_FWPC12_LTHFM_Msk (0x7f0000UL) /*!< LTHFM (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWPC20 ========================================================= */ + #define R_MFWD_FWPC20_LTWFM_Pos (16UL) /*!< LTWFM (Bit 16) */ + #define R_MFWD_FWPC20_LTWFM_Msk (0x7f0000UL) /*!< LTWFM (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWPC21 ========================================================= */ + #define R_MFWD_FWPC21_LTWFM_Pos (16UL) /*!< LTWFM (Bit 16) */ + #define R_MFWD_FWPC21_LTWFM_Msk (0x7f0000UL) /*!< LTWFM (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWPC22 ========================================================= */ + #define R_MFWD_FWPC22_LTWFM_Pos (16UL) /*!< LTWFM (Bit 16) */ + #define R_MFWD_FWPC22_LTWFM_Msk (0x7f0000UL) /*!< LTWFM (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTGC00 ======================================================== */ + #define R_MFWD_FWCTGC00_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC00_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC00_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC00_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC00_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC00_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC00_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC00_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC00_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC00_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC00_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC00_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC00_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC00_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC01 ======================================================== */ + #define R_MFWD_FWCTGC01_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC01_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC01_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC01_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC01_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC01_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC01_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC01_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC01_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC01_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC01_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC01_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC01_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC01_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC02 ======================================================== */ + #define R_MFWD_FWCTGC02_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC02_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC02_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC02_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC02_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC02_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC02_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC02_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC02_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC02_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC02_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC02_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC02_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC02_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC03 ======================================================== */ + #define R_MFWD_FWCTGC03_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC03_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC03_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC03_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC03_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC03_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC03_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC03_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC03_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC03_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC03_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC03_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC03_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC03_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC04 ======================================================== */ + #define R_MFWD_FWCTGC04_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC04_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC04_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC04_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC04_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC04_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC04_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC04_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC04_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC04_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC04_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC04_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC04_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC04_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC05 ======================================================== */ + #define R_MFWD_FWCTGC05_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC05_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC05_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC05_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC05_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC05_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC05_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC05_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC05_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC05_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC05_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC05_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC05_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC05_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC06 ======================================================== */ + #define R_MFWD_FWCTGC06_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC06_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC06_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC06_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC06_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC06_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC06_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC06_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC06_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC06_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC06_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC06_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC06_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC06_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC07 ======================================================== */ + #define R_MFWD_FWCTGC07_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC07_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC07_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC07_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC07_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC07_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC07_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC07_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC07_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC07_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC07_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC07_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC07_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC07_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC10 ======================================================== */ + #define R_MFWD_FWCTGC10_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC10_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTGC11 ======================================================== */ + #define R_MFWD_FWCTGC11_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC11_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTGC12 ======================================================== */ + #define R_MFWD_FWCTGC12_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC12_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTGC13 ======================================================== */ + #define R_MFWD_FWCTGC13_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC13_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTGC14 ======================================================== */ + #define R_MFWD_FWCTGC14_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC14_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTGC15 ======================================================== */ + #define R_MFWD_FWCTGC15_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC15_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTGC16 ======================================================== */ + #define R_MFWD_FWCTGC16_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC16_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTGC17 ======================================================== */ + #define R_MFWD_FWCTGC17_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC17_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTTC00 ======================================================== */ + #define R_MFWD_FWCTTC00_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC00_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC00_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC00_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC01 ======================================================== */ + #define R_MFWD_FWCTTC01_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC01_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC01_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC01_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC02 ======================================================== */ + #define R_MFWD_FWCTTC02_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC02_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC02_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC02_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC03 ======================================================== */ + #define R_MFWD_FWCTTC03_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC03_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC03_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC03_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC04 ======================================================== */ + #define R_MFWD_FWCTTC04_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC04_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC04_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC04_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC05 ======================================================== */ + #define R_MFWD_FWCTTC05_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC05_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC05_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC05_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC06 ======================================================== */ + #define R_MFWD_FWCTTC06_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC06_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC06_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC06_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC07 ======================================================== */ + #define R_MFWD_FWCTTC07_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC07_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC07_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC07_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC10 ======================================================== */ + #define R_MFWD_FWCTTC10_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC10_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC10_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC10_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC10_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC10_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC10_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC10_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC11 ======================================================== */ + #define R_MFWD_FWCTTC11_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC11_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC11_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC11_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC11_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC11_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC11_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC11_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC12 ======================================================== */ + #define R_MFWD_FWCTTC12_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC12_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC12_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC12_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC12_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC12_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC12_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC12_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC13 ======================================================== */ + #define R_MFWD_FWCTTC13_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC13_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC13_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC13_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC13_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC13_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC13_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC13_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC14 ======================================================== */ + #define R_MFWD_FWCTTC14_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC14_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC14_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC14_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC14_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC14_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC14_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC14_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC15 ======================================================== */ + #define R_MFWD_FWCTTC15_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC15_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC15_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC15_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC15_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC15_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC15_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC15_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC16 ======================================================== */ + #define R_MFWD_FWCTTC16_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC16_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC16_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC16_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC16_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC16_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC16_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC16_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC17 ======================================================== */ + #define R_MFWD_FWCTTC17_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC17_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC17_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC17_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC17_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC17_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC17_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC17_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC200 ======================================================= */ + #define R_MFWD_FWCTTC200_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC200_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTTC201 ======================================================= */ + #define R_MFWD_FWCTTC201_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC201_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTTC202 ======================================================= */ + #define R_MFWD_FWCTTC202_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC202_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTTC203 ======================================================= */ + #define R_MFWD_FWCTTC203_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC203_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTTC204 ======================================================= */ + #define R_MFWD_FWCTTC204_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC204_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTTC205 ======================================================= */ + #define R_MFWD_FWCTTC205_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC205_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTTC206 ======================================================= */ + #define R_MFWD_FWCTTC206_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC206_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTTC207 ======================================================= */ + #define R_MFWD_FWCTTC207_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC207_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTSC00 ======================================================== */ + #define R_MFWD_FWCTSC00_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC00_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC01 ======================================================== */ + #define R_MFWD_FWCTSC01_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC01_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC02 ======================================================== */ + #define R_MFWD_FWCTSC02_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC02_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC03 ======================================================== */ + #define R_MFWD_FWCTSC03_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC03_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC04 ======================================================== */ + #define R_MFWD_FWCTSC04_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC04_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC05 ======================================================== */ + #define R_MFWD_FWCTSC05_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC05_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC06 ======================================================== */ + #define R_MFWD_FWCTSC06_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC06_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC07 ======================================================== */ + #define R_MFWD_FWCTSC07_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC07_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC10 ======================================================== */ + #define R_MFWD_FWCTSC10_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC10_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC10_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC10_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC11 ======================================================== */ + #define R_MFWD_FWCTSC11_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC11_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC11_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC11_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC12 ======================================================== */ + #define R_MFWD_FWCTSC12_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC12_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC12_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC12_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC13 ======================================================== */ + #define R_MFWD_FWCTSC13_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC13_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC13_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC13_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC14 ======================================================== */ + #define R_MFWD_FWCTSC14_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC14_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC14_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC14_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC15 ======================================================== */ + #define R_MFWD_FWCTSC15_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC15_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC15_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC15_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC16 ======================================================== */ + #define R_MFWD_FWCTSC16_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC16_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC16_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC16_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC17 ======================================================== */ + #define R_MFWD_FWCTSC17_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC17_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC17_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC17_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC20 ======================================================== */ + #define R_MFWD_FWCTSC20_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC20_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC21 ======================================================== */ + #define R_MFWD_FWCTSC21_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC21_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC22 ======================================================== */ + #define R_MFWD_FWCTSC22_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC22_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC23 ======================================================== */ + #define R_MFWD_FWCTSC23_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC23_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC24 ======================================================== */ + #define R_MFWD_FWCTSC24_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC24_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC25 ======================================================== */ + #define R_MFWD_FWCTSC25_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC25_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC26 ======================================================== */ + #define R_MFWD_FWCTSC26_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC26_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC27 ======================================================== */ + #define R_MFWD_FWCTSC27_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC27_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC30 ======================================================== */ + #define R_MFWD_FWCTSC30_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC30_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC30_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC30_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC30_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC30_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC30_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC30_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC30_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC30_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC30_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC30_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC31 ======================================================== */ + #define R_MFWD_FWCTSC31_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC31_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC31_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC31_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC31_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC31_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC31_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC31_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC31_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC31_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC31_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC31_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC32 ======================================================== */ + #define R_MFWD_FWCTSC32_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC32_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC32_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC32_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC32_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC32_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC32_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC32_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC32_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC32_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC32_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC32_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC33 ======================================================== */ + #define R_MFWD_FWCTSC33_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC33_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC33_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC33_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC33_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC33_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC33_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC33_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC33_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC33_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC33_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC33_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC34 ======================================================== */ + #define R_MFWD_FWCTSC34_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC34_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC34_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC34_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC34_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC34_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC34_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC34_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC34_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC34_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC34_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC34_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC35 ======================================================== */ + #define R_MFWD_FWCTSC35_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC35_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC35_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC35_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC35_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC35_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC35_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC35_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC35_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC35_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC35_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC35_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC36 ======================================================== */ + #define R_MFWD_FWCTSC36_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC36_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC36_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC36_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC36_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC36_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC36_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC36_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC36_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC36_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC36_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC36_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC37 ======================================================== */ + #define R_MFWD_FWCTSC37_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC37_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC37_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC37_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC37_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC37_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC37_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC37_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC37_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC37_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC37_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC37_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC40 ======================================================== */ + #define R_MFWD_FWCTSC40_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC40_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC40_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC40_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWCTSC41 ======================================================== */ + #define R_MFWD_FWCTSC41_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC41_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC41_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC41_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWCTSC42 ======================================================== */ + #define R_MFWD_FWCTSC42_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC42_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC42_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC42_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWCTSC43 ======================================================== */ + #define R_MFWD_FWCTSC43_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC43_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC43_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC43_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWCTSC44 ======================================================== */ + #define R_MFWD_FWCTSC44_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC44_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC44_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC44_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWCTSC45 ======================================================== */ + #define R_MFWD_FWCTSC45_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC45_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC45_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC45_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWCTSC46 ======================================================== */ + #define R_MFWD_FWCTSC46_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC46_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC46_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC46_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWCTSC47 ======================================================== */ + #define R_MFWD_FWCTSC47_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC47_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC47_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC47_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWTWBFC0 ======================================================== */ + #define R_MFWD_FWTWBFC0_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC0_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC0_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC0_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC0_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC0_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC1 ======================================================== */ + #define R_MFWD_FWTWBFC1_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC1_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC1_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC1_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC1_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC1_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC2 ======================================================== */ + #define R_MFWD_FWTWBFC2_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC2_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC2_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC2_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC2_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC2_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC3 ======================================================== */ + #define R_MFWD_FWTWBFC3_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC3_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC3_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC3_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC3_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC3_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC4 ======================================================== */ + #define R_MFWD_FWTWBFC4_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC4_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC4_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC4_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC4_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC4_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC5 ======================================================== */ + #define R_MFWD_FWTWBFC5_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC5_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC5_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC5_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC5_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC5_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC6 ======================================================== */ + #define R_MFWD_FWTWBFC6_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC6_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC6_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC6_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC6_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC6_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC7 ======================================================== */ + #define R_MFWD_FWTWBFC7_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC7_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC7_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC7_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC7_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC7_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC8 ======================================================== */ + #define R_MFWD_FWTWBFC8_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC8_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC8_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC8_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC8_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC8_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC9 ======================================================== */ + #define R_MFWD_FWTWBFC9_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC9_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC9_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC9_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC9_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC9_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC10 ======================================================= */ + #define R_MFWD_FWTWBFC10_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC10_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC10_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC10_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC10_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC10_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC11 ======================================================= */ + #define R_MFWD_FWTWBFC11_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC11_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC11_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC11_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC11_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC11_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC12 ======================================================= */ + #define R_MFWD_FWTWBFC12_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC12_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC12_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC12_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC12_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC12_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC13 ======================================================= */ + #define R_MFWD_FWTWBFC13_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC13_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC13_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC13_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC13_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC13_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC14 ======================================================= */ + #define R_MFWD_FWTWBFC14_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC14_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC14_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC14_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC14_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC14_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC15 ======================================================= */ + #define R_MFWD_FWTWBFC15_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC15_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC15_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC15_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC15_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC15_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFVC0 ======================================================= */ + #define R_MFWD_FWTWBFVC0_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC0_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC0_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC0_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC1 ======================================================= */ + #define R_MFWD_FWTWBFVC1_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC1_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC1_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC1_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC2 ======================================================= */ + #define R_MFWD_FWTWBFVC2_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC2_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC2_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC2_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC3 ======================================================= */ + #define R_MFWD_FWTWBFVC3_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC3_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC3_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC3_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC4 ======================================================= */ + #define R_MFWD_FWTWBFVC4_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC4_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC4_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC4_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC5 ======================================================= */ + #define R_MFWD_FWTWBFVC5_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC5_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC5_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC5_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC6 ======================================================= */ + #define R_MFWD_FWTWBFVC6_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC6_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC6_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC6_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC7 ======================================================= */ + #define R_MFWD_FWTWBFVC7_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC7_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC7_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC7_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC8 ======================================================= */ + #define R_MFWD_FWTWBFVC8_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC8_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC8_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC8_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC9 ======================================================= */ + #define R_MFWD_FWTWBFVC9_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC9_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC9_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC9_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWTWBFVC10 ======================================================= */ + #define R_MFWD_FWTWBFVC10_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC10_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC10_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC10_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWTWBFVC11 ======================================================= */ + #define R_MFWD_FWTWBFVC11_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC11_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC11_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC11_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWTWBFVC12 ======================================================= */ + #define R_MFWD_FWTWBFVC12_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC12_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC12_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC12_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWTWBFVC13 ======================================================= */ + #define R_MFWD_FWTWBFVC13_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC13_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC13_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC13_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWTWBFVC14 ======================================================= */ + #define R_MFWD_FWTWBFVC14_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC14_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC14_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC14_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWTWBFVC15 ======================================================= */ + #define R_MFWD_FWTWBFVC15_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC15_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC15_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC15_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTHBFC0 ======================================================== */ + #define R_MFWD_FWTHBFC0_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC0_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC0_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC0_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC1 ======================================================== */ + #define R_MFWD_FWTHBFC1_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC1_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC1_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC1_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC2 ======================================================== */ + #define R_MFWD_FWTHBFC2_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC2_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC2_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC2_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC3 ======================================================== */ + #define R_MFWD_FWTHBFC3_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC3_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC3_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC3_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC4 ======================================================== */ + #define R_MFWD_FWTHBFC4_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC4_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC4_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC4_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC5 ======================================================== */ + #define R_MFWD_FWTHBFC5_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC5_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC5_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC5_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC6 ======================================================== */ + #define R_MFWD_FWTHBFC6_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC6_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC6_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC6_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC7 ======================================================== */ + #define R_MFWD_FWTHBFC7_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC7_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC7_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC7_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC8 ======================================================== */ + #define R_MFWD_FWTHBFC8_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC8_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC8_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC8_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC9 ======================================================== */ + #define R_MFWD_FWTHBFC9_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC9_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC9_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC9_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC10 ======================================================= */ + #define R_MFWD_FWTHBFC10_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC10_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC10_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC10_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC11 ======================================================= */ + #define R_MFWD_FWTHBFC11_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC11_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC11_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC11_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC12 ======================================================= */ + #define R_MFWD_FWTHBFC12_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC12_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC12_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC12_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC13 ======================================================= */ + #define R_MFWD_FWTHBFC13_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC13_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC13_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC13_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC14 ======================================================= */ + #define R_MFWD_FWTHBFC14_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC14_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC14_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC14_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC15 ======================================================= */ + #define R_MFWD_FWTHBFC15_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC15_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC15_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC15_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ====================================================== FWTHBFV0C0 ======================================================= */ + #define R_MFWD_FWTHBFV0C0_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C0_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C1 ======================================================= */ + #define R_MFWD_FWTHBFV0C1_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C1_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C2 ======================================================= */ + #define R_MFWD_FWTHBFV0C2_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C2_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C3 ======================================================= */ + #define R_MFWD_FWTHBFV0C3_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C3_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C4 ======================================================= */ + #define R_MFWD_FWTHBFV0C4_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C4_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C5 ======================================================= */ + #define R_MFWD_FWTHBFV0C5_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C5_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C6 ======================================================= */ + #define R_MFWD_FWTHBFV0C6_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C6_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C7 ======================================================= */ + #define R_MFWD_FWTHBFV0C7_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C7_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C8 ======================================================= */ + #define R_MFWD_FWTHBFV0C8_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C8_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C9 ======================================================= */ + #define R_MFWD_FWTHBFV0C9_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C9_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C10 ====================================================== */ + #define R_MFWD_FWTHBFV0C10_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C10_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C11 ====================================================== */ + #define R_MFWD_FWTHBFV0C11_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C11_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C12 ====================================================== */ + #define R_MFWD_FWTHBFV0C12_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C12_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C13 ====================================================== */ + #define R_MFWD_FWTHBFV0C13_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C13_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C14 ====================================================== */ + #define R_MFWD_FWTHBFV0C14_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C14_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C15 ====================================================== */ + #define R_MFWD_FWTHBFV0C15_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C15_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C0 ======================================================= */ + #define R_MFWD_FWTHBFV1C0_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C0_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C1 ======================================================= */ + #define R_MFWD_FWTHBFV1C1_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C1_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C2 ======================================================= */ + #define R_MFWD_FWTHBFV1C2_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C2_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C3 ======================================================= */ + #define R_MFWD_FWTHBFV1C3_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C3_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C4 ======================================================= */ + #define R_MFWD_FWTHBFV1C4_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C4_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C5 ======================================================= */ + #define R_MFWD_FWTHBFV1C5_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C5_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C6 ======================================================= */ + #define R_MFWD_FWTHBFV1C6_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C6_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C7 ======================================================= */ + #define R_MFWD_FWTHBFV1C7_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C7_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C8 ======================================================= */ + #define R_MFWD_FWTHBFV1C8_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C8_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C9 ======================================================= */ + #define R_MFWD_FWTHBFV1C9_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C9_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C10 ====================================================== */ + #define R_MFWD_FWTHBFV1C10_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C10_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C11 ====================================================== */ + #define R_MFWD_FWTHBFV1C11_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C11_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C12 ====================================================== */ + #define R_MFWD_FWTHBFV1C12_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C12_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C13 ====================================================== */ + #define R_MFWD_FWTHBFV1C13_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C13_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C14 ====================================================== */ + #define R_MFWD_FWTHBFV1C14_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C14_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C15 ====================================================== */ + #define R_MFWD_FWTHBFV1C15_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C15_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ======================================================= FWFOBFC0 ======================================================== */ + #define R_MFWD_FWFOBFC0_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC0_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC0_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC0_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC1 ======================================================== */ + #define R_MFWD_FWFOBFC1_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC1_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC1_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC1_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC2 ======================================================== */ + #define R_MFWD_FWFOBFC2_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC2_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC2_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC2_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC3 ======================================================== */ + #define R_MFWD_FWFOBFC3_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC3_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC3_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC3_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC4 ======================================================== */ + #define R_MFWD_FWFOBFC4_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC4_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC4_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC4_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC5 ======================================================== */ + #define R_MFWD_FWFOBFC5_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC5_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC5_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC5_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC6 ======================================================== */ + #define R_MFWD_FWFOBFC6_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC6_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC6_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC6_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC7 ======================================================== */ + #define R_MFWD_FWFOBFC7_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC7_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC7_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC7_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC8 ======================================================== */ + #define R_MFWD_FWFOBFC8_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC8_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC8_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC8_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC9 ======================================================== */ + #define R_MFWD_FWFOBFC9_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC9_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC9_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC9_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC10 ======================================================= */ + #define R_MFWD_FWFOBFC10_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC10_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC10_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC10_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC11 ======================================================= */ + #define R_MFWD_FWFOBFC11_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC11_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC11_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC11_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC12 ======================================================= */ + #define R_MFWD_FWFOBFC12_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC12_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC12_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC12_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC13 ======================================================= */ + #define R_MFWD_FWFOBFC13_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC13_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC13_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC13_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC14 ======================================================= */ + #define R_MFWD_FWFOBFC14_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC14_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC14_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC14_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC15 ======================================================= */ + #define R_MFWD_FWFOBFC15_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC15_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC15_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC15_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ====================================================== FWFOBFV0C0 ======================================================= */ + #define R_MFWD_FWFOBFV0C0_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C0_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C1 ======================================================= */ + #define R_MFWD_FWFOBFV0C1_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C1_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C2 ======================================================= */ + #define R_MFWD_FWFOBFV0C2_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C2_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C3 ======================================================= */ + #define R_MFWD_FWFOBFV0C3_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C3_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C4 ======================================================= */ + #define R_MFWD_FWFOBFV0C4_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C4_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C5 ======================================================= */ + #define R_MFWD_FWFOBFV0C5_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C5_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C6 ======================================================= */ + #define R_MFWD_FWFOBFV0C6_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C6_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C7 ======================================================= */ + #define R_MFWD_FWFOBFV0C7_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C7_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C8 ======================================================= */ + #define R_MFWD_FWFOBFV0C8_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C8_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C9 ======================================================= */ + #define R_MFWD_FWFOBFV0C9_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C9_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C10 ====================================================== */ + #define R_MFWD_FWFOBFV0C10_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C10_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C11 ====================================================== */ + #define R_MFWD_FWFOBFV0C11_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C11_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C12 ====================================================== */ + #define R_MFWD_FWFOBFV0C12_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C12_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C13 ====================================================== */ + #define R_MFWD_FWFOBFV0C13_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C13_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C14 ====================================================== */ + #define R_MFWD_FWFOBFV0C14_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C14_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C15 ====================================================== */ + #define R_MFWD_FWFOBFV0C15_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C15_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C0 ======================================================= */ + #define R_MFWD_FWFOBFV1C0_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C0_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C1 ======================================================= */ + #define R_MFWD_FWFOBFV1C1_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C1_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C2 ======================================================= */ + #define R_MFWD_FWFOBFV1C2_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C2_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C3 ======================================================= */ + #define R_MFWD_FWFOBFV1C3_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C3_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C4 ======================================================= */ + #define R_MFWD_FWFOBFV1C4_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C4_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C5 ======================================================= */ + #define R_MFWD_FWFOBFV1C5_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C5_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C6 ======================================================= */ + #define R_MFWD_FWFOBFV1C6_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C6_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C7 ======================================================= */ + #define R_MFWD_FWFOBFV1C7_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C7_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C8 ======================================================= */ + #define R_MFWD_FWFOBFV1C8_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C8_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C9 ======================================================= */ + #define R_MFWD_FWFOBFV1C9_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C9_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C10 ====================================================== */ + #define R_MFWD_FWFOBFV1C10_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C10_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C11 ====================================================== */ + #define R_MFWD_FWFOBFV1C11_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C11_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C12 ====================================================== */ + #define R_MFWD_FWFOBFV1C12_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C12_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C13 ====================================================== */ + #define R_MFWD_FWFOBFV1C13_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C13_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C14 ====================================================== */ + #define R_MFWD_FWFOBFV1C14_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C14_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C15 ====================================================== */ + #define R_MFWD_FWFOBFV1C15_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C15_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWRFC0 ========================================================= */ + #define R_MFWD_FWRFC0_RFM_Pos (8UL) /*!< RFM (Bit 8) */ + #define R_MFWD_FWRFC0_RFM_Msk (0x100UL) /*!< RFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWRFC0_RFOV_Pos (16UL) /*!< RFOV (Bit 16) */ + #define R_MFWD_FWRFC0_RFOV_Msk (0xff0000UL) /*!< RFOV (Bitfield-Mask: 0xff) */ +/* ======================================================== FWRFC1 ========================================================= */ + #define R_MFWD_FWRFC1_RFM_Pos (8UL) /*!< RFM (Bit 8) */ + #define R_MFWD_FWRFC1_RFM_Msk (0x100UL) /*!< RFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWRFC1_RFOV_Pos (16UL) /*!< RFOV (Bit 16) */ + #define R_MFWD_FWRFC1_RFOV_Msk (0xff0000UL) /*!< RFOV (Bitfield-Mask: 0xff) */ +/* ======================================================== FWRFVC0 ======================================================== */ + #define R_MFWD_FWRFVC0_RFSV_Pos (0UL) /*!< RFSV (Bit 0) */ + #define R_MFWD_FWRFVC0_RFSV_Msk (0xffUL) /*!< RFSV (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWRFVC0_RFRV_Pos (16UL) /*!< RFRV (Bit 16) */ + #define R_MFWD_FWRFVC0_RFRV_Msk (0xf0000UL) /*!< RFRV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWRFVC1 ======================================================== */ + #define R_MFWD_FWRFVC1_RFSV_Pos (0UL) /*!< RFSV (Bit 0) */ + #define R_MFWD_FWRFVC1_RFSV_Msk (0xffUL) /*!< RFSV (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWRFVC1_RFRV_Pos (16UL) /*!< RFRV (Bit 16) */ + #define R_MFWD_FWRFVC1_RFRV_Msk (0xf0000UL) /*!< RFRV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC0 ========================================================= */ + #define R_MFWD_FWCFC0_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC0_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC0_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC0_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC1 ========================================================= */ + #define R_MFWD_FWCFC1_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC1_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC1_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC1_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC2 ========================================================= */ + #define R_MFWD_FWCFC2_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC2_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC2_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC2_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC3 ========================================================= */ + #define R_MFWD_FWCFC3_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC3_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC3_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC3_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC4 ========================================================= */ + #define R_MFWD_FWCFC4_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC4_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC4_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC4_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC5 ========================================================= */ + #define R_MFWD_FWCFC5_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC5_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC5_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC5_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC6 ========================================================= */ + #define R_MFWD_FWCFC6_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC6_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC6_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC6_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC7 ========================================================= */ + #define R_MFWD_FWCFC7_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC7_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC7_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC7_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC8 ========================================================= */ + #define R_MFWD_FWCFC8_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC8_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC8_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC8_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC9 ========================================================= */ + #define R_MFWD_FWCFC9_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC9_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC9_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC9_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC10 ======================================================== */ + #define R_MFWD_FWCFC10_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC10_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC10_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC10_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC11 ======================================================== */ + #define R_MFWD_FWCFC11_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC11_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC11_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC11_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC12 ======================================================== */ + #define R_MFWD_FWCFC12_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC12_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC12_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC12_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC13 ======================================================== */ + #define R_MFWD_FWCFC13_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC13_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC13_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC13_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC14 ======================================================== */ + #define R_MFWD_FWCFC14_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC14_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC14_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC14_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC15 ======================================================== */ + #define R_MFWD_FWCFC15_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC15_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC15_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC15_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCFMC00 ======================================================== */ + #define R_MFWD_FWCFMC00_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC00_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC00_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC00_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC10 ======================================================== */ + #define R_MFWD_FWCFMC10_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC10_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC10_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC10_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC20 ======================================================== */ + #define R_MFWD_FWCFMC20_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC20_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC20_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC20_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC30 ======================================================== */ + #define R_MFWD_FWCFMC30_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC30_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC30_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC30_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC40 ======================================================== */ + #define R_MFWD_FWCFMC40_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC40_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC40_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC40_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC50 ======================================================== */ + #define R_MFWD_FWCFMC50_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC50_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC50_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC50_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC60 ======================================================== */ + #define R_MFWD_FWCFMC60_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC60_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC60_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC60_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC70 ======================================================== */ + #define R_MFWD_FWCFMC70_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC70_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC70_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC70_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC80 ======================================================== */ + #define R_MFWD_FWCFMC80_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC80_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC80_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC80_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC90 ======================================================== */ + #define R_MFWD_FWCFMC90_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC90_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC90_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC90_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC100 ======================================================= */ + #define R_MFWD_FWCFMC100_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC100_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC100_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC100_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC110 ======================================================= */ + #define R_MFWD_FWCFMC110_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC110_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC110_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC110_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC120 ======================================================= */ + #define R_MFWD_FWCFMC120_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC120_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC120_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC120_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC130 ======================================================= */ + #define R_MFWD_FWCFMC130_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC130_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC130_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC130_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC140 ======================================================= */ + #define R_MFWD_FWCFMC140_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC140_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC140_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC140_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC150 ======================================================= */ + #define R_MFWD_FWCFMC150_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC150_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC150_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC150_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC01 ======================================================== */ + #define R_MFWD_FWCFMC01_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC01_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC01_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC01_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC11 ======================================================== */ + #define R_MFWD_FWCFMC11_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC11_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC11_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC11_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC21 ======================================================== */ + #define R_MFWD_FWCFMC21_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC21_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC21_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC21_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC31 ======================================================== */ + #define R_MFWD_FWCFMC31_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC31_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC31_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC31_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC41 ======================================================== */ + #define R_MFWD_FWCFMC41_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC41_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC41_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC41_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC51 ======================================================== */ + #define R_MFWD_FWCFMC51_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC51_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC51_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC51_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC61 ======================================================== */ + #define R_MFWD_FWCFMC61_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC61_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC61_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC61_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC71 ======================================================== */ + #define R_MFWD_FWCFMC71_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC71_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC71_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC71_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC81 ======================================================== */ + #define R_MFWD_FWCFMC81_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC81_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC81_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC81_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC91 ======================================================== */ + #define R_MFWD_FWCFMC91_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC91_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC91_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC91_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC101 ======================================================= */ + #define R_MFWD_FWCFMC101_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC101_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC101_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC101_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC111 ======================================================= */ + #define R_MFWD_FWCFMC111_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC111_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC111_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC111_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC121 ======================================================= */ + #define R_MFWD_FWCFMC121_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC121_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC121_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC121_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC131 ======================================================= */ + #define R_MFWD_FWCFMC131_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC131_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC131_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC131_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC141 ======================================================= */ + #define R_MFWD_FWCFMC141_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC141_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC141_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC141_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC151 ======================================================= */ + #define R_MFWD_FWCFMC151_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC151_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC151_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC151_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC02 ======================================================== */ + #define R_MFWD_FWCFMC02_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC02_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC02_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC02_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC12 ======================================================== */ + #define R_MFWD_FWCFMC12_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC12_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC12_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC12_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC22 ======================================================== */ + #define R_MFWD_FWCFMC22_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC22_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC22_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC22_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC32 ======================================================== */ + #define R_MFWD_FWCFMC32_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC32_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC32_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC32_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC42 ======================================================== */ + #define R_MFWD_FWCFMC42_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC42_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC42_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC42_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC52 ======================================================== */ + #define R_MFWD_FWCFMC52_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC52_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC52_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC52_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC62 ======================================================== */ + #define R_MFWD_FWCFMC62_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC62_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC62_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC62_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC72 ======================================================== */ + #define R_MFWD_FWCFMC72_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC72_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC72_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC72_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC82 ======================================================== */ + #define R_MFWD_FWCFMC82_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC82_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC82_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC82_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC92 ======================================================== */ + #define R_MFWD_FWCFMC92_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC92_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC92_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC92_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC102 ======================================================= */ + #define R_MFWD_FWCFMC102_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC102_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC102_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC102_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC112 ======================================================= */ + #define R_MFWD_FWCFMC112_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC112_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC112_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC112_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC122 ======================================================= */ + #define R_MFWD_FWCFMC122_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC122_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC122_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC122_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC132 ======================================================= */ + #define R_MFWD_FWCFMC132_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC132_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC132_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC132_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC142 ======================================================= */ + #define R_MFWD_FWCFMC142_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC142_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC142_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC142_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC152 ======================================================= */ + #define R_MFWD_FWCFMC152_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC152_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC152_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC152_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC03 ======================================================== */ + #define R_MFWD_FWCFMC03_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC03_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC03_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC03_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC13 ======================================================== */ + #define R_MFWD_FWCFMC13_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC13_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC13_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC13_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC23 ======================================================== */ + #define R_MFWD_FWCFMC23_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC23_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC23_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC23_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC33 ======================================================== */ + #define R_MFWD_FWCFMC33_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC33_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC33_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC33_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC43 ======================================================== */ + #define R_MFWD_FWCFMC43_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC43_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC43_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC43_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC53 ======================================================== */ + #define R_MFWD_FWCFMC53_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC53_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC53_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC53_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC63 ======================================================== */ + #define R_MFWD_FWCFMC63_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC63_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC63_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC63_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC73 ======================================================== */ + #define R_MFWD_FWCFMC73_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC73_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC73_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC73_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC83 ======================================================== */ + #define R_MFWD_FWCFMC83_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC83_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC83_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC83_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC93 ======================================================== */ + #define R_MFWD_FWCFMC93_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC93_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC93_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC93_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC103 ======================================================= */ + #define R_MFWD_FWCFMC103_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC103_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC103_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC103_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC113 ======================================================= */ + #define R_MFWD_FWCFMC113_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC113_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC113_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC113_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC123 ======================================================= */ + #define R_MFWD_FWCFMC123_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC123_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC123_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC123_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC133 ======================================================= */ + #define R_MFWD_FWCFMC133_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC133_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC133_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC133_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC143 ======================================================= */ + #define R_MFWD_FWCFMC143_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC143_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC143_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC143_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC153 ======================================================= */ + #define R_MFWD_FWCFMC153_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC153_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC153_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC153_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC04 ======================================================== */ + #define R_MFWD_FWCFMC04_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC04_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC04_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC04_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC14 ======================================================== */ + #define R_MFWD_FWCFMC14_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC14_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC14_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC14_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC24 ======================================================== */ + #define R_MFWD_FWCFMC24_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC24_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC24_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC24_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC34 ======================================================== */ + #define R_MFWD_FWCFMC34_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC34_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC34_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC34_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC44 ======================================================== */ + #define R_MFWD_FWCFMC44_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC44_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC44_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC44_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC54 ======================================================== */ + #define R_MFWD_FWCFMC54_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC54_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC54_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC54_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC64 ======================================================== */ + #define R_MFWD_FWCFMC64_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC64_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC64_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC64_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC74 ======================================================== */ + #define R_MFWD_FWCFMC74_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC74_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC74_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC74_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC84 ======================================================== */ + #define R_MFWD_FWCFMC84_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC84_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC84_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC84_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC94 ======================================================== */ + #define R_MFWD_FWCFMC94_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC94_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC94_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC94_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC104 ======================================================= */ + #define R_MFWD_FWCFMC104_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC104_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC104_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC104_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC114 ======================================================= */ + #define R_MFWD_FWCFMC114_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC114_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC114_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC114_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC124 ======================================================= */ + #define R_MFWD_FWCFMC124_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC124_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC124_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC124_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC134 ======================================================= */ + #define R_MFWD_FWCFMC134_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC134_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC134_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC134_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC144 ======================================================= */ + #define R_MFWD_FWCFMC144_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC144_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC144_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC144_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC154 ======================================================= */ + #define R_MFWD_FWCFMC154_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC154_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC154_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC154_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC05 ======================================================== */ + #define R_MFWD_FWCFMC05_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC05_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC05_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC05_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC15 ======================================================== */ + #define R_MFWD_FWCFMC15_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC15_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC15_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC15_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC25 ======================================================== */ + #define R_MFWD_FWCFMC25_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC25_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC25_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC25_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC35 ======================================================== */ + #define R_MFWD_FWCFMC35_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC35_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC35_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC35_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC45 ======================================================== */ + #define R_MFWD_FWCFMC45_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC45_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC45_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC45_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC55 ======================================================== */ + #define R_MFWD_FWCFMC55_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC55_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC55_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC55_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC65 ======================================================== */ + #define R_MFWD_FWCFMC65_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC65_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC65_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC65_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC75 ======================================================== */ + #define R_MFWD_FWCFMC75_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC75_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC75_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC75_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC85 ======================================================== */ + #define R_MFWD_FWCFMC85_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC85_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC85_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC85_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC95 ======================================================== */ + #define R_MFWD_FWCFMC95_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC95_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC95_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC95_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC105 ======================================================= */ + #define R_MFWD_FWCFMC105_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC105_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC105_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC105_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC115 ======================================================= */ + #define R_MFWD_FWCFMC115_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC115_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC115_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC115_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC125 ======================================================= */ + #define R_MFWD_FWCFMC125_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC125_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC125_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC125_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC135 ======================================================= */ + #define R_MFWD_FWCFMC135_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC135_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC135_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC135_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC145 ======================================================= */ + #define R_MFWD_FWCFMC145_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC145_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC145_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC145_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC155 ======================================================= */ + #define R_MFWD_FWCFMC155_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC155_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC155_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC155_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC06 ======================================================== */ + #define R_MFWD_FWCFMC06_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC06_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC06_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC06_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC16 ======================================================== */ + #define R_MFWD_FWCFMC16_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC16_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC16_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC16_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC26 ======================================================== */ + #define R_MFWD_FWCFMC26_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC26_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC26_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC26_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC36 ======================================================== */ + #define R_MFWD_FWCFMC36_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC36_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC36_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC36_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC46 ======================================================== */ + #define R_MFWD_FWCFMC46_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC46_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC46_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC46_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC56 ======================================================== */ + #define R_MFWD_FWCFMC56_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC56_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC56_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC56_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC66 ======================================================== */ + #define R_MFWD_FWCFMC66_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC66_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC66_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC66_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC76 ======================================================== */ + #define R_MFWD_FWCFMC76_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC76_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC76_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC76_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC86 ======================================================== */ + #define R_MFWD_FWCFMC86_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC86_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC86_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC86_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC96 ======================================================== */ + #define R_MFWD_FWCFMC96_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC96_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC96_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC96_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC106 ======================================================= */ + #define R_MFWD_FWCFMC106_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC106_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC106_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC106_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC116 ======================================================= */ + #define R_MFWD_FWCFMC116_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC116_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC116_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC116_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC126 ======================================================= */ + #define R_MFWD_FWCFMC126_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC126_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC126_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC126_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC136 ======================================================= */ + #define R_MFWD_FWCFMC136_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC136_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC136_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC136_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC146 ======================================================= */ + #define R_MFWD_FWCFMC146_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC146_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC146_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC146_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC156 ======================================================= */ + #define R_MFWD_FWCFMC156_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC156_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC156_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC156_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================== FWIP4SC ======================================================== */ + #define R_MFWD_FWIP4SC_IP4IMDH_Pos (0UL) /*!< IP4IMDH (Bit 0) */ + #define R_MFWD_FWIP4SC_IP4IMDH_Msk (0x1UL) /*!< IP4IMDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IMSH_Pos (1UL) /*!< IP4IMSH (Bit 1) */ + #define R_MFWD_FWIP4SC_IP4IMSH_Msk (0x2UL) /*!< IP4IMSH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ISVH_Pos (2UL) /*!< IP4ISVH (Bit 2) */ + #define R_MFWD_FWIP4SC_IP4ISVH_Msk (0x4UL) /*!< IP4ISVH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ISPH_Pos (3UL) /*!< IP4ISPH (Bit 3) */ + #define R_MFWD_FWIP4SC_IP4ISPH_Msk (0x8UL) /*!< IP4ISPH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ISDH_Pos (4UL) /*!< IP4ISDH (Bit 4) */ + #define R_MFWD_FWIP4SC_IP4ISDH_Msk (0x10UL) /*!< IP4ISDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ICVH_Pos (5UL) /*!< IP4ICVH (Bit 5) */ + #define R_MFWD_FWIP4SC_IP4ICVH_Msk (0x20UL) /*!< IP4ICVH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ICPH_Pos (6UL) /*!< IP4ICPH (Bit 6) */ + #define R_MFWD_FWIP4SC_IP4ICPH_Msk (0x40UL) /*!< IP4ICPH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ICDH_Pos (7UL) /*!< IP4ICDH (Bit 7) */ + #define R_MFWD_FWIP4SC_IP4ICDH_Msk (0x80UL) /*!< IP4ICDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IISH_Pos (8UL) /*!< IP4IISH (Bit 8) */ + #define R_MFWD_FWIP4SC_IP4IISH_Msk (0x100UL) /*!< IP4IISH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IIDH_Pos (9UL) /*!< IP4IIDH (Bit 9) */ + #define R_MFWD_FWIP4SC_IP4IIDH_Msk (0x200UL) /*!< IP4IIDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IPH_Pos (10UL) /*!< IP4IPH (Bit 10) */ + #define R_MFWD_FWIP4SC_IP4IPH_Msk (0x400UL) /*!< IP4IPH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ISPTH_Pos (11UL) /*!< IP4ISPTH (Bit 11) */ + #define R_MFWD_FWIP4SC_IP4ISPTH_Msk (0x800UL) /*!< IP4ISPTH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IDPTH_Pos (12UL) /*!< IP4IDPTH (Bit 12) */ + #define R_MFWD_FWIP4SC_IP4IDPTH_Msk (0x1000UL) /*!< IP4IDPTH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ISVS_Pos (16UL) /*!< IP4ISVS (Bit 16) */ + #define R_MFWD_FWIP4SC_IP4ISVS_Msk (0x10000UL) /*!< IP4ISVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ISPS_Pos (17UL) /*!< IP4ISPS (Bit 17) */ + #define R_MFWD_FWIP4SC_IP4ISPS_Msk (0x20000UL) /*!< IP4ISPS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ISDS_Pos (18UL) /*!< IP4ISDS (Bit 18) */ + #define R_MFWD_FWIP4SC_IP4ISDS_Msk (0x40000UL) /*!< IP4ISDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ICVS_Pos (19UL) /*!< IP4ICVS (Bit 19) */ + #define R_MFWD_FWIP4SC_IP4ICVS_Msk (0x80000UL) /*!< IP4ICVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ICPS_Pos (20UL) /*!< IP4ICPS (Bit 20) */ + #define R_MFWD_FWIP4SC_IP4ICPS_Msk (0x100000UL) /*!< IP4ICPS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ICDS_Pos (21UL) /*!< IP4ICDS (Bit 21) */ + #define R_MFWD_FWIP4SC_IP4ICDS_Msk (0x200000UL) /*!< IP4ICDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IISS_Pos (22UL) /*!< IP4IISS (Bit 22) */ + #define R_MFWD_FWIP4SC_IP4IISS_Msk (0x400000UL) /*!< IP4IISS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IIDS_Pos (23UL) /*!< IP4IIDS (Bit 23) */ + #define R_MFWD_FWIP4SC_IP4IIDS_Msk (0x800000UL) /*!< IP4IIDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IDPTS_Pos (24UL) /*!< IP4IDPTS (Bit 24) */ + #define R_MFWD_FWIP4SC_IP4IDPTS_Msk (0x1000000UL) /*!< IP4IDPTS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWIP6SC ======================================================== */ + #define R_MFWD_FWIP6SC_IP6IMDH_Pos (0UL) /*!< IP6IMDH (Bit 0) */ + #define R_MFWD_FWIP6SC_IP6IMDH_Msk (0x1UL) /*!< IP6IMDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6IMSH_Pos (1UL) /*!< IP6IMSH (Bit 1) */ + #define R_MFWD_FWIP6SC_IP6IMSH_Msk (0x2UL) /*!< IP6IMSH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ISVH_Pos (2UL) /*!< IP6ISVH (Bit 2) */ + #define R_MFWD_FWIP6SC_IP6ISVH_Msk (0x4UL) /*!< IP6ISVH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ISPH_Pos (3UL) /*!< IP6ISPH (Bit 3) */ + #define R_MFWD_FWIP6SC_IP6ISPH_Msk (0x8UL) /*!< IP6ISPH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ISDH_Pos (4UL) /*!< IP6ISDH (Bit 4) */ + #define R_MFWD_FWIP6SC_IP6ISDH_Msk (0x10UL) /*!< IP6ISDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ICVH_Pos (5UL) /*!< IP6ICVH (Bit 5) */ + #define R_MFWD_FWIP6SC_IP6ICVH_Msk (0x20UL) /*!< IP6ICVH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ICPH_Pos (6UL) /*!< IP6ICPH (Bit 6) */ + #define R_MFWD_FWIP6SC_IP6ICPH_Msk (0x40UL) /*!< IP6ICPH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ICDH_Pos (7UL) /*!< IP6ICDH (Bit 7) */ + #define R_MFWD_FWIP6SC_IP6ICDH_Msk (0x80UL) /*!< IP6ICDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6IISH_Pos (8UL) /*!< IP6IISH (Bit 8) */ + #define R_MFWD_FWIP6SC_IP6IISH_Msk (0x100UL) /*!< IP6IISH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6IIDH_Pos (9UL) /*!< IP6IIDH (Bit 9) */ + #define R_MFWD_FWIP6SC_IP6IIDH_Msk (0x200UL) /*!< IP6IIDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6IPH_Pos (10UL) /*!< IP6IPH (Bit 10) */ + #define R_MFWD_FWIP6SC_IP6IPH_Msk (0x400UL) /*!< IP6IPH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ISPTH_Pos (11UL) /*!< IP6ISPTH (Bit 11) */ + #define R_MFWD_FWIP6SC_IP6ISPTH_Msk (0x800UL) /*!< IP6ISPTH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6IDPTH_Pos (12UL) /*!< IP6IDPTH (Bit 12) */ + #define R_MFWD_FWIP6SC_IP6IDPTH_Msk (0x1000UL) /*!< IP6IDPTH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ISVS_Pos (16UL) /*!< IP6ISVS (Bit 16) */ + #define R_MFWD_FWIP6SC_IP6ISVS_Msk (0x10000UL) /*!< IP6ISVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ISPS_Pos (17UL) /*!< IP6ISPS (Bit 17) */ + #define R_MFWD_FWIP6SC_IP6ISPS_Msk (0x20000UL) /*!< IP6ISPS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ISDS_Pos (18UL) /*!< IP6ISDS (Bit 18) */ + #define R_MFWD_FWIP6SC_IP6ISDS_Msk (0x40000UL) /*!< IP6ISDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ICVS_Pos (19UL) /*!< IP6ICVS (Bit 19) */ + #define R_MFWD_FWIP6SC_IP6ICVS_Msk (0x80000UL) /*!< IP6ICVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ICPS_Pos (20UL) /*!< IP6ICPS (Bit 20) */ + #define R_MFWD_FWIP6SC_IP6ICPS_Msk (0x100000UL) /*!< IP6ICPS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ICDS_Pos (21UL) /*!< IP6ICDS (Bit 21) */ + #define R_MFWD_FWIP6SC_IP6ICDS_Msk (0x200000UL) /*!< IP6ICDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6II0S_Pos (22UL) /*!< IP6II0S (Bit 22) */ + #define R_MFWD_FWIP6SC_IP6II0S_Msk (0x400000UL) /*!< IP6II0S (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6II1S_Pos (23UL) /*!< IP6II1S (Bit 23) */ + #define R_MFWD_FWIP6SC_IP6II1S_Msk (0x800000UL) /*!< IP6II1S (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6IDPTS_Pos (24UL) /*!< IP6IDPTS (Bit 24) */ + #define R_MFWD_FWIP6SC_IP6IDPTS_Msk (0x1000000UL) /*!< IP6IDPTS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWIP6OC ======================================================== */ + #define R_MFWD_FWIP6OC_IP6IPOM_Pos (0UL) /*!< IP6IPOM (Bit 0) */ + #define R_MFWD_FWIP6OC_IP6IPOM_Msk (0x1UL) /*!< IP6IPOM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6OC_IP6IPO_Pos (4UL) /*!< IP6IPO (Bit 4) */ + #define R_MFWD_FWIP6OC_IP6IPO_Msk (0xf0UL) /*!< IP6IPO (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWL2SC ========================================================= */ + #define R_MFWD_FWL2SC_L2IMDS_Pos (0UL) /*!< L2IMDS (Bit 0) */ + #define R_MFWD_FWL2SC_L2IMDS_Msk (0x1UL) /*!< L2IMDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL2SC_L2IMSS_Pos (1UL) /*!< L2IMSS (Bit 1) */ + #define R_MFWD_FWL2SC_L2IMSS_Msk (0x2UL) /*!< L2IMSS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL2SC_L2ISVS_Pos (2UL) /*!< L2ISVS (Bit 2) */ + #define R_MFWD_FWL2SC_L2ISVS_Msk (0x4UL) /*!< L2ISVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL2SC_L2ISPS_Pos (3UL) /*!< L2ISPS (Bit 3) */ + #define R_MFWD_FWL2SC_L2ISPS_Msk (0x8UL) /*!< L2ISPS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL2SC_L2ISDS_Pos (4UL) /*!< L2ISDS (Bit 4) */ + #define R_MFWD_FWL2SC_L2ISDS_Msk (0x10UL) /*!< L2ISDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL2SC_L2ICVS_Pos (5UL) /*!< L2ICVS (Bit 5) */ + #define R_MFWD_FWL2SC_L2ICVS_Msk (0x20UL) /*!< L2ICVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL2SC_L2ICPS_Pos (6UL) /*!< L2ICPS (Bit 6) */ + #define R_MFWD_FWL2SC_L2ICPS_Msk (0x40UL) /*!< L2ICPS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL2SC_L2ICDS_Pos (7UL) /*!< L2ICDS (Bit 7) */ + #define R_MFWD_FWL2SC_L2ICDS_Msk (0x80UL) /*!< L2ICDS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWSFHEC ======================================================== */ + #define R_MFWD_FWSFHEC_IP4HE_Pos (0UL) /*!< IP4HE (Bit 0) */ + #define R_MFWD_FWSFHEC_IP4HE_Msk (0xffffUL) /*!< IP4HE (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWSFHEC_IP6HE_Pos (16UL) /*!< IP6HE (Bit 16) */ + #define R_MFWD_FWSFHEC_IP6HE_Msk (0xffff0000UL) /*!< IP6HE (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWSHCR0 ======================================================== */ + #define R_MFWD_FWSHCR0_SHCMDP0_Pos (0UL) /*!< SHCMDP0 (Bit 0) */ + #define R_MFWD_FWSHCR0_SHCMDP0_Msk (0xffffffffUL) /*!< SHCMDP0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWSHCR1 ======================================================== */ + #define R_MFWD_FWSHCR1_SHCMSP0_Pos (0UL) /*!< SHCMSP0 (Bit 0) */ + #define R_MFWD_FWSHCR1_SHCMSP0_Msk (0xffffUL) /*!< SHCMSP0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWSHCR1_SHCMDP1_Pos (16UL) /*!< SHCMDP1 (Bit 16) */ + #define R_MFWD_FWSHCR1_SHCMDP1_Msk (0xffff0000UL) /*!< SHCMDP1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWSHCR2 ======================================================== */ + #define R_MFWD_FWSHCR2_SHCMSP1_Pos (0UL) /*!< SHCMSP1 (Bit 0) */ + #define R_MFWD_FWSHCR2_SHCMSP1_Msk (0xffffffffUL) /*!< SHCMSP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWSHCR3 ======================================================== */ + #define R_MFWD_FWSHCR3_SHCCV_Pos (0UL) /*!< SHCCV (Bit 0) */ + #define R_MFWD_FWSHCR3_SHCCV_Msk (0xfffUL) /*!< SHCCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWSHCR3_SHCCD_Pos (12UL) /*!< SHCCD (Bit 12) */ + #define R_MFWD_FWSHCR3_SHCCD_Msk (0x1000UL) /*!< SHCCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWSHCR3_SHCCP_Pos (13UL) /*!< SHCCP (Bit 13) */ + #define R_MFWD_FWSHCR3_SHCCP_Msk (0xe000UL) /*!< SHCCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWSHCR3_SHCSV_Pos (16UL) /*!< SHCSV (Bit 16) */ + #define R_MFWD_FWSHCR3_SHCSV_Msk (0xfff0000UL) /*!< SHCSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWSHCR3_SHCSD_Pos (28UL) /*!< SHCSD (Bit 28) */ + #define R_MFWD_FWSHCR3_SHCSD_Msk (0x10000000UL) /*!< SHCSD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWSHCR3_SHCSP_Pos (29UL) /*!< SHCSP (Bit 29) */ + #define R_MFWD_FWSHCR3_SHCSP_Msk (0xe0000000UL) /*!< SHCSP (Bitfield-Mask: 0x07) */ +/* ======================================================== FWSHCR4 ======================================================== */ + #define R_MFWD_FWSHCR4_SHCP_Pos (0UL) /*!< SHCP (Bit 0) */ + #define R_MFWD_FWSHCR4_SHCP_Msk (0xffUL) /*!< SHCP (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSHCR4_SHCFF_Pos (16UL) /*!< SHCFF (Bit 16) */ + #define R_MFWD_FWSHCR4_SHCFF_Msk (0x10000UL) /*!< SHCFF (Bitfield-Mask: 0x01) */ +/* ======================================================== FWSHCR5 ======================================================== */ + #define R_MFWD_FWSHCR5_SHCISP0_Pos (0UL) /*!< SHCISP0 (Bit 0) */ + #define R_MFWD_FWSHCR5_SHCISP0_Msk (0xffffffffUL) /*!< SHCISP0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWSHCR6 ======================================================== */ + #define R_MFWD_FWSHCR6_SHCISP1_Pos (0UL) /*!< SHCISP1 (Bit 0) */ + #define R_MFWD_FWSHCR6_SHCISP1_Msk (0xffffffffUL) /*!< SHCISP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWSHCR7 ======================================================== */ + #define R_MFWD_FWSHCR7_SHCISP2_Pos (0UL) /*!< SHCISP2 (Bit 0) */ + #define R_MFWD_FWSHCR7_SHCISP2_Msk (0xffffffffUL) /*!< SHCISP2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWSHCR8 ======================================================== */ + #define R_MFWD_FWSHCR8_SHCISP3_Pos (0UL) /*!< SHCISP3 (Bit 0) */ + #define R_MFWD_FWSHCR8_SHCISP3_Msk (0xffffffffUL) /*!< SHCISP3 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWSHCR9 ======================================================== */ + #define R_MFWD_FWSHCR9_SHCIDP0_Pos (0UL) /*!< SHCIDP0 (Bit 0) */ + #define R_MFWD_FWSHCR9_SHCIDP0_Msk (0xffffffffUL) /*!< SHCIDP0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWSHCR10 ======================================================== */ + #define R_MFWD_FWSHCR10_SHCIDP1_Pos (0UL) /*!< SHCIDP1 (Bit 0) */ + #define R_MFWD_FWSHCR10_SHCIDP1_Msk (0xffffffffUL) /*!< SHCIDP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWSHCR11 ======================================================== */ + #define R_MFWD_FWSHCR11_SHCIDP2_Pos (0UL) /*!< SHCIDP2 (Bit 0) */ + #define R_MFWD_FWSHCR11_SHCIDP2_Msk (0xffffffffUL) /*!< SHCIDP2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWSHCR12 ======================================================== */ + #define R_MFWD_FWSHCR12_SHCIDP3_Pos (0UL) /*!< SHCIDP3 (Bit 0) */ + #define R_MFWD_FWSHCR12_SHCIDP3_Msk (0xffffffffUL) /*!< SHCIDP3 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWSHCR13 ======================================================== */ + #define R_MFWD_FWSHCR13_SHCDP_Pos (0UL) /*!< SHCDP (Bit 0) */ + #define R_MFWD_FWSHCR13_SHCDP_Msk (0xffffUL) /*!< SHCDP (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWSHCR13_SHCSP_Pos (16UL) /*!< SHCSP (Bit 16) */ + #define R_MFWD_FWSHCR13_SHCSP_Msk (0xffff0000UL) /*!< SHCSP (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWSHCRR ======================================================== */ + #define R_MFWD_FWSHCRR_SHCR_Pos (0UL) /*!< SHCR (Bit 0) */ + #define R_MFWD_FWSHCRR_SHCR_Msk (0xffffUL) /*!< SHCR (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWSHCRR_SHC_Pos (31UL) /*!< SHC (Bit 31) */ + #define R_MFWD_FWSHCRR_SHC_Msk (0x80000000UL) /*!< SHC (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHHEC ======================================================== */ + #define R_MFWD_FWLTHHEC_LTHHMC_Pos (0UL) /*!< LTHHMC (Bit 0) */ + #define R_MFWD_FWLTHHEC_LTHHMC_Msk (0x3ffUL) /*!< LTHHMC (Bitfield-Mask: 0x3ff) */ + #define R_MFWD_FWLTHHEC_LTHHMUE_Pos (16UL) /*!< LTHHMUE (Bit 16) */ + #define R_MFWD_FWLTHHEC_LTHHMUE_Msk (0x7ff0000UL) /*!< LTHHMUE (Bitfield-Mask: 0x7ff) */ +/* ======================================================== FWLTHHC ======================================================== */ + #define R_MFWD_FWLTHHC_LTHHE_Pos (0UL) /*!< LTHHE (Bit 0) */ + #define R_MFWD_FWLTHHC_LTHHE_Msk (0x3ffUL) /*!< LTHHE (Bitfield-Mask: 0x3ff) */ +/* ======================================================= FWLTHTL0 ======================================================== */ + #define R_MFWD_FWLTHTL0_LTHSLP0_Pos (0UL) /*!< LTHSLP0 (Bit 0) */ + #define R_MFWD_FWLTHTL0_LTHSLP0_Msk (0x7UL) /*!< LTHSLP0 (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWLTHTL0_LTHSLL_Pos (8UL) /*!< LTHSLL (Bit 8) */ + #define R_MFWD_FWLTHTL0_LTHSLL_Msk (0x100UL) /*!< LTHSLL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTL0_LTHED_Pos (16UL) /*!< LTHED (Bit 16) */ + #define R_MFWD_FWLTHTL0_LTHED_Msk (0x10000UL) /*!< LTHED (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTL1 ======================================================== */ + #define R_MFWD_FWLTHTL1_LTHSLP1_Pos (0UL) /*!< LTHSLP1 (Bit 0) */ + #define R_MFWD_FWLTHTL1_LTHSLP1_Msk (0xffffffffUL) /*!< LTHSLP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTL2 ======================================================== */ + #define R_MFWD_FWLTHTL2_LTHSLP2_Pos (0UL) /*!< LTHSLP2 (Bit 0) */ + #define R_MFWD_FWLTHTL2_LTHSLP2_Msk (0xffffffffUL) /*!< LTHSLP2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTL3 ======================================================== */ + #define R_MFWD_FWLTHTL3_LTHSLP3_Pos (0UL) /*!< LTHSLP3 (Bit 0) */ + #define R_MFWD_FWLTHTL3_LTHSLP3_Msk (0xffffffffUL) /*!< LTHSLP3 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTL4 ======================================================== */ + #define R_MFWD_FWLTHTL4_LTHSLP4_Pos (0UL) /*!< LTHSLP4 (Bit 0) */ + #define R_MFWD_FWLTHTL4_LTHSLP4_Msk (0xffffffffUL) /*!< LTHSLP4 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTL5 ======================================================== */ + #define R_MFWD_FWLTHTL5_LTHMSDUNL_Pos (16UL) /*!< LTHMSDUNL (Bit 16) */ + #define R_MFWD_FWLTHTL5_LTHMSDUNL_Msk (0xf0000UL) /*!< LTHMSDUNL (Bitfield-Mask: 0x0f) */ + #define R_MFWD_FWLTHTL5_LTHMSDUVL_Pos (31UL) /*!< LTHMSDUVL (Bit 31) */ + #define R_MFWD_FWLTHTL5_LTHMSDUVL_Msk (0x80000000UL) /*!< LTHMSDUVL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTL6 ======================================================== */ + #define R_MFWD_FWLTHTL6_LTHFRERNL_Pos (0UL) /*!< LTHFRERNL (Bit 0) */ + #define R_MFWD_FWLTHTL6_LTHFRERNL_Msk (0x7fUL) /*!< LTHFRERNL (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWLTHTL6_LTHFRERVL_Pos (15UL) /*!< LTHFRERVL (Bit 15) */ + #define R_MFWD_FWLTHTL6_LTHFRERVL_Msk (0x8000UL) /*!< LTHFRERVL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTL6_LTHMTRNL_Pos (16UL) /*!< LTHMTRNL (Bit 16) */ + #define R_MFWD_FWLTHTL6_LTHMTRNL_Msk (0x1f0000UL) /*!< LTHMTRNL (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWLTHTL6_LTHMTRVL_Pos (31UL) /*!< LTHMTRVL (Bit 31) */ + #define R_MFWD_FWLTHTL6_LTHMTRVL_Msk (0x80000000UL) /*!< LTHMTRVL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTL7 ======================================================== */ + #define R_MFWD_FWLTHTL7_LTHRNL_Pos (0UL) /*!< LTHRNL (Bit 0) */ + #define R_MFWD_FWLTHTL7_LTHRNL_Msk (0xffUL) /*!< LTHRNL (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWLTHTL7_LTHRVL_Pos (15UL) /*!< LTHRVL (Bit 15) */ + #define R_MFWD_FWLTHTL7_LTHRVL_Msk (0x8000UL) /*!< LTHRVL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTL7_LTHSLVL_Pos (16UL) /*!< LTHSLVL (Bit 16) */ + #define R_MFWD_FWLTHTL7_LTHSLVL_Msk (0x7f0000UL) /*!< LTHSLVL (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWLTHTL80 ======================================================= */ + #define R_MFWD_FWLTHTL80_LTHCSDL_Pos (0UL) /*!< LTHCSDL (Bit 0) */ + #define R_MFWD_FWLTHTL80_LTHCSDL_Msk (0x7fUL) /*!< LTHCSDL (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWLTHTL9 ======================================================== */ + #define R_MFWD_FWLTHTL9_LTHDVL_Pos (0UL) /*!< LTHDVL (Bit 0) */ + #define R_MFWD_FWLTHTL9_LTHDVL_Msk (0x7fUL) /*!< LTHDVL (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWLTHTL9_LTHIPVL_Pos (16UL) /*!< LTHIPVL (Bit 16) */ + #define R_MFWD_FWLTHTL9_LTHIPVL_Msk (0x70000UL) /*!< LTHIPVL (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWLTHTL9_LTHIPUL_Pos (19UL) /*!< LTHIPUL (Bit 19) */ + #define R_MFWD_FWLTHTL9_LTHIPUL_Msk (0x80000UL) /*!< LTHIPUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTL9_LTHEMEL_Pos (20UL) /*!< LTHEMEL (Bit 20) */ + #define R_MFWD_FWLTHTL9_LTHEMEL_Msk (0x100000UL) /*!< LTHEMEL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTL9_LTHCMEL_Pos (21UL) /*!< LTHCMEL (Bit 21) */ + #define R_MFWD_FWLTHTL9_LTHCMEL_Msk (0x200000UL) /*!< LTHCMEL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTLR ======================================================== */ + #define R_MFWD_FWLTHTLR_LTHLF_Pos (0UL) /*!< LTHLF (Bit 0) */ + #define R_MFWD_FWLTHTLR_LTHLF_Msk (0x1UL) /*!< LTHLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTLR_LTHLSF_Pos (1UL) /*!< LTHLSF (Bit 1) */ + #define R_MFWD_FWLTHTLR_LTHLSF_Msk (0x2UL) /*!< LTHLSF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTLR_LTHLEF_Pos (2UL) /*!< LTHLEF (Bit 2) */ + #define R_MFWD_FWLTHTLR_LTHLEF_Msk (0x4UL) /*!< LTHLEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTLR_LTHLO_Pos (3UL) /*!< LTHLO (Bit 3) */ + #define R_MFWD_FWLTHTLR_LTHLO_Msk (0x8UL) /*!< LTHLO (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTLR_LTHLCN_Pos (16UL) /*!< LTHLCN (Bit 16) */ + #define R_MFWD_FWLTHTLR_LTHLCN_Msk (0x3ff0000UL) /*!< LTHLCN (Bitfield-Mask: 0x3ff) */ + #define R_MFWD_FWLTHTLR_LTHTL_Pos (31UL) /*!< LTHTL (Bit 31) */ + #define R_MFWD_FWLTHTLR_LTHTL_Msk (0x80000000UL) /*!< LTHTL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTIM ======================================================== */ + #define R_MFWD_FWLTHTIM_LTHTIOG_Pos (0UL) /*!< LTHTIOG (Bit 0) */ + #define R_MFWD_FWLTHTIM_LTHTIOG_Msk (0x1UL) /*!< LTHTIOG (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTIM_LTHTR_Pos (1UL) /*!< LTHTR (Bit 1) */ + #define R_MFWD_FWLTHTIM_LTHTR_Msk (0x2UL) /*!< LTHTR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTEM ======================================================== */ + #define R_MFWD_FWLTHTEM_LTHTEN_Pos (0UL) /*!< LTHTEN (Bit 0) */ + #define R_MFWD_FWLTHTEM_LTHTEN_Msk (0x7ffUL) /*!< LTHTEN (Bitfield-Mask: 0x7ff) */ + #define R_MFWD_FWLTHTEM_LTHTUEN_Pos (16UL) /*!< LTHTUEN (Bit 16) */ + #define R_MFWD_FWLTHTEM_LTHTUEN_Msk (0x7ff0000UL) /*!< LTHTUEN (Bitfield-Mask: 0x7ff) */ +/* ======================================================= FWLTHTS0 ======================================================== */ + #define R_MFWD_FWLTHTS0_LTHSSP0_Pos (0UL) /*!< LTHSSP0 (Bit 0) */ + #define R_MFWD_FWLTHTS0_LTHSSP0_Msk (0x7UL) /*!< LTHSSP0 (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWLTHTS0_LTHSSPFS_Pos (24UL) /*!< LTHSSPFS (Bit 24) */ + #define R_MFWD_FWLTHTS0_LTHSSPFS_Msk (0x1000000UL) /*!< LTHSSPFS (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTS1 ======================================================== */ + #define R_MFWD_FWLTHTS1_LTHSSP1_Pos (0UL) /*!< LTHSSP1 (Bit 0) */ + #define R_MFWD_FWLTHTS1_LTHSSP1_Msk (0xffffffffUL) /*!< LTHSSP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTS2 ======================================================== */ + #define R_MFWD_FWLTHTS2_LTHSSP2_Pos (0UL) /*!< LTHSSP2 (Bit 0) */ + #define R_MFWD_FWLTHTS2_LTHSSP2_Msk (0xffffffffUL) /*!< LTHSSP2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTS3 ======================================================== */ + #define R_MFWD_FWLTHTS3_LTHSSP3_Pos (0UL) /*!< LTHSSP3 (Bit 0) */ + #define R_MFWD_FWLTHTS3_LTHSSP3_Msk (0xffffffffUL) /*!< LTHSSP3 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTS4 ======================================================== */ + #define R_MFWD_FWLTHTS4_LTHSSP4_Pos (0UL) /*!< LTHSSP4 (Bit 0) */ + #define R_MFWD_FWLTHTS4_LTHSSP4_Msk (0xffffffffUL) /*!< LTHSSP4 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTSR0 ======================================================= */ + #define R_MFWD_FWLTHTSR0_LTHSEF_Pos (0UL) /*!< LTHSEF (Bit 0) */ + #define R_MFWD_FWLTHTSR0_LTHSEF_Msk (0x1UL) /*!< LTHSEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTSR0_LTHSNF_Pos (1UL) /*!< LTHSNF (Bit 1) */ + #define R_MFWD_FWLTHTSR0_LTHSNF_Msk (0x2UL) /*!< LTHSNF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTSR0_LTHSLS_Pos (8UL) /*!< LTHSLS (Bit 8) */ + #define R_MFWD_FWLTHTSR0_LTHSLS_Msk (0x100UL) /*!< LTHSLS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTSR0_LTHSCN_Pos (16UL) /*!< LTHSCN (Bit 16) */ + #define R_MFWD_FWLTHTSR0_LTHSCN_Msk (0x3ff0000UL) /*!< LTHSCN (Bitfield-Mask: 0x3ff) */ + #define R_MFWD_FWLTHTSR0_LTHTS_Pos (31UL) /*!< LTHTS (Bit 31) */ + #define R_MFWD_FWLTHTSR0_LTHTS_Msk (0x80000000UL) /*!< LTHTS (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTSR1 ======================================================= */ + #define R_MFWD_FWLTHTSR1_LTHMSDUNS_Pos (16UL) /*!< LTHMSDUNS (Bit 16) */ + #define R_MFWD_FWLTHTSR1_LTHMSDUNS_Msk (0xf0000UL) /*!< LTHMSDUNS (Bitfield-Mask: 0x0f) */ + #define R_MFWD_FWLTHTSR1_LTHMSDUVS_Pos (31UL) /*!< LTHMSDUVS (Bit 31) */ + #define R_MFWD_FWLTHTSR1_LTHMSDUVS_Msk (0x80000000UL) /*!< LTHMSDUVS (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTSR2 ======================================================= */ + #define R_MFWD_FWLTHTSR2_LTHFRERNS_Pos (0UL) /*!< LTHFRERNS (Bit 0) */ + #define R_MFWD_FWLTHTSR2_LTHFRERNS_Msk (0x3fUL) /*!< LTHFRERNS (Bitfield-Mask: 0x3f) */ + #define R_MFWD_FWLTHTSR2_LTHFRERVS_Pos (15UL) /*!< LTHFRERVS (Bit 15) */ + #define R_MFWD_FWLTHTSR2_LTHFRERVS_Msk (0x8000UL) /*!< LTHFRERVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTSR2_LTHMTRNS_Pos (16UL) /*!< LTHMTRNS (Bit 16) */ + #define R_MFWD_FWLTHTSR2_LTHMTRNS_Msk (0x1f0000UL) /*!< LTHMTRNS (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWLTHTSR2_LTHMTRVS_Pos (31UL) /*!< LTHMTRVS (Bit 31) */ + #define R_MFWD_FWLTHTSR2_LTHMTRVS_Msk (0x80000000UL) /*!< LTHMTRVS (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTSR3 ======================================================= */ + #define R_MFWD_FWLTHTSR3_LTHRNS_Pos (0UL) /*!< LTHRNS (Bit 0) */ + #define R_MFWD_FWLTHTSR3_LTHRNS_Msk (0xffUL) /*!< LTHRNS (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWLTHTSR3_LTHRVS_Pos (15UL) /*!< LTHRVS (Bit 15) */ + #define R_MFWD_FWLTHTSR3_LTHRVS_Msk (0x8000UL) /*!< LTHRVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTSR3_LTHSLVS_Pos (16UL) /*!< LTHSLVS (Bit 16) */ + #define R_MFWD_FWLTHTSR3_LTHSLVS_Msk (0x7f0000UL) /*!< LTHSLVS (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWLTHTSR40 ======================================================= */ + #define R_MFWD_FWLTHTSR40_LTHCSDS_Pos (0UL) /*!< LTHCSDS (Bit 0) */ + #define R_MFWD_FWLTHTSR40_LTHCSDS_Msk (0x7fUL) /*!< LTHCSDS (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWLTHTSR5 ======================================================= */ + #define R_MFWD_FWLTHTSR5_LTHDVS_Pos (0UL) /*!< LTHDVS (Bit 0) */ + #define R_MFWD_FWLTHTSR5_LTHDVS_Msk (0x7fUL) /*!< LTHDVS (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWLTHTSR5_LTHIPVS_Pos (16UL) /*!< LTHIPVS (Bit 16) */ + #define R_MFWD_FWLTHTSR5_LTHIPVS_Msk (0x70000UL) /*!< LTHIPVS (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWLTHTSR5_LTHIPUS_Pos (19UL) /*!< LTHIPUS (Bit 19) */ + #define R_MFWD_FWLTHTSR5_LTHIPUS_Msk (0x80000UL) /*!< LTHIPUS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTSR5_LTHEMES_Pos (20UL) /*!< LTHEMES (Bit 20) */ + #define R_MFWD_FWLTHTSR5_LTHEMES_Msk (0x100000UL) /*!< LTHEMES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTSR5_LTHCMES_Pos (21UL) /*!< LTHCMES (Bit 21) */ + #define R_MFWD_FWLTHTSR5_LTHCMES_Msk (0x200000UL) /*!< LTHCMES (Bitfield-Mask: 0x01) */ +/* ======================================================== FWLTHTR ======================================================== */ + #define R_MFWD_FWLTHTR_LTHAR_Pos (0UL) /*!< LTHAR (Bit 0) */ + #define R_MFWD_FWLTHTR_LTHAR_Msk (0x3ffUL) /*!< LTHAR (Bitfield-Mask: 0x3ff) */ +/* ======================================================= FWLTHTRR0 ======================================================= */ + #define R_MFWD_FWLTHTRR0_LTHREF_Pos (0UL) /*!< LTHREF (Bit 0) */ + #define R_MFWD_FWLTHTRR0_LTHREF_Msk (0x1UL) /*!< LTHREF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTRR0_LTHEVR_Pos (1UL) /*!< LTHEVR (Bit 1) */ + #define R_MFWD_FWLTHTRR0_LTHEVR_Msk (0x2UL) /*!< LTHEVR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTRR0_LTHTR_Pos (31UL) /*!< LTHTR (Bit 31) */ + #define R_MFWD_FWLTHTRR0_LTHTR_Msk (0x80000000UL) /*!< LTHTR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTRR1 ======================================================= */ + #define R_MFWD_FWLTHTRR1_LTHSRP0_Pos (0UL) /*!< LTHSRP0 (Bit 0) */ + #define R_MFWD_FWLTHTRR1_LTHSRP0_Msk (0x7UL) /*!< LTHSRP0 (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWLTHTRR1_LTHSLR_Pos (8UL) /*!< LTHSLR (Bit 8) */ + #define R_MFWD_FWLTHTRR1_LTHSLR_Msk (0x100UL) /*!< LTHSLR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTRR2 ======================================================= */ + #define R_MFWD_FWLTHTRR2_LTHSRP1_Pos (0UL) /*!< LTHSRP1 (Bit 0) */ + #define R_MFWD_FWLTHTRR2_LTHSRP1_Msk (0xffffffffUL) /*!< LTHSRP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTRR3 ======================================================= */ + #define R_MFWD_FWLTHTRR3_LTHSRP2_Pos (0UL) /*!< LTHSRP2 (Bit 0) */ + #define R_MFWD_FWLTHTRR3_LTHSRP2_Msk (0xffffffffUL) /*!< LTHSRP2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTRR4 ======================================================= */ + #define R_MFWD_FWLTHTRR4_LTHSRP3_Pos (0UL) /*!< LTHSRP3 (Bit 0) */ + #define R_MFWD_FWLTHTRR4_LTHSRP3_Msk (0xffffffffUL) /*!< LTHSRP3 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTRR5 ======================================================= */ + #define R_MFWD_FWLTHTRR5_LTHSRP4_Pos (0UL) /*!< LTHSRP4 (Bit 0) */ + #define R_MFWD_FWLTHTRR5_LTHSRP4_Msk (0xffffffffUL) /*!< LTHSRP4 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTRR6 ======================================================= */ + #define R_MFWD_FWLTHTRR6_LTHMSDUNR_Pos (16UL) /*!< LTHMSDUNR (Bit 16) */ + #define R_MFWD_FWLTHTRR6_LTHMSDUNR_Msk (0xf0000UL) /*!< LTHMSDUNR (Bitfield-Mask: 0x0f) */ + #define R_MFWD_FWLTHTRR6_LTHMSDUVR_Pos (31UL) /*!< LTHMSDUVR (Bit 31) */ + #define R_MFWD_FWLTHTRR6_LTHMSDUVR_Msk (0x80000000UL) /*!< LTHMSDUVR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTRR7 ======================================================= */ + #define R_MFWD_FWLTHTRR7_LTHFRERNR_Pos (0UL) /*!< LTHFRERNR (Bit 0) */ + #define R_MFWD_FWLTHTRR7_LTHFRERNR_Msk (0x3fUL) /*!< LTHFRERNR (Bitfield-Mask: 0x3f) */ + #define R_MFWD_FWLTHTRR7_LTHFRERVR_Pos (15UL) /*!< LTHFRERVR (Bit 15) */ + #define R_MFWD_FWLTHTRR7_LTHFRERVR_Msk (0x8000UL) /*!< LTHFRERVR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTRR7_LTHMTRNR_Pos (16UL) /*!< LTHMTRNR (Bit 16) */ + #define R_MFWD_FWLTHTRR7_LTHMTRNR_Msk (0x1f0000UL) /*!< LTHMTRNR (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWLTHTRR7_LTHMTRVR_Pos (31UL) /*!< LTHMTRVR (Bit 31) */ + #define R_MFWD_FWLTHTRR7_LTHMTRVR_Msk (0x80000000UL) /*!< LTHMTRVR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTRR8 ======================================================= */ + #define R_MFWD_FWLTHTRR8_LTHRNR_Pos (0UL) /*!< LTHRNR (Bit 0) */ + #define R_MFWD_FWLTHTRR8_LTHRNR_Msk (0xffUL) /*!< LTHRNR (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWLTHTRR8_LTHRVR_Pos (15UL) /*!< LTHRVR (Bit 15) */ + #define R_MFWD_FWLTHTRR8_LTHRVR_Msk (0x8000UL) /*!< LTHRVR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTRR8_LTHSLVR_Pos (16UL) /*!< LTHSLVR (Bit 16) */ + #define R_MFWD_FWLTHTRR8_LTHSLVR_Msk (0x7f0000UL) /*!< LTHSLVR (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWLTHTRR90 ======================================================= */ + #define R_MFWD_FWLTHTRR90_LTHCSDR_Pos (0UL) /*!< LTHCSDR (Bit 0) */ + #define R_MFWD_FWLTHTRR90_LTHCSDR_Msk (0x7fUL) /*!< LTHCSDR (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWLTHTRR10 ======================================================= */ + #define R_MFWD_FWLTHTRR10_LTHDVR_Pos (0UL) /*!< LTHDVR (Bit 0) */ + #define R_MFWD_FWLTHTRR10_LTHDVR_Msk (0x7fUL) /*!< LTHDVR (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWLTHTRR10_LTHIPVR_Pos (16UL) /*!< LTHIPVR (Bit 16) */ + #define R_MFWD_FWLTHTRR10_LTHIPVR_Msk (0x70000UL) /*!< LTHIPVR (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWLTHTRR10_LTHIPUR_Pos (19UL) /*!< LTHIPUR (Bit 19) */ + #define R_MFWD_FWLTHTRR10_LTHIPUR_Msk (0x80000UL) /*!< LTHIPUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTRR10_LTHEMER_Pos (20UL) /*!< LTHEMER (Bit 20) */ + #define R_MFWD_FWLTHTRR10_LTHEMER_Msk (0x100000UL) /*!< LTHEMER (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTRR10_LTHCMER_Pos (21UL) /*!< LTHCMER (Bit 21) */ + #define R_MFWD_FWLTHTRR10_LTHCMER_Msk (0x200000UL) /*!< LTHCMER (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACHEC ======================================================== */ + #define R_MFWD_FWMACHEC_MACHMC_Pos (0UL) /*!< MACHMC (Bit 0) */ + #define R_MFWD_FWMACHEC_MACHMC_Msk (0x7ffUL) /*!< MACHMC (Bitfield-Mask: 0x7ff) */ + #define R_MFWD_FWMACHEC_MACHMUE_Pos (16UL) /*!< MACHMUE (Bit 16) */ + #define R_MFWD_FWMACHEC_MACHMUE_Msk (0xfff0000UL) /*!< MACHMUE (Bitfield-Mask: 0xfff) */ +/* ======================================================== FWMACHC ======================================================== */ + #define R_MFWD_FWMACHC_MACHE_Pos (0UL) /*!< MACHE (Bit 0) */ + #define R_MFWD_FWMACHC_MACHE_Msk (0x7ffUL) /*!< MACHE (Bitfield-Mask: 0x7ff) */ +/* ======================================================= FWMACTL0 ======================================================== */ + #define R_MFWD_FWMACTL0_MACSLL_Pos (8UL) /*!< MACSLL (Bit 8) */ + #define R_MFWD_FWMACTL0_MACSLL_Msk (0x100UL) /*!< MACSLL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTL0_MACDEL_Pos (9UL) /*!< MACDEL (Bit 9) */ + #define R_MFWD_FWMACTL0_MACDEL_Msk (0x200UL) /*!< MACDEL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTL0_MACHLDL_Pos (10UL) /*!< MACHLDL (Bit 10) */ + #define R_MFWD_FWMACTL0_MACHLDL_Msk (0x400UL) /*!< MACHLDL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTL0_MACED_Pos (16UL) /*!< MACED (Bit 16) */ + #define R_MFWD_FWMACTL0_MACED_Msk (0x10000UL) /*!< MACED (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACTL1 ======================================================== */ + #define R_MFWD_FWMACTL1_MACMALP0_Pos (0UL) /*!< MACMALP0 (Bit 0) */ + #define R_MFWD_FWMACTL1_MACMALP0_Msk (0xffffUL) /*!< MACMALP0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWMACTL2 ======================================================== */ + #define R_MFWD_FWMACTL2_MACMALP1_Pos (0UL) /*!< MACMALP1 (Bit 0) */ + #define R_MFWD_FWMACTL2_MACMALP1_Msk (0xffffffffUL) /*!< MACMALP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWMACTL3 ======================================================== */ + #define R_MFWD_FWMACTL3_MACSSLVL_Pos (0UL) /*!< MACSSLVL (Bit 0) */ + #define R_MFWD_FWMACTL3_MACSSLVL_Msk (0x7fUL) /*!< MACSSLVL (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWMACTL3_MACDSLVL_Pos (16UL) /*!< MACDSLVL (Bit 16) */ + #define R_MFWD_FWMACTL3_MACDSLVL_Msk (0x7f0000UL) /*!< MACDSLVL (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWMACTL40 ======================================================= */ + #define R_MFWD_FWMACTL40_MACCSDL_Pos (0UL) /*!< MACCSDL (Bit 0) */ + #define R_MFWD_FWMACTL40_MACCSDL_Msk (0x7fUL) /*!< MACCSDL (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWMACTL5 ======================================================== */ + #define R_MFWD_FWMACTL5_MACDVL_Pos (0UL) /*!< MACDVL (Bit 0) */ + #define R_MFWD_FWMACTL5_MACDVL_Msk (0x7fUL) /*!< MACDVL (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWMACTL5_MACIPVL_Pos (16UL) /*!< MACIPVL (Bit 16) */ + #define R_MFWD_FWMACTL5_MACIPVL_Msk (0x70000UL) /*!< MACIPVL (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWMACTL5_MACIPUL_Pos (19UL) /*!< MACIPUL (Bit 19) */ + #define R_MFWD_FWMACTL5_MACIPUL_Msk (0x80000UL) /*!< MACIPUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTL5_MACEMEL_Pos (20UL) /*!< MACEMEL (Bit 20) */ + #define R_MFWD_FWMACTL5_MACEMEL_Msk (0x100000UL) /*!< MACEMEL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTL5_MACCMEL_Pos (21UL) /*!< MACCMEL (Bit 21) */ + #define R_MFWD_FWMACTL5_MACCMEL_Msk (0x200000UL) /*!< MACCMEL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACTLR ======================================================== */ + #define R_MFWD_FWMACTLR_MACLF_Pos (0UL) /*!< MACLF (Bit 0) */ + #define R_MFWD_FWMACTLR_MACLF_Msk (0x1UL) /*!< MACLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTLR_MACLSF_Pos (1UL) /*!< MACLSF (Bit 1) */ + #define R_MFWD_FWMACTLR_MACLSF_Msk (0x2UL) /*!< MACLSF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTLR_MACLEF_Pos (2UL) /*!< MACLEF (Bit 2) */ + #define R_MFWD_FWMACTLR_MACLEF_Msk (0x4UL) /*!< MACLEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTLR_MACLO_Pos (3UL) /*!< MACLO (Bit 3) */ + #define R_MFWD_FWMACTLR_MACLO_Msk (0x8UL) /*!< MACLO (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTLR_MACLCN_Pos (16UL) /*!< MACLCN (Bit 16) */ + #define R_MFWD_FWMACTLR_MACLCN_Msk (0x3ff0000UL) /*!< MACLCN (Bitfield-Mask: 0x3ff) */ + #define R_MFWD_FWMACTLR_MACTL_Pos (31UL) /*!< MACTL (Bit 31) */ + #define R_MFWD_FWMACTLR_MACTL_Msk (0x80000000UL) /*!< MACTL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACTIM ======================================================== */ + #define R_MFWD_FWMACTIM_MACTIOG_Pos (0UL) /*!< MACTIOG (Bit 0) */ + #define R_MFWD_FWMACTIM_MACTIOG_Msk (0x1UL) /*!< MACTIOG (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTIM_MACTR_Pos (1UL) /*!< MACTR (Bit 1) */ + #define R_MFWD_FWMACTIM_MACTR_Msk (0x2UL) /*!< MACTR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACTEM ======================================================== */ + #define R_MFWD_FWMACTEM_MACTEN_Pos (0UL) /*!< MACTEN (Bit 0) */ + #define R_MFWD_FWMACTEM_MACTEN_Msk (0x7ffUL) /*!< MACTEN (Bitfield-Mask: 0x7ff) */ + #define R_MFWD_FWMACTEM_MACTUEN_Pos (16UL) /*!< MACTUEN (Bit 16) */ + #define R_MFWD_FWMACTEM_MACTUEN_Msk (0x7ff0000UL) /*!< MACTUEN (Bitfield-Mask: 0x7ff) */ +/* ======================================================= FWMACTS0 ======================================================== */ + #define R_MFWD_FWMACTS0_MACMASP0_Pos (0UL) /*!< MACMASP0 (Bit 0) */ + #define R_MFWD_FWMACTS0_MACMASP0_Msk (0xffffUL) /*!< MACMASP0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWMACTS1 ======================================================== */ + #define R_MFWD_FWMACTS1_MACMASP1_Pos (0UL) /*!< MACMASP1 (Bit 0) */ + #define R_MFWD_FWMACTS1_MACMASP1_Msk (0xffffffffUL) /*!< MACMASP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWMACTSR0 ======================================================= */ + #define R_MFWD_FWMACTSR0_MACSEF_Pos (0UL) /*!< MACSEF (Bit 0) */ + #define R_MFWD_FWMACTSR0_MACSEF_Msk (0x1UL) /*!< MACSEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTSR0_MACSNF_Pos (1UL) /*!< MACSNF (Bit 1) */ + #define R_MFWD_FWMACTSR0_MACSNF_Msk (0x2UL) /*!< MACSNF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTSR0_MACSLS_Pos (8UL) /*!< MACSLS (Bit 8) */ + #define R_MFWD_FWMACTSR0_MACSLS_Msk (0x100UL) /*!< MACSLS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTSR0_MACDES_Pos (9UL) /*!< MACDES (Bit 9) */ + #define R_MFWD_FWMACTSR0_MACDES_Msk (0x200UL) /*!< MACDES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTSR0_MACHLDS_Pos (10UL) /*!< MACHLDS (Bit 10) */ + #define R_MFWD_FWMACTSR0_MACHLDS_Msk (0x400UL) /*!< MACHLDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTSR0_MACSCN_Pos (16UL) /*!< MACSCN (Bit 16) */ + #define R_MFWD_FWMACTSR0_MACSCN_Msk (0x3ff0000UL) /*!< MACSCN (Bitfield-Mask: 0x3ff) */ + #define R_MFWD_FWMACTSR0_MACTS_Pos (31UL) /*!< MACTS (Bit 31) */ + #define R_MFWD_FWMACTSR0_MACTS_Msk (0x80000000UL) /*!< MACTS (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACTSR1 ======================================================= */ + #define R_MFWD_FWMACTSR1_MACSSLVS_Pos (0UL) /*!< MACSSLVS (Bit 0) */ + #define R_MFWD_FWMACTSR1_MACSSLVS_Msk (0x7fUL) /*!< MACSSLVS (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWMACTSR1_MACDSLVS_Pos (16UL) /*!< MACDSLVS (Bit 16) */ + #define R_MFWD_FWMACTSR1_MACDSLVS_Msk (0x7f0000UL) /*!< MACDSLVS (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWMACTSR20 ======================================================= */ + #define R_MFWD_FWMACTSR20_MACCSDS_Pos (0UL) /*!< MACCSDS (Bit 0) */ + #define R_MFWD_FWMACTSR20_MACCSDS_Msk (0x7fUL) /*!< MACCSDS (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWMACTSR3 ======================================================= */ + #define R_MFWD_FWMACTSR3_MACDVS_Pos (0UL) /*!< MACDVS (Bit 0) */ + #define R_MFWD_FWMACTSR3_MACDVS_Msk (0x7fUL) /*!< MACDVS (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWMACTSR3_MACIPVS_Pos (16UL) /*!< MACIPVS (Bit 16) */ + #define R_MFWD_FWMACTSR3_MACIPVS_Msk (0x70000UL) /*!< MACIPVS (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWMACTSR3_MACIPUS_Pos (19UL) /*!< MACIPUS (Bit 19) */ + #define R_MFWD_FWMACTSR3_MACIPUS_Msk (0x80000UL) /*!< MACIPUS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTSR3_MACEMES_Pos (20UL) /*!< MACEMES (Bit 20) */ + #define R_MFWD_FWMACTSR3_MACEMES_Msk (0x100000UL) /*!< MACEMES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTSR3_MACCMES_Pos (21UL) /*!< MACCMES (Bit 21) */ + #define R_MFWD_FWMACTSR3_MACCMES_Msk (0x200000UL) /*!< MACCMES (Bitfield-Mask: 0x01) */ +/* ======================================================== FWMACTR ======================================================== */ + #define R_MFWD_FWMACTR_MACAR_Pos (0UL) /*!< MACAR (Bit 0) */ + #define R_MFWD_FWMACTR_MACAR_Msk (0x3ffUL) /*!< MACAR (Bitfield-Mask: 0x3ff) */ +/* ======================================================= FWMACTRR0 ======================================================= */ + #define R_MFWD_FWMACTRR0_MACEVR_Pos (0UL) /*!< MACEVR (Bit 0) */ + #define R_MFWD_FWMACTRR0_MACEVR_Msk (0x1UL) /*!< MACEVR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTRR0_MACREF_Pos (1UL) /*!< MACREF (Bit 1) */ + #define R_MFWD_FWMACTRR0_MACREF_Msk (0x2UL) /*!< MACREF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTRR0_MACTR_Pos (31UL) /*!< MACTR (Bit 31) */ + #define R_MFWD_FWMACTRR0_MACTR_Msk (0x80000000UL) /*!< MACTR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACTRR1 ======================================================= */ + #define R_MFWD_FWMACTRR1_MACSLR_Pos (8UL) /*!< MACSLR (Bit 8) */ + #define R_MFWD_FWMACTRR1_MACSLR_Msk (0x100UL) /*!< MACSLR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTRR1_MACDER_Pos (9UL) /*!< MACDER (Bit 9) */ + #define R_MFWD_FWMACTRR1_MACDER_Msk (0x200UL) /*!< MACDER (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTRR1_MACHLDR_Pos (10UL) /*!< MACHLDR (Bit 10) */ + #define R_MFWD_FWMACTRR1_MACHLDR_Msk (0x400UL) /*!< MACHLDR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTRR1_MACABR_Pos (11UL) /*!< MACABR (Bit 11) */ + #define R_MFWD_FWMACTRR1_MACABR_Msk (0x800UL) /*!< MACABR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACTRR2 ======================================================= */ + #define R_MFWD_FWMACTRR2_MACMARP0_Pos (0UL) /*!< MACMARP0 (Bit 0) */ + #define R_MFWD_FWMACTRR2_MACMARP0_Msk (0xffffUL) /*!< MACMARP0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWMACTRR3 ======================================================= */ + #define R_MFWD_FWMACTRR3_MACMARP1_Pos (0UL) /*!< MACMARP1 (Bit 0) */ + #define R_MFWD_FWMACTRR3_MACMARP1_Msk (0xffffffffUL) /*!< MACMARP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWMACTRR4 ======================================================= */ + #define R_MFWD_FWMACTRR4_MACSSLVR_Pos (0UL) /*!< MACSSLVR (Bit 0) */ + #define R_MFWD_FWMACTRR4_MACSSLVR_Msk (0x7fUL) /*!< MACSSLVR (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWMACTRR4_MACDSLVR_Pos (16UL) /*!< MACDSLVR (Bit 16) */ + #define R_MFWD_FWMACTRR4_MACDSLVR_Msk (0x7f0000UL) /*!< MACDSLVR (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWMACTRR50 ======================================================= */ + #define R_MFWD_FWMACTRR50_MACCSDR_Pos (0UL) /*!< MACCSDR (Bit 0) */ + #define R_MFWD_FWMACTRR50_MACCSDR_Msk (0x7fUL) /*!< MACCSDR (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWMACTRR6 ======================================================= */ + #define R_MFWD_FWMACTRR6_MACDVR_Pos (0UL) /*!< MACDVR (Bit 0) */ + #define R_MFWD_FWMACTRR6_MACDVR_Msk (0x7fUL) /*!< MACDVR (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWMACTRR6_MACIPVR_Pos (16UL) /*!< MACIPVR (Bit 16) */ + #define R_MFWD_FWMACTRR6_MACIPVR_Msk (0x70000UL) /*!< MACIPVR (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWMACTRR6_MACIPUR_Pos (19UL) /*!< MACIPUR (Bit 19) */ + #define R_MFWD_FWMACTRR6_MACIPUR_Msk (0x80000UL) /*!< MACIPUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTRR6_MACEMER_Pos (20UL) /*!< MACEMER (Bit 20) */ + #define R_MFWD_FWMACTRR6_MACEMER_Msk (0x100000UL) /*!< MACEMER (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTRR6_MACCMER_Pos (21UL) /*!< MACCMER (Bit 21) */ + #define R_MFWD_FWMACTRR6_MACCMER_Msk (0x200000UL) /*!< MACCMER (Bitfield-Mask: 0x01) */ +/* ====================================================== FWMACAGUSPC ====================================================== */ + #define R_MFWD_FWMACAGUSPC_MACAGUSP_Pos (0UL) /*!< MACAGUSP (Bit 0) */ + #define R_MFWD_FWMACAGUSPC_MACAGUSP_Msk (0x3ffUL) /*!< MACAGUSP (Bitfield-Mask: 0x3ff) */ +/* ======================================================= FWMACAGC ======================================================== */ + #define R_MFWD_FWMACAGC_MACAGT_Pos (0UL) /*!< MACAGT (Bit 0) */ + #define R_MFWD_FWMACAGC_MACAGT_Msk (0xffffUL) /*!< MACAGT (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWMACAGC_MACAGE_Pos (16UL) /*!< MACAGE (Bit 16) */ + #define R_MFWD_FWMACAGC_MACAGE_Msk (0x10000UL) /*!< MACAGE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACAGC_MACAGSL_Pos (17UL) /*!< MACAGSL (Bit 17) */ + #define R_MFWD_FWMACAGC_MACAGSL_Msk (0x20000UL) /*!< MACAGSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACAGC_MACAGPM_Pos (18UL) /*!< MACAGPM (Bit 18) */ + #define R_MFWD_FWMACAGC_MACAGPM_Msk (0x40000UL) /*!< MACAGPM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACAGC_MACDES_Pos (24UL) /*!< MACDES (Bit 24) */ + #define R_MFWD_FWMACAGC_MACDES_Msk (0x1000000UL) /*!< MACDES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACAGC_MACAGOG_Pos (28UL) /*!< MACAGOG (Bit 28) */ + #define R_MFWD_FWMACAGC_MACAGOG_Msk (0x10000000UL) /*!< MACAGOG (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACAGC_MACDESOG_Pos (29UL) /*!< MACDESOG (Bit 29) */ + #define R_MFWD_FWMACAGC_MACDESOG_Msk (0x20000000UL) /*!< MACDESOG (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACAGM0 ======================================================= */ + #define R_MFWD_FWMACAGM0_AGMACAP0_Pos (0UL) /*!< AGMACAP0 (Bit 0) */ + #define R_MFWD_FWMACAGM0_AGMACAP0_Msk (0xffffUL) /*!< AGMACAP0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWMACAGM1 ======================================================= */ + #define R_MFWD_FWMACAGM1_AGMACAP1_Pos (0UL) /*!< AGMACAP1 (Bit 0) */ + #define R_MFWD_FWMACAGM1_AGMACAP1_Msk (0xffffffffUL) /*!< AGMACAP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWVLANTEC ======================================================= */ + #define R_MFWD_FWVLANTEC_VLANTMUE_Pos (16UL) /*!< VLANTMUE (Bit 16) */ + #define R_MFWD_FWVLANTEC_VLANTMUE_Msk (0x1fff0000UL) /*!< VLANTMUE (Bitfield-Mask: 0x1fff) */ +/* ======================================================= FWVLANTL0 ======================================================= */ + #define R_MFWD_FWVLANTL0_VLANSLL_Pos (8UL) /*!< VLANSLL (Bit 8) */ + #define R_MFWD_FWVLANTL0_VLANSLL_Msk (0x100UL) /*!< VLANSLL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTL0_VLANHLDL_Pos (10UL) /*!< VLANHLDL (Bit 10) */ + #define R_MFWD_FWVLANTL0_VLANHLDL_Msk (0x400UL) /*!< VLANHLDL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTL0_VLANED_Pos (16UL) /*!< VLANED (Bit 16) */ + #define R_MFWD_FWVLANTL0_VLANED_Msk (0x10000UL) /*!< VLANED (Bitfield-Mask: 0x01) */ +/* ======================================================= FWVLANTL1 ======================================================= */ + #define R_MFWD_FWVLANTL1_VLANVIDL_Pos (0UL) /*!< VLANVIDL (Bit 0) */ + #define R_MFWD_FWVLANTL1_VLANVIDL_Msk (0xfffUL) /*!< VLANVIDL (Bitfield-Mask: 0xfff) */ +/* ======================================================= FWVLANTL2 ======================================================= */ + #define R_MFWD_FWVLANTL2_VLANSLVL_Pos (0UL) /*!< VLANSLVL (Bit 0) */ + #define R_MFWD_FWVLANTL2_VLANSLVL_Msk (0x7fUL) /*!< VLANSLVL (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWVLANTL30 ======================================================= */ + #define R_MFWD_FWVLANTL30_VLANCSDL_Pos (0UL) /*!< VLANCSDL (Bit 0) */ + #define R_MFWD_FWVLANTL30_VLANCSDL_Msk (0x7fUL) /*!< VLANCSDL (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWVLANTL4 ======================================================= */ + #define R_MFWD_FWVLANTL4_VLANDVL_Pos (0UL) /*!< VLANDVL (Bit 0) */ + #define R_MFWD_FWVLANTL4_VLANDVL_Msk (0x7fUL) /*!< VLANDVL (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWVLANTL4_VLANIPVL_Pos (16UL) /*!< VLANIPVL (Bit 16) */ + #define R_MFWD_FWVLANTL4_VLANIPVL_Msk (0x70000UL) /*!< VLANIPVL (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWVLANTL4_VLANIPUL_Pos (19UL) /*!< VLANIPUL (Bit 19) */ + #define R_MFWD_FWVLANTL4_VLANIPUL_Msk (0x80000UL) /*!< VLANIPUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTL4_VLANEMEL_Pos (20UL) /*!< VLANEMEL (Bit 20) */ + #define R_MFWD_FWVLANTL4_VLANEMEL_Msk (0x100000UL) /*!< VLANEMEL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTL4_VLANCMEL_Pos (21UL) /*!< VLANCMEL (Bit 21) */ + #define R_MFWD_FWVLANTL4_VLANCMEL_Msk (0x200000UL) /*!< VLANCMEL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWVLANTLR ======================================================= */ + #define R_MFWD_FWVLANTLR_VLANLF_Pos (0UL) /*!< VLANLF (Bit 0) */ + #define R_MFWD_FWVLANTLR_VLANLF_Msk (0x1UL) /*!< VLANLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTLR_VLANLSF_Pos (1UL) /*!< VLANLSF (Bit 1) */ + #define R_MFWD_FWVLANTLR_VLANLSF_Msk (0x2UL) /*!< VLANLSF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTLR_VLANLEF_Pos (2UL) /*!< VLANLEF (Bit 2) */ + #define R_MFWD_FWVLANTLR_VLANLEF_Msk (0x4UL) /*!< VLANLEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTLR_VLANLO_Pos (3UL) /*!< VLANLO (Bit 3) */ + #define R_MFWD_FWVLANTLR_VLANLO_Msk (0x8UL) /*!< VLANLO (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTLR_VLANTL_Pos (31UL) /*!< VLANTL (Bit 31) */ + #define R_MFWD_FWVLANTLR_VLANTL_Msk (0x80000000UL) /*!< VLANTL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWVLANTIM ======================================================= */ + #define R_MFWD_FWVLANTIM_VLANTIOG_Pos (0UL) /*!< VLANTIOG (Bit 0) */ + #define R_MFWD_FWVLANTIM_VLANTIOG_Msk (0x1UL) /*!< VLANTIOG (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTIM_VLANTR_Pos (1UL) /*!< VLANTR (Bit 1) */ + #define R_MFWD_FWVLANTIM_VLANTR_Msk (0x2UL) /*!< VLANTR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWVLANTEM ======================================================= */ + #define R_MFWD_FWVLANTEM_VLANTEN_Pos (0UL) /*!< VLANTEN (Bit 0) */ + #define R_MFWD_FWVLANTEM_VLANTEN_Msk (0x1fffUL) /*!< VLANTEN (Bitfield-Mask: 0x1fff) */ + #define R_MFWD_FWVLANTEM_VLANTUEN_Pos (16UL) /*!< VLANTUEN (Bit 16) */ + #define R_MFWD_FWVLANTEM_VLANTUEN_Msk (0x1fff0000UL) /*!< VLANTUEN (Bitfield-Mask: 0x1fff) */ +/* ======================================================= FWVLANTS ======================================================== */ + #define R_MFWD_FWVLANTS_VLANVIDS_Pos (0UL) /*!< VLANVIDS (Bit 0) */ + #define R_MFWD_FWVLANTS_VLANVIDS_Msk (0xfffUL) /*!< VLANVIDS (Bitfield-Mask: 0xfff) */ +/* ====================================================== FWVLANTSR0 ======================================================= */ + #define R_MFWD_FWVLANTSR0_VLANSEF_Pos (0UL) /*!< VLANSEF (Bit 0) */ + #define R_MFWD_FWVLANTSR0_VLANSEF_Msk (0x1UL) /*!< VLANSEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTSR0_VLANSNF_Pos (1UL) /*!< VLANSNF (Bit 1) */ + #define R_MFWD_FWVLANTSR0_VLANSNF_Msk (0x2UL) /*!< VLANSNF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTSR0_VLANSLS_Pos (8UL) /*!< VLANSLS (Bit 8) */ + #define R_MFWD_FWVLANTSR0_VLANSLS_Msk (0x100UL) /*!< VLANSLS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTSR0_VLANHLDS_Pos (10UL) /*!< VLANHLDS (Bit 10) */ + #define R_MFWD_FWVLANTSR0_VLANHLDS_Msk (0x400UL) /*!< VLANHLDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTSR0_VLANTS_Pos (31UL) /*!< VLANTS (Bit 31) */ + #define R_MFWD_FWVLANTSR0_VLANTS_Msk (0x80000000UL) /*!< VLANTS (Bitfield-Mask: 0x01) */ +/* ====================================================== FWVLANTSR1 ======================================================= */ + #define R_MFWD_FWVLANTSR1_VLANSLVS_Pos (0UL) /*!< VLANSLVS (Bit 0) */ + #define R_MFWD_FWVLANTSR1_VLANSLVS_Msk (0x7fUL) /*!< VLANSLVS (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWVLANTSR20 ====================================================== */ + #define R_MFWD_FWVLANTSR20_VLANCSDS_Pos (0UL) /*!< VLANCSDS (Bit 0) */ + #define R_MFWD_FWVLANTSR20_VLANCSDS_Msk (0x7fUL) /*!< VLANCSDS (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWVLANTSR3 ======================================================= */ + #define R_MFWD_FWVLANTSR3_VLANDVS_Pos (0UL) /*!< VLANDVS (Bit 0) */ + #define R_MFWD_FWVLANTSR3_VLANDVS_Msk (0x7fUL) /*!< VLANDVS (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWVLANTSR3_VLANIPVS_Pos (16UL) /*!< VLANIPVS (Bit 16) */ + #define R_MFWD_FWVLANTSR3_VLANIPVS_Msk (0x70000UL) /*!< VLANIPVS (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWVLANTSR3_VLANIPUS_Pos (19UL) /*!< VLANIPUS (Bit 19) */ + #define R_MFWD_FWVLANTSR3_VLANIPUS_Msk (0x80000UL) /*!< VLANIPUS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTSR3_VLANEMES_Pos (20UL) /*!< VLANEMES (Bit 20) */ + #define R_MFWD_FWVLANTSR3_VLANEMES_Msk (0x100000UL) /*!< VLANEMES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTSR3_VLANCMES_Pos (21UL) /*!< VLANCMES (Bit 21) */ + #define R_MFWD_FWVLANTSR3_VLANCMES_Msk (0x200000UL) /*!< VLANCMES (Bitfield-Mask: 0x01) */ +/* ======================================================== FWPBFC0 ======================================================== */ + #define R_MFWD_FWPBFC0_PBDV_Pos (0UL) /*!< PBDV (Bit 0) */ + #define R_MFWD_FWPBFC0_PBDV_Msk (0x7fUL) /*!< PBDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWPBFC0_PBIPV_Pos (16UL) /*!< PBIPV (Bit 16) */ + #define R_MFWD_FWPBFC0_PBIPV_Msk (0x70000UL) /*!< PBIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWPBFC0_PBIPU_Pos (19UL) /*!< PBIPU (Bit 19) */ + #define R_MFWD_FWPBFC0_PBIPU_Msk (0x80000UL) /*!< PBIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC0_PBEME_Pos (20UL) /*!< PBEME (Bit 20) */ + #define R_MFWD_FWPBFC0_PBEME_Msk (0x100000UL) /*!< PBEME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC0_PBCME_Pos (21UL) /*!< PBCME (Bit 21) */ + #define R_MFWD_FWPBFC0_PBCME_Msk (0x200000UL) /*!< PBCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC0_PBSL_Pos (22UL) /*!< PBSL (Bit 22) */ + #define R_MFWD_FWPBFC0_PBSL_Msk (0x400000UL) /*!< PBSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC0_IP4PDE_Pos (23UL) /*!< IP4PDE (Bit 23) */ + #define R_MFWD_FWPBFC0_IP4PDE_Msk (0x800000UL) /*!< IP4PDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC0_IP4PDM_Pos (24UL) /*!< IP4PDM (Bit 24) */ + #define R_MFWD_FWPBFC0_IP4PDM_Msk (0x1000000UL) /*!< IP4PDM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC0_IP6PDE_Pos (25UL) /*!< IP6PDE (Bit 25) */ + #define R_MFWD_FWPBFC0_IP6PDE_Msk (0x2000000UL) /*!< IP6PDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC0_FAIFP_Pos (26UL) /*!< FAIFP (Bit 26) */ + #define R_MFWD_FWPBFC0_FAIFP_Msk (0x4000000UL) /*!< FAIFP (Bitfield-Mask: 0x01) */ +/* ======================================================== FWPBFC1 ======================================================== */ + #define R_MFWD_FWPBFC1_PBDV_Pos (0UL) /*!< PBDV (Bit 0) */ + #define R_MFWD_FWPBFC1_PBDV_Msk (0x7fUL) /*!< PBDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWPBFC1_PBIPV_Pos (16UL) /*!< PBIPV (Bit 16) */ + #define R_MFWD_FWPBFC1_PBIPV_Msk (0x70000UL) /*!< PBIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWPBFC1_PBIPU_Pos (19UL) /*!< PBIPU (Bit 19) */ + #define R_MFWD_FWPBFC1_PBIPU_Msk (0x80000UL) /*!< PBIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC1_PBEME_Pos (20UL) /*!< PBEME (Bit 20) */ + #define R_MFWD_FWPBFC1_PBEME_Msk (0x100000UL) /*!< PBEME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC1_PBCME_Pos (21UL) /*!< PBCME (Bit 21) */ + #define R_MFWD_FWPBFC1_PBCME_Msk (0x200000UL) /*!< PBCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC1_PBSL_Pos (22UL) /*!< PBSL (Bit 22) */ + #define R_MFWD_FWPBFC1_PBSL_Msk (0x400000UL) /*!< PBSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC1_IP4PDE_Pos (23UL) /*!< IP4PDE (Bit 23) */ + #define R_MFWD_FWPBFC1_IP4PDE_Msk (0x800000UL) /*!< IP4PDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC1_IP4PDM_Pos (24UL) /*!< IP4PDM (Bit 24) */ + #define R_MFWD_FWPBFC1_IP4PDM_Msk (0x1000000UL) /*!< IP4PDM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC1_IP6PDE_Pos (25UL) /*!< IP6PDE (Bit 25) */ + #define R_MFWD_FWPBFC1_IP6PDE_Msk (0x2000000UL) /*!< IP6PDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC1_FAIFP_Pos (26UL) /*!< FAIFP (Bit 26) */ + #define R_MFWD_FWPBFC1_FAIFP_Msk (0x4000000UL) /*!< FAIFP (Bitfield-Mask: 0x01) */ +/* ======================================================== FWPBFC2 ======================================================== */ + #define R_MFWD_FWPBFC2_PBDV_Pos (0UL) /*!< PBDV (Bit 0) */ + #define R_MFWD_FWPBFC2_PBDV_Msk (0x7fUL) /*!< PBDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWPBFC2_PBIPV_Pos (16UL) /*!< PBIPV (Bit 16) */ + #define R_MFWD_FWPBFC2_PBIPV_Msk (0x70000UL) /*!< PBIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWPBFC2_PBIPU_Pos (19UL) /*!< PBIPU (Bit 19) */ + #define R_MFWD_FWPBFC2_PBIPU_Msk (0x80000UL) /*!< PBIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC2_PBEME_Pos (20UL) /*!< PBEME (Bit 20) */ + #define R_MFWD_FWPBFC2_PBEME_Msk (0x100000UL) /*!< PBEME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC2_PBCME_Pos (21UL) /*!< PBCME (Bit 21) */ + #define R_MFWD_FWPBFC2_PBCME_Msk (0x200000UL) /*!< PBCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC2_PBSL_Pos (22UL) /*!< PBSL (Bit 22) */ + #define R_MFWD_FWPBFC2_PBSL_Msk (0x400000UL) /*!< PBSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC2_IP4PDE_Pos (23UL) /*!< IP4PDE (Bit 23) */ + #define R_MFWD_FWPBFC2_IP4PDE_Msk (0x800000UL) /*!< IP4PDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC2_IP4PDM_Pos (24UL) /*!< IP4PDM (Bit 24) */ + #define R_MFWD_FWPBFC2_IP4PDM_Msk (0x1000000UL) /*!< IP4PDM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC2_IP6PDE_Pos (25UL) /*!< IP6PDE (Bit 25) */ + #define R_MFWD_FWPBFC2_IP6PDE_Msk (0x2000000UL) /*!< IP6PDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC2_FAIFP_Pos (26UL) /*!< FAIFP (Bit 26) */ + #define R_MFWD_FWPBFC2_FAIFP_Msk (0x4000000UL) /*!< FAIFP (Bitfield-Mask: 0x01) */ +/* ====================================================== FWPBFCSDC00 ====================================================== */ + #define R_MFWD_FWPBFCSDC00_PBCSD_Pos (0UL) /*!< PBCSD (Bit 0) */ + #define R_MFWD_FWPBFCSDC00_PBCSD_Msk (0x7fUL) /*!< PBCSD (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWPBFCSDC01 ====================================================== */ + #define R_MFWD_FWPBFCSDC01_PBCSD_Pos (0UL) /*!< PBCSD (Bit 0) */ + #define R_MFWD_FWPBFCSDC01_PBCSD_Msk (0x7fUL) /*!< PBCSD (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWPBFCSDC02 ====================================================== */ + #define R_MFWD_FWPBFCSDC02_PBCSD_Pos (0UL) /*!< PBCSD (Bit 0) */ + #define R_MFWD_FWPBFCSDC02_PBCSD_Msk (0x7fUL) /*!< PBCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWL23URL0 ======================================================= */ + #define R_MFWD_FWL23URL0_L23URNL_Pos (0UL) /*!< L23URNL (Bit 0) */ + #define R_MFWD_FWL23URL0_L23URNL_Msk (0xffUL) /*!< L23URNL (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URL0_L23URPVL_Pos (16UL) /*!< L23URPVL (Bit 16) */ + #define R_MFWD_FWL23URL0_L23URPVL_Msk (0x7f0000UL) /*!< L23URPVL (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWL23URL1 ======================================================= */ + #define R_MFWD_FWL23URL1_L23UMDALP0_Pos (0UL) /*!< L23UMDALP0 (Bit 0) */ + #define R_MFWD_FWL23URL1_L23UMDALP0_Msk (0xffffUL) /*!< L23UMDALP0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWL23URL1_L23UTTLUL_Pos (16UL) /*!< L23UTTLUL (Bit 16) */ + #define R_MFWD_FWL23URL1_L23UTTLUL_Msk (0x10000UL) /*!< L23UTTLUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23UMDAUL_Pos (17UL) /*!< L23UMDAUL (Bit 17) */ + #define R_MFWD_FWL23URL1_L23UMDAUL_Msk (0x20000UL) /*!< L23UMDAUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23UMSAUL_Pos (18UL) /*!< L23UMSAUL (Bit 18) */ + #define R_MFWD_FWL23URL1_L23UMSAUL_Msk (0x40000UL) /*!< L23UMSAUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23UCVIDUL_Pos (19UL) /*!< L23UCVIDUL (Bit 19) */ + #define R_MFWD_FWL23URL1_L23UCVIDUL_Msk (0x80000UL) /*!< L23UCVIDUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23UCPCPUL_Pos (20UL) /*!< L23UCPCPUL (Bit 20) */ + #define R_MFWD_FWL23URL1_L23UCPCPUL_Msk (0x100000UL) /*!< L23UCPCPUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23UCDEIUL_Pos (21UL) /*!< L23UCDEIUL (Bit 21) */ + #define R_MFWD_FWL23URL1_L23UCDEIUL_Msk (0x200000UL) /*!< L23UCDEIUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23USVIDUL_Pos (22UL) /*!< L23USVIDUL (Bit 22) */ + #define R_MFWD_FWL23URL1_L23USVIDUL_Msk (0x400000UL) /*!< L23USVIDUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23USPCPUL_Pos (23UL) /*!< L23USPCPUL (Bit 23) */ + #define R_MFWD_FWL23URL1_L23USPCPUL_Msk (0x800000UL) /*!< L23USPCPUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23USDEIUL_Pos (24UL) /*!< L23USDEIUL (Bit 24) */ + #define R_MFWD_FWL23URL1_L23USDEIUL_Msk (0x1000000UL) /*!< L23USDEIUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23URTUL_Pos (25UL) /*!< L23URTUL (Bit 25) */ + #define R_MFWD_FWL23URL1_L23URTUL_Msk (0x6000000UL) /*!< L23URTUL (Bitfield-Mask: 0x03) */ +/* ======================================================= FWL23URL2 ======================================================= */ + #define R_MFWD_FWL23URL2_L23UMDALP1_Pos (0UL) /*!< L23UMDALP1 (Bit 0) */ + #define R_MFWD_FWL23URL2_L23UMDALP1_Msk (0xffffffffUL) /*!< L23UMDALP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWL23URL3 ======================================================= */ + #define R_MFWD_FWL23URL3_L23UCVIDL_Pos (0UL) /*!< L23UCVIDL (Bit 0) */ + #define R_MFWD_FWL23URL3_L23UCVIDL_Msk (0xfffUL) /*!< L23UCVIDL (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWL23URL3_L23UCPCPL_Pos (12UL) /*!< L23UCPCPL (Bit 12) */ + #define R_MFWD_FWL23URL3_L23UCPCPL_Msk (0x7000UL) /*!< L23UCPCPL (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URL3_L23UCDEIL_Pos (15UL) /*!< L23UCDEIL (Bit 15) */ + #define R_MFWD_FWL23URL3_L23UCDEIL_Msk (0x8000UL) /*!< L23UCDEIL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL3_L23USVIDL_Pos (16UL) /*!< L23USVIDL (Bit 16) */ + #define R_MFWD_FWL23URL3_L23USVIDL_Msk (0xfff0000UL) /*!< L23USVIDL (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWL23URL3_L23USPCPL_Pos (28UL) /*!< L23USPCPL (Bit 28) */ + #define R_MFWD_FWL23URL3_L23USPCPL_Msk (0x70000000UL) /*!< L23USPCPL (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URL3_L23USDEIL_Pos (31UL) /*!< L23USDEIL (Bit 31) */ + #define R_MFWD_FWL23URL3_L23USDEIL_Msk (0x80000000UL) /*!< L23USDEIL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWL23URLR ======================================================= */ + #define R_MFWD_FWL23URLR_L23ULF_Pos (0UL) /*!< L23ULF (Bit 0) */ + #define R_MFWD_FWL23URLR_L23ULF_Msk (0x1UL) /*!< L23ULF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URLR_L23URL_Pos (31UL) /*!< L23URL (Bit 31) */ + #define R_MFWD_FWL23URLR_L23URL_Msk (0x80000000UL) /*!< L23URL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWL23UTIM ======================================================= */ + #define R_MFWD_FWL23UTIM_L23UTIOG_Pos (0UL) /*!< L23UTIOG (Bit 0) */ + #define R_MFWD_FWL23UTIM_L23UTIOG_Msk (0x1UL) /*!< L23UTIOG (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23UTIM_L23UTR_Pos (1UL) /*!< L23UTR (Bit 1) */ + #define R_MFWD_FWL23UTIM_L23UTR_Msk (0x2UL) /*!< L23UTR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWL23URR ======================================================== */ + #define R_MFWD_FWL23URR_L23RNR_Pos (0UL) /*!< L23RNR (Bit 0) */ + #define R_MFWD_FWL23URR_L23RNR_Msk (0xffUL) /*!< L23RNR (Bitfield-Mask: 0xff) */ +/* ====================================================== FWL23URRR0 ======================================================= */ + #define R_MFWD_FWL23URRR0_L23URPVR_Pos (0UL) /*!< L23URPVR (Bit 0) */ + #define R_MFWD_FWL23URRR0_L23URPVR_Msk (0x7fUL) /*!< L23URPVR (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWL23URRR0_L23UREF_Pos (16UL) /*!< L23UREF (Bit 16) */ + #define R_MFWD_FWL23URRR0_L23UREF_Msk (0x10000UL) /*!< L23UREF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR0_L23URR_Pos (31UL) /*!< L23URR (Bit 31) */ + #define R_MFWD_FWL23URRR0_L23URR_Msk (0x80000000UL) /*!< L23URR (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URRR1 ======================================================= */ + #define R_MFWD_FWL23URRR1_L23UMDARP0_Pos (0UL) /*!< L23UMDARP0 (Bit 0) */ + #define R_MFWD_FWL23URRR1_L23UMDARP0_Msk (0xffffUL) /*!< L23UMDARP0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWL23URRR1_L23UTTLUR_Pos (16UL) /*!< L23UTTLUR (Bit 16) */ + #define R_MFWD_FWL23URRR1_L23UTTLUR_Msk (0x10000UL) /*!< L23UTTLUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23UMDAUR_Pos (17UL) /*!< L23UMDAUR (Bit 17) */ + #define R_MFWD_FWL23URRR1_L23UMDAUR_Msk (0x20000UL) /*!< L23UMDAUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23UMSAUR_Pos (18UL) /*!< L23UMSAUR (Bit 18) */ + #define R_MFWD_FWL23URRR1_L23UMSAUR_Msk (0x40000UL) /*!< L23UMSAUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23UCVIDUR_Pos (19UL) /*!< L23UCVIDUR (Bit 19) */ + #define R_MFWD_FWL23URRR1_L23UCVIDUR_Msk (0x80000UL) /*!< L23UCVIDUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23UCPCPUR_Pos (20UL) /*!< L23UCPCPUR (Bit 20) */ + #define R_MFWD_FWL23URRR1_L23UCPCPUR_Msk (0x100000UL) /*!< L23UCPCPUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23UCDEIUR_Pos (21UL) /*!< L23UCDEIUR (Bit 21) */ + #define R_MFWD_FWL23URRR1_L23UCDEIUR_Msk (0x200000UL) /*!< L23UCDEIUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23USVIDUR_Pos (22UL) /*!< L23USVIDUR (Bit 22) */ + #define R_MFWD_FWL23URRR1_L23USVIDUR_Msk (0x400000UL) /*!< L23USVIDUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23USPCPUR_Pos (23UL) /*!< L23USPCPUR (Bit 23) */ + #define R_MFWD_FWL23URRR1_L23USPCPUR_Msk (0x800000UL) /*!< L23USPCPUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23USDEIUR_Pos (24UL) /*!< L23USDEIUR (Bit 24) */ + #define R_MFWD_FWL23URRR1_L23USDEIUR_Msk (0x1000000UL) /*!< L23USDEIUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23URTUR_Pos (25UL) /*!< L23URTUR (Bit 25) */ + #define R_MFWD_FWL23URRR1_L23URTUR_Msk (0x6000000UL) /*!< L23URTUR (Bitfield-Mask: 0x03) */ +/* ====================================================== FWL23URRR2 ======================================================= */ + #define R_MFWD_FWL23URRR2_L23UMDARP1_Pos (0UL) /*!< L23UMDARP1 (Bit 0) */ + #define R_MFWD_FWL23URRR2_L23UMDARP1_Msk (0xffffffffUL) /*!< L23UMDARP1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWL23URRR3 ======================================================= */ + #define R_MFWD_FWL23URRR3_L23UCVIDR_Pos (0UL) /*!< L23UCVIDR (Bit 0) */ + #define R_MFWD_FWL23URRR3_L23UCVIDR_Msk (0xfffUL) /*!< L23UCVIDR (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWL23URRR3_L23UCPCPR_Pos (12UL) /*!< L23UCPCPR (Bit 12) */ + #define R_MFWD_FWL23URRR3_L23UCPCPR_Msk (0x7000UL) /*!< L23UCPCPR (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URRR3_L23UCDEIR_Pos (15UL) /*!< L23UCDEIR (Bit 15) */ + #define R_MFWD_FWL23URRR3_L23UCDEIR_Msk (0x8000UL) /*!< L23UCDEIR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR3_L23USVIDR_Pos (16UL) /*!< L23USVIDR (Bit 16) */ + #define R_MFWD_FWL23URRR3_L23USVIDR_Msk (0xfff0000UL) /*!< L23USVIDR (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWL23URRR3_L23USPCPR_Pos (28UL) /*!< L23USPCPR (Bit 28) */ + #define R_MFWD_FWL23URRR3_L23USPCPR_Msk (0x70000000UL) /*!< L23USPCPR (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URRR3_L23USDEIR_Pos (31UL) /*!< L23USDEIR (Bit 31) */ + #define R_MFWD_FWL23URRR3_L23USDEIR_Msk (0x80000000UL) /*!< L23USDEIR (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC0 ======================================================= */ + #define R_MFWD_FWL23URMC0_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC0_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC0_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC0_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC0_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC0_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC0_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC0_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC1 ======================================================= */ + #define R_MFWD_FWL23URMC1_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC1_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC1_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC1_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC1_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC1_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC1_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC1_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC2 ======================================================= */ + #define R_MFWD_FWL23URMC2_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC2_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC2_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC2_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC2_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC2_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC2_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC2_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC3 ======================================================= */ + #define R_MFWD_FWL23URMC3_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC3_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC3_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC3_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC3_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC3_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC3_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC3_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC4 ======================================================= */ + #define R_MFWD_FWL23URMC4_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC4_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC4_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC4_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC4_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC4_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC4_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC4_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC5 ======================================================= */ + #define R_MFWD_FWL23URMC5_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC5_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC5_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC5_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC5_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC5_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC5_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC5_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC6 ======================================================= */ + #define R_MFWD_FWL23URMC6_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC6_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC6_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC6_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC6_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC6_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC6_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC6_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC7 ======================================================= */ + #define R_MFWD_FWL23URMC7_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC7_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC7_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC7_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC7_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC7_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC7_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC7_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC8 ======================================================= */ + #define R_MFWD_FWL23URMC8_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC8_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC8_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC8_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC8_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC8_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC8_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC8_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC9 ======================================================= */ + #define R_MFWD_FWL23URMC9_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC9_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC9_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC9_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC9_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC9_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC9_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC9_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC10 ====================================================== */ + #define R_MFWD_FWL23URMC10_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC10_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC10_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC10_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC10_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC10_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC10_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC10_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC11 ====================================================== */ + #define R_MFWD_FWL23URMC11_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC11_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC11_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC11_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC11_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC11_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC11_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC11_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC12 ====================================================== */ + #define R_MFWD_FWL23URMC12_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC12_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC12_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC12_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC12_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC12_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC12_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC12_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC13 ====================================================== */ + #define R_MFWD_FWL23URMC13_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC13_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC13_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC13_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC13_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC13_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC13_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC13_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC14 ====================================================== */ + #define R_MFWD_FWL23URMC14_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC14_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC14_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC14_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC14_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC14_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC14_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC14_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC15 ====================================================== */ + #define R_MFWD_FWL23URMC15_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC15_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC15_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC15_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC15_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC15_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC15_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC15_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC16 ====================================================== */ + #define R_MFWD_FWL23URMC16_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC16_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC16_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC16_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC16_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC16_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC16_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC16_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC17 ====================================================== */ + #define R_MFWD_FWL23URMC17_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC17_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC17_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC17_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC17_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC17_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC17_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC17_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC18 ====================================================== */ + #define R_MFWD_FWL23URMC18_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC18_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC18_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC18_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC18_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC18_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC18_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC18_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC19 ====================================================== */ + #define R_MFWD_FWL23URMC19_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC19_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC19_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC19_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC19_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC19_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC19_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC19_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC20 ====================================================== */ + #define R_MFWD_FWL23URMC20_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC20_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC20_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC20_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC20_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC20_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC20_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC20_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC21 ====================================================== */ + #define R_MFWD_FWL23URMC21_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC21_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC21_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC21_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC21_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC21_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC21_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC21_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC22 ====================================================== */ + #define R_MFWD_FWL23URMC22_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC22_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC22_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC22_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC22_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC22_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC22_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC22_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC23 ====================================================== */ + #define R_MFWD_FWL23URMC23_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC23_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC23_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC23_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC23_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC23_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC23_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC23_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC24 ====================================================== */ + #define R_MFWD_FWL23URMC24_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC24_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC24_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC24_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC24_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC24_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC24_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC24_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC25 ====================================================== */ + #define R_MFWD_FWL23URMC25_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC25_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC25_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC25_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC25_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC25_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC25_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC25_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC26 ====================================================== */ + #define R_MFWD_FWL23URMC26_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC26_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC26_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC26_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC26_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC26_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC26_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC26_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC27 ====================================================== */ + #define R_MFWD_FWL23URMC27_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC27_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC27_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC27_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC27_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC27_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC27_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC27_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC28 ====================================================== */ + #define R_MFWD_FWL23URMC28_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC28_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC28_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC28_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC28_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC28_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC28_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC28_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC29 ====================================================== */ + #define R_MFWD_FWL23URMC29_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC29_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC29_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC29_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC29_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC29_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC29_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC29_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC30 ====================================================== */ + #define R_MFWD_FWL23URMC30_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC30_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC30_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC30_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC30_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC30_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC30_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC30_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC31 ====================================================== */ + #define R_MFWD_FWL23URMC31_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC31_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC31_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC31_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC31_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC31_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC31_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC31_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC0 ======================================================== */ + #define R_MFWD_FWPMFGC0_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC0_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC0_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC0_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC1 ======================================================== */ + #define R_MFWD_FWPMFGC1_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC1_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC1_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC1_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC2 ======================================================== */ + #define R_MFWD_FWPMFGC2_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC2_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC2_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC2_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC3 ======================================================== */ + #define R_MFWD_FWPMFGC3_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC3_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC3_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC3_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC4 ======================================================== */ + #define R_MFWD_FWPMFGC4_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC4_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC4_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC4_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC5 ======================================================== */ + #define R_MFWD_FWPMFGC5_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC5_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC5_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC5_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC6 ======================================================== */ + #define R_MFWD_FWPMFGC6_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC6_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC6_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC6_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC7 ======================================================== */ + #define R_MFWD_FWPMFGC7_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC7_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC7_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC7_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC8 ======================================================== */ + #define R_MFWD_FWPMFGC8_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC8_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC8_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC8_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC9 ======================================================== */ + #define R_MFWD_FWPMFGC9_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC9_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC9_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC9_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC10 ======================================================= */ + #define R_MFWD_FWPMFGC10_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC10_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC10_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC10_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC11 ======================================================= */ + #define R_MFWD_FWPMFGC11_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC11_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC11_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC11_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC12 ======================================================= */ + #define R_MFWD_FWPMFGC12_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC12_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC12_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC12_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC13 ======================================================= */ + #define R_MFWD_FWPMFGC13_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC13_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC13_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC13_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC14 ======================================================= */ + #define R_MFWD_FWPMFGC14_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC14_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC14_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC14_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC15 ======================================================= */ + #define R_MFWD_FWPMFGC15_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC15_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC15_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC15_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMTRFC0 ======================================================= */ + #define R_MFWD_FWPMTRFC0_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC0_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC0_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC0_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC0_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC0_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC0_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC0_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC0_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC0_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC1 ======================================================= */ + #define R_MFWD_FWPMTRFC1_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC1_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC1_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC1_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC1_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC1_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC1_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC1_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC1_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC1_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC2 ======================================================= */ + #define R_MFWD_FWPMTRFC2_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC2_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC2_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC2_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC2_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC2_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC2_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC2_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC2_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC2_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC3 ======================================================= */ + #define R_MFWD_FWPMTRFC3_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC3_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC3_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC3_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC3_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC3_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC3_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC3_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC3_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC3_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC4 ======================================================= */ + #define R_MFWD_FWPMTRFC4_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC4_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC4_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC4_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC4_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC4_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC4_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC4_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC4_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC4_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC5 ======================================================= */ + #define R_MFWD_FWPMTRFC5_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC5_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC5_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC5_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC5_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC5_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC5_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC5_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC5_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC5_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC6 ======================================================= */ + #define R_MFWD_FWPMTRFC6_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC6_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC6_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC6_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC6_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC6_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC6_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC6_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC6_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC6_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC7 ======================================================= */ + #define R_MFWD_FWPMTRFC7_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC7_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC7_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC7_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC7_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC7_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC7_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC7_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC7_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC7_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC8 ======================================================= */ + #define R_MFWD_FWPMTRFC8_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC8_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC8_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC8_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC8_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC8_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC8_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC8_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC8_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC8_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC9 ======================================================= */ + #define R_MFWD_FWPMTRFC9_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC9_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC9_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC9_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC9_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC9_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC9_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC9_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC9_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC9_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC10 ======================================================= */ + #define R_MFWD_FWPMTRFC10_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC10_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC10_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC10_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC10_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC10_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC10_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC10_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC10_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC10_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC11 ======================================================= */ + #define R_MFWD_FWPMTRFC11_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC11_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC11_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC11_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC11_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC11_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC11_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC11_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC11_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC11_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC12 ======================================================= */ + #define R_MFWD_FWPMTRFC12_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC12_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC12_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC12_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC12_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC12_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC12_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC12_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC12_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC12_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC13 ======================================================= */ + #define R_MFWD_FWPMTRFC13_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC13_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC13_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC13_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC13_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC13_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC13_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC13_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC13_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC13_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC14 ======================================================= */ + #define R_MFWD_FWPMTRFC14_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC14_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC14_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC14_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC14_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC14_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC14_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC14_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC14_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC14_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC15 ======================================================= */ + #define R_MFWD_FWPMTRFC15_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC15_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC15_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC15_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC15_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC15_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC15_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC15_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC15_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC15_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC16 ======================================================= */ + #define R_MFWD_FWPMTRFC16_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC16_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC16_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC16_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC16_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC16_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC16_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC16_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC16_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC16_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC17 ======================================================= */ + #define R_MFWD_FWPMTRFC17_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC17_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC17_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC17_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC17_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC17_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC17_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC17_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC17_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC17_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC18 ======================================================= */ + #define R_MFWD_FWPMTRFC18_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC18_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC18_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC18_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC18_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC18_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC18_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC18_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC18_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC18_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC19 ======================================================= */ + #define R_MFWD_FWPMTRFC19_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC19_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC19_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC19_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC19_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC19_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC19_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC19_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC19_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC19_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC20 ======================================================= */ + #define R_MFWD_FWPMTRFC20_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC20_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC20_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC20_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC20_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC20_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC20_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC20_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC20_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC20_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC21 ======================================================= */ + #define R_MFWD_FWPMTRFC21_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC21_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC21_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC21_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC21_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC21_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC21_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC21_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC21_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC21_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC22 ======================================================= */ + #define R_MFWD_FWPMTRFC22_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC22_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC22_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC22_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC22_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC22_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC22_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC22_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC22_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC22_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC23 ======================================================= */ + #define R_MFWD_FWPMTRFC23_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC23_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC23_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC23_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC23_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC23_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC23_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC23_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC23_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC23_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC24 ======================================================= */ + #define R_MFWD_FWPMTRFC24_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC24_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC24_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC24_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC24_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC24_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC24_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC24_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC24_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC24_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC25 ======================================================= */ + #define R_MFWD_FWPMTRFC25_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC25_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC25_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC25_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC25_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC25_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC25_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC25_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC25_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC25_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC26 ======================================================= */ + #define R_MFWD_FWPMTRFC26_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC26_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC26_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC26_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC26_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC26_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC26_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC26_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC26_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC26_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC27 ======================================================= */ + #define R_MFWD_FWPMTRFC27_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC27_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC27_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC27_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC27_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC27_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC27_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC27_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC27_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC27_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC28 ======================================================= */ + #define R_MFWD_FWPMTRFC28_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC28_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC28_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC28_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC28_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC28_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC28_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC28_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC28_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC28_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC29 ======================================================= */ + #define R_MFWD_FWPMTRFC29_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC29_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC29_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC29_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC29_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC29_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC29_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC29_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC29_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC29_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC30 ======================================================= */ + #define R_MFWD_FWPMTRFC30_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC30_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC30_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC30_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC30_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC30_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC30_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC30_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC30_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC30_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC31 ======================================================= */ + #define R_MFWD_FWPMTRFC31_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC31_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC31_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC31_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC31_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC31_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC31_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC31_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC31_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC31_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRCBSC0 ====================================================== */ + #define R_MFWD_FWPMTRCBSC0_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC0_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC1 ====================================================== */ + #define R_MFWD_FWPMTRCBSC1_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC1_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC2 ====================================================== */ + #define R_MFWD_FWPMTRCBSC2_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC2_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC3 ====================================================== */ + #define R_MFWD_FWPMTRCBSC3_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC3_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC4 ====================================================== */ + #define R_MFWD_FWPMTRCBSC4_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC4_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC5 ====================================================== */ + #define R_MFWD_FWPMTRCBSC5_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC5_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC6 ====================================================== */ + #define R_MFWD_FWPMTRCBSC6_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC6_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC7 ====================================================== */ + #define R_MFWD_FWPMTRCBSC7_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC7_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC8 ====================================================== */ + #define R_MFWD_FWPMTRCBSC8_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC8_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC9 ====================================================== */ + #define R_MFWD_FWPMTRCBSC9_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC9_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC10 ====================================================== */ + #define R_MFWD_FWPMTRCBSC10_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC10_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC11 ====================================================== */ + #define R_MFWD_FWPMTRCBSC11_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC11_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC12 ====================================================== */ + #define R_MFWD_FWPMTRCBSC12_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC12_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC13 ====================================================== */ + #define R_MFWD_FWPMTRCBSC13_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC13_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC14 ====================================================== */ + #define R_MFWD_FWPMTRCBSC14_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC14_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC15 ====================================================== */ + #define R_MFWD_FWPMTRCBSC15_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC15_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC16 ====================================================== */ + #define R_MFWD_FWPMTRCBSC16_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC16_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC17 ====================================================== */ + #define R_MFWD_FWPMTRCBSC17_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC17_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC18 ====================================================== */ + #define R_MFWD_FWPMTRCBSC18_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC18_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC19 ====================================================== */ + #define R_MFWD_FWPMTRCBSC19_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC19_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC20 ====================================================== */ + #define R_MFWD_FWPMTRCBSC20_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC20_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC21 ====================================================== */ + #define R_MFWD_FWPMTRCBSC21_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC21_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC22 ====================================================== */ + #define R_MFWD_FWPMTRCBSC22_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC22_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC23 ====================================================== */ + #define R_MFWD_FWPMTRCBSC23_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC23_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC24 ====================================================== */ + #define R_MFWD_FWPMTRCBSC24_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC24_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC25 ====================================================== */ + #define R_MFWD_FWPMTRCBSC25_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC25_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC26 ====================================================== */ + #define R_MFWD_FWPMTRCBSC26_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC26_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC27 ====================================================== */ + #define R_MFWD_FWPMTRCBSC27_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC27_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC28 ====================================================== */ + #define R_MFWD_FWPMTRCBSC28_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC28_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC29 ====================================================== */ + #define R_MFWD_FWPMTRCBSC29_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC29_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC30 ====================================================== */ + #define R_MFWD_FWPMTRCBSC30_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC30_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC31 ====================================================== */ + #define R_MFWD_FWPMTRCBSC31_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC31_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCIRC0 ====================================================== */ + #define R_MFWD_FWPMTRCIRC0_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC0_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC1 ====================================================== */ + #define R_MFWD_FWPMTRCIRC1_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC1_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC2 ====================================================== */ + #define R_MFWD_FWPMTRCIRC2_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC2_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC3 ====================================================== */ + #define R_MFWD_FWPMTRCIRC3_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC3_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC4 ====================================================== */ + #define R_MFWD_FWPMTRCIRC4_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC4_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC5 ====================================================== */ + #define R_MFWD_FWPMTRCIRC5_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC5_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC6 ====================================================== */ + #define R_MFWD_FWPMTRCIRC6_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC6_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC7 ====================================================== */ + #define R_MFWD_FWPMTRCIRC7_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC7_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC8 ====================================================== */ + #define R_MFWD_FWPMTRCIRC8_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC8_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC9 ====================================================== */ + #define R_MFWD_FWPMTRCIRC9_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC9_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC10 ====================================================== */ + #define R_MFWD_FWPMTRCIRC10_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC10_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC11 ====================================================== */ + #define R_MFWD_FWPMTRCIRC11_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC11_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC12 ====================================================== */ + #define R_MFWD_FWPMTRCIRC12_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC12_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC13 ====================================================== */ + #define R_MFWD_FWPMTRCIRC13_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC13_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC14 ====================================================== */ + #define R_MFWD_FWPMTRCIRC14_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC14_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC15 ====================================================== */ + #define R_MFWD_FWPMTRCIRC15_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC15_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC16 ====================================================== */ + #define R_MFWD_FWPMTRCIRC16_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC16_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC17 ====================================================== */ + #define R_MFWD_FWPMTRCIRC17_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC17_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC18 ====================================================== */ + #define R_MFWD_FWPMTRCIRC18_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC18_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC19 ====================================================== */ + #define R_MFWD_FWPMTRCIRC19_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC19_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC20 ====================================================== */ + #define R_MFWD_FWPMTRCIRC20_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC20_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC21 ====================================================== */ + #define R_MFWD_FWPMTRCIRC21_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC21_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC22 ====================================================== */ + #define R_MFWD_FWPMTRCIRC22_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC22_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC23 ====================================================== */ + #define R_MFWD_FWPMTRCIRC23_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC23_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC24 ====================================================== */ + #define R_MFWD_FWPMTRCIRC24_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC24_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC25 ====================================================== */ + #define R_MFWD_FWPMTRCIRC25_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC25_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC26 ====================================================== */ + #define R_MFWD_FWPMTRCIRC26_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC26_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC27 ====================================================== */ + #define R_MFWD_FWPMTRCIRC27_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC27_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC28 ====================================================== */ + #define R_MFWD_FWPMTRCIRC28_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC28_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC29 ====================================================== */ + #define R_MFWD_FWPMTRCIRC29_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC29_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC30 ====================================================== */ + #define R_MFWD_FWPMTRCIRC30_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC30_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC31 ====================================================== */ + #define R_MFWD_FWPMTRCIRC31_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC31_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREBSC0 ====================================================== */ + #define R_MFWD_FWPMTREBSC0_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC0_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREBSC1 ====================================================== */ + #define R_MFWD_FWPMTREBSC1_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC1_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREBSC2 ====================================================== */ + #define R_MFWD_FWPMTREBSC2_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC2_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREBSC3 ====================================================== */ + #define R_MFWD_FWPMTREBSC3_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC3_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREBSC4 ====================================================== */ + #define R_MFWD_FWPMTREBSC4_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC4_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREBSC5 ====================================================== */ + #define R_MFWD_FWPMTREBSC5_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC5_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREBSC6 ====================================================== */ + #define R_MFWD_FWPMTREBSC6_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC6_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREBSC7 ====================================================== */ + #define R_MFWD_FWPMTREBSC7_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC7_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREIRC0 ====================================================== */ + #define R_MFWD_FWPMTREIRC0_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC0_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREIRC1 ====================================================== */ + #define R_MFWD_FWPMTREIRC1_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC1_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREIRC2 ====================================================== */ + #define R_MFWD_FWPMTREIRC2_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC2_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREIRC3 ====================================================== */ + #define R_MFWD_FWPMTREIRC3_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC3_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREIRC4 ====================================================== */ + #define R_MFWD_FWPMTREIRC4_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC4_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREIRC5 ====================================================== */ + #define R_MFWD_FWPMTREIRC5_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC5_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREIRC6 ====================================================== */ + #define R_MFWD_FWPMTREIRC6_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC6_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREIRC7 ====================================================== */ + #define R_MFWD_FWPMTREIRC7_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC7_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ======================================================= FWPMTRFM0 ======================================================= */ + #define R_MFWD_FWPMTRFM0_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM0_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM0_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM0_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM1 ======================================================= */ + #define R_MFWD_FWPMTRFM1_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM1_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM1_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM1_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM2 ======================================================= */ + #define R_MFWD_FWPMTRFM2_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM2_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM2_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM2_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM3 ======================================================= */ + #define R_MFWD_FWPMTRFM3_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM3_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM3_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM3_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM4 ======================================================= */ + #define R_MFWD_FWPMTRFM4_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM4_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM4_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM4_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM5 ======================================================= */ + #define R_MFWD_FWPMTRFM5_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM5_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM5_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM5_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM6 ======================================================= */ + #define R_MFWD_FWPMTRFM6_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM6_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM6_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM6_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM7 ======================================================= */ + #define R_MFWD_FWPMTRFM7_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM7_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM7_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM7_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM8 ======================================================= */ + #define R_MFWD_FWPMTRFM8_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM8_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM8_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM8_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM9 ======================================================= */ + #define R_MFWD_FWPMTRFM9_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM9_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM9_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM9_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM10 ======================================================= */ + #define R_MFWD_FWPMTRFM10_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM10_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM10_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM10_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM11 ======================================================= */ + #define R_MFWD_FWPMTRFM11_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM11_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM11_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM11_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM12 ======================================================= */ + #define R_MFWD_FWPMTRFM12_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM12_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM12_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM12_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM13 ======================================================= */ + #define R_MFWD_FWPMTRFM13_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM13_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM13_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM13_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM14 ======================================================= */ + #define R_MFWD_FWPMTRFM14_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM14_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM14_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM14_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM15 ======================================================= */ + #define R_MFWD_FWPMTRFM15_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM15_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM15_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM15_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM16 ======================================================= */ + #define R_MFWD_FWPMTRFM16_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM16_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM16_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM16_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM17 ======================================================= */ + #define R_MFWD_FWPMTRFM17_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM17_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM17_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM17_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM18 ======================================================= */ + #define R_MFWD_FWPMTRFM18_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM18_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM18_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM18_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM19 ======================================================= */ + #define R_MFWD_FWPMTRFM19_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM19_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM19_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM19_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM20 ======================================================= */ + #define R_MFWD_FWPMTRFM20_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM20_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM20_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM20_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM21 ======================================================= */ + #define R_MFWD_FWPMTRFM21_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM21_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM21_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM21_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM22 ======================================================= */ + #define R_MFWD_FWPMTRFM22_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM22_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM22_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM22_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM23 ======================================================= */ + #define R_MFWD_FWPMTRFM23_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM23_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM23_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM23_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM24 ======================================================= */ + #define R_MFWD_FWPMTRFM24_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM24_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM24_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM24_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM25 ======================================================= */ + #define R_MFWD_FWPMTRFM25_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM25_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM25_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM25_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM26 ======================================================= */ + #define R_MFWD_FWPMTRFM26_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM26_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM26_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM26_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM27 ======================================================= */ + #define R_MFWD_FWPMTRFM27_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM27_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM27_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM27_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM28 ======================================================= */ + #define R_MFWD_FWPMTRFM28_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM28_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM28_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM28_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM29 ======================================================= */ + #define R_MFWD_FWPMTRFM29_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM29_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM29_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM29_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM30 ======================================================= */ + #define R_MFWD_FWPMTRFM30_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM30_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM30_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM30_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM31 ======================================================= */ + #define R_MFWD_FWPMTRFM31_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM31_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM31_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM31_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================== FWFTL0 ========================================================= */ + #define R_MFWD_FWFTL0_FEAL_Pos (0UL) /*!< FEAL (Bit 0) */ + #define R_MFWD_FWFTL0_FEAL_Msk (0x7fUL) /*!< FEAL (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWFTL0_FSRPL_Pos (16UL) /*!< FSRPL (Bit 16) */ + #define R_MFWD_FWFTL0_FSRPL_Msk (0x7f0000UL) /*!< FSRPL (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWFTL1 ========================================================= */ + #define R_MFWD_FWFTL1_FSHLL_Pos (0UL) /*!< FSHLL (Bit 0) */ + #define R_MFWD_FWFTL1_FSHLL_Msk (0xfUL) /*!< FSHLL (Bitfield-Mask: 0x0f) */ + #define R_MFWD_FWFTL1_FTNSL_Pos (8UL) /*!< FTNSL (Bit 8) */ + #define R_MFWD_FWFTL1_FTNSL_Msk (0x100UL) /*!< FTNSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTL1_FSRPVL_Pos (9UL) /*!< FSRPVL (Bit 9) */ + #define R_MFWD_FWFTL1_FSRPVL_Msk (0x200UL) /*!< FSRPVL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTL1_FSRRTL_Pos (16UL) /*!< FSRRTL (Bit 16) */ + #define R_MFWD_FWFTL1_FSRRTL_Msk (0x3ff0000UL) /*!< FSRRTL (Bitfield-Mask: 0x3ff) */ +/* ======================================================== FWFTLR ========================================================= */ + #define R_MFWD_FWFTLR_FLF_Pos (0UL) /*!< FLF (Bit 0) */ + #define R_MFWD_FWFTLR_FLF_Msk (0x1UL) /*!< FLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTLR_FTL_Pos (31UL) /*!< FTL (Bit 31) */ + #define R_MFWD_FWFTLR_FTL_Msk (0x80000000UL) /*!< FTL (Bitfield-Mask: 0x01) */ +/* ======================================================== FWFTOC ========================================================= */ + #define R_MFWD_FWFTOC_TOT_Pos (0UL) /*!< TOT (Bit 0) */ + #define R_MFWD_FWFTOC_TOT_Msk (0xffffUL) /*!< TOT (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWFTOC_TOCE_Pos (16UL) /*!< TOCE (Bit 16) */ + #define R_MFWD_FWFTOC_TOCE_Msk (0x10000UL) /*!< TOCE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTOC_TOOG_Pos (17UL) /*!< TOOG (Bit 17) */ + #define R_MFWD_FWFTOC_TOOG_Msk (0x20000UL) /*!< TOOG (Bitfield-Mask: 0x01) */ +/* ======================================================== FWFTOPC ======================================================== */ + #define R_MFWD_FWFTOPC_USP_Pos (0UL) /*!< USP (Bit 0) */ + #define R_MFWD_FWFTOPC_USP_Msk (0x3ffUL) /*!< USP (Bitfield-Mask: 0x3ff) */ +/* ======================================================== FWFTIM ========================================================= */ + #define R_MFWD_FWFTIM_FTIOG_Pos (0UL) /*!< FTIOG (Bit 0) */ + #define R_MFWD_FWFTIM_FTIOG_Msk (0x1UL) /*!< FTIOG (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTIM_FTR_Pos (1UL) /*!< FTR (Bit 1) */ + #define R_MFWD_FWFTIM_FTR_Msk (0x2UL) /*!< FTR (Bitfield-Mask: 0x01) */ +/* ========================================================= FWFTR ========================================================= */ + #define R_MFWD_FWFTR_FEAR_Pos (0UL) /*!< FEAR (Bit 0) */ + #define R_MFWD_FWFTR_FEAR_Msk (0x7fUL) /*!< FEAR (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWFTRR0 ======================================================== */ + #define R_MFWD_FWFTRR0_FSHLR_Pos (0UL) /*!< FSHLR (Bit 0) */ + #define R_MFWD_FWFTRR0_FSHLR_Msk (0xfUL) /*!< FSHLR (Bitfield-Mask: 0x0f) */ + #define R_MFWD_FWFTRR0_FTNSR_Pos (8UL) /*!< FTNSR (Bit 8) */ + #define R_MFWD_FWFTRR0_FTNSR_Msk (0x100UL) /*!< FTNSR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTRR0_FSRPVR_Pos (9UL) /*!< FSRPVR (Bit 9) */ + #define R_MFWD_FWFTRR0_FSRPVR_Msk (0x200UL) /*!< FSRPVR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTRR0_FSRRTR_Pos (16UL) /*!< FSRRTR (Bit 16) */ + #define R_MFWD_FWFTRR0_FSRRTR_Msk (0x3ff0000UL) /*!< FSRRTR (Bitfield-Mask: 0x3ff) */ + #define R_MFWD_FWFTRR0_FTREF_Pos (30UL) /*!< FTREF (Bit 30) */ + #define R_MFWD_FWFTRR0_FTREF_Msk (0x40000000UL) /*!< FTREF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTRR0_FTR_Pos (31UL) /*!< FTR (Bit 31) */ + #define R_MFWD_FWFTRR0_FTR_Msk (0x80000000UL) /*!< FTR (Bitfield-Mask: 0x01) */ +/* ======================================================== FWFTRR1 ======================================================== */ + #define R_MFWD_FWFTRR1_FSHR_Pos (0UL) /*!< FSHR (Bit 0) */ + #define R_MFWD_FWFTRR1_FSHR_Msk (0x7fffUL) /*!< FSHR (Bitfield-Mask: 0x7fff) */ + #define R_MFWD_FWFTRR1_FSRPR_Pos (16UL) /*!< FSRPR (Bit 16) */ + #define R_MFWD_FWFTRR1_FSRPR_Msk (0x7f0000UL) /*!< FSRPR (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWFTRR2 ======================================================== */ + #define R_MFWD_FWFTRR2_FRSNR_Pos (0UL) /*!< FRSNR (Bit 0) */ + #define R_MFWD_FWFTRR2_FRSNR_Msk (0xffffUL) /*!< FRSNR (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWFTRR2_FRRTR_Pos (16UL) /*!< FRRTR (Bit 16) */ + #define R_MFWD_FWFTRR2_FRRTR_Msk (0x3ff0000UL) /*!< FRRTR (Bitfield-Mask: 0x3ff) */ +/* ======================================================= FWSEQNGC0 ======================================================= */ + #define R_MFWD_FWSEQNGC0_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC0_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC0_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC0_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC1 ======================================================= */ + #define R_MFWD_FWSEQNGC1_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC1_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC1_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC1_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC2 ======================================================= */ + #define R_MFWD_FWSEQNGC2_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC2_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC2_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC2_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC3 ======================================================= */ + #define R_MFWD_FWSEQNGC3_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC3_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC3_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC3_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC4 ======================================================= */ + #define R_MFWD_FWSEQNGC4_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC4_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC4_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC4_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC5 ======================================================= */ + #define R_MFWD_FWSEQNGC5_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC5_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC5_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC5_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC6 ======================================================= */ + #define R_MFWD_FWSEQNGC6_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC6_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC6_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC6_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC7 ======================================================= */ + #define R_MFWD_FWSEQNGC7_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC7_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC7_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC7_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC8 ======================================================= */ + #define R_MFWD_FWSEQNGC8_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC8_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC8_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC8_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC9 ======================================================= */ + #define R_MFWD_FWSEQNGC9_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC9_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC9_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC9_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC10 ======================================================= */ + #define R_MFWD_FWSEQNGC10_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC10_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC10_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC10_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC11 ======================================================= */ + #define R_MFWD_FWSEQNGC11_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC11_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC11_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC11_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC12 ======================================================= */ + #define R_MFWD_FWSEQNGC12_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC12_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC12_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC12_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC13 ======================================================= */ + #define R_MFWD_FWSEQNGC13_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC13_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC13_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC13_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC14 ======================================================= */ + #define R_MFWD_FWSEQNGC14_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC14_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC14_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC14_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC15 ======================================================= */ + #define R_MFWD_FWSEQNGC15_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC15_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC15_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC15_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC16 ======================================================= */ + #define R_MFWD_FWSEQNGC16_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC16_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC16_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC16_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC17 ======================================================= */ + #define R_MFWD_FWSEQNGC17_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC17_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC17_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC17_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC18 ======================================================= */ + #define R_MFWD_FWSEQNGC18_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC18_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC18_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC18_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC19 ======================================================= */ + #define R_MFWD_FWSEQNGC19_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC19_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC19_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC19_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC20 ======================================================= */ + #define R_MFWD_FWSEQNGC20_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC20_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC20_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC20_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC21 ======================================================= */ + #define R_MFWD_FWSEQNGC21_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC21_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC21_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC21_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC22 ======================================================= */ + #define R_MFWD_FWSEQNGC22_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC22_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC22_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC22_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC23 ======================================================= */ + #define R_MFWD_FWSEQNGC23_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC23_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC23_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC23_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC24 ======================================================= */ + #define R_MFWD_FWSEQNGC24_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC24_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC24_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC24_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC25 ======================================================= */ + #define R_MFWD_FWSEQNGC25_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC25_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC25_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC25_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC26 ======================================================= */ + #define R_MFWD_FWSEQNGC26_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC26_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC26_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC26_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC27 ======================================================= */ + #define R_MFWD_FWSEQNGC27_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC27_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC27_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC27_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC28 ======================================================= */ + #define R_MFWD_FWSEQNGC28_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC28_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC28_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC28_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC29 ======================================================= */ + #define R_MFWD_FWSEQNGC29_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC29_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC29_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC29_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC30 ======================================================= */ + #define R_MFWD_FWSEQNGC30_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC30_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC30_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC30_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC31 ======================================================= */ + #define R_MFWD_FWSEQNGC31_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC31_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC31_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC31_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGM0 ======================================================= */ + #define R_MFWD_FWSEQNGM0_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM0_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM1 ======================================================= */ + #define R_MFWD_FWSEQNGM1_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM1_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM2 ======================================================= */ + #define R_MFWD_FWSEQNGM2_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM2_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM3 ======================================================= */ + #define R_MFWD_FWSEQNGM3_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM3_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM4 ======================================================= */ + #define R_MFWD_FWSEQNGM4_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM4_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM5 ======================================================= */ + #define R_MFWD_FWSEQNGM5_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM5_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM6 ======================================================= */ + #define R_MFWD_FWSEQNGM6_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM6_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM7 ======================================================= */ + #define R_MFWD_FWSEQNGM7_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM7_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM8 ======================================================= */ + #define R_MFWD_FWSEQNGM8_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM8_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM9 ======================================================= */ + #define R_MFWD_FWSEQNGM9_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM9_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM10 ======================================================= */ + #define R_MFWD_FWSEQNGM10_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM10_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM11 ======================================================= */ + #define R_MFWD_FWSEQNGM11_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM11_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM12 ======================================================= */ + #define R_MFWD_FWSEQNGM12_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM12_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM13 ======================================================= */ + #define R_MFWD_FWSEQNGM13_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM13_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM14 ======================================================= */ + #define R_MFWD_FWSEQNGM14_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM14_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM15 ======================================================= */ + #define R_MFWD_FWSEQNGM15_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM15_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM16 ======================================================= */ + #define R_MFWD_FWSEQNGM16_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM16_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM17 ======================================================= */ + #define R_MFWD_FWSEQNGM17_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM17_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM18 ======================================================= */ + #define R_MFWD_FWSEQNGM18_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM18_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM19 ======================================================= */ + #define R_MFWD_FWSEQNGM19_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM19_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM20 ======================================================= */ + #define R_MFWD_FWSEQNGM20_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM20_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM21 ======================================================= */ + #define R_MFWD_FWSEQNGM21_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM21_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM22 ======================================================= */ + #define R_MFWD_FWSEQNGM22_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM22_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM23 ======================================================= */ + #define R_MFWD_FWSEQNGM23_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM23_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM24 ======================================================= */ + #define R_MFWD_FWSEQNGM24_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM24_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM25 ======================================================= */ + #define R_MFWD_FWSEQNGM25_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM25_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM26 ======================================================= */ + #define R_MFWD_FWSEQNGM26_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM26_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM27 ======================================================= */ + #define R_MFWD_FWSEQNGM27_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM27_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM28 ======================================================= */ + #define R_MFWD_FWSEQNGM28_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM28_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM29 ======================================================= */ + #define R_MFWD_FWSEQNGM29_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM29_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM30 ======================================================= */ + #define R_MFWD_FWSEQNGM30_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM30_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM31 ======================================================= */ + #define R_MFWD_FWSEQNGM31_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM31_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNRC ======================================================== */ + #define R_MFWD_FWSEQNRC_SEQNR_Pos (0UL) /*!< SEQNR (Bit 0) */ + #define R_MFWD_FWSEQNRC_SEQNR_Msk (0xffffffffUL) /*!< SEQNR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTFDCN0 ======================================================= */ + #define R_MFWD_FWCTFDCN0_CTFDN_Pos (0UL) /*!< CTFDN (Bit 0) */ + #define R_MFWD_FWCTFDCN0_CTFDN_Msk (0xffffffffUL) /*!< CTFDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTFDCN1 ======================================================= */ + #define R_MFWD_FWCTFDCN1_CTFDN_Pos (0UL) /*!< CTFDN (Bit 0) */ + #define R_MFWD_FWCTFDCN1_CTFDN_Msk (0xffffffffUL) /*!< CTFDN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWLTHFDCN0 ======================================================= */ + #define R_MFWD_FWLTHFDCN0_LTHFDN_Pos (0UL) /*!< LTHFDN (Bit 0) */ + #define R_MFWD_FWLTHFDCN0_LTHFDN_Msk (0xffffffffUL) /*!< LTHFDN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWLTHFDCN1 ======================================================= */ + #define R_MFWD_FWLTHFDCN1_LTHFDN_Pos (0UL) /*!< LTHFDN (Bit 0) */ + #define R_MFWD_FWLTHFDCN1_LTHFDN_Msk (0xffffffffUL) /*!< LTHFDN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWLTHFDCN2 ======================================================= */ + #define R_MFWD_FWLTHFDCN2_LTHFDN_Pos (0UL) /*!< LTHFDN (Bit 0) */ + #define R_MFWD_FWLTHFDCN2_LTHFDN_Msk (0xffffffffUL) /*!< LTHFDN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWLTWFDCN0 ======================================================= */ + #define R_MFWD_FWLTWFDCN0_LTWFDN_Pos (0UL) /*!< LTWFDN (Bit 0) */ + #define R_MFWD_FWLTWFDCN0_LTWFDN_Msk (0xffffffffUL) /*!< LTWFDN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWLTWFDCN1 ======================================================= */ + #define R_MFWD_FWLTWFDCN1_LTWFDN_Pos (0UL) /*!< LTWFDN (Bit 0) */ + #define R_MFWD_FWLTWFDCN1_LTWFDN_Msk (0xffffffffUL) /*!< LTWFDN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWLTWFDCN2 ======================================================= */ + #define R_MFWD_FWLTWFDCN2_LTWFDN_Pos (0UL) /*!< LTWFDN (Bit 0) */ + #define R_MFWD_FWLTWFDCN2_LTWFDN_Msk (0xffffffffUL) /*!< LTWFDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWPBFDCN0 ======================================================= */ + #define R_MFWD_FWPBFDCN0_PBFDN_Pos (0UL) /*!< PBFDN (Bit 0) */ + #define R_MFWD_FWPBFDCN0_PBFDN_Msk (0xffffffffUL) /*!< PBFDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWPBFDCN1 ======================================================= */ + #define R_MFWD_FWPBFDCN1_PBFDN_Pos (0UL) /*!< PBFDN (Bit 0) */ + #define R_MFWD_FWPBFDCN1_PBFDN_Msk (0xffffffffUL) /*!< PBFDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWPBFDCN2 ======================================================= */ + #define R_MFWD_FWPBFDCN2_PBFDN_Pos (0UL) /*!< PBFDN (Bit 0) */ + #define R_MFWD_FWPBFDCN2_PBFDN_Msk (0xffffffffUL) /*!< PBFDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWMHLCN0 ======================================================== */ + #define R_MFWD_FWMHLCN0_MHLN_Pos (0UL) /*!< MHLN (Bit 0) */ + #define R_MFWD_FWMHLCN0_MHLN_Msk (0xffffffffUL) /*!< MHLN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWMHLCN1 ======================================================== */ + #define R_MFWD_FWMHLCN1_MHLN_Pos (0UL) /*!< MHLN (Bit 0) */ + #define R_MFWD_FWMHLCN1_MHLN_Msk (0xffffffffUL) /*!< MHLN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWMHLCN2 ======================================================== */ + #define R_MFWD_FWMHLCN2_MHLN_Pos (0UL) /*!< MHLN (Bit 0) */ + #define R_MFWD_FWMHLCN2_MHLN_Msk (0xffffffffUL) /*!< MHLN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWDDFDCN0 ======================================================= */ + #define R_MFWD_FWDDFDCN0_DDFDN_Pos (0UL) /*!< DDFDN (Bit 0) */ + #define R_MFWD_FWDDFDCN0_DDFDN_Msk (0xffffffffUL) /*!< DDFDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWWMRDCN0 ======================================================= */ + #define R_MFWD_FWWMRDCN0_WMRDN_Pos (0UL) /*!< WMRDN (Bit 0) */ + #define R_MFWD_FWWMRDCN0_WMRDN_Msk (0xffffUL) /*!< WMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWWMRDCN1 ======================================================= */ + #define R_MFWD_FWWMRDCN1_WMRDN_Pos (0UL) /*!< WMRDN (Bit 0) */ + #define R_MFWD_FWWMRDCN1_WMRDN_Msk (0xffffUL) /*!< WMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWWMRDCN2 ======================================================= */ + #define R_MFWD_FWWMRDCN2_WMRDN_Pos (0UL) /*!< WMRDN (Bit 0) */ + #define R_MFWD_FWWMRDCN2_WMRDN_Msk (0xffffUL) /*!< WMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTRDCN0 ======================================================= */ + #define R_MFWD_FWCTRDCN0_CTRDN_Pos (0UL) /*!< CTRDN (Bit 0) */ + #define R_MFWD_FWCTRDCN0_CTRDN_Msk (0xffffUL) /*!< CTRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTRDCN1 ======================================================= */ + #define R_MFWD_FWCTRDCN1_CTRDN_Pos (0UL) /*!< CTRDN (Bit 0) */ + #define R_MFWD_FWCTRDCN1_CTRDN_Msk (0xffffUL) /*!< CTRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWLTHRDCN0 ======================================================= */ + #define R_MFWD_FWLTHRDCN0_LTHRDN_Pos (0UL) /*!< LTHRDN (Bit 0) */ + #define R_MFWD_FWLTHRDCN0_LTHRDN_Msk (0xffffUL) /*!< LTHRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWLTHRDCN1 ======================================================= */ + #define R_MFWD_FWLTHRDCN1_LTHRDN_Pos (0UL) /*!< LTHRDN (Bit 0) */ + #define R_MFWD_FWLTHRDCN1_LTHRDN_Msk (0xffffUL) /*!< LTHRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWLTHRDCN2 ======================================================= */ + #define R_MFWD_FWLTHRDCN2_LTHRDN_Pos (0UL) /*!< LTHRDN (Bit 0) */ + #define R_MFWD_FWLTHRDCN2_LTHRDN_Msk (0xffffUL) /*!< LTHRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWLTWRDCN0 ======================================================= */ + #define R_MFWD_FWLTWRDCN0_LTWRDN_Pos (0UL) /*!< LTWRDN (Bit 0) */ + #define R_MFWD_FWLTWRDCN0_LTWRDN_Msk (0xffffUL) /*!< LTWRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWLTWRDCN1 ======================================================= */ + #define R_MFWD_FWLTWRDCN1_LTWRDN_Pos (0UL) /*!< LTWRDN (Bit 0) */ + #define R_MFWD_FWLTWRDCN1_LTWRDN_Msk (0xffffUL) /*!< LTWRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWLTWRDCN2 ======================================================= */ + #define R_MFWD_FWLTWRDCN2_LTWRDN_Pos (0UL) /*!< LTWRDN (Bit 0) */ + #define R_MFWD_FWLTWRDCN2_LTWRDN_Msk (0xffffUL) /*!< LTWRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPBRDCN0 ======================================================= */ + #define R_MFWD_FWPBRDCN0_PBRDN_Pos (0UL) /*!< PBRDN (Bit 0) */ + #define R_MFWD_FWPBRDCN0_PBRDN_Msk (0xffffUL) /*!< PBRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPBRDCN1 ======================================================= */ + #define R_MFWD_FWPBRDCN1_PBRDN_Pos (0UL) /*!< PBRDN (Bit 0) */ + #define R_MFWD_FWPBRDCN1_PBRDN_Msk (0xffffUL) /*!< PBRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPBRDCN2 ======================================================= */ + #define R_MFWD_FWPBRDCN2_PBRDN_Pos (0UL) /*!< PBRDN (Bit 0) */ + #define R_MFWD_FWPBRDCN2_PBRDN_Msk (0xffffUL) /*!< PBRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWDDRDCN0 ======================================================= */ + #define R_MFWD_FWDDRDCN0_DDRDN_Pos (0UL) /*!< DDRDN (Bit 0) */ + #define R_MFWD_FWDDRDCN0_DDRDN_Msk (0xffffUL) /*!< DDRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN0 ======================================================= */ + #define R_MFWD_FWPMFDCN0_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN0_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN1 ======================================================= */ + #define R_MFWD_FWPMFDCN1_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN1_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN2 ======================================================= */ + #define R_MFWD_FWPMFDCN2_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN2_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN3 ======================================================= */ + #define R_MFWD_FWPMFDCN3_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN3_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN4 ======================================================= */ + #define R_MFWD_FWPMFDCN4_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN4_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN5 ======================================================= */ + #define R_MFWD_FWPMFDCN5_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN5_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN6 ======================================================= */ + #define R_MFWD_FWPMFDCN6_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN6_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN7 ======================================================= */ + #define R_MFWD_FWPMFDCN7_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN7_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN8 ======================================================= */ + #define R_MFWD_FWPMFDCN8_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN8_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN9 ======================================================= */ + #define R_MFWD_FWPMFDCN9_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN9_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMFDCN10 ======================================================= */ + #define R_MFWD_FWPMFDCN10_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN10_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMFDCN11 ======================================================= */ + #define R_MFWD_FWPMFDCN11_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN11_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMFDCN12 ======================================================= */ + #define R_MFWD_FWPMFDCN12_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN12_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMFDCN13 ======================================================= */ + #define R_MFWD_FWPMFDCN13_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN13_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMFDCN14 ======================================================= */ + #define R_MFWD_FWPMFDCN14_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN14_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMFDCN15 ======================================================= */ + #define R_MFWD_FWPMFDCN15_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN15_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN0 ======================================================= */ + #define R_MFWD_FWPMGDCN0_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN0_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN1 ======================================================= */ + #define R_MFWD_FWPMGDCN1_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN1_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN2 ======================================================= */ + #define R_MFWD_FWPMGDCN2_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN2_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN3 ======================================================= */ + #define R_MFWD_FWPMGDCN3_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN3_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN4 ======================================================= */ + #define R_MFWD_FWPMGDCN4_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN4_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN5 ======================================================= */ + #define R_MFWD_FWPMGDCN5_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN5_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN6 ======================================================= */ + #define R_MFWD_FWPMGDCN6_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN6_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN7 ======================================================= */ + #define R_MFWD_FWPMGDCN7_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN7_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN8 ======================================================= */ + #define R_MFWD_FWPMGDCN8_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN8_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN9 ======================================================= */ + #define R_MFWD_FWPMGDCN9_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN9_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN10 ======================================================= */ + #define R_MFWD_FWPMGDCN10_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN10_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN11 ======================================================= */ + #define R_MFWD_FWPMGDCN11_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN11_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN12 ======================================================= */ + #define R_MFWD_FWPMGDCN12_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN12_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN13 ======================================================= */ + #define R_MFWD_FWPMGDCN13_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN13_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN14 ======================================================= */ + #define R_MFWD_FWPMGDCN14_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN14_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN15 ======================================================= */ + #define R_MFWD_FWPMGDCN15_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN15_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN16 ======================================================= */ + #define R_MFWD_FWPMGDCN16_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN16_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN17 ======================================================= */ + #define R_MFWD_FWPMGDCN17_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN17_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN18 ======================================================= */ + #define R_MFWD_FWPMGDCN18_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN18_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN19 ======================================================= */ + #define R_MFWD_FWPMGDCN19_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN19_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN20 ======================================================= */ + #define R_MFWD_FWPMGDCN20_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN20_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN21 ======================================================= */ + #define R_MFWD_FWPMGDCN21_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN21_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN22 ======================================================= */ + #define R_MFWD_FWPMGDCN22_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN22_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN23 ======================================================= */ + #define R_MFWD_FWPMGDCN23_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN23_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN24 ======================================================= */ + #define R_MFWD_FWPMGDCN24_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN24_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN25 ======================================================= */ + #define R_MFWD_FWPMGDCN25_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN25_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN26 ======================================================= */ + #define R_MFWD_FWPMGDCN26_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN26_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN27 ======================================================= */ + #define R_MFWD_FWPMGDCN27_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN27_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN28 ======================================================= */ + #define R_MFWD_FWPMGDCN28_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN28_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN29 ======================================================= */ + #define R_MFWD_FWPMGDCN29_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN29_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN30 ======================================================= */ + #define R_MFWD_FWPMGDCN30_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN30_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN31 ======================================================= */ + #define R_MFWD_FWPMGDCN31_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN31_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN0 ======================================================= */ + #define R_MFWD_FWPMYDCN0_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN0_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN1 ======================================================= */ + #define R_MFWD_FWPMYDCN1_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN1_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN2 ======================================================= */ + #define R_MFWD_FWPMYDCN2_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN2_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN3 ======================================================= */ + #define R_MFWD_FWPMYDCN3_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN3_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN4 ======================================================= */ + #define R_MFWD_FWPMYDCN4_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN4_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN5 ======================================================= */ + #define R_MFWD_FWPMYDCN5_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN5_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN6 ======================================================= */ + #define R_MFWD_FWPMYDCN6_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN6_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN7 ======================================================= */ + #define R_MFWD_FWPMYDCN7_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN7_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN0 ======================================================= */ + #define R_MFWD_FWPMRDCN0_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN0_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN1 ======================================================= */ + #define R_MFWD_FWPMRDCN1_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN1_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN2 ======================================================= */ + #define R_MFWD_FWPMRDCN2_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN2_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN3 ======================================================= */ + #define R_MFWD_FWPMRDCN3_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN3_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN4 ======================================================= */ + #define R_MFWD_FWPMRDCN4_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN4_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN5 ======================================================= */ + #define R_MFWD_FWPMRDCN5_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN5_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN6 ======================================================= */ + #define R_MFWD_FWPMRDCN6_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN6_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN7 ======================================================= */ + #define R_MFWD_FWPMRDCN7_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN7_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN8 ======================================================= */ + #define R_MFWD_FWPMRDCN8_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN8_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN9 ======================================================= */ + #define R_MFWD_FWPMRDCN9_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN9_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN10 ======================================================= */ + #define R_MFWD_FWPMRDCN10_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN10_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN11 ======================================================= */ + #define R_MFWD_FWPMRDCN11_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN11_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN12 ======================================================= */ + #define R_MFWD_FWPMRDCN12_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN12_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN13 ======================================================= */ + #define R_MFWD_FWPMRDCN13_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN13_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN14 ======================================================= */ + #define R_MFWD_FWPMRDCN14_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN14_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN15 ======================================================= */ + #define R_MFWD_FWPMRDCN15_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN15_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN16 ======================================================= */ + #define R_MFWD_FWPMRDCN16_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN16_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN17 ======================================================= */ + #define R_MFWD_FWPMRDCN17_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN17_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN18 ======================================================= */ + #define R_MFWD_FWPMRDCN18_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN18_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN19 ======================================================= */ + #define R_MFWD_FWPMRDCN19_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN19_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN20 ======================================================= */ + #define R_MFWD_FWPMRDCN20_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN20_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN21 ======================================================= */ + #define R_MFWD_FWPMRDCN21_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN21_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN22 ======================================================= */ + #define R_MFWD_FWPMRDCN22_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN22_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN23 ======================================================= */ + #define R_MFWD_FWPMRDCN23_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN23_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN24 ======================================================= */ + #define R_MFWD_FWPMRDCN24_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN24_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN25 ======================================================= */ + #define R_MFWD_FWPMRDCN25_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN25_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN26 ======================================================= */ + #define R_MFWD_FWPMRDCN26_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN26_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN27 ======================================================= */ + #define R_MFWD_FWPMRDCN27_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN27_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN28 ======================================================= */ + #define R_MFWD_FWPMRDCN28_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN28_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN29 ======================================================= */ + #define R_MFWD_FWPMRDCN29_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN29_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN30 ======================================================= */ + #define R_MFWD_FWPMRDCN30_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN30_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN31 ======================================================= */ + #define R_MFWD_FWPMRDCN31_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN31_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN0 ======================================================= */ + #define R_MFWD_FWFRPPCN0_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN0_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN1 ======================================================= */ + #define R_MFWD_FWFRPPCN1_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN1_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN2 ======================================================= */ + #define R_MFWD_FWFRPPCN2_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN2_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN3 ======================================================= */ + #define R_MFWD_FWFRPPCN3_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN3_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN4 ======================================================= */ + #define R_MFWD_FWFRPPCN4_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN4_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN5 ======================================================= */ + #define R_MFWD_FWFRPPCN5_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN5_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN6 ======================================================= */ + #define R_MFWD_FWFRPPCN6_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN6_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN7 ======================================================= */ + #define R_MFWD_FWFRPPCN7_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN7_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN8 ======================================================= */ + #define R_MFWD_FWFRPPCN8_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN8_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN9 ======================================================= */ + #define R_MFWD_FWFRPPCN9_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN9_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN10 ======================================================= */ + #define R_MFWD_FWFRPPCN10_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN10_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN11 ======================================================= */ + #define R_MFWD_FWFRPPCN11_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN11_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN12 ======================================================= */ + #define R_MFWD_FWFRPPCN12_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN12_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN13 ======================================================= */ + #define R_MFWD_FWFRPPCN13_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN13_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN14 ======================================================= */ + #define R_MFWD_FWFRPPCN14_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN14_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN15 ======================================================= */ + #define R_MFWD_FWFRPPCN15_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN15_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN16 ======================================================= */ + #define R_MFWD_FWFRPPCN16_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN16_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN17 ======================================================= */ + #define R_MFWD_FWFRPPCN17_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN17_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN18 ======================================================= */ + #define R_MFWD_FWFRPPCN18_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN18_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN19 ======================================================= */ + #define R_MFWD_FWFRPPCN19_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN19_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN20 ======================================================= */ + #define R_MFWD_FWFRPPCN20_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN20_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN21 ======================================================= */ + #define R_MFWD_FWFRPPCN21_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN21_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN22 ======================================================= */ + #define R_MFWD_FWFRPPCN22_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN22_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN23 ======================================================= */ + #define R_MFWD_FWFRPPCN23_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN23_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN24 ======================================================= */ + #define R_MFWD_FWFRPPCN24_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN24_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN25 ======================================================= */ + #define R_MFWD_FWFRPPCN25_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN25_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN26 ======================================================= */ + #define R_MFWD_FWFRPPCN26_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN26_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN27 ======================================================= */ + #define R_MFWD_FWFRPPCN27_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN27_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN28 ======================================================= */ + #define R_MFWD_FWFRPPCN28_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN28_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN29 ======================================================= */ + #define R_MFWD_FWFRPPCN29_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN29_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN30 ======================================================= */ + #define R_MFWD_FWFRPPCN30_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN30_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN31 ======================================================= */ + #define R_MFWD_FWFRPPCN31_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN31_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN32 ======================================================= */ + #define R_MFWD_FWFRPPCN32_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN32_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN33 ======================================================= */ + #define R_MFWD_FWFRPPCN33_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN33_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN34 ======================================================= */ + #define R_MFWD_FWFRPPCN34_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN34_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN35 ======================================================= */ + #define R_MFWD_FWFRPPCN35_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN35_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN36 ======================================================= */ + #define R_MFWD_FWFRPPCN36_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN36_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN37 ======================================================= */ + #define R_MFWD_FWFRPPCN37_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN37_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN38 ======================================================= */ + #define R_MFWD_FWFRPPCN38_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN38_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN39 ======================================================= */ + #define R_MFWD_FWFRPPCN39_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN39_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN40 ======================================================= */ + #define R_MFWD_FWFRPPCN40_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN40_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN41 ======================================================= */ + #define R_MFWD_FWFRPPCN41_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN41_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN42 ======================================================= */ + #define R_MFWD_FWFRPPCN42_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN42_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN43 ======================================================= */ + #define R_MFWD_FWFRPPCN43_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN43_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN44 ======================================================= */ + #define R_MFWD_FWFRPPCN44_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN44_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN45 ======================================================= */ + #define R_MFWD_FWFRPPCN45_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN45_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN46 ======================================================= */ + #define R_MFWD_FWFRPPCN46_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN46_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN47 ======================================================= */ + #define R_MFWD_FWFRPPCN47_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN47_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN48 ======================================================= */ + #define R_MFWD_FWFRPPCN48_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN48_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN49 ======================================================= */ + #define R_MFWD_FWFRPPCN49_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN49_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN50 ======================================================= */ + #define R_MFWD_FWFRPPCN50_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN50_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN51 ======================================================= */ + #define R_MFWD_FWFRPPCN51_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN51_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN52 ======================================================= */ + #define R_MFWD_FWFRPPCN52_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN52_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN53 ======================================================= */ + #define R_MFWD_FWFRPPCN53_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN53_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN54 ======================================================= */ + #define R_MFWD_FWFRPPCN54_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN54_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN55 ======================================================= */ + #define R_MFWD_FWFRPPCN55_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN55_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN56 ======================================================= */ + #define R_MFWD_FWFRPPCN56_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN56_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN57 ======================================================= */ + #define R_MFWD_FWFRPPCN57_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN57_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN58 ======================================================= */ + #define R_MFWD_FWFRPPCN58_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN58_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN59 ======================================================= */ + #define R_MFWD_FWFRPPCN59_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN59_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN60 ======================================================= */ + #define R_MFWD_FWFRPPCN60_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN60_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN61 ======================================================= */ + #define R_MFWD_FWFRPPCN61_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN61_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN62 ======================================================= */ + #define R_MFWD_FWFRPPCN62_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN62_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN63 ======================================================= */ + #define R_MFWD_FWFRPPCN63_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN63_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN64 ======================================================= */ + #define R_MFWD_FWFRPPCN64_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN64_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN65 ======================================================= */ + #define R_MFWD_FWFRPPCN65_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN65_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN66 ======================================================= */ + #define R_MFWD_FWFRPPCN66_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN66_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN67 ======================================================= */ + #define R_MFWD_FWFRPPCN67_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN67_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN68 ======================================================= */ + #define R_MFWD_FWFRPPCN68_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN68_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN69 ======================================================= */ + #define R_MFWD_FWFRPPCN69_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN69_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN70 ======================================================= */ + #define R_MFWD_FWFRPPCN70_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN70_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN71 ======================================================= */ + #define R_MFWD_FWFRPPCN71_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN71_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN72 ======================================================= */ + #define R_MFWD_FWFRPPCN72_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN72_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN73 ======================================================= */ + #define R_MFWD_FWFRPPCN73_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN73_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN74 ======================================================= */ + #define R_MFWD_FWFRPPCN74_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN74_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN75 ======================================================= */ + #define R_MFWD_FWFRPPCN75_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN75_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN76 ======================================================= */ + #define R_MFWD_FWFRPPCN76_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN76_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN77 ======================================================= */ + #define R_MFWD_FWFRPPCN77_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN77_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN78 ======================================================= */ + #define R_MFWD_FWFRPPCN78_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN78_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN79 ======================================================= */ + #define R_MFWD_FWFRPPCN79_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN79_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN80 ======================================================= */ + #define R_MFWD_FWFRPPCN80_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN80_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN81 ======================================================= */ + #define R_MFWD_FWFRPPCN81_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN81_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN82 ======================================================= */ + #define R_MFWD_FWFRPPCN82_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN82_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN83 ======================================================= */ + #define R_MFWD_FWFRPPCN83_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN83_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN84 ======================================================= */ + #define R_MFWD_FWFRPPCN84_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN84_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN85 ======================================================= */ + #define R_MFWD_FWFRPPCN85_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN85_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN86 ======================================================= */ + #define R_MFWD_FWFRPPCN86_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN86_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN87 ======================================================= */ + #define R_MFWD_FWFRPPCN87_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN87_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN88 ======================================================= */ + #define R_MFWD_FWFRPPCN88_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN88_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN89 ======================================================= */ + #define R_MFWD_FWFRPPCN89_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN89_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN90 ======================================================= */ + #define R_MFWD_FWFRPPCN90_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN90_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN91 ======================================================= */ + #define R_MFWD_FWFRPPCN91_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN91_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN92 ======================================================= */ + #define R_MFWD_FWFRPPCN92_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN92_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN93 ======================================================= */ + #define R_MFWD_FWFRPPCN93_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN93_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN94 ======================================================= */ + #define R_MFWD_FWFRPPCN94_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN94_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN95 ======================================================= */ + #define R_MFWD_FWFRPPCN95_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN95_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN96 ======================================================= */ + #define R_MFWD_FWFRPPCN96_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN96_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN97 ======================================================= */ + #define R_MFWD_FWFRPPCN97_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN97_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN98 ======================================================= */ + #define R_MFWD_FWFRPPCN98_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN98_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN99 ======================================================= */ + #define R_MFWD_FWFRPPCN99_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN99_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN100 ====================================================== */ + #define R_MFWD_FWFRPPCN100_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN100_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN101 ====================================================== */ + #define R_MFWD_FWFRPPCN101_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN101_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN102 ====================================================== */ + #define R_MFWD_FWFRPPCN102_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN102_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN103 ====================================================== */ + #define R_MFWD_FWFRPPCN103_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN103_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN104 ====================================================== */ + #define R_MFWD_FWFRPPCN104_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN104_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN105 ====================================================== */ + #define R_MFWD_FWFRPPCN105_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN105_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN106 ====================================================== */ + #define R_MFWD_FWFRPPCN106_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN106_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN107 ====================================================== */ + #define R_MFWD_FWFRPPCN107_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN107_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN108 ====================================================== */ + #define R_MFWD_FWFRPPCN108_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN108_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN109 ====================================================== */ + #define R_MFWD_FWFRPPCN109_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN109_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN110 ====================================================== */ + #define R_MFWD_FWFRPPCN110_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN110_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN111 ====================================================== */ + #define R_MFWD_FWFRPPCN111_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN111_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN112 ====================================================== */ + #define R_MFWD_FWFRPPCN112_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN112_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN113 ====================================================== */ + #define R_MFWD_FWFRPPCN113_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN113_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN114 ====================================================== */ + #define R_MFWD_FWFRPPCN114_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN114_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN115 ====================================================== */ + #define R_MFWD_FWFRPPCN115_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN115_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN116 ====================================================== */ + #define R_MFWD_FWFRPPCN116_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN116_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN117 ====================================================== */ + #define R_MFWD_FWFRPPCN117_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN117_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN118 ====================================================== */ + #define R_MFWD_FWFRPPCN118_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN118_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN119 ====================================================== */ + #define R_MFWD_FWFRPPCN119_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN119_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN120 ====================================================== */ + #define R_MFWD_FWFRPPCN120_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN120_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN121 ====================================================== */ + #define R_MFWD_FWFRPPCN121_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN121_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN122 ====================================================== */ + #define R_MFWD_FWFRPPCN122_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN122_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN123 ====================================================== */ + #define R_MFWD_FWFRPPCN123_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN123_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN124 ====================================================== */ + #define R_MFWD_FWFRPPCN124_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN124_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN125 ====================================================== */ + #define R_MFWD_FWFRPPCN125_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN125_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN126 ====================================================== */ + #define R_MFWD_FWFRPPCN126_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN126_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN127 ====================================================== */ + #define R_MFWD_FWFRPPCN127_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN127_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN0 ======================================================= */ + #define R_MFWD_FWFRDPCN0_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN0_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN1 ======================================================= */ + #define R_MFWD_FWFRDPCN1_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN1_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN2 ======================================================= */ + #define R_MFWD_FWFRDPCN2_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN2_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN3 ======================================================= */ + #define R_MFWD_FWFRDPCN3_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN3_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN4 ======================================================= */ + #define R_MFWD_FWFRDPCN4_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN4_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN5 ======================================================= */ + #define R_MFWD_FWFRDPCN5_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN5_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN6 ======================================================= */ + #define R_MFWD_FWFRDPCN6_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN6_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN7 ======================================================= */ + #define R_MFWD_FWFRDPCN7_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN7_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN8 ======================================================= */ + #define R_MFWD_FWFRDPCN8_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN8_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN9 ======================================================= */ + #define R_MFWD_FWFRDPCN9_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN9_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN10 ======================================================= */ + #define R_MFWD_FWFRDPCN10_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN10_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN11 ======================================================= */ + #define R_MFWD_FWFRDPCN11_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN11_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN12 ======================================================= */ + #define R_MFWD_FWFRDPCN12_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN12_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN13 ======================================================= */ + #define R_MFWD_FWFRDPCN13_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN13_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN14 ======================================================= */ + #define R_MFWD_FWFRDPCN14_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN14_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN15 ======================================================= */ + #define R_MFWD_FWFRDPCN15_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN15_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN16 ======================================================= */ + #define R_MFWD_FWFRDPCN16_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN16_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN17 ======================================================= */ + #define R_MFWD_FWFRDPCN17_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN17_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN18 ======================================================= */ + #define R_MFWD_FWFRDPCN18_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN18_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN19 ======================================================= */ + #define R_MFWD_FWFRDPCN19_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN19_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN20 ======================================================= */ + #define R_MFWD_FWFRDPCN20_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN20_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN21 ======================================================= */ + #define R_MFWD_FWFRDPCN21_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN21_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN22 ======================================================= */ + #define R_MFWD_FWFRDPCN22_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN22_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN23 ======================================================= */ + #define R_MFWD_FWFRDPCN23_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN23_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN24 ======================================================= */ + #define R_MFWD_FWFRDPCN24_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN24_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN25 ======================================================= */ + #define R_MFWD_FWFRDPCN25_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN25_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN26 ======================================================= */ + #define R_MFWD_FWFRDPCN26_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN26_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN27 ======================================================= */ + #define R_MFWD_FWFRDPCN27_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN27_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN28 ======================================================= */ + #define R_MFWD_FWFRDPCN28_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN28_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN29 ======================================================= */ + #define R_MFWD_FWFRDPCN29_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN29_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN30 ======================================================= */ + #define R_MFWD_FWFRDPCN30_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN30_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN31 ======================================================= */ + #define R_MFWD_FWFRDPCN31_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN31_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN32 ======================================================= */ + #define R_MFWD_FWFRDPCN32_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN32_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN33 ======================================================= */ + #define R_MFWD_FWFRDPCN33_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN33_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN34 ======================================================= */ + #define R_MFWD_FWFRDPCN34_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN34_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN35 ======================================================= */ + #define R_MFWD_FWFRDPCN35_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN35_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN36 ======================================================= */ + #define R_MFWD_FWFRDPCN36_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN36_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN37 ======================================================= */ + #define R_MFWD_FWFRDPCN37_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN37_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN38 ======================================================= */ + #define R_MFWD_FWFRDPCN38_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN38_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN39 ======================================================= */ + #define R_MFWD_FWFRDPCN39_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN39_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN40 ======================================================= */ + #define R_MFWD_FWFRDPCN40_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN40_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN41 ======================================================= */ + #define R_MFWD_FWFRDPCN41_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN41_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN42 ======================================================= */ + #define R_MFWD_FWFRDPCN42_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN42_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN43 ======================================================= */ + #define R_MFWD_FWFRDPCN43_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN43_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN44 ======================================================= */ + #define R_MFWD_FWFRDPCN44_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN44_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN45 ======================================================= */ + #define R_MFWD_FWFRDPCN45_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN45_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN46 ======================================================= */ + #define R_MFWD_FWFRDPCN46_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN46_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN47 ======================================================= */ + #define R_MFWD_FWFRDPCN47_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN47_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN48 ======================================================= */ + #define R_MFWD_FWFRDPCN48_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN48_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN49 ======================================================= */ + #define R_MFWD_FWFRDPCN49_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN49_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN50 ======================================================= */ + #define R_MFWD_FWFRDPCN50_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN50_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN51 ======================================================= */ + #define R_MFWD_FWFRDPCN51_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN51_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN52 ======================================================= */ + #define R_MFWD_FWFRDPCN52_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN52_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN53 ======================================================= */ + #define R_MFWD_FWFRDPCN53_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN53_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN54 ======================================================= */ + #define R_MFWD_FWFRDPCN54_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN54_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN55 ======================================================= */ + #define R_MFWD_FWFRDPCN55_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN55_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN56 ======================================================= */ + #define R_MFWD_FWFRDPCN56_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN56_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN57 ======================================================= */ + #define R_MFWD_FWFRDPCN57_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN57_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN58 ======================================================= */ + #define R_MFWD_FWFRDPCN58_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN58_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN59 ======================================================= */ + #define R_MFWD_FWFRDPCN59_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN59_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN60 ======================================================= */ + #define R_MFWD_FWFRDPCN60_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN60_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN61 ======================================================= */ + #define R_MFWD_FWFRDPCN61_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN61_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN62 ======================================================= */ + #define R_MFWD_FWFRDPCN62_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN62_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN63 ======================================================= */ + #define R_MFWD_FWFRDPCN63_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN63_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN64 ======================================================= */ + #define R_MFWD_FWFRDPCN64_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN64_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN65 ======================================================= */ + #define R_MFWD_FWFRDPCN65_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN65_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN66 ======================================================= */ + #define R_MFWD_FWFRDPCN66_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN66_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN67 ======================================================= */ + #define R_MFWD_FWFRDPCN67_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN67_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN68 ======================================================= */ + #define R_MFWD_FWFRDPCN68_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN68_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN69 ======================================================= */ + #define R_MFWD_FWFRDPCN69_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN69_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN70 ======================================================= */ + #define R_MFWD_FWFRDPCN70_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN70_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN71 ======================================================= */ + #define R_MFWD_FWFRDPCN71_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN71_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN72 ======================================================= */ + #define R_MFWD_FWFRDPCN72_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN72_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN73 ======================================================= */ + #define R_MFWD_FWFRDPCN73_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN73_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN74 ======================================================= */ + #define R_MFWD_FWFRDPCN74_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN74_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN75 ======================================================= */ + #define R_MFWD_FWFRDPCN75_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN75_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN76 ======================================================= */ + #define R_MFWD_FWFRDPCN76_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN76_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN77 ======================================================= */ + #define R_MFWD_FWFRDPCN77_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN77_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN78 ======================================================= */ + #define R_MFWD_FWFRDPCN78_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN78_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN79 ======================================================= */ + #define R_MFWD_FWFRDPCN79_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN79_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN80 ======================================================= */ + #define R_MFWD_FWFRDPCN80_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN80_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN81 ======================================================= */ + #define R_MFWD_FWFRDPCN81_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN81_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN82 ======================================================= */ + #define R_MFWD_FWFRDPCN82_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN82_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN83 ======================================================= */ + #define R_MFWD_FWFRDPCN83_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN83_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN84 ======================================================= */ + #define R_MFWD_FWFRDPCN84_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN84_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN85 ======================================================= */ + #define R_MFWD_FWFRDPCN85_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN85_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN86 ======================================================= */ + #define R_MFWD_FWFRDPCN86_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN86_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN87 ======================================================= */ + #define R_MFWD_FWFRDPCN87_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN87_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN88 ======================================================= */ + #define R_MFWD_FWFRDPCN88_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN88_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN89 ======================================================= */ + #define R_MFWD_FWFRDPCN89_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN89_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN90 ======================================================= */ + #define R_MFWD_FWFRDPCN90_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN90_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN91 ======================================================= */ + #define R_MFWD_FWFRDPCN91_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN91_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN92 ======================================================= */ + #define R_MFWD_FWFRDPCN92_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN92_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN93 ======================================================= */ + #define R_MFWD_FWFRDPCN93_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN93_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN94 ======================================================= */ + #define R_MFWD_FWFRDPCN94_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN94_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN95 ======================================================= */ + #define R_MFWD_FWFRDPCN95_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN95_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN96 ======================================================= */ + #define R_MFWD_FWFRDPCN96_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN96_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN97 ======================================================= */ + #define R_MFWD_FWFRDPCN97_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN97_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN98 ======================================================= */ + #define R_MFWD_FWFRDPCN98_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN98_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN99 ======================================================= */ + #define R_MFWD_FWFRDPCN99_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN99_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN100 ====================================================== */ + #define R_MFWD_FWFRDPCN100_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN100_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN101 ====================================================== */ + #define R_MFWD_FWFRDPCN101_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN101_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN102 ====================================================== */ + #define R_MFWD_FWFRDPCN102_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN102_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN103 ====================================================== */ + #define R_MFWD_FWFRDPCN103_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN103_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN104 ====================================================== */ + #define R_MFWD_FWFRDPCN104_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN104_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN105 ====================================================== */ + #define R_MFWD_FWFRDPCN105_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN105_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN106 ====================================================== */ + #define R_MFWD_FWFRDPCN106_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN106_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN107 ====================================================== */ + #define R_MFWD_FWFRDPCN107_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN107_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN108 ====================================================== */ + #define R_MFWD_FWFRDPCN108_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN108_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN109 ====================================================== */ + #define R_MFWD_FWFRDPCN109_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN109_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN110 ====================================================== */ + #define R_MFWD_FWFRDPCN110_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN110_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN111 ====================================================== */ + #define R_MFWD_FWFRDPCN111_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN111_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN112 ====================================================== */ + #define R_MFWD_FWFRDPCN112_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN112_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN113 ====================================================== */ + #define R_MFWD_FWFRDPCN113_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN113_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN114 ====================================================== */ + #define R_MFWD_FWFRDPCN114_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN114_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN115 ====================================================== */ + #define R_MFWD_FWFRDPCN115_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN115_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN116 ====================================================== */ + #define R_MFWD_FWFRDPCN116_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN116_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN117 ====================================================== */ + #define R_MFWD_FWFRDPCN117_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN117_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN118 ====================================================== */ + #define R_MFWD_FWFRDPCN118_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN118_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN119 ====================================================== */ + #define R_MFWD_FWFRDPCN119_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN119_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN120 ====================================================== */ + #define R_MFWD_FWFRDPCN120_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN120_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN121 ====================================================== */ + #define R_MFWD_FWFRDPCN121_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN121_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN122 ====================================================== */ + #define R_MFWD_FWFRDPCN122_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN122_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN123 ====================================================== */ + #define R_MFWD_FWFRDPCN123_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN123_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN124 ====================================================== */ + #define R_MFWD_FWFRDPCN124_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN124_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN125 ====================================================== */ + #define R_MFWD_FWFRDPCN125_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN125_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN126 ====================================================== */ + #define R_MFWD_FWFRDPCN126_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN126_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN127 ====================================================== */ + #define R_MFWD_FWFRDPCN127_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN127_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWEIS00 ======================================================== */ + #define R_MFWD_FWEIS00_LTHSPFS_Pos (0UL) /*!< LTHSPFS (Bit 0) */ + #define R_MFWD_FWEIS00_LTHSPFS_Msk (0x1UL) /*!< LTHSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTHNTFS_Pos (2UL) /*!< LTHNTFS (Bit 2) */ + #define R_MFWD_FWEIS00_LTHNTFS_Msk (0x4UL) /*!< LTHNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTHUFS_Pos (3UL) /*!< LTHUFS (Bit 3) */ + #define R_MFWD_FWEIS00_LTHUFS_Msk (0x8UL) /*!< LTHUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTWDSPFS_Pos (10UL) /*!< LTWDSPFS (Bit 10) */ + #define R_MFWD_FWEIS00_LTWDSPFS_Msk (0x400UL) /*!< LTWDSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTWSSPFS_Pos (11UL) /*!< LTWSSPFS (Bit 11) */ + #define R_MFWD_FWEIS00_LTWSSPFS_Msk (0x800UL) /*!< LTWSSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTWVSPFS_Pos (12UL) /*!< LTWVSPFS (Bit 12) */ + #define R_MFWD_FWEIS00_LTWVSPFS_Msk (0x1000UL) /*!< LTWVSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTWNTFS_Pos (13UL) /*!< LTWNTFS (Bit 13) */ + #define R_MFWD_FWEIS00_LTWNTFS_Msk (0x2000UL) /*!< LTWNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTWSUFS_Pos (14UL) /*!< LTWSUFS (Bit 14) */ + #define R_MFWD_FWEIS00_LTWSUFS_Msk (0x4000UL) /*!< LTWSUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTWDUFS_Pos (15UL) /*!< LTWDUFS (Bit 15) */ + #define R_MFWD_FWEIS00_LTWDUFS_Msk (0x8000UL) /*!< LTWDUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTWVUFS_Pos (16UL) /*!< LTWVUFS (Bit 16) */ + #define R_MFWD_FWEIS00_LTWVUFS_Msk (0x10000UL) /*!< LTWVUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_PBNTFS_Pos (17UL) /*!< PBNTFS (Bit 17) */ + #define R_MFWD_FWEIS00_PBNTFS_Msk (0x20000UL) /*!< PBNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_SMHLFS_Pos (18UL) /*!< SMHLFS (Bit 18) */ + #define R_MFWD_FWEIS00_SMHLFS_Msk (0x40000UL) /*!< SMHLFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_SMHMFS_Pos (19UL) /*!< SMHMFS (Bit 19) */ + #define R_MFWD_FWEIS00_SMHMFS_Msk (0x80000UL) /*!< SMHMFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_WMCFS_Pos (22UL) /*!< WMCFS (Bit 22) */ + #define R_MFWD_FWEIS00_WMCFS_Msk (0x400000UL) /*!< WMCFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_WMFFS_Pos (23UL) /*!< WMFFS (Bit 23) */ + #define R_MFWD_FWEIS00_WMFFS_Msk (0x800000UL) /*!< WMFFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_WMISFS_Pos (24UL) /*!< WMISFS (Bit 24) */ + #define R_MFWD_FWEIS00_WMISFS_Msk (0x1000000UL) /*!< WMISFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_WMIUFS_Pos (25UL) /*!< WMIUFS (Bit 25) */ + #define R_MFWD_FWEIS00_WMIUFS_Msk (0x2000000UL) /*!< WMIUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_DDES_Pos (26UL) /*!< DDES (Bit 26) */ + #define R_MFWD_FWEIS00_DDES_Msk (0x4000000UL) /*!< DDES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_DDSES_Pos (28UL) /*!< DDSES (Bit 28) */ + #define R_MFWD_FWEIS00_DDSES_Msk (0x10000000UL) /*!< DDSES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_DDNTFS_Pos (29UL) /*!< DDNTFS (Bit 29) */ + #define R_MFWD_FWEIS00_DDNTFS_Msk (0x20000000UL) /*!< DDNTFS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIS01 ======================================================== */ + #define R_MFWD_FWEIS01_LTHSPFS_Pos (0UL) /*!< LTHSPFS (Bit 0) */ + #define R_MFWD_FWEIS01_LTHSPFS_Msk (0x1UL) /*!< LTHSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTHNTFS_Pos (2UL) /*!< LTHNTFS (Bit 2) */ + #define R_MFWD_FWEIS01_LTHNTFS_Msk (0x4UL) /*!< LTHNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTHUFS_Pos (3UL) /*!< LTHUFS (Bit 3) */ + #define R_MFWD_FWEIS01_LTHUFS_Msk (0x8UL) /*!< LTHUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTWDSPFS_Pos (10UL) /*!< LTWDSPFS (Bit 10) */ + #define R_MFWD_FWEIS01_LTWDSPFS_Msk (0x400UL) /*!< LTWDSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTWSSPFS_Pos (11UL) /*!< LTWSSPFS (Bit 11) */ + #define R_MFWD_FWEIS01_LTWSSPFS_Msk (0x800UL) /*!< LTWSSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTWVSPFS_Pos (12UL) /*!< LTWVSPFS (Bit 12) */ + #define R_MFWD_FWEIS01_LTWVSPFS_Msk (0x1000UL) /*!< LTWVSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTWNTFS_Pos (13UL) /*!< LTWNTFS (Bit 13) */ + #define R_MFWD_FWEIS01_LTWNTFS_Msk (0x2000UL) /*!< LTWNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTWSUFS_Pos (14UL) /*!< LTWSUFS (Bit 14) */ + #define R_MFWD_FWEIS01_LTWSUFS_Msk (0x4000UL) /*!< LTWSUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTWDUFS_Pos (15UL) /*!< LTWDUFS (Bit 15) */ + #define R_MFWD_FWEIS01_LTWDUFS_Msk (0x8000UL) /*!< LTWDUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTWVUFS_Pos (16UL) /*!< LTWVUFS (Bit 16) */ + #define R_MFWD_FWEIS01_LTWVUFS_Msk (0x10000UL) /*!< LTWVUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_PBNTFS_Pos (17UL) /*!< PBNTFS (Bit 17) */ + #define R_MFWD_FWEIS01_PBNTFS_Msk (0x20000UL) /*!< PBNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_SMHLFS_Pos (18UL) /*!< SMHLFS (Bit 18) */ + #define R_MFWD_FWEIS01_SMHLFS_Msk (0x40000UL) /*!< SMHLFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_SMHMFS_Pos (19UL) /*!< SMHMFS (Bit 19) */ + #define R_MFWD_FWEIS01_SMHMFS_Msk (0x80000UL) /*!< SMHMFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_WMCFS_Pos (22UL) /*!< WMCFS (Bit 22) */ + #define R_MFWD_FWEIS01_WMCFS_Msk (0x400000UL) /*!< WMCFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_WMFFS_Pos (23UL) /*!< WMFFS (Bit 23) */ + #define R_MFWD_FWEIS01_WMFFS_Msk (0x800000UL) /*!< WMFFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_WMISFS_Pos (24UL) /*!< WMISFS (Bit 24) */ + #define R_MFWD_FWEIS01_WMISFS_Msk (0x1000000UL) /*!< WMISFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_WMIUFS_Pos (25UL) /*!< WMIUFS (Bit 25) */ + #define R_MFWD_FWEIS01_WMIUFS_Msk (0x2000000UL) /*!< WMIUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_DDES_Pos (26UL) /*!< DDES (Bit 26) */ + #define R_MFWD_FWEIS01_DDES_Msk (0x4000000UL) /*!< DDES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_DDSES_Pos (28UL) /*!< DDSES (Bit 28) */ + #define R_MFWD_FWEIS01_DDSES_Msk (0x10000000UL) /*!< DDSES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_DDNTFS_Pos (29UL) /*!< DDNTFS (Bit 29) */ + #define R_MFWD_FWEIS01_DDNTFS_Msk (0x20000000UL) /*!< DDNTFS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIS02 ======================================================== */ + #define R_MFWD_FWEIS02_LTHSPFS_Pos (0UL) /*!< LTHSPFS (Bit 0) */ + #define R_MFWD_FWEIS02_LTHSPFS_Msk (0x1UL) /*!< LTHSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTHNTFS_Pos (2UL) /*!< LTHNTFS (Bit 2) */ + #define R_MFWD_FWEIS02_LTHNTFS_Msk (0x4UL) /*!< LTHNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTHUFS_Pos (3UL) /*!< LTHUFS (Bit 3) */ + #define R_MFWD_FWEIS02_LTHUFS_Msk (0x8UL) /*!< LTHUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTWDSPFS_Pos (10UL) /*!< LTWDSPFS (Bit 10) */ + #define R_MFWD_FWEIS02_LTWDSPFS_Msk (0x400UL) /*!< LTWDSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTWSSPFS_Pos (11UL) /*!< LTWSSPFS (Bit 11) */ + #define R_MFWD_FWEIS02_LTWSSPFS_Msk (0x800UL) /*!< LTWSSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTWVSPFS_Pos (12UL) /*!< LTWVSPFS (Bit 12) */ + #define R_MFWD_FWEIS02_LTWVSPFS_Msk (0x1000UL) /*!< LTWVSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTWNTFS_Pos (13UL) /*!< LTWNTFS (Bit 13) */ + #define R_MFWD_FWEIS02_LTWNTFS_Msk (0x2000UL) /*!< LTWNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTWSUFS_Pos (14UL) /*!< LTWSUFS (Bit 14) */ + #define R_MFWD_FWEIS02_LTWSUFS_Msk (0x4000UL) /*!< LTWSUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTWDUFS_Pos (15UL) /*!< LTWDUFS (Bit 15) */ + #define R_MFWD_FWEIS02_LTWDUFS_Msk (0x8000UL) /*!< LTWDUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTWVUFS_Pos (16UL) /*!< LTWVUFS (Bit 16) */ + #define R_MFWD_FWEIS02_LTWVUFS_Msk (0x10000UL) /*!< LTWVUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_PBNTFS_Pos (17UL) /*!< PBNTFS (Bit 17) */ + #define R_MFWD_FWEIS02_PBNTFS_Msk (0x20000UL) /*!< PBNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_SMHLFS_Pos (18UL) /*!< SMHLFS (Bit 18) */ + #define R_MFWD_FWEIS02_SMHLFS_Msk (0x40000UL) /*!< SMHLFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_SMHMFS_Pos (19UL) /*!< SMHMFS (Bit 19) */ + #define R_MFWD_FWEIS02_SMHMFS_Msk (0x80000UL) /*!< SMHMFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_WMCFS_Pos (22UL) /*!< WMCFS (Bit 22) */ + #define R_MFWD_FWEIS02_WMCFS_Msk (0x400000UL) /*!< WMCFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_WMFFS_Pos (23UL) /*!< WMFFS (Bit 23) */ + #define R_MFWD_FWEIS02_WMFFS_Msk (0x800000UL) /*!< WMFFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_WMISFS_Pos (24UL) /*!< WMISFS (Bit 24) */ + #define R_MFWD_FWEIS02_WMISFS_Msk (0x1000000UL) /*!< WMISFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_WMIUFS_Pos (25UL) /*!< WMIUFS (Bit 25) */ + #define R_MFWD_FWEIS02_WMIUFS_Msk (0x2000000UL) /*!< WMIUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_DDES_Pos (26UL) /*!< DDES (Bit 26) */ + #define R_MFWD_FWEIS02_DDES_Msk (0x4000000UL) /*!< DDES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_DDSES_Pos (28UL) /*!< DDSES (Bit 28) */ + #define R_MFWD_FWEIS02_DDSES_Msk (0x10000000UL) /*!< DDSES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_DDNTFS_Pos (29UL) /*!< DDNTFS (Bit 29) */ + #define R_MFWD_FWEIS02_DDNTFS_Msk (0x20000000UL) /*!< DDNTFS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIE00 ======================================================== */ + #define R_MFWD_FWEIE00_LTHSPFE_Pos (0UL) /*!< LTHSPFE (Bit 0) */ + #define R_MFWD_FWEIE00_LTHSPFE_Msk (0x1UL) /*!< LTHSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTHNTFE_Pos (2UL) /*!< LTHNTFE (Bit 2) */ + #define R_MFWD_FWEIE00_LTHNTFE_Msk (0x4UL) /*!< LTHNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTHUFE_Pos (3UL) /*!< LTHUFE (Bit 3) */ + #define R_MFWD_FWEIE00_LTHUFE_Msk (0x8UL) /*!< LTHUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTWDSPFE_Pos (10UL) /*!< LTWDSPFE (Bit 10) */ + #define R_MFWD_FWEIE00_LTWDSPFE_Msk (0x400UL) /*!< LTWDSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTWSSPFE_Pos (11UL) /*!< LTWSSPFE (Bit 11) */ + #define R_MFWD_FWEIE00_LTWSSPFE_Msk (0x800UL) /*!< LTWSSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTWVSPFE_Pos (12UL) /*!< LTWVSPFE (Bit 12) */ + #define R_MFWD_FWEIE00_LTWVSPFE_Msk (0x1000UL) /*!< LTWVSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTWNTFE_Pos (13UL) /*!< LTWNTFE (Bit 13) */ + #define R_MFWD_FWEIE00_LTWNTFE_Msk (0x2000UL) /*!< LTWNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTWSUFE_Pos (14UL) /*!< LTWSUFE (Bit 14) */ + #define R_MFWD_FWEIE00_LTWSUFE_Msk (0x4000UL) /*!< LTWSUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTWDUFE_Pos (15UL) /*!< LTWDUFE (Bit 15) */ + #define R_MFWD_FWEIE00_LTWDUFE_Msk (0x8000UL) /*!< LTWDUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTWVUFE_Pos (16UL) /*!< LTWVUFE (Bit 16) */ + #define R_MFWD_FWEIE00_LTWVUFE_Msk (0x10000UL) /*!< LTWVUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_PBNTFE_Pos (17UL) /*!< PBNTFE (Bit 17) */ + #define R_MFWD_FWEIE00_PBNTFE_Msk (0x20000UL) /*!< PBNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_SMHLFE_Pos (18UL) /*!< SMHLFE (Bit 18) */ + #define R_MFWD_FWEIE00_SMHLFE_Msk (0x40000UL) /*!< SMHLFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_SMHMFE_Pos (19UL) /*!< SMHMFE (Bit 19) */ + #define R_MFWD_FWEIE00_SMHMFE_Msk (0x80000UL) /*!< SMHMFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_WMCFE_Pos (22UL) /*!< WMCFE (Bit 22) */ + #define R_MFWD_FWEIE00_WMCFE_Msk (0x400000UL) /*!< WMCFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_WMFFE_Pos (23UL) /*!< WMFFE (Bit 23) */ + #define R_MFWD_FWEIE00_WMFFE_Msk (0x800000UL) /*!< WMFFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_WMISFE_Pos (24UL) /*!< WMISFE (Bit 24) */ + #define R_MFWD_FWEIE00_WMISFE_Msk (0x1000000UL) /*!< WMISFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_WMIUFE_Pos (25UL) /*!< WMIUFE (Bit 25) */ + #define R_MFWD_FWEIE00_WMIUFE_Msk (0x2000000UL) /*!< WMIUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_DDEE_Pos (26UL) /*!< DDEE (Bit 26) */ + #define R_MFWD_FWEIE00_DDEE_Msk (0x4000000UL) /*!< DDEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_DDFEE_Pos (27UL) /*!< DDFEE (Bit 27) */ + #define R_MFWD_FWEIE00_DDFEE_Msk (0x8000000UL) /*!< DDFEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_DDSEE_Pos (28UL) /*!< DDSEE (Bit 28) */ + #define R_MFWD_FWEIE00_DDSEE_Msk (0x10000000UL) /*!< DDSEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_DDNTFE_Pos (29UL) /*!< DDNTFE (Bit 29) */ + #define R_MFWD_FWEIE00_DDNTFE_Msk (0x20000000UL) /*!< DDNTFE (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIE01 ======================================================== */ + #define R_MFWD_FWEIE01_LTHSPFE_Pos (0UL) /*!< LTHSPFE (Bit 0) */ + #define R_MFWD_FWEIE01_LTHSPFE_Msk (0x1UL) /*!< LTHSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTHNTFE_Pos (2UL) /*!< LTHNTFE (Bit 2) */ + #define R_MFWD_FWEIE01_LTHNTFE_Msk (0x4UL) /*!< LTHNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTHUFE_Pos (3UL) /*!< LTHUFE (Bit 3) */ + #define R_MFWD_FWEIE01_LTHUFE_Msk (0x8UL) /*!< LTHUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTWDSPFE_Pos (10UL) /*!< LTWDSPFE (Bit 10) */ + #define R_MFWD_FWEIE01_LTWDSPFE_Msk (0x400UL) /*!< LTWDSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTWSSPFE_Pos (11UL) /*!< LTWSSPFE (Bit 11) */ + #define R_MFWD_FWEIE01_LTWSSPFE_Msk (0x800UL) /*!< LTWSSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTWVSPFE_Pos (12UL) /*!< LTWVSPFE (Bit 12) */ + #define R_MFWD_FWEIE01_LTWVSPFE_Msk (0x1000UL) /*!< LTWVSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTWNTFE_Pos (13UL) /*!< LTWNTFE (Bit 13) */ + #define R_MFWD_FWEIE01_LTWNTFE_Msk (0x2000UL) /*!< LTWNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTWSUFE_Pos (14UL) /*!< LTWSUFE (Bit 14) */ + #define R_MFWD_FWEIE01_LTWSUFE_Msk (0x4000UL) /*!< LTWSUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTWDUFE_Pos (15UL) /*!< LTWDUFE (Bit 15) */ + #define R_MFWD_FWEIE01_LTWDUFE_Msk (0x8000UL) /*!< LTWDUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTWVUFE_Pos (16UL) /*!< LTWVUFE (Bit 16) */ + #define R_MFWD_FWEIE01_LTWVUFE_Msk (0x10000UL) /*!< LTWVUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_PBNTFE_Pos (17UL) /*!< PBNTFE (Bit 17) */ + #define R_MFWD_FWEIE01_PBNTFE_Msk (0x20000UL) /*!< PBNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_SMHLFE_Pos (18UL) /*!< SMHLFE (Bit 18) */ + #define R_MFWD_FWEIE01_SMHLFE_Msk (0x40000UL) /*!< SMHLFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_SMHMFE_Pos (19UL) /*!< SMHMFE (Bit 19) */ + #define R_MFWD_FWEIE01_SMHMFE_Msk (0x80000UL) /*!< SMHMFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_WMCFE_Pos (22UL) /*!< WMCFE (Bit 22) */ + #define R_MFWD_FWEIE01_WMCFE_Msk (0x400000UL) /*!< WMCFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_WMFFE_Pos (23UL) /*!< WMFFE (Bit 23) */ + #define R_MFWD_FWEIE01_WMFFE_Msk (0x800000UL) /*!< WMFFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_WMISFE_Pos (24UL) /*!< WMISFE (Bit 24) */ + #define R_MFWD_FWEIE01_WMISFE_Msk (0x1000000UL) /*!< WMISFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_WMIUFE_Pos (25UL) /*!< WMIUFE (Bit 25) */ + #define R_MFWD_FWEIE01_WMIUFE_Msk (0x2000000UL) /*!< WMIUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_DDEE_Pos (26UL) /*!< DDEE (Bit 26) */ + #define R_MFWD_FWEIE01_DDEE_Msk (0x4000000UL) /*!< DDEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_DDFEE_Pos (27UL) /*!< DDFEE (Bit 27) */ + #define R_MFWD_FWEIE01_DDFEE_Msk (0x8000000UL) /*!< DDFEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_DDSEE_Pos (28UL) /*!< DDSEE (Bit 28) */ + #define R_MFWD_FWEIE01_DDSEE_Msk (0x10000000UL) /*!< DDSEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_DDNTFE_Pos (29UL) /*!< DDNTFE (Bit 29) */ + #define R_MFWD_FWEIE01_DDNTFE_Msk (0x20000000UL) /*!< DDNTFE (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIE02 ======================================================== */ + #define R_MFWD_FWEIE02_LTHSPFE_Pos (0UL) /*!< LTHSPFE (Bit 0) */ + #define R_MFWD_FWEIE02_LTHSPFE_Msk (0x1UL) /*!< LTHSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTHNTFE_Pos (2UL) /*!< LTHNTFE (Bit 2) */ + #define R_MFWD_FWEIE02_LTHNTFE_Msk (0x4UL) /*!< LTHNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTHUFE_Pos (3UL) /*!< LTHUFE (Bit 3) */ + #define R_MFWD_FWEIE02_LTHUFE_Msk (0x8UL) /*!< LTHUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTWDSPFE_Pos (10UL) /*!< LTWDSPFE (Bit 10) */ + #define R_MFWD_FWEIE02_LTWDSPFE_Msk (0x400UL) /*!< LTWDSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTWSSPFE_Pos (11UL) /*!< LTWSSPFE (Bit 11) */ + #define R_MFWD_FWEIE02_LTWSSPFE_Msk (0x800UL) /*!< LTWSSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTWVSPFE_Pos (12UL) /*!< LTWVSPFE (Bit 12) */ + #define R_MFWD_FWEIE02_LTWVSPFE_Msk (0x1000UL) /*!< LTWVSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTWNTFE_Pos (13UL) /*!< LTWNTFE (Bit 13) */ + #define R_MFWD_FWEIE02_LTWNTFE_Msk (0x2000UL) /*!< LTWNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTWSUFE_Pos (14UL) /*!< LTWSUFE (Bit 14) */ + #define R_MFWD_FWEIE02_LTWSUFE_Msk (0x4000UL) /*!< LTWSUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTWDUFE_Pos (15UL) /*!< LTWDUFE (Bit 15) */ + #define R_MFWD_FWEIE02_LTWDUFE_Msk (0x8000UL) /*!< LTWDUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTWVUFE_Pos (16UL) /*!< LTWVUFE (Bit 16) */ + #define R_MFWD_FWEIE02_LTWVUFE_Msk (0x10000UL) /*!< LTWVUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_PBNTFE_Pos (17UL) /*!< PBNTFE (Bit 17) */ + #define R_MFWD_FWEIE02_PBNTFE_Msk (0x20000UL) /*!< PBNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_SMHLFE_Pos (18UL) /*!< SMHLFE (Bit 18) */ + #define R_MFWD_FWEIE02_SMHLFE_Msk (0x40000UL) /*!< SMHLFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_SMHMFE_Pos (19UL) /*!< SMHMFE (Bit 19) */ + #define R_MFWD_FWEIE02_SMHMFE_Msk (0x80000UL) /*!< SMHMFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_WMCFE_Pos (22UL) /*!< WMCFE (Bit 22) */ + #define R_MFWD_FWEIE02_WMCFE_Msk (0x400000UL) /*!< WMCFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_WMFFE_Pos (23UL) /*!< WMFFE (Bit 23) */ + #define R_MFWD_FWEIE02_WMFFE_Msk (0x800000UL) /*!< WMFFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_WMISFE_Pos (24UL) /*!< WMISFE (Bit 24) */ + #define R_MFWD_FWEIE02_WMISFE_Msk (0x1000000UL) /*!< WMISFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_WMIUFE_Pos (25UL) /*!< WMIUFE (Bit 25) */ + #define R_MFWD_FWEIE02_WMIUFE_Msk (0x2000000UL) /*!< WMIUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_DDEE_Pos (26UL) /*!< DDEE (Bit 26) */ + #define R_MFWD_FWEIE02_DDEE_Msk (0x4000000UL) /*!< DDEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_DDFEE_Pos (27UL) /*!< DDFEE (Bit 27) */ + #define R_MFWD_FWEIE02_DDFEE_Msk (0x8000000UL) /*!< DDFEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_DDSEE_Pos (28UL) /*!< DDSEE (Bit 28) */ + #define R_MFWD_FWEIE02_DDSEE_Msk (0x10000000UL) /*!< DDSEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_DDNTFE_Pos (29UL) /*!< DDNTFE (Bit 29) */ + #define R_MFWD_FWEIE02_DDNTFE_Msk (0x20000000UL) /*!< DDNTFE (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEID00 ======================================================== */ + #define R_MFWD_FWEID00_LTHSPFD_Pos (0UL) /*!< LTHSPFD (Bit 0) */ + #define R_MFWD_FWEID00_LTHSPFD_Msk (0x1UL) /*!< LTHSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTHNTFD_Pos (2UL) /*!< LTHNTFD (Bit 2) */ + #define R_MFWD_FWEID00_LTHNTFD_Msk (0x4UL) /*!< LTHNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTHUFD_Pos (3UL) /*!< LTHUFD (Bit 3) */ + #define R_MFWD_FWEID00_LTHUFD_Msk (0x8UL) /*!< LTHUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTWDSPFD_Pos (10UL) /*!< LTWDSPFD (Bit 10) */ + #define R_MFWD_FWEID00_LTWDSPFD_Msk (0x400UL) /*!< LTWDSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTWSSPFD_Pos (11UL) /*!< LTWSSPFD (Bit 11) */ + #define R_MFWD_FWEID00_LTWSSPFD_Msk (0x800UL) /*!< LTWSSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTWVSPFD_Pos (12UL) /*!< LTWVSPFD (Bit 12) */ + #define R_MFWD_FWEID00_LTWVSPFD_Msk (0x1000UL) /*!< LTWVSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTWNTFD_Pos (13UL) /*!< LTWNTFD (Bit 13) */ + #define R_MFWD_FWEID00_LTWNTFD_Msk (0x2000UL) /*!< LTWNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTWSUFD_Pos (14UL) /*!< LTWSUFD (Bit 14) */ + #define R_MFWD_FWEID00_LTWSUFD_Msk (0x4000UL) /*!< LTWSUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTWDUFD_Pos (15UL) /*!< LTWDUFD (Bit 15) */ + #define R_MFWD_FWEID00_LTWDUFD_Msk (0x8000UL) /*!< LTWDUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTWVUFD_Pos (16UL) /*!< LTWVUFD (Bit 16) */ + #define R_MFWD_FWEID00_LTWVUFD_Msk (0x10000UL) /*!< LTWVUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_PBNTFD_Pos (17UL) /*!< PBNTFD (Bit 17) */ + #define R_MFWD_FWEID00_PBNTFD_Msk (0x20000UL) /*!< PBNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_SMHLFD_Pos (18UL) /*!< SMHLFD (Bit 18) */ + #define R_MFWD_FWEID00_SMHLFD_Msk (0x40000UL) /*!< SMHLFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_SMHMFD_Pos (19UL) /*!< SMHMFD (Bit 19) */ + #define R_MFWD_FWEID00_SMHMFD_Msk (0x80000UL) /*!< SMHMFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_WMCFD_Pos (22UL) /*!< WMCFD (Bit 22) */ + #define R_MFWD_FWEID00_WMCFD_Msk (0x400000UL) /*!< WMCFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_WMFFD_Pos (23UL) /*!< WMFFD (Bit 23) */ + #define R_MFWD_FWEID00_WMFFD_Msk (0x800000UL) /*!< WMFFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_WMISFD_Pos (24UL) /*!< WMISFD (Bit 24) */ + #define R_MFWD_FWEID00_WMISFD_Msk (0x1000000UL) /*!< WMISFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_WMIUFD_Pos (25UL) /*!< WMIUFD (Bit 25) */ + #define R_MFWD_FWEID00_WMIUFD_Msk (0x2000000UL) /*!< WMIUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_DDED_Pos (26UL) /*!< DDED (Bit 26) */ + #define R_MFWD_FWEID00_DDED_Msk (0x4000000UL) /*!< DDED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_DDFED_Pos (27UL) /*!< DDFED (Bit 27) */ + #define R_MFWD_FWEID00_DDFED_Msk (0x8000000UL) /*!< DDFED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_DDSED_Pos (28UL) /*!< DDSED (Bit 28) */ + #define R_MFWD_FWEID00_DDSED_Msk (0x10000000UL) /*!< DDSED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_DDNTFD_Pos (29UL) /*!< DDNTFD (Bit 29) */ + #define R_MFWD_FWEID00_DDNTFD_Msk (0x20000000UL) /*!< DDNTFD (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEID01 ======================================================== */ + #define R_MFWD_FWEID01_LTHSPFD_Pos (0UL) /*!< LTHSPFD (Bit 0) */ + #define R_MFWD_FWEID01_LTHSPFD_Msk (0x1UL) /*!< LTHSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTHNTFD_Pos (2UL) /*!< LTHNTFD (Bit 2) */ + #define R_MFWD_FWEID01_LTHNTFD_Msk (0x4UL) /*!< LTHNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTHUFD_Pos (3UL) /*!< LTHUFD (Bit 3) */ + #define R_MFWD_FWEID01_LTHUFD_Msk (0x8UL) /*!< LTHUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTWDSPFD_Pos (10UL) /*!< LTWDSPFD (Bit 10) */ + #define R_MFWD_FWEID01_LTWDSPFD_Msk (0x400UL) /*!< LTWDSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTWSSPFD_Pos (11UL) /*!< LTWSSPFD (Bit 11) */ + #define R_MFWD_FWEID01_LTWSSPFD_Msk (0x800UL) /*!< LTWSSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTWVSPFD_Pos (12UL) /*!< LTWVSPFD (Bit 12) */ + #define R_MFWD_FWEID01_LTWVSPFD_Msk (0x1000UL) /*!< LTWVSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTWNTFD_Pos (13UL) /*!< LTWNTFD (Bit 13) */ + #define R_MFWD_FWEID01_LTWNTFD_Msk (0x2000UL) /*!< LTWNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTWSUFD_Pos (14UL) /*!< LTWSUFD (Bit 14) */ + #define R_MFWD_FWEID01_LTWSUFD_Msk (0x4000UL) /*!< LTWSUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTWDUFD_Pos (15UL) /*!< LTWDUFD (Bit 15) */ + #define R_MFWD_FWEID01_LTWDUFD_Msk (0x8000UL) /*!< LTWDUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTWVUFD_Pos (16UL) /*!< LTWVUFD (Bit 16) */ + #define R_MFWD_FWEID01_LTWVUFD_Msk (0x10000UL) /*!< LTWVUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_PBNTFD_Pos (17UL) /*!< PBNTFD (Bit 17) */ + #define R_MFWD_FWEID01_PBNTFD_Msk (0x20000UL) /*!< PBNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_SMHLFD_Pos (18UL) /*!< SMHLFD (Bit 18) */ + #define R_MFWD_FWEID01_SMHLFD_Msk (0x40000UL) /*!< SMHLFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_SMHMFD_Pos (19UL) /*!< SMHMFD (Bit 19) */ + #define R_MFWD_FWEID01_SMHMFD_Msk (0x80000UL) /*!< SMHMFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_WMCFD_Pos (22UL) /*!< WMCFD (Bit 22) */ + #define R_MFWD_FWEID01_WMCFD_Msk (0x400000UL) /*!< WMCFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_WMFFD_Pos (23UL) /*!< WMFFD (Bit 23) */ + #define R_MFWD_FWEID01_WMFFD_Msk (0x800000UL) /*!< WMFFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_WMISFD_Pos (24UL) /*!< WMISFD (Bit 24) */ + #define R_MFWD_FWEID01_WMISFD_Msk (0x1000000UL) /*!< WMISFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_WMIUFD_Pos (25UL) /*!< WMIUFD (Bit 25) */ + #define R_MFWD_FWEID01_WMIUFD_Msk (0x2000000UL) /*!< WMIUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_DDED_Pos (26UL) /*!< DDED (Bit 26) */ + #define R_MFWD_FWEID01_DDED_Msk (0x4000000UL) /*!< DDED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_DDFED_Pos (27UL) /*!< DDFED (Bit 27) */ + #define R_MFWD_FWEID01_DDFED_Msk (0x8000000UL) /*!< DDFED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_DDSED_Pos (28UL) /*!< DDSED (Bit 28) */ + #define R_MFWD_FWEID01_DDSED_Msk (0x10000000UL) /*!< DDSED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_DDNTFD_Pos (29UL) /*!< DDNTFD (Bit 29) */ + #define R_MFWD_FWEID01_DDNTFD_Msk (0x20000000UL) /*!< DDNTFD (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEID02 ======================================================== */ + #define R_MFWD_FWEID02_LTHSPFD_Pos (0UL) /*!< LTHSPFD (Bit 0) */ + #define R_MFWD_FWEID02_LTHSPFD_Msk (0x1UL) /*!< LTHSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTHNTFD_Pos (2UL) /*!< LTHNTFD (Bit 2) */ + #define R_MFWD_FWEID02_LTHNTFD_Msk (0x4UL) /*!< LTHNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTHUFD_Pos (3UL) /*!< LTHUFD (Bit 3) */ + #define R_MFWD_FWEID02_LTHUFD_Msk (0x8UL) /*!< LTHUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTWDSPFD_Pos (10UL) /*!< LTWDSPFD (Bit 10) */ + #define R_MFWD_FWEID02_LTWDSPFD_Msk (0x400UL) /*!< LTWDSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTWSSPFD_Pos (11UL) /*!< LTWSSPFD (Bit 11) */ + #define R_MFWD_FWEID02_LTWSSPFD_Msk (0x800UL) /*!< LTWSSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTWVSPFD_Pos (12UL) /*!< LTWVSPFD (Bit 12) */ + #define R_MFWD_FWEID02_LTWVSPFD_Msk (0x1000UL) /*!< LTWVSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTWNTFD_Pos (13UL) /*!< LTWNTFD (Bit 13) */ + #define R_MFWD_FWEID02_LTWNTFD_Msk (0x2000UL) /*!< LTWNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTWSUFD_Pos (14UL) /*!< LTWSUFD (Bit 14) */ + #define R_MFWD_FWEID02_LTWSUFD_Msk (0x4000UL) /*!< LTWSUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTWDUFD_Pos (15UL) /*!< LTWDUFD (Bit 15) */ + #define R_MFWD_FWEID02_LTWDUFD_Msk (0x8000UL) /*!< LTWDUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTWVUFD_Pos (16UL) /*!< LTWVUFD (Bit 16) */ + #define R_MFWD_FWEID02_LTWVUFD_Msk (0x10000UL) /*!< LTWVUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_PBNTFD_Pos (17UL) /*!< PBNTFD (Bit 17) */ + #define R_MFWD_FWEID02_PBNTFD_Msk (0x20000UL) /*!< PBNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_SMHLFD_Pos (18UL) /*!< SMHLFD (Bit 18) */ + #define R_MFWD_FWEID02_SMHLFD_Msk (0x40000UL) /*!< SMHLFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_SMHMFD_Pos (19UL) /*!< SMHMFD (Bit 19) */ + #define R_MFWD_FWEID02_SMHMFD_Msk (0x80000UL) /*!< SMHMFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_WMCFD_Pos (22UL) /*!< WMCFD (Bit 22) */ + #define R_MFWD_FWEID02_WMCFD_Msk (0x400000UL) /*!< WMCFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_WMFFD_Pos (23UL) /*!< WMFFD (Bit 23) */ + #define R_MFWD_FWEID02_WMFFD_Msk (0x800000UL) /*!< WMFFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_WMISFD_Pos (24UL) /*!< WMISFD (Bit 24) */ + #define R_MFWD_FWEID02_WMISFD_Msk (0x1000000UL) /*!< WMISFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_WMIUFD_Pos (25UL) /*!< WMIUFD (Bit 25) */ + #define R_MFWD_FWEID02_WMIUFD_Msk (0x2000000UL) /*!< WMIUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_DDED_Pos (26UL) /*!< DDED (Bit 26) */ + #define R_MFWD_FWEID02_DDED_Msk (0x4000000UL) /*!< DDED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_DDFED_Pos (27UL) /*!< DDFED (Bit 27) */ + #define R_MFWD_FWEID02_DDFED_Msk (0x8000000UL) /*!< DDFED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_DDSED_Pos (28UL) /*!< DDSED (Bit 28) */ + #define R_MFWD_FWEID02_DDSED_Msk (0x10000000UL) /*!< DDSED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_DDNTFD_Pos (29UL) /*!< DDNTFD (Bit 29) */ + #define R_MFWD_FWEID02_DDNTFD_Msk (0x20000000UL) /*!< DDNTFD (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIS1 ========================================================= */ + #define R_MFWD_FWEIS1_LTHTEES_Pos (0UL) /*!< LTHTEES (Bit 0) */ + #define R_MFWD_FWEIS1_LTHTEES_Msk (0x1UL) /*!< LTHTEES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS1_LTHTSES_Pos (1UL) /*!< LTHTSES (Bit 1) */ + #define R_MFWD_FWEIS1_LTHTSES_Msk (0x2UL) /*!< LTHTSES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS1_MACTEES_Pos (4UL) /*!< MACTEES (Bit 4) */ + #define R_MFWD_FWEIS1_MACTEES_Msk (0x10UL) /*!< MACTEES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS1_MACTSES_Pos (5UL) /*!< MACTSES (Bit 5) */ + #define R_MFWD_FWEIS1_MACTSES_Msk (0x20UL) /*!< MACTSES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS1_VLANTEES_Pos (6UL) /*!< VLANTEES (Bit 6) */ + #define R_MFWD_FWEIS1_VLANTEES_Msk (0x40UL) /*!< VLANTEES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS1_VLANTSES_Pos (7UL) /*!< VLANTSES (Bit 7) */ + #define R_MFWD_FWEIS1_VLANTSES_Msk (0x80UL) /*!< VLANTSES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS1_L23UEES_Pos (8UL) /*!< L23UEES (Bit 8) */ + #define R_MFWD_FWEIS1_L23UEES_Msk (0x100UL) /*!< L23UEES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS1_AREES_Pos (16UL) /*!< AREES (Bit 16) */ + #define R_MFWD_FWEIS1_AREES_Msk (0x10000UL) /*!< AREES (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIE1 ========================================================= */ + #define R_MFWD_FWEIE1_LTHTEEE_Pos (0UL) /*!< LTHTEEE (Bit 0) */ + #define R_MFWD_FWEIE1_LTHTEEE_Msk (0x1UL) /*!< LTHTEEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE1_LTHTSEE_Pos (1UL) /*!< LTHTSEE (Bit 1) */ + #define R_MFWD_FWEIE1_LTHTSEE_Msk (0x2UL) /*!< LTHTSEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE1_MACTEEE_Pos (4UL) /*!< MACTEEE (Bit 4) */ + #define R_MFWD_FWEIE1_MACTEEE_Msk (0x10UL) /*!< MACTEEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE1_MACTSEE_Pos (5UL) /*!< MACTSEE (Bit 5) */ + #define R_MFWD_FWEIE1_MACTSEE_Msk (0x20UL) /*!< MACTSEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE1_VLANTEEE_Pos (6UL) /*!< VLANTEEE (Bit 6) */ + #define R_MFWD_FWEIE1_VLANTEEE_Msk (0x40UL) /*!< VLANTEEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE1_VLANTSEE_Pos (7UL) /*!< VLANTSEE (Bit 7) */ + #define R_MFWD_FWEIE1_VLANTSEE_Msk (0x80UL) /*!< VLANTSEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE1_L23UEEE_Pos (8UL) /*!< L23UEEE (Bit 8) */ + #define R_MFWD_FWEIE1_L23UEEE_Msk (0x100UL) /*!< L23UEEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE1_AREEE_Pos (16UL) /*!< AREEE (Bit 16) */ + #define R_MFWD_FWEIE1_AREEE_Msk (0x10000UL) /*!< AREEE (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEID1 ========================================================= */ + #define R_MFWD_FWEID1_LTHTEED_Pos (0UL) /*!< LTHTEED (Bit 0) */ + #define R_MFWD_FWEID1_LTHTEED_Msk (0x1UL) /*!< LTHTEED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID1_LTHTSED_Pos (1UL) /*!< LTHTSED (Bit 1) */ + #define R_MFWD_FWEID1_LTHTSED_Msk (0x2UL) /*!< LTHTSED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID1_MACTEED_Pos (4UL) /*!< MACTEED (Bit 4) */ + #define R_MFWD_FWEID1_MACTEED_Msk (0x10UL) /*!< MACTEED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID1_MACTSED_Pos (5UL) /*!< MACTSED (Bit 5) */ + #define R_MFWD_FWEID1_MACTSED_Msk (0x20UL) /*!< MACTSED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID1_VLANTEED_Pos (6UL) /*!< VLANTEED (Bit 6) */ + #define R_MFWD_FWEID1_VLANTEED_Msk (0x40UL) /*!< VLANTEED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID1_VLANTSED_Pos (7UL) /*!< VLANTSED (Bit 7) */ + #define R_MFWD_FWEID1_VLANTSED_Msk (0x80UL) /*!< VLANTSED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID1_L23UEED_Pos (8UL) /*!< L23UEED (Bit 8) */ + #define R_MFWD_FWEID1_L23UEED_Msk (0x100UL) /*!< L23UEED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID1_AREED_Pos (16UL) /*!< AREED (Bit 16) */ + #define R_MFWD_FWEID1_AREED_Msk (0x10000UL) /*!< AREED (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIS2 ========================================================= */ + #define R_MFWD_FWEIS2_PMFS_Pos (0UL) /*!< PMFS (Bit 0) */ + #define R_MFWD_FWEIS2_PMFS_Msk (0xffffUL) /*!< PMFS (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWEIE2 ========================================================= */ + #define R_MFWD_FWEIE2_PMFE_Pos (0UL) /*!< PMFE (Bit 0) */ + #define R_MFWD_FWEIE2_PMFE_Msk (0xffffUL) /*!< PMFE (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWEID2 ========================================================= */ + #define R_MFWD_FWEID2_PMFD_Pos (0UL) /*!< PMFD (Bit 0) */ + #define R_MFWD_FWEID2_PMFD_Msk (0xffffUL) /*!< PMFD (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWEIS5 ========================================================= */ + #define R_MFWD_FWEIS5_PMRFS_Pos (0UL) /*!< PMRFS (Bit 0) */ + #define R_MFWD_FWEIS5_PMRFS_Msk (0xffffffffUL) /*!< PMRFS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE5 ========================================================= */ + #define R_MFWD_FWEIE5_PMRFE_Pos (0UL) /*!< PMRFE (Bit 0) */ + #define R_MFWD_FWEIE5_PMRFE_Msk (0xffffffffUL) /*!< PMRFE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID5 ========================================================= */ + #define R_MFWD_FWEID5_PMRFD_Pos (0UL) /*!< PMRFD (Bit 0) */ + #define R_MFWD_FWEID5_PMRFD_Msk (0xffffffffUL) /*!< PMRFD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS60 ======================================================== */ + #define R_MFWD_FWEIS60_FFS_Pos (0UL) /*!< FFS (Bit 0) */ + #define R_MFWD_FWEIS60_FFS_Msk (0xffffffffUL) /*!< FFS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS61 ======================================================== */ + #define R_MFWD_FWEIS61_FFS_Pos (0UL) /*!< FFS (Bit 0) */ + #define R_MFWD_FWEIS61_FFS_Msk (0xffffffffUL) /*!< FFS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS62 ======================================================== */ + #define R_MFWD_FWEIS62_FFS_Pos (0UL) /*!< FFS (Bit 0) */ + #define R_MFWD_FWEIS62_FFS_Msk (0xffffffffUL) /*!< FFS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS63 ======================================================== */ + #define R_MFWD_FWEIS63_FFS_Pos (0UL) /*!< FFS (Bit 0) */ + #define R_MFWD_FWEIS63_FFS_Msk (0xffffffffUL) /*!< FFS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE60 ======================================================== */ + #define R_MFWD_FWEIE60_FFE_Pos (0UL) /*!< FFE (Bit 0) */ + #define R_MFWD_FWEIE60_FFE_Msk (0xffffffffUL) /*!< FFE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE61 ======================================================== */ + #define R_MFWD_FWEIE61_FFE_Pos (0UL) /*!< FFE (Bit 0) */ + #define R_MFWD_FWEIE61_FFE_Msk (0xffffffffUL) /*!< FFE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE62 ======================================================== */ + #define R_MFWD_FWEIE62_FFE_Pos (0UL) /*!< FFE (Bit 0) */ + #define R_MFWD_FWEIE62_FFE_Msk (0xffffffffUL) /*!< FFE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE63 ======================================================== */ + #define R_MFWD_FWEIE63_FFE_Pos (0UL) /*!< FFE (Bit 0) */ + #define R_MFWD_FWEIE63_FFE_Msk (0xffffffffUL) /*!< FFE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID60 ======================================================== */ + #define R_MFWD_FWEID60_FFD_Pos (0UL) /*!< FFD (Bit 0) */ + #define R_MFWD_FWEID60_FFD_Msk (0xffffffffUL) /*!< FFD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID61 ======================================================== */ + #define R_MFWD_FWEID61_FFD_Pos (0UL) /*!< FFD (Bit 0) */ + #define R_MFWD_FWEID61_FFD_Msk (0xffffffffUL) /*!< FFD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID62 ======================================================== */ + #define R_MFWD_FWEID62_FFD_Pos (0UL) /*!< FFD (Bit 0) */ + #define R_MFWD_FWEID62_FFD_Msk (0xffffffffUL) /*!< FFD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID63 ======================================================== */ + #define R_MFWD_FWEID63_FFD_Pos (0UL) /*!< FFD (Bit 0) */ + #define R_MFWD_FWEID63_FFD_Msk (0xffffffffUL) /*!< FFD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS70 ======================================================== */ + #define R_MFWD_FWEIS70_FOORS_Pos (0UL) /*!< FOORS (Bit 0) */ + #define R_MFWD_FWEIS70_FOORS_Msk (0xffffffffUL) /*!< FOORS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS71 ======================================================== */ + #define R_MFWD_FWEIS71_FOORS_Pos (0UL) /*!< FOORS (Bit 0) */ + #define R_MFWD_FWEIS71_FOORS_Msk (0xffffffffUL) /*!< FOORS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS72 ======================================================== */ + #define R_MFWD_FWEIS72_FOORS_Pos (0UL) /*!< FOORS (Bit 0) */ + #define R_MFWD_FWEIS72_FOORS_Msk (0xffffffffUL) /*!< FOORS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS73 ======================================================== */ + #define R_MFWD_FWEIS73_FOORS_Pos (0UL) /*!< FOORS (Bit 0) */ + #define R_MFWD_FWEIS73_FOORS_Msk (0xffffffffUL) /*!< FOORS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE70 ======================================================== */ + #define R_MFWD_FWEIE70_FOORE_Pos (0UL) /*!< FOORE (Bit 0) */ + #define R_MFWD_FWEIE70_FOORE_Msk (0xffffffffUL) /*!< FOORE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE71 ======================================================== */ + #define R_MFWD_FWEIE71_FOORE_Pos (0UL) /*!< FOORE (Bit 0) */ + #define R_MFWD_FWEIE71_FOORE_Msk (0xffffffffUL) /*!< FOORE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE72 ======================================================== */ + #define R_MFWD_FWEIE72_FOORE_Pos (0UL) /*!< FOORE (Bit 0) */ + #define R_MFWD_FWEIE72_FOORE_Msk (0xffffffffUL) /*!< FOORE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE73 ======================================================== */ + #define R_MFWD_FWEIE73_FOORE_Pos (0UL) /*!< FOORE (Bit 0) */ + #define R_MFWD_FWEIE73_FOORE_Msk (0xffffffffUL) /*!< FOORE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID70 ======================================================== */ + #define R_MFWD_FWEID70_FOORD_Pos (0UL) /*!< FOORD (Bit 0) */ + #define R_MFWD_FWEID70_FOORD_Msk (0xffffffffUL) /*!< FOORD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID71 ======================================================== */ + #define R_MFWD_FWEID71_FOORD_Pos (0UL) /*!< FOORD (Bit 0) */ + #define R_MFWD_FWEID71_FOORD_Msk (0xffffffffUL) /*!< FOORD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID72 ======================================================== */ + #define R_MFWD_FWEID72_FOORD_Pos (0UL) /*!< FOORD (Bit 0) */ + #define R_MFWD_FWEID72_FOORD_Msk (0xffffffffUL) /*!< FOORD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID73 ======================================================== */ + #define R_MFWD_FWEID73_FOORD_Pos (0UL) /*!< FOORD (Bit 0) */ + #define R_MFWD_FWEID73_FOORD_Msk (0xffffffffUL) /*!< FOORD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS80 ======================================================== */ + #define R_MFWD_FWEIS80_TOS_Pos (0UL) /*!< TOS (Bit 0) */ + #define R_MFWD_FWEIS80_TOS_Msk (0xffffffffUL) /*!< TOS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS81 ======================================================== */ + #define R_MFWD_FWEIS81_TOS_Pos (0UL) /*!< TOS (Bit 0) */ + #define R_MFWD_FWEIS81_TOS_Msk (0xffffffffUL) /*!< TOS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS82 ======================================================== */ + #define R_MFWD_FWEIS82_TOS_Pos (0UL) /*!< TOS (Bit 0) */ + #define R_MFWD_FWEIS82_TOS_Msk (0xffffffffUL) /*!< TOS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS83 ======================================================== */ + #define R_MFWD_FWEIS83_TOS_Pos (0UL) /*!< TOS (Bit 0) */ + #define R_MFWD_FWEIS83_TOS_Msk (0xffffffffUL) /*!< TOS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE80 ======================================================== */ + #define R_MFWD_FWEIE80_TOE_Pos (0UL) /*!< TOE (Bit 0) */ + #define R_MFWD_FWEIE80_TOE_Msk (0xffffffffUL) /*!< TOE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE81 ======================================================== */ + #define R_MFWD_FWEIE81_TOE_Pos (0UL) /*!< TOE (Bit 0) */ + #define R_MFWD_FWEIE81_TOE_Msk (0xffffffffUL) /*!< TOE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE82 ======================================================== */ + #define R_MFWD_FWEIE82_TOE_Pos (0UL) /*!< TOE (Bit 0) */ + #define R_MFWD_FWEIE82_TOE_Msk (0xffffffffUL) /*!< TOE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE83 ======================================================== */ + #define R_MFWD_FWEIE83_TOE_Pos (0UL) /*!< TOE (Bit 0) */ + #define R_MFWD_FWEIE83_TOE_Msk (0xffffffffUL) /*!< TOE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID80 ======================================================== */ + #define R_MFWD_FWEID80_TOD_Pos (0UL) /*!< TOD (Bit 0) */ + #define R_MFWD_FWEID80_TOD_Msk (0xffffffffUL) /*!< TOD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID81 ======================================================== */ + #define R_MFWD_FWEID81_TOD_Pos (0UL) /*!< TOD (Bit 0) */ + #define R_MFWD_FWEID81_TOD_Msk (0xffffffffUL) /*!< TOD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID82 ======================================================== */ + #define R_MFWD_FWEID82_TOD_Pos (0UL) /*!< TOD (Bit 0) */ + #define R_MFWD_FWEID82_TOD_Msk (0xffffffffUL) /*!< TOD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID83 ======================================================== */ + #define R_MFWD_FWEID83_TOD_Pos (0UL) /*!< TOD (Bit 0) */ + #define R_MFWD_FWEID83_TOD_Msk (0xffffffffUL) /*!< TOD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWMIS0 ========================================================= */ + #define R_MFWD_FWMIS0_LTHTFS_Pos (0UL) /*!< LTHTFS (Bit 0) */ + #define R_MFWD_FWMIS0_LTHTFS_Msk (0x1UL) /*!< LTHTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMIS0_MACTFS_Pos (2UL) /*!< MACTFS (Bit 2) */ + #define R_MFWD_FWMIS0_MACTFS_Msk (0x4UL) /*!< MACTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMIS0_VLANTFS_Pos (3UL) /*!< VLANTFS (Bit 3) */ + #define R_MFWD_FWMIS0_VLANTFS_Msk (0x8UL) /*!< VLANTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMIS0_MACADAS_Pos (17UL) /*!< MACADAS (Bit 17) */ + #define R_MFWD_FWMIS0_MACADAS_Msk (0x20000UL) /*!< MACADAS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWMIE0 ========================================================= */ + #define R_MFWD_FWMIE0_LTHTFE_Pos (0UL) /*!< LTHTFE (Bit 0) */ + #define R_MFWD_FWMIE0_LTHTFE_Msk (0x1UL) /*!< LTHTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMIE0_MACTFE_Pos (2UL) /*!< MACTFE (Bit 2) */ + #define R_MFWD_FWMIE0_MACTFE_Msk (0x4UL) /*!< MACTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMIE0_VLANTFE_Pos (3UL) /*!< VLANTFE (Bit 3) */ + #define R_MFWD_FWMIE0_VLANTFE_Msk (0x8UL) /*!< VLANTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMIE0_MACADAE_Pos (17UL) /*!< MACADAE (Bit 17) */ + #define R_MFWD_FWMIE0_MACADAE_Msk (0x20000UL) /*!< MACADAE (Bitfield-Mask: 0x01) */ +/* ======================================================== FWMID0 ========================================================= */ + #define R_MFWD_FWMID0_LTHTFD_Pos (0UL) /*!< LTHTFD (Bit 0) */ + #define R_MFWD_FWMID0_LTHTFD_Msk (0x1UL) /*!< LTHTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMID0_MACTFD_Pos (2UL) /*!< MACTFD (Bit 2) */ + #define R_MFWD_FWMID0_MACTFD_Msk (0x4UL) /*!< MACTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMID0_VLANTFD_Pos (3UL) /*!< VLANTFD (Bit 3) */ + #define R_MFWD_FWMID0_VLANTFD_Msk (0x8UL) /*!< VLANTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMID0_MACADAD_Pos (17UL) /*!< MACADAD (Bit 17) */ + #define R_MFWD_FWMID0_MACADAD_Msk (0x20000UL) /*!< MACADAD (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MIPI_DSI ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ISR ========================================================== */ + #define R_MIPI_DSI_ISR_SQ0_Pos (0UL) /*!< SQ0 (Bit 0) */ + #define R_MIPI_DSI_ISR_SQ0_Msk (0x1UL) /*!< SQ0 (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ISR_SQ1_Pos (4UL) /*!< SQ1 (Bit 4) */ + #define R_MIPI_DSI_ISR_SQ1_Msk (0x10UL) /*!< SQ1 (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ISR_VM_Pos (8UL) /*!< VM (Bit 8) */ + #define R_MIPI_DSI_ISR_VM_Msk (0x100UL) /*!< VM (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ISR_RCV_Pos (12UL) /*!< RCV (Bit 12) */ + #define R_MIPI_DSI_ISR_RCV_Msk (0x1000UL) /*!< RCV (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ISR_FERR_Pos (16UL) /*!< FERR (Bit 16) */ + #define R_MIPI_DSI_ISR_FERR_Msk (0x10000UL) /*!< FERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ISR_PPI_Pos (20UL) /*!< PPI (Bit 20) */ + #define R_MIPI_DSI_ISR_PPI_Msk (0x100000UL) /*!< PPI (Bitfield-Mask: 0x01) */ +/* ======================================================== LINKSR ========================================================= */ + #define R_MIPI_DSI_LINKSR_SQ0RUN_Pos (0UL) /*!< SQ0RUN (Bit 0) */ + #define R_MIPI_DSI_LINKSR_SQ0RUN_Msk (0x1UL) /*!< SQ0RUN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_LINKSR_SQ1RUN_Pos (4UL) /*!< SQ1RUN (Bit 4) */ + #define R_MIPI_DSI_LINKSR_SQ1RUN_Msk (0x10UL) /*!< SQ1RUN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_LINKSR_VRUN_Pos (8UL) /*!< VRUN (Bit 8) */ + #define R_MIPI_DSI_LINKSR_VRUN_Msk (0x100UL) /*!< VRUN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_LINKSR_HSBUSY_Pos (12UL) /*!< HSBUSY (Bit 12) */ + #define R_MIPI_DSI_LINKSR_HSBUSY_Msk (0x1000UL) /*!< HSBUSY (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_LINKSR_LPBUSY_Pos (13UL) /*!< LPBUSY (Bit 13) */ + #define R_MIPI_DSI_LINKSR_LPBUSY_Msk (0x2000UL) /*!< LPBUSY (Bitfield-Mask: 0x01) */ +/* ======================================================== TXSETR ========================================================= */ + #define R_MIPI_DSI_TXSETR_NUMLANE_Pos (0UL) /*!< NUMLANE (Bit 0) */ + #define R_MIPI_DSI_TXSETR_NUMLANE_Msk (0x3UL) /*!< NUMLANE (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_TXSETR_CLEN_Pos (8UL) /*!< CLEN (Bit 8) */ + #define R_MIPI_DSI_TXSETR_CLEN_Msk (0x100UL) /*!< CLEN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_TXSETR_DLEN_Pos (9UL) /*!< DLEN (Bit 9) */ + #define R_MIPI_DSI_TXSETR_DLEN_Msk (0x200UL) /*!< DLEN (Bitfield-Mask: 0x01) */ +/* ======================================================= HSCLKSETR ======================================================= */ + #define R_MIPI_DSI_HSCLKSETR_HSCLST_Pos (0UL) /*!< HSCLST (Bit 0) */ + #define R_MIPI_DSI_HSCLKSETR_HSCLST_Msk (0x1UL) /*!< HSCLST (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_HSCLKSETR_HSCLMD_Pos (1UL) /*!< HSCLMD (Bit 1) */ + #define R_MIPI_DSI_HSCLKSETR_HSCLMD_Msk (0x2UL) /*!< HSCLMD (Bitfield-Mask: 0x01) */ +/* ======================================================= ULPSSETR ======================================================== */ + #define R_MIPI_DSI_ULPSSETR_WKUP_Pos (0UL) /*!< WKUP (Bit 0) */ + #define R_MIPI_DSI_ULPSSETR_WKUP_Msk (0xffUL) /*!< WKUP (Bitfield-Mask: 0xff) */ +/* ======================================================== ULPSCR ========================================================= */ + #define R_MIPI_DSI_ULPSCR_CLENT_Pos (24UL) /*!< CLENT (Bit 24) */ + #define R_MIPI_DSI_ULPSCR_CLENT_Msk (0x1000000UL) /*!< CLENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ULPSCR_CLEXIT_Pos (25UL) /*!< CLEXIT (Bit 25) */ + #define R_MIPI_DSI_ULPSCR_CLEXIT_Msk (0x2000000UL) /*!< CLEXIT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ULPSCR_DLENT_Pos (28UL) /*!< DLENT (Bit 28) */ + #define R_MIPI_DSI_ULPSCR_DLENT_Msk (0x10000000UL) /*!< DLENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ULPSCR_DLEXIT_Pos (29UL) /*!< DLEXIT (Bit 29) */ + #define R_MIPI_DSI_ULPSCR_DLEXIT_Msk (0x20000000UL) /*!< DLEXIT (Bitfield-Mask: 0x01) */ +/* ========================================================= RSTCR ========================================================= */ + #define R_MIPI_DSI_RSTCR_SWRST_Pos (0UL) /*!< SWRST (Bit 0) */ + #define R_MIPI_DSI_RSTCR_SWRST_Msk (0x1UL) /*!< SWRST (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTCR_FTXSTP_Pos (16UL) /*!< FTXSTP (Bit 16) */ + #define R_MIPI_DSI_RSTCR_FTXSTP_Msk (0x10000UL) /*!< FTXSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= RSTSR ========================================================= */ + #define R_MIPI_DSI_RSTSR_RSTHS_Pos (0UL) /*!< RSTHS (Bit 0) */ + #define R_MIPI_DSI_RSTSR_RSTHS_Msk (0x1UL) /*!< RSTHS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_RSTLP_Pos (1UL) /*!< RSTLP (Bit 1) */ + #define R_MIPI_DSI_RSTSR_RSTLP_Msk (0x2UL) /*!< RSTLP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_RSTAPB_Pos (2UL) /*!< RSTAPB (Bit 2) */ + #define R_MIPI_DSI_RSTSR_RSTAPB_Msk (0x4UL) /*!< RSTAPB (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_RSTAXI_Pos (3UL) /*!< RSTAXI (Bit 3) */ + #define R_MIPI_DSI_RSTSR_RSTAXI_Msk (0x8UL) /*!< RSTAXI (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_RSTV_Pos (4UL) /*!< RSTV (Bit 4) */ + #define R_MIPI_DSI_RSTSR_RSTV_Msk (0x10UL) /*!< RSTV (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_DL0STP_Pos (8UL) /*!< DL0STP (Bit 8) */ + #define R_MIPI_DSI_RSTSR_DL0STP_Msk (0x100UL) /*!< DL0STP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_DL1STP_Pos (9UL) /*!< DL1STP (Bit 9) */ + #define R_MIPI_DSI_RSTSR_DL1STP_Msk (0x200UL) /*!< DL1STP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_DL0DIR_Pos (15UL) /*!< DL0DIR (Bit 15) */ + #define R_MIPI_DSI_RSTSR_DL0DIR_Msk (0x8000UL) /*!< DL0DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DSISETR ======================================================== */ + #define R_MIPI_DSI_DSISETR_MRPSZ_Pos (0UL) /*!< MRPSZ (Bit 0) */ + #define R_MIPI_DSI_DSISETR_MRPSZ_Msk (0xffffUL) /*!< MRPSZ (Bitfield-Mask: 0xffff) */ + #define R_MIPI_DSI_DSISETR_ECCEN_Pos (16UL) /*!< ECCEN (Bit 16) */ + #define R_MIPI_DSI_DSISETR_ECCEN_Msk (0x10000UL) /*!< ECCEN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_VC0CRCEN_Pos (20UL) /*!< VC0CRCEN (Bit 20) */ + #define R_MIPI_DSI_DSISETR_VC0CRCEN_Msk (0x100000UL) /*!< VC0CRCEN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_VC1CRCEN_Pos (21UL) /*!< VC1CRCEN (Bit 21) */ + #define R_MIPI_DSI_DSISETR_VC1CRCEN_Msk (0x200000UL) /*!< VC1CRCEN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_VC2CRCEN_Pos (22UL) /*!< VC2CRCEN (Bit 22) */ + #define R_MIPI_DSI_DSISETR_VC2CRCEN_Msk (0x400000UL) /*!< VC2CRCEN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_VC3CRCEN_Pos (23UL) /*!< VC3CRCEN (Bit 23) */ + #define R_MIPI_DSI_DSISETR_VC3CRCEN_Msk (0x800000UL) /*!< VC3CRCEN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_SCREN_Pos (29UL) /*!< SCREN (Bit 29) */ + #define R_MIPI_DSI_DSISETR_SCREN_Msk (0x20000000UL) /*!< SCREN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_EXTEMD_Pos (30UL) /*!< EXTEMD (Bit 30) */ + #define R_MIPI_DSI_DSISETR_EXTEMD_Msk (0x40000000UL) /*!< EXTEMD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_EOTPEN_Pos (31UL) /*!< EOTPEN (Bit 31) */ + #define R_MIPI_DSI_DSISETR_EOTPEN_Msk (0x80000000UL) /*!< EOTPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== TXPPD0R ======================================================== */ + #define R_MIPI_DSI_TXPPD0R_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_TXPPD0R_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD0R_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_TXPPD0R_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD0R_DATA2_Pos (16UL) /*!< DATA2 (Bit 16) */ + #define R_MIPI_DSI_TXPPD0R_DATA2_Msk (0xff0000UL) /*!< DATA2 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD0R_DATA3_Pos (24UL) /*!< DATA3 (Bit 24) */ + #define R_MIPI_DSI_TXPPD0R_DATA3_Msk (0xff000000UL) /*!< DATA3 (Bitfield-Mask: 0xff) */ +/* ======================================================== TXPPD1R ======================================================== */ + #define R_MIPI_DSI_TXPPD1R_DATA4_Pos (0UL) /*!< DATA4 (Bit 0) */ + #define R_MIPI_DSI_TXPPD1R_DATA4_Msk (0xffUL) /*!< DATA4 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD1R_DATA5_Pos (8UL) /*!< DATA5 (Bit 8) */ + #define R_MIPI_DSI_TXPPD1R_DATA5_Msk (0xff00UL) /*!< DATA5 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD1R_DATA6_Pos (16UL) /*!< DATA6 (Bit 16) */ + #define R_MIPI_DSI_TXPPD1R_DATA6_Msk (0xff0000UL) /*!< DATA6 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD1R_DATA7_Pos (24UL) /*!< DATA7 (Bit 24) */ + #define R_MIPI_DSI_TXPPD1R_DATA7_Msk (0xff000000UL) /*!< DATA7 (Bitfield-Mask: 0xff) */ +/* ======================================================== TXPPD2R ======================================================== */ + #define R_MIPI_DSI_TXPPD2R_DATA8_Pos (0UL) /*!< DATA8 (Bit 0) */ + #define R_MIPI_DSI_TXPPD2R_DATA8_Msk (0xffUL) /*!< DATA8 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD2R_DATA9_Pos (8UL) /*!< DATA9 (Bit 8) */ + #define R_MIPI_DSI_TXPPD2R_DATA9_Msk (0xff00UL) /*!< DATA9 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD2R_DATA10_Pos (16UL) /*!< DATA10 (Bit 16) */ + #define R_MIPI_DSI_TXPPD2R_DATA10_Msk (0xff0000UL) /*!< DATA10 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD2R_DATA11_Pos (24UL) /*!< DATA11 (Bit 24) */ + #define R_MIPI_DSI_TXPPD2R_DATA11_Msk (0xff000000UL) /*!< DATA11 (Bitfield-Mask: 0xff) */ +/* ======================================================== TXPPD3R ======================================================== */ + #define R_MIPI_DSI_TXPPD3R_DATA12_Pos (0UL) /*!< DATA12 (Bit 0) */ + #define R_MIPI_DSI_TXPPD3R_DATA12_Msk (0xffUL) /*!< DATA12 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD3R_DATA13_Pos (8UL) /*!< DATA13 (Bit 8) */ + #define R_MIPI_DSI_TXPPD3R_DATA13_Msk (0xff00UL) /*!< DATA13 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD3R_DATA14_Pos (16UL) /*!< DATA14 (Bit 16) */ + #define R_MIPI_DSI_TXPPD3R_DATA14_Msk (0xff0000UL) /*!< DATA14 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD3R_DATA15_Pos (24UL) /*!< DATA15 (Bit 24) */ + #define R_MIPI_DSI_TXPPD3R_DATA15_Msk (0xff000000UL) /*!< DATA15 (Bitfield-Mask: 0xff) */ +/* ========================================================= RXSR ========================================================== */ + #define R_MIPI_DSI_RXSR_BTAREND_Pos (0UL) /*!< BTAREND (Bit 0) */ + #define R_MIPI_DSI_RXSR_BTAREND_Msk (0x1UL) /*!< BTAREND (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_LRXHTO_Pos (1UL) /*!< LRXHTO (Bit 1) */ + #define R_MIPI_DSI_RXSR_LRXHTO_Msk (0x2UL) /*!< LRXHTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_TATO_Pos (2UL) /*!< TATO (Bit 2) */ + #define R_MIPI_DSI_RXSR_TATO_Msk (0x4UL) /*!< TATO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RXRESP_Pos (8UL) /*!< RXRESP (Bit 8) */ + #define R_MIPI_DSI_RXSR_RXRESP_Msk (0x100UL) /*!< RXRESP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RXEOTP_Pos (10UL) /*!< RXEOTP (Bit 10) */ + #define R_MIPI_DSI_RXSR_RXEOTP_Msk (0x400UL) /*!< RXEOTP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RXTE_Pos (13UL) /*!< RXTE (Bit 13) */ + #define R_MIPI_DSI_RXSR_RXTE_Msk (0x2000UL) /*!< RXTE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RXACK_Pos (14UL) /*!< RXACK (Bit 14) */ + #define R_MIPI_DSI_RXSR_RXACK_Msk (0x4000UL) /*!< RXACK (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_EXTEDET_Pos (15UL) /*!< EXTEDET (Bit 15) */ + #define R_MIPI_DSI_RXSR_EXTEDET_Msk (0x8000UL) /*!< EXTEDET (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_MLFERR_Pos (16UL) /*!< MLFERR (Bit 16) */ + #define R_MIPI_DSI_RXSR_MLFERR_Msk (0x10000UL) /*!< MLFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_ECCERRM_Pos (17UL) /*!< ECCERRM (Bit 17) */ + #define R_MIPI_DSI_RXSR_ECCERRM_Msk (0x20000UL) /*!< ECCERRM (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_UNEXERR_Pos (18UL) /*!< UNEXERR (Bit 18) */ + #define R_MIPI_DSI_RXSR_UNEXERR_Msk (0x40000UL) /*!< UNEXERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_WCERR_Pos (20UL) /*!< WCERR (Bit 20) */ + #define R_MIPI_DSI_RXSR_WCERR_Msk (0x100000UL) /*!< WCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_CRCERR_Pos (21UL) /*!< CRCERR (Bit 21) */ + #define R_MIPI_DSI_RXSR_CRCERR_Msk (0x200000UL) /*!< CRCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_IBERR_Pos (22UL) /*!< IBERR (Bit 22) */ + #define R_MIPI_DSI_RXSR_IBERR_Msk (0x400000UL) /*!< IBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RXOVFERR_Pos (23UL) /*!< RXOVFERR (Bit 23) */ + #define R_MIPI_DSI_RXSR_RXOVFERR_Msk (0x800000UL) /*!< RXOVFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_PRTOERR_Pos (24UL) /*!< PRTOERR (Bit 24) */ + #define R_MIPI_DSI_RXSR_PRTOERR_Msk (0x1000000UL) /*!< PRTOERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_NORESERR_Pos (25UL) /*!< NORESERR (Bit 25) */ + #define R_MIPI_DSI_RXSR_NORESERR_Msk (0x2000000UL) /*!< NORESERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RSIZEERR_Pos (26UL) /*!< RSIZEERR (Bit 26) */ + #define R_MIPI_DSI_RXSR_RSIZEERR_Msk (0x4000000UL) /*!< RSIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_ECCERRS_Pos (28UL) /*!< ECCERRS (Bit 28) */ + #define R_MIPI_DSI_RXSR_ECCERRS_Msk (0x10000000UL) /*!< ECCERRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXSR_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ========================================================= RXSCR ========================================================= */ + #define R_MIPI_DSI_RXSCR_BTAREND_Pos (0UL) /*!< BTAREND (Bit 0) */ + #define R_MIPI_DSI_RXSCR_BTAREND_Msk (0x1UL) /*!< BTAREND (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_LRXHTO_Pos (1UL) /*!< LRXHTO (Bit 1) */ + #define R_MIPI_DSI_RXSCR_LRXHTO_Msk (0x2UL) /*!< LRXHTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_TATO_Pos (2UL) /*!< TATO (Bit 2) */ + #define R_MIPI_DSI_RXSCR_TATO_Msk (0x4UL) /*!< TATO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RXRESP_Pos (8UL) /*!< RXRESP (Bit 8) */ + #define R_MIPI_DSI_RXSCR_RXRESP_Msk (0x100UL) /*!< RXRESP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RXEOTP_Pos (10UL) /*!< RXEOTP (Bit 10) */ + #define R_MIPI_DSI_RXSCR_RXEOTP_Msk (0x400UL) /*!< RXEOTP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RXTE_Pos (13UL) /*!< RXTE (Bit 13) */ + #define R_MIPI_DSI_RXSCR_RXTE_Msk (0x2000UL) /*!< RXTE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RXACK_Pos (14UL) /*!< RXACK (Bit 14) */ + #define R_MIPI_DSI_RXSCR_RXACK_Msk (0x4000UL) /*!< RXACK (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_EXTEDET_Pos (15UL) /*!< EXTEDET (Bit 15) */ + #define R_MIPI_DSI_RXSCR_EXTEDET_Msk (0x8000UL) /*!< EXTEDET (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_MLFERR_Pos (16UL) /*!< MLFERR (Bit 16) */ + #define R_MIPI_DSI_RXSCR_MLFERR_Msk (0x10000UL) /*!< MLFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_ECCERRM_Pos (17UL) /*!< ECCERRM (Bit 17) */ + #define R_MIPI_DSI_RXSCR_ECCERRM_Msk (0x20000UL) /*!< ECCERRM (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_UNEXERR_Pos (18UL) /*!< UNEXERR (Bit 18) */ + #define R_MIPI_DSI_RXSCR_UNEXERR_Msk (0x40000UL) /*!< UNEXERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_WCERR_Pos (20UL) /*!< WCERR (Bit 20) */ + #define R_MIPI_DSI_RXSCR_WCERR_Msk (0x100000UL) /*!< WCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_CRCERR_Pos (21UL) /*!< CRCERR (Bit 21) */ + #define R_MIPI_DSI_RXSCR_CRCERR_Msk (0x200000UL) /*!< CRCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_IBERR_Pos (22UL) /*!< IBERR (Bit 22) */ + #define R_MIPI_DSI_RXSCR_IBERR_Msk (0x400000UL) /*!< IBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RXOVFERR_Pos (23UL) /*!< RXOVFERR (Bit 23) */ + #define R_MIPI_DSI_RXSCR_RXOVFERR_Msk (0x800000UL) /*!< RXOVFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_PRTOERR_Pos (24UL) /*!< PRTOERR (Bit 24) */ + #define R_MIPI_DSI_RXSCR_PRTOERR_Msk (0x1000000UL) /*!< PRTOERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_NORESERR_Pos (25UL) /*!< NORESERR (Bit 25) */ + #define R_MIPI_DSI_RXSCR_NORESERR_Msk (0x2000000UL) /*!< NORESERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RSIZEERR_Pos (26UL) /*!< RSIZEERR (Bit 26) */ + #define R_MIPI_DSI_RXSCR_RSIZEERR_Msk (0x4000000UL) /*!< RSIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_ECCERRS_Pos (28UL) /*!< ECCERRS (Bit 28) */ + #define R_MIPI_DSI_RXSCR_ECCERRS_Msk (0x10000000UL) /*!< ECCERRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXSCR_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ========================================================= RXIER ========================================================= */ + #define R_MIPI_DSI_RXIER_BTAREND_Pos (0UL) /*!< BTAREND (Bit 0) */ + #define R_MIPI_DSI_RXIER_BTAREND_Msk (0x1UL) /*!< BTAREND (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_LRXHTO_Pos (1UL) /*!< LRXHTO (Bit 1) */ + #define R_MIPI_DSI_RXIER_LRXHTO_Msk (0x2UL) /*!< LRXHTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_TATO_Pos (2UL) /*!< TATO (Bit 2) */ + #define R_MIPI_DSI_RXIER_TATO_Msk (0x4UL) /*!< TATO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RXRESP_Pos (8UL) /*!< RXRESP (Bit 8) */ + #define R_MIPI_DSI_RXIER_RXRESP_Msk (0x100UL) /*!< RXRESP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RXEOTP_Pos (10UL) /*!< RXEOTP (Bit 10) */ + #define R_MIPI_DSI_RXIER_RXEOTP_Msk (0x400UL) /*!< RXEOTP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RXTE_Pos (13UL) /*!< RXTE (Bit 13) */ + #define R_MIPI_DSI_RXIER_RXTE_Msk (0x2000UL) /*!< RXTE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RXACK_Pos (14UL) /*!< RXACK (Bit 14) */ + #define R_MIPI_DSI_RXIER_RXACK_Msk (0x4000UL) /*!< RXACK (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_EXTEDET_Pos (15UL) /*!< EXTEDET (Bit 15) */ + #define R_MIPI_DSI_RXIER_EXTEDET_Msk (0x8000UL) /*!< EXTEDET (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_MLFERR_Pos (16UL) /*!< MLFERR (Bit 16) */ + #define R_MIPI_DSI_RXIER_MLFERR_Msk (0x10000UL) /*!< MLFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_ECCERRM_Pos (17UL) /*!< ECCERRM (Bit 17) */ + #define R_MIPI_DSI_RXIER_ECCERRM_Msk (0x20000UL) /*!< ECCERRM (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_UNEXERR_Pos (18UL) /*!< UNEXERR (Bit 18) */ + #define R_MIPI_DSI_RXIER_UNEXERR_Msk (0x40000UL) /*!< UNEXERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_WCERR_Pos (20UL) /*!< WCERR (Bit 20) */ + #define R_MIPI_DSI_RXIER_WCERR_Msk (0x100000UL) /*!< WCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_CRCERR_Pos (21UL) /*!< CRCERR (Bit 21) */ + #define R_MIPI_DSI_RXIER_CRCERR_Msk (0x200000UL) /*!< CRCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_IBERR_Pos (22UL) /*!< IBERR (Bit 22) */ + #define R_MIPI_DSI_RXIER_IBERR_Msk (0x400000UL) /*!< IBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RXOVFERR_Pos (23UL) /*!< RXOVFERR (Bit 23) */ + #define R_MIPI_DSI_RXIER_RXOVFERR_Msk (0x800000UL) /*!< RXOVFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_PRTOERR_Pos (24UL) /*!< PRTOERR (Bit 24) */ + #define R_MIPI_DSI_RXIER_PRTOERR_Msk (0x1000000UL) /*!< PRTOERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_NORESERR_Pos (25UL) /*!< NORESERR (Bit 25) */ + #define R_MIPI_DSI_RXIER_NORESERR_Msk (0x2000000UL) /*!< NORESERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RSIZEERR_Pos (26UL) /*!< RSIZEERR (Bit 26) */ + #define R_MIPI_DSI_RXIER_RSIZEERR_Msk (0x4000000UL) /*!< RSIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_ECCERRS_Pos (28UL) /*!< ECCERRS (Bit 28) */ + #define R_MIPI_DSI_RXIER_ECCERRS_Msk (0x10000000UL) /*!< ECCERRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXIER_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ==================================================== PRESPTOBTASETR ===================================================== */ + #define R_MIPI_DSI_PRESPTOBTASETR_PRTBTA_Pos (0UL) /*!< PRTBTA (Bit 0) */ + #define R_MIPI_DSI_PRESPTOBTASETR_PRTBTA_Msk (0xffffffffUL) /*!< PRTBTA (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== PRESPTOLPSETR ===================================================== */ + #define R_MIPI_DSI_PRESPTOLPSETR_LPWTO_Pos (0UL) /*!< LPWTO (Bit 0) */ + #define R_MIPI_DSI_PRESPTOLPSETR_LPWTO_Msk (0xffffUL) /*!< LPWTO (Bitfield-Mask: 0xffff) */ + #define R_MIPI_DSI_PRESPTOLPSETR_LPRTO_Pos (16UL) /*!< LPRTO (Bit 16) */ + #define R_MIPI_DSI_PRESPTOLPSETR_LPRTO_Msk (0xffff0000UL) /*!< LPRTO (Bitfield-Mask: 0xffff) */ +/* ===================================================== PRESPTOHSSETR ===================================================== */ + #define R_MIPI_DSI_PRESPTOHSSETR_HSWTO_Pos (0UL) /*!< HSWTO (Bit 0) */ + #define R_MIPI_DSI_PRESPTOHSSETR_HSWTO_Msk (0xffffUL) /*!< HSWTO (Bitfield-Mask: 0xffff) */ + #define R_MIPI_DSI_PRESPTOHSSETR_HSRTO_Pos (16UL) /*!< HSRTO (Bit 16) */ + #define R_MIPI_DSI_PRESPTOHSSETR_HSRTO_Msk (0xffff0000UL) /*!< HSRTO (Bitfield-Mask: 0xffff) */ +/* ======================================================= AKEPLATIR ======================================================= */ + #define R_MIPI_DSI_AKEPLATIR_EREP_Pos (0UL) /*!< EREP (Bit 0) */ + #define R_MIPI_DSI_AKEPLATIR_EREP_Msk (0xffffUL) /*!< EREP (Bitfield-Mask: 0xffff) */ + #define R_MIPI_DSI_AKEPLATIR_VC_Pos (16UL) /*!< VC (Bit 16) */ + #define R_MIPI_DSI_AKEPLATIR_VC_Msk (0xf0000UL) /*!< VC (Bitfield-Mask: 0x0f) */ +/* ======================================================= AKEPACMSR ======================================================= */ + #define R_MIPI_DSI_AKEPACMSR_AEREP_Pos (0UL) /*!< AEREP (Bit 0) */ + #define R_MIPI_DSI_AKEPACMSR_AEREP_Msk (0xffffUL) /*!< AEREP (Bitfield-Mask: 0xffff) */ + #define R_MIPI_DSI_AKEPACMSR_AVC_Pos (16UL) /*!< AVC (Bit 16) */ + #define R_MIPI_DSI_AKEPACMSR_AVC_Msk (0xf0000UL) /*!< AVC (Bitfield-Mask: 0x0f) */ +/* ======================================================== AKEPSCR ======================================================== */ + #define R_MIPI_DSI_AKEPSCR_AEREP_Pos (0UL) /*!< AEREP (Bit 0) */ + #define R_MIPI_DSI_AKEPSCR_AEREP_Msk (0xffffUL) /*!< AEREP (Bitfield-Mask: 0xffff) */ + #define R_MIPI_DSI_AKEPSCR_AVC_Pos (16UL) /*!< AVC (Bit 16) */ + #define R_MIPI_DSI_AKEPSCR_AVC_Msk (0xf0000UL) /*!< AVC (Bitfield-Mask: 0x0f) */ +/* ======================================================== RXRSSR ========================================================= */ + #define R_MIPI_DSI_RXRSSR_SLT0VLD_Pos (0UL) /*!< SLT0VLD (Bit 0) */ + #define R_MIPI_DSI_RXRSSR_SLT0VLD_Msk (0x1UL) /*!< SLT0VLD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSSR_SLT1VLD_Pos (1UL) /*!< SLT1VLD (Bit 1) */ + #define R_MIPI_DSI_RXRSSR_SLT1VLD_Msk (0x2UL) /*!< SLT1VLD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSSR_SLT2VLD_Pos (2UL) /*!< SLT2VLD (Bit 2) */ + #define R_MIPI_DSI_RXRSSR_SLT2VLD_Msk (0x4UL) /*!< SLT2VLD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSSR_SLT3VLD_Pos (3UL) /*!< SLT3VLD (Bit 3) */ + #define R_MIPI_DSI_RXRSSR_SLT3VLD_Msk (0x8UL) /*!< SLT3VLD (Bitfield-Mask: 0x01) */ +/* ======================================================== RXRSSCR ======================================================== */ + #define R_MIPI_DSI_RXRSSCR_SLT0VLD_Pos (0UL) /*!< SLT0VLD (Bit 0) */ + #define R_MIPI_DSI_RXRSSCR_SLT0VLD_Msk (0x1UL) /*!< SLT0VLD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSSCR_SLT1VLD_Pos (1UL) /*!< SLT1VLD (Bit 1) */ + #define R_MIPI_DSI_RXRSSCR_SLT1VLD_Msk (0x2UL) /*!< SLT1VLD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSSCR_SLT2VLD_Pos (2UL) /*!< SLT2VLD (Bit 2) */ + #define R_MIPI_DSI_RXRSSCR_SLT2VLD_Msk (0x4UL) /*!< SLT2VLD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSSCR_SLT3VLD_Pos (3UL) /*!< SLT3VLD (Bit 3) */ + #define R_MIPI_DSI_RXRSSCR_SLT3VLD_Msk (0x8UL) /*!< SLT3VLD (Bitfield-Mask: 0x01) */ +/* ====================================================== RXRINFOOWSR ====================================================== */ + #define R_MIPI_DSI_RXRINFOOWSR_SL0OW_Pos (0UL) /*!< SL0OW (Bit 0) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL0OW_Msk (0x1UL) /*!< SL0OW (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL1OW_Pos (1UL) /*!< SL1OW (Bit 1) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL1OW_Msk (0x2UL) /*!< SL1OW (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL2OW_Pos (2UL) /*!< SL2OW (Bit 2) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL2OW_Msk (0x4UL) /*!< SL2OW (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL3OW_Pos (3UL) /*!< SL3OW (Bit 3) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL3OW_Msk (0x8UL) /*!< SL3OW (Bitfield-Mask: 0x01) */ +/* ===================================================== RXRINFOOWSCR ====================================================== */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL0OW_Pos (0UL) /*!< SL0OW (Bit 0) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL0OW_Msk (0x1UL) /*!< SL0OW (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL1OW_Pos (1UL) /*!< SL1OW (Bit 1) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL1OW_Msk (0x2UL) /*!< SL1OW (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL2OW_Pos (2UL) /*!< SL2OW (Bit 2) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL2OW_Msk (0x4UL) /*!< SL2OW (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL3OW_Pos (3UL) /*!< SL3OW (Bit 3) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL3OW_Msk (0x8UL) /*!< SL3OW (Bitfield-Mask: 0x01) */ +/* ======================================================== RXRSS0R ======================================================== */ + #define R_MIPI_DSI_RXRSS0R_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS0R_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS0R_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS0R_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_RXRSS0R_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS0R_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_RXRSS0R_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS0R_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_RXRSS0R_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_RXSUC_Pos (25UL) /*!< RXSUC (Bit 25) */ + #define R_MIPI_DSI_RXRSS0R_RXSUC_Msk (0x2000000UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_RXRSS0R_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_RXRSS0R_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_RXRSS0R_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_RXCERR_Pos (29UL) /*!< RXCERR (Bit 29) */ + #define R_MIPI_DSI_RXRSS0R_RXCERR_Msk (0x20000000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXRSS0R_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_INFOOW_Pos (31UL) /*!< INFOOW (Bit 31) */ + #define R_MIPI_DSI_RXRSS0R_INFOOW_Msk (0x80000000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================== RXRSS1R ======================================================== */ + #define R_MIPI_DSI_RXRSS1R_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS1R_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS1R_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS1R_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_RXRSS1R_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS1R_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_RXRSS1R_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS1R_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_RXRSS1R_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_RXSUC_Pos (25UL) /*!< RXSUC (Bit 25) */ + #define R_MIPI_DSI_RXRSS1R_RXSUC_Msk (0x2000000UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_RXRSS1R_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_RXRSS1R_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_RXRSS1R_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_RXCERR_Pos (29UL) /*!< RXCERR (Bit 29) */ + #define R_MIPI_DSI_RXRSS1R_RXCERR_Msk (0x20000000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXRSS1R_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_INFOOW_Pos (31UL) /*!< INFOOW (Bit 31) */ + #define R_MIPI_DSI_RXRSS1R_INFOOW_Msk (0x80000000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================== RXRSS2R ======================================================== */ + #define R_MIPI_DSI_RXRSS2R_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS2R_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS2R_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS2R_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_RXRSS2R_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS2R_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_RXRSS2R_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS2R_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_RXRSS2R_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_RXSUC_Pos (25UL) /*!< RXSUC (Bit 25) */ + #define R_MIPI_DSI_RXRSS2R_RXSUC_Msk (0x2000000UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_RXRSS2R_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_RXRSS2R_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_RXRSS2R_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_RXCERR_Pos (29UL) /*!< RXCERR (Bit 29) */ + #define R_MIPI_DSI_RXRSS2R_RXCERR_Msk (0x20000000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXRSS2R_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_INFOOW_Pos (31UL) /*!< INFOOW (Bit 31) */ + #define R_MIPI_DSI_RXRSS2R_INFOOW_Msk (0x80000000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================== RXRSS3R ======================================================== */ + #define R_MIPI_DSI_RXRSS3R_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS3R_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS3R_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS3R_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_RXRSS3R_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS3R_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_RXRSS3R_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS3R_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_RXRSS3R_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_RXSUC_Pos (25UL) /*!< RXSUC (Bit 25) */ + #define R_MIPI_DSI_RXRSS3R_RXSUC_Msk (0x2000000UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_RXRSS3R_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_RXRSS3R_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_RXRSS3R_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_RXCERR_Pos (29UL) /*!< RXCERR (Bit 29) */ + #define R_MIPI_DSI_RXRSS3R_RXCERR_Msk (0x20000000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXRSS3R_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_INFOOW_Pos (31UL) /*!< INFOOW (Bit 31) */ + #define R_MIPI_DSI_RXRSS3R_INFOOW_Msk (0x80000000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================= RXRSS0R_L ======================================================= */ + #define R_MIPI_DSI_RXRSS0R_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS0R_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS0R_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ======================================================= RXRSS1R_L ======================================================= */ + #define R_MIPI_DSI_RXRSS1R_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS1R_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS1R_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ======================================================= RXRSS2R_L ======================================================= */ + #define R_MIPI_DSI_RXRSS2R_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS2R_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS2R_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ======================================================= RXRSS3R_L ======================================================= */ + #define R_MIPI_DSI_RXRSS3R_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS3R_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS3R_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS0R_LL ======================================================= */ + #define R_MIPI_DSI_RXRSS0R_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS1R_LL ======================================================= */ + #define R_MIPI_DSI_RXRSS1R_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS2R_LL ======================================================= */ + #define R_MIPI_DSI_RXRSS2R_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS3R_LL ======================================================= */ + #define R_MIPI_DSI_RXRSS3R_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS0R_LH ======================================================= */ + #define R_MIPI_DSI_RXRSS0R_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS1R_LH ======================================================= */ + #define R_MIPI_DSI_RXRSS1R_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS2R_LH ======================================================= */ + #define R_MIPI_DSI_RXRSS2R_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS3R_LH ======================================================= */ + #define R_MIPI_DSI_RXRSS3R_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ======================================================= RXRSS0R_H ======================================================= */ + #define R_MIPI_DSI_RXRSS0R_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS0R_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS0R_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS0R_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_RXRSS0R_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_RXSUC_Pos (9UL) /*!< RXSUC (Bit 9) */ + #define R_MIPI_DSI_RXRSS0R_H_RXSUC_Msk (0x200UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_RXFERR_Pos (10UL) /*!< RXFERR (Bit 10) */ + #define R_MIPI_DSI_RXRSS0R_H_RXFERR_Msk (0x400UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_RXFAIL_Pos (11UL) /*!< RXFAIL (Bit 11) */ + #define R_MIPI_DSI_RXRSS0R_H_RXFAIL_Msk (0x800UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_RXPFAIL_Pos (12UL) /*!< RXPFAIL (Bit 12) */ + #define R_MIPI_DSI_RXRSS0R_H_RXPFAIL_Msk (0x1000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_RXCERR_Pos (13UL) /*!< RXCERR (Bit 13) */ + #define R_MIPI_DSI_RXRSS0R_H_RXCERR_Msk (0x2000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_RXAKE_Pos (14UL) /*!< RXAKE (Bit 14) */ + #define R_MIPI_DSI_RXRSS0R_H_RXAKE_Msk (0x4000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_INFOOW_Pos (15UL) /*!< INFOOW (Bit 15) */ + #define R_MIPI_DSI_RXRSS0R_H_INFOOW_Msk (0x8000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================= RXRSS1R_H ======================================================= */ + #define R_MIPI_DSI_RXRSS1R_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS1R_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS1R_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS1R_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_RXRSS1R_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_RXSUC_Pos (9UL) /*!< RXSUC (Bit 9) */ + #define R_MIPI_DSI_RXRSS1R_H_RXSUC_Msk (0x200UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_RXFERR_Pos (10UL) /*!< RXFERR (Bit 10) */ + #define R_MIPI_DSI_RXRSS1R_H_RXFERR_Msk (0x400UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_RXFAIL_Pos (11UL) /*!< RXFAIL (Bit 11) */ + #define R_MIPI_DSI_RXRSS1R_H_RXFAIL_Msk (0x800UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_RXPFAIL_Pos (12UL) /*!< RXPFAIL (Bit 12) */ + #define R_MIPI_DSI_RXRSS1R_H_RXPFAIL_Msk (0x1000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_RXCERR_Pos (13UL) /*!< RXCERR (Bit 13) */ + #define R_MIPI_DSI_RXRSS1R_H_RXCERR_Msk (0x2000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_RXAKE_Pos (14UL) /*!< RXAKE (Bit 14) */ + #define R_MIPI_DSI_RXRSS1R_H_RXAKE_Msk (0x4000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_INFOOW_Pos (15UL) /*!< INFOOW (Bit 15) */ + #define R_MIPI_DSI_RXRSS1R_H_INFOOW_Msk (0x8000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================= RXRSS2R_H ======================================================= */ + #define R_MIPI_DSI_RXRSS2R_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS2R_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS2R_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS2R_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_RXRSS2R_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_RXSUC_Pos (9UL) /*!< RXSUC (Bit 9) */ + #define R_MIPI_DSI_RXRSS2R_H_RXSUC_Msk (0x200UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_RXFERR_Pos (10UL) /*!< RXFERR (Bit 10) */ + #define R_MIPI_DSI_RXRSS2R_H_RXFERR_Msk (0x400UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_RXFAIL_Pos (11UL) /*!< RXFAIL (Bit 11) */ + #define R_MIPI_DSI_RXRSS2R_H_RXFAIL_Msk (0x800UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_RXPFAIL_Pos (12UL) /*!< RXPFAIL (Bit 12) */ + #define R_MIPI_DSI_RXRSS2R_H_RXPFAIL_Msk (0x1000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_RXCERR_Pos (13UL) /*!< RXCERR (Bit 13) */ + #define R_MIPI_DSI_RXRSS2R_H_RXCERR_Msk (0x2000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_RXAKE_Pos (14UL) /*!< RXAKE (Bit 14) */ + #define R_MIPI_DSI_RXRSS2R_H_RXAKE_Msk (0x4000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_INFOOW_Pos (15UL) /*!< INFOOW (Bit 15) */ + #define R_MIPI_DSI_RXRSS2R_H_INFOOW_Msk (0x8000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================= RXRSS3R_H ======================================================= */ + #define R_MIPI_DSI_RXRSS3R_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS3R_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS3R_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS3R_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_RXRSS3R_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_RXSUC_Pos (9UL) /*!< RXSUC (Bit 9) */ + #define R_MIPI_DSI_RXRSS3R_H_RXSUC_Msk (0x200UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_RXFERR_Pos (10UL) /*!< RXFERR (Bit 10) */ + #define R_MIPI_DSI_RXRSS3R_H_RXFERR_Msk (0x400UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_RXFAIL_Pos (11UL) /*!< RXFAIL (Bit 11) */ + #define R_MIPI_DSI_RXRSS3R_H_RXFAIL_Msk (0x800UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_RXPFAIL_Pos (12UL) /*!< RXPFAIL (Bit 12) */ + #define R_MIPI_DSI_RXRSS3R_H_RXPFAIL_Msk (0x1000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_RXCERR_Pos (13UL) /*!< RXCERR (Bit 13) */ + #define R_MIPI_DSI_RXRSS3R_H_RXCERR_Msk (0x2000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_RXAKE_Pos (14UL) /*!< RXAKE (Bit 14) */ + #define R_MIPI_DSI_RXRSS3R_H_RXAKE_Msk (0x4000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_INFOOW_Pos (15UL) /*!< INFOOW (Bit 15) */ + #define R_MIPI_DSI_RXRSS3R_H_INFOOW_Msk (0x8000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ====================================================== RXRSS0R_HL ======================================================= */ + #define R_MIPI_DSI_RXRSS0R_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS0R_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS0R_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ====================================================== RXRSS1R_HL ======================================================= */ + #define R_MIPI_DSI_RXRSS1R_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS1R_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS1R_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ====================================================== RXRSS2R_HL ======================================================= */ + #define R_MIPI_DSI_RXRSS2R_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS2R_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS2R_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ====================================================== RXRSS3R_HL ======================================================= */ + #define R_MIPI_DSI_RXRSS3R_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS3R_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS3R_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ====================================================== RXRSS0R_HH ======================================================= */ + #define R_MIPI_DSI_RXRSS0R_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXSUC_Pos (1UL) /*!< RXSUC (Bit 1) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXSUC_Msk (0x2UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXFERR_Pos (2UL) /*!< RXFERR (Bit 2) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXFERR_Msk (0x4UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXFAIL_Pos (3UL) /*!< RXFAIL (Bit 3) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXFAIL_Msk (0x8UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXPFAIL_Pos (4UL) /*!< RXPFAIL (Bit 4) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXPFAIL_Msk (0x10UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXCERR_Pos (5UL) /*!< RXCERR (Bit 5) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXCERR_Msk (0x20UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXAKE_Pos (6UL) /*!< RXAKE (Bit 6) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXAKE_Msk (0x40UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_INFOOW_Pos (7UL) /*!< INFOOW (Bit 7) */ + #define R_MIPI_DSI_RXRSS0R_HH_INFOOW_Msk (0x80UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ====================================================== RXRSS1R_HH ======================================================= */ + #define R_MIPI_DSI_RXRSS1R_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXSUC_Pos (1UL) /*!< RXSUC (Bit 1) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXSUC_Msk (0x2UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXFERR_Pos (2UL) /*!< RXFERR (Bit 2) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXFERR_Msk (0x4UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXFAIL_Pos (3UL) /*!< RXFAIL (Bit 3) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXFAIL_Msk (0x8UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXPFAIL_Pos (4UL) /*!< RXPFAIL (Bit 4) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXPFAIL_Msk (0x10UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXCERR_Pos (5UL) /*!< RXCERR (Bit 5) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXCERR_Msk (0x20UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXAKE_Pos (6UL) /*!< RXAKE (Bit 6) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXAKE_Msk (0x40UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_INFOOW_Pos (7UL) /*!< INFOOW (Bit 7) */ + #define R_MIPI_DSI_RXRSS1R_HH_INFOOW_Msk (0x80UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ====================================================== RXRSS2R_HH ======================================================= */ + #define R_MIPI_DSI_RXRSS2R_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXSUC_Pos (1UL) /*!< RXSUC (Bit 1) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXSUC_Msk (0x2UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXFERR_Pos (2UL) /*!< RXFERR (Bit 2) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXFERR_Msk (0x4UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXFAIL_Pos (3UL) /*!< RXFAIL (Bit 3) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXFAIL_Msk (0x8UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXPFAIL_Pos (4UL) /*!< RXPFAIL (Bit 4) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXPFAIL_Msk (0x10UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXCERR_Pos (5UL) /*!< RXCERR (Bit 5) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXCERR_Msk (0x20UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXAKE_Pos (6UL) /*!< RXAKE (Bit 6) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXAKE_Msk (0x40UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_INFOOW_Pos (7UL) /*!< INFOOW (Bit 7) */ + #define R_MIPI_DSI_RXRSS2R_HH_INFOOW_Msk (0x80UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ====================================================== RXRSS3R_HH ======================================================= */ + #define R_MIPI_DSI_RXRSS3R_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXSUC_Pos (1UL) /*!< RXSUC (Bit 1) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXSUC_Msk (0x2UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXFERR_Pos (2UL) /*!< RXFERR (Bit 2) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXFERR_Msk (0x4UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXFAIL_Pos (3UL) /*!< RXFAIL (Bit 3) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXFAIL_Msk (0x8UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXPFAIL_Pos (4UL) /*!< RXPFAIL (Bit 4) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXPFAIL_Msk (0x10UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXCERR_Pos (5UL) /*!< RXCERR (Bit 5) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXCERR_Msk (0x20UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXAKE_Pos (6UL) /*!< RXAKE (Bit 6) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXAKE_Msk (0x40UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_INFOOW_Pos (7UL) /*!< INFOOW (Bit 7) */ + #define R_MIPI_DSI_RXRSS3R_HH_INFOOW_Msk (0x80UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================== RXPPD0R ======================================================== */ + #define R_MIPI_DSI_RXPPD0R_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXPPD0R_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD0R_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXPPD0R_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD0R_DATA2_Pos (16UL) /*!< DATA2 (Bit 16) */ + #define R_MIPI_DSI_RXPPD0R_DATA2_Msk (0xff0000UL) /*!< DATA2 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD0R_DATA3_Pos (24UL) /*!< DATA3 (Bit 24) */ + #define R_MIPI_DSI_RXPPD0R_DATA3_Msk (0xff000000UL) /*!< DATA3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RXPPD1R ======================================================== */ + #define R_MIPI_DSI_RXPPD1R_DATA4_Pos (0UL) /*!< DATA4 (Bit 0) */ + #define R_MIPI_DSI_RXPPD1R_DATA4_Msk (0xffUL) /*!< DATA4 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD1R_DATA5_Pos (8UL) /*!< DATA5 (Bit 8) */ + #define R_MIPI_DSI_RXPPD1R_DATA5_Msk (0xff00UL) /*!< DATA5 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD1R_DATA6_Pos (16UL) /*!< DATA6 (Bit 16) */ + #define R_MIPI_DSI_RXPPD1R_DATA6_Msk (0xff0000UL) /*!< DATA6 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD1R_DATA7_Pos (24UL) /*!< DATA7 (Bit 24) */ + #define R_MIPI_DSI_RXPPD1R_DATA7_Msk (0xff000000UL) /*!< DATA7 (Bitfield-Mask: 0xff) */ +/* ======================================================== RXPPD2R ======================================================== */ + #define R_MIPI_DSI_RXPPD2R_DATA8_Pos (0UL) /*!< DATA8 (Bit 0) */ + #define R_MIPI_DSI_RXPPD2R_DATA8_Msk (0xffUL) /*!< DATA8 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD2R_DATA9_Pos (8UL) /*!< DATA9 (Bit 8) */ + #define R_MIPI_DSI_RXPPD2R_DATA9_Msk (0xff00UL) /*!< DATA9 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD2R_DATA10_Pos (16UL) /*!< DATA10 (Bit 16) */ + #define R_MIPI_DSI_RXPPD2R_DATA10_Msk (0xff0000UL) /*!< DATA10 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD2R_DATA11_Pos (24UL) /*!< DATA11 (Bit 24) */ + #define R_MIPI_DSI_RXPPD2R_DATA11_Msk (0xff000000UL) /*!< DATA11 (Bitfield-Mask: 0xff) */ +/* ======================================================== RXPPD3R ======================================================== */ + #define R_MIPI_DSI_RXPPD3R_DATA12_Pos (0UL) /*!< DATA12 (Bit 0) */ + #define R_MIPI_DSI_RXPPD3R_DATA12_Msk (0xffUL) /*!< DATA12 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD3R_DATA13_Pos (8UL) /*!< DATA13 (Bit 8) */ + #define R_MIPI_DSI_RXPPD3R_DATA13_Msk (0xff00UL) /*!< DATA13 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD3R_DATA14_Pos (16UL) /*!< DATA14 (Bit 16) */ + #define R_MIPI_DSI_RXPPD3R_DATA14_Msk (0xff0000UL) /*!< DATA14 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD3R_DATA15_Pos (24UL) /*!< DATA15 (Bit 24) */ + #define R_MIPI_DSI_RXPPD3R_DATA15_Msk (0xff000000UL) /*!< DATA15 (Bitfield-Mask: 0xff) */ +/* ====================================================== HSTXTOSETR ======================================================= */ + #define R_MIPI_DSI_HSTXTOSETR_HTXTO_Pos (0UL) /*!< HTXTO (Bit 0) */ + #define R_MIPI_DSI_HSTXTOSETR_HTXTO_Msk (0xffffffffUL) /*!< HTXTO (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== LRXHTOSETR ======================================================= */ + #define R_MIPI_DSI_LRXHTOSETR_LRXHTO_Pos (0UL) /*!< LRXHTO (Bit 0) */ + #define R_MIPI_DSI_LRXHTOSETR_LRXHTO_Msk (0xffffffffUL) /*!< LRXHTO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TATOSETR ======================================================== */ + #define R_MIPI_DSI_TATOSETR_TATO_Pos (0UL) /*!< TATO (Bit 0) */ + #define R_MIPI_DSI_TATOSETR_TATO_Msk (0xffffffffUL) /*!< TATO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FERRSR ========================================================= */ + #define R_MIPI_DSI_FERRSR_HTXTO_Pos (0UL) /*!< HTXTO (Bit 0) */ + #define R_MIPI_DSI_FERRSR_HTXTO_Msk (0x1UL) /*!< HTXTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_LRXHTO_Pos (1UL) /*!< LRXHTO (Bit 1) */ + #define R_MIPI_DSI_FERRSR_LRXHTO_Msk (0x2UL) /*!< LRXHTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_TATO_Pos (2UL) /*!< TATO (Bit 2) */ + #define R_MIPI_DSI_FERRSR_TATO_Msk (0x4UL) /*!< TATO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_ESCENT_Pos (16UL) /*!< ESCENT (Bit 16) */ + #define R_MIPI_DSI_FERRSR_ESCENT_Msk (0x10000UL) /*!< ESCENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_SYNCESC_Pos (17UL) /*!< SYNCESC (Bit 17) */ + #define R_MIPI_DSI_FERRSR_SYNCESC_Msk (0x20000UL) /*!< SYNCESC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_CTRL_Pos (18UL) /*!< CTRL (Bit 18) */ + #define R_MIPI_DSI_FERRSR_CTRL_Msk (0x40000UL) /*!< CTRL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_CLP0_Pos (19UL) /*!< CLP0 (Bit 19) */ + #define R_MIPI_DSI_FERRSR_CLP0_Msk (0x80000UL) /*!< CLP0 (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_CLP1_Pos (20UL) /*!< CLP1 (Bit 20) */ + #define R_MIPI_DSI_FERRSR_CLP1_Msk (0x100000UL) /*!< CLP1 (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_CLP0S_Pos (27UL) /*!< CLP0S (Bit 27) */ + #define R_MIPI_DSI_FERRSR_CLP0S_Msk (0x8000000UL) /*!< CLP0S (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_CLP1S_Pos (28UL) /*!< CLP1S (Bit 28) */ + #define R_MIPI_DSI_FERRSR_CLP1S_Msk (0x10000000UL) /*!< CLP1S (Bitfield-Mask: 0x01) */ +/* ======================================================== FERRSCR ======================================================== */ + #define R_MIPI_DSI_FERRSCR_HTXTO_Pos (0UL) /*!< HTXTO (Bit 0) */ + #define R_MIPI_DSI_FERRSCR_HTXTO_Msk (0x1UL) /*!< HTXTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_LRXHTO_Pos (1UL) /*!< LRXHTO (Bit 1) */ + #define R_MIPI_DSI_FERRSCR_LRXHTO_Msk (0x2UL) /*!< LRXHTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_TATO_Pos (2UL) /*!< TATO (Bit 2) */ + #define R_MIPI_DSI_FERRSCR_TATO_Msk (0x4UL) /*!< TATO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_ESCENT_Pos (16UL) /*!< ESCENT (Bit 16) */ + #define R_MIPI_DSI_FERRSCR_ESCENT_Msk (0x10000UL) /*!< ESCENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_SYNCESC_Pos (17UL) /*!< SYNCESC (Bit 17) */ + #define R_MIPI_DSI_FERRSCR_SYNCESC_Msk (0x20000UL) /*!< SYNCESC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_CTRL_Pos (18UL) /*!< CTRL (Bit 18) */ + #define R_MIPI_DSI_FERRSCR_CTRL_Msk (0x40000UL) /*!< CTRL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_CLP0_Pos (19UL) /*!< CLP0 (Bit 19) */ + #define R_MIPI_DSI_FERRSCR_CLP0_Msk (0x80000UL) /*!< CLP0 (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_CLP1_Pos (20UL) /*!< CLP1 (Bit 20) */ + #define R_MIPI_DSI_FERRSCR_CLP1_Msk (0x100000UL) /*!< CLP1 (Bitfield-Mask: 0x01) */ +/* ======================================================== FERRIER ======================================================== */ + #define R_MIPI_DSI_FERRIER_HTXTO_Pos (0UL) /*!< HTXTO (Bit 0) */ + #define R_MIPI_DSI_FERRIER_HTXTO_Msk (0x1UL) /*!< HTXTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_LRXHTO_Pos (1UL) /*!< LRXHTO (Bit 1) */ + #define R_MIPI_DSI_FERRIER_LRXHTO_Msk (0x2UL) /*!< LRXHTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_TATO_Pos (2UL) /*!< TATO (Bit 2) */ + #define R_MIPI_DSI_FERRIER_TATO_Msk (0x4UL) /*!< TATO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_ESCENT_Pos (16UL) /*!< ESCENT (Bit 16) */ + #define R_MIPI_DSI_FERRIER_ESCENT_Msk (0x10000UL) /*!< ESCENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_SYNCESC_Pos (17UL) /*!< SYNCESC (Bit 17) */ + #define R_MIPI_DSI_FERRIER_SYNCESC_Msk (0x20000UL) /*!< SYNCESC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_CTRL_Pos (18UL) /*!< CTRL (Bit 18) */ + #define R_MIPI_DSI_FERRIER_CTRL_Msk (0x40000UL) /*!< CTRL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_CLP0_Pos (19UL) /*!< CLP0 (Bit 19) */ + #define R_MIPI_DSI_FERRIER_CLP0_Msk (0x80000UL) /*!< CLP0 (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_CLP1_Pos (20UL) /*!< CLP1 (Bit 20) */ + #define R_MIPI_DSI_FERRIER_CLP1_Msk (0x100000UL) /*!< CLP1 (Bitfield-Mask: 0x01) */ +/* ====================================================== CLSTPTSETR ======================================================= */ + #define R_MIPI_DSI_CLSTPTSETR_CLKSTPT_Pos (2UL) /*!< CLKSTPT (Bit 2) */ + #define R_MIPI_DSI_CLSTPTSETR_CLKSTPT_Msk (0xffcUL) /*!< CLKSTPT (Bitfield-Mask: 0x3ff) */ + #define R_MIPI_DSI_CLSTPTSETR_CLKBFHT_Pos (16UL) /*!< CLKBFHT (Bit 16) */ + #define R_MIPI_DSI_CLSTPTSETR_CLKBFHT_Msk (0xff0000UL) /*!< CLKBFHT (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_CLSTPTSETR_CLKKPT_Pos (24UL) /*!< CLKKPT (Bit 24) */ + #define R_MIPI_DSI_CLSTPTSETR_CLKKPT_Msk (0xff000000UL) /*!< CLKKPT (Bitfield-Mask: 0xff) */ +/* ====================================================== LPTRNSTSETR ====================================================== */ + #define R_MIPI_DSI_LPTRNSTSETR_GOLPBKT_Pos (0UL) /*!< GOLPBKT (Bit 0) */ + #define R_MIPI_DSI_LPTRNSTSETR_GOLPBKT_Msk (0x3ffUL) /*!< GOLPBKT (Bitfield-Mask: 0x3ff) */ +/* ========================================================= PLSR ========================================================== */ + #define R_MIPI_DSI_PLSR_CLUAN_Pos (0UL) /*!< CLUAN (Bit 0) */ + #define R_MIPI_DSI_PLSR_CLUAN_Msk (0x1UL) /*!< CLUAN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_CLSTP_Pos (1UL) /*!< CLSTP (Bit 1) */ + #define R_MIPI_DSI_PLSR_CLSTP_Msk (0x2UL) /*!< CLSTP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0RLE_Pos (2UL) /*!< DL0RLE (Bit 2) */ + #define R_MIPI_DSI_PLSR_DL0RLE_Msk (0x4UL) /*!< DL0RLE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0RUE_Pos (3UL) /*!< DL0RUE (Bit 3) */ + #define R_MIPI_DSI_PLSR_DL0RUE_Msk (0x8UL) /*!< DL0RUE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0UAN_Pos (4UL) /*!< DL0UAN (Bit 4) */ + #define R_MIPI_DSI_PLSR_DL0UAN_Msk (0x10UL) /*!< DL0UAN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL1UAN_Pos (5UL) /*!< DL1UAN (Bit 5) */ + #define R_MIPI_DSI_PLSR_DL1UAN_Msk (0x20UL) /*!< DL1UAN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0STP_Pos (8UL) /*!< DL0STP (Bit 8) */ + #define R_MIPI_DSI_PLSR_DL0STP_Msk (0x100UL) /*!< DL0STP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL1STP_Pos (9UL) /*!< DL1STP (Bit 9) */ + #define R_MIPI_DSI_PLSR_DL1STP_Msk (0x200UL) /*!< DL1STP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0RX2TX_Pos (12UL) /*!< DL0RX2TX (Bit 12) */ + #define R_MIPI_DSI_PLSR_DL0RX2TX_Msk (0x1000UL) /*!< DL0RX2TX (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0TX2RX_Pos (13UL) /*!< DL0TX2RX (Bit 13) */ + #define R_MIPI_DSI_PLSR_DL0TX2RX_Msk (0x2000UL) /*!< DL0TX2RX (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0DIR_Pos (15UL) /*!< DL0DIR (Bit 15) */ + #define R_MIPI_DSI_PLSR_DL0DIR_Msk (0x8000UL) /*!< DL0DIR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_CLULPENT_Pos (24UL) /*!< CLULPENT (Bit 24) */ + #define R_MIPI_DSI_PLSR_CLULPENT_Msk (0x1000000UL) /*!< CLULPENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_CLULPEXT_Pos (25UL) /*!< CLULPEXT (Bit 25) */ + #define R_MIPI_DSI_PLSR_CLULPEXT_Msk (0x2000000UL) /*!< CLULPEXT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_CLLP2HS_Pos (26UL) /*!< CLLP2HS (Bit 26) */ + #define R_MIPI_DSI_PLSR_CLLP2HS_Msk (0x4000000UL) /*!< CLLP2HS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_CLHS2LP_Pos (27UL) /*!< CLHS2LP (Bit 27) */ + #define R_MIPI_DSI_PLSR_CLHS2LP_Msk (0x8000000UL) /*!< CLHS2LP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DLULPENT_Pos (28UL) /*!< DLULPENT (Bit 28) */ + #define R_MIPI_DSI_PLSR_DLULPENT_Msk (0x10000000UL) /*!< DLULPENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DLULPEXT_Pos (29UL) /*!< DLULPEXT (Bit 29) */ + #define R_MIPI_DSI_PLSR_DLULPEXT_Msk (0x20000000UL) /*!< DLULPEXT (Bitfield-Mask: 0x01) */ +/* ========================================================= PLSCR ========================================================= */ + #define R_MIPI_DSI_PLSCR_DL0RX2TX_Pos (12UL) /*!< DL0RX2TX (Bit 12) */ + #define R_MIPI_DSI_PLSCR_DL0RX2TX_Msk (0x1000UL) /*!< DL0RX2TX (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_DL0TX2RX_Pos (13UL) /*!< DL0TX2RX (Bit 13) */ + #define R_MIPI_DSI_PLSCR_DL0TX2RX_Msk (0x2000UL) /*!< DL0TX2RX (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_CLULPENT_Pos (24UL) /*!< CLULPENT (Bit 24) */ + #define R_MIPI_DSI_PLSCR_CLULPENT_Msk (0x1000000UL) /*!< CLULPENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_CLULPEXT_Pos (25UL) /*!< CLULPEXT (Bit 25) */ + #define R_MIPI_DSI_PLSCR_CLULPEXT_Msk (0x2000000UL) /*!< CLULPEXT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_CLLP2HS_Pos (26UL) /*!< CLLP2HS (Bit 26) */ + #define R_MIPI_DSI_PLSCR_CLLP2HS_Msk (0x4000000UL) /*!< CLLP2HS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_CLHS2LP_Pos (27UL) /*!< CLHS2LP (Bit 27) */ + #define R_MIPI_DSI_PLSCR_CLHS2LP_Msk (0x8000000UL) /*!< CLHS2LP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_DLULPENT_Pos (28UL) /*!< DLULPENT (Bit 28) */ + #define R_MIPI_DSI_PLSCR_DLULPENT_Msk (0x10000000UL) /*!< DLULPENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_DLULPEXT_Pos (29UL) /*!< DLULPEXT (Bit 29) */ + #define R_MIPI_DSI_PLSCR_DLULPEXT_Msk (0x20000000UL) /*!< DLULPEXT (Bitfield-Mask: 0x01) */ +/* ========================================================= PLIER ========================================================= */ + #define R_MIPI_DSI_PLIER_DL0RX2TX_Pos (12UL) /*!< DL0RX2TX (Bit 12) */ + #define R_MIPI_DSI_PLIER_DL0RX2TX_Msk (0x1000UL) /*!< DL0RX2TX (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_DL0TX2RX_Pos (13UL) /*!< DL0TX2RX (Bit 13) */ + #define R_MIPI_DSI_PLIER_DL0TX2RX_Msk (0x2000UL) /*!< DL0TX2RX (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_CLULPENT_Pos (24UL) /*!< CLULPENT (Bit 24) */ + #define R_MIPI_DSI_PLIER_CLULPENT_Msk (0x1000000UL) /*!< CLULPENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_CLULPEXT_Pos (25UL) /*!< CLULPEXT (Bit 25) */ + #define R_MIPI_DSI_PLIER_CLULPEXT_Msk (0x2000000UL) /*!< CLULPEXT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_CLLP2HS_Pos (26UL) /*!< CLLP2HS (Bit 26) */ + #define R_MIPI_DSI_PLIER_CLLP2HS_Msk (0x4000000UL) /*!< CLLP2HS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_CLHS2LP_Pos (27UL) /*!< CLHS2LP (Bit 27) */ + #define R_MIPI_DSI_PLIER_CLHS2LP_Msk (0x8000000UL) /*!< CLHS2LP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_DLULPENT_Pos (28UL) /*!< DLULPENT (Bit 28) */ + #define R_MIPI_DSI_PLIER_DLULPENT_Msk (0x10000000UL) /*!< DLULPENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_DLULPEXT_Pos (29UL) /*!< DLULPEXT (Bit 29) */ + #define R_MIPI_DSI_PLIER_DLULPEXT_Msk (0x20000000UL) /*!< DLULPEXT (Bitfield-Mask: 0x01) */ +/* ======================================================== VMSET0R ======================================================== */ + #define R_MIPI_DSI_VMSET0R_VSTART_Pos (0UL) /*!< VSTART (Bit 0) */ + #define R_MIPI_DSI_VMSET0R_VSTART_Msk (0x1UL) /*!< VSTART (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSET0R_VSTOP_Pos (1UL) /*!< VSTOP (Bit 1) */ + #define R_MIPI_DSI_VMSET0R_VSTOP_Msk (0x2UL) /*!< VSTOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSET0R_HSANOLP_Pos (8UL) /*!< HSANOLP (Bit 8) */ + #define R_MIPI_DSI_VMSET0R_HSANOLP_Msk (0x100UL) /*!< HSANOLP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSET0R_HBPNOLP_Pos (9UL) /*!< HBPNOLP (Bit 9) */ + #define R_MIPI_DSI_VMSET0R_HBPNOLP_Msk (0x200UL) /*!< HBPNOLP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSET0R_HFPNOLP_Pos (10UL) /*!< HFPNOLP (Bit 10) */ + #define R_MIPI_DSI_VMSET0R_HFPNOLP_Msk (0x400UL) /*!< HFPNOLP (Bitfield-Mask: 0x01) */ +/* ======================================================== VMSET1R ======================================================== */ + #define R_MIPI_DSI_VMSET1R_DLY_Pos (2UL) /*!< DLY (Bit 2) */ + #define R_MIPI_DSI_VMSET1R_DLY_Msk (0x3ffcUL) /*!< DLY (Bitfield-Mask: 0xfff) */ +/* ========================================================= VMSR ========================================================== */ + #define R_MIPI_DSI_VMSR_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_MIPI_DSI_VMSR_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSR_STOP_Pos (1UL) /*!< STOP (Bit 1) */ + #define R_MIPI_DSI_VMSR_STOP_Msk (0x2UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSR_RUNNING_Pos (2UL) /*!< RUNNING (Bit 2) */ + #define R_MIPI_DSI_VMSR_RUNNING_Msk (0x4UL) /*!< RUNNING (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSR_VIRDY_Pos (3UL) /*!< VIRDY (Bit 3) */ + #define R_MIPI_DSI_VMSR_VIRDY_Msk (0x8UL) /*!< VIRDY (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSR_TIMERR_Pos (20UL) /*!< TIMERR (Bit 20) */ + #define R_MIPI_DSI_VMSR_TIMERR_Msk (0x100000UL) /*!< TIMERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSR_VBUFUDF_Pos (22UL) /*!< VBUFUDF (Bit 22) */ + #define R_MIPI_DSI_VMSR_VBUFUDF_Msk (0x400000UL) /*!< VBUFUDF (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSR_VBUFOVF_Pos (23UL) /*!< VBUFOVF (Bit 23) */ + #define R_MIPI_DSI_VMSR_VBUFOVF_Msk (0x800000UL) /*!< VBUFOVF (Bitfield-Mask: 0x01) */ +/* ========================================================= VMSCR ========================================================= */ + #define R_MIPI_DSI_VMSCR_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_MIPI_DSI_VMSCR_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSCR_STOP_Pos (1UL) /*!< STOP (Bit 1) */ + #define R_MIPI_DSI_VMSCR_STOP_Msk (0x2UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSCR_VIRDY_Pos (3UL) /*!< VIRDY (Bit 3) */ + #define R_MIPI_DSI_VMSCR_VIRDY_Msk (0x8UL) /*!< VIRDY (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSCR_TIMERR_Pos (20UL) /*!< TIMERR (Bit 20) */ + #define R_MIPI_DSI_VMSCR_TIMERR_Msk (0x100000UL) /*!< TIMERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSCR_VBUFUDF_Pos (22UL) /*!< VBUFUDF (Bit 22) */ + #define R_MIPI_DSI_VMSCR_VBUFUDF_Msk (0x400000UL) /*!< VBUFUDF (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSCR_VBUFOVF_Pos (23UL) /*!< VBUFOVF (Bit 23) */ + #define R_MIPI_DSI_VMSCR_VBUFOVF_Msk (0x800000UL) /*!< VBUFOVF (Bitfield-Mask: 0x01) */ +/* ========================================================= VMIER ========================================================= */ + #define R_MIPI_DSI_VMIER_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_MIPI_DSI_VMIER_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMIER_STOP_Pos (1UL) /*!< STOP (Bit 1) */ + #define R_MIPI_DSI_VMIER_STOP_Msk (0x2UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMIER_VIRDY_Pos (3UL) /*!< VIRDY (Bit 3) */ + #define R_MIPI_DSI_VMIER_VIRDY_Msk (0x8UL) /*!< VIRDY (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMIER_TIMERR_Pos (20UL) /*!< TIMERR (Bit 20) */ + #define R_MIPI_DSI_VMIER_TIMERR_Msk (0x100000UL) /*!< TIMERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMIER_VBUFUDF_Pos (22UL) /*!< VBUFUDF (Bit 22) */ + #define R_MIPI_DSI_VMIER_VBUFUDF_Msk (0x400000UL) /*!< VBUFUDF (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMIER_VBUFOVF_Pos (23UL) /*!< VBUFOVF (Bit 23) */ + #define R_MIPI_DSI_VMIER_VBUFOVF_Msk (0x800000UL) /*!< VBUFOVF (Bitfield-Mask: 0x01) */ +/* ======================================================= VMPPSETR ======================================================== */ + #define R_MIPI_DSI_VMPPSETR_TXESYNC_Pos (15UL) /*!< TXESYNC (Bit 15) */ + #define R_MIPI_DSI_VMPPSETR_TXESYNC_Msk (0x8000UL) /*!< TXESYNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMPPSETR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_VMPPSETR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_VMPPSETR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_VMPPSETR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ======================================================= VMVSSETR ======================================================== */ + #define R_MIPI_DSI_VMVSSETR_VSA_Pos (0UL) /*!< VSA (Bit 0) */ + #define R_MIPI_DSI_VMVSSETR_VSA_Msk (0xfffUL) /*!< VSA (Bitfield-Mask: 0xfff) */ + #define R_MIPI_DSI_VMVSSETR_VSPOL_Pos (15UL) /*!< VSPOL (Bit 15) */ + #define R_MIPI_DSI_VMVSSETR_VSPOL_Msk (0x8000UL) /*!< VSPOL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMVSSETR_VACT_Pos (16UL) /*!< VACT (Bit 16) */ + #define R_MIPI_DSI_VMVSSETR_VACT_Msk (0x7fff0000UL) /*!< VACT (Bitfield-Mask: 0x7fff) */ +/* ======================================================= VMVPSETR ======================================================== */ + #define R_MIPI_DSI_VMVPSETR_VBP_Pos (0UL) /*!< VBP (Bit 0) */ + #define R_MIPI_DSI_VMVPSETR_VBP_Msk (0x1fffUL) /*!< VBP (Bitfield-Mask: 0x1fff) */ + #define R_MIPI_DSI_VMVPSETR_VFP_Pos (16UL) /*!< VFP (Bit 16) */ + #define R_MIPI_DSI_VMVPSETR_VFP_Msk (0x1fff0000UL) /*!< VFP (Bitfield-Mask: 0x1fff) */ +/* ======================================================= VMHSSETR ======================================================== */ + #define R_MIPI_DSI_VMHSSETR_HSA_Pos (0UL) /*!< HSA (Bit 0) */ + #define R_MIPI_DSI_VMHSSETR_HSA_Msk (0xfffUL) /*!< HSA (Bitfield-Mask: 0xfff) */ + #define R_MIPI_DSI_VMHSSETR_HSPOL_Pos (15UL) /*!< HSPOL (Bit 15) */ + #define R_MIPI_DSI_VMHSSETR_HSPOL_Msk (0x8000UL) /*!< HSPOL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMHSSETR_HACT_Pos (16UL) /*!< HACT (Bit 16) */ + #define R_MIPI_DSI_VMHSSETR_HACT_Msk (0x7fff0000UL) /*!< HACT (Bitfield-Mask: 0x7fff) */ +/* ======================================================= VMHPSETR ======================================================== */ + #define R_MIPI_DSI_VMHPSETR_HBP_Pos (0UL) /*!< HBP (Bit 0) */ + #define R_MIPI_DSI_VMHPSETR_HBP_Msk (0x1fffUL) /*!< HBP (Bitfield-Mask: 0x1fff) */ + #define R_MIPI_DSI_VMHPSETR_HFP_Pos (16UL) /*!< HFP (Bit 16) */ + #define R_MIPI_DSI_VMHPSETR_HFP_Msk (0x1fff0000UL) /*!< HFP (Bitfield-Mask: 0x1fff) */ +/* ====================================================== SQCH0SET0R ======================================================= */ + #define R_MIPI_DSI_SQCH0SET0R_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_MIPI_DSI_SQCH0SET0R_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ======================================================== SQCH0SR ======================================================== */ + #define R_MIPI_DSI_SQCH0SR_RUNNING_Pos (2UL) /*!< RUNNING (Bit 2) */ + #define R_MIPI_DSI_SQCH0SR_RUNNING_Msk (0x4UL) /*!< RUNNING (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_AACTFIN_Pos (4UL) /*!< AACTFIN (Bit 4) */ + #define R_MIPI_DSI_SQCH0SR_AACTFIN_Msk (0x10UL) /*!< AACTFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_ADESFIN_Pos (8UL) /*!< ADESFIN (Bit 8) */ + #define R_MIPI_DSI_SQCH0SR_ADESFIN_Msk (0x100UL) /*!< ADESFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_DABORT_Pos (16UL) /*!< DABORT (Bit 16) */ + #define R_MIPI_DSI_SQCH0SR_DABORT_Msk (0x10000UL) /*!< DABORT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_SIZEERR_Pos (19UL) /*!< SIZEERR (Bit 19) */ + #define R_MIPI_DSI_SQCH0SR_SIZEERR_Msk (0x80000UL) /*!< SIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_TXIBERR_Pos (24UL) /*!< TXIBERR (Bit 24) */ + #define R_MIPI_DSI_SQCH0SR_TXIBERR_Msk (0x1000000UL) /*!< TXIBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_SQCH0SR_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_SQCH0SR_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_SQCH0SR_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_RXCORERR_Pos (29UL) /*!< RXCORERR (Bit 29) */ + #define R_MIPI_DSI_SQCH0SR_RXCORERR_Msk (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_SQCH0SR_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ======================================================= SQCH0SCR ======================================================== */ + #define R_MIPI_DSI_SQCH0SCR_AACTFIN_Pos (4UL) /*!< AACTFIN (Bit 4) */ + #define R_MIPI_DSI_SQCH0SCR_AACTFIN_Msk (0x10UL) /*!< AACTFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_ADESFIN_Pos (8UL) /*!< ADESFIN (Bit 8) */ + #define R_MIPI_DSI_SQCH0SCR_ADESFIN_Msk (0x100UL) /*!< ADESFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_DABORT_Pos (16UL) /*!< DABORT (Bit 16) */ + #define R_MIPI_DSI_SQCH0SCR_DABORT_Msk (0x10000UL) /*!< DABORT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_SIZEERR_Pos (19UL) /*!< SIZEERR (Bit 19) */ + #define R_MIPI_DSI_SQCH0SCR_SIZEERR_Msk (0x80000UL) /*!< SIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_TXIBERR_Pos (24UL) /*!< TXIBERR (Bit 24) */ + #define R_MIPI_DSI_SQCH0SCR_TXIBERR_Msk (0x1000000UL) /*!< TXIBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_SQCH0SCR_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_SQCH0SCR_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_SQCH0SCR_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_RXCORERR_Pos (29UL) /*!< RXCORERR (Bit 29) */ + #define R_MIPI_DSI_SQCH0SCR_RXCORERR_Msk (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_SQCH0SCR_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ======================================================= SQCH0IER ======================================================== */ + #define R_MIPI_DSI_SQCH0IER_AACTFIN_Pos (4UL) /*!< AACTFIN (Bit 4) */ + #define R_MIPI_DSI_SQCH0IER_AACTFIN_Msk (0x10UL) /*!< AACTFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_ADESFIN_Pos (8UL) /*!< ADESFIN (Bit 8) */ + #define R_MIPI_DSI_SQCH0IER_ADESFIN_Msk (0x100UL) /*!< ADESFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_DABORT_Pos (16UL) /*!< DABORT (Bit 16) */ + #define R_MIPI_DSI_SQCH0IER_DABORT_Msk (0x10000UL) /*!< DABORT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_SIZEERR_Pos (19UL) /*!< SIZEERR (Bit 19) */ + #define R_MIPI_DSI_SQCH0IER_SIZEERR_Msk (0x80000UL) /*!< SIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_TXIBERR_Pos (24UL) /*!< TXIBERR (Bit 24) */ + #define R_MIPI_DSI_SQCH0IER_TXIBERR_Msk (0x1000000UL) /*!< TXIBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_SQCH0IER_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_SQCH0IER_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_SQCH0IER_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_RXCORERR_Pos (29UL) /*!< RXCORERR (Bit 29) */ + #define R_MIPI_DSI_SQCH0IER_RXCORERR_Msk (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_SQCH0IER_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ====================================================== SQCH1SET0R ======================================================= */ + #define R_MIPI_DSI_SQCH1SET0R_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_MIPI_DSI_SQCH1SET0R_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ======================================================== SQCH1SR ======================================================== */ + #define R_MIPI_DSI_SQCH1SR_RUNNING_Pos (2UL) /*!< RUNNING (Bit 2) */ + #define R_MIPI_DSI_SQCH1SR_RUNNING_Msk (0x4UL) /*!< RUNNING (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_AACTFIN_Pos (4UL) /*!< AACTFIN (Bit 4) */ + #define R_MIPI_DSI_SQCH1SR_AACTFIN_Msk (0x10UL) /*!< AACTFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_ADESFIN_Pos (8UL) /*!< ADESFIN (Bit 8) */ + #define R_MIPI_DSI_SQCH1SR_ADESFIN_Msk (0x100UL) /*!< ADESFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_DABORT_Pos (16UL) /*!< DABORT (Bit 16) */ + #define R_MIPI_DSI_SQCH1SR_DABORT_Msk (0x10000UL) /*!< DABORT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_SIZEERR_Pos (19UL) /*!< SIZEERR (Bit 19) */ + #define R_MIPI_DSI_SQCH1SR_SIZEERR_Msk (0x80000UL) /*!< SIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_TXIBERR_Pos (24UL) /*!< TXIBERR (Bit 24) */ + #define R_MIPI_DSI_SQCH1SR_TXIBERR_Msk (0x1000000UL) /*!< TXIBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_SQCH1SR_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_SQCH1SR_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_SQCH1SR_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_RXCORERR_Pos (29UL) /*!< RXCORERR (Bit 29) */ + #define R_MIPI_DSI_SQCH1SR_RXCORERR_Msk (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_SQCH1SR_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ======================================================= SQCH1SCR ======================================================== */ + #define R_MIPI_DSI_SQCH1SCR_AACTFIN_Pos (4UL) /*!< AACTFIN (Bit 4) */ + #define R_MIPI_DSI_SQCH1SCR_AACTFIN_Msk (0x10UL) /*!< AACTFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_ADESFIN_Pos (8UL) /*!< ADESFIN (Bit 8) */ + #define R_MIPI_DSI_SQCH1SCR_ADESFIN_Msk (0x100UL) /*!< ADESFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_DABORT_Pos (16UL) /*!< DABORT (Bit 16) */ + #define R_MIPI_DSI_SQCH1SCR_DABORT_Msk (0x10000UL) /*!< DABORT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_SIZEERR_Pos (19UL) /*!< SIZEERR (Bit 19) */ + #define R_MIPI_DSI_SQCH1SCR_SIZEERR_Msk (0x80000UL) /*!< SIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_TXIBERR_Pos (24UL) /*!< TXIBERR (Bit 24) */ + #define R_MIPI_DSI_SQCH1SCR_TXIBERR_Msk (0x1000000UL) /*!< TXIBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_SQCH1SCR_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_SQCH1SCR_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_SQCH1SCR_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_RXCORERR_Pos (29UL) /*!< RXCORERR (Bit 29) */ + #define R_MIPI_DSI_SQCH1SCR_RXCORERR_Msk (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_SQCH1SCR_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ======================================================= SQCH1IER ======================================================== */ + #define R_MIPI_DSI_SQCH1IER_AACTFIN_Pos (4UL) /*!< AACTFIN (Bit 4) */ + #define R_MIPI_DSI_SQCH1IER_AACTFIN_Msk (0x10UL) /*!< AACTFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_ADESFIN_Pos (8UL) /*!< ADESFIN (Bit 8) */ + #define R_MIPI_DSI_SQCH1IER_ADESFIN_Msk (0x100UL) /*!< ADESFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_DABORT_Pos (16UL) /*!< DABORT (Bit 16) */ + #define R_MIPI_DSI_SQCH1IER_DABORT_Msk (0x10000UL) /*!< DABORT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_SIZEERR_Pos (19UL) /*!< SIZEERR (Bit 19) */ + #define R_MIPI_DSI_SQCH1IER_SIZEERR_Msk (0x80000UL) /*!< SIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_TXIBERR_Pos (24UL) /*!< TXIBERR (Bit 24) */ + #define R_MIPI_DSI_SQCH1IER_TXIBERR_Msk (0x1000000UL) /*!< TXIBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_SQCH1IER_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_SQCH1IER_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_SQCH1IER_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_RXCORERR_Pos (29UL) /*!< RXCORERR (Bit 29) */ + #define R_MIPI_DSI_SQCH1IER_RXCORERR_Msk (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_SQCH1IER_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ====================================================== SQCH0DSC0AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC0AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC0AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC0AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC0AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC0AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC0AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC0AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC0AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC0AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC0AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC0AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC0AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC1AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC1AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC1AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC1AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC1AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC1AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC1AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC1AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC1AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC1AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC1AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC1AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC1AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC2AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC2AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC2AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC2AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC2AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC2AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC2AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC2AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC2AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC2AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC2AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC2AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC2AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC3AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC3AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC3AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC3AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC3AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC3AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC3AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC3AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC3AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC3AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC3AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC3AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC3AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC4AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC4AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC4AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC4AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC4AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC4AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC4AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC4AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC4AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC4AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC4AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC4AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC4AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC5AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC5AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC5AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC5AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC5AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC5AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC5AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC5AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC5AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC5AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC5AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC5AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC5AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC6AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC6AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC6AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC6AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC6AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC6AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC6AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC6AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC6AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC6AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC6AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC6AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC6AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC7AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC7AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC7AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC7AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC7AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC7AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC7AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC7AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC7AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC7AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC7AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC7AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC7AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC0AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC0AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC0AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC1AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC1AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC1AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC2AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC2AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC2AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC3AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC3AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC3AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC4AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC4AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC4AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC5AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC5AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC5AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC6AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC6AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC6AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC7AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC7AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC7AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC0AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC0AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC0AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC1AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC2AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC3AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC4AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC5AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC6AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC7AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC0AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC1AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC2AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC3AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC4AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC5AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC6AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC7AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC0AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC1AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC2AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC3AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC4AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC5AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC6AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC7AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC0BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC0BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC0BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC1BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC1BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC1BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC2BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC2BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC2BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC3BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC3BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC3BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC4BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC4BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC4BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC5BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC5BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC5BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC6BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC6BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC6BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC7BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC7BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC7BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC0CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC0CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC0CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC0CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC1CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC1CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC1CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC1CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC2CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC2CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC2CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC2CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC3CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC3CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC3CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC3CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC4CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC4CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC4CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC4CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC5CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC5CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC5CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC5CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC6CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC6CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC6CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC6CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC7CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC7CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC7CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC7CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC0CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC1CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC2CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC3CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC4CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC5CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC6CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC7CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC0CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC1CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC2CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC3CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC4CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC5CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC6CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC7CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC0CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC0CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC0CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC1CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC1CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC1CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC2CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC2CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC2CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC3CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC3CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC3CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC4CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC4CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC4CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC5CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC5CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC5CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC6CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC6CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC6CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC7CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC7CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC7CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC0CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC0CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC1CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC1CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC2CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC2CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC3CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC3CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC4CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC4CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC5CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC5CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC6CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC6CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC7CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC7CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC0CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC0DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC1DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC2DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC3DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC4DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC5DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC6DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC7DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== SQCH0DSC0DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC1DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC2DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC3DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC4DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC5DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC6DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC7DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ==================================================== SQCH0DSC0DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC0DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC0DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC1DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC2DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC3DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC4DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC5DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC6DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC7DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ==================================================== SQCH0DSC0DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC0DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC0AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC0AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC0AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC0AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC0AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC0AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC0AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC0AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC0AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC0AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC0AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC0AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC0AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC1AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC1AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC1AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC1AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC1AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC1AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC1AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC1AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC1AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC1AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC1AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC1AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC1AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC2AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC2AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC2AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC2AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC2AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC2AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC2AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC2AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC2AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC2AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC2AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC2AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC2AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC3AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC3AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC3AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC3AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC3AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC3AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC3AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC3AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC3AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC3AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC3AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC3AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC3AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC4AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC4AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC4AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC4AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC4AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC4AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC4AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC4AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC4AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC4AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC4AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC4AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC4AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC5AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC5AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC5AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC5AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC5AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC5AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC5AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC5AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC5AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC5AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC5AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC5AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC5AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC6AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC6AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC6AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC6AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC6AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC6AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC6AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC6AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC6AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC6AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC6AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC6AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC6AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC7AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC7AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC7AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC7AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC7AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC7AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC7AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC7AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC7AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC7AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC7AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC7AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC7AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC0AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC0AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC0AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC1AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC1AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC1AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC2AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC2AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC2AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC3AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC3AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC3AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC4AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC4AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC4AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC5AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC5AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC5AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC6AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC6AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC6AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC7AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC7AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC7AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC0AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC0AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC0AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC1AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC2AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC3AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC4AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC5AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC6AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC7AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC0AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC1AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC2AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC3AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC4AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC5AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC6AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC7AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC0AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC1AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC2AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC3AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC4AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC5AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC6AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC7AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC0BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC0BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC0BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC1BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC1BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC1BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC2BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC2BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC2BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC3BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC3BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC3BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC4BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC4BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC4BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC5BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC5BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC5BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC6BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC6BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC6BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC7BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC7BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC7BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC0CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC0CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC0CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC0CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC1CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC1CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC1CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC1CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC2CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC2CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC2CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC2CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC3CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC3CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC3CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC3CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC4CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC4CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC4CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC4CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC5CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC5CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC5CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC5CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC6CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC6CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC6CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC6CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC7CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC7CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC7CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC7CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC0CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC1CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC2CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC3CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC4CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC5CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC6CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC7CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC0CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC1CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC2CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC3CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC4CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC5CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC6CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC7CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC0CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC0CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC0CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC1CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC1CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC1CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC2CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC2CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC2CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC3CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC3CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC3CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC4CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC4CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC4CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC5CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC5CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC5CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC6CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC6CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC6CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC7CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC7CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC7CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC0CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC0CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC1CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC1CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC2CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC2CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC3CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC3CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC4CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC4CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC5CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC5CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC6CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC6CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC7CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC7CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC0CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC0DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC0DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC1DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC1DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC2DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC2DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC3DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC3DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC4DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC4DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC5DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC5DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC6DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC6DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC7DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC7DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== SQCH1DSC0DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC1DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC2DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC3DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC4DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC5DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC6DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC7DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ==================================================== SQCH1DSC0DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC0DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC0DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC0DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_MRMS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MRCPFB ========================================================= */ + #define R_MRMS_MRCPFB_MPFBEN_Pos (0UL) /*!< MPFBEN (Bit 0) */ + #define R_MRMS_MRCPFB_MPFBEN_Msk (0x1UL) /*!< MPFBEN (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCFREQ ======================================================== */ + #define R_MRMS_MRCFREQ_MRCMHZ_Pos (0UL) /*!< MRCMHZ (Bit 0) */ + #define R_MRMS_MRCFREQ_MRCMHZ_Msk (0x3ffUL) /*!< MRCMHZ (Bitfield-Mask: 0x3ff) */ + #define R_MRMS_MRCFREQ_KEY_Pos (24UL) /*!< KEY (Bit 24) */ + #define R_MRMS_MRCFREQ_KEY_Msk (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== MREFREQ ======================================================== */ + #define R_MRMS_MREFREQ_MREMHZ_Pos (0UL) /*!< MREMHZ (Bit 0) */ + #define R_MRMS_MREFREQ_MREMHZ_Msk (0xffUL) /*!< MREMHZ (Bitfield-Mask: 0xff) */ + #define R_MRMS_MREFREQ_KEY_Pos (24UL) /*!< KEY (Bit 24) */ + #define R_MRMS_MREFREQ_KEY_Msk (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== MRCDECC ======================================================== */ + #define R_MRMS_MRCDECC_DECDISC_Pos (0UL) /*!< DECDISC (Bit 0) */ + #define R_MRMS_MRCDECC_DECDISC_Msk (0x1UL) /*!< DECDISC (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCDECC_ECCSELC_Pos (1UL) /*!< ECCSELC (Bit 1) */ + #define R_MRMS_MRCDECC_ECCSELC_Msk (0x2UL) /*!< ECCSELC (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCDECC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MRCDECC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= MRCRAEINT ======================================================= */ + #define R_MRMS_MRCRAEINT_INTENBDC_Pos (0UL) /*!< INTENBDC (Bit 0) */ + #define R_MRMS_MRCRAEINT_INTENBDC_Msk (0x1UL) /*!< INTENBDC (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCRAEINT_INTENBTC_Pos (1UL) /*!< INTENBTC (Bit 1) */ + #define R_MRMS_MRCRAEINT_INTENBTC_Msk (0x2UL) /*!< INTENBTC (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCRAES ======================================================== */ + #define R_MRMS_MRCRAES_DECERRC_Pos (0UL) /*!< DECERRC (Bit 0) */ + #define R_MRMS_MRCRAES_DECERRC_Msk (0x1UL) /*!< DECERRC (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCRAES_TEDERRC_Pos (1UL) /*!< TEDERRC (Bit 1) */ + #define R_MRMS_MRCRAES_TEDERRC_Msk (0x2UL) /*!< TEDERRC (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCRTEA ======================================================== */ + #define R_MRMS_MRCRTEA_MRCRTEA_Pos (5UL) /*!< MRCRTEA (Bit 5) */ + #define R_MRMS_MRCRTEA_MRCRTEA_Msk (0xffffffe0UL) /*!< MRCRTEA (Bitfield-Mask: 0x7ffffff) */ +/* ======================================================== MRCRDEA ======================================================== */ + #define R_MRMS_MRCRDEA_MRCRDEA_Pos (5UL) /*!< MRCRDEA (Bit 5) */ + #define R_MRMS_MRCRDEA_MRCRDEA_Msk (0xffffffe0UL) /*!< MRCRDEA (Bitfield-Mask: 0x7ffffff) */ +/* ======================================================= MRERAINT ======================================================== */ + #define R_MRMS_MRERAINT_INTENBDE_Pos (0UL) /*!< INTENBDE (Bit 0) */ + #define R_MRMS_MRERAINT_INTENBDE_Msk (0x1UL) /*!< INTENBDE (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRERAINT_INTENBTE_Pos (1UL) /*!< INTENBTE (Bit 1) */ + #define R_MRMS_MRERAINT_INTENBTE_Msk (0x2UL) /*!< INTENBTE (Bitfield-Mask: 0x01) */ +/* ======================================================== MRERAES ======================================================== */ + #define R_MRMS_MRERAES_DECERRE_Pos (0UL) /*!< DECERRE (Bit 0) */ + #define R_MRMS_MRERAES_DECERRE_Msk (0x1UL) /*!< DECERRE (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRERAES_TEDERRE_Pos (1UL) /*!< TEDERRE (Bit 1) */ + #define R_MRMS_MRERAES_TEDERRE_Msk (0x2UL) /*!< TEDERRE (Bitfield-Mask: 0x01) */ +/* ======================================================== MRERTEA ======================================================== */ + #define R_MRMS_MRERTEA_MRERTEA_Pos (4UL) /*!< MRERTEA (Bit 4) */ + #define R_MRMS_MRERTEA_MRERTEA_Msk (0xfffffff0UL) /*!< MRERTEA (Bitfield-Mask: 0xfffffff) */ +/* ======================================================== MRERDEA ======================================================== */ + #define R_MRMS_MRERDEA_MRERDEA_Pos (4UL) /*!< MRERDEA (Bit 4) */ + #define R_MRMS_MRERDEA_MRERDEA_Msk (0xfffffff0UL) /*!< MRERDEA (Bitfield-Mask: 0xfffffff) */ +/* ========================================================= MSAR ========================================================== */ + #define R_MRMS_MSAR_MREECCSA_Pos (0UL) /*!< MREECCSA (Bit 0) */ + #define R_MRMS_MSAR_MREECCSA_Msk (0x1UL) /*!< MREECCSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MREFREQSA_Pos (1UL) /*!< MREFREQSA (Bit 1) */ + #define R_MRMS_MSAR_MREFREQSA_Msk (0x2UL) /*!< MREFREQSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MRCECCSA_Pos (2UL) /*!< MRCECCSA (Bit 2) */ + #define R_MRMS_MSAR_MRCECCSA_Msk (0x4UL) /*!< MRCECCSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MRCFREQSA_Pos (3UL) /*!< MRCFREQSA (Bit 3) */ + #define R_MRMS_MSAR_MRCFREQSA_Msk (0x8UL) /*!< MRCFREQSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MPFBENSA_Pos (4UL) /*!< MPFBENSA (Bit 4) */ + #define R_MRMS_MSAR_MPFBENSA_Msk (0x10UL) /*!< MPFBENSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MACICMISA_Pos (9UL) /*!< MACICMISA (Bit 9) */ + #define R_MRMS_MSAR_MACICMISA_Msk (0x200UL) /*!< MACICMISA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MACICMRSA_Pos (10UL) /*!< MACICMRSA (Bit 10) */ + #define R_MRMS_MSAR_MACICMRSA_Msk (0x400UL) /*!< MACICMRSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MACITRSA_Pos (11UL) /*!< MACITRSA (Bit 11) */ + #define R_MRMS_MSAR_MACITRSA_Msk (0x800UL) /*!< MACITRSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MRCPSA_Pos (13UL) /*!< MRCPSA (Bit 13) */ + #define R_MRMS_MSAR_MRCPSA_Msk (0x2000UL) /*!< MRCPSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MREPSEQSA_Pos (14UL) /*!< MREPSEQSA (Bit 14) */ + #define R_MRMS_MSAR_MREPSEQSA_Msk (0x4000UL) /*!< MREPSEQSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MRCPSEQSA_Pos (15UL) /*!< MRCPSEQSA (Bit 15) */ + #define R_MRMS_MSAR_MRCPSEQSA_Msk (0x8000UL) /*!< MRCPSEQSA (Bitfield-Mask: 0x01) */ +/* ========================================================= MREZS ========================================================= */ + #define R_MRMS_MREZS_WHUKZF_Pos (0UL) /*!< WHUKZF (Bit 0) */ + #define R_MRMS_MREZS_WHUKZF_Msk (0x1UL) /*!< WHUKZF (Bitfield-Mask: 0x01) */ + #define R_MRMS_MREZS_WHUKEXE_Pos (1UL) /*!< WHUKEXE (Bit 1) */ + #define R_MRMS_MREZS_WHUKEXE_Msk (0x2UL) /*!< WHUKEXE (Bitfield-Mask: 0x01) */ +/* ========================================================= MREZC ========================================================= */ + #define R_MRMS_MREZC_WHUKZE_Pos (0UL) /*!< WHUKZE (Bit 0) */ + #define R_MRMS_MREZC_WHUKZE_Msk (0x7UL) /*!< WHUKZE (Bitfield-Mask: 0x07) */ + #define R_MRMS_MREZC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MREZC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== MASTAT ========================================================= */ + #define R_MRMS_MASTAT_MREAE_Pos (3UL) /*!< MREAE (Bit 3) */ + #define R_MRMS_MASTAT_MREAE_Msk (0x8UL) /*!< MREAE (Bitfield-Mask: 0x01) */ + #define R_MRMS_MASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */ + #define R_MRMS_MASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */ +/* ======================================================== MPAEINT ======================================================== */ + #define R_MRMS_MPAEINT_MREAEIE_Pos (3UL) /*!< MREAEIE (Bit 3) */ + #define R_MRMS_MPAEINT_MREAEIE_Msk (0x8UL) /*!< MREAEIE (Bitfield-Mask: 0x01) */ + #define R_MRMS_MPAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */ + #define R_MRMS_MPAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */ +/* ======================================================== MRDYIE ========================================================= */ + #define R_MRMS_MRDYIE_MRDYIE_Pos (0UL) /*!< MRDYIE (Bit 0) */ + #define R_MRMS_MRDYIE_MRDYIE_Msk (0x1UL) /*!< MRDYIE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSADDR ========================================================= */ + #define R_MRMS_MSADDR_MSADDR_Pos (0UL) /*!< MSADDR (Bit 0) */ + #define R_MRMS_MSADDR_MSADDR_Msk (0xffffffffUL) /*!< MSADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= MCNTSELR ======================================================== */ + #define R_MRMS_MCNTSELR_CNTSEL_Pos (0UL) /*!< CNTSEL (Bit 0) */ + #define R_MRMS_MCNTSELR_CNTSEL_Msk (0x7UL) /*!< CNTSEL (Bitfield-Mask: 0x07) */ +/* ======================================================= MCNTDTR0 ======================================================== */ + #define R_MRMS_MCNTDTR0_CNTRDAT_Pos (0UL) /*!< CNTRDAT (Bit 0) */ + #define R_MRMS_MCNTDTR0_CNTRDAT_Msk (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= MCNTDTR1 ======================================================== */ + #define R_MRMS_MCNTDTR1_CNTRDAT_Pos (0UL) /*!< CNTRDAT (Bit 0) */ + #define R_MRMS_MCNTDTR1_CNTRDAT_Msk (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= MCTRCNTR ======================================================== */ + #define R_MRMS_MCTRCNTR_TRTRG_Pos (0UL) /*!< TRTRG (Bit 0) */ + #define R_MRMS_MCTRCNTR_TRTRG_Msk (0x1UL) /*!< TRTRG (Bitfield-Mask: 0x01) */ + #define R_MRMS_MCTRCNTR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MCTRCNTR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== MCTRLSR ======================================================== */ + #define R_MRMS_MCTRLSR_TRLIST_Pos (0UL) /*!< TRLIST (Bit 0) */ + #define R_MRMS_MCTRLSR_TRLIST_Msk (0x7UL) /*!< TRLIST (Bitfield-Mask: 0x07) */ +/* ======================================================= MCTRSTATR ======================================================= */ + #define R_MRMS_MCTRSTATR_TRBUSY_Pos (0UL) /*!< TRBUSY (Bit 0) */ + #define R_MRMS_MCTRSTATR_TRBUSY_Msk (0x1UL) /*!< TRBUSY (Bitfield-Mask: 0x01) */ + #define R_MRMS_MCTRSTATR_TRMD_Pos (2UL) /*!< TRMD (Bit 2) */ + #define R_MRMS_MCTRSTATR_TRMD_Msk (0x4UL) /*!< TRMD (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTATR ========================================================= */ + #define R_MRMS_MSTATR_CFGSETERR_Pos (5UL) /*!< CFGSETERR (Bit 5) */ + #define R_MRMS_MSTATR_CFGSETERR_Msk (0x20UL) /*!< CFGSETERR (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */ + #define R_MRMS_MSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */ + #define R_MRMS_MSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSTATR_MRDY_Pos (15UL) /*!< MRDY (Bit 15) */ + #define R_MRMS_MSTATR_MRDY_Msk (0x8000UL) /*!< MRDY (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSTATR_TZFERR_Pos (19UL) /*!< TZFERR (Bit 19) */ + #define R_MRMS_MSTATR_TZFERR_Msk (0x80000UL) /*!< TZFERR (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSTATR_OTERR_Pos (20UL) /*!< OTERR (Bit 20) */ + #define R_MRMS_MSTATR_OTERR_Msk (0x100000UL) /*!< OTERR (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSTATR_SECERR_Pos (21UL) /*!< SECERR (Bit 21) */ + #define R_MRMS_MSTATR_SECERR_Msk (0x200000UL) /*!< SECERR (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSTATR_ILGCOMERR_Pos (23UL) /*!< ILGCOMERR (Bit 23) */ + #define R_MRMS_MSTATR_ILGCOMERR_Msk (0x800000UL) /*!< ILGCOMERR (Bitfield-Mask: 0x01) */ +/* ======================================================== MENTRYR ======================================================== */ + #define R_MRMS_MENTRYR_MENTRY_Pos (7UL) /*!< MENTRY (Bit 7) */ + #define R_MRMS_MENTRYR_MENTRY_Msk (0x80UL) /*!< MENTRY (Bitfield-Mask: 0x01) */ + #define R_MRMS_MENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= MSUINITR ======================================================== */ + #define R_MRMS_MSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */ + #define R_MRMS_MSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================= MCMDR ========================================================= */ + #define R_MRMS_MCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */ + #define R_MRMS_MCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */ + #define R_MRMS_MCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */ + #define R_MRMS_MCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */ +/* ======================================================= MSUASMON ======================================================== */ + #define R_MRMS_MSUASMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */ + #define R_MRMS_MSUASMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSUASMON_BTSIZE_Pos (29UL) /*!< BTSIZE (Bit 29) */ + #define R_MRMS_MSUASMON_BTSIZE_Msk (0x60000000UL) /*!< BTSIZE (Bitfield-Mask: 0x03) */ + #define R_MRMS_MSUASMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */ + #define R_MRMS_MSUASMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */ +/* ======================================================== MSUACR ========================================================= */ + #define R_MRMS_MSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */ + #define R_MRMS_MSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */ + #define R_MRMS_MSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================= MRPSC ========================================================= */ + #define R_MRMS_MRPSC_MHSPEN_Pos (0UL) /*!< MHSPEN (Bit 0) */ + #define R_MRMS_MRPSC_MHSPEN_Msk (0x1UL) /*!< MHSPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCPC0 ========================================================= */ + #define R_MRMS_MRCPC0_MRCPNEN_Pos (0UL) /*!< MRCPNEN (Bit 0) */ + #define R_MRMS_MRCPC0_MRCPNEN_Msk (0x1UL) /*!< MRCPNEN (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCPC0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MRCPC0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== MRCPC1 ========================================================= */ + #define R_MRMS_MRCPC1_MRCPSEN_Pos (0UL) /*!< MRCPSEN (Bit 0) */ + #define R_MRMS_MRCPC1_MRCPSEN_Msk (0x1UL) /*!< MRCPSEN (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCPC1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MRCPC1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= MRCBPROT0 ======================================================= */ + #define R_MRMS_MRCBPROT0_BPCN0_Pos (0UL) /*!< BPCN0 (Bit 0) */ + #define R_MRMS_MRCBPROT0_BPCN0_Msk (0x1UL) /*!< BPCN0 (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCBPROT0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MRCBPROT0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= MRCBPROT1 ======================================================= */ + #define R_MRMS_MRCBPROT1_BPCN1_Pos (0UL) /*!< BPCN1 (Bit 0) */ + #define R_MRMS_MRCBPROT1_BPCN1_Msk (0x1UL) /*!< BPCN1 (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCBPROT1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MRCBPROT1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================= MRCPS ========================================================= */ + #define R_MRMS_MRCPS_PRGERRC_Pos (0UL) /*!< PRGERRC (Bit 0) */ + #define R_MRMS_MRCPS_PRGERRC_Msk (0x1UL) /*!< PRGERRC (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCPS_ECCERRC_Pos (1UL) /*!< ECCERRC (Bit 1) */ + #define R_MRMS_MRCPS_ECCERRC_Msk (0x2UL) /*!< ECCERRC (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCPS_ABUFEMP_Pos (5UL) /*!< ABUFEMP (Bit 5) */ + #define R_MRMS_MRCPS_ABUFEMP_Msk (0x20UL) /*!< ABUFEMP (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCPS_ABUFFULL_Pos (6UL) /*!< ABUFFULL (Bit 6) */ + #define R_MRMS_MRCPS_ABUFFULL_Msk (0x40UL) /*!< ABUFFULL (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCPS_PRGBSYC_Pos (7UL) /*!< PRGBSYC (Bit 7) */ + #define R_MRMS_MRCPS_PRGBSYC_Msk (0x80UL) /*!< PRGBSYC (Bitfield-Mask: 0x01) */ +/* ======================================================= MRCPAEINT ======================================================= */ + #define R_MRMS_MRCPAEINT_MRCAEIE_Pos (7UL) /*!< MRCAEIE (Bit 7) */ + #define R_MRMS_MRCPAEINT_MRCAEIE_Msk (0x80UL) /*!< MRCAEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCPEA ========================================================= */ + #define R_MRMS_MRCPEA_MCPEA_Pos (5UL) /*!< MCPEA (Bit 5) */ + #define R_MRMS_MRCPEA_MCPEA_Msk (0xffffffe0UL) /*!< MCPEA (Bitfield-Mask: 0x7ffffff) */ +/* ======================================================== MRCFLR ========================================================= */ + #define R_MRMS_MRCFLR_MRCFL_Pos (0UL) /*!< MRCFL (Bit 0) */ + #define R_MRMS_MRCFLR_MRCFL_Msk (0x1UL) /*!< MRCFL (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCFLR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MRCFLR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== MRCEECC ======================================================== */ + #define R_MRMS_MRCEECC_ECCBYPC_Pos (0UL) /*!< ECCBYPC (Bit 0) */ + #define R_MRMS_MRCEECC_ECCBYPC_Msk (0x1UL) /*!< ECCBYPC (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCEECC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MRCEECC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_NPU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_NPU_ID_arch_major_rev_Pos (28UL) /*!< arch_major_rev (Bit 28) */ + #define R_NPU_ID_arch_major_rev_Msk (0xf0000000UL) /*!< arch_major_rev (Bitfield-Mask: 0x0f) */ + #define R_NPU_ID_arch_minor_rev_Pos (20UL) /*!< arch_minor_rev (Bit 20) */ + #define R_NPU_ID_arch_minor_rev_Msk (0xff00000UL) /*!< arch_minor_rev (Bitfield-Mask: 0xff) */ + #define R_NPU_ID_arch_patch_rev_Pos (16UL) /*!< arch_patch_rev (Bit 16) */ + #define R_NPU_ID_arch_patch_rev_Msk (0xf0000UL) /*!< arch_patch_rev (Bitfield-Mask: 0x0f) */ + #define R_NPU_ID_product_major_Pos (12UL) /*!< product_major (Bit 12) */ + #define R_NPU_ID_product_major_Msk (0xf000UL) /*!< product_major (Bitfield-Mask: 0x0f) */ + #define R_NPU_ID_version_major_Pos (8UL) /*!< version_major (Bit 8) */ + #define R_NPU_ID_version_major_Msk (0xf00UL) /*!< version_major (Bitfield-Mask: 0x0f) */ + #define R_NPU_ID_version_minor_Pos (4UL) /*!< version_minor (Bit 4) */ + #define R_NPU_ID_version_minor_Msk (0xf0UL) /*!< version_minor (Bitfield-Mask: 0x0f) */ + #define R_NPU_ID_version_status_Pos (0UL) /*!< version_status (Bit 0) */ + #define R_NPU_ID_version_status_Msk (0xfUL) /*!< version_status (Bitfield-Mask: 0x0f) */ +/* ======================================================== STATUS ========================================================= */ + #define R_NPU_STATUS_irq_history_mask_Pos (16UL) /*!< irq_history_mask (Bit 16) */ + #define R_NPU_STATUS_irq_history_mask_Msk (0xffff0000UL) /*!< irq_history_mask (Bitfield-Mask: 0xffff) */ + #define R_NPU_STATUS_faulting_channel_Pos (12UL) /*!< faulting_channel (Bit 12) */ + #define R_NPU_STATUS_faulting_channel_Msk (0xf000UL) /*!< faulting_channel (Bitfield-Mask: 0x0f) */ + #define R_NPU_STATUS_faulting_interface_Pos (11UL) /*!< faulting_interface (Bit 11) */ + #define R_NPU_STATUS_faulting_interface_Msk (0x800UL) /*!< faulting_interface (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_ecc_fault_Pos (8UL) /*!< ecc_fault (Bit 8) */ + #define R_NPU_STATUS_ecc_fault_Msk (0x100UL) /*!< ecc_fault (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_pmu_irq_raised_Pos (6UL) /*!< pmu_irq_raised (Bit 6) */ + #define R_NPU_STATUS_pmu_irq_raised_Msk (0x40UL) /*!< pmu_irq_raised (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_cmd_end_reached_Pos (5UL) /*!< cmd_end_reached (Bit 5) */ + #define R_NPU_STATUS_cmd_end_reached_Msk (0x20UL) /*!< cmd_end_reached (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_cmd_parse_error_Pos (4UL) /*!< cmd_parse_error (Bit 4) */ + #define R_NPU_STATUS_cmd_parse_error_Msk (0x10UL) /*!< cmd_parse_error (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_reset_status_Pos (3UL) /*!< reset_status (Bit 3) */ + #define R_NPU_STATUS_reset_status_Msk (0x8UL) /*!< reset_status (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_bus_status_Pos (2UL) /*!< bus_status (Bit 2) */ + #define R_NPU_STATUS_bus_status_Msk (0x4UL) /*!< bus_status (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_irq_raised_Pos (1UL) /*!< irq_raised (Bit 1) */ + #define R_NPU_STATUS_irq_raised_Msk (0x2UL) /*!< irq_raised (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_state_Pos (0UL) /*!< state (Bit 0) */ + #define R_NPU_STATUS_state_Msk (0x1UL) /*!< state (Bitfield-Mask: 0x01) */ +/* ========================================================== CMD ========================================================== */ + #define R_NPU_CMD_clear_irq_history_Pos (16UL) /*!< clear_irq_history (Bit 16) */ + #define R_NPU_CMD_clear_irq_history_Msk (0xffff0000UL) /*!< clear_irq_history (Bitfield-Mask: 0xffff) */ + #define R_NPU_CMD_power_q_enable_Pos (3UL) /*!< power_q_enable (Bit 3) */ + #define R_NPU_CMD_power_q_enable_Msk (0x8UL) /*!< power_q_enable (Bitfield-Mask: 0x01) */ + #define R_NPU_CMD_clock_q_enable_Pos (2UL) /*!< clock_q_enable (Bit 2) */ + #define R_NPU_CMD_clock_q_enable_Msk (0x4UL) /*!< clock_q_enable (Bitfield-Mask: 0x01) */ + #define R_NPU_CMD_clear_irq_Pos (1UL) /*!< clear_irq (Bit 1) */ + #define R_NPU_CMD_clear_irq_Msk (0x2UL) /*!< clear_irq (Bitfield-Mask: 0x01) */ + #define R_NPU_CMD_transition_to_running_state_Pos (0UL) /*!< transition_to_running_state (Bit 0) */ + #define R_NPU_CMD_transition_to_running_state_Msk (0x1UL) /*!< transition_to_running_state (Bitfield-Mask: 0x01) */ +/* ========================================================= RESET ========================================================= */ + #define R_NPU_RESET_pending_CSL_Pos (1UL) /*!< pending_CSL (Bit 1) */ + #define R_NPU_RESET_pending_CSL_Msk (0x2UL) /*!< pending_CSL (Bitfield-Mask: 0x01) */ + #define R_NPU_RESET_pending_CPL_Pos (0UL) /*!< pending_CPL (Bit 0) */ + #define R_NPU_RESET_pending_CPL_Msk (0x1UL) /*!< pending_CPL (Bitfield-Mask: 0x01) */ +/* ======================================================== QBASE0 ========================================================= */ + #define R_NPU_QBASE0_QBASE0_Pos (0UL) /*!< QBASE0 (Bit 0) */ + #define R_NPU_QBASE0_QBASE0_Msk (0xffffffffUL) /*!< QBASE0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== QBASE1 ========================================================= */ + #define R_NPU_QBASE1_QBASE1_Pos (0UL) /*!< QBASE1 (Bit 0) */ + #define R_NPU_QBASE1_QBASE1_Msk (0xffffffffUL) /*!< QBASE1 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= QREAD ========================================================= */ + #define R_NPU_QREAD_QREAD_Pos (0UL) /*!< QREAD (Bit 0) */ + #define R_NPU_QREAD_QREAD_Msk (0xffffffffUL) /*!< QREAD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== QCONFIG ======================================================== */ + #define R_NPU_QCONFIG_QCONFIG_Pos (0UL) /*!< QCONFIG (Bit 0) */ + #define R_NPU_QCONFIG_QCONFIG_Msk (0xffffffffUL) /*!< QCONFIG (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= QSIZE ========================================================= */ + #define R_NPU_QSIZE_QSIZE_Pos (0UL) /*!< QSIZE (Bit 0) */ + #define R_NPU_QSIZE_QSIZE_Msk (0xffffffffUL) /*!< QSIZE (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PROT ========================================================== */ + #define R_NPU_PROT_active_CSL_Pos (1UL) /*!< active_CSL (Bit 1) */ + #define R_NPU_PROT_active_CSL_Msk (0x2UL) /*!< active_CSL (Bitfield-Mask: 0x01) */ + #define R_NPU_PROT_active_CPL_Pos (0UL) /*!< active_CPL (Bit 0) */ + #define R_NPU_PROT_active_CPL_Msk (0x1UL) /*!< active_CPL (Bitfield-Mask: 0x01) */ +/* ======================================================== CONFIG ========================================================= */ + #define R_NPU_CONFIG_product_Pos (28UL) /*!< product (Bit 28) */ + #define R_NPU_CONFIG_product_Msk (0xf0000000UL) /*!< product (Bitfield-Mask: 0x0f) */ + #define R_NPU_CONFIG_custom_dma_Pos (27UL) /*!< custom_dma (Bit 27) */ + #define R_NPU_CONFIG_custom_dma_Msk (0x8000000UL) /*!< custom_dma (Bitfield-Mask: 0x01) */ + #define R_NPU_CONFIG_shram_size_Pos (8UL) /*!< shram_size (Bit 8) */ + #define R_NPU_CONFIG_shram_size_Msk (0xff00UL) /*!< shram_size (Bitfield-Mask: 0xff) */ + #define R_NPU_CONFIG_cmd_stream_version_Pos (4UL) /*!< cmd_stream_version (Bit 4) */ + #define R_NPU_CONFIG_cmd_stream_version_Msk (0xf0UL) /*!< cmd_stream_version (Bitfield-Mask: 0x0f) */ + #define R_NPU_CONFIG_macs_per_cc_Pos (0UL) /*!< macs_per_cc (Bit 0) */ + #define R_NPU_CONFIG_macs_per_cc_Msk (0xfUL) /*!< macs_per_cc (Bitfield-Mask: 0x0f) */ +/* ========================================================= LOCK ========================================================== */ + #define R_NPU_LOCK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ + #define R_NPU_LOCK_LOCK_Msk (0xffffffffUL) /*!< LOCK (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= REGIONCFG ======================================================= */ + #define R_NPU_REGIONCFG_region7_Pos (14UL) /*!< region7 (Bit 14) */ + #define R_NPU_REGIONCFG_region7_Msk (0xc000UL) /*!< region7 (Bitfield-Mask: 0x03) */ + #define R_NPU_REGIONCFG_region6_Pos (12UL) /*!< region6 (Bit 12) */ + #define R_NPU_REGIONCFG_region6_Msk (0x3000UL) /*!< region6 (Bitfield-Mask: 0x03) */ + #define R_NPU_REGIONCFG_region5_Pos (10UL) /*!< region5 (Bit 10) */ + #define R_NPU_REGIONCFG_region5_Msk (0xc00UL) /*!< region5 (Bitfield-Mask: 0x03) */ + #define R_NPU_REGIONCFG_region4_Pos (8UL) /*!< region4 (Bit 8) */ + #define R_NPU_REGIONCFG_region4_Msk (0x300UL) /*!< region4 (Bitfield-Mask: 0x03) */ + #define R_NPU_REGIONCFG_region3_Pos (6UL) /*!< region3 (Bit 6) */ + #define R_NPU_REGIONCFG_region3_Msk (0xc0UL) /*!< region3 (Bitfield-Mask: 0x03) */ + #define R_NPU_REGIONCFG_region2_Pos (4UL) /*!< region2 (Bit 4) */ + #define R_NPU_REGIONCFG_region2_Msk (0x30UL) /*!< region2 (Bitfield-Mask: 0x03) */ + #define R_NPU_REGIONCFG_region1_Pos (2UL) /*!< region1 (Bit 2) */ + #define R_NPU_REGIONCFG_region1_Msk (0xcUL) /*!< region1 (Bitfield-Mask: 0x03) */ + #define R_NPU_REGIONCFG_region0_Pos (0UL) /*!< region0 (Bit 0) */ + #define R_NPU_REGIONCFG_region0_Msk (0x3UL) /*!< region0 (Bitfield-Mask: 0x03) */ +/* ====================================================== AXI_LIMIT0 ======================================================= */ + #define R_NPU_AXI_LIMIT0_max_outstanding_write_m1_Pos (24UL) /*!< max_outstanding_write_m1 (Bit 24) */ + #define R_NPU_AXI_LIMIT0_max_outstanding_write_m1_Msk (0xff000000UL) /*!< max_outstanding_write_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT0_max_outstanding_read_m1_Pos (16UL) /*!< max_outstanding_read_m1 (Bit 16) */ + #define R_NPU_AXI_LIMIT0_max_outstanding_read_m1_Msk (0xff0000UL) /*!< max_outstanding_read_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT0_memtype_Pos (4UL) /*!< memtype (Bit 4) */ + #define R_NPU_AXI_LIMIT0_memtype_Msk (0xf0UL) /*!< memtype (Bitfield-Mask: 0x0f) */ + #define R_NPU_AXI_LIMIT0_max_beats_Pos (0UL) /*!< max_beats (Bit 0) */ + #define R_NPU_AXI_LIMIT0_max_beats_Msk (0x3UL) /*!< max_beats (Bitfield-Mask: 0x03) */ +/* ====================================================== AXI_LIMIT1 ======================================================= */ + #define R_NPU_AXI_LIMIT1_max_outstanding_write_m1_Pos (24UL) /*!< max_outstanding_write_m1 (Bit 24) */ + #define R_NPU_AXI_LIMIT1_max_outstanding_write_m1_Msk (0xff000000UL) /*!< max_outstanding_write_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT1_max_outstanding_read_m1_Pos (16UL) /*!< max_outstanding_read_m1 (Bit 16) */ + #define R_NPU_AXI_LIMIT1_max_outstanding_read_m1_Msk (0xff0000UL) /*!< max_outstanding_read_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT1_memtype_Pos (4UL) /*!< memtype (Bit 4) */ + #define R_NPU_AXI_LIMIT1_memtype_Msk (0xf0UL) /*!< memtype (Bitfield-Mask: 0x0f) */ + #define R_NPU_AXI_LIMIT1_max_beats_Pos (0UL) /*!< max_beats (Bit 0) */ + #define R_NPU_AXI_LIMIT1_max_beats_Msk (0x3UL) /*!< max_beats (Bitfield-Mask: 0x03) */ +/* ====================================================== AXI_LIMIT2 ======================================================= */ + #define R_NPU_AXI_LIMIT2_max_outstanding_write_m1_Pos (24UL) /*!< max_outstanding_write_m1 (Bit 24) */ + #define R_NPU_AXI_LIMIT2_max_outstanding_write_m1_Msk (0xff000000UL) /*!< max_outstanding_write_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT2_max_outstanding_read_m1_Pos (16UL) /*!< max_outstanding_read_m1 (Bit 16) */ + #define R_NPU_AXI_LIMIT2_max_outstanding_read_m1_Msk (0xff0000UL) /*!< max_outstanding_read_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT2_memtype_Pos (4UL) /*!< memtype (Bit 4) */ + #define R_NPU_AXI_LIMIT2_memtype_Msk (0xf0UL) /*!< memtype (Bitfield-Mask: 0x0f) */ + #define R_NPU_AXI_LIMIT2_max_beats_Pos (0UL) /*!< max_beats (Bit 0) */ + #define R_NPU_AXI_LIMIT2_max_beats_Msk (0x3UL) /*!< max_beats (Bitfield-Mask: 0x03) */ +/* ====================================================== AXI_LIMIT3 ======================================================= */ + #define R_NPU_AXI_LIMIT3_max_outstanding_write_m1_Pos (24UL) /*!< max_outstanding_write_m1 (Bit 24) */ + #define R_NPU_AXI_LIMIT3_max_outstanding_write_m1_Msk (0xff000000UL) /*!< max_outstanding_write_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT3_max_outstanding_read_m1_Pos (16UL) /*!< max_outstanding_read_m1 (Bit 16) */ + #define R_NPU_AXI_LIMIT3_max_outstanding_read_m1_Msk (0xff0000UL) /*!< max_outstanding_read_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT3_memtype_Pos (4UL) /*!< memtype (Bit 4) */ + #define R_NPU_AXI_LIMIT3_memtype_Msk (0xf0UL) /*!< memtype (Bitfield-Mask: 0x0f) */ + #define R_NPU_AXI_LIMIT3_max_beats_Pos (0UL) /*!< max_beats (Bit 0) */ + #define R_NPU_AXI_LIMIT3_max_beats_Msk (0x3UL) /*!< max_beats (Bitfield-Mask: 0x03) */ +/* ======================================================== BASEP0 ========================================================= */ + #define R_NPU_BASEP0_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP0_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP1 ========================================================= */ + #define R_NPU_BASEP1_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP1_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP2 ========================================================= */ + #define R_NPU_BASEP2_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP2_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP3 ========================================================= */ + #define R_NPU_BASEP3_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP3_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP4 ========================================================= */ + #define R_NPU_BASEP4_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP4_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP5 ========================================================= */ + #define R_NPU_BASEP5_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP5_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP6 ========================================================= */ + #define R_NPU_BASEP6_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP6_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP7 ========================================================= */ + #define R_NPU_BASEP7_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP7_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP8 ========================================================= */ + #define R_NPU_BASEP8_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP8_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP9 ========================================================= */ + #define R_NPU_BASEP9_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP9_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP10 ======================================================== */ + #define R_NPU_BASEP10_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP10_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP11 ======================================================== */ + #define R_NPU_BASEP11_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP11_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP12 ======================================================== */ + #define R_NPU_BASEP12_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP12_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP13 ======================================================== */ + #define R_NPU_BASEP13_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP13_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP14 ======================================================== */ + #define R_NPU_BASEP14_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP14_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP15 ======================================================== */ + #define R_NPU_BASEP15_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP15_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID4 ========================================================== */ + #define R_NPU_PID4_PID4_Pos (0UL) /*!< PID4 (Bit 0) */ + #define R_NPU_PID4_PID4_Msk (0xffffffffUL) /*!< PID4 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID5 ========================================================== */ + #define R_NPU_PID5_PID5_Pos (0UL) /*!< PID5 (Bit 0) */ + #define R_NPU_PID5_PID5_Msk (0xffffffffUL) /*!< PID5 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID6 ========================================================== */ + #define R_NPU_PID6_PID6_Pos (0UL) /*!< PID6 (Bit 0) */ + #define R_NPU_PID6_PID6_Msk (0xffffffffUL) /*!< PID6 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID7 ========================================================== */ + #define R_NPU_PID7_PID7_Pos (0UL) /*!< PID7 (Bit 0) */ + #define R_NPU_PID7_PID7_Msk (0xffffffffUL) /*!< PID7 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID0 ========================================================== */ + #define R_NPU_PID0_PID0_Pos (0UL) /*!< PID0 (Bit 0) */ + #define R_NPU_PID0_PID0_Msk (0xffffffffUL) /*!< PID0 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID1 ========================================================== */ + #define R_NPU_PID1_PID1_Pos (0UL) /*!< PID1 (Bit 0) */ + #define R_NPU_PID1_PID1_Msk (0xffffffffUL) /*!< PID1 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID2 ========================================================== */ + #define R_NPU_PID2_PID2_Pos (0UL) /*!< PID2 (Bit 0) */ + #define R_NPU_PID2_PID2_Msk (0xffffffffUL) /*!< PID2 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID3 ========================================================== */ + #define R_NPU_PID3_PID3_Pos (0UL) /*!< PID3 (Bit 0) */ + #define R_NPU_PID3_PID3_Msk (0xffffffffUL) /*!< PID3 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CID0 ========================================================== */ + #define R_NPU_CID0_CID0_Pos (0UL) /*!< CID0 (Bit 0) */ + #define R_NPU_CID0_CID0_Msk (0xffffffffUL) /*!< CID0 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CID1 ========================================================== */ + #define R_NPU_CID1_CID1_Pos (0UL) /*!< CID1 (Bit 0) */ + #define R_NPU_CID1_CID1_Msk (0xffffffffUL) /*!< CID1 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CID2 ========================================================== */ + #define R_NPU_CID2_CID2_Pos (0UL) /*!< CID2 (Bit 0) */ + #define R_NPU_CID2_CID2_Msk (0xffffffffUL) /*!< CID2 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CID3 ========================================================== */ + #define R_NPU_CID3_CID3_Pos (0UL) /*!< CID3 (Bit 0) */ + #define R_NPU_CID3_CID3_Msk (0xffffffffUL) /*!< CID3 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PMCR ========================================================== */ + #define R_NPU_PMCR_num_event_cnt_Pos (11UL) /*!< num_event_cnt (Bit 11) */ + #define R_NPU_PMCR_num_event_cnt_Msk (0xf800UL) /*!< num_event_cnt (Bitfield-Mask: 0x1f) */ + #define R_NPU_PMCR_mask_en_Pos (3UL) /*!< mask_en (Bit 3) */ + #define R_NPU_PMCR_mask_en_Msk (0x8UL) /*!< mask_en (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCR_cycle_cnt_rst_Pos (2UL) /*!< cycle_cnt_rst (Bit 2) */ + #define R_NPU_PMCR_cycle_cnt_rst_Msk (0x4UL) /*!< cycle_cnt_rst (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCR_event_cnt_rst_Pos (1UL) /*!< event_cnt_rst (Bit 1) */ + #define R_NPU_PMCR_event_cnt_rst_Msk (0x2UL) /*!< event_cnt_rst (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCR_cnt_en_Pos (0UL) /*!< cnt_en (Bit 0) */ + #define R_NPU_PMCR_cnt_en_Msk (0x1UL) /*!< cnt_en (Bitfield-Mask: 0x01) */ +/* ====================================================== PMCNTENSET ======================================================= */ + #define R_NPU_PMCNTENSET_CYCLE_CNT_Pos (31UL) /*!< CYCLE_CNT (Bit 31) */ + #define R_NPU_PMCNTENSET_CYCLE_CNT_Msk (0x80000000UL) /*!< CYCLE_CNT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_3_Pos (3UL) /*!< EVENT_CNT_3 (Bit 3) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_3_Msk (0x8UL) /*!< EVENT_CNT_3 (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_2_Pos (2UL) /*!< EVENT_CNT_2 (Bit 2) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_2_Msk (0x4UL) /*!< EVENT_CNT_2 (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_1_Pos (1UL) /*!< EVENT_CNT_1 (Bit 1) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_1_Msk (0x2UL) /*!< EVENT_CNT_1 (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_0_Pos (0UL) /*!< EVENT_CNT_0 (Bit 0) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_0_Msk (0x1UL) /*!< EVENT_CNT_0 (Bitfield-Mask: 0x01) */ +/* ====================================================== PMCNTENCLR ======================================================= */ + #define R_NPU_PMCNTENCLR_CYCLE_CNT_Pos (31UL) /*!< CYCLE_CNT (Bit 31) */ + #define R_NPU_PMCNTENCLR_CYCLE_CNT_Msk (0x80000000UL) /*!< CYCLE_CNT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_3_Pos (3UL) /*!< EVENT_CNT_3 (Bit 3) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_3_Msk (0x8UL) /*!< EVENT_CNT_3 (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_2_Pos (2UL) /*!< EVENT_CNT_2 (Bit 2) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_2_Msk (0x4UL) /*!< EVENT_CNT_2 (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_1_Pos (1UL) /*!< EVENT_CNT_1 (Bit 1) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_1_Msk (0x2UL) /*!< EVENT_CNT_1 (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_0_Pos (0UL) /*!< EVENT_CNT_0 (Bit 0) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_0_Msk (0x1UL) /*!< EVENT_CNT_0 (Bitfield-Mask: 0x01) */ +/* ======================================================= PMOVSSET ======================================================== */ + #define R_NPU_PMOVSSET_CYCLE_CNT_OVF_Pos (31UL) /*!< CYCLE_CNT_OVF (Bit 31) */ + #define R_NPU_PMOVSSET_CYCLE_CNT_OVF_Msk (0x80000000UL) /*!< CYCLE_CNT_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSSET_EVENT_CNT_3_OVF_Pos (3UL) /*!< EVENT_CNT_3_OVF (Bit 3) */ + #define R_NPU_PMOVSSET_EVENT_CNT_3_OVF_Msk (0x8UL) /*!< EVENT_CNT_3_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSSET_EVENT_CNT_2_OVF_Pos (2UL) /*!< EVENT_CNT_2_OVF (Bit 2) */ + #define R_NPU_PMOVSSET_EVENT_CNT_2_OVF_Msk (0x4UL) /*!< EVENT_CNT_2_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSSET_EVENT_CNT_1_OVF_Pos (1UL) /*!< EVENT_CNT_1_OVF (Bit 1) */ + #define R_NPU_PMOVSSET_EVENT_CNT_1_OVF_Msk (0x2UL) /*!< EVENT_CNT_1_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSSET_EVENT_CNT_0_OVF_Pos (0UL) /*!< EVENT_CNT_0_OVF (Bit 0) */ + #define R_NPU_PMOVSSET_EVENT_CNT_0_OVF_Msk (0x1UL) /*!< EVENT_CNT_0_OVF (Bitfield-Mask: 0x01) */ +/* ======================================================= PMOVSCLR ======================================================== */ + #define R_NPU_PMOVSCLR_CYCLE_CNT_OVF_Pos (31UL) /*!< CYCLE_CNT_OVF (Bit 31) */ + #define R_NPU_PMOVSCLR_CYCLE_CNT_OVF_Msk (0x80000000UL) /*!< CYCLE_CNT_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_3_OVF_Pos (3UL) /*!< EVENT_CNT_3_OVF (Bit 3) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_3_OVF_Msk (0x8UL) /*!< EVENT_CNT_3_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_2_OVF_Pos (2UL) /*!< EVENT_CNT_2_OVF (Bit 2) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_2_OVF_Msk (0x4UL) /*!< EVENT_CNT_2_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_1_OVF_Pos (1UL) /*!< EVENT_CNT_1_OVF (Bit 1) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_1_OVF_Msk (0x2UL) /*!< EVENT_CNT_1_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_0_OVF_Pos (0UL) /*!< EVENT_CNT_0_OVF (Bit 0) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_0_OVF_Msk (0x1UL) /*!< EVENT_CNT_0_OVF (Bitfield-Mask: 0x01) */ +/* ======================================================= PMINTSET ======================================================== */ + #define R_NPU_PMINTSET_CYCLE_CNT_INT_Pos (31UL) /*!< CYCLE_CNT_INT (Bit 31) */ + #define R_NPU_PMINTSET_CYCLE_CNT_INT_Msk (0x80000000UL) /*!< CYCLE_CNT_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTSET_EVENT_CNT_3_INT_Pos (3UL) /*!< EVENT_CNT_3_INT (Bit 3) */ + #define R_NPU_PMINTSET_EVENT_CNT_3_INT_Msk (0x8UL) /*!< EVENT_CNT_3_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTSET_EVENT_CNT_2_INT_Pos (2UL) /*!< EVENT_CNT_2_INT (Bit 2) */ + #define R_NPU_PMINTSET_EVENT_CNT_2_INT_Msk (0x4UL) /*!< EVENT_CNT_2_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTSET_EVENT_CNT_1_INT_Pos (1UL) /*!< EVENT_CNT_1_INT (Bit 1) */ + #define R_NPU_PMINTSET_EVENT_CNT_1_INT_Msk (0x2UL) /*!< EVENT_CNT_1_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTSET_EVENT_CNT_0_INT_Pos (0UL) /*!< EVENT_CNT_0_INT (Bit 0) */ + #define R_NPU_PMINTSET_EVENT_CNT_0_INT_Msk (0x1UL) /*!< EVENT_CNT_0_INT (Bitfield-Mask: 0x01) */ +/* ======================================================= PMINTCLR ======================================================== */ + #define R_NPU_PMINTCLR_CYCLE_CNT_INT_Pos (31UL) /*!< CYCLE_CNT_INT (Bit 31) */ + #define R_NPU_PMINTCLR_CYCLE_CNT_INT_Msk (0x80000000UL) /*!< CYCLE_CNT_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTCLR_EVENT_CNT_3_INT_Pos (3UL) /*!< EVENT_CNT_3_INT (Bit 3) */ + #define R_NPU_PMINTCLR_EVENT_CNT_3_INT_Msk (0x8UL) /*!< EVENT_CNT_3_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTCLR_EVENT_CNT_2_INT_Pos (2UL) /*!< EVENT_CNT_2_INT (Bit 2) */ + #define R_NPU_PMINTCLR_EVENT_CNT_2_INT_Msk (0x4UL) /*!< EVENT_CNT_2_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTCLR_EVENT_CNT_1_INT_Pos (1UL) /*!< EVENT_CNT_1_INT (Bit 1) */ + #define R_NPU_PMINTCLR_EVENT_CNT_1_INT_Msk (0x2UL) /*!< EVENT_CNT_1_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTCLR_EVENT_CNT_0_INT_Pos (0UL) /*!< EVENT_CNT_0_INT (Bit 0) */ + #define R_NPU_PMINTCLR_EVENT_CNT_0_INT_Msk (0x1UL) /*!< EVENT_CNT_0_INT (Bitfield-Mask: 0x01) */ +/* ====================================================== PMCCNTR_LO ======================================================= */ + #define R_NPU_PMCCNTR_LO_CYCLE_CNT_LO_Pos (0UL) /*!< CYCLE_CNT_LO (Bit 0) */ + #define R_NPU_PMCCNTR_LO_CYCLE_CNT_LO_Msk (0xffffffffUL) /*!< CYCLE_CNT_LO (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PMCCNTR_HI ======================================================= */ + #define R_NPU_PMCCNTR_HI_CYCLE_CNT_HI_Pos (0UL) /*!< CYCLE_CNT_HI (Bit 0) */ + #define R_NPU_PMCCNTR_HI_CYCLE_CNT_HI_Msk (0xffffffffUL) /*!< CYCLE_CNT_HI (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PMCAXI_CHAN ====================================================== */ + #define R_NPU_PMCAXI_CHAN_BW_CH_SEL_EN_Pos (10UL) /*!< BW_CH_SEL_EN (Bit 10) */ + #define R_NPU_PMCAXI_CHAN_BW_CH_SEL_EN_Msk (0x400UL) /*!< BW_CH_SEL_EN (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCAXI_CHAN_AXI_CNT_SEL_Pos (8UL) /*!< AXI_CNT_SEL (Bit 8) */ + #define R_NPU_PMCAXI_CHAN_AXI_CNT_SEL_Msk (0x300UL) /*!< AXI_CNT_SEL (Bitfield-Mask: 0x03) */ + #define R_NPU_PMCAXI_CHAN_CH_SEL_Pos (0UL) /*!< CH_SEL (Bit 0) */ + #define R_NPU_PMCAXI_CHAN_CH_SEL_Msk (0xfUL) /*!< CH_SEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== PMU_EVCNTR0 ====================================================== */ + #define R_NPU_PMU_EVCNTR0_PMEVCNTR_Pos (0UL) /*!< PMEVCNTR (Bit 0) */ + #define R_NPU_PMU_EVCNTR0_PMEVCNTR_Msk (0xffffffffUL) /*!< PMEVCNTR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PMU_EVCNTR1 ====================================================== */ + #define R_NPU_PMU_EVCNTR1_PMEVCNTR_Pos (0UL) /*!< PMEVCNTR (Bit 0) */ + #define R_NPU_PMU_EVCNTR1_PMEVCNTR_Msk (0xffffffffUL) /*!< PMEVCNTR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PMU_EVCNTR2 ====================================================== */ + #define R_NPU_PMU_EVCNTR2_PMEVCNTR_Pos (0UL) /*!< PMEVCNTR (Bit 0) */ + #define R_NPU_PMU_EVCNTR2_PMEVCNTR_Msk (0xffffffffUL) /*!< PMEVCNTR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PMU_EVCNTR3 ====================================================== */ + #define R_NPU_PMU_EVCNTR3_PMEVCNTR_Pos (0UL) /*!< PMEVCNTR (Bit 0) */ + #define R_NPU_PMU_EVCNTR3_PMEVCNTR_Msk (0xffffffffUL) /*!< PMEVCNTR (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== PMU_EVTYPER0 ====================================================== */ + #define R_NPU_PMU_EVTYPER0_EV_TYPE_Pos (0UL) /*!< EV_TYPE (Bit 0) */ + #define R_NPU_PMU_EVTYPER0_EV_TYPE_Msk (0xffffffffUL) /*!< EV_TYPE (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== PMU_EVTYPER1 ====================================================== */ + #define R_NPU_PMU_EVTYPER1_EV_TYPE_Pos (0UL) /*!< EV_TYPE (Bit 0) */ + #define R_NPU_PMU_EVTYPER1_EV_TYPE_Msk (0xffffffffUL) /*!< EV_TYPE (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== PMU_EVTYPER2 ====================================================== */ + #define R_NPU_PMU_EVTYPER2_EV_TYPE_Pos (0UL) /*!< EV_TYPE (Bit 0) */ + #define R_NPU_PMU_EVTYPER2_EV_TYPE_Msk (0xffffffffUL) /*!< EV_TYPE (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== PMU_EVTYPER3 ====================================================== */ + #define R_NPU_PMU_EVTYPER3_EV_TYPE_Pos (0UL) /*!< EV_TYPE (Bit 0) */ + #define R_NPU_PMU_EVTYPER3_EV_TYPE_Msk (0xffffffffUL) /*!< EV_TYPE (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_PDM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PDCSTRTR ======================================================== */ + #define R_PDM_PDCSTRTR_STRTRG0_Pos (0UL) /*!< STRTRG0 (Bit 0) */ + #define R_PDM_PDCSTRTR_STRTRG0_Msk (0x1UL) /*!< STRTRG0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSTRTR_STRTRG1_Pos (1UL) /*!< STRTRG1 (Bit 1) */ + #define R_PDM_PDCSTRTR_STRTRG1_Msk (0x2UL) /*!< STRTRG1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSTRTR_STRTRG2_Pos (2UL) /*!< STRTRG2 (Bit 2) */ + #define R_PDM_PDCSTRTR_STRTRG2_Msk (0x4UL) /*!< STRTRG2 (Bitfield-Mask: 0x01) */ +/* ======================================================= PDCSTPTR ======================================================== */ + #define R_PDM_PDCSTPTR_STPTRG0_Pos (0UL) /*!< STPTRG0 (Bit 0) */ + #define R_PDM_PDCSTPTR_STPTRG0_Msk (0x1UL) /*!< STPTRG0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSTPTR_STPTRG1_Pos (1UL) /*!< STPTRG1 (Bit 1) */ + #define R_PDM_PDCSTPTR_STPTRG1_Msk (0x2UL) /*!< STPTRG1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSTPTR_STPTRG2_Pos (2UL) /*!< STPTRG2 (Bit 2) */ + #define R_PDM_PDCSTPTR_STPTRG2_Msk (0x4UL) /*!< STPTRG2 (Bitfield-Mask: 0x01) */ +/* ======================================================= PDCCHGTR ======================================================== */ + #define R_PDM_PDCCHGTR_CHGTRG0_Pos (0UL) /*!< CHGTRG0 (Bit 0) */ + #define R_PDM_PDCCHGTR_CHGTRG0_Msk (0x1UL) /*!< CHGTRG0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCCHGTR_CHGTRG1_Pos (1UL) /*!< CHGTRG1 (Bit 1) */ + #define R_PDM_PDCCHGTR_CHGTRG1_Msk (0x2UL) /*!< CHGTRG1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCCHGTR_CHGTRG2_Pos (2UL) /*!< CHGTRG2 (Bit 2) */ + #define R_PDM_PDCCHGTR_CHGTRG2_Msk (0x4UL) /*!< CHGTRG2 (Bitfield-Mask: 0x01) */ +/* ======================================================== PDCICR ========================================================= */ + #define R_PDM_PDCICR_ISDE0_Pos (8UL) /*!< ISDE0 (Bit 8) */ + #define R_PDM_PDCICR_ISDE0_Msk (0x100UL) /*!< ISDE0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_ISDE1_Pos (9UL) /*!< ISDE1 (Bit 9) */ + #define R_PDM_PDCICR_ISDE1_Msk (0x200UL) /*!< ISDE1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_ISDE2_Pos (10UL) /*!< ISDE2 (Bit 10) */ + #define R_PDM_PDCICR_ISDE2_Msk (0x400UL) /*!< ISDE2 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_IDRE0_Pos (16UL) /*!< IDRE0 (Bit 16) */ + #define R_PDM_PDCICR_IDRE0_Msk (0x10000UL) /*!< IDRE0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_IDRE1_Pos (17UL) /*!< IDRE1 (Bit 17) */ + #define R_PDM_PDCICR_IDRE1_Msk (0x20000UL) /*!< IDRE1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_IDRE2_Pos (18UL) /*!< IDRE2 (Bit 18) */ + #define R_PDM_PDCICR_IDRE2_Msk (0x40000UL) /*!< IDRE2 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_IEDE0_Pos (24UL) /*!< IEDE0 (Bit 24) */ + #define R_PDM_PDCICR_IEDE0_Msk (0x1000000UL) /*!< IEDE0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_IEDE1_Pos (25UL) /*!< IEDE1 (Bit 25) */ + #define R_PDM_PDCICR_IEDE1_Msk (0x2000000UL) /*!< IEDE1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_IEDE2_Pos (26UL) /*!< IEDE2 (Bit 26) */ + #define R_PDM_PDCICR_IEDE2_Msk (0x4000000UL) /*!< IEDE2 (Bitfield-Mask: 0x01) */ +/* ========================================================= PDCSR ========================================================= */ + #define R_PDM_PDCSR_STATE0_Pos (0UL) /*!< STATE0 (Bit 0) */ + #define R_PDM_PDCSR_STATE0_Msk (0x1UL) /*!< STATE0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_STATE1_Pos (1UL) /*!< STATE1 (Bit 1) */ + #define R_PDM_PDCSR_STATE1_Msk (0x2UL) /*!< STATE1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_STATE2_Pos (2UL) /*!< STATE2 (Bit 2) */ + #define R_PDM_PDCSR_STATE2_Msk (0x4UL) /*!< STATE2 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_SDF0_Pos (8UL) /*!< SDF0 (Bit 8) */ + #define R_PDM_PDCSR_SDF0_Msk (0x100UL) /*!< SDF0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_SDF1_Pos (9UL) /*!< SDF1 (Bit 9) */ + #define R_PDM_PDCSR_SDF1_Msk (0x200UL) /*!< SDF1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_SDF2_Pos (10UL) /*!< SDF2 (Bit 10) */ + #define R_PDM_PDCSR_SDF2_Msk (0x400UL) /*!< SDF2 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_DRF0_Pos (16UL) /*!< DRF0 (Bit 16) */ + #define R_PDM_PDCSR_DRF0_Msk (0x10000UL) /*!< DRF0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_DRF1_Pos (17UL) /*!< DRF1 (Bit 17) */ + #define R_PDM_PDCSR_DRF1_Msk (0x20000UL) /*!< DRF1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_DRF2_Pos (18UL) /*!< DRF2 (Bit 18) */ + #define R_PDM_PDCSR_DRF2_Msk (0x40000UL) /*!< DRF2 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_EDF0_Pos (24UL) /*!< EDF0 (Bit 24) */ + #define R_PDM_PDCSR_EDF0_Msk (0x1000000UL) /*!< EDF0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_EDF1_Pos (25UL) /*!< EDF1 (Bit 25) */ + #define R_PDM_PDCSR_EDF1_Msk (0x2000000UL) /*!< EDF1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_EDF2_Pos (26UL) /*!< EDF2 (Bit 26) */ + #define R_PDM_PDCSR_EDF2_Msk (0x4000000UL) /*!< EDF2 (Bitfield-Mask: 0x01) */ +/* ======================================================== PDCSCR ========================================================= */ + #define R_PDM_PDCSCR_SDFC0_Pos (8UL) /*!< SDFC0 (Bit 8) */ + #define R_PDM_PDCSCR_SDFC0_Msk (0x100UL) /*!< SDFC0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSCR_SDFC1_Pos (9UL) /*!< SDFC1 (Bit 9) */ + #define R_PDM_PDCSCR_SDFC1_Msk (0x200UL) /*!< SDFC1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSCR_SDFC2_Pos (10UL) /*!< SDFC2 (Bit 10) */ + #define R_PDM_PDCSCR_SDFC2_Msk (0x400UL) /*!< SDFC2 (Bitfield-Mask: 0x01) */ +/* ======================================================== PDCSDCR ======================================================== */ + #define R_PDM_PDCSDCR_SDE0_Pos (0UL) /*!< SDE0 (Bit 0) */ + #define R_PDM_PDCSDCR_SDE0_Msk (0x1UL) /*!< SDE0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSDCR_SDE1_Pos (1UL) /*!< SDE1 (Bit 1) */ + #define R_PDM_PDCSDCR_SDE1_Msk (0x2UL) /*!< SDE1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSDCR_SDE2_Pos (2UL) /*!< SDE2 (Bit 2) */ + #define R_PDM_PDCSDCR_SDE2_Msk (0x4UL) /*!< SDE2 (Bitfield-Mask: 0x01) */ +/* ======================================================== PDCDRCR ======================================================== */ + #define R_PDM_PDCDRCR_DATRE0_Pos (0UL) /*!< DATRE0 (Bit 0) */ + #define R_PDM_PDCDRCR_DATRE0_Msk (0x1UL) /*!< DATRE0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCDRCR_DATRE1_Pos (1UL) /*!< DATRE1 (Bit 1) */ + #define R_PDM_PDCDRCR_DATRE1_Msk (0x2UL) /*!< DATRE1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCDRCR_DATRE2_Pos (2UL) /*!< DATRE2 (Bit 2) */ + #define R_PDM_PDCDRCR_DATRE2_Msk (0x4UL) /*!< DATRE2 (Bitfield-Mask: 0x01) */ +/* ======================================================== PDCDCR ========================================================= */ + #define R_PDM_PDCDCR_DATC0_Pos (0UL) /*!< DATC0 (Bit 0) */ + #define R_PDM_PDCDCR_DATC0_Msk (0x1UL) /*!< DATC0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCDCR_DATC1_Pos (1UL) /*!< DATC1 (Bit 1) */ + #define R_PDM_PDCDCR_DATC1_Msk (0x2UL) /*!< DATC1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCDCR_DATC2_Pos (2UL) /*!< DATC2 (Bit 2) */ + #define R_PDM_PDCDCR_DATC2_Msk (0x4UL) /*!< DATC2 (Bitfield-Mask: 0x01) */ +/* ========================================================= PDVR ========================================================== */ + #define R_PDM_PDVR_VER_Pos (0UL) /*!< VER (Bit 0) */ + #define R_PDM_PDVR_VER_Msk (0xfffUL) /*!< VER (Bitfield-Mask: 0xfff) */ + +/* =========================================================================================================================== */ +/* ================ R_RMAC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= MPSM ========================================================== */ + #define R_RMAC0_MPSM_PSME_Pos (0UL) /*!< PSME (Bit 0) */ + #define R_RMAC0_MPSM_PSME_Msk (0x1UL) /*!< PSME (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPSM_MFF_Pos (2UL) /*!< MFF (Bit 2) */ + #define R_RMAC0_MPSM_MFF_Msk (0x4UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPSM_PDA_Pos (3UL) /*!< PDA (Bit 3) */ + #define R_RMAC0_MPSM_PDA_Msk (0xf8UL) /*!< PDA (Bitfield-Mask: 0x1f) */ + #define R_RMAC0_MPSM_PRA_Pos (8UL) /*!< PRA (Bit 8) */ + #define R_RMAC0_MPSM_PRA_Msk (0x1f00UL) /*!< PRA (Bitfield-Mask: 0x1f) */ + #define R_RMAC0_MPSM_POP_Pos (13UL) /*!< POP (Bit 13) */ + #define R_RMAC0_MPSM_POP_Msk (0x6000UL) /*!< POP (Bitfield-Mask: 0x03) */ + #define R_RMAC0_MPSM_PRD_Pos (16UL) /*!< PRD (Bit 16) */ + #define R_RMAC0_MPSM_PRD_Msk (0xffff0000UL) /*!< PRD (Bitfield-Mask: 0xffff) */ +/* ========================================================= MPIC ========================================================== */ + #define R_RMAC0_MPIC_PIS_Pos (0UL) /*!< PIS (Bit 0) */ + #define R_RMAC0_MPIC_PIS_Msk (0x7UL) /*!< PIS (Bitfield-Mask: 0x07) */ + #define R_RMAC0_MPIC_LSC_Pos (3UL) /*!< LSC (Bit 3) */ + #define R_RMAC0_MPIC_LSC_Msk (0x38UL) /*!< LSC (Bitfield-Mask: 0x07) */ + #define R_RMAC0_MPIC_PIP_Pos (8UL) /*!< PIP (Bit 8) */ + #define R_RMAC0_MPIC_PIP_Msk (0x100UL) /*!< PIP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPIC_PIPP_Pos (9UL) /*!< PIPP (Bit 9) */ + #define R_RMAC0_MPIC_PIPP_Msk (0x200UL) /*!< PIPP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPIC_PLSPP_Pos (10UL) /*!< PLSPP (Bit 10) */ + #define R_RMAC0_MPIC_PLSPP_Msk (0x400UL) /*!< PLSPP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPIC_PSMCS_Pos (16UL) /*!< PSMCS (Bit 16) */ + #define R_RMAC0_MPIC_PSMCS_Msk (0x7f0000UL) /*!< PSMCS (Bitfield-Mask: 0x7f) */ + #define R_RMAC0_MPIC_PSMDP_Pos (23UL) /*!< PSMDP (Bit 23) */ + #define R_RMAC0_MPIC_PSMDP_Msk (0x800000UL) /*!< PSMDP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPIC_PSMHT_Pos (24UL) /*!< PSMHT (Bit 24) */ + #define R_RMAC0_MPIC_PSMHT_Msk (0x7000000UL) /*!< PSMHT (Bitfield-Mask: 0x07) */ + #define R_RMAC0_MPIC_PSMCT_Pos (28UL) /*!< PSMCT (Bit 28) */ + #define R_RMAC0_MPIC_PSMCT_Msk (0x70000000UL) /*!< PSMCT (Bitfield-Mask: 0x07) */ +/* ========================================================= MPIM ========================================================== */ + #define R_RMAC0_MPIM_PLS_Pos (0UL) /*!< PLS (Bit 0) */ + #define R_RMAC0_MPIM_PLS_Msk (0x1UL) /*!< PLS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPIM_LPIA_Pos (1UL) /*!< LPIA (Bit 1) */ + #define R_RMAC0_MPIM_LPIA_Msk (0x2UL) /*!< LPIA (Bitfield-Mask: 0x01) */ +/* ========================================================= MIOC ========================================================== */ + #define R_RMAC0_MIOC_MIOC_Pos (0UL) /*!< MIOC (Bit 0) */ + #define R_RMAC0_MIOC_MIOC_Msk (0xffffffffUL) /*!< MIOC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MTFFC ========================================================= */ + #define R_RMAC0_MTFFC_DPAD_Pos (0UL) /*!< DPAD (Bit 0) */ + #define R_RMAC0_MTFFC_DPAD_Msk (0x1UL) /*!< DPAD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTFFC_FCM_Pos (1UL) /*!< FCM (Bit 1) */ + #define R_RMAC0_MTFFC_FCM_Msk (0x2UL) /*!< FCM (Bitfield-Mask: 0x01) */ +/* ========================================================= MTPFC ========================================================= */ + #define R_RMAC0_MTPFC_PT_Pos (0UL) /*!< PT (Bit 0) */ + #define R_RMAC0_MTPFC_PT_Msk (0xffffUL) /*!< PT (Bitfield-Mask: 0xffff) */ + #define R_RMAC0_MTPFC_PFRT_Pos (16UL) /*!< PFRT (Bit 16) */ + #define R_RMAC0_MTPFC_PFRT_Msk (0xff0000UL) /*!< PFRT (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MTPFC_PFM_Pos (26UL) /*!< PFM (Bit 26) */ + #define R_RMAC0_MTPFC_PFM_Msk (0x4000000UL) /*!< PFM (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTPFC_PFRLV_Pos (27UL) /*!< PFRLV (Bit 27) */ + #define R_RMAC0_MTPFC_PFRLV_Msk (0xf8000000UL) /*!< PFRLV (Bitfield-Mask: 0x1f) */ +/* ======================================================== MTPFC2 ========================================================= */ + #define R_RMAC0_MTPFC2_PFCTTZ_Pos (0UL) /*!< PFCTTZ (Bit 0) */ + #define R_RMAC0_MTPFC2_PFCTTZ_Msk (0x3UL) /*!< PFCTTZ (Bitfield-Mask: 0x03) */ + #define R_RMAC0_MTPFC2_MPFCFR0_Pos (8UL) /*!< MPFCFR0 (Bit 8) */ + #define R_RMAC0_MTPFC2_MPFCFR0_Msk (0x100UL) /*!< MPFCFR0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTPFC2_MPFCFR1_Pos (9UL) /*!< MPFCFR1 (Bit 9) */ + #define R_RMAC0_MTPFC2_MPFCFR1_Msk (0x200UL) /*!< MPFCFR1 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTPFC2_PFTTZ_Pos (16UL) /*!< PFTTZ (Bit 16) */ + #define R_RMAC0_MTPFC2_PFTTZ_Msk (0x10000UL) /*!< PFTTZ (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTPFC2_MPFR_Pos (17UL) /*!< MPFR (Bit 17) */ + #define R_RMAC0_MTPFC2_MPFR_Msk (0x20000UL) /*!< MPFR (Bitfield-Mask: 0x01) */ +/* ======================================================== MTPFC30 ======================================================== */ + #define R_RMAC0_MTPFC30_PFCPG_Pos (0UL) /*!< PFCPG (Bit 0) */ + #define R_RMAC0_MTPFC30_PFCPG_Msk (0xffUL) /*!< PFCPG (Bitfield-Mask: 0xff) */ +/* ======================================================== MTPFC31 ======================================================== */ + #define R_RMAC0_MTPFC31_PFCPG_Pos (0UL) /*!< PFCPG (Bit 0) */ + #define R_RMAC0_MTPFC31_PFCPG_Msk (0xffUL) /*!< PFCPG (Bitfield-Mask: 0xff) */ +/* ======================================================== MTATC0 ========================================================= */ + #define R_RMAC0_MTATC0_TRTP_Pos (0UL) /*!< TRTP (Bit 0) */ + #define R_RMAC0_MTATC0_TRTP_Msk (0xffUL) /*!< TRTP (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MTATC0_TRTL_Pos (8UL) /*!< TRTL (Bit 8) */ + #define R_RMAC0_MTATC0_TRTL_Msk (0x700UL) /*!< TRTL (Bitfield-Mask: 0x07) */ +/* ======================================================== MTATC1 ========================================================= */ + #define R_RMAC0_MTATC1_TRTP_Pos (0UL) /*!< TRTP (Bit 0) */ + #define R_RMAC0_MTATC1_TRTP_Msk (0xffUL) /*!< TRTP (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MTATC1_TRTL_Pos (8UL) /*!< TRTL (Bit 8) */ + #define R_RMAC0_MTATC1_TRTL_Msk (0x700UL) /*!< TRTL (Bitfield-Mask: 0x07) */ +/* ========================================================= MTIM ========================================================== */ + #define R_RMAC0_MTIM_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_RMAC0_MTIM_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ +/* ========================================================= MRGC ========================================================== */ + #define R_RMAC0_MRGC_RCPT_Pos (0UL) /*!< RCPT (Bit 0) */ + #define R_RMAC0_MRGC_RCPT_Msk (0x1UL) /*!< RCPT (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRGC_PFRC_Pos (1UL) /*!< PFRC (Bit 1) */ + #define R_RMAC0_MRGC_PFRC_Msk (0x2UL) /*!< PFRC (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRGC_PFRTZ_Pos (2UL) /*!< PFRTZ (Bit 2) */ + #define R_RMAC0_MRGC_PFRTZ_Msk (0x4UL) /*!< PFRTZ (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRGC_MPDE_Pos (3UL) /*!< MPDE (Bit 3) */ + #define R_RMAC0_MRGC_MPDE_Msk (0x8UL) /*!< MPDE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRGC_RFCFE_Pos (4UL) /*!< RFCFE (Bit 4) */ + #define R_RMAC0_MRGC_RFCFE_Msk (0x10UL) /*!< RFCFE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRGC_PFCRC_Pos (16UL) /*!< PFCRC (Bit 16) */ + #define R_RMAC0_MRGC_PFCRC_Msk (0xff0000UL) /*!< PFCRC (Bitfield-Mask: 0xff) */ +/* ======================================================== MRMAC0 ========================================================= */ + #define R_RMAC0_MRMAC0_MAU_Pos (0UL) /*!< MAU (Bit 0) */ + #define R_RMAC0_MRMAC0_MAU_Msk (0xffffUL) /*!< MAU (Bitfield-Mask: 0xffff) */ +/* ======================================================== MRMAC1 ========================================================= */ + #define R_RMAC0_MRMAC1_MAL_Pos (0UL) /*!< MAL (Bit 0) */ + #define R_RMAC0_MRMAC1_MAL_Msk (0xffffffffUL) /*!< MAL (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MRAFC ========================================================= */ + #define R_RMAC0_MRAFC_UCENE_Pos (0UL) /*!< UCENE (Bit 0) */ + #define R_RMAC0_MRAFC_UCENE_Msk (0x1UL) /*!< UCENE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MCENE_Pos (1UL) /*!< MCENE (Bit 1) */ + #define R_RMAC0_MRAFC_MCENE_Msk (0x2UL) /*!< MCENE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_BCENE_Pos (2UL) /*!< BCENE (Bit 2) */ + #define R_RMAC0_MRAFC_BCENE_Msk (0x4UL) /*!< BCENE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MSTENE_Pos (3UL) /*!< MSTENE (Bit 3) */ + #define R_RMAC0_MRAFC_MSTENE_Msk (0x8UL) /*!< MSTENE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_BSTENE_Pos (4UL) /*!< BSTENE (Bit 4) */ + #define R_RMAC0_MRAFC_BSTENE_Msk (0x10UL) /*!< BSTENE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MCACE_Pos (5UL) /*!< MCACE (Bit 5) */ + #define R_RMAC0_MRAFC_MCACE_Msk (0x20UL) /*!< MCACE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_BCACE_Pos (6UL) /*!< BCACE (Bit 6) */ + #define R_RMAC0_MRAFC_BCACE_Msk (0x40UL) /*!< BCACE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_NDAREE_Pos (7UL) /*!< NDAREE (Bit 7) */ + #define R_RMAC0_MRAFC_NDAREE_Msk (0x80UL) /*!< NDAREE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_SDSFREE_Pos (8UL) /*!< SDSFREE (Bit 8) */ + #define R_RMAC0_MRAFC_SDSFREE_Msk (0x100UL) /*!< SDSFREE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_NSAREE_Pos (9UL) /*!< NSAREE (Bit 9) */ + #define R_RMAC0_MRAFC_NSAREE_Msk (0x200UL) /*!< NSAREE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MSAREE_Pos (10UL) /*!< MSAREE (Bit 10) */ + #define R_RMAC0_MRAFC_MSAREE_Msk (0x400UL) /*!< MSAREE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_UCENP_Pos (16UL) /*!< UCENP (Bit 16) */ + #define R_RMAC0_MRAFC_UCENP_Msk (0x10000UL) /*!< UCENP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MCENP_Pos (17UL) /*!< MCENP (Bit 17) */ + #define R_RMAC0_MRAFC_MCENP_Msk (0x20000UL) /*!< MCENP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_BCENP_Pos (18UL) /*!< BCENP (Bit 18) */ + #define R_RMAC0_MRAFC_BCENP_Msk (0x40000UL) /*!< BCENP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MSTENP_Pos (19UL) /*!< MSTENP (Bit 19) */ + #define R_RMAC0_MRAFC_MSTENP_Msk (0x80000UL) /*!< MSTENP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_BSTENP_Pos (20UL) /*!< BSTENP (Bit 20) */ + #define R_RMAC0_MRAFC_BSTENP_Msk (0x100000UL) /*!< BSTENP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MCACP_Pos (21UL) /*!< MCACP (Bit 21) */ + #define R_RMAC0_MRAFC_MCACP_Msk (0x200000UL) /*!< MCACP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_BCACP_Pos (22UL) /*!< BCACP (Bit 22) */ + #define R_RMAC0_MRAFC_BCACP_Msk (0x400000UL) /*!< BCACP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_NDAREP_Pos (23UL) /*!< NDAREP (Bit 23) */ + #define R_RMAC0_MRAFC_NDAREP_Msk (0x800000UL) /*!< NDAREP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_SDSFREP_Pos (24UL) /*!< SDSFREP (Bit 24) */ + #define R_RMAC0_MRAFC_SDSFREP_Msk (0x1000000UL) /*!< SDSFREP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_NSAREP_Pos (25UL) /*!< NSAREP (Bit 25) */ + #define R_RMAC0_MRAFC_NSAREP_Msk (0x2000000UL) /*!< NSAREP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MSAREP_Pos (26UL) /*!< MSAREP (Bit 26) */ + #define R_RMAC0_MRAFC_MSAREP_Msk (0x4000000UL) /*!< MSAREP (Bitfield-Mask: 0x01) */ +/* ========================================================= MRSCE ========================================================= */ + #define R_RMAC0_MRSCE_CMFE_Pos (0UL) /*!< CMFE (Bit 0) */ + #define R_RMAC0_MRSCE_CMFE_Msk (0xffffUL) /*!< CMFE (Bitfield-Mask: 0xffff) */ + #define R_RMAC0_MRSCE_CBFE_Pos (16UL) /*!< CBFE (Bit 16) */ + #define R_RMAC0_MRSCE_CBFE_Msk (0xffff0000UL) /*!< CBFE (Bitfield-Mask: 0xffff) */ +/* ========================================================= MRSCP ========================================================= */ + #define R_RMAC0_MRSCP_CMFP_Pos (0UL) /*!< CMFP (Bit 0) */ + #define R_RMAC0_MRSCP_CMFP_Msk (0xffffUL) /*!< CMFP (Bitfield-Mask: 0xffff) */ + #define R_RMAC0_MRSCP_CBFP_Pos (16UL) /*!< CBFP (Bit 16) */ + #define R_RMAC0_MRSCP_CBFP_Msk (0xffff0000UL) /*!< CBFP (Bitfield-Mask: 0xffff) */ +/* ========================================================= MRSCC ========================================================= */ + #define R_RMAC0_MRSCC_MSCCE_Pos (0UL) /*!< MSCCE (Bit 0) */ + #define R_RMAC0_MRSCC_MSCCE_Msk (0x1UL) /*!< MSCCE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRSCC_BSCCE_Pos (1UL) /*!< BSCCE (Bit 1) */ + #define R_RMAC0_MRSCC_BSCCE_Msk (0x2UL) /*!< BSCCE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRSCC_MSCCP_Pos (16UL) /*!< MSCCP (Bit 16) */ + #define R_RMAC0_MRSCC_MSCCP_Msk (0x10000UL) /*!< MSCCP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRSCC_BSCCP_Pos (17UL) /*!< BSCCP (Bit 17) */ + #define R_RMAC0_MRSCC_BSCCP_Msk (0x20000UL) /*!< BSCCP (Bitfield-Mask: 0x01) */ +/* ======================================================== MRFSCE ========================================================= */ + #define R_RMAC0_MRFSCE_EMXS_Pos (0UL) /*!< EMXS (Bit 0) */ + #define R_RMAC0_MRFSCE_EMXS_Msk (0xffffUL) /*!< EMXS (Bitfield-Mask: 0xffff) */ + #define R_RMAC0_MRFSCE_EMNS_Pos (16UL) /*!< EMNS (Bit 16) */ + #define R_RMAC0_MRFSCE_EMNS_Msk (0xffff0000UL) /*!< EMNS (Bitfield-Mask: 0xffff) */ +/* ======================================================== MRFSCP ========================================================= */ + #define R_RMAC0_MRFSCP_PMXS_Pos (0UL) /*!< PMXS (Bit 0) */ + #define R_RMAC0_MRFSCP_PMXS_Msk (0xffffUL) /*!< PMXS (Bitfield-Mask: 0xffff) */ + #define R_RMAC0_MRFSCP_PMNS_Pos (16UL) /*!< PMNS (Bit 16) */ + #define R_RMAC0_MRFSCP_PMNS_Msk (0xffff0000UL) /*!< PMNS (Bitfield-Mask: 0xffff) */ +/* ========================================================= MTRC ========================================================== */ + #define R_RMAC0_MTRC_TRHFME0_Pos (0UL) /*!< TRHFME0 (Bit 0) */ + #define R_RMAC0_MTRC_TRHFME0_Msk (0x1UL) /*!< TRHFME0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTRC_TRHFME1_Pos (1UL) /*!< TRHFME1 (Bit 1) */ + #define R_RMAC0_MTRC_TRHFME1_Msk (0x2UL) /*!< TRHFME1 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTRC_TRDDE_Pos (24UL) /*!< TRDDE (Bit 24) */ + #define R_RMAC0_MTRC_TRDDE_Msk (0x1000000UL) /*!< TRDDE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTRC_TRDDP_Pos (25UL) /*!< TRDDP (Bit 25) */ + #define R_RMAC0_MTRC_TRDDP_Msk (0x2000000UL) /*!< TRDDP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTRC_TCTSE_Pos (26UL) /*!< TCTSE (Bit 26) */ + #define R_RMAC0_MTRC_TCTSE_Msk (0x4000000UL) /*!< TCTSE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTRC_TCTSP_Pos (27UL) /*!< TCTSP (Bit 27) */ + #define R_RMAC0_MTRC_TCTSP_Msk (0x8000000UL) /*!< TCTSP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTRC_DTN_Pos (28UL) /*!< DTN (Bit 28) */ + #define R_RMAC0_MTRC_DTN_Msk (0x10000000UL) /*!< DTN (Bitfield-Mask: 0x01) */ +/* ========================================================= MRPFM ========================================================= */ + #define R_RMAC0_MRPFM_PTCA_Pos (0UL) /*!< PTCA (Bit 0) */ + #define R_RMAC0_MRPFM_PTCA_Msk (0x1UL) /*!< PTCA (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRPFM_PFCTCA_Pos (16UL) /*!< PFCTCA (Bit 16) */ + #define R_RMAC0_MRPFM_PFCTCA_Msk (0xff0000UL) /*!< PFCTCA (Bitfield-Mask: 0xff) */ +/* ========================================================= MPFC0 ========================================================= */ + #define R_RMAC0_MPFC0_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC0_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC0_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC0_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC0_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC0_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC0_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC0_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC1 ========================================================= */ + #define R_RMAC0_MPFC1_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC1_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC1_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC1_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC1_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC1_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC1_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC1_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC2 ========================================================= */ + #define R_RMAC0_MPFC2_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC2_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC2_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC2_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC2_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC2_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC2_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC2_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC3 ========================================================= */ + #define R_RMAC0_MPFC3_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC3_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC3_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC3_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC3_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC3_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC3_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC3_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC4 ========================================================= */ + #define R_RMAC0_MPFC4_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC4_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC4_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC4_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC4_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC4_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC4_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC4_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC5 ========================================================= */ + #define R_RMAC0_MPFC5_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC5_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC5_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC5_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC5_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC5_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC5_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC5_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC6 ========================================================= */ + #define R_RMAC0_MPFC6_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC6_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC6_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC6_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC6_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC6_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC6_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC6_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC7 ========================================================= */ + #define R_RMAC0_MPFC7_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC7_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC7_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC7_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC7_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC7_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC7_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC7_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC8 ========================================================= */ + #define R_RMAC0_MPFC8_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC8_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC8_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC8_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC8_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC8_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC8_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC8_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC9 ========================================================= */ + #define R_RMAC0_MPFC9_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC9_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC9_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC9_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC9_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC9_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC9_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC9_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MPFC10 ========================================================= */ + #define R_RMAC0_MPFC10_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC10_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC10_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC10_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC10_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC10_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC10_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC10_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MPFC11 ========================================================= */ + #define R_RMAC0_MPFC11_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC11_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC11_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC11_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC11_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC11_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC11_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC11_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MPFC12 ========================================================= */ + #define R_RMAC0_MPFC12_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC12_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC12_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC12_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC12_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC12_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC12_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC12_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MPFC13 ========================================================= */ + #define R_RMAC0_MPFC13_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC13_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC13_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC13_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC13_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC13_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC13_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC13_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MPFC14 ========================================================= */ + #define R_RMAC0_MPFC14_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC14_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC14_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC14_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC14_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC14_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC14_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC14_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MPFC15 ========================================================= */ + #define R_RMAC0_MPFC15_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC15_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC15_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC15_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC15_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC15_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC15_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC15_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MLVC ========================================================== */ + #define R_RMAC0_MLVC_LVT_Pos (0UL) /*!< LVT (Bit 0) */ + #define R_RMAC0_MLVC_LVT_Msk (0x7fUL) /*!< LVT (Bitfield-Mask: 0x7f) */ + #define R_RMAC0_MLVC_PASE_Pos (8UL) /*!< PASE (Bit 8) */ + #define R_RMAC0_MLVC_PASE_Msk (0x100UL) /*!< PASE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MLVC_PLV_Pos (16UL) /*!< PLV (Bit 16) */ + #define R_RMAC0_MLVC_PLV_Msk (0x10000UL) /*!< PLV (Bitfield-Mask: 0x01) */ +/* ========================================================= MEEEC ========================================================= */ + #define R_RMAC0_MEEEC_LPITR_Pos (0UL) /*!< LPITR (Bit 0) */ + #define R_RMAC0_MEEEC_LPITR_Msk (0x1UL) /*!< LPITR (Bitfield-Mask: 0x01) */ +/* ========================================================= MLBC ========================================================== */ + #define R_RMAC0_MLBC_LBME_Pos (0UL) /*!< LBME (Bit 0) */ + #define R_RMAC0_MLBC_LBME_Msk (0x1UL) /*!< LBME (Bitfield-Mask: 0x01) */ +/* ======================================================== MXGMIIC ======================================================== */ + #define R_RMAC0_MXGMIIC_LFS_TXRFS_Pos (0UL) /*!< LFS_TXRFS (Bit 0) */ + #define R_RMAC0_MXGMIIC_LFS_TXRFS_Msk (0x1UL) /*!< LFS_TXRFS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MXGMIIC_LFS_TXIDLE_Pos (1UL) /*!< LFS_TXIDLE (Bit 1) */ + #define R_RMAC0_MXGMIIC_LFS_TXIDLE_Msk (0x2UL) /*!< LFS_TXIDLE (Bitfield-Mask: 0x01) */ +/* ========================================================= MPCH ========================================================== */ + #define R_RMAC0_MPCH_TXPCH_M_Pos (0UL) /*!< TXPCH_M (Bit 0) */ + #define R_RMAC0_MPCH_TXPCH_M_Msk (0x1UL) /*!< TXPCH_M (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPCH_TXPCH_ETYPE_Pos (2UL) /*!< TXPCH_ETYPE (Bit 2) */ + #define R_RMAC0_MPCH_TXPCH_ETYPE_Msk (0xcUL) /*!< TXPCH_ETYPE (Bitfield-Mask: 0x03) */ + #define R_RMAC0_MPCH_TXPCH_PID_Pos (4UL) /*!< TXPCH_PID (Bit 4) */ + #define R_RMAC0_MPCH_TXPCH_PID_Msk (0xf0UL) /*!< TXPCH_PID (Bitfield-Mask: 0x0f) */ + #define R_RMAC0_MPCH_IETPTE_Pos (8UL) /*!< IETPTE (Bit 8) */ + #define R_RMAC0_MPCH_IETPTE_Msk (0x100UL) /*!< IETPTE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPCH_CTPTE_Pos (9UL) /*!< CTPTE (Bit 9) */ + #define R_RMAC0_MPCH_CTPTE_Msk (0x200UL) /*!< CTPTE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPCH_IETRIOD_Pos (10UL) /*!< IETRIOD (Bit 10) */ + #define R_RMAC0_MPCH_IETRIOD_Msk (0x400UL) /*!< IETRIOD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPCH_CTRIOD_Pos (11UL) /*!< CTRIOD (Bit 11) */ + #define R_RMAC0_MPCH_CTRIOD_Msk (0x800UL) /*!< CTRIOD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPCH_RXPCH_TSM_Pos (16UL) /*!< RXPCH_TSM (Bit 16) */ + #define R_RMAC0_MPCH_RXPCH_TSM_Msk (0x10000UL) /*!< RXPCH_TSM (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPCH_RPHCRCD_Pos (17UL) /*!< RPHCRCD (Bit 17) */ + #define R_RMAC0_MPCH_RPHCRCD_Msk (0x20000UL) /*!< RPHCRCD (Bitfield-Mask: 0x01) */ +/* ========================================================= MANM ========================================================== */ + #define R_RMAC0_MANM_RX_AN_MES_Pos (0UL) /*!< RX_AN_MES (Bit 0) */ + #define R_RMAC0_MANM_RX_AN_MES_Msk (0xffffUL) /*!< RX_AN_MES (Bitfield-Mask: 0xffff) */ +/* ========================================================= MEIS ========================================================== */ + #define R_RMAC0_MEIS_TSLS_Pos (0UL) /*!< TSLS (Bit 0) */ + #define R_RMAC0_MEIS_TSLS_Msk (0x1UL) /*!< TSLS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_TIES_Pos (1UL) /*!< TIES (Bit 1) */ + #define R_RMAC0_MEIS_TIES_Msk (0x2UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_PRES_Pos (2UL) /*!< PRES (Bit 2) */ + #define R_RMAC0_MEIS_PRES_Msk (0x4UL) /*!< PRES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_PFRROS_Pos (3UL) /*!< PFRROS (Bit 3) */ + #define R_RMAC0_MEIS_PFRROS_Msk (0x8UL) /*!< PFRROS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FCDS_Pos (4UL) /*!< FCDS (Bit 4) */ + #define R_RMAC0_MEIS_FCDS_Msk (0x10UL) /*!< FCDS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_TCES_Pos (5UL) /*!< TCES (Bit 5) */ + #define R_RMAC0_MEIS_TCES_Msk (0x20UL) /*!< TCES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_TBCIS_Pos (6UL) /*!< TBCIS (Bit 6) */ + #define R_RMAC0_MEIS_TBCIS_Msk (0x40UL) /*!< TBCIS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_BFES_Pos (7UL) /*!< BFES (Bit 7) */ + #define R_RMAC0_MEIS_BFES_Msk (0x80UL) /*!< BFES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FCES_Pos (8UL) /*!< FCES (Bit 8) */ + #define R_RMAC0_MEIS_FCES_Msk (0x100UL) /*!< FCES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_REOES_Pos (9UL) /*!< REOES (Bit 9) */ + #define R_RMAC0_MEIS_REOES_Msk (0x200UL) /*!< REOES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_RPOES_Pos (10UL) /*!< RPOES (Bit 10) */ + #define R_RMAC0_MEIS_RPOES_Msk (0x400UL) /*!< RPOES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_RPCRES_Pos (11UL) /*!< RPCRES (Bit 11) */ + #define R_RMAC0_MEIS_RPCRES_Msk (0x800UL) /*!< RPCRES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_CTLES0_Pos (12UL) /*!< CTLES0 (Bit 12) */ + #define R_RMAC0_MEIS_CTLES0_Msk (0x1000UL) /*!< CTLES0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_CTLES1_Pos (13UL) /*!< CTLES1 (Bit 13) */ + #define R_RMAC0_MEIS_CTLES1_Msk (0x2000UL) /*!< CTLES1 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_PDES_Pos (20UL) /*!< PDES (Bit 20) */ + #define R_RMAC0_MEIS_PDES_Msk (0x100000UL) /*!< PDES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_PNAES_Pos (21UL) /*!< PNAES (Bit 21) */ + #define R_RMAC0_MEIS_PNAES_Msk (0x200000UL) /*!< PNAES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FCMCES_Pos (22UL) /*!< FCMCES (Bit 22) */ + #define R_RMAC0_MEIS_FCMCES_Msk (0x400000UL) /*!< FCMCES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FFMES_Pos (23UL) /*!< FFMES (Bit 23) */ + #define R_RMAC0_MEIS_FFMES_Msk (0x800000UL) /*!< FFMES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_CFCES_Pos (24UL) /*!< CFCES (Bit 24) */ + #define R_RMAC0_MEIS_CFCES_Msk (0x1000000UL) /*!< CFCES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FRCES_Pos (25UL) /*!< FRCES (Bit 25) */ + #define R_RMAC0_MEIS_FRCES_Msk (0x2000000UL) /*!< FRCES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_RPOOMS_Pos (26UL) /*!< RPOOMS (Bit 26) */ + #define R_RMAC0_MEIS_RPOOMS_Msk (0x4000000UL) /*!< RPOOMS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FFS_Pos (27UL) /*!< FFS (Bit 27) */ + #define R_RMAC0_MEIS_FFS_Msk (0x8000000UL) /*!< FFS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FUES_Pos (28UL) /*!< FUES (Bit 28) */ + #define R_RMAC0_MEIS_FUES_Msk (0x10000000UL) /*!< FUES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FOES_Pos (29UL) /*!< FOES (Bit 29) */ + #define R_RMAC0_MEIS_FOES_Msk (0x20000000UL) /*!< FOES (Bitfield-Mask: 0x01) */ +/* ========================================================= MEIE ========================================================== */ + #define R_RMAC0_MEIE_TSLE_Pos (0UL) /*!< TSLE (Bit 0) */ + #define R_RMAC0_MEIE_TSLE_Msk (0x1UL) /*!< TSLE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_TIEE_Pos (1UL) /*!< TIEE (Bit 1) */ + #define R_RMAC0_MEIE_TIEE_Msk (0x2UL) /*!< TIEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_PMSEE_Pos (2UL) /*!< PMSEE (Bit 2) */ + #define R_RMAC0_MEIE_PMSEE_Msk (0x4UL) /*!< PMSEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_PFRROE_Pos (3UL) /*!< PFRROE (Bit 3) */ + #define R_RMAC0_MEIE_PFRROE_Msk (0x8UL) /*!< PFRROE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FCDE_Pos (4UL) /*!< FCDE (Bit 4) */ + #define R_RMAC0_MEIE_FCDE_Msk (0x10UL) /*!< FCDE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_TCEE_Pos (5UL) /*!< TCEE (Bit 5) */ + #define R_RMAC0_MEIE_TCEE_Msk (0x20UL) /*!< TCEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_TBCIE_Pos (6UL) /*!< TBCIE (Bit 6) */ + #define R_RMAC0_MEIE_TBCIE_Msk (0x40UL) /*!< TBCIE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_BFEE_Pos (7UL) /*!< BFEE (Bit 7) */ + #define R_RMAC0_MEIE_BFEE_Msk (0x80UL) /*!< BFEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FCEE_Pos (8UL) /*!< FCEE (Bit 8) */ + #define R_RMAC0_MEIE_FCEE_Msk (0x100UL) /*!< FCEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_REOEE_Pos (9UL) /*!< REOEE (Bit 9) */ + #define R_RMAC0_MEIE_REOEE_Msk (0x200UL) /*!< REOEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_RPOEE_Pos (10UL) /*!< RPOEE (Bit 10) */ + #define R_RMAC0_MEIE_RPOEE_Msk (0x400UL) /*!< RPOEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_RPCREE_Pos (11UL) /*!< RPCREE (Bit 11) */ + #define R_RMAC0_MEIE_RPCREE_Msk (0x800UL) /*!< RPCREE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_CTLEE0_Pos (12UL) /*!< CTLEE0 (Bit 12) */ + #define R_RMAC0_MEIE_CTLEE0_Msk (0x1000UL) /*!< CTLEE0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_CTLEE1_Pos (13UL) /*!< CTLEE1 (Bit 13) */ + #define R_RMAC0_MEIE_CTLEE1_Msk (0x2000UL) /*!< CTLEE1 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_PDEE_Pos (20UL) /*!< PDEE (Bit 20) */ + #define R_RMAC0_MEIE_PDEE_Msk (0x100000UL) /*!< PDEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_PNAEE_Pos (21UL) /*!< PNAEE (Bit 21) */ + #define R_RMAC0_MEIE_PNAEE_Msk (0x200000UL) /*!< PNAEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FCMCEE_Pos (22UL) /*!< FCMCEE (Bit 22) */ + #define R_RMAC0_MEIE_FCMCEE_Msk (0x400000UL) /*!< FCMCEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FFMEE_Pos (23UL) /*!< FFMEE (Bit 23) */ + #define R_RMAC0_MEIE_FFMEE_Msk (0x800000UL) /*!< FFMEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_CFCEE_Pos (24UL) /*!< CFCEE (Bit 24) */ + #define R_RMAC0_MEIE_CFCEE_Msk (0x1000000UL) /*!< CFCEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FRCEE_Pos (25UL) /*!< FRCEE (Bit 25) */ + #define R_RMAC0_MEIE_FRCEE_Msk (0x2000000UL) /*!< FRCEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_RPOOME_Pos (26UL) /*!< RPOOME (Bit 26) */ + #define R_RMAC0_MEIE_RPOOME_Msk (0x4000000UL) /*!< RPOOME (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FFE_Pos (27UL) /*!< FFE (Bit 27) */ + #define R_RMAC0_MEIE_FFE_Msk (0x8000000UL) /*!< FFE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FUEE_Pos (28UL) /*!< FUEE (Bit 28) */ + #define R_RMAC0_MEIE_FUEE_Msk (0x10000000UL) /*!< FUEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FOEE_Pos (29UL) /*!< FOEE (Bit 29) */ + #define R_RMAC0_MEIE_FOEE_Msk (0x20000000UL) /*!< FOEE (Bitfield-Mask: 0x01) */ +/* ========================================================= MEID ========================================================== */ + #define R_RMAC0_MEID_TSLD_Pos (0UL) /*!< TSLD (Bit 0) */ + #define R_RMAC0_MEID_TSLD_Msk (0x1UL) /*!< TSLD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_TIED_Pos (1UL) /*!< TIED (Bit 1) */ + #define R_RMAC0_MEID_TIED_Msk (0x2UL) /*!< TIED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_PRED_Pos (2UL) /*!< PRED (Bit 2) */ + #define R_RMAC0_MEID_PRED_Msk (0x4UL) /*!< PRED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_PFRROD_Pos (3UL) /*!< PFRROD (Bit 3) */ + #define R_RMAC0_MEID_PFRROD_Msk (0x8UL) /*!< PFRROD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FCDD_Pos (4UL) /*!< FCDD (Bit 4) */ + #define R_RMAC0_MEID_FCDD_Msk (0x10UL) /*!< FCDD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_TCED_Pos (5UL) /*!< TCED (Bit 5) */ + #define R_RMAC0_MEID_TCED_Msk (0x20UL) /*!< TCED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_TBCID_Pos (6UL) /*!< TBCID (Bit 6) */ + #define R_RMAC0_MEID_TBCID_Msk (0x40UL) /*!< TBCID (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_BFED_Pos (7UL) /*!< BFED (Bit 7) */ + #define R_RMAC0_MEID_BFED_Msk (0x80UL) /*!< BFED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FCED_Pos (8UL) /*!< FCED (Bit 8) */ + #define R_RMAC0_MEID_FCED_Msk (0x100UL) /*!< FCED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_REOED_Pos (9UL) /*!< REOED (Bit 9) */ + #define R_RMAC0_MEID_REOED_Msk (0x200UL) /*!< REOED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_RPOED_Pos (10UL) /*!< RPOED (Bit 10) */ + #define R_RMAC0_MEID_RPOED_Msk (0x400UL) /*!< RPOED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_RPCRED_Pos (11UL) /*!< RPCRED (Bit 11) */ + #define R_RMAC0_MEID_RPCRED_Msk (0x800UL) /*!< RPCRED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_CTLED0_Pos (12UL) /*!< CTLED0 (Bit 12) */ + #define R_RMAC0_MEID_CTLED0_Msk (0x1000UL) /*!< CTLED0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_CTLED1_Pos (13UL) /*!< CTLED1 (Bit 13) */ + #define R_RMAC0_MEID_CTLED1_Msk (0x2000UL) /*!< CTLED1 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_PDED_Pos (20UL) /*!< PDED (Bit 20) */ + #define R_RMAC0_MEID_PDED_Msk (0x100000UL) /*!< PDED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_PNAED_Pos (21UL) /*!< PNAED (Bit 21) */ + #define R_RMAC0_MEID_PNAED_Msk (0x200000UL) /*!< PNAED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FCMCED_Pos (22UL) /*!< FCMCED (Bit 22) */ + #define R_RMAC0_MEID_FCMCED_Msk (0x400000UL) /*!< FCMCED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FFMED_Pos (23UL) /*!< FFMED (Bit 23) */ + #define R_RMAC0_MEID_FFMED_Msk (0x800000UL) /*!< FFMED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_CFCED_Pos (24UL) /*!< CFCED (Bit 24) */ + #define R_RMAC0_MEID_CFCED_Msk (0x1000000UL) /*!< CFCED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FRCED_Pos (25UL) /*!< FRCED (Bit 25) */ + #define R_RMAC0_MEID_FRCED_Msk (0x2000000UL) /*!< FRCED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_RPOOMD_Pos (26UL) /*!< RPOOMD (Bit 26) */ + #define R_RMAC0_MEID_RPOOMD_Msk (0x4000000UL) /*!< RPOOMD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FFD_Pos (27UL) /*!< FFD (Bit 27) */ + #define R_RMAC0_MEID_FFD_Msk (0x8000000UL) /*!< FFD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FUED_Pos (28UL) /*!< FUED (Bit 28) */ + #define R_RMAC0_MEID_FUED_Msk (0x10000000UL) /*!< FUED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FOED_Pos (29UL) /*!< FOED (Bit 29) */ + #define R_RMAC0_MEID_FOED_Msk (0x20000000UL) /*!< FOED (Bitfield-Mask: 0x01) */ +/* ========================================================= MMIS0 ========================================================= */ + #define R_RMAC0_MMIS0_PLSCS_Pos (0UL) /*!< PLSCS (Bit 0) */ + #define R_RMAC0_MMIS0_PLSCS_Msk (0x1UL) /*!< PLSCS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_PIDS_Pos (1UL) /*!< PIDS (Bit 1) */ + #define R_RMAC0_MMIS0_PIDS_Msk (0x2UL) /*!< PIDS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_LVSS_Pos (2UL) /*!< LVSS (Bit 2) */ + #define R_RMAC0_MMIS0_LVSS_Msk (0x4UL) /*!< LVSS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_LVFS_Pos (3UL) /*!< LVFS (Bit 3) */ + #define R_RMAC0_MMIS0_LVFS_Msk (0x8UL) /*!< LVFS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_VFRS_Pos (4UL) /*!< VFRS (Bit 4) */ + #define R_RMAC0_MMIS0_VFRS_Msk (0x10UL) /*!< VFRS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_ANDETS_Pos (6UL) /*!< ANDETS (Bit 6) */ + #define R_RMAC0_MMIS0_ANDETS_Msk (0x40UL) /*!< ANDETS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_XLFDS_Pos (8UL) /*!< XLFDS (Bit 8) */ + #define R_RMAC0_MMIS0_XLFDS_Msk (0x100UL) /*!< XLFDS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_XLFES_Pos (9UL) /*!< XLFES (Bit 9) */ + #define R_RMAC0_MMIS0_XLFES_Msk (0x200UL) /*!< XLFES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_XLFSDS_Pos (10UL) /*!< XLFSDS (Bit 10) */ + #define R_RMAC0_MMIS0_XLFSDS_Msk (0x400UL) /*!< XLFSDS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_XRFSDS_Pos (11UL) /*!< XRFSDS (Bit 11) */ + #define R_RMAC0_MMIS0_XRFSDS_Msk (0x800UL) /*!< XRFSDS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_XLISDS_Pos (12UL) /*!< XLISDS (Bit 12) */ + #define R_RMAC0_MMIS0_XLISDS_Msk (0x1000UL) /*!< XLISDS (Bitfield-Mask: 0x01) */ +/* ========================================================= MMIE0 ========================================================= */ + #define R_RMAC0_MMIE0_PLSCE_Pos (0UL) /*!< PLSCE (Bit 0) */ + #define R_RMAC0_MMIE0_PLSCE_Msk (0x1UL) /*!< PLSCE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_PIDE_Pos (1UL) /*!< PIDE (Bit 1) */ + #define R_RMAC0_MMIE0_PIDE_Msk (0x2UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_LVSE_Pos (2UL) /*!< LVSE (Bit 2) */ + #define R_RMAC0_MMIE0_LVSE_Msk (0x4UL) /*!< LVSE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_LVFE_Pos (3UL) /*!< LVFE (Bit 3) */ + #define R_RMAC0_MMIE0_LVFE_Msk (0x8UL) /*!< LVFE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_VFRE_Pos (4UL) /*!< VFRE (Bit 4) */ + #define R_RMAC0_MMIE0_VFRE_Msk (0x10UL) /*!< VFRE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_ANDETE_Pos (6UL) /*!< ANDETE (Bit 6) */ + #define R_RMAC0_MMIE0_ANDETE_Msk (0x40UL) /*!< ANDETE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_XLFDE_Pos (8UL) /*!< XLFDE (Bit 8) */ + #define R_RMAC0_MMIE0_XLFDE_Msk (0x100UL) /*!< XLFDE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_XLFEE_Pos (9UL) /*!< XLFEE (Bit 9) */ + #define R_RMAC0_MMIE0_XLFEE_Msk (0x200UL) /*!< XLFEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_XLFSDE_Pos (10UL) /*!< XLFSDE (Bit 10) */ + #define R_RMAC0_MMIE0_XLFSDE_Msk (0x400UL) /*!< XLFSDE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_XRFSDE_Pos (11UL) /*!< XRFSDE (Bit 11) */ + #define R_RMAC0_MMIE0_XRFSDE_Msk (0x800UL) /*!< XRFSDE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_XLISDE_Pos (12UL) /*!< XLISDE (Bit 12) */ + #define R_RMAC0_MMIE0_XLISDE_Msk (0x1000UL) /*!< XLISDE (Bitfield-Mask: 0x01) */ +/* ========================================================= MMID0 ========================================================= */ + #define R_RMAC0_MMID0_PLSCD_Pos (0UL) /*!< PLSCD (Bit 0) */ + #define R_RMAC0_MMID0_PLSCD_Msk (0x1UL) /*!< PLSCD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_PIDD_Pos (1UL) /*!< PIDD (Bit 1) */ + #define R_RMAC0_MMID0_PIDD_Msk (0x2UL) /*!< PIDD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_LVSD_Pos (2UL) /*!< LVSD (Bit 2) */ + #define R_RMAC0_MMID0_LVSD_Msk (0x4UL) /*!< LVSD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_LVFD_Pos (3UL) /*!< LVFD (Bit 3) */ + #define R_RMAC0_MMID0_LVFD_Msk (0x8UL) /*!< LVFD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_VFRD_Pos (4UL) /*!< VFRD (Bit 4) */ + #define R_RMAC0_MMID0_VFRD_Msk (0x10UL) /*!< VFRD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_ANDETD_Pos (6UL) /*!< ANDETD (Bit 6) */ + #define R_RMAC0_MMID0_ANDETD_Msk (0x40UL) /*!< ANDETD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_XLFDD_Pos (8UL) /*!< XLFDD (Bit 8) */ + #define R_RMAC0_MMID0_XLFDD_Msk (0x100UL) /*!< XLFDD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_XLFED_Pos (9UL) /*!< XLFED (Bit 9) */ + #define R_RMAC0_MMID0_XLFED_Msk (0x200UL) /*!< XLFED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_XLFSDD_Pos (10UL) /*!< XLFSDD (Bit 10) */ + #define R_RMAC0_MMID0_XLFSDD_Msk (0x400UL) /*!< XLFSDD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_XRFSDD_Pos (11UL) /*!< XRFSDD (Bit 11) */ + #define R_RMAC0_MMID0_XRFSDD_Msk (0x800UL) /*!< XRFSDD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_XLISDD_Pos (12UL) /*!< XLISDD (Bit 12) */ + #define R_RMAC0_MMID0_XLISDD_Msk (0x1000UL) /*!< XLISDD (Bitfield-Mask: 0x01) */ +/* ========================================================= MMIS1 ========================================================= */ + #define R_RMAC0_MMIS1_PRACS_Pos (0UL) /*!< PRACS (Bit 0) */ + #define R_RMAC0_MMIS1_PRACS_Msk (0x1UL) /*!< PRACS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS1_PWACS_Pos (1UL) /*!< PWACS (Bit 1) */ + #define R_RMAC0_MMIS1_PWACS_Msk (0x2UL) /*!< PWACS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS1_PAACS_Pos (2UL) /*!< PAACS (Bit 2) */ + #define R_RMAC0_MMIS1_PAACS_Msk (0x4UL) /*!< PAACS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS1_PPRACS_Pos (3UL) /*!< PPRACS (Bit 3) */ + #define R_RMAC0_MMIS1_PPRACS_Msk (0x8UL) /*!< PPRACS (Bitfield-Mask: 0x01) */ +/* ========================================================= MMIE1 ========================================================= */ + #define R_RMAC0_MMIE1_PRACE_Pos (0UL) /*!< PRACE (Bit 0) */ + #define R_RMAC0_MMIE1_PRACE_Msk (0x1UL) /*!< PRACE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE1_PWACE_Pos (1UL) /*!< PWACE (Bit 1) */ + #define R_RMAC0_MMIE1_PWACE_Msk (0x2UL) /*!< PWACE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE1_PAACE_Pos (2UL) /*!< PAACE (Bit 2) */ + #define R_RMAC0_MMIE1_PAACE_Msk (0x4UL) /*!< PAACE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE1_PPRACE_Pos (3UL) /*!< PPRACE (Bit 3) */ + #define R_RMAC0_MMIE1_PPRACE_Msk (0x8UL) /*!< PPRACE (Bitfield-Mask: 0x01) */ +/* ========================================================= MMID1 ========================================================= */ + #define R_RMAC0_MMID1_PRACD_Pos (0UL) /*!< PRACD (Bit 0) */ + #define R_RMAC0_MMID1_PRACD_Msk (0x1UL) /*!< PRACD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID1_PWACD_Pos (1UL) /*!< PWACD (Bit 1) */ + #define R_RMAC0_MMID1_PWACD_Msk (0x2UL) /*!< PWACD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID1_PAACD_Pos (2UL) /*!< PAACD (Bit 2) */ + #define R_RMAC0_MMID1_PAACD_Msk (0x4UL) /*!< PAACD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID1_PPRACD_Pos (3UL) /*!< PPRACD (Bit 3) */ + #define R_RMAC0_MMID1_PPRACD_Msk (0x8UL) /*!< PPRACD (Bitfield-Mask: 0x01) */ +/* ========================================================= MMIS2 ========================================================= */ + #define R_RMAC0_MMIS2_MPDIS_Pos (0UL) /*!< MPDIS (Bit 0) */ + #define R_RMAC0_MMIS2_MPDIS_Msk (0x1UL) /*!< MPDIS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS2_LPIAIS_Pos (1UL) /*!< LPIAIS (Bit 1) */ + #define R_RMAC0_MMIS2_LPIAIS_Msk (0x2UL) /*!< LPIAIS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS2_LPIDIS_Pos (2UL) /*!< LPIDIS (Bit 2) */ + #define R_RMAC0_MMIS2_LPIDIS_Msk (0x4UL) /*!< LPIDIS (Bitfield-Mask: 0x01) */ +/* ========================================================= MMIE2 ========================================================= */ + #define R_RMAC0_MMIE2_MPDIE_Pos (0UL) /*!< MPDIE (Bit 0) */ + #define R_RMAC0_MMIE2_MPDIE_Msk (0x1UL) /*!< MPDIE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE2_LPIAIE_Pos (1UL) /*!< LPIAIE (Bit 1) */ + #define R_RMAC0_MMIE2_LPIAIE_Msk (0x2UL) /*!< LPIAIE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE2_LPIDIE_Pos (2UL) /*!< LPIDIE (Bit 2) */ + #define R_RMAC0_MMIE2_LPIDIE_Msk (0x4UL) /*!< LPIDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= MMID2 ========================================================= */ + #define R_RMAC0_MMID2_MPDID_Pos (0UL) /*!< MPDID (Bit 0) */ + #define R_RMAC0_MMID2_MPDID_Msk (0x1UL) /*!< MPDID (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID2_LPIAID_Pos (1UL) /*!< LPIAID (Bit 1) */ + #define R_RMAC0_MMID2_LPIAID_Msk (0x2UL) /*!< LPIAID (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID2_LPIDID_Pos (2UL) /*!< LPIDID (Bit 2) */ + #define R_RMAC0_MMID2_LPIDID_Msk (0x4UL) /*!< LPIDID (Bitfield-Mask: 0x01) */ +/* ======================================================== MMPFTCT ======================================================== */ + #define R_RMAC0_MMPFTCT_MPFTC_Pos (0UL) /*!< MPFTC (Bit 0) */ + #define R_RMAC0_MMPFTCT_MPFTC_Msk (0xffffUL) /*!< MPFTC (Bitfield-Mask: 0xffff) */ +/* ======================================================== MAPFTCT ======================================================== */ + #define R_RMAC0_MAPFTCT_APFTC_Pos (0UL) /*!< APFTC (Bit 0) */ + #define R_RMAC0_MAPFTCT_APFTC_Msk (0xffffUL) /*!< APFTC (Bitfield-Mask: 0xffff) */ +/* ======================================================== MPFRCT ========================================================= */ + #define R_RMAC0_MPFRCT_PFRC_Pos (0UL) /*!< PFRC (Bit 0) */ + #define R_RMAC0_MPFRCT_PFRC_Msk (0xffffUL) /*!< PFRC (Bitfield-Mask: 0xffff) */ +/* ======================================================== MFCICT ========================================================= */ + #define R_RMAC0_MFCICT_FCIC_Pos (0UL) /*!< FCIC (Bit 0) */ + #define R_RMAC0_MFCICT_FCIC_Msk (0xffffUL) /*!< FCIC (Bitfield-Mask: 0xffff) */ +/* ======================================================== MEEECT ========================================================= */ + #define R_RMAC0_MEEECT_EEERC_Pos (0UL) /*!< EEERC (Bit 0) */ + #define R_RMAC0_MEEECT_EEERC_Msk (0xffffUL) /*!< EEERC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MMPCFTCT0 ======================================================= */ + #define R_RMAC0_MMPCFTCT0_MPCFCTC_Pos (0UL) /*!< MPCFCTC (Bit 0) */ + #define R_RMAC0_MMPCFTCT0_MPCFCTC_Msk (0xffffUL) /*!< MPCFCTC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MMPCFTCT1 ======================================================= */ + #define R_RMAC0_MMPCFTCT1_MPCFCTC_Pos (0UL) /*!< MPCFCTC (Bit 0) */ + #define R_RMAC0_MMPCFTCT1_MPCFCTC_Msk (0xffffUL) /*!< MPCFCTC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MAPCFTCT0 ======================================================= */ + #define R_RMAC0_MAPCFTCT0_APCFCTC_Pos (0UL) /*!< APCFCTC (Bit 0) */ + #define R_RMAC0_MAPCFTCT0_APCFCTC_Msk (0xffffUL) /*!< APCFCTC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MAPCFTCT1 ======================================================= */ + #define R_RMAC0_MAPCFTCT1_APCFCTC_Pos (0UL) /*!< APCFCTC (Bit 0) */ + #define R_RMAC0_MAPCFTCT1_APCFCTC_Msk (0xffffUL) /*!< APCFCTC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT0 ======================================================== */ + #define R_RMAC0_MPCFRCT0_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT0_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT1 ======================================================== */ + #define R_RMAC0_MPCFRCT1_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT1_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT2 ======================================================== */ + #define R_RMAC0_MPCFRCT2_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT2_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT3 ======================================================== */ + #define R_RMAC0_MPCFRCT3_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT3_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT4 ======================================================== */ + #define R_RMAC0_MPCFRCT4_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT4_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT5 ======================================================== */ + #define R_RMAC0_MPCFRCT5_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT5_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT6 ======================================================== */ + #define R_RMAC0_MPCFRCT6_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT6_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT7 ======================================================== */ + #define R_RMAC0_MPCFRCT7_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT7_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================== MROVFC ========================================================= */ + #define R_RMAC0_MROVFC_ROVFC_Pos (0UL) /*!< ROVFC (Bit 0) */ + #define R_RMAC0_MROVFC_ROVFC_Msk (0xffffffffUL) /*!< ROVFC (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= MRHCRCEC ======================================================== */ + #define R_RMAC0_MRHCRCEC_RHCRCEC_Pos (0UL) /*!< RHCRCEC (Bit 0) */ + #define R_RMAC0_MRHCRCEC_RHCRCEC_Msk (0xffffUL) /*!< RHCRCEC (Bitfield-Mask: 0xffff) */ +/* ======================================================== MRGFCE ========================================================= */ + #define R_RMAC0_MRGFCE_RGFNE_Pos (0UL) /*!< RGFNE (Bit 0) */ + #define R_RMAC0_MRGFCE_RGFNE_Msk (0xffffffffUL) /*!< RGFNE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRGFCP ========================================================= */ + #define R_RMAC0_MRGFCP_RGFNP_Pos (0UL) /*!< RGFNP (Bit 0) */ + #define R_RMAC0_MRGFCP_RGFNP_Msk (0xffffffffUL) /*!< RGFNP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MRBFC ========================================================= */ + #define R_RMAC0_MRBFC_RBFN_Pos (0UL) /*!< RBFN (Bit 0) */ + #define R_RMAC0_MRBFC_RBFN_Msk (0xffffffffUL) /*!< RBFN (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MRMFC ========================================================= */ + #define R_RMAC0_MRMFC_RMFN_Pos (0UL) /*!< RMFN (Bit 0) */ + #define R_RMAC0_MRMFC_RMFN_Msk (0xffffffffUL) /*!< RMFN (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MRUFC ========================================================= */ + #define R_RMAC0_MRUFC_RUFN_Pos (0UL) /*!< RUFN (Bit 0) */ + #define R_RMAC0_MRUFC_RUFN_Msk (0xffffffffUL) /*!< RUFN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRPEFC ========================================================= */ + #define R_RMAC0_MRPEFC_RPEFN_Pos (0UL) /*!< RPEFN (Bit 0) */ + #define R_RMAC0_MRPEFC_RPEFN_Msk (0xffffUL) /*!< RPEFN (Bitfield-Mask: 0xffff) */ +/* ======================================================== MRNEFC ========================================================= */ + #define R_RMAC0_MRNEFC_RNEFN_Pos (0UL) /*!< RNEFN (Bit 0) */ + #define R_RMAC0_MRNEFC_RNEFN_Msk (0xffffUL) /*!< RNEFN (Bitfield-Mask: 0xffff) */ +/* ======================================================== MRFMEFC ======================================================== */ + #define R_RMAC0_MRFMEFC_RFMEFN_Pos (0UL) /*!< RFMEFN (Bit 0) */ + #define R_RMAC0_MRFMEFC_RFMEFN_Msk (0xffffffffUL) /*!< RFMEFN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= MRFFMEFC ======================================================== */ + #define R_RMAC0_MRFFMEFC_RFFMEFN_Pos (0UL) /*!< RFFMEFN (Bit 0) */ + #define R_RMAC0_MRFFMEFC_RFFMEFN_Msk (0xffffUL) /*!< RFFMEFN (Bitfield-Mask: 0xffff) */ +/* ======================================================= MRCFCEFC ======================================================== */ + #define R_RMAC0_MRCFCEFC_RCFCEFN_Pos (0UL) /*!< RCFCEFN (Bit 0) */ + #define R_RMAC0_MRCFCEFC_RCFCEFN_Msk (0xffffUL) /*!< RCFCEFN (Bitfield-Mask: 0xffff) */ +/* ======================================================== MRFCEFC ======================================================== */ + #define R_RMAC0_MRFCEFC_RFCEFN_Pos (0UL) /*!< RFCEFN (Bit 0) */ + #define R_RMAC0_MRFCEFC_RFCEFN_Msk (0xffffUL) /*!< RFCEFN (Bitfield-Mask: 0xffff) */ +/* ======================================================= MRRCFEFC ======================================================== */ + #define R_RMAC0_MRRCFEFC_RRCFEFN_Pos (0UL) /*!< RRCFEFN (Bit 0) */ + #define R_RMAC0_MRRCFEFC_RRCFEFN_Msk (0xffffUL) /*!< RRCFEFN (Bitfield-Mask: 0xffff) */ +/* ========================================================= MRFC ========================================================== */ + #define R_RMAC0_MRFC_RFN_Pos (0UL) /*!< RFN (Bit 0) */ + #define R_RMAC0_MRFC_RFN_Msk (0xffffffffUL) /*!< RFN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRGUEFC ======================================================== */ + #define R_RMAC0_MRGUEFC_RUEFN_Pos (0UL) /*!< RUEFN (Bit 0) */ + #define R_RMAC0_MRGUEFC_RUEFN_Msk (0xffffffffUL) /*!< RUEFN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRBUEFC ======================================================== */ + #define R_RMAC0_MRBUEFC_RUEFN_Pos (0UL) /*!< RUEFN (Bit 0) */ + #define R_RMAC0_MRBUEFC_RUEFN_Msk (0xffffffffUL) /*!< RUEFN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRGOEFC ======================================================== */ + #define R_RMAC0_MRGOEFC_RGOEFN_Pos (0UL) /*!< RGOEFN (Bit 0) */ + #define R_RMAC0_MRGOEFC_RGOEFN_Msk (0xffffffffUL) /*!< RGOEFN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRBOEFC ======================================================== */ + #define R_RMAC0_MRBOEFC_RBOEFN_Pos (0UL) /*!< RBOEFN (Bit 0) */ + #define R_RMAC0_MRBOEFC_RBOEFN_Msk (0xffffffffUL) /*!< RBOEFN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRXBCEU ======================================================== */ + #define R_RMAC0_MRXBCEU_RBNEU_Pos (0UL) /*!< RBNEU (Bit 0) */ + #define R_RMAC0_MRXBCEU_RBNEU_Msk (0xffffffffUL) /*!< RBNEU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRXBCEL ======================================================== */ + #define R_RMAC0_MRXBCEL_RBNEL_Pos (0UL) /*!< RBNEL (Bit 0) */ + #define R_RMAC0_MRXBCEL_RBNEL_Msk (0xffffffffUL) /*!< RBNEL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRXBCPU ======================================================== */ + #define R_RMAC0_MRXBCPU_RBNPU_Pos (0UL) /*!< RBNPU (Bit 0) */ + #define R_RMAC0_MRXBCPU_RBNPU_Msk (0xffffffffUL) /*!< RBNPU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRXBCPL ======================================================== */ + #define R_RMAC0_MRXBCPL_RBNPL_Pos (0UL) /*!< RBNPL (Bit 0) */ + #define R_RMAC0_MRXBCPL_RBNPL_Msk (0xffffffffUL) /*!< RBNPL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MTGFCE ========================================================= */ + #define R_RMAC0_MTGFCE_TGFNE_Pos (0UL) /*!< TGFNE (Bit 0) */ + #define R_RMAC0_MTGFCE_TGFNE_Msk (0xffffffffUL) /*!< TGFNE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MTGFCP ========================================================= */ + #define R_RMAC0_MTGFCP_TGFNP_Pos (0UL) /*!< TGFNP (Bit 0) */ + #define R_RMAC0_MTGFCP_TGFNP_Msk (0xffffffffUL) /*!< TGFNP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MTBFC ========================================================= */ + #define R_RMAC0_MTBFC_TBFN_Pos (0UL) /*!< TBFN (Bit 0) */ + #define R_RMAC0_MTBFC_TBFN_Msk (0xffffffffUL) /*!< TBFN (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MTMFC ========================================================= */ + #define R_RMAC0_MTMFC_TMFN_Pos (0UL) /*!< TMFN (Bit 0) */ + #define R_RMAC0_MTMFC_TMFN_Msk (0xffffffffUL) /*!< TMFN (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MTUFC ========================================================= */ + #define R_RMAC0_MTUFC_TUFN_Pos (0UL) /*!< TUFN (Bit 0) */ + #define R_RMAC0_MTUFC_TUFN_Msk (0xffffffffUL) /*!< TUFN (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MTEFC ========================================================= */ + #define R_RMAC0_MTEFC_TEFN_Pos (0UL) /*!< TEFN (Bit 0) */ + #define R_RMAC0_MTEFC_TEFN_Msk (0xffffUL) /*!< TEFN (Bitfield-Mask: 0xffff) */ +/* ======================================================== MTXBCEU ======================================================== */ + #define R_RMAC0_MTXBCEU_TBNEU_Pos (0UL) /*!< TBNEU (Bit 0) */ + #define R_RMAC0_MTXBCEU_TBNEU_Msk (0xffffffffUL) /*!< TBNEU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MTXBCEL ======================================================== */ + #define R_RMAC0_MTXBCEL_TBNEL_Pos (0UL) /*!< TBNEL (Bit 0) */ + #define R_RMAC0_MTXBCEL_TBNEL_Msk (0xffffffffUL) /*!< TBNEL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MTXBCPU ======================================================== */ + #define R_RMAC0_MTXBCPU_TBNPU_Pos (0UL) /*!< TBNPU (Bit 0) */ + #define R_RMAC0_MTXBCPU_TBNPU_Msk (0xffffffffUL) /*!< TBNPU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MTXBCPL ======================================================== */ + #define R_RMAC0_MTXBCPL_TBNPL_Pos (0UL) /*!< TBNPL (Bit 0) */ + #define R_RMAC0_MTXBCPL_TBNPL_Msk (0xffffffffUL) /*!< TBNPL (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_TCM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= TCMPRCR_S ======================================================= */ + #define R_TCM_TCMPRCR_S_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_TCM_TCMPRCR_S_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMPRCR_S_KW_Pos (8UL) /*!< KW (Bit 8) */ + #define R_TCM_TCMPRCR_S_KW_Msk (0xff00UL) /*!< KW (Bitfield-Mask: 0xff) */ +/* ====================================================== TCMPRCR_NS ======================================================= */ + #define R_TCM_TCMPRCR_NS_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_TCM_TCMPRCR_NS_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMPRCR_NS_KW_Pos (8UL) /*!< KW (Bit 8) */ + #define R_TCM_TCMPRCR_NS_KW_Msk (0xff00UL) /*!< KW (Bitfield-Mask: 0xff) */ +/* ======================================================== TCMCRC ========================================================= */ + #define R_TCM_TCMCRC_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_TCM_TCMCRC_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMCRC_ECCMOD_Pos (2UL) /*!< ECCMOD (Bit 2) */ + #define R_TCM_TCMCRC_ECCMOD_Msk (0xcUL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ + #define R_TCM_TCMCRC_E1STSEN_Pos (4UL) /*!< E1STSEN (Bit 4) */ + #define R_TCM_TCMCRC_E1STSEN_Msk (0x10UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMCRC_TSTBYP_Pos (7UL) /*!< TSTBYP (Bit 7) */ + #define R_TCM_TCMCRC_TSTBYP_Msk (0x80UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== TCMCRS ========================================================= */ + #define R_TCM_TCMCRS_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_TCM_TCMCRS_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMCRS_ECCMOD_Pos (2UL) /*!< ECCMOD (Bit 2) */ + #define R_TCM_TCMCRS_ECCMOD_Msk (0xcUL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ + #define R_TCM_TCMCRS_E1STSEN_Pos (4UL) /*!< E1STSEN (Bit 4) */ + #define R_TCM_TCMCRS_E1STSEN_Msk (0x10UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMCRS_TSTBYP_Pos (7UL) /*!< TSTBYP (Bit 7) */ + #define R_TCM_TCMCRS_TSTBYP_Msk (0x80UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== TCMESR ========================================================= */ + #define R_TCM_TCMESR_ERRC0_Pos (0UL) /*!< ERRC0 (Bit 0) */ + #define R_TCM_TCMESR_ERRC0_Msk (0x1UL) /*!< ERRC0 (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMESR_ERRC1_Pos (1UL) /*!< ERRC1 (Bit 1) */ + #define R_TCM_TCMESR_ERRC1_Msk (0x2UL) /*!< ERRC1 (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMESR_ERRS0_Pos (2UL) /*!< ERRS0 (Bit 2) */ + #define R_TCM_TCMESR_ERRS0_Msk (0x4UL) /*!< ERRS0 (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMESR_ERRS1_Pos (3UL) /*!< ERRS1 (Bit 3) */ + #define R_TCM_TCMESR_ERRS1_Msk (0x8UL) /*!< ERRS1 (Bitfield-Mask: 0x01) */ +/* ======================================================= TCMESCLR ======================================================== */ + #define R_TCM_TCMESCLR_CLRC0_Pos (0UL) /*!< CLRC0 (Bit 0) */ + #define R_TCM_TCMESCLR_CLRC0_Msk (0x1UL) /*!< CLRC0 (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMESCLR_CLRC1_Pos (1UL) /*!< CLRC1 (Bit 1) */ + #define R_TCM_TCMESCLR_CLRC1_Msk (0x2UL) /*!< CLRC1 (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMESCLR_CLRS0_Pos (2UL) /*!< CLRS0 (Bit 2) */ + #define R_TCM_TCMESCLR_CLRS0_Msk (0x4UL) /*!< CLRS0 (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMESCLR_CLRS1_Pos (3UL) /*!< CLRS1 (Bit 3) */ + #define R_TCM_TCMESCLR_CLRS1_Msk (0x8UL) /*!< CLRS1 (Bitfield-Mask: 0x01) */ +/* ======================================================= TCMEARC0 ======================================================== */ + #define R_TCM_TCMEARC0_EAR_Pos (2UL) /*!< EAR (Bit 2) */ + #define R_TCM_TCMEARC0_EAR_Msk (0x3fffcUL) /*!< EAR (Bitfield-Mask: 0xffff) */ +/* ======================================================= TCMEARC1 ======================================================== */ + #define R_TCM_TCMEARC1_EAR_Pos (2UL) /*!< EAR (Bit 2) */ + #define R_TCM_TCMEARC1_EAR_Msk (0x3fffcUL) /*!< EAR (Bitfield-Mask: 0xffff) */ +/* ======================================================= TCMEARS0 ======================================================== */ + #define R_TCM_TCMEARS0_EAR_Pos (2UL) /*!< EAR (Bit 2) */ + #define R_TCM_TCMEARS0_EAR_Msk (0x3fffcUL) /*!< EAR (Bitfield-Mask: 0xffff) */ +/* ======================================================= TCMEARS1 ======================================================== */ + #define R_TCM_TCMEARS1_EAR_Pos (2UL) /*!< EAR (Bit 2) */ + #define R_TCM_TCMEARS1_EAR_Msk (0x3fffcUL) /*!< EAR (Bitfield-Mask: 0xffff) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R7KA8P1KF_CORE1_H */ + +/** @} */ /* End of group R7KA8P1KF_core1 */ + +/** @} */ /* End of group Renesas */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h new file mode 100644 index 00000000000..c424780f8bf --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h @@ -0,0 +1,198 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/* Ensure Renesas MCU variation definitions are included to ensure MCU + * specific register variations are handled correctly. */ +#ifndef BSP_FEATURE_H + #error "INTERNAL ERROR: bsp_feature.h must be included before renesas.h." +#endif + +/** @addtogroup Renesas + * @{ + */ + +/** @addtogroup RA + * @{ + */ + +#ifndef RA_H + #define RA_H + + #ifdef __cplusplus +extern "C" { + #endif + + #include "cmsis_compiler.h" + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ +/* IRQn_Type is provided in bsp_exceptions.h. Vectors generated by the FSP Configuration tool are in vector_data.h */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + + #if BSP_MCU_GROUP_RA0E1 + #include "R7FA0E107.h" + #elif BSP_MCU_GROUP_RA0E2 + #include "R7FA0E209.h" + #elif BSP_MCU_GROUP_RA0L1 + #include "R7FA0L107.h" + #elif BSP_MCU_GROUP_RA2A1 + #include "R7FA2A1AB.h" + #elif BSP_MCU_GROUP_RA2A2 + #include "R7FA2A2AD.h" + #elif BSP_MCU_GROUP_RA2E1 + #include "R7FA2E1A9.h" + #elif BSP_MCU_GROUP_RA2E2 + #include "R7FA2E2A7.h" + #elif BSP_MCU_GROUP_RA2E3 + #include "R7FA2E307.h" + #elif BSP_MCU_GROUP_RA2L1 + #include "R7FA2L1AB.h" + #elif BSP_MCU_GROUP_RA2L2 + #include "R7FA2L209.h" + #elif BSP_MCU_GROUP_RA2T1 + #include "R7FA2T107.h" + #elif BSP_MCU_GROUP_RA4C1 + #include "R7FA4C1BD.h" + #elif BSP_MCU_GROUP_RA4E1 + #include "R7FA4E10D.h" + #elif BSP_MCU_GROUP_RA4E2 + #include "R7FA4E2B9.h" + #elif BSP_MCU_GROUP_RA4M1 + #include "R7FA4M1AB.h" + #elif BSP_MCU_GROUP_RA4M2 + #include "R7FA4M2AD.h" + #elif BSP_MCU_GROUP_RA4M3 + #include "R7FA4M3AF.h" + #elif BSP_MCU_GROUP_RA4T1 + #include "R7FA4T1BB.h" + #elif BSP_MCU_GROUP_RA4W1 + #include "R7FA4W1AD.h" + #elif BSP_MCU_GROUP_RA4L1 + #include "R7FA4L1BD.h" + #elif BSP_MCU_GROUP_RA6E1 + #include "R7FA6E10F.h" + #elif BSP_MCU_GROUP_RA6E2 + #include "R7FA6E2BB.h" + #elif BSP_MCU_GROUP_RA6M1 + #include "R7FA6M1AD.h" + #elif BSP_MCU_GROUP_RA6M2 + #include "R7FA6M2AF.h" + #elif BSP_MCU_GROUP_RA6M3 + #include "R7FA6M3AH.h" + #elif BSP_MCU_GROUP_RA6M4 + #include "R7FA6M4AF.h" + #elif BSP_MCU_GROUP_RA6M5 + #include "R7FA6M5BH.h" + #elif BSP_MCU_GROUP_RA6T1 + #include "R7FA6T1AD.h" + #elif BSP_MCU_GROUP_RA6T2 + #include "R7FA6T2BD.h" + #elif BSP_MCU_GROUP_RA6T3 + #include "R7FA6T3BB.h" + #elif BSP_MCU_GROUP_RA8D1 + #include "R7FA8D1BH.h" + #elif BSP_MCU_GROUP_RA8E1 + #include "R7FA8E1AF.h" + #elif BSP_MCU_GROUP_RA8E2 + #include "R7FA8E2AF.h" + #elif BSP_MCU_GROUP_RA8M1 + #include "R7FA8M1AH.h" + #elif BSP_MCU_GROUP_RA8P1 + #if 0U == BSP_CFG_CPU_CORE + #include "R7KA8P1KF_core0.h" + #elif 1U == BSP_CFG_CPU_CORE + #include "R7KA8P1KF_core1.h" + #else + #warning "Unsupported CPU number" + #endif + #elif BSP_MCU_GROUP_RA8T1 + #include "R7FA8T1AH.h" + #elif BSP_MCU_GROUP_RA8T2 + #if 0U == BSP_CFG_CPU_CORE + #include "R7KA8T2LF_core0.h" + #elif 1U == BSP_CFG_CPU_CORE + #include "R7KA8T2LF_core1.h" + #else + #warning "Unsupported CPU number" + #endif + #elif BSP_MCU_GROUP_RA8M2 + #if 0U == BSP_CFG_CPU_CORE + #include "R7KA8M2JF_core0.h" + #elif 1U == BSP_CFG_CPU_CORE + #include "R7KA8M2JF_core1.h" + #else + #warning "Unsupported CPU number" + #endif + #elif BSP_MCU_GROUP_RA8D2 + #if 0U == BSP_CFG_CPU_CORE + #include "R7KA8D2KF_core0.h" + #elif 1U == BSP_CFG_CPU_CORE + #include "R7KA8D2KF_core1.h" + #else + #warning "Unsupported CPU number" + #endif + #else + #if __has_include("renesas_internal.h") + #include "renesas_internal.h" + #else + #warning "Unsupported MCU" + #endif + #endif + +/* + * ARM has advised to no longer use the __ARM_ARCH_8_1M_MAIN__ type macro and to instead use the __ARM_ARCH and __ARM_ARCH_ISA_THUMB + * macros for differentiating architectures. However, with all of our toolchains, neither paradigm is being correctly produced for Cortex-M85 + * and thus we still need a workaround. Below is a summary of the current macros produced by each toolchain for CM85: + * + * | Toolchain | __ARM_ARCH | _ARM_ARCH_xx__ | + * |-----------|------------|------------------------| + * | GCC | 8 | __ARM_ARCH_8M_MAIN__ | + * | LLVM | 8 | __ARM_ARCH_8_1M_MAIN__ | + * | AC6 | 8 | __ARM_ARCH_8_1M_MAIN__ | + * | IAR | 801 | __ARM_ARCH_8M_MAIN__ | + * + * The expected output for CM85 should be __ARM_ARCH == 801, __ARM_ARCH_ISA_THUMB == 2, and __ARM_ARCH_8_1M_MAIN__ + * + * IAR is currently the only toolchain producing the correct __ARM_ARCH value. + * + *- See https://github.com/ARM-software/CMSIS_6/issues/159 + */ + #if BSP_CFG_MCU_PART_SERIES == 8 && !defined(__ICCARM__) && BSP_CFG_CPU_CORE != 1 + #undef __ARM_ARCH + #define __ARM_ARCH 801 + #endif + + #if (__ARM_ARCH == 7) && (__ARM_ARCH_ISA_THUMB == 2) + #define RENESAS_CORTEX_M4 + #elif (__ARM_ARCH == 8) && (__ARM_ARCH_ISA_THUMB == 1) + #define RENESAS_CORTEX_M23 + #elif (__ARM_ARCH == 8) && (__ARM_ARCH_ISA_THUMB == 2) + #define RENESAS_CORTEX_M33 + #elif (__ARM_ARCH == 801) && (__ARM_ARCH_ISA_THUMB == 2) + #define RENESAS_CORTEX_M85 + #else + #warning Unsupported Architecture + #endif + + #ifdef __cplusplus +} + #endif + +#endif /* RA_H */ + +/** @} */ /* End of group RA */ + +/** @} */ /* End of group Renesas */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h new file mode 100644 index 00000000000..68d603720c4 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h @@ -0,0 +1,44 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef SYSTEM_RENESAS_ARM_H + #define SYSTEM_RENESAS_ARM_H + + #ifdef __cplusplus +extern "C" { + #endif + + #include + +extern uint32_t SystemCoreClock; /** System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit(void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate(void); + + #ifdef __cplusplus +} + #endif + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c new file mode 100644 index 00000000000..6877f953fcd --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c @@ -0,0 +1,141 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#if BSP_TZ_SECURE_BUILD + #define BSP_TZ_STACK_SEAL_SIZE (8U) +#else + #define BSP_TZ_STACK_SEAL_SIZE (0U) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* Defines function pointers to be used with vector table. */ +typedef void (* exc_ptr_t)(void); + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +void Reset_Handler(void); +void Default_Handler(void); +int32_t main(void); + +/*******************************************************************************************************************//** + * MCU starts executing here out of reset. Main stack pointer is set up already. + **********************************************************************************************************************/ +void Reset_Handler (void) +{ + /* Initialize system using BSP. */ + SystemInit(); + + /* Call user application. */ +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) + extern int entry(void); + entry(); +#elif defined(__ICCARM__) + extern void __low_level_init(void); + __low_level_init(); +#else + /* Jump to main. */ + main(); +#endif + + while (1) + { + /* Infinite Loop. */ + } +} + +/*******************************************************************************************************************//** + * Default exception handler. + **********************************************************************************************************************/ +void Default_Handler (void) +{ + /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption + * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status + * registers for more information. + */ + BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(0); +} + +/* Main stack */ +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); + +/* Heap */ +BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); + +/* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle + * these exceptions in their code they should define their own function with the same name. + */ +#if defined(__ICCARM__) + #define WEAK_REF_ATTRIBUTE + + #pragma weak HardFault_Handler = Default_Handler + #pragma weak MemManage_Handler = Default_Handler + #pragma weak BusFault_Handler = Default_Handler + #pragma weak UsageFault_Handler = Default_Handler + #pragma weak SecureFault_Handler = Default_Handler + #pragma weak SVC_Handler = Default_Handler + #pragma weak DebugMon_Handler = Default_Handler + #pragma weak PendSV_Handler = Default_Handler + #pragma weak SysTick_Handler = Default_Handler +#elif defined(__GNUC__) + + #define WEAK_REF_ATTRIBUTE __attribute__((weak, alias("Default_Handler"))) +#endif + +void NMI_Handler(void); // NMI has many sources and is handled by BSP +void HardFault_Handler(void) WEAK_REF_ATTRIBUTE; +void MemManage_Handler(void) WEAK_REF_ATTRIBUTE; +void BusFault_Handler(void) WEAK_REF_ATTRIBUTE; +void UsageFault_Handler(void) WEAK_REF_ATTRIBUTE; +void SecureFault_Handler(void) WEAK_REF_ATTRIBUTE; +void SVC_Handler(void) WEAK_REF_ATTRIBUTE; +void DebugMon_Handler(void) WEAK_REF_ATTRIBUTE; +void PendSV_Handler(void) WEAK_REF_ATTRIBUTE; +void SysTick_Handler(void) WEAK_REF_ATTRIBUTE; + +/* Vector table. */ +BSP_DONT_REMOVE const exc_ptr_t __VECTOR_TABLE[BSP_CORTEX_VECTOR_TABLE_ENTRIES] BSP_PLACE_IN_SECTION( + BSP_SECTION_FIXED_VECTORS) = +{ + (exc_ptr_t) (&g_main_stack[0] + BSP_CFG_STACK_MAIN_BYTES), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* NMI Handler */ + HardFault_Handler, /* Hard Fault Handler */ + MemManage_Handler, /* MPU Fault Handler */ + BusFault_Handler, /* Bus Fault Handler */ + UsageFault_Handler, /* Usage Fault Handler */ + SecureFault_Handler, /* Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* SVCall Handler */ + DebugMon_Handler, /* Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* PendSV Handler */ + SysTick_Handler, /* SysTick Handler */ +}; + +/** @} (end addtogroup BSP_MCU) */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c new file mode 100644 index 00000000000..4ca04e2b0d3 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c @@ -0,0 +1,718 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include +#if defined(__GNUC__) && defined(__llvm__) && !defined(__ARMCC_VERSION) && !defined(__CLANG_TIDY__) + #include +#endif +#if defined(__ARMCC_VERSION) + #if defined(__ARMCC_USING_STANDARDLIB) + #include + #endif +#endif +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Mask to select CP bits( 0xF00000 ) */ +#define CP_MASK (0xFU << 20) + +/* Startup value for CCR to enable instruction cache, branch prediction and LOB extension */ +#define CCR_CACHE_ENABLE (0x000E0201) + +/* Value to write to OAD register of MPU stack monitor to enable NMI when a stack overflow is detected. */ +#define BSP_STACK_POINTER_MONITOR_NMI_ON_DETECTION (0xA500U) + +/* Key code for writing PRCR register. */ +#define BSP_PRV_PRCR_KEY (0xA500U) +#define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U) +#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U) +#define BSP_PRV_STACK_LIMIT ((uint32_t) &g_main_stack[0]) +#define BSP_PRV_STACK_TOP ((uint32_t) (uint32_t) &g_main_stack[BSP_CFG_STACK_MAIN_BYTES]) +#define BSP_TZ_STACK_SEAL_VALUE (0xFEF5EDA5) + +#define ARMV8_MPU_REGION_MIN_SIZE (32U) + +#if (BSP_CFG_CPU_CORE == 0) && (BSP_FEATURE_BSP_HAS_ITCM || BSP_FEATURE_BSP_HAS_DTCM) + #define BSP_PRV_ITCM_START_ADDRESS (0x00000000UL) + #define BSP_PRV_DTCM_START_ADDRESS (0x20000000UL) + #define BSP_PRV_VTOR_FIRST_PROJECT (0x02000000UL) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/** System Clock Frequency (Core Clock) */ +uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT; + +#if defined(__GNUC__) + +/* Nested in __GNUC__ because LLVM generates both __GNUC__ and __llvm__*/ + #if defined(__llvm__) && !defined(__CLANG_TIDY__) +extern uint32_t __tls_base; + #endif + +#endif + +/* Initialize static constructors */ +#if defined(__GNUC__) + +extern void (* __init_array_start[])(void); + +extern void (* __init_array_end[])(void); +#elif defined(__ICCARM__) +extern void __call_ctors(void const *, void const *); + + #pragma section = "SHT$$PREINIT_ARRAY" const + #pragma section = "SHT$$INIT_ARRAY" const +#endif + +extern void * __VECTOR_TABLE[]; +extern uint8_t g_main_stack[]; + +extern void R_BSP_SAUInit(void); +extern void R_BSP_SecurityInit(void); + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +#if BSP_FEATURE_BSP_RESET_TRNG +static void bsp_reset_trng_circuit(void); + +#endif + +#if defined(__ICCARM__) + +void R_BSP_WarmStart(bsp_warm_start_event_t event); + + #pragma weak R_BSP_WarmStart + +#elif defined(__GNUC__) || defined(__ARMCC_VERSION) + +void R_BSP_WarmStart(bsp_warm_start_event_t event) __attribute__((weak)); + +#endif + +#if BSP_CFG_EARLY_INIT +static void bsp_init_uninitialized_vars(void); + +#endif + +#if (BSP_CFG_CPU_CORE == 0) && (BSP_FEATURE_BSP_HAS_ITCM || BSP_FEATURE_BSP_HAS_DTCM) + #if !BSP_TZ_NONSECURE_BUILD +static void memset_64(uint64_t * destination, const uint64_t value, size_t count); + + #endif +#endif + +#if BSP_CFG_DCACHE_ENABLED +static void bsp_init_mpu(void); + +#endif + +#if BSP_CFG_C_RUNTIME_INIT +static void SystemRuntimeInit(const uint32_t external); + +#endif + +#if BSP_CFG_C_RUNTIME_INIT +static void SystemRuntimeInit (const uint32_t external) +{ + /* Initialize C runtime environment. */ + for (uint32_t i = 0; i < g_init_info.zero_count; i++) + { + if (external == g_init_info.p_zero_list[i].type.external) + { + memset(g_init_info.p_zero_list[i].p_base, 0U, + ((uint32_t) g_init_info.p_zero_list[i].p_limit - (uint32_t) g_init_info.p_zero_list[i].p_base)); + } + } + + for (uint32_t i = 0; i < g_init_info.copy_count; i++) + { + if (external == g_init_info.p_copy_list[i].type.external) + { + memcpy(g_init_info.p_copy_list[i].p_base, g_init_info.p_copy_list[i].p_load, + ((uint32_t) g_init_info.p_copy_list[i].p_limit - (uint32_t) g_init_info.p_copy_list[i].p_base)); + } + } +} + +#endif + +/*******************************************************************************************************************//** + * Initialize the MCU and the runtime environment. + **********************************************************************************************************************/ +void SystemInit (void) +{ +#if defined(RENESAS_CORTEX_M85) + + /* Enable the instruction cache, branch prediction, and the branch cache (required for Low Overhead Branch (LOB) extension). + * See sections 6.5, 6.6, and 6.7 in the Arm Cortex-M85 Processor Technical Reference Manual (Document ID: 101924_0002_05_en, Issue: 05) + * See section D1.2.9 in the Armv8-M Architecture Reference Manual (Document number: DDI0553B.w, Document version: ID07072023) */ + SCB->CCR = (uint32_t) CCR_CACHE_ENABLE; + __DSB(); + __ISB(); + + #if !BSP_TZ_NONSECURE_BUILD + + /* If Cortex-M85 revision is r1p1 or newer. */ + const uint32_t cpuid = SCB->CPUID; + const uint32_t cpuid_variant = ((cpuid & SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); + const uint32_t cpuid_revision = ((cpuid & SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); + if (((cpuid_variant == 1) && (cpuid_revision >= 1)) || (cpuid_variant > 1)) + { + /* Set D-Cache forced write-through according to BSP configuration. */ + #if BSP_CFG_DCACHE_FORCE_WRITETHROUGH + MEMSYSCTL->MSCR |= MEMSYSCTL_MSCR_FORCEWT_Msk; + #else + MEMSYSCTL->MSCR &= ~(MEMSYSCTL_MSCR_FORCEWT_Msk); + #endif + __DSB(); + __ISB(); + } + else + { + /* Apply Arm Cortex-M85 errata workarounds for D-Cache. + * See erratum 3175626 and 3190818 in the Cortex-M85 AT640 and Cortex-M85 with FPU AT641 Software Developer Errata Notice (Date of issue: March 07, 2024, Document version: 13.0, Document ID: SDEN-2236668). */ + MEMSYSCTL->MSCR |= MEMSYSCTL_MSCR_FORCEWT_Msk; + __DSB(); + __ISB(); + ICB->ACTLR |= (1U << 16U); + __DSB(); + __ISB(); + } + #endif +#endif + +#if __FPU_USED + + /* Enable the FPU only when it is used. + * Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C) */ + + /* Set bits 20-23 (CP10 and CP11) to enable FPU. */ + SCB->CPACR = (uint32_t) CP_MASK; +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Seal the main stack for secure projects. Reference: + * https://developer.arm.com/documentation/100720/0300 + * https://developer.arm.com/support/arm-security-updates/armv8-m-stack-sealing */ + uint32_t * p_main_stack_top = (uint32_t *) &g_main_stack[BSP_CFG_STACK_MAIN_BYTES]; + *p_main_stack_top = BSP_TZ_STACK_SEAL_VALUE; + + #if BSP_SECONDARY_CORE_BUILD + + /* Configure SAU early for secondary core since primary has already configured SAR registers */ + R_BSP_SAUInit(); + #endif +#endif + +#if !BSP_TZ_NONSECURE_BUILD + + /* VTOR is in undefined state out of RESET: + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-control-block/system-control-block-registers-summary?lang=en. + * Set the Secure/Non-Secure VTOR to the vector table address based on the build. This is skipped for non-secure + * projects because SCB_NS->VTOR is set by the secure project before the non-secure project runs. */ + SCB->VTOR = (uint32_t) &__VECTOR_TABLE; +#endif + +#if !BSP_TZ_CFG_SKIP_INIT && !BSP_CFG_SKIP_INIT + #if BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP + + /* Unlock VBTCR1 register. */ + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK; + + /* The VBTCR1.BPWSWSTP must be set after reset on MCUs that have VBTCR1.BPWSWSTP. Reference section 11.2.1 + * "VBATT Control Register 1 (VBTCR1)" and Figure 11.2 "Setting flow of the VBTCR1.BPWSWSTP bit" in the RA4M1 manual + * R01UM0007EU0110. This must be done before bsp_clock_init because LOCOCR, LOCOUTCR, SOSCCR, and SOMCR cannot + * be accessed until VBTSR.VBTRVLD is set. */ + R_SYSTEM->VBTCR1 = 1U; + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->VBTSR_b.VBTRVLD, 1U); + + /* Lock VBTCR1 register. */ + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; + #endif +#endif + +#if BSP_FEATURE_TFU_SUPPORTED + R_BSP_MODULE_START(FSP_IP_TFU, 0U); +#endif + +#if BSP_FEATURE_MACL_SUPPORTED + #if __has_include("arm_math_types.h") + R_BSP_MODULE_START(FSP_IP_MACL, 0U); + #endif +#endif + +#if BSP_CFG_EARLY_INIT + + /* Initialize uninitialized BSP variables early for use in R_BSP_WarmStart. */ + bsp_init_uninitialized_vars(); +#endif + + /* Call pre clock initialization hook. */ + R_BSP_WarmStart(BSP_WARM_START_RESET); + +#if BSP_TZ_CFG_SKIP_INIT || BSP_CFG_SKIP_INIT + + /* Initialize clock variables to be used with R_BSP_SoftwareDelay. */ + bsp_clock_freq_var_init(); + + #if !BSP_TZ_CFG_SKIP_INIT && defined(R_CACHE) + + /* Enable C-Cache if secondary core has one. + * Do not enable CM33 C-Cache for secondary core TrustZone projects because of limitations listed in + * RA8P1 UM 2.16.5.3 Restrictions Relating to Security Attribution of C-Cache and S-Cache */ + #if !(BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD) + + /* Enable cache */ + R_BSP_FlashCacheEnable(); + #endif + #endif +#else + + /* Configure system clocks. */ + bsp_clock_init(); + + #if BSP_FEATURE_BSP_RESET_TRNG + + /* To prevent an undesired current draw, this MCU requires a reset + * of the TRNG circuit after the clocks are initialized */ + + bsp_reset_trng_circuit(); + #endif +#endif + +#if BSP_FEATURE_IOPORT_HAS_LVOCR + #if !BSP_TZ_NONSECURE_BUILD && !BSP_SECONDARY_CORE_BUILD + + /* Unlock LVOCR register. */ + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK; + + /* Set LVOCR according to BSP configuration. + * Configure prior to warm start post clock, since OSPI_B may initialize within and begin using I/O. */ + R_SYSTEM->LVOCR = ((BSP_CFG_IOPORT_VOLTAGE_MODE_VCC2 << R_SYSTEM_LVOCR_LVO1E_Pos) & R_SYSTEM_LVOCR_LVO1E_Msk) | + ((BSP_CFG_IOPORT_VOLTAGE_MODE_VCC << R_SYSTEM_LVOCR_LVO0E_Pos) & R_SYSTEM_LVOCR_LVO0E_Msk); + + /* Lock LVOCR register. */ + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; + #endif +#endif + + /* Call post clock initialization hook. */ + R_BSP_WarmStart(BSP_WARM_START_POST_CLOCK); + +#if BSP_FEATURE_BSP_HAS_SP_MON + + /* Disable MSP monitoring */ + R_MPU_SPMON->SP[0].CTL = 0; + + /* Setup NMI interrupt */ + R_MPU_SPMON->SP[0].OAD = BSP_STACK_POINTER_MONITOR_NMI_ON_DETECTION; + + /* Setup start address */ + R_MPU_SPMON->SP[0].SA = BSP_PRV_STACK_LIMIT; + + /* Setup end address */ + R_MPU_SPMON->SP[0].EA = BSP_PRV_STACK_TOP; + + /* Set SPEEN bit to enable NMI on stack monitor exception. NMIER bits cannot be cleared after reset, so no need + * to read-modify-write. */ + R_ICU->NMIER = R_ICU_NMIER_SPEEN_Msk; + + /* Enable MSP monitoring */ + R_MPU_SPMON->SP[0].CTL = 1U; +#endif + +#if BSP_FEATURE_TZ_HAS_TRUSTZONE + __set_MSPLIM(BSP_PRV_STACK_LIMIT); +#endif + +#if (BSP_CFG_CPU_CORE == 0) && (BSP_FEATURE_BSP_HAS_ITCM || BSP_FEATURE_BSP_HAS_DTCM) + #if !BSP_TZ_NONSECURE_BUILD + + /* Zero initialize all available Cortex-M85 TCM memory if ECC is enabled for it and the very first project is executing. + * This may be either a bootloader if present, or a Flat or Secure application. */ + if ((MEMSYSCTL->MSCR & MEMSYSCTL_MSCR_ECCEN_Msk) && + (SCB->VTOR == BSP_PRV_VTOR_FIRST_PROJECT)) + { + const size_t itcm_num_doublewords = + (1U << (((MEMSYSCTL->ITCMCR & MEMSYSCTL_ITCMCR_SZ_Msk) >> MEMSYSCTL_ITCMCR_SZ_Pos) + 9U)) / + sizeof(uint64_t); + const size_t dtcm_num_doublewords = + (1U << (((MEMSYSCTL->DTCMCR & MEMSYSCTL_DTCMCR_SZ_Msk) >> MEMSYSCTL_DTCMCR_SZ_Pos) + 9U)) / + sizeof(uint64_t); + memset_64((uint64_t *) BSP_PRV_ITCM_START_ADDRESS, 0, itcm_num_doublewords); + memset_64((uint64_t *) BSP_PRV_DTCM_START_ADDRESS, 0, dtcm_num_doublewords); + } + #endif +#endif + +#if BSP_CFG_C_RUNTIME_INIT + + /* Initialize data placed in internal memories. */ + SystemRuntimeInit(0); +#endif + + /* Initialize SystemCoreClock variable. */ + SystemCoreClockUpdate(); + +#if BSP_FEATURE_RTC_IS_AVAILABLE || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_RTC_HAS_VBTICTLR + + /* For TZ project, it should be called by the secure application, whether RTC module is to be configured as secure or not. */ + #if !BSP_TZ_NONSECURE_BUILD && !BSP_CFG_BOOT_IMAGE && !BSP_CFG_SKIP_INIT + + /* Perform RTC reset sequence to avoid unintended operation. */ + R_BSP_Init_RTC(); + #endif +#endif + +#if !BSP_CFG_PFS_PROTECT && defined(R_PMISC) && !BSP_CFG_SKIP_INIT + #if BSP_TZ_SECURE_BUILD || (BSP_FEATURE_TZ_VERSION == 2 && FSP_PRIV_TZ_USE_SECURE_REGS) + R_PMISC->PWPRS = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled + R_PMISC->PWPRS = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled + #else + R_PMISC->PWPR = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled + R_PMISC->PWPR = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled + #endif +#endif + +#if FSP_PRIV_TZ_USE_SECURE_REGS && !BSP_CFG_SKIP_INIT + + /* Ensure that the PMSAR registers are set to their default value. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); + + for (uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++) + { + #if BSP_FEATURE_TZ_VERSION == 2 + R_PMISC->PMSAR[i].PMSAR = 0U; + #else + R_PMISC->PMSAR[i].PMSAR = UINT16_MAX; + #endif + } + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Initialize security features. */ + R_BSP_SecurityInit(); +#else + #if FSP_PRIV_TZ_USE_SECURE_REGS && !BSP_SECONDARY_CORE_BUILD + + /* Initialize peripherals to secure mode for flat projects */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); + R_PSCU->PSARB = 0; + R_PSCU->PSARC = 0; + R_PSCU->PSARD = 0; + R_PSCU->PSARE = 0; + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); + #endif +#endif + +#if BSP_CFG_DCACHE_ENABLED + bsp_init_mpu(); + + SCB_EnableDCache(); +#endif + +#if BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN && !BSP_CFG_SKIP_INIT + if ((((0 == R_SYSTEM->PGCSAR_b.NONSEC1) && FSP_PRIV_TZ_USE_SECURE_REGS) || + ((1 == R_SYSTEM->PGCSAR_b.NONSEC1) && BSP_TZ_NONSECURE_BUILD)) && (0 != R_SYSTEM->PDCTRGD)) + { + /* Turn on graphics power domain. + * This requires MOCO to be enabled, but MOCO is always enabled after bsp_clock_init(). */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT); + FSP_HARDWARE_REGISTER_WAIT((R_SYSTEM->PDCTRGD & (R_SYSTEM_PDCTRGD_PDCSF_Msk | R_SYSTEM_PDCTRGD_PDPGSF_Msk)), + R_SYSTEM_PDCTRGD_PDPGSF_Msk); + R_SYSTEM->PDCTRGD = 0; + FSP_HARDWARE_REGISTER_WAIT((R_SYSTEM->PDCTRGD & (R_SYSTEM_PDCTRGD_PDCSF_Msk | R_SYSTEM_PDCTRGD_PDPGSF_Msk)), 0); + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT); + } +#endif + +#if BSP_FEATURE_CGC_HAS_NPUCLK && !BSP_CFG_SKIP_INIT + if ((((0 == R_SYSTEM->PGCSAR_b.NONSEC2) && FSP_PRIV_TZ_USE_SECURE_REGS) || + ((1 == R_SYSTEM->PGCSAR_b.NONSEC2) && BSP_TZ_NONSECURE_BUILD)) && (0 != R_SYSTEM->PDCTRNPU)) + { + /* Turn on NPU power domain */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT); + FSP_HARDWARE_REGISTER_WAIT((R_SYSTEM->PDCTRNPU & (R_SYSTEM_PDCTRNPU_PDCSF_Msk | R_SYSTEM_PDCTRNPU_PDPGSF_Msk)), + R_SYSTEM_PDCTRNPU_PDPGSF_Msk); + R_SYSTEM->PDCTRNPU = 0; + FSP_HARDWARE_REGISTER_WAIT((R_SYSTEM->PDCTRNPU & (R_SYSTEM_PDCTRNPU_PDCSF_Msk | R_SYSTEM_PDCTRNPU_PDPGSF_Msk)), + 0); + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT); + } +#endif + + /* Call Post C runtime initialization hook. */ + R_BSP_WarmStart(BSP_WARM_START_POST_C); + +#if BSP_CFG_C_RUNTIME_INIT + + /* Initialize data placed in external memories. */ + SystemRuntimeInit(1); + + #if defined(__GNUC__) && defined(__llvm__) && !defined(__CLANG_TIDY__) && !(defined __ARMCC_VERSION) + + /* Initialize TLS memory. */ + _init_tls(&__tls_base); + _set_tls(&__tls_base); + #endif +#endif + +#if defined(__ICCARM__) + + /* Copy main thread TLS to RAM. */ + #pragma section="__DLIB_PERTHREAD_init" + #pragma section="__DLIB_PERTHREAD" + memcpy((uint32_t *) __section_begin("__DLIB_PERTHREAD"), (uint32_t *) __section_begin("__DLIB_PERTHREAD_init"), + (uint32_t) __section_size("__DLIB_PERTHREAD_init")); +#endif + +#if defined(RENESAS_CORTEX_M85) + + /* Invalidate I-Cache after initializing the .ram_from_flash section. */ + SCB_InvalidateICache(); +#endif + + /* Initialize static constructors */ +#if defined(__ARMCC_VERSION) + + /* TODO: should be replaced with some macro generated by e2studio */ + #if defined(__ARMCC_USING_STANDARDLIB) + + /* C++ requires default lib: https://developer.arm.com/documentation/dui0475/i/the-arm-c-micro-library/differences-between-microlib-and-the-default-c-library?lang=en */ + extern uint8_t g_heap[BSP_CFG_HEAP_BYTES]; + __rt_lib_init((uint32_t) g_heap, (uint32_t) g_heap + BSP_CFG_HEAP_BYTES); + #endif +#elif defined(__GNUC__) + int32_t count = __init_array_end - __init_array_start; + for (int32_t i = 0; i < count; i++) + { + __init_array_start[i](); + } + +#elif defined(__ICCARM__) + void const * pibase = __section_begin("SHT$$PREINIT_ARRAY"); + void const * ilimit = __section_end("SHT$$INIT_ARRAY"); + __call_ctors(pibase, ilimit); +#endif + + /* Initialize ELC events that will be used to trigger NVIC interrupts. */ + bsp_irq_cfg(); + + /* Call any BSP specific code. No arguments are needed so NULL is sent. */ + bsp_init(NULL); +} + +/*******************************************************************************************************************//** + * This function is called at various points during the startup process. + * This function is declared as a weak symbol higher up in this file because it is meant to be overridden by a user + * implemented version. One of the main uses for this function is to call functional safety code during the startup + * process. To use this function just copy this function into your own code and modify it to meet your needs. + * + * @param[in] event Where the code currently is in the start up process + **********************************************************************************************************************/ +void R_BSP_WarmStart (bsp_warm_start_event_t event) +{ + if (BSP_WARM_START_RESET == event) + { + /* C runtime environment has not been setup so you cannot use globals. System clocks are not setup. */ + } + + if (BSP_WARM_START_POST_CLOCK == event) + { + /* C runtime environment has not been setup so you cannot use globals. Clocks have been initialized. */ + } + else if (BSP_WARM_START_POST_C == event) + { + /* C runtime environment, system clocks, and pins are all setup. */ + } + else + { + /* Do nothing */ + } +} + +/*******************************************************************************************************************//** + * Disable TRNG circuit to prevent unnecessary current draw which may otherwise occur when the Crypto module + * is not in use. + **********************************************************************************************************************/ +#if BSP_FEATURE_BSP_RESET_TRNG +static void bsp_reset_trng_circuit (void) +{ + volatile uint8_t read_port = 0U; + FSP_PARAMETER_NOT_USED(read_port); /// Prevent compiler 'unused' warning + + /* Release register protection for low power modes (as per Figure "Example + * of initial setting flow for an unused circuit" in the LPM section of the relevant hardware manual) */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT); + + /* Enable TRNG function (disable stop function) */ + #if (BSP_FEATURE_RSIP_AES_SUPPORTED || BSP_FEATURE_RSIP_AES_B_SUPPORTED || BSP_FEATURE_RSIP_TRNG_SUPPORTED) + R_BSP_MODULE_START(FSP_IP_TRNG, 0); ///< TRNG Module Stop needs to be started/stopped for RA2 series. + #elif BSP_FEATURE_RSIP_SCE5_SUPPORTED + R_BSP_MODULE_START(FSP_IP_SCE, 0); ///< TRNG Module Stop needs to be started/stopped for RA4 series. + #else + #error "BSP_FEATURE_BSP_RESET_TRNG is defined but not handled." + #endif + + /* Wait for at least 3 PCLKB cycles */ + read_port = R_PFS->PORT[0].PIN[0].PmnPFS_b.PODR; + read_port = R_PFS->PORT[0].PIN[0].PmnPFS_b.PODR; + read_port = R_PFS->PORT[0].PIN[0].PmnPFS_b.PODR; + + /* Disable TRNG function */ + #if (BSP_FEATURE_RSIP_AES_SUPPORTED || BSP_FEATURE_RSIP_AES_B_SUPPORTED || BSP_FEATURE_RSIP_TRNG_SUPPORTED) + R_BSP_MODULE_STOP(FSP_IP_TRNG, 0); ///< TRNG Module Stop needs to be started/stopped for RA2 series. + #elif BSP_FEATURE_RSIP_SCE5_SUPPORTED + R_BSP_MODULE_STOP(FSP_IP_SCE, 0); ///< TRNG Module Stop needs to be started/stopped for RA4 series. + #else + #error "BSP_FEATURE_BSP_RESET_TRNG is defined but not handled." + #endif + + /* Reapply register protection for low power modes (as per Figure "Example + * of initial setting flow for an unused circuit" in the LPM section of the relevant hardware manual) */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT); +} + +#endif + +#if BSP_CFG_EARLY_INIT + +/*******************************************************************************************************************//** + * Initialize BSP variables not handled by C runtime startup. + **********************************************************************************************************************/ +static void bsp_init_uninitialized_vars (void) +{ + g_protect_pfswe_counter = 0; + + extern volatile uint16_t g_protect_counters[]; + for (uint32_t i = 0; i < 4; i++) + { + g_protect_counters[i] = 0; + } + + extern bsp_grp_irq_cb_t g_bsp_group_irq_sources[]; + for (uint32_t i = 0; i < 16; i++) + { + g_bsp_group_irq_sources[i] = 0; + } + + #if BSP_FEATURE_CGC_HAS_MOCO + + /* Set SystemCoreClock to MOCO */ + SystemCoreClock = BSP_MOCO_HZ; + #else + + /* Set SystemCoreClock to HOCO */ + SystemCoreClock = BSP_HOCO_HZ; + #endif +} + +#endif + +#if (BSP_CFG_CPU_CORE == 0) && (BSP_FEATURE_BSP_HAS_ITCM || BSP_FEATURE_BSP_HAS_DTCM) + #if !BSP_TZ_NONSECURE_BUILD + +/*******************************************************************************************************************//** + * 64-bit memory set for Armv8.1-M using low overhead loop instructions. + * + * @param[in] destination set destination start address, word aligned + * @param[in] value value to set + * @param[in] count number of doublewords to set + **********************************************************************************************************************/ +static void memset_64 (uint64_t * destination, const uint64_t value, size_t count) +{ + __asm volatile ( + "wls lr, %[count], memset_64_loop_end_%=\n" + #if (defined(__ARMCC_VERSION) || defined(__GNUC__)) + + /* Align the branch target to a 64-bit boundary, a CM85 specific optimization. */ + /* IAR does not support alignment control within inline assembly. */ + ".balign 8\n" + #endif + "memset_64_loop_start_%=:\n" + "strd %Q[value], %R[value], [%[destination]], #+8\n" + "le lr, memset_64_loop_start_%=\n" + "memset_64_loop_end_%=:" + :[destination] "+&r" (destination) + :[count] "r" (count), [value] "r" (value) + : "lr", "memory" + ); +} + + #endif +#endif + +#if BSP_CFG_DCACHE_ENABLED + +/*******************************************************************************************************************//** + * Initialize MPU for Armv8-M devices. + **********************************************************************************************************************/ +static void bsp_init_mpu (void) +{ + /* Maximum of eight attributes. */ + const uint8_t bsp_mpu_mair_attributes[] = + { + /* Normal, Non-cacheable */ + ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE) + }; + + /* Initialize MPU_MAIR0 and MPU_MAIR1 from attributes table. */ + uint8_t num_attr = (sizeof(bsp_mpu_mair_attributes) / sizeof(bsp_mpu_mair_attributes[0])); + for (uint8_t i = 0; i < num_attr; i++) + { + ARM_MPU_SetMemAttr(i, bsp_mpu_mair_attributes[i]); + } + + /* Initialize MPU from configuration table. */ + for (uint8_t i = 0; i < g_init_info.nocache_count; i++) + { + uint32_t rbar = ARM_MPU_RBAR((uint32_t) (g_init_info.p_nocache_list[i].p_base), ARM_MPU_SH_NON, 0U, 0U, 1U); + uint32_t rlar = ARM_MPU_RLAR((((uint32_t) g_init_info.p_nocache_list[i].p_limit) - ARMV8_MPU_REGION_MIN_SIZE), + 0U); + + /* Only configure regions of non-zero size. */ + if ((((rlar & MPU_RLAR_LIMIT_Msk) >> MPU_RLAR_LIMIT_Pos) + ARMV8_MPU_REGION_MIN_SIZE) > + ((rbar & MPU_RBAR_BASE_Msk) >> MPU_RBAR_BASE_Pos)) + { + ARM_MPU_SetRegion(i, rbar, rlar); + } + } + + /* + * SHCSR.MEMFAULTENA is set inside ARM_MPU_Enable(). + * Leave SHPR1.PRI_4 at reset value of zero. + * Leave MPU_CTRL.HFNMIENA at reset value of zero. + * Provide MPU_CTRL_PRIVDEFENA_Msk to ARM_MPU_Enable() to set MPU_CTRL.PRIVDEFENA. + */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); +} + +#endif + +/** @} (end addtogroup BSP_MCU) */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_clocks.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_clocks.c new file mode 100644 index 00000000000..0e8fc7eca7d --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_clocks.c @@ -0,0 +1,3532 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_clocks.h" + +#if BSP_TZ_NONSECURE_BUILD + #include "bsp_guard.h" +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Key code for writing PRCR register. */ +#define BSP_PRV_PRCR_KEY (0xA500U) +#define BSP_PRV_PRCR_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x3U) +#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U) + +/* Key code for writing LSMRWDIS register. */ +#define BSP_PRV_LSMRDIS_KEY (0xA500U) + +/* Wait state definitions for MEMWAIT. */ +#define BSP_PRV_MEMWAIT_ZERO_WAIT_CYCLES (0U) +#define BSP_PRV_MEMWAIT_ONE_WAIT_CYCLES (1U) +#define BSP_PRV_MEMWAIT_TWO_WAIT_CYCLES (2U) +#define BSP_PRV_MEMWAIT_MAX_ZERO_WAIT_FREQ (32000000U) +#define BSP_PRV_MEMWAIT_MAX_ONE_WAIT_FREQ (48000000U) + +/* Wait state definitions for FLDWAITR. */ +#define BSP_PRV_FLDWAITR_ONE_WAIT_CYCLES (0U) +#define BSP_PRV_FLDWAITR_TWO_WAIT_CYCLES (1U) +#define BSP_PRV_FLDWAITR_MAX_ONE_WAIT_FREQ (32000000U) + +/* Temporary solution until R_FACI is added to renesas.h. */ +#define BSP_PRV_FLDWAITR_REG_ACCESS (*((volatile uint8_t *) (0x407EFFC4U))) + +/* Wait state definitions for MCUS with SRAMWTSC and FLWT. */ +#define BSP_PRV_SRAMWTSC_WAIT_CYCLES_DISABLE (0U) +#define BSP_PRV_ROM_ZERO_WAIT_CYCLES (0U) +#define BSP_PRV_ROM_ONE_WAIT_CYCLES (1U) +#define BSP_PRV_ROM_TWO_WAIT_CYCLES (2U) +#define BSP_PRV_ROM_THREE_WAIT_CYCLES (3U) +#define BSP_PRV_ROM_FOUR_WAIT_CYCLES (4U) +#define BSP_PRV_ROM_FIVE_WAIT_CYCLES (5U) +#define BSP_PRV_SRAM_UNLOCK (((BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE) << \ + BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET) | 0x1U) +#define BSP_PRV_SRAM_LOCK (((BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE) << \ + BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET) | 0x0U) + +/* Determine whether SRAM wait states should be enabled */ +#if BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_SYSC_CLOCK_FREQ_NO_RAM_WAITS + #define BSP_PRV_SRAM_WAIT_CYCLES BSP_PRV_SRAMWTSC_WAIT_CYCLES_DISABLE +#else + #define BSP_PRV_SRAM_WAIT_CYCLES BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE +#endif + +/* Calculate value to write to MOMCR/CMC (MODRV controls main clock drive strength and MOSEL determines the source of the + * main oscillator). */ +#define BSP_PRV_MODRV ((CGC_MAINCLOCK_DRIVE << BSP_FEATURE_CGC_MODRV_SHIFT) & \ + BSP_FEATURE_CGC_MODRV_MASK) + +#if BSP_CFG_AUTODRVEN + #define BSP_PRV_AUTODRVEN (BSP_CFG_AUTODRVEN << R_SYSTEM_MOMCR_AUTODRVEN_Pos) +#else + #define BSP_PRV_AUTODRVEN (0U) +#endif + +#if !BSP_FEATURE_CGC_REGISTER_SET_B + #define BSP_PRV_MOSEL (BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE << R_SYSTEM_MOMCR_MOSEL_Pos) + #define BSP_PRV_MOMCR (BSP_PRV_MODRV | BSP_PRV_MOSEL | BSP_PRV_AUTODRVEN) +#else + #if BSP_CLOCK_CFG_MAIN_OSC_POPULATED + #if BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE + #define BSP_PRV_MOSEL (3U << R_SYSTEM_CMC_MOSEL_Pos) // External clock input mode + #else + #define BSP_PRV_MOSEL (1U << R_SYSTEM_CMC_MOSEL_Pos) // Oscillation mode + #endif + #define BSP_PRV_CMC_MOSC (BSP_PRV_MODRV | BSP_PRV_MOSEL) + #endif + +/* Calculate value to write to CMC (SODRV controls sub-clock oscillator drive capability and SOSEL determines the source of the + * sub-clock oscillator). */ + #if (0 == BSP_CLOCK_CFG_SUBCLOCK_DRIVE) + #define BSP_PRV_SODRV (1U << R_SYSTEM_CMC_SODRV_Pos) // Sub-Clock Oscillator Drive Capability Normal mode + #elif (1 == BSP_CLOCK_CFG_SUBCLOCK_DRIVE) + #define BSP_PRV_SODRV (0U << R_SYSTEM_CMC_SODRV_Pos) // Sub-Clock Oscillator Drive Capability Low Power Mode 1 + #else + #define BSP_PRV_SODRV (BSP_CLOCK_CFG_SUBCLOCK_DRIVE << R_SYSTEM_CMC_SODRV_Pos) + #endif + #define BSP_PRV_CMC_SOSC (BSP_PRV_SODRV | \ + (BSP_CLOCK_CFG_SUBCLOCK_POPULATED << R_SYSTEM_CMC_SOSEL_Pos) | \ + (BSP_CLOCK_CFG_SUBCLOCK_POPULATED << R_SYSTEM_CMC_XTSEL_Pos)) + + #if (BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_FSXP_SOURCE) + #define BSP_PRV_OSMC (0U << R_SYSTEM_OSMC_WUTMMCK0_Pos) // Use Sub-clock oscillator (SOSC) as Subsystem Clock (FSXP) source. + #elif (BSP_CLOCKS_SOURCE_CLOCK_LOCO == BSP_CFG_FSXP_SOURCE) + #define BSP_PRV_OSMC (1U << R_SYSTEM_OSMC_WUTMMCK0_Pos) // Use Low-speed on-chip oscillator clock (LOCO) as Subsystem Clock (FSXP) source. + #endif + + #if (BSP_CFG_CLKOUT_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) && (BSP_CFG_CLKOUT_SOURCE != BSP_CFG_CLOCK_SOURCE) + #define BSP_PRV_CLKOUT_SOURCE_SET (1U) + #elif defined(BSP_CFG_CLKOUT1_SOURCE) && (BSP_CFG_CLKOUT1_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) && \ + (BSP_CFG_CLKOUT1_SOURCE != BSP_CFG_CLOCK_SOURCE) + #define BSP_PRV_CLKOUT_SOURCE_SET (2U) + #else + #define BSP_PRV_CLKOUT_SOURCE_SET (0U) + #endif +#endif + +/* Locations of bitfields used to configure CLKOUT. */ +#define BSP_PRV_CKOCR_CKODIV_BIT (4U) +#define BSP_PRV_CKOCR_CKOEN_BIT (7U) + +/* Stop interval of at least 5 SOSC clock cycles between stop and restart of SOSC. + * Calculated based on 8Mhz of MOCO clock. */ +#define BSP_PRV_SUBCLOCK_STOP_INTERVAL_US (200U) + +/* Locations of bitfields used to configure Peripheral Clocks. */ +#define BSP_PRV_PERIPHERAL_CLK_REQ_BIT_POS (6U) +#define BSP_PRV_PERIPHERAL_CLK_REQ_BIT_MASK (1U << BSP_PRV_PERIPHERAL_CLK_REQ_BIT_POS) +#define BSP_PRV_PERIPHERAL_CLK_RDY_BIT_POS (7U) +#define BSP_PRV_PERIPHERAL_CLK_RDY_BIT_MASK (1U << BSP_PRV_PERIPHERAL_CLK_RDY_BIT_POS) + +#ifdef BSP_CFG_UCLK_DIV + +/* If the MCU has SCKDIVCR2 for USBCK configuration. */ + #if !BSP_FEATURE_USB_HAS_USBCKDIVCR + +/* Location of bitfield used to configure USB clock divider. */ + #define BSP_PRV_SCKDIVCR2_UCK_BIT (4U) + #define BSP_PRV_UCK_DIV (BSP_CFG_UCLK_DIV) + +/* If the MCU has USBCKDIVCR. */ + #elif BSP_FEATURE_USB_HAS_USBCKDIVCR + #if BSP_CLOCKS_USB_CLOCK_DIV_1 == BSP_CFG_UCLK_DIV + #define BSP_PRV_UCK_DIV (0U) + #elif BSP_CLOCKS_USB_CLOCK_DIV_2 == BSP_CFG_UCLK_DIV + #define BSP_PRV_UCK_DIV (1U) + #elif BSP_CLOCKS_USB_CLOCK_DIV_3 == BSP_CFG_UCLK_DIV + #define BSP_PRV_UCK_DIV (5U) + #elif BSP_CLOCKS_USB_CLOCK_DIV_4 == BSP_CFG_UCLK_DIV + #define BSP_PRV_UCK_DIV (2U) + #elif BSP_CLOCKS_USB_CLOCK_DIV_5 == BSP_CFG_UCLK_DIV + #define BSP_PRV_UCK_DIV (6U) + #elif BSP_CLOCKS_USB_CLOCK_DIV_6 == BSP_CFG_UCLK_DIV + #define BSP_PRV_UCK_DIV (3U) + #elif BSP_CLOCKS_USB_CLOCK_DIV_8 == BSP_CFG_UCLK_DIV + #define BSP_PRV_UCK_DIV (4U) + #elif BSP_CLOCKS_USB_CLOCK_DIV_10 == BSP_CFG_UCLK_DIV + #define BSP_PRV_UCK_DIV (7U) + #elif BSP_CLOCKS_USB_CLOCK_DIV_16 == BSP_CFG_UCLK_DIV + #define BSP_PRV_UCK_DIV (8U) + #else + + #error "BSP_CFG_UCLK_DIV not supported." + + #endif + #endif +#endif + +/* Choose the value to write to FLLCR2 (if applicable). */ +#if BSP_PRV_HOCO_USE_FLL + #if 1U == BSP_CFG_HOCO_FREQUENCY + #define BSP_PRV_FLL_FLLCR2 (0x226U) + #elif 2U == BSP_CFG_HOCO_FREQUENCY + #define BSP_PRV_FLL_FLLCR2 (0x263U) + #elif 4U == BSP_CFG_HOCO_FREQUENCY + #define BSP_PRV_FLL_FLLCR2 (0x263U) + #else + +/* When BSP_CFG_HOCO_FREQUENCY is 0, 4, 7 */ + #define BSP_PRV_FLL_FLLCR2 (0x1E9U) + #endif +#endif + +/* Calculate the value to write to SCKDIVCR. */ +#define BSP_PRV_STARTUP_SCKDIVCR_ICLK_BITS ((BSP_CFG_ICLK_DIV & 0xFU) << 24U) +#if BSP_FEATURE_CGC_HAS_PCLKE + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKE_BITS ((BSP_CFG_PCLKE_DIV & 0xFU) << 20U) +#else + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKE_BITS (0U) +#endif +#if BSP_FEATURE_CGC_HAS_PCLKD + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS (BSP_CFG_PCLKD_DIV & 0xFU) +#else + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS (0U) +#endif +#if BSP_FEATURE_CGC_HAS_PCLKC + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS ((BSP_CFG_PCLKC_DIV & 0xFU) << 4U) +#else + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS (0U) +#endif +#if BSP_FEATURE_CGC_HAS_PCLKB + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS ((BSP_CFG_PCLKB_DIV & 0xFU) << 8U) +#else + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS (0U) +#endif +#if BSP_FEATURE_CGC_HAS_PCLKA + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS ((BSP_CFG_PCLKA_DIV & 0xFU) << 12U) +#else + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS (0U) +#endif +#if BSP_FEATURE_CGC_HAS_BCLK + #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS ((BSP_CFG_BCLK_DIV & 0xFU) << 16U) +#elif BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB + +/* Some MCUs have a requirement that bits 18-16 be set to the same value as the bits for configuring the PCLKB divisor. */ + #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS ((BSP_CFG_PCLKB_DIV & 0xFU) << 16U) +#else + #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS (0U) +#endif +#if BSP_FEATURE_CGC_HAS_FCLK + #define BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS ((BSP_CFG_FCLK_DIV & 0xFU) << 28U) +#else + #define BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS (0U) +#endif +#define BSP_PRV_STARTUP_SCKDIVCR (BSP_PRV_STARTUP_SCKDIVCR_ICLK_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_PCLKE_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS) +#if BSP_FEATURE_CGC_HAS_CPUCLK + #define BSP_PRV_STARTUP_SCKDIVCR2_CPUCK_BITS (BSP_CFG_CPUCLK_DIV & 0xFU) +#else + #define BSP_PRV_STARTUP_SCKDIVCR2_CPUCK_BITS (0) +#endif +#if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + +/* Key codes for MRAM registers. */ + #define BSP_PRV_MRCFREQ_KEY (0x1E000000) + #define BSP_PRV_MREFREQ_KEY (0xE1000000) + #ifndef BSP_PRV_MRCPFB_LIMIT + #define BSP_PRV_MRCPFB_LIMIT (0x65) + #endif + #define BSP_PRV_MRFREQ_MIN_HZ (32768) + +/* Set npuclk to the same value as mriclk if the MCU does not support npuclk. */ + #if (BSP_FEATURE_CGC_HAS_NPUCLK == 0) + #define BSP_CFG_NPUCLK_DIV (BSP_CFG_MRICLK_DIV) + #endif + #define BSP_PRV_STARTUP_SCKDIVCR2_CPUCK1_BITS ((BSP_CFG_CPUCLK1_DIV & 0xFU) << 4U) + #define BSP_PRV_STARTUP_SCKDIVCR2_NPUCK_BITS ((BSP_CFG_NPUCLK_DIV & 0xFU) << 8U) + #define BSP_PRV_STARTUP_SCKDIVCR2_MRICK_BITS ((BSP_CFG_MRICLK_DIV & 0xFU) << 12U) +#else + #define BSP_PRV_STARTUP_SCKDIVCR2_CPUCK1_BITS (0) + #define BSP_PRV_STARTUP_SCKDIVCR2_NPUCK_BITS (0) + #define BSP_PRV_STARTUP_SCKDIVCR2_MRICK_BITS (0) +#endif +#define BSP_PRV_STARTUP_SCKDIVCR2 (BSP_PRV_STARTUP_SCKDIVCR2_CPUCK_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR2_CPUCK1_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR2_NPUCK_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR2_MRICK_BITS) + +/* The number of clocks is used to size the g_clock_freq array. */ +#if BSP_PRV_PLL2_SUPPORTED + #define BSP_PRV_NUM_CLOCKS ((uint8_t) BSP_CLOCKS_SOURCE_CLOCK_PLL2 + \ + (BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS - 1) + \ + BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS) +#elif BSP_PRV_PLL_SUPPORTED + #define BSP_PRV_NUM_CLOCKS ((uint8_t) BSP_CLOCKS_SOURCE_CLOCK_PLL + \ + BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS) +#else + #define BSP_PRV_NUM_CLOCKS ((uint8_t) BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK + 1U) +#endif + +/* Calculate PLLCCR value. */ +#if BSP_PRV_PLL_SUPPORTED + #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL_SOURCE + #define BSP_PRV_PLSRCSEL (0) + #define BSP_PRV_PLL_USED (1) + #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE + #define BSP_PRV_PLSRCSEL (1) + #define BSP_PRV_PLL_USED (1) + #else + #define BSP_PRV_PLL_USED (0) + #endif + #define BSP_PRV_PLLCCR_PLLMUL_MASK (0x3F) // PLLMUL in PLLCCR is 6 bits wide + #define BSP_PRV_PLLCCR_PLLMUL_BIT (8) // PLLMUL in PLLCCR starts at bit 8 + #define BSP_PRV_PLLCCR_PLSRCSEL_BIT (4) // PLSRCSEL in PLLCCR starts at bit 4 + #define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) << \ + BSP_PRV_PLLCCR_PLLMUL_BIT) | \ + (BSP_PRV_PLSRCSEL << BSP_PRV_PLLCCR_PLSRCSEL_BIT)) | \ + BSP_CFG_PLL_DIV) + #endif + #if (2U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL_SOURCE + #define BSP_PRV_PLSRCSEL (0) + #define BSP_PRV_PLL_USED (1) + #else + #define BSP_PRV_PLL_USED (0) + #endif + #define BSP_PRV_PLLCCR2_PLLMUL_MASK (0x1F) // PLLMUL in PLLCCR2 is 5 bits wide + #define BSP_PRV_PLLCCR2_PLODIV_BIT (6) // PLODIV in PLLCCR2 starts at bit 6 + + #define BSP_PRV_PLLCCR2_PLLMUL (BSP_CFG_PLL_MUL >> 1) + #define BSP_PRV_PLLCCR ((BSP_PRV_PLLCCR2_PLLMUL & BSP_PRV_PLLCCR2_PLLMUL_MASK) | \ + (BSP_CFG_PLL_DIV << BSP_PRV_PLLCCR2_PLODIV_BIT)) + #endif + #if (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL_SOURCE + #define BSP_PRV_PLSRCSEL (0) + #define BSP_PRV_PLL_USED (1) + #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE + #define BSP_PRV_PLSRCSEL (1) + #define BSP_PRV_PLL_USED (1) + #else + #define BSP_PRV_PLL_USED (0) + #endif + + #if (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #define BSP_PRV_PLL_MUL_CFG_MACRO_PLLMUL_MASK (0x3FFU) + #elif (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #define BSP_PRV_PLL_MUL_CFG_MACRO_PLLMUL_MASK (0x7FFU) + #endif + + #define BSP_PRV_PLLCCR_PLLMULNF_BIT (6) // PLLMULNF in PLLCCR starts at bit 6 + #define BSP_PRV_PLLCCR_PLSRCSEL_BIT (4) // PLSRCSEL in PLLCCR starts at bit 4 + #define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLL_MUL_CFG_MACRO_PLLMUL_MASK) << \ + BSP_PRV_PLLCCR_PLLMULNF_BIT) | \ + (BSP_PRV_PLSRCSEL << BSP_PRV_PLLCCR_PLSRCSEL_BIT)) | \ + BSP_CFG_PLL_DIV) + #define BSP_PRV_PLLCCR2_PLL_DIV_MASK (0x0F) // PLL DIV in PLLCCR2/PLL2CCR2 is 4 bits wide + #define BSP_PRV_PLLCCR2_PLL_DIV_Q_BIT (4) // PLL DIV Q in PLLCCR2/PLL2CCR2 starts at bit 4 + #define BSP_PRV_PLLCCR2_PLL_DIV_R_BIT (8) // PLL DIV R in PLLCCR2/PLL2CCR2 starts at bit 8 + #define BSP_PRV_PLLCCR2 (((BSP_CFG_PLODIVR & BSP_PRV_PLLCCR2_PLL_DIV_MASK) << \ + BSP_PRV_PLLCCR2_PLL_DIV_R_BIT) | \ + ((BSP_CFG_PLODIVQ & BSP_PRV_PLLCCR2_PLL_DIV_MASK) << \ + BSP_PRV_PLLCCR2_PLL_DIV_Q_BIT) | \ + (BSP_CFG_PLODIVP & BSP_PRV_PLLCCR2_PLL_DIV_MASK)) + #endif + #if (4U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #if BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_PLL_SOURCE + #define BSP_PRV_PLL_USED (1) + #else + #define BSP_PRV_PLL_USED (0) + #endif + + #define BSP_PRV_PLLCCR_PLLMUL_MASK (0xFFU) // PLLMUL is 8 bits wide + #define BSP_PRV_PLLCCR_PLLMUL_BIT (8) // PLLMUL starts at bit 8 + #define BSP_PRV_PLLCCR_RESET (0x0004U) // Bit 2 must be written as 1 + #define BSP_PRV_PLLCCR (((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) << \ + BSP_PRV_PLLCCR_PLLMUL_BIT) | \ + BSP_PRV_PLLCCR_RESET) + #endif + + #if (5U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL_SOURCE + #define BSP_PRV_PLSRCSEL (0) + #define BSP_PRV_PLL_USED (1) + #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE + #define BSP_PRV_PLSRCSEL (1) + #define BSP_PRV_PLL_USED (1) + #else + #define BSP_PRV_PLL_USED (0) + #endif + #define BSP_PRV_PLLCCR_PLLMUL_MASK (0x1F) // PLLMUL in PLLCCR is 5 bits wide + #define BSP_PRV_PLLCCR_PLLMUL_BIT (8) // PLLMUL in PLLCCR starts at bit 8 + #define BSP_PRV_PLLCCR_PLSRCSEL_BIT (4) // PLSRCSEL in PLLCCR starts at bit 4 + #if (BSP_CFG_PLL_DIV == BSP_CLOCKS_PLL_DIV_1) + #define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) << \ + BSP_PRV_PLLCCR_PLLMUL_BIT) | \ + (BSP_PRV_PLSRCSEL << BSP_PRV_PLLCCR_PLSRCSEL_BIT)) | \ + (0U)) + #elif (BSP_CFG_PLL_DIV == BSP_CLOCKS_PLL_DIV_4) + #define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) << \ + BSP_PRV_PLLCCR_PLLMUL_BIT) | \ + (BSP_PRV_PLSRCSEL << BSP_PRV_PLLCCR_PLSRCSEL_BIT)) | \ + (1U)) + #elif (BSP_CFG_PLL_DIV == BSP_CLOCKS_PLL_DIV_6) + #define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) << \ + BSP_PRV_PLLCCR_PLLMUL_BIT) | \ + (BSP_PRV_PLSRCSEL << BSP_PRV_PLLCCR_PLSRCSEL_BIT)) | \ + (2U)) + #endif + #endif +#endif + +#if BSP_FEATURE_CGC_HAS_PLL2 + #if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL2_SOURCE + #define BSP_PRV_PL2SRCSEL (0) + #define BSP_PRV_PLL2_USED (1) + #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL2_SOURCE + #define BSP_PRV_PL2SRCSEL (1) + #define BSP_PRV_PLL2_USED (1) + #else + #define BSP_PRV_PLL2_USED (0) + #endif + + #if (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) + + #if (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #define BSP_PRV_PLL2_MUL_CFG_MACRO_PLLMUL_MASK (0x3FFU) + #elif (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #define BSP_PRV_PLL2_MUL_CFG_MACRO_PLLMUL_MASK (0x7FFU) + #endif + + #define BSP_PRV_PLL2_MUL_CFG_MACRO_PLLMULNF_MASK (0x003U) + #define BSP_PRV_PLL2CCR_PLLMULNF_BIT (6) // PLLMULNF in PLLCCR starts at bit 6 + #define BSP_PRV_PLL2CCR_PLSRCSEL_BIT (4) // PLSRCSEL in PLLCCR starts at bit 4 + #define BSP_PRV_PLL2CCR ((((BSP_CFG_PLL2_MUL & BSP_PRV_PLL2_MUL_CFG_MACRO_PLLMUL_MASK) << \ + BSP_PRV_PLL2CCR_PLLMULNF_BIT) | \ + (BSP_PRV_PL2SRCSEL << BSP_PRV_PLL2CCR_PLSRCSEL_BIT)) | \ + BSP_CFG_PLL2_DIV) + #define BSP_PRV_PLL2CCR2_PLL_DIV_MASK (0x0F) // PLL DIV in PLL2CCR2 is 4 bits wide + #define BSP_PRV_PLL2CCR2_PLL_DIV_Q_BIT (4) // PLL DIV Q in PLL2CCR2 starts at bit 4 + #define BSP_PRV_PLL2CCR2_PLL_DIV_R_BIT (8) // PLL DIV R in PLL2CCR2 starts at bit 8 + #define BSP_PRV_PLL2CCR2 (((BSP_CFG_PL2ODIVR & BSP_PRV_PLL2CCR2_PLL_DIV_MASK) << \ + BSP_PRV_PLL2CCR2_PLL_DIV_R_BIT) | \ + ((BSP_CFG_PL2ODIVQ & BSP_PRV_PLL2CCR2_PLL_DIV_MASK) << \ + BSP_PRV_PLL2CCR2_PLL_DIV_Q_BIT) | \ + (BSP_CFG_PL2ODIVP & BSP_PRV_PLL2CCR2_PLL_DIV_MASK)) + #else + #define BSP_PRV_PLL2CCR ((BSP_CFG_PLL2_MUL << R_SYSTEM_PLL2CCR_PLL2MUL_Pos) | \ + (BSP_CFG_PLL2_DIV << R_SYSTEM_PLL2CCR_PL2IDIV_Pos) | \ + (BSP_PRV_PL2SRCSEL << R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos)) + #endif +#endif + +/* All clocks with configurable source except PLL and CLKOUT can use PLL. */ +#if (BSP_CFG_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL) + #define BSP_PRV_STABILIZE_PLL (1) +#endif + +/* All clocks with configurable source can use the main oscillator. */ +#if (BSP_CFG_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) + #define BSP_PRV_STABILIZE_MAIN_OSC (1) +#elif defined(BSP_CFG_UCLK_SOURCE) && BSP_FEATURE_USB_HAS_CLOCK_REQ && \ + (BSP_CFG_UCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_CANFDCLK_SOURCE) && (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_PLL_SOURCE) && (BSP_CFG_PLL_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) && BSP_PRV_PLL_USED + #define BSP_PRV_MAIN_OSC_USED (1) + #define BSP_PRV_STABILIZE_MAIN_OSC (1) +#elif defined(BSP_CFG_PLL2_SOURCE) && (BSP_CFG_PLL2_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) && BSP_PRV_PLL2_USED + #define BSP_PRV_MAIN_OSC_USED (1) + #define BSP_PRV_STABILIZE_MAIN_OSC (1) +#elif defined(BSP_CFG_CLKOUT_SOURCE) && (BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_CLKOUT1_SOURCE) && (BSP_CFG_CLKOUT1_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_SCISPICLK_SOURCE) && (BSP_CFG_SCISPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_SPICLK_SOURCE) && (BSP_CFG_SPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_SCICLK_SOURCE) && (BSP_CFG_SCICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_CANFDCLK_SOURCE) && (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_GPTCLK_SOURCE) && (BSP_CFG_GPTCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_IICCLK_SOURCE) && (BSP_CFG_IICCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_CECCLK_SOURCE) && (BSP_CFG_CECCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_I3CCLK_SOURCE) && (BSP_CFG_I3CCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_LCDCLK_SOURCE) && (BSP_CFG_LCDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_USB60CLK_SOURCE) && (BSP_CFG_USB60CLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_OCTACLK_SOURCE) && (BSP_CFG_OCTACLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_SDADC_CLOCK_SOURCE) && (BSP_CFG_SDADC_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_UARTA0_CLOCK_SOURCE) && (BSP_CFG_UARTA0_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_UARTA1_CLOCK_SOURCE) && (BSP_CFG_UARTA1_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_TML_FITL0_SOURCE) && (BSP_CFG_TML_FITL0_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_TML_FITL1_SOURCE) && (BSP_CFG_TML_FITL1_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_ETHPHY_SOURCE) && (BSP_CFG_ETHPHY_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#else + #define BSP_PRV_MAIN_OSC_USED (0) +#endif + +/* All clocks with configurable source can use HOCO except the CECCLK and I3CCLK. */ +#if (BSP_CFG_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) + #define BSP_PRV_HOCO_USED (1) + #define BSP_PRV_STABILIZE_HOCO (1) +#elif defined(BSP_CFG_PLL_SOURCE) && (BSP_CFG_PLL_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) && BSP_PRV_PLL_USED + #define BSP_PRV_HOCO_USED (1) + #define BSP_PRV_STABILIZE_HOCO (1) +#elif defined(BSP_CFG_PLL2_SOURCE) && (BSP_CFG_PLL2_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) && BSP_PRV_PLL2_USED + #define BSP_PRV_HOCO_USED (1) + #define BSP_PRV_STABILIZE_HOCO (1) +#elif defined(BSP_CFG_UCLK_SOURCE) && BSP_FEATURE_USB_HAS_CLOCK_REQ && \ + (BSP_CFG_UCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_CLKOUT_SOURCE) && (BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_CLKOUT1_SOURCE) && (BSP_CFG_CLKOUT1_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_SCISPICLK_SOURCE) && (BSP_CFG_SCISPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_SPICLK_SOURCE) && (BSP_CFG_SPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_SCICLK_SOURCE) && (BSP_CFG_SCICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_CANFDCLK_SOURCE) && (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_GPTCLK_SOURCE) && (BSP_CFG_GPTCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_IICCLK_SOURCE) && (BSP_CFG_IICCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_LCDCLK_SOURCE) && (BSP_CFG_LCDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_USB60CLK_SOURCE) && (BSP_CFG_USB60CLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_OCTACLK_SOURCE) && (BSP_CFG_OCTACLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_SDADC_CLOCK_SOURCE) && (BSP_CFG_SDADC_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_UARTA0_CLOCK_SOURCE) && (BSP_CFG_UARTA0_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_UARTA1_CLOCK_SOURCE) && (BSP_CFG_UARTA1_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_TML_FITL0_SOURCE) && (BSP_CFG_TML_FITL0_SOURCE == BSP_CLOCKS_SOURCE_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_TML_FITL1_SOURCE) && (BSP_CFG_TML_FITL1_SOURCE == BSP_CLOCKS_SOURCE_HOCO) + #define BSP_PRV_HOCO_USED (1) +#else + #define BSP_PRV_HOCO_USED (0) +#endif + +/* All clocks with configurable source except PLL can use MOCO. */ +#if (BSP_CFG_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) + #define BSP_PRV_STABILIZE_MOCO (1) +#elif defined(BSP_CFG_CLKOUT_SOURCE) && (BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_CLKOUT1_SOURCE) && (BSP_CFG_CLKOUT1_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_UCLK_SOURCE) && BSP_FEATURE_USB_HAS_CLOCK_REQ && \ + (BSP_CFG_UCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_SCISPICLK_SOURCE) && (BSP_CFG_SCISPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_SPICLK_SOURCE) && (BSP_CFG_SPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_SCICLK_SOURCE) && (BSP_CFG_SCICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_CANFDCLK_SOURCE) && (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_GPTCLK_SOURCE) && (BSP_CFG_GPTCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_IICCLK_SOURCE) && (BSP_CFG_IICCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_I3CCLK_SOURCE) && (BSP_CFG_I3CCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_LCDCLK_SOURCE) && (BSP_CFG_LCDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_USB60CLK_SOURCE) && (BSP_CFG_USB60CLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_OCTACLK_SOURCE) && (BSP_CFG_OCTACLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_UARTA0_CLOCK_SOURCE) && (BSP_CFG_UARTA0_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_UARTA1_CLOCK_SOURCE) && (BSP_CFG_UARTA1_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_TML_FITL0_SOURCE) && (BSP_CFG_TML_FITL0_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_TML_FITL1_SOURCE) && (BSP_CFG_TML_FITL1_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_ESWCLK_SOURCE) && (BSP_CFG_ESWCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_ESWPHYCLK_SOURCE) && (BSP_CFG_ESWPHYCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_ESCCLK_SOURCE) && (BSP_CFG_ESCCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_ETHPHYCLK_SOURCE) && (BSP_CFG_ETHPHYCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_BCLKA_SOURCE) && (BSP_CFG_BCLKA_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#else + #define BSP_PRV_MOCO_USED (0) +#endif + +/* All clocks with configurable source except UCK, CANFD, LCDCLK, USBHSCLK, I3CCLK and PLL can use LOCO. */ +#if (BSP_CFG_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) + #define BSP_PRV_LOCO_USED (1) + #define BSP_PRV_STABILIZE_LOCO (1) +#elif defined(BSP_CFG_CLKOUT_SOURCE) && (BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) + #define BSP_PRV_LOCO_USED (1) +#elif defined(BSP_CFG_CLKOUT1_SOURCE) && (BSP_CFG_CLKOUT1_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) + #define BSP_PRV_LOCO_USED (1) +#elif defined(BSP_CFG_SCISPICLK_SOURCE) && (BSP_CFG_SCISPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) + #define BSP_PRV_LOCO_USED (1) +#elif defined(BSP_CFG_SPICLK_SOURCE) && (BSP_CFG_SPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) + #define BSP_PRV_LOCO_USED (1) +#elif defined(BSP_CFG_SCICLK_SOURCE) && (BSP_CFG_SCICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) + #define BSP_PRV_LOCO_USED (1) +#elif defined(BSP_CFG_CANFDCLK_SOURCE) && (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) + #define BSP_PRV_LOCO_USED (1) +#elif defined(BSP_CFG_GPTCLK_SOURCE) && (BSP_CFG_GPTCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) + #define BSP_PRV_LOCO_USED (1) +#elif defined(BSP_CFG_IICCLK_SOURCE) && (BSP_CFG_IICCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) + #define BSP_PRV_LOCO_USED (1) +#elif defined(BSP_CFG_OCTACLK_SOURCE) && (BSP_CFG_OCTACLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) + #define BSP_PRV_LOCO_USED (1) +#elif defined(BSP_CFG_UARTA0_CLOCK_SOURCE) && (BSP_CFG_UARTA0_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) + #define BSP_PRV_LOCO_USED (1) +#elif defined(BSP_CFG_UARTA1_CLOCK_SOURCE) && (BSP_CFG_UARTA1_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) + #define BSP_PRV_LOCO_USED (1) +#elif (defined(BSP_CFG_FSXP_SOURCE) && (BSP_CFG_FSXP_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO)) + #define BSP_PRV_LOCO_USED (1) +#else + #define BSP_PRV_LOCO_USED (0) +#endif + +/* Determine the optimal operating speed mode to apply after clock configuration based on the startup clock + * frequency. */ +#if BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ && !BSP_PRV_PLL_USED && !BSP_PRV_PLL2_USED && \ + (BSP_FEATURE_CGC_LOW_SPEED_SUPPORT_MAIN_OSC || !BSP_PRV_MAIN_OSC_USED) + #define BSP_PRV_STARTUP_OPERATING_MODE (BSP_PRV_OPERATING_MODE_LOW_SPEED) +#elif BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ + #define BSP_PRV_STARTUP_OPERATING_MODE (BSP_PRV_OPERATING_MODE_MIDDLE_SPEED) +#else + #define BSP_PRV_STARTUP_OPERATING_MODE (BSP_PRV_OPERATING_MODE_HIGH_SPEED) +#endif + +#if defined(BSP_CFG_OPTION_SETTING_OFS1_ICSATS) && BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB + #define BSP_PRV_CLOCK_SUPPLY_TYPE_B (0 == BSP_CFG_OPTION_SETTING_OFS1_ICSATS) +#else + #define BSP_PRV_CLOCK_SUPPLY_TYPE_B (0) +#endif + +#if (BSP_FEATURE_CANFD_HAS_CLOCK && (BSP_CFG_CANFDCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) && \ + (BSP_CFG_CANFDCLK_SOURCE != BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)) || \ + (BSP_FEATURE_SCI_HAS_SCISPI_CLOCK && (BSP_CFG_SCISPICLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (BSP_FEATURE_SCI_HAS_CLOCK && (BSP_CFG_SCICLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (BSP_FEATURE_SPI_HAS_CLOCK && (BSP_CFG_SPICLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (BSP_PERIPHERAL_GPT_GTCLK_PRESENT && (BSP_CFG_GPTCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (BSP_FEATURE_IIC_HAS_CLOCK && (BSP_CFG_IICCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (BSP_FEATURE_CEC_HAS_CLOCK && (BSP_CFG_CECCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (BSP_FEATURE_I3C_HAS_CLOCK && (BSP_CFG_I3CCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (BSP_FEATURE_USB_HAS_USB60_CLOCK && (BSP_CFG_USB60CLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (BSP_FEATURE_LCD_HAS_CLOCK && (BSP_CFG_LCDCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (BSP_FEATURE_ADC_HAS_CLOCK && (BSP_CFG_ADCCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (BSP_FEATURE_ESWM_HAS_CLOCK && (BSP_CFG_ESWCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (BSP_FEATURE_ESWM_HAS_ESWPHY_CLOCK && (BSP_CFG_ESWPHYCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (defined(BSP_CFG_BCLKA_SOURCE) && (BSP_CFG_BCLKA_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (BSP_FEATURE_BSP_HAS_DSMIF_CLOCK && \ + (BSP_CFG_DSMIFCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (BSP_FEATURE_BSP_HAS_ESC_CLOCK && \ + (BSP_CFG_ESCCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) + + #define BSP_PRV_HAS_ENABLED_PERIPHERAL_CLOCKS (1U) +#else + #define BSP_PRV_HAS_ENABLED_PERIPHERAL_CLOCKS (0U) +#endif + +#define BSP_PRV_HZ_PER_MHZ (1000000) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +#if !BSP_FEATURE_CGC_REGISTER_SET_B +static uint8_t bsp_clock_set_prechange(uint32_t requested_freq_hz); +static void bsp_clock_set_postchange(uint32_t updated_freq_hz, uint8_t new_rom_wait_state); + + #if BSP_FEATURE_CGC_HAS_MEMWAIT && !BSP_PRV_CLOCK_SUPPLY_TYPE_B +static void bsp_clock_set_memwait(uint32_t updated_freq_hz); + + #endif + + #if !BSP_CFG_USE_LOW_VOLTAGE_MODE +static void bsp_prv_operating_mode_opccr_set(uint8_t operating_mode); + + #endif +void bsp_prv_clock_dividers_set(uint32_t sckdivcr, uint16_t sckdivcr2); + +#else +static void bsp_prv_cmc_init(void); +static void bsp_prv_operating_mode_flmode_set(uint8_t operating_mode); + +static void bsp_prv_clkout_set(void); + +#endif + +static void bsp_prv_sosc_init(void); + +#if BSP_CLOCK_CFG_SUBCLOCK_POPULATED + #if defined(__ICCARM__) + +void R_BSP_SubClockStabilizeWait(uint32_t delay_ms); +void R_BSP_SubClockStabilizeWaitAfterReset(uint32_t delay_ms); + + #pragma weak R_BSP_SubClockStabilizeWait + #pragma weak R_BSP_SubClockStabilizeWaitAfterReset + + #elif defined(__GNUC__) || defined(__ARMCC_VERSION) + +void R_BSP_SubClockStabilizeWait(uint32_t delay_ms) __attribute__((weak)); +void R_BSP_SubClockStabilizeWaitAfterReset(uint32_t delay_ms) __attribute__((weak)); + + #endif +#endif + +#if (BSP_PRV_HAS_ENABLED_PERIPHERAL_CLOCKS == 1U) +static void bsp_peripheral_clock_set(volatile uint8_t * p_clk_ctrl_reg, + volatile uint8_t * p_clk_div_reg, + uint8_t peripheral_clk_div, + uint8_t peripheral_clk_source); + +#endif + +#if !BSP_FEATURE_CGC_REGISTER_SET_B + #if !BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET +static void bsp_prv_clock_set_hard_reset(void); + + #else +void bsp_soft_reset_prepare(void); + + #endif +#endif + +/* This array stores the clock frequency of each system clock. This section of RAM should not be initialized by the C + * runtime environment. This is initialized and used in bsp_clock_init, which is called before the C runtime + * environment is initialized. */ +static uint32_t g_clock_freq[BSP_PRV_NUM_CLOCKS] BSP_PLACE_IN_SECTION(BSP_SECTION_NOINIT); + +#if BSP_TZ_SECURE_BUILD + +/* Callback used to notify the nonsecure project that the clock settings have changed. */ +static bsp_clock_update_callback_t g_bsp_clock_update_callback = NULL; + +/* Pointer to nonsecure memory to store the callback args. */ +static bsp_clock_update_callback_args_t * gp_callback_memory = NULL; + +/* Reentrant method of calling the clock_update_callback. */ +static void r_bsp_clock_update_callback_call (bsp_clock_update_callback_t p_callback, + bsp_clock_update_callback_args_t * p_callback_args) +{ + /* Allocate memory for saving global callback args on the secure stack. */ + bsp_clock_update_callback_args_t callback_args; + + /* Save current info stored in callback memory. */ + callback_args = *gp_callback_memory; + + /* Write the callback args to the nonsecure callback memory. */ + *gp_callback_memory = *p_callback_args; + + /* Call the callback to notifiy ns project about clock changes. */ + p_callback(gp_callback_memory); + + /* Restore the info in callback memory. */ + *gp_callback_memory = callback_args; +} + +/* Initialize the callback, callback memory and invoke the callback to ensure the nonsecure project has the correct clock settings. */ +void r_bsp_clock_update_callback_set (bsp_clock_update_callback_t p_callback, + bsp_clock_update_callback_args_t * p_callback_memory) +{ + /* Store pointer to nonsecure callback memory. */ + gp_callback_memory = p_callback_memory; + + /* Store callback. */ + g_bsp_clock_update_callback = p_callback; + + /* Set callback args. */ + bsp_clock_update_callback_args_t callback_args = + { + .pll_freq = g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] + }; + + /* Call the callback. */ + r_bsp_clock_update_callback_call(g_bsp_clock_update_callback, &callback_args); +} + +#elif BSP_TZ_NONSECURE_BUILD && BSP_CFG_CLOCKS_SECURE == 1 + +bsp_clock_update_callback_args_t g_callback_memory; + #if BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD + #if defined(__ARMCC_VERSION) || defined(__ICCARM__) +static void BSP_CMSE_NONSECURE_CALL g_bsp_clock_update_callback (bsp_clock_update_callback_args_t * p_callback_args) + #elif defined(__GNUC__) + +static BSP_CMSE_NONSECURE_CALL void g_bsp_clock_update_callback (bsp_clock_update_callback_args_t * p_callback_args) + #endif + +{ + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = p_callback_args->pll_freq; + + /* Update the SystemCoreClock value based on the new g_clock_freq settings. */ + SystemCoreClockUpdate(); +} + + #endif +#endif + +#if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED + +/* List of MSTP bits that must be set before entering low power modes or changing SCKDIVCR. */ +static const uint8_t g_bsp_prv_power_change_mstp_data[][2] = BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY; + +static const uint8_t g_bsp_prv_power_change_mstp_length = sizeof(g_bsp_prv_power_change_mstp_data) / + sizeof(g_bsp_prv_power_change_mstp_data[0]); + +static volatile uint32_t * const gp_bsp_prv_mstp = &R_MSTP->MSTPCRB; +#endif + +#if (BSP_CFG_SLEEP_MODE_DELAY_ENABLE || BSP_CFG_RTOS_SLEEP_MODE_DELAY_ENABLE) && \ + BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS +static uint16_t g_pre_sleep_sckdivcr2; +#endif + +/*******************************************************************************************************************//** + * @internal + * @addtogroup BSP_MCU_PRV Internal BSP Documentation + * @ingroup RENESAS_INTERNAL + * @{ + **********************************************************************************************************************/ + +#if !BSP_FEATURE_CGC_REGISTER_SET_B + #if !BSP_CFG_USE_LOW_VOLTAGE_MODE + +/*********************************************************************************************************************** + * Changes the operating speed in OPCCR. Assumes the LPM registers are unlocked in PRCR and cache is off. + * + * @param[in] operating_mode Desired operating mode, must be one of the BSP_PRV_OPERATING_MODE_* macros, cannot be + * BSP_PRV_OPERATING_MODE_SUBOSC_SPEED + **********************************************************************************************************************/ +static void bsp_prv_operating_mode_opccr_set (uint8_t operating_mode) +{ + #if BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR + + /* If the desired operating mode is already set, return. */ + if (operating_mode == R_SYSTEM->OPCCR) + { + return; + } + + /* On some MCUs, the HOCO must be stable before updating OPCCR.OPCM. */ + if (0U == R_SYSTEM->HOCOCR) + { + /* Wait for HOCO to stabilize. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.HOCOSF, 1U); + } + #endif + + /* Wait for transition to complete. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OPCCR_b.OPCMTSF, 0U); + + /* Apply requested operating speed mode. */ + R_SYSTEM->OPCCR = operating_mode; + + /* Wait for transition to complete. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OPCCR_b.OPCMTSF, 0U); +} + + #endif +#endif + +#if !BSP_CFG_USE_LOW_VOLTAGE_MODE + +/*********************************************************************************************************************** + * Changes the operating speed mode. Assumes the LPM registers are unlocked in PRCR and cache is off. + * + * @param[in] operating_mode Desired operating mode, must be one of the BSP_PRV_OPERATING_MODE_* macros + **********************************************************************************************************************/ +void bsp_prv_operating_mode_set (uint8_t operating_mode) +{ + #if BSP_PRV_POWER_USE_DCDC + static bsp_power_mode_t power_mode = BSP_POWER_MODE_LDO; + + /* Disable DCDC if transitioning to an incompatible mode. */ + if ((operating_mode > BSP_PRV_OPERATING_MODE_MIDDLE_SPEED) && (R_SYSTEM->DCDCCTL & R_SYSTEM_DCDCCTL_DCDCON_Msk)) + { + /* LDO boost must be used if entering subclock speed mode (see "Switching from High-speed/Middle-speed mode + * in DCDC power mode to Subosc-speed mode or Software Standby mode" in the LPM section of the relevant hardware manual). */ + power_mode = R_BSP_PowerModeSet((BSP_PRV_OPERATING_MODE_SUBOSC_SPEED == operating_mode) ? + BSP_POWER_MODE_LDO_BOOST : BSP_POWER_MODE_LDO); + } + #endif + + #if BSP_FEATURE_CGC_HAS_SOPCCR + if (BSP_PRV_OPERATING_MODE_SUBOSC_SPEED == operating_mode) + { + /* Wait for transition to complete. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOPCCR_b.SOPCMTSF, 0U); + + /* Set subosc speed mode. */ + R_SYSTEM->SOPCCR = 0x1U; + + /* Wait for transition to complete. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOPCCR_b.SOPCMTSF, 0U); + } + else + #endif + { + #if BSP_FEATURE_CGC_HAS_SOPCCR + + /* Wait for transition to complete. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOPCCR_b.SOPCMTSF, 0U); + + /* Exit subosc speed mode first. */ + R_SYSTEM->SOPCCR = 0U; + + /* Wait for transition to complete. Check the entire register here since it should be set to 0 at this point. + * Checking the entire register is slightly more efficient. This will also hang the program if the LPM + * registers are not unlocked, which can help catch programming errors. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOPCCR, 0U); + #endif + + #if BSP_FEATURE_CGC_REGISTER_SET_B + bsp_prv_operating_mode_flmode_set(operating_mode); + #else + bsp_prv_operating_mode_opccr_set(operating_mode); + #endif + } + + #if BSP_PRV_POWER_USE_DCDC + + /* Enable DCDC if it was previously enabled. */ + if ((operating_mode <= BSP_PRV_OPERATING_MODE_MIDDLE_SPEED) && (power_mode < BSP_POWER_MODE_LDO)) + { + R_BSP_PowerModeSet(power_mode); + power_mode = BSP_POWER_MODE_LDO; + } + #endif +} + +#endif + +#if BSP_PRV_PLL_SUPPORTED + +/*********************************************************************************************************************** + * Updates the operating frequency of the specified PLL and all its output channels. + * + * @param[in] clock PLL being configured + * @param[in] p_pll_hz Array of values of the new PLL output clock frequencies + **********************************************************************************************************************/ +void bsp_prv_prepare_pll (uint32_t clock, uint32_t const * const p_pll_hz) +{ + if (BSP_CLOCKS_SOURCE_CLOCK_PLL == clock) + { + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = p_pll_hz[0]; + #if 3 == BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL1Q] = p_pll_hz[1]; + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL1R] = p_pll_hz[2]; + #endif + } + + #if BSP_PRV_PLL2_SUPPORTED + else + { + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL2] = p_pll_hz[0]; + #if 3 == BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL2Q] = p_pll_hz[1]; + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL2R] = p_pll_hz[2]; + #endif + } + #endif +} + +#endif + +/*******************************************************************************************************************//** + * Update SystemCoreClock variable based on current clock settings. + **********************************************************************************************************************/ +void SystemCoreClockUpdate (void) +{ +#if !BSP_FEATURE_CGC_REGISTER_SET_B + #if BSP_FEATURE_TZ_HAS_TRUSTZONE && (BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD) && BSP_FEATURE_TZ_VERSION == 2 + bool secure = !R_SYSTEM->CGFSAR_b.NONSEC00; + #endif + + uint32_t clock_index = FSP_STYPE3_REG8_READ(R_SYSTEM->SCKSCR, secure); + + #if !BSP_FEATURE_CGC_HAS_CPUCLK + uint32_t ick = + (FSP_STYPE3_REG32_READ(R_SYSTEM->SCKDIVCR, secure) & R_SYSTEM_SCKDIVCR_ICK_Msk) >> R_SYSTEM_SCKDIVCR_ICK_Pos; + SystemCoreClock = g_clock_freq[clock_index] >> ick; + #else + #if (BSP_CFG_CPU_CORE == 1) + uint8_t cpuck = (FSP_STYPE3_REG8_READ(R_SYSTEM->SCKDIVCR2, secure) & R_SYSTEM_SCKDIVCR2_CPUCK1_Msk) >> + R_SYSTEM_SCKDIVCR2_CPUCK1_Pos; + #else + uint8_t cpuck = (FSP_STYPE3_REG8_READ(R_SYSTEM->SCKDIVCR2, secure) & R_SYSTEM_SCKDIVCR2_CPUCK_Msk) >> + R_SYSTEM_SCKDIVCR2_CPUCK_Pos; + #endif + uint8_t cpuclk_div = cpuck; + + if (8U == cpuclk_div) + { + SystemCoreClock = g_clock_freq[clock_index] / 3U; + } + else if (9U == cpuclk_div) + { + SystemCoreClock = g_clock_freq[clock_index] / 6U; + } + else if (10U == cpuclk_div) + { + SystemCoreClock = g_clock_freq[clock_index] / 12U; + } + else if (11U == cpuclk_div) + { + SystemCoreClock = g_clock_freq[clock_index] / 24U; + } + else + { + SystemCoreClock = g_clock_freq[clock_index] >> cpuclk_div; + } + #endif +#else + #if BSP_CLOCK_CFG_MAIN_OSC_POPULATED + SystemCoreClock = g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC] >> R_SYSTEM->MOSCDIV; + #endif + if (BSP_CLOCKS_SOURCE_CLOCK_FSUB == R_SYSTEM->ICLKSCR_b.CKST) + { + #if BSP_CLOCK_CFG_SUBCLOCK_POPULATED + SystemCoreClock = R_SYSTEM->FSUBSCR ? g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_LOCO] : \ + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK]; + #else + SystemCoreClock = g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_LOCO]; + #endif + } + else + { + #if BSP_CLOCK_CFG_MAIN_OSC_POPULATED + if (BSP_CLOCKS_FMAIN_SOURCE_CLOCK_FOCO == R_SYSTEM->FMAINSCR_b.CKST) + #endif + { + #if BSP_FEATURE_CGC_HAS_MOCO + SystemCoreClock = R_SYSTEM->FOCOSCR_b.CKST ? \ + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_MOCO] >> R_SYSTEM->MOCODIV : \ + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_HOCO] >> R_SYSTEM->HOCODIV; + #else + SystemCoreClock = g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_HOCO] >> R_SYSTEM->HOCODIV; + #endif + } + } +#endif +} + +#if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED + +/*******************************************************************************************************************//** + * Sets MSTP bits as required by the hardware manual for the MCU (refer Figure "Example flow for changing the + * value of SCKDIVCR" in the CGC section of the relevant hardware manual). + * + * This function must be called before entering standby or changing SCKDIVCR. + * + * @return bitmask of bits set, where each bit corresponds to an index in g_bsp_prv_power_change_mstp_data + **********************************************************************************************************************/ +uint32_t bsp_prv_power_change_mstp_set (void) +{ + uint32_t mstp_set_bitmask = 0U; + for (uint32_t i = 0U; i < g_bsp_prv_power_change_mstp_length; i++) + { + /* Get the MSTP register index and the bit to test from the MCU specific array. */ + uint32_t mstp_index = g_bsp_prv_power_change_mstp_data[i][0]; + uint32_t mstp_bit = 1U << g_bsp_prv_power_change_mstp_data[i][1]; + + /* Only set the bit if it's currently cleared. */ + if (!(gp_bsp_prv_mstp[mstp_index] & mstp_bit)) + { + gp_bsp_prv_mstp[mstp_index] |= mstp_bit; + mstp_set_bitmask |= 1U << i; + } + + /* This loop takes over 250 ns (30 cycles at 120 MHz) between 2 consecutive bits being set. It was measured + * at 58 cycles for default IAR build configurations and 59 cycles for default GCC build configurations. */ + } + + /* The time between setting last MSTP bit and setting SCKDIVCR takes over 750 ns (90 cycles at 120 MHz). It was + * measured at 96 cycles for default IAR build configurations and 102 cycles for default GCC build + * configurations. */ + + return mstp_set_bitmask; +} + +#endif + +#if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED + +/*******************************************************************************************************************//** + * Clears MSTP bits set by bsp_prv_power_change_mstp_set as required by the hardware manual for the MCU (reference + * Figure "Example flow for changing the value of SCKDIVCR" in the CGC section of the relevant hardware manual). + * + * This function must be called after exiting standby or changing SCKDIVCR. + * + * @param[in] mstp_clear_bitmask bitmask of bits to clear, where each bit corresponds to an index in + * g_bsp_prv_power_change_mstp_data + **********************************************************************************************************************/ +void bsp_prv_power_change_mstp_clear (uint32_t mstp_clear_bitmask) +{ + /* The time between setting SCKDIVCR and clearing the first MSTP bit takes over 250 ns (30 cycles at 120 MHz). It + * was measured at 38 cycles for default IAR build configurations and 68 cycles for default GCC build + * configurations. */ + + for (uint32_t i = 0U; i < g_bsp_prv_power_change_mstp_length; i++) + { + /* Only clear the bit if it was set in bsp_prv_power_change_mstp_set. */ + if ((1U << i) & mstp_clear_bitmask) + { + /* Get the MSTP register index and the bit to test from the MCU specific array. */ + uint32_t mstp_index = g_bsp_prv_power_change_mstp_data[i][0]; + uint32_t mstp_bit = 1U << g_bsp_prv_power_change_mstp_data[i][1]; + + gp_bsp_prv_mstp[mstp_index] &= ~mstp_bit; + } + + /* This loop takes over 250 ns (30 cycles at 120 MHz) between 2 consecutive bits being cleared. It was measured + * at 44 cycles for default IAR build configurations and 53 cycles for default GCC build configurations. */ + } +} + +#endif + +#if !BSP_FEATURE_CGC_REGISTER_SET_B + +/*******************************************************************************************************************//** + * Write SCKDIVCR and SCKDIVCR2 in the correct order to ensure that CPUCLK frequency is greater than ICLK frequency. + * + * @param[in] sckdivcr The new SCKDIVCR setting. + * @param[in] sckdivcr2 The new SCKDIVCR2 setting. + **********************************************************************************************************************/ +void bsp_prv_clock_dividers_set (uint32_t sckdivcr, uint16_t sckdivcr2) +{ + #if BSP_FEATURE_CGC_HAS_CPUCLK + uint32_t requested_iclk_div = BSP_PRV_SCKDIVCR_DIV_VALUE( + (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRV_SCKDIVCR_DIV_MASK); + uint32_t current_iclk_div = BSP_PRV_SCKDIVCR_DIV_VALUE(R_SYSTEM->SCKDIVCR_b.ICK); + + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + uint16_t temp_sckdivcr2 = sckdivcr2; + #else + uint8_t temp_sckdivcr2 = ((uint8_t) sckdivcr2) & R_SYSTEM_SCKDIVCR2_CPUCK_Msk; + #endif + + if (requested_iclk_div >= current_iclk_div) + { + /* If the requested ICLK divider is greater than or equal to the current ICLK divider, then writing to + * SCKDIVCR first will always satisfy the constraint: CPUCLK frequency >= ICLK frequency. */ + R_SYSTEM->SCKDIVCR = sckdivcr; + R_SYSTEM->SCKDIVCR2 = temp_sckdivcr2; + } + else + { + /* If the requested ICLK divider is less than the current ICLK divider, then writing to SCKDIVCR2 first + * will always satisfy the constraint: CPUCLK frequency >= ICLK frequency. */ + R_SYSTEM->SCKDIVCR2 = temp_sckdivcr2; + R_SYSTEM->SCKDIVCR = sckdivcr; + } + + #else + FSP_PARAMETER_NOT_USED(sckdivcr2); + + R_SYSTEM->SCKDIVCR = sckdivcr; + #endif +} + + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + +/*******************************************************************************************************************//** + * Clears the PFB for MRAM. + **********************************************************************************************************************/ +void bsp_prv_clear_pfb (void) +{ + /* Clear MRAM pre-fetch buffer, see 54.4.3 Frequency Change Procedure for MRAM */ + R_MRMS->MRCPFB = 0x00; + (void) R_MRMS->MRCPFB; + (void) R_MRMS->MRCPFB; + (void) R_MRMS->MRCPFB; +} + +/*******************************************************************************************************************//** + * Sets the PFB for MRAM if the frequency exceeds the threshold. + **********************************************************************************************************************/ +void bsp_prv_set_pfb (void) +{ + uint32_t mrcfreq = R_MRMS->MRCFREQ_b.MRCMHZ; + + /* Do not enable Prefetch Buffer when MRAM read frequency is set to 100MHz or less. */ + if (mrcfreq >= BSP_PRV_MRCPFB_LIMIT) + { + R_MRMS->MRCPFB = 0x01; + } +} + +/*******************************************************************************************************************//** + * Sets the wait states for MRAM. + **********************************************************************************************************************/ +__STATIC_INLINE void bsp_prv_set_wait_state_frequency (uint32_t mriclk_frequency_hz, uint32_t mrpclk_frequency_hz) +{ + uint32_t freq_mhz; + + /* Set Code MRAM wait states */ + if (mriclk_frequency_hz <= BSP_PRV_MRFREQ_MIN_HZ) + { + /* When under the minimum set MRCFREQ to 0 */ + freq_mhz = 0; + } + else + { + /* Round up the result when converting to MHz */ + freq_mhz = (mriclk_frequency_hz + BSP_PRV_HZ_PER_MHZ - 1) / BSP_PRV_HZ_PER_MHZ; + } + + /* Write MRCFREQ */ + while (freq_mhz != R_MRMS->MRCFREQ) + { + R_MRMS->MRCFREQ = BSP_PRV_MRCFREQ_KEY | freq_mhz; + } + + /* Set Extra MRAM wait states */ + if (mrpclk_frequency_hz <= BSP_PRV_MRFREQ_MIN_HZ) + { + /* When under the minimum set MREFREQ to 0 */ + freq_mhz = 0; + } + else + { + /* Round up the result when converting to MHz */ + freq_mhz = (mrpclk_frequency_hz + BSP_PRV_HZ_PER_MHZ - 1) / BSP_PRV_HZ_PER_MHZ; + } + + /* Write MREFREQ */ + while (freq_mhz != R_MRMS->MREFREQ) + { + R_MRMS->MREFREQ = BSP_PRV_MREFREQ_KEY | freq_mhz; + } +} + + #endif + +/*******************************************************************************************************************//** + * Applies system core clock source and divider changes. The MCU is expected to be in high speed mode during this + * configuration and the CGC registers are expected to be unlocked in PRCR. + * + * @param[in] clock Desired system clock + * @param[in] sckdivcr Value to set in SCKDIVCR register + * @param[in] sckdivcr2 Value to set in SCKDIVCR2 register + **********************************************************************************************************************/ +void bsp_prv_clock_set (uint32_t clock, uint32_t sckdivcr, uint16_t sckdivcr2) +{ + #if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED + + /* Set MSTP bits as required by the hardware manual. This is done first to ensure the 750 ns delay required after + * increasing any division ratio in SCKDIVCR is met. */ + uint32_t mstp_set_bitmask = bsp_prv_power_change_mstp_set(); + #endif + + uint32_t iclk_div = (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRV_SCKDIVCR_DIV_MASK; + uint32_t iclk_freq_hz_post_change = g_clock_freq[clock] / BSP_PRV_SCKDIVCR_DIV_VALUE(iclk_div); + #if BSP_FEATURE_CGC_HAS_CPUCLK + uint32_t cpuclk_div = sckdivcr2 & R_SYSTEM_SCKDIVCR2_CPUCK_Msk; + uint32_t clock_freq_hz_post_change = g_clock_freq[clock] / BSP_PRV_SCKDIVCR_DIV_VALUE(cpuclk_div); + #else + uint32_t clock_freq_hz_post_change = iclk_freq_hz_post_change; + #endif + + /* Adjust the MCU specific wait state right before the system clock is set, if the system clock frequency to be + * set is higher than before. */ + uint8_t new_rom_wait_state = bsp_clock_set_prechange(iclk_freq_hz_post_change); + + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + uint32_t mriclk_div = (sckdivcr2 & R_SYSTEM_SCKDIVCR2_MRICK_Msk) >> + R_SYSTEM_SCKDIVCR2_MRICK_Pos; + uint32_t mriclk_freq_hz_post_change = g_clock_freq[clock] / BSP_PRV_SCKDIVCR_DIV_VALUE(mriclk_div); + + uint32_t mrpclk_div = (sckdivcr & R_SYSTEM_SCKDIVCR_FCK_Msk) >> R_SYSTEM_SCKDIVCR_FCK_Pos; + uint32_t mrpclk_freq_hz_post_change = g_clock_freq[clock] / BSP_PRV_SCKDIVCR_DIV_VALUE(mrpclk_div); + + /* Clear the PFB before doing any clock changes according to Frequency Change Procedure. */ + bsp_prv_clear_pfb(); + #endif + + /* Switching to a faster source clock. */ + if (g_clock_freq[clock] >= g_clock_freq[R_SYSTEM->SCKSCR]) + { + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + + /* New source clock will be faster so set wait state frequency according to Frequency Change Procedure. */ + bsp_prv_set_wait_state_frequency(mriclk_freq_hz_post_change, mrpclk_freq_hz_post_change); + #endif + #if BSP_CFG_CLOCK_SETTLING_DELAY_ENABLE && 0 == BSP_MCU_GROUP_RA8_GEN2 + bool post_div_set_delay = false; + + if ((clock_freq_hz_post_change > SystemCoreClock) && + ((clock_freq_hz_post_change - SystemCoreClock) > BSP_MAX_CLOCK_CHANGE_THRESHOLD)) + { + /* If the requested ICLK divider is greater than or equal to the current ICLK divider, then writing to + * SCKDIVCR first will always satisfy the constraint: CPUCLK frequency >= ICLK frequency. */ + + if (iclk_div == cpuclk_div) + { + /* If dividers are equal, bump both down 1 notch. + * /1 and /2 are the only possible options. */ + uint32_t new_div = BSP_CLOCKS_SYS_CLOCK_DIV_2; + if (cpuclk_div == BSP_CLOCKS_SYS_CLOCK_DIV_1) + { + new_div = BSP_CLOCKS_SYS_CLOCK_DIV_4; + } + + R_SYSTEM->SCKDIVCR = (sckdivcr & ~(R_SYSTEM_SCKDIVCR_ICK_Msk)) | + (new_div << R_SYSTEM_SCKDIVCR_ICK_Pos); + R_SYSTEM->SCKDIVCR2 = (uint8_t) new_div; + } + else + { + R_SYSTEM->SCKDIVCR = sckdivcr; + if (cpuclk_div == BSP_CLOCKS_SYS_CLOCK_DIV_1) + { + /* Determine what the other dividers are using and stay aligned with that. */ + R_SYSTEM->SCKDIVCR2 = + (iclk_div & 0x8) ? BSP_CLOCKS_SYS_CLOCK_DIV_3 : BSP_CLOCKS_SYS_CLOCK_DIV_2; + } + else + { + /* If not /1, can just add 1 to it. */ + R_SYSTEM->SCKDIVCR2 = (uint8_t) sckdivcr2 + 1; + } + } + + /* Set the system source clock */ + R_SYSTEM->SCKSCR = (uint8_t) clock; + + /* Wait for settling delay. */ + SystemCoreClockUpdate(); + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + + /* Trigger delay after setting dividers */ + post_div_set_delay = true; + } + /* Continue and set clock to actual target speed. */ + #endif + + /* Set the clock dividers before switching to the new clock source. */ + bsp_prv_clock_dividers_set(sckdivcr, sckdivcr2); + + #if BSP_CFG_CLOCK_SETTLING_DELAY_ENABLE + #if BSP_MCU_GROUP_RA8_GEN2 + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + #else + if (post_div_set_delay) + { + /* Update the CMSIS core clock variable so that it reflects the new ICLK frequency. */ + SystemCoreClock = clock_freq_hz_post_change; + + /* Wait for settling delay. */ + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + } + else + #endif + #endif + { + /* Switch to the new clock source. */ + R_SYSTEM->SCKSCR = (uint8_t) clock; + } + } + /* Switching to a slower source clock. */ + else + { + #if BSP_CFG_CLOCK_SETTLING_DELAY_ENABLE + #if 0 == BSP_MCU_GROUP_RA8_GEN2 + if ((SystemCoreClock > clock_freq_hz_post_change) && + ((SystemCoreClock - clock_freq_hz_post_change) > BSP_MAX_CLOCK_CHANGE_THRESHOLD)) + { + uint32_t current_sckdivcr = R_SYSTEM->SCKDIVCR; + + /* Must first step CPUCLK down by factor of 2 or 3 if it is currently above threshold. */ + if (R_SYSTEM->SCKDIVCR2 == ((current_sckdivcr >> R_SYSTEM_SCKDIVCR_ICK_Pos) & 0xF)) + { + /* If ICLK and CPUCLK have same divider currently, move ICLK down 1 notch first. */ + uint32_t current_iclk_div = (current_sckdivcr >> R_SYSTEM_SCKDIVCR_ICK_Pos) & 0xF; + uint32_t new_div = (uint16_t) current_iclk_div + 1; + if (current_iclk_div == 0) + { + /* Align with already selected divider for PCLKA because it must have one > 1 already. */ + new_div = + (current_sckdivcr & + (0x8 << R_SYSTEM_SCKDIVCR_PCKA_Pos)) ? BSP_CLOCKS_SYS_CLOCK_DIV_3 : BSP_CLOCKS_SYS_CLOCK_DIV_2; + } + + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + R_SYSTEM->SCKDIVCR = (current_sckdivcr & ~(R_SYSTEM_SCKDIVCR_ICK_Msk)) | + (new_div << R_SYSTEM_SCKDIVCR_ICK_Pos); + R_SYSTEM->SCKDIVCR2 = (uint8_t) new_div; + + SystemCoreClockUpdate(); + } + } + #endif + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + #endif + R_SYSTEM->SCKSCR = (uint8_t) clock; + + /* Set the clock dividers after switching to the new clock source. */ + bsp_prv_clock_dividers_set(sckdivcr, sckdivcr2); + + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + + /* New source clock will be slower so set wait state frequency after changing clock frequency according to Frequency Change Procedure. */ + bsp_prv_set_wait_state_frequency(mriclk_freq_hz_post_change, mrpclk_freq_hz_post_change); + #endif + } + + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + bsp_prv_set_pfb(); + #endif + + /* Clock is now at requested frequency. */ + + /* Update the CMSIS core clock variable so that it reflects the new ICLK frequency. */ + SystemCoreClock = clock_freq_hz_post_change; + + #if BSP_TZ_SECURE_BUILD + if (NULL != g_bsp_clock_update_callback) + { + /* Set callback args. */ + bsp_clock_update_callback_args_t callback_args = + { + .pll_freq = g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] + }; + + /* Call the callback. */ + r_bsp_clock_update_callback_call(g_bsp_clock_update_callback, &callback_args); + } + #endif + + /* Adjust the MCU specific wait state soon after the system clock is set, if the system clock frequency to be + * set is lower than previous. */ + bsp_clock_set_postchange(iclk_freq_hz_post_change, new_rom_wait_state); + + #if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED + + /* Clear MSTP bits as required by the hardware manual. This is done last to ensure the 250 ns delay required after + * decreasing any division ratio in SCKDIVCR is met. */ + bsp_prv_power_change_mstp_clear(mstp_set_bitmask); + #endif +} + + #if BSP_CFG_SLEEP_MODE_DELAY_ENABLE || BSP_CFG_RTOS_SLEEP_MODE_DELAY_ENABLE + +bool bsp_prv_clock_prepare_pre_sleep (void) +{ + /* Must wait before entering or exiting sleep modes. + * See "Notes on transitioning to or canceling low power state" in the LPM section of the relevant hardware manual */ + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + + /* Need to slow CPUCLK down before sleeping if it is above 240MHz. */ + bool cpuclk_slowed = false; + if (SystemCoreClock > BSP_MAX_CLOCK_CHANGE_THRESHOLD) + { + #if BSP_MCU_GROUP_RA8_GEN2 + g_pre_sleep_sckdivcr2 = R_SYSTEM->SCKDIVCR2; + uint32_t iclk_div = (R_SYSTEM->SCKDIVCR & R_SYSTEM_SCKDIVCR_ICK_Msk) >> R_SYSTEM_SCKDIVCR_ICK_Pos; + + /* Drop all dividers which could be higher than ICLK to match ICLK. */ + R_SYSTEM->SCKDIVCR2 = + (uint16_t) ((iclk_div << R_SYSTEM_SCKDIVCR2_CPUCK_Pos) | (iclk_div << R_SYSTEM_SCKDIVCR2_CPUCK1_Pos) | + (iclk_div << R_SYSTEM_SCKDIVCR2_NPUCK_Pos) | (iclk_div << R_SYSTEM_SCKDIVCR2_MRICK_Pos)); + #else + + /* Reduce speed of CPUCLK to /2 or /3 of current, select which ones based on what ICLK divider is. */ + R_SYSTEM->SCKDIVCR2 = + (R_SYSTEM->SCKDIVCR & + (0x8 << R_SYSTEM_SCKDIVCR_ICK_Pos)) ? BSP_CLOCKS_SYS_CLOCK_DIV_3 : BSP_CLOCKS_SYS_CLOCK_DIV_2; + #endif + cpuclk_slowed = true; + SystemCoreClockUpdate(); + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + } + + return cpuclk_slowed; +} + +void bsp_prv_clock_prepare_post_sleep (bool cpuclk_slowed) +{ + /* Set CPUCLK back to original speed here if it was slowed down before sleeping (dropped to below 240MHz) + * Add delays as described in "Notes on transitioning to or canceling low power state" in the LPM section of the relevant hardware manual */ + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + if (cpuclk_slowed) + { + #if BSP_MCU_GROUP_RA8_GEN2 + R_SYSTEM->SCKDIVCR2 = g_pre_sleep_sckdivcr2; + #else + + /* Set divider of CPUCLK back to /1. This is the only possible value for it to have been over 240MHz before sleeping. */ + R_SYSTEM->SCKDIVCR2 = BSP_CLOCKS_SYS_CLOCK_DIV_1; + #endif + SystemCoreClockUpdate(); + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + } +} + + #endif + +#else + +/*******************************************************************************************************************//** + * Get system core clock source. + * + **********************************************************************************************************************/ +uint32_t bsp_prv_clock_source_get (void) +{ + /* + * | System clock source | FOCOSCR.CKSEL | FMAINSCR.CKSEL | FSUBSCR.CKSEL | ICLKSCR.CKSEL | + * | ------------------- | ------------- | -------------- | ------------- | ------------- | + * | HOCO | 0U | 0U | x | 0U | + * | MOCO | 1U | 0U | x | 0U | + * | MOSC | x | 1U | x | 0U | + * | LOCO | x | x | 1U | 1U | + * | SOSC | x | x | 0U | 1U | + * + * */ + #if BSP_FEATURE_CGC_HAS_MOSC + uint32_t clock = BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC; + #else + uint32_t clock = BSP_CLOCKS_SOURCE_CLOCK_HOCO; + #endif + + if (BSP_CLOCKS_SOURCE_CLOCK_FSUB == R_SYSTEM->ICLKSCR_b.CKST) + { + #if BSP_FEATURE_CGC_HAS_SOSC + clock = R_SYSTEM->FSUBSCR ? BSP_CLOCKS_SOURCE_CLOCK_LOCO : BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK; + #else + clock = BSP_CLOCKS_SOURCE_CLOCK_LOCO; + #endif + } + + #if BSP_FEATURE_CGC_HAS_MOCO + else if (BSP_CLOCKS_FMAIN_SOURCE_CLOCK_FOCO == R_SYSTEM->FMAINSCR_b.CKST) + { + clock = R_SYSTEM->FOCOSCR_b.CKST ? BSP_CLOCKS_SOURCE_CLOCK_MOCO : BSP_CLOCKS_SOURCE_CLOCK_HOCO; + } + #endif + else + { + /* Do nothing. */ + } + + return clock; +} + +/*******************************************************************************************************************//** + * Applies system core clock source and divider changes. The MCU is expected to be in high speed mode during this + * configuration and the CGC registers are expected to be unlocked in PRCR. + * + * @param[in] clock Desired system clock + * @param[in] hocodiv The new HOCODIV setting. + * @param[in] mocodiv The new MOCODIV setting. + * @param[in] moscdiv The new MOSCDIV setting. + **********************************************************************************************************************/ +void bsp_prv_clock_set (uint32_t clock, uint8_t hocodiv, uint8_t mocodiv, uint8_t moscdiv) +{ + /* + * | System clock source | FOCOSCR.CKSEL | FMAINSCR.CKSEL | FSUBSCR.CKSEL | ICLKSCR.CKSEL | + * | ------------------- | ------------- | -------------- | ------------- | ------------- | + * | HOCO | 0U | 0U | x | 0U | + * | MOCO | 1U | 0U | x | 0U | + * | MOSC | x | 1U | x | 0U | + * | LOCO | x | x | 1U | 1U | + * | SOSC | x | x | 0U | 1U | + * + * */ + R_SYSTEM->ICLKSCR_b.CKSEL = BSP_CLOCKS_SOURCE_CLOCK_FMAIN; + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->ICLKSCR_b.CKST, BSP_CLOCKS_SOURCE_CLOCK_FMAIN); + + #if BSP_FEATURE_CGC_HAS_MOCO + if ((BSP_CLOCKS_SOURCE_CLOCK_HOCO == clock) || (BSP_CLOCKS_SOURCE_CLOCK_MOCO == clock)) + { + R_SYSTEM->FMAINSCR_b.CKSEL = BSP_CLOCKS_FMAIN_SOURCE_CLOCK_FOCO; + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->FMAINSCR_b.CKST, BSP_CLOCKS_FMAIN_SOURCE_CLOCK_FOCO); + + if (BSP_CLOCKS_SOURCE_CLOCK_HOCO == clock) + { + R_SYSTEM->FOCOSCR_b.CKSEL = BSP_CLOCKS_FOCO_SOURCE_CLOCK_HOCO; + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->FOCOSCR_b.CKST, BSP_CLOCKS_FOCO_SOURCE_CLOCK_HOCO); + + /* Due to register access restrictions, only set the HOCODIV when system clock source is HOCO. * + * See in hardware manual: Clock Generation Circuit > Usage Notes > Register Access */ + R_SYSTEM->HOCODIV = hocodiv; + } + else + { + R_SYSTEM->FOCOSCR_b.CKSEL = BSP_CLOCKS_FOCO_SOURCE_CLOCK_MOCO; + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->FOCOSCR_b.CKST, BSP_CLOCKS_FOCO_SOURCE_CLOCK_MOCO); + } + } + + #else + if (BSP_CLOCKS_SOURCE_CLOCK_HOCO == clock) + { + /* Due to register access restrictions, only set the HOCODIV when system clock source is HOCO. * + * See in hardware manual: Clock Generation Circuit > Usage Notes > Register Access */ + R_SYSTEM->HOCODIV = hocodiv; + } + #endif + + #if BSP_CLOCK_CFG_MAIN_OSC_POPULATED + else if (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == clock) + { + R_SYSTEM->FMAINSCR_b.CKSEL = BSP_CLOCKS_FMAIN_SOURCE_CLOCK_MAIN_OSC; + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->FMAINSCR_b.CKST, BSP_CLOCKS_FMAIN_SOURCE_CLOCK_MAIN_OSC); + } + #endif + else + { + if (BSP_CLOCKS_SOURCE_CLOCK_LOCO == clock) + { + R_SYSTEM->FSUBSCR = BSP_CLOCKS_FSUB_SOURCE_CLOCK_LOCO; + } + + #if BSP_CLOCK_CFG_SUBCLOCK_POPULATED + else + { + R_SYSTEM->FSUBSCR = BSP_CLOCKS_FSUB_SOURCE_CLOCK_SUBCLOCK; + } + #endif + + R_SYSTEM->ICLKSCR_b.CKSEL = BSP_CLOCKS_SOURCE_CLOCK_FSUB; + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->ICLKSCR_b.CKST, BSP_CLOCKS_SOURCE_CLOCK_FSUB); + } + + #if BSP_FEATURE_CGC_HAS_MOCO + R_SYSTEM->MOCODIV = mocodiv; + #else + FSP_PARAMETER_NOT_USED(mocodiv); + #endif + + #if BSP_FEATURE_CGC_HAS_MOSC + R_SYSTEM->MOSCDIV = moscdiv; + #else + FSP_PARAMETER_NOT_USED(moscdiv); + #endif + + /* Clock is now at requested frequency. Update the CMSIS core clock variable so that it reflects the new ICLK frequency.*/ + SystemCoreClockUpdate(); +} + +/*******************************************************************************************************************//** + * Setting for CLKOUT/CLKOUT1 + **********************************************************************************************************************/ +static void bsp_prv_clkout_set (void) +{ + #if BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_CLOCK_DISABLED + #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + R_PCLBUZ->CKS[0] = 0U; + #endif + #else + uint8_t cks0 = (BSP_CFG_CLKOUT_DIV << R_PCLBUZ_CKS_CCS_Pos); + #if (BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) || \ + (BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK) + cks0 |= (BSP_CLOCKS_CLKOUT_SOURCE_CLOCK_FSUB << R_PCLBUZ_CKS_CSEL_Pos); + #else + cks0 |= (BSP_CLOCKS_CLKOUT_SOURCE_CLOCK_FMAIN << R_PCLBUZ_CKS_CSEL_Pos); + #endif + R_PCLBUZ->CKS[0] = cks0; + R_PCLBUZ->CKS[0] |= (1U << R_PCLBUZ_CKS_PCLOE_Pos); + #endif + + #if defined(BSP_CFG_CLKOUT1_SOURCE) + #if BSP_CFG_CLKOUT1_SOURCE == BSP_CLOCKS_CLOCK_DISABLED + #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + R_PCLBUZ->CKS[1] = 0U; + #endif + #else + uint8_t cks1 = (BSP_CFG_CLKOUT1_DIV << R_PCLBUZ_CKS_CCS_Pos); + #if (BSP_CFG_CLKOUT1_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) || \ + (BSP_CFG_CLKOUT1_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK) + cks1 |= (BSP_CLOCKS_CLKOUT_SOURCE_CLOCK_FSUB << R_PCLBUZ_CKS_CSEL_Pos); + #else + cks1 |= (BSP_CLOCKS_CLKOUT_SOURCE_CLOCK_FMAIN << R_PCLBUZ_CKS_CSEL_Pos); + #endif + R_PCLBUZ->CKS[1] = cks1; + R_PCLBUZ->CKS[1] |= (1U << R_PCLBUZ_CKS_PCLOE_Pos); + #endif + #endif +} + +#endif + +#if !BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET && !BSP_FEATURE_CGC_REGISTER_SET_B +static void bsp_prv_clock_set_hard_reset (void) +{ + /* Wait states in SRAMWTSC are set after hard reset. No change required here. */ + + /* Calculate the wait states for ROM */ + #if BSP_FEATURE_CGC_HAS_FLWT + #if BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_SYSC_CLOCK_FREQ_ONE_ROM_WAITS + + /* Do nothing. Default setting in FLWT is correct. */ + #elif BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_SYSC_CLOCK_FREQ_TWO_ROM_WAITS || \ + BSP_FEATURE_SYSC_CLOCK_FREQ_TWO_ROM_WAITS == 0 + R_FCACHE->FLWT = BSP_PRV_ROM_ONE_WAIT_CYCLES; + #elif 0 == BSP_FEATURE_SYSC_CLOCK_FREQ_THREE_ROM_WAITS || \ + (BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_SYSC_CLOCK_FREQ_THREE_ROM_WAITS) + R_FCACHE->FLWT = BSP_PRV_ROM_TWO_WAIT_CYCLES; + #elif 0 == BSP_FEATURE_SYSC_CLOCK_FREQ_FOUR_ROM_WAITS || \ + (BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_SYSC_CLOCK_FREQ_FOUR_ROM_WAITS) + R_FCACHE->FLWT = BSP_PRV_ROM_THREE_WAIT_CYCLES; + #elif 0 == BSP_FEATURE_SYSC_CLOCK_FREQ_FIVE_ROM_WAITS || \ + (BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_SYSC_CLOCK_FREQ_FIVE_ROM_WAITS) + R_FCACHE->FLWT = BSP_PRV_ROM_FOUR_WAIT_CYCLES; + #else + R_FCACHE->FLWT = BSP_PRV_ROM_FIVE_WAIT_CYCLES; + #endif + #endif + + #if BSP_FEATURE_CGC_HAS_MEMWAIT && !BSP_PRV_CLOCK_SUPPLY_TYPE_B + #if BSP_STARTUP_ICLK_HZ > BSP_PRV_MEMWAIT_MAX_ZERO_WAIT_FREQ + #if ((BSP_STARTUP_ICLK_HZ > BSP_PRV_MEMWAIT_MAX_ONE_WAIT_FREQ) && \ + (BSP_PRV_MEMWAIT_TWO_WAIT_CYCLES & R_SYSTEM_MEMWAIT_MEMWAIT_Msk)) + + /* The MCU must be in high speed mode to set wait states to 2. High speed mode is the default out of reset. */ + R_SYSTEM->MEMWAIT = BSP_PRV_MEMWAIT_TWO_WAIT_CYCLES; + #else + R_SYSTEM->MEMWAIT = BSP_PRV_MEMWAIT_ONE_WAIT_CYCLES; + #endif + #endif + #endif + + #if BSP_FEATURE_CGC_HAS_FLDWAITR && !BSP_PRV_CLOCK_SUPPLY_TYPE_B + #if BSP_STARTUP_ICLK_HZ > BSP_PRV_FLDWAITR_MAX_ONE_WAIT_FREQ + + /* The MCU must be in high speed mode to set wait states to 2. High speed mode is the default out of reset. */ + BSP_PRV_FLDWAITR_REG_ACCESS = BSP_PRV_FLDWAITR_TWO_WAIT_CYCLES; + #endif + #endif + + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + + /* Clear the PFB before doing any clock changes according to Frequency Change Procedure. */ + bsp_prv_clear_pfb(); + #endif + + /* In order to avoid a system clock (momentarily) higher than expected, the order of switching the clock and + * dividers must be so that the frequency of the clock goes lower, instead of higher, before being correct. */ + + /* MOCO is the source clock after reset. If the new source clock is faster than the current source clock, + * then set the clock dividers before switching to the new source clock. */ + #if BSP_MOCO_FREQ_HZ <= BSP_STARTUP_SOURCE_CLOCK_HZ + #if BSP_FEATURE_CGC_HAS_CPUCLK + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + + /* New source clock will be faster so set wait state frequency before changing clock frequency + * according to Frequency Change Procedure. */ + bsp_prv_set_wait_state_frequency(BSP_STARTUP_MRICLK_HZ, BSP_STARTUP_FCLK_HZ); + #endif + #if BSP_CFG_CLOCK_SETTLING_DELAY_ENABLE && (BSP_STARTUP_CPUCLK_HZ >= BSP_MAX_CLOCK_CHANGE_THRESHOLD) && \ + (0 == BSP_MCU_GROUP_RA8_GEN2) + + /* If the requested ICLK divider is greater than or equal to the current ICLK divider, then writing to + * SCKDIVCR first will always satisfy the constraint: CPUCLK frequency >= ICLK frequency. */ + #if BSP_CFG_ICLK_DIV == BSP_CFG_CPUCLK_DIV + + /* If dividers are equal, bump both down 1 notch. + * /1 and /2 are the only possible options. */ + #if BSP_CFG_CPUCLK_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1 + R_SYSTEM->SCKDIVCR = (BSP_PRV_STARTUP_SCKDIVCR & ~(R_SYSTEM_SCKDIVCR_ICK_Msk)) | + (BSP_CLOCKS_SYS_CLOCK_DIV_2 << R_SYSTEM_SCKDIVCR_ICK_Pos); + R_SYSTEM->SCKDIVCR2 = BSP_CLOCKS_SYS_CLOCK_DIV_2; + #else + R_SYSTEM->SCKDIVCR = (BSP_PRV_STARTUP_SCKDIVCR & ~(R_SYSTEM_SCKDIVCR_ICK_Msk)) | + (BSP_CLOCKS_SYS_CLOCK_DIV_4 << R_SYSTEM_SCKDIVCR_ICK_Pos); + R_SYSTEM->SCKDIVCR2 = BSP_CLOCKS_SYS_CLOCK_DIV_4; + #endif + #else + R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR; + + #if BSP_CFG_CPUCLK_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1 + + /* Determine what the other dividers are using and stay aligned with that. */ + R_SYSTEM->SCKDIVCR2 = (BSP_CFG_ICLK_DIV & 0x8) ? BSP_CLOCKS_SYS_CLOCK_DIV_3 : BSP_CLOCKS_SYS_CLOCK_DIV_2; + #else + + /* If not /1, can just add 1 to it. */ + R_SYSTEM->SCKDIVCR2 = BSP_PRV_STARTUP_SCKDIVCR2 + 1; + #endif + #endif + + /* Set the system source clock */ + R_SYSTEM->SCKSCR = BSP_CFG_CLOCK_SOURCE; + + /* Wait for settling delay. */ + SystemCoreClockUpdate(); + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + + /* Continue and set clock to actual target speed. */ + R_SYSTEM->SCKDIVCR2 = BSP_PRV_STARTUP_SCKDIVCR2; + R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR; + + /* Wait for settling delay. */ + SystemCoreClockUpdate(); + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + #else + #if BSP_PRV_ICLK_DIV_VALUE >= BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_FEATURE_CGC_ICLK_DIV_RESET) + + /* If the requested ICLK divider is greater than or equal to the current ICLK divider, then writing to + * SCKDIVCR first will always satisfy the constraint: CPUCLK frequency >= ICLK frequency. */ + R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR; + R_SYSTEM->SCKDIVCR2 = BSP_PRV_STARTUP_SCKDIVCR2; + #else + + /* If the requested ICLK divider is less than the current ICLK divider, then writing to SCKDIVCR2 first + * will always satisfy the constraint: CPUCLK frequency >= ICLK frequency. */ + R_SYSTEM->SCKDIVCR2 = BSP_PRV_STARTUP_SCKDIVCR2; + R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR; + #endif + #endif + #else + R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR; + #endif + #endif + + /* Set the system source clock */ + R_SYSTEM->SCKSCR = BSP_CFG_CLOCK_SOURCE; + + #if BSP_MCU_GROUP_RA8_GEN2 && BSP_CFG_CLOCK_SETTLING_DELAY_ENABLE && \ + (BSP_CLOCKS_SOURCE_CLOCK_PLL1P == BSP_CFG_CLOCK_SOURCE) + + /* Wait for settling delay. */ + SystemCoreClockUpdate(); + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + #endif + + /* MOCO is the source clock after reset. If the new source clock is slower than the current source clock, + * then set the clock dividers after switching to the new source clock. */ + #if BSP_MOCO_FREQ_HZ > BSP_STARTUP_SOURCE_CLOCK_HZ + #if BSP_FEATURE_CGC_HAS_CPUCLK + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + + /* New source clock will be slower so set wait state frequency after changing clock frequency according to Frequency Change Procedure. */ + bsp_prv_set_wait_state_frequency(BSP_STARTUP_MRICLK_HZ, BSP_STARTUP_FCLK_HZ); + #endif + #if BSP_PRV_ICLK_DIV_VALUE >= BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_FEATURE_CGC_ICLK_DIV_RESET) + + /* If the requested ICLK divider is greater than or equal to the current ICLK divider, then writing to + * SCKDIVCR first will always satisfy the constraint: CPUCLK frequency >= ICLK frequency. */ + R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR; + R_SYSTEM->SCKDIVCR2 = BSP_PRV_STARTUP_SCKDIVCR2; + #else + + /* If the requested ICLK divider is less than the current ICLK divider, then writing to SCKDIVCR2 first + * will always satisfy the constraint: CPUCLK frequency >= ICLK frequency. */ + R_SYSTEM->SCKDIVCR2 = BSP_PRV_STARTUP_SCKDIVCR2; + R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR; + #endif + #else + R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR; + #endif + #endif + + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + bsp_prv_set_pfb(); + #endif + + /* Update the CMSIS core clock variable so that it reflects the new ICLK frequency. */ + SystemCoreClockUpdate(); + + /* Clocks are now at requested frequencies. */ + + /* Adjust the MCU specific wait state soon after the system clock is set, if the system clock frequency to be + * set is lower than previous. */ + #if BSP_FEATURE_CGC_HAS_SRAMWTSC + #if BSP_FEATURE_CGC_HAS_SRAMPRCR2 == 1 + R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_UNLOCK; + R_SRAM->SRAMWTSC = BSP_PRV_SRAM_WAIT_CYCLES; + R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_LOCK; + #else + + /* Devices with TrustZone version 2 have a separate non-secure register for SRAM register protection. */ + #if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + R_SRAM->SRAMPRCR_NS = BSP_PRV_SRAM_UNLOCK; + #else + R_SRAM->SRAMPRCR = BSP_PRV_SRAM_UNLOCK; + #endif + + /* Execute data memory barrier before and after setting the wait states, See "Note of write to SRAMCR0, SRAMCR1 and SRAMECCRGN0 registers" + * in the SRAM section of the relevant hardware manual */ + __DMB(); + R_SRAM->SRAMWTSC = BSP_PRV_SRAM_WAIT_CYCLES; + __DMB(); + + /* Devices with TrustZone version 2 have a separate non-secure register for SRAM register protection. */ + #if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + R_SRAM->SRAMPRCR_NS = BSP_PRV_SRAM_LOCK; + #else + R_SRAM->SRAMPRCR = BSP_PRV_SRAM_LOCK; + #endif + #endif + #endif + + /* ROM wait states are 0 by default. No change required here. */ +} + +#endif + +/*******************************************************************************************************************//** + * Initializes variable to store system clock frequencies. + **********************************************************************************************************************/ +#if BSP_TZ_NONSECURE_BUILD || BSP_SECONDARY_CORE_BUILD +void bsp_clock_freq_var_init (void) +#else +static void bsp_clock_freq_var_init (void) +#endif +{ + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_HOCO] = BSP_HOCO_HZ; + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_MOCO] = BSP_MOCO_FREQ_HZ; + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_LOCO] = BSP_LOCO_FREQ_HZ; +#if BSP_CLOCK_CFG_MAIN_OSC_POPULATED + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC] = BSP_CFG_XTAL_HZ; +#else + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC] = 0U; +#endif +#if BSP_CLOCK_CFG_SUBCLOCK_POPULATED + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK] = BSP_SUBCLOCK_FREQ_HZ; +#else + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK] = 0U; +#endif +#if BSP_PRV_PLL_SUPPORTED + #if BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE + #if (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) && (6U != BSP_FEATURE_CGC_PLLCCR_TYPE) + + /* The PLL Is the startup clock. */ + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = BSP_STARTUP_SOURCE_CLOCK_HZ; + #else + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = BSP_CFG_PLL1P_FREQUENCY_HZ; + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL1Q] = BSP_CFG_PLL1Q_FREQUENCY_HZ; + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL1R] = BSP_CFG_PLL1R_FREQUENCY_HZ; + #endif + #else + + /* The PLL value will be calculated at initialization. */ + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = BSP_CFG_XTAL_HZ; + #endif +#endif + +#if BSP_TZ_NONSECURE_BUILD && BSP_CFG_CLOCKS_SECURE == 1 + + /* If the CGC is secure and this is a non secure project, register a callback for getting clock settings. */ + R_BSP_ClockUpdateCallbackSet(g_bsp_clock_update_callback, &g_callback_memory); +#endif + + /* Update PLL Clock Frequency based on BSP Configuration. */ +#if BSP_PRV_PLL_SUPPORTED && BSP_CLOCKS_SOURCE_CLOCK_PLL != BSP_CFG_CLOCK_SOURCE && BSP_PRV_PLL_USED + #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (5U == BSP_FEATURE_CGC_PLLCCR_TYPE) + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = + ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U) / + (BSP_CFG_PLL_DIV + 1U); + #elif (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = BSP_CFG_PLL1P_FREQUENCY_HZ; + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL1Q] = BSP_CFG_PLL1Q_FREQUENCY_HZ; + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL1R] = BSP_CFG_PLL1R_FREQUENCY_HZ; + #elif (4U == BSP_FEATURE_CGC_PLLCCR_TYPE) + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = (g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> + 1U; + #else + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = + ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U) >> + BSP_CFG_PLL_DIV; + #endif +#endif + + /* Update PLL2 Clock Frequency based on BSP Configuration. */ +#if BSP_PRV_PLL2_SUPPORTED && BSP_PRV_PLL2_USED + #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL2] = + ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) / + (BSP_CFG_PLL2_DIV + 1U); + #elif (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL2] = BSP_CFG_PLL2P_FREQUENCY_HZ; + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL2Q] = BSP_CFG_PLL2Q_FREQUENCY_HZ; + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL2R] = BSP_CFG_PLL2R_FREQUENCY_HZ; + #else + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL2] = + ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) >> BSP_CFG_PLL2_DIV; + #endif +#endif + + /* The SystemCoreClock needs to be updated before calling R_BSP_SoftwareDelay. */ + SystemCoreClockUpdate(); +} + +#if !BSP_FEATURE_CGC_REGISTER_SET_B + #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + +/* + * If the clock registers are not guaranteed to be set to their value after reset (Ie. the application is executing after a bootloader), + * then the current state of the registers must be taken into consideration before writing the clock configuration. + * + * The HOCO must be stopped in the following situations: + * - The application configures the HOCO to be stopped. + * - The application enables the FLL, but the HOCO is already running. In order to enable the FLL, the HOCO must be stopped. + * The PLL must be stopped in the following situations: + * - The application configures the PLL to be stopped. + * - The application configures settings that are different than the current settings, but the PLL is already running. In order to + * write new PLL settings, the PLL must be stopped. + * - The HOCO is the PLL source clock and the HOCO is being stopped. + * The PLL2 must be stopped in the following situations: + * - The application configures the PLL2 to be stopped. + * - The application configures settings that are different than the current settings, but the PLL2 is already running. In order to + * write new PLL2 settings, the PLL2 must be stopped. + * - The HOCO is the PLL2 source clock and the HOCO is being stopped. + * + * If the HOCO or PLL are being used as the system clock source and they need to be stopped, then the system clock source needs to be switched + * to the default system clock source before the current system clock source is disabled. + */ +void bsp_soft_reset_prepare (void) +{ + bool stop_hoco = false; + #if BSP_PRV_PLL_SUPPORTED + bool stop_pll = false; + #endif + #if BSP_PRV_PLL2_SUPPORTED + bool stop_pll2 = false; + #endif + + #if BSP_PRV_HOCO_USE_FLL || !BSP_PRV_HOCO_USED + #if BSP_PRV_HOCO_USE_FLL + + /* Determine if the FLL needs to be enabled. */ + bool enable_fll = (0 == R_SYSTEM->FLLCR1 && BSP_PRV_HOCO_USE_FLL); + #else + bool enable_fll = false; + #endif + + /* If the HOCO is already enabled and either the FLL needs to be enabled or the HOCO is not used, then stop the HOCO. */ + if ((0 == R_SYSTEM->HOCOCR) && (enable_fll || !BSP_PRV_HOCO_USED)) + { + stop_hoco = true; + } + #endif + + #if BSP_PRV_PLL_SUPPORTED + if (0 == R_SYSTEM->PLLCR) + { + /* + * If any of the following conditions are true, then the PLL needs to be stopped: + * - The PLL is not used + * - The PLL settings need to be changed + * - The HOCO is selected as the PLL clock source and the HOCO needs to be stopped + * - Note that PLL type 2 does not support running off of the HOCO + */ + #if BSP_PRV_PLL_USED + #if (3 == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6 == BSP_FEATURE_CGC_PLLCCR_TYPE) + if ((BSP_PRV_PLLCCR != R_SYSTEM->PLLCCR) || (BSP_PRV_PLLCCR2 != R_SYSTEM->PLLCCR2) || + (stop_hoco && (1 == R_SYSTEM->PLLCCR_b.PLSRCSEL))) + #elif 2 == BSP_FEATURE_CGC_PLLCCR_TYPE + if (BSP_PRV_PLLCCR != R_SYSTEM->PLLCCR2) + #else + if ((BSP_PRV_PLLCCR != R_SYSTEM->PLLCCR) || (stop_hoco && (1 == R_SYSTEM->PLLCCR_b.PLSRCSEL))) + #endif + #endif + { + stop_pll = true; + } + } + #endif + + #if BSP_PRV_PLL2_SUPPORTED + if (0 == R_SYSTEM->PLL2CR) + { + /* + * If any of the following conditions are true, then the PLL2 needs to be stopped: + * - The PLL2 is not used + * - The PLL2 settings need to be changed + * - The HOCO is selected as the PLL2 clock source and the HOCO needs to be stopped + * - Note that PLL type 2 does not support running off of the HOCO + */ + #if BSP_PRV_PLL2_USED + #if (3 == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6 == BSP_FEATURE_CGC_PLLCCR_TYPE) + if ((BSP_PRV_PLL2CCR != R_SYSTEM->PLL2CCR) || (BSP_PRV_PLL2CCR2 != R_SYSTEM->PLL2CCR2) || + (stop_hoco && (1 == R_SYSTEM->PLL2CCR_b.PL2SRCSEL))) + #else + if ((BSP_PRV_PLL2CCR != R_SYSTEM->PLL2CCR) || (stop_hoco && (1 == R_SYSTEM->PLL2CCR_b.PL2SRCSEL))) + #endif + #endif + { + stop_pll2 = true; + } + } + #endif + + uint8_t sckscr = R_SYSTEM->SCKSCR; + + /* If the System Clock source needs to be stopped, then switch to the MOCO. */ + #if BSP_PRV_PLL_SUPPORTED + if ((stop_hoco && (BSP_CLOCKS_SOURCE_CLOCK_HOCO == sckscr)) || + (stop_pll && (BSP_CLOCKS_SOURCE_CLOCK_PLL == sckscr))) + #else + if (stop_hoco && (BSP_CLOCKS_SOURCE_CLOCK_HOCO == sckscr)) + #endif + { + bsp_prv_clock_set(BSP_FEATURE_CGC_STARTUP_SCKSCR, + BSP_FEATURE_CGC_STARTUP_SCKDIVCR, + BSP_FEATURE_CGC_STARTUP_SCKDIVCR2); + } + + /* Disable the oscillators so that the application can write the new clock configuration. */ + + #if BSP_PRV_PLL_SUPPORTED + if (stop_pll) + { + R_SYSTEM->PLLCR = 1; + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.PLLSF, 0); + } + #endif + + #if BSP_PRV_PLL2_SUPPORTED + if (stop_pll2) + { + R_SYSTEM->PLL2CR = 1; + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.PLL2SF, 0); + } + #endif + + if (stop_hoco) + { + R_SYSTEM->HOCOCR = 1; + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.HOCOSF, 0); + } +} + + #endif +#else + +/*******************************************************************************************************************//** + * Initializes CMC and OSMC registers according to the BSP configuration. + **********************************************************************************************************************/ +void bsp_prv_cmc_init (void) +{ + #if BSP_FEATURE_CGC_HAS_MOSC || BSP_FEATURE_CGC_HAS_SOSC + + /* The CMC register can be written only once after release from the reset state. If clock registers not reset + * values during startup, assume CMC register has already been set appropriately. */ + uint8_t cmc_reg = 0x00U; + + /* Set main clock oscillator drive capability */ + #if BSP_CLOCK_CFG_MAIN_OSC_POPULATED + cmc_reg |= BSP_PRV_CMC_MOSC; + #endif + + /* Set sub-clock oscillator drive capability and pin switching */ + #if BSP_CLOCK_CFG_SUBCLOCK_POPULATED + cmc_reg |= BSP_PRV_CMC_SOSC; + #endif + + R_SYSTEM->CMC = cmc_reg; + #endif + + #if (BSP_CFG_FSXP_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + uint8_t osmc = R_SYSTEM->OSMC; + + if (BSP_PRV_OSMC != osmc) + { + #if BSP_PERIPHERAL_RTC_C_PRESENT || BSP_PERIPHERAL_RTC_PRESENT + + /* Stop RTC counter operation to update the OSMC register. */ + BSP_MSTP_REG_FSP_IP_RTC(0) &= ~BSP_MSTP_BIT_FSP_IP_RTC(0); + FSP_REGISTER_READ(BSP_MSTP_REG_FSP_IP_RTC(0)); + R_RTC_C->RTCC0_b.RTCE = 0U; + BSP_MSTP_REG_FSP_IP_RTC(0) |= BSP_MSTP_BIT_FSP_IP_RTC(0); + FSP_REGISTER_READ(BSP_MSTP_REG_FSP_IP_RTC(0)); + #endif + + #if BSP_CLOCK_CFG_SUBCLOCK_POPULATED + if (0U == osmc) + { + /* Current Subsystem Clock (FSXP) source is SOSC. */ + if (0U == R_SYSTEM->SOSCCR) + { + /* Stop the Sub-Clock Oscillator to update the OSMC register. */ + R_SYSTEM->SOSCCR = 1U; + + /* Allow a stop interval of at least 5 SOSC clock cycles before restarting Sub-Clock Oscillator. */ + R_BSP_SoftwareDelay(BSP_PRV_SUBCLOCK_STOP_INTERVAL_US, BSP_DELAY_UNITS_MICROSECONDS); + + /* When changing the value of the SOSTP bit, only execute subsequent + * instructions after reading the bit to check that the value is updated. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOSCCR, 1U); + } + } + #endif + + R_SYSTEM->OSMC = BSP_PRV_OSMC; + } + #endif +} + +/*********************************************************************************************************************** + * Changes the operating speed in FLMODE. Assumes the LPM registers are unlocked in PRCR. + * + * @param[in] operating_mode Desired operating mode, must be one of the BSP_PRV_OPERATING_MODE_* macros, cannot be + * BSP_PRV_OPERATING_MODE_SUBOSC_SPEED + **********************************************************************************************************************/ +static void bsp_prv_operating_mode_flmode_set (uint8_t operating_mode) +{ + if (operating_mode != R_FACI_LP->FLMODE_b.MODE) + { + /* Enable FLMWRP.FLMWEN bit to before rewrite to FLMODE register */ + R_FACI_LP->FLMWRP_b.FLMWEN = 0x1U; + + if ((BSP_PRV_OPERATING_MODE_MIDDLE_SPEED != operating_mode) && + (BSP_PRV_OPERATING_MODE_MIDDLE_SPEED != R_FACI_LP->FLMODE_b.MODE)) + { + /* Set flash operating mode to middle-speed mode first */ + R_FACI_LP->FLMODE = (uint8_t) (BSP_PRV_OPERATING_MODE_MIDDLE_SPEED << R_FACI_LP_FLMODE_MODE_Pos); + } + + /* Set flash operating mode */ + R_FACI_LP->FLMODE = (uint8_t) (operating_mode << R_FACI_LP_FLMODE_MODE_Pos); + + /* Disable FLMWRP.FLMWEN bit to after rewrite to FLMODE register */ + R_FACI_LP->FLMWRP_b.FLMWEN = 0x0U; + } +} + +#endif + +/*******************************************************************************************************************//** + * Initializes system clocks. Makes no assumptions about current register settings. + **********************************************************************************************************************/ +void bsp_clock_init (void) +{ + /* Unlock CGC and LPM protection registers. */ +#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + R_SYSTEM->PRCR_NS = (uint16_t) BSP_PRV_PRCR_UNLOCK; +#else + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_UNLOCK; +#endif + +#if BSP_FEATURE_FLASH_CACHE || defined(R_CACHE) + #if !BSP_CFG_USE_LOW_VOLTAGE_MODE && BSP_FEATURE_FLASH_CACHE_DISABLE_OPM + + /* Disable flash cache before modifying MEMWAIT, SOPCCR, or OPCCR. */ + R_BSP_FlashCacheDisable(); + #else + + /* Do not enable CM33 C-Cache for secondary core TrustZone projects because of limitations listed in + * RA8P1 UM 2.16.5.3 Restrictions Relating to Security Attribution of C-Cache and S-Cache */ + #if !((BSP_FEATURE_BSP_CODE_CACHE_VERSION == 2) && (BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD)) + + /* Enable the flash cache and don't disable it while running from flash. On these MCUs, the flash cache does not + * need to be disabled when adjusting the operating power mode. */ + R_BSP_FlashCacheEnable(); + #endif + #endif +#endif + +#if BSP_FEATURE_FLASH_PREFETCH_BUFFER + + /* Enable the flash prefetch buffer. */ + R_FACI_LP->PFBER = 1; +#endif + + bsp_clock_freq_var_init(); + +#if BSP_FEATURE_CGC_REGISTER_SET_B + bsp_prv_cmc_init(); +#else + #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + + /* Transition to an intermediate clock configuration in order to prepare for writing the new clock configuration. */ + bsp_soft_reset_prepare(); + #endif +#endif + +#if BSP_CLOCK_CFG_MAIN_OSC_POPULATED + #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + + /* Update the main oscillator drive, source, and wait states if the main oscillator is stopped. If the main + * oscillator is running, the drive, source, and wait states are assumed to be already set appropriately. */ + if (R_SYSTEM->MOSCCR) + { + #if BSP_FEATURE_CGC_REGISTER_SET_B + + /* Set the main oscillator wait time. */ + R_SYSTEM->OSTS = BSP_CLOCK_CFG_MAIN_OSC_WAIT; + #else + + /* Don't write to MOSCWTCR unless MOSTP is 1 and MOSCSF = 0. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.MOSCSF, 0U); + + /* Configure main oscillator drive. */ + R_SYSTEM->MOMCR = BSP_PRV_MOMCR; + + /* Set the main oscillator wait time. */ + R_SYSTEM->MOSCWTCR = (uint8_t) BSP_CLOCK_CFG_MAIN_OSC_WAIT; + #endif + } + + #else + #if BSP_FEATURE_CGC_REGISTER_SET_B + + /* Set the main oscillator wait time. */ + R_SYSTEM->OSTS = BSP_CLOCK_CFG_MAIN_OSC_WAIT; + #else + + /* Configure main oscillator drive. */ + R_SYSTEM->MOMCR = BSP_PRV_MOMCR; + + /* Set the stabilization time for XTAL. */ + R_SYSTEM->MOSCWTCR = (uint8_t) BSP_CLOCK_CFG_MAIN_OSC_WAIT; + #endif + #endif +#endif + + /* Initialize the sub-clock according to the BSP configuration. */ + bsp_prv_sosc_init(); + +#if BSP_FEATURE_CGC_HAS_HOCOWTCR + #if BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY + + /* These MCUs only require writes to HOCOWTCR if HOCO is set to 64 MHz. */ + #if 64000000 == BSP_HOCO_HZ + #if BSP_CFG_USE_LOW_VOLTAGE_MODE + + /* Wait for HOCO to stabilize before writing to HOCOWTCR. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.HOCOSF, 1U); + #else + + /* HOCO is assumed to be stable because these MCUs also require the HOCO to be stable before changing the operating + * power control mode. */ + #endif + R_SYSTEM->HOCOWTCR = BSP_FEATURE_CGC_HOCOWTCR_VALUE; + #endif + #else + + /* These MCUs require HOCOWTCR to be set to the maximum value except in snooze mode. There is no restriction to + * writing this register. */ + R_SYSTEM->HOCOWTCR = BSP_FEATURE_CGC_HOCOWTCR_VALUE; + #endif +#endif + +#if !BSP_CFG_USE_LOW_VOLTAGE_MODE + #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + + /* Switch to high-speed to prevent any issues with the subsequent clock configurations. */ + bsp_prv_operating_mode_set(BSP_PRV_OPERATING_MODE_HIGH_SPEED); + #elif BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ > 0U + + /* MCUs that support low voltage mode start up in low voltage mode. */ + bsp_prv_operating_mode_opccr_set(BSP_PRV_OPERATING_MODE_HIGH_SPEED); + + #if !BSP_PRV_HOCO_USED + + /* HOCO must be running during startup in low voltage mode. If HOCO is not used, turn it off after exiting low + * voltage mode. */ + R_SYSTEM->HOCOCR = 1U; + #endif + #elif BSP_FEATURE_CGC_STARTUP_OPCCR_MODE != BSP_PRV_OPERATING_MODE_HIGH_SPEED + + /* Some MCUs do not start in high speed mode. */ + #if !BSP_FEATURE_CGC_REGISTER_SET_B + bsp_prv_operating_mode_opccr_set(BSP_PRV_OPERATING_MODE_HIGH_SPEED); + #else + bsp_prv_operating_mode_set(BSP_PRV_OPERATING_MODE_HIGH_SPEED); + #endif + #endif +#endif + + /* The FLL function can only be used when the subclock is running. */ +#if BSP_PRV_HOCO_USE_FLL + + /* If FLL is to be used configure FLLCR1 and FLLCR2 before starting HOCO. */ + R_SYSTEM->FLLCR2 = BSP_PRV_FLL_FLLCR2; + R_SYSTEM->FLLCR1 = 1U; +#endif + + /* Start all clocks used by other clocks first. */ +#if BSP_PRV_HOCO_USED + R_SYSTEM->HOCOCR = 0U; + + #if BSP_PRV_HOCO_USE_FLL && (BSP_CLOCKS_SOURCE_CLOCK_HOCO != BSP_CFG_PLL_SOURCE) + + /* If FLL is enabled, wait for the FLL stabilization delay (1.8 ms) */ + R_BSP_SoftwareDelay(BSP_PRV_FLL_STABILIZATION_TIME_US, BSP_DELAY_UNITS_MICROSECONDS); + #endif + + #if BSP_PRV_STABILIZE_HOCO + + /* Wait for HOCO to stabilize. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.HOCOSF, 1U); + #endif +#endif +#if BSP_PRV_MOCO_USED + #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + + /* If the MOCO is not running, start it and wait for it to stabilize using a software delay. */ + if (0U != R_SYSTEM->MOCOCR) + { + R_SYSTEM->MOCOCR = 0U; + #if BSP_PRV_STABILIZE_MOCO + R_BSP_SoftwareDelay(BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US, BSP_DELAY_UNITS_MICROSECONDS); + #endif + } + + #else + #if BSP_FEATURE_CGC_REGISTER_SET_B + R_SYSTEM->MOCOCR = 0U; + #if BSP_PRV_STABILIZE_MOCO + R_BSP_SoftwareDelay(BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US, BSP_DELAY_UNITS_MICROSECONDS); + #endif + #endif + #endif +#endif +#if BSP_PRV_LOCO_USED + #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + + /* If the LOCO is not running, start it and wait for it to stabilize using a software delay. */ + if (0U != R_SYSTEM->LOCOCR) + { + R_SYSTEM->LOCOCR = 0U; + #if BSP_PRV_STABILIZE_LOCO + R_BSP_SoftwareDelay(BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US, BSP_DELAY_UNITS_MICROSECONDS); + #endif + } + + #else + R_SYSTEM->LOCOCR = 0U; + #if BSP_PRV_STABILIZE_LOCO + R_BSP_SoftwareDelay(BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US, BSP_DELAY_UNITS_MICROSECONDS); + #endif + #endif +#endif +#if BSP_PRV_MAIN_OSC_USED + #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + if (R_SYSTEM->MOSCCR) + #endif + { + R_SYSTEM->MOSCCR = 0U; + + #if BSP_PRV_STABILIZE_MAIN_OSC + + /* Wait for main oscillator to stabilize. */ + #if BSP_FEATURE_CGC_REGISTER_SET_B + #if !BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE + + /* + * The main oscillation stabilization time countered by OSTC + * 0x80: 2^8/fx min + * 0xC0: 2^9/fx min + * 0xE0: 2^10/fx min + * 0xF0: 2^11/fx min + * 0xF8: 2^13/fx min + * 0xFC: 2^15/fx min + * 0xFE: 2^17/fx min + * 0xFF: 2^18/fx min + * Note: The oscillation stabilization time counter is not applied for External clock input. + */ + uint8_t mainosc_stable_value = (uint8_t) ~(BSP_PRV_OSTC_OFFSET >> BSP_CLOCK_CFG_MAIN_OSC_WAIT); + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSTC, mainosc_stable_value); + #endif + #else + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.MOSCSF, 1U); + #endif + #endif + } +#endif + + /* Start clocks that require other clocks. At this point, all dependent clocks are running and stable if needed. */ + +#if BSP_PRV_STARTUP_OPERATING_MODE != BSP_PRV_OPERATING_MODE_LOW_SPEED + #if BSP_FEATURE_CGC_HAS_PLL2 && BSP_CFG_PLL2_SOURCE != BSP_CLOCKS_CLOCK_DISABLED + #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + if (R_SYSTEM->PLL2CR) + #endif + { + R_SYSTEM->PLL2CCR = BSP_PRV_PLL2CCR; + #if (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) + R_SYSTEM->PLL2CCR2 = BSP_PRV_PLL2CCR2; + #endif + + /* Start PLL2. */ + R_SYSTEM->PLL2CR = 0U; + } + #endif /* BSP_FEATURE_CGC_HAS_PLL2 && BSP_CFG_PLL2_ENABLE */ +#endif + +#if BSP_PRV_PLL_SUPPORTED && BSP_PRV_PLL_USED + #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + if (R_SYSTEM->PLLCR) + #endif + { + #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (4U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (5U == BSP_FEATURE_CGC_PLLCCR_TYPE) + R_SYSTEM->PLLCCR = (uint16_t) BSP_PRV_PLLCCR; + #elif 2U == BSP_FEATURE_CGC_PLLCCR_TYPE + R_SYSTEM->PLLCCR2 = (uint8_t) BSP_PRV_PLLCCR; + #elif (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #if 6U == BSP_FEATURE_CGC_PLLCCR_TYPE + R_SYSTEM->PLLCCR = BSP_PRV_PLLCCR; + #else + R_SYSTEM->PLLCCR = (uint16_t) BSP_PRV_PLLCCR; + #endif + R_SYSTEM->PLLCCR2 = (uint16_t) BSP_PRV_PLLCCR2; + #endif + + #if BSP_FEATURE_CGC_PLLCCR_WAIT_US > 0 + + /* This loop is provided to ensure at least 1 us passes between setting PLLMUL and clearing PLLSTP on some + * MCUs (see PLLSTP notes in "PLL Control Register (PLLCR)" description in the CGC section of the relevant hardware manual). + * Five loops are needed here to ensure the most efficient path takes at least 1 us from the setting of + * PLLMUL to the clearing of PLLSTP. HOCO is the fastest clock we can be using here since PLL cannot be running + * while setting PLLCCR. */ + bsp_prv_software_delay_loop(BSP_DELAY_LOOPS_CALCULATE(BSP_PRV_MAX_HOCO_CYCLES_PER_US)); + #endif + + #if BSP_MCU_GROUP_RA8_GEN2 && (BSP_CFG_CPU_CORE == 0) + + /* Do not access the CM85 ITCM, DTCM, I-Cache, or D-Cache during voltage scaling change. */ + /* Disable CM85 I-Cache allocations and invalidate for later coherence. */ + SCB_DisableICache(); + + /* Disable CM85 I-Cache and D-Cache lookups and allocations. D-Cache should already be clean and allocations disabled, so no cache maintenance required. */ + MEMSYSCTL->MSCR &= ~(MEMSYSCTL_MSCR_ICACTIVE_Msk | MEMSYSCTL_MSCR_DCACTIVE_Msk); + __DSB(); + __ISB(); + + /* Always set not high VSCR_1 (non-default), change before enabling PLL. + * - Note this will consume more power than necessary for certain configurations. See User Manual for more information. */ + R_SYSTEM->VSCR_b.VSCM = 0x1U; + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->VSCR_b.VSCMTSF, 0U); + + /* Re-enable CM85 I-Cache and D-Cache lookups and allow allocations per CCR.xC (TZ banked) bits . */ + MEMSYSCTL->MSCR |= (MEMSYSCTL_MSCR_ICACTIVE_Msk | MEMSYSCTL_MSCR_DCACTIVE_Msk); + __DSB(); + __ISB(); + SCB_EnableICache(); + #endif + + R_SYSTEM->PLLCR = 0U; + + #if BSP_PRV_STABILIZE_PLL + + /* Wait for PLL to stabilize. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.PLLSF, 1U); + #endif + } +#endif + + /* Set source clock and dividers. */ +#if !BSP_FEATURE_CGC_REGISTER_SET_B + #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + #if BSP_TZ_SECURE_BUILD + + /* In case of soft reset, make sure callback pointer is NULL initially. */ + g_bsp_clock_update_callback = NULL; + #endif + + #if BSP_FEATURE_CGC_HAS_CPUCLK + bsp_prv_clock_set(BSP_CFG_CLOCK_SOURCE, BSP_PRV_STARTUP_SCKDIVCR, BSP_PRV_STARTUP_SCKDIVCR2); + #else + bsp_prv_clock_set(BSP_CFG_CLOCK_SOURCE, BSP_PRV_STARTUP_SCKDIVCR, 0); + #endif + #else + bsp_prv_clock_set_hard_reset(); + #endif +#else + #if (1U == BSP_PRV_CLKOUT_SOURCE_SET) + bsp_prv_clock_set(BSP_CFG_CLKOUT_SOURCE, BSP_CFG_HOCO_DIV, BSP_CFG_MOCO_DIV, BSP_CFG_XTAL_DIV); + #elif (2U == BSP_PRV_CLKOUT_SOURCE_SET) + bsp_prv_clock_set(BSP_CFG_CLKOUT1_SOURCE, BSP_CFG_HOCO_DIV, BSP_CFG_MOCO_DIV, BSP_CFG_XTAL_DIV); + #endif + bsp_prv_clock_set(BSP_CFG_CLOCK_SOURCE, BSP_CFG_HOCO_DIV, BSP_CFG_MOCO_DIV, BSP_CFG_XTAL_DIV); +#endif + + /* If the MCU can run in a lower power mode, apply the optimal operating speed mode. */ +#if !BSP_CFG_USE_LOW_VOLTAGE_MODE + #if BSP_PRV_STARTUP_OPERATING_MODE != BSP_PRV_OPERATING_MODE_HIGH_SPEED + bsp_prv_operating_mode_set(BSP_PRV_STARTUP_OPERATING_MODE); + #endif +#endif + +#if defined(BSP_PRV_POWER_USE_DCDC) && (BSP_PRV_POWER_USE_DCDC == BSP_PRV_POWER_DCDC_STARTUP) && \ + (BSP_PRV_STARTUP_OPERATING_MODE <= BSP_PRV_OPERATING_MODE_MIDDLE_SPEED) + + /* Start DCDC as part of BSP startup when configured (BSP_CFG_DCDC_ENABLE == 2). */ + R_BSP_PowerModeSet(BSP_CFG_DCDC_VOLTAGE_RANGE); +#endif + + /* Need to start BCLKA before selecting which BCLK will be used. */ +#if defined(BSP_CFG_BCLKA_SOURCE) && (BSP_CFG_BCLKA_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->BCKACR, &R_SYSTEM->BCKADIVCR, BSP_CFG_BCLKA_DIV, BSP_CFG_BCLKA_SOURCE); +#endif + + /* Configure BCLK if it exists on the MCU. */ +#ifdef BSP_CFG_BCLK_OUTPUT + #if BSP_CFG_BCLK_OUTPUT > 0U + #ifdef BSP_CFG_EBCLKA_SEL + R_SYSTEM->BCKCR = (BSP_CFG_BCLK_OUTPUT - 1U) | (BSP_CFG_EBCLKA_SEL << R_SYSTEM_BCKCR_EBCKASEL_Pos); + #else + R_SYSTEM->BCKCR = BSP_CFG_BCLK_OUTPUT - 1U; + #endif + R_SYSTEM->EBCKOCR = 1U; + #else + #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + R_SYSTEM->EBCKOCR = 0U; + #endif + #endif +#endif + + /* Configure SDRAM clock if it exists on the MCU. */ +#ifdef BSP_CFG_SDCLK_OUTPUT + R_SYSTEM->SDCKOCR = BSP_CFG_SDCLK_OUTPUT; +#endif + + /* Configure CLKOUT. */ +#if !BSP_FEATURE_CGC_REGISTER_SET_B + #if BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_CLOCK_DISABLED + #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + R_SYSTEM->CKOCR = 0U; + #endif + #else + uint8_t ckocr = BSP_CFG_CLKOUT_SOURCE | (BSP_CFG_CLKOUT_DIV << BSP_PRV_CKOCR_CKODIV_BIT); + R_SYSTEM->CKOCR = ckocr; + ckocr |= (1U << BSP_PRV_CKOCR_CKOEN_BIT); + R_SYSTEM->CKOCR = ckocr; + #endif +#else + bsp_prv_clkout_set(); +#endif + +#if BSP_PRV_STARTUP_OPERATING_MODE != BSP_PRV_OPERATING_MODE_LOW_SPEED + #if BSP_CFG_UCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED + + /* If the USB clock has a divider setting in SCKDIVCR2. */ + #if BSP_FEATURE_USB_SCKDIVCR2_HAS_CLOCK_DIV + R_SYSTEM->SCKDIVCR2 = BSP_PRV_UCK_DIV << BSP_PRV_SCKDIVCR2_UCK_BIT; + #endif /* BSP_FEATURE_USB_SCKDIVCR2_HAS_CLOCK_DIV */ + + /* If there is a REQ bit in USBCKCR, then follow sequence from "USBCKCR : USB Clock Control Register" description in the CGC section of the relevant hardware manual. */ + #if BSP_FEATURE_USB_HAS_CLOCK_REQ + + /* Request to change the USB Clock. */ + R_SYSTEM->USBCKCR_b.USBCKSREQ = 1; + + /* Wait for the clock to be stopped. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->USBCKCR_b.USBCKSRDY, 1U); + + #if BSP_FEATURE_USB_HAS_USBCKDIVCR + + /* Write the settings. */ + R_SYSTEM->USBCKDIVCR = BSP_PRV_UCK_DIV; + #endif /* BSP_FEATURE_USB_HAS_USBCKDIVCR */ + + /* Select the USB Clock without enabling it. */ + R_SYSTEM->USBCKCR = BSP_CFG_UCLK_SOURCE | R_SYSTEM_USBCKCR_USBCKSREQ_Msk; + #endif /* BSP_FEATURE_USB_HAS_CLOCK_REQ */ + + #if BSP_FEATURE_USB_HAS_CLOCK_SEL + + /* Some MCUs use an alternate register for selecting the USB clock source. */ + #if BSP_FEATURE_USB_HAS_CLOCK_SEL_ALT + #if BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_UCLK_SOURCE + + /* Write to USBCKCR to select the PLL. */ + R_SYSTEM->USBCKCR_ALT = 0; + #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_UCLK_SOURCE + + /* Write to USBCKCR to select the HOCO. */ + R_SYSTEM->USBCKCR_ALT = 1; + #endif + #else + + /* Select the USB Clock. */ + R_SYSTEM->USBCKCR = BSP_CFG_UCLK_SOURCE; + #endif + #endif /* BSP_FEATURE_USB_HAS_CLOCK_REQ */ + + #if BSP_FEATURE_USB_HAS_CLOCK_REQ + + /* Wait for the USB Clock to be started. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->USBCKCR_b.USBCKSRDY, 0U); + #endif /* BSP_FEATURE_USB_HAS_CLOCK_REQ */ + #endif /* BSP_CFG_USB_ENABLE */ +#endif /* BSP_PRV_STARTUP_OPERATING_MODE != BSP_PRV_OPERATING_MODE_LOW_SPEED */ + + /* Set the OCTASPI clock if it exists on the MCU (See "OCTACKCR : Octal-SPI Clock Control Register" description in the CGC section of the relevant hardware manual). */ +#if BSP_FEATURE_OSPI_HAS_CLOCK && BSP_CFG_OCTACLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED + bsp_octaclk_settings_t octaclk_settings = + { + .source_clock = (bsp_clocks_source_t) BSP_CFG_OCTACLK_SOURCE, + .divider = (bsp_clocks_octaclk_div_t) BSP_CFG_OCTACLK_DIV + }; + R_BSP_OctaclkUpdate(&octaclk_settings); +#endif /* BSP_FEATURE_OSPI_HAS_CLOCK && BSP_CFG_OCTASPI_CLOCK_ENABLE */ + + /* Set the CANFD clock if it exists on the MCU */ +#if BSP_FEATURE_CANFD_HAS_CLOCK && (BSP_CFG_CANFDCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) && \ + (BSP_CFG_CANFDCLK_SOURCE != BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + + bsp_peripheral_clock_set(&R_SYSTEM->CANFDCKCR, + &R_SYSTEM->CANFDCKDIVCR, + BSP_CFG_CANFDCLK_DIV, + BSP_CFG_CANFDCLK_SOURCE); +#endif + + /* Set the SCISPI clock if it exists on the MCU */ +#if BSP_FEATURE_SCI_HAS_SCISPI_CLOCK && (BSP_CFG_SCISPICLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->SCISPICKCR, + &R_SYSTEM->SCISPICKDIVCR, + BSP_CFG_SCISPICLK_DIV, + BSP_CFG_SCISPICLK_SOURCE); +#endif + + /* Set the SCI clock if it exists on the MCU */ +#if BSP_FEATURE_SCI_HAS_CLOCK && (BSP_CFG_SCICLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->SCICKCR, &R_SYSTEM->SCICKDIVCR, BSP_CFG_SCICLK_DIV, BSP_CFG_SCICLK_SOURCE); +#endif + + /* Set the SPI clock if it exists on the MCU */ +#if BSP_FEATURE_SPI_HAS_CLOCK && (BSP_CFG_SPICLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->SPICKCR, &R_SYSTEM->SPICKDIVCR, BSP_CFG_SPICLK_DIV, BSP_CFG_SPICLK_SOURCE); +#endif + + /* Set the GPT clock if it exists on the MCU */ +#if BSP_PERIPHERAL_GPT_GTCLK_PRESENT && (BSP_CFG_GPTCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->GPTCKCR, &R_SYSTEM->GPTCKDIVCR, BSP_CFG_GPTCLK_DIV, BSP_CFG_GPTCLK_SOURCE); +#endif + + /* Set the IIC clock if it exists on the MCU */ +#if BSP_FEATURE_IIC_HAS_CLOCK && (BSP_CFG_IICCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->IICCKCR, &R_SYSTEM->IICCKDIVCR, BSP_CFG_IICCLK_DIV, BSP_CFG_IICCLK_SOURCE); +#endif + + /* Set the CEC clock if it exists on the MCU */ +#if BSP_FEATURE_CEC_HAS_CLOCK && (BSP_CFG_CECCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->CECCKCR, &R_SYSTEM->CECCKDIVCR, BSP_CFG_CECCLK_DIV, BSP_CFG_CECCLK_SOURCE); +#endif + + /* Set the I3C clock if it exists on the MCU */ +#if BSP_FEATURE_I3C_HAS_CLOCK && (BSP_CFG_I3CCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->I3CCKCR, &R_SYSTEM->I3CCKDIVCR, BSP_CFG_I3CCLK_DIV, BSP_CFG_I3CCLK_SOURCE); +#endif + + /* Set the LCD clock if it exists on the MCU */ +#if BSP_FEATURE_LCD_HAS_CLOCK && (BSP_CFG_LCDCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->LCDCKCR, &R_SYSTEM->LCDCKDIVCR, BSP_CFG_LCDCLK_DIV, BSP_CFG_LCDCLK_SOURCE); +#endif + + /* Set the USB-HS clock if it exists on the MCU */ +#if BSP_FEATURE_USB_HAS_USB60_CLOCK && (BSP_CFG_USB60CLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->USB60CKCR, + &R_SYSTEM->USB60CKDIVCR, + BSP_CFG_USB60CLK_DIV, + BSP_CFG_USB60CLK_SOURCE); +#endif + + /* Set the ADC clock if it exists on the MCU */ +#if BSP_FEATURE_ADC_HAS_CLOCK && (BSP_CFG_ADCCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->ADCCKCR, &R_SYSTEM->ADCCKDIVCR, BSP_CFG_ADCCLK_DIV, BSP_CFG_ADCCLK_SOURCE); +#endif + + /* Set the ESW clock if it exists on the MCU */ +#if BSP_FEATURE_ESWM_HAS_CLOCK && (BSP_CFG_ESWCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->ESWCKCR, &R_SYSTEM->ESWCKDIVCR, BSP_CFG_ESWCLK_DIV, BSP_CFG_ESWCLK_SOURCE); +#endif + + /* Set the ESWPHY clock if it exists on the MCU */ +#if BSP_FEATURE_ESWM_HAS_ESWPHY_CLOCK && (BSP_CFG_ESWPHYCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->ESWPCKCR, + &R_SYSTEM->ESWPCKDIVCR, + BSP_CFG_ESWPHYCLK_DIV, + BSP_CFG_ESWPHYCLK_SOURCE); +#endif + + /* Set the ETHPHY clock if it exists on the MCU */ +#if BSP_FEATURE_BSP_HAS_ETHPHY_CLOCK && (BSP_CFG_ETHPHYCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->ETHPCKCR, + &R_SYSTEM->ETHPCKDIVCR, + BSP_CFG_ETHPHYCLK_DIV, + BSP_CFG_ETHPHYCLK_SOURCE); +#endif + +#if BSP_FEATURE_BSP_HAS_DSMIF_CLOCK && \ + (BSP_CFG_DSMIFCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->DSMIFCKCR, + &R_SYSTEM->DSMIFCKDIVCR, + BSP_CFG_DSMIFCLK_DIV, + BSP_CFG_DSMIFCLK_SOURCE); +#endif + +#if BSP_FEATURE_BSP_HAS_ESC_CLOCK && \ + (BSP_CFG_ESCCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->ESCCKCR, &R_SYSTEM->ESCCKDIVCR, BSP_CFG_ESCCLK_DIV, BSP_CFG_ESCCLK_SOURCE); +#endif + + /* Set the SDADC clock if it exists on the MCU. */ +#if BSP_FEATURE_SDADC_HAS_CLOCK && (BSP_CFG_SDADC_CLOCK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + #if BSP_CFG_SDADC_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO + uint8_t sdadcckcr = 1U; + #elif BSP_CFG_SDADC_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL + uint8_t sdadcckcr = 2U; + #else /* BSP_CLOCK_SOURCE_CLOCK_MOSC */ + uint8_t sdadcckcr = 0U; + #endif + + /* SDADC isn't controlled like the other peripheral clocks so we cannot use the generic setter. */ + R_SYSTEM->SDADCCKCR = sdadcckcr & R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk; +#endif + + /* Lock CGC and LPM protection registers. */ +#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + R_SYSTEM->PRCR_NS = (uint16_t) BSP_PRV_PRCR_LOCK; +#else + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; +#endif + +#if (BSP_FEATURE_FLASH_CACHE || defined(R_CACHE)) && BSP_FEATURE_FLASH_CACHE_DISABLE_OPM + R_BSP_FlashCacheEnable(); +#endif +} + +#if BSP_CLOCK_CFG_SUBCLOCK_POPULATED + +/*******************************************************************************************************************//** + * This function is called during SOSC stabilization when Sub-Clock oscillator is populated. + * This function is declared as a weak symbol higher up in this file because it is meant to be overridden by a user + * implemented version. One of the main uses for this function is to update the IWDT/WDT Refresh Register if an + * application starts IWDT/WDT automatically after reset. To use this function just copy this function into your own + * code and modify it to meet your needs. + * + * @param[in] delay_ms Stabilization Time for the clock. + **********************************************************************************************************************/ +void R_BSP_SubClockStabilizeWait (uint32_t delay_ms) +{ + /* Wait for clock to stabilize. */ + R_BSP_SoftwareDelay(delay_ms, BSP_DELAY_UNITS_MILLISECONDS); +} + +/*******************************************************************************************************************//** + * This function is called during SOSC registers initialization when Sub-Clock oscillator is populated. + * This function is declared as a weak symbol higher up in this file because it is meant to be overridden by a user + * implemented version. One of the main uses for this function is to skip waiting for stabilization time after reset. + * To use this function just copy this function into your own code and modify it to meet your needs. + * + * @param[in] delay_ms Stabilization Time for the clock. + **********************************************************************************************************************/ +void R_BSP_SubClockStabilizeWaitAfterReset (uint32_t delay_ms) +{ + #if (BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE) || (BSP_PRV_HOCO_USE_FLL) + + /* Wait for clock to stabilize after reset. */ + R_BSP_SoftwareDelay(delay_ms, BSP_DELAY_UNITS_MILLISECONDS); + #else + FSP_PARAMETER_NOT_USED(delay_ms); + #endif +} + +#endif + +#if (BSP_PRV_HAS_ENABLED_PERIPHERAL_CLOCKS == 1U) + +/*******************************************************************************************************************//** + * Set the peripheral clock on the MCU + * + * @param[in] p_clk_ctrl_reg Pointer to peripheral clock control register + * @param[in] p_clk_div_reg Pointer to peripheral clock division control register + * @param[in] peripheral_clk_div Peripheral clock division + * @param[in] peripheral_clk_source Peripheral clock source + * + * @return The wait states for FLWT required after the clock change (or 0 if FLWT does not exist). + **********************************************************************************************************************/ +static void bsp_peripheral_clock_set (volatile uint8_t * p_clk_ctrl_reg, + volatile uint8_t * p_clk_div_reg, + uint8_t peripheral_clk_div, + uint8_t peripheral_clk_source) +{ + /* Request to stop the peripheral clock. */ + *p_clk_ctrl_reg |= (uint8_t) BSP_PRV_PERIPHERAL_CLK_REQ_BIT_MASK; + + /* Wait for the peripheral clock to stop. */ + FSP_HARDWARE_REGISTER_WAIT((uint8_t) ((*p_clk_ctrl_reg & BSP_PRV_PERIPHERAL_CLK_RDY_BIT_MASK) >> + BSP_PRV_PERIPHERAL_CLK_RDY_BIT_POS), + 1U); + + /* Select the peripheral clock divisor and source. */ + *p_clk_div_reg = peripheral_clk_div; + *p_clk_ctrl_reg = peripheral_clk_source | BSP_PRV_PERIPHERAL_CLK_REQ_BIT_MASK | + BSP_PRV_PERIPHERAL_CLK_RDY_BIT_MASK; + + /* Request to start the peripheral clock. */ + *p_clk_ctrl_reg &= (uint8_t) ~BSP_PRV_PERIPHERAL_CLK_REQ_BIT_MASK; + + /* Wait for the peripheral clock to start. */ + FSP_HARDWARE_REGISTER_WAIT((uint8_t) ((*p_clk_ctrl_reg & BSP_PRV_PERIPHERAL_CLK_RDY_BIT_MASK) >> + BSP_PRV_PERIPHERAL_CLK_RDY_BIT_POS), + 0U); +} + +#endif + +#if !BSP_FEATURE_CGC_REGISTER_SET_B + +/*******************************************************************************************************************//** + * Increases the ROM and RAM wait state settings to the minimum required based on the requested clock change. + * + * @param[in] requested_freq_hz New core clock frequency after the clock change. + * + * @return The wait states for FLWT required after the clock change (or 0 if FLWT does not exist). + **********************************************************************************************************************/ +static uint8_t bsp_clock_set_prechange (uint32_t requested_freq_hz) +{ + uint8_t new_rom_wait_state = 0U; + + FSP_PARAMETER_NOT_USED(requested_freq_hz); + + #if BSP_FEATURE_CGC_HAS_SRAMWTSC + + /* Wait states for SRAM (SRAM0, SRAM1 and SRAM0 (DED)). */ + if (requested_freq_hz > BSP_FEATURE_SYSC_CLOCK_FREQ_NO_RAM_WAITS) + { + #if BSP_FEATURE_CGC_HAS_SRAMPRCR2 == 1 + R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_UNLOCK; + R_SRAM->SRAMWTSC = BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE; + R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_LOCK; + #else + + /* Devices with TrustZone version 2 have a separate non-secure register for SRAM register protection. */ + #if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + R_SRAM->SRAMPRCR_NS = BSP_PRV_SRAM_UNLOCK; + #else + R_SRAM->SRAMPRCR = BSP_PRV_SRAM_UNLOCK; + #endif + + /* Execute data memory barrier before and after setting the wait states, See "Note of write to SRAMCR0, SRAMCR1 and SRAMECCRGN0 registers" + * in the SRAM section of the relevant hardware manual */ + __DMB(); + R_SRAM->SRAMWTSC = BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE; + __DMB(); + + /* Devices with TrustZone version 2 have a separate non-secure register for SRAM register protection. */ + #if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + R_SRAM->SRAMPRCR_NS = BSP_PRV_SRAM_LOCK; + #else + R_SRAM->SRAMPRCR = BSP_PRV_SRAM_LOCK; + #endif + #endif + } + #endif + + #if BSP_FEATURE_CGC_HAS_FLWT + + /* Calculate the wait states for ROM */ + #if BSP_FEATURE_SYSC_CLOCK_FREQ_TWO_ROM_WAITS == 0 + if (requested_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_ONE_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_ZERO_WAIT_CYCLES; + } + else + { + new_rom_wait_state = BSP_PRV_ROM_ONE_WAIT_CYCLES; + } + + #elif BSP_FEATURE_SYSC_CLOCK_FREQ_THREE_ROM_WAITS == 0 + if (requested_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_ONE_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_ZERO_WAIT_CYCLES; + } + else if (requested_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_TWO_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_ONE_WAIT_CYCLES; + } + else + { + new_rom_wait_state = BSP_PRV_ROM_TWO_WAIT_CYCLES; + } + + #elif BSP_FEATURE_SYSC_CLOCK_FREQ_FOUR_ROM_WAITS == 0 + if (requested_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_ONE_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_ZERO_WAIT_CYCLES; + } + else if (requested_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_TWO_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_ONE_WAIT_CYCLES; + } + else if (requested_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_THREE_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_TWO_WAIT_CYCLES; + } + else + { + new_rom_wait_state = BSP_PRV_ROM_THREE_WAIT_CYCLES; + } + + #elif BSP_FEATURE_SYSC_CLOCK_FREQ_FIVE_ROM_WAITS == 0 + if (requested_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_ONE_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_ZERO_WAIT_CYCLES; + } + else if (requested_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_TWO_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_ONE_WAIT_CYCLES; + } + else if (requested_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_THREE_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_TWO_WAIT_CYCLES; + } + else if (requested_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_FOUR_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_THREE_WAIT_CYCLES; + } + else + { + new_rom_wait_state = BSP_PRV_ROM_FOUR_WAIT_CYCLES; + } + + #else + if (requested_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_ONE_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_ZERO_WAIT_CYCLES; + } + else if (requested_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_TWO_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_ONE_WAIT_CYCLES; + } + else if (requested_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_THREE_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_TWO_WAIT_CYCLES; + } + else if (requested_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_FOUR_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_THREE_WAIT_CYCLES; + } + else if (requested_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_FIVE_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_FOUR_WAIT_CYCLES; + } + else + { + new_rom_wait_state = BSP_PRV_ROM_FIVE_WAIT_CYCLES; + } + #endif + + /* If more wait states are required after the change, then set the wait states before changing the clock. */ + if (new_rom_wait_state > R_FCACHE->FLWT) + { + R_FCACHE->FLWT = new_rom_wait_state; + } + #endif + + #if BSP_FEATURE_CGC_HAS_MEMWAIT && !BSP_PRV_CLOCK_SUPPLY_TYPE_B + + /* Set the wait state to MEMWAIT */ + bsp_clock_set_memwait(requested_freq_hz); + #endif + + #if BSP_FEATURE_CGC_HAS_FLDWAITR && !BSP_PRV_CLOCK_SUPPLY_TYPE_B + if (requested_freq_hz > BSP_PRV_FLDWAITR_MAX_ONE_WAIT_FREQ) + { + /* The MCU must be in high speed mode to set wait states to 2. The MCU should already be in high speed mode as + * a precondition to bsp_prv_clock_set. */ + BSP_PRV_FLDWAITR_REG_ACCESS = BSP_PRV_FLDWAITR_TWO_WAIT_CYCLES; + } + #endif + + return new_rom_wait_state; +} + +/*******************************************************************************************************************//** + * Decreases the ROM and RAM wait state settings to the minimum supported based on the applied clock change. + * + * @param[in] updated_freq_hz New clock frequency after clock change + * @param[in] new_rom_wait_state Optimal value for FLWT if it exists, 0 if FLWT does not exist on the MCU + **********************************************************************************************************************/ +static void bsp_clock_set_postchange (uint32_t updated_freq_hz, uint8_t new_rom_wait_state) +{ + /* These variables are unused for some MCUs. */ + FSP_PARAMETER_NOT_USED(new_rom_wait_state); + FSP_PARAMETER_NOT_USED(updated_freq_hz); + + #if BSP_FEATURE_CGC_HAS_SRAMWTSC + + /* Wait states for SRAM (SRAM0, SRAM1 and SRAM0 (DED)). */ + if (updated_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_NO_RAM_WAITS) + { + #if BSP_FEATURE_CGC_HAS_SRAMPRCR2 == 1 + R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_UNLOCK; + R_SRAM->SRAMWTSC = BSP_PRV_SRAMWTSC_WAIT_CYCLES_DISABLE; + R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_LOCK; + #else + + /* Devices with TrustZone version 2 have a separate non-secure register for SRAM register protection. */ + #if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + R_SRAM->SRAMPRCR_NS = BSP_PRV_SRAM_UNLOCK; + #else + R_SRAM->SRAMPRCR = BSP_PRV_SRAM_UNLOCK; + #endif + + /* Execute data memory barrier before and after setting the wait states, See "Note of write to SRAMCR0, SRAMCR1 and SRAMECCRGN0 registers" + * in the SRAM section of the relevant hardware manual*/ + __DMB(); + R_SRAM->SRAMWTSC = BSP_PRV_SRAMWTSC_WAIT_CYCLES_DISABLE; + __DMB(); + + /* Devices with TrustZone version 2 have a separate non-secure register for SRAM register protection. */ + #if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + R_SRAM->SRAMPRCR_NS = BSP_PRV_SRAM_LOCK; + #else + R_SRAM->SRAMPRCR = BSP_PRV_SRAM_LOCK; + #endif + #endif + } + #endif + + #if BSP_FEATURE_CGC_HAS_FLWT + if (new_rom_wait_state != R_FCACHE->FLWT) + { + R_FCACHE->FLWT = new_rom_wait_state; + } + #endif + + #if BSP_FEATURE_CGC_HAS_MEMWAIT && !BSP_PRV_CLOCK_SUPPLY_TYPE_B + + /* Set the wait state to MEMWAIT */ + bsp_clock_set_memwait(updated_freq_hz); + #endif + + #if BSP_FEATURE_CGC_HAS_FLDWAITR && !BSP_PRV_CLOCK_SUPPLY_TYPE_B + if (updated_freq_hz <= BSP_PRV_FLDWAITR_MAX_ONE_WAIT_FREQ) + { + BSP_PRV_FLDWAITR_REG_ACCESS = BSP_PRV_FLDWAITR_ONE_WAIT_CYCLES; + } + #endif +} + +#endif + +/*******************************************************************************************************************//** + * Set the wait state to MEMWAIT. + **********************************************************************************************************************/ +#if BSP_FEATURE_CGC_HAS_MEMWAIT && !BSP_PRV_CLOCK_SUPPLY_TYPE_B +static void bsp_clock_set_memwait (uint32_t updated_freq_hz) +{ + uint8_t memwait; + if ((updated_freq_hz > BSP_PRV_MEMWAIT_MAX_ONE_WAIT_FREQ) && + ((BSP_PRV_MEMWAIT_TWO_WAIT_CYCLES & R_SYSTEM_MEMWAIT_MEMWAIT_Msk) != 0)) + { + /* The MCU must be in high speed mode to set wait states to 2. The MCU should already be in high speed mode as + * a precondition to bsp_prv_clock_set. */ + memwait = BSP_PRV_MEMWAIT_TWO_WAIT_CYCLES; + } + else if (updated_freq_hz > BSP_PRV_MEMWAIT_MAX_ZERO_WAIT_FREQ) + { + memwait = BSP_PRV_MEMWAIT_ONE_WAIT_CYCLES; + } + else + { + memwait = BSP_PRV_MEMWAIT_ZERO_WAIT_CYCLES; + } + + R_SYSTEM->MEMWAIT = memwait; +} + +#endif + +/*******************************************************************************************************************//** + * Initializes sub-clock according to the BSP configuration. + **********************************************************************************************************************/ +static void bsp_prv_sosc_init (void) +{ +#if BSP_FEATURE_CGC_HAS_SOSC + #if BSP_CLOCK_CFG_SUBCLOCK_POPULATED + #if BSP_FEATURE_RTC_IS_IRTC + #if ((BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE) || (BSP_PRV_HOCO_USE_FLL)) + + /* If sub-clock is used as system clock source or HOCO FLL source, wait for VRTC-domain become valid */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->VRTSR_b.VRTVLD, 1); + #else + + /* Check if VRTC-domain area is valid. */ + if (1U == R_SYSTEM->VRTSR_b.VRTVLD) + #endif + #endif + { + #if !BSP_FEATURE_CGC_REGISTER_SET_B + if (R_SYSTEM->SOSCCR || (BSP_CLOCK_CFG_SUBCLOCK_DRIVE != R_SYSTEM->SOMCR_b.SODRV)) + { + /* If Sub-Clock Oscillator is started at reset, stop it before configuring the subclock drive. */ + if (0U == R_SYSTEM->SOSCCR) + { + /* Stop the Sub-Clock Oscillator to update the SOMCR register. */ + R_SYSTEM->SOSCCR = 1U; + + /* Allow a stop interval of at least 5 SOSC clock cycles before configuring the drive capacity + * and restarting Sub-Clock Oscillator. */ + R_BSP_SoftwareDelay(BSP_PRV_SUBCLOCK_STOP_INTERVAL_US, BSP_DELAY_UNITS_MICROSECONDS); + + /* + * In the CGC section of the relevant hardware manual, SOSCCR : Sub-Clock Oscillator Control Register: + * When changing the value of the SOSTP bit, execute subsequent instructions + * only after reading the bit to check that the value is updated. + */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOSCCR, 1U); + } + + /* Configure the subclock drive as subclock is not running. */ + R_SYSTEM->SOMCR = + ((BSP_CLOCK_CFG_SUBCLOCK_DRIVE << BSP_FEATURE_CGC_SODRV_SHIFT) & BSP_FEATURE_CGC_SODRV_MASK); + #else + if (R_SYSTEM->SOSCCR) + { + #endif + + R_SYSTEM->SOSCCR = 0U; + + /* In the CGC sectin of the relevant hardware manual "SOSCCR : Sub-Clock Oscillator Control Register": + * After setting the SOSTP bit to 0, use the sub-clock only after the sub-clock + * oscillation stabilization time has elapsed. + */ + #if (BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE) || (BSP_PRV_HOCO_USE_FLL) + R_BSP_SubClockStabilizeWait(BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS); + #endif + } + else + { + /* + * RA MCUs like RA6M5 requires to use sub-clock after oscillation stabilization time + * has elapsed on Power-On-Reset. But, POR is not well supported on EK boards, so BSP + * has to wait on any reset. Please override this function in application if waiting + * for stabilization is not required. + */ + R_BSP_SubClockStabilizeWaitAfterReset(BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS); + } + } + + #else + R_SYSTEM->SOSCCR = 1U; + #endif +#endif +} + +/*******************************************************************************************************************//** + * Octa-SPI clock update. + * @param[in] p_octaclk_setting Pointer to Octaclk setting structure which provides information regarding + * Octaclk source and divider settings to be applied. + * @note The requested Octaclk source must be started before calling this function. + **********************************************************************************************************************/ +void R_BSP_OctaclkUpdate (bsp_octaclk_settings_t * p_octaclk_setting) +{ +#if BSP_FEATURE_OSPI_HAS_CLOCK + #if BSP_FEATURE_OSPI_B_IS_AVAILABLE + #define OSPI_UNIT_COUNT BSP_FEATURE_OSPI_B_UNIT_COUNT + #else + #define OSPI_UNIT_COUNT (1U) + #endif + + /* Store initial value of CGC and LPM protection registers. */ + #if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + uint16_t bsp_prv_prcr_orig = R_SYSTEM->PRCR_NS; + #else + uint16_t bsp_prv_prcr_orig = R_SYSTEM->PRCR; + #endif + + /* Unlock CGC and LPM protection registers. */ + #if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + R_SYSTEM->PRCR_NS = (uint16_t) BSP_PRV_PRCR_UNLOCK; + #else + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_UNLOCK; + #endif + + /* All OSPI_B peripherals need to be stopped before the clock change. + * Technical Update TN-RA*-A0147A/E. */ + uint32_t started_modules = 0; + for (uint32_t i = 0; i < OSPI_UNIT_COUNT; i++) + { + /* BSP_MSTP_BIT_FSP_IP_OSPI has a semi-colon at the end of the macro which messes up using + * it in an expression. Save the flag then if it is zero the IP is stopped. */ + const uint32_t ip_stopped = BSP_MSTP_REG_FSP_IP_OSPI(i) & BSP_MSTP_BIT_FSP_IP_OSPI(i); + if (0 == ip_stopped) + { + /* Save the module index as a flag then stop it. */ + started_modules |= (1U << i); + R_BSP_MODULE_STOP(FSP_IP_OSPI, i); + } + } + + /* Must wait 2 OCTACLK cycles after the module has been stopped before changing the clock: TU TN-RA*-A0147A/E. */ + const uint32_t octaclk_freq_hz = R_BSP_SourceClockHzGet((fsp_priv_source_clock_t) R_SYSTEM->OCTACKCR_b.OCTACKSEL) / + R_FSP_ClockDividerGet(R_SYSTEM->OCTACKDIVCR_b.OCTACKDIV); + const uint32_t octaclk_period_us = octaclk_freq_hz / BSP_PRV_HZ_PER_MHZ; + + R_BSP_SoftwareDelay(2U * octaclk_period_us, BSP_DELAY_UNITS_MICROSECONDS); + + /* Request to change the OCTASPI Clock. */ + R_SYSTEM->OCTACKCR_b.OCTACKSREQ = 1; + + /* Wait for the clock to be stopped. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OCTACKCR_b.OCTACKSRDY, 1U); + + /* Write the settings. */ + R_SYSTEM->OCTACKDIVCR = (uint8_t) p_octaclk_setting->divider; + R_SYSTEM->OCTACKCR = (uint8_t) (p_octaclk_setting->source_clock | R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk); + + /* Start the OCTASPI Clock by setting OCTACKSREQ to zero. */ + R_SYSTEM->OCTACKCR = (uint8_t) p_octaclk_setting->source_clock; + + /* Wait for the OCTASPI Clock to be started. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OCTACKCR_b.OCTACKSRDY, 0U); + + /* Restore any OSPI_B peripherals that were stopped. */ + for (uint32_t i = 0; i < OSPI_UNIT_COUNT; i++) + { + if (started_modules & (1U << i)) + { + R_BSP_MODULE_START(FSP_IP_OSPI, i); + } + } + + /* Restore CGC and LPM protection registers. */ + #if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + R_SYSTEM->PRCR_NS = BSP_PRV_PRCR_KEY | bsp_prv_prcr_orig; + #else + R_SYSTEM->PRCR = BSP_PRV_PRCR_KEY | bsp_prv_prcr_orig; + #endif +#else + FSP_PARAMETER_NOT_USED(p_octaclk_setting); +#endif +} + +/*******************************************************************************************************************//** + * Gets the frequency of a source clock. + * @param[in] clock Pointer to Octaclk setting structure which provides information regarding + * Octaclk source and divider settings to be applied. + * @return Frequency of requested clock in Hertz. + **********************************************************************************************************************/ +uint32_t R_BSP_SourceClockHzGet (fsp_priv_source_clock_t clock) +{ + uint32_t source_clock = g_clock_freq[clock]; + + return source_clock; +} + +#if BSP_FEATURE_RTC_IS_AVAILABLE || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_RTC_HAS_VBTICTLR + +/*******************************************************************************************************************//** + * RTC Initialization + * + * Some RTC registers must be initialized after reset to ensure correct operation. + * This reset is not performed automatically if the RTC is used in a project as it will + * be handled by the RTC driver if needed. + **********************************************************************************************************************/ +void R_BSP_Init_RTC (void) +{ + /* Figure "Initialization procedure" in the RTC section of the relevant hardware manual */ + + /* RCKSEL bit is not initialized after reset. Use LOCO as the default + * clock source if it is available. Note RCR4.ROPSEL is also cleared. + */ + + #if BSP_FEATURE_RTC_IS_IRTC + if (0U == R_SYSTEM->VRTSR_b.VRTVLD) // Return if VRTC-domain is invalid + { + return; + } + #endif + #if !BSP_FEATURE_CGC_REGISTER_SET_B + #if BSP_PRV_LOCO_USED && !BSP_FEATURE_RTC_IS_IRTC + R_RTC->RCR4 = 1 << R_RTC_RCR4_RCKSEL_Pos; + #else + + /* Sses SOSC as clock source, or there is no clock source. */ + R_RTC->RCR4 = 0; + #endif + #endif + + #if !BSP_CFG_RTC_USED + #if BSP_PRV_LOCO_USED || (BSP_FEATURE_CGC_HAS_SOSC && BSP_CLOCK_CFG_SUBCLOCK_POPULATED) + #if !BSP_FEATURE_CGC_REGISTER_SET_B + + /*Wait for 6 clocks: 200 > (6*1000000) / 32K */ + R_BSP_SoftwareDelay(BSP_PRV_RTC_RESET_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + + R_RTC->RCR2 = 0; + FSP_HARDWARE_REGISTER_WAIT(R_RTC->RCR2, 0); + + R_RTC->RCR2_b.RESET = 1; + FSP_HARDWARE_REGISTER_WAIT(R_RTC->RCR2_b.RESET, 0); + + /* Disable RTC interrupts */ + R_RTC->RCR1 = 0; + + /* When the RCR1 register is modified, check that all the bits are updated before proceeding + * (see "RTC Control Register 1 (RCR1)" description in the RTC section of the relevant hardware manual)*/ + FSP_HARDWARE_REGISTER_WAIT(R_RTC->RCR1, 0); + #endif + + #if BSP_FEATURE_RTC_HAS_TCEN + for (uint8_t index = 0U; index < BSP_FEATURE_RTC_RTCCR_CHANNELS; index++) + { + /* RTCCRn.TCEN must be cleared after reset. */ + R_RTC->RTCCR[index].RTCCR_b.TCEN = 0U; + FSP_HARDWARE_REGISTER_WAIT(R_RTC->RTCCR[index].RTCCR_b.TCEN, 0); + } + #endif + #endif + #endif + + #if BSP_FEATURE_RTC_HAS_VBTICTLR + + /* VBTICTLR.VCHnINEN must be cleared after reset. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT); + R_SYSTEM->VBTICTLR = 0U; + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT); + #endif + + #if BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE + + /* Enable low power counter measures. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_CGC); + R_SYSTEM->LPOPT = R_SYSTEM_LPOPT_LPOPTEN_Msk; + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_CGC); + + /* Disable RTC Register Read/Write Clock to reduce power consumption. */ + bsp_prv_rtc_register_clock_set(false); + + /* Enable Asynchronous interrupts */ + R_ICU->IELEN = R_ICU_IELEN_RTCINTEN_Msk | R_ICU_IELEN_IELEN_Msk; + #endif +} + +#endif + +#if BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE + +/*******************************************************************************************************************//** + * Enable or disable the RTC Register Read/Write Clock in order to save power. + **********************************************************************************************************************/ +bool bsp_prv_rtc_register_clock_set (bool enable) +{ + /* Save the previous state of RTCRWDIS. + * - RTCRWDIS = 0: Register Clock enabled. + * - RTCRWDIS = 1: Register Clock disabled. + */ + bool previous_state = !R_MSTP->LSMRWDIS_b.RTCRWDIS; + + if (previous_state == enable) + { + return previous_state; + } + + /* Critical section required when writing to registers that are shared between modules. */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* Set WREN. */ + R_MSTP->LSMRWDIS = BSP_PRV_LSMRDIS_KEY | R_MSTP_LSMRWDIS_WREN_Msk; + + /* Set RTCRWDIS and clear WREN. */ + R_MSTP->LSMRWDIS = BSP_PRV_LSMRDIS_KEY | !enable; + + /* Wait 2 cycles of PCLKB (See Table 3.2 "Access Cycles" in the RA2A2 user manual). */ + FSP_REGISTER_READ(R_MSTP->LSMRWDIS); + + FSP_CRITICAL_SECTION_EXIT; + + return previous_state; +} + +#endif + +#if BSP_FEATURE_RTC_IS_IRTC + +/*******************************************************************************************************************//** + * To check sub-clock status. + * + * @retval FSP_SUCCESS Sub-clock is ready to use. + * @retval FSP_ERR_INVALID_HW_CONDITION VRTC-domain area is invalid. + * @retval FSP_ERR_NOT_INITIALIZED Sub-clock has not been inititalized yet. + **********************************************************************************************************************/ +fsp_err_t R_BSP_SubclockStatusGet () +{ + #if BSP_CLOCK_CFG_SUBCLOCK_POPULATED + + /* Check if VRTC-domain area is invalid */ + FSP_ERROR_RETURN(1U == R_SYSTEM->VRTSR_b.VRTVLD, FSP_ERR_INVALID_HW_CONDITION); + + /* Check if SOSC has been configured */ + if ((0U == R_SYSTEM->SOSCCR) && (BSP_CLOCK_CFG_SUBCLOCK_DRIVE == R_SYSTEM->SOMCR_b.SODRV)) + { + return FSP_SUCCESS; + } + #endif + + return FSP_ERR_NOT_INITIALIZED; +} + +/*******************************************************************************************************************//** + * To initialize the sub-clock. + * + * @retval FSP_SUCCESS Sub-clock successfully initialized. + * @retval FSP_ERR_INVALID_HW_CONDITION Sub-clock cannot be initialized. + **********************************************************************************************************************/ +fsp_err_t R_BSP_SubclockInitialize () +{ + #if BSP_CLOCK_CFG_SUBCLOCK_POPULATED + + /* Check if VRTC-domain area is valid */ + FSP_ERROR_RETURN(1U == R_SYSTEM->VRTSR_b.VRTVLD, FSP_ERR_INVALID_HW_CONDITION); + + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_CGC); + bsp_prv_sosc_init(); + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_CGC); + + return FSP_SUCCESS; + #else + + return FSP_ERR_INVALID_HW_CONDITION; + #endif +} + +#endif + +/** @} (end addtogroup BSP_MCU_PRV) */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_clocks.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_clocks.h new file mode 100644 index 00000000000..406618cec1a --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_clocks.h @@ -0,0 +1,1793 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_CLOCKS_H +#define BSP_CLOCKS_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_clock_cfg.h" +#include "bsp_api.h" + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* The following definitions are macros instead of enums because the values are used in preprocessor conditionals. */ +/* Must match SCKCR.CKSEL values. */ +#define BSP_CLOCKS_SOURCE_CLOCK_HOCO (0) // The high speed on chip oscillator. +#define BSP_CLOCKS_SOURCE_CLOCK_MOCO (1) // The middle speed on chip oscillator. +#define BSP_CLOCKS_SOURCE_CLOCK_LOCO (2) // The low speed on chip oscillator. +#define BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC (3) // The main oscillator. +#define BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK (4) // The subclock oscillator. + +#if !BSP_FEATURE_CGC_REGISTER_SET_B + #if 0 < BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS + #define BSP_CLOCKS_SOURCE_CLOCK_PLL (5) // The PLL oscillator. + #endif + #if 0 < BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS + #define BSP_CLOCKS_SOURCE_CLOCK_PLL2 (6) // The PLL2 oscillator. + #endif + #if (1 < BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS && 1 < BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS) + #define BSP_CLOCKS_SOURCE_CLOCK_PLL1P (BSP_CLOCKS_SOURCE_CLOCK_PLL) + #define BSP_CLOCKS_SOURCE_CLOCK_PLL2P (BSP_CLOCKS_SOURCE_CLOCK_PLL2) + #define BSP_CLOCKS_SOURCE_CLOCK_PLL1Q (7) // The PLL1Q oscillator. + #define BSP_CLOCKS_SOURCE_CLOCK_PLL1R (8) // The PLL1R oscillator. + #define BSP_CLOCKS_SOURCE_CLOCK_PLL2Q (9) // The PLL2Q oscillator. + #define BSP_CLOCKS_SOURCE_CLOCK_PLL2R (10) // The PLL2R oscillator. + #endif +#else + +/* The following definitions are macros instead of enums because the values are used in preprocessor conditionals. */ +/* Must match ICLKSCR.CKSEL, FMAINSCR.CKSEL, FOCOSCR.CKSEL, FSUBSCR.CKSEL, OSMC.WUTMMCK0 and CKS0.CSEL values. */ + #define BSP_CLOCKS_SOURCE_CLOCK_FMAIN (0) // Use Main System clock (FMAIN) as System clock (ICLK) source. + #define BSP_CLOCKS_SOURCE_CLOCK_FSUB (1) // Use Sub System clock (FSUB) as System clock (ICLK) source. + #define BSP_CLOCKS_FMAIN_SOURCE_CLOCK_FOCO (0) // Use Main on-chip oscillator clock (FOCO) as Main System clock (FMAIN) source. + #define BSP_CLOCKS_FMAIN_SOURCE_CLOCK_MAIN_OSC (1) // Use Main clock oscillator (MOSC) as Main System clock (FMAIN) source. + #define BSP_CLOCKS_FOCO_SOURCE_CLOCK_HOCO (0) // Use High-speed on-chip oscillator (HOCO) as Main on-chip oscillator clock (FOCO) source. + #define BSP_CLOCKS_FOCO_SOURCE_CLOCK_MOCO (1) // Use Middle-speed on-chip oscillator (MOCO) as Main on-chip oscillator clock (FOCO) source. + #define BSP_CLOCKS_FSUB_SOURCE_CLOCK_SUBCLOCK (0) // Use Sub-clock oscillator (SOSC) as Sub System clock (FSUB) source. + #define BSP_CLOCKS_FSUB_SOURCE_CLOCK_LOCO (1) // Use Low-speed on-chip oscillator clock (LOCO) as Sub System clock (FSUB) source. + #define BSP_CLOCKS_CLKOUT_SOURCE_CLOCK_FMAIN (0) // Use Main System clock (FMAIN) as Clock Out (CLKOUT) source. + #define BSP_CLOCKS_CLKOUT_SOURCE_CLOCK_FSUB (1) // Use Subsystem Clock (FSUB) as Clock Out (CLKOUT) source. + +/* Offset to convert OSTS setting to OSTC value (OSTC = ~(BSP_PRV_OSTC_OFFSET >> OSTS)) */ + #define BSP_PRV_OSTC_OFFSET (0x7FU) + +#endif + +/* PLLs are not supported in the following scenarios: + * - When using low voltage mode + * - When using an MCU that does not have a PLL + * - When the PLL only accepts the main oscillator as a source and XTAL is not used + */ +#if BSP_FEATURE_CGC_HAS_PLL && !BSP_CFG_USE_LOW_VOLTAGE_MODE && \ + !((1U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ + (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ + (4U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ + (5U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ + !BSP_CLOCK_CFG_MAIN_OSC_POPULATED) + #define BSP_PRV_PLL_SUPPORTED (1) + #if BSP_FEATURE_CGC_HAS_PLL2 + #define BSP_PRV_PLL2_SUPPORTED (1) + #else + #define BSP_PRV_PLL2_SUPPORTED (0) + #endif +#else + #define BSP_PRV_PLL_SUPPORTED (0) + #define BSP_PRV_PLL2_SUPPORTED (0) +#endif + +/* The ICLK frequency at startup is used to determine the ideal operating mode to set after startup. The PLL frequency + * calculated here is also used to initialize the g_clock_freq array. */ +#if BSP_PRV_PLL_SUPPORTED + #if ((1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (5U == BSP_FEATURE_CGC_PLLCCR_TYPE)) && \ + (BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE) + #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_HOCO_HZ) + #else + #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) + #endif +#endif +#if BSP_PRV_PLL2_SUPPORTED + #if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL2_SOURCE + #define BSP_PRV_PLL2_SOURCE_FREQ_HZ (BSP_HOCO_HZ) + #else + #define BSP_PRV_PLL2_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) + #endif +#endif + +#define BSP_MOCO_FREQ_HZ (BSP_MOCO_HZ) + +/* Frequencies of clocks with fixed freqencies. */ +#define BSP_LOCO_FREQ_HZ (32768U) // LOCO frequency is fixed at 32768 Hz +#define BSP_SUBCLOCK_FREQ_HZ (32768U) // Subclock frequency is 32768 Hz + +#if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_CLOCK_SOURCE + #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_HOCO_HZ) +#elif BSP_CLOCKS_SOURCE_CLOCK_MOCO == BSP_CFG_CLOCK_SOURCE + #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_MOCO_FREQ_HZ) +#elif BSP_CLOCKS_SOURCE_CLOCK_LOCO == BSP_CFG_CLOCK_SOURCE + #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_LOCO_FREQ_HZ) +#elif BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE + #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_SUBCLOCK_FREQ_HZ) +#elif BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_CLOCK_SOURCE + #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_CFG_XTAL_HZ) +#elif BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE + #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (5U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL_SOURCE + #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) + #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE + #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_HOCO_HZ) + #endif + #define BSP_STARTUP_SOURCE_CLOCK_HZ (((BSP_PRV_PLL_SOURCE_FREQ_HZ * (BSP_CFG_PLL_MUL + 1U)) >> 1) / \ + (BSP_CFG_PLL_DIV + 1U)) + #elif (2U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) + #define BSP_STARTUP_SOURCE_CLOCK_HZ ((BSP_PRV_PLL_SOURCE_FREQ_HZ * ((BSP_CFG_PLL_MUL + 1U) >> 1)) >> \ + (BSP_CFG_PLL_DIV)) + #elif (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_CFG_PLL1P_FREQUENCY_HZ) + #endif +#endif + +/* Convert divisor bitfield settings into divisor values to calculate startup clocks */ +#define BSP_PRV_SCKDIVCR_DIV_VALUE(div) (((div) & 8U) ? (3U << ((div) & ~8U)) : (1U << (div))) +#define BSP_PRV_CPUCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_CPUCLK_DIV) + +#if !BSP_FEATURE_CGC_REGISTER_SET_B + #define BSP_PRV_ICLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_ICLK_DIV) +#else + #define BSP_PRV_ICLK_DIV_VALUE (1U << BSP_CFG_ICLK_DIV) +#endif + +#define BSP_PRV_PCLKA_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKA_DIV) +#define BSP_PRV_PCLKB_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKB_DIV) +#define BSP_PRV_PCLKC_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKC_DIV) +#define BSP_PRV_PCLKD_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKD_DIV) +#define BSP_PRV_PCLKE_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKE_DIV) +#define BSP_PRV_BCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_BCLK_DIV) +#define BSP_PRV_FCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_FCLK_DIV) +#define BSP_PRV_MRICLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_MRICLK_DIV) + +/* Startup clock frequency of each system clock. These macros are only helpful if the system clock and dividers have + * not changed since startup. These macros are not used in FSP modules except for the clock startup code. */ +#define BSP_STARTUP_CPUCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_CPUCLK_DIV_VALUE) +#define BSP_STARTUP_ICLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_ICLK_DIV_VALUE) +#define BSP_STARTUP_PCLKA_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKA_DIV_VALUE) +#define BSP_STARTUP_PCLKB_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKB_DIV_VALUE) +#define BSP_STARTUP_PCLKC_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKC_DIV_VALUE) +#define BSP_STARTUP_PCLKD_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKD_DIV_VALUE) +#define BSP_STARTUP_PCLKE_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKE_DIV_VALUE) +#define BSP_STARTUP_BCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_BCLK_DIV_VALUE) +#define BSP_STARTUP_FCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_FCLK_DIV_VALUE) +#define BSP_STARTUP_MRICLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_MRICLK_DIV_VALUE) + +/* System clock divider options. */ +#define BSP_CLOCKS_SYS_CLOCK_DIV_1 (0) // System clock divided by 1. +#define BSP_CLOCKS_SYS_CLOCK_DIV_2 (1) // System clock divided by 2. +#define BSP_CLOCKS_SYS_CLOCK_DIV_4 (2) // System clock divided by 4. +#define BSP_CLOCKS_SYS_CLOCK_DIV_8 (3) // System clock divided by 8. +#define BSP_CLOCKS_SYS_CLOCK_DIV_16 (4) // System clock divided by 16. +#define BSP_CLOCKS_SYS_CLOCK_DIV_32 (5) // System clock divided by 32. +#define BSP_CLOCKS_SYS_CLOCK_DIV_64 (6) // System clock divided by 64. +#define BSP_CLOCKS_SYS_CLOCK_DIV_128 (7) // System clock divided by 128 (available for CLKOUT only). +#define BSP_CLOCKS_SYS_CLOCK_DIV_3 (8) // System clock divided by 3. +#define BSP_CLOCKS_SYS_CLOCK_DIV_6 (9) // System clock divided by 6. +#define BSP_CLOCKS_SYS_CLOCK_DIV_12 (10) // System clock divided by 12. +#define BSP_CLOCKS_SYS_CLOCK_DIV_24 (11) // System clock divided by 24. + +/* USB clock divider options. */ +#define BSP_CLOCKS_USB_CLOCK_DIV_1 (0) // Divide USB source clock by 1 +#define BSP_CLOCKS_USB_CLOCK_DIV_2 (1) // Divide USB source clock by 2 +#define BSP_CLOCKS_USB_CLOCK_DIV_3 (2) // Divide USB source clock by 3 +#define BSP_CLOCKS_USB_CLOCK_DIV_4 (3) // Divide USB source clock by 4 +#define BSP_CLOCKS_USB_CLOCK_DIV_5 (4) // Divide USB source clock by 5 +#define BSP_CLOCKS_USB_CLOCK_DIV_6 (5) // Divide USB source clock by 6 +#define BSP_CLOCKS_USB_CLOCK_DIV_8 (7) // Divide USB source clock by 8 +#define BSP_CLOCKS_USB_CLOCK_DIV_10 (9) // Divide USB source clock by 10 +#define BSP_CLOCKS_USB_CLOCK_DIV_16 (15) // Divide USB source clock by 16 +#define BSP_CLOCKS_USB_CLOCK_DIV_32 (9) // Divide USB source clock by 32 + +/* USB60 clock divider options. */ +#define BSP_CLOCKS_USB60_CLOCK_DIV_1 (0) // Divide USB60 source clock by 1 +#define BSP_CLOCKS_USB60_CLOCK_DIV_2 (1) // Divide USB60 source clock by 2 +#define BSP_CLOCKS_USB60_CLOCK_DIV_3 (5) // Divide USB60 source clock by 3 +#define BSP_CLOCKS_USB60_CLOCK_DIV_4 (2) // Divide USB60 source clock by 4 +#define BSP_CLOCKS_USB60_CLOCK_DIV_5 (6) // Divide USB60 source clock by 5 +#define BSP_CLOCKS_USB60_CLOCK_DIV_6 (3) // Divide USB66 source clock by 6 +#define BSP_CLOCKS_USB60_CLOCK_DIV_8 (4) // Divide USB60 source clock by 8 +#define BSP_CLOCKS_USB60_CLOCK_DIV_10 (7) // Divide USB60 source clock by 10 +#define BSP_CLOCKS_USB60_CLOCK_DIV_16 (8) // Divide USB60 source clock by 16 +#define BSP_CLOCKS_USB60_CLOCK_DIV_32 (9) // Divide USB60 source clock by 32 + +/* GLCD clock divider options. */ +#define BSP_CLOCKS_LCD_CLOCK_DIV_1 (0) // Divide LCD source clock by 1 +#define BSP_CLOCKS_LCD_CLOCK_DIV_2 (1) // Divide LCD source clock by 2 +#define BSP_CLOCKS_LCD_CLOCK_DIV_3 (5) // Divide LCD source clock by 3 +#define BSP_CLOCKS_LCD_CLOCK_DIV_4 (2) // Divide LCD source clock by 4 +#define BSP_CLOCKS_LCD_CLOCK_DIV_5 (6) // Divide LCD source clock by 5 +#define BSP_CLOCKS_LCD_CLOCK_DIV_6 (3) // Divide LCD source clock by 6 +#define BSP_CLOCKS_LCD_CLOCK_DIV_8 (4) // Divide LCD source clock by 8 +#define BSP_CLOCKS_LCD_CLOCK_DIV_10 (7) // Divide LCD source clock by 10 +#define BSP_CLOCKS_LCD_CLOCK_DIV_16 (8) // Divide LCD source clock by 16 +#define BSP_CLOCKS_LCD_CLOCK_DIV_32 (9) // Divide LCD source clock by 32 + +/* OCTA clock divider options. */ +#define BSP_CLOCKS_OCTA_CLOCK_DIV_1 (0) // Divide OCTA source clock by 1 +#define BSP_CLOCKS_OCTA_CLOCK_DIV_2 (1) // Divide OCTA source clock by 2 +#define BSP_CLOCKS_OCTA_CLOCK_DIV_3 (5) // Divide OCTA source clock by 3 +#define BSP_CLOCKS_OCTA_CLOCK_DIV_4 (2) // Divide OCTA source clock by 4 +#define BSP_CLOCKS_OCTA_CLOCK_DIV_5 (6) // Divide OCTA source clock by 5 +#define BSP_CLOCKS_OCTA_CLOCK_DIV_6 (3) // Divide OCTA source clock by 6 +#define BSP_CLOCKS_OCTA_CLOCK_DIV_8 (4) // Divide OCTA source clock by 8 +#define BSP_CLOCKS_OCTA_CLOCK_DIV_10 (7) // Divide OCTA source clock by 10 +#define BSP_CLOCKS_OCTA_CLOCK_DIV_16 (8) // Divide OCTA source clock by 16 +#define BSP_CLOCKS_OCTA_CLOCK_DIV_32 (9) // Divide OCTA source clock by 32 + +/* CANFD clock divider options. */ +#define BSP_CLOCKS_CANFD_CLOCK_DIV_1 (0) // Divide CANFD source clock by 1 +#define BSP_CLOCKS_CANFD_CLOCK_DIV_2 (1) // Divide CANFD source clock by 2 +#define BSP_CLOCKS_CANFD_CLOCK_DIV_3 (5) // Divide CANFD source clock by 3 +#define BSP_CLOCKS_CANFD_CLOCK_DIV_4 (2) // Divide CANFD source clock by 4 +#define BSP_CLOCKS_CANFD_CLOCK_DIV_5 (6) // Divide CANFD source clock by 5 +#define BSP_CLOCKS_CANFD_CLOCK_DIV_6 (3) // Divide CANFD source clock by 6 +#define BSP_CLOCKS_CANFD_CLOCK_DIV_8 (4) // Divide CANFD source clock by 8 +#define BSP_CLOCKS_CANFD_CLOCK_DIV_10 (7) // Divide CANFD source clock by 10 +#define BSP_CLOCKS_CANFD_CLOCK_DIV_16 (8) // Divide CANFD source clock by 16 +#define BSP_CLOCKS_CANFD_CLOCK_DIV_32 (9) // Divide CANFD source clock by 32 + +/* SCI clock divider options. */ +#define BSP_CLOCKS_SCI_CLOCK_DIV_1 (0) // Divide SCI source clock by 1 +#define BSP_CLOCKS_SCI_CLOCK_DIV_2 (1) // Divide SCI source clock by 2 +#define BSP_CLOCKS_SCI_CLOCK_DIV_3 (5) // Divide SCI source clock by 3 +#define BSP_CLOCKS_SCI_CLOCK_DIV_4 (2) // Divide SCI source clock by 4 +#define BSP_CLOCKS_SCI_CLOCK_DIV_5 (6) // Divide SCI source clock by 5 +#define BSP_CLOCKS_SCI_CLOCK_DIV_6 (3) // Divide SCI source clock by 6 +#define BSP_CLOCKS_SCI_CLOCK_DIV_8 (4) // Divide SCI source clock by 8 +#define BSP_CLOCKS_SCI_CLOCK_DIV_10 (7) // Divide SCI source clock by 10 +#define BSP_CLOCKS_SCI_CLOCK_DIV_16 (8) // Divide SCI source clock by 16 +#define BSP_CLOCKS_SCI_CLOCK_DIV_32 (9) // Divide SCI source clock by 32 + +/* SPI clock divider options. */ +#define BSP_CLOCKS_SPI_CLOCK_DIV_1 (0) // Divide SPI source clock by 1 +#define BSP_CLOCKS_SPI_CLOCK_DIV_2 (1) // Divide SPI source clock by 2 +#define BSP_CLOCKS_SPI_CLOCK_DIV_3 (5) // Divide SPI source clock by 3 +#define BSP_CLOCKS_SPI_CLOCK_DIV_4 (2) // Divide SPI source clock by 4 +#define BSP_CLOCKS_SPI_CLOCK_DIV_5 (6) // Divide SPI source clock by 5 +#define BSP_CLOCKS_SPI_CLOCK_DIV_6 (3) // Divide SPI source clock by 6 +#define BSP_CLOCKS_SPI_CLOCK_DIV_8 (4) // Divide SPI source clock by 8 +#define BSP_CLOCKS_SPI_CLOCK_DIV_10 (7) // Divide SPI source clock by 10 +#define BSP_CLOCKS_SPI_CLOCK_DIV_16 (8) // Divide SPI source clock by 16 +#define BSP_CLOCKS_SPI_CLOCK_DIV_32 (9) // Divide SPI source clock by 32 + +/* SCISPI clock divider options. */ +#define BSP_CLOCKS_SCISPI_CLOCK_DIV_1 (0) // Divide SCISPI source clock by 1 +#define BSP_CLOCKS_SCISPI_CLOCK_DIV_2 (1) // Divide SCISPI source clock by 2 +#define BSP_CLOCKS_SCISPI_CLOCK_DIV_4 (2) // Divide SCISPI source clock by 4 +#define BSP_CLOCKS_SCISPI_CLOCK_DIV_6 (3) // Divide SCISPI source clock by 6 +#define BSP_CLOCKS_SCISPI_CLOCK_DIV_8 (4) // Divide SCISPI source clock by 8 + +/* GPT clock divider options. */ +#define BSP_CLOCKS_GPT_CLOCK_DIV_1 (0) // Divide GPT source clock by 1 +#define BSP_CLOCKS_GPT_CLOCK_DIV_2 (1) // Divide GPT source clock by 2 +#define BSP_CLOCKS_GPT_CLOCK_DIV_3 (5) // Divide GPT source clock by 3 +#define BSP_CLOCKS_GPT_CLOCK_DIV_4 (2) // Divide GPT source clock by 4 +#define BSP_CLOCKS_GPT_CLOCK_DIV_5 (6) // Divide GPT source clock by 5 +#define BSP_CLOCKS_GPT_CLOCK_DIV_6 (3) // Divide GPT source clock by 6 +#define BSP_CLOCKS_GPT_CLOCK_DIV_8 (4) // Divide GPT source clock by 8 +#define BSP_CLOCKS_GPT_CLOCK_DIV_10 (7) // Divide GPT source clock by 10 +#define BSP_CLOCKS_GPT_CLOCK_DIV_16 (8) // Divide GPT source clock by 16 +#define BSP_CLOCKS_GPT_CLOCK_DIV_32 (9) // Divide GPT source clock by 32 + +/* IIC clock divider options. */ +#define BSP_CLOCKS_IIC_CLOCK_DIV_1 (0) // Divide IIC source clock by 1 +#define BSP_CLOCKS_IIC_CLOCK_DIV_2 (1) // Divide IIC source clock by 2 +#define BSP_CLOCKS_IIC_CLOCK_DIV_4 (2) // Divide IIC source clock by 4 +#define BSP_CLOCKS_IIC_CLOCK_DIV_6 (3) // Divide IIC source clock by 6 +#define BSP_CLOCKS_IIC_CLOCK_DIV_8 (4) // Divide IIC source clock by 8 + +/* CEC clock divider options. */ +#define BSP_CLOCKS_CEC_CLOCK_DIV_1 (0) // Divide CEC source clock by 1 +#define BSP_CLOCKS_CEC_CLOCK_DIV_2 (1) // Divide CEC source clock by 2 + +/* I3C clock divider options. */ +#define BSP_CLOCKS_I3C_CLOCK_DIV_1 (0) // Divide I3C source clock by 1 +#define BSP_CLOCKS_I3C_CLOCK_DIV_2 (1) // Divide I3C source clock by 2 +#define BSP_CLOCKS_I3C_CLOCK_DIV_3 (5) // Divide I3C source clock by 3 +#define BSP_CLOCKS_I3C_CLOCK_DIV_4 (2) // Divide I3C source clock by 4 +#define BSP_CLOCKS_I3C_CLOCK_DIV_5 (6) // Divide I3C source clock by 5 +#define BSP_CLOCKS_I3C_CLOCK_DIV_6 (3) // Divide I3C source clock by 6 +#define BSP_CLOCKS_I3C_CLOCK_DIV_8 (4) // Divide I3C source clock by 8 +#define BSP_CLOCKS_I3C_CLOCK_DIV_10 (7) // Divide I3C source clock by 10 +#define BSP_CLOCKS_I3C_CLOCK_DIV_16 (8) // Divide I3C source clock by 16 +#define BSP_CLOCKS_I3C_CLOCK_DIV_32 (9) // Divide I3C source clock by 32 + +/* ADC clock divider options. */ +#define BSP_CLOCKS_ADC_CLOCK_DIV_1 (0) // Divide ADC source clock by 1 +#define BSP_CLOCKS_ADC_CLOCK_DIV_2 (1) // Divide ADC source clock by 2 +#define BSP_CLOCKS_ADC_CLOCK_DIV_3 (5) // Divide ADC source clock by 3 +#define BSP_CLOCKS_ADC_CLOCK_DIV_4 (2) // Divide ADC source clock by 4 +#define BSP_CLOCKS_ADC_CLOCK_DIV_5 (6) // Divide ADC source clock by 5 +#define BSP_CLOCKS_ADC_CLOCK_DIV_6 (3) // Divide ADC source clock by 6 +#define BSP_CLOCKS_ADC_CLOCK_DIV_8 (4) // Divide ADC source clock by 8 +#define BSP_CLOCKS_ADC_CLOCK_DIV_10 (7) // Divide ADC source clock by 10 +#define BSP_CLOCKS_ADC_CLOCK_DIV_16 (8) // Divide ADC source clock by 16 +#define BSP_CLOCKS_ADC_CLOCK_DIV_32 (9) // Divide ADC source clock by 32 + +/* ESW clock divider options. */ +#define BSP_CLOCKS_ESW_CLOCK_DIV_1 (0) // Divide ESW source clock by 1 +#define BSP_CLOCKS_ESW_CLOCK_DIV_2 (1) // Divide ESW source clock by 2 +#define BSP_CLOCKS_ESW_CLOCK_DIV_3 (5) // Divide ESW source clock by 3 +#define BSP_CLOCKS_ESW_CLOCK_DIV_4 (2) // Divide ESW source clock by 4 +#define BSP_CLOCKS_ESW_CLOCK_DIV_5 (6) // Divide ESW source clock by 5 +#define BSP_CLOCKS_ESW_CLOCK_DIV_6 (3) // Divide ESW source clock by 6 +#define BSP_CLOCKS_ESW_CLOCK_DIV_8 (4) // Divide ESW source clock by 8 +#define BSP_CLOCKS_ESW_CLOCK_DIV_10 (7) // Divide ESW source clock by 10 +#define BSP_CLOCKS_ESW_CLOCK_DIV_16 (8) // Divide ESW source clock by 16 +#define BSP_CLOCKS_ESW_CLOCK_DIV_32 (9) // Divide ESW source clock by 32 + +/* ESWPHY clock divider options. */ +#define BSP_CLOCKS_ESWPHY_CLOCK_DIV_1 (0) // Divide ESWPHY source clock by 1 +#define BSP_CLOCKS_ESWPHY_CLOCK_DIV_2 (1) // Divide ESWPHY source clock by 2 +#define BSP_CLOCKS_ESWPHY_CLOCK_DIV_3 (5) // Divide ESWPHY source clock by 3 +#define BSP_CLOCKS_ESWPHY_CLOCK_DIV_4 (2) // Divide ESWPHY source clock by 4 +#define BSP_CLOCKS_ESWPHY_CLOCK_DIV_5 (6) // Divide ESWPHY source clock by 5 +#define BSP_CLOCKS_ESWPHY_CLOCK_DIV_6 (3) // Divide ESWPHY source clock by 6 +#define BSP_CLOCKS_ESWPHY_CLOCK_DIV_8 (4) // Divide ESWPHY source clock by 8 +#define BSP_CLOCKS_ESWPHY_CLOCK_DIV_10 (7) // Divide ESWPHY source clock by 10 +#define BSP_CLOCKS_ESWPHY_CLOCK_DIV_16 (8) // Divide ESWPHY source clock by 16 +#define BSP_CLOCKS_ESWPHY_CLOCK_DIV_32 (9) // Divide ESWPHY source clock by 32 + +/* ETHPHY clock divider options. */ +#define BSP_CLOCKS_ETHPHY_CLOCK_DIV_1 (0) // Divide ETHPHY source clock by 1 +#define BSP_CLOCKS_ETHPHY_CLOCK_DIV_2 (1) // Divide ETHPHY source clock by 2 +#define BSP_CLOCKS_ETHPHY_CLOCK_DIV_3 (5) // Divide ETHPHY source clock by 3 +#define BSP_CLOCKS_ETHPHY_CLOCK_DIV_4 (2) // Divide ETHPHY source clock by 4 +#define BSP_CLOCKS_ETHPHY_CLOCK_DIV_5 (6) // Divide ETHPHY source clock by 5 +#define BSP_CLOCKS_ETHPHY_CLOCK_DIV_6 (3) // Divide ETHPHY source clock by 6 +#define BSP_CLOCKS_ETHPHY_CLOCK_DIV_8 (4) // Divide ETHPHY source clock by 8 +#define BSP_CLOCKS_ETHPHY_CLOCK_DIV_10 (7) // Divide ETHPHY source clock by 10 +#define BSP_CLOCKS_ETHPHY_CLOCK_DIV_16 (8) // Divide ETHPHY source clock by 16 +#define BSP_CLOCKS_ETHPHY_CLOCK_DIV_32 (9) // Divide ETHPHY source clock by 32 + +/* BCLKA clock divider options. */ +#define BSP_CLOCKS_BCLKA_CLOCK_DIV_1 (0) // Divide BCLKA source clock by 1 +#define BSP_CLOCKS_BCLKA_CLOCK_DIV_2 (1) // Divide BCLKA source clock by 2 +#define BSP_CLOCKS_BCLKA_CLOCK_DIV_3 (5) // Divide BCLKA source clock by 3 +#define BSP_CLOCKS_BCLKA_CLOCK_DIV_4 (2) // Divide BCLKA source clock by 4 +#define BSP_CLOCKS_BCLKA_CLOCK_DIV_5 (6) // Divide BCLKA source clock by 5 +#define BSP_CLOCKS_BCLKA_CLOCK_DIV_6 (3) // Divide BCLKA source clock by 6 +#define BSP_CLOCKS_BCLKA_CLOCK_DIV_8 (4) // Divide BCLKA source clock by 8 +#define BSP_CLOCKS_BCLKA_CLOCK_DIV_10 (7) // Divide BCLKA source clock by 10 +#define BSP_CLOCKS_BCLKA_CLOCK_DIV_16 (8) // Divide BCLKA source clock by 16 +#define BSP_CLOCKS_BCLKA_CLOCK_DIV_32 (9) // Divide BCLKA source clock by 32 + +/* SAU clock divider options. */ +#define BSP_CLOCKS_SAU_CLOCK_DIV_1 (0) // Divide SAU source clock by 1 +#define BSP_CLOCKS_SAU_CLOCK_DIV_2 (1) // Divide SAU source clock by 2 +#define BSP_CLOCKS_SAU_CLOCK_DIV_4 (2) // Divide SAU source clock by 4 +#define BSP_CLOCKS_SAU_CLOCK_DIV_8 (3) // Divide SAU source clock by 8 +#define BSP_CLOCKS_SAU_CLOCK_DIV_16 (4) // Divide SAU source clock by 16 +#define BSP_CLOCKS_SAU_CLOCK_DIV_32 (5) // Divide SAU source clock by 32 +#define BSP_CLOCKS_SAU_CLOCK_DIV_64 (6) // Divide SAU source clock by 64 +#define BSP_CLOCKS_SAU_CLOCK_DIV_128 (7) // Divide SAU source clock by 128 +#define BSP_CLOCKS_SAU_CLOCK_DIV_256 (8) // Divide SAU source clock by 256 +#define BSP_CLOCKS_SAU_CLOCK_DIV_512 (9) // Divide SAU source clock by 512 +#define BSP_CLOCKS_SAU_CLOCK_DIV_1024 (10) // Divide SAU source clock by 1024 +#define BSP_CLOCKS_SAU_CLOCK_DIV_2048 (11) // Divide SAU source clock by 2048 +#define BSP_CLOCKS_SAU_CLOCK_DIV_4096 (12) // Divide SAU source clock by 4096 +#define BSP_CLOCKS_SAU_CLOCK_DIV_8192 (13) // Divide SAU source clock by 8192 +#define BSP_CLOCKS_SAU_CLOCK_DIV_16384 (14) // Divide SAU source clock by 16384 +#define BSP_CLOCKS_SAU_CLOCK_DIV_32768 (15) // Divide SAU source clock by 32768 + +/* Extra peripheral 0 clock divider options. */ +#define BSP_CLOCKS_DSMIF_CLOCK_DIV_1 (0) // Divide extra peripheral 0 source clock by 1 +#define BSP_CLOCKS_DSMIF_CLOCK_DIV_2 (1) // Divide extra peripheral 0 source clock by 2 +#define BSP_CLOCKS_DSMIF_CLOCK_DIV_3 (5) // Divide extra peripheral 0 source clock by 3 +#define BSP_CLOCKS_DSMIF_CLOCK_DIV_4 (2) // Divide extra peripheral 0 source clock by 4 +#define BSP_CLOCKS_DSMIF_CLOCK_DIV_5 (6) // Divide extra peripheral 0 source clock by 5 +#define BSP_CLOCKS_DSMIF_CLOCK_DIV_6 (3) // Divide extra peripheral 0 source clock by 6 +#define BSP_CLOCKS_DSMIF_CLOCK_DIV_8 (4) // Divide extra peripheral 0 source clock by 8 +#define BSP_CLOCKS_DSMIF_CLOCK_DIV_10 (7) // Divide extra peripheral 0 source clock by 10 +#define BSP_CLOCKS_DSMIF_CLOCK_DIV_16 (8) // Divide extra peripheral 0 source clock by 16 +#define BSP_CLOCKS_DSMIF_CLOCK_DIV_32 (9) // Divide extra peripheral 0 source clock by 32 + +/* Extra peripheral 1 clock divider options. */ +#define BSP_CLOCKS_ESC_CLOCK_DIV_1 (0) // Divide extra peripheral 1 source clock by 1 +#define BSP_CLOCKS_ESC_CLOCK_DIV_2 (1) // Divide extra peripheral 1 source clock by 2 +#define BSP_CLOCKS_ESC_CLOCK_DIV_3 (5) // Divide extra peripheral 1 source clock by 3 +#define BSP_CLOCKS_ESC_CLOCK_DIV_4 (2) // Divide extra peripheral 1 source clock by 4 +#define BSP_CLOCKS_ESC_CLOCK_DIV_5 (6) // Divide extra peripheral 1 source clock by 5 +#define BSP_CLOCKS_ESC_CLOCK_DIV_6 (3) // Divide extra peripheral 1 source clock by 6 +#define BSP_CLOCKS_ESC_CLOCK_DIV_8 (4) // Divide extra peripheral 1 source clock by 8 +#define BSP_CLOCKS_ESC_CLOCK_DIV_10 (7) // Divide extra peripheral 1 source clock by 10 +#define BSP_CLOCKS_ESC_CLOCK_DIV_16 (8) // Divide extra peripheral 1 source clock by 16 +#define BSP_CLOCKS_ESC_CLOCK_DIV_32 (9) // Divide extra peripheral 1 source clock by 32 + +/* PLL divider options. */ +#define BSP_CLOCKS_PLL_DIV_1 (0) +#define BSP_CLOCKS_PLL_DIV_2 (1) +#define BSP_CLOCKS_PLL_DIV_3 (2) +#define BSP_CLOCKS_PLL_DIV_4 (3) +#define BSP_CLOCKS_PLL_DIV_5 (4) +#define BSP_CLOCKS_PLL_DIV_6 (5) +#define BSP_CLOCKS_PLL_DIV_8 (7) +#define BSP_CLOCKS_PLL_DIV_9 (8) +#define BSP_CLOCKS_PLL_DIV_1_5 (9) +#define BSP_CLOCKS_PLL_DIV_16 (15) + +/* PLL multiplier options. */ +#if (4U == BSP_FEATURE_CGC_PLLCCR_TYPE) + +/* Offset from decimal multiplier to register value for PLLCCR type 4. */ + #define BSP_PRV_CLOCKS_PLL_MUL_INT_OFFSET (574) + +/** + * X=Integer portion of the multiplier. + * Y=Fractional portion of the multiplier. (not used for this PLLCCR type) + */ + #define BSP_CLOCKS_PLL_MUL(X, Y) (X - BSP_PRV_CLOCKS_PLL_MUL_INT_OFFSET) + +#elif (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) && (6U != BSP_FEATURE_CGC_PLLCCR_TYPE) + +/** + * X=Integer portion of the multiplier. + * Y=Fractional portion of the multiplier. + */ + #define BSP_CLOCKS_PLL_MUL(X, Y) (((X) << 1 | ((Y) >= 50U ? 1 : 0)) - 1U) + +#else + + #define BSP_PRV_CLOCKS_PLL_MUL_INT_SHIFT (2U) + #define BSP_PRV_CLOCKS_PLL_MUL_FRAC_MASK (0x3U) + #define BSP_PRV_CLOCKS_PLL_MUL_FRAC_SHIFT (0U) + +/** + * X=Integer portion of the multiplier. + * Y=Fractional portion of the multiplier. + */ + #define BSP_CLOCKS_PLL_MUL(X, Y) ((((X) -1U) << 2UL) | ((Y) == 50U ? 3U : ((Y) / 33UL))) + +#endif + +/* Configuration option used to disable clock output. */ +#define BSP_CLOCKS_CLOCK_DISABLED (0xFFU) + +/* HOCO cycles per microsecond. */ +#define BSP_PRV_HOCO_CYCLES_PER_US (BSP_HOCO_HZ / 1000000U) + +/* Maximum number of delay cycles required to ensure 1 us passes between setting PLLCCR and clearing PLLCR. */ +#if BSP_HOCO_HZ < 48000000U + #define BSP_PRV_MAX_HOCO_CYCLES_PER_US (BSP_PRV_HOCO_CYCLES_PER_US) +#else + #define BSP_PRV_MAX_HOCO_CYCLES_PER_US (48U) +#endif + +/* Create a mask of valid bits in SCKDIVCR. */ +#define BSP_PRV_SCKDIVCR_ICLK_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 24) +#if BSP_FEATURE_CGC_HAS_PCLKD + #define BSP_PRV_SCKDIVCR_PCLKD_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 0) +#else + #define BSP_PRV_SCKDIVCR_PCLKD_MASK (0U) +#endif +#if BSP_FEATURE_CGC_HAS_PCLKC + #define BSP_PRV_SCKDIVCR_PCLKC_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 4) +#else + #define BSP_PRV_SCKDIVCR_PCLKC_MASK (0U) +#endif +#if BSP_FEATURE_CGC_HAS_PCLKB + #define BSP_PRV_SCKDIVCR_PCLKB_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 8) +#else + #define BSP_PRV_SCKDIVCR_PCLKB_MASK (0U) +#endif +#if BSP_FEATURE_CGC_HAS_PCLKA + #define BSP_PRV_SCKDIVCR_PCLKA_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 12) +#else + #define BSP_PRV_SCKDIVCR_PCLKA_MASK (0U) +#endif +#if BSP_FEATURE_CGC_HAS_BCLK || BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB + #define BSP_PRV_SCKDIVCR_BCLK_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 16) +#else + #define BSP_PRV_SCKDIVCR_BCLK_MASK (0U) +#endif +#if BSP_FEATURE_CGC_HAS_PCLKE + #define BSP_PRV_SCKDIVCR_PCLKE_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 24) +#else + #define BSP_PRV_SCKDIVCR_PCLKE_MASK (0U) +#endif +#if BSP_FEATURE_CGC_HAS_FCLK + #define BSP_PRV_SCKDIVCR_FCLK_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 28) +#else + #define BSP_PRV_SCKDIVCR_FCLK_MASK (0U) +#endif +#define BSP_PRV_SCKDIVCR_MASK (BSP_PRV_SCKDIVCR_ICLK_MASK | BSP_PRV_SCKDIVCR_PCLKD_MASK | \ + BSP_PRV_SCKDIVCR_PCLKC_MASK | BSP_PRV_SCKDIVCR_PCLKB_MASK | \ + BSP_PRV_SCKDIVCR_PCLKA_MASK | BSP_PRV_SCKDIVCR_BCLK_MASK | \ + BSP_PRV_SCKDIVCR_PCLKE_MASK | BSP_PRV_SCKDIVCR_FCLK_MASK) + +/* FLL is only used when enabled, present and the subclock is populated. */ +#if BSP_FEATURE_CGC_HAS_FLL && BSP_CFG_FLL_ENABLE && BSP_CLOCK_CFG_SUBCLOCK_POPULATED + #define BSP_PRV_HOCO_USE_FLL (1) + #ifndef BSP_PRV_FLL_STABILIZATION_TIME_US + #define BSP_PRV_FLL_STABILIZATION_TIME_US (1800) + #endif +#else + #define BSP_PRV_HOCO_USE_FLL (0) + #define BSP_PRV_FLL_STABILIZATION_TIME_US (0) +#endif + +#if BSP_FEATURE_RTC_IS_AVAILABLE || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_RTC_HAS_VBTICTLR + #define BSP_PRV_RTC_RESET_DELAY_US (200) +#endif + +/* Operating power control modes. */ +#if BSP_FEATURE_CGC_REGISTER_SET_B + #define BSP_PRV_OPERATING_MODE_LOW_SPEED (1U) // Should match FLMODE low speed + #define BSP_PRV_OPERATING_MODE_MIDDLE_SPEED (2U) // Should match FLMODE middle speed + #define BSP_PRV_OPERATING_MODE_HIGH_SPEED (3U) // Should match FLMODE high speed +#else + #define BSP_PRV_OPERATING_MODE_HIGH_SPEED (0U) // Should match OPCCR OPCM high speed + #define BSP_PRV_OPERATING_MODE_MIDDLE_SPEED (1U) // Should match OPCCR OPCM middle speed + #define BSP_PRV_OPERATING_MODE_LOW_VOLTAGE (2U) // Should match OPCCR OPCM low voltage + #define BSP_PRV_OPERATING_MODE_LOW_SPEED (3U) // Should match OPCCR OPCM low speed +#endif +#define BSP_PRV_OPERATING_MODE_SUBOSC_SPEED (4U) // Can be any value not otherwise used + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#if BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD +typedef struct +{ + uint32_t pll_freq; +} bsp_clock_update_callback_args_t; + + #if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * bsp_clock_update_callback_t)(bsp_clock_update_callback_args_t * + p_callback_args); + #elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile bsp_clock_update_callback_t)(bsp_clock_update_callback_args_t * + p_callback_args); + #endif + +#endif + +/** PLL multiplier values */ +typedef enum e_cgc_pll_mul +{ + CGC_PLL_MUL_4_0 = BSP_CLOCKS_PLL_MUL(4U, 0U), ///< PLL multiplier of 4.00 + CGC_PLL_MUL_4_5 = BSP_CLOCKS_PLL_MUL(4U, 50U), ///< PLL multiplier of 4.50 + CGC_PLL_MUL_5_0 = BSP_CLOCKS_PLL_MUL(5U, 0U), ///< PLL multiplier of 5.00 + CGC_PLL_MUL_5_5 = BSP_CLOCKS_PLL_MUL(5U, 50U), ///< PLL multiplier of 5.50 + CGC_PLL_MUL_6_0 = BSP_CLOCKS_PLL_MUL(6U, 0U), ///< PLL multiplier of 6.00 + CGC_PLL_MUL_6_5 = BSP_CLOCKS_PLL_MUL(6U, 50U), ///< PLL multiplier of 6.50 + CGC_PLL_MUL_7_0 = BSP_CLOCKS_PLL_MUL(7U, 0U), ///< PLL multiplier of 7.00 + CGC_PLL_MUL_7_5 = BSP_CLOCKS_PLL_MUL(7U, 50U), ///< PLL multiplier of 7.50 + CGC_PLL_MUL_8_0 = BSP_CLOCKS_PLL_MUL(8U, 0U), ///< PLL multiplier of 8.00 + CGC_PLL_MUL_8_5 = BSP_CLOCKS_PLL_MUL(8U, 50U), ///< PLL multiplier of 8.50 + CGC_PLL_MUL_9_0 = BSP_CLOCKS_PLL_MUL(9U, 0U), ///< PLL multiplier of 9.00 + CGC_PLL_MUL_9_5 = BSP_CLOCKS_PLL_MUL(9U, 50U), ///< PLL multiplier of 9.50 + CGC_PLL_MUL_10_0 = BSP_CLOCKS_PLL_MUL(10U, 0U), ///< PLL multiplier of 10.00 + CGC_PLL_MUL_10_5 = BSP_CLOCKS_PLL_MUL(10U, 50U), ///< PLL multiplier of 10.50 + CGC_PLL_MUL_11_0 = BSP_CLOCKS_PLL_MUL(11U, 0U), ///< PLL multiplier of 11.00 + CGC_PLL_MUL_11_5 = BSP_CLOCKS_PLL_MUL(11U, 50U), ///< PLL multiplier of 11.50 + CGC_PLL_MUL_12_0 = BSP_CLOCKS_PLL_MUL(12U, 0U), ///< PLL multiplier of 12.00 + CGC_PLL_MUL_12_5 = BSP_CLOCKS_PLL_MUL(12U, 50U), ///< PLL multiplier of 12.50 + CGC_PLL_MUL_13_0 = BSP_CLOCKS_PLL_MUL(13U, 0U), ///< PLL multiplier of 13.00 + CGC_PLL_MUL_13_5 = BSP_CLOCKS_PLL_MUL(13U, 50U), ///< PLL multiplier of 13.50 + CGC_PLL_MUL_14_0 = BSP_CLOCKS_PLL_MUL(14U, 0U), ///< PLL multiplier of 14.00 + CGC_PLL_MUL_14_5 = BSP_CLOCKS_PLL_MUL(14U, 50U), ///< PLL multiplier of 14.50 + CGC_PLL_MUL_15_0 = BSP_CLOCKS_PLL_MUL(15U, 0U), ///< PLL multiplier of 15.00 + CGC_PLL_MUL_15_5 = BSP_CLOCKS_PLL_MUL(15U, 50U), ///< PLL multiplier of 15.50 + CGC_PLL_MUL_16_0 = BSP_CLOCKS_PLL_MUL(16U, 0U), ///< PLL multiplier of 16.00 + CGC_PLL_MUL_16_5 = BSP_CLOCKS_PLL_MUL(16U, 50U), ///< PLL multiplier of 16.50 + CGC_PLL_MUL_17_0 = BSP_CLOCKS_PLL_MUL(17U, 0U), ///< PLL multiplier of 17.00 + CGC_PLL_MUL_17_5 = BSP_CLOCKS_PLL_MUL(17U, 50U), ///< PLL multiplier of 17.50 + CGC_PLL_MUL_18_0 = BSP_CLOCKS_PLL_MUL(18U, 0U), ///< PLL multiplier of 18.00 + CGC_PLL_MUL_18_5 = BSP_CLOCKS_PLL_MUL(18U, 50U), ///< PLL multiplier of 18.50 + CGC_PLL_MUL_19_0 = BSP_CLOCKS_PLL_MUL(19U, 0U), ///< PLL multiplier of 19.00 + CGC_PLL_MUL_19_5 = BSP_CLOCKS_PLL_MUL(19U, 50U), ///< PLL multiplier of 19.50 + CGC_PLL_MUL_20_0 = BSP_CLOCKS_PLL_MUL(20U, 0U), ///< PLL multiplier of 20.00 + CGC_PLL_MUL_20_5 = BSP_CLOCKS_PLL_MUL(20U, 50U), ///< PLL multiplier of 20.50 + CGC_PLL_MUL_21_0 = BSP_CLOCKS_PLL_MUL(21U, 0U), ///< PLL multiplier of 21.00 + CGC_PLL_MUL_21_5 = BSP_CLOCKS_PLL_MUL(21U, 50U), ///< PLL multiplier of 21.50 + CGC_PLL_MUL_22_0 = BSP_CLOCKS_PLL_MUL(22U, 0U), ///< PLL multiplier of 22.00 + CGC_PLL_MUL_22_5 = BSP_CLOCKS_PLL_MUL(22U, 50U), ///< PLL multiplier of 22.50 + CGC_PLL_MUL_23_0 = BSP_CLOCKS_PLL_MUL(23U, 0U), ///< PLL multiplier of 23.00 + CGC_PLL_MUL_23_5 = BSP_CLOCKS_PLL_MUL(23U, 50U), ///< PLL multiplier of 23.50 + CGC_PLL_MUL_24_0 = BSP_CLOCKS_PLL_MUL(24U, 0U), ///< PLL multiplier of 24.00 + CGC_PLL_MUL_24_5 = BSP_CLOCKS_PLL_MUL(24U, 50U), ///< PLL multiplier of 24.50 + CGC_PLL_MUL_25_0 = BSP_CLOCKS_PLL_MUL(25U, 0U), ///< PLL multiplier of 25.00 + CGC_PLL_MUL_25_5 = BSP_CLOCKS_PLL_MUL(25U, 50U), ///< PLL multiplier of 25.50 + CGC_PLL_MUL_26_0 = BSP_CLOCKS_PLL_MUL(26U, 0U), ///< PLL multiplier of 26.00 + CGC_PLL_MUL_26_33 = BSP_CLOCKS_PLL_MUL(26U, 33U), ///< PLL multiplier of 26.33 + CGC_PLL_MUL_26_5 = BSP_CLOCKS_PLL_MUL(26U, 50U), ///< PLL multiplier of 26.50 + CGC_PLL_MUL_26_66 = BSP_CLOCKS_PLL_MUL(26U, 66U), ///< PLL multiplier of 26.66 + CGC_PLL_MUL_27_0 = BSP_CLOCKS_PLL_MUL(27U, 0U), ///< PLL multiplier of 27.00 + CGC_PLL_MUL_27_33 = BSP_CLOCKS_PLL_MUL(27U, 33U), ///< PLL multiplier of 27.33 + CGC_PLL_MUL_27_5 = BSP_CLOCKS_PLL_MUL(27U, 50U), ///< PLL multiplier of 27.50 + CGC_PLL_MUL_27_66 = BSP_CLOCKS_PLL_MUL(27U, 66U), ///< PLL multiplier of 27.66 + CGC_PLL_MUL_28_0 = BSP_CLOCKS_PLL_MUL(28U, 0U), ///< PLL multiplier of 28.00 + CGC_PLL_MUL_28_33 = BSP_CLOCKS_PLL_MUL(28U, 33U), ///< PLL multiplier of 28.33 + CGC_PLL_MUL_28_5 = BSP_CLOCKS_PLL_MUL(28U, 50U), ///< PLL multiplier of 28.50 + CGC_PLL_MUL_28_66 = BSP_CLOCKS_PLL_MUL(28U, 66U), ///< PLL multiplier of 28.66 + CGC_PLL_MUL_29_0 = BSP_CLOCKS_PLL_MUL(29U, 0U), ///< PLL multiplier of 29.00 + CGC_PLL_MUL_29_33 = BSP_CLOCKS_PLL_MUL(29U, 33U), ///< PLL multiplier of 29.33 + CGC_PLL_MUL_29_5 = BSP_CLOCKS_PLL_MUL(29U, 50U), ///< PLL multiplier of 29.50 + CGC_PLL_MUL_29_66 = BSP_CLOCKS_PLL_MUL(29U, 66U), ///< PLL multiplier of 29.66 + CGC_PLL_MUL_30_0 = BSP_CLOCKS_PLL_MUL(30U, 0U), ///< PLL multiplier of 30.00 + CGC_PLL_MUL_30_33 = BSP_CLOCKS_PLL_MUL(30U, 33U), ///< PLL multiplier of 30.33 + CGC_PLL_MUL_30_5 = BSP_CLOCKS_PLL_MUL(30U, 50U), ///< PLL multiplier of 30.50 + CGC_PLL_MUL_30_66 = BSP_CLOCKS_PLL_MUL(30U, 66U), ///< PLL multiplier of 30.66 + CGC_PLL_MUL_31_0 = BSP_CLOCKS_PLL_MUL(31U, 0U), ///< PLL multiplier of 31.00 + CGC_PLL_MUL_31_33 = BSP_CLOCKS_PLL_MUL(31U, 33U), ///< PLL multiplier of 31.33 + CGC_PLL_MUL_31_5 = BSP_CLOCKS_PLL_MUL(31U, 50U), ///< PLL multiplier of 31.50 + CGC_PLL_MUL_31_66 = BSP_CLOCKS_PLL_MUL(31U, 66U), ///< PLL multiplier of 31.66 + CGC_PLL_MUL_32_0 = BSP_CLOCKS_PLL_MUL(32U, 0U), ///< PLL multiplier of 32.00 + CGC_PLL_MUL_32_33 = BSP_CLOCKS_PLL_MUL(32U, 33U), ///< PLL multiplier of 32.33 + CGC_PLL_MUL_32_5 = BSP_CLOCKS_PLL_MUL(32U, 50U), ///< PLL multiplier of 32.50 + CGC_PLL_MUL_32_66 = BSP_CLOCKS_PLL_MUL(32U, 66U), ///< PLL multiplier of 32.66 + CGC_PLL_MUL_33_0 = BSP_CLOCKS_PLL_MUL(33U, 0U), ///< PLL multiplier of 33.00 + CGC_PLL_MUL_33_33 = BSP_CLOCKS_PLL_MUL(33U, 33U), ///< PLL multiplier of 33.33 + CGC_PLL_MUL_33_5 = BSP_CLOCKS_PLL_MUL(33U, 50U), ///< PLL multiplier of 33.50 + CGC_PLL_MUL_33_66 = BSP_CLOCKS_PLL_MUL(33U, 66U), ///< PLL multiplier of 33.66 + CGC_PLL_MUL_34_0 = BSP_CLOCKS_PLL_MUL(34U, 0U), ///< PLL multiplier of 34.00 + CGC_PLL_MUL_34_33 = BSP_CLOCKS_PLL_MUL(34U, 33U), ///< PLL multiplier of 34.33 + CGC_PLL_MUL_34_5 = BSP_CLOCKS_PLL_MUL(34U, 50U), ///< PLL multiplier of 34.50 + CGC_PLL_MUL_34_66 = BSP_CLOCKS_PLL_MUL(34U, 66U), ///< PLL multiplier of 34.66 + CGC_PLL_MUL_35_0 = BSP_CLOCKS_PLL_MUL(35U, 0U), ///< PLL multiplier of 35.00 + CGC_PLL_MUL_35_33 = BSP_CLOCKS_PLL_MUL(35U, 33U), ///< PLL multiplier of 35.33 + CGC_PLL_MUL_35_5 = BSP_CLOCKS_PLL_MUL(35U, 50U), ///< PLL multiplier of 35.50 + CGC_PLL_MUL_35_66 = BSP_CLOCKS_PLL_MUL(35U, 66U), ///< PLL multiplier of 35.66 + CGC_PLL_MUL_36_0 = BSP_CLOCKS_PLL_MUL(36U, 0U), ///< PLL multiplier of 36.00 + CGC_PLL_MUL_36_33 = BSP_CLOCKS_PLL_MUL(36U, 33U), ///< PLL multiplier of 36.33 + CGC_PLL_MUL_36_5 = BSP_CLOCKS_PLL_MUL(36U, 50U), ///< PLL multiplier of 36.50 + CGC_PLL_MUL_36_66 = BSP_CLOCKS_PLL_MUL(36U, 66U), ///< PLL multiplier of 36.66 + CGC_PLL_MUL_37_0 = BSP_CLOCKS_PLL_MUL(37U, 0U), ///< PLL multiplier of 37.00 + CGC_PLL_MUL_37_33 = BSP_CLOCKS_PLL_MUL(37U, 33U), ///< PLL multiplier of 37.33 + CGC_PLL_MUL_37_5 = BSP_CLOCKS_PLL_MUL(37U, 50U), ///< PLL multiplier of 37.50 + CGC_PLL_MUL_37_66 = BSP_CLOCKS_PLL_MUL(37U, 66U), ///< PLL multiplier of 37.66 + CGC_PLL_MUL_38_0 = BSP_CLOCKS_PLL_MUL(38U, 0U), ///< PLL multiplier of 38.00 + CGC_PLL_MUL_38_33 = BSP_CLOCKS_PLL_MUL(38U, 33U), ///< PLL multiplier of 38.33 + CGC_PLL_MUL_38_5 = BSP_CLOCKS_PLL_MUL(38U, 50U), ///< PLL multiplier of 38.50 + CGC_PLL_MUL_38_66 = BSP_CLOCKS_PLL_MUL(38U, 66U), ///< PLL multiplier of 38.66 + CGC_PLL_MUL_39_0 = BSP_CLOCKS_PLL_MUL(39U, 0U), ///< PLL multiplier of 39.00 + CGC_PLL_MUL_39_33 = BSP_CLOCKS_PLL_MUL(39U, 33U), ///< PLL multiplier of 39.33 + CGC_PLL_MUL_39_5 = BSP_CLOCKS_PLL_MUL(39U, 50U), ///< PLL multiplier of 39.50 + CGC_PLL_MUL_39_66 = BSP_CLOCKS_PLL_MUL(39U, 66U), ///< PLL multiplier of 39.66 + CGC_PLL_MUL_40_0 = BSP_CLOCKS_PLL_MUL(40U, 0U), ///< PLL multiplier of 40.00 + CGC_PLL_MUL_40_33 = BSP_CLOCKS_PLL_MUL(40U, 33U), ///< PLL multiplier of 40.33 + CGC_PLL_MUL_40_5 = BSP_CLOCKS_PLL_MUL(40U, 50U), ///< PLL multiplier of 40.50 + CGC_PLL_MUL_40_66 = BSP_CLOCKS_PLL_MUL(40U, 66U), ///< PLL multiplier of 40.66 + CGC_PLL_MUL_41_0 = BSP_CLOCKS_PLL_MUL(41U, 0U), ///< PLL multiplier of 41.00 + CGC_PLL_MUL_41_33 = BSP_CLOCKS_PLL_MUL(41U, 33U), ///< PLL multiplier of 41.33 + CGC_PLL_MUL_41_5 = BSP_CLOCKS_PLL_MUL(41U, 50U), ///< PLL multiplier of 41.50 + CGC_PLL_MUL_41_66 = BSP_CLOCKS_PLL_MUL(41U, 66U), ///< PLL multiplier of 41.66 + CGC_PLL_MUL_42_0 = BSP_CLOCKS_PLL_MUL(42U, 0U), ///< PLL multiplier of 42.00 + CGC_PLL_MUL_42_33 = BSP_CLOCKS_PLL_MUL(42U, 33U), ///< PLL multiplier of 42.33 + CGC_PLL_MUL_42_5 = BSP_CLOCKS_PLL_MUL(42U, 50U), ///< PLL multiplier of 42.50 + CGC_PLL_MUL_42_66 = BSP_CLOCKS_PLL_MUL(42U, 66U), ///< PLL multiplier of 42.66 + CGC_PLL_MUL_43_0 = BSP_CLOCKS_PLL_MUL(43U, 0U), ///< PLL multiplier of 43.00 + CGC_PLL_MUL_43_33 = BSP_CLOCKS_PLL_MUL(43U, 33U), ///< PLL multiplier of 43.33 + CGC_PLL_MUL_43_5 = BSP_CLOCKS_PLL_MUL(43U, 50U), ///< PLL multiplier of 43.50 + CGC_PLL_MUL_43_66 = BSP_CLOCKS_PLL_MUL(43U, 66U), ///< PLL multiplier of 43.66 + CGC_PLL_MUL_44_0 = BSP_CLOCKS_PLL_MUL(44U, 0U), ///< PLL multiplier of 44.00 + CGC_PLL_MUL_44_33 = BSP_CLOCKS_PLL_MUL(44U, 33U), ///< PLL multiplier of 44.33 + CGC_PLL_MUL_44_5 = BSP_CLOCKS_PLL_MUL(44U, 50U), ///< PLL multiplier of 44.50 + CGC_PLL_MUL_44_66 = BSP_CLOCKS_PLL_MUL(44U, 66U), ///< PLL multiplier of 44.66 + CGC_PLL_MUL_45_0 = BSP_CLOCKS_PLL_MUL(45U, 0U), ///< PLL multiplier of 45.00 + CGC_PLL_MUL_45_33 = BSP_CLOCKS_PLL_MUL(45U, 33U), ///< PLL multiplier of 45.33 + CGC_PLL_MUL_45_5 = BSP_CLOCKS_PLL_MUL(45U, 50U), ///< PLL multiplier of 45.50 + CGC_PLL_MUL_45_66 = BSP_CLOCKS_PLL_MUL(45U, 66U), ///< PLL multiplier of 45.66 + CGC_PLL_MUL_46_0 = BSP_CLOCKS_PLL_MUL(46U, 0U), ///< PLL multiplier of 46.00 + CGC_PLL_MUL_46_33 = BSP_CLOCKS_PLL_MUL(46U, 33U), ///< PLL multiplier of 46.33 + CGC_PLL_MUL_46_5 = BSP_CLOCKS_PLL_MUL(46U, 50U), ///< PLL multiplier of 46.50 + CGC_PLL_MUL_46_66 = BSP_CLOCKS_PLL_MUL(46U, 66U), ///< PLL multiplier of 46.66 + CGC_PLL_MUL_47_0 = BSP_CLOCKS_PLL_MUL(47U, 0U), ///< PLL multiplier of 47.00 + CGC_PLL_MUL_47_33 = BSP_CLOCKS_PLL_MUL(47U, 33U), ///< PLL multiplier of 47.33 + CGC_PLL_MUL_47_5 = BSP_CLOCKS_PLL_MUL(47U, 50U), ///< PLL multiplier of 47.50 + CGC_PLL_MUL_47_66 = BSP_CLOCKS_PLL_MUL(47U, 66U), ///< PLL multiplier of 47.66 + CGC_PLL_MUL_48_0 = BSP_CLOCKS_PLL_MUL(48U, 0U), ///< PLL multiplier of 48.00 + CGC_PLL_MUL_48_33 = BSP_CLOCKS_PLL_MUL(48U, 33U), ///< PLL multiplier of 48.33 + CGC_PLL_MUL_48_5 = BSP_CLOCKS_PLL_MUL(48U, 50U), ///< PLL multiplier of 48.50 + CGC_PLL_MUL_48_66 = BSP_CLOCKS_PLL_MUL(48U, 66U), ///< PLL multiplier of 48.66 + CGC_PLL_MUL_49_0 = BSP_CLOCKS_PLL_MUL(49U, 0U), ///< PLL multiplier of 49.00 + CGC_PLL_MUL_49_33 = BSP_CLOCKS_PLL_MUL(49U, 33U), ///< PLL multiplier of 49.33 + CGC_PLL_MUL_49_5 = BSP_CLOCKS_PLL_MUL(49U, 50U), ///< PLL multiplier of 49.50 + CGC_PLL_MUL_49_66 = BSP_CLOCKS_PLL_MUL(49U, 66U), ///< PLL multiplier of 49.66 + CGC_PLL_MUL_50_0 = BSP_CLOCKS_PLL_MUL(50U, 0U), ///< PLL multiplier of 50.00 + CGC_PLL_MUL_50_33 = BSP_CLOCKS_PLL_MUL(50U, 33U), ///< PLL multiplier of 50.33 + CGC_PLL_MUL_50_5 = BSP_CLOCKS_PLL_MUL(50U, 50U), ///< PLL multiplier of 50.50 + CGC_PLL_MUL_50_66 = BSP_CLOCKS_PLL_MUL(50U, 66U), ///< PLL multiplier of 50.66 + CGC_PLL_MUL_51_0 = BSP_CLOCKS_PLL_MUL(51U, 0U), ///< PLL multiplier of 51.00 + CGC_PLL_MUL_51_33 = BSP_CLOCKS_PLL_MUL(51U, 33U), ///< PLL multiplier of 51.33 + CGC_PLL_MUL_51_5 = BSP_CLOCKS_PLL_MUL(51U, 50U), ///< PLL multiplier of 51.50 + CGC_PLL_MUL_51_66 = BSP_CLOCKS_PLL_MUL(51U, 66U), ///< PLL multiplier of 51.66 + CGC_PLL_MUL_52_0 = BSP_CLOCKS_PLL_MUL(52U, 0U), ///< PLL multiplier of 52.00 + CGC_PLL_MUL_52_33 = BSP_CLOCKS_PLL_MUL(52U, 33U), ///< PLL multiplier of 52.33 + CGC_PLL_MUL_52_5 = BSP_CLOCKS_PLL_MUL(52U, 50U), ///< PLL multiplier of 52.50 + CGC_PLL_MUL_52_66 = BSP_CLOCKS_PLL_MUL(52U, 66U), ///< PLL multiplier of 52.66 + CGC_PLL_MUL_53_0 = BSP_CLOCKS_PLL_MUL(53U, 0U), ///< PLL multiplier of 53.00 + CGC_PLL_MUL_53_33 = BSP_CLOCKS_PLL_MUL(53U, 33U), ///< PLL multiplier of 53.33 + CGC_PLL_MUL_53_5 = BSP_CLOCKS_PLL_MUL(53U, 50U), ///< PLL multiplier of 53.50 + CGC_PLL_MUL_53_66 = BSP_CLOCKS_PLL_MUL(53U, 66U), ///< PLL multiplier of 53.66 + CGC_PLL_MUL_54_0 = BSP_CLOCKS_PLL_MUL(54U, 0U), ///< PLL multiplier of 54.00 + CGC_PLL_MUL_54_33 = BSP_CLOCKS_PLL_MUL(54U, 33U), ///< PLL multiplier of 54.33 + CGC_PLL_MUL_54_5 = BSP_CLOCKS_PLL_MUL(54U, 50U), ///< PLL multiplier of 54.50 + CGC_PLL_MUL_54_66 = BSP_CLOCKS_PLL_MUL(54U, 66U), ///< PLL multiplier of 54.66 + CGC_PLL_MUL_55_0 = BSP_CLOCKS_PLL_MUL(55U, 0U), ///< PLL multiplier of 55.00 + CGC_PLL_MUL_55_33 = BSP_CLOCKS_PLL_MUL(55U, 33U), ///< PLL multiplier of 55.33 + CGC_PLL_MUL_55_5 = BSP_CLOCKS_PLL_MUL(55U, 50U), ///< PLL multiplier of 55.50 + CGC_PLL_MUL_55_66 = BSP_CLOCKS_PLL_MUL(55U, 66U), ///< PLL multiplier of 55.66 + CGC_PLL_MUL_56_0 = BSP_CLOCKS_PLL_MUL(56U, 0U), ///< PLL multiplier of 56.00 + CGC_PLL_MUL_56_33 = BSP_CLOCKS_PLL_MUL(56U, 33U), ///< PLL multiplier of 56.33 + CGC_PLL_MUL_56_5 = BSP_CLOCKS_PLL_MUL(56U, 50U), ///< PLL multiplier of 56.50 + CGC_PLL_MUL_56_66 = BSP_CLOCKS_PLL_MUL(56U, 66U), ///< PLL multiplier of 56.66 + CGC_PLL_MUL_57_0 = BSP_CLOCKS_PLL_MUL(57U, 0U), ///< PLL multiplier of 57.00 + CGC_PLL_MUL_57_33 = BSP_CLOCKS_PLL_MUL(57U, 33U), ///< PLL multiplier of 57.33 + CGC_PLL_MUL_57_5 = BSP_CLOCKS_PLL_MUL(57U, 50U), ///< PLL multiplier of 57.50 + CGC_PLL_MUL_57_66 = BSP_CLOCKS_PLL_MUL(57U, 66U), ///< PLL multiplier of 57.66 + CGC_PLL_MUL_58_0 = BSP_CLOCKS_PLL_MUL(58U, 0U), ///< PLL multiplier of 58.00 + CGC_PLL_MUL_58_33 = BSP_CLOCKS_PLL_MUL(58U, 33U), ///< PLL multiplier of 58.33 + CGC_PLL_MUL_58_5 = BSP_CLOCKS_PLL_MUL(58U, 50U), ///< PLL multiplier of 58.50 + CGC_PLL_MUL_58_66 = BSP_CLOCKS_PLL_MUL(58U, 66U), ///< PLL multiplier of 58.66 + CGC_PLL_MUL_59_0 = BSP_CLOCKS_PLL_MUL(59U, 0U), ///< PLL multiplier of 59.00 + CGC_PLL_MUL_59_33 = BSP_CLOCKS_PLL_MUL(59U, 33U), ///< PLL multiplier of 59.33 + CGC_PLL_MUL_59_5 = BSP_CLOCKS_PLL_MUL(59U, 50U), ///< PLL multiplier of 59.50 + CGC_PLL_MUL_59_66 = BSP_CLOCKS_PLL_MUL(59U, 66U), ///< PLL multiplier of 59.66 + CGC_PLL_MUL_60_0 = BSP_CLOCKS_PLL_MUL(60U, 0U), ///< PLL multiplier of 60.00 + CGC_PLL_MUL_60_33 = BSP_CLOCKS_PLL_MUL(60U, 33U), ///< PLL multiplier of 60.33 + CGC_PLL_MUL_60_5 = BSP_CLOCKS_PLL_MUL(60U, 50U), ///< PLL multiplier of 60.50 + CGC_PLL_MUL_60_66 = BSP_CLOCKS_PLL_MUL(60U, 66U), ///< PLL multiplier of 60.66 + CGC_PLL_MUL_61_0 = BSP_CLOCKS_PLL_MUL(61U, 0U), ///< PLL multiplier of 61.00 + CGC_PLL_MUL_61_33 = BSP_CLOCKS_PLL_MUL(61U, 33U), ///< PLL multiplier of 61.33 + CGC_PLL_MUL_61_5 = BSP_CLOCKS_PLL_MUL(61U, 50U), ///< PLL multiplier of 61.50 + CGC_PLL_MUL_61_66 = BSP_CLOCKS_PLL_MUL(61U, 66U), ///< PLL multiplier of 61.66 + CGC_PLL_MUL_62_0 = BSP_CLOCKS_PLL_MUL(62U, 0U), ///< PLL multiplier of 62.00 + CGC_PLL_MUL_62_33 = BSP_CLOCKS_PLL_MUL(62U, 33U), ///< PLL multiplier of 62.33 + CGC_PLL_MUL_62_5 = BSP_CLOCKS_PLL_MUL(62U, 50U), ///< PLL multiplier of 62.50 + CGC_PLL_MUL_62_66 = BSP_CLOCKS_PLL_MUL(62U, 66U), ///< PLL multiplier of 62.66 + CGC_PLL_MUL_63_0 = BSP_CLOCKS_PLL_MUL(63U, 0U), ///< PLL multiplier of 63.00 + CGC_PLL_MUL_63_33 = BSP_CLOCKS_PLL_MUL(63U, 33U), ///< PLL multiplier of 63.33 + CGC_PLL_MUL_63_5 = BSP_CLOCKS_PLL_MUL(63U, 50U), ///< PLL multiplier of 63.50 + CGC_PLL_MUL_63_66 = BSP_CLOCKS_PLL_MUL(63U, 66U), ///< PLL multiplier of 63.66 + CGC_PLL_MUL_64_0 = BSP_CLOCKS_PLL_MUL(64U, 0U), ///< PLL multiplier of 64.00 + CGC_PLL_MUL_64_33 = BSP_CLOCKS_PLL_MUL(64U, 33U), ///< PLL multiplier of 64.33 + CGC_PLL_MUL_64_5 = BSP_CLOCKS_PLL_MUL(64U, 50U), ///< PLL multiplier of 64.50 + CGC_PLL_MUL_64_66 = BSP_CLOCKS_PLL_MUL(64U, 66U), ///< PLL multiplier of 64.66 + CGC_PLL_MUL_65_0 = BSP_CLOCKS_PLL_MUL(65U, 0U), ///< PLL multiplier of 65.00 + CGC_PLL_MUL_65_33 = BSP_CLOCKS_PLL_MUL(65U, 33U), ///< PLL multiplier of 65.33 + CGC_PLL_MUL_65_5 = BSP_CLOCKS_PLL_MUL(65U, 50U), ///< PLL multiplier of 65.50 + CGC_PLL_MUL_65_66 = BSP_CLOCKS_PLL_MUL(65U, 66U), ///< PLL multiplier of 65.66 + CGC_PLL_MUL_66_0 = BSP_CLOCKS_PLL_MUL(66U, 0U), ///< PLL multiplier of 66.00 + CGC_PLL_MUL_66_33 = BSP_CLOCKS_PLL_MUL(66U, 33U), ///< PLL multiplier of 66.33 + CGC_PLL_MUL_66_5 = BSP_CLOCKS_PLL_MUL(66U, 50U), ///< PLL multiplier of 66.50 + CGC_PLL_MUL_66_66 = BSP_CLOCKS_PLL_MUL(66U, 66U), ///< PLL multiplier of 66.66 + CGC_PLL_MUL_67_0 = BSP_CLOCKS_PLL_MUL(67U, 0U), ///< PLL multiplier of 67.00 + CGC_PLL_MUL_67_33 = BSP_CLOCKS_PLL_MUL(67U, 33U), ///< PLL multiplier of 67.33 + CGC_PLL_MUL_67_5 = BSP_CLOCKS_PLL_MUL(67U, 50U), ///< PLL multiplier of 67.50 + CGC_PLL_MUL_67_66 = BSP_CLOCKS_PLL_MUL(67U, 66U), ///< PLL multiplier of 67.66 + CGC_PLL_MUL_68_0 = BSP_CLOCKS_PLL_MUL(68U, 0U), ///< PLL multiplier of 68.00 + CGC_PLL_MUL_68_33 = BSP_CLOCKS_PLL_MUL(68U, 33U), ///< PLL multiplier of 68.33 + CGC_PLL_MUL_68_5 = BSP_CLOCKS_PLL_MUL(68U, 50U), ///< PLL multiplier of 68.50 + CGC_PLL_MUL_68_66 = BSP_CLOCKS_PLL_MUL(68U, 66U), ///< PLL multiplier of 68.66 + CGC_PLL_MUL_69_0 = BSP_CLOCKS_PLL_MUL(69U, 0U), ///< PLL multiplier of 69.00 + CGC_PLL_MUL_69_33 = BSP_CLOCKS_PLL_MUL(69U, 33U), ///< PLL multiplier of 69.33 + CGC_PLL_MUL_69_5 = BSP_CLOCKS_PLL_MUL(69U, 50U), ///< PLL multiplier of 69.50 + CGC_PLL_MUL_69_66 = BSP_CLOCKS_PLL_MUL(69U, 66U), ///< PLL multiplier of 69.66 + CGC_PLL_MUL_70_0 = BSP_CLOCKS_PLL_MUL(70U, 0U), ///< PLL multiplier of 70.00 + CGC_PLL_MUL_70_33 = BSP_CLOCKS_PLL_MUL(70U, 33U), ///< PLL multiplier of 70.33 + CGC_PLL_MUL_70_5 = BSP_CLOCKS_PLL_MUL(70U, 50U), ///< PLL multiplier of 70.50 + CGC_PLL_MUL_70_66 = BSP_CLOCKS_PLL_MUL(70U, 66U), ///< PLL multiplier of 70.66 + CGC_PLL_MUL_71_0 = BSP_CLOCKS_PLL_MUL(71U, 0U), ///< PLL multiplier of 71.00 + CGC_PLL_MUL_71_33 = BSP_CLOCKS_PLL_MUL(71U, 33U), ///< PLL multiplier of 71.33 + CGC_PLL_MUL_71_5 = BSP_CLOCKS_PLL_MUL(71U, 50U), ///< PLL multiplier of 71.50 + CGC_PLL_MUL_71_66 = BSP_CLOCKS_PLL_MUL(71U, 66U), ///< PLL multiplier of 71.66 + CGC_PLL_MUL_72_0 = BSP_CLOCKS_PLL_MUL(72U, 0U), ///< PLL multiplier of 72.00 + CGC_PLL_MUL_72_33 = BSP_CLOCKS_PLL_MUL(72U, 33U), ///< PLL multiplier of 72.33 + CGC_PLL_MUL_72_5 = BSP_CLOCKS_PLL_MUL(72U, 50U), ///< PLL multiplier of 72.50 + CGC_PLL_MUL_72_66 = BSP_CLOCKS_PLL_MUL(72U, 66U), ///< PLL multiplier of 72.66 + CGC_PLL_MUL_73_0 = BSP_CLOCKS_PLL_MUL(73U, 0U), ///< PLL multiplier of 73.00 + CGC_PLL_MUL_73_33 = BSP_CLOCKS_PLL_MUL(73U, 33U), ///< PLL multiplier of 73.33 + CGC_PLL_MUL_73_5 = BSP_CLOCKS_PLL_MUL(73U, 50U), ///< PLL multiplier of 73.50 + CGC_PLL_MUL_73_66 = BSP_CLOCKS_PLL_MUL(73U, 66U), ///< PLL multiplier of 73.66 + CGC_PLL_MUL_74_0 = BSP_CLOCKS_PLL_MUL(74U, 0U), ///< PLL multiplier of 74.00 + CGC_PLL_MUL_74_33 = BSP_CLOCKS_PLL_MUL(74U, 33U), ///< PLL multiplier of 74.33 + CGC_PLL_MUL_74_5 = BSP_CLOCKS_PLL_MUL(74U, 50U), ///< PLL multiplier of 74.50 + CGC_PLL_MUL_74_66 = BSP_CLOCKS_PLL_MUL(74U, 66U), ///< PLL multiplier of 74.66 + CGC_PLL_MUL_75_0 = BSP_CLOCKS_PLL_MUL(75U, 0U), ///< PLL multiplier of 75.00 + CGC_PLL_MUL_75_33 = BSP_CLOCKS_PLL_MUL(75U, 33U), ///< PLL multiplier of 75.33 + CGC_PLL_MUL_75_5 = BSP_CLOCKS_PLL_MUL(75U, 50U), ///< PLL multiplier of 75.50 + CGC_PLL_MUL_75_66 = BSP_CLOCKS_PLL_MUL(75U, 66U), ///< PLL multiplier of 75.66 + CGC_PLL_MUL_76_0 = BSP_CLOCKS_PLL_MUL(76U, 0U), ///< PLL multiplier of 76.00 + CGC_PLL_MUL_76_33 = BSP_CLOCKS_PLL_MUL(76U, 33U), ///< PLL multiplier of 76.33 + CGC_PLL_MUL_76_5 = BSP_CLOCKS_PLL_MUL(76U, 50U), ///< PLL multiplier of 76.50 + CGC_PLL_MUL_76_66 = BSP_CLOCKS_PLL_MUL(76U, 66U), ///< PLL multiplier of 76.66 + CGC_PLL_MUL_77_0 = BSP_CLOCKS_PLL_MUL(77U, 0U), ///< PLL multiplier of 77.00 + CGC_PLL_MUL_77_33 = BSP_CLOCKS_PLL_MUL(77U, 33U), ///< PLL multiplier of 77.33 + CGC_PLL_MUL_77_5 = BSP_CLOCKS_PLL_MUL(77U, 50U), ///< PLL multiplier of 77.50 + CGC_PLL_MUL_77_66 = BSP_CLOCKS_PLL_MUL(77U, 66U), ///< PLL multiplier of 77.66 + CGC_PLL_MUL_78_0 = BSP_CLOCKS_PLL_MUL(78U, 0U), ///< PLL multiplier of 78.00 + CGC_PLL_MUL_78_33 = BSP_CLOCKS_PLL_MUL(78U, 33U), ///< PLL multiplier of 78.33 + CGC_PLL_MUL_78_5 = BSP_CLOCKS_PLL_MUL(78U, 50U), ///< PLL multiplier of 78.50 + CGC_PLL_MUL_78_66 = BSP_CLOCKS_PLL_MUL(78U, 66U), ///< PLL multiplier of 78.66 + CGC_PLL_MUL_79_0 = BSP_CLOCKS_PLL_MUL(79U, 0U), ///< PLL multiplier of 79.00 + CGC_PLL_MUL_79_33 = BSP_CLOCKS_PLL_MUL(79U, 33U), ///< PLL multiplier of 79.33 + CGC_PLL_MUL_79_5 = BSP_CLOCKS_PLL_MUL(79U, 50U), ///< PLL multiplier of 79.50 + CGC_PLL_MUL_79_66 = BSP_CLOCKS_PLL_MUL(79U, 66U), ///< PLL multiplier of 79.66 + CGC_PLL_MUL_80_0 = BSP_CLOCKS_PLL_MUL(80U, 0U), ///< PLL multiplier of 80.00 + CGC_PLL_MUL_80_33 = BSP_CLOCKS_PLL_MUL(80U, 33U), ///< PLL multiplier of 80.33 + CGC_PLL_MUL_80_5 = BSP_CLOCKS_PLL_MUL(80U, 50U), ///< PLL multiplier of 80.50 + CGC_PLL_MUL_80_66 = BSP_CLOCKS_PLL_MUL(80U, 66U), ///< PLL multiplier of 80.66 + CGC_PLL_MUL_81_0 = BSP_CLOCKS_PLL_MUL(81U, 0U), ///< PLL multiplier of 81.00 + CGC_PLL_MUL_81_33 = BSP_CLOCKS_PLL_MUL(81U, 33U), ///< PLL multiplier of 81.33 + CGC_PLL_MUL_81_5 = BSP_CLOCKS_PLL_MUL(81U, 50U), ///< PLL multiplier of 81.50 + CGC_PLL_MUL_81_66 = BSP_CLOCKS_PLL_MUL(81U, 66U), ///< PLL multiplier of 81.66 + CGC_PLL_MUL_82_0 = BSP_CLOCKS_PLL_MUL(82U, 0U), ///< PLL multiplier of 82.00 + CGC_PLL_MUL_82_33 = BSP_CLOCKS_PLL_MUL(82U, 33U), ///< PLL multiplier of 82.33 + CGC_PLL_MUL_82_5 = BSP_CLOCKS_PLL_MUL(82U, 50U), ///< PLL multiplier of 82.50 + CGC_PLL_MUL_82_66 = BSP_CLOCKS_PLL_MUL(82U, 66U), ///< PLL multiplier of 82.66 + CGC_PLL_MUL_83_0 = BSP_CLOCKS_PLL_MUL(83U, 0U), ///< PLL multiplier of 83.00 + CGC_PLL_MUL_83_33 = BSP_CLOCKS_PLL_MUL(83U, 33U), ///< PLL multiplier of 83.33 + CGC_PLL_MUL_83_5 = BSP_CLOCKS_PLL_MUL(83U, 50U), ///< PLL multiplier of 83.50 + CGC_PLL_MUL_83_66 = BSP_CLOCKS_PLL_MUL(83U, 66U), ///< PLL multiplier of 83.66 + CGC_PLL_MUL_84_0 = BSP_CLOCKS_PLL_MUL(84U, 0U), ///< PLL multiplier of 84.00 + CGC_PLL_MUL_84_33 = BSP_CLOCKS_PLL_MUL(84U, 33U), ///< PLL multiplier of 84.33 + CGC_PLL_MUL_84_5 = BSP_CLOCKS_PLL_MUL(84U, 50U), ///< PLL multiplier of 84.50 + CGC_PLL_MUL_84_66 = BSP_CLOCKS_PLL_MUL(84U, 66U), ///< PLL multiplier of 84.66 + CGC_PLL_MUL_85_0 = BSP_CLOCKS_PLL_MUL(85U, 0U), ///< PLL multiplier of 85.00 + CGC_PLL_MUL_85_33 = BSP_CLOCKS_PLL_MUL(85U, 33U), ///< PLL multiplier of 85.33 + CGC_PLL_MUL_85_5 = BSP_CLOCKS_PLL_MUL(85U, 50U), ///< PLL multiplier of 85.50 + CGC_PLL_MUL_85_66 = BSP_CLOCKS_PLL_MUL(85U, 66U), ///< PLL multiplier of 85.66 + CGC_PLL_MUL_86_0 = BSP_CLOCKS_PLL_MUL(86U, 0U), ///< PLL multiplier of 86.00 + CGC_PLL_MUL_86_33 = BSP_CLOCKS_PLL_MUL(86U, 33U), ///< PLL multiplier of 86.33 + CGC_PLL_MUL_86_5 = BSP_CLOCKS_PLL_MUL(86U, 50U), ///< PLL multiplier of 86.50 + CGC_PLL_MUL_86_66 = BSP_CLOCKS_PLL_MUL(86U, 66U), ///< PLL multiplier of 86.66 + CGC_PLL_MUL_87_0 = BSP_CLOCKS_PLL_MUL(87U, 0U), ///< PLL multiplier of 87.00 + CGC_PLL_MUL_87_33 = BSP_CLOCKS_PLL_MUL(87U, 33U), ///< PLL multiplier of 87.33 + CGC_PLL_MUL_87_5 = BSP_CLOCKS_PLL_MUL(87U, 50U), ///< PLL multiplier of 87.50 + CGC_PLL_MUL_87_66 = BSP_CLOCKS_PLL_MUL(87U, 66U), ///< PLL multiplier of 87.66 + CGC_PLL_MUL_88_0 = BSP_CLOCKS_PLL_MUL(88U, 0U), ///< PLL multiplier of 88.00 + CGC_PLL_MUL_88_33 = BSP_CLOCKS_PLL_MUL(88U, 33U), ///< PLL multiplier of 88.33 + CGC_PLL_MUL_88_5 = BSP_CLOCKS_PLL_MUL(88U, 50U), ///< PLL multiplier of 88.50 + CGC_PLL_MUL_88_66 = BSP_CLOCKS_PLL_MUL(88U, 66U), ///< PLL multiplier of 88.66 + CGC_PLL_MUL_89_0 = BSP_CLOCKS_PLL_MUL(89U, 0U), ///< PLL multiplier of 89.00 + CGC_PLL_MUL_89_33 = BSP_CLOCKS_PLL_MUL(89U, 33U), ///< PLL multiplier of 89.33 + CGC_PLL_MUL_89_5 = BSP_CLOCKS_PLL_MUL(89U, 50U), ///< PLL multiplier of 89.50 + CGC_PLL_MUL_89_66 = BSP_CLOCKS_PLL_MUL(89U, 66U), ///< PLL multiplier of 89.66 + CGC_PLL_MUL_90_0 = BSP_CLOCKS_PLL_MUL(90U, 0U), ///< PLL multiplier of 90.00 + CGC_PLL_MUL_90_33 = BSP_CLOCKS_PLL_MUL(90U, 33U), ///< PLL multiplier of 90.33 + CGC_PLL_MUL_90_5 = BSP_CLOCKS_PLL_MUL(90U, 50U), ///< PLL multiplier of 90.50 + CGC_PLL_MUL_90_66 = BSP_CLOCKS_PLL_MUL(90U, 66U), ///< PLL multiplier of 90.66 + CGC_PLL_MUL_91_0 = BSP_CLOCKS_PLL_MUL(91U, 0U), ///< PLL multiplier of 91.00 + CGC_PLL_MUL_91_33 = BSP_CLOCKS_PLL_MUL(91U, 33U), ///< PLL multiplier of 91.33 + CGC_PLL_MUL_91_5 = BSP_CLOCKS_PLL_MUL(91U, 50U), ///< PLL multiplier of 91.50 + CGC_PLL_MUL_91_66 = BSP_CLOCKS_PLL_MUL(91U, 66U), ///< PLL multiplier of 91.66 + CGC_PLL_MUL_92_0 = BSP_CLOCKS_PLL_MUL(92U, 0U), ///< PLL multiplier of 92.00 + CGC_PLL_MUL_92_33 = BSP_CLOCKS_PLL_MUL(92U, 33U), ///< PLL multiplier of 92.33 + CGC_PLL_MUL_92_5 = BSP_CLOCKS_PLL_MUL(92U, 50U), ///< PLL multiplier of 92.50 + CGC_PLL_MUL_92_66 = BSP_CLOCKS_PLL_MUL(92U, 66U), ///< PLL multiplier of 92.66 + CGC_PLL_MUL_93_0 = BSP_CLOCKS_PLL_MUL(93U, 0U), ///< PLL multiplier of 93.00 + CGC_PLL_MUL_93_33 = BSP_CLOCKS_PLL_MUL(93U, 33U), ///< PLL multiplier of 93.33 + CGC_PLL_MUL_93_5 = BSP_CLOCKS_PLL_MUL(93U, 50U), ///< PLL multiplier of 93.50 + CGC_PLL_MUL_93_66 = BSP_CLOCKS_PLL_MUL(93U, 66U), ///< PLL multiplier of 93.66 + CGC_PLL_MUL_94_0 = BSP_CLOCKS_PLL_MUL(94U, 0U), ///< PLL multiplier of 94.00 + CGC_PLL_MUL_94_33 = BSP_CLOCKS_PLL_MUL(94U, 33U), ///< PLL multiplier of 94.33 + CGC_PLL_MUL_94_5 = BSP_CLOCKS_PLL_MUL(94U, 50U), ///< PLL multiplier of 94.50 + CGC_PLL_MUL_94_66 = BSP_CLOCKS_PLL_MUL(94U, 66U), ///< PLL multiplier of 94.66 + CGC_PLL_MUL_95_0 = BSP_CLOCKS_PLL_MUL(95U, 0U), ///< PLL multiplier of 95.00 + CGC_PLL_MUL_95_33 = BSP_CLOCKS_PLL_MUL(95U, 33U), ///< PLL multiplier of 95.33 + CGC_PLL_MUL_95_5 = BSP_CLOCKS_PLL_MUL(95U, 50U), ///< PLL multiplier of 95.50 + CGC_PLL_MUL_95_66 = BSP_CLOCKS_PLL_MUL(95U, 66U), ///< PLL multiplier of 95.66 + CGC_PLL_MUL_96_0 = BSP_CLOCKS_PLL_MUL(96U, 0U), ///< PLL multiplier of 96.00 + CGC_PLL_MUL_96_33 = BSP_CLOCKS_PLL_MUL(96U, 33U), ///< PLL multiplier of 96.33 + CGC_PLL_MUL_96_5 = BSP_CLOCKS_PLL_MUL(96U, 50U), ///< PLL multiplier of 96.50 + CGC_PLL_MUL_96_66 = BSP_CLOCKS_PLL_MUL(96U, 66U), ///< PLL multiplier of 96.66 + CGC_PLL_MUL_97_0 = BSP_CLOCKS_PLL_MUL(97U, 0U), ///< PLL multiplier of 97.00 + CGC_PLL_MUL_97_33 = BSP_CLOCKS_PLL_MUL(97U, 33U), ///< PLL multiplier of 97.33 + CGC_PLL_MUL_97_5 = BSP_CLOCKS_PLL_MUL(97U, 50U), ///< PLL multiplier of 97.50 + CGC_PLL_MUL_97_66 = BSP_CLOCKS_PLL_MUL(97U, 66U), ///< PLL multiplier of 97.66 + CGC_PLL_MUL_98_0 = BSP_CLOCKS_PLL_MUL(98U, 0U), ///< PLL multiplier of 98.00 + CGC_PLL_MUL_98_33 = BSP_CLOCKS_PLL_MUL(98U, 33U), ///< PLL multiplier of 98.33 + CGC_PLL_MUL_98_5 = BSP_CLOCKS_PLL_MUL(98U, 50U), ///< PLL multiplier of 98.50 + CGC_PLL_MUL_98_66 = BSP_CLOCKS_PLL_MUL(98U, 66U), ///< PLL multiplier of 98.66 + CGC_PLL_MUL_99_0 = BSP_CLOCKS_PLL_MUL(99U, 0U), ///< PLL multiplier of 99.00 + CGC_PLL_MUL_99_33 = BSP_CLOCKS_PLL_MUL(99U, 33U), ///< PLL multiplier of 99.33 + CGC_PLL_MUL_99_5 = BSP_CLOCKS_PLL_MUL(99U, 50U), ///< PLL multiplier of 99.50 + CGC_PLL_MUL_99_66 = BSP_CLOCKS_PLL_MUL(99U, 66U), ///< PLL multiplier of 99.66 + CGC_PLL_MUL_100_0 = BSP_CLOCKS_PLL_MUL(100U, 0U), ///< PLL multiplier of 100.00 + CGC_PLL_MUL_100_33 = BSP_CLOCKS_PLL_MUL(100U, 33U), ///< PLL multiplier of 100.33 + CGC_PLL_MUL_100_5 = BSP_CLOCKS_PLL_MUL(100U, 50U), ///< PLL multiplier of 100.50 + CGC_PLL_MUL_100_66 = BSP_CLOCKS_PLL_MUL(100U, 66U), ///< PLL multiplier of 100.66 + CGC_PLL_MUL_101_0 = BSP_CLOCKS_PLL_MUL(101U, 0U), ///< PLL multiplier of 101.00 + CGC_PLL_MUL_101_33 = BSP_CLOCKS_PLL_MUL(101U, 33U), ///< PLL multiplier of 101.33 + CGC_PLL_MUL_101_5 = BSP_CLOCKS_PLL_MUL(101U, 50U), ///< PLL multiplier of 101.50 + CGC_PLL_MUL_101_66 = BSP_CLOCKS_PLL_MUL(101U, 66U), ///< PLL multiplier of 101.66 + CGC_PLL_MUL_102_0 = BSP_CLOCKS_PLL_MUL(102U, 0U), ///< PLL multiplier of 102.00 + CGC_PLL_MUL_102_33 = BSP_CLOCKS_PLL_MUL(102U, 33U), ///< PLL multiplier of 102.33 + CGC_PLL_MUL_102_5 = BSP_CLOCKS_PLL_MUL(102U, 50U), ///< PLL multiplier of 102.50 + CGC_PLL_MUL_102_66 = BSP_CLOCKS_PLL_MUL(102U, 66U), ///< PLL multiplier of 102.66 + CGC_PLL_MUL_103_0 = BSP_CLOCKS_PLL_MUL(103U, 0U), ///< PLL multiplier of 103.00 + CGC_PLL_MUL_103_33 = BSP_CLOCKS_PLL_MUL(103U, 33U), ///< PLL multiplier of 103.33 + CGC_PLL_MUL_103_5 = BSP_CLOCKS_PLL_MUL(103U, 50U), ///< PLL multiplier of 103.50 + CGC_PLL_MUL_103_66 = BSP_CLOCKS_PLL_MUL(103U, 66U), ///< PLL multiplier of 103.66 + CGC_PLL_MUL_104_0 = BSP_CLOCKS_PLL_MUL(104U, 0U), ///< PLL multiplier of 104.00 + CGC_PLL_MUL_104_33 = BSP_CLOCKS_PLL_MUL(104U, 33U), ///< PLL multiplier of 104.33 + CGC_PLL_MUL_104_5 = BSP_CLOCKS_PLL_MUL(104U, 50U), ///< PLL multiplier of 104.50 + CGC_PLL_MUL_104_66 = BSP_CLOCKS_PLL_MUL(104U, 66U), ///< PLL multiplier of 104.66 + CGC_PLL_MUL_105_0 = BSP_CLOCKS_PLL_MUL(105U, 0U), ///< PLL multiplier of 105.00 + CGC_PLL_MUL_105_33 = BSP_CLOCKS_PLL_MUL(105U, 33U), ///< PLL multiplier of 105.33 + CGC_PLL_MUL_105_5 = BSP_CLOCKS_PLL_MUL(105U, 50U), ///< PLL multiplier of 105.50 + CGC_PLL_MUL_105_66 = BSP_CLOCKS_PLL_MUL(105U, 66U), ///< PLL multiplier of 105.66 + CGC_PLL_MUL_106_0 = BSP_CLOCKS_PLL_MUL(106U, 0U), ///< PLL multiplier of 106.00 + CGC_PLL_MUL_106_33 = BSP_CLOCKS_PLL_MUL(106U, 33U), ///< PLL multiplier of 106.33 + CGC_PLL_MUL_106_5 = BSP_CLOCKS_PLL_MUL(106U, 50U), ///< PLL multiplier of 106.50 + CGC_PLL_MUL_106_66 = BSP_CLOCKS_PLL_MUL(106U, 66U), ///< PLL multiplier of 106.66 + CGC_PLL_MUL_107_0 = BSP_CLOCKS_PLL_MUL(107U, 0U), ///< PLL multiplier of 107.00 + CGC_PLL_MUL_107_33 = BSP_CLOCKS_PLL_MUL(107U, 33U), ///< PLL multiplier of 107.33 + CGC_PLL_MUL_107_5 = BSP_CLOCKS_PLL_MUL(107U, 50U), ///< PLL multiplier of 107.50 + CGC_PLL_MUL_107_66 = BSP_CLOCKS_PLL_MUL(107U, 66U), ///< PLL multiplier of 107.66 + CGC_PLL_MUL_108_0 = BSP_CLOCKS_PLL_MUL(108U, 0U), ///< PLL multiplier of 108.00 + CGC_PLL_MUL_108_33 = BSP_CLOCKS_PLL_MUL(108U, 33U), ///< PLL multiplier of 108.33 + CGC_PLL_MUL_108_5 = BSP_CLOCKS_PLL_MUL(108U, 50U), ///< PLL multiplier of 108.50 + CGC_PLL_MUL_108_66 = BSP_CLOCKS_PLL_MUL(108U, 66U), ///< PLL multiplier of 108.66 + CGC_PLL_MUL_109_0 = BSP_CLOCKS_PLL_MUL(109U, 0U), ///< PLL multiplier of 109.00 + CGC_PLL_MUL_109_33 = BSP_CLOCKS_PLL_MUL(109U, 33U), ///< PLL multiplier of 109.33 + CGC_PLL_MUL_109_5 = BSP_CLOCKS_PLL_MUL(109U, 50U), ///< PLL multiplier of 109.50 + CGC_PLL_MUL_109_66 = BSP_CLOCKS_PLL_MUL(109U, 66U), ///< PLL multiplier of 109.66 + CGC_PLL_MUL_110_0 = BSP_CLOCKS_PLL_MUL(110U, 0U), ///< PLL multiplier of 110.00 + CGC_PLL_MUL_110_33 = BSP_CLOCKS_PLL_MUL(110U, 33U), ///< PLL multiplier of 110.33 + CGC_PLL_MUL_110_5 = BSP_CLOCKS_PLL_MUL(110U, 50U), ///< PLL multiplier of 110.50 + CGC_PLL_MUL_110_66 = BSP_CLOCKS_PLL_MUL(110U, 66U), ///< PLL multiplier of 110.66 + CGC_PLL_MUL_111_0 = BSP_CLOCKS_PLL_MUL(111U, 0U), ///< PLL multiplier of 111.00 + CGC_PLL_MUL_111_33 = BSP_CLOCKS_PLL_MUL(111U, 33U), ///< PLL multiplier of 111.33 + CGC_PLL_MUL_111_5 = BSP_CLOCKS_PLL_MUL(111U, 50U), ///< PLL multiplier of 111.50 + CGC_PLL_MUL_111_66 = BSP_CLOCKS_PLL_MUL(111U, 66U), ///< PLL multiplier of 111.66 + CGC_PLL_MUL_112_0 = BSP_CLOCKS_PLL_MUL(112U, 0U), ///< PLL multiplier of 112.00 + CGC_PLL_MUL_112_33 = BSP_CLOCKS_PLL_MUL(112U, 33U), ///< PLL multiplier of 112.33 + CGC_PLL_MUL_112_5 = BSP_CLOCKS_PLL_MUL(112U, 50U), ///< PLL multiplier of 112.50 + CGC_PLL_MUL_112_66 = BSP_CLOCKS_PLL_MUL(112U, 66U), ///< PLL multiplier of 112.66 + CGC_PLL_MUL_113_0 = BSP_CLOCKS_PLL_MUL(113U, 0U), ///< PLL multiplier of 113.00 + CGC_PLL_MUL_113_33 = BSP_CLOCKS_PLL_MUL(113U, 33U), ///< PLL multiplier of 113.33 + CGC_PLL_MUL_113_5 = BSP_CLOCKS_PLL_MUL(113U, 50U), ///< PLL multiplier of 113.50 + CGC_PLL_MUL_113_66 = BSP_CLOCKS_PLL_MUL(113U, 66U), ///< PLL multiplier of 113.66 + CGC_PLL_MUL_114_0 = BSP_CLOCKS_PLL_MUL(114U, 0U), ///< PLL multiplier of 114.00 + CGC_PLL_MUL_114_33 = BSP_CLOCKS_PLL_MUL(114U, 33U), ///< PLL multiplier of 114.33 + CGC_PLL_MUL_114_5 = BSP_CLOCKS_PLL_MUL(114U, 50U), ///< PLL multiplier of 114.50 + CGC_PLL_MUL_114_66 = BSP_CLOCKS_PLL_MUL(114U, 66U), ///< PLL multiplier of 114.66 + CGC_PLL_MUL_115_0 = BSP_CLOCKS_PLL_MUL(115U, 0U), ///< PLL multiplier of 115.00 + CGC_PLL_MUL_115_33 = BSP_CLOCKS_PLL_MUL(115U, 33U), ///< PLL multiplier of 115.33 + CGC_PLL_MUL_115_5 = BSP_CLOCKS_PLL_MUL(115U, 50U), ///< PLL multiplier of 115.50 + CGC_PLL_MUL_115_66 = BSP_CLOCKS_PLL_MUL(115U, 66U), ///< PLL multiplier of 115.66 + CGC_PLL_MUL_116_0 = BSP_CLOCKS_PLL_MUL(116U, 0U), ///< PLL multiplier of 116.00 + CGC_PLL_MUL_116_33 = BSP_CLOCKS_PLL_MUL(116U, 33U), ///< PLL multiplier of 116.33 + CGC_PLL_MUL_116_5 = BSP_CLOCKS_PLL_MUL(116U, 50U), ///< PLL multiplier of 116.50 + CGC_PLL_MUL_116_66 = BSP_CLOCKS_PLL_MUL(116U, 66U), ///< PLL multiplier of 116.66 + CGC_PLL_MUL_117_0 = BSP_CLOCKS_PLL_MUL(117U, 0U), ///< PLL multiplier of 117.00 + CGC_PLL_MUL_117_33 = BSP_CLOCKS_PLL_MUL(117U, 33U), ///< PLL multiplier of 117.33 + CGC_PLL_MUL_117_5 = BSP_CLOCKS_PLL_MUL(117U, 50U), ///< PLL multiplier of 117.50 + CGC_PLL_MUL_117_66 = BSP_CLOCKS_PLL_MUL(117U, 66U), ///< PLL multiplier of 117.66 + CGC_PLL_MUL_118_0 = BSP_CLOCKS_PLL_MUL(118U, 0U), ///< PLL multiplier of 118.00 + CGC_PLL_MUL_118_33 = BSP_CLOCKS_PLL_MUL(118U, 33U), ///< PLL multiplier of 118.33 + CGC_PLL_MUL_118_5 = BSP_CLOCKS_PLL_MUL(118U, 50U), ///< PLL multiplier of 118.50 + CGC_PLL_MUL_118_66 = BSP_CLOCKS_PLL_MUL(118U, 66U), ///< PLL multiplier of 118.66 + CGC_PLL_MUL_119_0 = BSP_CLOCKS_PLL_MUL(119U, 0U), ///< PLL multiplier of 119.00 + CGC_PLL_MUL_119_33 = BSP_CLOCKS_PLL_MUL(119U, 33U), ///< PLL multiplier of 119.33 + CGC_PLL_MUL_119_5 = BSP_CLOCKS_PLL_MUL(119U, 50U), ///< PLL multiplier of 119.50 + CGC_PLL_MUL_119_66 = BSP_CLOCKS_PLL_MUL(119U, 66U), ///< PLL multiplier of 119.66 + CGC_PLL_MUL_120_0 = BSP_CLOCKS_PLL_MUL(120U, 0U), ///< PLL multiplier of 120.00 + CGC_PLL_MUL_120_33 = BSP_CLOCKS_PLL_MUL(120U, 33U), ///< PLL multiplier of 120.33 + CGC_PLL_MUL_120_5 = BSP_CLOCKS_PLL_MUL(120U, 50U), ///< PLL multiplier of 120.50 + CGC_PLL_MUL_120_66 = BSP_CLOCKS_PLL_MUL(120U, 66U), ///< PLL multiplier of 120.66 + CGC_PLL_MUL_121_0 = BSP_CLOCKS_PLL_MUL(121U, 0U), ///< PLL multiplier of 121.00 + CGC_PLL_MUL_121_33 = BSP_CLOCKS_PLL_MUL(121U, 33U), ///< PLL multiplier of 121.33 + CGC_PLL_MUL_121_5 = BSP_CLOCKS_PLL_MUL(121U, 50U), ///< PLL multiplier of 121.50 + CGC_PLL_MUL_121_66 = BSP_CLOCKS_PLL_MUL(121U, 66U), ///< PLL multiplier of 121.66 + CGC_PLL_MUL_122_0 = BSP_CLOCKS_PLL_MUL(122U, 0U), ///< PLL multiplier of 122.00 + CGC_PLL_MUL_122_33 = BSP_CLOCKS_PLL_MUL(122U, 33U), ///< PLL multiplier of 122.33 + CGC_PLL_MUL_122_5 = BSP_CLOCKS_PLL_MUL(122U, 50U), ///< PLL multiplier of 122.50 + CGC_PLL_MUL_122_66 = BSP_CLOCKS_PLL_MUL(122U, 66U), ///< PLL multiplier of 122.66 + CGC_PLL_MUL_123_0 = BSP_CLOCKS_PLL_MUL(123U, 0U), ///< PLL multiplier of 123.00 + CGC_PLL_MUL_123_33 = BSP_CLOCKS_PLL_MUL(123U, 33U), ///< PLL multiplier of 123.33 + CGC_PLL_MUL_123_5 = BSP_CLOCKS_PLL_MUL(123U, 50U), ///< PLL multiplier of 123.50 + CGC_PLL_MUL_123_66 = BSP_CLOCKS_PLL_MUL(123U, 66U), ///< PLL multiplier of 123.66 + CGC_PLL_MUL_124_0 = BSP_CLOCKS_PLL_MUL(124U, 0U), ///< PLL multiplier of 124.00 + CGC_PLL_MUL_124_33 = BSP_CLOCKS_PLL_MUL(124U, 33U), ///< PLL multiplier of 124.33 + CGC_PLL_MUL_124_5 = BSP_CLOCKS_PLL_MUL(124U, 50U), ///< PLL multiplier of 124.50 + CGC_PLL_MUL_124_66 = BSP_CLOCKS_PLL_MUL(124U, 66U), ///< PLL multiplier of 124.66 + CGC_PLL_MUL_125_0 = BSP_CLOCKS_PLL_MUL(125U, 0U), ///< PLL multiplier of 125.00 + CGC_PLL_MUL_125_33 = BSP_CLOCKS_PLL_MUL(125U, 33U), ///< PLL multiplier of 125.33 + CGC_PLL_MUL_125_5 = BSP_CLOCKS_PLL_MUL(125U, 50U), ///< PLL multiplier of 125.50 + CGC_PLL_MUL_125_66 = BSP_CLOCKS_PLL_MUL(125U, 66U), ///< PLL multiplier of 125.66 + CGC_PLL_MUL_126_0 = BSP_CLOCKS_PLL_MUL(126U, 0U), ///< PLL multiplier of 126.00 + CGC_PLL_MUL_126_33 = BSP_CLOCKS_PLL_MUL(126U, 33U), ///< PLL multiplier of 126.33 + CGC_PLL_MUL_126_5 = BSP_CLOCKS_PLL_MUL(126U, 50U), ///< PLL multiplier of 126.50 + CGC_PLL_MUL_126_66 = BSP_CLOCKS_PLL_MUL(126U, 66U), ///< PLL multiplier of 126.66 + CGC_PLL_MUL_127_0 = BSP_CLOCKS_PLL_MUL(127U, 0U), ///< PLL multiplier of 127.00 + CGC_PLL_MUL_127_33 = BSP_CLOCKS_PLL_MUL(127U, 33U), ///< PLL multiplier of 127.33 + CGC_PLL_MUL_127_5 = BSP_CLOCKS_PLL_MUL(127U, 50U), ///< PLL multiplier of 127.50 + CGC_PLL_MUL_127_66 = BSP_CLOCKS_PLL_MUL(127U, 66U), ///< PLL multiplier of 127.66 + CGC_PLL_MUL_128_0 = BSP_CLOCKS_PLL_MUL(128U, 0U), ///< PLL multiplier of 128.00 + CGC_PLL_MUL_128_33 = BSP_CLOCKS_PLL_MUL(128U, 33U), ///< PLL multiplier of 128.33 + CGC_PLL_MUL_128_5 = BSP_CLOCKS_PLL_MUL(128U, 50U), ///< PLL multiplier of 128.50 + CGC_PLL_MUL_128_66 = BSP_CLOCKS_PLL_MUL(128U, 66U), ///< PLL multiplier of 128.66 + CGC_PLL_MUL_129_0 = BSP_CLOCKS_PLL_MUL(129U, 0U), ///< PLL multiplier of 129.00 + CGC_PLL_MUL_129_33 = BSP_CLOCKS_PLL_MUL(129U, 33U), ///< PLL multiplier of 129.33 + CGC_PLL_MUL_129_5 = BSP_CLOCKS_PLL_MUL(129U, 50U), ///< PLL multiplier of 129.50 + CGC_PLL_MUL_129_66 = BSP_CLOCKS_PLL_MUL(129U, 66U), ///< PLL multiplier of 129.66 + CGC_PLL_MUL_130_0 = BSP_CLOCKS_PLL_MUL(130U, 0U), ///< PLL multiplier of 130.00 + CGC_PLL_MUL_130_33 = BSP_CLOCKS_PLL_MUL(130U, 33U), ///< PLL multiplier of 130.33 + CGC_PLL_MUL_130_5 = BSP_CLOCKS_PLL_MUL(130U, 50U), ///< PLL multiplier of 130.50 + CGC_PLL_MUL_130_66 = BSP_CLOCKS_PLL_MUL(130U, 66U), ///< PLL multiplier of 130.66 + CGC_PLL_MUL_131_0 = BSP_CLOCKS_PLL_MUL(131U, 0U), ///< PLL multiplier of 131.00 + CGC_PLL_MUL_131_33 = BSP_CLOCKS_PLL_MUL(131U, 33U), ///< PLL multiplier of 131.33 + CGC_PLL_MUL_131_5 = BSP_CLOCKS_PLL_MUL(131U, 50U), ///< PLL multiplier of 131.50 + CGC_PLL_MUL_131_66 = BSP_CLOCKS_PLL_MUL(131U, 66U), ///< PLL multiplier of 131.66 + CGC_PLL_MUL_132_0 = BSP_CLOCKS_PLL_MUL(132U, 0U), ///< PLL multiplier of 132.00 + CGC_PLL_MUL_132_33 = BSP_CLOCKS_PLL_MUL(132U, 33U), ///< PLL multiplier of 132.33 + CGC_PLL_MUL_132_5 = BSP_CLOCKS_PLL_MUL(132U, 50U), ///< PLL multiplier of 132.50 + CGC_PLL_MUL_132_66 = BSP_CLOCKS_PLL_MUL(132U, 66U), ///< PLL multiplier of 132.66 + CGC_PLL_MUL_133_0 = BSP_CLOCKS_PLL_MUL(133U, 0U), ///< PLL multiplier of 133.00 + CGC_PLL_MUL_133_33 = BSP_CLOCKS_PLL_MUL(133U, 33U), ///< PLL multiplier of 133.33 + CGC_PLL_MUL_133_5 = BSP_CLOCKS_PLL_MUL(133U, 50U), ///< PLL multiplier of 133.50 + CGC_PLL_MUL_133_66 = BSP_CLOCKS_PLL_MUL(133U, 66U), ///< PLL multiplier of 133.66 + CGC_PLL_MUL_134_0 = BSP_CLOCKS_PLL_MUL(134U, 0U), ///< PLL multiplier of 134.00 + CGC_PLL_MUL_134_33 = BSP_CLOCKS_PLL_MUL(134U, 33U), ///< PLL multiplier of 134.33 + CGC_PLL_MUL_134_5 = BSP_CLOCKS_PLL_MUL(134U, 50U), ///< PLL multiplier of 134.50 + CGC_PLL_MUL_134_66 = BSP_CLOCKS_PLL_MUL(134U, 66U), ///< PLL multiplier of 134.66 + CGC_PLL_MUL_135_0 = BSP_CLOCKS_PLL_MUL(135U, 0U), ///< PLL multiplier of 135.00 + CGC_PLL_MUL_135_33 = BSP_CLOCKS_PLL_MUL(135U, 33U), ///< PLL multiplier of 135.33 + CGC_PLL_MUL_135_5 = BSP_CLOCKS_PLL_MUL(135U, 50U), ///< PLL multiplier of 135.50 + CGC_PLL_MUL_135_66 = BSP_CLOCKS_PLL_MUL(135U, 66U), ///< PLL multiplier of 135.66 + CGC_PLL_MUL_136_0 = BSP_CLOCKS_PLL_MUL(136U, 0U), ///< PLL multiplier of 136.00 + CGC_PLL_MUL_136_33 = BSP_CLOCKS_PLL_MUL(136U, 33U), ///< PLL multiplier of 136.33 + CGC_PLL_MUL_136_5 = BSP_CLOCKS_PLL_MUL(136U, 50U), ///< PLL multiplier of 136.50 + CGC_PLL_MUL_136_66 = BSP_CLOCKS_PLL_MUL(136U, 66U), ///< PLL multiplier of 136.66 + CGC_PLL_MUL_137_0 = BSP_CLOCKS_PLL_MUL(137U, 0U), ///< PLL multiplier of 137.00 + CGC_PLL_MUL_137_33 = BSP_CLOCKS_PLL_MUL(137U, 33U), ///< PLL multiplier of 137.33 + CGC_PLL_MUL_137_5 = BSP_CLOCKS_PLL_MUL(137U, 50U), ///< PLL multiplier of 137.50 + CGC_PLL_MUL_137_66 = BSP_CLOCKS_PLL_MUL(137U, 66U), ///< PLL multiplier of 137.66 + CGC_PLL_MUL_138_0 = BSP_CLOCKS_PLL_MUL(138U, 0U), ///< PLL multiplier of 138.00 + CGC_PLL_MUL_138_33 = BSP_CLOCKS_PLL_MUL(138U, 33U), ///< PLL multiplier of 138.33 + CGC_PLL_MUL_138_5 = BSP_CLOCKS_PLL_MUL(138U, 50U), ///< PLL multiplier of 138.50 + CGC_PLL_MUL_138_66 = BSP_CLOCKS_PLL_MUL(138U, 66U), ///< PLL multiplier of 138.66 + CGC_PLL_MUL_139_0 = BSP_CLOCKS_PLL_MUL(139U, 0U), ///< PLL multiplier of 139.00 + CGC_PLL_MUL_139_33 = BSP_CLOCKS_PLL_MUL(139U, 33U), ///< PLL multiplier of 139.33 + CGC_PLL_MUL_139_5 = BSP_CLOCKS_PLL_MUL(139U, 50U), ///< PLL multiplier of 139.50 + CGC_PLL_MUL_139_66 = BSP_CLOCKS_PLL_MUL(139U, 66U), ///< PLL multiplier of 139.66 + CGC_PLL_MUL_140_0 = BSP_CLOCKS_PLL_MUL(140U, 0U), ///< PLL multiplier of 140.00 + CGC_PLL_MUL_140_33 = BSP_CLOCKS_PLL_MUL(140U, 33U), ///< PLL multiplier of 140.33 + CGC_PLL_MUL_140_5 = BSP_CLOCKS_PLL_MUL(140U, 50U), ///< PLL multiplier of 140.50 + CGC_PLL_MUL_140_66 = BSP_CLOCKS_PLL_MUL(140U, 66U), ///< PLL multiplier of 140.66 + CGC_PLL_MUL_141_0 = BSP_CLOCKS_PLL_MUL(141U, 0U), ///< PLL multiplier of 141.00 + CGC_PLL_MUL_141_33 = BSP_CLOCKS_PLL_MUL(141U, 33U), ///< PLL multiplier of 141.33 + CGC_PLL_MUL_141_5 = BSP_CLOCKS_PLL_MUL(141U, 50U), ///< PLL multiplier of 141.50 + CGC_PLL_MUL_141_66 = BSP_CLOCKS_PLL_MUL(141U, 66U), ///< PLL multiplier of 141.66 + CGC_PLL_MUL_142_0 = BSP_CLOCKS_PLL_MUL(142U, 0U), ///< PLL multiplier of 142.00 + CGC_PLL_MUL_142_33 = BSP_CLOCKS_PLL_MUL(142U, 33U), ///< PLL multiplier of 142.33 + CGC_PLL_MUL_142_5 = BSP_CLOCKS_PLL_MUL(142U, 50U), ///< PLL multiplier of 142.50 + CGC_PLL_MUL_142_66 = BSP_CLOCKS_PLL_MUL(142U, 66U), ///< PLL multiplier of 142.66 + CGC_PLL_MUL_143_0 = BSP_CLOCKS_PLL_MUL(143U, 0U), ///< PLL multiplier of 143.00 + CGC_PLL_MUL_143_33 = BSP_CLOCKS_PLL_MUL(143U, 33U), ///< PLL multiplier of 143.33 + CGC_PLL_MUL_143_5 = BSP_CLOCKS_PLL_MUL(143U, 50U), ///< PLL multiplier of 143.50 + CGC_PLL_MUL_143_66 = BSP_CLOCKS_PLL_MUL(143U, 66U), ///< PLL multiplier of 143.66 + CGC_PLL_MUL_144_0 = BSP_CLOCKS_PLL_MUL(144U, 0U), ///< PLL multiplier of 144.00 + CGC_PLL_MUL_144_33 = BSP_CLOCKS_PLL_MUL(144U, 33U), ///< PLL multiplier of 144.33 + CGC_PLL_MUL_144_5 = BSP_CLOCKS_PLL_MUL(144U, 50U), ///< PLL multiplier of 144.50 + CGC_PLL_MUL_144_66 = BSP_CLOCKS_PLL_MUL(144U, 66U), ///< PLL multiplier of 144.66 + CGC_PLL_MUL_145_0 = BSP_CLOCKS_PLL_MUL(145U, 0U), ///< PLL multiplier of 145.00 + CGC_PLL_MUL_145_33 = BSP_CLOCKS_PLL_MUL(145U, 33U), ///< PLL multiplier of 145.33 + CGC_PLL_MUL_145_5 = BSP_CLOCKS_PLL_MUL(145U, 50U), ///< PLL multiplier of 145.50 + CGC_PLL_MUL_145_66 = BSP_CLOCKS_PLL_MUL(145U, 66U), ///< PLL multiplier of 145.66 + CGC_PLL_MUL_146_0 = BSP_CLOCKS_PLL_MUL(146U, 0U), ///< PLL multiplier of 146.00 + CGC_PLL_MUL_146_33 = BSP_CLOCKS_PLL_MUL(146U, 33U), ///< PLL multiplier of 146.33 + CGC_PLL_MUL_146_5 = BSP_CLOCKS_PLL_MUL(146U, 50U), ///< PLL multiplier of 146.50 + CGC_PLL_MUL_146_66 = BSP_CLOCKS_PLL_MUL(146U, 66U), ///< PLL multiplier of 146.66 + CGC_PLL_MUL_147_0 = BSP_CLOCKS_PLL_MUL(147U, 0U), ///< PLL multiplier of 147.00 + CGC_PLL_MUL_147_33 = BSP_CLOCKS_PLL_MUL(147U, 33U), ///< PLL multiplier of 147.33 + CGC_PLL_MUL_147_5 = BSP_CLOCKS_PLL_MUL(147U, 50U), ///< PLL multiplier of 147.50 + CGC_PLL_MUL_147_66 = BSP_CLOCKS_PLL_MUL(147U, 66U), ///< PLL multiplier of 147.66 + CGC_PLL_MUL_148_0 = BSP_CLOCKS_PLL_MUL(148U, 0U), ///< PLL multiplier of 148.00 + CGC_PLL_MUL_148_33 = BSP_CLOCKS_PLL_MUL(148U, 33U), ///< PLL multiplier of 148.33 + CGC_PLL_MUL_148_5 = BSP_CLOCKS_PLL_MUL(148U, 50U), ///< PLL multiplier of 148.50 + CGC_PLL_MUL_148_66 = BSP_CLOCKS_PLL_MUL(148U, 66U), ///< PLL multiplier of 148.66 + CGC_PLL_MUL_149_0 = BSP_CLOCKS_PLL_MUL(149U, 0U), ///< PLL multiplier of 149.00 + CGC_PLL_MUL_149_33 = BSP_CLOCKS_PLL_MUL(149U, 33U), ///< PLL multiplier of 149.33 + CGC_PLL_MUL_149_5 = BSP_CLOCKS_PLL_MUL(149U, 50U), ///< PLL multiplier of 149.50 + CGC_PLL_MUL_149_66 = BSP_CLOCKS_PLL_MUL(149U, 66U), ///< PLL multiplier of 149.66 + CGC_PLL_MUL_150_0 = BSP_CLOCKS_PLL_MUL(150U, 0U), ///< PLL multiplier of 150.00 + CGC_PLL_MUL_150_33 = BSP_CLOCKS_PLL_MUL(150U, 33U), ///< PLL multiplier of 150.33 + CGC_PLL_MUL_150_5 = BSP_CLOCKS_PLL_MUL(150U, 50U), ///< PLL multiplier of 150.50 + CGC_PLL_MUL_150_66 = BSP_CLOCKS_PLL_MUL(150U, 66U), ///< PLL multiplier of 150.66 + CGC_PLL_MUL_151_0 = BSP_CLOCKS_PLL_MUL(151U, 0U), ///< PLL multiplier of 151.00 + CGC_PLL_MUL_151_33 = BSP_CLOCKS_PLL_MUL(151U, 33U), ///< PLL multiplier of 151.33 + CGC_PLL_MUL_151_5 = BSP_CLOCKS_PLL_MUL(151U, 50U), ///< PLL multiplier of 151.50 + CGC_PLL_MUL_151_66 = BSP_CLOCKS_PLL_MUL(151U, 66U), ///< PLL multiplier of 151.66 + CGC_PLL_MUL_152_0 = BSP_CLOCKS_PLL_MUL(152U, 0U), ///< PLL multiplier of 152.00 + CGC_PLL_MUL_152_33 = BSP_CLOCKS_PLL_MUL(152U, 33U), ///< PLL multiplier of 152.33 + CGC_PLL_MUL_152_5 = BSP_CLOCKS_PLL_MUL(152U, 50U), ///< PLL multiplier of 152.50 + CGC_PLL_MUL_152_66 = BSP_CLOCKS_PLL_MUL(152U, 66U), ///< PLL multiplier of 152.66 + CGC_PLL_MUL_153_0 = BSP_CLOCKS_PLL_MUL(153U, 0U), ///< PLL multiplier of 153.00 + CGC_PLL_MUL_153_33 = BSP_CLOCKS_PLL_MUL(153U, 33U), ///< PLL multiplier of 153.33 + CGC_PLL_MUL_153_5 = BSP_CLOCKS_PLL_MUL(153U, 50U), ///< PLL multiplier of 153.50 + CGC_PLL_MUL_153_66 = BSP_CLOCKS_PLL_MUL(153U, 66U), ///< PLL multiplier of 153.66 + CGC_PLL_MUL_154_0 = BSP_CLOCKS_PLL_MUL(154U, 0U), ///< PLL multiplier of 154.00 + CGC_PLL_MUL_154_33 = BSP_CLOCKS_PLL_MUL(154U, 33U), ///< PLL multiplier of 154.33 + CGC_PLL_MUL_154_5 = BSP_CLOCKS_PLL_MUL(154U, 50U), ///< PLL multiplier of 154.50 + CGC_PLL_MUL_154_66 = BSP_CLOCKS_PLL_MUL(154U, 66U), ///< PLL multiplier of 154.66 + CGC_PLL_MUL_155_0 = BSP_CLOCKS_PLL_MUL(155U, 0U), ///< PLL multiplier of 155.00 + CGC_PLL_MUL_155_33 = BSP_CLOCKS_PLL_MUL(155U, 33U), ///< PLL multiplier of 155.33 + CGC_PLL_MUL_155_5 = BSP_CLOCKS_PLL_MUL(155U, 50U), ///< PLL multiplier of 155.50 + CGC_PLL_MUL_155_66 = BSP_CLOCKS_PLL_MUL(155U, 66U), ///< PLL multiplier of 155.66 + CGC_PLL_MUL_156_0 = BSP_CLOCKS_PLL_MUL(156U, 0U), ///< PLL multiplier of 156.00 + CGC_PLL_MUL_156_33 = BSP_CLOCKS_PLL_MUL(156U, 33U), ///< PLL multiplier of 156.33 + CGC_PLL_MUL_156_5 = BSP_CLOCKS_PLL_MUL(156U, 50U), ///< PLL multiplier of 156.50 + CGC_PLL_MUL_156_66 = BSP_CLOCKS_PLL_MUL(156U, 66U), ///< PLL multiplier of 156.66 + CGC_PLL_MUL_157_0 = BSP_CLOCKS_PLL_MUL(157U, 0U), ///< PLL multiplier of 157.00 + CGC_PLL_MUL_157_33 = BSP_CLOCKS_PLL_MUL(157U, 33U), ///< PLL multiplier of 157.33 + CGC_PLL_MUL_157_5 = BSP_CLOCKS_PLL_MUL(157U, 50U), ///< PLL multiplier of 157.50 + CGC_PLL_MUL_157_66 = BSP_CLOCKS_PLL_MUL(157U, 66U), ///< PLL multiplier of 157.66 + CGC_PLL_MUL_158_0 = BSP_CLOCKS_PLL_MUL(158U, 0U), ///< PLL multiplier of 158.00 + CGC_PLL_MUL_158_33 = BSP_CLOCKS_PLL_MUL(158U, 33U), ///< PLL multiplier of 158.33 + CGC_PLL_MUL_158_5 = BSP_CLOCKS_PLL_MUL(158U, 50U), ///< PLL multiplier of 158.50 + CGC_PLL_MUL_158_66 = BSP_CLOCKS_PLL_MUL(158U, 66U), ///< PLL multiplier of 158.66 + CGC_PLL_MUL_159_0 = BSP_CLOCKS_PLL_MUL(159U, 0U), ///< PLL multiplier of 159.00 + CGC_PLL_MUL_159_33 = BSP_CLOCKS_PLL_MUL(159U, 33U), ///< PLL multiplier of 159.33 + CGC_PLL_MUL_159_5 = BSP_CLOCKS_PLL_MUL(159U, 50U), ///< PLL multiplier of 159.50 + CGC_PLL_MUL_159_66 = BSP_CLOCKS_PLL_MUL(159U, 66U), ///< PLL multiplier of 159.66 + CGC_PLL_MUL_160_0 = BSP_CLOCKS_PLL_MUL(160U, 0U), ///< PLL multiplier of 160.00 + CGC_PLL_MUL_160_33 = BSP_CLOCKS_PLL_MUL(160U, 33U), ///< PLL multiplier of 160.33 + CGC_PLL_MUL_160_5 = BSP_CLOCKS_PLL_MUL(160U, 50U), ///< PLL multiplier of 160.50 + CGC_PLL_MUL_160_66 = BSP_CLOCKS_PLL_MUL(160U, 66U), ///< PLL multiplier of 160.66 + CGC_PLL_MUL_161_0 = BSP_CLOCKS_PLL_MUL(161U, 0U), ///< PLL multiplier of 161.00 + CGC_PLL_MUL_161_33 = BSP_CLOCKS_PLL_MUL(161U, 33U), ///< PLL multiplier of 161.33 + CGC_PLL_MUL_161_5 = BSP_CLOCKS_PLL_MUL(161U, 50U), ///< PLL multiplier of 161.50 + CGC_PLL_MUL_161_66 = BSP_CLOCKS_PLL_MUL(161U, 66U), ///< PLL multiplier of 161.66 + CGC_PLL_MUL_162_0 = BSP_CLOCKS_PLL_MUL(162U, 0U), ///< PLL multiplier of 162.00 + CGC_PLL_MUL_162_33 = BSP_CLOCKS_PLL_MUL(162U, 33U), ///< PLL multiplier of 162.33 + CGC_PLL_MUL_162_5 = BSP_CLOCKS_PLL_MUL(162U, 50U), ///< PLL multiplier of 162.50 + CGC_PLL_MUL_162_66 = BSP_CLOCKS_PLL_MUL(162U, 66U), ///< PLL multiplier of 162.66 + CGC_PLL_MUL_163_0 = BSP_CLOCKS_PLL_MUL(163U, 0U), ///< PLL multiplier of 163.00 + CGC_PLL_MUL_163_33 = BSP_CLOCKS_PLL_MUL(163U, 33U), ///< PLL multiplier of 163.33 + CGC_PLL_MUL_163_5 = BSP_CLOCKS_PLL_MUL(163U, 50U), ///< PLL multiplier of 163.50 + CGC_PLL_MUL_163_66 = BSP_CLOCKS_PLL_MUL(163U, 66U), ///< PLL multiplier of 163.66 + CGC_PLL_MUL_164_0 = BSP_CLOCKS_PLL_MUL(164U, 0U), ///< PLL multiplier of 164.00 + CGC_PLL_MUL_164_33 = BSP_CLOCKS_PLL_MUL(164U, 33U), ///< PLL multiplier of 164.33 + CGC_PLL_MUL_164_5 = BSP_CLOCKS_PLL_MUL(164U, 50U), ///< PLL multiplier of 164.50 + CGC_PLL_MUL_164_66 = BSP_CLOCKS_PLL_MUL(164U, 66U), ///< PLL multiplier of 164.66 + CGC_PLL_MUL_165_0 = BSP_CLOCKS_PLL_MUL(165U, 0U), ///< PLL multiplier of 165.00 + CGC_PLL_MUL_165_33 = BSP_CLOCKS_PLL_MUL(165U, 33U), ///< PLL multiplier of 165.33 + CGC_PLL_MUL_165_5 = BSP_CLOCKS_PLL_MUL(165U, 50U), ///< PLL multiplier of 165.50 + CGC_PLL_MUL_165_66 = BSP_CLOCKS_PLL_MUL(165U, 66U), ///< PLL multiplier of 165.66 + CGC_PLL_MUL_166_0 = BSP_CLOCKS_PLL_MUL(166U, 0U), ///< PLL multiplier of 166.00 + CGC_PLL_MUL_166_33 = BSP_CLOCKS_PLL_MUL(166U, 33U), ///< PLL multiplier of 166.33 + CGC_PLL_MUL_166_5 = BSP_CLOCKS_PLL_MUL(166U, 50U), ///< PLL multiplier of 166.50 + CGC_PLL_MUL_166_66 = BSP_CLOCKS_PLL_MUL(166U, 66U), ///< PLL multiplier of 166.66 + CGC_PLL_MUL_167_0 = BSP_CLOCKS_PLL_MUL(167U, 0U), ///< PLL multiplier of 167.00 + CGC_PLL_MUL_167_33 = BSP_CLOCKS_PLL_MUL(167U, 33U), ///< PLL multiplier of 167.33 + CGC_PLL_MUL_167_5 = BSP_CLOCKS_PLL_MUL(167U, 50U), ///< PLL multiplier of 167.50 + CGC_PLL_MUL_167_66 = BSP_CLOCKS_PLL_MUL(167U, 66U), ///< PLL multiplier of 167.66 + CGC_PLL_MUL_168_0 = BSP_CLOCKS_PLL_MUL(168U, 0U), ///< PLL multiplier of 168.00 + CGC_PLL_MUL_168_33 = BSP_CLOCKS_PLL_MUL(168U, 33U), ///< PLL multiplier of 168.33 + CGC_PLL_MUL_168_5 = BSP_CLOCKS_PLL_MUL(168U, 50U), ///< PLL multiplier of 168.50 + CGC_PLL_MUL_168_66 = BSP_CLOCKS_PLL_MUL(168U, 66U), ///< PLL multiplier of 168.66 + CGC_PLL_MUL_169_0 = BSP_CLOCKS_PLL_MUL(169U, 0U), ///< PLL multiplier of 169.00 + CGC_PLL_MUL_169_33 = BSP_CLOCKS_PLL_MUL(169U, 33U), ///< PLL multiplier of 169.33 + CGC_PLL_MUL_169_5 = BSP_CLOCKS_PLL_MUL(169U, 50U), ///< PLL multiplier of 169.50 + CGC_PLL_MUL_169_66 = BSP_CLOCKS_PLL_MUL(169U, 66U), ///< PLL multiplier of 169.66 + CGC_PLL_MUL_170_0 = BSP_CLOCKS_PLL_MUL(170U, 0U), ///< PLL multiplier of 170.00 + CGC_PLL_MUL_170_33 = BSP_CLOCKS_PLL_MUL(170U, 33U), ///< PLL multiplier of 170.33 + CGC_PLL_MUL_170_5 = BSP_CLOCKS_PLL_MUL(170U, 50U), ///< PLL multiplier of 170.50 + CGC_PLL_MUL_170_66 = BSP_CLOCKS_PLL_MUL(170U, 66U), ///< PLL multiplier of 170.66 + CGC_PLL_MUL_171_0 = BSP_CLOCKS_PLL_MUL(171U, 0U), ///< PLL multiplier of 171.00 + CGC_PLL_MUL_171_33 = BSP_CLOCKS_PLL_MUL(171U, 33U), ///< PLL multiplier of 171.33 + CGC_PLL_MUL_171_5 = BSP_CLOCKS_PLL_MUL(171U, 50U), ///< PLL multiplier of 171.50 + CGC_PLL_MUL_171_66 = BSP_CLOCKS_PLL_MUL(171U, 66U), ///< PLL multiplier of 171.66 + CGC_PLL_MUL_172_0 = BSP_CLOCKS_PLL_MUL(172U, 0U), ///< PLL multiplier of 172.00 + CGC_PLL_MUL_172_33 = BSP_CLOCKS_PLL_MUL(172U, 33U), ///< PLL multiplier of 172.33 + CGC_PLL_MUL_172_5 = BSP_CLOCKS_PLL_MUL(172U, 50U), ///< PLL multiplier of 172.50 + CGC_PLL_MUL_172_66 = BSP_CLOCKS_PLL_MUL(172U, 66U), ///< PLL multiplier of 172.66 + CGC_PLL_MUL_173_0 = BSP_CLOCKS_PLL_MUL(173U, 0U), ///< PLL multiplier of 173.00 + CGC_PLL_MUL_173_33 = BSP_CLOCKS_PLL_MUL(173U, 33U), ///< PLL multiplier of 173.33 + CGC_PLL_MUL_173_5 = BSP_CLOCKS_PLL_MUL(173U, 50U), ///< PLL multiplier of 173.50 + CGC_PLL_MUL_173_66 = BSP_CLOCKS_PLL_MUL(173U, 66U), ///< PLL multiplier of 173.66 + CGC_PLL_MUL_174_0 = BSP_CLOCKS_PLL_MUL(174U, 0U), ///< PLL multiplier of 174.00 + CGC_PLL_MUL_174_33 = BSP_CLOCKS_PLL_MUL(174U, 33U), ///< PLL multiplier of 174.33 + CGC_PLL_MUL_174_5 = BSP_CLOCKS_PLL_MUL(174U, 50U), ///< PLL multiplier of 174.50 + CGC_PLL_MUL_174_66 = BSP_CLOCKS_PLL_MUL(174U, 66U), ///< PLL multiplier of 174.66 + CGC_PLL_MUL_175_0 = BSP_CLOCKS_PLL_MUL(175U, 0U), ///< PLL multiplier of 175.00 + CGC_PLL_MUL_175_33 = BSP_CLOCKS_PLL_MUL(175U, 33U), ///< PLL multiplier of 175.33 + CGC_PLL_MUL_175_5 = BSP_CLOCKS_PLL_MUL(175U, 50U), ///< PLL multiplier of 175.50 + CGC_PLL_MUL_175_66 = BSP_CLOCKS_PLL_MUL(175U, 66U), ///< PLL multiplier of 175.66 + CGC_PLL_MUL_176_0 = BSP_CLOCKS_PLL_MUL(176U, 0U), ///< PLL multiplier of 176.00 + CGC_PLL_MUL_176_33 = BSP_CLOCKS_PLL_MUL(176U, 33U), ///< PLL multiplier of 176.33 + CGC_PLL_MUL_176_5 = BSP_CLOCKS_PLL_MUL(176U, 50U), ///< PLL multiplier of 176.50 + CGC_PLL_MUL_176_66 = BSP_CLOCKS_PLL_MUL(176U, 66U), ///< PLL multiplier of 176.66 + CGC_PLL_MUL_177_0 = BSP_CLOCKS_PLL_MUL(177U, 0U), ///< PLL multiplier of 177.00 + CGC_PLL_MUL_177_33 = BSP_CLOCKS_PLL_MUL(177U, 33U), ///< PLL multiplier of 177.33 + CGC_PLL_MUL_177_5 = BSP_CLOCKS_PLL_MUL(177U, 50U), ///< PLL multiplier of 177.50 + CGC_PLL_MUL_177_66 = BSP_CLOCKS_PLL_MUL(177U, 66U), ///< PLL multiplier of 177.66 + CGC_PLL_MUL_178_0 = BSP_CLOCKS_PLL_MUL(178U, 0U), ///< PLL multiplier of 178.00 + CGC_PLL_MUL_178_33 = BSP_CLOCKS_PLL_MUL(178U, 33U), ///< PLL multiplier of 178.33 + CGC_PLL_MUL_178_5 = BSP_CLOCKS_PLL_MUL(178U, 50U), ///< PLL multiplier of 178.50 + CGC_PLL_MUL_178_66 = BSP_CLOCKS_PLL_MUL(178U, 66U), ///< PLL multiplier of 178.66 + CGC_PLL_MUL_179_0 = BSP_CLOCKS_PLL_MUL(179U, 0U), ///< PLL multiplier of 179.00 + CGC_PLL_MUL_179_33 = BSP_CLOCKS_PLL_MUL(179U, 33U), ///< PLL multiplier of 179.33 + CGC_PLL_MUL_179_5 = BSP_CLOCKS_PLL_MUL(179U, 50U), ///< PLL multiplier of 179.50 + CGC_PLL_MUL_179_66 = BSP_CLOCKS_PLL_MUL(179U, 66U), ///< PLL multiplier of 179.66 + CGC_PLL_MUL_180_0 = BSP_CLOCKS_PLL_MUL(180U, 0U), ///< PLL multiplier of 180.00 + CGC_PLL_MUL_180_33 = BSP_CLOCKS_PLL_MUL(180U, 33U), ///< PLL multiplier of 180.33 + CGC_PLL_MUL_180_5 = BSP_CLOCKS_PLL_MUL(180U, 50U), ///< PLL multiplier of 180.50 + CGC_PLL_MUL_180_66 = BSP_CLOCKS_PLL_MUL(180U, 66U), ///< PLL multiplier of 180.66 + CGC_PLL_MUL_181_0 = BSP_CLOCKS_PLL_MUL(181U, 0U), ///< PLL multiplier of 181.00 + CGC_PLL_MUL_181_33 = BSP_CLOCKS_PLL_MUL(181U, 33U), ///< PLL multiplier of 181.33 + CGC_PLL_MUL_181_5 = BSP_CLOCKS_PLL_MUL(181U, 50U), ///< PLL multiplier of 181.50 + CGC_PLL_MUL_181_66 = BSP_CLOCKS_PLL_MUL(181U, 66U), ///< PLL multiplier of 181.66 + CGC_PLL_MUL_182_0 = BSP_CLOCKS_PLL_MUL(182U, 0U), ///< PLL multiplier of 182.00 + CGC_PLL_MUL_182_33 = BSP_CLOCKS_PLL_MUL(182U, 33U), ///< PLL multiplier of 182.33 + CGC_PLL_MUL_182_5 = BSP_CLOCKS_PLL_MUL(182U, 50U), ///< PLL multiplier of 182.50 + CGC_PLL_MUL_182_66 = BSP_CLOCKS_PLL_MUL(182U, 66U), ///< PLL multiplier of 182.66 + CGC_PLL_MUL_183_0 = BSP_CLOCKS_PLL_MUL(183U, 0U), ///< PLL multiplier of 183.00 + CGC_PLL_MUL_183_33 = BSP_CLOCKS_PLL_MUL(183U, 33U), ///< PLL multiplier of 183.33 + CGC_PLL_MUL_183_5 = BSP_CLOCKS_PLL_MUL(183U, 50U), ///< PLL multiplier of 183.50 + CGC_PLL_MUL_183_66 = BSP_CLOCKS_PLL_MUL(183U, 66U), ///< PLL multiplier of 183.66 + CGC_PLL_MUL_184_0 = BSP_CLOCKS_PLL_MUL(184U, 0U), ///< PLL multiplier of 184.00 + CGC_PLL_MUL_184_33 = BSP_CLOCKS_PLL_MUL(184U, 33U), ///< PLL multiplier of 184.33 + CGC_PLL_MUL_184_5 = BSP_CLOCKS_PLL_MUL(184U, 50U), ///< PLL multiplier of 184.50 + CGC_PLL_MUL_184_66 = BSP_CLOCKS_PLL_MUL(184U, 66U), ///< PLL multiplier of 184.66 + CGC_PLL_MUL_185_0 = BSP_CLOCKS_PLL_MUL(185U, 0U), ///< PLL multiplier of 185.00 + CGC_PLL_MUL_185_33 = BSP_CLOCKS_PLL_MUL(185U, 33U), ///< PLL multiplier of 185.33 + CGC_PLL_MUL_185_5 = BSP_CLOCKS_PLL_MUL(185U, 50U), ///< PLL multiplier of 185.50 + CGC_PLL_MUL_185_66 = BSP_CLOCKS_PLL_MUL(185U, 66U), ///< PLL multiplier of 185.66 + CGC_PLL_MUL_186_0 = BSP_CLOCKS_PLL_MUL(186U, 0U), ///< PLL multiplier of 186.00 + CGC_PLL_MUL_186_33 = BSP_CLOCKS_PLL_MUL(186U, 33U), ///< PLL multiplier of 186.33 + CGC_PLL_MUL_186_5 = BSP_CLOCKS_PLL_MUL(186U, 50U), ///< PLL multiplier of 186.50 + CGC_PLL_MUL_186_66 = BSP_CLOCKS_PLL_MUL(186U, 66U), ///< PLL multiplier of 186.66 + CGC_PLL_MUL_187_0 = BSP_CLOCKS_PLL_MUL(187U, 0U), ///< PLL multiplier of 187.00 + CGC_PLL_MUL_187_33 = BSP_CLOCKS_PLL_MUL(187U, 33U), ///< PLL multiplier of 187.33 + CGC_PLL_MUL_187_5 = BSP_CLOCKS_PLL_MUL(187U, 50U), ///< PLL multiplier of 187.50 + CGC_PLL_MUL_187_66 = BSP_CLOCKS_PLL_MUL(187U, 66U), ///< PLL multiplier of 187.66 + CGC_PLL_MUL_188_0 = BSP_CLOCKS_PLL_MUL(188U, 0U), ///< PLL multiplier of 188.00 + CGC_PLL_MUL_188_33 = BSP_CLOCKS_PLL_MUL(188U, 33U), ///< PLL multiplier of 188.33 + CGC_PLL_MUL_188_5 = BSP_CLOCKS_PLL_MUL(188U, 50U), ///< PLL multiplier of 188.50 + CGC_PLL_MUL_188_66 = BSP_CLOCKS_PLL_MUL(188U, 66U), ///< PLL multiplier of 188.66 + CGC_PLL_MUL_189_0 = BSP_CLOCKS_PLL_MUL(189U, 0U), ///< PLL multiplier of 189.00 + CGC_PLL_MUL_189_33 = BSP_CLOCKS_PLL_MUL(189U, 33U), ///< PLL multiplier of 189.33 + CGC_PLL_MUL_189_5 = BSP_CLOCKS_PLL_MUL(189U, 50U), ///< PLL multiplier of 189.50 + CGC_PLL_MUL_189_66 = BSP_CLOCKS_PLL_MUL(189U, 66U), ///< PLL multiplier of 189.66 + CGC_PLL_MUL_190_0 = BSP_CLOCKS_PLL_MUL(190U, 0U), ///< PLL multiplier of 190.00 + CGC_PLL_MUL_190_33 = BSP_CLOCKS_PLL_MUL(190U, 33U), ///< PLL multiplier of 190.33 + CGC_PLL_MUL_190_5 = BSP_CLOCKS_PLL_MUL(190U, 50U), ///< PLL multiplier of 190.50 + CGC_PLL_MUL_190_66 = BSP_CLOCKS_PLL_MUL(190U, 66U), ///< PLL multiplier of 190.66 + CGC_PLL_MUL_191_0 = BSP_CLOCKS_PLL_MUL(191U, 0U), ///< PLL multiplier of 191.00 + CGC_PLL_MUL_191_33 = BSP_CLOCKS_PLL_MUL(191U, 33U), ///< PLL multiplier of 191.33 + CGC_PLL_MUL_191_5 = BSP_CLOCKS_PLL_MUL(191U, 50U), ///< PLL multiplier of 191.50 + CGC_PLL_MUL_191_66 = BSP_CLOCKS_PLL_MUL(191U, 66U), ///< PLL multiplier of 191.66 + CGC_PLL_MUL_192_0 = BSP_CLOCKS_PLL_MUL(192U, 0U), ///< PLL multiplier of 192.00 + CGC_PLL_MUL_192_33 = BSP_CLOCKS_PLL_MUL(192U, 33U), ///< PLL multiplier of 192.33 + CGC_PLL_MUL_192_5 = BSP_CLOCKS_PLL_MUL(192U, 50U), ///< PLL multiplier of 192.50 + CGC_PLL_MUL_192_66 = BSP_CLOCKS_PLL_MUL(192U, 66U), ///< PLL multiplier of 192.66 + CGC_PLL_MUL_193_0 = BSP_CLOCKS_PLL_MUL(193U, 0U), ///< PLL multiplier of 193.00 + CGC_PLL_MUL_193_33 = BSP_CLOCKS_PLL_MUL(193U, 33U), ///< PLL multiplier of 193.33 + CGC_PLL_MUL_193_5 = BSP_CLOCKS_PLL_MUL(193U, 50U), ///< PLL multiplier of 193.50 + CGC_PLL_MUL_193_66 = BSP_CLOCKS_PLL_MUL(193U, 66U), ///< PLL multiplier of 193.66 + CGC_PLL_MUL_194_0 = BSP_CLOCKS_PLL_MUL(194U, 0U), ///< PLL multiplier of 194.00 + CGC_PLL_MUL_194_33 = BSP_CLOCKS_PLL_MUL(194U, 33U), ///< PLL multiplier of 194.33 + CGC_PLL_MUL_194_5 = BSP_CLOCKS_PLL_MUL(194U, 50U), ///< PLL multiplier of 194.50 + CGC_PLL_MUL_194_66 = BSP_CLOCKS_PLL_MUL(194U, 66U), ///< PLL multiplier of 194.66 + CGC_PLL_MUL_195_0 = BSP_CLOCKS_PLL_MUL(195U, 0U), ///< PLL multiplier of 195.00 + CGC_PLL_MUL_195_33 = BSP_CLOCKS_PLL_MUL(195U, 33U), ///< PLL multiplier of 195.33 + CGC_PLL_MUL_195_5 = BSP_CLOCKS_PLL_MUL(195U, 50U), ///< PLL multiplier of 195.50 + CGC_PLL_MUL_195_66 = BSP_CLOCKS_PLL_MUL(195U, 66U), ///< PLL multiplier of 195.66 + CGC_PLL_MUL_196_0 = BSP_CLOCKS_PLL_MUL(196U, 0U), ///< PLL multiplier of 196.00 + CGC_PLL_MUL_196_33 = BSP_CLOCKS_PLL_MUL(196U, 33U), ///< PLL multiplier of 196.33 + CGC_PLL_MUL_196_5 = BSP_CLOCKS_PLL_MUL(196U, 50U), ///< PLL multiplier of 196.50 + CGC_PLL_MUL_196_66 = BSP_CLOCKS_PLL_MUL(196U, 66U), ///< PLL multiplier of 196.66 + CGC_PLL_MUL_197_0 = BSP_CLOCKS_PLL_MUL(197U, 0U), ///< PLL multiplier of 197.00 + CGC_PLL_MUL_197_33 = BSP_CLOCKS_PLL_MUL(197U, 33U), ///< PLL multiplier of 197.33 + CGC_PLL_MUL_197_5 = BSP_CLOCKS_PLL_MUL(197U, 50U), ///< PLL multiplier of 197.50 + CGC_PLL_MUL_197_66 = BSP_CLOCKS_PLL_MUL(197U, 66U), ///< PLL multiplier of 197.66 + CGC_PLL_MUL_198_0 = BSP_CLOCKS_PLL_MUL(198U, 0U), ///< PLL multiplier of 198.00 + CGC_PLL_MUL_198_33 = BSP_CLOCKS_PLL_MUL(198U, 33U), ///< PLL multiplier of 198.33 + CGC_PLL_MUL_198_5 = BSP_CLOCKS_PLL_MUL(198U, 50U), ///< PLL multiplier of 198.50 + CGC_PLL_MUL_198_66 = BSP_CLOCKS_PLL_MUL(198U, 66U), ///< PLL multiplier of 198.66 + CGC_PLL_MUL_199_0 = BSP_CLOCKS_PLL_MUL(199U, 0U), ///< PLL multiplier of 199.00 + CGC_PLL_MUL_199_33 = BSP_CLOCKS_PLL_MUL(199U, 33U), ///< PLL multiplier of 199.33 + CGC_PLL_MUL_199_5 = BSP_CLOCKS_PLL_MUL(199U, 50U), ///< PLL multiplier of 199.50 + CGC_PLL_MUL_199_66 = BSP_CLOCKS_PLL_MUL(199U, 66U), ///< PLL multiplier of 199.66 + CGC_PLL_MUL_200_0 = BSP_CLOCKS_PLL_MUL(200U, 0U), ///< PLL multiplier of 200.00 + CGC_PLL_MUL_200_33 = BSP_CLOCKS_PLL_MUL(200U, 33U), ///< PLL multiplier of 200.33 + CGC_PLL_MUL_200_5 = BSP_CLOCKS_PLL_MUL(200U, 50U), ///< PLL multiplier of 200.50 + CGC_PLL_MUL_200_66 = BSP_CLOCKS_PLL_MUL(200U, 66U), ///< PLL multiplier of 200.66 + CGC_PLL_MUL_201_0 = BSP_CLOCKS_PLL_MUL(201U, 0U), ///< PLL multiplier of 201.00 + CGC_PLL_MUL_201_33 = BSP_CLOCKS_PLL_MUL(201U, 33U), ///< PLL multiplier of 201.33 + CGC_PLL_MUL_201_5 = BSP_CLOCKS_PLL_MUL(201U, 50U), ///< PLL multiplier of 201.50 + CGC_PLL_MUL_201_66 = BSP_CLOCKS_PLL_MUL(201U, 66U), ///< PLL multiplier of 201.66 + CGC_PLL_MUL_202_0 = BSP_CLOCKS_PLL_MUL(202U, 0U), ///< PLL multiplier of 202.00 + CGC_PLL_MUL_202_33 = BSP_CLOCKS_PLL_MUL(202U, 33U), ///< PLL multiplier of 202.33 + CGC_PLL_MUL_202_5 = BSP_CLOCKS_PLL_MUL(202U, 50U), ///< PLL multiplier of 202.50 + CGC_PLL_MUL_202_66 = BSP_CLOCKS_PLL_MUL(202U, 66U), ///< PLL multiplier of 202.66 + CGC_PLL_MUL_203_0 = BSP_CLOCKS_PLL_MUL(203U, 0U), ///< PLL multiplier of 203.00 + CGC_PLL_MUL_203_33 = BSP_CLOCKS_PLL_MUL(203U, 33U), ///< PLL multiplier of 203.33 + CGC_PLL_MUL_203_5 = BSP_CLOCKS_PLL_MUL(203U, 50U), ///< PLL multiplier of 203.50 + CGC_PLL_MUL_203_66 = BSP_CLOCKS_PLL_MUL(203U, 66U), ///< PLL multiplier of 203.66 + CGC_PLL_MUL_204_0 = BSP_CLOCKS_PLL_MUL(204U, 0U), ///< PLL multiplier of 204.00 + CGC_PLL_MUL_204_33 = BSP_CLOCKS_PLL_MUL(204U, 33U), ///< PLL multiplier of 204.33 + CGC_PLL_MUL_204_5 = BSP_CLOCKS_PLL_MUL(204U, 50U), ///< PLL multiplier of 204.50 + CGC_PLL_MUL_204_66 = BSP_CLOCKS_PLL_MUL(204U, 66U), ///< PLL multiplier of 204.66 + CGC_PLL_MUL_205_0 = BSP_CLOCKS_PLL_MUL(205U, 0U), ///< PLL multiplier of 205.00 + CGC_PLL_MUL_205_33 = BSP_CLOCKS_PLL_MUL(205U, 33U), ///< PLL multiplier of 205.33 + CGC_PLL_MUL_205_5 = BSP_CLOCKS_PLL_MUL(205U, 50U), ///< PLL multiplier of 205.50 + CGC_PLL_MUL_205_66 = BSP_CLOCKS_PLL_MUL(205U, 66U), ///< PLL multiplier of 205.66 + CGC_PLL_MUL_206_0 = BSP_CLOCKS_PLL_MUL(206U, 0U), ///< PLL multiplier of 206.00 + CGC_PLL_MUL_206_33 = BSP_CLOCKS_PLL_MUL(206U, 33U), ///< PLL multiplier of 206.33 + CGC_PLL_MUL_206_5 = BSP_CLOCKS_PLL_MUL(206U, 50U), ///< PLL multiplier of 206.50 + CGC_PLL_MUL_206_66 = BSP_CLOCKS_PLL_MUL(206U, 66U), ///< PLL multiplier of 206.66 + CGC_PLL_MUL_207_0 = BSP_CLOCKS_PLL_MUL(207U, 0U), ///< PLL multiplier of 207.00 + CGC_PLL_MUL_207_33 = BSP_CLOCKS_PLL_MUL(207U, 33U), ///< PLL multiplier of 207.33 + CGC_PLL_MUL_207_5 = BSP_CLOCKS_PLL_MUL(207U, 50U), ///< PLL multiplier of 207.50 + CGC_PLL_MUL_207_66 = BSP_CLOCKS_PLL_MUL(207U, 66U), ///< PLL multiplier of 207.66 + CGC_PLL_MUL_208_0 = BSP_CLOCKS_PLL_MUL(208U, 0U), ///< PLL multiplier of 208.00 + CGC_PLL_MUL_208_33 = BSP_CLOCKS_PLL_MUL(208U, 33U), ///< PLL multiplier of 208.33 + CGC_PLL_MUL_208_5 = BSP_CLOCKS_PLL_MUL(208U, 50U), ///< PLL multiplier of 208.50 + CGC_PLL_MUL_208_66 = BSP_CLOCKS_PLL_MUL(208U, 66U), ///< PLL multiplier of 208.66 + CGC_PLL_MUL_209_0 = BSP_CLOCKS_PLL_MUL(209U, 0U), ///< PLL multiplier of 209.00 + CGC_PLL_MUL_209_33 = BSP_CLOCKS_PLL_MUL(209U, 33U), ///< PLL multiplier of 209.33 + CGC_PLL_MUL_209_5 = BSP_CLOCKS_PLL_MUL(209U, 50U), ///< PLL multiplier of 209.50 + CGC_PLL_MUL_209_66 = BSP_CLOCKS_PLL_MUL(209U, 66U), ///< PLL multiplier of 209.66 + CGC_PLL_MUL_210_0 = BSP_CLOCKS_PLL_MUL(210U, 0U), ///< PLL multiplier of 210.00 + CGC_PLL_MUL_210_33 = BSP_CLOCKS_PLL_MUL(210U, 33U), ///< PLL multiplier of 210.33 + CGC_PLL_MUL_210_5 = BSP_CLOCKS_PLL_MUL(210U, 50U), ///< PLL multiplier of 210.50 + CGC_PLL_MUL_210_66 = BSP_CLOCKS_PLL_MUL(210U, 66U), ///< PLL multiplier of 210.66 + CGC_PLL_MUL_211_0 = BSP_CLOCKS_PLL_MUL(211U, 0U), ///< PLL multiplier of 211.00 + CGC_PLL_MUL_211_33 = BSP_CLOCKS_PLL_MUL(211U, 33U), ///< PLL multiplier of 211.33 + CGC_PLL_MUL_211_5 = BSP_CLOCKS_PLL_MUL(211U, 50U), ///< PLL multiplier of 211.50 + CGC_PLL_MUL_211_66 = BSP_CLOCKS_PLL_MUL(211U, 66U), ///< PLL multiplier of 211.66 + CGC_PLL_MUL_212_0 = BSP_CLOCKS_PLL_MUL(212U, 0U), ///< PLL multiplier of 212.00 + CGC_PLL_MUL_212_33 = BSP_CLOCKS_PLL_MUL(212U, 33U), ///< PLL multiplier of 212.33 + CGC_PLL_MUL_212_5 = BSP_CLOCKS_PLL_MUL(212U, 50U), ///< PLL multiplier of 212.50 + CGC_PLL_MUL_212_66 = BSP_CLOCKS_PLL_MUL(212U, 66U), ///< PLL multiplier of 212.66 + CGC_PLL_MUL_213_0 = BSP_CLOCKS_PLL_MUL(213U, 0U), ///< PLL multiplier of 213.00 + CGC_PLL_MUL_213_33 = BSP_CLOCKS_PLL_MUL(213U, 33U), ///< PLL multiplier of 213.33 + CGC_PLL_MUL_213_5 = BSP_CLOCKS_PLL_MUL(213U, 50U), ///< PLL multiplier of 213.50 + CGC_PLL_MUL_213_66 = BSP_CLOCKS_PLL_MUL(213U, 66U), ///< PLL multiplier of 213.66 + CGC_PLL_MUL_214_0 = BSP_CLOCKS_PLL_MUL(214U, 0U), ///< PLL multiplier of 214.00 + CGC_PLL_MUL_214_33 = BSP_CLOCKS_PLL_MUL(214U, 33U), ///< PLL multiplier of 214.33 + CGC_PLL_MUL_214_5 = BSP_CLOCKS_PLL_MUL(214U, 50U), ///< PLL multiplier of 214.50 + CGC_PLL_MUL_214_66 = BSP_CLOCKS_PLL_MUL(214U, 66U), ///< PLL multiplier of 214.66 + CGC_PLL_MUL_215_0 = BSP_CLOCKS_PLL_MUL(215U, 0U), ///< PLL multiplier of 215.00 + CGC_PLL_MUL_215_33 = BSP_CLOCKS_PLL_MUL(215U, 33U), ///< PLL multiplier of 215.33 + CGC_PLL_MUL_215_5 = BSP_CLOCKS_PLL_MUL(215U, 50U), ///< PLL multiplier of 215.50 + CGC_PLL_MUL_215_66 = BSP_CLOCKS_PLL_MUL(215U, 66U), ///< PLL multiplier of 215.66 + CGC_PLL_MUL_216_0 = BSP_CLOCKS_PLL_MUL(216U, 0U), ///< PLL multiplier of 216.00 + CGC_PLL_MUL_216_33 = BSP_CLOCKS_PLL_MUL(216U, 33U), ///< PLL multiplier of 216.33 + CGC_PLL_MUL_216_5 = BSP_CLOCKS_PLL_MUL(216U, 50U), ///< PLL multiplier of 216.50 + CGC_PLL_MUL_216_66 = BSP_CLOCKS_PLL_MUL(216U, 66U), ///< PLL multiplier of 216.66 + CGC_PLL_MUL_217_0 = BSP_CLOCKS_PLL_MUL(217U, 0U), ///< PLL multiplier of 217.00 + CGC_PLL_MUL_217_33 = BSP_CLOCKS_PLL_MUL(217U, 33U), ///< PLL multiplier of 217.33 + CGC_PLL_MUL_217_5 = BSP_CLOCKS_PLL_MUL(217U, 50U), ///< PLL multiplier of 217.50 + CGC_PLL_MUL_217_66 = BSP_CLOCKS_PLL_MUL(217U, 66U), ///< PLL multiplier of 217.66 + CGC_PLL_MUL_218_0 = BSP_CLOCKS_PLL_MUL(218U, 0U), ///< PLL multiplier of 218.00 + CGC_PLL_MUL_218_33 = BSP_CLOCKS_PLL_MUL(218U, 33U), ///< PLL multiplier of 218.33 + CGC_PLL_MUL_218_5 = BSP_CLOCKS_PLL_MUL(218U, 50U), ///< PLL multiplier of 218.50 + CGC_PLL_MUL_218_66 = BSP_CLOCKS_PLL_MUL(218U, 66U), ///< PLL multiplier of 218.66 + CGC_PLL_MUL_219_0 = BSP_CLOCKS_PLL_MUL(219U, 0U), ///< PLL multiplier of 219.00 + CGC_PLL_MUL_219_33 = BSP_CLOCKS_PLL_MUL(219U, 33U), ///< PLL multiplier of 219.33 + CGC_PLL_MUL_219_5 = BSP_CLOCKS_PLL_MUL(219U, 50U), ///< PLL multiplier of 219.50 + CGC_PLL_MUL_219_66 = BSP_CLOCKS_PLL_MUL(219U, 66U), ///< PLL multiplier of 219.66 + CGC_PLL_MUL_220_0 = BSP_CLOCKS_PLL_MUL(220U, 0U), ///< PLL multiplier of 220.00 + CGC_PLL_MUL_220_33 = BSP_CLOCKS_PLL_MUL(220U, 33U), ///< PLL multiplier of 220.33 + CGC_PLL_MUL_220_5 = BSP_CLOCKS_PLL_MUL(220U, 50U), ///< PLL multiplier of 220.50 + CGC_PLL_MUL_220_66 = BSP_CLOCKS_PLL_MUL(220U, 66U), ///< PLL multiplier of 220.66 + CGC_PLL_MUL_221_0 = BSP_CLOCKS_PLL_MUL(221U, 0U), ///< PLL multiplier of 221.00 + CGC_PLL_MUL_221_33 = BSP_CLOCKS_PLL_MUL(221U, 33U), ///< PLL multiplier of 221.33 + CGC_PLL_MUL_221_5 = BSP_CLOCKS_PLL_MUL(221U, 50U), ///< PLL multiplier of 221.50 + CGC_PLL_MUL_221_66 = BSP_CLOCKS_PLL_MUL(221U, 66U), ///< PLL multiplier of 221.66 + CGC_PLL_MUL_222_0 = BSP_CLOCKS_PLL_MUL(222U, 0U), ///< PLL multiplier of 222.00 + CGC_PLL_MUL_222_33 = BSP_CLOCKS_PLL_MUL(222U, 33U), ///< PLL multiplier of 222.33 + CGC_PLL_MUL_222_5 = BSP_CLOCKS_PLL_MUL(222U, 50U), ///< PLL multiplier of 222.50 + CGC_PLL_MUL_222_66 = BSP_CLOCKS_PLL_MUL(222U, 66U), ///< PLL multiplier of 222.66 + CGC_PLL_MUL_223_0 = BSP_CLOCKS_PLL_MUL(223U, 0U), ///< PLL multiplier of 223.00 + CGC_PLL_MUL_223_33 = BSP_CLOCKS_PLL_MUL(223U, 33U), ///< PLL multiplier of 223.33 + CGC_PLL_MUL_223_5 = BSP_CLOCKS_PLL_MUL(223U, 50U), ///< PLL multiplier of 223.50 + CGC_PLL_MUL_223_66 = BSP_CLOCKS_PLL_MUL(223U, 66U), ///< PLL multiplier of 223.66 + CGC_PLL_MUL_224_0 = BSP_CLOCKS_PLL_MUL(224U, 0U), ///< PLL multiplier of 224.00 + CGC_PLL_MUL_224_33 = BSP_CLOCKS_PLL_MUL(224U, 33U), ///< PLL multiplier of 224.33 + CGC_PLL_MUL_224_5 = BSP_CLOCKS_PLL_MUL(224U, 50U), ///< PLL multiplier of 224.50 + CGC_PLL_MUL_224_66 = BSP_CLOCKS_PLL_MUL(224U, 66U), ///< PLL multiplier of 224.66 + CGC_PLL_MUL_225_0 = BSP_CLOCKS_PLL_MUL(225U, 0U), ///< PLL multiplier of 225.00 + CGC_PLL_MUL_225_33 = BSP_CLOCKS_PLL_MUL(225U, 33U), ///< PLL multiplier of 225.33 + CGC_PLL_MUL_225_5 = BSP_CLOCKS_PLL_MUL(225U, 50U), ///< PLL multiplier of 225.50 + CGC_PLL_MUL_225_66 = BSP_CLOCKS_PLL_MUL(225U, 66U), ///< PLL multiplier of 225.66 + CGC_PLL_MUL_226_0 = BSP_CLOCKS_PLL_MUL(226U, 0U), ///< PLL multiplier of 226.00 + CGC_PLL_MUL_226_33 = BSP_CLOCKS_PLL_MUL(226U, 33U), ///< PLL multiplier of 226.33 + CGC_PLL_MUL_226_5 = BSP_CLOCKS_PLL_MUL(226U, 50U), ///< PLL multiplier of 226.50 + CGC_PLL_MUL_226_66 = BSP_CLOCKS_PLL_MUL(226U, 66U), ///< PLL multiplier of 226.66 + CGC_PLL_MUL_227_0 = BSP_CLOCKS_PLL_MUL(227U, 0U), ///< PLL multiplier of 227.00 + CGC_PLL_MUL_227_33 = BSP_CLOCKS_PLL_MUL(227U, 33U), ///< PLL multiplier of 227.33 + CGC_PLL_MUL_227_5 = BSP_CLOCKS_PLL_MUL(227U, 50U), ///< PLL multiplier of 227.50 + CGC_PLL_MUL_227_66 = BSP_CLOCKS_PLL_MUL(227U, 66U), ///< PLL multiplier of 227.66 + CGC_PLL_MUL_228_0 = BSP_CLOCKS_PLL_MUL(228U, 0U), ///< PLL multiplier of 228.00 + CGC_PLL_MUL_228_33 = BSP_CLOCKS_PLL_MUL(228U, 33U), ///< PLL multiplier of 228.33 + CGC_PLL_MUL_228_5 = BSP_CLOCKS_PLL_MUL(228U, 50U), ///< PLL multiplier of 228.50 + CGC_PLL_MUL_228_66 = BSP_CLOCKS_PLL_MUL(228U, 66U), ///< PLL multiplier of 228.66 + CGC_PLL_MUL_229_0 = BSP_CLOCKS_PLL_MUL(229U, 0U), ///< PLL multiplier of 229.00 + CGC_PLL_MUL_229_33 = BSP_CLOCKS_PLL_MUL(229U, 33U), ///< PLL multiplier of 229.33 + CGC_PLL_MUL_229_5 = BSP_CLOCKS_PLL_MUL(229U, 50U), ///< PLL multiplier of 229.50 + CGC_PLL_MUL_229_66 = BSP_CLOCKS_PLL_MUL(229U, 66U), ///< PLL multiplier of 229.66 + CGC_PLL_MUL_230_0 = BSP_CLOCKS_PLL_MUL(230U, 0U), ///< PLL multiplier of 230.00 + CGC_PLL_MUL_230_33 = BSP_CLOCKS_PLL_MUL(230U, 33U), ///< PLL multiplier of 230.33 + CGC_PLL_MUL_230_5 = BSP_CLOCKS_PLL_MUL(230U, 50U), ///< PLL multiplier of 230.50 + CGC_PLL_MUL_230_66 = BSP_CLOCKS_PLL_MUL(230U, 66U), ///< PLL multiplier of 230.66 + CGC_PLL_MUL_231_0 = BSP_CLOCKS_PLL_MUL(231U, 0U), ///< PLL multiplier of 231.00 + CGC_PLL_MUL_231_33 = BSP_CLOCKS_PLL_MUL(231U, 33U), ///< PLL multiplier of 231.33 + CGC_PLL_MUL_231_5 = BSP_CLOCKS_PLL_MUL(231U, 50U), ///< PLL multiplier of 231.50 + CGC_PLL_MUL_231_66 = BSP_CLOCKS_PLL_MUL(231U, 66U), ///< PLL multiplier of 231.66 + CGC_PLL_MUL_232_0 = BSP_CLOCKS_PLL_MUL(232U, 0U), ///< PLL multiplier of 232.00 + CGC_PLL_MUL_232_33 = BSP_CLOCKS_PLL_MUL(232U, 33U), ///< PLL multiplier of 232.33 + CGC_PLL_MUL_232_5 = BSP_CLOCKS_PLL_MUL(232U, 50U), ///< PLL multiplier of 232.50 + CGC_PLL_MUL_232_66 = BSP_CLOCKS_PLL_MUL(232U, 66U), ///< PLL multiplier of 232.66 + CGC_PLL_MUL_233_0 = BSP_CLOCKS_PLL_MUL(233U, 0U), ///< PLL multiplier of 233.00 + CGC_PLL_MUL_233_33 = BSP_CLOCKS_PLL_MUL(233U, 33U), ///< PLL multiplier of 233.33 + CGC_PLL_MUL_233_5 = BSP_CLOCKS_PLL_MUL(233U, 50U), ///< PLL multiplier of 233.50 + CGC_PLL_MUL_233_66 = BSP_CLOCKS_PLL_MUL(233U, 66U), ///< PLL multiplier of 233.66 + CGC_PLL_MUL_234_0 = BSP_CLOCKS_PLL_MUL(234U, 0U), ///< PLL multiplier of 234.00 + CGC_PLL_MUL_234_33 = BSP_CLOCKS_PLL_MUL(234U, 33U), ///< PLL multiplier of 234.33 + CGC_PLL_MUL_234_5 = BSP_CLOCKS_PLL_MUL(234U, 50U), ///< PLL multiplier of 234.50 + CGC_PLL_MUL_234_66 = BSP_CLOCKS_PLL_MUL(234U, 66U), ///< PLL multiplier of 234.66 + CGC_PLL_MUL_235_0 = BSP_CLOCKS_PLL_MUL(235U, 0U), ///< PLL multiplier of 235.00 + CGC_PLL_MUL_235_33 = BSP_CLOCKS_PLL_MUL(235U, 33U), ///< PLL multiplier of 235.33 + CGC_PLL_MUL_235_5 = BSP_CLOCKS_PLL_MUL(235U, 50U), ///< PLL multiplier of 235.50 + CGC_PLL_MUL_235_66 = BSP_CLOCKS_PLL_MUL(235U, 66U), ///< PLL multiplier of 235.66 + CGC_PLL_MUL_236_0 = BSP_CLOCKS_PLL_MUL(236U, 0U), ///< PLL multiplier of 236.00 + CGC_PLL_MUL_236_33 = BSP_CLOCKS_PLL_MUL(236U, 33U), ///< PLL multiplier of 236.33 + CGC_PLL_MUL_236_5 = BSP_CLOCKS_PLL_MUL(236U, 50U), ///< PLL multiplier of 236.50 + CGC_PLL_MUL_236_66 = BSP_CLOCKS_PLL_MUL(236U, 66U), ///< PLL multiplier of 236.66 + CGC_PLL_MUL_237_0 = BSP_CLOCKS_PLL_MUL(237U, 0U), ///< PLL multiplier of 237.00 + CGC_PLL_MUL_237_33 = BSP_CLOCKS_PLL_MUL(237U, 33U), ///< PLL multiplier of 237.33 + CGC_PLL_MUL_237_5 = BSP_CLOCKS_PLL_MUL(237U, 50U), ///< PLL multiplier of 237.50 + CGC_PLL_MUL_237_66 = BSP_CLOCKS_PLL_MUL(237U, 66U), ///< PLL multiplier of 237.66 + CGC_PLL_MUL_238_0 = BSP_CLOCKS_PLL_MUL(238U, 0U), ///< PLL multiplier of 238.00 + CGC_PLL_MUL_238_33 = BSP_CLOCKS_PLL_MUL(238U, 33U), ///< PLL multiplier of 238.33 + CGC_PLL_MUL_238_5 = BSP_CLOCKS_PLL_MUL(238U, 50U), ///< PLL multiplier of 238.50 + CGC_PLL_MUL_238_66 = BSP_CLOCKS_PLL_MUL(238U, 66U), ///< PLL multiplier of 238.66 + CGC_PLL_MUL_239_0 = BSP_CLOCKS_PLL_MUL(239U, 0U), ///< PLL multiplier of 239.00 + CGC_PLL_MUL_239_33 = BSP_CLOCKS_PLL_MUL(239U, 33U), ///< PLL multiplier of 239.33 + CGC_PLL_MUL_239_5 = BSP_CLOCKS_PLL_MUL(239U, 50U), ///< PLL multiplier of 239.50 + CGC_PLL_MUL_239_66 = BSP_CLOCKS_PLL_MUL(239U, 66U), ///< PLL multiplier of 239.66 + CGC_PLL_MUL_240_0 = BSP_CLOCKS_PLL_MUL(240U, 0U), ///< PLL multiplier of 240.00 + CGC_PLL_MUL_240_33 = BSP_CLOCKS_PLL_MUL(240U, 33U), ///< PLL multiplier of 240.33 + CGC_PLL_MUL_240_5 = BSP_CLOCKS_PLL_MUL(240U, 50U), ///< PLL multiplier of 240.50 + CGC_PLL_MUL_240_66 = BSP_CLOCKS_PLL_MUL(240U, 66U), ///< PLL multiplier of 240.66 + CGC_PLL_MUL_241_0 = BSP_CLOCKS_PLL_MUL(241U, 0U), ///< PLL multiplier of 241.00 + CGC_PLL_MUL_241_33 = BSP_CLOCKS_PLL_MUL(241U, 33U), ///< PLL multiplier of 241.33 + CGC_PLL_MUL_241_5 = BSP_CLOCKS_PLL_MUL(241U, 50U), ///< PLL multiplier of 241.50 + CGC_PLL_MUL_241_66 = BSP_CLOCKS_PLL_MUL(241U, 66U), ///< PLL multiplier of 241.66 + CGC_PLL_MUL_242_0 = BSP_CLOCKS_PLL_MUL(242U, 0U), ///< PLL multiplier of 242.00 + CGC_PLL_MUL_242_33 = BSP_CLOCKS_PLL_MUL(242U, 33U), ///< PLL multiplier of 242.33 + CGC_PLL_MUL_242_5 = BSP_CLOCKS_PLL_MUL(242U, 50U), ///< PLL multiplier of 242.50 + CGC_PLL_MUL_242_66 = BSP_CLOCKS_PLL_MUL(242U, 66U), ///< PLL multiplier of 242.66 + CGC_PLL_MUL_243_0 = BSP_CLOCKS_PLL_MUL(243U, 0U), ///< PLL multiplier of 243.00 + CGC_PLL_MUL_243_33 = BSP_CLOCKS_PLL_MUL(243U, 33U), ///< PLL multiplier of 243.33 + CGC_PLL_MUL_243_5 = BSP_CLOCKS_PLL_MUL(243U, 50U), ///< PLL multiplier of 243.50 + CGC_PLL_MUL_243_66 = BSP_CLOCKS_PLL_MUL(243U, 66U), ///< PLL multiplier of 243.66 + CGC_PLL_MUL_244_0 = BSP_CLOCKS_PLL_MUL(244U, 0U), ///< PLL multiplier of 244.00 + CGC_PLL_MUL_244_33 = BSP_CLOCKS_PLL_MUL(244U, 33U), ///< PLL multiplier of 244.33 + CGC_PLL_MUL_244_5 = BSP_CLOCKS_PLL_MUL(244U, 50U), ///< PLL multiplier of 244.50 + CGC_PLL_MUL_244_66 = BSP_CLOCKS_PLL_MUL(244U, 66U), ///< PLL multiplier of 244.66 + CGC_PLL_MUL_245_0 = BSP_CLOCKS_PLL_MUL(245U, 0U), ///< PLL multiplier of 245.00 + CGC_PLL_MUL_245_33 = BSP_CLOCKS_PLL_MUL(245U, 33U), ///< PLL multiplier of 245.33 + CGC_PLL_MUL_245_5 = BSP_CLOCKS_PLL_MUL(245U, 50U), ///< PLL multiplier of 245.50 + CGC_PLL_MUL_245_66 = BSP_CLOCKS_PLL_MUL(245U, 66U), ///< PLL multiplier of 245.66 + CGC_PLL_MUL_246_0 = BSP_CLOCKS_PLL_MUL(246U, 0U), ///< PLL multiplier of 246.00 + CGC_PLL_MUL_246_33 = BSP_CLOCKS_PLL_MUL(246U, 33U), ///< PLL multiplier of 246.33 + CGC_PLL_MUL_246_5 = BSP_CLOCKS_PLL_MUL(246U, 50U), ///< PLL multiplier of 246.50 + CGC_PLL_MUL_246_66 = BSP_CLOCKS_PLL_MUL(246U, 66U), ///< PLL multiplier of 246.66 + CGC_PLL_MUL_247_0 = BSP_CLOCKS_PLL_MUL(247U, 0U), ///< PLL multiplier of 247.00 + CGC_PLL_MUL_247_33 = BSP_CLOCKS_PLL_MUL(247U, 33U), ///< PLL multiplier of 247.33 + CGC_PLL_MUL_247_5 = BSP_CLOCKS_PLL_MUL(247U, 50U), ///< PLL multiplier of 247.50 + CGC_PLL_MUL_247_66 = BSP_CLOCKS_PLL_MUL(247U, 66U), ///< PLL multiplier of 247.66 + CGC_PLL_MUL_248_0 = BSP_CLOCKS_PLL_MUL(248U, 0U), ///< PLL multiplier of 248.00 + CGC_PLL_MUL_248_33 = BSP_CLOCKS_PLL_MUL(248U, 33U), ///< PLL multiplier of 248.33 + CGC_PLL_MUL_248_5 = BSP_CLOCKS_PLL_MUL(248U, 50U), ///< PLL multiplier of 248.50 + CGC_PLL_MUL_248_66 = BSP_CLOCKS_PLL_MUL(248U, 66U), ///< PLL multiplier of 248.66 + CGC_PLL_MUL_249_0 = BSP_CLOCKS_PLL_MUL(249U, 0U), ///< PLL multiplier of 249.00 + CGC_PLL_MUL_249_33 = BSP_CLOCKS_PLL_MUL(249U, 33U), ///< PLL multiplier of 249.33 + CGC_PLL_MUL_249_5 = BSP_CLOCKS_PLL_MUL(249U, 50U), ///< PLL multiplier of 249.50 + CGC_PLL_MUL_249_66 = BSP_CLOCKS_PLL_MUL(249U, 66U), ///< PLL multiplier of 249.66 + CGC_PLL_MUL_250_0 = BSP_CLOCKS_PLL_MUL(250U, 0U), ///< PLL multiplier of 250.00 + CGC_PLL_MUL_250_33 = BSP_CLOCKS_PLL_MUL(250U, 33U), ///< PLL multiplier of 250.33 + CGC_PLL_MUL_250_5 = BSP_CLOCKS_PLL_MUL(250U, 50U), ///< PLL multiplier of 250.50 + CGC_PLL_MUL_250_66 = BSP_CLOCKS_PLL_MUL(250U, 66U), ///< PLL multiplier of 250.66 + CGC_PLL_MUL_251_0 = BSP_CLOCKS_PLL_MUL(251U, 0U), ///< PLL multiplier of 251.00 + CGC_PLL_MUL_251_33 = BSP_CLOCKS_PLL_MUL(251U, 33U), ///< PLL multiplier of 251.33 + CGC_PLL_MUL_251_5 = BSP_CLOCKS_PLL_MUL(251U, 50U), ///< PLL multiplier of 251.50 + CGC_PLL_MUL_251_66 = BSP_CLOCKS_PLL_MUL(251U, 66U), ///< PLL multiplier of 251.66 + CGC_PLL_MUL_252_0 = BSP_CLOCKS_PLL_MUL(252U, 0U), ///< PLL multiplier of 252.00 + CGC_PLL_MUL_252_33 = BSP_CLOCKS_PLL_MUL(252U, 33U), ///< PLL multiplier of 252.33 + CGC_PLL_MUL_252_5 = BSP_CLOCKS_PLL_MUL(252U, 50U), ///< PLL multiplier of 252.50 + CGC_PLL_MUL_252_66 = BSP_CLOCKS_PLL_MUL(252U, 66U), ///< PLL multiplier of 252.66 + CGC_PLL_MUL_253_0 = BSP_CLOCKS_PLL_MUL(253U, 0U), ///< PLL multiplier of 253.00 + CGC_PLL_MUL_253_33 = BSP_CLOCKS_PLL_MUL(253U, 33U), ///< PLL multiplier of 253.33 + CGC_PLL_MUL_253_5 = BSP_CLOCKS_PLL_MUL(253U, 50U), ///< PLL multiplier of 253.50 + CGC_PLL_MUL_253_66 = BSP_CLOCKS_PLL_MUL(253U, 66U), ///< PLL multiplier of 253.66 + CGC_PLL_MUL_254_0 = BSP_CLOCKS_PLL_MUL(254U, 0U), ///< PLL multiplier of 254.00 + CGC_PLL_MUL_254_33 = BSP_CLOCKS_PLL_MUL(254U, 33U), ///< PLL multiplier of 254.33 + CGC_PLL_MUL_254_5 = BSP_CLOCKS_PLL_MUL(254U, 50U), ///< PLL multiplier of 254.50 + CGC_PLL_MUL_254_66 = BSP_CLOCKS_PLL_MUL(254U, 66U), ///< PLL multiplier of 254.66 + CGC_PLL_MUL_255_0 = BSP_CLOCKS_PLL_MUL(255U, 0U), ///< PLL multiplier of 255.00 + CGC_PLL_MUL_255_33 = BSP_CLOCKS_PLL_MUL(255U, 33U), ///< PLL multiplier of 255.33 + CGC_PLL_MUL_255_5 = BSP_CLOCKS_PLL_MUL(255U, 50U), ///< PLL multiplier of 255.50 + CGC_PLL_MUL_255_66 = BSP_CLOCKS_PLL_MUL(255U, 66U), ///< PLL multiplier of 255.66 + CGC_PLL_MUL_256_0 = BSP_CLOCKS_PLL_MUL(256U, 0U), ///< PLL multiplier of 256.00 + CGC_PLL_MUL_256_33 = BSP_CLOCKS_PLL_MUL(256U, 33U), ///< PLL multiplier of 256.33 + CGC_PLL_MUL_256_5 = BSP_CLOCKS_PLL_MUL(256U, 50U), ///< PLL multiplier of 256.50 + CGC_PLL_MUL_256_66 = BSP_CLOCKS_PLL_MUL(256U, 66U), ///< PLL multiplier of 256.66 + CGC_PLL_MUL_257_0 = BSP_CLOCKS_PLL_MUL(257U, 0U), ///< PLL multiplier of 257.00 + CGC_PLL_MUL_257_33 = BSP_CLOCKS_PLL_MUL(257U, 33U), ///< PLL multiplier of 257.33 + CGC_PLL_MUL_257_5 = BSP_CLOCKS_PLL_MUL(257U, 50U), ///< PLL multiplier of 257.50 + CGC_PLL_MUL_257_66 = BSP_CLOCKS_PLL_MUL(257U, 66U), ///< PLL multiplier of 257.66 + CGC_PLL_MUL_258_0 = BSP_CLOCKS_PLL_MUL(258U, 0U), ///< PLL multiplier of 258.00 + CGC_PLL_MUL_258_33 = BSP_CLOCKS_PLL_MUL(258U, 33U), ///< PLL multiplier of 258.33 + CGC_PLL_MUL_258_5 = BSP_CLOCKS_PLL_MUL(258U, 50U), ///< PLL multiplier of 258.50 + CGC_PLL_MUL_258_66 = BSP_CLOCKS_PLL_MUL(258U, 66U), ///< PLL multiplier of 258.66 + CGC_PLL_MUL_259_0 = BSP_CLOCKS_PLL_MUL(259U, 0U), ///< PLL multiplier of 259.00 + CGC_PLL_MUL_259_33 = BSP_CLOCKS_PLL_MUL(259U, 33U), ///< PLL multiplier of 259.33 + CGC_PLL_MUL_259_5 = BSP_CLOCKS_PLL_MUL(259U, 50U), ///< PLL multiplier of 259.50 + CGC_PLL_MUL_259_66 = BSP_CLOCKS_PLL_MUL(259U, 66U), ///< PLL multiplier of 259.66 + CGC_PLL_MUL_260_0 = BSP_CLOCKS_PLL_MUL(260U, 0U), ///< PLL multiplier of 260.00 + CGC_PLL_MUL_260_33 = BSP_CLOCKS_PLL_MUL(260U, 33U), ///< PLL multiplier of 260.33 + CGC_PLL_MUL_260_5 = BSP_CLOCKS_PLL_MUL(260U, 50U), ///< PLL multiplier of 260.50 + CGC_PLL_MUL_260_66 = BSP_CLOCKS_PLL_MUL(260U, 66U), ///< PLL multiplier of 260.66 + CGC_PLL_MUL_261_0 = BSP_CLOCKS_PLL_MUL(261U, 0U), ///< PLL multiplier of 261.00 + CGC_PLL_MUL_261_33 = BSP_CLOCKS_PLL_MUL(261U, 33U), ///< PLL multiplier of 261.33 + CGC_PLL_MUL_261_5 = BSP_CLOCKS_PLL_MUL(261U, 50U), ///< PLL multiplier of 261.50 + CGC_PLL_MUL_261_66 = BSP_CLOCKS_PLL_MUL(261U, 66U), ///< PLL multiplier of 261.66 + CGC_PLL_MUL_262_0 = BSP_CLOCKS_PLL_MUL(262U, 0U), ///< PLL multiplier of 262.00 + CGC_PLL_MUL_262_33 = BSP_CLOCKS_PLL_MUL(262U, 33U), ///< PLL multiplier of 262.33 + CGC_PLL_MUL_262_5 = BSP_CLOCKS_PLL_MUL(262U, 50U), ///< PLL multiplier of 262.50 + CGC_PLL_MUL_262_66 = BSP_CLOCKS_PLL_MUL(262U, 66U), ///< PLL multiplier of 262.66 + CGC_PLL_MUL_263_0 = BSP_CLOCKS_PLL_MUL(263U, 0U), ///< PLL multiplier of 263.00 + CGC_PLL_MUL_263_33 = BSP_CLOCKS_PLL_MUL(263U, 33U), ///< PLL multiplier of 263.33 + CGC_PLL_MUL_263_5 = BSP_CLOCKS_PLL_MUL(263U, 50U), ///< PLL multiplier of 263.50 + CGC_PLL_MUL_263_66 = BSP_CLOCKS_PLL_MUL(263U, 66U), ///< PLL multiplier of 263.66 + CGC_PLL_MUL_264_0 = BSP_CLOCKS_PLL_MUL(264U, 0U), ///< PLL multiplier of 264.00 + CGC_PLL_MUL_264_33 = BSP_CLOCKS_PLL_MUL(264U, 33U), ///< PLL multiplier of 264.33 + CGC_PLL_MUL_264_5 = BSP_CLOCKS_PLL_MUL(264U, 50U), ///< PLL multiplier of 264.50 + CGC_PLL_MUL_264_66 = BSP_CLOCKS_PLL_MUL(264U, 66U), ///< PLL multiplier of 264.66 + CGC_PLL_MUL_265_0 = BSP_CLOCKS_PLL_MUL(265U, 0U), ///< PLL multiplier of 265.00 + CGC_PLL_MUL_265_33 = BSP_CLOCKS_PLL_MUL(265U, 33U), ///< PLL multiplier of 265.33 + CGC_PLL_MUL_265_5 = BSP_CLOCKS_PLL_MUL(265U, 50U), ///< PLL multiplier of 265.50 + CGC_PLL_MUL_265_66 = BSP_CLOCKS_PLL_MUL(265U, 66U), ///< PLL multiplier of 265.66 + CGC_PLL_MUL_266_0 = BSP_CLOCKS_PLL_MUL(266U, 0U), ///< PLL multiplier of 266.00 + CGC_PLL_MUL_266_33 = BSP_CLOCKS_PLL_MUL(266U, 33U), ///< PLL multiplier of 266.33 + CGC_PLL_MUL_266_5 = BSP_CLOCKS_PLL_MUL(266U, 50U), ///< PLL multiplier of 266.50 + CGC_PLL_MUL_266_66 = BSP_CLOCKS_PLL_MUL(266U, 66U), ///< PLL multiplier of 266.66 + CGC_PLL_MUL_267_0 = BSP_CLOCKS_PLL_MUL(267U, 0U), ///< PLL multiplier of 267.00 + CGC_PLL_MUL_267_33 = BSP_CLOCKS_PLL_MUL(267U, 33U), ///< PLL multiplier of 267.33 + CGC_PLL_MUL_267_5 = BSP_CLOCKS_PLL_MUL(267U, 50U), ///< PLL multiplier of 267.50 + CGC_PLL_MUL_267_66 = BSP_CLOCKS_PLL_MUL(267U, 66U), ///< PLL multiplier of 267.66 + CGC_PLL_MUL_268_0 = BSP_CLOCKS_PLL_MUL(268U, 0U), ///< PLL multiplier of 268.00 + CGC_PLL_MUL_268_33 = BSP_CLOCKS_PLL_MUL(268U, 33U), ///< PLL multiplier of 268.33 + CGC_PLL_MUL_268_5 = BSP_CLOCKS_PLL_MUL(268U, 50U), ///< PLL multiplier of 268.50 + CGC_PLL_MUL_268_66 = BSP_CLOCKS_PLL_MUL(268U, 66U), ///< PLL multiplier of 268.66 + CGC_PLL_MUL_269_0 = BSP_CLOCKS_PLL_MUL(269U, 0U), ///< PLL multiplier of 269.00 + CGC_PLL_MUL_269_33 = BSP_CLOCKS_PLL_MUL(269U, 33U), ///< PLL multiplier of 269.33 + CGC_PLL_MUL_269_5 = BSP_CLOCKS_PLL_MUL(269U, 50U), ///< PLL multiplier of 269.50 + CGC_PLL_MUL_269_66 = BSP_CLOCKS_PLL_MUL(269U, 66U), ///< PLL multiplier of 269.66 + CGC_PLL_MUL_270_0 = BSP_CLOCKS_PLL_MUL(270U, 0U), ///< PLL multiplier of 270.00 + CGC_PLL_MUL_270_33 = BSP_CLOCKS_PLL_MUL(270U, 33U), ///< PLL multiplier of 270.33 + CGC_PLL_MUL_270_5 = BSP_CLOCKS_PLL_MUL(270U, 50U), ///< PLL multiplier of 270.50 + CGC_PLL_MUL_270_66 = BSP_CLOCKS_PLL_MUL(270U, 66U), ///< PLL multiplier of 270.66 + CGC_PLL_MUL_271_0 = BSP_CLOCKS_PLL_MUL(271U, 0U), ///< PLL multiplier of 271.00 + CGC_PLL_MUL_271_33 = BSP_CLOCKS_PLL_MUL(271U, 33U), ///< PLL multiplier of 271.33 + CGC_PLL_MUL_271_5 = BSP_CLOCKS_PLL_MUL(271U, 50U), ///< PLL multiplier of 271.50 + CGC_PLL_MUL_271_66 = BSP_CLOCKS_PLL_MUL(271U, 66U), ///< PLL multiplier of 271.66 + CGC_PLL_MUL_272_0 = BSP_CLOCKS_PLL_MUL(272U, 0U), ///< PLL multiplier of 272.00 + CGC_PLL_MUL_272_33 = BSP_CLOCKS_PLL_MUL(272U, 33U), ///< PLL multiplier of 272.33 + CGC_PLL_MUL_272_5 = BSP_CLOCKS_PLL_MUL(272U, 50U), ///< PLL multiplier of 272.50 + CGC_PLL_MUL_272_66 = BSP_CLOCKS_PLL_MUL(272U, 66U), ///< PLL multiplier of 272.66 + CGC_PLL_MUL_273_0 = BSP_CLOCKS_PLL_MUL(273U, 0U), ///< PLL multiplier of 273.00 + CGC_PLL_MUL_273_33 = BSP_CLOCKS_PLL_MUL(273U, 33U), ///< PLL multiplier of 273.33 + CGC_PLL_MUL_273_5 = BSP_CLOCKS_PLL_MUL(273U, 50U), ///< PLL multiplier of 273.50 + CGC_PLL_MUL_273_66 = BSP_CLOCKS_PLL_MUL(273U, 66U), ///< PLL multiplier of 273.66 + CGC_PLL_MUL_274_0 = BSP_CLOCKS_PLL_MUL(274U, 0U), ///< PLL multiplier of 274.00 + CGC_PLL_MUL_274_33 = BSP_CLOCKS_PLL_MUL(274U, 33U), ///< PLL multiplier of 274.33 + CGC_PLL_MUL_274_5 = BSP_CLOCKS_PLL_MUL(274U, 50U), ///< PLL multiplier of 274.50 + CGC_PLL_MUL_274_66 = BSP_CLOCKS_PLL_MUL(274U, 66U), ///< PLL multiplier of 274.66 + CGC_PLL_MUL_275_0 = BSP_CLOCKS_PLL_MUL(275U, 0U), ///< PLL multiplier of 275.00 + CGC_PLL_MUL_275_33 = BSP_CLOCKS_PLL_MUL(275U, 33U), ///< PLL multiplier of 275.33 + CGC_PLL_MUL_275_5 = BSP_CLOCKS_PLL_MUL(275U, 50U), ///< PLL multiplier of 275.50 + CGC_PLL_MUL_275_66 = BSP_CLOCKS_PLL_MUL(275U, 66U), ///< PLL multiplier of 275.66 + CGC_PLL_MUL_276_0 = BSP_CLOCKS_PLL_MUL(276U, 0U), ///< PLL multiplier of 276.00 + CGC_PLL_MUL_276_33 = BSP_CLOCKS_PLL_MUL(276U, 33U), ///< PLL multiplier of 276.33 + CGC_PLL_MUL_276_5 = BSP_CLOCKS_PLL_MUL(276U, 50U), ///< PLL multiplier of 276.50 + CGC_PLL_MUL_276_66 = BSP_CLOCKS_PLL_MUL(276U, 66U), ///< PLL multiplier of 276.66 + CGC_PLL_MUL_277_0 = BSP_CLOCKS_PLL_MUL(277U, 0U), ///< PLL multiplier of 277.00 + CGC_PLL_MUL_277_33 = BSP_CLOCKS_PLL_MUL(277U, 33U), ///< PLL multiplier of 277.33 + CGC_PLL_MUL_277_5 = BSP_CLOCKS_PLL_MUL(277U, 50U), ///< PLL multiplier of 277.50 + CGC_PLL_MUL_277_66 = BSP_CLOCKS_PLL_MUL(277U, 66U), ///< PLL multiplier of 277.66 + CGC_PLL_MUL_278_0 = BSP_CLOCKS_PLL_MUL(278U, 0U), ///< PLL multiplier of 278.00 + CGC_PLL_MUL_278_33 = BSP_CLOCKS_PLL_MUL(278U, 33U), ///< PLL multiplier of 278.33 + CGC_PLL_MUL_278_5 = BSP_CLOCKS_PLL_MUL(278U, 50U), ///< PLL multiplier of 278.50 + CGC_PLL_MUL_278_66 = BSP_CLOCKS_PLL_MUL(278U, 66U), ///< PLL multiplier of 278.66 + CGC_PLL_MUL_279_0 = BSP_CLOCKS_PLL_MUL(279U, 0U), ///< PLL multiplier of 279.00 + CGC_PLL_MUL_279_33 = BSP_CLOCKS_PLL_MUL(279U, 33U), ///< PLL multiplier of 279.33 + CGC_PLL_MUL_279_5 = BSP_CLOCKS_PLL_MUL(279U, 50U), ///< PLL multiplier of 279.50 + CGC_PLL_MUL_279_66 = BSP_CLOCKS_PLL_MUL(279U, 66U), ///< PLL multiplier of 279.66 + CGC_PLL_MUL_280_0 = BSP_CLOCKS_PLL_MUL(280U, 0U), ///< PLL multiplier of 280.00 + CGC_PLL_MUL_280_33 = BSP_CLOCKS_PLL_MUL(280U, 33U), ///< PLL multiplier of 280.33 + CGC_PLL_MUL_280_5 = BSP_CLOCKS_PLL_MUL(280U, 50U), ///< PLL multiplier of 280.50 + CGC_PLL_MUL_280_66 = BSP_CLOCKS_PLL_MUL(280U, 66U), ///< PLL multiplier of 280.66 + CGC_PLL_MUL_281_0 = BSP_CLOCKS_PLL_MUL(281U, 0U), ///< PLL multiplier of 281.00 + CGC_PLL_MUL_281_33 = BSP_CLOCKS_PLL_MUL(281U, 33U), ///< PLL multiplier of 281.33 + CGC_PLL_MUL_281_5 = BSP_CLOCKS_PLL_MUL(281U, 50U), ///< PLL multiplier of 281.50 + CGC_PLL_MUL_281_66 = BSP_CLOCKS_PLL_MUL(281U, 66U), ///< PLL multiplier of 281.66 + CGC_PLL_MUL_282_0 = BSP_CLOCKS_PLL_MUL(282U, 0U), ///< PLL multiplier of 282.00 + CGC_PLL_MUL_282_33 = BSP_CLOCKS_PLL_MUL(282U, 33U), ///< PLL multiplier of 282.33 + CGC_PLL_MUL_282_5 = BSP_CLOCKS_PLL_MUL(282U, 50U), ///< PLL multiplier of 282.50 + CGC_PLL_MUL_282_66 = BSP_CLOCKS_PLL_MUL(282U, 66U), ///< PLL multiplier of 282.66 + CGC_PLL_MUL_283_0 = BSP_CLOCKS_PLL_MUL(283U, 0U), ///< PLL multiplier of 283.00 + CGC_PLL_MUL_283_33 = BSP_CLOCKS_PLL_MUL(283U, 33U), ///< PLL multiplier of 283.33 + CGC_PLL_MUL_283_5 = BSP_CLOCKS_PLL_MUL(283U, 50U), ///< PLL multiplier of 283.50 + CGC_PLL_MUL_283_66 = BSP_CLOCKS_PLL_MUL(283U, 66U), ///< PLL multiplier of 283.66 + CGC_PLL_MUL_284_0 = BSP_CLOCKS_PLL_MUL(284U, 0U), ///< PLL multiplier of 284.00 + CGC_PLL_MUL_284_33 = BSP_CLOCKS_PLL_MUL(284U, 33U), ///< PLL multiplier of 284.33 + CGC_PLL_MUL_284_5 = BSP_CLOCKS_PLL_MUL(284U, 50U), ///< PLL multiplier of 284.50 + CGC_PLL_MUL_284_66 = BSP_CLOCKS_PLL_MUL(284U, 66U), ///< PLL multiplier of 284.66 + CGC_PLL_MUL_285_0 = BSP_CLOCKS_PLL_MUL(285U, 0U), ///< PLL multiplier of 285.00 + CGC_PLL_MUL_285_33 = BSP_CLOCKS_PLL_MUL(285U, 33U), ///< PLL multiplier of 285.33 + CGC_PLL_MUL_285_5 = BSP_CLOCKS_PLL_MUL(285U, 50U), ///< PLL multiplier of 285.50 + CGC_PLL_MUL_285_66 = BSP_CLOCKS_PLL_MUL(285U, 66U), ///< PLL multiplier of 285.66 + CGC_PLL_MUL_286_0 = BSP_CLOCKS_PLL_MUL(286U, 0U), ///< PLL multiplier of 286.00 + CGC_PLL_MUL_286_33 = BSP_CLOCKS_PLL_MUL(286U, 33U), ///< PLL multiplier of 286.33 + CGC_PLL_MUL_286_5 = BSP_CLOCKS_PLL_MUL(286U, 50U), ///< PLL multiplier of 286.50 + CGC_PLL_MUL_286_66 = BSP_CLOCKS_PLL_MUL(286U, 66U), ///< PLL multiplier of 286.66 + CGC_PLL_MUL_287_0 = BSP_CLOCKS_PLL_MUL(287U, 0U), ///< PLL multiplier of 287.00 + CGC_PLL_MUL_287_33 = BSP_CLOCKS_PLL_MUL(287U, 33U), ///< PLL multiplier of 287.33 + CGC_PLL_MUL_287_5 = BSP_CLOCKS_PLL_MUL(287U, 50U), ///< PLL multiplier of 287.50 + CGC_PLL_MUL_287_66 = BSP_CLOCKS_PLL_MUL(287U, 66U), ///< PLL multiplier of 287.66 + CGC_PLL_MUL_288_0 = BSP_CLOCKS_PLL_MUL(288U, 0U), ///< PLL multiplier of 288.00 + CGC_PLL_MUL_288_33 = BSP_CLOCKS_PLL_MUL(288U, 33U), ///< PLL multiplier of 288.33 + CGC_PLL_MUL_288_5 = BSP_CLOCKS_PLL_MUL(288U, 50U), ///< PLL multiplier of 288.50 + CGC_PLL_MUL_288_66 = BSP_CLOCKS_PLL_MUL(288U, 66U), ///< PLL multiplier of 288.66 + CGC_PLL_MUL_289_0 = BSP_CLOCKS_PLL_MUL(289U, 0U), ///< PLL multiplier of 289.00 + CGC_PLL_MUL_289_33 = BSP_CLOCKS_PLL_MUL(289U, 33U), ///< PLL multiplier of 289.33 + CGC_PLL_MUL_289_5 = BSP_CLOCKS_PLL_MUL(289U, 50U), ///< PLL multiplier of 289.50 + CGC_PLL_MUL_289_66 = BSP_CLOCKS_PLL_MUL(289U, 66U), ///< PLL multiplier of 289.66 + CGC_PLL_MUL_290_0 = BSP_CLOCKS_PLL_MUL(290U, 0U), ///< PLL multiplier of 290.00 + CGC_PLL_MUL_290_33 = BSP_CLOCKS_PLL_MUL(290U, 33U), ///< PLL multiplier of 290.33 + CGC_PLL_MUL_290_5 = BSP_CLOCKS_PLL_MUL(290U, 50U), ///< PLL multiplier of 290.50 + CGC_PLL_MUL_290_66 = BSP_CLOCKS_PLL_MUL(290U, 66U), ///< PLL multiplier of 290.66 + CGC_PLL_MUL_291_0 = BSP_CLOCKS_PLL_MUL(291U, 0U), ///< PLL multiplier of 291.00 + CGC_PLL_MUL_291_33 = BSP_CLOCKS_PLL_MUL(291U, 33U), ///< PLL multiplier of 291.33 + CGC_PLL_MUL_291_5 = BSP_CLOCKS_PLL_MUL(291U, 50U), ///< PLL multiplier of 291.50 + CGC_PLL_MUL_291_66 = BSP_CLOCKS_PLL_MUL(291U, 66U), ///< PLL multiplier of 291.66 + CGC_PLL_MUL_292_0 = BSP_CLOCKS_PLL_MUL(292U, 0U), ///< PLL multiplier of 292.00 + CGC_PLL_MUL_292_33 = BSP_CLOCKS_PLL_MUL(292U, 33U), ///< PLL multiplier of 292.33 + CGC_PLL_MUL_292_5 = BSP_CLOCKS_PLL_MUL(292U, 50U), ///< PLL multiplier of 292.50 + CGC_PLL_MUL_292_66 = BSP_CLOCKS_PLL_MUL(292U, 66U), ///< PLL multiplier of 292.66 + CGC_PLL_MUL_293_0 = BSP_CLOCKS_PLL_MUL(293U, 0U), ///< PLL multiplier of 293.00 + CGC_PLL_MUL_293_33 = BSP_CLOCKS_PLL_MUL(293U, 33U), ///< PLL multiplier of 293.33 + CGC_PLL_MUL_293_5 = BSP_CLOCKS_PLL_MUL(293U, 50U), ///< PLL multiplier of 293.50 + CGC_PLL_MUL_293_66 = BSP_CLOCKS_PLL_MUL(293U, 66U), ///< PLL multiplier of 293.66 + CGC_PLL_MUL_294_0 = BSP_CLOCKS_PLL_MUL(294U, 0U), ///< PLL multiplier of 294.00 + CGC_PLL_MUL_294_33 = BSP_CLOCKS_PLL_MUL(294U, 33U), ///< PLL multiplier of 294.33 + CGC_PLL_MUL_294_5 = BSP_CLOCKS_PLL_MUL(294U, 50U), ///< PLL multiplier of 294.50 + CGC_PLL_MUL_294_66 = BSP_CLOCKS_PLL_MUL(294U, 66U), ///< PLL multiplier of 294.66 + CGC_PLL_MUL_295_0 = BSP_CLOCKS_PLL_MUL(295U, 0U), ///< PLL multiplier of 295.00 + CGC_PLL_MUL_295_33 = BSP_CLOCKS_PLL_MUL(295U, 33U), ///< PLL multiplier of 295.33 + CGC_PLL_MUL_295_5 = BSP_CLOCKS_PLL_MUL(295U, 50U), ///< PLL multiplier of 295.50 + CGC_PLL_MUL_295_66 = BSP_CLOCKS_PLL_MUL(295U, 66U), ///< PLL multiplier of 295.66 + CGC_PLL_MUL_296_0 = BSP_CLOCKS_PLL_MUL(296U, 0U), ///< PLL multiplier of 296.00 + CGC_PLL_MUL_296_33 = BSP_CLOCKS_PLL_MUL(296U, 33U), ///< PLL multiplier of 296.33 + CGC_PLL_MUL_296_5 = BSP_CLOCKS_PLL_MUL(296U, 50U), ///< PLL multiplier of 296.50 + CGC_PLL_MUL_296_66 = BSP_CLOCKS_PLL_MUL(296U, 66U), ///< PLL multiplier of 296.66 + CGC_PLL_MUL_297_0 = BSP_CLOCKS_PLL_MUL(297U, 0U), ///< PLL multiplier of 297.00 + CGC_PLL_MUL_297_33 = BSP_CLOCKS_PLL_MUL(297U, 33U), ///< PLL multiplier of 297.33 + CGC_PLL_MUL_297_5 = BSP_CLOCKS_PLL_MUL(297U, 50U), ///< PLL multiplier of 297.50 + CGC_PLL_MUL_297_66 = BSP_CLOCKS_PLL_MUL(297U, 66U), ///< PLL multiplier of 297.66 + CGC_PLL_MUL_298_0 = BSP_CLOCKS_PLL_MUL(298U, 0U), ///< PLL multiplier of 298.00 + CGC_PLL_MUL_298_33 = BSP_CLOCKS_PLL_MUL(298U, 33U), ///< PLL multiplier of 298.33 + CGC_PLL_MUL_298_5 = BSP_CLOCKS_PLL_MUL(298U, 50U), ///< PLL multiplier of 298.50 + CGC_PLL_MUL_298_66 = BSP_CLOCKS_PLL_MUL(298U, 66U), ///< PLL multiplier of 298.66 + CGC_PLL_MUL_299_0 = BSP_CLOCKS_PLL_MUL(299U, 0U), ///< PLL multiplier of 299.00 + CGC_PLL_MUL_299_33 = BSP_CLOCKS_PLL_MUL(299U, 33U), ///< PLL multiplier of 299.33 + CGC_PLL_MUL_299_5 = BSP_CLOCKS_PLL_MUL(299U, 50U), ///< PLL multiplier of 299.50 + CGC_PLL_MUL_299_66 = BSP_CLOCKS_PLL_MUL(299U, 66U), ///< PLL multiplier of 299.66 + CGC_PLL_MUL_300_0 = BSP_CLOCKS_PLL_MUL(300U, 0U), ///< PLL multiplier of 300.00 + CGC_PLL_MUL_300_33 = BSP_CLOCKS_PLL_MUL(300U, 33U), ///< PLL multiplier of 300.33 + CGC_PLL_MUL_300_5 = BSP_CLOCKS_PLL_MUL(300U, 50U), ///< PLL multiplier of 300.50 + CGC_PLL_MUL_300_66 = BSP_CLOCKS_PLL_MUL(300U, 66U), ///< PLL multiplier of 300.66 + CGC_PLL_MUL_732_0 = BSP_CLOCKS_PLL_MUL(732U, 0U), ///< PLL multiplier of 732.00 + CGC_PLL_MUL_781_0 = BSP_CLOCKS_PLL_MUL(781U, 0U), ///< PLL multiplier of 781.00 +} cgc_pll_mul_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/* Public functions defined in bsp.h */ +void bsp_clock_init(void); // Used internally by BSP + +#if BSP_TZ_NONSECURE_BUILD || BSP_SECONDARY_CORE_BUILD +void bsp_clock_freq_var_init(void); // Used internally by BSP + +#endif + +#if BSP_TZ_SECURE_BUILD +void r_bsp_clock_update_callback_set(bsp_clock_update_callback_t p_callback, + bsp_clock_update_callback_args_t * p_callback_memory); + +#endif + +/* Used internally by CGC */ + +#if !BSP_CFG_USE_LOW_VOLTAGE_MODE +void bsp_prv_operating_mode_set(uint8_t operating_mode); + +#endif + +#if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED +uint32_t bsp_prv_power_change_mstp_set(void); +void bsp_prv_power_change_mstp_clear(uint32_t mstp_clear_bitmask); + +#endif + +void bsp_prv_prepare_pll(uint32_t clock, uint32_t const * const p_pll_hz); + +#if !BSP_FEATURE_CGC_REGISTER_SET_B +void bsp_prv_clock_set(uint32_t clock, uint32_t sckdivcr, uint16_t sckdivcr2); + +#else +void bsp_prv_clock_set(uint32_t clock, uint8_t hocodiv, uint8_t mocodiv, uint8_t moscdiv); +uint32_t bsp_prv_clock_source_get(void); + +#endif + +/* RTC Initialization */ +#if BSP_FEATURE_RTC_IS_AVAILABLE || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_RTC_HAS_VBTICTLR +void R_BSP_Init_RTC(void); + +#endif + +#if BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE +bool bsp_prv_rtc_register_clock_set(bool enable); + +#endif + +#if BSP_CFG_SLEEP_MODE_DELAY_ENABLE || BSP_CFG_RTOS_SLEEP_MODE_DELAY_ENABLE +bool bsp_prv_clock_prepare_pre_sleep(void); +void bsp_prv_clock_prepare_post_sleep(bool cpuclk_slowed); + +#endif + +/* The public function is used to get state or initialize the sub-clock. */ +#if BSP_FEATURE_RTC_IS_IRTC +fsp_err_t R_BSP_SubclockStatusGet(); +fsp_err_t R_BSP_SubclockInitialize(); + +#endif + +#if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS +void bsp_prv_clear_pfb(void); +void bsp_prv_set_pfb(void); + +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_common.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_common.c new file mode 100644 index 00000000000..4368950994b --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_common.c @@ -0,0 +1,311 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#if defined(__ICCARM__) + #define WEAK_ERROR_ATTRIBUTE + #define WEAK_INIT_ATTRIBUTE + #pragma weak fsp_error_log = fsp_error_log_internal + #pragma weak bsp_init = bsp_init_internal +#elif defined(__GNUC__) + + #define WEAK_ERROR_ATTRIBUTE __attribute__((weak, alias("fsp_error_log_internal"))) + + #define WEAK_INIT_ATTRIBUTE __attribute__((weak, alias("bsp_init_internal"))) +#endif + +#define FSP_SECTION_VERSION ".version" + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/** Prototype of initialization function called before main. This prototype sets the weak association of this + * function to an internal example implementation. If this function is defined in the application code, the + * application code version is used. */ + +void bsp_init(void * p_args) WEAK_INIT_ATTRIBUTE; + +void bsp_init_internal(void * p_args); /// Default initialization function + +#if (1 == BSP_CFG_ASSERT) + +/** Prototype of function called before errors are returned in FSP code if BSP_CFG_ASSERT is set to 1. This + * prototype sets the weak association of this function to an internal example implementation. */ + +void fsp_error_log(fsp_err_t err, const char * file, int32_t line) WEAK_ERROR_ATTRIBUTE; + +void fsp_error_log_internal(fsp_err_t err, const char * file, int32_t line); /// Default error logger function + +#endif +#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_SECURE_BUILD == 1 +static bool bsp_valid_register_check(uint32_t register_address, + uint32_t const * const p_register_table, + uint32_t register_table_length); + +#endif + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/* FSP pack version structure. */ +static BSP_DONT_REMOVE const fsp_pack_version_t g_fsp_version BSP_PLACE_IN_SECTION (FSP_SECTION_VERSION) = +{ + .version_id_b = + { + .minor = FSP_VERSION_MINOR, + .major = FSP_VERSION_MAJOR, + .build = FSP_VERSION_BUILD, + .patch = FSP_VERSION_PATCH + } +}; + +/* Public FSP version name. */ +static BSP_DONT_REMOVE const uint8_t g_fsp_version_string[] BSP_PLACE_IN_SECTION(FSP_SECTION_VERSION) = + FSP_VERSION_STRING; + +/* Unique FSP version ID. */ +static BSP_DONT_REMOVE const uint8_t g_fsp_version_build_string[] BSP_PLACE_IN_SECTION(FSP_SECTION_VERSION) = + FSP_VERSION_BUILD_STRING; + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Get the FSP version based on compile time macros. + * + * @param[out] p_version Memory address to return version information to. + * + * @retval FSP_SUCCESS Version information stored. + * @retval FSP_ERR_ASSERTION The parameter p_version is NULL. + **********************************************************************************************************************/ +fsp_err_t R_FSP_VersionGet (fsp_pack_version_t * const p_version) +{ +#if BSP_CFG_PARAM_CHECKING_ENABLE + + /** Verify parameters are valid */ + FSP_ASSERT(NULL != p_version); +#endif + + *p_version = g_fsp_version; + + return FSP_SUCCESS; +} + +#if (1 == BSP_CFG_ASSERT) + +/*******************************************************************************************************************//** + * Default error logger function, used only if fsp_error_log is not defined in the user application. + * + * @param[in] err The error code encountered. + * @param[in] file The file name in which the error code was encountered. + * @param[in] line The line number at which the error code was encountered. + **********************************************************************************************************************/ +void fsp_error_log_internal (fsp_err_t err, const char * file, int32_t line) +{ + /** Do nothing. Do not generate any 'unused' warnings. */ + FSP_PARAMETER_NOT_USED(err); + FSP_PARAMETER_NOT_USED(file); + FSP_PARAMETER_NOT_USED(line); +} + +#endif + +#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_SECURE_BUILD == 1 + +/*******************************************************************************************************************//** + * Read a secure 8-bit STYPE3 register in the non-secure state. + * + * @param[in] p_reg The address of the secure register. + * + * @return Value read from the register. + **********************************************************************************************************************/ +BSP_CMSE_NONSECURE_ENTRY uint8_t R_BSP_NSC_STYPE3_RegU8Read (uint8_t volatile const * p_reg) +{ + uint8_t volatile * p_reg_s = (uint8_t volatile *) ((uint32_t) p_reg & ~BSP_FEATURE_TZ_NS_OFFSET); + + /* Table of secure registers that may be read from the non-secure application. */ + static const uint32_t valid_addresses[] = + { + (uint32_t) &R_SYSTEM->SCKDIVCR2, + (uint32_t) &R_SYSTEM->SCKSCR, + (uint32_t) &R_SYSTEM->SPICKDIVCR, + (uint32_t) &R_SYSTEM->SPICKCR, + (uint32_t) &R_SYSTEM->SCICKDIVCR, + (uint32_t) &R_SYSTEM->SCICKCR, + (uint32_t) &R_SYSTEM->CANFDCKCR, + (uint32_t) &R_SYSTEM->PLLCR, + (uint32_t) &R_SYSTEM->PLL2CR, + (uint32_t) &R_SYSTEM->MOCOCR, + (uint32_t) &R_SYSTEM->OPCCR, + }; + + if (bsp_valid_register_check((uint32_t) p_reg_s, valid_addresses, + sizeof(valid_addresses) / sizeof(valid_addresses[0]))) + { + return *p_reg_s; + } + + /* Generate a trustzone access violation by accessing the non-secure aliased address. */ + return *((uint8_t volatile *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET)); +} + +/*******************************************************************************************************************//** + * Read a secure 16-bit STYPE3 register in the non-secure state. + * + * @param[in] p_reg The address of the secure register. + * + * @return Value read from the register. + **********************************************************************************************************************/ +BSP_CMSE_NONSECURE_ENTRY uint16_t R_BSP_NSC_STYPE3_RegU16Read (uint16_t volatile const * p_reg) +{ + uint16_t volatile * p_reg_s = (uint16_t volatile *) ((uint32_t) p_reg & ~BSP_FEATURE_TZ_NS_OFFSET); + + /* Table of secure registers that may be read from the non-secure application. */ + static const uint32_t valid_addresses[] = + { + (uint32_t) &R_DTC->DTCSTS, + }; + + if (bsp_valid_register_check((uint32_t) p_reg_s, valid_addresses, + sizeof(valid_addresses) / sizeof(valid_addresses[0]))) + { + return *p_reg_s; + } + + /* Generate a trustzone access violation by accessing the non-secure aliased address. */ + return *((uint16_t volatile *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET)); +} + +/*******************************************************************************************************************//** + * Read a secure 32-bit STYPE3 register in the non-secure state. + * + * @param[in] p_reg The address of the secure register. + * + * @return Value read from the register. + **********************************************************************************************************************/ +BSP_CMSE_NONSECURE_ENTRY uint32_t R_BSP_NSC_STYPE3_RegU32Read (uint32_t volatile const * p_reg) +{ + uint32_t volatile * p_reg_s = (uint32_t volatile *) ((uint32_t) p_reg & ~BSP_FEATURE_TZ_NS_OFFSET); + + /* Table of secure registers that may be read from the non-secure application. */ + static const uint32_t valid_addresses[] = + { + (uint32_t) &R_SYSTEM->SCKDIVCR, + }; + + if (bsp_valid_register_check((uint32_t) p_reg_s, valid_addresses, + sizeof(valid_addresses) / sizeof(valid_addresses[0]))) + { + return *p_reg_s; + } + + /* Generate a trustzone access violation by accessing the non-secure aliased address. */ + return *((uint32_t volatile *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET)); +} + +#endif + +/** @} (end addtogroup BSP_MCU) */ + +/*******************************************************************************************************************//** + * Default initialization function, used only if bsp_init is not defined in the user application. + **********************************************************************************************************************/ +void bsp_init_internal (void * p_args) +{ + /* Do nothing. */ + FSP_PARAMETER_NOT_USED(p_args); +} + +#if defined(__ARMCC_VERSION) + +/*******************************************************************************************************************//** + * Default implementation of assert for AC6. + **********************************************************************************************************************/ +__attribute__((weak, noreturn)) +void __aeabi_assert (const char * expr, const char * file, int line) +{ + FSP_PARAMETER_NOT_USED(expr); + FSP_PARAMETER_NOT_USED(file); + FSP_PARAMETER_NOT_USED(line); + __BKPT(0); + while (1) + { + /* Do nothing. */ + } +} + +#elif defined(__GNUC__) + +/* The default assert implementation for GCC brings in printing/formatting code. FSP overrides the default assert + * behavior to reduce code size. */ + + #if !BSP_CFG_USE_STANDARD_ASSERT + +/*******************************************************************************************************************//** + * Default implementation of assert for GCC. + **********************************************************************************************************************/ +BSP_WEAK_REFERENCE void __assert_func (const char * file, int line, const char * func, const char * expr) +{ + FSP_PARAMETER_NOT_USED(file); + FSP_PARAMETER_NOT_USED(line); + FSP_PARAMETER_NOT_USED(func); + FSP_PARAMETER_NOT_USED(expr); + __BKPT(0); + while (1) + { + /* Do nothing. */ + } +} + + #endif + +#endif + +#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_SECURE_BUILD == 1 + +/*******************************************************************************************************************//** + * Check if a register address should be accessible by the non-secure application. + **********************************************************************************************************************/ +static bool bsp_valid_register_check (uint32_t register_address, + uint32_t const * const p_register_table, + uint32_t register_table_length) +{ + bool valid = false; + + /* Check if the given address is valid. */ + for (uint32_t i = 0; i < register_table_length; i++) + { + if (p_register_table[i] == register_address) + { + valid = true; + break; + } + } + + return valid; +} + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_common.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_common.h new file mode 100644 index 00000000000..e92fe1470e8 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_common.h @@ -0,0 +1,767 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_COMMON_H +#define BSP_COMMON_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* C99 includes. */ +#include +#include +#include +#include +#include + +/* Different compiler support. */ +#include "../../inc/api/fsp_common_api.h" +#include "bsp_compiler_support.h" + +/* BSP module includes */ +#include "../../src/bsp/mcu/all/bsp_tfu.h" +#include "../../src/bsp/mcu/all/bsp_sdram.h" +#include "../../src/bsp/mcu/all/bsp_mmf.h" +#include "../../src/bsp/mcu/all/bsp_ipc.h" +#include "../../src/bsp/mcu/all/bsp_ospi_b.h" + +#include "bsp_linker_info.h" + +#include "bsp_cfg.h" + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** Used to signify that an ELC event is not able to be used as an interrupt. */ +#define BSP_IRQ_DISABLED (0xFFU) + +/* Version of this module's code and API. */ + +#if 1 == BSP_CFG_RTOS /* ThreadX */ + #include "tx_user.h" + #if defined(TX_ENABLE_EVENT_TRACE) || defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) + #include "tx_port.h" + #define FSP_CONTEXT_SAVE tx_isr_start((uint32_t) R_FSP_CurrentIrqGet()); + #define FSP_CONTEXT_RESTORE tx_isr_end((uint32_t) R_FSP_CurrentIrqGet()); + #else + #define FSP_CONTEXT_SAVE + #define FSP_CONTEXT_RESTORE + #endif +#else + #define FSP_CONTEXT_SAVE + #define FSP_CONTEXT_RESTORE +#endif + +/** Macro that can be defined in order to enable logging in FSP modules. */ +#ifndef FSP_LOG_PRINT + #define FSP_LOG_PRINT(X) +#endif + +/** Macro to log and return error without an assertion. */ +#ifndef FSP_RETURN + + #define FSP_RETURN(err) FSP_ERROR_LOG((err)); \ + return err; +#endif + +/** This function is called before returning an error code. To stop on a runtime error, define fsp_error_log in + * user code and do required debugging (breakpoints, stack dump, etc) in this function.*/ +#if (1 == BSP_CFG_ASSERT) + + #ifndef FSP_ERROR_LOG + #define FSP_ERROR_LOG(err) \ + fsp_error_log((err), __FILE__, __LINE__); + #endif +#else + + #define FSP_ERROR_LOG(err) +#endif + +/** Default assertion calls ::FSP_ERROR_RETURN if condition "a" is false. Used to identify incorrect use of API's in FSP + * functions. */ +#if (3 == BSP_CFG_ASSERT) + #define FSP_ASSERT(a) +#elif (2 == BSP_CFG_ASSERT) + #define FSP_ASSERT(a) {assert(a);} +#else + #define FSP_ASSERT(a) FSP_ERROR_RETURN((a), FSP_ERR_ASSERTION) +#endif // ifndef FSP_ASSERT + +/** All FSP error codes are returned using this macro. Calls ::FSP_ERROR_LOG function if condition "a" is false. Used + * to identify runtime errors in FSP functions. */ + +#define FSP_ERROR_RETURN(a, err) \ + { \ + if ((a)) \ + { \ + (void) 0; /* Do nothing */ \ + } \ + else \ + { \ + FSP_ERROR_LOG(err); \ + return err; \ + } \ + } + +/* Function-like macro used to wait for a condition to be met, most often used to wait for hardware register updates. + * This macro can be redefined to add a timeout if necessary. */ +#ifndef FSP_HARDWARE_REGISTER_WAIT + #define FSP_HARDWARE_REGISTER_WAIT(reg, required_value) while (reg != required_value) { /* Wait. */} +#endif + +#ifndef FSP_REGISTER_READ + +/* Read a register and discard the result. */ + #define FSP_REGISTER_READ(A) __ASM volatile ("" : : "r" (A)); +#endif + +/**************************************************************** + * + * This check is performed to select suitable ASM API with respect to core + * + * The macros __CORE__ , __ARM7EM__ and __ARM_ARCH_8M_BASE__ are undefined for GCC, but defined(__IAR_SYSTEMS_ICC__) is false for GCC, so + * the left half of the || expression evaluates to false for GCC regardless of the values of these macros. */ + +#if (defined(__IICARM__) && defined(RENESAS_CORTEX_M23)) || defined(RENESAS_CORTEX_M4) + #ifndef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION + #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U) + #endif +#else + #ifdef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION + #undef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION + #endif + #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U) +#endif + +/* This macro defines a variable for saving previous mask value */ +#ifndef FSP_CRITICAL_SECTION_DEFINE + + #define FSP_CRITICAL_SECTION_DEFINE uint32_t old_mask_level = 0U +#endif + +/* These macros abstract methods to save and restore the interrupt state for different architectures. */ +#if (0 == BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION) + #define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_PRIMASK + #define FSP_CRITICAL_SECTION_SET_STATE __set_PRIMASK + #define FSP_CRITICAL_SECTION_IRQ_MASK_SET (1U) +#else + #define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_BASEPRI + #define FSP_CRITICAL_SECTION_SET_STATE __set_BASEPRI + #define FSP_CRITICAL_SECTION_IRQ_MASK_SET ((uint8_t) (BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION << \ + (8U - __NVIC_PRIO_BITS))) +#endif + +/** This macro temporarily saves the current interrupt state and disables interrupts. */ +#ifndef FSP_CRITICAL_SECTION_ENTER + #define FSP_CRITICAL_SECTION_ENTER \ + old_mask_level = FSP_CRITICAL_SECTION_GET_CURRENT_STATE(); \ + FSP_CRITICAL_SECTION_SET_STATE(FSP_CRITICAL_SECTION_IRQ_MASK_SET) +#endif + +/** This macro restores the previously saved interrupt state, reenabling interrupts. */ +#ifndef FSP_CRITICAL_SECTION_EXIT + #define FSP_CRITICAL_SECTION_EXIT FSP_CRITICAL_SECTION_SET_STATE(old_mask_level) +#endif + +/* Number of Cortex processor exceptions, used as an offset from XPSR value for the IRQn_Type macro. */ +#define FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS (16U) + +/** Used to signify that the requested IRQ vector is not defined in this system. */ +#define FSP_INVALID_VECTOR ((IRQn_Type) - 33) + +/* Private definition used in bsp_clocks and R_FSP_SystemClockHzGet. Each bitfield in SCKDIVCR is up to 4 bits wide. */ +#if (BSP_CFG_MCU_PART_SERIES == 8) + #define FSP_PRV_SCKDIVCR_DIV_MASK (0xFU) +#else + #define FSP_PRV_SCKDIVCR_DIV_MASK (0x7U) +#endif + +/* Use the secure registers for secure projects and flat projects. */ +#if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE + #define FSP_PRIV_TZ_USE_SECURE_REGS (1) +#else + #define FSP_PRIV_TZ_USE_SECURE_REGS (0) +#endif + +/* Put certain BSP variables in uninitialized RAM when initializing BSP early. */ +#if BSP_CFG_EARLY_INIT + #define BSP_SECTION_EARLY_INIT BSP_PLACE_IN_SECTION(BSP_SECTION_NOINIT) +#else + #define BSP_SECTION_EARLY_INIT +#endif + +/* Used to determine if this project is part of a multicore FSP Solution. */ +#if defined(BSP_PARTITION_FLASH_CPU1_S_START) + #define BSP_MULTICORE_PROJECT (1) +#else + #define BSP_MULTICORE_PROJECT (0) +#endif + +#if (BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD) && BSP_FEATURE_TZ_VERSION == 2 +BSP_CMSE_NONSECURE_ENTRY uint8_t R_BSP_NSC_STYPE3_RegU8Read(uint8_t volatile const * p_reg); +BSP_CMSE_NONSECURE_ENTRY uint16_t R_BSP_NSC_STYPE3_RegU16Read(uint16_t volatile const * p_reg); +BSP_CMSE_NONSECURE_ENTRY uint32_t R_BSP_NSC_STYPE3_RegU32Read(uint32_t volatile const * p_reg); + +#endif + +#if BSP_FEATURE_TZ_HAS_TRUSTZONE && BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 + +/* + * If the STYPE3 register's security attribution is set to secure, the non-secure application must read the register + * from the secure application using the provided non-secure callable functions. + */ + #define FSP_STYPE3_REG8_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU8Read((uint8_t const volatile *) &X))) + #define FSP_STYPE3_REG16_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU16Read((uint16_t const volatile *) &X))) + #define FSP_STYPE3_REG32_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU32Read((uint32_t const volatile *) &X))) +#elif BSP_FEATURE_TZ_HAS_TRUSTZONE && BSP_TZ_SECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 + +/*******************************************************************************************************************//** + * Read a non-secure 8-bit STYPE3 register in the secure state. + * + * @param[in] p_reg The address of the non-secure register. + * + * @return Value read from the register. + **********************************************************************************************************************/ +__STATIC_INLINE uint8_t R_BSP_S_STYPE3_RegU8Read (uint8_t volatile const * p_reg) +{ + p_reg = (uint8_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET); + + return *p_reg; +} + +/*******************************************************************************************************************//** + * Read a non-secure 16-bit STYPE3 register in the secure state. + * + * @param[in] p_reg The address of the non-secure register. + * + * @return Value read from the register. + **********************************************************************************************************************/ +__STATIC_INLINE uint16_t R_BSP_S_STYPE3_RegU16Read (uint16_t volatile const * p_reg) +{ + p_reg = (uint16_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET); + + return *p_reg; +} + +/*******************************************************************************************************************//** + * Read a non-secure 32-bit STYPE3 register in the secure state. + * + * @param[in] p_reg The address of the non-secure register. + * + * @return Value read from the register. + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_BSP_S_STYPE3_RegU32Read (uint32_t volatile const * p_reg) +{ + p_reg = (uint32_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET); + + return *p_reg; +} + +/* + * If the STYPE3 register's security attribution is set to non-secure, the secure application must read the register + * using the non-secure aliased address. + */ + #define FSP_STYPE3_REG8_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU8Read((uint8_t const volatile *) &X)) + #define FSP_STYPE3_REG16_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU16Read((uint16_t const volatile *) &X)) + #define FSP_STYPE3_REG32_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU32Read((uint32_t const volatile *) &X)) +#else + #define FSP_STYPE3_REG8_READ(X, S) (X) + #define FSP_STYPE3_REG16_READ(X, S) (X) + #define FSP_STYPE3_REG32_READ(X, S) (X) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Different warm start entry locations in the BSP. */ +typedef enum e_bsp_warm_start_event +{ + BSP_WARM_START_RESET = 0, ///< Called almost immediately after reset. No C runtime environment, clocks, or IRQs. + BSP_WARM_START_POST_CLOCK, ///< Called after clock initialization. No C runtime environment or IRQs. + BSP_WARM_START_POST_C ///< Called after clocks and C runtime environment have been set up +} bsp_warm_start_event_t; + +/* Private enum used in R_FSP_SystemClockHzGet. Maps clock name to base bit in SCKDIVCR. */ +typedef enum e_fsp_priv_clock +{ + FSP_PRIV_CLOCK_PCLKD = 0, + FSP_PRIV_CLOCK_PCLKC = 4, + FSP_PRIV_CLOCK_PCLKB = 8, + FSP_PRIV_CLOCK_PCLKA = 12, + FSP_PRIV_CLOCK_BCLK = 16, + FSP_PRIV_CLOCK_PCLKE = 20, + FSP_PRIV_CLOCK_ICLK = 24, + FSP_PRIV_CLOCK_FCLK = 28, + FSP_PRIV_CLOCK_CPUCLK = 32, + FSP_PRIV_CLOCK_UNUSED = 255, ///< Sentinel value for unused clock +} fsp_priv_clock_t; + +/* Private enum used in R_FSP_SciSpiClockHzGe. Maps clock name to base bit in SCISPICKCR. */ +typedef enum e_fsp_priv_source_clock +{ + FSP_PRIV_CLOCK_HOCO = 0, ///< The high speed on chip oscillator + FSP_PRIV_CLOCK_MOCO = 1, ///< The middle speed on chip oscillator + FSP_PRIV_CLOCK_LOCO = 2, ///< The low speed on chip oscillator + FSP_PRIV_CLOCK_MAIN_OSC = 3, ///< The main oscillator + FSP_PRIV_CLOCK_SUBCLOCK = 4, ///< The subclock oscillator + FSP_PRIV_CLOCK_PLL = 5, ///< The PLL output + FSP_PRIV_CLOCK_PLL1P = 5, ///< The PLL1P output + FSP_PRIV_CLOCK_PLL2 = 6, ///< The PLL2 output + FSP_PRIV_CLOCK_PLL2P = 6, ///< The PLL2P output + FSP_PRIV_CLOCK_PLL1Q = 7, ///< The PLL1Q output + FSP_PRIV_CLOCK_PLL1R = 8, ///< The PLL1R output + FSP_PRIV_CLOCK_PLL2Q = 9, ///< The PLL2Q output + FSP_PRIV_CLOCK_PLL2R = 10, ///< The PLL2R output +} fsp_priv_source_clock_t; + +typedef struct st_bsp_unique_id +{ + union + { + uint32_t unique_id_words[4]; + uint8_t unique_id_bytes[16]; + }; +} bsp_unique_id_t; + +typedef struct st_bsp_part_number +{ + union + { + uint32_t part_number_words[4]; + uint8_t part_number_bytes[16]; + }; +} bsp_part_number_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ +uint32_t R_BSP_SourceClockHzGet(fsp_priv_source_clock_t clock); + +/*********************************************************************************************************************** + * Global variables (defined in other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Inline Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Return active interrupt vector number value + * + * @return Active interrupt vector number value + **********************************************************************************************************************/ +__STATIC_INLINE IRQn_Type R_FSP_CurrentIrqGet (void) +{ + xPSR_Type xpsr_value; + xpsr_value.w = __get_xPSR(); + + return (IRQn_Type) (xpsr_value.b.ISR - FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS); +} + +/*******************************************************************************************************************//** + * Gets the frequency of a system clock. + * + * @return Frequency of requested clock in Hertz. + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock) +{ + /* Check if the provided clock is an unused clock. */ + if (FSP_PRIV_CLOCK_UNUSED == clock) + { + return 0; + } + +#if !BSP_FEATURE_CGC_REGISTER_SET_B + uint32_t sckdivcr = FSP_STYPE3_REG32_READ(R_SYSTEM->SCKDIVCR, BSP_CFG_CLOCKS_SECURE); + uint32_t clock_div = (sckdivcr >> clock) & FSP_PRV_SCKDIVCR_DIV_MASK; + + #if BSP_FEATURE_CGC_HAS_CPUCLK + if (FSP_PRIV_CLOCK_CPUCLK == clock) + { + return SystemCoreClock; + } + + /* Get CPUCLK divisor */ + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + #if (BSP_CFG_CPU_CORE == 1) + uint32_t cpuclk_div = + (FSP_STYPE3_REG16_READ(R_SYSTEM->SCKDIVCR2, BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SCKDIVCR2_CPUCK1_Msk) >> + R_SYSTEM_SCKDIVCR2_CPUCK1_Pos; + #else + uint32_t cpuclk_div = FSP_STYPE3_REG16_READ(R_SYSTEM->SCKDIVCR2, BSP_CFG_CLOCKS_SECURE) & FSP_PRV_SCKDIVCR_DIV_MASK; + #endif + #else + uint32_t cpuclk_div = FSP_STYPE3_REG8_READ(R_SYSTEM->SCKDIVCR2, BSP_CFG_CLOCKS_SECURE) & FSP_PRV_SCKDIVCR_DIV_MASK; + #endif + + /* Determine if either divisor is a multiple of 3 */ + if ((cpuclk_div | clock_div) & 8U) + { + /* Convert divisor settings to their actual values */ + cpuclk_div = (cpuclk_div & 8U) ? (3U << (cpuclk_div & 7U)) : (1U << cpuclk_div); + clock_div = (clock_div & 8U) ? (3U << (clock_div & 7U)) : (1U << clock_div); + + /* Calculate clock with multiplication and division instead of shifting */ + return (SystemCoreClock * cpuclk_div) / clock_div; + } + else + { + return (SystemCoreClock << cpuclk_div) >> clock_div; + } + + #else + uint32_t iclk_div = (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRV_SCKDIVCR_DIV_MASK; + + return (SystemCoreClock << iclk_div) >> clock_div; + #endif +#else + FSP_PARAMETER_NOT_USED(clock); + + return SystemCoreClock; +#endif +} + +/*******************************************************************************************************************//** + * Converts a clock's CKDIVCR register value to a clock divider (Eg: SPICKDIVCR). + * + * @return Clock Divider + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_FSP_ClockDividerGet (uint32_t ckdivcr) +{ + if (2U >= ckdivcr) + { + + /* clock_div: + * - Clock Divided by 1: 0 + * - Clock Divided by 2: 1 + * - Clock Divided by 4: 2 + */ + return 1U << ckdivcr; + } + else if (3U == ckdivcr) + { + + /* Clock Divided by 6 */ + return 6U; + } + else if (4U == ckdivcr) + { + + /* Clock Divided by 8 */ + return 8U; + } + else if (5U == ckdivcr) + { + + /* Clock Divided by 3 */ + return 3U; + } + else if (6U == ckdivcr) + { + + /* Clock Divided by 5 */ + return 5U; + } + else if (7U == ckdivcr) + { + + /* Clock Divided by 10 */ + return 10U; + } + else + { + + /* clock_div: + * - Clock Divided by 16: 8 + * - Clock Divided by 32: 9 + */ + return 16U << (ckdivcr - 8U); + } +} + +#if BSP_FEATURE_SCI_HAS_SCISPI_CLOCK + +/*******************************************************************************************************************//** + * Gets the frequency of a SCI/SPI clock. + * + * @return Frequency of requested clock in Hertz. + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_FSP_SciSpiClockHzGet (void) +{ + uint32_t scispidivcr = R_SYSTEM->SCISPICKDIVCR; + uint32_t clock_div = R_FSP_ClockDividerGet(scispidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); + fsp_priv_source_clock_t scispicksel = (fsp_priv_source_clock_t) R_SYSTEM->SCISPICKCR_b.SCISPICKSEL; + + return R_BSP_SourceClockHzGet(scispicksel) / clock_div; +} + +#endif +#if BSP_FEATURE_SPI_HAS_CLOCK + +/*******************************************************************************************************************//** + * Gets the frequency of a SPI clock. + * + * @return Frequency of requested clock in Hertz. + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_FSP_SpiClockHzGet (void) +{ + uint32_t spidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKDIVCR, BSP_CFG_CLOCKS_SECURE); + uint32_t clock_div = R_FSP_ClockDividerGet(spidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); + fsp_priv_source_clock_t spicksel = + (fsp_priv_source_clock_t) ((FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKCR, + BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SPICKCR_CKSEL_Msk) >> + R_SYSTEM_SPICKCR_CKSEL_Pos); + + return R_BSP_SourceClockHzGet(spicksel) / clock_div; +} + +#endif +#if BSP_FEATURE_SCI_HAS_CLOCK + +/*******************************************************************************************************************//** + * Gets the frequency of a SCI clock. + * + * @return Frequency of requested clock in Hertz. + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_FSP_SciClockHzGet (void) +{ + uint32_t scidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKDIVCR, BSP_CFG_CLOCKS_SECURE); + uint32_t clock_div = R_FSP_ClockDividerGet(scidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); + fsp_priv_source_clock_t scicksel = + (fsp_priv_source_clock_t) (FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKCR, + BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SCICKCR_SCICKSEL_Msk >> + R_SYSTEM_SCICKCR_SCICKSEL_Pos); + + return R_BSP_SourceClockHzGet(scicksel) / clock_div; +} + +#endif + +/*******************************************************************************************************************//** + * Get unique ID for this device. + * + * @return A pointer to the unique identifier structure + **********************************************************************************************************************/ +__STATIC_INLINE bsp_unique_id_t const * R_BSP_UniqueIdGet (void) +{ +#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + + return (bsp_unique_id_t *) (BSP_FEATURE_BSP_UNIQUE_ID_POINTER | BSP_FEATURE_TZ_NS_OFFSET); +#else + + return (bsp_unique_id_t *) BSP_FEATURE_BSP_UNIQUE_ID_POINTER; +#endif +} + +/*******************************************************************************************************************//** + * Get part number for this device. + * + * @param[out] p_part_number Memory address to return MCU's part number to. + * + * @retval FSP_SUCCESS Part number information stored. + * @retval FSP_ERR_ASSERTION The parameter p_part_number is NULL. + * @retval FSP_ERR_NOT_FOUND An error occurred when retrieving data from part number register. + **********************************************************************************************************************/ +__STATIC_INLINE fsp_err_t R_BSP_PartNumberGet (bsp_part_number_t * const p_part_number) +{ +#if BSP_CFG_PARAM_CHECKING_ENABLE + + /** Verify parameters are valid */ + if (NULL == p_part_number) + { + return FSP_ERR_ASSERTION; + } +#endif + + /* Pointer to Part Numbering Register PNR */ +#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + bsp_part_number_t * p_pnr = (bsp_part_number_t *) (BSP_FEATURE_BSP_PART_NUMBER_POINTER | BSP_FEATURE_TZ_NS_OFFSET); +#else + bsp_part_number_t * p_pnr = (bsp_part_number_t *) BSP_FEATURE_BSP_PART_NUMBER_POINTER; +#endif + + /* In case part number is following the right order + * for example: R 7 F A 8 E 1 A F D C F B_ _ _ */ + if (p_pnr->part_number_bytes[0] == 'R') + { + memcpy(p_part_number, p_pnr, sizeof(bsp_part_number_t)); + } + /* In case part number is in reverse order, 'R' letter should be in position 12 + * for example: K N C 3 7 0 1 E 0 A F 7 R _ _ _ */ + else if (p_pnr->part_number_bytes[12] == 'R') + { + for (uint8_t i = 0; i < sizeof(bsp_part_number_t); i++) + { + if (i <= 12) + { + p_part_number->part_number_bytes[i] = p_pnr->part_number_bytes[12 - i]; + } + else + { + p_part_number->part_number_bytes[i] = p_pnr->part_number_bytes[i]; + } + } + } + else + { + return FSP_ERR_NOT_FOUND; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Disables the flash cache. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_FlashCacheDisable (void) +{ +#if BSP_FEATURE_FLASH_CACHE + R_FCACHE->FCACHEE = 0U; +#endif + +#ifdef R_CACHE + #if BSP_FEATURE_FLASH_CODE_CACHE_VERSION == 2 + uint32_t volatile * p_ccactl = &R_CACHE->CCACTL; + uint32_t volatile * p_ccawta = &R_CACHE->CCAWTA; + + #if BSP_TZ_SECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 + if (1 == R_CPSCU->CACHESAR_b.CACHESA) + { + /* Access CCACTL using the non-secure alias. */ + p_ccactl = (uint32_t volatile *) ((uint32_t) p_ccactl | BSP_FEATURE_TZ_NS_OFFSET); + + /* Access CCAWTA using the non-secure alias. */ + p_ccawta = (uint32_t volatile *) ((uint32_t) p_ccawta | BSP_FEATURE_TZ_NS_OFFSET); + } + #endif + + /* Writeback and flush cache when disabling + * Refer to the CCAFCT register description in the relevant hardware manual */ + if (*p_ccawta & R_CACHE_CCAWTA_WT_Msk) + { + *p_ccactl = R_CACHE_CCACTL_FC_Msk; + } + else + { + *p_ccactl = R_CACHE_CCACTL_FC_Msk | R_CACHE_CCACTL_WB_Msk; + } + + FSP_HARDWARE_REGISTER_WAIT(R_CACHE->CCAFCT, 0U); + #else + + /* Disable the C-Cache. */ + R_CACHE->CCACTL = 0U; + #endif +#endif +} + +/*******************************************************************************************************************//** + * Enables the flash cache. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_FlashCacheEnable (void) +{ +#if BSP_FEATURE_FLASH_CACHE + + /* Invalidate the flash cache and wait until it is invalidated. (See "Operation" in the Flash Memory section + * of the relevant hardware manual). */ + R_FCACHE->FCACHEIV = 1U; + FSP_HARDWARE_REGISTER_WAIT(R_FCACHE->FCACHEIV, 0U); + + /* Enable flash cache. */ + R_FCACHE->FCACHEE = 1U; +#endif + +#ifdef R_CACHE + #if BSP_FEATURE_FLASH_CODE_CACHE_VERSION == 1 + + /* Configure the C-Cache line size. */ + R_CACHE->CCALCF = BSP_CFG_C_CACHE_LINE_SIZE; + + /* Enable the C-Cache. */ + R_CACHE->CCACTL = 1U; + #else + uint32_t volatile * p_ccactl = &R_CACHE->CCACTL; + + /* Flush cache before enabling */ + R_CACHE->CCAFCT_b.FC = 1; + + /* Check that no flush or writeback are ongoing before enabling + * Refer to the CCAFCT register description in the relevant hardware manual */ + FSP_HARDWARE_REGISTER_WAIT(R_CACHE->CCAFCT, 0U); + + #if BSP_TZ_SECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 + if (1 == R_CPSCU->CACHESAR_b.CACHESA) + { + /* Access CCACTL using the non-secure alias. */ + p_ccactl = (uint32_t volatile *) ((uint32_t) p_ccactl | BSP_FEATURE_TZ_NS_OFFSET); + } + #endif + + /* Enable the C-Cache. */ + *p_ccactl = 1U; + #endif +#endif +} + +#if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS && !BSP_SECONDARY_CORE_BUILD && defined(BSP_PARTITION_FLASH_CPU1_S_START) + #define BSP_CPU1ACTCSR_KEY_CODE 0xA5 + +/*******************************************************************************************************************//** + * Sets the secondary core VTOR and activates the secondary core. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_SecondaryCoreStart (void) +{ + /* Setup secondary CPU vector table */ + R_CPU_CTRL->CPU1INITVTOR = (uint32_t) BSP_PARTITION_FLASH_CPU1_S_START; + + /* When debugging multicore projects, CPU1 may already be activated by the debugger with CPU1WAITCR set to 1. + * This allows the debugger to connect to CPU1 prior to it being started by CPU0. + * If this is the case, then the secondary core must be started by clearing CPU1WAITCR. */ + R_CPU_CTRL->CPU1WAITCR = 0; + + /* Activate secondary CPU by setting key code and activation request in CPU1ACTCSR */ + R_CPU_CTRL->CPU1ACTCSR = (BSP_CPU1ACTCSR_KEY_CODE << R_CPU_CTRL_CPU1ACTCSR_KEY_Pos) | + R_CPU_CTRL_CPU1ACTCSR_ACTREQ_Msk; +} + +#endif + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +#if (1 == BSP_CFG_ASSERT) + +/** Prototype of default function called before errors are returned in FSP code if BSP_CFG_LOG_ERRORS is set to 1. */ +void fsp_error_log(fsp_err_t err, const char * file, int32_t line); + +#endif + +/** In the event of an unrecoverable error the BSP will by default call the __BKPT() intrinsic function which will + * alert the user of the error. The user can override this default behavior by defining their own + * BSP_CFG_HANDLE_UNRECOVERABLE_ERROR macro. + */ +#if !defined(BSP_CFG_HANDLE_UNRECOVERABLE_ERROR) + + #define BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(x) __BKPT((x)) +#endif + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h new file mode 100644 index 00000000000..9ddff68ed5d --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h @@ -0,0 +1,90 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +#ifndef BSP_COMPILER_SUPPORT_H + #define BSP_COMPILER_SUPPORT_H + + #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + #include "arm_cmse.h" + #endif + + #ifdef __cplusplus +extern "C" { + #endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + #if defined(__ARMCC_VERSION) /* AC6 compiler */ + +/* The AC6 linker requires uninitialized code to be placed in a section that starts with ".bss." Without this, load + * memory (ROM) is reserved unnecessarily. */ + #define BSP_UNINIT_SECTION_PREFIX ".bss" + #define BSP_DONT_REMOVE __attribute__((used)) + #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked)) + #define BSP_FORCE_INLINE __attribute__((always_inline)) + #elif defined(__GNUC__) /* GCC compiler */ + #define BSP_UNINIT_SECTION_PREFIX + #define BSP_DONT_REMOVE __attribute__((used)) + #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked)) + #define BSP_FORCE_INLINE __attribute__((always_inline)) + #elif defined(__ICCARM__) /* IAR compiler */ + #define BSP_UNINIT_SECTION_PREFIX + #define BSP_DONT_REMOVE __root + #define BSP_ATTRIBUTE_STACKLESS __stackless + #define BSP_FORCE_INLINE _Pragma("inline=forced") + #endif + + #define BSP_SECTION_NOINIT BSP_UNINIT_SECTION_PREFIX ".ram_noinit" + #define BSP_SECTION_FIXED_VECTORS ".fixed_vectors" + #define BSP_SECTION_APPLICATION_VECTORS ".application_vectors" + +/* Compiler neutral macros. */ + #define BSP_PLACE_IN_SECTION(x) __attribute__((section(x))) __attribute__((__used__)) + + #define BSP_ALIGN_VARIABLE(x) __attribute__((aligned(x))) + + #define BSP_WEAK_REFERENCE __attribute__((weak)) + +/** Stacks (and heap) must be sized and aligned to an integer multiple of this number. */ + #define BSP_STACK_ALIGNMENT (8) + +/*********************************************************************************************************************** + * TrustZone definitions + **********************************************************************************************************************/ + #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) && !defined(__clang_analyzer__) + #if defined(__ICCARM__) /* IAR compiler */ + #define BSP_CMSE_NONSECURE_CALL __cmse_nonsecure_call + #define BSP_CMSE_NONSECURE_ENTRY __cmse_nonsecure_entry + #else + #define BSP_CMSE_NONSECURE_CALL __attribute__((cmse_nonsecure_call)) + #define BSP_CMSE_NONSECURE_ENTRY __attribute__((cmse_nonsecure_entry)) + #endif + #else + #define BSP_CMSE_NONSECURE_CALL + #define BSP_CMSE_NONSECURE_ENTRY + #endif + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** @} (end of addtogroup BSP_MCU) */ + + #ifdef __cplusplus +} + #endif + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_delay.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_delay.c new file mode 100644 index 00000000000..56411fd2e4a --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_delay.c @@ -0,0 +1,205 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "bsp_delay.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_DELAY_NS_PER_SECOND (1000000000) +#define BSP_DELAY_US_PER_SECOND (1000000) +#define BSP_DELAY_NS_PER_US (1000) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Delay for at least the specified duration in units and return. + * @param[in] delay The number of 'units' to delay. + * @param[in] units The 'base' (bsp_delay_units_t) for the units specified. Valid values are: + * BSP_DELAY_UNITS_SECONDS, BSP_DELAY_UNITS_MILLISECONDS, BSP_DELAY_UNITS_MICROSECONDS.@n + * For example:@n + * At 1 MHz one cycle takes 1 microsecond (.000001 seconds).@n + * At 12 MHz one cycle takes 1/12 microsecond or 83 nanoseconds.@n + * Therefore one run through bsp_prv_software_delay_loop() takes: + * ~ (83 * BSP_DELAY_LOOP_CYCLES) or 332 ns. + * A delay of 2 us therefore requires 2000ns/332ns or 6 loops. + * + * The 'theoretical' maximum delay that may be obtained is determined by a full 32 bit loop count and the system clock rate. + * @120MHz: ((0xFFFFFFFF loops * 4 cycles /loop) / 120000000) = 143 seconds. + * @32MHz: ((0xFFFFFFFF loops * 4 cycles /loop) / 32000000) = 536 seconds + * + * Note that requests for very large delays will be affected by rounding in the calculations and the actual delay + * achieved may be slightly longer. @32 MHz, for example, a request for 532 seconds will be closer to 536 seconds. + * + * Note also that if the calculations result in a loop_cnt of zero, the bsp_prv_software_delay_loop() function is not called + * at all. In this case the requested delay is too small (nanoseconds) to be carried out by the loop itself, and the + * overhead associated with executing the code to just get to this point has certainly satisfied the requested delay. + * + * @note This function calls bsp_cpu_clock_get() which ultimately calls R_CGC_SystemClockFreqGet() and therefore requires + * that the BSP has already initialized the CGC (which it does as part of the Sysinit). + * Care should be taken to ensure this remains the case if in the future this function were to be called as part + * of the BSP initialization. + * + * @note This function will delay for **at least** the specified duration. Due to overhead in calculating the correct number + * of loops to delay, very small delay values (generally 1-5 microseconds) may be significantly longer than specified. + * Approximate overhead for this function is as follows: + * - CM4: 20-50 cycles + * - CM33: 10-60 cycles + * - CM23: 75-200 cycles + * + * @note If more accurate microsecond timing must be performed in software it is recommended to use + * bsp_prv_software_delay_loop() directly. In this case, use BSP_DELAY_LOOP_CYCLES or BSP_DELAY_LOOPS_CALCULATE() + * to convert a calculated delay cycle count to a number of software delay loops. + * + * @note Delays may be longer than expected when compiler optimization is turned off. + * + * @warning The delay will be longer than specified on CM23 devices when the core clock is greater than 32 MHz. Setting + * BSP_DELAY_LOOP_CYCLES to 6 will improve accuracy at 48 MHz but will result in shorter than expected delays + * at lower speeds. + **********************************************************************************************************************/ + +void R_BSP_SoftwareDelay (uint32_t delay, bsp_delay_units_t units) +{ + uint32_t iclk_hz; + uint32_t loops_required = 0; + uint32_t total_us = (delay * units); /** Convert the requested time to microseconds. */ + + iclk_hz = SystemCoreClock; /** Get the system clock frequency in Hz. */ + +#if (BSP_CFG_MCU_PART_SERIES == 8) || (BSP_CFG_MCU_PART_SERIES == 6) + if (iclk_hz >= BSP_MOCO_HZ) + { + /* For larger system clock values the below calculation in the else causes inaccurate delays due to rounding errors: + * + * ns_per_cycle = BSP_DELAY_NS_PER_SECOND / iclk_hz + * + * For system clock values greater than the MOCO speed the following delay calculation is used instead. + * The value is always rounded up to ensure the delay is at least the supplied value. + */ + uint32_t cycles_per_us = (iclk_hz + (BSP_DELAY_US_PER_SECOND * BSP_DELAY_LOOP_CYCLES) - 1) / + (BSP_DELAY_US_PER_SECOND * BSP_DELAY_LOOP_CYCLES); + + uint64_t loops_required_u64 = ((uint64_t) total_us) * cycles_per_us; + + if (loops_required_u64 > UINT32_MAX) + { + loops_required = UINT32_MAX; + } + else + { + loops_required = (uint32_t) loops_required_u64; + } + } + else +#endif + { + uint32_t cycles_requested; + uint32_t ns_per_cycle; + uint64_t ns_64bits; + + /* Running on the Sub-clock (32768 Hz) there are 30517 ns/cycle. This means one cycle takes 31 us. One execution + * loop of the delay_loop takes 6 cycles which at 32768 Hz is 180 us. That does not include the overhead below prior to even getting + * to the delay loop. Given this, at this frequency anything less then a delay request of 122 us will not even generate a single + * pass through the delay loop. For this reason small delays (<=~200 us) at this slow clock rate will not be possible and such a request + * will generate a minimum delay of ~200 us.*/ + ns_per_cycle = BSP_DELAY_NS_PER_SECOND / iclk_hz; /** Get the # of nanoseconds/cycle. */ + + /* We want to get the time in total nanoseconds but need to be conscious of overflowing 32 bits. We also do not want to do 64 bit */ + /* division as that pulls in a division library. */ + ns_64bits = (uint64_t) total_us * (uint64_t) BSP_DELAY_NS_PER_US; // Convert to ns. + + /* Have we overflowed 32 bits? */ + if (ns_64bits <= UINT32_MAX) + { + /* No, we will not overflow. */ + cycles_requested = ((uint32_t) ns_64bits / ns_per_cycle); + loops_required = cycles_requested / BSP_DELAY_LOOP_CYCLES; + } + else + { + /* We did overflow. Try dividing down first. */ + total_us = (total_us / (ns_per_cycle * BSP_DELAY_LOOP_CYCLES)); + ns_64bits = (uint64_t) total_us * (uint64_t) BSP_DELAY_NS_PER_US; // Convert to ns. + + /* Have we overflowed 32 bits? */ + if (ns_64bits <= UINT32_MAX) + { + /* No, we will not overflow. */ + loops_required = (uint32_t) ns_64bits; + } + else + { + /* We still overflowed, use the max count for cycles */ + loops_required = UINT32_MAX; + } + } + } + + /** Only delay if the supplied parameters constitute a delay. */ + if (loops_required > (uint32_t) 0) + { + bsp_prv_software_delay_loop(loops_required); + } +} + +/** @} (end addtogroup BSP_MCU) */ + +/*******************************************************************************************************************//** + * This assembly language routine takes roughly 4 cycles per loop. 2 additional cycles + * occur when the loop exits. The 'naked' attribute indicates that the specified function does not need + * prologue/epilogue sequences generated by the compiler. + * @param[in] loop_cnt The number of loops to iterate. + **********************************************************************************************************************/ +BSP_ATTRIBUTE_STACKLESS void bsp_prv_software_delay_loop (__attribute__( + (unused)) uint32_t loop_cnt) +{ + __asm volatile ( +#if defined(RENESAS_CORTEX_M85) && (defined(__ARMCC_VERSION) || defined(__GNUC__)) + + /* Align the branch target to a 64-bit boundary, a CM85 specific optimization. */ + /* IAR does not support alignment control within inline assembly. */ + ".balign 8\n" +#endif + "sw_delay_loop: \n" +#if defined(__ICCARM__) || defined(__ARMCC_VERSION) || (defined(__llvm__) && !defined(__CLANG_TIDY__)) + " subs r0, #1 \n" ///< 1 cycle +#elif defined(__GNUC__) + " sub r0, r0, #1 \n" ///< 1 cycle +#endif + + " cmp r0, #0 \n" ///< 1 cycle + +/* CM0 and CM23 have a different instruction set */ +#if defined(__CORE_CM0PLUS_H_GENERIC) || defined(__CORE_CM23_H_GENERIC) + " bne sw_delay_loop \n" ///< 2 cycles +#else + " bne.n sw_delay_loop \n" ///< 2 cycles +#endif + " bx lr \n"); ///< 2 cycles +} diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_delay.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_delay.h new file mode 100644 index 00000000000..a2f699765a5 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_delay.h @@ -0,0 +1,77 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_DELAY_H +#define BSP_DELAY_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#include "bsp_compiler_support.h" + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* The number of cycles required per software delay loop. */ +#ifndef BSP_DELAY_LOOP_CYCLES + #if defined(RENESAS_CORTEX_M85) + +/* On M85 cores, code alignment can affect execution speed. bsp_prv_software_delay_loop is aligned to 8 bytes for + * GCC and AC6, but IAR does not support aligning code. The below ensures the correct loop cycle count is used in + * this case. */ + #if defined(__ICCARM__) + #define BSP_DELAY_LOOP_CYCLES (((uint32_t) bsp_prv_software_delay_loop & 0x6) ? 2 : 1) + #else + #define BSP_DELAY_LOOP_CYCLES (1) + #endif + +/* On devices with Flash LP, ROM reads take an additional cycle when ICLK is greater than 32 MHz. */ + #elif BSP_FEATURE_CGC_HAS_MEMWAIT && !BSP_FEATURE_FLASH_CACHE && (BSP_FEATURE_FLASH_CODE_CACHE_VERSION == 0) + #define BSP_DELAY_LOOP_CYCLES (4 + (2 * (uint32_t) (SystemCoreClock > 32000000))) + #else + #define BSP_DELAY_LOOP_CYCLES (4) + #endif +#endif + +/* Calculates the number of delay loops to pass to bsp_prv_software_delay_loop to achieve at least the requested cycle + * count delay. This is 1 loop longer than optimal if cycles is a multiple of BSP_DELAY_LOOP_CYCLES, but it ensures + * the requested number of loops is at least 1 since bsp_prv_software_delay_loop cannot be called with a loop count + * of 0. */ +#define BSP_DELAY_LOOPS_CALCULATE(cycles) (((cycles) / BSP_DELAY_LOOP_CYCLES) + 1U) + +/** Available delay units for R_BSP_SoftwareDelay(). These are ultimately used to calculate a total # of microseconds */ +typedef enum +{ + BSP_DELAY_UNITS_SECONDS = 1000000, ///< Requested delay amount is in seconds + BSP_DELAY_UNITS_MILLISECONDS = 1000, ///< Requested delay amount is in milliseconds + BSP_DELAY_UNITS_MICROSECONDS = 1 ///< Requested delay amount is in microseconds +} bsp_delay_units_t; + +/** @} (end addtogroup BSP_MCU) */ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +BSP_ATTRIBUTE_STACKLESS void bsp_prv_software_delay_loop(uint32_t loop_cnt); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_exceptions.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_exceptions.h new file mode 100644 index 00000000000..f388be32937 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_exceptions.h @@ -0,0 +1,44 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/** @} (end addtogroup BSP_MCU) */ + +#ifndef BSP_EXCEPTIONS_H + #define BSP_EXCEPTIONS_H + + #ifdef __cplusplus +extern "C" { + #endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* This list includes only Arm standard exceptions. Renesas interrupts are defined in vector_data.h. */ +typedef enum IRQn +{ + Reset_IRQn = -15, /* 1 Reset Vector invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /* 2 Non maskable Interrupt cannot be stopped or preempted */ + HardFault_IRQn = -13, /* 3 Hard Fault all classes of Fault */ + MemoryManagement_IRQn = -12, /* 4 Memory Management MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /* 5 Bus Fault Pre-Fetch-, Memory Access, other address/memory Fault */ + UsageFault_IRQn = -10, /* 6 Usage Fault i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ + SVCall_IRQn = -5, /* 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor */ + PendSV_IRQn = -2, /* 14 Pendable request for system service */ + SysTick_IRQn = -1, /* 15 System Tick Timer */ +} IRQn_Type; + + #ifdef __cplusplus +} + #endif + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c new file mode 100644 index 00000000000..6b6f6d8c467 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c @@ -0,0 +1,122 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#if (BSP_FEATURE_ICU_NMIER_MAX_INDEX > 15U) + #define BSP_PRV_NMIER_T uint32_t +#else + #define BSP_PRV_NMIER_T uint16_t +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/** This array holds callback functions. */ +bsp_grp_irq_cb_t g_bsp_group_irq_sources[BSP_FEATURE_ICU_NMIER_MAX_INDEX + 1] BSP_SECTION_EARLY_INIT; + +void NMI_Handler(void); +static void bsp_group_irq_call(bsp_grp_irq_t irq); + +/*******************************************************************************************************************//** + * Calls the callback function for an interrupt if a callback has been registered. + * + * @param[in] irq Which interrupt to check and possibly call. + * + * @retval FSP_SUCCESS Callback was called. + * @retval FSP_ERR_INVALID_ARGUMENT No valid callback has been registered for this interrupt source. + * + * @warning This function is called from within an interrupt + **********************************************************************************************************************/ +static void bsp_group_irq_call (bsp_grp_irq_t irq) +{ + /** Check for valid callback */ + if (NULL != g_bsp_group_irq_sources[irq]) + { + /** Callback has been found. Call it. */ + g_bsp_group_irq_sources[irq](irq); + } +} + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Register a callback function for supported interrupts. If NULL is passed for the callback argument then any + * previously registered callbacks are unregistered. + * + * @param[in] irq Interrupt for which to register a callback. + * @param[in] p_callback Pointer to function to call when interrupt occurs. + * + * @retval FSP_SUCCESS Callback registered + * @retval FSP_ERR_ASSERTION Callback pointer is NULL + **********************************************************************************************************************/ +fsp_err_t R_BSP_GroupIrqWrite (bsp_grp_irq_t irq, void (* p_callback)(bsp_grp_irq_t irq)) +{ +#if BSP_CFG_PARAM_CHECKING_ENABLE + + /* Check pointer for NULL value. */ + FSP_ASSERT(p_callback); +#endif + + /* Register callback. */ + g_bsp_group_irq_sources[irq] = p_callback; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Non-maskable interrupt handler. This exception is defined by the BSP, unlike other system exceptions, because + * there are many sources that map to the NMI exception. + **********************************************************************************************************************/ +void NMI_Handler (void) +{ + /* NMISR is masked by NMIER to prevent iterating over NMI status flags that are not enabled. */ + BSP_PRV_NMIER_T nmier = R_ICU->NMIER; + BSP_PRV_NMIER_T nmisr = R_ICU->NMISR & nmier; + + /* Loop over all NMI status flags */ + for (bsp_grp_irq_t irq = BSP_GRP_IRQ_IWDT_ERROR; irq <= (bsp_grp_irq_t) (BSP_FEATURE_ICU_NMIER_MAX_INDEX); irq++) + { + /* If the current irq status register is set call the irq callback. */ + if (0U != (nmisr & (1U << irq))) + { + (void) bsp_group_irq_call(irq); + } + } + + /* Clear status flags that have been handled. */ + R_ICU->NMICLR = nmisr; + +#if BSP_CFG_MCU_PART_SERIES == 8 + + /* Wait for NMISR to be cleared before exiting the ISR to prevent the IRQ from being regenerated. + * See "NMICLR : Non-Maskable Interrupt Status Clear Register" description in the ICU section + * of the relevant hardware manual */ + FSP_HARDWARE_REGISTER_WAIT((R_ICU->NMISR & nmisr), 0); +#endif +} + +/** @} (end addtogroup BSP_MCU) */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h new file mode 100644 index 00000000000..5aede0736ca --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h @@ -0,0 +1,69 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_GROUP_IRQ_H +#define BSP_GROUP_IRQ_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#ifndef BSP_OVERRIDE_GROUP_IRQ_T + +/** Which interrupts can have callbacks registered. */ +typedef enum e_bsp_grp_irq +{ + BSP_GRP_IRQ_IWDT_ERROR = 0, ///< IWDT underflow/refresh error has occurred + BSP_GRP_IRQ_WDT_ERROR = 1, ///< WDT underflow/refresh error has occurred + BSP_GRP_IRQ_LVD1 = 2, ///< Voltage monitoring 1 interrupt + BSP_GRP_IRQ_LVD2 = 3, ///< Voltage monitoring 2 interrupt + BSP_GRP_IRQ_VBATT = 4, ///< VBATT monitor interrupt + BSP_GRP_IRQ_OSC_STOP_DETECT = 6, ///< Oscillation stop is detected + BSP_GRP_IRQ_NMI_PIN = 7, ///< NMI Pin interrupt + BSP_GRP_IRQ_RAM_PARITY = 8, ///< RAM Parity Error + BSP_GRP_IRQ_RAM_ECC = 9, ///< RAM ECC Error + BSP_GRP_IRQ_MPU_BUS_SLAVE = 10, ///< MPU Bus Slave Error + BSP_GRP_IRQ_MPU_BUS_MASTER = 11, ///< MPU Bus Master Error + BSP_GRP_IRQ_MPU_STACK = 12, ///< MPU Stack Error + BSP_GRP_IRQ_TRUSTZONE = 13, ///< MPU Stack Error + BSP_GRP_IRQ_CACHE_PARITY = 15, ///< MPU Stack Error +} bsp_grp_irq_t; + +#endif + +/* Callback type. */ +typedef void (* bsp_grp_irq_cb_t)(bsp_grp_irq_t irq); + +/** @} (end addtogroup BSP_MCU) */ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/* Public functions defined in bsp.h */ +void bsp_group_interrupt_open(void); // Used internally by BSP + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_guard.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_guard.c new file mode 100644 index 00000000000..605fc63af26 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_guard.c @@ -0,0 +1,41 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "bsp_guard.h" + +/* Only the secure project has nonsecure callable functions. */ +#if BSP_TZ_SECURE_BUILD + +/* If the CGG Security Attribution is configured to secure access only. */ + #if BSP_CFG_CLOCKS_SECURE == 1 + +/*******************************************************************************************************************//** + * Set the callback used by the secure project to notify the nonsecure project when the clock settings have changed. + * + * @retval FSP_SUCCESS Callback set. + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + **********************************************************************************************************************/ +BSP_CMSE_NONSECURE_ENTRY fsp_err_t R_BSP_ClockUpdateCallbackSet (bsp_clock_update_callback_t p_callback, + bsp_clock_update_callback_args_t * p_callback_memory) +{ + bsp_clock_update_callback_t p_callback_checked = + (bsp_clock_update_callback_t) cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE); + + bsp_clock_update_callback_args_t * p_callback_memory_checked = + (bsp_clock_update_callback_args_t *) cmse_check_address_range(p_callback_memory, + sizeof(bsp_clock_update_callback_args_t), + CMSE_AU_NONSECURE); + FSP_ASSERT(p_callback == p_callback_checked); + FSP_ASSERT(p_callback_memory == p_callback_memory_checked); + + r_bsp_clock_update_callback_set(p_callback_checked, p_callback_memory_checked); + + return FSP_SUCCESS; +} + + #endif + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_guard.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_guard.h new file mode 100644 index 00000000000..bb9617de61b --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_guard.h @@ -0,0 +1,32 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_GUARD_H +#define BSP_GUARD_H + +#include "bsp_api.h" + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#if BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD +BSP_CMSE_NONSECURE_ENTRY fsp_err_t R_BSP_ClockUpdateCallbackSet(bsp_clock_update_callback_t p_callback, + bsp_clock_update_callback_args_t * p_callback_memory); + +#endif + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_io.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_io.c new file mode 100644 index 00000000000..b53d7b98056 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_io.c @@ -0,0 +1,27 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ +volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT; + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_io.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_io.h new file mode 100644 index 00000000000..418c753808d --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_io.h @@ -0,0 +1,465 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @defgroup BSP_IO BSP I/O access + * @ingroup RENESAS_COMMON + * @brief This module provides basic read/write access to port pins. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BSP_IO_H +#define BSP_IO_H + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Private definition to set enumeration values. */ +#define BSP_IO_PRV_PFS_PSEL_OFFSET (24) +#define BSP_IO_PRV_8BIT_MASK (0xFF) +#define BSP_IO_PWPR_B0WI_OFFSET (7U) +#define BSP_IO_PWPR_PFSWE_OFFSET (6U) +#define BSP_IO_PFS_PDR_OUTPUT (4U) +#define BSP_IO_PRV_PIN_WRITE_MASK (0xFFFE3FFE) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Levels that can be set and read for individual pins */ +typedef enum e_bsp_io_level +{ + BSP_IO_LEVEL_LOW = 0, ///< Low + BSP_IO_LEVEL_HIGH ///< High +} bsp_io_level_t; + +/** Direction of individual pins */ +typedef enum e_bsp_io_dir +{ + BSP_IO_DIRECTION_INPUT = 0, ///< Input + BSP_IO_DIRECTION_OUTPUT ///< Output +} bsp_io_direction_t; + +/** Superset list of all possible IO ports. */ +typedef enum e_bsp_io_port +{ + BSP_IO_PORT_00 = 0x0000, ///< IO port 0 + BSP_IO_PORT_01 = 0x0100, ///< IO port 1 + BSP_IO_PORT_02 = 0x0200, ///< IO port 2 + BSP_IO_PORT_03 = 0x0300, ///< IO port 3 + BSP_IO_PORT_04 = 0x0400, ///< IO port 4 + BSP_IO_PORT_05 = 0x0500, ///< IO port 5 + BSP_IO_PORT_06 = 0x0600, ///< IO port 6 + BSP_IO_PORT_07 = 0x0700, ///< IO port 7 + BSP_IO_PORT_08 = 0x0800, ///< IO port 8 + BSP_IO_PORT_09 = 0x0900, ///< IO port 9 + BSP_IO_PORT_10 = 0x0A00, ///< IO port 10 + BSP_IO_PORT_11 = 0x0B00, ///< IO port 11 + BSP_IO_PORT_12 = 0x0C00, ///< IO port 12 + BSP_IO_PORT_13 = 0x0D00, ///< IO port 13 + BSP_IO_PORT_14 = 0x0E00, ///< IO port 14 +} bsp_io_port_t; + +/** Superset list of all possible IO port pins. */ +typedef enum e_bsp_io_port_pin_t +{ + BSP_IO_PORT_00_PIN_00 = 0x0000, ///< IO port 0 pin 0 + BSP_IO_PORT_00_PIN_01 = 0x0001, ///< IO port 0 pin 1 + BSP_IO_PORT_00_PIN_02 = 0x0002, ///< IO port 0 pin 2 + BSP_IO_PORT_00_PIN_03 = 0x0003, ///< IO port 0 pin 3 + BSP_IO_PORT_00_PIN_04 = 0x0004, ///< IO port 0 pin 4 + BSP_IO_PORT_00_PIN_05 = 0x0005, ///< IO port 0 pin 5 + BSP_IO_PORT_00_PIN_06 = 0x0006, ///< IO port 0 pin 6 + BSP_IO_PORT_00_PIN_07 = 0x0007, ///< IO port 0 pin 7 + BSP_IO_PORT_00_PIN_08 = 0x0008, ///< IO port 0 pin 8 + BSP_IO_PORT_00_PIN_09 = 0x0009, ///< IO port 0 pin 9 + BSP_IO_PORT_00_PIN_10 = 0x000A, ///< IO port 0 pin 10 + BSP_IO_PORT_00_PIN_11 = 0x000B, ///< IO port 0 pin 11 + BSP_IO_PORT_00_PIN_12 = 0x000C, ///< IO port 0 pin 12 + BSP_IO_PORT_00_PIN_13 = 0x000D, ///< IO port 0 pin 13 + BSP_IO_PORT_00_PIN_14 = 0x000E, ///< IO port 0 pin 14 + BSP_IO_PORT_00_PIN_15 = 0x000F, ///< IO port 0 pin 15 + + BSP_IO_PORT_01_PIN_00 = 0x0100, ///< IO port 1 pin 0 + BSP_IO_PORT_01_PIN_01 = 0x0101, ///< IO port 1 pin 1 + BSP_IO_PORT_01_PIN_02 = 0x0102, ///< IO port 1 pin 2 + BSP_IO_PORT_01_PIN_03 = 0x0103, ///< IO port 1 pin 3 + BSP_IO_PORT_01_PIN_04 = 0x0104, ///< IO port 1 pin 4 + BSP_IO_PORT_01_PIN_05 = 0x0105, ///< IO port 1 pin 5 + BSP_IO_PORT_01_PIN_06 = 0x0106, ///< IO port 1 pin 6 + BSP_IO_PORT_01_PIN_07 = 0x0107, ///< IO port 1 pin 7 + BSP_IO_PORT_01_PIN_08 = 0x0108, ///< IO port 1 pin 8 + BSP_IO_PORT_01_PIN_09 = 0x0109, ///< IO port 1 pin 9 + BSP_IO_PORT_01_PIN_10 = 0x010A, ///< IO port 1 pin 10 + BSP_IO_PORT_01_PIN_11 = 0x010B, ///< IO port 1 pin 11 + BSP_IO_PORT_01_PIN_12 = 0x010C, ///< IO port 1 pin 12 + BSP_IO_PORT_01_PIN_13 = 0x010D, ///< IO port 1 pin 13 + BSP_IO_PORT_01_PIN_14 = 0x010E, ///< IO port 1 pin 14 + BSP_IO_PORT_01_PIN_15 = 0x010F, ///< IO port 1 pin 15 + + BSP_IO_PORT_02_PIN_00 = 0x0200, ///< IO port 2 pin 0 + BSP_IO_PORT_02_PIN_01 = 0x0201, ///< IO port 2 pin 1 + BSP_IO_PORT_02_PIN_02 = 0x0202, ///< IO port 2 pin 2 + BSP_IO_PORT_02_PIN_03 = 0x0203, ///< IO port 2 pin 3 + BSP_IO_PORT_02_PIN_04 = 0x0204, ///< IO port 2 pin 4 + BSP_IO_PORT_02_PIN_05 = 0x0205, ///< IO port 2 pin 5 + BSP_IO_PORT_02_PIN_06 = 0x0206, ///< IO port 2 pin 6 + BSP_IO_PORT_02_PIN_07 = 0x0207, ///< IO port 2 pin 7 + BSP_IO_PORT_02_PIN_08 = 0x0208, ///< IO port 2 pin 8 + BSP_IO_PORT_02_PIN_09 = 0x0209, ///< IO port 2 pin 9 + BSP_IO_PORT_02_PIN_10 = 0x020A, ///< IO port 2 pin 10 + BSP_IO_PORT_02_PIN_11 = 0x020B, ///< IO port 2 pin 11 + BSP_IO_PORT_02_PIN_12 = 0x020C, ///< IO port 2 pin 12 + BSP_IO_PORT_02_PIN_13 = 0x020D, ///< IO port 2 pin 13 + BSP_IO_PORT_02_PIN_14 = 0x020E, ///< IO port 2 pin 14 + BSP_IO_PORT_02_PIN_15 = 0x020F, ///< IO port 2 pin 15 + + BSP_IO_PORT_03_PIN_00 = 0x0300, ///< IO port 3 pin 0 + BSP_IO_PORT_03_PIN_01 = 0x0301, ///< IO port 3 pin 1 + BSP_IO_PORT_03_PIN_02 = 0x0302, ///< IO port 3 pin 2 + BSP_IO_PORT_03_PIN_03 = 0x0303, ///< IO port 3 pin 3 + BSP_IO_PORT_03_PIN_04 = 0x0304, ///< IO port 3 pin 4 + BSP_IO_PORT_03_PIN_05 = 0x0305, ///< IO port 3 pin 5 + BSP_IO_PORT_03_PIN_06 = 0x0306, ///< IO port 3 pin 6 + BSP_IO_PORT_03_PIN_07 = 0x0307, ///< IO port 3 pin 7 + BSP_IO_PORT_03_PIN_08 = 0x0308, ///< IO port 3 pin 8 + BSP_IO_PORT_03_PIN_09 = 0x0309, ///< IO port 3 pin 9 + BSP_IO_PORT_03_PIN_10 = 0x030A, ///< IO port 3 pin 10 + BSP_IO_PORT_03_PIN_11 = 0x030B, ///< IO port 3 pin 11 + BSP_IO_PORT_03_PIN_12 = 0x030C, ///< IO port 3 pin 12 + BSP_IO_PORT_03_PIN_13 = 0x030D, ///< IO port 3 pin 13 + BSP_IO_PORT_03_PIN_14 = 0x030E, ///< IO port 3 pin 14 + BSP_IO_PORT_03_PIN_15 = 0x030F, ///< IO port 3 pin 15 + + BSP_IO_PORT_04_PIN_00 = 0x0400, ///< IO port 4 pin 0 + BSP_IO_PORT_04_PIN_01 = 0x0401, ///< IO port 4 pin 1 + BSP_IO_PORT_04_PIN_02 = 0x0402, ///< IO port 4 pin 2 + BSP_IO_PORT_04_PIN_03 = 0x0403, ///< IO port 4 pin 3 + BSP_IO_PORT_04_PIN_04 = 0x0404, ///< IO port 4 pin 4 + BSP_IO_PORT_04_PIN_05 = 0x0405, ///< IO port 4 pin 5 + BSP_IO_PORT_04_PIN_06 = 0x0406, ///< IO port 4 pin 6 + BSP_IO_PORT_04_PIN_07 = 0x0407, ///< IO port 4 pin 7 + BSP_IO_PORT_04_PIN_08 = 0x0408, ///< IO port 4 pin 8 + BSP_IO_PORT_04_PIN_09 = 0x0409, ///< IO port 4 pin 9 + BSP_IO_PORT_04_PIN_10 = 0x040A, ///< IO port 4 pin 10 + BSP_IO_PORT_04_PIN_11 = 0x040B, ///< IO port 4 pin 11 + BSP_IO_PORT_04_PIN_12 = 0x040C, ///< IO port 4 pin 12 + BSP_IO_PORT_04_PIN_13 = 0x040D, ///< IO port 4 pin 13 + BSP_IO_PORT_04_PIN_14 = 0x040E, ///< IO port 4 pin 14 + BSP_IO_PORT_04_PIN_15 = 0x040F, ///< IO port 4 pin 15 + + BSP_IO_PORT_05_PIN_00 = 0x0500, ///< IO port 5 pin 0 + BSP_IO_PORT_05_PIN_01 = 0x0501, ///< IO port 5 pin 1 + BSP_IO_PORT_05_PIN_02 = 0x0502, ///< IO port 5 pin 2 + BSP_IO_PORT_05_PIN_03 = 0x0503, ///< IO port 5 pin 3 + BSP_IO_PORT_05_PIN_04 = 0x0504, ///< IO port 5 pin 4 + BSP_IO_PORT_05_PIN_05 = 0x0505, ///< IO port 5 pin 5 + BSP_IO_PORT_05_PIN_06 = 0x0506, ///< IO port 5 pin 6 + BSP_IO_PORT_05_PIN_07 = 0x0507, ///< IO port 5 pin 7 + BSP_IO_PORT_05_PIN_08 = 0x0508, ///< IO port 5 pin 8 + BSP_IO_PORT_05_PIN_09 = 0x0509, ///< IO port 5 pin 9 + BSP_IO_PORT_05_PIN_10 = 0x050A, ///< IO port 5 pin 10 + BSP_IO_PORT_05_PIN_11 = 0x050B, ///< IO port 5 pin 11 + BSP_IO_PORT_05_PIN_12 = 0x050C, ///< IO port 5 pin 12 + BSP_IO_PORT_05_PIN_13 = 0x050D, ///< IO port 5 pin 13 + BSP_IO_PORT_05_PIN_14 = 0x050E, ///< IO port 5 pin 14 + BSP_IO_PORT_05_PIN_15 = 0x050F, ///< IO port 5 pin 15 + + BSP_IO_PORT_06_PIN_00 = 0x0600, ///< IO port 6 pin 0 + BSP_IO_PORT_06_PIN_01 = 0x0601, ///< IO port 6 pin 1 + BSP_IO_PORT_06_PIN_02 = 0x0602, ///< IO port 6 pin 2 + BSP_IO_PORT_06_PIN_03 = 0x0603, ///< IO port 6 pin 3 + BSP_IO_PORT_06_PIN_04 = 0x0604, ///< IO port 6 pin 4 + BSP_IO_PORT_06_PIN_05 = 0x0605, ///< IO port 6 pin 5 + BSP_IO_PORT_06_PIN_06 = 0x0606, ///< IO port 6 pin 6 + BSP_IO_PORT_06_PIN_07 = 0x0607, ///< IO port 6 pin 7 + BSP_IO_PORT_06_PIN_08 = 0x0608, ///< IO port 6 pin 8 + BSP_IO_PORT_06_PIN_09 = 0x0609, ///< IO port 6 pin 9 + BSP_IO_PORT_06_PIN_10 = 0x060A, ///< IO port 6 pin 10 + BSP_IO_PORT_06_PIN_11 = 0x060B, ///< IO port 6 pin 11 + BSP_IO_PORT_06_PIN_12 = 0x060C, ///< IO port 6 pin 12 + BSP_IO_PORT_06_PIN_13 = 0x060D, ///< IO port 6 pin 13 + BSP_IO_PORT_06_PIN_14 = 0x060E, ///< IO port 6 pin 14 + BSP_IO_PORT_06_PIN_15 = 0x060F, ///< IO port 6 pin 15 + + BSP_IO_PORT_07_PIN_00 = 0x0700, ///< IO port 7 pin 0 + BSP_IO_PORT_07_PIN_01 = 0x0701, ///< IO port 7 pin 1 + BSP_IO_PORT_07_PIN_02 = 0x0702, ///< IO port 7 pin 2 + BSP_IO_PORT_07_PIN_03 = 0x0703, ///< IO port 7 pin 3 + BSP_IO_PORT_07_PIN_04 = 0x0704, ///< IO port 7 pin 4 + BSP_IO_PORT_07_PIN_05 = 0x0705, ///< IO port 7 pin 5 + BSP_IO_PORT_07_PIN_06 = 0x0706, ///< IO port 7 pin 6 + BSP_IO_PORT_07_PIN_07 = 0x0707, ///< IO port 7 pin 7 + BSP_IO_PORT_07_PIN_08 = 0x0708, ///< IO port 7 pin 8 + BSP_IO_PORT_07_PIN_09 = 0x0709, ///< IO port 7 pin 9 + BSP_IO_PORT_07_PIN_10 = 0x070A, ///< IO port 7 pin 10 + BSP_IO_PORT_07_PIN_11 = 0x070B, ///< IO port 7 pin 11 + BSP_IO_PORT_07_PIN_12 = 0x070C, ///< IO port 7 pin 12 + BSP_IO_PORT_07_PIN_13 = 0x070D, ///< IO port 7 pin 13 + BSP_IO_PORT_07_PIN_14 = 0x070E, ///< IO port 7 pin 14 + BSP_IO_PORT_07_PIN_15 = 0x070F, ///< IO port 7 pin 15 + + BSP_IO_PORT_08_PIN_00 = 0x0800, ///< IO port 8 pin 0 + BSP_IO_PORT_08_PIN_01 = 0x0801, ///< IO port 8 pin 1 + BSP_IO_PORT_08_PIN_02 = 0x0802, ///< IO port 8 pin 2 + BSP_IO_PORT_08_PIN_03 = 0x0803, ///< IO port 8 pin 3 + BSP_IO_PORT_08_PIN_04 = 0x0804, ///< IO port 8 pin 4 + BSP_IO_PORT_08_PIN_05 = 0x0805, ///< IO port 8 pin 5 + BSP_IO_PORT_08_PIN_06 = 0x0806, ///< IO port 8 pin 6 + BSP_IO_PORT_08_PIN_07 = 0x0807, ///< IO port 8 pin 7 + BSP_IO_PORT_08_PIN_08 = 0x0808, ///< IO port 8 pin 8 + BSP_IO_PORT_08_PIN_09 = 0x0809, ///< IO port 8 pin 9 + BSP_IO_PORT_08_PIN_10 = 0x080A, ///< IO port 8 pin 10 + BSP_IO_PORT_08_PIN_11 = 0x080B, ///< IO port 8 pin 11 + BSP_IO_PORT_08_PIN_12 = 0x080C, ///< IO port 8 pin 12 + BSP_IO_PORT_08_PIN_13 = 0x080D, ///< IO port 8 pin 13 + BSP_IO_PORT_08_PIN_14 = 0x080E, ///< IO port 8 pin 14 + BSP_IO_PORT_08_PIN_15 = 0x080F, ///< IO port 8 pin 15 + + BSP_IO_PORT_09_PIN_00 = 0x0900, ///< IO port 9 pin 0 + BSP_IO_PORT_09_PIN_01 = 0x0901, ///< IO port 9 pin 1 + BSP_IO_PORT_09_PIN_02 = 0x0902, ///< IO port 9 pin 2 + BSP_IO_PORT_09_PIN_03 = 0x0903, ///< IO port 9 pin 3 + BSP_IO_PORT_09_PIN_04 = 0x0904, ///< IO port 9 pin 4 + BSP_IO_PORT_09_PIN_05 = 0x0905, ///< IO port 9 pin 5 + BSP_IO_PORT_09_PIN_06 = 0x0906, ///< IO port 9 pin 6 + BSP_IO_PORT_09_PIN_07 = 0x0907, ///< IO port 9 pin 7 + BSP_IO_PORT_09_PIN_08 = 0x0908, ///< IO port 9 pin 8 + BSP_IO_PORT_09_PIN_09 = 0x0909, ///< IO port 9 pin 9 + BSP_IO_PORT_09_PIN_10 = 0x090A, ///< IO port 9 pin 10 + BSP_IO_PORT_09_PIN_11 = 0x090B, ///< IO port 9 pin 11 + BSP_IO_PORT_09_PIN_12 = 0x090C, ///< IO port 9 pin 12 + BSP_IO_PORT_09_PIN_13 = 0x090D, ///< IO port 9 pin 13 + BSP_IO_PORT_09_PIN_14 = 0x090E, ///< IO port 9 pin 14 + BSP_IO_PORT_09_PIN_15 = 0x090F, ///< IO port 9 pin 15 + + BSP_IO_PORT_10_PIN_00 = 0x0A00, ///< IO port 10 pin 0 + BSP_IO_PORT_10_PIN_01 = 0x0A01, ///< IO port 10 pin 1 + BSP_IO_PORT_10_PIN_02 = 0x0A02, ///< IO port 10 pin 2 + BSP_IO_PORT_10_PIN_03 = 0x0A03, ///< IO port 10 pin 3 + BSP_IO_PORT_10_PIN_04 = 0x0A04, ///< IO port 10 pin 4 + BSP_IO_PORT_10_PIN_05 = 0x0A05, ///< IO port 10 pin 5 + BSP_IO_PORT_10_PIN_06 = 0x0A06, ///< IO port 10 pin 6 + BSP_IO_PORT_10_PIN_07 = 0x0A07, ///< IO port 10 pin 7 + BSP_IO_PORT_10_PIN_08 = 0x0A08, ///< IO port 10 pin 8 + BSP_IO_PORT_10_PIN_09 = 0x0A09, ///< IO port 10 pin 9 + BSP_IO_PORT_10_PIN_10 = 0x0A0A, ///< IO port 10 pin 10 + BSP_IO_PORT_10_PIN_11 = 0x0A0B, ///< IO port 10 pin 11 + BSP_IO_PORT_10_PIN_12 = 0x0A0C, ///< IO port 10 pin 12 + BSP_IO_PORT_10_PIN_13 = 0x0A0D, ///< IO port 10 pin 13 + BSP_IO_PORT_10_PIN_14 = 0x0A0E, ///< IO port 10 pin 14 + BSP_IO_PORT_10_PIN_15 = 0x0A0F, ///< IO port 10 pin 15 + + BSP_IO_PORT_11_PIN_00 = 0x0B00, ///< IO port 11 pin 0 + BSP_IO_PORT_11_PIN_01 = 0x0B01, ///< IO port 11 pin 1 + BSP_IO_PORT_11_PIN_02 = 0x0B02, ///< IO port 11 pin 2 + BSP_IO_PORT_11_PIN_03 = 0x0B03, ///< IO port 11 pin 3 + BSP_IO_PORT_11_PIN_04 = 0x0B04, ///< IO port 11 pin 4 + BSP_IO_PORT_11_PIN_05 = 0x0B05, ///< IO port 11 pin 5 + BSP_IO_PORT_11_PIN_06 = 0x0B06, ///< IO port 11 pin 6 + BSP_IO_PORT_11_PIN_07 = 0x0B07, ///< IO port 11 pin 7 + BSP_IO_PORT_11_PIN_08 = 0x0B08, ///< IO port 11 pin 8 + BSP_IO_PORT_11_PIN_09 = 0x0B09, ///< IO port 11 pin 9 + BSP_IO_PORT_11_PIN_10 = 0x0B0A, ///< IO port 11 pin 10 + BSP_IO_PORT_11_PIN_11 = 0x0B0B, ///< IO port 11 pin 11 + BSP_IO_PORT_11_PIN_12 = 0x0B0C, ///< IO port 11 pin 12 + BSP_IO_PORT_11_PIN_13 = 0x0B0D, ///< IO port 11 pin 13 + BSP_IO_PORT_11_PIN_14 = 0x0B0E, ///< IO port 11 pin 14 + BSP_IO_PORT_11_PIN_15 = 0x0B0F, ///< IO port 11 pin 15 + + BSP_IO_PORT_12_PIN_00 = 0x0C00, ///< IO port 12 pin 0 + BSP_IO_PORT_12_PIN_01 = 0x0C01, ///< IO port 12 pin 1 + BSP_IO_PORT_12_PIN_02 = 0x0C02, ///< IO port 12 pin 2 + BSP_IO_PORT_12_PIN_03 = 0x0C03, ///< IO port 12 pin 3 + BSP_IO_PORT_12_PIN_04 = 0x0C04, ///< IO port 12 pin 4 + BSP_IO_PORT_12_PIN_05 = 0x0C05, ///< IO port 12 pin 5 + BSP_IO_PORT_12_PIN_06 = 0x0C06, ///< IO port 12 pin 6 + BSP_IO_PORT_12_PIN_07 = 0x0C07, ///< IO port 12 pin 7 + BSP_IO_PORT_12_PIN_08 = 0x0C08, ///< IO port 12 pin 8 + BSP_IO_PORT_12_PIN_09 = 0x0C09, ///< IO port 12 pin 9 + BSP_IO_PORT_12_PIN_10 = 0x0C0A, ///< IO port 12 pin 10 + BSP_IO_PORT_12_PIN_11 = 0x0C0B, ///< IO port 12 pin 11 + BSP_IO_PORT_12_PIN_12 = 0x0C0C, ///< IO port 12 pin 12 + BSP_IO_PORT_12_PIN_13 = 0x0C0D, ///< IO port 12 pin 13 + BSP_IO_PORT_12_PIN_14 = 0x0C0E, ///< IO port 12 pin 14 + BSP_IO_PORT_12_PIN_15 = 0x0C0F, ///< IO port 12 pin 15 + + BSP_IO_PORT_13_PIN_00 = 0x0D00, ///< IO port 13 pin 0 + BSP_IO_PORT_13_PIN_01 = 0x0D01, ///< IO port 13 pin 1 + BSP_IO_PORT_13_PIN_02 = 0x0D02, ///< IO port 13 pin 2 + BSP_IO_PORT_13_PIN_03 = 0x0D03, ///< IO port 13 pin 3 + BSP_IO_PORT_13_PIN_04 = 0x0D04, ///< IO port 13 pin 4 + BSP_IO_PORT_13_PIN_05 = 0x0D05, ///< IO port 13 pin 5 + BSP_IO_PORT_13_PIN_06 = 0x0D06, ///< IO port 13 pin 6 + BSP_IO_PORT_13_PIN_07 = 0x0D07, ///< IO port 13 pin 7 + BSP_IO_PORT_13_PIN_08 = 0x0D08, ///< IO port 13 pin 8 + BSP_IO_PORT_13_PIN_09 = 0x0D09, ///< IO port 13 pin 9 + BSP_IO_PORT_13_PIN_10 = 0x0D0A, ///< IO port 13 pin 10 + BSP_IO_PORT_13_PIN_11 = 0x0D0B, ///< IO port 13 pin 11 + BSP_IO_PORT_13_PIN_12 = 0x0D0C, ///< IO port 13 pin 12 + BSP_IO_PORT_13_PIN_13 = 0x0D0D, ///< IO port 13 pin 13 + BSP_IO_PORT_13_PIN_14 = 0x0D0E, ///< IO port 13 pin 14 + BSP_IO_PORT_13_PIN_15 = 0x0D0F, ///< IO port 13 pin 15 + + BSP_IO_PORT_14_PIN_00 = 0x0E00, ///< IO port 14 pin 0 + BSP_IO_PORT_14_PIN_01 = 0x0E01, ///< IO port 14 pin 1 + BSP_IO_PORT_14_PIN_02 = 0x0E02, ///< IO port 14 pin 2 + BSP_IO_PORT_14_PIN_03 = 0x0E03, ///< IO port 14 pin 3 + BSP_IO_PORT_14_PIN_04 = 0x0E04, ///< IO port 14 pin 4 + BSP_IO_PORT_14_PIN_05 = 0x0E05, ///< IO port 14 pin 5 + BSP_IO_PORT_14_PIN_06 = 0x0E06, ///< IO port 14 pin 6 + BSP_IO_PORT_14_PIN_07 = 0x0E07, ///< IO port 14 pin 7 + BSP_IO_PORT_14_PIN_08 = 0x0E08, ///< IO port 14 pin 8 + BSP_IO_PORT_14_PIN_09 = 0x0E09, ///< IO port 14 pin 9 + BSP_IO_PORT_14_PIN_10 = 0x0E0A, ///< IO port 14 pin 10 + BSP_IO_PORT_14_PIN_11 = 0x0E0B, ///< IO port 14 pin 11 + BSP_IO_PORT_14_PIN_12 = 0x0E0C, ///< IO port 14 pin 12 + BSP_IO_PORT_14_PIN_13 = 0x0E0D, ///< IO port 14 pin 13 + BSP_IO_PORT_14_PIN_14 = 0x0E0E, ///< IO port 14 pin 14 + BSP_IO_PORT_14_PIN_15 = 0x0E0F, ///< IO port 14 pin 15 + BSP_IO_PORT_FF_PIN_FF = 0xFFFF, ///< Invalid IO port +} bsp_io_port_pin_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ +extern volatile uint32_t g_protect_pfswe_counter; + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Read the current input level of the pin. + * + * @param[in] pin The pin + * + * @retval Current input level + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_BSP_PinRead (bsp_io_port_pin_t pin) +{ + /* Read pin level. */ + return R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS_b.PIDR; +} + +/*******************************************************************************************************************//** + * Set a pin to output and set the output level to the level provided. If PFS protection is enabled, disable PFS + * protection using R_BSP_PinAccessEnable() before calling this function. + * + * @param[in] pin The pin + * @param[in] level The level + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinWrite (bsp_io_port_pin_t pin, bsp_io_level_t level) +{ + /* Clear PMR, ASEL, ISEL and PODR bits. */ + uint32_t pfs_bits = R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS; + pfs_bits &= BSP_IO_PRV_PIN_WRITE_MASK; + + /* Set output level and pin direction to output. */ + uint32_t lvl = ((uint32_t) level | pfs_bits); +#if (3U == BSP_FEATURE_IOPORT_VERSION) + R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = (uint16_t) (BSP_IO_PFS_PDR_OUTPUT | lvl); +#else + R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = (BSP_IO_PFS_PDR_OUTPUT | lvl); +#endif +} + +/*******************************************************************************************************************//** + * Configure a pin. If PFS protection is enabled, disable PFS protection using R_BSP_PinAccessEnable() before calling + * this function. + * + * @param[in] pin The pin + * @param[in] cfg Configuration for the pin (PmnPFS register setting) + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinCfg (bsp_io_port_pin_t pin, uint32_t cfg) +{ + /* Configure a pin. */ +#if (3U == BSP_FEATURE_IOPORT_VERSION) + R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = (uint16_t) cfg; +#else + R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = cfg; +#endif +} + +/*******************************************************************************************************************//** + * Enable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur + * via multiple threads or an ISR re-entering this code. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinAccessEnable (void) +{ +#if BSP_CFG_PFS_PROTECT + + /** Get the current state of interrupts */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /** If this is first entry then allow writing of PFS. */ + if (0 == g_protect_pfswe_counter) + { + #if BSP_TZ_SECURE_BUILD || (BSP_FEATURE_TZ_VERSION == 2 && FSP_PRIV_TZ_USE_SECURE_REGS) + R_PMISC->PWPRS = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled + R_PMISC->PWPRS = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled + #else + R_PMISC->PWPR = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled + R_PMISC->PWPR = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled + #endif + } + + /** Increment the protect counter */ + g_protect_pfswe_counter++; + + /** Restore the interrupt state */ + FSP_CRITICAL_SECTION_EXIT; +#endif +} + +/*******************************************************************************************************************//** + * Disable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur via + * multiple threads or an ISR re-entering this code. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinAccessDisable (void) +{ +#if BSP_CFG_PFS_PROTECT + + /** Get the current state of interrupts */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /** Is it safe to disable PFS register? */ + if (0 != g_protect_pfswe_counter) + { + /* Decrement the protect counter */ + g_protect_pfswe_counter--; + } + + /** Is it safe to disable writing of PFS? */ + if (0 == g_protect_pfswe_counter) + { + #if BSP_TZ_SECURE_BUILD || (BSP_FEATURE_TZ_VERSION == 2 && FSP_PRIV_TZ_USE_SECURE_REGS) + R_PMISC->PWPRS = 0; ///< Clear PFSWE bit - writing to PFSWE bit enabled + R_PMISC->PWPRS = 1U << BSP_IO_PWPR_B0WI_OFFSET; ///< Set BOWI bit - writing to PFS register enabled + #else + R_PMISC->PWPR = 0; ///< Clear PFSWE bit - writing to PFS register disabled + R_PMISC->PWPR = 1U << BSP_IO_PWPR_B0WI_OFFSET; ///< Set BOWI bit - writing to PFSWE bit disabled + #endif + } + + /** Restore the interrupt state */ + FSP_CRITICAL_SECTION_EXIT; +#endif +} + +/** @} (end addtogroup BSP_IO) */ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_ipc.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_ipc.c new file mode 100644 index 00000000000..5e8a7da2b7e --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_ipc.c @@ -0,0 +1,148 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +#ifdef R_IPC + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* IPC0NMI is Core1 -> Core0, IPC1NMI is Core0 -> Core1 */ + #if (BSP_CFG_CPU_CORE == 0) + #define BSP_IPC_PRV_NMI_REG_SET IPC1NMI + #define BSP_IPC_PRV_NMI_REG_CLEAR IPC0NMI + #else + #define BSP_IPC_PRV_NMI_REG_SET IPC0NMI + #define BSP_IPC_PRV_NMI_REG_CLEAR IPC1NMI + #endif + + #define BSP_IPC_PRV_SEMAPHORE_CLEAR 1 + #define BSP_IPC_PRV_VALID_SEMAPHORE_MASK (0xFFFFU) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +static void ipc_nmi_internal_callback(bsp_grp_irq_t irq); + +static bsp_ipc_nmi_cb_t gp_nmi_callback = NULL; + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Attempt to take IPC semaphore + * + * @param[in] p_semaphore_handle Semaphore handle corresponding to IPCSEMn to use. + * + * @retval FSP_SUCCESS Semaphore successfully taken + * @retval FSP_ERR_IN_USE Semaphore already taken + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT Specified semaphore doesn't exist on device + **********************************************************************************************************************/ +fsp_err_t R_BSP_IpcSemaphoreTake (bsp_ipc_semaphore_handle_t const * const p_semaphore_handle) +{ + #if BSP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_semaphore_handle); + FSP_ERROR_RETURN(BSP_IPC_PRV_VALID_SEMAPHORE_MASK & (1 << p_semaphore_handle->semaphore_num), + FSP_ERR_IP_CHANNEL_NOT_PRESENT); + #endif + + FSP_ERROR_RETURN(!R_IPC->IPCSEM[p_semaphore_handle->semaphore_num], FSP_ERR_IN_USE); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Give/clear the IPC semaphore + * + * @param[in] p_semaphore_handle Semaphore handle corresponding to IPCSEMn to use. + * + * @retval FSP_SUCCESS Semaphore successfully given + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT Specified semaphore doesn't exist on device + **********************************************************************************************************************/ +fsp_err_t R_BSP_IpcSemaphoreGive (bsp_ipc_semaphore_handle_t const * const p_semaphore_handle) +{ + #if BSP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_semaphore_handle); + FSP_ERROR_RETURN(BSP_IPC_PRV_VALID_SEMAPHORE_MASK & (1 << p_semaphore_handle->semaphore_num), + FSP_ERR_IP_CHANNEL_NOT_PRESENT); + #endif + + R_IPC->IPCSEM[p_semaphore_handle->semaphore_num] = BSP_IPC_PRV_SEMAPHORE_CLEAR; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Enable NMI for current core + * + * @param[in] p_callback Pointer to callback to use for NMI. + * + * @retval FSP_SUCCESS NMI request set + **********************************************************************************************************************/ +fsp_err_t R_BSP_IpcNmiEnable (bsp_ipc_nmi_cb_t p_callback) +{ + #if BSP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_callback); + #endif + + gp_nmi_callback = p_callback; + + /* Setup NMI callback */ + R_BSP_GroupIrqWrite(BSP_GRP_IRQ_IPC, ipc_nmi_internal_callback); + + /* Set IPCEN bit to enable NMI. NMIER bits cannot be cleared after reset, so no need to read-modify-write. */ + R_ICU->NMIER = R_ICU_NMIER_IPCEN_Msk; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Set NMI request for the opposing core + * + * @retval FSP_SUCCESS NMI request set + **********************************************************************************************************************/ +fsp_err_t R_BSP_IpcNmiRequestSet (void) +{ + R_IPC->BSP_IPC_PRV_NMI_REG_SET.SET = 1; + + return FSP_SUCCESS; +} + +/** @} (end addtogroup BSP_MCU) */ + +static void ipc_nmi_internal_callback (bsp_grp_irq_t irq) +{ + if (BSP_GRP_IRQ_IPC == irq) + { + /* Clear NMI request */ + R_IPC->BSP_IPC_PRV_NMI_REG_CLEAR.CLR = 1; + + if (NULL != gp_nmi_callback) + { + /* Call user callback */ + gp_nmi_callback(); + } + } +} + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_ipc.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_ipc.h new file mode 100644 index 00000000000..f243dfbe20f --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_ipc.h @@ -0,0 +1,60 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/** @} (end addtogroup BSP_MCU) */ + +#ifndef BSP_IPC_H +#define BSP_IPC_H + +#ifdef R_IPC + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Semaphore handle for IPC semaphores. */ +typedef struct st_bsp_ipc_semaphore_handle +{ + uint8_t semaphore_num; ///< Semaphore number, controls which IPCSEMn register is used. +} bsp_ipc_semaphore_handle_t; + +/** IPC NMI callback type. */ +typedef void (* bsp_ipc_nmi_cb_t)(void); + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +fsp_err_t R_BSP_IpcSemaphoreTake(bsp_ipc_semaphore_handle_t const * const p_semaphore_handle); +fsp_err_t R_BSP_IpcSemaphoreGive(bsp_ipc_semaphore_handle_t const * const p_semaphore_handle); +fsp_err_t R_BSP_IpcNmiRequestSet(void); +fsp_err_t R_BSP_IpcNmiEnable(bsp_ipc_nmi_cb_t p_callback); + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_irq.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_irq.c new file mode 100644 index 00000000000..eb752391656 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_irq.c @@ -0,0 +1,310 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/** ELC event definitions. */ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_IRQ_UINT32_MAX (0xFFFFFFFFU) +#define BSP_PRV_BITS_PER_WORD (32) + +#if (BSP_CFG_CPU_CORE == 1) + #define BSP_EVENT_NUM_TO_INTSELR(x) (x >> 5) // Convert event number to INTSELR register number + #define BSP_EVENT_NUM_TO_INTSELR_MASK(x) (1 << (x % 32)) // Convert event number to INTSELR bit mask +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/* This table is used to store the context in the ISR. */ +void * gp_renesas_isr_context[BSP_ICU_VECTOR_NUM_ENTRIES]; + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +#if (BSP_CFG_CPU_CORE == 1) +BSP_CMSE_NONSECURE_ENTRY void bsp_prv_intselr_set(bsp_interrupt_event_t interrupt_event_link_select); + +#endif + +const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_NUM_ENTRIES] BSP_WEAK_REFERENCE = +{ + (bsp_interrupt_event_t) 0 +}; + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ +#if 0 == BSP_CFG_INLINE_IRQ_FUNCTIONS + #if BSP_FEATURE_ICU_HAS_IELSR + +/*******************************************************************************************************************//** + * Clear the interrupt status flag (IR) for a given interrupt. When an interrupt is triggered the IR bit + * is set. If it is not cleared in the ISR then the interrupt will trigger again immediately. + * + * @param[in] irq Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +void R_BSP_IrqStatusClear (IRQn_Type irq) +{ + /* Clear the IR bit in the selected IELSR register. */ + R_ICU->IELSR_b[irq].IR = 0U; + + /* Read back the IELSR register to ensure that the IR bit is cleared. + * See "Operations During an Interrupt" in the ICU section of the relevant hardware manual. */ + FSP_REGISTER_READ(R_ICU->IELSR[irq]); +} + + #endif + +/*******************************************************************************************************************//** + * Clear the interrupt status flag (IR) for a given interrupt and clear the NVIC pending interrupt. + * + * @param[in] irq Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +void R_BSP_IrqClearPending (IRQn_Type irq) +{ + #if BSP_FEATURE_ICU_HAS_IELSR + + /* Clear the IR bit in the selected IELSR register. */ + R_BSP_IrqStatusClear(irq); + + /* Flush memory transactions to ensure that the IR bit is cleared before clearing the pending bit in the NVIC. */ + __DMB(); + #endif + + /* The following statement is used in place of NVIC_ClearPendingIRQ to avoid including a branch for system + * exceptions every time an interrupt is cleared in the NVIC. */ + uint32_t _irq = (uint32_t) irq; + NVIC->ICPR[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); +} + +/*******************************************************************************************************************//** + * Sets the interrupt priority and context. + * + * @param[in] irq The IRQ to configure. + * @param[in] priority NVIC priority of the interrupt + * @param[in] p_context The interrupt context is a pointer to data required in the ISR. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +void R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void * p_context) +{ + /* The following statement is used in place of NVIC_SetPriority to avoid including a branch for system exceptions + * every time a priority is configured in the NVIC. */ + #if (4U == __CORTEX_M) + NVIC->IPR[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX); + #elif (33 == __CORTEX_M) + NVIC->IPR[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX); + #elif (23 == __CORTEX_M) + NVIC->IPR[_IP_IDX(irq)] = ((uint32_t) (NVIC->IPR[_IP_IDX(irq)] & ~((uint32_t) UINT8_MAX << _BIT_SHIFT(irq))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX) << _BIT_SHIFT(irq))); + #else + NVIC_SetPriority(irq, priority); + #endif + + /* Store the context. The context is recovered in the ISR. */ + R_FSP_IsrContextSet(irq, p_context); +} + +/*******************************************************************************************************************//** + * Enable the IRQ in the NVIC (Without clearing the pending bit). + * + * @param[in] irq The IRQ to enable. Note that the enums listed for IRQn_Type are only those for the Cortex + * Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +void R_BSP_IrqEnableNoClear (IRQn_Type const irq) +{ + /* The following statement is used in place of NVIC_EnableIRQ to avoid including a branch for system exceptions + * every time an interrupt is enabled in the NVIC. */ + uint32_t _irq = (uint32_t) irq; + + __COMPILER_BARRIER(); + NVIC->ISER[(_irq >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); + __COMPILER_BARRIER(); +} + +/*******************************************************************************************************************//** + * Clears pending interrupts in both ICU and NVIC, then enables the interrupt. + * + * @param[in] irq Interrupt for which to clear the IR bit and enable in the NVIC. Note that the enums listed + * for IRQn_Type are only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +void R_BSP_IrqEnable (IRQn_Type const irq) +{ + /* Clear pending interrupts in the ICU and NVIC. */ + R_BSP_IrqClearPending(irq); + + /* Enable the IRQ in the NVIC. */ + R_BSP_IrqEnableNoClear(irq); +} + +/*******************************************************************************************************************//** + * Disables interrupts in the NVIC. + * + * @param[in] irq The IRQ to disable in the NVIC. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +void R_BSP_IrqDisable (IRQn_Type const irq) +{ + /* The following statements is used in place of NVIC_DisableIRQ to avoid including a branch for system + * exceptions every time an interrupt is cleared in the NVIC. */ + uint32_t _irq = (uint32_t) irq; + NVIC->ICER[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); + + __DSB(); + __ISB(); +} + +/*******************************************************************************************************************//** + * Sets the interrupt priority and context, clears pending interrupts, then enables the interrupt. + * + * @param[in] irq Interrupt number. + * @param[in] priority NVIC priority of the interrupt + * @param[in] p_context The interrupt context is a pointer to data required in the ISR. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +void R_BSP_IrqCfgEnable (IRQn_Type const irq, uint32_t priority, void * p_context) +{ + R_BSP_IrqCfg(irq, priority, p_context); + R_BSP_IrqEnable(irq); +} + +#endif // 0 == BSP_CFG_INLINE_IRQ_FUNCTIONS + +/** @} (end addtogroup BSP_MCU) */ + +#if (BSP_CFG_CPU_CORE == 1) && !BSP_TZ_NONSECURE_BUILD + +/*******************************************************************************************************************//** + * INTSELR is a S-TYPE-6 register but it needs to be set based on interrupts that are used in each project. + * By making this into a NSC, INTSELR can be set from NS. + **********************************************************************************************************************/ +BSP_CMSE_NONSECURE_ENTRY void bsp_prv_intselr_set (bsp_interrupt_event_t interrupt_event_link_select) +{ + uint32_t inteslr_num_max = sizeof(R_ICU->INTSELR) / sizeof(R_ICU->INTSELR[0]); + + /* Calculate which INTSELRn to use */ + uint32_t intselr_num = BSP_EVENT_NUM_TO_INTSELR((uint32_t) interrupt_event_link_select); + + /* Only set if a valid INTSELRn */ + if (intselr_num < inteslr_num_max) + { + /* Set INTSELR for selected events. */ + uint32_t intselr = R_ICU->INTSELR[intselr_num]; + + intselr |= BSP_EVENT_NUM_TO_INTSELR_MASK((uint32_t) interrupt_event_link_select); + R_ICU->INTSELR[intselr_num] = intselr; + } +} + +#endif + +/*******************************************************************************************************************//** + * Using the vector table information section that has been built by the linker and placed into ROM in the + * .vector_info. section, this function will initialize the ICU so that configured ELC events will trigger interrupts + * in the NVIC. + * + **********************************************************************************************************************/ +void bsp_irq_cfg (void) +{ +#if FSP_PRIV_TZ_USE_SECURE_REGS + #if (BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_SECURE_BUILD == 0) + + /* On MCUs with this implementation of TrustZone, IRQ security attribution is set to secure by default. + * This means that flat projects do not need to set security attribution to secure. */ + #else + + /* Unprotect security registers. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); + + #if !BSP_TZ_SECURE_BUILD + + /* Set the DMAC channels to secure access. */ + #ifdef BSP_TZ_CFG_ICUSARC + R_CPSCU->ICUSARC = ~R_CPSCU_ICUSARC_SADMACn_Msk; + #endif + #endif + + /* Place all vectors in non-secure state unless they are used in the secure project. */ + uint32_t interrupt_security_state[BSP_ICU_VECTOR_MAX_ENTRIES / BSP_PRV_BITS_PER_WORD]; + memset(&interrupt_security_state, UINT8_MAX, sizeof(interrupt_security_state)); + + for (uint32_t i = 0U; i < BSP_ICU_VECTOR_NUM_ENTRIES; i++) + { + if (0U != g_interrupt_event_link_select[i]) + { + /* This is a secure vector. Clear the associated bit. */ + uint32_t index = i / BSP_PRV_BITS_PER_WORD; + uint32_t bit = i % BSP_PRV_BITS_PER_WORD; + interrupt_security_state[index] &= ~(1U << bit); + } + } + + /* The Secure Attribute managed within the ARM CPU NVIC must match the security attribution of IELSEn + * (Refer "ICUSARI : Interrupt Controller Unit Security Attribution Register I" description in the ICU section of the relevant hardware manual). */ + #if (BSP_CFG_CPU_CORE == 1) + uint32_t volatile * p_icusarg = &R_CPSCU->ICUSARJ; + #else + uint32_t volatile * p_icusarg = &R_CPSCU->ICUSARG; + #endif + for (uint32_t i = 0U; i < BSP_ICU_VECTOR_MAX_ENTRIES / BSP_PRV_BITS_PER_WORD; i++) + { + p_icusarg[i] = interrupt_security_state[i]; + NVIC->ITNS[i] = interrupt_security_state[i]; + } + + /* Protect security registers. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); + #endif +#endif +#if BSP_FEATURE_ICU_HAS_IELSR + + /* Calculate the number of IELSR registers that need to be initialized. */ + uint32_t ielsr_count = BSP_ICU_VECTOR_MAX_ENTRIES - BSP_FEATURE_ICU_FIXED_IELSR_COUNT; + if (ielsr_count > BSP_ICU_VECTOR_NUM_ENTRIES) + { + ielsr_count = BSP_ICU_VECTOR_NUM_ENTRIES; + } + + for (uint32_t i = 0U; i < ielsr_count; i++) + { + if (0U != g_interrupt_event_link_select[i]) + { + R_ICU->IELSR[i] = (uint32_t) g_interrupt_event_link_select[i]; + + #if (BSP_CFG_CPU_CORE == 1) + bsp_prv_intselr_set(g_interrupt_event_link_select[i]); + #endif + } + } +#endif +} diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_irq.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_irq.h new file mode 100644 index 00000000000..ec4a5b9678a --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_irq.h @@ -0,0 +1,238 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/** @} (end addtogroup BSP_MCU) */ + +#ifndef BSP_IRQ_H +#define BSP_IRQ_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_ICU_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES - BSP_CORTEX_VECTOR_TABLE_ENTRIES) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ +extern void * gp_renesas_isr_context[BSP_ICU_VECTOR_NUM_ENTRIES]; + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Sets the ISR context associated with the requested IRQ. + * + * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this + * function. + * @param[in] p_context ISR context for IRQ. + **********************************************************************************************************************/ +__STATIC_INLINE void R_FSP_IsrContextSet (IRQn_Type const irq, void * p_context) +{ + /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of + * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */ + gp_renesas_isr_context[irq] = p_context; +} + +/*******************************************************************************************************************//** + * @brief Finds the ISR context associated with the requested IRQ. + * + * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this + * function. + * @return ISR context for IRQ. + **********************************************************************************************************************/ +__STATIC_INLINE void * R_FSP_IsrContextGet (IRQn_Type const irq) +{ + /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of + * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */ + return gp_renesas_isr_context[irq]; +} + +#if BSP_CFG_INLINE_IRQ_FUNCTIONS + + #if BSP_FEATURE_ICU_HAS_IELSR + +/*******************************************************************************************************************//** + * Clear the interrupt status flag (IR) for a given interrupt. When an interrupt is triggered the IR bit + * is set. If it is not cleared in the ISR then the interrupt will trigger again immediately. + * + * @param[in] irq Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqStatusClear (IRQn_Type irq) +{ + /* Clear the IR bit in the selected IELSR register. */ + R_ICU->IELSR_b[irq].IR = 0U; + + /* Read back the IELSR register to ensure that the IR bit is cleared. + * See "Operations During an Interrupt" in the ICU section of the relevant hardware manual. */ + FSP_REGISTER_READ(R_ICU->IELSR[irq]); +} + + #endif + +/*******************************************************************************************************************//** + * Clear the interrupt status flag (IR) for a given interrupt and clear the NVIC pending interrupt. + * + * @param[in] irq Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqClearPending (IRQn_Type irq) +{ + #if BSP_FEATURE_ICU_HAS_IELSR + + /* Clear the IR bit in the selected IELSR register. */ + R_BSP_IrqStatusClear(irq); + + /* Flush memory transactions to ensure that the IR bit is cleared before clearing the pending bit in the NVIC. */ + __DMB(); + #endif + + /* The following statement is used in place of NVIC_ClearPendingIRQ to avoid including a branch for system + * exceptions every time an interrupt is cleared in the NVIC. */ + uint32_t _irq = (uint32_t) irq; + NVIC->ICPR[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); +} + +/*******************************************************************************************************************//** + * Sets the interrupt priority and context. + * + * @param[in] irq The IRQ to configure. + * @param[in] priority NVIC priority of the interrupt + * @param[in] p_context The interrupt context is a pointer to data required in the ISR. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void * p_context) +{ + /* The following statement is used in place of NVIC_SetPriority to avoid including a branch for system exceptions + * every time a priority is configured in the NVIC. */ + #if (4U == __CORTEX_M) + NVIC->IPR[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX); + #elif (33 == __CORTEX_M) + NVIC->IPR[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX); + #elif (23 == __CORTEX_M) + NVIC->IPR[_IP_IDX(irq)] = ((uint32_t) (NVIC->IPR[_IP_IDX(irq)] & ~((uint32_t) UINT8_MAX << _BIT_SHIFT(irq))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX) << _BIT_SHIFT(irq))); + #else + NVIC_SetPriority(irq, priority); + #endif + + /* Store the context. The context is recovered in the ISR. */ + R_FSP_IsrContextSet(irq, p_context); +} + +/*******************************************************************************************************************//** + * Enable the IRQ in the NVIC (Without clearing the pending bit). + * + * @param[in] irq The IRQ to enable. Note that the enums listed for IRQn_Type are only those for the Cortex + * Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqEnableNoClear (IRQn_Type const irq) +{ + /* The following statement is used in place of NVIC_EnableIRQ to avoid including a branch for system exceptions + * every time an interrupt is enabled in the NVIC. */ + uint32_t _irq = (uint32_t) irq; + + __COMPILER_BARRIER(); + NVIC->ISER[(_irq >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); + __COMPILER_BARRIER(); +} + +/*******************************************************************************************************************//** + * Clears pending interrupts in both ICU and NVIC, then enables the interrupt. + * + * @param[in] irq Interrupt for which to clear the IR bit and enable in the NVIC. Note that the enums listed + * for IRQn_Type are only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqEnable (IRQn_Type const irq) +{ + /* Clear pending interrupts in the ICU and NVIC. */ + R_BSP_IrqClearPending(irq); + + /* Enable the IRQ in the NVIC. */ + R_BSP_IrqEnableNoClear(irq); +} + +/*******************************************************************************************************************//** + * Disables interrupts in the NVIC. + * + * @param[in] irq The IRQ to disable in the NVIC. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqDisable (IRQn_Type const irq) +{ + /* The following statements is used in place of NVIC_DisableIRQ to avoid including a branch for system + * exceptions every time an interrupt is cleared in the NVIC. */ + uint32_t _irq = (uint32_t) irq; + NVIC->ICER[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); + + __DSB(); + __ISB(); +} + +/*******************************************************************************************************************//** + * Sets the interrupt priority and context, clears pending interrupts, then enables the interrupt. + * + * @param[in] irq Interrupt number. + * @param[in] priority NVIC priority of the interrupt + * @param[in] p_context The interrupt context is a pointer to data required in the ISR. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqCfgEnable (IRQn_Type const irq, uint32_t priority, void * p_context) +{ + R_BSP_IrqCfg(irq, priority, p_context); + R_BSP_IrqEnable(irq); +} + +#else + #if BSP_FEATURE_ICU_HAS_IELSR +void R_BSP_IrqStatusClear(IRQn_Type irq); + + #endif +void R_BSP_IrqClearPending(IRQn_Type irq); +void R_BSP_IrqCfg(IRQn_Type const irq, uint32_t priority, void * p_context); +void R_BSP_IrqEnableNoClear(IRQn_Type const irq); +void R_BSP_IrqEnable(IRQn_Type const irq); +void R_BSP_IrqDisable(IRQn_Type const irq); +void R_BSP_IrqCfgEnable(IRQn_Type const irq, uint32_t priority, void * p_context); + +#endif + +/*******************************************************************************************************************//** + * @internal + * @addtogroup BSP_MCU_PRV Internal BSP Documentation + * @ingroup RENESAS_INTERNAL + * @{ + **********************************************************************************************************************/ + +/* Public functions defined in bsp.h */ +void bsp_irq_cfg(void); // Used internally by BSP + +/** @} (end addtogroup BSP_MCU_PRV) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_macl.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_macl.c new file mode 100644 index 00000000000..045e84ba721 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_macl.c @@ -0,0 +1,2050 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_macl.h" + +#if BSP_FEATURE_MACL_SUPPORTED + #if __has_include("arm_math_types.h") + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + + #ifndef INDEX_MASK + +/* This used to be defined in CMSIS DSP. But they have added an undef of the macro in utils.h and therefore it is no longer + * in scope for the uses of this file. */ + #define INDEX_MASK 0x0000003F + #endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static inline void r_macl_wait_operation(void); + +static void r_macl_mul_q31(const q31_t * p_src_a, const q31_t * p_src_b, q31_t * p_dst, uint32_t block_size); + +static void r_macl_scale_q31(const q31_t * p_src, q31_t scale_fract, int8_t shift, q31_t * p_dst, uint32_t block_size); + +static void r_macl_mat_mul_q31(const arm_matrix_instance_q31 * p_src_a, + const arm_matrix_instance_q31 * p_src_b, + arm_matrix_instance_q31 * p_dst); + +static void r_macl_mat_mul_acc_q31(const q31_t * p_in_a, + const q31_t * p_in_b, + q31_t * p_out, + uint16_t num_cols_a, + uint16_t num_cols_b); + +static void r_macl_mat_scale_q31(const arm_matrix_instance_q31 * p_src, + q31_t scale_fract, + int32_t shift, + arm_matrix_instance_q31 * p_dst); +static void r_macl_conv_q31(const q31_t * p_src_a, const q31_t * p_src_b, q31_t * p_dst, uint8_t block_size); + +static uint32_t r_macl_recip_q31(q31_t in, q31_t * dst, const q31_t * p_recip_table); + +/*******************************************************************************************************************//** + * @addtogroup BSP_MACL + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Perform multiplication via MACL module. + * + * @param[in] p_src_a Pointer which point to data A. + * @param[in] p_src_b Pointer which point to data B. + * @param[out] p_dst Pointer to buffer which will hold the calculation result. + * @param[in] block_size Numbers of elements to be calculated. + **********************************************************************************************************************/ +void R_BSP_MaclMulQ31 (const q31_t * p_src_a, const q31_t * p_src_b, q31_t * p_dst, uint32_t block_size) +{ + /* Enable Fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_ENABLE; + + r_macl_mul_q31(p_src_a, p_src_b, p_dst, block_size); + + /* Disable Fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; +} + +/*******************************************************************************************************************//** + * Perform scaling a vector by multiplying scalar via MACL module. + * + * @param[in] p_src Pointer which point to a vector. + * @param[in] scale_fract Pointer to the scalar number. + * @param[in] shift Number of bits to shift the result by + * @param[out] p_dst Pointer to buffer which will hold the calculation result. + * @param[in] block_size Numbers of elements to be calculated. + **********************************************************************************************************************/ +void R_BSP_MaclScaleQ31 (const q31_t * p_src, q31_t scale_fract, int8_t shift, q31_t * p_dst, uint32_t block_size) +{ + /* Disable Fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + + r_macl_scale_q31(p_src, scale_fract, shift, p_dst, block_size); +} + +/*******************************************************************************************************************//** + * Perform Q31 matrix multiplication via MACL module. + * + * @param[in] p_src_a Points to the first input matrix structure A. + * @param[in] p_src_b Points to the second input matrix structure B. + * @param[out] p_dst Points to the buffer which hold output matrix structure. + **********************************************************************************************************************/ +void R_BSP_MaclMatMulQ31 (const arm_matrix_instance_q31 * p_src_a, + const arm_matrix_instance_q31 * p_src_b, + arm_matrix_instance_q31 * p_dst) +{ + /* Disable Fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + + r_macl_mat_mul_q31(p_src_a, p_src_b, p_dst); +} + +/*******************************************************************************************************************//** + * Perform Q31 matrix and vector multiplication via MACL module. + * + * @param[in] p_src_mat Points to the first input matrix structure. + * @param[in] p_vec Points to the input vector. + * @param[out] p_dst Points to the buffer which hold the output vector. + **********************************************************************************************************************/ +void R_BSP_MaclMatVecMulQ31 (const arm_matrix_instance_q31 * p_src_mat, const q31_t * p_vec, q31_t * p_dst) +{ + uint16_t num_rows = p_src_mat->numRows; // Number of rows of input matrix + uint16_t num_cols = p_src_mat->numCols; // Number of columns of input matrix + const q31_t * p_src = p_src_mat->pData; // Input data matrix + const q31_t * p_in_vec = p_vec; // Input data vector + q31_t * p_out = p_dst; // Output data vector + uint16_t row = num_rows; // Loop counters + uint16_t num_cols_vec = 1; + + /* Disable Fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + + /* Row loop of the matrix */ + do + { + /* Perform the multiply-accumulates a row in p_src with the input vector */ + r_macl_mat_mul_acc_q31(p_src, p_in_vec, p_out, num_cols, num_cols_vec); + + p_out++; + row--; + p_src += num_cols; + } while (row > 0U); +} + +/*******************************************************************************************************************//** + * Perform scaling a matrix by multiplying scalar via MACL module. + * + * @param[in] p_src Points to the vector. + * @param[in] scale_fract Points to the scalar number. + * @param[in] shift Number of bits to shift the result by + * @param[out] p_dst Points to the buffer which will hold the calculation result. + **********************************************************************************************************************/ +void R_BSP_MaclMatScaleQ31 (const arm_matrix_instance_q31 * p_src, + q31_t scale_fract, + int32_t shift, + arm_matrix_instance_q31 * p_dst) +{ + /* Disable Fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + + r_macl_mat_scale_q31(p_src, scale_fract, shift, p_dst); +} + +/*******************************************************************************************************************//** + * Perform the biquad cascade direct form I filter in Q31 via MACL module + * + * @param[in] p_biquad_csd_df1_inst Point to instance of the Q31 Biquad cascade structure + * @param[in] p_src Point to input sample to be filtered. + * @param[out] p_dst Point to buffer for storing filtered sample. + * @param[in] block_size Numbers of input sample. + **********************************************************************************************************************/ +void R_BSP_MaclBiquadCsdDf1Q31 (const arm_biquad_casd_df1_inst_q31 * p_biquad_csd_df1_inst, + const q31_t * p_src, + q31_t * p_dst, + uint32_t block_size) +{ + const q31_t * p_coeffs = p_biquad_csd_df1_inst->pCoeffs; // Coefficient pointer + q31_t * p_state = p_biquad_csd_df1_inst->pState; // State pointer + const q31_t * p_src_local = p_src; // Local pointer for p_src + q31_t * p_dst_local = p_dst; // Local pointer for p_dst + uint32_t stage = p_biquad_csd_df1_inst->numStages; // Loop counter + uint32_t sample; // Loop counter + uint32_t state_update_element; // Update state buffer + uint32_t src_ctrl; // Control the value of source + uint32_t sample_ctrl; // Control the value of sample + uint32_t coeffs_ctrl; // Control the value of coefficient + uint32_t shift = ((uint32_t) p_biquad_csd_df1_inst->postShift + 1U); // Shift to be applied to the output + uint32_t r_shift = BSP_MACL_32_BIT - shift; // Shift to be applied to the output + volatile uint64_t * p_result_in_q62 = (uint64_t *) &(R_MACL->MULR0.MULRL); // Assign to address of MULR0 + + state_update_element = 0U; + coeffs_ctrl = 0U; + + /* Disable Fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + + while (stage > 0U) + { + sample = block_size; + src_ctrl = 0U; + sample_ctrl = 0U; + + /** + * y[n] = b0 * x[n] + b1 * x[n - 1] + b2 * x[n -2] + a1 * y[n - 1] + a2 * y[n - 2] + */ + while (sample > 0U) + { + /* Clean result reg */ + R_MACL->MULRCLR = 0U; + + /* Calculate b0.x[n] */ + R_MACL->MAC32S = (uint32_t) p_src_local[src_ctrl]; + R_MACL->MULB0 = (uint32_t) p_coeffs[coeffs_ctrl]; + r_macl_wait_operation(); + + /* Calculate for b1.x[n-1] and a1.y[n-1] */ + if (sample_ctrl >= 1U) + { + /* b1 * x[n - 1] */ + R_MACL->MAC32S = (uint32_t) p_state[state_update_element]; + R_MACL->MULB0 = (uint32_t) p_coeffs[coeffs_ctrl + 1U]; + r_macl_wait_operation(); + + /* a1 * y[n - 1] */ + R_MACL->MAC32S = (uint32_t) p_state[state_update_element + 2U]; + R_MACL->MULB0 = (uint32_t) p_coeffs[coeffs_ctrl + 3U]; + r_macl_wait_operation(); + } + + /* Calculate for b2 * x[n - 2] and a2 * y[n - 2]*/ + if (sample_ctrl >= 2U) + { + /* b2 * x[n - 2] */ + R_MACL->MAC32S = (uint32_t) p_state[state_update_element + 1U]; + R_MACL->MULB0 = (uint32_t) p_coeffs[coeffs_ctrl + 2U]; + r_macl_wait_operation(); + + /* a2 * y[n - 2] */ + R_MACL->MAC32S = (uint32_t) p_state[state_update_element + 3U]; + R_MACL->MULB0 = (uint32_t) p_coeffs[coeffs_ctrl + 4U]; + r_macl_wait_operation(); + } + + /* Update state buffer */ + p_state[state_update_element + 1U] = p_state[state_update_element]; // x[n - 2] = x[n - 1] + p_state[state_update_element] = p_src_local[src_ctrl]; // x[n - 1] = x[n] + + /* Shift and write result to buffer */ + *p_dst_local = (q31_t) (*p_result_in_q62 >> r_shift); + + /* Update state buffer */ + p_state[state_update_element + 3U] = p_state[state_update_element + 2U]; // y[n - 2] = y[n - 1] + p_state[state_update_element + 2U] = *p_dst_local; // Update value of y[n-1] + + sample--; + src_ctrl++; + sample_ctrl++; + + /* Check before update addr of p_dst to prevent segmentation fault */ + if (sample != 0U) + { + p_dst_local++; + } + } + + p_src_local = p_dst; + p_dst_local = p_dst; + state_update_element += 4U; + coeffs_ctrl += 5U; + stage--; + } +} + +/*******************************************************************************************************************//** + * Perform the convolution in Q31 via MACL module. + * + * @param[in] p_src_a Point to input source A + * @param[in] src_a_len Length of source A + * @param[in] p_src_b Point to input source B + * @param[in] src_b_len Length of source B + * @param[out] p_dst Point to result buffer + **********************************************************************************************************************/ +void R_BSP_MaclConvQ31 (const q31_t * p_src_a, + uint32_t src_a_len, + const q31_t * p_src_b, + uint32_t src_b_len, + q31_t * p_dst) +{ + uint8_t src_a_ctrl; // Control the value of source A + uint8_t src_b_ctrl; // Control the value of source B + uint8_t element_ctrl; // Control the value of element + uint32_t src_a_len_local; // Local length of source A + uint32_t src_b_len_local; // Local length of source B + const q31_t * p_data_a; // Input source A pointer + const q31_t * p_data_b; // Input source B pointer + q31_t * p_dst_local = p_dst; // Output pointer + + src_a_ctrl = 1U; + src_b_ctrl = 1U; + element_ctrl = 1U; + + /* Enable Fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_ENABLE; + + /* The algorithm implementation is based on the lengths of the inputs. src B is always made to slide across src A. + * Therefore, length of B is always considered as shorter or equal to length of A */ + if (src_a_len >= src_b_len) + { + p_data_a = p_src_a; + p_data_b = p_src_b; + src_a_len_local = src_a_len; + src_b_len_local = src_b_len; + } + else + { + p_data_a = p_src_b; + p_data_b = p_src_a; + src_a_len_local = src_b_len; + src_b_len_local = src_a_len; + } + + /* Stage 1 */ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + while (src_b_ctrl < src_b_len_local) + { + /* Perform multiply-accumulate via MACL for convolution operation */ + r_macl_conv_q31(p_data_a, p_data_b, p_dst_local, element_ctrl); + + p_data_b++; + p_dst_local++; + element_ctrl++; + src_b_ctrl++; + src_a_ctrl++; + } + + /* Stage 2 */ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + while (src_a_ctrl <= src_a_len_local) + { + /* Perform multiply-accumulate via MACL for convolution operation */ + r_macl_conv_q31(p_data_a, p_data_b, p_dst_local, element_ctrl); + + p_data_a++; + p_dst_local++; + src_a_ctrl++; + } + + element_ctrl--; + + /* Stage 3 */ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + while (element_ctrl > 0U) + { + /* Perform multiply-accumulate via MACL for convolution operation */ + r_macl_conv_q31(p_data_a, p_data_b, p_dst_local, element_ctrl); + + p_data_a++; + element_ctrl--; + p_dst_local++; + } + + /* Disable Fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; +} + +/*******************************************************************************************************************//** + * Perform the partial convolution in Q31 via MACL module. + * + * @param[in] p_src_a Point to input source A + * @param[in] src_a_len Length of source A + * @param[in] p_src_b Point to input source B + * @param[in] src_b_len Length of source B + * @param[out] p_dst Point to result buffer + * @param[in] first_idx The first output sample to start with + * @param[in] num_points The number of output points to be computed + * + * @retval ARM_MATH_SUCCESS Operation successful + * @retval ARM_MATH_ARGUMENT_ERROR Requested compute points is bigger than result size + **********************************************************************************************************************/ +arm_status R_BSP_MaclConvPartialQ31 (const q31_t * p_src_a, + uint32_t src_a_len, + const q31_t * p_src_b, + uint32_t src_b_len, + q31_t * p_dst, + uint32_t first_idx, + uint32_t num_points) +{ + /* Status of Partial convolution */ + arm_status status; + + /* Enable Fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_ENABLE; + + /* Check for range of output samples to be calculated */ + if ((first_idx + num_points) > (src_a_len + (src_b_len - 1U))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* Loop to calculate convolution for output length number of values */ + for (uint32_t i = first_idx; i <= (first_idx + num_points - 1U); i++) + { + /* Clear the Result registers. */ + R_MACL->MULRCLR = 0U; + + /* Loop to perform MAC operations according to convolution equation */ + for (uint32_t j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < src_b_len) && (j < src_a_len)) + { + /* z[i] += x[i-j] * y[j] */ + R_MACL->MAC32S = (uint32_t) (p_src_a[j]); + R_MACL->MULB0 = (uint32_t) (p_src_b[i - j]); + r_macl_wait_operation(); + } + } + + /* Store the output in the destination buffer */ + p_dst[i] = (q31_t) R_MACL->MULR0.MULRH; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Disable Fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + + return status; +} + +/*******************************************************************************************************************//** + * Perform the Q31 FIR Decimate Q31 via MACL module. + * + * @param[in] p_fir_decimate_ins_q31 Pointer which point to an instance of the Q31 FIR Decimate structure. + * @param[in] p_src Pointer which point to the input vector. + * @param[out] p_dst Pointer to buffer which hold the output vector. + * @param[in] block_size Numbers of samples to be calculated. + **********************************************************************************************************************/ +void R_BSP_MaclFirDecimateQ31 (const arm_fir_decimate_instance_q31 * p_fir_decimate_ins_q31, + const q31_t * p_src, + q31_t * p_dst, + uint32_t block_size) +{ + q31_t * p_state = p_fir_decimate_ins_q31->pState; // State pointer + const q31_t * p_coeffs = p_fir_decimate_ins_q31->pCoeffs; // Coefficient pointer + q31_t * p_state_cur; // Points to the current sample of the state + q31_t * p_state_buffer; // Temporary pointer for state buffer + const q31_t * p_coeff_buffer; // Temporary pointer for coefficient buffer + uint32_t num_taps = p_fir_decimate_ins_q31->numTaps; // Number of filter coefficients in the filter + uint32_t num_of_decimate_factor; // Number of decimation factor + uint32_t tap_cnt; // Loop counters + uint32_t blk_cnt; // Loop counters + + /* Enable Fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_ENABLE; + + /* p_fir_decimate_ins_q31->pState buffer contains previous frame (num_taps - 1) samples */ + /* p_state_cur points to the location where the new input data should be written */ + p_state_cur = p_fir_decimate_ins_q31->pState + (num_taps - 1U); + + /* Initialize blk_cnt with number of samples */ + blk_cnt = block_size / p_fir_decimate_ins_q31->M; + + while (blk_cnt > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + num_of_decimate_factor = p_fir_decimate_ins_q31->M; + + do + { + *p_state_cur++ = *p_src++; + --num_of_decimate_factor; + } while (num_of_decimate_factor > 0); + + /* Set accumulator to zero */ + R_MACL->MULRCLR = BSP_MACL_CLEAR_MULR_REG; + + /* Initialize state pointer */ + p_state_buffer = p_state; + + /* Initialize coeff pointer */ + p_coeff_buffer = p_coeffs; + + /* Initialize tap_cnt with number of taps */ + tap_cnt = num_taps; + + while (tap_cnt > 0U) + { + /* Perform the multiply-accumulate */ + /* Write state variable to register A */ + R_MACL->MAC32S = (uint32_t) *p_state_buffer++; + + /* Write coeficients to register B*/ + R_MACL->MULB0 = (uint32_t) *p_coeff_buffer++; + r_macl_wait_operation(); + + /* Decrement loop counter */ + tap_cnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + p_state = p_state + p_fir_decimate_ins_q31->M; + + /* The result is in the accumulator, store in the destination buffer. */ + *p_dst++ = (q31_t) (R_MACL->MULR0.MULRH); + + /* Decrement loop counter */ + blk_cnt--; + } + + /* Processing is complete. + * Now copy the last num_taps - 1 samples to the satrt of the state buffer. + * This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + p_state_cur = p_fir_decimate_ins_q31->pState; + + /* Initialize tap_cnt with number of taps */ + tap_cnt = (num_taps - 1U); + + /* Copy data */ + while (tap_cnt > 0U) + { + *p_state_cur++ = *p_state++; + + /* Decrement loop counter */ + tap_cnt--; + } + + /* Disable Fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; +} + +/*******************************************************************************************************************//** + * Perform the Q31 FIR interpolator via MACL module. + * + * @param[in] p_fir_interpolate_ins_q31 Pointer which point to an instance of the Q31 FIR interpolator structure. + * @param[in] p_src Pointer which point to the input vector. + * @param[out] p_dst Pointer to buffer which hold the output vector. + * @param[in] block_size Numbers of samples to be calculated. + **********************************************************************************************************************/ +void R_BSP_MaclFirInterpolateQ31 (const arm_fir_interpolate_instance_q31 * p_fir_interpolate_ins_q31, + const q31_t * p_src, + q31_t * p_dst, + uint32_t block_size) +{ + /* Disable Fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + + q31_t * p_state = p_fir_interpolate_ins_q31->pState; // State pointer + const q31_t * p_coeffs = p_fir_interpolate_ins_q31->pCoeffs; // Coefficient pointer + q31_t * p_state_cur; // Points to the current sample of the state + q31_t * p_state_tmp; // Temporary pointer for state buffer + const q31_t * p_coef_tmp; // Temporary pointer for coefficient buffer + uint32_t coef_idx; // Index of coefficient + uint32_t factor_cnt; // Loop counters + uint32_t blk_cnt; // Loop counters + uint32_t tap_cnt; // Loop counters + uint32_t phase_len = p_fir_interpolate_ins_q31->phaseLength; // Length of each polyphase filter component + volatile uint64_t * p_result_r0 = (uint64_t *) &(R_MACL->MULR0.MULRL); // Assign to address of MULR0 + + /* p_state_cur points to the location where the new input data should be written */ + p_state_cur = p_fir_interpolate_ins_q31->pState + (phase_len - 1U); + + /* Initialize blk_cnt with number of samples */ + blk_cnt = block_size; + + while (blk_cnt > 0U) + { + /* Copy new input sample into the state buffer */ + *p_state_cur++ = *p_src++; + + /* Address modifier index of coefficient buffer */ + coef_idx = 1U; + + /* Loop over the Interpolation factor. */ + factor_cnt = p_fir_interpolate_ins_q31->L; + + while (factor_cnt > 0U) + { + /* Clear registers */ + R_MACL->MULRCLR = BSP_MACL_CLEAR_MULR_REG; + + /* Initialize state pointer */ + p_state_tmp = p_state; + + /* Initialize coefficient pointer */ + p_coef_tmp = p_coeffs + (p_fir_interpolate_ins_q31->L - coef_idx); + + /* Initialize tap_cnt with number of samples */ + tap_cnt = phase_len; + + while (tap_cnt > 0U) + { + R_MACL->MAC32S = (uint32_t) (*p_state_tmp); + R_MACL->MULB0 = (uint32_t) (*p_coef_tmp); + + /* Wait for the calculation. */ + r_macl_wait_operation(); + + tap_cnt--; + p_state_tmp++; + p_coef_tmp += p_fir_interpolate_ins_q31->L; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *p_dst++ = (q31_t) (*p_result_r0 >> BSP_MACL_SHIFT_31_BIT); + + /* Increment the address modifier index of coefficient buffer */ + coef_idx++; + + /* Decrement the loop counter */ + factor_cnt--; + } + + /* Advance the state pointer by 1 to process the next group of interpolation factor number samples */ + p_state = p_state + 1; + + /* Decrement the loop counter */ + blk_cnt--; + } + + /* Points to the start of the state buffer */ + p_state_cur = p_fir_interpolate_ins_q31->pState; + + /* Initialize tap_cnt with number of samples */ + tap_cnt = (phase_len - 1U); + + /* Copy data */ + while (tap_cnt > 0U) + { + *p_state_cur++ = *p_state++; + + /* Decrement loop counter */ + tap_cnt--; + } +} + +/*******************************************************************************************************************//** + * Perform the Q31 Correlate via MACL module. + * + * @param[in] p_src_a Point to the first input sequence. + * @param[in] src_a_len Length of the first input sequence. + * @param[in] p_src_b Point to the second input sequence. + * @param[in] src_b_len Length of the second input sequence. + * @param[out] p_dst Points to the location where the output result is written. + * Length 2 * max(src_a_len, src_b_len) - 1. + **********************************************************************************************************************/ +void R_BSP_MaclCorrelateQ31 (const q31_t * p_src_a, + uint32_t src_a_len, + const q31_t * p_src_b, + uint32_t src_b_len, + q31_t * p_dst) +{ + const q31_t * p_in1; // InputA pointer + const q31_t * p_in2; // InputB pointer + q31_t * p_out = p_dst; // Output pointer + const q31_t * p_in_a_buf; // Intermediate inputA pointer + const q31_t * p_in_b_buf; // Intermediate inputB pointer + const q31_t * p_src1; // Intermediate pointers + uint32_t block_size1; // Loop counters + uint32_t block_size2; // Loop counters + uint32_t block_size3; // Loop counters + uint32_t len_diff_cnt; // Number of output samples + uint32_t cal_cnt; // Loop counters + uint32_t count; // Loop counters + int32_t inc = 1; // Destination address modifier + + /* Enable Fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_ENABLE; + + /* If src_a_len > src_b_len, + * (src_a_len - src_b_len) zeroes has to included in the starting of the output buffer */ + + /* If src_a_len < src_b_len, + * (src_b_len - src_a_len) zeroes has to included in the ending of the output buffer */ + if (src_a_len >= src_b_len) + { + /* Initialization of inputA pointer */ + p_in1 = p_src_a; + + /* Initialization of inputB pointer */ + p_in2 = p_src_b; + + /* When src_a_len > src_b_len, zero padding is done to srcB + * to make their lengths equal. + * Instead, (src_a_len - src_b_len) + * number of output samples are made zero */ + len_diff_cnt = src_a_len - src_b_len; + + /* Updating the pointer position to non zero value */ + p_out += len_diff_cnt; + } + else + { + /* Initialization of inputA pointer */ + p_in1 = p_src_b; + + /* Initialization of inputB pointer */ + p_in2 = p_src_a; + + /* src_b_len is always considered as shorter or equal to src_a_len */ + len_diff_cnt = src_b_len; + src_b_len = src_a_len; + src_a_len = len_diff_cnt; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + p_out = p_dst + ((src_a_len + src_b_len) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, src_b_len number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. + * The algorithm is implemented in three stages. + * The loop counters of each stage is initiated here. */ + block_size1 = src_b_len - 1U; + block_size2 = src_a_len - (src_b_len - 1U); + block_size3 = block_size1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[src_b_len - 1] + * sum = x[0] * y[src_b_len - 2] + x[1] * y[src_b_len - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[src_b_len - 1] * y[src_b_len - 1] + *//* In this stage the MAC operations are increased by 1 for every iteration. + * The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + p_in_a_buf = p_in1; + + /* Working pointer of inputB */ + p_src1 = p_in2 + (src_b_len - 1U); + p_in_b_buf = p_src1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (block_size1 > 0U) + { + /* Accumulator is made zero for every iteration */ + R_MACL->MULRCLR = BSP_MACL_CLEAR_MULR_REG; + + /* Initialize cal_cnt with number of samples */ + cal_cnt = count; + + while (cal_cnt > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[src_b_len - 1] */ + R_MACL->MAC32S = (uint32_t) *p_in_a_buf++; + R_MACL->MULB0 = (uint32_t) *p_in_b_buf++; + r_macl_wait_operation(); + + /* Decrement loop counter */ + cal_cnt--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *p_out = (q31_t) (R_MACL->MULR0.MULRH); + + /* Destination pointer is updated according to the address modifier, inc */ + p_out += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + p_in_b_buf = p_src1 - count; + p_in_a_buf = p_in1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + block_size1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[src_b_len-1] * y[src_b_len-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[src_b_len] * y[src_b_len-1] + * .... + * sum = x[src_a_len-src_b_len-2] * y[0] + x[src_a_len-src_b_len-1] * y[1] +...+ x[src_a_len-1] * y[src_b_len-1] + *//* Working pointer of inputA */ + p_in_a_buf = p_in1; + + /* Working pointer of inputB */ + p_in_b_buf = p_in2; + + /* count is index by which the pointer p_in1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on src_b_len as in this stage src_b_len number of MACS are performed. */ + + while (block_size2 > 0U) + { + /* Accumulator is made zero for every iteration */ + R_MACL->MULRCLR = BSP_MACL_CLEAR_MULR_REG; + + /* Initialize cal_cnt with number of samples */ + cal_cnt = src_b_len; + + while (cal_cnt > 0U) + { + /* Perform the multiply-accumulate */ + R_MACL->MAC32S = (uint32_t) *p_in_a_buf++; + R_MACL->MULB0 = (uint32_t) *p_in_b_buf++; + r_macl_wait_operation(); + + /* Decrement the loop counter */ + cal_cnt--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *p_out = (q31_t) (R_MACL->MULR0.MULRH); + + /* Destination pointer is updated according to the address modifier, inc */ + p_out += inc; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + p_in_a_buf = p_in1 + count; + p_in_b_buf = p_in2; + + /* Decrement loop counter */ + block_size2--; + } + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[src_a_len-src_b_len+1] * y[0] + x[src_a_len-src_b_len+2] * y[1] +...+ x[src_a_len-1] * y[src_b_len-1] + * sum += x[src_a_len-src_b_len+2] * y[0] + x[src_a_len-src_b_len+3] * y[1] +...+ x[src_a_len-1] * y[src_b_len-1] + * .... + * sum += x[src_a_len-2] * y[0] + x[src_a_len-1] * y[1] + * sum += x[src_a_len-1] * y[0] + *//* In this stage the MAC operations are decreased by 1 for every iteration. + * The count variable holds the number of MAC operations performed */ + count = src_b_len - 1U; + + /* Working pointer of inputA */ + p_src1 = p_in1 + (src_a_len - (src_b_len - 1U)); + p_in_a_buf = p_src1; + + /* Working pointer of inputB */ + p_in_b_buf = p_in2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (block_size3 > 0U) + { + /* Accumulator is made zero for every iteration */ + R_MACL->MULRCLR = BSP_MACL_CLEAR_MULR_REG; + + /* Initialize cal_cnt with number of samples */ + cal_cnt = count; + + while (cal_cnt > 0U) + { + /* Perform the multiply-accumulate */ + R_MACL->MAC32S = (uint32_t) *p_in_a_buf++; + R_MACL->MULB0 = (uint32_t) *p_in_b_buf++; + r_macl_wait_operation(); + + /* Decrement loop counter */ + cal_cnt--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *p_out = (q31_t) (R_MACL->MULR0.MULRH); + + /* Destination pointer is updated according to the address modifier, inc */ + p_out += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + p_in_a_buf = ++p_src1; + p_in_b_buf = p_in2; + + /* Decrement MAC count */ + count--; + + /* Decrement loop counter */ + block_size3--; + } + + /* Disable fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; +} + +/*******************************************************************************************************************//** + * Perform the Q31 FIR Sparse filter via MACL module. + * + * @note The number of p_fir_sparse_ins_q31->numTaps must be greater than or equal to 2 + * + * @param[in] p_fir_sparse_ins_q31 points to an instance of the Q31 sparse FIR structure + * @param[in] p_src points to the block of input data + * @param[out] p_dst points to the block of output data + * @param[in] p_scratch_in points to a temporary buffer of size blockSize + * @param[in] block_size number of input samples to process + **********************************************************************************************************************/ +void R_BSP_MaclFirSparseQ31 (arm_fir_sparse_instance_q31 * p_fir_sparse_ins_q31, + const q31_t * p_src, + q31_t * p_dst, + q31_t * p_scratch_in, + uint32_t block_size) +{ + q31_t * p_state = p_fir_sparse_ins_q31->pState; + const q31_t * p_coeffs = p_fir_sparse_ins_q31->pCoeffs; + q31_t * p_scratch_tmp; + q31_t * p_state_tmp = p_state; + q31_t * p_scratch_in_tmp = p_scratch_in; + q31_t * p_out; + int32_t * p_tap_delay = p_fir_sparse_ins_q31->pTapDelay; + uint32_t delay_size = p_fir_sparse_ins_q31->maxDelay + block_size; + uint16_t num_taps = p_fir_sparse_ins_q31->numTaps; + int32_t read_index; + uint32_t tap_cnt; + uint32_t blk_cnt; + q31_t coeff = *p_coeffs++; + q31_t in; + + /* Disable fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + + /* block_size of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer */ + arm_circularWrite_f32((int32_t *) p_state_tmp, (int32_t) delay_size, &p_fir_sparse_ins_q31->stateIndex, 1, + (int32_t *) p_src, 1, block_size); + + /* Read Index, from where the state buffer should be read, is calculated. */ + read_index = (int32_t) (p_fir_sparse_ins_q31->stateIndex - block_size) - *p_tap_delay++; + + /* Wraparound of read_index */ + if (read_index < 0) + { + read_index += (int32_t) delay_size; + } + + /* Working pointer for state buffer is updated */ + p_state_tmp = p_state; + + /* block_size samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) p_state_tmp, (int32_t) delay_size, &read_index, 1, (int32_t *) p_scratch_in_tmp, + (int32_t *) p_scratch_in_tmp, (int32_t) block_size, 1, block_size); + + /* Working pointer for the scratch buffer of state values */ + p_scratch_tmp = p_scratch_in_tmp; + + /* Working pointer for scratch buffer of output values */ + p_out = p_dst; + + /* Initialize blk_cnt with number of samples */ + blk_cnt = block_size; + + while (blk_cnt > 0U) + { + /* Perform Multiplication and store in destination buffer */ + R_MACL->MUL32S = (uint32_t) *p_scratch_tmp++; + R_MACL->MULB0 = (uint32_t) coeff; + r_macl_wait_operation(); + *p_out++ = (q31_t) R_MACL->MULR0.MULRH; + + /* Decrement loop counter */ + blk_cnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *p_coeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + read_index = (int32_t) (p_fir_sparse_ins_q31->stateIndex - block_size) - *p_tap_delay++; + + /* Wraparound of read_index */ + if (read_index < 0) + { + read_index += (int32_t) delay_size; + } + + /* Loop over the number of taps. */ + tap_cnt = (uint32_t) num_taps - 2U; + + while (tap_cnt > 0U) + { + /* Working pointer for state buffer is updated */ + p_state_tmp = p_state; + + /* block_size samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) p_state_tmp, + (int32_t) delay_size, + &read_index, + 1, + (int32_t *) p_scratch_in_tmp, + (int32_t *) p_scratch_in_tmp, + (int32_t) block_size, + 1, + block_size); + + /* Working pointer for the scratch buffer of state values */ + p_scratch_tmp = p_scratch_in_tmp; + + /* Working pointer for scratch buffer of output values */ + p_out = p_dst; + + /* Initialize blk_cnt with number of samples */ + blk_cnt = block_size; + + while (blk_cnt > 0U) + { + /* Perform Multiply-Accumulate */ + /* Initialize out value*/ + R_MACL->MULR0.MULRH = (uint32_t) *p_out; + R_MACL->MULR0.MULRL = 0x0; + + /* Assign p_scratch_tmp value to register*/ + R_MACL->MAC32S = (uint32_t) *p_scratch_tmp++; + + /* Assign coeff value to register. */ + R_MACL->MULB0 = (uint32_t) coeff; + r_macl_wait_operation(); + + /* Read the result in Q31*/ + *p_out++ = (q31_t) R_MACL->MULR0.MULRH; + + /* Decrement loop counter */ + blk_cnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *p_coeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + read_index = (int32_t) (p_fir_sparse_ins_q31->stateIndex - block_size) - *p_tap_delay++; + + /* Wraparound of read_index */ + if (read_index < 0) + { + read_index += (int32_t) delay_size; + } + + /* Decrement tap loop counter */ + tap_cnt--; + } + + /* Compute last tap without the final read of p_tap_delay */ + + /* Working pointer for state buffer is updated */ + p_state_tmp = p_state; + + /* block_size samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) p_state_tmp, (int32_t) delay_size, &read_index, 1, (int32_t *) p_scratch_in_tmp, + (int32_t *) p_scratch_in_tmp, (int32_t) block_size, 1, block_size); + + /* Working pointer for the scratch buffer of state values */ + p_scratch_tmp = p_scratch_in_tmp; + + /* Working pointer for scratch buffer of output values */ + p_out = p_dst; + + /* Initialize blk_cnt with number of samples */ + blk_cnt = block_size; + + while (blk_cnt > 0U) + { + /* Perform Multiply-Accumulate */ + /* Initialize out value*/ + R_MACL->MULR0.MULRH = (uint32_t) *p_out; + R_MACL->MULR0.MULRL = 0x0; + + /* Assign p_scratch_tmp value to register*/ + R_MACL->MAC32S = (uint32_t) *p_scratch_tmp++; + + /* Assign coeff value to register. */ + R_MACL->MULB0 = (uint32_t) coeff; + r_macl_wait_operation(); + + /* Read the result in Q31*/ + *p_out++ = (q31_t) R_MACL->MULR0.MULRH; + + /* Decrement loop counter */ + blk_cnt--; + } + + /* Working output pointer is updated */ + p_out = p_dst; + + /* Output is converted into 1.31 format. */ + /* Initialize blk_cnt with number of samples */ + blk_cnt = block_size; + + while (blk_cnt > 0U) + { + in = *p_out << BSP_MACL_SHIFT_1_BIT; + *p_out++ = in; + + /* Decrement loop counter */ + blk_cnt--; + } +} + +/*******************************************************************************************************************//** + * Perform the Q31 normalized LMS filter via MACL module. + * @param[in] p_lms_norm_ins_q31 points to an instance of the Q31 normalized LMS filter structure + * @param[in] p_src points to the block of input data + * @param[in] p_ref points to the block of reference data + * @param[out] p_out points to the block of output data + * @param[out] p_err points to the block of error data + * @param[in] block_size number of samples to process + **********************************************************************************************************************/ +void R_BSP_MaclLmsNormQ31 (arm_lms_norm_instance_q31 * p_lms_norm_ins_q31, + const q31_t * p_src, + q31_t * p_ref, + q31_t * p_out, + q31_t * p_err, + uint32_t block_size) +{ + q31_t * p_state = p_lms_norm_ins_q31->pState; // State pointer + q31_t * p_coeffs = p_lms_norm_ins_q31->pCoeffs; // Coefficient pointer + q31_t * p_state_curnt; // Points to the current sample of the state + q31_t * p_state_buf; // Temporary pointers for state + q31_t * p_coeffs_buf; // Coefficient buffers + q31_t mu = p_lms_norm_ins_q31->mu; // Adaptive factor + uint32_t num_taps = p_lms_norm_ins_q31->numTaps; // Number of filter coefficients in the filter + uint32_t tap_cnt; // Loop counters + uint32_t blk_cnt; // Loop counters + q31_t acc; // Accumulator + q63_t energy; // Energy of the input + q31_t err_data; // Error data sample + q31_t weight_factor; // Weight factor and state + q31_t data_in; + q31_t x0; // Temporary variable to hold input sample + q31_t error_x_mu; // Temporary variable to store error + q31_t one_by_energy; // Temporary variables to store mu product and reciprocal of energy + q31_t post_shift; // Post shift to be applied to weight after reciprocal calculation + q31_t acc_l; // Low accumulator + q31_t acc_h; // High accumulator + uint32_t u_shift = ((uint32_t) p_lms_norm_ins_q31->postShift + 1U); + uint32_t l_shift = BSP_MACL_32_BIT - u_shift; // Shift to be applied to the output + q63_t result_temp; // Temporary variable to read result register + volatile uint64_t * p_result_r4 = (uint64_t *) &(R_MACL->MULR4.MULRL); // Assign to address of MULR4 + uint32_t tmp_check; // Check overflow/underflow value + q63_t mul_tmp = 0; + energy = p_lms_norm_ins_q31->energy; // Frame energy + x0 = p_lms_norm_ins_q31->x0; // Input sample + + /* p_lms_norm_ins_q31->pState points to buffer which contains previous frame (num_taps - 1) samples */ + /* p_state_curnt points to the location where the new input data should be written */ + p_state_curnt = &(p_lms_norm_ins_q31->pState[(num_taps - 1U)]); + + /* Initialise loop count */ + blk_cnt = block_size; + + /* Clear the Result registers. */ + R_MACL->MULRCLR = BSP_MACL_CLEAR_MULR_REG; + + /* Disable fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + + while (blk_cnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *p_state_curnt++ = *p_src; + + /* Initialize p_state pointer */ + p_state_buf = p_state; + + /* Initialize coefficient pointer */ + p_coeffs_buf = p_coeffs; + + /* Read the sample from input buffer */ + data_in = *p_src++; + + /* Update the energy calculation */ + R_MACL->MUL32S = (uint32_t) x0; + R_MACL->MULB1 = (uint32_t) x0; + r_macl_wait_operation(); + mul_tmp = (q63_t) R_MACL->MULR1.MULRH << BSP_MACL_SHIFT_32_BIT; + mul_tmp |= R_MACL->MULR1.MULRL; + energy = (energy << BSP_MACL_SHIFT_32_BIT) - (mul_tmp << 1); + R_MACL->MUL32S = (uint32_t) data_in; + R_MACL->MULB1 = (uint32_t) data_in; + r_macl_wait_operation(); + mul_tmp = (q63_t) R_MACL->MULR1.MULRH << BSP_MACL_SHIFT_32_BIT; + mul_tmp |= R_MACL->MULR1.MULRL; + + energy = (energy + (mul_tmp << 1)) >> BSP_MACL_SHIFT_32_BIT; + + /* Set the accumulator to zero */ + R_MACL->MULR0.MULRH = BSP_MACL_CLEAR_MULR_REG; + R_MACL->MULR0.MULRL = BSP_MACL_CLEAR_MULR_REG; + + /* Initialize tap_cnt with number of samples */ + tap_cnt = num_taps; + + while (tap_cnt > 0U) + { + /* Perform the multiply-accumulate */ + R_MACL->MAC32S = (uint32_t) *p_state_buf++; + R_MACL->MULB0 = (uint32_t) *p_coeffs_buf++; + r_macl_wait_operation(); + + /* Decrement the loop counter */ + tap_cnt--; + } + + /* Converting the result to 1.31 format */ + /* Calc lower part of acc */ + acc_l = (q31_t) (R_MACL->MULR0.MULRL >> l_shift); + + /* Calc upper part of acc */ + acc_h = (q31_t) R_MACL->MULR0.MULRH << u_shift; + + acc = acc_l | acc_h; + + /* Store the result from accumulator into the destination buffer. */ + *p_out++ = acc; + + /* Compute and store error */ + err_data = *p_ref++ - acc; + *p_err++ = err_data; + + /* Calculates the reciprocal of energy */ + post_shift = (q31_t) r_macl_recip_q31((q31_t) energy + DELTA_Q31, + &one_by_energy, + &p_lms_norm_ins_q31->recipTable[0]); + + /* Calculation of product of (e * mu) */ + /* Enable Fixed Point Mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_ENABLE; + R_MACL->MUL32S = (uint32_t) err_data; + R_MACL->MULB4 = (uint32_t) mu; + r_macl_wait_operation(); + error_x_mu = (q31_t) R_MACL->MULR4.MULRH; + + /* Disable fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + + /* Weighting factor for the normalized version */ + R_MACL->MUL32S = (uint32_t) error_x_mu; + R_MACL->MULB4 = (uint32_t) one_by_energy; + r_macl_wait_operation(); + result_temp = (q63_t) *p_result_r4; + weight_factor = clip_q63_to_q31(result_temp >> (31 - post_shift)); + + /* Initialize p_state pointer */ + p_state_buf = p_state; + + /* Initialize coefficient pointer */ + p_coeffs_buf = p_coeffs; + + /* Initialize tap_cnt with number of samples */ + tap_cnt = num_taps; + + while (tap_cnt > 0U) + { + /* Perform the multiply-accumulate */ + R_MACL->MULR5.MULRH = (uint32_t) (*p_coeffs_buf >> BSP_MACL_SHIFT_1_BIT); + R_MACL->MULR5.MULRL = (uint32_t) *p_coeffs_buf << BSP_MACL_SHIFT_31_BIT; + R_MACL->MAC32S = (uint32_t) weight_factor; + R_MACL->MULB5 = (uint32_t) *p_state_buf++; + r_macl_wait_operation(); + + tmp_check = (R_MACL->MULR5.MULRH >> BSP_MACL_SHIFT_30_BIT); + + /* Check overflow/underflow coefficient value */ + if (BSP_MACL_OVERFLOW_VALUE == tmp_check) + { + *p_coeffs_buf = (q31_t) BSP_MACL_Q31_MAX_VALUE; + } + else if (BSP_MACL_UNDERFLOW_VALUE == tmp_check) + { + *p_coeffs_buf = (q31_t) BSP_MACL_Q31_MIN_VALUE; + } + else + { + /* Enable fixed point mode. */ + R_MACL->MULC |= (uint8_t) R_MACL_MULC_MULFRAC_Msk; + + *p_coeffs_buf = (q31_t) R_MACL->MULR5.MULRH; + + /* Disable fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + } + + /* Increment the coefficient buffer */ + p_coeffs_buf++; + + /* Decrement loop counter */ + tap_cnt--; + } + + /* Read the sample from state buffer */ + x0 = *p_state; + + /* Advance state pointer by 1 for the next sample */ + p_state = p_state + 1; + + /* Decrement loop counter */ + blk_cnt--; + } + + /* Save energy and x0 values for the next frame */ + p_lms_norm_ins_q31->energy = (q31_t) energy; + p_lms_norm_ins_q31->x0 = x0; + + /* Processing is complete. + * Now copy the last num_taps - 1 samples to the start of the state buffer. + * This prepares the state buffer for the next function call. */ + + /* Points to the start of the p_state buffer */ + p_state_curnt = p_lms_norm_ins_q31->pState; + + /* Initialize tap_cnt with number of samples */ + tap_cnt = (num_taps - 1U); + + while (tap_cnt > 0U) + { + *p_state_curnt++ = *p_state++; + + /* Decrement loop counter */ + tap_cnt--; + } +} + +/*******************************************************************************************************************//** + * Perform the Q31 LMS filter via MACL module. + * @param[in] p_lms_ins_q31 points to an instance of the Q31 normalized LMS filter structure + * @param[in] p_src points to the block of input data + * @param[in] p_ref points to the block of reference data + * @param[out] p_out points to the block of output data + * @param[out] p_err points to the block of error data + * @param[in] block_size number of samples to process + **********************************************************************************************************************/ +void R_BSP_MaclLmsQ31 (const arm_lms_instance_q31 * p_lms_ins_q31, + const q31_t * p_src, + q31_t * p_ref, + q31_t * p_out, + q31_t * p_err, + uint32_t block_size) +{ + q31_t * p_state = p_lms_ins_q31->pState; // State pointer + q31_t * p_coeffs = p_lms_ins_q31->pCoeffs; // Coefficient pointer + q31_t * p_state_curnt; // Points to the current sample of the state + q31_t * p_state_buf; // Temporary pointers for state + q31_t * p_coeffs_buf; // Coefficient buffers + q31_t mu = p_lms_ins_q31->mu; // Adaptive factor + uint32_t num_taps = p_lms_ins_q31->numTaps; // Number of filter coefficients in the filter + uint32_t tap_cnt; // Loop counters + uint32_t blk_cnt; // Loop counters + q63_t acc; // Accumulator + q31_t err_data = 0; // Error data sample + q31_t alpha; // Intermediate constant for taps update + q31_t acc_l; // Low accumulator + q31_t acc_h; // High accumulator + uint32_t u_shift = (p_lms_ins_q31->postShift + 1); + uint32_t l_shift = BSP_MACL_32_BIT - u_shift; // Shift to be applied to the output + uint32_t tmp_check; // Check overflow/underflow value + + /* Disable fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + + /* p_lms_ins_q31->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + p_state_curnt = &(p_lms_ins_q31->pState[(num_taps - 1U)]); + + /* initialise loop count */ + blk_cnt = block_size; + + while (blk_cnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *p_state_curnt++ = *p_src++; + + /* Initialize pState pointer */ + p_state_buf = p_state; + + /* Initialize coefficient pointer */ + p_coeffs_buf = p_coeffs; + + /* Set the accumulator to zero */ + R_MACL->MULRCLR = BSP_MACL_CLEAR_MULR_REG; + + /* Initialize tapCnt with number of samples */ + tap_cnt = num_taps; + + while (tap_cnt > 0U) + { + /* Perform the multiply-accumulate */ + + R_MACL->MAC32S = (uint32_t) *p_state_buf++; + R_MACL->MULB0 = (uint32_t) *p_coeffs_buf++; + r_macl_wait_operation(); + + /* Decrement the loop counter */ + tap_cnt--; + } + + /* Converting the result to 1.31 format */ + /* Calc lower part of acc */ + acc_l = (q31_t) (R_MACL->MULR0.MULRL >> l_shift); + + /* Calc upper part of acc */ + acc_h = (q31_t) R_MACL->MULR0.MULRH << u_shift; + + acc = acc_l | acc_h; + + /* Store the result from accumulator into the destination buffer. */ + *p_out++ = (q31_t) acc; + + /* Compute and store error */ + err_data = *p_ref++ - (q31_t) acc; + *p_err++ = err_data; + + /* Compute alpha i.e. intermediate constant for taps update */ + /* Enable Fixed Point Mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_ENABLE; + R_MACL->MUL32S = (uint32_t) err_data; + R_MACL->MULB4 = (uint32_t) mu; + r_macl_wait_operation(); + alpha = (q31_t) R_MACL->MULR4.MULRH; + + /* Initialize pState pointer */ + /* Advance state pointer by 1 for the next sample */ + p_state_buf = p_state++; + + /* Initialize coefficient pointer */ + p_coeffs_buf = p_coeffs; + + /* Initialize tapCnt with number of samples */ + tap_cnt = num_taps; + + /* Disable fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + + while (tap_cnt > 0U) + { + /* Perform the multiply-accumulate */ + + /* coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32)); + * pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); */ + R_MACL->MULR5.MULRH = (uint32_t) (*p_coeffs_buf >> BSP_MACL_SHIFT_1_BIT); + R_MACL->MULR5.MULRL = (uint32_t) *p_coeffs_buf << BSP_MACL_SHIFT_31_BIT; + + R_MACL->MAC32S = (uint32_t) alpha; + R_MACL->MULB5 = (uint32_t) *p_state_buf++; + r_macl_wait_operation(); + + tmp_check = (R_MACL->MULR5.MULRH >> BSP_MACL_SHIFT_30_BIT); + + /* Check overflow/underflow coefficient value */ + if (BSP_MACL_OVERFLOW_VALUE == tmp_check) + { + *p_coeffs_buf = (q31_t) BSP_MACL_Q31_MAX_VALUE; + } + else if (BSP_MACL_UNDERFLOW_VALUE == tmp_check) + { + *p_coeffs_buf = (q31_t) BSP_MACL_Q31_MIN_VALUE; + } + else + { + /* Enable fixed point mode. */ + R_MACL->MULC |= (uint8_t) R_MACL_MULC_MULFRAC_Msk; + + *p_coeffs_buf = (q31_t) R_MACL->MULR5.MULRH; + + /* Disable fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + } + + /* Increment the coefficient buffer */ + p_coeffs_buf++; + + /* Decrement loop counter */ + tap_cnt--; + } + + /* Decrement loop counter */ + blk_cnt--; + } + + /* Processing is complete. + * Now copy the last numTaps - 1 samples to the start of the state buffer. + * This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + p_state_curnt = p_lms_ins_q31->pState; + + /* copy data */ + /* Initialize tapCnt with number of samples */ + tap_cnt = (num_taps - 1U); + + while (tap_cnt > 0U) + { + *p_state_curnt++ = *p_state++; + + /* Decrement loop counter */ + tap_cnt--; + } +} + +/*******************************************************************************************************************//** + * Perform the Q31 FIR filter via MACL module. + * + * @param[in] p_fir_inst Points to an instance of the Q31 FIR filter structure + * @param[in] p_src Points to the block of input data + * @param[in] p_ref Points to the block of reference data + * @param[out] p_out Points to the block of output data + * @param[out] p_err Points to the block of error data + * @param[in] block_size Number of samples to process + **********************************************************************************************************************/ +void R_BSP_MaclFirQ31 (const arm_fir_instance_q31 * p_fir_inst, const q31_t * p_src, q31_t * p_dst, uint32_t block_size) +{ + q31_t * p_state; // Pointer to state buffer which will be used to hold calculated sample + q31_t * p_state_curnt; // Intermediate pointer used to write sample into state buffer + q31_t * p_state_tmp; // Intermediate pointer to write sample value into register MAC32S + const q31_t * p_coeff_tmp; // Intermediate pointer to write coefficient into register MULB0 + const q31_t * p_coeffs; // Local pointer for p_Coeff of instance p_fir_inst + uint16_t num_taps; // Numbers of coefficient + uint32_t tap_cnt; // Loop count + uint32_t blk_cnt; // Loop count + + p_state = p_fir_inst->pState; + p_coeffs = p_fir_inst->pCoeffs; + + num_taps = p_fir_inst->numTaps; + blk_cnt = block_size; + + /* p_fir_inst->pState points to state array which contains previous frame (num_taps - 1) samples */ + /* p_state_curnt points to the location where the new input data should be written */ + p_state_curnt = &(p_fir_inst->pState[(num_taps - 1U)]); + + /* Enable fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_ENABLE; + + while (blk_cnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *p_state_curnt++ = *p_src++; + + /* Initialize state pointer */ + p_state_tmp = p_state; + + /* Initialize Coefficient pointer */ + p_coeff_tmp = p_coeffs; + + tap_cnt = num_taps; + + /* Clean result reg */ + R_MACL->MULRCLR = 0U; + + /* Perform the multiply-accumulates */ + do + { + /* y[n] = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */ + R_MACL->MAC32S = (uint32_t) (*p_state_tmp++); + R_MACL->MULB0 = (uint32_t) (*p_coeff_tmp++); + + r_macl_wait_operation(); + + tap_cnt--; + } while (tap_cnt > 0U); + + /* Store result into destination buffer. */ + *p_dst++ = (q31_t) R_MACL->MULR0.MULRH; + + /* Advance state pointer by 1 for the next sample */ + p_state++; + + /* Decrement loop counter */ + blk_cnt--; + } + + /* Disable fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + + /* Processing is complete. Now copy the last num_taps - 1 samples to the start of the state buffer. This prepares + * the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + p_state_curnt = p_fir_inst->pState; + + /* Initialize tapCnt with number of taps */ + tap_cnt = (num_taps - 1U); + + /* Copy remaining data */ + while (tap_cnt > 0U) + { + *p_state_curnt++ = *p_state++; + + /* Decrement loop counter */ + tap_cnt--; + } +} + +/*******************************************************************************************************************//** + * Waiting for MACL module finish 5 cycles of processing. + * + **********************************************************************************************************************/ +static inline void r_macl_wait_operation () +{ + /* Wait for 5 cycles */ + __asm volatile ( + "nop \n" + "nop \n" + "nop \n" + "nop \n" + "nop \n" + ); +} + +/*******************************************************************************************************************//** + * Multiplication operation of MACL module. + * + * @param[in] p_src_a Pointer to multiplied number. + * @param[in] p_src_b Pointer to multiplicand number. + * @param[out] p_dst Pointer to buffer which will hold the calculation result. + * @param[in] block_size Numbers of elements to be calculated. + **********************************************************************************************************************/ +static void r_macl_mul_q31 (const q31_t * p_src_a, const q31_t * p_src_b, q31_t * p_dst, uint32_t block_size) +{ + const q31_t * p_src_a_local; + const q31_t * p_src_b_local; + q31_t * p_dst_local; + uint32_t block_size_cnt; + + block_size_cnt = block_size; + + p_src_a_local = p_src_a; + p_src_b_local = p_src_b; + p_dst_local = p_dst; + + /* Clean result register before perform the calculation */ + R_MACL->MULRCLR = 0U; + + while (block_size_cnt > 0U) + { + if ((*p_src_a_local == (q31_t) BSP_MACL_Q31_MIN_VALUE) && (*p_src_b_local == (q31_t) BSP_MACL_Q31_MIN_VALUE)) + { + /* Overflow case */ + *p_dst_local = (q31_t) BSP_MACL_Q31_MAX_VALUE; + } + else + { + /* Write value to perform the multiply operation */ + R_MACL->MUL32S = (uint32_t) (*p_src_a_local); + R_MACL->MULB0 = (uint32_t) (*p_src_b_local); + + /* Wait for the calculation. */ + r_macl_wait_operation(); + + *p_dst_local = (q31_t) R_MACL->MULR0.MULRH; + } + + block_size_cnt--; + p_src_a_local++; + p_src_b_local++; + p_dst_local++; + } +} + +/*******************************************************************************************************************//** + * Perform scaling a vector by multiplying scalar via MACL module. + * + * @param[in] p_src Pointer which point to a vector. + * @param[in] scale_fract Pointer to the scalar number. + * @param[in] shift Number of bits to shift the result by + * @param[out] p_dst Pointer to buffer which will hold the calculation result. + * @param[in] block_size Numbers of elements to be calculated. + **********************************************************************************************************************/ +static void r_macl_scale_q31 (const q31_t * p_src, q31_t scale_fract, int8_t shift, q31_t * p_dst, uint32_t block_size) +{ + const q31_t * p_src_local; + q31_t * p_dst_local; + q31_t out; + uint32_t block_size_cnt; + bool shift_signed; + int32_t scale_shift; /* Shift to apply after scaling */ + + volatile uint32_t * p_result = &(R_MACL->MULR0.MULRH); + + block_size_cnt = block_size; + shift_signed = (bool) (shift & BSP_MACL_SHIFT_SIGN); + scale_shift = shift + 1; + + p_src_local = p_src; + p_dst_local = p_dst; + + /* Clean result register before perform the calculation */ + R_MACL->MULRCLR = 0U; + + /* Write data to register MUL32S. */ + R_MACL->MUL32S = (uint32_t) scale_fract; + + while (block_size_cnt > 0U) + { + /* Write data to register B */ + R_MACL->MULB0 = (uint32_t) (*p_src_local); + + /* Wait for the calculation. */ + r_macl_wait_operation(); + + if (shift_signed == BSP_MACL_POSITIVE_NUM) + { + /* Read data to register MULRLn.MULRH */ + out = (q31_t) (*p_result) << scale_shift; + + if (*p_result != (uint32_t) (out >> scale_shift)) + { + /* Overflow/underflow check for shifting result */ + if (BSP_MACL_POSITIVE_NUM == (*p_result >> BSP_MACL_SHIFT_31_BIT)) + { + out = (q31_t) (BSP_MACL_Q31_MAX_VALUE); + } + else + { + out = (q31_t) (BSP_MACL_Q31_MIN_VALUE); + } + } + + /* Write out the result */ + *p_dst_local = out; + } + else + { + /* Read data to register MULRLn.MULRH. */ + out = (q31_t) (*p_result) >> -scale_shift; + + /* Write out the result */ + *p_dst_local = out; + } + + block_size_cnt--; + p_src_local++; + p_dst_local++; + } +} + +/*******************************************************************************************************************//** + * Perform Q31 matrix multiplication via MACL module. + * + * @param[in] p_src_a Points to the first input matrix structure A. + * @param[in] p_src_b Points to the second input matrix structure B. + * @param[out] p_dst Points to the buffer which hold output matrix structure. + **********************************************************************************************************************/ +static void r_macl_mat_mul_q31 (const arm_matrix_instance_q31 * p_src_a, + const arm_matrix_instance_q31 * p_src_b, + arm_matrix_instance_q31 * p_dst) +{ + const q31_t * p_in_a = p_src_a->pData; // Input data matrix pointer A + const q31_t * p_in_b; // Input data matrix pointer B + q31_t * p_out = p_dst->pData; // Output data matrix pointer + uint16_t num_rows_a = p_src_a->numRows; // Number of rows of input matrix A + uint16_t num_cols_b = p_src_b->numCols; // Number of columns of input matrix B + uint16_t num_cols_a = p_src_a->numCols; // Number of columns of input matrix A + uint16_t col; // Column loop counters + uint16_t row = num_rows_a; // Row loop counters + + /* Row loop */ + do + { + /* For every row wise process, column loop counter is to be initiated */ + col = num_cols_b; + + /* For every row wise process, p_in_b pointer is set to starting address of p_src_b data */ + p_in_b = p_src_b->pData; + + /* Column loop */ + do + { + /* Perform the multiply-accumulates a row in p_src_a with a column in p_src_b */ + r_macl_mat_mul_acc_q31(p_in_a, p_in_b, p_out, num_cols_a, num_cols_b); + + p_in_b++; + p_out++; + col--; + } while (col > 0U); + + row--; + p_in_a += num_cols_a; + } while (row > 0U); +} + +/*******************************************************************************************************************//** + * Perform the multiply-accumulates a row with a column. + * + * @param[in] p_in_a Points to the input data matrix pointer A. + * @param[in] p_in_b Points to the input data matrix pointer B. + * @param[out] p_out Points to the output data matrix pointer. + * @param[in] num_cols_a Number of columns of input matrix A. + * @param[in] num_cols_b Number of columns of input matrix B. + **********************************************************************************************************************/ +static void r_macl_mat_mul_acc_q31 (const q31_t * p_in_a, + const q31_t * p_in_b, + q31_t * p_out, + uint16_t num_cols_a, + uint16_t num_cols_b) +{ + uint16_t cnt = num_cols_a; + const q31_t * p_tmp_a = p_in_a; + const q31_t * p_tmp_b = p_in_b; + q31_t out_h; + q31_t out_l; + + R_MACL->MULRCLR = 0U; + + while (cnt > 0U) + { + R_MACL->MAC32S = (uint32_t) (*p_tmp_a); + R_MACL->MULB0 = (uint32_t) (*p_tmp_b); + + /* Wait for the calculation. */ + r_macl_wait_operation(); + cnt--; + p_tmp_a++; + p_tmp_b += num_cols_b; + } + + /* Read data to register MULR0. */ + out_h = (q31_t) (R_MACL->MULR0.MULRH << BSP_MACL_SHIFT_1_BIT); + out_l = (q31_t) (R_MACL->MULR0.MULRL >> BSP_MACL_SHIFT_31_BIT); + *p_out = (out_h | out_l); +} + +/*******************************************************************************************************************//** + * Perform scaling a matrix by multiplying scalar via MACL module. + * + * @param[in] p_src Points to the input matrix. + * @param[in] scale_fract Fractional portion of the scale factor. + * @param[in] shift Number of bits to shift the result by + * @param[out] p_dst Points to the output matrix structure which will hold the calculation result. + **********************************************************************************************************************/ +static void r_macl_mat_scale_q31 (const arm_matrix_instance_q31 * p_src, + q31_t scale_fract, + int32_t shift, + arm_matrix_instance_q31 * p_dst) +{ + q31_t * p_in = p_src->pData; // Input data matrix pointer + q31_t * p_out = p_dst->pData; // Output data matrix pointer + uint32_t block_size; // Loop counter + q31_t out; // Temporary output data + int32_t scale_shift; // Shift to apply after scaling + volatile uint32_t * p_result = &(R_MACL->MULR0.MULRH); + + scale_shift = shift + 1; + + /* Total number of samples in input matrix */ + block_size = (uint32_t) (p_src->numRows * p_src->numCols); + + /* Clean result register before perform the calculation */ + R_MACL->MULRCLR = 0U; + + /* Write data to register MUL32S. */ + R_MACL->MUL32S = (uint32_t) scale_fract; + + while (block_size > 0U) + { + /* Write data to register B. */ + R_MACL->MULB0 = (uint32_t) (*p_in); + + /* Wait for the calculation. */ + r_macl_wait_operation(); + + /* Read data to register MULRL.MULRH. */ + out = (q31_t) (*p_result) << scale_shift; + + if (*p_result != (uint32_t) (out >> scale_shift)) + { + /* Overflow/underflow check for shifting result */ + if (BSP_MACL_POSITIVE_NUM == (*p_result >> BSP_MACL_SHIFT_31_BIT)) + { + out = (q31_t) (BSP_MACL_Q31_MAX_VALUE); + } + else + { + out = (q31_t) (BSP_MACL_Q31_MIN_VALUE); + } + } + + /* Write out the result. */ + *p_out = out; + + block_size--; + p_in++; + p_out++; + } +} + +/*******************************************************************************************************************//** + * Perform multiply-accumulate via MACL for convolution operation. + * + * @param[in] check_value Value which got from result register MULRH. + * @param[out] p_dst Pointer to destination buffer. + **********************************************************************************************************************/ +void r_macl_conv_q31 (const q31_t * p_src_a, const q31_t * p_src_b, q31_t * p_dst, uint8_t block_size) +{ + uint8_t cnt; + const q31_t * p_src_a_local; + const q31_t * p_src_b_local; + q31_t * p_dst_local; + + p_src_a_local = p_src_a; + p_src_b_local = p_src_b; + p_dst_local = p_dst; + + cnt = block_size; + + /* Clean register result */ + R_MACL->MULRCLR = 0U; + + /* Perform multiply-accumulate */ + while (cnt > 0) + { + R_MACL->MAC32S = (uint32_t) (*p_src_a_local); + R_MACL->MULB0 = (uint32_t) (*p_src_b_local); + + /* Wait for the calculation. */ + r_macl_wait_operation(); + + p_src_a_local++; + p_src_b_local--; + cnt--; + } + + /* Store result into desire buffer */ + *p_dst_local = (q31_t) R_MACL->MULR0.MULRH; +} + +/*******************************************************************************************************************//** + * Function to Calculates 1/in (reciprocal) value of Q31 Data type. + * + * @param[in] in Input data. + * @param[out] dst Point to output data. + * @param[in] p_recip_table Points to the reciprocal initial value table. + **********************************************************************************************************************/ + +uint32_t r_macl_recip_q31 (q31_t in, q31_t * dst, const q31_t * p_recip_table) +{ + q31_t out; + uint32_t temp_val; + uint32_t index; + uint32_t sign_bits; + uint64_t reg_val; + volatile uint64_t * p_result_r3 = (uint64_t *) &(R_MACL->MULR3.MULRL); + + /* Enable fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_ENABLE; + if (in > 0) + { + sign_bits = ((uint32_t) (__CLZ((uint32_t) in) - 1)); + } + else + { + sign_bits = ((uint32_t) (__CLZ((uint32_t) (-in)) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << sign_bits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t) (in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = p_recip_table[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (uint32_t i = 0U; i < 2U; i++) + { + R_MACL->MUL32S = (uint32_t) in; + R_MACL->MULB3 = (uint32_t) out; + r_macl_wait_operation(); + temp_val = R_MACL->MULR3.MULRH; + + /* Disable fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + temp_val = BSP_MACL_Q31_MAX_VALUE - temp_val; + + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * temp_val) >> 30); */ + R_MACL->MUL32S = (uint32_t) out; + R_MACL->MULB3 = temp_val; + r_macl_wait_operation(); + reg_val = *p_result_r3; + out = clip_q63_to_q31(((q63_t) reg_val) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of sign_bits of out = 1/in value */ + return sign_bits + 1U; +} + + #endif +#endif + +/******************************************************************************************************************//** + * @} (end addtogroup BSP_MACL) + **********************************************************************************************************************/ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_macl.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_macl.h new file mode 100644 index 00000000000..416228d5c7c --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_macl.h @@ -0,0 +1,164 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef RENESAS_MACL +#define RENESAS_MACL + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +#include +#include "bsp_api.h" + +#if BSP_FEATURE_MACL_SUPPORTED + #if __has_include("arm_math_types.h") + +/* Ignore certain math warnings in ARM CMSIS DSP headers */ + #if defined(__ARMCC_VERSION) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wsign-conversion" + #pragma clang diagnostic ignored "-Wimplicit-int-conversion" + #pragma clang diagnostic ignored "-Wimplicit-int-float-conversion" + #elif defined(__GNUC__) + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wconversion" + #pragma GCC diagnostic ignored "-Wsign-conversion" + #pragma GCC diagnostic ignored "-Wfloat-conversion" + #endif + #if defined(__IAR_SYSTEMS_ICC__) + #pragma diag_suppress=Pe223 + #endif + + #include "arm_math_types.h" + #include "dsp/basic_math_functions.h" + #include "dsp/matrix_functions.h" + #include "dsp/filtering_functions.h" + #include "dsp/support_functions.h" + #include "dsp/fast_math_functions.h" + + #if defined(__IAR_SYSTEMS_ICC__) + #pragma diag_default=Pe223 + #endif + #if defined(__ARMCC_VERSION) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + #pragma GCC diagnostic pop + #endif + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MACL + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Common macro used by MACL */ + #define BSP_MACL_FIXED_POINT_MODE_DISABLE (0x0) + #define BSP_MACL_FIXED_POINT_MODE_ENABLE (0x10) + + #define BSP_MACL_SHIFT_SIGN (0x80) + #define BSP_MACL_SHIFT_1_BIT (1U) + #define BSP_MACL_SHIFT_30_BIT (30U) + #define BSP_MACL_SHIFT_31_BIT (31U) + #define BSP_MACL_SHIFT_32_BIT (32U) + + #define BSP_MACL_32_BIT (32U) + + #define BSP_MACL_Q31_MAX_VALUE (0x7FFFFFFF) // Max value is 0.999999999534 + #define BSP_MACL_Q31_MIN_VALUE (0x80000000) // Min value is -1.0 + + #define BSP_MACL_OVERFLOW_VALUE (0x1) // 0b01 + #define BSP_MACL_UNDERFLOW_VALUE (0x2) // 0b10 + + #define BSP_MACL_CLEAR_MULR_REG (0x0U) + + #define BSP_MACL_POSITIVE_NUM (0U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +void R_BSP_MaclMulQ31(const q31_t * p_src_a, const q31_t * p_src_b, q31_t * p_dst, uint32_t block_size); +void R_BSP_MaclScaleQ31(const q31_t * p_src, q31_t scale_fract, int8_t shift, q31_t * p_dst, uint32_t block_size); +void R_BSP_MaclMatMulQ31(const arm_matrix_instance_q31 * p_src_a, + const arm_matrix_instance_q31 * p_src_b, + arm_matrix_instance_q31 * p_dst); +void R_BSP_MaclMatVecMulQ31(const arm_matrix_instance_q31 * p_src_mat, const q31_t * p_vec, q31_t * p_dst); +void R_BSP_MaclMatScaleQ31(const arm_matrix_instance_q31 * p_src, + q31_t scale_fract, + int32_t shift, + arm_matrix_instance_q31 * p_dst); +void R_BSP_MaclBiquadCsdDf1Q31(const arm_biquad_casd_df1_inst_q31 * p_biquad_csd_df1_inst, + const q31_t * p_src, + q31_t * p_dst, + uint32_t block_size); +void R_BSP_MaclConvQ31(const q31_t * p_src_a, + uint32_t src_a_len, + const q31_t * p_src_b, + uint32_t src_b_len, + q31_t * p_dst); +arm_status R_BSP_MaclConvPartialQ31(const q31_t * p_src_a, + uint32_t src_a_len, + const q31_t * p_src_b, + uint32_t src_b_len, + q31_t * p_dst, + uint32_t first_idx, + uint32_t num_points); + +void R_BSP_MaclFirDecimateQ31(const arm_fir_decimate_instance_q31 * p_fir_decimate_ins_q31, + const q31_t * p_src, + q31_t * p_dst, + uint32_t block_size); + +void R_BSP_MaclFirInterpolateQ31(const arm_fir_interpolate_instance_q31 * p_fir_interpolate_ins_q31, + const q31_t * p_src, + q31_t * p_dst, + uint32_t block_size); + +void R_BSP_MaclCorrelateQ31(const q31_t * p_src_a, + uint32_t src_a_len, + const q31_t * p_src_b, + uint32_t src_b_len, + q31_t * p_dst); + +void R_BSP_MaclFirSparseQ31(arm_fir_sparse_instance_q31 * p_fir_sparse_ins_q31, + const q31_t * p_src, + q31_t * p_dst, + q31_t * p_scratch_in, + uint32_t block_size); + +void R_BSP_MaclLmsNormQ31(arm_lms_norm_instance_q31 * p_lms_norm_ins_q31, + const q31_t * p_src, + q31_t * p_ref, + q31_t * p_out, + q31_t * p_err, + uint32_t block_size); + +void R_BSP_MaclLmsQ31(const arm_lms_instance_q31 * p_lms_ins_q31, + const q31_t * p_src, + q31_t * p_ref, + q31_t * p_out, + q31_t * p_err, + uint32_t block_size); + +void R_BSP_MaclFirQ31(const arm_fir_instance_q31 * p_fir_inst, const q31_t * p_src, q31_t * p_dst, uint32_t block_size); + +/******************************************************************************************************************//** + * @} (end addtogroup BSP_MACL) + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + + #endif +#endif +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h new file mode 100644 index 00000000000..b548ca79dca --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h @@ -0,0 +1,87 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_MCU_API_H +#define BSP_MCU_API_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP Linker Includes. */ +#include "bsp_linker_info.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#if BSP_PERIPHERAL_ELC_PRESENT || BSP_PERIPHERAL_ELC_B_PRESENT +typedef struct st_bsp_event_info +{ + IRQn_Type irq; + elc_event_t event; +} bsp_event_info_t; +#endif + +#ifndef BSP_OVERRIDE_BSP_CLOCKS_OCTACLK_DIV_T + +typedef enum e_bsp_clocks_octaclk_div +{ + BSP_CLOCKS_OCTACLK_DIV_1 = 0, ///< Divide OCTA source clock by 1 + BSP_CLOCKS_OCTACLK_DIV_2, ///< Divide OCTA source clock by 2 + BSP_CLOCKS_OCTACLK_DIV_4, ///< Divide OCTA source clock by 4 + BSP_CLOCKS_OCTACLK_DIV_6, ///< Divide OCTA source clock by 6 + BSP_CLOCKS_OCTACLK_DIV_8, ///< Divide OCTA source clock by 8 + BSP_CLOCKS_OCTACLK_DIV_3, ///< Divide OCTA source clock by 3 + BSP_CLOCKS_OCTACLK_DIV_5, ///< Divide OCTA source clock by 5 + BSP_CLOCKS_OCTACLK_DIV_10, ///< Divide OCTA source clock by 10 + BSP_CLOCKS_OCTACLK_DIV_16, ///< Divide OCTA source clock by 16 + BSP_CLOCKS_OCTACLK_DIV_32, ///< Divide OCTA source clock by 32 +} bsp_clocks_octaclk_div_t; +#endif + +typedef enum e_bsp_clocks_source +{ + BSP_CLOCKS_CLOCK_HOCO = 0, ///< The high speed on chip oscillator. + BSP_CLOCKS_CLOCK_MOCO, ///< The middle speed on chip oscillator. + BSP_CLOCKS_CLOCK_LOCO, ///< The low speed on chip oscillator. + BSP_CLOCKS_CLOCK_MAIN_OSC, ///< The main oscillator. + BSP_CLOCKS_CLOCK_SUBCLOCK, ///< The subclock oscillator. + BSP_CLOCKS_CLOCK_PLL, ///< The PLL oscillator. + BSP_CLOCKS_CLOCK_PLL2, ///< The PLL2 oscillator. +} bsp_clocks_source_t; + +typedef struct st_bsp_octaclk_settings +{ + bsp_clocks_source_t source_clock; ///< OCTACLK source clock + bsp_clocks_octaclk_div_t divider; ///< OCTACLK divider +} bsp_octaclk_settings_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +void R_BSP_RegisterProtectEnable(bsp_reg_protect_t regs_to_protect); +void R_BSP_RegisterProtectDisable(bsp_reg_protect_t regs_to_unprotect); +fsp_err_t R_BSP_GroupIrqWrite(bsp_grp_irq_t irq, void (* p_callback)(bsp_grp_irq_t irq)); +void R_BSP_OctaclkUpdate(bsp_octaclk_settings_t * p_octaclk_setting); +void R_BSP_SoftwareDelay(uint32_t delay, bsp_delay_units_t units); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_mmf.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_mmf.h new file mode 100644 index 00000000000..9b7f1b143fd --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_mmf.h @@ -0,0 +1,141 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_MMF_H +#define BSP_MMF_H + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define MEMORY_MIRROR_REG_KEY (0xDBU) +#define MEMORY_MIRROR_BOUNDARY (0x80U) // 128 bytes +#define MEMORY_MIRROR_ADDR_MASK (0x007FFFFFU) + +/* The highest address which MMF able to support is the last address of code flash area which aligns with 128. */ +#define MEMORY_MIRROR_MAX_ADDR (BSP_FEATURE_FLASH_CODE_FLASH_START + BSP_ROM_SIZE_BYTES - MEMORY_MIRROR_BOUNDARY) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Enum for state of Memory Mirror Function. */ +typedef enum e_mmf_state +{ + MEMORY_MIRROR_DISABLED = 0, + MEMORY_MIRROR_ENABLED = 1, +} mmf_state_t; + +/** Status instance of Memory Mirror Function. */ +typedef struct st_mmf_status +{ + mmf_state_t mmf_state; // Current state of Memory Mirror Region. + uint32_t mmf_cur_addr; // Current address in register MMSFR. +} mmf_status_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Get the current status of Memory Mirror. + * + * @param[out] p_mmf_status Pointer to instance which used for storing the state of MMF after invoked this function. + * + * @retval FSP_SUCCESS MMF status retrieved successfully. + * @retval FSP_ERR_UNSUPPORTED MCU does not support MMF. + * @retval FSP_ERR_ASSERTION NULL pointer passed as argument. + * + * This function retrieves the current state of the MMF and the mirrored address into a user provided structure. + **********************************************************************************************************************/ +__STATIC_INLINE fsp_err_t R_BSP_MemoryMirrorStatusGet (mmf_status_t * p_mmf_status) +{ +#if BSP_FEATURE_BSP_MMF_SUPPORTED + #if BSP_CFG_PARAM_CHECKING_ENABLE + + /* Ensure that variable for storing the status of MMF was provided. */ + if (NULL == p_mmf_status) + { + return FSP_ERR_ASSERTION; + } + #endif + + p_mmf_status->mmf_state = (mmf_state_t) R_MMF->MMEN_b.EN; + p_mmf_status->mmf_cur_addr = R_MMF->MMSFR & MEMORY_MIRROR_ADDR_MASK; + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_mmf_status); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Set address for MMF region. + * + * @param[in] addr Address of memory region to be mirrored into MMF region. + * + * @retval FSP_SUCCESS Address is set successfully. + * @retval FSP_ERR_UNSUPPORTED MCU does not support MMF. + * @retval FSP_ERR_INVALID_ADDRESS Requested address is out of supported range. + * + * This function sets the memory address to be mirrored by MMF. + **********************************************************************************************************************/ +__STATIC_INLINE fsp_err_t R_BSP_MemoryMirrorAddrSet (const uint32_t addr) +{ +#if BSP_FEATURE_BSP_MMF_SUPPORTED + #if BSP_CFG_PARAM_CHECKING_ENABLE + + /* Ensure that requested address is in supported range and must align with 128 */ + if ((MEMORY_MIRROR_MAX_ADDR < addr) || (0 != addr % MEMORY_MIRROR_BOUNDARY)) + { + return FSP_ERR_INVALID_ADDRESS; + } + #endif + + /* If MMF is enabled, disable MMF before updating the address register. + * For disabling MMF, write 0xDB00 to register MMEN. */ + if (1U == R_MMF->MMEN_b.EN) + { + R_MMF->MMEN = ((uint32_t) (MEMORY_MIRROR_REG_KEY << R_MMF_MMSFR_KEY_Pos) | 0U); + } + + R_MMF->MMSFR = ((uint32_t) (MEMORY_MIRROR_REG_KEY << R_MMF_MMSFR_KEY_Pos) | addr); + + /* Enable MMF by writing 0xDB01 to register MMEN. After this point target memory address will be reflected into + * MMF region. */ + R_MMF->MMEN = ((uint32_t) (MEMORY_MIRROR_REG_KEY << R_MMF_MMSFR_KEY_Pos) | 1U); + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(addr); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif + +/** @} (end addtogroup BSP_MCU) */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h new file mode 100644 index 00000000000..ab3b22b4e28 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h @@ -0,0 +1,389 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_MODULE_H +#define BSP_MODULE_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +#if BSP_FEATURE_TZ_HAS_TRUSTZONE + +/* MSTPCRA is located in R_MSTP for Star devices. */ + #define R_BSP_MSTPCRA (R_MSTP->MSTPCRA) +#else + +/* MSTPCRA is located in R_SYSTEM for W1D and Peaks devices. */ + #define R_BSP_MSTPCRA (R_SYSTEM->MSTPCRA) +#endif + +/*******************************************************************************************************************//** + * Cancels the module stop state. + * + * @param ip fsp_ip_t enum value for the module to be stopped + * @param channel The channel. Use channel 0 for modules without channels. + **********************************************************************************************************************/ +#if BSP_CFG_MSTP_CHANGE_DELAY_ENABLE + #define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_MSTP_REG_ ## ip(channel) &= ~BSP_MSTP_BIT_ ## ip(channel); \ + FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, \ + BSP_DELAY_UNITS_MICROSECONDS); \ + FSP_CRITICAL_SECTION_EXIT;} +#else + #define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_MSTP_REG_ ## ip(channel) &= \ + (BSP_MSTP_REG_TYPE_ ## ip(channel)) ~BSP_MSTP_BIT_ ## ip(channel); \ + FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ + FSP_CRITICAL_SECTION_EXIT;} +#endif + +/*******************************************************************************************************************//** + * Enables the module stop state. + * + * @param ip fsp_ip_t enum value for the module to be stopped + * @param channel The channel. Use channel 0 for modules without channels. + **********************************************************************************************************************/ +#if BSP_CFG_MSTP_CHANGE_DELAY_ENABLE + #define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \ + FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, \ + BSP_DELAY_UNITS_MICROSECONDS); \ + FSP_CRITICAL_SECTION_EXIT;} +#else + #define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \ + FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ + FSP_CRITICAL_SECTION_EXIT;} +#endif + +/** @} (end addtogroup BSP_MCU) */ + +#if 0U == BSP_FEATURE_GPT_MSTP_HAS_MSTPCRE + #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRD + #if !BSP_FEATURE_GPT_MSTP_MSTPD5 + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << 6U) + #else + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) ((BSP_FEATURE_GPT_MSTP_MSTPD5_MAX_CH >= \ + channel) ? (1U << 5U) : (1U << 6U)); + #endif + #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); + #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t + + #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD + + #if BSP_MCU_GROUP_RA2A2 + +/* RA2A2 has a combination of AGT and AGTW. + * Ch 0-1: MSTPD[ 3: 2] (AGTW0, AGTW1) + * Ch 2-3: MSTPD[19:18] (AGT0, AGT1) + * Ch 4-5: MSTPD[ 1: 0] (AGT2, AGT3) + * Ch 6-9: MSTPD[10: 7] (AGT4, AGT5, AGT6, AGT7) + */ + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << \ + ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT) \ + ? (3U - channel) \ + : ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + 2U) \ + ? (19U - channel + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT) \ + : ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + 4U) \ + ? (1U - channel + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + \ + 2U) \ + : (10U - channel + \ + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + \ + 4U))))); + + #else + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); + #endif + #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t + + #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD + #if BSP_FEATURE_POEG_MSTP_MSTPD13 + #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); + #else + #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U)); + #endif + #define BSP_MSTP_REG_TYPE_FSP_IP_POEG(channel) uint32_t +#else + #if (2U == BSP_FEATURE_ELC_VERSION) + #if BSP_MCU_GROUP_RA6T2 + #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << 31); + #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); + #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); + #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t + #elif BSP_MCU_GROUP_RA8_GEN2 + #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << \ + (31 - ((channel >= 4U && channel <= 9U) ? 4U : channel))) // GPT Channels 4-9 share stop bits on this MCU + #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (6U)); + #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel)); + #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t + #else + #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel)); + #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); + #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel)); + #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t + #endif + #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << 4U); + #define BSP_MSTP_REG_TYPE_FSP_IP_KEY(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); + #define BSP_MSTP_REG_TYPE_FSP_IP_POEG(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_ULPT(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_ULPT(channel) (1U << (9U - channel)); + #define BSP_MSTP_REG_TYPE_FSP_IP_ULPT(channel) uint32_t + #else + #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel)); + #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); + #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_AGT(channel) *((3U >= channel) ? &R_MSTP->MSTPCRD : &R_MSTP->MSTPCRE) + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) ((3U >= \ + channel) ? (1U << (3U - channel)) : (1U << \ + (15U - \ + (channel - 4U)))); + #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << (4U - channel)); + #define BSP_MSTP_REG_TYPE_FSP_IP_KEY(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); + #define BSP_MSTP_REG_TYPE_FSP_IP_POEG(channel) uint32_t + #endif +#endif + +#if (1U == BSP_FEATURE_CGC_HAS_OSTDCSE) + #define BSP_MSTP_REG_FSP_IP_SOSTD(channel) R_BSP_MSTPCRA + #define BSP_MSTP_BIT_FSP_IP_SOSTD(channel) (1U << (16U)); + #define BSP_MSTP_REG_TYPE_FSP_IP_SOSTD(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_MOSTD(channel) R_BSP_MSTPCRA + #define BSP_MSTP_BIT_FSP_IP_MOSTD(channel) (1U << (17U)); + #define BSP_MSTP_REG_TYPE_FSP_IP_MOSTD(channel) uint32_t +#endif + +#define BSP_MSTP_REG_FSP_IP_NPU(channel) R_BSP_MSTPCRA +#define BSP_MSTP_BIT_FSP_IP_NPU(channel) (1U << (16U)); + +#define BSP_MSTP_REG_FSP_IP_DMAC(channel) R_BSP_MSTPCRA +#if BSP_MCU_GROUP_RA8_GEN2 && (1U == BSP_CFG_CPU_CORE) + #define BSP_MSTP_BIT_FSP_IP_DMAC(channel) (1U << (23U)); +#else + #define BSP_MSTP_BIT_FSP_IP_DMAC(channel) (1U << (22U)); +#endif + +#define BSP_MSTP_REG_TYPE_FSP_IP_DMAC(channel) uint32_t + +#if BSP_FEATURE_CGC_REGISTER_SET_B + #define BSP_MSTP_REG_FSP_IP_DTC(channel) R_BSP_MSTPCRA + #define BSP_MSTP_BIT_FSP_IP_DTC(channel) (1U << (6U)) + #define BSP_MSTP_REG_TYPE_FSP_IP_DTC(channel) uint16_t +#else + #define BSP_MSTP_REG_FSP_IP_DTC(channel) R_BSP_MSTPCRA + #if BSP_MCU_GROUP_RA8_GEN2 && (1U == BSP_CFG_CPU_CORE) + #define BSP_MSTP_BIT_FSP_IP_DTC(channel) (1U << (23U)); + #else + #define BSP_MSTP_BIT_FSP_IP_DTC(channel) (1U << (22U)); + #endif + #define BSP_MSTP_REG_TYPE_FSP_IP_DTC(channel) uint32_t +#endif +#define BSP_MSTP_REG_FSP_IP_CAN(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_CAN(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_CEC(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_CEC(channel) (1U << (3U)); +#define BSP_MSTP_REG_TYPE_FSP_IP_CEC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_I3C(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_I3C(channel) (1U << (BSP_FEATURE_I3C_MSTP_OFFSET - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_I3C(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_IRDA(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_IRDA(channel) (1U << (5U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_IRDA(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_QSPI(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_QSPI(channel) (1U << (6U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_QSPI(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_SAU(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_SAU(channel) (1U << (6U + channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_SAU(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_IIC(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_IIC(channel) (1U << (9U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_IIC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_IICA(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_IICA(channel) (1U << (10U + channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_IICA(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_USBFS(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_USBFS(channel) (1U << (11U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_USBFS(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_USBHS(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_USBHS(channel) (1U << (12U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_USBHS(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_EPTPC(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_EPTPC(channel) (1U << (13U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_EPTPC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_USBCC(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_USBCC(channel) (1U << (14U)); +#define BSP_MSTP_REG_TYPE_FSP_IP_USBCC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_ETHER(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_ETHER(channel) (1U << (15U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_ETHER(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_UARTA(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_UARTA(channel) (1U << BSP_FEATURE_UARTA_MSTP_OFFSET); +#define BSP_MSTP_REG_TYPE_FSP_IP_UARTA(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_OSPI(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_OSPI(channel) (1U << (16U + channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_OSPI(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_SPI(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_SPI(channel) (1U << (19U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_SPI(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_SCI(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_REG_TYPE_FSP_IP_SCI(channel) uint32_t +#define BSP_MSTP_BIT_FSP_IP_SCI(channel) (1U << (31U - channel)); +#define BSP_MSTP_REG_FSP_IP_CAC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_REG_TYPE_FSP_IP_CAC(channel) uint32_t +#define BSP_MSTP_BIT_FSP_IP_CAC(channel) (1U << (0U - channel)); +#define BSP_MSTP_REG_FSP_IP_CRC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_REG_TYPE_FSP_IP_CRC(channel) uint32_t +#define BSP_MSTP_BIT_FSP_IP_CRC(channel) (1U << (1U - channel)); +#define BSP_MSTP_REG_FSP_IP_PDC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_PDC(channel) (1U << (2U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_PDC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_CTSU(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_CTSU(channel) (1U << (3U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_CTSU(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_SLCDC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SLCDC(channel) (1U << (4U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_SLCDC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_GLCDC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_GLCDC(channel) (1U << (4U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_GLCDC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_JPEG(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_JPEG(channel) (1U << (5U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_JPEG(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_DRW(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_DRW(channel) (1U << (6U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_DRW(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_SSI(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SSI(channel) (1U << (8U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_SSI(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_SRC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SRC(channel) (1U << (9U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_SRC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_MIPI_DSI(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_MIPI_DSI(channel) (1U << (10U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_MIPI_DSI(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_SDHIMMC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SDHIMMC(channel) (1U << (12U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_SDHIMMC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_DOC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_DOC(channel) (1U << (13U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_DOC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_ELC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_ELC(channel) (1U << (14U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_ELC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_MACL(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_MACL(channel) (1U << (15U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_MACL(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_CEU(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_REG_TYPE_FSP_IP_CEU(channel) uint32_t +#define BSP_MSTP_BIT_FSP_IP_CEU(channel) (1U << (16U - channel)); +#define BSP_MSTP_REG_FSP_IP_MIPI_CSI(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_MIPI_CSI(channel) (1U << (17U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_MIPI_CSI(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_TFU(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_TFU(channel) (1U << (20U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_TFU(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_IIRFA(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_IIRFA(channel) (1U << (21U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_IIRFA(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_PDM(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_PDM(channel) (1U << (24U)); +#define BSP_MSTP_REG_TYPE_FSP_IP_PDM(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_CANFD(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_CANFD(channel) (1U << (27U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_CANFD(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_TRNG(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_TRNG(channel) (1U << (28U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_TRNG(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_SCE(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SCE(channel) (1U << (31U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_SCE(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_AES(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_AES(channel) (1U << (31U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_AES(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_TAU(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_TAU(channel) (1U << (0U)); +#define BSP_MSTP_REG_TYPE_FSP_IP_TAU(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_TML(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_TML(channel) (1U << (4U)); +#define BSP_MSTP_REG_TYPE_FSP_IP_TML(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_DSMIF(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_DSMIF(channel) (1U << (9U - channel)); +#define BSP_MSTP_REG_FSP_IP_ADC(channel) R_MSTP->MSTPCRD +#if BSP_MCU_GROUP_RA8_GEN2 + #define BSP_MSTP_BIT_FSP_IP_ADC(channel) (1U << (21U - channel)); +#else + #define BSP_MSTP_BIT_FSP_IP_ADC(channel) (1U << (16U - channel)); +#endif +#define BSP_MSTP_REG_TYPE_FSP_IP_ADC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_SDADC(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_SDADC(channel) (1U << (17U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_SDADC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_DAC(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_DAC(channel) (1U << (20U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_DAC(channel) uint32_t +#if (BSP_PERIPHERAL_DAC8_PRESENT) + #define BSP_MSTP_REG_FSP_IP_DAC8(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_DAC8(channel) (1U << (19U)); + #define BSP_MSTP_REG_TYPE_FSP_IP_DAC8(channel) uint32_t +#endif +#define BSP_MSTP_REG_FSP_IP_TSN(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_TSN(channel) (1U << (22U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_TSN(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_RTC(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_RTC(channel) (1U << (23U)); +#define BSP_MSTP_REG_TYPE_FSP_IP_RTC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_ACMPHS(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_ACMPHS(channel) (1U << (28U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_ACMPHS(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_ACMPLP(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_ACMPLP(channel) (1U << 29U); +#define BSP_MSTP_REG_TYPE_FSP_IP_ACMPLP(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_OPAMP(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_OPAMP(channel) (1U << (31U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_OPAMP(channel) uint32_t + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_ospi_b.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_ospi_b.c new file mode 100644 index 00000000000..11e03626810 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_ospi_b.c @@ -0,0 +1,77 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @defgroup BSP_OSPI_B BSP OSPI_B support + * @ingroup RENESAS_COMMON + * @brief Code that initializes the OSPI_B device memory. + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" + +#if 0 != BSP_FEATURE_OSPI_B_IS_AVAILABLE + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Initializes OSPI_B. + * @param p_startup_fn Function pointer to the method which starts the OSPI and transitions it to the + * appropriate mode. + * @param init_from_sip_memory If true, this function will initialize internal memory regions sourced from SiP Flash. + * + * This function initializes an attached OSPI_B memory device. + * + * @note This function must only be called once after reset. + **********************************************************************************************************************/ +void R_BSP_OspiBInit (bsp_ospi_b_startup_fn_t p_startup_fn, bool init_from_sip_memory) +{ + /* Call the startup function to open the OSPI_B peripheral and put it into the correct mode. */ + if (FSP_SUCCESS != p_startup_fn()) + { + /* If startup fails memory cannot be initialized so return. */ + return; + } + + if (init_from_sip_memory) + { + /* Initialize internal memory regions sourced from SiP Flash. */ + for (uint32_t i = 0; i < g_init_info.copy_count; i++) + { + const bsp_init_copy_info_t * const p_copy = &g_init_info.p_copy_list[i]; + if ((INIT_MEM_SIP_FLASH == p_copy->type.source_type) && !p_copy->type.external) + { + memcpy(p_copy->p_base, p_copy->p_load, ((uint32_t) p_copy->p_limit - (uint32_t) p_copy->p_base)); + } + } + } +} + +#endif + +/** @} (end addtogroup BSP_OSPI_B) */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_ospi_b.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_ospi_b.h new file mode 100644 index 00000000000..ce3e62ad0c6 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_ospi_b.h @@ -0,0 +1,39 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_OSPI_B_H +#define BSP_OSPI_B_H + +#include "bsp_api.h" + +#if 0 != BSP_FEATURE_OSPI_B_IS_AVAILABLE + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +typedef fsp_err_t (* bsp_ospi_b_startup_fn_t)(void); + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +void R_BSP_OspiBInit(bsp_ospi_b_startup_fn_t p_startup_fn, bool init_from_sip_memory); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c new file mode 100644 index 00000000000..f1747b8bc1f --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c @@ -0,0 +1,120 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Key code for writing PRCR register. */ +#define BSP_PRV_PRCR_KEY (0xA500U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/** Used for holding reference counters for protection bits. */ +volatile uint16_t g_protect_counters[5] BSP_SECTION_EARLY_INIT; + +/** Masks for setting or clearing the PRCR register. Use -1 for size because PWPR in MPC is used differently. */ +static const uint16_t g_prcr_masks[] = +{ + 0x0001U, /* PRC0. */ + 0x0002U, /* PRC1. */ + 0x0008U, /* PRC3. */ + 0x0010U, /* PRC4. */ + 0x0020U, /* PRC5. */ +}; + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Enable register protection. Registers that are protected cannot be written to. Register protection is + * enabled by using the Protect Register (PRCR) and the MPC's Write-Protect Register (PWPR). + * + * @param[in] regs_to_protect Registers which have write protection enabled. + **********************************************************************************************************************/ +void R_BSP_RegisterProtectEnable (bsp_reg_protect_t regs_to_protect) +{ + /** Get/save the current state of interrupts */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* Is it safe to disable write access? */ + if (0U != g_protect_counters[regs_to_protect]) + { + /* Decrement the protect counter */ + g_protect_counters[regs_to_protect]--; + } + + /* Is it safe to disable write access? */ + if (0U == g_protect_counters[regs_to_protect]) + { + /** Enable protection using PRCR register. + * + * When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to + * disable writes. */ +#if BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 + R_SYSTEM->PRCR_NS = ((R_SYSTEM->PRCR_NS | BSP_PRV_PRCR_KEY) & (uint16_t) (~g_prcr_masks[regs_to_protect])); +#else + R_SYSTEM->PRCR = ((R_SYSTEM->PRCR | BSP_PRV_PRCR_KEY) & (uint16_t) (~g_prcr_masks[regs_to_protect])); +#endif + } + + /** Restore the interrupt state */ + FSP_CRITICAL_SECTION_EXIT; +} + +/*******************************************************************************************************************//** + * Disable register protection. Registers that are protected cannot be written to. Register protection is + * disabled by using the Protect Register (PRCR) and the MPC's Write-Protect Register (PWPR). + * + * @param[in] regs_to_unprotect Registers which have write protection disabled. + **********************************************************************************************************************/ +void R_BSP_RegisterProtectDisable (bsp_reg_protect_t regs_to_unprotect) +{ + /** Get/save the current state of interrupts */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* If this is first entry then disable protection. */ + if (0U == g_protect_counters[regs_to_unprotect]) + { + /** Disable protection using PRCR register. + * + * When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to + * disable writes. */ +#if BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 + R_SYSTEM->PRCR_NS = ((R_SYSTEM->PRCR_NS | BSP_PRV_PRCR_KEY) | g_prcr_masks[regs_to_unprotect]); +#else + R_SYSTEM->PRCR = ((R_SYSTEM->PRCR | BSP_PRV_PRCR_KEY) | g_prcr_masks[regs_to_unprotect]); +#endif + } + + /** Increment the protect counter */ + g_protect_counters[regs_to_unprotect]++; + + /** Restore the interrupt state */ + FSP_CRITICAL_SECTION_EXIT; +} + +/** @} (end addtogroup BSP_MCU) */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h new file mode 100644 index 00000000000..171a2f69ba2 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h @@ -0,0 +1,63 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_REGISTER_PROTECTION_H +#define BSP_REGISTER_PROTECTION_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/** The different types of registers that can be protected. */ +typedef enum e_bsp_reg_protect +{ + /** Enables writing to the registers related to the clock generation circuit. */ + BSP_REG_PROTECT_CGC = 0, + + /** Enables writing to the registers related to operating modes, low power consumption, and battery backup + * function. */ + BSP_REG_PROTECT_OM_LPC_BATT, + + /** Enables writing to the registers related to the LVD: LVCMPCR, LVDLVLR, LVD1CR0, LVD1CR1, LVD1SR, LVD2CR0, + * LVD2CR1, LVD2SR. */ + BSP_REG_PROTECT_LVD, + + /** Enables writing to the registers related to the security function. */ + BSP_REG_PROTECT_SAR, + + /** Enables writing to the registers related to reset control. */ + BSP_REG_PROTECT_RESET, +} bsp_reg_protect_t; + +/** @} (end addtogroup BSP_MCU) */ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/* Public functions defined in bsp.h */ +void bsp_register_protect_open(void); // Used internally by BSP + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c new file mode 100644 index 00000000000..b58e49fed21 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c @@ -0,0 +1,104 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) +#include "bsp_api.h" +#include +#include + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +#if defined(__llvm__) +void * sbrk(ptrdiff_t incr); + +#else +caddr_t _sbrk(int incr); + +#endif + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * FSP implementation of the standard library _sbrk() function. + * @param[in] inc The number of bytes being asked for by malloc(). + * + * @note This function overrides the _sbrk version that exists in the newlib library that is linked with. + * That version improperly relies on the SP as part of it's allocation strategy. This is bad in general and + * worse in an RTOS environment. This version insures that we allocate the byte pool requested by malloc() + * only from our allocated HEAP area. Also note that newlib is pre-built and forces the pagesize used by + * malloc() to be 4096. That requires that we have a HEAP of at least 4096 if we are to support malloc(). + * @retval Address of allocated area if successful, -1 otherwise. + **********************************************************************************************************************/ + +#if defined(__llvm__) +void * sbrk (ptrdiff_t incr) +#else +caddr_t _sbrk (int incr) +#endif +{ +#if (BSP_CFG_HEAP_BYTES > 0) + extern uint8_t g_heap[BSP_CFG_HEAP_BYTES]; + + uint32_t bytes = (uint32_t) incr; + static uint32_t current_block_offset = 0; + char * current_block_address; + + current_block_address = (char *) &g_heap[current_block_offset]; + + /* The returned address must be aligned to a word boundary to prevent hard faults on cores that do not support + * unaligned access. We assume the heap starts on a word boundary and make sure all allocations are a multiple + * of 4. */ + bytes = (bytes + 3U) & (~3U); + if (current_block_offset + bytes > BSP_CFG_HEAP_BYTES) + { + /** Heap has overflowed */ + errno = ENOMEM; + + return (caddr_t) -1; + } + + current_block_offset += bytes; + + return (caddr_t) current_block_address; +#else + FSP_PARAMETER_NOT_USED(incr); + + /** Heap not allocated!!! */ + errno = ENOMEM; + + return (caddr_t) -1; +#endif +} + +#endif + +/******************************************************************************************************************//** + * @} (end addtogroup BSP_MCU) + *********************************************************************************************************************/ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_sdram.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_sdram.c new file mode 100644 index 00000000000..22999c9274a --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_sdram.c @@ -0,0 +1,199 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @defgroup BSP_SDRAM BSP SDRAM support + * @ingroup RENESAS_COMMON + * @brief Code that initializes the SDRAMC and SDR SDRAM device memory. + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Due to hardware limitations of the SDRAM peripheral, + * it is not expected any of these need to be changeable by end user. + * Only sequential, single access at a time is supported. */ +#define BSP_PRV_SDRAM_MR_WB_SINGLE_LOC_ACC (1U) /* MR.M9 : Single Location Access */ +#define BSP_PRV_SDRAM_MR_OP_MODE (0U) /* MR.M8:M7 : Standard Operation */ +#define BSP_PRV_SDRAM_MR_BT_SEQUENTIAL (0U) /* MR.M3 Burst Type : Sequential */ +#define BSP_PRV_SDRAM_MR_BURST_LENGTH (0U) /* MR.M2:M0 Burst Length: 0(1 burst) */ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +#if 0 != BSP_FEATURE_SDRAM_START_ADDRESS + +/*******************************************************************************************************************//** + * @brief Initializes SDRAM. + * @param init_memory If true, this function will execute the initialization of the external modules. + * Otherwise, it will only initialize the SDRAMC and leave the memory in self-refresh mode. + * + * This function initializes SDRAMC and SDR SDRAM device. + * + * @note This function must only be called once after reset. + **********************************************************************************************************************/ +void R_BSP_SdramInit (bool init_memory) +{ + /** Setting for SDRAM initialization sequence */ + while (R_BUS->SDRAM.SDSR) + { + /* According to h/w manual, need to confirm that all the status bits in SDSR are 0 before SDICR modification. */ + } + + /* Must only write to SDIR once after reset. */ + R_BUS->SDRAM.SDIR = ((BSP_CFG_SDRAM_INIT_ARFI - 3U) << R_BUS_SDRAM_SDIR_ARFI_Pos) | + (BSP_CFG_SDRAM_INIT_ARFC << R_BUS_SDRAM_SDIR_ARFC_Pos) | + ((BSP_CFG_SDRAM_INIT_PRC - 3U) << R_BUS_SDRAM_SDIR_PRC_Pos); + + R_BUS->SDRAM.SDCCR = (BSP_CFG_SDRAM_BUS_WIDTH << R_BUS_SDRAM_SDCCR_BSIZE_Pos); /* set SDRAM bus width */ + + if (init_memory) + { + /* Enable the SDCLK output. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_CGC); + R_SYSTEM->SDCKOCR = 1; + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_CGC); + + /** If requested, start SDRAM initialization sequence. */ + R_BUS->SDRAM.SDICR = 1U; + while (R_BUS->SDRAM.SDSR_b.INIST) + { + /* Wait the end of initialization sequence. */ + } + } + + /** Setting for SDRAM controller */ + R_BUS->SDRAM.SDAMOD = BSP_CFG_SDRAM_ACCESS_MODE; /* enable continuous access */ + R_BUS->SDRAM.SDCMOD = BSP_CFG_SDRAM_ENDIAN_MODE; /* set endian mode for SDRAM address space */ + + while (R_BUS->SDRAM.SDSR) + { + /* According to h/w manual, need to confirm that all the status bits in SDSR are 0 before SDMOD modification. */ + } + + if (init_memory) + { + /** Using LMR command, program the mode register */ + R_BUS->SDRAM.SDMOD = (BSP_PRV_SDRAM_MR_WB_SINGLE_LOC_ACC << 9) | + (BSP_PRV_SDRAM_MR_OP_MODE << 7) | + (BSP_CFG_SDRAM_TCL << 4) | + (BSP_PRV_SDRAM_MR_BT_SEQUENTIAL << 3) | + (BSP_PRV_SDRAM_MR_BURST_LENGTH << 0); + + /** wait at least tMRD time */ + while (R_BUS->SDRAM.SDSR_b.MRSST) + { + /* Wait until Mode Register setting done. */ + } + } + + /** Set timing parameters for SDRAM. Must do in single write. */ + R_BUS->SDRAM.SDTR = ((BSP_CFG_SDRAM_TRAS - 1U) << R_BUS_SDRAM_SDTR_RAS_Pos) | + ((BSP_CFG_SDRAM_TRCD - 1U) << R_BUS_SDRAM_SDTR_RCD_Pos) | + ((BSP_CFG_SDRAM_TRP - 1U) << R_BUS_SDRAM_SDTR_RP_Pos) | + ((BSP_CFG_SDRAM_TWR - 1U) << R_BUS_SDRAM_SDTR_WR_Pos) | + (BSP_CFG_SDRAM_TCL << R_BUS_SDRAM_SDTR_CL_Pos); + + /** Set row address offset for target SDRAM */ + R_BUS->SDRAM.SDADR = BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT; + + /* Set Auto-Refresh timings. */ + R_BUS->SDRAM.SDRFCR = ((BSP_CFG_SDRAM_TREFW - 1U) << R_BUS_SDRAM_SDRFCR_REFW_Pos) | + ((BSP_CFG_SDRAM_TRFC - 1U) << R_BUS_SDRAM_SDRFCR_RFC_Pos); + + /** Start Auto-refresh */ + R_BUS->SDRAM.SDRFEN = 1U; + + if (init_memory) + { + /** Enable SDRAM access */ + R_BUS->SDRAM.SDCCR = R_BUS_SDRAM_SDCCR_EXENB_Msk | (BSP_CFG_SDRAM_BUS_WIDTH << R_BUS_SDRAM_SDCCR_BSIZE_Pos); + } + else + { + /* If not initializing memory modules, start in self-refresh mode. */ + while (R_BUS->SDRAM.SDCCR_b.EXENB || (0U != R_BUS->SDRAM.SDSR)) + { + /* Wait for access to be disabled and no status bits set. */ + } + + /* Enable the self-refresh mode. */ + R_BUS->SDRAM.SDSELF = 1U; + } +} + +/*******************************************************************************************************************//** + * @brief Changes SDRAM from Auto-refresh to Self-refresh + * + * This function allows Software Standby and Deep Software Standby modes to be entered without data loss. + * + * @note SDRAM cannot be accessed after calling this function. Use @ref R_BSP_SdramSelfRefreshDisable to resume normal + * SDRAM operation. + **********************************************************************************************************************/ +void R_BSP_SdramSelfRefreshEnable (void) +{ + R_BUS->SDRAM.SDCCR = (BSP_CFG_SDRAM_BUS_WIDTH << R_BUS_SDRAM_SDCCR_BSIZE_Pos); + while (R_BUS->SDRAM.SDCCR_b.EXENB || (0U != R_BUS->SDRAM.SDSR)) + { + /* Wait for access to be disabled and no status bits set. */ + } + + /* Enable the self-refresh mode. */ + R_BUS->SDRAM.SDSELF = 1U; +} + +/*******************************************************************************************************************//** + * @brief Changes SDRAM from Self-refresh to Auto-refresh + * + * This function changes back to Auto-refresh and allows normal SDRAM operation to resume. + * + **********************************************************************************************************************/ +void R_BSP_SdramSelfRefreshDisable (void) +{ + if (0 == R_SYSTEM->SDCKOCR) + { + /* Enable the SDCLK output. It may not already be enabled here if recovering from Deep Software Standby. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_CGC); + R_SYSTEM->SDCKOCR = 1; + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_CGC); + } + + while (0U != R_BUS->SDRAM.SDSR) + { + /* Wait for all status bits to be cleared. */ + } + + /* Disable the self-refresh mode. */ + R_BUS->SDRAM.SDSELF = 0U; + + /* Reenable SDRAM bus access. */ + R_BUS->SDRAM.SDCCR = R_BUS_SDRAM_SDCCR_EXENB_Msk | (BSP_CFG_SDRAM_BUS_WIDTH << R_BUS_SDRAM_SDCCR_BSIZE_Pos); +} + +#endif + +/** @} (end addtogroup BSP_SDRAM) */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_sdram.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_sdram.h new file mode 100644 index 00000000000..5ba56a63830 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_sdram.h @@ -0,0 +1,37 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_SDRAM_H +#define BSP_SDRAM_H + +#if 0 != BSP_FEATURE_SDRAM_START_ADDRESS + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +void R_BSP_SdramInit(bool init_memory); +void R_BSP_SdramSelfRefreshEnable(void); +void R_BSP_SdramSelfRefreshDisable(void); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_security.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_security.c new file mode 100644 index 00000000000..5feceda11ca --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_security.c @@ -0,0 +1,563 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +#if BSP_FEATURE_TZ_HAS_TRUSTZONE + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + #define BSP_PRV_TZ_REG_KEY (0xA500U) + #define BSP_PRV_AIRCR_VECTKEY (0x05FA0000U) + #define RA_NOT_DEFINED (0) + +/* Branch T3 Instruction (IMM11=-2) */ + #define BSP_PRV_INFINITE_LOOP (0xE7FE) + + #define BSP_SAU_REGION_CODE_FLASH_NSC (0U) + #define BSP_SAU_REGION_1_NS (1U) + #define BSP_SAU_REGION_SRAM_NSC (2U) + #define BSP_SAU_REGION_2_NS (3U) + #define BSP_SAU_REGION_3_NS (4U) + +/* Non-secure regions defined by the IDAU. These regions must be defined as non-secure in the SAU. */ + #define BSP_PRV_SAU_NS_REGION_1_BASE_ADDRESS (0x10000000U) + #define BSP_PRV_SAU_NS_REGION_1_LIMIT_ADDRESS (0x1FFFFFFFU) + #define BSP_PRV_SAU_NS_REGION_2_BASE_ADDRESS (0x30000000U) + #define BSP_PRV_SAU_NS_REGION_2_LIMIT_ADDRESS (0x3FFFFFFFU) + #define BSP_PRV_SAU_NS_REGION_3_BASE_ADDRESS (0x50000000U) + #define BSP_PRV_SAU_NS_REGION_3_LIMIT_ADDRESS (0xDFFFFFFFU) + +/* Protect DMAST/DTCST from nonsecure write access. */ + #if (1U == BSP_CFG_CPU_CORE) + #define DMACX_REGISTER_SHIFT (16) + #define DTCX_REGISTER_SHIFT (16) + #else + #define DMACX_REGISTER_SHIFT (0) + #define DTCX_REGISTER_SHIFT (0) + #endif + +/* Macros to align to next memory region for TZ (mainly to "find" NS locations) */ + #if defined(BSP_PARTITION_FLASH_CPU0_S_START) && (0U == BSP_CFG_CPU_CORE) + +/* Use partition macros for primary core */ + #define FLASH_NSC_START ((uint32_t *) BSP_PARTITION_FLASH_CPU0_C_START) + #define FLASH_NSC_LIMIT ((uint32_t) BSP_PARTITION_FLASH_CPU0_C_START + BSP_PARTITION_FLASH_CPU0_C_SIZE - 1) + #define FLASH_NS_START ((uint32_t *) BSP_PARTITION_FLASH_CPU0_N_START) + #define RAM_NSC_START ((uint32_t *) BSP_PARTITION_RAM_CPU0_C_START) + #define RAM_NSC_LIMIT ((uint32_t) BSP_PARTITION_RAM_CPU0_C_START + BSP_PARTITION_RAM_CPU0_C_SIZE - 1) + #define RAM_NS_START ((uint32_t *) BSP_PARTITION_RAM_CPU0_N_START) + #define DATA_FLASH_NS_START ((uint32_t *) BSP_PARTITION_DATA_FLASH_CPU0_N_START) + + #elif defined(BSP_PARTITION_FLASH_CPU1_S_START) && (1U == BSP_CFG_CPU_CORE) + +/* Use partition macros for secondary core */ + #define FLASH_NSC_START ((uint32_t *) BSP_PARTITION_FLASH_CPU1_C_START) + #define FLASH_NSC_LIMIT ((uint32_t) BSP_PARTITION_FLASH_CPU1_C_START + BSP_PARTITION_FLASH_CPU1_C_SIZE - 1) + #define FLASH_NS_START ((uint32_t *) BSP_PARTITION_FLASH_CPU1_N_START) + #define RAM_NSC_START ((uint32_t *) BSP_PARTITION_RAM_CPU1_C_START) + #define RAM_NSC_LIMIT ((uint32_t) BSP_PARTITION_RAM_CPU1_C_START + BSP_PARTITION_RAM_CPU1_C_SIZE - 1) + #define RAM_NS_START ((uint32_t *) BSP_PARTITION_RAM_CPU1_N_START) + #define DATA_FLASH_NS_START ((uint32_t *) BSP_PARTITION_DATA_FLASH_CPU1_N_START) + + #else + +/* Use legacy tail-chaining to find NS */ + #define FLASH_NS_START ((uint32_t *) ((((uint32_t) gp_ddsc_FLASH_END + 0x8000 - 1) & \ + 0xFFFF8000) | BSP_FEATURE_TZ_NS_OFFSET)) + #define FLASH_NSC_START ((uint32_t *) gp_ddsc_FLASH_NSC) + #define FLASH_NSC_LIMIT (((uint32_t) FLASH_NS_START & ~BSP_FEATURE_TZ_NS_OFFSET) - 1U) + #define RAM_NS_START ((uint32_t *) ((((uint32_t) gp_ddsc_RAM_END + 0x2000 - 1) & \ + 0xFFFFE000) | BSP_FEATURE_TZ_NS_OFFSET)) + #define RAM_NSC_START ((uint32_t *) gp_ddsc_RAM_NSC) + #define RAM_NSC_LIMIT (((uint32_t) RAM_NS_START & ~BSP_FEATURE_TZ_NS_OFFSET) - 1U) + #define DATA_FLASH_NS_START ((uint32_t *) ((((uint32_t) gp_ddsc_DATA_FLASH_END + 0x400 - 1) & \ + 0xFFFFFC00) | BSP_FEATURE_TZ_NS_OFFSET)) + + #endif + + #define RAM_NS_START_S_ALIAS ((uint32_t *) ((uint32_t) RAM_NS_START & ~BSP_FEATURE_TZ_NS_OFFSET)) + +/* Operation after detection registers. + * RA8 devices have the registers under MSA/BUS while other devices have them under TZF. */ + #ifdef R_TZF + #define BSP_PRV_OAD_REG R_TZF->TZFOAD + #define BSP_PRV_OAD_PT_REG R_TZF->TZFPT + #else + #define BSP_PRV_OAD_REG R_BUS->OAD.MSAOAD + #define BSP_PRV_OAD_PT_REG R_BUS->OAD.MSAPT + #endif + + #if BSP_SECONDARY_CORE_BUILD + +/* For a secure secondary core the SAR has already been written so it + * only needs to modify the security attributes it is using: + * - Secure (0) will always stay Secure + * - Non-secure (1) will either stay non-secure or become secure + * This is the same as using a bitwise AND. + */ + #define BSP_PRV_SAR_WRITE(register, value) register &= value + #else + #define BSP_PRV_SAR_WRITE(register, value) register = value + #endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ +void R_BSP_SAUInit(void); +void R_BSP_SecurityInit(void); +void R_BSP_PinCfgSecurityInit(void); +void R_BSP_ElcCfgSecurityInit(void); + +/*********************************************************************************************************************** + * External symbols + **********************************************************************************************************************/ + + #if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * bsp_nonsecure_func_t)(void); + #elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile bsp_nonsecure_func_t)(void); + #endif + + #if BSP_TZ_SECURE_BUILD + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Enter the non-secure code environment. + * + * This function configures the non-secure MSP and vector table then jumps to the non-secure project's Reset_Handler. + * + * @note This function (and therefore the non-secure code) should not return. + **********************************************************************************************************************/ +void R_BSP_NonSecureEnter (void) +{ + /* The NS vector table is at the start of the NS section in flash */ + uint32_t const * p_ns_vector_table = FLASH_NS_START; + + /* Set up the NS Reset_Handler to be called */ + uint32_t const * p_ns_reset_address = (uint32_t const *) ((uint32_t) p_ns_vector_table + sizeof(uint32_t)); + bsp_nonsecure_func_t p_ns_reset = (bsp_nonsecure_func_t) (*p_ns_reset_address); + + #if BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK + + /* Check if the NS application exists. If the address of the Reset_Handler is all '1's, then assume that + * the NS application has not been programmed. + * + * If the secure application attempts to jump to an invalid instruction, a HardFault will occur. If the + * MCU is in NSECSD state, then the debugger will be unable to connect and program the NS Application. Jumping to + * a valid instruction ensures that the debugger will be able to connect. + */ + if (UINT32_MAX == *p_ns_reset_address) + { + p_ns_reset = (bsp_nonsecure_func_t) ((uint32_t) RAM_NS_START); + + /* Write an infinite loop into start of NS RAM (Branch T3 Instruction (b.n )). */ + uint16_t * infinite_loop = (uint16_t *) ((uint32_t) RAM_NS_START); + *infinite_loop = BSP_PRV_INFINITE_LOOP; + + /* Set the NS stack pointer to a valid location in NS RAM. */ + __TZ_set_MSP_NS((uint32_t) RAM_NS_START + 0x20U); + + /* Jump to the infinite loop. */ + p_ns_reset(); + } + #endif + + /* Set the NS vector table address */ + SCB_NS->VTOR = (uint32_t) p_ns_vector_table; + + /* Set the NS stack pointer to the first entry in the NS vector table */ + __TZ_set_MSP_NS(p_ns_vector_table[0]); + + /* Jump to the NS Reset_Handler */ + p_ns_reset(); +} + +/** @} (end addtogroup BSP_MCU) */ + +/*******************************************************************************************************************//** + * Initialize SAU regions for TrustZone. + * + * This function initializes ARM SAU regions for secure projects. + * + * @note IDAU settings must be configured to match project settings with a separate configuration tool. + **********************************************************************************************************************/ +void R_BSP_SAUInit (void) +{ + #if __SAUREGION_PRESENT + #if !BSP_SECONDARY_CORE_BUILD + + /* Configure IDAU to divide SRAM region into NSC/NS. */ + R_CPSCU->SRAMSABAR0 = (uint32_t) RAM_NS_START_S_ALIAS & R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk; + R_CPSCU->SRAMSABAR1 = (uint32_t) RAM_NS_START_S_ALIAS & R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk; + #if BSP_FEATURE_SRAM_HAS_EXTRA_SRAMSABAR + R_CPSCU->SRAMSABAR2 = (uint32_t) RAM_NS_START_S_ALIAS & R_CPSCU_SRAMSABAR2_SRAMSABAR_Msk; + R_CPSCU->SRAMSABAR3 = (uint32_t) RAM_NS_START_S_ALIAS & R_CPSCU_SRAMSABAR3_SRAMSABAR_Msk; + #endif + + #ifdef BSP_TZ_CFG_SRAMESAR + + /* Configure SRAM ECC Region as S/NS */ + R_CPSCU->SRAMESAR = BSP_TZ_CFG_SRAMESAR; + #endif + #endif + + /* Configure SAU region used for Code Flash Non-secure callable. */ + SAU->RNR = BSP_SAU_REGION_CODE_FLASH_NSC; + SAU->RBAR = (uint32_t) FLASH_NSC_START & SAU_RBAR_BADDR_Msk; + SAU->RLAR = (FLASH_NSC_LIMIT & SAU_RLAR_LADDR_Msk) | SAU_RLAR_NSC_Msk | + SAU_RLAR_ENABLE_Msk; + + /* Configure SAU region used for Non-secure region 1: + * - ITCM + * - Code Flash + * - On-chip flash (Factory Flash) + * - On-chip flash (option-setting memory) + */ + SAU->RNR = BSP_SAU_REGION_1_NS; + SAU->RBAR = (uint32_t) BSP_PRV_SAU_NS_REGION_1_BASE_ADDRESS & SAU_RBAR_BADDR_Msk; + SAU->RLAR = ((BSP_PRV_SAU_NS_REGION_1_LIMIT_ADDRESS) &SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; + + /* Configure SAU region used for Non-secure callable SRAM. */ + SAU->RNR = BSP_SAU_REGION_SRAM_NSC; + SAU->RBAR = (uint32_t) RAM_NSC_START & SAU_RBAR_BADDR_Msk; + SAU->RLAR = (RAM_NSC_LIMIT & SAU_RLAR_LADDR_Msk) | SAU_RLAR_NSC_Msk | + SAU_RLAR_ENABLE_Msk; + + /* Configure SAU region used for Non-secure region 2: + * - DTCM + * - On-chip SRAM + * - Standby SRAM + * - On-chip flash (data flash) + */ + SAU->RNR = BSP_SAU_REGION_2_NS; + SAU->RBAR = ((uint32_t) BSP_PRV_SAU_NS_REGION_2_BASE_ADDRESS & SAU_RBAR_BADDR_Msk) | BSP_FEATURE_TZ_NS_OFFSET; + SAU->RLAR = (BSP_PRV_SAU_NS_REGION_2_LIMIT_ADDRESS & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; + + /* Configure SAU region used for Non-secure region 3: + * - Peripheral I/O registers + * - Flash I/O registers + * - External address space (CS area) + * - External address space (SDRAM area) + * - External address space (OSPI area) + */ + SAU->RNR = BSP_SAU_REGION_3_NS; + SAU->RBAR = BSP_PRV_SAU_NS_REGION_3_BASE_ADDRESS & SAU_RBAR_BADDR_Msk; + SAU->RLAR = (BSP_PRV_SAU_NS_REGION_3_LIMIT_ADDRESS & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; + + /* Enable the SAU. */ + SAU->CTRL = SAU_CTRL_ENABLE_Msk; + + #if __ICACHE_PRESENT == 1U + + /* Cache maintenance is required when changing security attribution of an address. + * Barrier instructions are required to guarantee intended operation + * (See Arm Cortex-M85 Technical Reference Manual Section 10.9.3). */ + SCB_InvalidateICache(); + #endif + #else + + /* Setting SAU_CTRL.ALLNS to 1 allows the security attribution of all addresses to be set by the IDAU in the + * system. */ + SAU->CTRL = SAU_CTRL_ALLNS_Msk; + #endif +} + +/*******************************************************************************************************************//** + * Initialize security features for TrustZone. + * + * This function initializes ARM security register and Renesas SAR registers for secure projects. + * + * @note IDAU settings must be configured to match project settings with a separate configuration tool. + **********************************************************************************************************************/ +void R_BSP_SecurityInit (void) +{ + /* Disable PRCR for SARs. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); + + #if 0 == BSP_FEATURE_TZ_HAS_DLM + + /* If DLM is not implemented, then the TrustZone partitions must be set at run-time. */ + R_PSCU->CFSAMONA = (uint32_t) FLASH_NS_START & ~BSP_FEATURE_TZ_NS_OFFSET & R_PSCU_CFSAMONA_CFS2_Msk; + R_PSCU->CFSAMONB = (uint32_t) FLASH_NSC_START & R_PSCU_CFSAMONB_CFS1_Msk; + R_PSCU->DFSAMON = (uint32_t) DATA_FLASH_NS_START & R_PSCU_DFSAMON_DFS_Msk; + R_PSCU->SSAMONA = (uint32_t) RAM_NS_START_S_ALIAS & R_PSCU_SSAMONA_SS2_Msk; + R_PSCU->SSAMONB = (uint32_t) RAM_NSC_START & R_PSCU_SSAMONB_SS1_Msk; + #endif + + #if (BSP_CFG_CPU_CORE == 0) && (BSP_FEATURE_BSP_HAS_ITCM) + + /* Total ITCM block size in bytes is equal to 2 ^ (BLKSZ + 5). */ + uint32_t itcm_block_exponent = + ((MEMSYSCTL->ITGU_CFG & MEMSYSCTL_ITGU_CFG_BLKSZ_Msk) >> MEMSYSCTL_ITGU_CFG_BLKSZ_Pos) + + 5U; + uint32_t itcm_block_size = (1U << itcm_block_exponent); + + /* The number of secure ITCM blocks is equal to size of the secure region in bytes divided by the ITCM block size. */ + uint32_t itcm_num_sec_blocks = + ((uint32_t) gp_ddsc_ITCM_END + itcm_block_size - 1 - (uint32_t) gp_ddsc_ITCM_START) >> + itcm_block_exponent; + + /* Set all secure blocks to '0' and all non-secure blocks to 1. */ + MEMSYSCTL->ITGU_LUT[0] = ~((1U << itcm_num_sec_blocks) - 1U); + #endif + + #if (BSP_CFG_CPU_CORE == 0) && (BSP_FEATURE_BSP_HAS_DTCM) + + /* Total DTCM block size in bytes is equal to 2 ^ (BLKSZ + 5). */ + uint32_t dtcm_block_exponent = + ((MEMSYSCTL->DTGU_CFG & MEMSYSCTL_DTGU_CFG_BLKSZ_Msk) >> MEMSYSCTL_DTGU_CFG_BLKSZ_Pos) + + 5U; + uint32_t dtcm_block_size = (1U << dtcm_block_exponent); + + /* The number of secure DTCM blocks is equal to size of the secure region in bytes divided by the DTCM block size. */ + uint32_t dtcm_num_sec_blocks = + ((uint32_t) gp_ddsc_DTCM_END + dtcm_block_size - 1 - (uint32_t) gp_ddsc_DTCM_START) >> + dtcm_block_exponent; + + /* Set all secure blocks to '0' and all non-secure blocks to 1. */ + MEMSYSCTL->DTGU_LUT[0] = ~((1U << dtcm_num_sec_blocks) - 1U); + #endif + + #if (BSP_CFG_CPU_CORE == 1) && defined(R_TCM) + #ifdef BSP_PARTITION_CTCM_CPU1_S_START + + /* Set boundary address for CTCM S/NS */ + R_CPSCU->TCMSABARC = BSP_PARTITION_CTCM_CPU1_S_START + BSP_PARTITION_CTCM_CPU1_S_SIZE; + #endif + #ifdef BSP_PARTITION_STCM_CPU1_S_START + + /* Set boundary address for STCM S/NS */ + R_CPSCU->TCMSABARS = BSP_PARTITION_STCM_CPU1_S_START + BSP_PARTITION_STCM_CPU1_S_SIZE; + #endif + #endif + + #if !BSP_SECONDARY_CORE_BUILD + + /* Skip SAU init on secondary build since it is being done earlier in system initialization. */ + R_BSP_SAUInit(); + #endif + + /* The following section of code to configure SCB->AIRCR, SCB->NSACR, and FPU->FPCCR is taken from + * system_ARMCM33.c in the CMSIS_5 repository. SCB->SCR SLEEPDEEPS bit is not configured because the + * SCB->SCR SLEEPDEEP bit is ignored on RA MCUs. */ + #if defined(SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + + /* Configure whether non-secure projects have access to system reset, whether bus fault, hard fault, and NMI target + * secure or non-secure, and whether non-secure interrupt priorities are reduced to the lowest 8 priority levels. */ + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk)) | + BSP_PRV_AIRCR_VECTKEY | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif + + #if defined(__FPU_USED) && (__FPU_USED == 1U) && \ + defined(TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + /* Configure whether the FPU can be accessed in the non-secure project. */ + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + /* Configure whether FPU registers are always treated as non-secure (and therefore not preserved on the stack when + * switching from secure to non-secure), and whether the FPU registers should be cleared on exception return. */ + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos) & FPU_FPCCR_TS_Msk) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos) & FPU_FPCCR_CLRONRET_Msk); + #endif + + #if !BSP_SECONDARY_CORE_BUILD + #if BSP_FEATURE_TZ_HAS_TZFSAR + + /* Set TrustZone filter to Secure. */ + R_CPSCU->TZFSAR = ~R_CPSCU_TZFSAR_TZFSA0_Msk; + #endif + + /* Set TrustZone filter exception response. */ + BSP_PRV_OAD_PT_REG = BSP_PRV_TZ_REG_KEY + 1U; + BSP_PRV_OAD_REG = BSP_PRV_TZ_REG_KEY + BSP_TZ_CFG_EXCEPTION_RESPONSE; + BSP_PRV_OAD_PT_REG = BSP_PRV_TZ_REG_KEY + 0U; + #endif + + /* Initialize PSARs. */ + BSP_PRV_SAR_WRITE(R_PSCU->PSARB, BSP_TZ_CFG_PSARB); + BSP_PRV_SAR_WRITE(R_PSCU->PSARC, BSP_TZ_CFG_PSARC); + BSP_PRV_SAR_WRITE(R_PSCU->PSARD, BSP_TZ_CFG_PSARD); + BSP_PRV_SAR_WRITE(R_PSCU->PSARE, BSP_TZ_CFG_PSARE); + + #if !BSP_SECONDARY_CORE_BUILD + R_PSCU->MSSAR = BSP_TZ_CFG_MSSAR; + #endif + + /* Initialize Type 2 SARs. */ + #ifdef BSP_TZ_CFG_CSAR + R_CPSCU->CSAR = BSP_TZ_CFG_CSAR; /* Cache Security Attribution. */ + #endif + #ifdef BSP_TZ_CFG_CACHESAR + R_CPSCU->CACHESAR = BSP_TZ_CFG_CACHESAR; /* Cache Security Attribution. */ + #endif + #if !BSP_SECONDARY_CORE_BUILD + R_SYSTEM->RSTSAR = BSP_TZ_CFG_RSTSAR; /* RSTSRn Security Attribution. */ + #endif + BSP_PRV_SAR_WRITE(R_SYSTEM->LVDSAR, BSP_TZ_CFG_LVDSAR); /* LVD Security Attribution. */ + + #if !BSP_SECONDARY_CORE_BUILD + R_SYSTEM->CGFSAR = BSP_TZ_CFG_CGFSAR; /* CGC Security Attribution. */ + R_SYSTEM->LPMSAR = BSP_TZ_CFG_LPMSAR; /* LPM Security Attribution. */ + #ifdef BSP_TZ_CFG_DPFSAR + R_SYSTEM->DPFSAR = BSP_TZ_CFG_DPFSAR; /* Deep Standby Interrupt Factor Security Attribution. */ + #endif + #ifdef BSP_TZ_CFG_RSCSAR + R_SYSTEM->RSCSAR = BSP_TZ_CFG_RSCSAR; /* RAM Standby Control Security Attribution. */ + #endif + #ifdef BSP_TZ_CFG_PGCSAR + R_SYSTEM->PGCSAR = BSP_TZ_CFG_PGCSAR; /* Power Gating Control Security Attribution. */ + #endif + #ifdef BSP_TZ_CFG_BBFSAR + R_SYSTEM->BBFSAR = BSP_TZ_CFG_BBFSAR; /* Battery Backup Security Attribution. */ + #endif + #ifdef BSP_TZ_CFG_VBRSABAR + R_SYSTEM->VBRSABAR = BSP_TZ_CFG_VBRSABAR; /* Battery Backup Security Attribution (VBTBKRn). */ + #endif + #endif + + BSP_PRV_SAR_WRITE(R_CPSCU->ICUSARA, BSP_TZ_CFG_ICUSARA); /* External IRQ Security Attribution. */ + BSP_PRV_SAR_WRITE(R_CPSCU->ICUSARB, BSP_TZ_CFG_ICUSARB); /* NMI Security Attribution. */ + + #if !BSP_SECONDARY_CORE_BUILD + #ifdef BSP_TZ_CFG_ICUSARC + R_CPSCU->ICUSARC = BSP_TZ_CFG_ICUSARC; /* DMAC Channel Security Attribution. */ + #endif + #endif + + #ifdef BSP_TZ_CFG_DMACCHSAR + R_CPSCU->DMACCHSAR |= (BSP_TZ_CFG_DMACCHSAR << DMACX_REGISTER_SHIFT); /* DMAC Channel Security Attribution. */ + #endif + + #if !BSP_SECONDARY_CORE_BUILD + #ifdef BSP_TZ_CFG_ICUSARD + R_CPSCU->ICUSARD = BSP_TZ_CFG_ICUSARD; /* SELSR0 Security Attribution. */ + #endif + R_CPSCU->ICUSARE = BSP_TZ_CFG_ICUSARE; /* WUPEN0 Security Attribution. */ + #ifdef BSP_TZ_CFG_ICUSARF + R_CPSCU->ICUSARF = BSP_TZ_CFG_ICUSARF; /* WUPEN1 Security Attribution. */ + #endif + #ifdef BSP_TZ_CFG_TEVTRCR + R_CPSCU->TEVTRCR = BSP_TZ_CFG_TEVTRCR; /* Trusted Event Route Enable. */ + #endif + #ifdef BSP_TZ_CFG_ELCSARA + R_ELC->ELCSARA = BSP_TZ_CFG_ELCSARA; /* ELCR, ELSEGR0, ELSEGR1 Security Attribution. */ + #endif + #ifdef BSP_TZ_CFG_FSAR + R_FCACHE->FSAR = BSP_TZ_CFG_FSAR; /* FLWT and FCKMHZ Security Attribution. */ + #endif + #ifdef BSP_TZ_CFG_MSAR + R_MRMS->MSAR = BSP_TZ_CFG_MSAR; /* MRAM Security Attribution. */ + #endif + + R_CPSCU->SRAMSAR = BSP_TZ_CFG_SRAMSAR; /* SRAM Security Attribution. */ + #ifdef BSP_TZ_CFG_STBRAMSAR + R_CPSCU->STBRAMSAR = BSP_TZ_CFG_STBRAMSAR; /* Standby RAM Security Attribution. */ + #endif + #endif + + R_CPSCU->MMPUSARA |= (BSP_TZ_CFG_MMPUSARA << DMACX_REGISTER_SHIFT); /* Security Attribution for the DMAC Bus Master MPU. */ + + #if !BSP_SECONDARY_CORE_BUILD + R_CPSCU->BUSSARA = BSP_TZ_CFG_BUSSARA; /* Security Attribution Register A for the BUS Control Registers. */ + R_CPSCU->BUSSARB = BSP_TZ_CFG_BUSSARB; /* Security Attribution Register B for the BUS Control Registers. */ + #ifdef BSP_TZ_CFG_BUSSARC + R_CPSCU->BUSSARC = BSP_TZ_CFG_BUSSARC; /* Security Attribution Register C for the BUS Control Registers. */ + #endif + #endif + + #ifdef BSP_TZ_CFG_IPCSAR + BSP_PRV_SAR_WRITE(R_CPSCU->IPCSAR, BSP_TZ_CFG_IPCSAR); /* IPC Security Attribution */ + #endif + + #if (defined(BSP_TZ_CFG_ICUSARC) && (BSP_TZ_CFG_ICUSARC != UINT32_MAX)) || \ + (defined(BSP_TZ_CFG_DMACCHSAR) && \ + ((BSP_TZ_CFG_DMACCHSAR & R_CPSCU_DMACCHSAR_DMACCHSARn_Msk) != R_CPSCU_DMACCHSAR_DMACCHSARn_Msk)) + + R_BSP_MODULE_START(FSP_IP_DMAC, 0); + + #if BSP_FEATURE_TZ_VERSION == 2 + + /* On MCUs with this implementation of trustzone, DMAST security attribution is set to secure after reset. */ + #else + + /* If any DMAC channels are required by secure program, disable nonsecure write access to DMAST + * in order to prevent the nonsecure program from disabling all DMAC channels. */ + R_CPSCU->DMACSAR &= ~(1U << DMACX_REGISTER_SHIFT); /* Protect DMAST from nonsecure write access. */ + #endif + + /* Ensure that DMAST is set so that the nonsecure program can use DMA. */ + R_DMA->DMAST = 1U; + #else + + /* On MCUs with this implementation of trustzone, DMACSAR security attribution is set to secure after reset. + * If the DMAC is not used in the secure application,then configure DMAST security attribution to non-secure. */ + R_CPSCU->DMACSAR = 1U; + #endif + + #if BSP_TZ_CFG_DTC_USED + R_BSP_MODULE_START(FSP_IP_DTC, 0); + + #if BSP_FEATURE_TZ_VERSION == 2 + + /* On MCUs with this implementation of trustzone, DTCST security attribution is set to secure after reset. */ + #else + + /* If the DTC is used by the secure program, disable nonsecure write access to DTCST + * in order to prevent the nonsecure program from disabling all DTC transfers. */ + R_CPSCU->DTCSAR &= ~(1U << DTCX_REGISTER_SHIFT); + #endif + + /* Ensure that DTCST is set so that the nonsecure program can use DTC. */ + R_DTC->DTCST = 1U; + #elif BSP_FEATURE_TZ_VERSION == 2 + + /* On MCUs with this implementation of trustzone, DTCST security attribution is set to secure after reset. + * If the DTC is not used in the secure application,then configure DTCST security attribution to non-secure. */ + R_CPSCU->DTCSAR |= (1U << DTCX_REGISTER_SHIFT); + #endif + + /* Initialize security attribution registers for Pins. */ + R_BSP_PinCfgSecurityInit(); + + /* Initialize security attribution registers for ELC. */ + R_BSP_ElcCfgSecurityInit(); + + /* Reenable PRCR for SARs. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); +} + +/* This function is overridden by tooling. */ +BSP_WEAK_REFERENCE void R_BSP_PinCfgSecurityInit (void) +{ +} + +/* This function is overridden by tooling. */ +BSP_WEAK_REFERENCE void R_BSP_ElcCfgSecurityInit (void) +{ +} + + #endif +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_security.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_security.h new file mode 100644 index 00000000000..3ceb51f921a --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_security.h @@ -0,0 +1,33 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_SECURITY_H +#define BSP_SECURITY_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +void R_BSP_NonSecureEnter(void); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_tfu.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_tfu.h new file mode 100644 index 00000000000..98b09caee38 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/all/bsp_tfu.h @@ -0,0 +1,218 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef RENESAS_TFU +#define RENESAS_TFU + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* Mathematical Functions includes. */ +#ifdef __cplusplus + #include +#else + #include +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +#if BSP_FEATURE_TFU_SUPPORTED + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + + #define R_TFU_HYPOT_SCALING_FACTOR 0.607252935f + + #ifdef __GNUC__ /* and (arm)clang */ + #if (__STDC_VERSION__ < 199901L) && defined(__STRICT_ANSI__) && !defined(__cplusplus) + +/* No form of inline is available, it happens only when -std=c89, gnu89 and + * above are OK */ + #warning \ + "-std=c89 doesn't support type checking on TFU. Please use -std=gnu89 or higher for example -std=c99" + #else + #ifdef __GNUC_GNU_INLINE__ + +/* gnu89 semantics of inline and extern inline are essentially the exact + * opposite of those in C99 */ + #define BSP_TFU_INLINE extern inline __attribute__((always_inline)) + #else /* __GNUC_STDC_INLINE__ */ + #define BSP_TFU_INLINE static inline __attribute__((always_inline)) + #endif + #endif + #elif __ICCARM__ + #define BSP_TFU_INLINE + #else + #error "Compiler not supported!" + #endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Inline Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Calculates sine of the given angle. + * @param[in] angle The value of an angle in radian. + * + * @retval Sine value of an angle. + **********************************************************************************************************************/ + #if __ICCARM__ + #pragma inline = forced + #endif +BSP_TFU_INLINE float __sinf (float angle) +{ + /* Set the angle to R_TFU->SCDT1 */ + R_TFU->SCDT1 = angle; + + /* Read sin from R_TFU->SCDT1 */ + return R_TFU->SCDT1; +} + +/*******************************************************************************************************************//** + * Calculates cosine of the given angle. + * @param[in] angle The value of an angle in radian. + * + * @retval Cosine value of an angle. + **********************************************************************************************************************/ + #if __ICCARM__ + #pragma inline = forced + #endif +BSP_TFU_INLINE float __cosf (float angle) +{ + /* Set the angle to R_TFU->SCDT1 */ + R_TFU->SCDT1 = angle; + + /* Read cos from R_TFU->SCDT1 */ + return R_TFU->SCDT0; +} + +/*******************************************************************************************************************//** + * Calculates sine and cosine of the given angle. + * @param[in] angle The value of an angle in radian. + * @param[out] sin Sine value of an angle. + * @param[out] cos Cosine value of an angle. + **********************************************************************************************************************/ + #if __ICCARM__ + #pragma inline = forced + #endif +BSP_TFU_INLINE void __sincosf (float angle, float * sin, float * cos) +{ + /* Set the angle to R_TFU->SCDT1 */ + R_TFU->SCDT1 = angle; + + /* Read sin from R_TFU->SCDT1 */ + *sin = R_TFU->SCDT1; + + /* Read sin from R_TFU->SCDT1 */ + *cos = R_TFU->SCDT0; +} + +/*******************************************************************************************************************//** + * Calculates the arc tangent based on given X-cordinate and Y-cordinate values. + * @param[in] y_cord Y-Axis cordinate value. + * @param[in] x_cord X-Axis cordinate value. + * + * @retval Arc tangent for given values. + **********************************************************************************************************************/ + #if __ICCARM__ + #pragma inline = forced + #endif +BSP_TFU_INLINE float __atan2f (float y_cord, float x_cord) +{ + /* Set X-cordinate to R_TFU->ATDT0 */ + R_TFU->ATDT0 = x_cord; + + /* set Y-cordinate to R_TFU->ATDT1 */ + R_TFU->ATDT1 = y_cord; + + /* Read arctan(y/x) from R_TFU->ATDT1 */ + return R_TFU->ATDT1; +} + +/*******************************************************************************************************************//** + * Calculates the hypotenuse based on given X-cordinate and Y-cordinate values. + * @param[in] y_cord Y-cordinate value. + * @param[in] x_cord X-cordinate value. + * + * @retval Hypotenuse for given values. + **********************************************************************************************************************/ + #if __ICCARM__ + #pragma inline = forced + #endif +BSP_TFU_INLINE float __hypotf (float x_cord, float y_cord) +{ + /* Set X-coordinate to R_TFU->ATDT0 */ + R_TFU->ATDT0 = x_cord; + + /* set Y-coordinate to R_TFU->ATDT1 */ + R_TFU->ATDT1 = y_cord; + + /* Read sqrt (x_cord2 + y_cord2) from R_TFU->ATDT0 */ + return R_TFU->ATDT0 * R_TFU_HYPOT_SCALING_FACTOR; +} + +/*******************************************************************************************************************//** + * Calculates the arc tangent and hypotenuse based on given X-cordinate and Y-cordinate values. + * @param[in] y_cord Y-cordinate value. + * @param[in] x_cord X-cordinate value. + * @param[out] atan2 Arc tangent for given values. + * @param[out] hypot Hypotenuse for given values. + **********************************************************************************************************************/ + #if __ICCARM__ + #pragma inline = forced + #endif +BSP_TFU_INLINE void __atan2hypotf (float y_cord, float x_cord, float * atan2, float * hypot) +{ + /* Set X-coordinate to R_TFU->ATDT0 */ + R_TFU->ATDT0 = x_cord; + + /* set Y-coordinate to R_TFU->ATDT1 */ + R_TFU->ATDT1 = y_cord; + + /* Read arctan(y/x) from R_TFU->ATDT1 */ + *atan2 = R_TFU->ATDT1; + + /* Read sqrt (x_cord2 + y_cord2) from R_TFU->ATDT0 */ + *hypot = R_TFU->ATDT0 * R_TFU_HYPOT_SCALING_FACTOR; +} + + #if BSP_CFG_USE_TFU_MATHLIB + #define sinf(x) __sinf(x) + #define cosf(x) __cosf(x) + #define atan2f(y, x) __atan2f(y, x) + #define hypotf(x, y) __hypotf(x, y) + #define atan2hypotf(y, x, a, h) __atan2hypotf(y, x, a, h) + #define sincosf(a, s, c) __sincosf(a, s, c) + #endif + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +#endif + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* RENESAS_TFU */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/ra8p1/bsp_elc.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/ra8p1/bsp_elc.h new file mode 100644 index 00000000000..f641ae90e7e --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/ra8p1/bsp_elc.h @@ -0,0 +1,583 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_ELC_H +#define BSP_ELC_H + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RA8P1 + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/* UNCRUSTIFY-OFF */ + +/** Sources of event signals to be linked to other peripherals or the CPU + * @note This list is device specific. + * */ +typedef enum e_elc_event_ra8p1 +{ + ELC_EVENT_NONE = (0x0), // Link disabled + ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 + ELC_EVENT_ICU_IRQ1 = (0x002), // External pin interrupt 1 + ELC_EVENT_ICU_IRQ2 = (0x003), // External pin interrupt 2 + ELC_EVENT_ICU_IRQ3 = (0x004), // External pin interrupt 3 + ELC_EVENT_ICU_IRQ4 = (0x005), // External pin interrupt 4 + ELC_EVENT_ICU_IRQ5 = (0x006), // External pin interrupt 5 + ELC_EVENT_ICU_IRQ6 = (0x007), // External pin interrupt 6 + ELC_EVENT_ICU_IRQ7 = (0x008), // External pin interrupt 7 + ELC_EVENT_ICU_IRQ8 = (0x009), // External pin interrupt 8 + ELC_EVENT_ICU_IRQ9 = (0x00A), // External pin interrupt 9 + ELC_EVENT_ICU_IRQ10 = (0x00B), // External pin interrupt 10 + ELC_EVENT_ICU_IRQ11 = (0x00C), // External pin interrupt 11 + ELC_EVENT_ICU_IRQ12 = (0x00D), // External pin interrupt 12 + ELC_EVENT_ICU_IRQ13 = (0x00E), // External pin interrupt 13 + ELC_EVENT_ICU_IRQ14 = (0x00F), // External pin interrupt 14 + ELC_EVENT_ICU_IRQ15 = (0x010), // External pin interrupt 15 + ELC_EVENT_ICU_IRQ16 = (0x011), // External pin interrupt 16 + ELC_EVENT_ICU_IRQ17 = (0x012), // External pin interrupt 17 + ELC_EVENT_ICU_IRQ18 = (0x013), // External pin interrupt 18 + ELC_EVENT_ICU_IRQ19 = (0x014), // External pin interrupt 19 + ELC_EVENT_ICU_IRQ20 = (0x015), // External pin interrupt 20 + ELC_EVENT_ICU_IRQ21 = (0x016), // External pin interrupt 21 + ELC_EVENT_ICU_IRQ22 = (0x017), // External pin interrupt 22 + ELC_EVENT_ICU_IRQ23 = (0x018), // External pin interrupt 23 + ELC_EVENT_ICU_IRQ24 = (0x019), // External pin interrupt 24 + ELC_EVENT_ICU_IRQ25 = (0x01A), // External pin interrupt 25 + ELC_EVENT_ICU_IRQ26 = (0x01B), // External pin interrupt 26 + ELC_EVENT_ICU_IRQ27 = (0x01C), // External pin interrupt 27 + ELC_EVENT_ICU_IRQ28 = (0x01D), // External pin interrupt 28 + ELC_EVENT_ICU_IRQ29 = (0x01E), // External pin interrupt 29 + ELC_EVENT_ICU_IRQ30 = (0x01F), // External pin interrupt 30 + ELC_EVENT_ICU_IRQ31 = (0x020), // External pin interrupt 31 + ELC_EVENT_DMAC0_INT = (0x040), // DMAC0 transfer end + ELC_EVENT_DMAC1_INT = (0x041), // DMAC1 transfer end + ELC_EVENT_DMAC2_INT = (0x042), // DMAC2 transfer end + ELC_EVENT_DMAC3_INT = (0x043), // DMAC3 transfer end + ELC_EVENT_DMAC4_INT = (0x044), // DMAC4 transfer end + ELC_EVENT_DMAC5_INT = (0x045), // DMAC5 transfer end + ELC_EVENT_DMAC6_INT = (0x046), // DMAC6 transfer end + ELC_EVENT_DMAC7_INT = (0x047), // DMAC7 transfer end + ELC_EVENT_DMAC10_INT = (0x048), // DMAC10 transfer end + ELC_EVENT_DMAC11_INT = (0x049), // DMAC11 transfer end + ELC_EVENT_DMAC12_INT = (0x04A), // DMAC12 transfer end + ELC_EVENT_DMAC13_INT = (0x04B), // DMAC13 transfer end + ELC_EVENT_DMAC14_INT = (0x04C), // DMAC14 transfer end + ELC_EVENT_DMAC15_INT = (0x04D), // DMAC15 transfer end + ELC_EVENT_DMAC16_INT = (0x04E), // DMAC16 transfer end + ELC_EVENT_DMAC17_INT = (0x04F), // DMAC17 transfer end + ELC_EVENT_DTC_END = (0x052), // DTC transfer end + ELC_EVENT_DTC1_END = (0x055), // DTC1 transfer end + ELC_EVENT_DMA_TRANSERR = (0x056), // DMA/DTC transfer error + ELC_EVENT_DMA1_TRANSERR = (0x057), // DMA1/DTC1 transfer error + ELC_EVENT_DBG_CTIIRQ0 = (0x058), // Coresight Crosstrigger Event + ELC_EVENT_DBG_CTIIRQ1 = (0x059), // Coresight Crosstrigger Event + ELC_EVENT_DBG_JBRXI = (0x05A), // JB RXI + ELC_EVENT_IPC_IRQ0 = (0x05B), // CPU Mutual Interrupt 0 + ELC_EVENT_IPC_IRQ1 = (0x05C), // CPU Mutual Interrupt 1 + ELC_EVENT_LM0_ERR = (0x05F), // Local memory 0 error + ELC_EVENT_LM1_ERR = (0x060), // Local memory 1 error + ELC_EVENT_CPU0_LOCKUP = (0x061), // CPU 0 lockup + ELC_EVENT_CPU1_LOCKUP = (0x062), // CPU 1 lockup + ELC_EVENT_BUS_ERR = (0x063), // BUS error + ELC_EVENT_CM_ERR = (0x064), // Common memory error + ELC_EVENT_FPU_EXC = (0x065), // FPU exception + ELC_EVENT_NPU_IRQ = (0x067), // NPU IRQ + ELC_EVENT_MRAM_MRCRD = (0x068), // MRAM read error interrupt for MRC + ELC_EVENT_MRAM_MRERD = (0x069), // MRAM read error interrupt for MRE + ELC_EVENT_MRAM_MRCPR = (0x06B), // MRAM sequencer error interrupt for MRC + ELC_EVENT_MRAM_MREPR = (0x06C), // MRAM sequencer error interrupt for MRE + ELC_EVENT_MRAM_ENDOFPE = (0x06D), // MRAM sequencer ready + ELC_EVENT_LVD_LVD1 = (0x070), // Voltage monitor 1 interrupt + ELC_EVENT_LVD_LVD2 = (0x071), // Voltage monitor 2 interrupt + ELC_EVENT_VBATT_TADI = (0x075), // VBATT Tamper Detection + ELC_EVENT_CGC_MOSC_STOP = (0x076), // Main Clock oscillation stop + ELC_EVENT_CGC_SOSC_STOP = (0x077), // Sub oscillation stop + ELC_EVENT_ULPT0_INT = (0x080), // ULPT0 Underflow + ELC_EVENT_ULPT0_COMPARE_A = (0x081), // ULPT0 Compare match A + ELC_EVENT_ULPT0_COMPARE_B = (0x082), // ULPT0 Compare match B + ELC_EVENT_ULPT1_INT = (0x083), // ULPT1 Underflow + ELC_EVENT_ULPT1_COMPARE_A = (0x084), // ULPT1 Compare match A + ELC_EVENT_ULPT1_COMPARE_B = (0x085), // ULPT1 Compare match B + ELC_EVENT_AGT0_INT = (0x086), // AGT interrupt + ELC_EVENT_AGT0_COMPARE_A = (0x087), // Compare match A + ELC_EVENT_AGT0_COMPARE_B = (0x088), // Compare match B + ELC_EVENT_AGT1_INT = (0x089), // AGT interrupt + ELC_EVENT_AGT1_COMPARE_A = (0x08A), // Compare match A + ELC_EVENT_AGT1_COMPARE_B = (0x08B), // Compare match B + ELC_EVENT_IWDT_UNDERFLOW = (0x092), // IWDT underflow + ELC_EVENT_WDT0_UNDERFLOW = (0x093), // WDT0 underflow + ELC_EVENT_WDT1_UNDERFLOW = (0x094), // WDT1 underflow + ELC_EVENT_RTC_ALARM = (0x095), // Alarm interrupt + ELC_EVENT_RTC_PERIOD = (0x096), // Periodic interrupt + ELC_EVENT_RTC_CARRY = (0x097), // Carry interrupt + ELC_EVENT_USBFS_FIFO_0 = (0x098), // DMA/DTC transfer request 0 + ELC_EVENT_USBFS_FIFO_1 = (0x099), // DMA/DTC transfer request 1 + ELC_EVENT_USBFS_INT = (0x09A), // USBFS interrupt + ELC_EVENT_USBFS_RESUME = (0x09B), // USBFS resume interrupt + ELC_EVENT_IIC0_RXI = (0x09C), // Receive data full + ELC_EVENT_IIC0_TXI = (0x09D), // Transmit data empty + ELC_EVENT_IIC0_TEI = (0x09E), // Transmit end + ELC_EVENT_IIC0_ERI = (0x09F), // Transfer error + ELC_EVENT_IIC0_WUI = (0x0A0), // Wakeup interrupt + ELC_EVENT_IIC1_RXI = (0x0A1), // Receive data full + ELC_EVENT_IIC1_TXI = (0x0A2), // Transmit data empty + ELC_EVENT_IIC1_TEI = (0x0A3), // Transmit end + ELC_EVENT_IIC1_ERI = (0x0A4), // Transfer error + ELC_EVENT_IIC2_RXI = (0x0A6), // Receive data full + ELC_EVENT_IIC2_TXI = (0x0A7), // Transmit data empty + ELC_EVENT_IIC2_TEI = (0x0A8), // Transmit end + ELC_EVENT_IIC2_ERI = (0x0A9), // Transfer error + ELC_EVENT_SDHIMMC0_ACCS = (0x0AB), // Card access + ELC_EVENT_SDHIMMC0_SDIO = (0x0AC), // SDIO access + ELC_EVENT_SDHIMMC0_CARD = (0x0AD), // Card detect + ELC_EVENT_SDHIMMC0_DMA_REQ = (0x0AE), // DMA transfer request + ELC_EVENT_SDHIMMC1_ACCS = (0x0AF), // Card access + ELC_EVENT_SDHIMMC1_SDIO = (0x0B0), // SDIO access + ELC_EVENT_SDHIMMC1_CARD = (0x0B1), // Card detect + ELC_EVENT_SDHIMMC1_DMA_REQ = (0x0B2), // DMA transfer request + ELC_EVENT_SSI0_TXI = (0x0B3), // Transmit data empty + ELC_EVENT_SSI0_RXI = (0x0B4), // Receive data full + ELC_EVENT_SSI0_INT = (0x0B6), // Error interrupt + ELC_EVENT_SSI1_TXI = (0x0B9), // Receive data full/Transmit data empty + ELC_EVENT_SSI1_RXI = (0x0B9), // Receive data full/Transmit data empty + ELC_EVENT_SSI1_INT = (0x0BA), // Error interrupt + ELC_EVENT_XSPI_ERR = (0x0BB), // xSPI Error + ELC_EVENT_XSPI_CMP = (0x0BC), // xSPI Complete + ELC_EVENT_XSPI1_ERR = (0x0BD), // xSPI1 Error + ELC_EVENT_XSPI1_CMP = (0x0BE), // xSPI1 Complete + ELC_EVENT_PDM_DAT0 = (0x0BF), // Data reception interrupt channel 0 + ELC_EVENT_PDM_DAT1 = (0x0C0), // Data reception interrupt channel 1 + ELC_EVENT_PDM_DAT2 = (0x0C1), // Data reception interrupt channel 2 + ELC_EVENT_PDM_SDET = (0x0C2), // Sound detection interrupt + ELC_EVENT_PDM_ERR0 = (0x0C3), // Error detection interrupt channel 0 + ELC_EVENT_PDM_ERR1 = (0x0C4), // Error detection interrupt channel 1 + ELC_EVENT_PDM_ERR2 = (0x0C5), // Error detection interrupt channel 2 + ELC_EVENT_ACMPHS0_INT = (0x0C6), // High Speed Comparator channel 0 interrupt + ELC_EVENT_ACMPHS1_INT = (0x0C7), // High Speed Comparator channel 1 interrupt + ELC_EVENT_ACMPHS2_INT = (0x0C8), // High Speed Comparator channel 2 interrupt + ELC_EVENT_ACMPHS3_INT = (0x0C9), // High Speed Comparator channel 3 interrupt + ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x0CC), // Software event 0 + ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x0CD), // Software event 1 + ELC_EVENT_ELC_SOFTWARE_EVENT_2 = (0x0CE), // Software event 2 + ELC_EVENT_ELC_SOFTWARE_EVENT_3 = (0x0CF), // Software event 3 + ELC_EVENT_IOPORT_EVENT_1 = (0x0D0), // Port 1 event + ELC_EVENT_IOPORT_EVENT_2 = (0x0D1), // Port 2 event + ELC_EVENT_IOPORT_EVENT_3 = (0x0D2), // Port 3 event + ELC_EVENT_IOPORT_EVENT_4 = (0x0D3), // Port 4 event + ELC_EVENT_CAC_FREQUENCY_ERROR = (0x0D4), // Frequency error interrupt + ELC_EVENT_CAC_MEASUREMENT_END = (0x0D5), // Measurement end interrupt + ELC_EVENT_CAC_OVERFLOW = (0x0D6), // Overflow interrupt + ELC_EVENT_POEG0_EVENT = (0x0D7), // Port Output disable 0 interrupt + ELC_EVENT_POEG1_EVENT = (0x0D8), // Port Output disable 1 interrupt + ELC_EVENT_POEG2_EVENT = (0x0D9), // Port Output disable 2 interrupt + ELC_EVENT_POEG3_EVENT = (0x0DA), // Port Output disable 3 interrupt + ELC_EVENT_OPS_UVW_EDGE = (0x180), // UVW edge event + ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x181), // Capture/Compare match A + ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x182), // Capture/Compare match B + ELC_EVENT_GPT0_COMPARE_C = (0x183), // Compare match C + ELC_EVENT_GPT0_COMPARE_D = (0x184), // Compare match D + ELC_EVENT_GPT0_COMPARE_E = (0x185), // Compare match E + ELC_EVENT_GPT0_COMPARE_F = (0x186), // Compare match F + ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x187), // Overflow + ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x188), // Underflow + ELC_EVENT_GPT0_PC = (0x189), // Period count function finish + ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x18A), // Capture/Compare match A + ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x18B), // Capture/Compare match B + ELC_EVENT_GPT1_COMPARE_C = (0x18C), // Compare match C + ELC_EVENT_GPT1_COMPARE_D = (0x18D), // Compare match D + ELC_EVENT_GPT1_COMPARE_E = (0x18E), // Compare match E + ELC_EVENT_GPT1_COMPARE_F = (0x18F), // Compare match F + ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x190), // Overflow + ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x191), // Underflow + ELC_EVENT_GPT1_PC = (0x192), // Period count function finish + ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x193), // Capture/Compare match A + ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x194), // Capture/Compare match B + ELC_EVENT_GPT2_COMPARE_C = (0x195), // Compare match C + ELC_EVENT_GPT2_COMPARE_D = (0x196), // Compare match D + ELC_EVENT_GPT2_COMPARE_E = (0x197), // Compare match E + ELC_EVENT_GPT2_COMPARE_F = (0x198), // Compare match F + ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x199), // Overflow + ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x19A), // Underflow + ELC_EVENT_GPT2_PC = (0x19B), // Period count function finish + ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x19C), // Capture/Compare match A + ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x19D), // Capture/Compare match B + ELC_EVENT_GPT3_COMPARE_C = (0x19E), // Compare match C + ELC_EVENT_GPT3_COMPARE_D = (0x19F), // Compare match D + ELC_EVENT_GPT3_COMPARE_E = (0x1A0), // Compare match E + ELC_EVENT_GPT3_COMPARE_F = (0x1A1), // Compare match F + ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x1A2), // Overflow + ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x1A3), // Underflow + ELC_EVENT_GPT3_PC = (0x1A4), // Period count function finish + ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x1A5), // Capture/Compare match A + ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x1A6), // Capture/Compare match B + ELC_EVENT_GPT4_COMPARE_C = (0x1A7), // Compare match C + ELC_EVENT_GPT4_COMPARE_D = (0x1A8), // Compare match D + ELC_EVENT_GPT4_COMPARE_E = (0x1A9), // Compare match E + ELC_EVENT_GPT4_COMPARE_F = (0x1AA), // Compare match F + ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x1AB), // Overflow + ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x1AC), // Underflow + ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x1AE), // Capture/Compare match A + ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x1AF), // Capture/Compare match B + ELC_EVENT_GPT5_COMPARE_C = (0x1B0), // Compare match C + ELC_EVENT_GPT5_COMPARE_D = (0x1B1), // Compare match D + ELC_EVENT_GPT5_COMPARE_E = (0x1B2), // Compare match E + ELC_EVENT_GPT5_COMPARE_F = (0x1B3), // Compare match F + ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x1B4), // Overflow + ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x1B5), // Underflow + ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x1B7), // Capture/Compare match A + ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x1B8), // Capture/Compare match B + ELC_EVENT_GPT6_COMPARE_C = (0x1B9), // Compare match C + ELC_EVENT_GPT6_COMPARE_D = (0x1BA), // Compare match D + ELC_EVENT_GPT6_COMPARE_E = (0x1BB), // Compare match E + ELC_EVENT_GPT6_COMPARE_F = (0x1BC), // Compare match F + ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x1BD), // Overflow + ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x1BE), // Underflow + ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x1C0), // Capture/Compare match A + ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x1C1), // Capture/Compare match B + ELC_EVENT_GPT7_COMPARE_C = (0x1C2), // Compare match C + ELC_EVENT_GPT7_COMPARE_D = (0x1C3), // Compare match D + ELC_EVENT_GPT7_COMPARE_E = (0x1C4), // Compare match E + ELC_EVENT_GPT7_COMPARE_F = (0x1C5), // Compare match F + ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x1C6), // Overflow + ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x1C7), // Underflow + ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x1C9), // Capture/Compare match A + ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x1CA), // Capture/Compare match B + ELC_EVENT_GPT8_COMPARE_C = (0x1CB), // Compare match C + ELC_EVENT_GPT8_COMPARE_D = (0x1CC), // Compare match D + ELC_EVENT_GPT8_COMPARE_E = (0x1CD), // Compare match E + ELC_EVENT_GPT8_COMPARE_F = (0x1CE), // Compare match F + ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0x1CF), // Overflow + ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0x1D0), // Underflow + ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0x1D2), // Capture/Compare match A + ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0x1D3), // Capture/Compare match B + ELC_EVENT_GPT9_COMPARE_C = (0x1D4), // Compare match C + ELC_EVENT_GPT9_COMPARE_D = (0x1D5), // Compare match D + ELC_EVENT_GPT9_COMPARE_E = (0x1D6), // Compare match E + ELC_EVENT_GPT9_COMPARE_F = (0x1D7), // Compare match F + ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0x1D8), // Overflow + ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0x1D9), // Underflow + ELC_EVENT_GPT10_CAPTURE_COMPARE_A = (0x1DB), // Capture/Compare match A + ELC_EVENT_GPT10_CAPTURE_COMPARE_B = (0x1DC), // Capture/Compare match B + ELC_EVENT_GPT10_COMPARE_C = (0x1DD), // Compare match C + ELC_EVENT_GPT10_COMPARE_D = (0x1DE), // Compare match D + ELC_EVENT_GPT10_COMPARE_E = (0x1DF), // Compare match E + ELC_EVENT_GPT10_COMPARE_F = (0x1E0), // Compare match F + ELC_EVENT_GPT10_COUNTER_OVERFLOW = (0x1E1), // Overflow + ELC_EVENT_GPT10_COUNTER_UNDERFLOW = (0x1E2), // Underflow + ELC_EVENT_GPT10_PC = (0x1E3), // Period count function finish + ELC_EVENT_GPT11_CAPTURE_COMPARE_A = (0x1E4), // Capture/Compare match A + ELC_EVENT_GPT11_CAPTURE_COMPARE_B = (0x1E5), // Capture/Compare match B + ELC_EVENT_GPT11_COMPARE_C = (0x1E6), // Compare match C + ELC_EVENT_GPT11_COMPARE_D = (0x1E7), // Compare match D + ELC_EVENT_GPT11_COMPARE_E = (0x1E8), // Compare match E + ELC_EVENT_GPT11_COMPARE_F = (0x1E9), // Compare match F + ELC_EVENT_GPT11_COUNTER_OVERFLOW = (0x1EA), // Overflow + ELC_EVENT_GPT11_COUNTER_UNDERFLOW = (0x1EB), // Underflow + ELC_EVENT_GPT11_PC = (0x1EC), // Period count function finish + ELC_EVENT_GPT12_CAPTURE_COMPARE_A = (0x1ED), // Capture/Compare match A + ELC_EVENT_GPT12_CAPTURE_COMPARE_B = (0x1EE), // Capture/Compare match B + ELC_EVENT_GPT12_COMPARE_C = (0x1EF), // Compare match C + ELC_EVENT_GPT12_COMPARE_D = (0x1F0), // Compare match D + ELC_EVENT_GPT12_COMPARE_E = (0x1F1), // Compare match E + ELC_EVENT_GPT12_COMPARE_F = (0x1F2), // Compare match F + ELC_EVENT_GPT12_COUNTER_OVERFLOW = (0x1F3), // Overflow + ELC_EVENT_GPT12_COUNTER_UNDERFLOW = (0x1F4), // Underflow + ELC_EVENT_GPT12_PC = (0x1F5), // Period count function finish + ELC_EVENT_GPT13_CAPTURE_COMPARE_A = (0x1F6), // Capture/Compare match A + ELC_EVENT_GPT13_CAPTURE_COMPARE_B = (0x1F7), // Capture/Compare match B + ELC_EVENT_GPT13_COMPARE_C = (0x1F8), // Compare match C + ELC_EVENT_GPT13_COMPARE_D = (0x1F9), // Compare match D + ELC_EVENT_GPT13_COMPARE_E = (0x1FA), // Compare match E + ELC_EVENT_GPT13_COMPARE_F = (0x1FB), // Compare match F + ELC_EVENT_GPT13_COUNTER_OVERFLOW = (0x1FC), // Overflow + ELC_EVENT_GPT13_COUNTER_UNDERFLOW = (0x1FD), // Underflow + ELC_EVENT_GPT13_PC = (0x1FE), // Period count function finish + ELC_EVENT_ETHER_FWEI = (0x29A), // Forwarding Error Interrupt + ELC_EVENT_ETHER_CAEI = (0x29B), // Common Error Interrupt + ELC_EVENT_ETHER_GWEI = (0x29C), // GWCA0 Error Interrupt + ELC_EVENT_ETHER_EAEI0 = (0x29D), // ETHA0 Error Interrupt + ELC_EVENT_ETHER_EAEI1 = (0x29E), // ETHA1 Error Interrupt + ELC_EVENT_ETHER_PTPSI0 = (0x29F), // gPTP Status Interrupt 0 + ELC_EVENT_ETHER_PTPSI1 = (0x2A0), // gPTP Status Interrupt 1 + ELC_EVENT_ETHER_FWSI = (0x2A1), // Forwarding Status Interrupt + ELC_EVENT_ETHER_SWSI = (0x2A2), // Switch Status Interrupt + ELC_EVENT_ETHER_CAMI = (0x2A3), // Common Status Interrupt + ELC_EVENT_ETHER_EASI0 = (0x2A4), // ETHA0 Status Interrupt + ELC_EVENT_ETHER_EASI1 = (0x2A5), // ETHA1 Status Interrupt + ELC_EVENT_ETHER_GWDI0 = (0x2A6), // GWCA Data Interrupt 0 + ELC_EVENT_ETHER_GWDI1 = (0x2A7), // GWCA Data Interrupt 1 + ELC_EVENT_ETHER_GWDI2 = (0x2A8), // GWCA Data Interrupt 2 + ELC_EVENT_ETHER_GWDI3 = (0x2A9), // GWCA Data Interrupt 3 + ELC_EVENT_ETHER_GWDI4 = (0x2AA), // GWCA Data Interrupt 4 + ELC_EVENT_ETHER_GWDI5 = (0x2AB), // GWCA Data Interrupt 5 + ELC_EVENT_ETHER_GWDI6 = (0x2AC), // GWCA Data Interrupt 6 + ELC_EVENT_ETHER_GWDI7 = (0x2AD), // GWCA Data Interrupt 7 + ELC_EVENT_ETHER_TSDI0 = (0x2AE), // Time Stamp Data Interrupt 0 + ELC_EVENT_ETHER_TSDI1 = (0x2AF), // Time Stamp Data Interrupt 1 + ELC_EVENT_ETHER_MDIO0 = (0x2B0), // MDIO Interrupt 0 + ELC_EVENT_ETHER_MDIO1 = (0x2B1), // MDIO Interrupt 1 + ELC_EVENT_ETHER_RMPI0 = (0x2B2), // RMAC0 PHY Interrupt + ELC_EVENT_ETHER_RMPI1 = (0x2B3), // RMAC1 PHY Interrupt + ELC_EVENT_GPTP_PTPOUT0 = (0x2B4), // PTP Pulse Out 0 + ELC_EVENT_GPTP_PTPOUT1 = (0x2B5), // PTP Pulse Out 1 + ELC_EVENT_GPTP_PTPOUT2 = (0x2B6), // PTP Pulse Out 2 + ELC_EVENT_GPTP_PTPOUT3 = (0x2B7), // PTP Pulse Out 3 + ELC_EVENT_GPTP0_MATCH = (0x2B8), // Media Clock Recovery Match + ELC_EVENT_GPTP1_MATCH = (0x2B9), // Media Clock Recovery Match + ELC_EVENT_USBHS_FIFO_0 = (0x2C1), // DMA transfer request 0 + ELC_EVENT_USBHS_FIFO_1 = (0x2C2), // DMA transfer request 1 + ELC_EVENT_USBHS_USB_INT_RESUME = (0x2C3), // USBHS interrupt + ELC_EVENT_SCI0_RXI = (0x2C4), // Receive data full + ELC_EVENT_SCI0_TXI = (0x2C5), // Transmit data empty + ELC_EVENT_SCI0_TEI = (0x2C6), // Transmit end + ELC_EVENT_SCI0_ERI = (0x2C7), // Receive error + ELC_EVENT_SCI0_AED = (0x2C8), // Active edge detection + ELC_EVENT_SCI0_BFD = (0x2C9), // Break field detection + ELC_EVENT_SCI0_AM = (0x2CA), // Address match event + ELC_EVENT_SCI1_RXI = (0x2CB), // Receive data full + ELC_EVENT_SCI1_TXI = (0x2CC), // Transmit data empty + ELC_EVENT_SCI1_TEI = (0x2CD), // Transmit end + ELC_EVENT_SCI1_ERI = (0x2CE), // Receive error + ELC_EVENT_SCI1_AED = (0x2CF), // Active edge detection + ELC_EVENT_SCI1_BFD = (0x2D0), // Break field detection + ELC_EVENT_SCI1_AM = (0x2D1), // Address match event + ELC_EVENT_SCI2_RXI = (0x2D2), // Receive data full + ELC_EVENT_SCI2_TXI = (0x2D3), // Transmit data empty + ELC_EVENT_SCI2_TEI = (0x2D4), // Transmit end + ELC_EVENT_SCI2_ERI = (0x2D5), // Receive error + ELC_EVENT_SCI2_AED = (0x2D6), // Active edge detection + ELC_EVENT_SCI2_BFD = (0x2D7), // Break field detection + ELC_EVENT_SCI2_AM = (0x2D8), // Address match event + ELC_EVENT_SCI3_RXI = (0x2D9), // Receive data full + ELC_EVENT_SCI3_TXI = (0x2DA), // Transmit data empty + ELC_EVENT_SCI3_TEI = (0x2DB), // Transmit end + ELC_EVENT_SCI3_ERI = (0x2DC), // Receive error + ELC_EVENT_SCI3_AED = (0x2DD), // Active edge detection + ELC_EVENT_SCI3_BFD = (0x2DE), // Break field detection + ELC_EVENT_SCI3_AM = (0x2DF), // Address match event + ELC_EVENT_SCI4_RXI = (0x2E0), // Receive data full + ELC_EVENT_SCI4_TXI = (0x2E1), // Transmit data empty + ELC_EVENT_SCI4_TEI = (0x2E2), // Transmit end + ELC_EVENT_SCI4_ERI = (0x2E3), // Receive error + ELC_EVENT_SCI4_AED = (0x2E4), // Active edge detection + ELC_EVENT_SCI4_BFD = (0x2E5), // Break field detection + ELC_EVENT_SCI4_AM = (0x2E6), // Address match event + ELC_EVENT_SCI5_RXI = (0x2E7), // Receive data full + ELC_EVENT_SCI5_TXI = (0x2E8), // Transmit data empty + ELC_EVENT_SCI5_TEI = (0x2E9), // Transmit end + ELC_EVENT_SCI5_ERI = (0x2EA), // Receive error + ELC_EVENT_SCI5_AED = (0x2EB), // Active edge detection + ELC_EVENT_SCI5_BFD = (0x2EC), // Break field detection + ELC_EVENT_SCI5_AM = (0x2ED), // Address match event + ELC_EVENT_SCI6_RXI = (0x2EE), // Receive data full + ELC_EVENT_SCI6_TXI = (0x2EF), // Transmit data empty + ELC_EVENT_SCI6_TEI = (0x2F0), // Transmit end + ELC_EVENT_SCI6_ERI = (0x2F1), // Receive error + ELC_EVENT_SCI6_AED = (0x2F2), // Active edge detection + ELC_EVENT_SCI6_BFD = (0x2F3), // Break field detection + ELC_EVENT_SCI6_AM = (0x2F4), // Address match event + ELC_EVENT_SCI7_RXI = (0x2F5), // Receive data full + ELC_EVENT_SCI7_TXI = (0x2F6), // Transmit data empty + ELC_EVENT_SCI7_TEI = (0x2F7), // Transmit end + ELC_EVENT_SCI7_ERI = (0x2F8), // Receive error + ELC_EVENT_SCI7_AED = (0x2F9), // Active edge detection + ELC_EVENT_SCI7_BFD = (0x2FA), // Break field detection + ELC_EVENT_SCI7_AM = (0x2FB), // Address match event + ELC_EVENT_SCI8_RXI = (0x2FC), // Receive data full + ELC_EVENT_SCI8_TXI = (0x2FD), // Transmit data empty + ELC_EVENT_SCI8_TEI = (0x2FE), // Transmit end + ELC_EVENT_SCI8_ERI = (0x2FF), // Receive error + ELC_EVENT_SCI8_AED = (0x300), // Active edge detection + ELC_EVENT_SCI8_BFD = (0x301), // Break field detection + ELC_EVENT_SCI8_AM = (0x302), // Address match event + ELC_EVENT_SCI9_RXI = (0x303), // Receive data full + ELC_EVENT_SCI9_TXI = (0x304), // Transmit data empty + ELC_EVENT_SCI9_TEI = (0x305), // Transmit end + ELC_EVENT_SCI9_ERI = (0x306), // Receive error + ELC_EVENT_SCI9_AED = (0x307), // Active edge detection + ELC_EVENT_SCI9_BFD = (0x308), // Break field detection + ELC_EVENT_SCI9_AM = (0x309), // Address match event + ELC_EVENT_SCI10_RXI = (0x30A), // Receive data full + ELC_EVENT_SCI10_TXI = (0x30B), // Transmit data empty + ELC_EVENT_SCI10_TEI = (0x30C), // Transmit end + ELC_EVENT_SCI10_ERI = (0x30D), // Receive error + ELC_EVENT_SCI10_AED = (0x30E), // Active edge detection + ELC_EVENT_SCI10_BFD = (0x30F), // Break field detection + ELC_EVENT_SCI10_AM = (0x310), // Address match event + ELC_EVENT_SCI11_RXI = (0x311), // Receive data full + ELC_EVENT_SCI11_TXI = (0x312), // Transmit data empty + ELC_EVENT_SCI11_TEI = (0x313), // Transmit end + ELC_EVENT_SCI11_ERI = (0x314), // Receive error + ELC_EVENT_SCI11_AED = (0x315), // Active edge detection + ELC_EVENT_SCI11_BFD = (0x316), // Break field detection + ELC_EVENT_SCI11_AM = (0x317), // Address match event + ELC_EVENT_SPI0_RXI = (0x318), // Receive buffer full + ELC_EVENT_SPI0_TXI = (0x319), // Transmit buffer empty + ELC_EVENT_SPI0_IDLE = (0x31A), // Idle + ELC_EVENT_SPI0_ERI = (0x31B), // Error + ELC_EVENT_SPI0_TEI = (0x31C), // Transmission complete event + ELC_EVENT_SPI1_RXI = (0x31D), // Receive buffer full + ELC_EVENT_SPI1_TXI = (0x31E), // Transmit buffer empty + ELC_EVENT_SPI1_IDLE = (0x31F), // Idle + ELC_EVENT_SPI1_ERI = (0x320), // Error + ELC_EVENT_SPI1_TEI = (0x321), // Transmission complete event + ELC_EVENT_CAN_RXF = (0x322), // Global receive FIFO interrupt + ELC_EVENT_CAN_GLERR = (0x323), // Global error + ELC_EVENT_CAN0_DMAREQ0 = (0x324), // RX fifo DMA request 0 + ELC_EVENT_CAN0_DMAREQ1 = (0x325), // RX fifo DMA request 1 + ELC_EVENT_CAN1_DMAREQ0 = (0x328), // RX fifo DMA request 0 + ELC_EVENT_CAN1_DMAREQ1 = (0x329), // RX fifo DMA request 1 + ELC_EVENT_CAN0_TX = (0x32C), // Transmit interrupt + ELC_EVENT_CAN0_CHERR = (0x32D), // Channel error + ELC_EVENT_CAN0_COMFRX = (0x32E), // Common FIFO receive interrupt + ELC_EVENT_CAN0_CF_DMAREQ = (0x32F), // Channel DMA request + ELC_EVENT_CAN0_RXMB = (0x330), // Receive message buffer interrupt + ELC_EVENT_CAN1_TX = (0x331), // Transmit interrupt + ELC_EVENT_CAN1_CHERR = (0x332), // Channel error + ELC_EVENT_CAN1_COMFRX = (0x333), // Common FIFO receive interrupt + ELC_EVENT_CAN1_CF_DMAREQ = (0x334), // Channel DMA request + ELC_EVENT_CAN1_RXMB = (0x335), // Receive message buffer interrupt + ELC_EVENT_CAN0_MRAM_ERI = (0x338), // CANFD0 ECC error + ELC_EVENT_CAN1_MRAM_ERI = (0x339), // CANFD1 ECC error + ELC_EVENT_I3C0_RESPONSE = (0x33A), // Response status buffer full + ELC_EVENT_I3C0_COMMAND = (0x33B), // Command buffer empty + ELC_EVENT_I3C0_IBI = (0x33C), // IBI status buffer full + ELC_EVENT_I3C0_RX = (0x33D), // Receive + ELC_EVENT_IICB0_RXI = (0x33D), // Receive + ELC_EVENT_I3C0_TX = (0x33E), // Transmit + ELC_EVENT_IICB0_TXI = (0x33E), // Transmit + ELC_EVENT_I3C0_RCV_STATUS = (0x33F), // Receive status buffer full + ELC_EVENT_I3C0_HRESP = (0x340), // High priority response queue full + ELC_EVENT_I3C0_HCMD = (0x341), // High priority command queue empty + ELC_EVENT_I3C0_HRX = (0x342), // High priority rx data buffer full + ELC_EVENT_I3C0_HTX = (0x343), // High priority tx data buffer empty + ELC_EVENT_I3C0_TEND = (0x344), // Transmit end + ELC_EVENT_IICB0_TEI = (0x344), // Transmit end + ELC_EVENT_I3C0_EEI = (0x345), // Error + ELC_EVENT_IICB0_ERI = (0x345), // Error + ELC_EVENT_I3C0_STEV = (0x346), // Synchronous timing + ELC_EVENT_I3C0_MREFOVF = (0x347), // MREF counter overflow + ELC_EVENT_I3C0_MREFCPT = (0x348), // MREF capture + ELC_EVENT_I3C0_AMEV = (0x349), // Additional master-initiated bus event + ELC_EVENT_I3C0_WU = (0x34A), // Wake-up Condition Detection interrupt + ELC_EVENT_ADC_LIMCLPI = (0x34B), // Limiter clip interrupt with the limit table 0 to 7 + ELC_EVENT_ADC_FIFOOVF = (0x34C), // FIFO data overflow + ELC_EVENT_ADC_ADI0 = (0x34D), // End of A/D scanning operation(Gr.0) + ELC_EVENT_ADC_ADI1 = (0x34E), // End of A/D scanning operation(Gr.1) + ELC_EVENT_ADC_ADI2 = (0x34F), // End of A/D scanning operation(Gr.2) + ELC_EVENT_ADC_ADI3 = (0x350), // End of A/D scanning operation(Gr.3) + ELC_EVENT_ADC_ADI4 = (0x351), // End of A/D scanning operation(Gr.4) + ELC_EVENT_ADC_ADI5 = (0x352), // End of A/D scanning operation(Gr.5) + ELC_EVENT_ADC_ADI6 = (0x353), // End of A/D scanning operation(Gr.6) + ELC_EVENT_ADC_ADI7 = (0x354), // End of A/D scanning operation(Gr.7) + ELC_EVENT_ADC_ADI8 = (0x355), // End of A/D scanning operation(Gr.8) + ELC_EVENT_ADC_FIFOREQ0 = (0x356), // FIFO data read request interrupt(Gr.0) + ELC_EVENT_ADC_FIFOREQ1 = (0x357), // FIFO data read request interrupt(Gr.1) + ELC_EVENT_ADC_FIFOREQ2 = (0x358), // FIFO data read request interrupt(Gr.2) + ELC_EVENT_ADC_FIFOREQ3 = (0x359), // FIFO data read request interrupt(Gr.3) + ELC_EVENT_ADC_FIFOREQ4 = (0x35A), // FIFO data read request interrupt(Gr.4) + ELC_EVENT_ADC_FIFOREQ5 = (0x35B), // FIFO data read request interrupt(Gr.5) + ELC_EVENT_ADC_FIFOREQ6 = (0x35C), // FIFO data read request interrupt(Gr.6) + ELC_EVENT_ADC_FIFOREQ7 = (0x35D), // FIFO data read request interrupt(Gr.7) + ELC_EVENT_ADC_FIFOREQ8 = (0x35E), // FIFO data read request interrupt(Gr.8) + ELC_EVENT_ADC_CMPI0 = (0x35F), // Compare match interrupt with compare table 0 + ELC_EVENT_ADC_CMPI1 = (0x360), // Compare match interrupt with compare table 1 + ELC_EVENT_ADC_CCMPM0 = (0x361), // Composite compare match 0 + ELC_EVENT_ADC_CCMPUM0 = (0x362), // Composite condition compare mismatch 0 + ELC_EVENT_ADC_ERR0 = (0x363), // A/D converter unit 0 Error + ELC_EVENT_ADC_RESOVF0 = (0x364), // A/D conversion overflow on A/D converter unit 0 + ELC_EVENT_ADC_CALREQ0 = (0x365), // Calibration request unit 0 + ELC_EVENT_ADC_CALEND0 = (0x366), // End of calibration of A/D converter unit 0 + ELC_EVENT_ADC_CMPI2 = (0x367), // Compare match interrupt with compare table 2 + ELC_EVENT_ADC_CMPI3 = (0x368), // Compare match interrupt with compare table 3 + ELC_EVENT_ADC_CCMPM1 = (0x369), // Composite compare match 1 + ELC_EVENT_ADC_CCMPUM1 = (0x36A), // Composite condition compare mismatch 1 + ELC_EVENT_ADC_ERR1 = (0x36B), // A/D converter unit 1 Error + ELC_EVENT_ADC_RESOVF1 = (0x36C), // A/D conversion overflow on A/D converter unit 1 + ELC_EVENT_ADC_CALREQ1 = (0x36D), // Calibration request unit 1 + ELC_EVENT_ADC_CALEND1 = (0x36E), // End of calibration of A/D converter unit 1 + ELC_EVENT_DOC_INT = (0x36F), // Data operation circuit interrupt + ELC_EVENT_RSIP_TADI = (0x371), // RSIP Tamper Detection + ELC_EVENT_GLCDC_LINE_DETECT = (0x382), // Specified line + ELC_EVENT_GLCDC_UNDERFLOW_1 = (0x383), // Graphic 1 underflow + ELC_EVENT_GLCDC_UNDERFLOW_2 = (0x384), // Graphic 2 underflow + ELC_EVENT_DRW_INT = (0x385), // DRW interrupt + ELC_EVENT_MIPIDSI_SEQ0 = (0x388), // Sequence operation channel 0 interrupt + ELC_EVENT_MIPIDSI_SEQ1 = (0x389), // Sequence operation channel 1 interrupt + ELC_EVENT_MIPIDSI_VIN1 = (0x38A), // Video-Input operation channel1 interrupt + ELC_EVENT_MIPIDSI_RCV = (0x38B), // DSI packet receive interrupt + ELC_EVENT_MIPIDSI_FERR = (0x38C), // DSI fatal error interrupt + ELC_EVENT_MIPIDSI_PPI = (0x38D), // DSI D-PHY PPI interrupt + ELC_EVENT_MIPICSI_RX = (0x38F), // Receive interrupt + ELC_EVENT_MIPICSI_DL = (0x390), // Data Lane interrupt + ELC_EVENT_MIPICSI_VC = (0x391), // Virtual Channel interrupt + ELC_EVENT_MIPICSI_PM = (0x392), // Power Management interrupt + ELC_EVENT_MIPICSI_GST = (0x393), // Generic Short Packet interrupt + ELC_EVENT_VIN_IRQ = (0x395), // Interrupt Request + ELC_EVENT_VIN_ERR = (0x396), // Interrupt Request for SYNC Error + ELC_EVENT_CEU_CEUI = (0x397) // CEU interrupt +} elc_event_t; + +#define BSP_PRV_VECT_ENUM(event,group) (ELC_ ## event) + +#define ELC_PERIPHERAL_NUM (33U) +#define BSP_OVERRIDE_ELC_PERIPHERAL_T +/** Possible peripherals to be linked to event signals + * @note This list is device specific. + * */ +typedef enum e_elc_peripheral +{ + ELC_PERIPHERAL_GPT_A = (0), + ELC_PERIPHERAL_GPT_B = (1), + ELC_PERIPHERAL_GPT_C = (2), + ELC_PERIPHERAL_GPT_D = (3), + ELC_PERIPHERAL_GPT_E = (4), + ELC_PERIPHERAL_GPT_F = (5), + ELC_PERIPHERAL_GPT_G = (6), + ELC_PERIPHERAL_GPT_H = (7), + ELC_PERIPHERAL_DAC0 = (12), + ELC_PERIPHERAL_DAC1 = (13), + ELC_PERIPHERAL_IOPORT1 = (14), + ELC_PERIPHERAL_IOPORT2 = (15), + ELC_PERIPHERAL_IOPORT3 = (16), + ELC_PERIPHERAL_IOPORT4 = (17), + ELC_PERIPHERAL_ADC0 = (19), + ELC_PERIPHERAL_ADC0_B = (20), + ELC_PERIPHERAL_ADC0_C = (21), + ELC_PERIPHERAL_ADC1 = (22), + ELC_PERIPHERAL_ADC1_B = (23), + ELC_PERIPHERAL_ADC1_C = (24), + ELC_PERIPHERAL_ADC2 = (25), + ELC_PERIPHERAL_ADC2_B = (26), + ELC_PERIPHERAL_ADC2_C = (27), + ELC_PERIPHERAL_I3C = (30), + ELC_PERIPHERAL_GPTP0 = (31), + ELC_PERIPHERAL_GPTP1 = (32) +} elc_peripheral_t; + +/** Positions of event link set registers (ELSRs) available on this MCU */ +#define BSP_ELC_PERIPHERAL_MASK (0x1CFFBF0FFU) + +/* UNCRUSTIFY-ON */ +/** @} (end addtogroup BSP_MCU_RA8P1) */ + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/ra8p1/bsp_feature.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/ra8p1/bsp_feature.h new file mode 100644 index 00000000000..901a901faaf --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/ra8p1/bsp_feature.h @@ -0,0 +1,622 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * + * AUTOGENERATED FILE. DO NOT EDIT. + * + **********************************************************************************************************************/ + +#ifndef BSP_FEATURE_H +#define BSP_FEATURE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +#include "bsp_peripheral.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** The main oscillator drive value is based upon the oscillator frequency selected in the configuration. */ +#define CGC_MAINCLOCK_DRIVE_RESERVED_MASK (0x10U) +#if (BSP_CFG_XTAL_HZ >= (24000000)) + #define CGC_MAINCLOCK_DRIVE (0x5U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#elif (BSP_CFG_XTAL_HZ >= (8000000)) + #define CGC_MAINCLOCK_DRIVE (0x3U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#else + #define CGC_MAINCLOCK_DRIVE (0x0U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#endif + +// *UNCRUSTIFY-OFF* + +#define BSP_FEATURE_ACMPHS_IS_AVAILABLE (1UL) +#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (1UL) // Operation stabilization wait time. +#define BSP_FEATURE_ACMPHS_VREF (ACMPHS_REFERENCE_IVREF2) // The IVREF selection that corresponds to the internal voltage reference. + +#define BSP_FEATURE_ACMPLP_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0UL) // Feature not available on this device. +#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ADC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (0UL) // Check to see if the ADADC register is available on any ADC peripheral. +#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0UL) // Check to see if the ADCALEXE register is available on any ADC peripheral. +#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_UNUSED) // Clock source used for the ADC peripheral. +#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (0UL) // The Extended Input Control Register (ADEXICR) controls if sensors are enabled per group. +#define BSP_FEATURE_ADC_HAS_ADBUF (0UL) // Determine if the ADBUFn registers are present. +#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (0UL) // Determine if the ADPRC field exists on the ADCER register. +#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (0UL) // Determine if the ADRFMT field exists on the ADCER register. +#define BSP_FEATURE_ADC_HAS_ADHVREFCNT (0UL) // Determine if the ADHVREFCNT register is available. +#define BSP_FEATURE_ADC_HAS_CLOCK (1UL) // Indicates there is a separate clock for the ADC. +#define BSP_FEATURE_ADC_HAS_PGA (0UL) // Determine if ADPGACR is present. +#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0UL) // Specifies configuration for the sample and hold circuit is available (specifically ADSHCR register). +#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0UL) // Determine if VREFAMPCNT is present. +#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (0UL) // Maximum ADC resolution supported. +#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150UL) // Minimum time, in nanoseconds, required for ADC sampling of the sensors. +#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0UL) // Specifies that the temperature and VREF sensors are exclusive to other ADC channel operations and cannot be executed concurrently. +#define BSP_FEATURE_ADC_TSN_SLOPE (4000UL) // DEPRECATED; use BSP_FEATURE_TSN_SLOPE. +#define BSP_FEATURE_ADC_UNIT_0_CHANNELS_MASK (0x00UL) // Mask of available channels in ADC unit 0. +#define BSP_FEATURE_ADC_UNIT_1_CHANNELS_MASK (0x00UL) // Mask of available channels in ADC unit 1. +#define BSP_FEATURE_ADC_VALID_UNIT_MASK (0x03UL) // Mask of whole, physical ADC units present in the MCU. + +#define BSP_FEATURE_ADC_B_IS_AVAILABLE (1UL) +#define BSP_FEATURE_ADC_B_PGA_CHANNEL_MASK (0x00UL) // Mask of ADC_B peripherals that support PGA. +#define BSP_FEATURE_ADC_B_PGA_SUPPORTED (0UL) // Programmable Gain Amplifier is supported. +#define BSP_FEATURE_ADC_B_TSN_SLOPE (4000UL) // DEPRECATED; use BSP_FEATURE_TSN_SLOPE. +#define BSP_FEATURE_ADC_B_UNIT_0_CHANNELS_MASK (0x00770373007F503FULL) // Mask of channels available to ADC_B Unit 0. +#define BSP_FEATURE_ADC_B_UNIT_1_CHANNELS_MASK (0x00770373007FAFC0ULL) // Mask of channels available to ADC_B Unit 1. + +#define BSP_FEATURE_ADC_D_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ADC_D_CHANNELS_MASK (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_D_SCAN_MODE_CHANNELS_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_AGT_IS_AVAILABLE (1UL) +#define BSP_FEATURE_AGT_AGT_CHANNEL_COUNT (2U) // Number of channels for only AGT (not AGTW) peripherals. +#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT (0U) // Number of channels for only AGTW (not AGT) peripherals. +#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0UL) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL for AGTW instances. +#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03UL) // A mask of all valid AGTx channels. + +#define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0UL) // Check for the ICSTATS bit field that specifies clock power architecture type. +#define BSP_FEATURE_BSP_HAS_DSMIF_CLOCK (0UL) // Flag indicating an extra peripheral clock is present. +#define BSP_FEATURE_BSP_HAS_DTCM (1UL) // Indicates DTCM is available. +#define BSP_FEATURE_BSP_HAS_ESC_CLOCK (0UL) // Flag indicating an extra peripheral clock is present. +#define BSP_FEATURE_BSP_HAS_ETHPHY_CLOCK (1UL) // Flag indicating an extra peripheral clock is present. +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0UL) // Indicates FSXP (subsystem clock) is available. +#define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (1UL) // Indicates that the MCU has a power domain specifically for graphics peripherals. +#define BSP_FEATURE_BSP_HAS_ITCM (1UL) // Indicates ITCM is available. +#define BSP_FEATURE_BSP_HAS_OFS2 (1UL) // Indicates the OFS2 register is available. +#define BSP_FEATURE_BSP_HAS_OFS3 (0UL) // OSF3 register is available; currently only available for RA8. +#define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0UL) // Indicates the MCU has security MPU systems available. +#define BSP_FEATURE_BSP_HAS_SP_MON (0UL) // Indicates the Stack Pointer monitor is available. +#define BSP_FEATURE_BSP_HAS_SYRACCR (1UL) // SYRACCR register is available. +#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0x00U) // Location of the FMIFRT register. +#define BSP_FEATURE_BSP_MMF_SUPPORTED (0UL) // Memory-mirror function is available. +#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00UL) // Mask for allowed address range of the MPU. +#define BSP_FEATURE_BSP_NUM_PMSAR (14UL) // Number of available Port Security Attribution Registers. +#define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (1UL) // Indicates security attribution settings for banks are present in the OFS registers. +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF1FFUL) // Inverted mask of the HOCOFRQx bit field of the OFS1 register. +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9UL) // Offset to the OFS1.HOCOFRQx bitfield. +#define BSP_FEATURE_BSP_OSIS_PADDING (0UL) // Indicates there is 32-bits of padding between each 32-bit word of the OSIS ID registers. +#define BSP_FEATURE_BSP_PART_NUMBER_OFFSET (0x00UL) // Bit offset of the Part Number in the mcu info block. +#define BSP_FEATURE_BSP_PART_NUMBER_POINTER (0x02C1EC38UL) // Address of the Part Numbering register (PNR). +#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0UL) // Indicates extra modules must be manually stopped before switching the system clock from the PLL. +#define BSP_FEATURE_BSP_RESET_TRNG (0UL) // Specifies the TRNG must be reset after clock initialization to prevent excess current draw. +#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0x00UL) // Bit offset of the Unique ID in the mcu info block. +#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER (0x02F07B00UL) // Address of the MCU Unique ID register (UIDR). +#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0UL) // VCC can switch to VBAT if the voltage drops too low. + +#define BSP_FEATURE_CAN_IS_AVAILABLE (0UL) +#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO_FLAG (0UL) // Feature not available on this device. +#define BSP_FEATURE_CAN_CLOCK (FSP_PRIV_CLOCK_UNUSED) // Feature not available on this device. +#define BSP_FEATURE_CAN_MCLOCK_ONLY (0UL) // Feature not available on this device. +#define BSP_FEATURE_CAN_NUM_CHANNELS (0UL) // Feature not available on this device. + +#define BSP_FEATURE_CANFD_IS_AVAILABLE (1UL) +#define BSP_FEATURE_CANFD_FD_SUPPORT (1UL) // Flexible data rate support. +#define BSP_FEATURE_CANFD_HAS_CLOCK (1UL) // Indicates there is a separate clock for the CANFD. +#define BSP_FEATURE_CANFD_LITE (1UL) // CANFD Lite or CANFD_B is the standard CAN peripheral for new designs. +#define BSP_FEATURE_CANFD_NUM_CHANNELS (1UL) // Number of CANFD channels per CANFD peripheral instance. +#define BSP_FEATURE_CANFD_NUM_INSTANCES (2UL) // Number of hardware instances of the CANFD peripheral. + +#define BSP_FEATURE_CEC_IS_AVAILABLE (0UL) +#define BSP_FEATURE_CEC_HAS_CLOCK (0UL) // Feature not available on this device. + +#define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (0UL) // Indicates the system clock can be sourced by the LOCO. +#define BSP_FEATURE_CGC_HAS_BCLK (1UL) // External Bus Clock is available. +#define BSP_FEATURE_CGC_HAS_CPUCLK (1UL) // CPU Clock is available. +#define BSP_FEATURE_CGC_HAS_CPUCLK1 (1UL) // CPU1 Clock is available. +#define BSP_FEATURE_CGC_HAS_FCLK (1UL) // FlashIF clock is available. +#define BSP_FEATURE_CGC_HAS_FLDWAITR (0UL) // FLDWAITR register is available. +#define BSP_FEATURE_CGC_HAS_FLL (1UL) // FLL is available. +#define BSP_FEATURE_CGC_HAS_FLWT (0UL) // FLWT register is available. +#define BSP_FEATURE_CGC_HAS_HOCOWTCR (0UL) // HOCOWTCR register is available. +#define BSP_FEATURE_CGC_HAS_MEMWAIT (0UL) // MEMWAIT register is available. +#define BSP_FEATURE_CGC_HAS_MOCO (1UL) // Middle clock oscillator is available. +#define BSP_FEATURE_CGC_HAS_MOSC (1UL) // Main clock oscillator is available. +#define BSP_FEATURE_CGC_HAS_MRICLK (1UL) // MRAM bus clock is available. +#define BSP_FEATURE_CGC_HAS_NPUCLK (1UL) // NPU clock is available. +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0UL) // OSTDCSE register is available. +#define BSP_FEATURE_CGC_HAS_PCLKA (1UL) // Peripheral module clock A is available. +#define BSP_FEATURE_CGC_HAS_PCLKB (1UL) // Peripheral module clock B is available. +#define BSP_FEATURE_CGC_HAS_PCLKC (1UL) // Peripheral module clock C is available. +#define BSP_FEATURE_CGC_HAS_PCLKD (1UL) // Peripheral module clock D is available. +#define BSP_FEATURE_CGC_HAS_PCLKE (1UL) // Peripheral module clock E is available. +#define BSP_FEATURE_CGC_HAS_PLL (1UL) // PLL is available. +#define BSP_FEATURE_CGC_HAS_PLL2 (1UL) // PLL2 is available. +#define BSP_FEATURE_CGC_HAS_SOPCCR (0UL) // SOPCCR register is available. +#define BSP_FEATURE_CGC_HAS_SOSC (1UL) // Sub-clock oscillator is available. +#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0UL) // SRAMPRCR2 register is available. +#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1UL) // SRAM Wait State Control Register is available. +#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0UL) // Changes to OPCCR must only occur with HOCO is stopped or stable. +#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0UL) // HOCO wait control register changes value for 64 MHz speed. +#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0UL) // HOCO stabilization wait time when using SCI0. +#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (0UL) // HOCO stabilization wait time register value for 64 MHz. +#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_1) // Reset value of the ICLK divider. +#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61UL) // LOCO stabilization time in microseconds. +#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000UL) // Maximum frequency during low-speed operation. +#define BSP_FEATURE_CGC_LOW_SPEED_SUPPORT_MAIN_OSC (1UL) // The main clock oscillator is available in low-speed mode. +#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0UL) // Maximum frequency during low-voltage mode. +#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0UL) // Middle speed clock maximum frequency. +#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15UL) // MOCO stabilization time in microseconds. +#define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) // Mask used on MODRV register. +#define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) // Shift used for MODRV register. +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1UL) // Oscillation stop detection is available. +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (960000000UL) // Maximum allowed clock speed when HOCO is the PLL source clock for the CPUCLK. +#define BSP_FEATURE_CGC_PLL_INPUT_POST_DIV_MAX_HZ (24000000UL) // Maximum input frequency for PLL (after input divider). +#define BSP_FEATURE_CGC_PLL_INPUT_POST_DIV_MIN_HZ (8000000UL) // Minimum input frequency for PLL (after input divider). +#define BSP_FEATURE_CGC_PLL_INPUT_PRE_DIV_MAX_HZ (48000000UL) // Maximum input frequency of the PLL (before input divider). +#define BSP_FEATURE_CGC_PLL_INPUT_PRE_DIV_MIN_HZ (8000000UL) // Minimum input frequency of the PLL (before input divider). +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (1200000000UL) // Maximum output frequency for PLL unit 1. +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (60000000UL) // Minimum output frequency for PLL unit 1. +#define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (3UL) // Number of output clocks for PLL1. +#define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (3UL) // Number of output clocks for PLL2. +#define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (1200000000UL) // Maximum output frequency for PLL unit 2. +#define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (60000000UL) // Minimum output frequency for PLL unit 2. +#define BSP_FEATURE_CGC_PLLCCR_TYPE (6UL) // Indicates the type of PLLCCR register and PLL. +#define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (2400000000UL) // PLL VCO maximum frequency. +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (960000000UL) // PLL VCO minimum frequency. +#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0UL) // Time required, in microseconds, between changing PLLCCR.PLLMUL to clearing PLLCR.PLLSTP. +#define BSP_FEATURE_CGC_REGISTER_SET_B (0UL) // Clock generation uses an alternative register set. +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0UL) // Requires the SCKDIVCR.BCLK bits [18:16] to match SCKDIVCR.PCLKB. +#define BSP_FEATURE_CGC_SCKDIVCR2_CPUCLK1_MATCHES_MRICLK (BSP_NUMBER_OF_CORES == 2U ? 0U : 1U) // Requires the SCKDIVCR2.CPUCLK1 bits to match SCKDIVCR2.MRICLK. +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (1UL) // Indicates the SCKDIVCR2 register has additional clocks. +#define BSP_FEATURE_CGC_SCKDIVCR2_NPUCLK_MATCHES_MRICLK (0UL) // Requires the bits [11:8] to match SCKDIVCR2.MRICLK. +#define BSP_FEATURE_CGC_SODRV_MASK (0x03UL) // Sub-clock drive field mask. +#define BSP_FEATURE_CGC_SODRV_SHIFT (0UL) // Sub-clock drive field shift. +#define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (8UL) // Bit offset for SRAMPRCR.KW field. +#define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0xA5U) // Write enable key code for SRAMPRCR bit. +#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0x00UL) // Reset value for the OPCCR regsiter. +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x00UL) // Reset value for the SCKDIVCR register. +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00UL) // Reset value for the SCKDIVCR2 register. +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01UL) // Reset value for the SCKSCR register. + +#define BSP_FEATURE_CRC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1UL) // The CRC peripheral supports both LSB- and MSB-first calculations. +#define BSP_FEATURE_CRC_HAS_SNOOP (1UL) // The CRC peripheral can snoop on (monitor a) SCI data register for data to checksum. +#define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) // Mask of available CRC polynomials; should match the mask of indexes relating to r_crc_api.h::crc_polynomial_t. +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x04UL) // Used to indicate the type of register being snooped on; derived from the least-significant nybble of the address of SCI TDR registers. + +#define BSP_FEATURE_CTSU_IS_AVAILABLE (0UL) +#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (0UL) // Feature not available on this device. +#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (0UL) // Feature not available on this device. +#define BSP_FEATURE_CTSU_HAS_TXVSEL (0UL) // Feature not available on this device. +#define BSP_FEATURE_CTSU_VERSION (0UL) // Feature not available on this device. + +#define BSP_FEATURE_DAC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0x00UL) // DAADSCR register is available. +#define BSP_FEATURE_DAC_B_CHANNELS_PER_UNIT (1UL) // Number of available channels per DAC_B instance. +#define BSP_FEATURE_DAC_B_UNIT_COUNT (2UL) // Number of available DAC_B instance. +#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0UL) // DAPC register is available. +#define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (0UL) // At least one channel supports A/D synchronization with the DAC. +#define BSP_FEATURE_DAC_HAS_DAASWCR_INTERNAL_OUTPUT_CONTROL (0UL) // DAC output can be routed to specific extra internal modules using DAASWCR register. +#define BSP_FEATURE_DAC_HAS_DAVREFCR (0UL) // DAVREFCR register is available. +#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (0UL) // DAAMPCR register is available. + +#define BSP_FEATURE_DAC8_IS_AVAILABLE (0UL) +#define BSP_FEATURE_DAC8_CHANNELS_PER_UNIT (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_UNIT_COUNT (0UL) // Feature not available on this device. + +#define BSP_FEATURE_DAC12_IS_AVAILABLE (0UL) +#define BSP_FEATURE_DAC12_CHANNELS_PER_UNIT (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC12_UNIT_COUNT (0UL) // Feature not available on this device. + +#define BSP_FEATURE_DMAC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_DMAC_HAS_DELSR (0UL) // DELSRn registers are available in the DMA peripheral block. +#define BSP_FEATURE_DMAC_HAS_DMCTL (1UL) // DMCTL register is available in the DMA peripheral block. +#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1UL) // DMTMD register's MD bit-field allows repeat-block transfers (value: 0b11). +#define BSP_FEATURE_DMAC_NUM_CHANNELS (8UL) // Number of DMAC channels available. + +#define BSP_FEATURE_DOC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_DOC_VERSION (2UL) // The version of the DOC peripheral. + +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (16UL) // Byte alignment that must be used for DTC transfer info structs. + +#define BSP_FEATURE_DWT_CYCCNT (1UL) // CYCNT register is available on CM33 and higher devices. + +#define BSP_FEATURE_ELC_VERSION (2UL) // Version of the ELC peripheral. + +#define BSP_FEATURE_ESC_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ESC_NUM_PORTS (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ESWM_IS_AVAILABLE (1UL) +#define BSP_FEATURE_ESWM_ETHA_IPV_QUEUE_NUM (8UL) // Number of IPV based transmission queue for each port. +#define BSP_FEATURE_ESWM_FRER_TABLE_SIZE (128UL) // Maximum number of FRER table entry. +#define BSP_FEATURE_ESWM_GPTP_PULSE_GENERATOR_NUM (4UL) // Number of Pulse Generator. +#define BSP_FEATURE_ESWM_GPTP_TIMER_NUM (2UL) // Number of gPTP timer. +#define BSP_FEATURE_ESWM_GWCA_PORT (2UL) // Port number of the CPU. +#define BSP_FEATURE_ESWM_HAS_CLOCK (1UL) // Flag indicating an extra peripheral clock is present. +#define BSP_FEATURE_ESWM_HAS_DOMAIN (1UL) // Indicates that the MCU has a power domain specifically for ESWM peripherals. +#define BSP_FEATURE_ESWM_HAS_ESWPHY_CLOCK (1UL) // Flag indicating an extra peripheral clock is present. +#define BSP_FEATURE_ESWM_MAX_QUEUE_NUM (64UL) // The number of AXI bus descriptors available to Ethernet components. +#define BSP_FEATURE_ESWM_TS_DESCRIPTOR_QUEUE_MAX_NUM (2UL) // Number of TS reception descriptor queue. + +#define BSP_FEATURE_ETHER_IS_AVAILABLE (1UL) +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0x070FUL) // Valid value of EDMACn.FDR register. +#define BSP_FEATURE_ETHER_MAX_QUEUE_NUM (64UL) // The number of AXI bus descriptors available to Ethernet components. +#define BSP_FEATURE_ETHER_NUM_CHANNELS (2UL) // Number of available ethernet PHYs. +#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (1UL) // Whether or not the ETHERC peripheral supports TrustZone secure access. + +#define BSP_FEATURE_FLASH_ARC_NSEC_MULTIPLE_MAX_COUNT (64UL) // Number of bits per counter when ARC_NSEC is configured as multiple counters. +#define BSP_FEATURE_FLASH_ARC_NSEC_NUM_COUNTERS (4L) // Number of non-secure application anti-rollback counters that can be configured. +#define BSP_FEATURE_FLASH_ARC_NSEC_SINGLE_MAX_COUNT (256UL) // Number of counter bits available when using the ARC_NSEC counter as a single, large counter. +#define BSP_FEATURE_FLASH_ARC_OEMBL_MAX_COUNT (64UL) // Number of counter bits for the ARC_OEMBL counter. +#define BSP_FEATURE_FLASH_ARC_SEC_MAX_COUNT (64UL) // Number of counter bits for the ARC_SEC counter. +#define BSP_FEATURE_FLASH_CACHE (0UL) // Flash cache is present. +#define BSP_FEATURE_FLASH_CACHE_DISABLE_OPM (0UL) // Constraints exist for flash cache operation either during power mode sequencing or flash programming access. +#define BSP_FEATURE_FLASH_CODE_CACHE_VERSION (2UL) // Version of C-Cache implemented in a CM33 core. +#define BSP_FEATURE_FLASH_CODE_FLASH_START (0x02000000UL) // Start address of the Code Flash region. +#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x27000000UL) // Start address of the Data Flash region. +#define BSP_FEATURE_FLASH_PREFETCH_BUFFER (0UL) // Indicates the prefetch buffer is available on the flash. +#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0UL) // Flash supports protected access window (AWS register is available). +#define BSP_FEATURE_FLASH_SUPPORTS_ANTI_ROLLBACK (1UL) // Flash supports anti-rollback counter (ARC_* registers are available). +#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0UL) // ID code is supported (OSIS register is available). +#define BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_SIZE (0UL) // Size of the user lockable areas (non-OFS registers). +#define BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_START (0x00UL) // Start address of the first non-OFS lockable word by LK_CD_A0. + +#define BSP_FEATURE_FLASH_HP_IS_AVAILABLE (0UL) +#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (0UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (0UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (0UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_HP_FCACHE_DISABLE_BEFORE_PE (0UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_HP_HAS_BANKSEL (0UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (0UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (0UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_HP_VERSION (0UL) // Feature not available on this device. + +#define BSP_FEATURE_FLASH_LP_IS_AVAILABLE (0UL) +#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (FSP_PRIV_CLOCK_UNUSED) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_VERSION (0UL) // Feature not available on this device. + +#define BSP_FEATURE_GPT_IS_AVAILABLE (1UL) +#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x3FFFUL) // Mask of 32-bit GPT channel indices. +#define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0x3FFFUL) // Mask of GPT channels supporting A/D conversion start. +#define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (1UL) // At least one GPT channel with A/D conversion start is available. +#define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2UL) // Multiplicative step size of the clock divider (GTCR.TPCS). +#define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0UL) // Whether or not the bit-values of 0b0111 and 0b1001 are valid divider settings (GTCR.TPCS). +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x3FFFUL) // Mask of channels that support event count input (has GTUPSR register). +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1UL) // At least one channel supports event counts. +#define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0x3FF0UL) // Mask of GPT channels that are the GPTE implementation. +#define BSP_FEATURE_GPT_GPTE_SUPPORTED (1UL) // At least one GPTE implementation is available, GPTE implementations have a GTITC register. +#define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0x0FUL) // Mask of GPT channels that are the GPTEH implementation. +#define BSP_FEATURE_GPT_GPTEH_SUPPORTED (1UL) // At least one GPTEH implementation is available, GPTEH implementations have a PDG module. +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x3FFFUL) // Mask of channels that support dead time control. +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1UL) // At least one GPT channel with GTDVU support is available. +#define BSP_FEATURE_GPT_MSTP_HAS_MSTPCRE (1UL) // Indicates the MSTP peripheral has an MSTPCRE register. +#define BSP_FEATURE_GPT_MSTP_MSTPD5 (0UL) // GPT stop bits use MSTPCRD.MSTPD5. +#define BSP_FEATURE_GPT_MSTP_MSTPD5_MAX_CH (0UL) // Largest channel number associated with GPT on the MSTPCRD.MSTPD5 field on this MCU. +#define BSP_FEATURE_GPT_ODC_128_RESOLUTION_CHANNEL_MASK (0x00UL) // Mask of PWM channels which support 128-bit delay resolution. +#define BSP_FEATURE_GPT_ODC_128_RESOLUTION_SUPPORTED (0UL) // The PWM delay circuit supports 128-bit resolution for delays. +#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (160000000UL) // Minimum frequency for standard PDG operation, must set GTCLYCR.FRANGE bit below this value. +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) ((BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN <= (gpt_frequency)) ? 1UL : 0UL) // Obtains the set bit based on the GPT frequency and the FRANGE threshold. +#define BSP_FEATURE_GPT_ODC_FREQ_MAX (300000000UL) // Maximum supported frequency of the PWM Delay Generation circuit. +#define BSP_FEATURE_GPT_ODC_FREQ_MIN (80000000UL) // Minimum supported frequency of the PWM Delay Generation circuit. +#define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0x01UL) // Mask of channels supporting output phase switching. +#define BSP_FEATURE_GPT_OPS_SUPPORTED (1UL) // At least one GPT channel with OPS support is available. +#define BSP_FEATURE_GPT_POLARITY_CONTROL_SUPPORTED (1UL) // At least one GPT channel supports polarity inversion of the GTIOCnA or GTIOCnB I/O pins. +#define BSP_FEATURE_GPT_TPCS_SHIFT (0UL) // Shift value to convert TPCS bit values to real multiplicative values. + +#define BSP_FEATURE_I3C_IS_AVAILABLE (1UL) +#define BSP_FEATURE_I3C_HAS_CLOCK (1UL) // Indicates there is a separate clock for the I3C. +#define BSP_FEATURE_I3C_HAS_HDR_MODE (1UL) // I3C support high data rate mode. +#define BSP_FEATURE_I3C_MAX_DEV_COUNT (8UL) // Maximum number of bus devices. +#define BSP_FEATURE_I3C_MSTP_OFFSET (4UL) // Offset of the MSTP bit for the I3C peripherals. +#define BSP_FEATURE_I3C_NTDTBP0_DEPTH (16UL) // Depth of the normal transmit data buffer. +#define BSP_FEATURE_I3C_NUM_CHANNELS (1UL) // Total number of available channels. + +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0UL) // Number of IELSRn registers that have a fixed event source. +#define BSP_FEATURE_ICU_HAS_FILTER (1UL) // ICU contains digital input filtering. +#define BSP_FEATURE_ICU_HAS_IELSR (1UL) // ICU Event Link is available. +#define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0UL) // Indicates that event links are grouped with multiple sources. +#define BSP_FEATURE_ICU_HAS_LOCO_FILTER (0UL) // Register IRQCR has LOCOSEL. +#define BSP_FEATURE_ICU_HAS_WUPEN1 (1UL) // WUPEN1 register is available. +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0UL) // WUPEN2 register is available. +#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFFFFFUL) // Mask of available IRQ control registers. +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (20UL) // Maximum bit field index of valid fields of the NMIER register. +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0x00ULL) // A mask of valid bits for [SBYEDCR1:SBYEDCR0]. +#define BSP_FEATURE_ICU_WUPEN_MASK (0xFFFFFF88FF1DFFFFULL) // A mask of valid bits for [WUPEN1:WUPEN0]. + +#define BSP_FEATURE_IIC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_IIC_B_BUS_FREE_TIME_MULTIPLIER (5UL) // Multiplication factor to calculate SDA bus free time. +#define BSP_FEATURE_IIC_B_CHECK_SCILV_BEFORE_MASTER_WRITE_TX_DATA (0UL) // SCL status needs to be checked before writing the transmission data in master mode. +#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS_CHANNELS_MASK (0x01UL) // Mask of channels which support "Fast Mode Plus": up to 1 Mbps bit rates. +#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0x01UL) // Mask of available IIC_B or compatible I3C channels. +#define BSP_FEATURE_IIC_FAST_MODE_PLUS_CHANNELS_MASK (7UL) // Mask of channels which support "Fast Mode Plus": up to 1 Mbps bit rates. +#define BSP_FEATURE_IIC_HAS_CLOCK (0UL) // Indicates there is a separate IIC clock. +#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x07UL) // Mask of available IIC channels. + +#define BSP_FEATURE_IOPORT_CCD_PINS_MASK (0x00UL) // Mask of valid indices for CCD pins. +#define BSP_FEATURE_IOPORT_ELC_PORTS_MASK (0x1EUL) // Mask of valid indices for ELC signal mapping of port input data. +#define BSP_FEATURE_IOPORT_HAS_LVOCR (1UL) // The LVOCR register is available. +#define BSP_FEATURE_IOPORT_VERSION (2UL) // Version of the system PFS block. + +#define BSP_FEATURE_IWDT_IS_AVAILABLE (1UL) +#define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (16384UL) // Frequency of the independent watchdog clock source. +#define BSP_FEATURE_IWDT_SUPPORTS_REGISTER_START_MODE (1UL) // IWDT peripheral supports register start mode. + +#define BSP_FEATURE_KINT_IS_AVAILABLE (0UL) +#define BSP_FEATURE_KINT_HAS_MSTP (0UL) // Feature not available on this device. + +#define BSP_FEATURE_LCD_HAS_CLOCK (1UL) // Indicates there is a separate clock for the LCD. + +#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY {} // An array of tuples (MSTP index, bit) that indicate which modules must enter the stop state before the system enters low power mode or when changes to SCKDIVCR are made. +#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0UL) // Indicates some modules must be explicitly stopped before entering low power modes or changing SCKDIVCR. +#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x000000FFFF13FFFFULL) // Mask of valid bit-fields of the DPSIEGRn registers. +#define BSP_FEATURE_LPM_DPSIER_MASK (0x0000FFFFEF1FFFFFULL) // Mask of valid bit-fields of the DPSIERn registers. +#define BSP_FEATURE_LPM_HAS_DCDC_REGULATOR (0UL) // DCDCCTL register is present in SYSC. +#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (1UL) // The device supports deep sleep mode. +#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1UL) // The device supports deep standby mode. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DCSSMODE (1UL) // The DPSBYCR.DCSSMODE field is available. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (0UL) // The DPSBYCR.DEEPCUT field is available. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (0UL) // The DPSBYCR.DPSBY field is available. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0UL) // The DPSBYCR.SRKEEP field is available. +#define BSP_FEATURE_LPM_HAS_DPSIEGR3 (1UL) // The DPSIEGR3 register is available. +#define BSP_FEATURE_LPM_HAS_DPSIEGR4 (1UL) // The DPSIEGR4 register is available. +#define BSP_FEATURE_LPM_HAS_DPSIER4 (1UL) // The DPSIER4 register is available. +#define BSP_FEATURE_LPM_HAS_DPSIER5 (1UL) // The DPSIER5 register is available. +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0UL) // The SBYCR.FLSTP field is available. +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0UL) // The SBYCR.FWKUP field is available. +#define BSP_FEATURE_LPM_HAS_LDO_SKEEP (1UL) // PLL1LDOCR, PLL2LDOCR and HOCOLDOCR registers are available. +#define BSP_FEATURE_LPM_HAS_LPSCR (1UL) // The LPSCR register is available. +#define BSP_FEATURE_LPM_HAS_PDRAMSCR (1UL) // The PDRAMSCRn registers are available. +#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1UL) // The SBYCR.OPE field is available. +#define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (0UL) // The SBYCR.SSBY field is available. +#define BSP_FEATURE_LPM_HAS_SNOOZE (0UL) // The MCU supports Snooze. +#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0UL) // The SNZEDCR1 register is available. +#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0UL) // The SNZREQCR1 register is available. +#define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0UL) // The SBYCR.RTCLPC field is available. +#define BSP_FEATURE_LPM_HAS_STCONR (0UL) // The STCONR register is available. +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0UL) // RTC registers' clock should be disabled for additional power savings in LPM. +#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0UL) // Indicates that bit 14 of the SBYCR register should always be set. +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x00UL) // Mask of valid bits for the SNZEDCRn registers. +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x00ULL) // Mask of valid bits for the SNZREQCRn registers. +#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (1UL) // The Middle-speed On-Chip Oscillator must be operating prior to entering standby mode. +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0UL) // DTCST register must be cleared prior to entering standby mode. + +#define BSP_FEATURE_LVD_IS_AVAILABLE (1UL) +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0UL) // Detection delay time for EXLVD pin input. +#define BSP_FEATURE_LVD_EXLVDVBAT_HI_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VBAT reference voltage high threshold. +#define BSP_FEATURE_LVD_EXLVDVBAT_LOW_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VBAT reference voltage low threshold. +#define BSP_FEATURE_LVD_EXLVDVRTC_HI_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VRTC reference voltage high threshold. +#define BSP_FEATURE_LVD_EXLVDVRTC_LOW_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VRTC reference voltage low threshold. +#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1UL) // Digital input filtering is available. +#define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0UL) // Voltage monitoring is available for an external power supply via pin. +#define BSP_FEATURE_LVD_HAS_LVDLVLR (0UL) // LVDLVLR register is available. +#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_LEVEL_3_86V) // Typical higher bound of the detection threshold for LVD1. +#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_LEVEL_1_71V) // Typical lower bound of the detection threshold for LVD1. +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (30UL) // Maximum stabilization time to wait after LVD1 is enabled. +#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_LEVEL_3_86V) // Typical higher bound of the detection threshold for LVD2. +#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_LEVEL_1_71V) // Typical lower bound of the detection threshold for LVD2. +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (30UL) // Maximum stabilization time to wait after LVD2 is enabled. +#define BSP_FEATURE_LVD_MONITOR_MASK (0x1BUL) // Mask of programmable monitors. +#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (1UL) // Voltage monitors support rising edge detections (i.e. +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0UL) // Detection delay time for EXLVDVBAT pin input. +#define BSP_FEATURE_LVD_VERSION (3UL) // Version of the LVD peripheral. +#define BSP_FEATURE_LVD_VRTC_LVL_STABILIZATION_TIME_US (0UL) // Stabilization wait time after writing to VRTLVDCR.LVL. +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0UL) // Detection delay time for VRTC pin input. + +#define BSP_FEATURE_MACL_SUPPORTED (0UL) // On-chip multiplier and multiply-accumulator is available. + +#define BSP_FEATURE_MIPI_CSI_IS_AVAILABLE (1UL) + +#define BSP_FEATURE_MIPI_DSI_IS_AVAILABLE (1UL) + +#define BSP_FEATURE_MIPI_PHY_IS_AVAILABLE (1UL) + +#define BSP_FEATURE_MRAM_IS_AVAILABLE (1UL) +#define BSP_FEATURE_MRAM_PROGRAMMING_SIZE_BYTES (32UL) // Write size for code MRAM. + +#define BSP_FEATURE_OPAMP_IS_AVAILABLE (0UL) +#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_OSPI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x80000000UL) // Start address of the CS0 memory mapped region for OSPI. +#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x90000000UL) // Start address of the CS1 memory mapped region for OSPI. +#define BSP_FEATURE_OSPI_HAS_CLOCK (1UL) // Indicates there is a separate clock for the OSPI. + +#define BSP_FEATURE_OSPI_B_IS_AVAILABLE (1UL) +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0x80000000UL) // Start address of the CS0 memory mapped region for OSPI_B. +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0x90000000UL) // Start address of the CS1 memory mapped region for OSPI_B. +#define BSP_FEATURE_OSPI_B_UNIT_COUNT (2UL) // Number of OSPI_B peripheral units available. + +#define BSP_FEATURE_POEG_CHANNEL_MASK (0x0FUL) // Mask of valid channels for POEG. +#define BSP_FEATURE_POEG_HAS_POEGG_DERRST (0UL) // Indicates POEGG.DERRSTn registers are available. +#define BSP_FEATURE_POEG_MSTP_MSTPD13 (0UL) // Indicates the MSTP uses bit 13 of MSTPCRD to control the POEG. + +#define BSP_FEATURE_QSPI_IS_AVAILABLE (0UL) +#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_RSIP_AES_B_SUPPORTED (0UL) // The device supports cryptography using AES_B. +#define BSP_FEATURE_RSIP_AES_SUPPORTED (0UL) // The device supports cryptography using AES. +#define BSP_FEATURE_RSIP_RSIP_E11A_SUPPORTED (0UL) // The device supports cryptography using RSIP-E11A. +#define BSP_FEATURE_RSIP_RSIP_E31A_SUPPORTED (0UL) // The device supports cryptography using RSIP-E31A. +#define BSP_FEATURE_RSIP_RSIP_E50D_SUPPORTED (1UL) // The device supports cryptography using RSIP-E50D. +#define BSP_FEATURE_RSIP_RSIP_E51A_SUPPORTED (0UL) // The device supports cryptography using RSIP-E51A. +#define BSP_FEATURE_RSIP_SCE5_SUPPORTED (0UL) // The device supports cryptography using SCE5. +#define BSP_FEATURE_RSIP_SCE5B_SUPPORTED (0UL) // The device supports cryptography using SCE5B. +#define BSP_FEATURE_RSIP_SCE7_SUPPORTED (0UL) // The device supports cryptography using SCE7. +#define BSP_FEATURE_RSIP_SCE9_SUPPORTED (0UL) // The device supports cryptography using SCE9. +#define BSP_FEATURE_RSIP_TRNG_SUPPORTED (0UL) // The device supports a TRNG module. + +#define BSP_FEATURE_RTC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_RTC_HAS_ALARM1 (0UL) // Alarm 1 is available. +#define BSP_FEATURE_RTC_HAS_RADJ_ADJ6 (0UL) // ADJ6 is appended to upper part of RADJ.ADJ[0:5] as ADJ[6]. +#define BSP_FEATURE_RTC_HAS_ROPSEL (0UL) // The RCR4.ROPSEL field is available. +#define BSP_FEATURE_RTC_HAS_TCEN (1UL) // Timer capture is available. +#define BSP_FEATURE_RTC_HAS_VBTICTLR (1UL) // System supports VBATT input control to the RTC. +#define BSP_FEATURE_RTC_IS_IRTC (0UL) // RTC has a separate power domain (VRTC) for the sub-clock oscillator and RTC peripheral. +#define BSP_FEATURE_RTC_RTCCR_CHANNELS (3UL) // Number of RTCCRn registers that are available. + +#define BSP_FEATURE_SAU_IS_AVAILABLE (0UL) +#define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_SCI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS_MASK (0x00UL) // Mask of channels with data compare match (DCCR) available. +#define BSP_FEATURE_SCI_CHANNELS_MASK (0x03FFUL) // Mask of available SCI channels. +#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) // Clock source routed to the SCI peripherals. +#define BSP_FEATURE_SCI_HAS_CLOCK (1UL) // Indicates there is a separate SCI clock. +#define BSP_FEATURE_SCI_HAS_SCISPI_CLOCK (0UL) // Indicates there is a separate SCI SPI clock. +#define BSP_FEATURE_SCI_IRDA_CHANNEL_MASK (0x00UL) // Mask of channels that support IrDA. +#define BSP_FEATURE_SCI_IRDA_SUPPORTED (0UL) // Indicates IrDA is supported on at least one SCI channel. +#define BSP_FEATURE_SCI_LIN_CHANNELS_MASK (0x03FFUL) // Mask of channels that can support LIN. +#define BSP_FEATURE_SCI_SPI_SCKSEL_MASK (1UL) // Mask indicating CCR4.SCKSEL is available. +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS_MASK (0x00UL) // List of channels that do not support ABCSE functionality. +#define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS_MASK (0x03FFUL) // Mask of channels which support CTS external pins. +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0UL) // Indicates the PSEL value used to enable `DEn` output signal is opposite compared to other MCUs. +#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS_MASK (0x03FFUL) // Mask of channels which support the UART FIFO. +#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16UL) // Depth of the UART FIFO if available. +#define BSP_FEATURE_SCI_VERSION (2UL) // Version of the SCI peripheral. + +#define BSP_FEATURE_SDADC_HAS_CLOCK (0UL) // Indicates there is a separate clock for the SDADC. + +#define BSP_FEATURE_SDHI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) // Clock source for the SDHI peripheral clock. +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1UL) // Peripheral can detect if a card is present or not based on signal pull-ups. +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0UL) // Smallest shift value for the divider pre-scaller available on the SDHI clock. +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (1UL) // Supports 8-bit data bus width to the MMC device. +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x03UL) // Mask of valid SDHI channels. + +#define BSP_FEATURE_SDRAM_START_ADDRESS (0x68000000UL) // Start address of the external address space for SDRAM memory. + +#define BSP_FEATURE_SLCDC_IS_AVAILABLE (0UL) +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_VLCD_MDSET2 (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0UL) // Feature not available on this device. + +#define BSP_FEATURE_SPI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_SPI_CLOCK (FSP_PRIV_CLOCK_PCLKA) // Clock source for SPI peripherals. +#define BSP_FEATURE_SPI_HAS_CLOCK (1UL) // Indicates there is a separate clock for the SPI. +#define BSP_FEATURE_SPI_HAS_SPCR3 (1UL) // SPCR3 register is available. +#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1UL) // SPCMDn.SSLKP field is available. +#define BSP_FEATURE_SPI_NUM_CHANNELS (2UL) // Number of available SPI channels. +#define BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK (0x03UL) // Mask of channel indices that support SSL Level Keep. + +#define BSP_FEATURE_SRAM_HAS_EXTRA_SRAMSABAR (1UL) // Flag indicating that SRAMSABAR2 and SRAMSABAR3 are present. +#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0x01UL) // Mask of bits needed to enable SRAM wait for all regions. + +#define BSP_FEATURE_SSI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32UL) // Depth of the SSI data FIFO. +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (3UL) // Mask of valid SSI channel indices. + +#define BSP_FEATURE_SYSC_CLOCK_FREQ_FIVE_ROM_WAITS (240000000UL) // Maximum frequency allowed before requiring five wait cycles. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_FOUR_ROM_WAITS (192000000UL) // The maximum frequency allowed without having four ROM wait cycles. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_NO_RAM_WAITS (100000000UL) // The maximum frequency that can be used before wait cycles are necessary. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_ONE_ROM_WAITS (48000000UL) // Maximum frequency allowed before requiring one wait cycle. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_THREE_ROM_WAITS (144000000UL) // Maximum frequency allowed before requiring three wait cycles. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_TWO_ROM_WAITS (96000000UL) // Maximum frequency allowed before requiring two wait cycles. + +#define BSP_FEATURE_TAU_IS_AVAILABLE (0UL) +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_TFU_IS_AVAILABLE (0UL) +#define BSP_FEATURE_TFU_SUPPORTED (0UL) // Feature not available on this device. + +#define BSP_FEATURE_TML_IS_AVAILABLE (0UL) +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0UL) // Feature not available on this device. +#define BSP_FEATURE_TML_NUM_CHANNELS (0UL) // Feature not available on this device. +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0UL) // A module stop control is available for TRNG. + +#define BSP_FEATURE_TSN_IS_AVAILABLE (1UL) +#define BSP_FEATURE_TSN_CALIBRATION_AVAILABLE (1UL) // Determine if the temperature sensor supports calibration, either factory or runtime. +#define BSP_FEATURE_TSN_CALIBRATION32_AVAILABLE (1UL) // Determine if TSCDR is available for TSN. +#define BSP_FEATURE_TSN_CALIBRATION32_MASK (0xFFFFUL) // Mask of valid bits for TSN calibration. +#define BSP_FEATURE_TSN_CONTROL_AVAILABLE (1UL) // Determine if the TSCR register is present. +#define BSP_FEATURE_TSN_HAS_LOW_TEMP_REG (0UL) // Determine if the TSCDRL (Low Temperature) is present. +#define BSP_FEATURE_TSN_HAS_ROOM_TEMP_REG (0UL) // Determine if the TSCDRR (Room Temperature) is present. +#define BSP_FEATURE_TSN_SLOPE (4000UL) // Typical slope for the temperature sensor, in uV/degC. + +#define BSP_FEATURE_TZ_IS_AVAILABLE (1UL) +#define BSP_FEATURE_TZ_HAS_DLM (1UL) // Device Lifecycle Management Monitor (DLMMON) register is available. +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1UL) // The device supports Arm TrustZone. +#define BSP_FEATURE_TZ_HAS_TZFSAR (0UL) // Specifies the TrustZone filter can be secured. +#define BSP_FEATURE_TZ_NS_OFFSET (0x10000000UL) // Offset for the Non-secure address space of a peripheral. +#define BSP_FEATURE_TZ_VERSION (2UL) // Version of the TrustZone implementation. + +#define BSP_FEATURE_UARTA_IS_AVAILABLE (0UL) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0UL) // Feature not available on this device. +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0UL) // Feature not available on this device. +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ULPT_IS_AVAILABLE (1UL) +#define BSP_FEATURE_ULPT_NUM_CHANNELS_AVAILABLE (2UL) // Number of channels available for ULPT. +#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (3UL) // Mask of available channels for ULPT. + +#define BSP_FEATURE_USB_IS_AVAILABLE (1UL) +#define BSP_FEATURE_USB_HAS_CLOCK_REQ (1UL) // Indicates that a request bit must be set before changing USB clock settings. +#define BSP_FEATURE_USB_HAS_CLOCK_SEL (1UL) // Indicates the USB clock has a selectable source. +#define BSP_FEATURE_USB_HAS_CLOCK_SEL_ALT (0UL) // Indicates the USBCKCR_ALT register should be used instead of USBCKCR. +#define BSP_FEATURE_USB_HAS_NOT_HOST (0UL) // Indicates that USB Host mode is not available. +#define BSP_FEATURE_USB_HAS_PIPE04567 (0UL) // USB peripheral only has pipes 0, 4, 5, 6, and 7. +#define BSP_FEATURE_USB_HAS_TYPEC (0UL) // Supports USB-C control specifications. +#define BSP_FEATURE_USB_HAS_USB60_CLOCK (1UL) // Indicates the USB60 clock is available. +#define BSP_FEATURE_USB_HAS_USBCKDIVCR (1UL) // USBCKDIVCR register is available. +#define BSP_FEATURE_USB_HAS_USBFS (1UL) // Supports USB 2.0 Full-Speed mode. +#define BSP_FEATURE_USB_HAS_USBFS_BC (0UL) // Supports battery charging in full-speed mode. +#define BSP_FEATURE_USB_HAS_USBHS (1UL) // Supports USB 2.0 High-Speed mode. +#define BSP_FEATURE_USB_HAS_USBHS_BC (1UL) // Supports battery charging in high-speed mode. +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0UL) // Supports low-speed connections in device controller mode. +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0UL) // Indicates the PHYSECTRL.CNEN field is available. +#define BSP_FEATURE_USB_REG_PHYSLEW (0UL) // Indicates the PHYSLEW register is available. +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0x00UL) // Reset value of the PHYSLEW register. +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0UL) // Indicates the UCKSEL.UCKSELC bit field is available. +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0UL) // Indicates the USBMC.VDCEN bit field is available. +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0UL) // Indicates the USBMC.VDDUSBE bit field is available. +#define BSP_FEATURE_USB_SCKDIVCR2_HAS_CLOCK_DIV (0UL) // Indicates there is a USB clock divider setting as part of the SCKDIVCR2 register. + +#define BSP_FEATURE_VIN_IS_AVAILABLE (1UL) + +// *UNCRUSTIFY-ON* + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/ra8p1/bsp_linker.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/ra8p1/bsp_linker.c new file mode 100644 index 00000000000..4cee90e3e39 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/ra8p1/bsp_linker.c @@ -0,0 +1,99 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "bsp_api.h" + +/* UNCRUSTIFY-OFF */ + +/* boot loaded applications cannot set ofs registers (only do so in the boot loader) */ +#ifndef BSP_BOOTLOADED_APPLICATION +/** configuration register output to sections */ +#if defined BSP_CFG_OPTION_SETTING_OFS0 && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs0") g_bsp_cfg_option_setting_ofs0[] = {BSP_CFG_OPTION_SETTING_OFS0}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OFS2 && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs2") g_bsp_cfg_option_setting_ofs2[] = {BSP_CFG_OPTION_SETTING_OFS2}; +#endif +#if defined BSP_CFG_OPTION_SETTING_SAS && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_sas") g_bsp_cfg_option_setting_sas[] = {BSP_CFG_OPTION_SETTING_SAS}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OFS1 && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1") g_bsp_cfg_option_setting_ofs1[] = {BSP_CFG_OPTION_SETTING_OFS1}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OFS1_SEC && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1_sec") g_bsp_cfg_option_setting_ofs1_sec[] = {BSP_CFG_OPTION_SETTING_OFS1_SEC}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OFS1_SEL && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1_sel") g_bsp_cfg_option_setting_ofs1_sel[] = {BSP_CFG_OPTION_SETTING_OFS1_SEL}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OFS3 && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs3") g_bsp_cfg_option_setting_ofs3[] = {BSP_CFG_OPTION_SETTING_OFS3}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OFS3_SEC && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs3_sec") g_bsp_cfg_option_setting_ofs3_sec[] = {BSP_CFG_OPTION_SETTING_OFS3_SEC}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OFS3_SEL && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs3_sel") g_bsp_cfg_option_setting_ofs3_sel[] = {BSP_CFG_OPTION_SETTING_OFS3_SEL}; +#endif +#if defined BSP_CFG_OPTION_SETTING_BPS && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps") g_bsp_cfg_option_setting_bps[] = {BSP_CFG_OPTION_SETTING_BPS}; +#endif +#if defined BSP_CFG_OPTION_SETTING_BPS_SEC && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sec") g_bsp_cfg_option_setting_bps_sec[] = {BSP_CFG_OPTION_SETTING_BPS_SEC}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OTP_FSBLCTRL0 && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_otp_fsblctrl0") g_bsp_cfg_option_setting_otp_fsblctrl0[] = {BSP_CFG_OPTION_SETTING_OTP_FSBLCTRL0}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OTP_FSBLCTRL1 && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_otp_fsblctrl1") g_bsp_cfg_option_setting_otp_fsblctrl1[] = {BSP_CFG_OPTION_SETTING_OTP_FSBLCTRL1}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OTP_FSBLCTRL2 && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_otp_fsblctrl2") g_bsp_cfg_option_setting_otp_fsblctrl2[] = {BSP_CFG_OPTION_SETTING_OTP_FSBLCTRL2}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OTP_SAMR && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_otp_samr") g_bsp_cfg_option_setting_otp_samr[] = {BSP_CFG_OPTION_SETTING_OTP_SAMR}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OTP_SACC00 && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_otp_sacc00") g_bsp_cfg_option_setting_otp_sacc00[] = {BSP_CFG_OPTION_SETTING_OTP_SACC00}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OTP_SACC10 && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_otp_sacc10") g_bsp_cfg_option_setting_otp_sacc10[] = {BSP_CFG_OPTION_SETTING_OTP_SACC10}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OTP_SACC01 && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_otp_sacc01") g_bsp_cfg_option_setting_otp_sacc01[] = {BSP_CFG_OPTION_SETTING_OTP_SACC01}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OTP_SACC11 && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_otp_sacc11") g_bsp_cfg_option_setting_otp_sacc11[] = {BSP_CFG_OPTION_SETTING_OTP_SACC11}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OTP_SACC02 && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_otp_sacc02") g_bsp_cfg_option_setting_otp_sacc02[] = {BSP_CFG_OPTION_SETTING_OTP_SACC02}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OTP_SACC12 && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_otp_sacc12") g_bsp_cfg_option_setting_otp_sacc12[] = {BSP_CFG_OPTION_SETTING_OTP_SACC12}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OTP_SACC03 && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_otp_sacc03") g_bsp_cfg_option_setting_otp_sacc03[] = {BSP_CFG_OPTION_SETTING_OTP_SACC03}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OTP_SACC13 && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_otp_sacc13") g_bsp_cfg_option_setting_otp_sacc13[] = {BSP_CFG_OPTION_SETTING_OTP_SACC13}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OTP_PBPS_SEC && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_otp_pbps_sec") g_bsp_cfg_option_setting_otp_pbps_sec[] = {BSP_CFG_OPTION_SETTING_OTP_PBPS_SEC}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OTP_PBPS && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_otp_pbps") g_bsp_cfg_option_setting_otp_pbps[] = {BSP_CFG_OPTION_SETTING_OTP_PBPS}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OTP_ZHUK && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_otp_zhuk") g_bsp_cfg_option_setting_otp_zhuk[] = {BSP_CFG_OPTION_SETTING_OTP_ZHUK}; +#endif +#endif // BSP_BOOTLOADED_APPLICATION + +/******************************/ +/* the init tables are located in bsp_linker_info.h */ +#define BSP_LINKER_C +#include "bsp_linker_info.h" + +/* UNCRUSTIFY-ON */ diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/ra8p1/bsp_mcu_info.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/ra8p1/bsp_mcu_info.h new file mode 100644 index 00000000000..86a5235fae7 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/ra8p1/bsp_mcu_info.h @@ -0,0 +1,45 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup BSP_MCU + * @defgroup BSP_MCU_RA8P1 RA8P1 + * @{ + **********************************************************************************************************************/ + +// RA8P1_TODO: includedoc config_bsp_ra8p1_fsp.html + +/** @} (end defgroup BSP_MCU_RA8P1) */ + +#ifndef BSP_MCU_INFO_H +#define BSP_MCU_INFO_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP MCU Specific Includes. */ +#include "bsp_elc.h" +#include "bsp_feature.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef elc_event_t bsp_interrupt_event_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/ra8p1/bsp_override.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/ra8p1/bsp_override.h new file mode 100644 index 00000000000..a9a64d1895d --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/ra8p1/bsp_override.h @@ -0,0 +1,298 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RA8P1 + * @{ + **********************************************************************************************************************/ + +/** @} (end addtogroup BSP_MCU_RA8P1) */ + +#ifndef BSP_OVERRIDE_H +#define BSP_OVERRIDE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +#if __has_include("r_lpm_device_types.h") + #include "r_lpm_device_types.h" +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Define overrides required for this MCU. */ + +#define BSP_OVERRIDE_CGC_DIVIDER_CFG_T +#define BSP_OVERRIDE_CGC_SYS_CLOCK_DIV_T +#define BSP_OVERRIDE_GROUP_IRQ_T +#define BSP_OVERRIDE_IOPORT_PERIPHERAL_T +#define BSP_OVERRIDE_LVD_PERIPHERAL_T + +/* Override definitions. */ + +/* Private definition to set enumeration values. */ +#define IOPORT_PRV_PFS_PSEL_OFFSET (24) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** System clock divider values - The individually selectable divider of each of the system clocks, ICLK, BCLK, FCLK, + * PCLKS A-D. */ +typedef enum e_cgc_sys_clock_div +{ + CGC_SYS_CLOCK_DIV_1 = 0, ///< System clock divided by 1 + CGC_SYS_CLOCK_DIV_2 = 1, ///< System clock divided by 2 + CGC_SYS_CLOCK_DIV_4 = 2, ///< System clock divided by 4 + CGC_SYS_CLOCK_DIV_8 = 3, ///< System clock divided by 8 + CGC_SYS_CLOCK_DIV_16 = 4, ///< System clock divided by 16 + CGC_SYS_CLOCK_DIV_32 = 5, ///< System clock divided by 32 + CGC_SYS_CLOCK_DIV_64 = 6, ///< System clock divided by 64 + CGC_SYS_CLOCK_DIV_3 = 8, ///< System clock divided by 3 + CGC_SYS_CLOCK_DIV_6 = 9, ///< System clock divided by 6 + CGC_SYS_CLOCK_DIV_12 = 10, ///< System clock divided by 12 + CGC_SYS_CLOCK_DIV_24 = 11, ///< System clock divided by 24 +} cgc_sys_clock_div_t; + +/** Clock configuration structure - Used as an input parameter to the @ref cgc_api_t::systemClockSet and @ref cgc_api_t::systemClockGet + * functions. */ +typedef struct st_cgc_divider_cfg +{ + union + { + uint32_t sckdivcr_w; ///< System clock Division control register + + struct + { + cgc_sys_clock_div_t pclkd_div : 4; ///< Divider value for PCLKD + cgc_sys_clock_div_t pclkc_div : 4; ///< Divider value for PCLKC + cgc_sys_clock_div_t pclkb_div : 4; ///< Divider value for PCLKB + cgc_sys_clock_div_t pclka_div : 4; ///< Divider value for PCLKA + cgc_sys_clock_div_t bclk_div : 4; ///< Divider value for BCLK + cgc_sys_clock_div_t pclke_div : 4; ///< Divider value for PCLKE + cgc_sys_clock_div_t iclk_div : 4; ///< Divider value for ICLK + cgc_sys_clock_div_t fclk_div : 4; ///< Divider value for FCLK + } sckdivcr_b; + }; + + union + { + uint16_t sckdivcr2; ///< System clock Division control register 2 + + struct + { + cgc_sys_clock_div_t cpuclk_div : 4; ///< Divider value for CPUCLK0 + cgc_sys_clock_div_t cpuclk1_div : 4; ///< Divider value for CPUCLK1 + cgc_sys_clock_div_t npuclk_div : 4; ///< Divider value for NPUCLK + cgc_sys_clock_div_t mriclk_div : 4; ///< Divider value for MRICLK + } sckdivcr2_b; + }; +} cgc_divider_cfg_t; + +/* Which interrupts can have callbacks registered. */ +typedef enum e_bsp_grp_irq +{ + BSP_GRP_IRQ_IWDT_ERROR = 0, ///< IWDT underflow/refresh error has occurred + BSP_GRP_IRQ_WDT_ERROR = 1, ///< WDT underflow/refresh error has occurred + BSP_GRP_IRQ_LVD1 = 2, ///< Voltage monitoring 1 interrupt + BSP_GRP_IRQ_LVD2 = 3, ///< Voltage monitoring 2 interrupt + BSP_GRP_IRQ_SOSC_STOP_DETECT = 5, ///< Sub Oscillation stop is detected + BSP_GRP_IRQ_OSC_STOP_DETECT = 6, ///< Oscillation stop is detected + BSP_GRP_IRQ_NMI_PIN = 7, ///< NMI Pin interrupt + BSP_GRP_IRQ_MPU_BUS_TZF = 12, ///< MPU Bus or TrustZone Filter Error + BSP_GRP_IRQ_COMMON_MEMORY = 13, ///< SRAM ECC or SRAM Parity Error + BSP_GRP_IRQ_LOCAL_MEMORY = 14, ///< Local Memory Error + BSP_GRP_IRQ_LOCKUP = 15, ///< LockUp Error + BSP_GRP_IRQ_FPU = 16, ///< FPU Exception + BSP_GRP_IRQ_MRC = 17, ///< MRAM Code read error + BSP_GRP_IRQ_MRE = 18, ///< MRAM Extra read error + BSP_GRP_IRQ_IPC = 20, ///< IPC Interrupt +} bsp_grp_irq_t; + +/** Superset of all peripheral functions. */ +typedef enum e_ioport_peripheral +{ + /** Pin will functions as an IO pin */ + IOPORT_PERIPHERAL_IO = 0x00, + + /** Pin will function as a DEBUG pin */ + IOPORT_PERIPHERAL_DEBUG = (0x00UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an AGT peripheral pin */ + IOPORT_PERIPHERAL_AGT = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an AGT peripheral pin */ + IOPORT_PERIPHERAL_AGTW = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an AGT peripheral pin */ + IOPORT_PERIPHERAL_AGT1 = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a GPT peripheral pin */ + IOPORT_PERIPHERAL_GPT0 = (0x02UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a GPT peripheral pin */ + IOPORT_PERIPHERAL_GPT1 = (0x03UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SCI peripheral pin */ + IOPORT_PERIPHERAL_SCI0_2_4_6_8 = (0x04UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SCI peripheral pin */ + IOPORT_PERIPHERAL_SCI1_3_5_7_9 = (0x05UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a SPI peripheral pin */ + IOPORT_PERIPHERAL_SPI = (0x06UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a IIC peripheral pin */ + IOPORT_PERIPHERAL_IIC = (0x07UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a KEY peripheral pin */ + IOPORT_PERIPHERAL_KEY = (0x08UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a clock/comparator/RTC peripheral pin */ + IOPORT_PERIPHERAL_CLKOUT_COMP_RTC = (0x09UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CAC/ADC peripheral pin */ + IOPORT_PERIPHERAL_CAC_AD = (0x0AUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a BUS peripheral pin */ + IOPORT_PERIPHERAL_BUS = (0x0BUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CTSU peripheral pin */ + IOPORT_PERIPHERAL_CTSU = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CMPHS peripheral pin */ + IOPORT_PERIPHERAL_ACMPHS = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a segment LCD peripheral pin */ + IOPORT_PERIPHERAL_LCDC = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), + +#if BSP_FEATURE_SCI_UART_DE_IS_INVERTED + + /** Pin will function as an SCI peripheral DEn pin */ + IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SCI DEn peripheral pin */ + IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), +#else + + /** Pin will function as an SCI peripheral DEn pin */ + IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SCI DEn peripheral pin */ + IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), +#endif + + /** Pin will function as a DALI peripheral pin */ + IOPORT_PERIPHERAL_DALI = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CEU peripheral pin */ + IOPORT_PERIPHERAL_CEU = (0x0FUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CAN peripheral pin */ + IOPORT_PERIPHERAL_CAN = (0x10UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a QSPI peripheral pin */ + IOPORT_PERIPHERAL_QSPI = (0x11UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SSI peripheral pin */ + IOPORT_PERIPHERAL_SSI = (0x12UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a USB full speed peripheral pin */ + IOPORT_PERIPHERAL_USB_FS = (0x13UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a USB high speed peripheral pin */ + IOPORT_PERIPHERAL_USB_HS = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a GPT peripheral pin */ + IOPORT_PERIPHERAL_GPT2 = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SD/MMC peripheral pin */ + IOPORT_PERIPHERAL_SDHI_MMC = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a GPT peripheral pin */ + IOPORT_PERIPHERAL_GPT3 = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an Ethernet MMI peripheral pin */ + IOPORT_PERIPHERAL_ETHER_MII = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a GPT peripheral pin */ + IOPORT_PERIPHERAL_GPT4 = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an Ethernet RMMI peripheral pin */ + IOPORT_PERIPHERAL_ETHER_RMII = (0x17UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a PDC peripheral pin */ + IOPORT_PERIPHERAL_PDC = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a graphics LCD peripheral pin */ + IOPORT_PERIPHERAL_LCD_GRAPHICS = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CAC peripheral pin */ + IOPORT_PERIPHERAL_CAC = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a debug trace peripheral pin */ + IOPORT_PERIPHERAL_TRACE = (0x1AUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a OSPI peripheral pin */ + IOPORT_PERIPHERAL_OSPI = (0x1CUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CEC peripheral pin */ + IOPORT_PERIPHERAL_CEC = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a PGAOUT peripheral pin */ + IOPORT_PERIPHERAL_PGAOUT0 = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a PGAOUT peripheral pin */ + IOPORT_PERIPHERAL_PGAOUT1 = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a ULPT peripheral pin */ + IOPORT_PERIPHERAL_ULPT = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a MIPI DSI peripheral pin */ + IOPORT_PERIPHERAL_MIPI = (0x1FUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a RGMII peripheral pin */ + IOPORT_PERIPHERAL_ETHER_RGMII = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a ETHERNET slave controller peripheral pin */ + IOPORT_PERIPHERAL_ESC = (0x1AUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a PDM peripheral pin */ + IOPORT_PERIPHERAL_PDM = (0x1BUL << IOPORT_PRV_PFS_PSEL_OFFSET), +} ioport_peripheral_t; + +/** The thresholds supported by each MCU are in the MCU User's Manual as well as + * in the r_lvd module description on the stack tab of the RA project. */ +typedef enum +{ + LVD_THRESHOLD_MONITOR_LEVEL_3_86V = 0x03UL, ///< 3.86V + LVD_THRESHOLD_MONITOR_LEVEL_3_14V = 0x04UL, ///< 3.14V + LVD_THRESHOLD_MONITOR_LEVEL_3_10V = 0x05UL, ///< 3.10V + LVD_THRESHOLD_MONITOR_LEVEL_3_08V = 0x06UL, ///< 3.08V + LVD_THRESHOLD_MONITOR_LEVEL_2_85V = 0x07UL, ///< 2.85V + LVD_THRESHOLD_MONITOR_LEVEL_2_83V = 0x08UL, ///< 2.83V + LVD_THRESHOLD_MONITOR_LEVEL_2_80V = 0x09UL, ///< 2.80V + LVD_THRESHOLD_MONITOR_LEVEL_2_62V = 0x0AUL, ///< 2.62V + LVD_THRESHOLD_MONITOR_LEVEL_2_33V = 0x0BUL, ///< 2.33V + LVD_THRESHOLD_MONITOR_LEVEL_1_90V = 0x0CUL, ///< 1.90V + LVD_THRESHOLD_MONITOR_LEVEL_1_86V = 0x0DUL, ///< 1.86V + LVD_THRESHOLD_MONITOR_LEVEL_1_74V = 0x0EUL, ///< 1.74V + LVD_THRESHOLD_MONITOR_LEVEL_1_71V = 0x0FUL, ///< 1.71V + LVD_THRESHOLD_NOT_AVAILABLE = 0xFFUL, ///< Not Used +} lvd_threshold_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/ra8p1/bsp_peripheral.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/ra8p1/bsp_peripheral.h new file mode 100644 index 00000000000..71f2edda2e4 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/ra8p1/bsp_peripheral.h @@ -0,0 +1,218 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * + * AUTOGENERATED FILE. DO NOT EDIT. + * + **********************************************************************************************************************/ + +#ifndef BSP_PERIPHERAL_H +#define BSP_PERIPHERAL_H + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +// *UNCRUSTIFY-OFF* + +#define BSP_PERIPHERAL_ACMP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (1) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0xFU) +#define BSP_PERIPHERAL_ACMPHS_B_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ADC_PRESENT (0) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ADC_B_PRESENT (1) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_PRESENT (0) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CACHE_PRESENT (0) +#define BSP_PERIPHERAL_CAN_PRESENT (0) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_CANFD_PRESENT (1) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_CEC_PRESENT (0) +#define BSP_PERIPHERAL_CEU_PRESENT (1) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_PRESENT (1) +#define BSP_PERIPHERAL_CPU_CTRL_PRESENT (1) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CTSU_PRESENT (0) +#define BSP_PERIPHERAL_DAC_PRESENT (0) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_DAC_B_PRESENT (1) +#define BSP_PERIPHERAL_DAC_B_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_DAC12_PRESENT (0) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DMA_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xFFU) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DRW_PRESENT (1) +#define BSP_PERIPHERAL_DSMIF_PRESENT (0) +#define BSP_PERIPHERAL_DSMIF_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ECCMB_PRESENT (1) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ESWM_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_FACI_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (1) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x3FFFU) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (1) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (1) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0xFU) +#define BSP_PERIPHERAL_I3C_PRESENT (1) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0xFFFFFFFFU) +#define BSP_PERIPHERAL_IIC_PRESENT (1) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x7U) +#define BSP_PERIPHERAL_IIC_B_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (1) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_IPC_PRESENT (1) +#define BSP_PERIPHERAL_IRDA_PRESENT (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_CSI_PRESENT (1) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (1) +#define BSP_PERIPHERAL_MIPI_PHY_PRESENT (1) +#define BSP_PERIPHERAL_MMF_PRESENT (0) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_MRMS_PRESENT (1) +#define BSP_PERIPHERAL_MRRGE_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_NPU_PRESENT (1) +#define BSP_PERIPHERAL_OCD_PRESENT (1) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (1) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDM_PRESENT (1) +#define BSP_PERIPHERAL_PDM_CHANNEL_MASK (0x7U) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_PRESENT (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0x3FFFU) +#define BSP_PERIPHERAL_PSCU_PRESENT (1) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_PRESENT (0) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RSIP_PRESENT (1) +#define BSP_PERIPHERAL_RTC_PRESENT (1) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SCI_PRESENT (0) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SCI_B_PRESENT (1) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0x3FFU) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SDHI_PRESENT (1) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SPI_B_PRESENT (1) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_SPMON_PRESENT (0) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRC_PRESENT (0) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_PRESENT (1) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_TRNG_PRESENT (0) +#define BSP_PERIPHERAL_TSD_PRESENT (1) +#define BSP_PERIPHERAL_TSN_PRESENT (1) +#define BSP_PERIPHERAL_TZF_PRESENT (1) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ULPT_PRESENT (1) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_USB_PRESENT (1) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_USB_FS_PRESENT (1) +#define BSP_PERIPHERAL_USB_HS_PRESENT (1) +#define BSP_PERIPHERAL_USBCC_PRESENT (0) +#define BSP_PERIPHERAL_VIN_PRESENT (1) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x3U) + +// *UNCRUSTIFY-ON* + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/ra8p1/r_adc_device_types.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/ra8p1/r_adc_device_types.h new file mode 100644 index 00000000000..959e34888ff --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/ra8p1/r_adc_device_types.h @@ -0,0 +1,182 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RA8P1 + * @{ + **********************************************************************************************************************/ + +/** @} (end addtogroup BSP_MCU_RA8P1) */ + +#ifndef R_ADC_DEVICE_TYPES +#define R_ADC_DEVICE_TYPES + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define ADC_B_CHANNEL_MASK_EXT_OFFSET (32U) + +/* Define overrides required for this MCU. */ +#define BSP_OVERRIDE_ADC_CHANNEL_T + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** ADC Clock source selection */ +typedef enum e_adc_b_clock_source +{ + ADC_B_CLOCK_SOURCE_ADC = 0, ///< ADC Clock Source ADCCLK + ADC_B_CLOCK_SOURCE_GPT = 1, ///< ADC Clock Source GPT + ADC_B_CLOCK_SOURCE_PCLKA = 2 ///< ADC Clock Source PCLKA +} adc_b_clock_source_t; + +/** ADC channels */ +typedef enum e_adc_b_virtual_channel +{ + ADC_B_VIRTUAL_CHANNEL_0 = 0, ///< ADC B virtual channel 0 + ADC_B_VIRTUAL_CHANNEL_1 = 1, ///< ADC B virtual channel 1 + ADC_B_VIRTUAL_CHANNEL_2 = 2, ///< ADC B virtual channel 2 + ADC_B_VIRTUAL_CHANNEL_3 = 3, ///< ADC B virtual channel 3 + ADC_B_VIRTUAL_CHANNEL_4 = 4, ///< ADC B virtual channel 4 + ADC_B_VIRTUAL_CHANNEL_5 = 5, ///< ADC B virtual channel 5 + ADC_B_VIRTUAL_CHANNEL_6 = 6, ///< ADC B virtual channel 6 + ADC_B_VIRTUAL_CHANNEL_7 = 7, ///< ADC B virtual channel 7 + ADC_B_VIRTUAL_CHANNEL_8 = 8, ///< ADC B virtual channel 8 + ADC_B_VIRTUAL_CHANNEL_9 = 9, ///< ADC B virtual channel 9 + ADC_B_VIRTUAL_CHANNEL_10 = 10, ///< ADC B virtual channel 10 + ADC_B_VIRTUAL_CHANNEL_11 = 11, ///< ADC B virtual channel 11 + ADC_B_VIRTUAL_CHANNEL_12 = 12, ///< ADC B virtual channel 12 + ADC_B_VIRTUAL_CHANNEL_13 = 13, ///< ADC B virtual channel 13 + ADC_B_VIRTUAL_CHANNEL_14 = 14, ///< ADC B virtual channel 14 + ADC_B_VIRTUAL_CHANNEL_15 = 15, ///< ADC B virtual channel 15 + ADC_B_VIRTUAL_CHANNEL_16 = 16, ///< ADC B virtual channel 16 + ADC_B_VIRTUAL_CHANNEL_17 = 17, ///< ADC B virtual channel 17 + ADC_B_VIRTUAL_CHANNEL_18 = 18, ///< ADC B virtual channel 18 + ADC_B_VIRTUAL_CHANNEL_19 = 19, ///< ADC B virtual channel 19 + ADC_B_VIRTUAL_CHANNEL_20 = 20, ///< ADC B virtual channel 20 + ADC_B_VIRTUAL_CHANNEL_21 = 21, ///< ADC B virtual channel 21 + ADC_B_VIRTUAL_CHANNEL_22 = 22, ///< ADC B virtual channel 22 + ADC_B_VIRTUAL_CHANNEL_23 = 23, ///< ADC B virtual channel 23 + ADC_B_VIRTUAL_CHANNEL_24 = 24, ///< ADC B virtual channel 24 + ADC_B_VIRTUAL_CHANNEL_25 = 25, ///< ADC B virtual channel 25 + ADC_B_VIRTUAL_CHANNEL_26 = 26, ///< ADC B virtual channel 26 + ADC_B_VIRTUAL_CHANNEL_27 = 27, ///< ADC B virtual channel 27 + ADC_B_VIRTUAL_CHANNEL_28 = 28, ///< ADC B virtual channel 28 + ADC_B_VIRTUAL_CHANNEL_29 = 29, ///< ADC B virtual channel 29 + ADC_B_VIRTUAL_CHANNEL_30 = 30, ///< ADC B virtual channel 30 + ADC_B_VIRTUAL_CHANNEL_31 = 31, ///< ADC B virtual channel 31 + ADC_B_VIRTUAL_CHANNEL_32 = 32, ///< ADC B virtual channel 32 + ADC_B_VIRTUAL_CHANNEL_COUNT // Number of available ADC B virtual channels +} adc_b_virtual_channel_t; + +/** ADC channels */ +typedef enum e_adc_channel +{ + /* These channels map to physical pins */ + ADC_CHANNEL_0 = 0, ///< ADC channel 0 + ADC_CHANNEL_1 = 1, ///< ADC channel 1 + ADC_CHANNEL_2 = 2, ///< ADC channel 2 + ADC_CHANNEL_3 = 3, ///< ADC channel 3 + ADC_CHANNEL_4 = 4, ///< ADC channel 4 + ADC_CHANNEL_5 = 5, ///< ADC channel 5 + ADC_CHANNEL_6 = 6, ///< ADC channel 6 + ADC_CHANNEL_7 = 7, ///< ADC channel 7 + ADC_CHANNEL_8 = 8, ///< ADC channel 8 + ADC_CHANNEL_9 = 9, ///< ADC channel 9 + ADC_CHANNEL_10 = 10, ///< ADC channel 10 + ADC_CHANNEL_11 = 11, ///< ADC channel 11 + ADC_CHANNEL_12 = 12, ///< ADC channel 12 + ADC_CHANNEL_13 = 13, ///< ADC channel 13 + ADC_CHANNEL_14 = 14, ///< ADC channel 14 + ADC_CHANNEL_15 = 15, ///< ADC channel 15 + ADC_CHANNEL_16 = 16, ///< ADC channel 16 + ADC_CHANNEL_17 = 17, ///< ADC channel 17 + ADC_CHANNEL_18 = 18, ///< ADC channel 18 + ADC_CHANNEL_19 = 19, ///< ADC channel 19 + ADC_CHANNEL_20 = 20, ///< ADC channel 20 + ADC_CHANNEL_21 = 21, ///< ADC channel 21 + ADC_CHANNEL_22 = 22, ///< ADC channel 22 + + /* Extended Channels, See Implementation for details */ + /* Implementation specific extended channels */ + ADC_CHANNEL_SELF_DIAGNOSIS_ADC0 = 0x60, ///< Self-Diagnosis channel for ADC Unit 0 + ADC_CHANNEL_SELF_DIAGNOSIS_ADC1 = 0x61, ///< Self-Diagnosis channel for ADC Unit 1 + ADC_CHANNEL_TEMPERATURE = 0x64, ///< Temperature sensor output + ADC_CHANNEL_VOLT = 0x65, ///< Internal reference voltage + ADC_CHANNEL_VBATT = 0x66, ///< VBATT 1/3 voltage monitor + ADC_CHANNEL_DA0 = 0x68, ///< D/A converter channel 0 + ADC_CHANNEL_DA1 = 0x69, ///< D/A converter channel 1 + + ADC_CHANNEL_SELF_DIAGNOSIS_SH0 = 0x70, ///< Self-Diagnosis Sample-and-hold Circuit Unit 0 + ADC_CHANNEL_SELF_DIAGNOSIS_SH1 = 0x71, ///< Self-Diagnosis Sample-and-hold Circuit Unit 1 + ADC_CHANNEL_SELF_DIAGNOSIS_SH2 = 0x72, ///< Self-Diagnosis Sample-and-hold Circuit Unit 2 + ADC_CHANNEL_SELF_DIAGNOSIS_SH4 = 0x74, ///< Self-Diagnosis Sample-and-hold Circuit Unit 4 + ADC_CHANNEL_SELF_DIAGNOSIS_SH5 = 0x75, ///< Self-Diagnosis Sample-and-hold Circuit Unit 5 + ADC_CHANNEL_SELF_DIAGNOSIS_SH6 = 0x76, ///< Self-Diagnosis Sample-and-hold Circuit Unit 6 + + ADC_CHANNEL_LAST_EXTERNAL = ADC_CHANNEL_22, /// Highest physical channel + ADC_CHANNEL_FIRST_INTERNAL = ADC_CHANNEL_SELF_DIAGNOSIS_ADC0, /// First internal channel + ADC_CHANNEL_LAST_INTERNAL = ADC_CHANNEL_SELF_DIAGNOSIS_SH6, /// Last internal channel +} adc_channel_t; + +/** ADC channel mask */ +typedef enum e_adc_b_channel_mask +{ + ADC_B_CHANNEL_MASK_NONE = 0ULL, + ADC_B_CHANNEL_MASK_0 = (1ULL << 0), ///< Channel 0 + ADC_B_CHANNEL_MASK_1 = (1ULL << 1), ///< Channel 1 + ADC_B_CHANNEL_MASK_2 = (1ULL << 2), ///< Channel 2 + ADC_B_CHANNEL_MASK_3 = (1ULL << 3), ///< Channel 3 + ADC_B_CHANNEL_MASK_4 = (1ULL << 4), ///< Channel 4 + ADC_B_CHANNEL_MASK_5 = (1ULL << 5), ///< Channel 5 + ADC_B_CHANNEL_MASK_6 = (1ULL << 6), ///< Channel 6 + ADC_B_CHANNEL_MASK_7 = (1ULL << 7), ///< Channel 7 + ADC_B_CHANNEL_MASK_8 = (1ULL << 8), ///< Channel 8 + ADC_B_CHANNEL_MASK_9 = (1ULL << 9), ///< Channel 9 + ADC_B_CHANNEL_MASK_10 = (1ULL << 10), ///< Channel 10 + ADC_B_CHANNEL_MASK_11 = (1ULL << 11), ///< Channel 11 + ADC_B_CHANNEL_MASK_12 = (1ULL << 12), ///< Channel 12 + ADC_B_CHANNEL_MASK_13 = (1ULL << 13), ///< Channel 13 + ADC_B_CHANNEL_MASK_14 = (1ULL << 14), ///< Channel 14 + ADC_B_CHANNEL_MASK_15 = (1ULL << 15), ///< Channel 15 + ADC_B_CHANNEL_MASK_16 = (1ULL << 16), ///< Channel 16 + ADC_B_CHANNEL_MASK_17 = (1ULL << 17), ///< Channel 17 + ADC_B_CHANNEL_MASK_18 = (1ULL << 18), ///< Channel 18 + ADC_B_CHANNEL_MASK_19 = (1ULL << 19), ///< Channel 19 + ADC_B_CHANNEL_MASK_20 = (1ULL << 20), ///< Channel 20 + ADC_B_CHANNEL_MASK_21 = (1ULL << 21), ///< Channel 21 + ADC_B_CHANNEL_MASK_22 = (1ULL << 22), ///< Channel 22 + + ADC_B_CHANNEL_MASK_DIAGNOSIS_ADC0 = (1ULL << (ADC_B_CHANNEL_MASK_EXT_OFFSET + 0)), ///< Converter 0 Self-Diagnosis Channel + ADC_B_CHANNEL_MASK_DIAGNOSIS_ADC1 = (1ULL << (ADC_B_CHANNEL_MASK_EXT_OFFSET + 1)), ///< Converter 1 Self-Diagnosis Channel + ADC_B_CHANNEL_MASK_TEMPERATURE = (1ULL << (ADC_B_CHANNEL_MASK_EXT_OFFSET + 4)), ///< Temperature sensor channel + ADC_B_CHANNEL_MASK_VOLT = (1ULL << (ADC_B_CHANNEL_MASK_EXT_OFFSET + 5)), ///< Voltage Reference channel + ADC_B_CHANNEL_MASK_VBATT = (1ULL << (ADC_B_CHANNEL_MASK_EXT_OFFSET + 6)), ///< VBATT 1/3 voltage monitor + ADC_B_CHANNEL_MASK_DAC0 = (1ULL << (ADC_B_CHANNEL_MASK_EXT_OFFSET + 8)), ///< DAC 1 Channel + ADC_B_CHANNEL_MASK_DAC1 = (1ULL << (ADC_B_CHANNEL_MASK_EXT_OFFSET + 9)), ///< DAC 2 Channel + ADC_B_CHANNEL_MASK_DIAGNOSIS_SH0 = (1ULL << (ADC_B_CHANNEL_MASK_EXT_OFFSET + 16)), ///< Sample-and-hold 0 Self-Diagnosis + ADC_B_CHANNEL_MASK_DIAGNOSIS_SH1 = (1ULL << (ADC_B_CHANNEL_MASK_EXT_OFFSET + 17)), ///< Sample-and-hold 1 Self-Diagnosis + ADC_B_CHANNEL_MASK_DIAGNOSIS_SH2 = (1ULL << (ADC_B_CHANNEL_MASK_EXT_OFFSET + 18)), ///< Sample-and-hold 2 Self-Diagnosis + ADC_B_CHANNEL_MASK_DIAGNOSIS_SH4 = (1ULL << (ADC_B_CHANNEL_MASK_EXT_OFFSET + 20)), ///< Sample-and-hold 3 Self-Diagnosis + ADC_B_CHANNEL_MASK_DIAGNOSIS_SH5 = (1ULL << (ADC_B_CHANNEL_MASK_EXT_OFFSET + 21)), ///< Sample-and-hold 4 Self-Diagnosis + ADC_B_CHANNEL_MASK_DIAGNOSIS_SH6 = (1ULL << (ADC_B_CHANNEL_MASK_EXT_OFFSET + 22)), ///< Sample-and-hold 5 Self-Diagnosis +} adc_b_channel_mask_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/ra8p1/r_lpm_device_types.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/ra8p1/r_lpm_device_types.h new file mode 100644 index 00000000000..76e9561b73e --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/bsp/mcu/ra8p1/r_lpm_device_types.h @@ -0,0 +1,104 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RA8P1 + * @{ + **********************************************************************************************************************/ + +/** @} (end addtogroup BSP_MCU_RA8P1) */ + +#ifndef R_LPM_DEVICE_TYPES_H +#define R_LPM_DEVICE_TYPES_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_OVERRIDE_LPM_STANDBY_WAKE_SOURCE_T +#define BSP_OVERRIDE_LPM_SNOOZE_CANCEL_T + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Wake from deep sleep or standby mode sources, does not apply to sleep or deep standby modes */ +typedef enum e_lpm_standby_wake_source +{ + LPM_STANDBY_WAKE_SOURCE_IRQ0 = 0x00000001ULL, ///< IRQ0 + LPM_STANDBY_WAKE_SOURCE_IRQ1 = 0x00000002ULL, ///< IRQ1 + LPM_STANDBY_WAKE_SOURCE_IRQ2 = 0x00000004ULL, ///< IRQ2 + LPM_STANDBY_WAKE_SOURCE_IRQ3 = 0x00000008ULL, ///< IRQ3 + LPM_STANDBY_WAKE_SOURCE_IRQ4 = 0x00000010ULL, ///< IRQ4 + LPM_STANDBY_WAKE_SOURCE_IRQ5 = 0x00000020ULL, ///< IRQ5 + LPM_STANDBY_WAKE_SOURCE_IRQ6 = 0x00000040ULL, ///< IRQ6 + LPM_STANDBY_WAKE_SOURCE_IRQ7 = 0x00000080ULL, ///< IRQ7 + LPM_STANDBY_WAKE_SOURCE_IRQ8 = 0x00000100ULL, ///< IRQ8 + LPM_STANDBY_WAKE_SOURCE_IRQ9 = 0x00000200ULL, ///< IRQ9 + LPM_STANDBY_WAKE_SOURCE_IRQ10 = 0x00000400ULL, ///< IRQ10 + LPM_STANDBY_WAKE_SOURCE_IRQ11 = 0x00000800ULL, ///< IRQ11 + LPM_STANDBY_WAKE_SOURCE_IRQ12 = 0x00001000ULL, ///< IRQ12 + LPM_STANDBY_WAKE_SOURCE_IRQ13 = 0x00002000ULL, ///< IRQ13 + LPM_STANDBY_WAKE_SOURCE_IRQ14 = 0x00004000ULL, ///< IRQ14 + LPM_STANDBY_WAKE_SOURCE_IRQ15 = 0x00008000ULL, ///< IRQ15 + LPM_STANDBY_WAKE_SOURCE_IWDT = 0x00010000ULL, ///< Independent watchdog interrupt + LPM_STANDBY_WAKE_SOURCE_LVD1 = 0x00040000ULL, ///< Low Voltage Detection 1 interrupt + LPM_STANDBY_WAKE_SOURCE_LVD2 = 0x00080000ULL, ///< Low Voltage Detection 2 interrupt + LPM_STANDBY_WAKE_SOURCE_VBATT = 0x00100000ULL, ///< VBATT Monitor interrupt + LPM_STANDBY_WAKE_SOURCE_RTCALM = 0x01000000ULL, ///< RTC Alarm interrupt + LPM_STANDBY_WAKE_SOURCE_RTCPRD = 0x02000000ULL, ///< RTC Period interrupt + LPM_STANDBY_WAKE_SOURCE_USBHS = 0x04000000ULL, ///< USB High-speed interrupt + LPM_STANDBY_WAKE_SOURCE_USBFS = 0x08000000ULL, ///< USB Full-speed interrupt + LPM_STANDBY_WAKE_SOURCE_AGT1UD = 0x10000000ULL, ///< AGT1 Underflow interrupt + LPM_STANDBY_WAKE_SOURCE_AGT1CA = 0x20000000ULL, ///< AGT1 Compare Match A interrupt + LPM_STANDBY_WAKE_SOURCE_AGT1CB = 0x40000000ULL, ///< AGT1 Compare Match B interrupt + LPM_STANDBY_WAKE_SOURCE_IIC0 = 0x80000000ULL, ///< I2C 0 interrupt + LPM_STANDBY_WAKE_SOURCE_COMPHS0 = 0x800000000ULL, ///< Comparator-HS0 Interrupt + LPM_STANDBY_WAKE_SOURCE_SOSTD = 0x8000000000ULL, ///< SOSTD interrupt + LPM_STANDBY_WAKE_SOURCE_ULP0U = 0x10000000000ULL, ///< ULPT0 Underflow Interrupt + LPM_STANDBY_WAKE_SOURCE_ULP0A = 0x20000000000ULL, ///< ULPT0 Compare Match A Interrupt + LPM_STANDBY_WAKE_SOURCE_ULP0B = 0x40000000000ULL, ///< ULPT0 Compare Match B Interrupt + LPM_STANDBY_WAKE_SOURCE_I3C0 = 0x80000000000ULL, ///< I3C0 address match interrupt + LPM_STANDBY_WAKE_SOURCE_ULP1U = 0x100000000000ULL, ///< ULPT1 Underflow Interrupt + LPM_STANDBY_WAKE_SOURCE_ULP1A = 0x200000000000ULL, ///< ULPT1 Compare Match A Interrupt + LPM_STANDBY_WAKE_SOURCE_ULP1B = 0x400000000000ULL, ///< ULPT1 Compare Match B Interrupt + LPM_STANDBY_WAKE_SOURCE_PDM = 0x800000000000ULL, ///< PDM Sound Detection + LPM_STANDBY_WAKE_SOURCE_IRQ16 = 0x1000000000000ULL, ///< IRQ16 + LPM_STANDBY_WAKE_SOURCE_IRQ17 = 0x2000000000000ULL, ///< IRQ17 + LPM_STANDBY_WAKE_SOURCE_IRQ18 = 0x4000000000000ULL, ///< IRQ18 + LPM_STANDBY_WAKE_SOURCE_IRQ19 = 0x8000000000000ULL, ///< IRQ19 + LPM_STANDBY_WAKE_SOURCE_IRQ20 = 0x10000000000000ULL, ///< IRQ20 + LPM_STANDBY_WAKE_SOURCE_IRQ21 = 0x20000000000000ULL, ///< IRQ21 + LPM_STANDBY_WAKE_SOURCE_IRQ22 = 0x40000000000000ULL, ///< IRQ22 + LPM_STANDBY_WAKE_SOURCE_IRQ23 = 0x80000000000000ULL, ///< IRQ23 + LPM_STANDBY_WAKE_SOURCE_IRQ24 = 0x100000000000000ULL, ///< IRQ24 + LPM_STANDBY_WAKE_SOURCE_IRQ25 = 0x200000000000000ULL, ///< IRQ25 + LPM_STANDBY_WAKE_SOURCE_IRQ26 = 0x400000000000000ULL, ///< IRQ26 + LPM_STANDBY_WAKE_SOURCE_IRQ27 = 0x800000000000000ULL, ///< IRQ27 + LPM_STANDBY_WAKE_SOURCE_IRQ28 = 0x1000000000000000ULL, ///< IRQ28 + LPM_STANDBY_WAKE_SOURCE_IRQ29 = 0x2000000000000000ULL, ///< IRQ29 + LPM_STANDBY_WAKE_SOURCE_IRQ30 = 0x4000000000000000ULL, ///< IRQ30 + LPM_STANDBY_WAKE_SOURCE_IRQ31 = 0x8000000000000000ULL, ///< IRQ31 +} lpm_standby_wake_source_t; + +typedef uint64_t lpm_standby_wake_source_bits_t; + +/** Snooze cancel control */ +typedef enum e_lpm_snooze_cancel +{ + LPM_SNOOZE_CANCEL_SOURCE_NONE = 0, ///< No snooze cancel source +} lpm_snooze_cancel_t; + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_adc_b/r_adc_b.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_adc_b/r_adc_b.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_adc_b/r_adc_b.c rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_adc_b/r_adc_b.c diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_canfd/r_canfd.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_canfd/r_canfd.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_canfd/r_canfd.c rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_canfd/r_canfd.c diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_dmac/r_dmac.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_dmac/r_dmac.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_dmac/r_dmac.c rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_dmac/r_dmac.c diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_gpt/r_gpt.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_gpt/r_gpt.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_gpt/r_gpt.c rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_gpt/r_gpt.c diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_iic_master/r_iic_master.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_iic_master/r_iic_master.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_iic_master/r_iic_master.c rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_iic_master/r_iic_master.c diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_ioport/r_ioport.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_ioport/r_ioport.c new file mode 100644 index 00000000000..f747af1aad7 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_ioport/r_ioport.c @@ -0,0 +1,1034 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include "bsp_api.h" +#include "r_ioport.h" +#include "r_ioport_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* "PORT" in ASCII, used to determine if the module is open */ +#define IOPORT_OPEN (0x504F5254U) +#define IOPORT_CLOSED (0x00000000U) + +/* Mask to get PSEL bitfield from PFS register. */ +#define BSP_PRV_PFS_PSEL_MASK (R_PFS_PORT_PIN_PmnPFS_PSEL_Msk) + +/* Shift to get port in bsp_io_port_t and bsp_io_port_pin_t enums. */ +#define IOPORT_PRV_PORT_OFFSET (8U) + +#define IOPORT_PRV_PORT_BITS (0xFF00U) +#define IOPORT_PRV_PIN_BITS (0x00FFU) + +#define IOPORT_PRV_PERIPHERAL_FUNCTION (1U << 16) + +#define IOPORT_PRV_8BIT_MASK (0xFFU) +#define IOPORT_PRV_16BIT_MASK (0xFFFFU) + +#define IOPORT_PRV_PORT_ADDRESS(port_number) ((uint32_t) (R_PORT1 - R_PORT0) * (port_number) + R_PORT0) + +/* Stabilization time when output current control is enabled */ +#define IOPORT_PRV_CCDE_STABILIZATION_DELAY_US (10U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static void r_ioport_pins_config(const ioport_cfg_t * p_cfg); + +#if BSP_FEATURE_ELC_VERSION +static void r_ioport_hw_pin_event_output_data_write(bsp_io_port_t port, ioport_size_t pin, bsp_io_level_t pin_level); + +#endif + +static void r_ioport_pfs_write(bsp_io_port_pin_t pin, uint32_t value); + +#if BSP_FEATURE_RTC_HAS_VBTICTLR || BSP_FEATURE_RTC_HAS_TCEN +static void bsp_vbatt_init(ioport_cfg_t const * const p_pin_cfg); // Used internally by BSP + +#endif + +#if IOPORT_CFG_CCD_SUPPORT_ENABLE +static fsp_err_t r_ioport_ccd_pins_config(const ioport_extended_cfg_t * p_cfg_extend); + +#endif + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* IOPort Implementation of IOPort Driver */ +const ioport_api_t g_ioport_on_ioport = +{ + .open = R_IOPORT_Open, + .close = R_IOPORT_Close, + .pinsCfg = R_IOPORT_PinsCfg, + .pinCfg = R_IOPORT_PinCfg, + .pinEventInputRead = R_IOPORT_PinEventInputRead, + .pinEventOutputWrite = R_IOPORT_PinEventOutputWrite, + .pinRead = R_IOPORT_PinRead, + .pinWrite = R_IOPORT_PinWrite, + .portDirectionSet = R_IOPORT_PortDirectionSet, + .portEventInputRead = R_IOPORT_PortEventInputRead, + .portEventOutputWrite = R_IOPORT_PortEventOutputWrite, + .portRead = R_IOPORT_PortRead, + .portWrite = R_IOPORT_PortWrite, +}; + +#if BSP_FEATURE_RTC_HAS_VBTICTLR || BSP_FEATURE_RTC_HAS_TCEN +static const bsp_io_port_pin_t g_vbatt_pins_input[] = +{ + BSP_IO_PORT_04_PIN_02, ///< Associated with VBTICTLR->VCH0INEN + BSP_IO_PORT_04_PIN_03, ///< Associated with VBTICTLR->VCH1INEN + BSP_IO_PORT_04_PIN_04 ///< Associated with VBTICTLR->VCH2INEN +}; +#endif + +/*******************************************************************************************************************//** + * @addtogroup IOPORT + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initializes internal driver data, then calls pin configuration function to configure pins. + * + * @retval FSP_SUCCESS Pin configuration data written to PFS register(s) + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + * @retval FSP_ERR_INVALID_ARGUMENT Pin configurations is invalid. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_Open (ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg) +{ + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_pin_cfg_data || 0 == p_cfg->number_of_pins); + FSP_ERROR_RETURN(IOPORT_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* Set driver status to open */ + p_instance_ctrl->open = IOPORT_OPEN; + +#if IOPORT_CFG_CCD_SUPPORT_ENABLE + if (NULL != p_cfg->p_extend) + { + FSP_ERROR_RETURN(FSP_SUCCESS == r_ioport_ccd_pins_config((ioport_extended_cfg_t *) p_cfg->p_extend), + FSP_ERR_INVALID_ARGUMENT); + } +#endif + + r_ioport_pins_config(p_cfg); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Resets IOPORT registers. Implements @ref ioport_api_t::close + * + * @retval FSP_SUCCESS The IOPORT was successfully uninitialized + * @retval FSP_ERR_ASSERTION p_ctrl was NULL + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_Close (ioport_ctrl_t * const p_ctrl) +{ + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* Set state to closed */ + p_instance_ctrl->open = IOPORT_CLOSED; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configures the functions of multiple pins by loading configuration data into pin PFS registers. + * Implements @ref ioport_api_t::pinsCfg. + * + * This function initializes the supplied list of PmnPFS registers with the supplied values. This data can be generated + * by the Pins tab of the RA Configuration editor or manually by the developer. Different pin configurations can be + * loaded for different situations such as low power modes and testing. + * + * @retval FSP_SUCCESS Pin configuration data written to PFS register(s) + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinsCfg (ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_pin_cfg_data); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + r_ioport_pins_config(p_cfg); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configures the settings of a pin. Implements @ref ioport_api_t::pinCfg. + * + * @retval FSP_SUCCESS Pin configured + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + * + * @note This function is re-entrant for different pins. + * This function will change the configuration of the pin with the new configuration. For example it is not possible + * with this function to change the drive strength of a pin while leaving all the other pin settings unchanged. To + * achieve this the original settings with the required change will need to be written using this function. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinCfg (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + +#if BSP_FEATURE_RTC_HAS_VBTICTLR || BSP_FEATURE_RTC_HAS_TCEN + + /* Create temporary structure for handling VBATT pins. */ + ioport_cfg_t temp_cfg; + ioport_pin_cfg_t temp_pin_cfg; + + temp_pin_cfg.pin = pin; + temp_pin_cfg.pin_cfg = cfg; + + temp_cfg.number_of_pins = 1U; + temp_cfg.p_pin_cfg_data = &temp_pin_cfg; + + /* Handle any VBATT domain pin configuration. */ + bsp_vbatt_init(&temp_cfg); +#endif + + R_BSP_PinAccessEnable(); + + r_ioport_pfs_write(pin, cfg); + + R_BSP_PinAccessDisable(); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads the level on a pin. Implements @ref ioport_api_t::pinRead. + * + * @retval FSP_SUCCESS Pin read + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * + * @note This function is re-entrant for different pins. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_pin_value); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + *p_pin_value = (bsp_io_level_t) R_BSP_PinRead(pin); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads the value on an IO port. Implements @ref ioport_api_t::portRead. + * + * The specified port will be read, and the levels for all the pins will be returned. + * Each bit in the returned value corresponds to a pin on the port. For example, bit 7 corresponds + * to pin 7, bit 6 to pin 6, and so on. + * + * @retval FSP_SUCCESS Port read + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * + * @note This function is re-entrant for different ports. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PortRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_port_value); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* Get the port address */ + R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((port >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK); +#if (3U == BSP_FEATURE_IOPORT_VERSION) + + /* Read current value of PIDR for the specified port */ + *p_port_value = p_ioport_regs->PIDR; +#else + + /* Read current value of PCNTR2 register for the specified port */ + *p_port_value = p_ioport_regs->PCNTR2 & IOPORT_PRV_16BIT_MASK; +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Writes to multiple pins on a port. Implements @ref ioport_api_t::portWrite. + * + * The input value will be written to the specified port. Each bit in the value parameter corresponds to a bit + * on the port. For example, bit 7 corresponds to pin 7, bit 6 to pin 6, and so on. + * Each bit in the mask parameter corresponds to a pin on the port. + * + * Only the bits with the corresponding bit in the mask value set will be updated. + * For example, value = 0xFFFF, mask = 0x0003 results in only bits 0 and 1 being updated. + * + * @retval FSP_SUCCESS Port written to + * @retval FSP_ERR_INVALID_ARGUMENT The port and/or mask not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + * + * @note This function is re-entrant for different ports. This function makes use of the PCNTR3 register to atomically + * modify the levels on the specified pins on a port. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PortWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(mask > (ioport_size_t) 0, FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + ioport_size_t setbits; + ioport_size_t clrbits; + + /* High bits */ + setbits = value & mask; + + /* Low bits */ + /* Cast to ensure size */ + clrbits = (ioport_size_t) ((~value) & mask); + + /* Get the port address */ + R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((port >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK); + +#if (3U == BSP_FEATURE_IOPORT_VERSION) + + /* Reset data in PORR, set data in POSR register */ + p_ioport_regs->PORR = (uint16_t) clrbits; + p_ioport_regs->POSR = (uint16_t) setbits; +#else + + /* PCNTR3 register: lower word = set data, upper word = reset_data */ + p_ioport_regs->PCNTR3 = (uint32_t) (((uint32_t) clrbits << 16) | setbits); +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets a pin's output either high or low. Implements @ref ioport_api_t::pinWrite. + * + * @retval FSP_SUCCESS Pin written to + * @retval FSP_ERR_INVALID_ARGUMENT The pin and/or level not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + * + * @note This function is re-entrant for different pins. This function makes use of the PCNTR3 register to atomically + * modify the level on the specified pin on a port. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(level <= BSP_IO_LEVEL_HIGH, FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + ioport_size_t setbits = 0U; + ioport_size_t clrbits = 0U; + bsp_io_port_t port = (bsp_io_port_t) (IOPORT_PRV_PORT_BITS & (ioport_size_t) pin); + + ioport_size_t shift = IOPORT_PRV_PIN_BITS & (ioport_size_t) pin; + ioport_size_t pin_mask = (ioport_size_t) (1U << shift); + + if (BSP_IO_LEVEL_LOW == level) + { + clrbits = pin_mask; + } + else + { + setbits = pin_mask; + } + + /* PCNTR register is updated instead of using PFS as access is atomic and PFS requires separate enable/disable + * using PWPR register */ + + /* Get the port address */ + R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((port >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK); +#if (3U == BSP_FEATURE_IOPORT_VERSION) + + /* Reset data in PORR, set data in POSR register */ + p_ioport_regs->PORR = (uint16_t) clrbits; + p_ioport_regs->POSR = (uint16_t) setbits; +#else + + /* PCNTR3 register: lower word = set data, upper word = reset_data */ + p_ioport_regs->PCNTR3 = (uint32_t) (((uint32_t) clrbits << 16) | setbits); +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets the direction of individual pins on a port. Implements @ref ioport_api_t::portDirectionSet(). + * + * Multiple pins on a port can be set to inputs or outputs at once. + * Each bit in the mask parameter corresponds to a pin on the port. For example, bit 7 corresponds to + * pin 7, bit 6 to pin 6, and so on. If a bit is set to 1 then the corresponding pin will be changed to + * an input or an output as specified by the direction values. If a mask bit is set to 0 then the direction of + * the pin will not be changed. + * + * @retval FSP_SUCCESS Port direction updated + * @retval FSP_ERR_INVALID_ARGUMENT The port and/or mask not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + * + * @note This function is re-entrant for different ports. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PortDirectionSet (ioport_ctrl_t * const p_ctrl, + bsp_io_port_t port, + ioport_size_t direction_values, + ioport_size_t mask) +{ + uint32_t orig_value; + uint32_t set_bits; + uint32_t clr_bits; + uint32_t write_value; + +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(mask > (ioport_size_t) 0, FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* Get the port address */ + R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((port >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK); +#if (3U == BSP_FEATURE_IOPORT_VERSION) + + /* Read current value of PDR register for the specified port */ + orig_value = p_ioport_regs->PDR; +#else + + /* Read current value of PCNTR1 register for the specified port */ + orig_value = p_ioport_regs->PCNTR1; +#endif + + /* High bits */ + set_bits = direction_values & mask; + + /* Low bits */ + /* Cast to ensure size */ + clr_bits = (uint32_t) ((~direction_values) & mask); + + /* New value to write to port direction register */ + write_value = orig_value; + write_value |= set_bits; + + /* Clear bits as needed */ + write_value &= ~clr_bits; +#if (3U == BSP_FEATURE_IOPORT_VERSION) + p_ioport_regs->PDR = (uint16_t) write_value; +#else + p_ioport_regs->PCNTR1 = write_value; +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads the value of the event input data. Implements @ref ioport_api_t::portEventInputRead(). + * + * The event input data for the port will be read. Each bit in the returned value corresponds to a pin on the port. + * For example, bit 7 corresponds to pin 7, bit 6 to pin 6, and so on. + * + * The port event data is captured in response to a trigger from the ELC. This function enables this data to be read. + * Using the event system allows the captured data to be stored when it occurs and then read back at a later time. + * + * @retval FSP_SUCCESS Port read + * @retval FSP_ERR_INVALID_ARGUMENT Port not a valid ELC port + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_UNSUPPORTED Function not supported. + * + * @note This function is re-entrant for different ports. + * + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PortEventInputRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data) +{ +#if (3U != BSP_FEATURE_IOPORT_VERSION) + #if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_event_data); + uint32_t port_number = port >> IOPORT_PRV_PORT_OFFSET; + FSP_ERROR_RETURN((BSP_FEATURE_IOPORT_ELC_PORTS_MASK & (1 << port_number)), FSP_ERR_INVALID_ARGUMENT); + #else + FSP_PARAMETER_NOT_USED(p_ctrl); + #endif + + /* Get the port address */ + R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(port >> IOPORT_PRV_PORT_OFFSET & IOPORT_PRV_8BIT_MASK); + + /* Read current value of EIDR value from PCNTR2 register for the specified port */ + *p_event_data = p_ioport_regs->PCNTR2_b.EIDR; + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(port); + FSP_PARAMETER_NOT_USED(p_event_data); + + /* Return the unsupported error. */ + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Reads the value of the event input data of a specific pin. Implements @ref ioport_api_t::pinEventInputRead. + * + * The pin event data is captured in response to a trigger from the ELC. This function enables this data to be read. + * Using the event system allows the captured data to be stored when it occurs and then read back at a later time. + * + * @retval FSP_SUCCESS Pin read + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_INVALID_ARGUMENT Port is not valid ELC PORT. + * @retval FSP_ERR_UNSUPPORTED Function not supported. + * + * @note This function is re-entrant. + * + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinEventInputRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event) +{ +#if (3U != BSP_FEATURE_IOPORT_VERSION) + #if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_pin_event); + uint32_t port_number = pin >> IOPORT_PRV_PORT_OFFSET; + FSP_ERROR_RETURN((BSP_FEATURE_IOPORT_ELC_PORTS_MASK & (1 << port_number)), FSP_ERR_INVALID_ARGUMENT); + #else + FSP_PARAMETER_NOT_USED(p_ctrl); + #endif + + ioport_size_t portvalue; + ioport_size_t mask; + + /* Get the port address */ + R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((pin >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK); + + /* Read current value of EIDR value from PCNTR2 register for the specified port */ + portvalue = p_ioport_regs->PCNTR2_b.EIDR; + mask = (ioport_size_t) (1U << (IOPORT_PRV_PIN_BITS & (bsp_io_port_t) pin)); + + if ((portvalue & mask) == mask) + { + *p_pin_event = BSP_IO_LEVEL_HIGH; + } + else + { + *p_pin_event = BSP_IO_LEVEL_LOW; + } + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(pin); + FSP_PARAMETER_NOT_USED(p_pin_event); + + /* Return the unsupported error. */ + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * This function writes the set and reset event output data for a port. Implements + * @ref ioport_api_t::portEventOutputWrite. + * + * Using the event system enables a port state to be stored by this function in advance of being output on the port. + * The output to the port will occur when the ELC event occurs. + * + * The input value will be written to the specified port when an ELC event configured for that port occurs. + * Each bit in the value parameter corresponds to a bit on the port. For example, bit 7 corresponds to pin 7, + * bit 6 to pin 6, and so on. Each bit in the mask parameter corresponds to a pin on the port. + * + * @retval FSP_SUCCESS Port event data written + * @retval FSP_ERR_INVALID_ARGUMENT Port or Mask not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_UNSUPPORTED Function not supported + * + * @note This function is re-entrant for different ports. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PortEventOutputWrite (ioport_ctrl_t * const p_ctrl, + bsp_io_port_t port, + ioport_size_t event_data, + ioport_size_t mask_value) +{ +#if BSP_FEATURE_ELC_VERSION + ioport_size_t set_bits; + ioport_size_t reset_bits; + + #if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(mask_value > (ioport_size_t) 0, FSP_ERR_INVALID_ARGUMENT); + uint32_t port_number = port >> IOPORT_PRV_PORT_OFFSET; + FSP_ERROR_RETURN((BSP_FEATURE_IOPORT_ELC_PORTS_MASK & (1 << port_number)), FSP_ERR_INVALID_ARGUMENT); + #else + FSP_PARAMETER_NOT_USED(p_ctrl); + #endif + + set_bits = event_data & mask_value; + + /* Cast to ensure size */ + reset_bits = (ioport_size_t) ((~event_data) & mask_value); + + /* Get the port address */ + R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((port >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK); + #if (3U == BSP_FEATURE_IOPORT_VERSION) + + /* Reset data in EORR, set data in EOSR register */ + p_ioport_regs->EOSR = (uint16_t) set_bits; + p_ioport_regs->EORR = (uint16_t) reset_bits; + #else + + /* PCNTR4 register: lower word = set data, upper word = reset_data */ + p_ioport_regs->PCNTR4 = (uint32_t) (((uint32_t) reset_bits << 16) | set_bits); + #endif + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(port); + FSP_PARAMETER_NOT_USED(event_data); + FSP_PARAMETER_NOT_USED(mask_value); + + /* Return the unsupported error. */ + return FSP_ERR_UNSUPPORTED; +#endif +} + +/**********************************************************************************************************************//** + * This function writes the event output data value to a pin. Implements @ref ioport_api_t::pinEventOutputWrite. + * + * Using the event system enables a pin state to be stored by this function in advance of being output on the pin. + * The output to the pin will occur when the ELC event occurs. + * + * @retval FSP_SUCCESS Pin event data written + * @retval FSP_ERR_INVALID_ARGUMENT Port or Pin or value not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_UNSUPPORTED Function not supported + * + * @note This function is re-entrant for different ports. + * + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinEventOutputWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value) +{ +#if BSP_FEATURE_ELC_VERSION + #if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN((pin_value == BSP_IO_LEVEL_HIGH) || (pin_value == BSP_IO_LEVEL_LOW), FSP_ERR_INVALID_ARGUMENT); + uint32_t port_number = pin >> IOPORT_PRV_PORT_OFFSET; + FSP_ERROR_RETURN((BSP_FEATURE_IOPORT_ELC_PORTS_MASK & (1 << port_number)), FSP_ERR_INVALID_ARGUMENT); + #else + FSP_PARAMETER_NOT_USED(p_ctrl); + #endif + + r_ioport_hw_pin_event_output_data_write((bsp_io_port_t) (pin & IOPORT_PRV_PORT_BITS), + (ioport_size_t) (pin & IOPORT_PRV_PIN_BITS), pin_value); + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(pin); + FSP_PARAMETER_NOT_USED(pin_value); + + /* Return the unsupported error. */ + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * @} (end addtogroup IOPORT) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configures pins. + * + * @param[in] p_cfg Pin configuration data + **********************************************************************************************************************/ +void r_ioport_pins_config (const ioport_cfg_t * p_cfg) +{ +#if BSP_FEATURE_RTC_HAS_VBTICTLR || BSP_FEATURE_RTC_HAS_TCEN + + /* Handle any VBATT domain pin configuration. */ + bsp_vbatt_init(p_cfg); +#endif + + uint16_t pin_count; + ioport_cfg_t * p_pin_data; + + p_pin_data = (ioport_cfg_t *) p_cfg; + + R_BSP_PinAccessEnable(); // Protect PWPR from re-entrancy + + for (pin_count = 0U; pin_count < p_pin_data->number_of_pins; pin_count++) + { + r_ioport_pfs_write(p_pin_data->p_pin_cfg_data[pin_count].pin, p_pin_data->p_pin_cfg_data[pin_count].pin_cfg); + } + + R_BSP_PinAccessDisable(); +} + +#if BSP_FEATURE_ELC_VERSION + +/*******************************************************************************************************************//** + * Writes the set and clear values on a pin of the port when an ELC event occurs. This allows accurate timing of + * pin output level. + * + * @param[in] port Port to read event data + * @param[in] pin Bit in the EORR/EOSR to be set + * @param[in] pin_level Event data for pin + **********************************************************************************************************************/ +static void r_ioport_hw_pin_event_output_data_write (bsp_io_port_t port, ioport_size_t pin, bsp_io_level_t pin_level) +{ + /* Get the port address */ + R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((port >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK); + #if (3U == BSP_FEATURE_IOPORT_VERSION) + uint16_t set_value_high = (uint16_t) (pin_level << pin); + uint16_t set_value_low = (uint16_t) ((!pin_level) << pin); + + /* Ensure the same bits are not set in both registers */ + p_ioport_regs->EORR &= ~set_value_high; + p_ioport_regs->EOSR = (p_ioport_regs->EOSR & ~set_value_low) | set_value_high; + p_ioport_regs->EORR |= set_value_low; + #else + uint32_t set_value = (uint32_t) (1 << pin); + + /* Read current value of PCNTR4 register */ + uint32_t port_value = p_ioport_regs->PCNTR4; + + if (BSP_IO_LEVEL_HIGH == pin_level) + { + /* To avoid setting bit high in both EOSR and EORR */ + port_value &= ~(set_value << 16); + + /* Set output high */ + port_value |= set_value; + } + else + { + /* To avoid setting bit high in both EOSR and EORR */ + port_value &= ~set_value; + + /* Set output low */ + port_value |= set_value << 16; + } + p_ioport_regs->PCNTR4 = port_value; + #endif +} + +#endif + +/*******************************************************************************************************************//** + * Writes to the specified pin's PFS register + * + * @param[in] pin Pin to write PFS data for + * @param[in] value Value to be written to the PFS register + * + **********************************************************************************************************************/ +static void r_ioport_pfs_write (bsp_io_port_pin_t pin, uint32_t value) +{ +#if (3U != BSP_FEATURE_IOPORT_VERSION) + + /* PMR bits should be cleared before specifying PSEL. See "Notes on the PmnPFS Register Setting" + * in the I/O Ports section of the relevant hardware manual. */ + if ((value & IOPORT_PRV_PERIPHERAL_FUNCTION) > 0) + { + /* Clear PMR */ + R_PFS->PORT[pin >> IOPORT_PRV_PORT_OFFSET].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS_b.PMR = 0; + + /* New config with PMR = 0 */ + R_PFS->PORT[pin >> IOPORT_PRV_PORT_OFFSET].PIN[pin & + BSP_IO_PRV_8BIT_MASK].PmnPFS = + (value & ~((uint32_t) IOPORT_PRV_PERIPHERAL_FUNCTION)); + } + + /* Write configuration */ + R_PFS->PORT[pin >> IOPORT_PRV_PORT_OFFSET].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = value; +#else + + /* Write configuration */ + R_PFS->PORT[pin >> IOPORT_PRV_PORT_OFFSET].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = (uint16_t) value; +#endif +} + +#if BSP_FEATURE_RTC_HAS_VBTICTLR || BSP_FEATURE_RTC_HAS_TCEN + +/*******************************************************************************************************************//** + * @brief Initializes VBTICTLR register based on pin configuration. + * + * The VBTICTLR register may need to be modified based on the project's pin configuration. There is a set of pins that + * needs to be checked. If one of these pins is found in the pin configuration table then it will be tested to see if + * the appropriate VBTICTLR bit needs to be set or cleared. If one of the pins that is being searched for is not found + * then the accompanying VBTICTLR bit is left as-is. + **********************************************************************************************************************/ +static void bsp_vbatt_init (ioport_cfg_t const * const p_pin_cfg) +{ + uint32_t pin_index; + uint32_t vbatt_index; + + #if BSP_FEATURE_RTC_HAS_VBTICTLR + R_SYSTEM_Type * p_system = R_SYSTEM; + #endif + #if BSP_FEATURE_RTC_HAS_TCEN + R_RTC_Type * p_rtc = R_RTC; + #endif + + #if BSP_TZ_SECURE_BUILD && BSP_FEATURE_TZ_NS_OFFSET > 0 + #if BSP_FEATURE_RTC_HAS_VBTICTLR + if (1 == R_SYSTEM->BBFSAR_b.NONSEC2) + { + /* If security attribution of VBTICTLR is set to non-secure, then use the non-secure alias. */ + p_system = (R_SYSTEM_Type *) ((uint32_t) p_system | BSP_FEATURE_TZ_NS_OFFSET); + } + #endif + + #if BSP_FEATURE_RTC_HAS_TCEN + #if (BSP_FEATURE_TZ_NS_OFFSET == 0) + if (1 == R_PSCU->PSARE_b.PSARE2) + #else + if (1 == R_PSCU->PSARE_b.PSARE3) + #endif + { + /* If security attribution of RTC is set to non-secure, then use the non-secure alias. */ + p_rtc = (R_RTC_Type *) ((uint32_t) p_rtc | BSP_FEATURE_TZ_NS_OFFSET); + } + #endif + #endif + + /* Must loop over all pins as pin configuration table is unordered. */ + for (pin_index = 0U; pin_index < p_pin_cfg->number_of_pins; pin_index++) + { + /* Loop over VBATT input pins. */ + for (vbatt_index = 0U; + vbatt_index < (sizeof(g_vbatt_pins_input) / sizeof(g_vbatt_pins_input[0])); + vbatt_index++) + { + if (p_pin_cfg->p_pin_cfg_data[pin_index].pin == g_vbatt_pins_input[vbatt_index]) + { + /* Get PSEL value for pin. */ + uint32_t pfs_psel_value = p_pin_cfg->p_pin_cfg_data[pin_index].pin_cfg & BSP_PRV_PFS_PSEL_MASK; + + /* Check if pin is being used for RTC or AGT use. */ + if ((IOPORT_PERIPHERAL_AGT == pfs_psel_value) || (IOPORT_PERIPHERAL_CLKOUT_COMP_RTC == pfs_psel_value)) + { + /* Bit should be set to 1. */ + #if BSP_FEATURE_RTC_HAS_VBTICTLR + #if BSP_TZ_NONSECURE_BUILD + if (0 == R_SYSTEM->BBFSAR_b.NONSEC2) + { + /* Do nothing: non secure build can't configure secure VBTICTLR register. */ + } + else + #endif + if (0 == (p_system->VBTICTLR & (uint8_t) (1U << vbatt_index))) + { + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT); + p_system->VBTICTLR |= (uint8_t) (1U << vbatt_index); + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT); + } + else + { + /* Do nothing: it is already enabled. */ + } + #endif + #if BSP_FEATURE_RTC_HAS_TCEN + #if BSP_TZ_NONSECURE_BUILD + #if (BSP_FEATURE_TZ_NS_OFFSET == 0) + if (0 == R_PSCU->PSARE_b.PSARE2) + #else + if (0 == R_PSCU->PSARE_b.PSARE3) + #endif + { + /* Do nothing: non secure build can't configure secure RTC registers. */ + } + else + #endif + { + if (0 == p_rtc->RTCCR[vbatt_index].RTCCR_b.TCEN) + { + p_rtc->RTCCR[vbatt_index].RTCCR_b.TCEN = 1; + R_BSP_SoftwareDelay(BSP_PRV_RTC_RESET_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + } + else + { + /* Do nothing: it is already enabled. */ + } + } + #endif + } + else + { + /* Bit should be cleared to 0. */ + #if BSP_FEATURE_RTC_HAS_VBTICTLR + #if BSP_TZ_NONSECURE_BUILD + if (0 == R_SYSTEM->BBFSAR_b.NONSEC2) + { + /* Do nothing: non secure build can't configure secure VBTICTLR register. */ + } + else + #endif + if ((p_system->VBTICTLR & (uint8_t) (1U << vbatt_index)) > 0) + { + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT); + p_system->VBTICTLR &= (uint8_t) ~(1U << vbatt_index); + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT); + } + else + { + /* Do nothing: it is already disabled. */ + } + #endif + #if BSP_FEATURE_RTC_HAS_TCEN + #if BSP_TZ_NONSECURE_BUILD + #if (BSP_FEATURE_TZ_NS_OFFSET == 0) + if (0 == R_PSCU->PSARE_b.PSARE2) + #else + if (0 == R_PSCU->PSARE_b.PSARE3) + #endif + { + /* Do nothing: non secure build can't configure secure RTC registers. */ + } + else + #endif + { + if (p_rtc->RTCCR[vbatt_index].RTCCR_b.TCEN > 0) + { + p_rtc->RTCCR[vbatt_index].RTCCR_b.TCEN = 0; + R_BSP_SoftwareDelay(BSP_PRV_RTC_RESET_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + } + else + { + /* Do nothing: it is already disabled. */ + } + } + #endif + } + } + } + } +} + +#endif + +#if IOPORT_CFG_CCD_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * @brief Initializes the low-level output current control settings for CCD pins. + * + * This internal function configures the low-level output current values for CCD pins based on the provided extended + * configuration. It updates the CCS registers with the specified current levels, modifies the CCDE register to enable + * the required CCD pins, and waits for stabilization. + * + * @retval FSP_SUCCESS CCD pins configured. + * @retval FSP_ERR_INVALID_ARGUMENT CCD pin configurations are invalid. + * + **********************************************************************************************************************/ +static fsp_err_t r_ioport_ccd_pins_config (const ioport_extended_cfg_t * p_cfg_extend) +{ + uint8_t ccde_value = 0U; + + for (uint8_t index = 0; index < IOPORT_PRV_CCD_PIN_COUNT; index++) + { + ioport_output_current_t ccd_cfg = p_cfg_extend->ccd_pin_cfg_data[index]; + #if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + + /* 15 mA is only for CCD4 to CCD7 */ + FSP_ERROR_RETURN(((IOPORT_OUTPUT_CURRENT_15_MA != ccd_cfg) || (index > 3)), FSP_ERR_INVALID_ARGUMENT); + #endif + if ((BSP_FEATURE_IOPORT_CCD_PINS_MASK & (1U << index)) && (IOPORT_OUTPUT_CURRENT_DISABLE != ccd_cfg)) + { + R_PORGA->CCS[index] = (uint8_t) ccd_cfg; + ccde_value |= (1U << index); + } + } + + R_PORGA->CCDE = ccde_value; + + /* Wait for the stable time (10 us). See in hardware manual: IOPORT > Register Descriptions > CCDE */ + R_BSP_SoftwareDelay(IOPORT_PRV_CCDE_STABILIZATION_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + + return FSP_SUCCESS; +} + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_layer3_switch/r_layer3_switch.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_layer3_switch/r_layer3_switch.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_layer3_switch/r_layer3_switch.c rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_layer3_switch/r_layer3_switch.c diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_ospi_b/r_ospi_b.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_ospi_b/r_ospi_b.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_ospi_b/r_ospi_b.c rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_ospi_b/r_ospi_b.c diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_rmac/r_rmac.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_rmac/r_rmac.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_rmac/r_rmac.c rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_rmac/r_rmac.c diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_rmac_phy/r_rmac_phy.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_rmac_phy/r_rmac_phy.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_rmac_phy/r_rmac_phy.c rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_rmac_phy/r_rmac_phy.c diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_rmac_phy/targets/DP83620/r_rmac_phy_target_dp83620.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_rmac_phy/targets/DP83620/r_rmac_phy_target_dp83620.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_rmac_phy/targets/DP83620/r_rmac_phy_target_dp83620.c rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_rmac_phy/targets/DP83620/r_rmac_phy_target_dp83620.c diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_rmac_phy/targets/GPY111/r_rmac_phy_target_gpy111.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_rmac_phy/targets/GPY111/r_rmac_phy_target_gpy111.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_rmac_phy/targets/GPY111/r_rmac_phy_target_gpy111.c rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_rmac_phy/targets/GPY111/r_rmac_phy_target_gpy111.c diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_rmac_phy/targets/ICS1894/r_rmac_phy_target_ics1894.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_rmac_phy/targets/ICS1894/r_rmac_phy_target_ics1894.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_rmac_phy/targets/ICS1894/r_rmac_phy_target_ics1894.c rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_rmac_phy/targets/ICS1894/r_rmac_phy_target_ics1894.c diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_rmac_phy/targets/KSZ8041/r_rmac_phy_target_ksz8041.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_rmac_phy/targets/KSZ8041/r_rmac_phy_target_ksz8041.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_rmac_phy/targets/KSZ8041/r_rmac_phy_target_ksz8041.c rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_rmac_phy/targets/KSZ8041/r_rmac_phy_target_ksz8041.c diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_rmac_phy/targets/KSZ8091RNB/r_rmac_phy_target_ksz8091rnb.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_rmac_phy/targets/KSZ8091RNB/r_rmac_phy_target_ksz8091rnb.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_rmac_phy/targets/KSZ8091RNB/r_rmac_phy_target_ksz8091rnb.c rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_rmac_phy/targets/KSZ8091RNB/r_rmac_phy_target_ksz8091rnb.c diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_rtc/r_rtc.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_rtc/r_rtc.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_rtc/r_rtc.c rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_rtc/r_rtc.c diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_sci_b_uart/r_sci_b_uart.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_sci_b_uart/r_sci_b_uart.c new file mode 100644 index 00000000000..330c23cfb4b --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_sci_b_uart/r_sci_b_uart.c @@ -0,0 +1,1821 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_sci_b_uart.h" +#include + +/***********************************************************************************************************************fCCR0 + * Macro definitions + **********************************************************************************************************************/ +#ifndef SCI_B_UART_CFG_RX_ENABLE + #define SCI_B_UART_CFG_RX_ENABLE 1 +#endif +#ifndef SCI_B_UART_CFG_TX_ENABLE + #define SCI_B_UART_CFG_TX_ENABLE 1 +#endif + +/* Number of divisors in the data table used for baud rate calculation. */ +#define SCI_B_UART_NUM_DIVISORS_ASYNC (13U) + +/* Valid range of values for the modulation duty register is 128 - 256 (256 = modulation disabled). */ +#define SCI_B_UART_MDDR_MIN (128U) +#define SCI_B_UART_MDDR_MAX (256U) + +/* The bit rate setting field is of 8-bits, so the maximum value is 255. */ +#define SCI_B_UART_BRR_MAX (255U) + +/* No limit to the number of bytes to read or write if DTC is not used. */ +#define SCI_B_UART_MAX_READ_WRITE_NO_DTC (0xFFFFFFFFU) + +/* Mask off invalid data bits in 9-bit mode. */ +#define SCI_B_UART_ALIGN_2_BYTES (0x1U) + +/* "SCIB" in ASCII. Used to determine if the control block is open. */ +#define SCI_B_UART_OPEN (0x53434942U) + +/* Default SCI Register values. */ +#define SCI_B_UART_CCR2_DEFAULT_VALUE (0xFF00FF04U) +#define SCI_B_UART_FCR_DEFAULT_VALUE (0x1F1F0000U) + +/* SCI CCR1 register bit offsets and masks */ +#define SCI_B_UART_CCR1_SPB2_OFFSET (4U) +#define SCI_B_UART_CCR1_SPB2_MASK (0x00000030U) +#define SCI_B_UART_CCR1_PARITY_OFFSET (8U) +#define SCI_B_UART_CCR1_PARITY_MASK (0x00000300U) +#define SCI_B_UART_CCR1_FLOW_CTSRTS_MASK (0x00000003U) + +/* SCI CCR3 register bit offsets and masks */ +#define SCI_B_UART_CCR3_CHAR_OFFSET (8U) +#define SCI_B_UART_CCR3_CHAR_MASK (0x00000300U) +#define SCI_B_UART_CCR3_CKE_OFFSET (24U) +#define SCI_B_UART_CCR3_CKE_MASK (0x03000000U) + +/* SCI Data register bit masks */ +#define SCI_B_UART_TDR_TDAT_MASK_9BITS (0x000091FFU) + +/* SCI CSR register receiver error (overflow, framing, parity) bits masks */ +#define SCI_B_UART_RCVR_ERR_MASK (R_SCI_B0_CSR_ORER_Msk | R_SCI_B0_CSR_FER_Msk | R_SCI_B0_CSR_PER_Msk) + +/* SCI Error event masks */ +#define SCI_B_UART_ORR_EVENT8_MASK (0x20) +#define SCI_B_UART_ERR_EVENT8_MASK (0x38) + +/* SCI CFCLR register bit masks */ +#define SCI_B_UART_CFCLR_CLEAR_ALL_MASK (0x9D070010U) +#define SCI_B_UART_CFCLR_RDRFC_MASK (0x80000000U) +#define SCI_B_UART_CFCLR_TDREC_MASK (0x20000000U) + +/* SCI FFCLR register bit masks */ +#define SCI_B_UART_FFCLR_CLEAR_ALL_MASK (0x00000001U) + +/* SCI chanel size */ +#define SCI_B_REG_SIZE (R_SCI1_BASE - R_SCI0_BASE) + +#define SCI_B_UART_INVALID_16BIT_PARAM (0xFFFFU) +#define SCI_B_UART_DTC_MAX_TRANSFER (0x10000U) + +/* SCI FCR register bit masks */ +#define SCI_B_UART_FCR_TRIGGER_MASK (0xF) +#define SCI_B_UART_FCR_RESET_TX_RX (0x00808000U) + +/* DTC Configuration for Receive operation */ +#define SCI_B_UART_DTC_RX_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << TRANSFER_SETTINGS_DEST_ADDR_BITS)) + +/* DTC Configuration for Transmit operation */ +#define SCI_B_UART_DTC_TX_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << TRANSFER_SETTINGS_DEST_ADDR_BITS)) + +/* Flow Control pin active state */ +#ifndef SCI_B_UART_FLOW_CONTROL_ACTIVE + #define SCI_B_UART_FLOW_CONTROL_ACTIVE BSP_IO_LEVEL_HIGH +#endif + +/* Flow Control pin inactive state */ +#ifndef SCI_B_UART_FLOW_CONTROL_INACTIVE + #define SCI_B_UART_FLOW_CONTROL_INACTIVE BSP_IO_LEVEL_LOW +#endif + +/*********************************************************************************************************************** + * Private constants + **********************************************************************************************************************/ +static const int32_t SCI_B_UART_100_PERCENT_X_1000 = 100000; +static const int32_t SCI_B_UART_MDDR_DIVISOR = 256; + +#if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) +static const uint32_t SCI_B_UART_MAX_BAUD_RATE_ERROR_X_1000 = 15000; +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef struct st_baud_setting_const_t +{ + uint8_t bgdm : 1; /**< BGDM value to get divisor */ + uint8_t abcs : 1; /**< ABCS value to get divisor */ + uint8_t abcse : 1; /**< ABCSE value to get divisor */ + uint8_t cks : 2; /**< CKS value to get divisor (CKS = N) */ +} baud_setting_const_t; + +/* Noise filter setting definition */ +typedef enum e_noise_cancel_lvl +{ + NOISE_CANCEL_LVL1 = 0, /**< Noise filter level 1(weak) */ + NOISE_CANCEL_LVL2 = 2, /**< Noise filter level 2 */ + NOISE_CANCEL_LVL3 = 4, /**< Noise filter level 3 */ + NOISE_CANCEL_LVL4 = 8, /**< Noise filter level 4(strong) */ +} noise_cancel_lvl_t; + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * sci_b_uart_prv_ns_callback)(uart_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile sci_b_uart_prv_ns_callback)(uart_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +#if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) +static fsp_err_t r_sci_b_read_write_param_check(sci_b_uart_instance_ctrl_t const * const p_ctrl, + uint8_t const * const addr, + uint32_t const bytes); + +#endif + +static void r_sci_b_uart_config_set(sci_b_uart_instance_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg); + +#if SCI_B_UART_CFG_DTC_SUPPORTED +static fsp_err_t r_sci_b_uart_transfer_configure(sci_b_uart_instance_ctrl_t * const p_ctrl, + transfer_instance_t const * p_transfer, + uint32_t * p_transfer_reg, + uint32_t address); + +static fsp_err_t r_sci_b_uart_transfer_open(sci_b_uart_instance_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg); + +static void r_sci_b_uart_transfer_close(sci_b_uart_instance_ctrl_t * p_ctrl); + +#endif + +static void r_sci_b_uart_call_callback(sci_b_uart_instance_ctrl_t * p_ctrl, uint32_t data, uart_event_t event); + +#if SCI_B_UART_CFG_FIFO_SUPPORT +static void r_sci_b_uart_fifo_cfg(sci_b_uart_instance_ctrl_t * const p_ctrl); + +#endif + +static void r_sci_b_irq_cfg(sci_b_uart_instance_ctrl_t * const p_ctrl, uint8_t const ipl, IRQn_Type const p_irq); + +static void r_sci_b_irqs_cfg(sci_b_uart_instance_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg); + +#if (SCI_B_UART_CFG_RX_ENABLE) +void sci_b_uart_rxi_isr(void); + +void sci_b_uart_eri_isr(void); + +#endif + +#if (SCI_B_UART_CFG_TX_ENABLE) +void sci_b_uart_txi_isr(void); +void sci_b_uart_tei_isr(void); + +#endif + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/* Baud rate divisor information (UART mode) */ +static const baud_setting_const_t g_async_baud[SCI_B_UART_NUM_DIVISORS_ASYNC] = +{ + {0U, 0U, 1U, 0U}, /* BGDM, ABCS, ABCSE, n */ + {1U, 1U, 0U, 0U}, + {1U, 0U, 0U, 0U}, + {0U, 0U, 1U, 1U}, + {0U, 0U, 0U, 0U}, + {1U, 0U, 0U, 1U}, + {0U, 0U, 1U, 2U}, + {0U, 0U, 0U, 1U}, + {1U, 0U, 0U, 2U}, + {0U, 0U, 1U, 3U}, + {0U, 0U, 0U, 2U}, + {1U, 0U, 0U, 3U}, + {0U, 0U, 0U, 3U} +}; + +static const uint16_t g_div_coefficient[SCI_B_UART_NUM_DIVISORS_ASYNC] = +{ + 6U, + 8U, + 16U, + 24U, + 32U, + 64U, + 96U, + 128U, + 256U, + 384U, + 512U, + 1024U, + 2048U, +}; + +/* UART on SCI HAL API mapping for UART interface */ +const uart_api_t g_uart_on_sci_b = +{ + .open = R_SCI_B_UART_Open, + .close = R_SCI_B_UART_Close, + .write = R_SCI_B_UART_Write, + .read = R_SCI_B_UART_Read, + .infoGet = R_SCI_B_UART_InfoGet, + .baudSet = R_SCI_B_UART_BaudSet, + .communicationAbort = R_SCI_B_UART_Abort, + .callbackSet = R_SCI_B_UART_CallbackSet, + .readStop = R_SCI_B_UART_ReadStop, + .receiveSuspend = R_SCI_B_UART_ReceiveSuspend, + .receiveResume = R_SCI_B_UART_ReceiveResume, +}; + +/*******************************************************************************************************************//** + * @addtogroup SCI_B_UART + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configures the UART driver based on the input configurations. If reception is enabled at compile time, reception is + * enabled at the end of this function. Implements @ref uart_api_t::open + * + * @retval FSP_SUCCESS Channel opened successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block or configuration structure is NULL. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The requested channel does not exist on this MCU. + * @retval FSP_ERR_INVALID_ARGUMENT Flow control is enabled but flow control pin is not defined. + * @retval FSP_ERR_ALREADY_OPEN Control block has already been opened or channel is being used by another + * instance. Call close() then open() to reconfigure. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::open + **********************************************************************************************************************/ +fsp_err_t R_SCI_B_UART_Open (uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const p_cfg) +{ + sci_b_uart_instance_ctrl_t * p_ctrl = (sci_b_uart_instance_ctrl_t *) p_api_ctrl; + +#if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) + + /* Check parameters. */ + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_cfg); + + FSP_ASSERT(p_cfg->p_extend); + FSP_ASSERT(((sci_b_uart_extended_cfg_t *) p_cfg->p_extend)->p_baud_setting); + FSP_ERROR_RETURN(SCI_B_UART_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); + + /* Make sure this channel exists. */ + FSP_ERROR_RETURN(BSP_FEATURE_SCI_CHANNELS_MASK & (1U << p_cfg->channel), FSP_ERR_IP_CHANNEL_NOT_PRESENT); + + if (((sci_b_uart_extended_cfg_t *) p_cfg->p_extend)->flow_control == SCI_B_UART_FLOW_CONTROL_CTSRTS) + { + FSP_ERROR_RETURN( + ((sci_b_uart_extended_cfg_t *) p_cfg->p_extend)->flow_control_pin != SCI_B_UART_INVALID_16BIT_PARAM, + FSP_ERR_INVALID_ARGUMENT); + } + + FSP_ASSERT(p_cfg->rxi_irq >= 0); + FSP_ASSERT(p_cfg->txi_irq >= 0); + FSP_ASSERT(p_cfg->tei_irq >= 0); + FSP_ASSERT(p_cfg->eri_irq >= 0); +#endif + + p_ctrl->p_reg = (R_SCI_B0_Type *) (R_SCI0_BASE + (SCI_B_REG_SIZE * p_cfg->channel)); + + p_ctrl->fifo_depth = 0U; +#if SCI_B_UART_CFG_FIFO_SUPPORT + + /* Check if the channel supports fifo */ + if (BSP_FEATURE_SCI_UART_FIFO_CHANNELS_MASK & (1U << p_cfg->channel)) + { + /* Set fifo depth. */ + p_ctrl->fifo_depth = BSP_FEATURE_SCI_UART_FIFO_DEPTH; + } +#endif + + p_ctrl->p_cfg = p_cfg; + + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; + sci_b_uart_extended_cfg_t * p_extend = (sci_b_uart_extended_cfg_t *) p_cfg->p_extend; + + p_ctrl->data_bytes = 1U; + if (UART_DATA_BITS_9 == p_cfg->data_bits) + { + p_ctrl->data_bytes = 2U; + } + + /* Configure the interrupts. */ + r_sci_b_irqs_cfg(p_ctrl, p_cfg); + +#if SCI_B_UART_CFG_DTC_SUPPORTED + + /* Configure the transfer interface for transmission and reception if provided. */ + fsp_err_t err = r_sci_b_uart_transfer_open(p_ctrl, p_cfg); + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + uint32_t ccr0 = R_SCI_B0_CCR0_IDSEL_Msk; + + /* Enable the SCI channel */ + R_BSP_MODULE_START(FSP_IP_SCI, p_cfg->channel); + + /* Initialize registers as defined in "SCI Initialization in Asynchronous Mode" + * in relevant hardware manual. */ + p_ctrl->p_reg->CCR0 = ccr0; + + /* Set the UART configuration settings provided in ::uart_cfg_t and ::sci_b_uart_extended_cfg_t. */ + r_sci_b_uart_config_set(p_ctrl, p_cfg); + + p_ctrl->p_tx_src = NULL; + p_ctrl->tx_src_bytes = 0U; + p_ctrl->p_rx_dest = NULL; + p_ctrl->rx_dest_bytes = 0; + + /* Set flow control pins. */ + p_ctrl->flow_pin = p_extend->flow_control_pin; + +#if SCI_B_UART_CFG_FLOW_CONTROL_SUPPORT + if (p_ctrl->flow_pin != SCI_B_UART_INVALID_16BIT_PARAM) + { + R_BSP_PinAccessEnable(); + R_BSP_PinWrite(p_ctrl->flow_pin, SCI_B_UART_FLOW_CONTROL_INACTIVE); + R_BSP_PinAccessDisable(); + } +#endif + + /* Clear all flags in CSR register. */ + p_ctrl->p_reg->CFCLR = SCI_B_UART_CFCLR_CLEAR_ALL_MASK; + +#if SCI_B_UART_CFG_FIFO_SUPPORT + p_ctrl->p_reg->FFCLR = SCI_B_UART_FFCLR_CLEAR_ALL_MASK; +#endif + +#if (SCI_B_UART_CFG_RX_ENABLE) + + /* If reception is enabled at build time, enable reception. */ + ccr0 |= R_SCI_B0_CCR0_RE_Msk; + R_BSP_IrqEnable(p_ctrl->p_cfg->rxi_irq); + R_BSP_IrqEnable(p_ctrl->p_cfg->eri_irq); + + ccr0 |= R_SCI_B0_CCR0_RIE_Msk; +#endif + +#if (SCI_B_UART_CFG_TX_ENABLE) + + /* NOTE: Transmitter and its interrupt are enabled in R_SCI_B_UART_Write(). */ + R_BSP_IrqEnable(p_ctrl->p_cfg->txi_irq); + R_BSP_IrqEnable(p_ctrl->p_cfg->tei_irq); + + ccr0 |= R_SCI_B0_CCR0_TE_Msk; +#endif + p_ctrl->p_reg->CCR0 = ccr0; + + /* Wait until interanl state of RE is 1 as it takes some time for the state to be reflected internally after + * rewriting the control register. See "CESR : Communication Enable Status Register" description + * in the SCI section of the relevant hardware manual. */ + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->CESR_b.RIST, 1U); + + p_ctrl->open = SCI_B_UART_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Aborts any in progress transfers. Disables interrupts, receiver, and transmitter. Closes lower level transfer + * drivers if used. Removes power. Implements @ref uart_api_t::close + * + * @retval FSP_SUCCESS Channel successfully closed. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + **********************************************************************************************************************/ +fsp_err_t R_SCI_B_UART_Close (uart_ctrl_t * const p_api_ctrl) +{ + sci_b_uart_instance_ctrl_t * p_ctrl = (sci_b_uart_instance_ctrl_t *) p_api_ctrl; +#if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); +#endif + + FSP_ERROR_RETURN(SCI_B_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + +#if (SCI_B_UART_CFG_TX_ENABLE) + p_ctrl->p_reg->CCR0 &= (uint32_t) ~(R_SCI_B0_CCR0_TIE_Msk | R_SCI_B0_CCR0_TEIE_Msk); + + #if SCI_B_UART_CFG_FIFO_SUPPORT + if (p_ctrl->fifo_depth > 0U) + { + /* Reset the transmit fifo */ + p_ctrl->p_reg->FCR_b.TFRST = 1U; + + /* Clear the CCR3_b.FM bit. This is necessary to set the TEND bit before setting the TE bit. If TEND is 0 + * when TE is set to 0, the SCI peripheral works abnormally next time the TE made to 1.*/ + p_ctrl->p_reg->CCR3 = 0U; + } + #endif + + /* Disable transmission */ + p_ctrl->p_reg->CCR0 &= (uint32_t) ~(R_SCI_B0_CCR0_TE_Msk); + + /* Wait until interanl state of TE is 0 as it takes some time for the state to be reflected internally after + * rewriting the control register. See "CESR : Communication Enable Status Register" description + * in the SCI section of the relevant hardware manual. */ + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->CESR_b.TIST, 0U); + + /* If transmission is enabled at build time, disable transmission irqs. */ + R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); + R_BSP_IrqDisable(p_ctrl->p_cfg->tei_irq); +#endif + +#if (SCI_B_UART_CFG_RX_ENABLE) + p_ctrl->p_reg->CCR0 &= (uint32_t) ~(R_SCI_B0_CCR0_RIE_Msk); + + /* If reception is enabled at build time, disable reception irqs. */ + R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq); + R_BSP_IrqDisable(p_ctrl->p_cfg->eri_irq); +#endif + +#if SCI_B_UART_CFG_DTC_SUPPORTED + + /* Close the lower level transfer instances. */ + r_sci_b_uart_transfer_close(p_ctrl); +#endif + + /* Remove power to the channel. */ + R_BSP_MODULE_STOP(FSP_IP_SCI, p_ctrl->p_cfg->channel); + + /* Mark the channel not open so other APIs cannot use it. */ + p_ctrl->open = 0U; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Receives user specified number of bytes into destination buffer pointer. Implements @ref uart_api_t::read + * + * @retval FSP_SUCCESS Data reception successfully ends. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * Number of transfers outside the max or min boundary when transfer instance used + * @retval FSP_ERR_INVALID_ARGUMENT Destination address or data size is not valid for 9-bit mode. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_IN_USE A previous read operation is still in progress. + * @retval FSP_ERR_UNSUPPORTED SCI_B_UART_CFG_RX_ENABLE is set to 0 + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::reset + * + * @note If 9-bit data length is specified at R_SCI_B_UART_Open call, p_dest must be aligned 16-bit boundary. + **********************************************************************************************************************/ +fsp_err_t R_SCI_B_UART_Read (uart_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes) +{ +#if (SCI_B_UART_CFG_RX_ENABLE) + sci_b_uart_instance_ctrl_t * p_ctrl = (sci_b_uart_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; + + #if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) + err = r_sci_b_read_write_param_check(p_ctrl, p_dest, bytes); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ERROR_RETURN(0U == p_ctrl->rx_dest_bytes, FSP_ERR_IN_USE); + #endif + + #if SCI_B_UART_CFG_DTC_SUPPORTED + + /* Configure transfer instance to receive the requested number of bytes if transfer is used for reception. */ + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + uint32_t size = bytes >> (p_ctrl->data_bytes - 1); + #if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) + + /* Check that the number of transfers is within the 16-bit limit. */ + FSP_ASSERT(size <= SCI_B_UART_DTC_MAX_TRANSFER); + #endif + err = + p_ctrl->p_cfg->p_transfer_rx->p_api->reset(p_ctrl->p_cfg->p_transfer_rx->p_ctrl, NULL, (void *) p_dest, + (uint16_t) size); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif + + /* Save the destination address and size for use in rxi_isr. */ + p_ctrl->p_rx_dest = p_dest; + p_ctrl->rx_dest_bytes = bytes; + + return err; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_dest); + FSP_PARAMETER_NOT_USED(bytes); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Transmits user specified number of bytes from the source buffer pointer. Implements @ref uart_api_t::write + * + * @retval FSP_SUCCESS Data transmission finished successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * Number of transfers outside the max or min boundary when transfer instance used + * @retval FSP_ERR_INVALID_ARGUMENT Source address or data size is not valid for 9-bit mode. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_IN_USE A UART transmission is in progress + * @retval FSP_ERR_UNSUPPORTED SCI_B_UART_CFG_TX_ENABLE is set to 0 + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::reset + * + * @note If 9-bit data length is specified at R_SCI_B_UART_Open call, p_src must be aligned on a 16-bit boundary. + **********************************************************************************************************************/ +fsp_err_t R_SCI_B_UART_Write (uart_ctrl_t * const p_api_ctrl, uint8_t const * const p_src, uint32_t const bytes) +{ +#if (SCI_B_UART_CFG_TX_ENABLE) + sci_b_uart_instance_ctrl_t * p_ctrl = (sci_b_uart_instance_ctrl_t *) p_api_ctrl; + #if SCI_B_UART_CFG_PARAM_CHECKING_ENABLE || SCI_B_UART_CFG_DTC_SUPPORTED + fsp_err_t err = FSP_SUCCESS; + #endif + + #if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) + err = r_sci_b_read_write_param_check(p_ctrl, p_src, bytes); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ERROR_RETURN(0U == p_ctrl->tx_src_bytes, FSP_ERR_IN_USE); + #endif + + /* Transmit interrupts must be disabled to start with. */ + p_ctrl->p_reg->CCR0 &= (uint32_t) ~(R_SCI_B0_CCR0_TIE_Msk | R_SCI_B0_CCR0_TEIE_Msk); + + /* Make sure no transmission is in progress. Setting CCR0_b.TE to 0 when CSR_b.TEND is 0 causes SCI peripheral + * to work abnormally. */ + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->CSR_b.TEND, 1U); + + /* Set TE bit to 0. This is done to set TE and TIE bit simultaneously at the end of this function. + * See "Serial Data Transmission in Asynchronous Mode" in the SCI section of the relevant hardware manual. */ + p_ctrl->p_reg->CCR0 &= (uint32_t) ~(R_SCI_B0_CCR0_TE_Msk); + + /* Wait until interanl state of TE is 0 as it takes some time for the state to be reflected internally after + * rewriting the control register. See "CESR : Communication Enable Status Register" description + * in the SCI section of the relevant hardware manual. */ + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->CESR_b.TIST, 0U); + + p_ctrl->tx_src_bytes = bytes; + p_ctrl->p_tx_src = p_src; + + #if SCI_B_UART_CFG_DTC_SUPPORTED + + /* If a transfer instance is used for transmission, reset the transfer instance to transmit the requested + * data. */ + if ((NULL != p_ctrl->p_cfg->p_transfer_tx) && p_ctrl->tx_src_bytes) + { + uint32_t data_bytes = p_ctrl->data_bytes; + uint32_t num_transfers = p_ctrl->tx_src_bytes >> (data_bytes - 1); + p_ctrl->tx_src_bytes = 0U; + #if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) + + /* Check that the number of transfers is within the 16-bit limit. */ + FSP_ASSERT(num_transfers <= SCI_B_UART_DTC_MAX_TRANSFER); + #endif + + err = p_ctrl->p_cfg->p_transfer_tx->p_api->reset(p_ctrl->p_cfg->p_transfer_tx->p_ctrl, + (void const *) p_ctrl->p_tx_src, + NULL, + (uint16_t) num_transfers); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif + + /* Set TE and TIE bits simultaneously by single instruction to enable TIE interrupt. + * See "Serial Data Transmission in Asynchronous Mode" in the SCI section of the relevant + * hardware manual. */ + p_ctrl->p_reg->CCR0 |= (uint32_t) (R_SCI_B0_CCR0_TE_Msk | R_SCI_B0_CCR0_TIE_Msk); + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_src); + FSP_PARAMETER_NOT_USED(bytes); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements uart_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_SCI_B_UART_CallbackSet (uart_ctrl_t * const p_api_ctrl, + void ( * p_callback)(uart_callback_args_t *), + void * const p_context, + uart_callback_args_t * const p_callback_memory) +{ + sci_b_uart_instance_ctrl_t * p_ctrl = (sci_b_uart_instance_ctrl_t *) p_api_ctrl; + +#if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(SCI_B_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if SCI_B_UART_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + uart_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(uart_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the baud rate using the clock selected in Open. p_baud_setting is a pointer to a + * sci_b_baud_setting_t structure. + * Implements @ref uart_api_t::baudSet + * + * @warning This terminates any in-progress transmission. + * + * @retval FSP_SUCCESS Baud rate was successfully changed. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL or the UART is not configured to use the + * internal clock. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + **********************************************************************************************************************/ +fsp_err_t R_SCI_B_UART_BaudSet (uart_ctrl_t * const p_api_ctrl, void const * const p_baud_setting) +{ + sci_b_uart_instance_ctrl_t * p_ctrl = (sci_b_uart_instance_ctrl_t *) p_api_ctrl; + +#if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(SCI_B_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + + /* Verify that the On-Chip baud rate generator is currently selected. */ + FSP_ASSERT((p_ctrl->p_reg->CCR3_b.CKE & 0x2) == 0U); +#endif + + /* Save SCR configurations except transmit interrupts. Resuming transmission after reconfiguring baud settings is + * not supported. */ + uint32_t preserved_ccr0 = p_ctrl->p_reg->CCR0 & (uint32_t) ~(R_SCI_B0_CCR0_TIE_Msk | R_SCI_B0_CCR0_TEIE_Msk); + + /* Disables transmitter and receiver. This terminates any in-progress transmission. */ + p_ctrl->p_reg->CCR0 = preserved_ccr0 & + (uint32_t) ~(R_SCI_B0_CCR0_TE_Msk | R_SCI_B0_CCR0_RE_Msk | R_SCI_B0_CCR0_RIE_Msk); + p_ctrl->p_tx_src = NULL; + + /* Apply new baud rate register settings. */ + p_ctrl->p_reg->CCR2 = ((sci_b_baud_setting_t *) p_baud_setting)->baudrate_bits; + + /* Restore all settings except transmit interrupts. */ + p_ctrl->p_reg->CCR0 = preserved_ccr0; + + /* Restore all settings except transmit interrupts. */ + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides the driver information, including the maximum number of bytes that can be received or transmitted at a time. + * Implements @ref uart_api_t::infoGet + * + * @retval FSP_SUCCESS Information stored in provided p_info. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + **********************************************************************************************************************/ +fsp_err_t R_SCI_B_UART_InfoGet (uart_ctrl_t * const p_api_ctrl, uart_info_t * const p_info) +{ +#if SCI_B_UART_CFG_PARAM_CHECKING_ENABLE || SCI_B_UART_CFG_DTC_SUPPORTED + sci_b_uart_instance_ctrl_t * p_ctrl = (sci_b_uart_instance_ctrl_t *) p_api_ctrl; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); +#endif + +#if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_info); + FSP_ERROR_RETURN(SCI_B_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_info->read_bytes_max = SCI_B_UART_MAX_READ_WRITE_NO_DTC; + p_info->write_bytes_max = SCI_B_UART_MAX_READ_WRITE_NO_DTC; + +#if (SCI_B_UART_CFG_RX_ENABLE) + + /* Store number of bytes that can be read at a time. */ + #if SCI_B_UART_CFG_DTC_SUPPORTED + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + p_info->read_bytes_max = SCI_B_UART_DTC_MAX_TRANSFER; + } + #endif +#endif + +#if (SCI_B_UART_CFG_TX_ENABLE) + + /* Store number of bytes that can be written at a time. */ + #if SCI_B_UART_CFG_DTC_SUPPORTED + if (NULL != p_ctrl->p_cfg->p_transfer_tx) + { + p_info->write_bytes_max = SCI_B_UART_DTC_MAX_TRANSFER; + } + #endif +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides API to abort ongoing transfer. Transmission is aborted after the current character is transmitted. + * Reception is still enabled after abort(). Any characters received after abort() and before the transfer + * is reset in the next call to read(), will arrive via the callback function with event UART_EVENT_RX_CHAR. + * Implements @ref uart_api_t::communicationAbort + * + * @retval FSP_SUCCESS UART transaction aborted successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_UNSUPPORTED The requested Abort direction is unsupported. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::disable + **********************************************************************************************************************/ +fsp_err_t R_SCI_B_UART_Abort (uart_ctrl_t * const p_api_ctrl, uart_dir_t communication_to_abort) +{ + sci_b_uart_instance_ctrl_t * p_ctrl = (sci_b_uart_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_ERR_UNSUPPORTED; + +#if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(SCI_B_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if (SCI_B_UART_CFG_TX_ENABLE) + if (UART_DIR_TX & communication_to_abort) + { + err = FSP_SUCCESS; + + /* Transmit interrupts must be disabled to start with. */ + p_ctrl->p_reg->CCR0 &= (uint32_t) ~(R_SCI_B0_CCR0_TIE_Msk | R_SCI_B0_CCR0_TEIE_Msk); + + /* Make sure no transmission is in progress. Setting CCR0_b.TE to 0 when CSR_b.TEND is 0 causes SCI peripheral + * to work abnormally. */ + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->CSR_b.TEND, 1U); + + p_ctrl->p_reg->CCR0 &= (uint32_t) ~(R_SCI_B0_CCR0_TE_Msk); + + /* Wait until interanl state of TE is 0 as it takes some time for the state to be reflected + * internally after rewriting the control register. See "CESR : Communication + * Enable Status Register" description in the SCI section of the relevant hardware manual. */ + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->CESR_b.TIST, 0U); + + #if SCI_B_UART_CFG_DTC_SUPPORTED + if (NULL != p_ctrl->p_cfg->p_transfer_tx) + { + err = p_ctrl->p_cfg->p_transfer_tx->p_api->disable(p_ctrl->p_cfg->p_transfer_tx->p_ctrl); + } + #endif + + #if SCI_B_UART_CFG_FIFO_SUPPORT + if (p_ctrl->fifo_depth > 0U) + { + /* Reset the transmit fifo */ + p_ctrl->p_reg->FCR_b.TFRST = 1U; + } + #endif + p_ctrl->tx_src_bytes = 0U; + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } +#endif +#if (SCI_B_UART_CFG_RX_ENABLE) + if (UART_DIR_RX & communication_to_abort) + { + err = FSP_SUCCESS; + + p_ctrl->rx_dest_bytes = 0U; + #if SCI_B_UART_CFG_DTC_SUPPORTED + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + err = p_ctrl->p_cfg->p_transfer_rx->p_api->disable(p_ctrl->p_cfg->p_transfer_rx->p_ctrl); + } + #endif + #if SCI_B_UART_CFG_FIFO_SUPPORT + if (0U != p_ctrl->fifo_depth) + { + /* Reset the receive fifo */ + p_ctrl->p_reg->FCR_b.RFRST = 1U; + } + #endif + } +#endif + + return err; +} + +/*******************************************************************************************************************//** + * Provides API to abort ongoing read. Reception is still enabled after abort(). Any characters received after abort() + * and before the transfer is reset in the next call to read(), will arrive via the callback function with event + * UART_EVENT_RX_CHAR. + * Implements @ref uart_api_t::readStop + * + * @retval FSP_SUCCESS UART transaction aborted successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_UNSUPPORTED The requested Abort direction is unsupported. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::disable + **********************************************************************************************************************/ +fsp_err_t R_SCI_B_UART_ReadStop (uart_ctrl_t * const p_api_ctrl, uint32_t * remaining_bytes) +{ + sci_b_uart_instance_ctrl_t * p_ctrl = (sci_b_uart_instance_ctrl_t *) p_api_ctrl; + +#if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(SCI_B_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if (SCI_B_UART_CFG_RX_ENABLE) + *remaining_bytes = p_ctrl->rx_dest_bytes; + p_ctrl->rx_dest_bytes = 0U; + #if SCI_B_UART_CFG_DTC_SUPPORTED + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + fsp_err_t err = p_ctrl->p_cfg->p_transfer_rx->p_api->disable(p_ctrl->p_cfg->p_transfer_rx->p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + transfer_properties_t transfer_info; + err = p_ctrl->p_cfg->p_transfer_rx->p_api->infoGet(p_ctrl->p_cfg->p_transfer_rx->p_ctrl, &transfer_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + *remaining_bytes = transfer_info.transfer_length_remaining; + } + #endif + #if SCI_B_UART_CFG_FIFO_SUPPORT + if (0U != p_ctrl->fifo_depth) + { + /* Reset the receive fifo */ + p_ctrl->p_reg->FCR_b.RFRST = 1U; + } + #endif +#else + + return FSP_ERR_UNSUPPORTED; +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Calculates baud rate register settings. Evaluates and determines the best possible settings set to the baud rate + * related registers. + * + * @param[in] baudrate Baud rate [bps]. For example, 19200, 57600, 115200, etc. + * @param[in] bitrate_modulation Enable bitrate modulation + * @param[in] baud_rate_error_x_1000 Max baud rate error. At most <baud_rate_percent_error> x 1000 required + * for module to function. Absolute max baud_rate_error is 15000 (15%). + * @param[out] p_baud_setting Baud setting information stored here if successful + * + * @retval FSP_SUCCESS Baud rate is set successfully + * @retval FSP_ERR_ASSERTION Null pointer + * @retval FSP_ERR_INVALID_ARGUMENT Baud rate is '0', error in calculated baud rate is larger than requested + * max error, or requested max error in baud rate is larger than 15%. + **********************************************************************************************************************/ +fsp_err_t R_SCI_B_UART_BaudCalculate (uint32_t baudrate, + bool bitrate_modulation, + uint32_t baud_rate_error_x_1000, + sci_b_baud_setting_t * const p_baud_setting) +{ +#if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_baud_setting); + FSP_ERROR_RETURN(SCI_B_UART_MAX_BAUD_RATE_ERROR_X_1000 >= baud_rate_error_x_1000, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN((0U != baudrate), FSP_ERR_INVALID_ARGUMENT); +#endif + + p_baud_setting->baudrate_bits_b.brr = SCI_B_UART_BRR_MAX; + p_baud_setting->baudrate_bits_b.brme = 0U; + p_baud_setting->baudrate_bits_b.mddr = SCI_B_UART_MDDR_MIN; + + /* Find the best BRR (bit rate register) value. + * In table g_async_baud, divisor values are stored for BGDM, ABCS, ABCSE and N values. Each set of divisors + * is tried, and the settings with the lowest bit rate error are stored. The formula to calculate BRR is as + * follows and it must be 255 or less: + * BRR = (PCLK / (div_coefficient * baud)) - 1 + */ + int32_t hit_bit_err = SCI_B_UART_100_PERCENT_X_1000; + uint8_t hit_mddr = 0U; + uint32_t divisor = 0U; + +#if (BSP_FEATURE_SCI_HAS_SCISPI_CLOCK) + uint32_t freq_hz = R_FSP_SciSpiClockHzGet(); +#else + uint32_t freq_hz = R_FSP_SciClockHzGet(); +#endif + + for (uint32_t select_16_base_clk_cycles = 0U; + select_16_base_clk_cycles <= 1U && (hit_bit_err > ((int32_t) baud_rate_error_x_1000)); + select_16_base_clk_cycles++) + { + for (uint32_t i = 0U; i < SCI_B_UART_NUM_DIVISORS_ASYNC; i++) + { + /* if select_16_base_clk_cycles == true: Skip this calculation for divisors that are not achievable with 16 base clk cycles per bit. + * if select_16_base_clk_cycles == false: Skip this calculation for divisors that are only achievable without 16 base clk cycles per bit. + */ + if (((uint8_t) select_16_base_clk_cycles) ^ (g_async_baud[i].abcs | g_async_baud[i].abcse)) + { + continue; + } + + divisor = (uint32_t) g_div_coefficient[i] * baudrate; + uint32_t temp_brr = freq_hz / divisor; + + if (temp_brr <= (SCI_B_UART_BRR_MAX + 1U)) + { + while (temp_brr > 0U) + { + temp_brr -= 1U; + + /* Calculate the bit rate error. The formula is as follows: + * bit rate error[%] = {(PCLK / (baud * div_coefficient * (BRR + 1)) - 1} x 100 + * calculates bit rate error[%] to three decimal places + */ + int32_t err_divisor = (int32_t) (divisor * (temp_brr + 1U)); + + /* Promoting to 64 bits for calculation, but the final value can never be more than 32 bits, as + * described below, so this cast is safe. + * 1. (temp_brr + 1) can be off by an upper limit of 1 due to rounding from the calculation: + * freq_hz / divisor, or: + * freq_hz / divisor <= (temp_brr + 1) < (freq_hz / divisor) + 1 + * 2. Solving for err_divisor: + * freq_hz <= err_divisor < freq_hz + divisor + * 3. Solving for bit_err: + * 0 >= bit_err >= (freq_hz * 100000 / (freq_hz + divisor)) - 100000 + * 4. freq_hz >= divisor (or temp_brr would be -1 and we would never enter this while loop), so: + * 0 >= bit_err >= 100000 / freq_hz - 100000 + * 5. Larger frequencies yield larger bit errors (absolute value). As the frequency grows, + * the bit_err approaches -100000, so: + * 0 >= bit_err >= -100000 + * 6. bit_err is between -100000 and 0. This entire range fits in an int32_t type, so the cast + * to (int32_t) is safe. + */ + int32_t bit_err = (int32_t) (((((int64_t) freq_hz) * SCI_B_UART_100_PERCENT_X_1000) / + err_divisor) - SCI_B_UART_100_PERCENT_X_1000); + + uint8_t mddr = 0U; + if (bitrate_modulation) + { + /* Calculate the MDDR (M) value if bit rate modulation is enabled, + * The formula to calculate MBBR (from the M and N relationship given in the hardware manual) is as follows + * and it must be between 128 and 255. + * MDDR = ((div_coefficient * baud * 256) * (BRR + 1)) / PCLK */ + mddr = (uint8_t) ((uint32_t) err_divisor / (freq_hz / SCI_B_UART_MDDR_MAX)); + + /* MDDR value must be greater than or equal to SCI_B_UART_MDDR_MIN. */ + if (mddr < SCI_B_UART_MDDR_MIN) + { + break; + } + + /* Adjust bit rate error for bit rate modulation. The following formula is used: + * bit rate error [%] = ((bit rate error [%, no modulation] + 100) * MDDR / 256) - 100 + */ + bit_err = (((bit_err + SCI_B_UART_100_PERCENT_X_1000) * (int32_t) mddr) / + SCI_B_UART_MDDR_DIVISOR) - SCI_B_UART_100_PERCENT_X_1000; + } + + /* Take the absolute value of the bit rate error. */ + if (bit_err < 0) + { + bit_err = -bit_err; + } + + /* If the absolute value of the bit rate error is less than the previous lowest absolute value of + * bit rate error, then store these settings as the best value. + */ + if (bit_err < hit_bit_err) + { + p_baud_setting->baudrate_bits_b.bgdm = g_async_baud[i].bgdm; + p_baud_setting->baudrate_bits_b.abcs = g_async_baud[i].abcs; + p_baud_setting->baudrate_bits_b.abcse = g_async_baud[i].abcse; + p_baud_setting->baudrate_bits_b.cks = g_async_baud[i].cks; + p_baud_setting->baudrate_bits_b.brr = (uint8_t) temp_brr; + hit_bit_err = bit_err; + hit_mddr = mddr; + } + + if (bitrate_modulation) + { + p_baud_setting->baudrate_bits_b.brme = 1U; + p_baud_setting->baudrate_bits_b.mddr = hit_mddr; + } + else + { + break; + } + } + } + } + } + + /* Return an error if the percent error is larger than the maximum percent error allowed for this instance */ + FSP_ERROR_RETURN((hit_bit_err <= (int32_t) baud_rate_error_x_1000), FSP_ERR_INVALID_ARGUMENT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Suspend Reception + * + * @retval FSP_ERR_UNSUPPORTED Functionality not supported by this driver instance + **********************************************************************************************************************/ +fsp_err_t R_SCI_B_UART_ReceiveSuspend (uart_ctrl_t * const p_api_ctrl) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Resume Reception + * + * @retval FSP_ERR_UNSUPPORTED Functionality not supported by this driver instance + **********************************************************************************************************************/ +fsp_err_t R_SCI_B_UART_ReceiveResume (uart_ctrl_t * const p_api_ctrl) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup SCI_B_UART) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +#if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) + +/*******************************************************************************************************************//** + * Parameter error check function for read/write. + * + * @param[in] p_ctrl Pointer to the control block for the channel + * @param[in] addr Pointer to the buffer + * @param[in] bytes Number of bytes to read or write + * + * @retval FSP_SUCCESS No parameter error found + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_ASSERTION Pointer to UART control block or configuration structure is NULL + * @retval FSP_ERR_INVALID_ARGUMENT Address is not aligned to 2-byte boundary or size is the odd number when the data + * length is 9-bit + **********************************************************************************************************************/ +static fsp_err_t r_sci_b_read_write_param_check (sci_b_uart_instance_ctrl_t const * const p_ctrl, + uint8_t const * const addr, + uint32_t const bytes) +{ + FSP_ASSERT(p_ctrl); + FSP_ASSERT(addr); + FSP_ASSERT(0U != bytes); + FSP_ERROR_RETURN(SCI_B_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + + if (2U == p_ctrl->data_bytes) + { + /* Do not allow odd buffer address if data length is 9 bits. */ + FSP_ERROR_RETURN((0U == ((uint32_t) addr & SCI_B_UART_ALIGN_2_BYTES)), FSP_ERR_INVALID_ARGUMENT); + + /* Do not allow odd number of data bytes if data length is 9 bits. */ + FSP_ERROR_RETURN(0U == (bytes % 2U), FSP_ERR_INVALID_ARGUMENT); + } + + return FSP_SUCCESS; +} + +#endif +#if SCI_B_UART_CFG_DTC_SUPPORTED + +/*******************************************************************************************************************//** + * Subroutine to apply common UART transfer settings. + * + * @param[in] p_cfg Pointer to UART specific configuration structure + * @param[in] p_transfer Pointer to transfer instance to configure + * + * @retval FSP_SUCCESS UART transfer drivers successfully configured + * @retval FSP_ERR_ASSERTION Invalid pointer + **********************************************************************************************************************/ +static fsp_err_t r_sci_b_uart_transfer_configure (sci_b_uart_instance_ctrl_t * const p_ctrl, + transfer_instance_t const * p_transfer, + uint32_t * p_transfer_reg, + uint32_t sci_buffer_address) +{ + /* Configure the transfer instance, if enabled. */ + #if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_transfer->p_api); + FSP_ASSERT(NULL != p_transfer->p_cfg); + FSP_ASSERT(NULL != p_transfer->p_cfg->p_info); + FSP_ASSERT(NULL != p_transfer->p_cfg->p_extend); + #endif + + transfer_info_t * p_info = p_transfer->p_cfg->p_info; + + p_info->transfer_settings_word_b.size = TRANSFER_SIZE_1_BYTE; + + if (UART_DATA_BITS_9 == p_ctrl->p_cfg->data_bits) + { + p_info->transfer_settings_word_b.size = TRANSFER_SIZE_2_BYTE; + } + + /* Casting for compatibility with 7 or 8 bit mode. */ + *p_transfer_reg = sci_buffer_address; + + fsp_err_t err = p_transfer->p_api->open(p_transfer->p_ctrl, p_transfer->p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +#endif + +#if SCI_B_UART_CFG_DTC_SUPPORTED + +/*******************************************************************************************************************//** + * Configures UART related transfer drivers (if enabled). + * + * @param[in] p_ctrl Pointer to UART control structure + * @param[in] p_cfg Pointer to UART specific configuration structure + * + * @retval FSP_SUCCESS UART transfer drivers successfully configured + * @retval FSP_ERR_ASSERTION Invalid pointer or required interrupt not enabled in vector table + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::open + **********************************************************************************************************************/ +static fsp_err_t r_sci_b_uart_transfer_open (sci_b_uart_instance_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + + #if (SCI_B_UART_CFG_RX_ENABLE) + + /* If a transfer instance is used for reception, apply UART specific settings and open the transfer instance. */ + if (NULL != p_cfg->p_transfer_rx) + { + transfer_info_t * p_info = p_cfg->p_transfer_rx->p_cfg->p_info; + + p_info->transfer_settings_word = SCI_B_UART_DTC_RX_TRANSFER_SETTINGS; + + err = + r_sci_b_uart_transfer_configure(p_ctrl, p_cfg->p_transfer_rx, (uint32_t *) &p_info->p_src, + (uint32_t) &(p_ctrl->p_reg->RDR)); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif + #if (SCI_B_UART_CFG_TX_ENABLE) + + /* If a transfer instance is used for transmission, apply UART specific settings and open the transfer instance. */ + if (NULL != p_cfg->p_transfer_tx) + { + transfer_info_t * p_info = p_cfg->p_transfer_tx->p_cfg->p_info; + + p_info->transfer_settings_word = SCI_B_UART_DTC_TX_TRANSFER_SETTINGS; + + err = r_sci_b_uart_transfer_configure(p_ctrl, + p_cfg->p_transfer_tx, + (uint32_t *) &p_info->p_dest, + (uint32_t) &p_ctrl->p_reg->TDR); + + #if (SCI_B_UART_CFG_RX_ENABLE) + if ((err != FSP_SUCCESS) && (NULL != p_cfg->p_transfer_rx)) + { + p_cfg->p_transfer_rx->p_api->close(p_cfg->p_transfer_rx->p_ctrl); + } + #endif + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif + + return err; +} + +#endif + +/*******************************************************************************************************************//** + * Configures UART related registers based on user configurations. + * + * @param[in] p_ctrl Pointer to UART control structure + * @param[in] p_cfg Pointer to UART specific configuration structure + **********************************************************************************************************************/ +static void r_sci_b_uart_config_set (sci_b_uart_instance_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg) +{ + sci_b_uart_extended_cfg_t * p_extend = (sci_b_uart_extended_cfg_t *) p_cfg->p_extend; + sci_b_baud_setting_t * p_baud_setting = p_extend->p_baud_setting; + uint32_t ccr2 = 0U; + + /* Set Character length, Stop bit length, Start bit edge detection and SCI mode as Asynchronous mode. */ + uint32_t ccr3 = (uint32_t) R_SCI_B0_CCR3_LSBF_Msk; + ccr3 |= ((uint32_t) p_cfg->data_bits << SCI_B_UART_CCR3_CHAR_OFFSET) & SCI_B_UART_CCR3_CHAR_MASK; + ccr3 |= ((uint32_t) p_cfg->stop_bits << R_SCI_B0_CCR3_STP_Pos) & R_SCI_B0_CCR3_STP_Msk; + ccr3 |= ((uint32_t) p_extend->rx_edge_start << R_SCI_B0_CCR3_RXDESEL_Pos) & R_SCI_B0_CCR3_RXDESEL_Msk; + ccr3 |= ((uint32_t) p_extend->rs485_setting.enable << R_SCI_B0_CCR3_DEN_Pos) & R_SCI_B0_CCR3_DEN_Msk; + ccr3 |= ((uint32_t) p_extend->clock << SCI_B_UART_CCR3_CKE_OFFSET) & SCI_B_UART_CCR3_CKE_MASK; +#if SCI_B_UART_CFG_FIFO_SUPPORT + if (p_ctrl->fifo_depth > 0U) + { + ccr3 |= (1U << R_SCI_B0_CCR3_FM_Pos) & R_SCI_B0_CCR3_FM_Msk; + } +#endif + p_ctrl->p_reg->CCR3 = ccr3; + + if ((SCI_B_UART_CLOCK_EXT8X == p_extend->clock) || (SCI_B_UART_CLOCK_EXT16X == p_extend->clock)) + { + /* Use external clock for baud rate */ + ccr2 = SCI_B_UART_CCR2_DEFAULT_VALUE; + + if (SCI_B_UART_CLOCK_EXT8X == p_extend->clock) + { + /* Set baud rate as (external clock / 8) */ + ccr2 |= 1U << R_SCI_B0_CCR2_ABCS_Pos; + } + } + else + { + /* Set the baud rate settings for the internal baud rate generator. */ + ccr2 |= p_baud_setting->baudrate_bits; + } + + p_ctrl->p_reg->CCR2 = ccr2; + + /* Configure flow control pin. */ + uint32_t ccr1 = ((uint32_t) (p_extend->flow_control << R_SCI_B0_CCR1_CTSE_Pos) & SCI_B_UART_CCR1_FLOW_CTSRTS_MASK); + + /* TXD pin is at high level when TE is 0. */ + ccr1 |= (3U << SCI_B_UART_CCR1_SPB2_OFFSET) & SCI_B_UART_CCR1_SPB2_MASK; + + if (0 != p_cfg->parity) + { + ccr1 |= + (((UART_PARITY_EVEN == + p_cfg->parity) ? 1U : 3U) << SCI_B_UART_CCR1_PARITY_OFFSET) & SCI_B_UART_CCR1_PARITY_MASK; + } + + ccr1 |= ((uint32_t) p_extend->noise_cancel << R_SCI_B0_CCR1_NFEN_Pos) & + R_SCI_B0_CCR1_NFEN_Msk; + p_ctrl->p_reg->CCR1 = ccr1; + + p_ctrl->p_reg->CCR4 = 0U; + +#if SCI_B_UART_CFG_FIFO_SUPPORT + + /* Configure FIFO related registers. */ + r_sci_b_uart_fifo_cfg(p_ctrl); +#else + + /* If fifo support is disabled and the current channel supports fifo set FCR to default */ + if (BSP_FEATURE_SCI_UART_FIFO_CHANNELS_MASK & (1U << p_cfg->channel)) + { + p_ctrl->p_reg->FCR = SCI_B_UART_FCR_DEFAULT_VALUE; + } +#endif + + /* Configure RS-485 DE assertion settings. */ + uint32_t dcr = ((uint32_t) (p_extend->rs485_setting.polarity << R_SCI_B0_DCR_DEPOL_Pos)) & R_SCI_B0_DCR_DEPOL_Msk; + dcr |= ((uint32_t) p_extend->rs485_setting.assertion_time << R_SCI_B0_DCR_DEAST_Pos) & + R_SCI_B0_DCR_DEAST_Msk; + dcr |= ((uint32_t) p_extend->rs485_setting.negation_time << R_SCI_B0_DCR_DENGT_Pos) & + R_SCI_B0_DCR_DENGT_Msk; + p_ctrl->p_reg->DCR = dcr; +} + +#if SCI_B_UART_CFG_FIFO_SUPPORT + +/*******************************************************************************************************************//** + * Resets FIFO related registers. + * + * @param[in] p_ctrl Pointer to UART instance control + * @param[in] p_cfg Pointer to UART configuration structure + **********************************************************************************************************************/ +static void r_sci_b_uart_fifo_cfg (sci_b_uart_instance_ctrl_t * const p_ctrl) +{ + if (0U != p_ctrl->fifo_depth) + { + uint32_t fcr = 0U; + + /* Set the tx and rx reset bits */ + p_ctrl->p_reg->FCR = (uint32_t) (SCI_B_UART_FCR_RESET_TX_RX); + + #if SCI_B_UART_CFG_RX_ENABLE + #if SCI_B_UART_CFG_DTC_SUPPORTED + + /* If DTC is used keep the receive trigger at the default level of 0. */ + if (NULL == p_ctrl->p_cfg->p_transfer_rx) + #endif + { + /* Otherwise, set receive trigger number as configured by the user. */ + sci_b_uart_extended_cfg_t const * p_extend = p_ctrl->p_cfg->p_extend; + + /* RTRG(Receive FIFO Data Trigger Number) controls when the RXI interrupt will be generated. If data is + * received but the trigger number is not met the RXI interrupt will be generated after 15 ETUs from + * the last stop bit in asynchronous mode. For more information see the FIFO Selected section of "Serial + * Data Reception in Asynchronous Mode" in the SCI section of the relevant hardware manual. */ + fcr |= (((p_ctrl->fifo_depth - 1U) & p_extend->rx_fifo_trigger) & SCI_B_UART_FCR_TRIGGER_MASK) << + R_SCI_B0_FCR_RTRG_Pos; + } + + /* RTS asserts when the amount of received data stored in the fifo is equal or less than this value. */ + fcr |= ((p_ctrl->fifo_depth - 1U) & SCI_B_UART_FCR_TRIGGER_MASK) << R_SCI_B0_FCR_RSTRG_Pos; + #endif + + /* Set the FCR and reset the fifos. */ + p_ctrl->p_reg->FCR |= fcr; + } +} + +#endif + +/*******************************************************************************************************************//** + * Sets interrupt priority and initializes vector info. + * + * @param[in] p_ctrl Pointer to driver control block + * @param[in] ipl Interrupt priority level + * @param[in] irq IRQ number for this interrupt + **********************************************************************************************************************/ +static void r_sci_b_irq_cfg (sci_b_uart_instance_ctrl_t * const p_ctrl, uint8_t const ipl, IRQn_Type const irq) +{ + /* Disable interrupts, set priority, and store control block in the vector information so it can be accessed + * from the callback. */ + R_BSP_IrqDisable(irq); + R_BSP_IrqStatusClear(irq); + R_BSP_IrqCfg(irq, ipl, p_ctrl); +} + +/*******************************************************************************************************************//** + * Sets interrupt priority and initializes vector info for all interrupts. + * + * @param[in] p_ctrl Pointer to UART instance control block + * @param[in] p_cfg Pointer to UART specific configuration structure + **********************************************************************************************************************/ +static void r_sci_b_irqs_cfg (sci_b_uart_instance_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg) +{ +#if (SCI_B_UART_CFG_RX_ENABLE) + + /* ERI is optional. */ + r_sci_b_irq_cfg(p_ctrl, p_cfg->eri_ipl, p_cfg->eri_irq); + r_sci_b_irq_cfg(p_ctrl, p_cfg->rxi_ipl, p_cfg->rxi_irq); +#endif +#if (SCI_B_UART_CFG_TX_ENABLE) + r_sci_b_irq_cfg(p_ctrl, p_cfg->txi_ipl, p_cfg->txi_irq); + r_sci_b_irq_cfg(p_ctrl, p_cfg->tei_ipl, p_cfg->tei_irq); +#endif +} + +#if SCI_B_UART_CFG_DTC_SUPPORTED + +/*******************************************************************************************************************//** + * Closes transfer interfaces. + * + * @param[in] p_ctrl Pointer to UART instance control block + **********************************************************************************************************************/ +static void r_sci_b_uart_transfer_close (sci_b_uart_instance_ctrl_t * p_ctrl) +{ + #if (SCI_B_UART_CFG_RX_ENABLE) + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + p_ctrl->p_cfg->p_transfer_rx->p_api->close(p_ctrl->p_cfg->p_transfer_rx->p_ctrl); + } + #endif + #if (SCI_B_UART_CFG_TX_ENABLE) + if (NULL != p_ctrl->p_cfg->p_transfer_tx) + { + p_ctrl->p_cfg->p_transfer_tx->p_api->close(p_ctrl->p_cfg->p_transfer_tx->p_ctrl); + } + #endif +} + +#endif + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to UART instance control block + * @param[in] data See uart_callback_args_t in r_uart_api.h + * @param[in] event Event code + **********************************************************************************************************************/ +static void r_sci_b_uart_call_callback (sci_b_uart_instance_ctrl_t * p_ctrl, uint32_t data, uart_event_t event) +{ + uart_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + uart_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->channel = p_ctrl->p_cfg->channel; + p_args->data = data; + p_args->event = event; + p_args->p_context = p_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + sci_b_uart_prv_ns_callback p_callback = (sci_b_uart_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + +#if (SCI_B_UART_CFG_TX_ENABLE) + +/*******************************************************************************************************************//** + * TXI interrupt processing for UART mode. TXI interrupt fires when the data in the data register or FIFO register has + * been transferred to the data shift register, and the next data can be written. This interrupt writes the next data. + * After the last data byte is written, this interrupt disables the TXI interrupt and enables the TEI (transmit end) + * interrupt. + **********************************************************************************************************************/ +void sci_b_uart_txi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Recover ISR context saved in open. */ + sci_b_uart_instance_ctrl_t * p_ctrl = (sci_b_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + if ((NULL == p_ctrl->p_cfg->p_transfer_tx) && (0U != p_ctrl->tx_src_bytes)) + { + /* Fill the FIFO if its used. Otherwise write data to the TDR. */ + #if SCI_B_UART_CFG_FIFO_SUPPORT + if (0U != p_ctrl->fifo_depth) + { + uint32_t fifo_count = p_ctrl->p_reg->FTSR_b.T; + for (uint32_t cnt = fifo_count; (cnt < p_ctrl->fifo_depth) && p_ctrl->tx_src_bytes; cnt++) + { + if ((2U == p_ctrl->data_bytes)) + { + /* Write 16-bit data to TDR register */ + p_ctrl->p_reg->TDR = (uint32_t) (*(uint16_t *) (p_ctrl->p_tx_src)) & SCI_B_UART_TDR_TDAT_MASK_9BITS; + } + else + { + /* Write 1byte data to TDR_BY register */ + p_ctrl->p_reg->TDR_BY = (*(p_ctrl->p_tx_src)); + } + + p_ctrl->tx_src_bytes -= p_ctrl->data_bytes; + p_ctrl->p_tx_src += p_ctrl->data_bytes; + } + + /* Clear TDRE flag */ + p_ctrl->p_reg->CFCLR |= SCI_B_UART_CFCLR_TDREC_MASK; + } + else + #endif + { + if ((2U == p_ctrl->data_bytes)) + { + /* Write 16-bit data to TDR register */ + p_ctrl->p_reg->TDR = (uint32_t) (*(uint16_t *) (p_ctrl->p_tx_src)) & SCI_B_UART_TDR_TDAT_MASK_9BITS; + } + else + { + /* Write 1byte data to TDR_BY register */ + p_ctrl->p_reg->TDR_BY = (*(p_ctrl->p_tx_src)); + } + + p_ctrl->tx_src_bytes -= p_ctrl->data_bytes; + p_ctrl->p_tx_src += p_ctrl->data_bytes; + } + } + + if (0U == p_ctrl->tx_src_bytes) + { + /* After all data has been transmitted, disable transmit interrupts and enable the transmit end interrupt. */ + uint32_t ccr0_temp = p_ctrl->p_reg->CCR0; + ccr0_temp |= R_SCI_B0_CCR0_TEIE_Msk; + ccr0_temp &= (uint32_t) ~(R_SCI_B0_CCR0_TIE_Msk); + p_ctrl->p_reg->CCR0 = ccr0_temp; + + p_ctrl->p_tx_src = NULL; + + /* If a callback was provided, call it with the argument */ + if (NULL != p_ctrl->p_callback) + { + r_sci_b_uart_call_callback(p_ctrl, 0U, UART_EVENT_TX_DATA_EMPTY); + } + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +#endif + +#if (SCI_B_UART_CFG_RX_ENABLE) + +/*******************************************************************************************************************//** + * RXI interrupt processing for UART mode. RXI interrupt happens when data arrives to the data register or the FIFO + * register. This function calls callback function when it meets conditions below. + * - UART_EVENT_RX_COMPLETE: The number of data which has been read reaches to the number specified in R_SCI_B_UART_Read() + * if a transfer instance is used for reception. + * - UART_EVENT_RX_CHAR: Data is received asynchronously (read has not been called) + * + * This interrupt also calls the callback function for RTS pin control if it is registered in R_SCI_B_UART_Open(). This is + * special functionality to expand SCI hardware capability and make RTS/CTS hardware flow control possible. If macro + * 'SCI_B_UART_CFG_FLOW_CONTROL_SUPPORT' is set, it is called at the beginning in this function to set the RTS pin high, + * then it is it is called again just before leaving this function to set the RTS pin low. + * @retval none + **********************************************************************************************************************/ +void sci_b_uart_rxi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Recover ISR context saved in open. */ + sci_b_uart_instance_ctrl_t * p_ctrl = (sci_b_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + #if SCI_B_UART_CFG_DTC_SUPPORTED + if ((p_ctrl->p_cfg->p_transfer_rx == NULL) || (0 == p_ctrl->rx_dest_bytes)) + #endif + { + #if (SCI_B_UART_CFG_FLOW_CONTROL_SUPPORT) + if (p_ctrl->flow_pin != SCI_B_UART_INVALID_16BIT_PARAM) + { + R_BSP_PinAccessEnable(); + + /* Pause the transmission of data from the other device. */ + R_BSP_PinWrite(p_ctrl->flow_pin, SCI_B_UART_FLOW_CONTROL_ACTIVE); + } + #endif + + uint32_t data; + #if SCI_B_UART_CFG_FIFO_SUPPORT + do + { + if ((p_ctrl->fifo_depth > 0U)) + { + if (p_ctrl->p_reg->FRSR_b.R > 0U) + { + if (2U == p_ctrl->data_bytes) + { + data = p_ctrl->p_reg->RDR & R_SCI_B0_RDR_RDAT_Msk; + } + else + { + data = p_ctrl->p_reg->RDR_BY; + } + } + else + { + break; + } + } + else if (2U == p_ctrl->data_bytes) + #else + { + if (2U == p_ctrl->data_bytes) + #endif + { + data = p_ctrl->p_reg->RDR & R_SCI_B0_RDR_RDAT_Msk; + } + else + { + data = p_ctrl->p_reg->RDR_BY; + } + + if (0 == p_ctrl->rx_dest_bytes) + { + /* If a callback was provided, call it with the argument */ + if (NULL != p_ctrl->p_callback) + { + /* Call user callback with the data. */ + r_sci_b_uart_call_callback(p_ctrl, data, UART_EVENT_RX_CHAR); + } + } + else + { + memcpy((void *) p_ctrl->p_rx_dest, &data, p_ctrl->data_bytes); + p_ctrl->p_rx_dest += p_ctrl->data_bytes; + p_ctrl->rx_dest_bytes -= p_ctrl->data_bytes; + + if (0 == p_ctrl->rx_dest_bytes) + { + /* If a callback was provided, call it with the argument */ + if (NULL != p_ctrl->p_callback) + { + r_sci_b_uart_call_callback(p_ctrl, 0U, UART_EVENT_RX_COMPLETE); + } + } + } + + #if SCI_B_UART_CFG_FIFO_SUPPORT + } while ((p_ctrl->fifo_depth > 0U) && ((p_ctrl->p_reg->FRSR_b.R) > 0U)); + + if (p_ctrl->fifo_depth > 0U) + { + p_ctrl->p_reg->CFCLR |= SCI_B_UART_CFCLR_RDRFC_MASK; + } + + #else + } + #endif + #if (SCI_B_UART_CFG_FLOW_CONTROL_SUPPORT) + if (p_ctrl->flow_pin != SCI_B_UART_INVALID_16BIT_PARAM) + { + /* Resume the transmission of data from the other device. */ + R_BSP_PinWrite(p_ctrl->flow_pin, SCI_B_UART_FLOW_CONTROL_INACTIVE); + R_BSP_PinAccessDisable(); + } + #endif + } + + #if SCI_B_UART_CFG_DTC_SUPPORTED + else + { + p_ctrl->rx_dest_bytes = 0; + + p_ctrl->p_rx_dest = NULL; + + /* If a callback was provided, call it with the argument */ + if (NULL != p_ctrl->p_callback) + { + /* Call callback */ + r_sci_b_uart_call_callback(p_ctrl, 0U, UART_EVENT_RX_COMPLETE); + } + } + #endif + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +#endif + +#if (SCI_B_UART_CFG_TX_ENABLE) + +/*******************************************************************************************************************//** + * TEI interrupt processing for UART mode. The TEI interrupt fires after the last byte is transmitted on the TX pin. + * The user callback function is called with the UART_EVENT_TX_COMPLETE event code (if it is registered in + * R_SCI_B_UART_Open()). + **********************************************************************************************************************/ +void sci_b_uart_tei_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + sci_b_uart_instance_ctrl_t * p_ctrl = (sci_b_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + p_ctrl->p_reg->CCR0 &= (uint32_t) ~(R_SCI_B0_CCR0_TE_Msk | R_SCI_B0_CCR0_TIE_Msk | R_SCI_B0_CCR0_TEIE_Msk); + + /* If a callback was provided, call it with the argument */ + if (NULL != p_ctrl->p_callback) + { + /* Receiving TEI(transmit end interrupt) means the completion of transmission, so call callback function here. */ + r_sci_b_uart_call_callback(p_ctrl, 0U, UART_EVENT_TX_COMPLETE); + } + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +#endif + +#if (SCI_B_UART_CFG_RX_ENABLE) + +/*******************************************************************************************************************//** + * ERI interrupt processing for UART mode. When an ERI interrupt fires, the user callback function is called if it is + * registered in R_SCI_B_UART_Open() with the event code that triggered the interrupt. + **********************************************************************************************************************/ +void sci_b_uart_eri_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + sci_b_uart_instance_ctrl_t * p_ctrl = (sci_b_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + uint32_t data = 0U; + + /* Read data. */ + if (2U == p_ctrl->data_bytes) + { + data = p_ctrl->p_reg->RDR & R_SCI_B0_RDR_RDAT_Msk; + } + else + { + data = p_ctrl->p_reg->RDR_BY; + } + + /* Determine cause of error. */ + uint32_t csr = p_ctrl->p_reg->CSR; + uart_event_t event = (uart_event_t) ((((csr & R_SCI_B0_CSR_ORER_Msk) == R_SCI_B0_CSR_ORER_Msk) << 5U) | + (((csr & R_SCI_B0_CSR_FER_Msk) == R_SCI_B0_CSR_FER_Msk) << 4U) | + (((csr & R_SCI_B0_CSR_PER_Msk) == R_SCI_B0_CSR_PER_Msk) << 3U)); + + /* Check if there is a break detected. */ + if ((UART_EVENT_ERR_FRAMING == (event & UART_EVENT_ERR_FRAMING)) && (0U == p_ctrl->p_reg->CSR_b.RXDMON)) + { + event |= UART_EVENT_BREAK_DETECT; + } + + /* Clear error condition. */ + p_ctrl->p_reg->CFCLR |= SCI_B_UART_RCVR_ERR_MASK; + + /* If a callback was provided, call it with the argument */ + if (NULL != p_ctrl->p_callback) + { + /* Call callback. */ + r_sci_b_uart_call_callback(p_ctrl, data, event); + } + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +#endif diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_sdhi/r_sdhi.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_sdhi/r_sdhi.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_sdhi/r_sdhi.c rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_sdhi/r_sdhi.c diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_sdhi/r_sdhi_private.h b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_sdhi/r_sdhi_private.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_sdhi/r_sdhi_private.h rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_sdhi/r_sdhi_private.h diff --git a/bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_spi_b/r_spi_b.c b/bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_spi_b/r_spi_b.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra/fsp/src/r_spi_b/r_spi_b.c rename to bsp/renesas/ra8p1-titan-board/m85/ra/fsp/src/r_spi_b/r_spi_b.c diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra_cfg/SConscript b/bsp/renesas/ra8p1-titan-board/m85/ra_cfg/SConscript new file mode 100644 index 00000000000..a20b1173946 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra_cfg/SConscript @@ -0,0 +1,16 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * +from gcc import * + +cwd = GetCurrentDir() +src = [] +group = [] +CPPPATH = [] + +if rtconfig.PLATFORM in ['iccarm'] + GetGCCLikePLATFORM(): + src = Glob('*.c') + CPPPATH = [cwd+'/fsp_cfg', cwd + '/fsp_cfg/bsp'] + +group += DefineGroup('RA_cfg', src, depend = [''], CPPPATH = CPPPATH) +Return('group') diff --git a/bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/bsp/board_cfg.h b/bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/bsp/board_cfg.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/bsp/board_cfg.h rename to bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/bsp/board_cfg.h diff --git a/bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/bsp/bsp_cfg.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/bsp/bsp_cfg.h rename to bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/bsp/bsp_cfg.h diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h new file mode 100644 index 00000000000..92e7ddcdb62 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_MCU_PART_SERIES (8) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h rename to bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h diff --git a/bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h rename to bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/bsp/bsp_mcu_ofs_cfg.h b/bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/bsp/bsp_mcu_ofs_cfg.h new file mode 100644 index 00000000000..635745be8a5 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/bsp/bsp_mcu_ofs_cfg.h @@ -0,0 +1,4 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_OFS_CFG_H_ +#define BSP_MCU_OFS_CFG_H_ +#endif /* BSP_MCU_OFS_CFG_H_ */ diff --git a/bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h rename to bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h diff --git a/bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/r_adc_b_cfg.h b/bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/r_adc_b_cfg.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/r_adc_b_cfg.h rename to bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/r_adc_b_cfg.h diff --git a/bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/r_canfd_cfg.h b/bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/r_canfd_cfg.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/r_canfd_cfg.h rename to bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/r_canfd_cfg.h diff --git a/bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/r_dmac_cfg.h b/bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/r_dmac_cfg.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/r_dmac_cfg.h rename to bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/r_dmac_cfg.h diff --git a/bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/r_gpt_cfg.h b/bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/r_gpt_cfg.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/r_gpt_cfg.h rename to bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/r_gpt_cfg.h diff --git a/bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/r_iic_master_cfg.h b/bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/r_iic_master_cfg.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/r_iic_master_cfg.h rename to bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/r_iic_master_cfg.h diff --git a/bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/r_ioport_cfg.h b/bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/r_ioport_cfg.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/r_ioport_cfg.h rename to bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/r_ioport_cfg.h diff --git a/bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/r_layer3_switch_cfg.h b/bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/r_layer3_switch_cfg.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/r_layer3_switch_cfg.h rename to bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/r_layer3_switch_cfg.h diff --git a/bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/r_ospi_b_cfg.h b/bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/r_ospi_b_cfg.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/r_ospi_b_cfg.h rename to bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/r_ospi_b_cfg.h diff --git a/bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/r_rmac_cfg.h b/bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/r_rmac_cfg.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/r_rmac_cfg.h rename to bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/r_rmac_cfg.h diff --git a/bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/r_rmac_phy_cfg.h b/bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/r_rmac_phy_cfg.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/r_rmac_phy_cfg.h rename to bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/r_rmac_phy_cfg.h diff --git a/bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/r_rtc_cfg.h b/bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/r_rtc_cfg.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/r_rtc_cfg.h rename to bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/r_rtc_cfg.h diff --git a/bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/r_sci_b_uart_cfg.h b/bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/r_sci_b_uart_cfg.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/r_sci_b_uart_cfg.h rename to bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/r_sci_b_uart_cfg.h diff --git a/bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/r_sdhi_cfg.h b/bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/r_sdhi_cfg.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/r_sdhi_cfg.h rename to bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/r_sdhi_cfg.h diff --git a/bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/r_spi_b_cfg.h b/bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/r_spi_b_cfg.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_cfg/fsp_cfg/r_spi_b_cfg.h rename to bsp/renesas/ra8p1-titan-board/m85/ra_cfg/fsp_cfg/r_spi_b_cfg.h diff --git a/bsp/renesas/ra8p1-titan-board/m85/ra_gen/SConscript b/bsp/renesas/ra8p1-titan-board/m85/ra_gen/SConscript new file mode 100644 index 00000000000..e414161de51 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/ra_gen/SConscript @@ -0,0 +1,16 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * +from gcc import * + +cwd = GetCurrentDir() +src = [] +group = [] +CPPPATH = [] + +if rtconfig.PLATFORM in ['iccarm'] + GetGCCLikePLATFORM(): + src = Glob('*.c') + CPPPATH = [cwd, ] + +group = DefineGroup('RA_gen', src, depend = [''], CPPPATH = CPPPATH) +Return('group') diff --git a/bsp/renesas/ra8p1-titan-board/ra_gen/bsp_clock_cfg.h b/bsp/renesas/ra8p1-titan-board/m85/ra_gen/bsp_clock_cfg.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_gen/bsp_clock_cfg.h rename to bsp/renesas/ra8p1-titan-board/m85/ra_gen/bsp_clock_cfg.h diff --git a/bsp/renesas/ra8p1-titan-board/ra_gen/common_data.c b/bsp/renesas/ra8p1-titan-board/m85/ra_gen/common_data.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_gen/common_data.c rename to bsp/renesas/ra8p1-titan-board/m85/ra_gen/common_data.c diff --git a/bsp/renesas/ra8p1-titan-board/ra_gen/common_data.h b/bsp/renesas/ra8p1-titan-board/m85/ra_gen/common_data.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_gen/common_data.h rename to bsp/renesas/ra8p1-titan-board/m85/ra_gen/common_data.h diff --git a/bsp/renesas/ra8p1-titan-board/ra_gen/hal_data.c b/bsp/renesas/ra8p1-titan-board/m85/ra_gen/hal_data.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_gen/hal_data.c rename to bsp/renesas/ra8p1-titan-board/m85/ra_gen/hal_data.c diff --git a/bsp/renesas/ra8p1-titan-board/ra_gen/hal_data.h b/bsp/renesas/ra8p1-titan-board/m85/ra_gen/hal_data.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_gen/hal_data.h rename to bsp/renesas/ra8p1-titan-board/m85/ra_gen/hal_data.h diff --git a/bsp/renesas/ra8p1-titan-board/ra_gen/main.c b/bsp/renesas/ra8p1-titan-board/m85/ra_gen/main.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_gen/main.c rename to bsp/renesas/ra8p1-titan-board/m85/ra_gen/main.c diff --git a/bsp/renesas/ra8p1-titan-board/ra_gen/pin_data.c b/bsp/renesas/ra8p1-titan-board/m85/ra_gen/pin_data.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_gen/pin_data.c rename to bsp/renesas/ra8p1-titan-board/m85/ra_gen/pin_data.c diff --git a/bsp/renesas/ra8p1-titan-board/ra_gen/vector_data.c b/bsp/renesas/ra8p1-titan-board/m85/ra_gen/vector_data.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_gen/vector_data.c rename to bsp/renesas/ra8p1-titan-board/m85/ra_gen/vector_data.c diff --git a/bsp/renesas/ra8p1-titan-board/ra_gen/vector_data.h b/bsp/renesas/ra8p1-titan-board/m85/ra_gen/vector_data.h similarity index 100% rename from bsp/renesas/ra8p1-titan-board/ra_gen/vector_data.h rename to bsp/renesas/ra8p1-titan-board/m85/ra_gen/vector_data.h diff --git a/bsp/renesas/ra8p1-titan-board/m85/rasc_launcher.bat b/bsp/renesas/ra8p1-titan-board/m85/rasc_launcher.bat new file mode 100644 index 00000000000..db4a2e1c500 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/rasc_launcher.bat @@ -0,0 +1,43 @@ +@echo off +setlocal ENABLEEXTENSIONS ENABLEDELAYEDEXPANSION + +set "RascVersionFile=%~1" +shift + +set "InputFile=%~dp0configuration.xml" +set "OutputFile=%~dp0output.rasc" + +if /i "%~3"=="--gensmartbundle" ( + set "InputFile=%~9" + set "OutputFile=%~dpn9.sbd" +) + +if not exist "%InputFile%" ( + echo [ERROR] Input file "%InputFile%" does not exist. + exit /b 1 +) + +call "%~dp0rasc_version.bat" "%RascVersionFile%" +if errorlevel 1 exit /b 1 + +set /a idx=0 +for /f "usebackq tokens=*" %%a in ("%RascVersionFile%") do ( + if !idx! EQU 2 set "RascExe=%%a" + set /a idx+=1 +) + +if not defined RascExe ( + echo [ERROR] RASC executable is not configured. + exit /b 1 +) + +set "RascExe=%RascExe:rasc.exe=rascc.exe%" +set "Parameters=" +for %%a in (%*) do ( + if defined FirstParamSkipped set Parameters=!Parameters! %%a + set FirstParamSkipped=true +) + +echo [INFO] Generating Smart Bundle "%OutputFile%"... +"%RascExe%" %Parameters% +exit /b %errorlevel% diff --git a/bsp/renesas/ra8p1-titan-board/m85/rasc_version.bat b/bsp/renesas/ra8p1-titan-board/m85/rasc_version.bat new file mode 100644 index 00000000000..7ae172b6242 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/m85/rasc_version.bat @@ -0,0 +1,36 @@ +@echo off +setlocal ENABLEEXTENSIONS ENABLEDELAYEDEXPANSION + +set "RascVersionFile=%~1" +set "RascVersion=" +set "RascExe=" + +if exist "%RascVersionFile%" ( + set /a idx=0 + for /f "usebackq tokens=*" %%a in ("%RascVersionFile%") do ( + if !idx! EQU 1 set "RascVersion=%%a" + if !idx! EQU 2 set "RascExe=%%a" + set /a idx+=1 + ) +) + +if defined RascExe if exist "%RascExe%" exit /b 0 + +set "RascExe=" +for %%r in ("C:\Tools\Renesas\FSP" "C:\Renesas\RA" "C:\Renesas") do ( + if not defined RascExe if exist "%%~r" ( + for /d %%d in ("%%~r\*fsp_v6.2.0*") do ( + if not defined RascExe if exist "%%~d\eclipse\rascc.exe" set "RascExe=%%~d\eclipse\rascc.exe" + ) + ) +) + +if not defined RascExe ( + echo [ERROR] Renesas FSP 6.2.0 Smart Configurator was not found. + exit /b 1 +) + +>"%RascVersionFile%" echo # RASC version and installation file +>>"%RascVersionFile%" echo 6.2.0 +>>"%RascVersionFile%" echo %RascExe% +exit /b 0 diff --git a/bsp/renesas/ra8p1-titan-board/rtconfig.h b/bsp/renesas/ra8p1-titan-board/m85/rtconfig.h similarity index 97% rename from bsp/renesas/ra8p1-titan-board/rtconfig.h rename to bsp/renesas/ra8p1-titan-board/m85/rtconfig.h index d4e69ec4f15..e8c6e46213b 100644 --- a/bsp/renesas/ra8p1-titan-board/rtconfig.h +++ b/bsp/renesas/ra8p1-titan-board/m85/rtconfig.h @@ -305,6 +305,10 @@ /* end of Kendryte SDK */ +/* MM32 HAL & SDK Drivers */ + +/* end of MM32 HAL & SDK Drivers */ + /* WCH HAL & SDK Drivers */ /* end of WCH HAL & SDK Drivers */ @@ -336,6 +340,10 @@ /* FT32 HAL & SDK Drivers */ /* end of FT32 HAL & SDK Drivers */ + +/* NOVOSNS Drivers */ + +/* end of NOVOSNS Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -417,11 +425,13 @@ /* end of RT-Thread online packages */ #define SOC_FAMILY_RENESAS_RA #define SOC_SERIES_R7KA8P1 +#define SOC_SERIES_R7KA8P1_CORE0 /* Hardware Drivers Config */ /* Onboard Peripheral Drivers */ +#define BSP_START_SECONDARY_CORE /* end of Onboard Peripheral Drivers */ /* On-chip Peripheral Drivers */ diff --git a/bsp/renesas/ra8p1-titan-board/rtconfig.py b/bsp/renesas/ra8p1-titan-board/m85/rtconfig.py similarity index 100% rename from bsp/renesas/ra8p1-titan-board/rtconfig.py rename to bsp/renesas/ra8p1-titan-board/m85/rtconfig.py diff --git a/bsp/renesas/ra8p1-titan-board/script/fsp.icf b/bsp/renesas/ra8p1-titan-board/m85/script/fsp.icf similarity index 99% rename from bsp/renesas/ra8p1-titan-board/script/fsp.icf rename to bsp/renesas/ra8p1-titan-board/m85/script/fsp.icf index ab13b52a8de..d84049c0e2b 100644 --- a/bsp/renesas/ra8p1-titan-board/script/fsp.icf +++ b/bsp/renesas/ra8p1-titan-board/m85/script/fsp.icf @@ -2,7 +2,7 @@ define symbol RAM_START = 0x22000000; define symbol RAM_LENGTH = 0x174000; define symbol FLASH_START = 0x02000000; - define symbol FLASH_LENGTH = 0x00100000; + define symbol FLASH_LENGTH = 0x000C0000; define symbol DATA_FLASH_START = 0x27000000; define symbol DATA_FLASH_LENGTH = 0x00000000; define symbol SDRAM_START = 0x68000000; @@ -967,4 +967,3 @@ initialize manually with alignment preservation{ do not initialize{zi}; initialize manually with alignment preservation{rw}; - diff --git a/bsp/renesas/ra8p1-titan-board/script/fsp.ld b/bsp/renesas/ra8p1-titan-board/m85/script/fsp.ld similarity index 99% rename from bsp/renesas/ra8p1-titan-board/script/fsp.ld rename to bsp/renesas/ra8p1-titan-board/m85/script/fsp.ld index c4e847235ef..1d69809f7c5 100644 --- a/bsp/renesas/ra8p1-titan-board/script/fsp.ld +++ b/bsp/renesas/ra8p1-titan-board/m85/script/fsp.ld @@ -7,7 +7,7 @@ RAM_START = 0x22000000; RAM_LENGTH = 0x174000; FLASH_START = 0x02000000; -FLASH_LENGTH = 0x00100000; +FLASH_LENGTH = 0x000C0000; DATA_FLASH_START = 0x27000000; DATA_FLASH_LENGTH = 0x00000000; SDRAM_START = 0x68000000; diff --git a/bsp/renesas/ra8p1-titan-board/script/fsp.scat b/bsp/renesas/ra8p1-titan-board/m85/script/fsp.scat similarity index 99% rename from bsp/renesas/ra8p1-titan-board/script/fsp.scat rename to bsp/renesas/ra8p1-titan-board/m85/script/fsp.scat index 5c4fa231f21..d124a9c2573 100644 --- a/bsp/renesas/ra8p1-titan-board/script/fsp.scat +++ b/bsp/renesas/ra8p1-titan-board/m85/script/fsp.scat @@ -3,7 +3,7 @@ #define RAM_START 0x22000000 #define RAM_LENGTH 0x00174000 #define FLASH_START 0x02000000 - #define FLASH_LENGTH 0x00100000 + #define FLASH_LENGTH 0x000C0000 #define DATA_FLASH_START 0x27000000 #define DATA_FLASH_LENGTH 0x00000000 #define SDRAM_START 0x68000000 diff --git a/bsp/renesas/ra8p1-titan-board/src/hal_entry.c b/bsp/renesas/ra8p1-titan-board/m85/src/hal_entry.c similarity index 100% rename from bsp/renesas/ra8p1-titan-board/src/hal_entry.c rename to bsp/renesas/ra8p1-titan-board/m85/src/hal_entry.c diff --git a/bsp/renesas/ra8p1-titan-board/template.uvoptx b/bsp/renesas/ra8p1-titan-board/m85/template.uvoptx similarity index 90% rename from bsp/renesas/ra8p1-titan-board/template.uvoptx rename to bsp/renesas/ra8p1-titan-board/m85/template.uvoptx index 19bf068336b..b4908b6fb24 100644 --- a/bsp/renesas/ra8p1-titan-board/template.uvoptx +++ b/bsp/renesas/ra8p1-titan-board/m85/template.uvoptx @@ -125,12 +125,12 @@ 0 JL2CM3 - -O111 -N00("ARM CoreSight SW-DP") -S2 -ZTIFSpeedSel5000 -A0 -C-1 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD0 -FC800 -FN0 + -O111 -N00("ARM CoreSight SW-DP") -S2 -ZTIFSpeedSel5000 -A0 -C-1 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD22000000 -FC7800 -FN3 -FF0RA8P1_1M.FLM -FS02000000 -FL0100000 -FP0($$Device:R7KA8P1KF$Flash\RA8P1_1M.FLM) -FF1RA8P1_CONF.FLM -FS102C9F040 -FL17C0 -FP1($$Device:R7KA8P1KF$Flash\RA8P1_CONF.FLM) -FF2RA8P1_OTP.FLM -FS202E07600 -FL210334 -FP2($$Device:R7KA8P1KF$Flash\RA8P1_OTP.FLM) 0 UL2V8M - UL2V8M(-S0 -C0 -P0 ) + UL2V8M(-S0 -C0 -P0 ) -FN3 -FC7800 -FD22000000 -FF0RA8P1_1M -FF1RA8P1_CONF -FF2RA8P1_OTP -FL0100000 -FL17C0 -FL210334 -FS02000000 -FS102C9F040 -FS202E07600 -FP0($$Device:R7KA8P1KF$Flash\RA8P1_1M.FLM) -FP1($$Device:R7KA8P1KF$Flash\RA8P1_CONF.FLM) -FP2($$Device:R7KA8P1KF$Flash\RA8P1_OTP.FLM) diff --git a/bsp/renesas/ra8p1-titan-board/template.uvprojx b/bsp/renesas/ra8p1-titan-board/m85/template.uvprojx similarity index 95% rename from bsp/renesas/ra8p1-titan-board/template.uvprojx rename to bsp/renesas/ra8p1-titan-board/m85/template.uvprojx index 199ed07a779..c07e7209167 100644 --- a/bsp/renesas/ra8p1-titan-board/template.uvprojx +++ b/bsp/renesas/ra8p1-titan-board/m85/template.uvprojx @@ -21,7 +21,7 @@ CPUTYPE("Cortex-M85") DSP TZ MVE(FP) FPU3(DFPU) PACBTI CLOCK(12000000) ELITTLE - + UL2V8M(-S0 -C0 -P0 -FD22000000 -FC7800 -FN3 -FF0RA8P1_1M -FS02000000 -FL0100000 -FF1RA8P1_CONF -FS102C9F040 -FL17C0 -FF2RA8P1_OTP -FS202E07600 -FL210334 -FP0($$Device:R7KA8P1KF$Flash\RA8P1_1M.FLM) -FP1($$Device:R7KA8P1KF$Flash\RA8P1_CONF.FLM) -FP2($$Device:R7KA8P1KF$Flash\RA8P1_OTP.FLM)) 0 @@ -80,9 +80,9 @@ 0 - 0 + 1 0 - + cmd /c ""$Prasc_launcher.bat" "$Prasc_version.txt" -nosplash --launcher.suppressErrors --gensmartbundle --compiler ARMv6 --devicefamily ra "$Pconfiguration.xml" "$L%L" 2> "$PObjects\rasc_stderr.out"" 0 0 @@ -134,10 +134,10 @@ 0 0 1 - -1 + 4102 1 - + BIN\UL2V8M.DLL "" () diff --git a/bsp/renesas/ra8p1-titan-board/project.uvprojx b/bsp/renesas/ra8p1-titan-board/project.uvprojx deleted file mode 100644 index dcf071cfdaf..00000000000 --- a/bsp/renesas/ra8p1-titan-board/project.uvprojx +++ /dev/null @@ -1,2332 +0,0 @@ - - - - 2.1 - -
### uVision Project, (C) Keil Software
- - - - Target_1 - 0x4 - ARM-ADS - 6240000::V6.24::ARMCLANG - 1 - - - R7KA8P1KF:CPU0 - Renesas - Renesas.RA_DFP.6.5.1 - https://www2.renesas.eu/Keil_MDK_Packs/ - CPUTYPE("Cortex-M85") DSP TZ MVE(FP) FPU3(DFPU) PACBTI CLOCK(12000000) ELITTLE - - - - 0 - - - - - - - - - - - $$Device:R7KA8P1KF$SVD\R7KA8P1AD.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\Objects\ - template - 1 - 0 - 1 - 1 - 1 - .\Listings\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 2 - 0 - - - 0 - 0 - - - 0 - 0 - 2 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMV8M.DLL - -MPU - DCM.DLL - -pCM4 - SARMV8M.DLL - -MPU -MVE -PACBTI - TCM.DLL - -pCM85 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 0 - 1 - -1 - - 1 - - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M85" - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 3 - 2 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 2 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 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